From ec3ee27ad6b030fa47244450bd4af2e5d6f7d189 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sat, 13 Sep 2025 15:37:34 +0200 Subject: [PATCH 001/230] fixes & extends logging of priv wrapper & mmu --- src/iss/arch/riscv_hart_m_p.h | 6 +++--- src/iss/arch/riscv_hart_msu_vp.h | 12 ++++++------ src/iss/arch/riscv_hart_mu_p.h | 12 ++++++------ src/iss/mem/mmu.h | 20 +++++++++++--------- src/sysc/core_complex.cpp | 2 +- 5 files changed, 27 insertions(+), 25 deletions(-) diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 73ea7d1..9c94636 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -508,9 +508,9 @@ uint64_t riscv_hart_m_p::enter_trap(uint64_t flags, uint64_t sprintf(buffer.data(), "0x%016lx", addr); #endif if((flags & 0xffffffff) != 0xffffffff) - NSCLOG(INFO, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '" - << (trap_id ? this->irq_str[cause] : this->trap_str[cause]) << "' (" << cause << ")" << " at address " - << buffer.data() << " occurred"; + NSCLOG(DEBUG, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '" + << (trap_id ? this->irq_str[cause] : this->trap_str[cause]) << "' (" << cause << ")" << " at address " + << buffer.data() << " occurred"; // reset trap state this->reg.PRIV = new_priv; this->reg.trap_state = 0; diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index f48509c..a4db91c 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -689,10 +689,10 @@ uint64_t riscv_hart_msu_vp::enter_trap(uint64_t flags, uint6 sprintf(buffer.data(), "0x%016lx", addr); #endif if((flags & 0xffffffff) != 0xffffffff) - NSCLOG(INFO, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '" - << (trap_id ? this->irq_str[cause] : this->trap_str[cause]) << "' (" << cause << ")" << " at address " - << buffer.data() << " occurred, changing privilege level from " << this->lvl[this->reg.PRIV] << " to " - << this->lvl[new_priv]; + NSCLOG(DEBUG, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '" + << (trap_id ? this->irq_str[cause] : this->trap_str[cause]) << "' (" << cause << ")" << " at address " + << buffer.data() << " occurred, changing privilege level from " << this->lvl[this->reg.PRIV] << " to " + << this->lvl[new_priv]; // reset trap this->state this->reg.PRIV = new_priv; this->reg.trap_state = 0; @@ -732,8 +732,8 @@ template uint64_t riscv_hart_m } // sets the pc to the value stored in the x epc register. this->reg.NEXT_PC = this->csr[uepc | inst_priv << 8]; - NSCLOG(INFO, LOGCAT) << "Executing xRET , changing privilege level from " << this->lvl[cur_priv] << " to " - << this->lvl[this->reg.PRIV]; + NSCLOG(DEBUG, LOGCAT) << "Executing xRET , changing privilege level from " << this->lvl[cur_priv] << " to " + << this->lvl[this->reg.PRIV]; check_interrupt(); } this->reg.trap_state = this->reg.pending_trap; diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index fe1dbe5..2090c49 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -565,10 +565,10 @@ uint64_t riscv_hart_mu_p::enter_trap(uint64_t flags, uint64_ sprintf(buffer.data(), "0x%016lx", addr); #endif if((flags & 0xffffffff) != 0xffffffff) - NSCLOG(INFO, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '" - << (trap_id ? this->irq_str[cause] : this->trap_str[cause]) << "' (" << cause << ")" << " at address " - << buffer.data() << " occurred, changing privilege level from " << this->lvl[this->reg.PRIV] << " to " - << this->lvl[new_priv]; + NSCLOG(DEBUG, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '" + << (trap_id ? this->irq_str[cause] : this->trap_str[cause]) << "' (" << cause << ")" << " at address " + << buffer.data() << " occurred, changing privilege level from " << this->lvl[this->reg.PRIV] << " to " + << this->lvl[new_priv]; // reset trap state this->reg.PRIV = new_priv; this->reg.trap_state = 0; @@ -600,8 +600,8 @@ template uint64_t riscv_hart_m } // sets the pc to the value stored in the x epc register. this->reg.NEXT_PC = this->csr[uepc | inst_priv << 8]; - NSCLOG(INFO, LOGCAT) << "Executing xRET , changing privilege level from " << this->lvl[cur_priv] << " to " - << this->lvl[this->reg.PRIV]; + NSCLOG(DEBUG, LOGCAT) << "Executing xRET , changing privilege level from " << this->lvl[cur_priv] << " to " + << this->lvl[this->reg.PRIV]; check_interrupt(); } this->reg.trap_state = this->reg.pending_trap; diff --git a/src/iss/mem/mmu.h b/src/iss/mem/mmu.h index 8e59be0..93e18e0 100644 --- a/src/iss/mem/mmu.h +++ b/src/iss/mem/mmu.h @@ -157,6 +157,7 @@ template struct mmu : public memory_elem { hart_if.raise_trap(0, 2, hart_if.PC); return iss::Err; } + CPPLOG(INFO) << "mmu: writing satp with 0x" << std::hex << val; satp = val; update_vm_info(); return iss::Ok; @@ -224,12 +225,13 @@ template uint64_t mmu::virt2phys(iss::access_typ if(auto it = tlb.find(addr >> PGSHIFT); it != tlb.end()) { pte = it->second; } else { + update_vm_info(); reg_t base = vm_setting.ptbase; const int va_bits = vm_setting.idxbits * vm_setting.levels + PGSHIFT; const reg_t mask = (reg_t(1) << (sizeof(reg_t) * 8 - (va_bits - 1))) - 1; const reg_t masked_msbs = (addr >> (va_bits - 1)) & mask; if(masked_msbs != 0 && masked_msbs != mask) { - CPPLOG(DEBUG) << "Page fault because of invalid unused address bits"; + CPPLOG(DEBUG) << "Page fault for address 0x" << std::hex << addr << ": invalid unused address bits"; throw_page_fault(type, addr); } for(int i = vm_setting.levels - 1; i >= 0; i--) { @@ -251,20 +253,20 @@ template uint64_t mmu::virt2phys(iss::access_typ }; } if(bit_sub<63, 1>(static_cast(pte))) { - CPPLOG(DEBUG) << "Page fault because of set 'N' bit without Svnapot extension present"; + CPPLOG(DEBUG) << "Page fault for address 0x" << std::hex << addr << ": set 'N' bit without Svnapot extension present"; throw_page_fault(type, addr); } if(bit_sub<61, 2>(static_cast(pte))) { - CPPLOG(DEBUG) << "Page fault because of set 'PBMT' bit(s) without Svpbmt extension present"; + CPPLOG(DEBUG) << "Page fault for address 0x" << std::hex << addr << ": set 'PBMT' bit(s) without Svpbmt extension present"; throw_page_fault(type, addr); } if(bit_sub<54, 7>(static_cast(pte))) { - CPPLOG(DEBUG) << "Page fault because of set 'reserved' bits"; + CPPLOG(DEBUG) << "Page fault for address 0x" << std::hex << addr << ": set 'reserved' bits"; throw_page_fault(type, addr); } if(!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { - CPPLOG(DEBUG) << "Page fault because of invalid page"; + CPPLOG(INFO) << "Page fault for address 0x" << std::hex << addr << ": invalid page, PTE=0x" << std::hex << pte; throw_page_fault(type, addr); } const reg_t ppn = pte >> PTE_PPN_SHIFT; @@ -273,7 +275,7 @@ template uint64_t mmu::virt2phys(iss::access_typ continue; } if((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { - CPPLOG(DEBUG) << "Page fault because of page misalignment"; + CPPLOG(DEBUG) << "Page fault for address 0x" << std::hex << addr << ": page misalignment"; throw_page_fault(type, addr); } if(!(pte & PTE_A) || (type == iss::access_type::WRITE && !(pte & PTE_D))) { @@ -287,7 +289,7 @@ template uint64_t mmu::virt2phys(iss::access_typ // pte |= PTE_D; // Svade behavior - CPPLOG(DEBUG) << "Page fault because of unset A or D bit"; + CPPLOG(DEBUG) << "Page fault for address 0x" << std::hex << addr << ": unset A or D bit"; throw_page_fault(type, addr); } const reg_t vpn = addr >> PGSHIFT; @@ -301,14 +303,14 @@ template uint64_t mmu::virt2phys(iss::access_typ const bool s_mode = effective_priv(type) == arch::PRIV_S; const bool sum = hart_if.state.mstatus.SUM; if((pte & PTE_U) ? s_mode && (type == iss::access_type::FETCH || !sum) : !s_mode) { - CPPLOG(DEBUG) << "Page fault because of SUM bit"; + CPPLOG(DEBUG) << "Page fault for address 0x" << std::hex << addr << ": SUM bit"; throw_page_fault(type, addr); } const bool mxr = hart_if.state.mstatus.MXR; if(type == iss::access_type::FETCH ? !(pte & PTE_X) : type == iss::access_type::WRITE ? !(pte & PTE_W) : !((pte & PTE_R) || (mxr && (pte & PTE_X)))) { - CPPLOG(DEBUG) << "Page fault because of Invalid request"; + CPPLOG(DEBUG) << "Page fault for address 0x" << std::hex << addr << ": Invalid request"; throw_page_fault(type, addr); } diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index 917841d..fd9550f 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -161,7 +161,7 @@ class core_wrapper { core->set_hartid(hart_id); auto* srv = debugger::server::get(); if(srv) - tgt_adapter = srv->get_target(); + tgt_adapter = srv->get_target(0); // FIXME: add core_id if(tgt_adapter) tgt_adapter->add_custom_command({"sysc", [this](int argc, char* argv[], debugger::out_func of, debugger::data_func df) -> int { From db9784cb3c99758078ec0f4bbc7186dfc0242847 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sun, 14 Sep 2025 14:54:03 +0200 Subject: [PATCH 002/230] corrects cmake preset visibility --- CMakePresets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/CMakePresets.json b/CMakePresets.json index 0a22ba1..6079f1b 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -13,6 +13,7 @@ "name": "Base", "generator": "Ninja", "binaryDir": "${sourceDir}/build/${presetName}", + "hidden": true, "cacheVariables": { "CMAKE_POLICY_DEFAULT_CMP0091": "NEW", "CMAKE_CXX_STANDARD": "17", From 64f870b7e16b4eb8f6437e40f6aa23e4640dcffc Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Mon, 15 Sep 2025 12:41:19 +0200 Subject: [PATCH 003/230] updates core definitions and shortens ISA spec --- contrib/generate_custom_cores.sh | 88 ++++++++++++++++++ gen_input/cores.core_desc | 31 ++++++- gen_input/templates/CORENAME_sysc.cpp.gtl | 78 ++++++++-------- gen_input/templates/asmjit/CORENAME.cpp.gtl | 6 +- gen_input/templates/interp/CORENAME.cpp.gtl | 24 ++--- src/iss/arch/rv64gc.h | 2 - src/main.cpp | 23 +++-- src/sysc/core_complex.cpp | 26 ++++-- src/sysc/register_cores.cpp | 64 +++++++------- src/vm/asmjit/vm_rv32gc.cpp | 6 +- src/vm/asmjit/vm_rv32i.cpp | 4 +- src/vm/asmjit/vm_rv32imac.cpp | 4 +- src/vm/asmjit/vm_rv64gc.cpp | 98 +-------------------- src/vm/asmjit/vm_rv64i.cpp | 4 +- src/vm/asmjit/vm_tgc5c.cpp | 4 +- src/vm/interp/vm_rv32gc.cpp | 6 +- src/vm/interp/vm_rv32i.cpp | 4 +- src/vm/interp/vm_rv32imac.cpp | 4 +- src/vm/interp/vm_rv64gc.cpp | 56 +----------- src/vm/interp/vm_rv64i.cpp | 4 +- src/vm/interp/vm_tgc5c.cpp | 4 +- 21 files changed, 269 insertions(+), 271 deletions(-) create mode 100644 contrib/generate_custom_cores.sh diff --git a/contrib/generate_custom_cores.sh b/contrib/generate_custom_cores.sh new file mode 100644 index 0000000..dc1dbe6 --- /dev/null +++ b/contrib/generate_custom_cores.sh @@ -0,0 +1,88 @@ +#!/bin/bash +## + +# Absolute path to this script, e.g. /home/user/bin/foo.sh +SCRIPT=`readlink -f "$0"` +# Absolute path this script is in, thus /home/user/bin +MYSCRIPTDIR=`dirname "$SCRIPT"` +SCRIPTNAME=`basename "$SCRIPT"` + +ROOT_DIR=$(realpath $MYSCRIPTDIR/../..) +SCRIPTDIR=$ROOT_DIR/build/TGC-GEN/scripts +CORE_DSL_DIR=$(realpath ${SCRIPTDIR}/../CoreDSL) + +print_help() { + echo "Usage: $SCRIPTNAME [-h] -c -v " + echo "Generate RTL for TGC & custom cores" + echo " -b list of backends to generate code for, default: '$BACKENDS'" + echo " -x use extended list of cores" + exit 0 +} + +OUTPUT_ROOT=${ROOT_DIR}/dbt-rise-riscv +TMPL_DIR=${OUTPUT_ROOT}/gen_input/templates + +BACKENDS="interp asmjit" +EXT_LIST=0 +while getopts 'b:hx' c; do + case $c in + x) EXT_LIST=1 ;; + b) BACKENDS=$OPTARG ;; + h) print_help ;; + ?) die "Unknown CLI option!" 255 + esac +done + +[[ -d $ROOT_DIR/build/TGC-GEN ]] || (cd build; git clone --recursive -b develop https://git.minres.com/TGFS/TGC-GEN.git ) + +Generate standard cores +for core in RV32I RV32IMAC RV32GC RV64I RV64GC; do + for backend in ${BACKENDS}; do + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${TMPL_DIR}/../../gen_input/cores.core_desc + done + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow +done + +# Generate for TGC5C +core=TGC5C +for backend in ${BACKENDS}; do + echo ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc +done +unset core +python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/TGC5C_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/TGC5C_fast.yaml -s fast +python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/TGC5C_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/TGC5C_slow.yaml -s slow +exit +# Generate for other TGCs +OUTPUT_ROOT=${ROOT_DIR}/dbt-rise-custom +for core in TGC5A TGC5B TGC5D TGC5E TGC6B TGC6C TGC6D TGC6E; do + for backend in ${BACKENDS}; do + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc + done + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow +done +for core in TGC5C_XRB_NN; do + for backend in interp; do + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow + done +done +for core in RV32GCV RV64GCV; do + echo ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b interp ${TMPL_DIR}/../../gen_input/cores.core_desc + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b interp ${TMPL_DIR}/../../gen_input/cores.core_desc + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow +done +# Generate extended list +if [ $EXT_LIST -ne 0 ]; then + for core in TGC5Xe TGC5Xi TGC5Xec TGC5Xic TGC5Xem TGC5Xim TGC5Xemc TGC5Ximc; do + for backend in ${BACKENDS}; do + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -c $core -b ${backend} ${CORE_DSL_DIR}/TGC5.core_desc + done + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow + done +fi diff --git a/gen_input/cores.core_desc b/gen_input/cores.core_desc index 7a0a36b..aeb5f92 100644 --- a/gen_input/cores.core_desc +++ b/gen_input/cores.core_desc @@ -5,6 +5,8 @@ import "ISA/RVA.core_desc" import "ISA/Zc.core_desc" import "ISA/RVF.core_desc" import "ISA/RVD.core_desc" +import "ISA/RVV/RVV.core_desc" +import "ISA/Zvk.core_desc" Core RV32I provides RVI, Zicsr, Zifencei { @@ -41,6 +43,20 @@ Core RV32GC provides RVI, Zicsr, Zifencei, RVM, RVA, Zca, Zcf, Zcd, RVSMode { } } +Core RV32GCV provides RVI, Zicsr, Zifencei, RVM, RVA, Zca, Zcf, Zcd, RVSMode, RVVBase_vset, RVVBase_mem, RVVBase_arith, RVVBase_fixed, RVVBase_red_fp, RVVBase_mask, RVVBase_perm_fp, RVVBase_fp { + architectural_state { + XLEN=32; + FLEN=64; + VLEN=256; + ELEN=32; + // definitions for the architecture wrapper + // XL ZYXWVUTSRQPONMLKJIHGFEDCBA + unsigned MISA_VAL = 0b01000000000000000001000100101101; + unsigned int MARCHID_VAL = 0x00000000; + unsigned int CLIC_NUM_IRQ = 0; + } +} + Core RV64I provides RVI, Zicsr, Zifencei { architectural_state { XLEN=64; @@ -62,6 +78,19 @@ Core RV64GC provides RVI, Zicsr, Zifencei, RVM, RVA, Zca, Zcd, RVSMode { } } +Core RV64GCV provides RVI, Zicsr, Zifencei, RVM, RVA, Zca, Zcd, RVSMode, RVVBase_vset, RVVBase_mem, RVVBase_arith, RVVBase_fixed, RVVBase_red_fp, RVVBase_mask, RVVBase_perm_fp, RVVBase_fp{ + architectural_state { + XLEN=64; + FLEN=64; + VLEN=512; + ELEN=64; + // definitions for the architecture wrapper + unsigned MISA_VAL = 0x800000000000112d; + unsigned int MARCHID_VAL = 0x00000000; + unsigned int CLIC_NUM_IRQ = 0; + } +} + /* -for b in interp tcc llvm asmjit; do for i in RV32I RV32IMAC RV32IMACF RV32GC RV64I RV64GC; do ./build/TGC-GEN/scripts/generate_iss.sh -b $b -o . -m src -r gen_input -t gen_input/templates -c $i gen_input/cores.core_desc; done ; done +for b in interp asmjit; do for i in RV32I RV32IMAC RV32IMACF RV32GC RV64I RV64GC; do ./build/TGC-GEN/scripts/generate_iss.sh -b $b -o . -m src -r gen_input -t gen_input/templates -c $i gen_input/cores.core_desc; done ; done */ diff --git a/gen_input/templates/CORENAME_sysc.cpp.gtl b/gen_input/templates/CORENAME_sysc.cpp.gtl index 2127194..c387531 100644 --- a/gen_input/templates/CORENAME_sysc.cpp.gtl +++ b/gen_input/templates/CORENAME_sysc.cpp.gtl @@ -44,20 +44,20 @@ namespace iss { namespace interp { using namespace sysc; volatile std::array ${coreDef.name.toLowerCase()}_init = { - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>, - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%}%> }; } @@ -65,20 +65,20 @@ volatile std::array ${coreDef.name.toLowerCase()}_init = { namespace llvm { using namespace sysc; volatile std::array ${coreDef.name.toLowerCase()}_init = { - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>, - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%}%> }; } @@ -87,20 +87,20 @@ volatile std::array ${coreDef.name.toLowerCase()}_init = { namespace tcc { using namespace sysc; volatile std::array ${coreDef.name.toLowerCase()}_init = { - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>, - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%}%> }; } @@ -109,20 +109,20 @@ volatile std::array ${coreDef.name.toLowerCase()}_init = { namespace asmjit { using namespace sysc; volatile std::array ${coreDef.name.toLowerCase()}_init = { - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>, - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); - return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%}%> }; } diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 317bf37..bc583bb 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -368,7 +368,7 @@ namespace iss { namespace { <% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) {%> volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|msu_vp|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}_msu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_msu_vp(); auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -379,7 +379,7 @@ volatile std::array dummy = { return {cpu_ptr{cpu}, vm_ptr{vm}}; }),<% } else { %> volatile std::array dummy = {<%}%> - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -389,7 +389,7 @@ volatile std::array dummy = {<%}%> } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index fda5303..4dcab0e 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -30,9 +30,9 @@ * *******************************************************************************/ <% -def floating_point = registers.find {it.name=='FCSR'} -def vector = registers.find {it.name=='vtype'} -def aes = functions.find { it.contains('aes') } +def floating_point = registers.find {it.name=='FCSR'} != null +def vector = registers.find {it.name=='vtype'} != null +def aes = functions.find { it.contains('aes') } != null def nativeTypeSize(int size){ if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64; } @@ -45,13 +45,13 @@ def nativeTypeSize(int size){ #include #include <% -if(floating_point != null) {%> +if(floating_point) {%> #include <%} -if(vector != null) {%> +if(vector) {%> #include <%} -if(aes != null) {%> +if(aes) {%> #include <%}%> #include @@ -114,10 +114,10 @@ protected: inline const char *name(size_t index){return traits::reg_aliases.at(index);} <% -if(floating_point != null) {%> +if(floating_point) {%> inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";} <%} -if(vector != null) {%> +if(vector) {%> inline const char* vname(size_t index) { return index < 32 ? name(index + traits::V0) : "illegal"; } inline const char* sew_name(size_t bits) { switch(bits) { @@ -177,7 +177,7 @@ if(vector != null) {%> inline void set_tval(uint64_t new_tval){ tval = new_tval; } -<%if(vector != null) { +<%if(vector) { def xlen = constants.find { it.name == 'XLEN' }?.value ?: 0 def vlen = constants.find { it.name == 'VLEN' }?.value ?: 0 %> inline void lower(){ @@ -1179,7 +1179,7 @@ namespace iss { namespace { <% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) {%> volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|msu_vp|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}_msu:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_msu_vp(); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -1190,7 +1190,7 @@ volatile std::array dummy = { return {cpu_ptr{cpu}, vm_ptr{vm}}; }),<% } else { %> volatile std::array dummy = {<%}%> - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -1200,7 +1200,7 @@ volatile std::array dummy = {<%}%> } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/iss/arch/rv64gc.h b/src/iss/arch/rv64gc.h index 57110b8..ae13610 100644 --- a/src/iss/arch/rv64gc.h +++ b/src/iss/arch/rv64gc.h @@ -679,8 +679,6 @@ template <> struct traits { C__FSD = 195, C__FLDSP = 196, C__FSDSP = 197, - SFENCE__VMA = 198, - SRET = 199, MAX_OPCODE }; }; diff --git a/src/main.cpp b/src/main.cpp index 5432f46..46d7347 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -127,19 +127,28 @@ int main(int argc, char* argv[]) { semihosting_cb_t semihosting_cb = [&cb](iss::arch_if* i, uint32_t* a0, uint32_t* a1) { cb(i, a0, a1); }; std::string isa_opt(clim["isa"].as()); if(isa_opt.size() == 0 || isa_opt == "?") { - auto list = f.get_names(); - std::sort(std::begin(list), std::end(list)); - std::cout << "Available implementations (core|platform|backend):\n - " << util::join(list, "\n - ") << std::endl; + std::unordered_map> core_by_backend; + for(auto& e: f.get_names()) { + auto p = e.find(':'); + assert(p!=std::string::npos); + core_by_backend[e.substr(p+1)].push_back(e.substr(0, p)); + } + std::cout << "Available implementations\n"; + std::cout << "=========================\n"; + for(auto& e:core_by_backend) { + std::sort(std::begin(e.second), std::end(e.second)); + std::cout<<" backend "<(), clim["gdb-port"].as(), &semihosting_cb); + f.create(isa_opt + ":" + clim["backend"].as(), clim["gdb-port"].as(), &semihosting_cb); } else { auto base_isa = isa_opt.substr(0, 5); if(base_isa == "tgc5d" || base_isa == "tgc5e") { - isa_opt += "|mu_p_clic_pmp|" + clim["backend"].as(); + isa_opt += "_clic_pmp:" + clim["backend"].as(); } else { - isa_opt += "|m_p|" + clim["backend"].as(); + isa_opt += ":" + clim["backend"].as(); } std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as(), &semihosting_cb); } diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index fd9550f..e5f8f73 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -39,6 +39,7 @@ #include #include #include "iss_factory.h" +#include #include #ifndef WIN32 #include @@ -137,18 +138,29 @@ class core_wrapper { void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) { auto& f = sysc::iss_factory::instance(); if(type.size() == 0 || type == "?") { - auto names = f.get_names(); - std::sort(names.begin(), names.end()); - SCCINFO(owner->hier_name()) << "Available cores: \n " << util::join(names, ",\n ") << std::endl; + std::unordered_map> core_by_backend; + for(auto& e: f.get_names()) { + auto p = e.find(':'); + assert(p!=std::string::npos); + core_by_backend[e.substr(p+1)].push_back(e.substr(0, p)); + } + std::ostringstream os; + os << "Available implementations\n"; + os << "=========================\n"; + for(auto& e:core_by_backend) { + std::sort(std::begin(e.second), std::end(e.second)); + os<<" backend "<hier_name()) << "\n"< riscv_init = { - iss_factory::instance().register_creator("rv32i|m_p|interp", + iss_factory::instance().register_creator("rv32i_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32i|mu_p|interp", + iss_factory::instance().register_creator("rv32i_mu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32imac|m_p|interp", + iss_factory::instance().register_creator("rv32imac_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32imac|mu_p|interp", + iss_factory::instance().register_creator("rv32imac_mu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32gc|m_p|interp", + iss_factory::instance().register_creator("rv32gc_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32gc|mu_p|interp", + iss_factory::instance().register_creator("rv32gc_mu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32gc|msu_vp|interp", + iss_factory::instance().register_creator("rv32gc_msu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv64i|m_p|interp", + iss_factory::instance().register_creator("rv64i_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv64i|mu_p|interp", + iss_factory::instance().register_creator("rv64i_mu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv64gc|m_p|interp", + iss_factory::instance().register_creator("rv64gc_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv64gc|mu_p|interp", + iss_factory::instance().register_creator("rv64gc_mu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv64gc|msu_vp|interp", + iss_factory::instance().register_creator("rv64gc_msu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("tgc5c|m_p|interp", + iss_factory::instance().register_creator("tgc5c_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("tgc5c_mu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; @@ -137,25 +137,25 @@ volatile std::array riscv_init = { namespace llvm { using namespace sysc; volatile std::array riscv_init = { - iss_factory::instance().register_creator("rv32imc|m_p|llvm", + iss_factory::instance().register_creator("rv32imc_m:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32imc|mu_p|llvm", + iss_factory::instance().register_creator("rv32imc_mu:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("tgc5c|m_p|llvm", + iss_factory::instance().register_creator("tgc5c_m:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("tgc5c_mu:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; @@ -166,85 +166,85 @@ volatile std::array riscv_init = { namespace asmjit { using namespace sysc; volatile std::array riscv_init = { - iss_factory::instance().register_creator("rv32i|m_p|asmjit", + iss_factory::instance().register_creator("rv32i_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32i|mu_p|asmjit", + iss_factory::instance().register_creator("rv32i_mu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32imac|m_p|asmjit", + iss_factory::instance().register_creator("rv32imac_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32imac|mu_p|asmjit", + iss_factory::instance().register_creator("rv32imac_mu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32gc|m_p|asmjit", + iss_factory::instance().register_creator("rv32gc_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32gc|mu_p|asmjit", + iss_factory::instance().register_creator("rv32gc_mu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv32gc|msu_vp|asmjit", + iss_factory::instance().register_creator("rv32gc_msu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv64i|m_p|asmjit", + iss_factory::instance().register_creator("rv64i_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv64i|mu_p|asmjit", + iss_factory::instance().register_creator("rv64i_mu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv64gc|m_p|asmjit", + iss_factory::instance().register_creator("rv64gc_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv64gc|mu_p|asmjit", + iss_factory::instance().register_creator("rv64gc_mu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("rv64gc|msu_vp|asmjit", + iss_factory::instance().register_creator("rv64gc_msu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("tgc5c|m_p|asmjit", + iss_factory::instance().register_creator("tgc5c_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("tgc5c_mu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; diff --git a/src/vm/asmjit/vm_rv32gc.cpp b/src/vm/asmjit/vm_rv32gc.cpp index 6168c05..533bfaa 100644 --- a/src/vm/asmjit/vm_rv32gc.cpp +++ b/src/vm/asmjit/vm_rv32gc.cpp @@ -10098,7 +10098,7 @@ namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("rv32gc|msu_vp|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32gc_msu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_msu_vp(); auto vm = new asmjit::rv32gc::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -10108,7 +10108,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv32gc|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32gc_m:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new asmjit::rv32gc::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -10118,7 +10118,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv32gc|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32gc_mu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new asmjit::rv32gc::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/asmjit/vm_rv32i.cpp b/src/vm/asmjit/vm_rv32i.cpp index 02e4afe..53e3f4e 100644 --- a/src/vm/asmjit/vm_rv32i.cpp +++ b/src/vm/asmjit/vm_rv32i.cpp @@ -2946,7 +2946,7 @@ namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("rv32i|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32i_m:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new asmjit::rv32i::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -2956,7 +2956,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv32i|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32i_mu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new asmjit::rv32i::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/asmjit/vm_rv32imac.cpp b/src/vm/asmjit/vm_rv32imac.cpp index 8b09fee..e6df724 100644 --- a/src/vm/asmjit/vm_rv32imac.cpp +++ b/src/vm/asmjit/vm_rv32imac.cpp @@ -5546,7 +5546,7 @@ namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("rv32imac|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32imac_m:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new asmjit::rv32imac::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -5556,7 +5556,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv32imac|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32imac_mu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new asmjit::rv32imac::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/asmjit/vm_rv64gc.cpp b/src/vm/asmjit/vm_rv64gc.cpp index 110814a..4f66aaf 100644 --- a/src/vm/asmjit/vm_rv64gc.cpp +++ b/src/vm/asmjit/vm_rv64gc.cpp @@ -183,7 +183,7 @@ template class vm_impl : public iss::asmjit::vm_base { compile_func op; }; - const std::array instr_descr = {{ + const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI, encoding '0b00000000000000000000000000110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, @@ -581,10 +581,6 @@ template class vm_impl : public iss::asmjit::vm_base { {16, 0b0010000000000010, 0b1110000000000011, &this_class::__c__fldsp}, /* instruction C__FSDSP, encoding '0b1010000000000010' */ {16, 0b1010000000000010, 0b1110000000000011, &this_class::__c__fsdsp}, - /* instruction SFENCE__VMA, encoding '0b00010010000000000000000001110011' */ - {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence__vma}, - /* instruction SRET, encoding '0b00010000001000000000000001110011' */ - {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, }}; //needs to be declared after instr_descr @@ -12435,82 +12431,6 @@ template class vm_impl : public iss::asmjit::vm_base { return returnValue; } - /* instruction 198: SFENCE__VMA */ - continuation_e __sfence__vma(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ - uint64_t PC = pc.val; - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t asid = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate disass */ - - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {asid}", fmt::arg("mnemonic", "sfence.vma"), - fmt::arg("rs1", name(rs1)), fmt::arg("asid", name(asid))); - InvokeNode* call_print_disass; - char* mnemonic_ptr = strdup(mnemonic.c_str()); - jh.disass_collection.push_back(mnemonic_ptr); - jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); - call_print_disass->setArg(0, jh.arch_if_ptr); - call_print_disass->setArg(1, pc.val); - call_print_disass->setArg(2, mnemonic_ptr); - - } - x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("SFENCE__VMA_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 198); - mov(cc, jh.pc, pc.val); - gen_set_tval(jh, instr); - pc = pc+4; - mov(cc, jh.next_pc, pc.val); - cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); - - gen_instr_prologue(jh); - /*generate behavior*/ - gen_write_mem(jh, traits::FENCE, static_cast(traits::fencevma), ((uint8_t)rs1<<8)|(uint8_t)asid, 8); - auto returnValue = CONT; - - gen_sync(jh, POST_SYNC, 198); - gen_instr_epilogue(jh); - return returnValue; - } - - /* instruction 199: SRET */ - continuation_e __sret(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ - uint64_t PC = pc.val; - if(this->disass_enabled){ - /* generate disass */ - - //No disass specified, using instruction name - std::string mnemonic = "sret"; - InvokeNode* call_print_disass; - char* mnemonic_ptr = strdup(mnemonic.c_str()); - jh.disass_collection.push_back(mnemonic_ptr); - jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); - call_print_disass->setArg(0, jh.arch_if_ptr); - call_print_disass->setArg(1, pc.val); - call_print_disass->setArg(2, mnemonic_ptr); - - } - x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("SRET_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 199); - mov(cc, jh.pc, pc.val); - gen_set_tval(jh, instr); - pc = pc+4; - mov(cc, jh.next_pc, pc.val); - cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); - - gen_instr_prologue(jh); - /*generate behavior*/ - mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); - gen_leave(jh, 1); - auto returnValue = TRAP; - - gen_sync(jh, POST_SYNC, 199); - gen_instr_epilogue(jh); - return returnValue; - } - /**************************************************************************** * end opcode definitions ****************************************************************************/ @@ -12678,18 +12598,8 @@ std::unique_ptr create(arch::rv64gc *core, unsigned short p namespace iss { namespace { -volatile std::array dummy = { - core_factory::instance().register_creator("rv64gc|msu_vp|asmjit", [](unsigned port, void* init_data) -> std::tuple{ - auto* cpu = new iss::arch::riscv_hart_msu_vp(); - auto vm = new asmjit::rv64gc::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); - if(init_data){ - auto* cb = reinterpret_cast::reg_t>*>(init_data); - cpu->set_semihosting_callback(*cb); - } - return {cpu_ptr{cpu}, vm_ptr{vm}}; - }), - core_factory::instance().register_creator("rv64gc|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ +volatile std::array dummy = { + core_factory::instance().register_creator("rv64gc_m:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new asmjit::rv64gc::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -12699,7 +12609,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv64gc|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv64gc_mu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new asmjit::rv64gc::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/asmjit/vm_rv64i.cpp b/src/vm/asmjit/vm_rv64i.cpp index 8b867a4..b522f00 100644 --- a/src/vm/asmjit/vm_rv64i.cpp +++ b/src/vm/asmjit/vm_rv64i.cpp @@ -3601,7 +3601,7 @@ namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("rv64i|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv64i_m:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new asmjit::rv64i::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -3611,7 +3611,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv64i|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv64i_mu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new asmjit::rv64i::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index f7a7ffd..1d1dd12 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -4840,7 +4840,7 @@ namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("tgc5c|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("tgc5c_m:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new asmjit::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -4850,7 +4850,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("tgc5c_mu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new asmjit::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/interp/vm_rv32gc.cpp b/src/vm/interp/vm_rv32gc.cpp index 771f533..efe26bf 100644 --- a/src/vm/interp/vm_rv32gc.cpp +++ b/src/vm/interp/vm_rv32gc.cpp @@ -4925,7 +4925,7 @@ namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("rv32gc|msu_vp|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32gc_msu:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_msu_vp(); auto vm = new interp::rv32gc::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -4935,7 +4935,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv32gc|m_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32gc_m:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::rv32gc::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -4945,7 +4945,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv32gc|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32gc_mu:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::rv32gc::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/interp/vm_rv32i.cpp b/src/vm/interp/vm_rv32i.cpp index 5003f44..340fe3a 100644 --- a/src/vm/interp/vm_rv32i.cpp +++ b/src/vm/interp/vm_rv32i.cpp @@ -1792,7 +1792,7 @@ namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("rv32i|m_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32i_m:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::rv32i::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -1802,7 +1802,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv32i|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32i_mu:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::rv32i::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/interp/vm_rv32imac.cpp b/src/vm/interp/vm_rv32imac.cpp index 5ff1407..4b045be 100644 --- a/src/vm/interp/vm_rv32imac.cpp +++ b/src/vm/interp/vm_rv32imac.cpp @@ -3194,7 +3194,7 @@ namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("rv32imac|m_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32imac_m:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::rv32imac::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -3204,7 +3204,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv32imac|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv32imac_mu:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::rv32imac::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/interp/vm_rv64gc.cpp b/src/vm/interp/vm_rv64gc.cpp index ed1c1ce..c1c046c 100644 --- a/src/vm/interp/vm_rv64gc.cpp +++ b/src/vm/interp/vm_rv64gc.cpp @@ -189,7 +189,7 @@ template class vm_impl : public iss::interp::vm_base { typename arch::traits::opcode_e op; }; - const std::array instr_descr = {{ + const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits::opcode_e::LUI}, {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits::opcode_e::AUIPC}, @@ -389,8 +389,6 @@ template class vm_impl : public iss::interp::vm_base { {16, 0b1010000000000000, 0b1110000000000011, arch::traits::opcode_e::C__FSD}, {16, 0b0010000000000010, 0b1110000000000011, arch::traits::opcode_e::C__FLDSP}, {16, 0b1010000000000010, 0b1110000000000011, arch::traits::opcode_e::C__FSDSP}, - {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, arch::traits::opcode_e::SFENCE__VMA}, - {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::SRET}, }}; //needs to be declared after instr_descr @@ -6180,42 +6178,6 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SFENCE__VMA: { - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t asid = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {asid}", fmt::arg("mnemonic", "sfence.vma"), - fmt::arg("rs1", name(rs1)), fmt::arg("asid", name(asid))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - // calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - super::template write_mem(traits::FENCE, traits::fencevma, ((uint16_t)(uint8_t)rs1<<8)|(uint8_t)asid); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRET: { - if(this->disass_enabled){ - /* generate console output when executing the command */ - //No disass specified, using instruction name - std::string mnemonic = "sret"; - this->core.disass_output(pc.val, mnemonic); - } - // used registers - // calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - leave(1); - } - break; - }// @suppress("No break at end of case") default: { if(this->disass_enabled){ std::string mnemonic = "Illegal Instruction"; @@ -6267,18 +6229,8 @@ std::unique_ptr create(arch::rv64gc *core, unsigned short p namespace iss { namespace { -volatile std::array dummy = { - core_factory::instance().register_creator("rv64gc|msu_vp|interp", [](unsigned port, void* init_data) -> std::tuple{ - auto* cpu = new iss::arch::riscv_hart_msu_vp(); - auto vm = new interp::rv64gc::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); - if(init_data){ - auto* cb = reinterpret_cast::reg_t>*>(init_data); - cpu->set_semihosting_callback(*cb); - } - return {cpu_ptr{cpu}, vm_ptr{vm}}; - }), - core_factory::instance().register_creator("rv64gc|m_p|interp", [](unsigned port, void* init_data) -> std::tuple{ +volatile std::array dummy = { + core_factory::instance().register_creator("rv64gc_m:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::rv64gc::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -6288,7 +6240,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv64gc|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv64gc_mu:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::rv64gc::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/interp/vm_rv64i.cpp b/src/vm/interp/vm_rv64i.cpp index 434f7e3..a8c262c 100644 --- a/src/vm/interp/vm_rv64i.cpp +++ b/src/vm/interp/vm_rv64i.cpp @@ -2158,7 +2158,7 @@ namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("rv64i|m_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv64i_m:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::rv64i::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -2168,7 +2168,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("rv64i|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("rv64i_mu:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::rv64i::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 6be289e..821d4e2 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -2779,7 +2779,7 @@ namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("tgc5c_m:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -2789,7 +2789,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple{ + core_factory::instance().register_creator("tgc5c_mu:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); From 04962945ef6556213768a465935d2925127edd53 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Mon, 15 Sep 2025 12:51:04 +0200 Subject: [PATCH 004/230] updates isa reporting --- .gitignore | 2 ++ src/sysc/core_complex.cpp | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 79ba466..b189e80 100644 --- a/.gitignore +++ b/.gitignore @@ -36,3 +36,5 @@ /.direnv/ /.envrc.* build +contrib/instr/*_fast.yaml +contrib/instr/*_slow.yaml diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index e5f8f73..81a74d2 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -149,7 +149,8 @@ class core_wrapper { os << "=========================\n"; for(auto& e:core_by_backend) { std::sort(std::begin(e.second), std::end(e.second)); - os<<" backend "<hier_name()) << "\n"< Date: Mon, 15 Sep 2025 20:26:34 +0200 Subject: [PATCH 005/230] fixes missing generated configurations --- contrib/generate_custom_cores.sh | 2 +- gen_input/cores.core_desc | 2 - gen_input/templates/CORENAME_sysc.cpp.gtl | 11 ++- src/iss/arch/rv64gc.h | 2 + src/vm/asmjit/vm_rv64gc.cpp | 94 ++++++++++++++++++++++- src/vm/interp/vm_rv64gc.cpp | 52 ++++++++++++- 6 files changed, 154 insertions(+), 9 deletions(-) diff --git a/contrib/generate_custom_cores.sh b/contrib/generate_custom_cores.sh index dc1dbe6..17db3cb 100644 --- a/contrib/generate_custom_cores.sh +++ b/contrib/generate_custom_cores.sh @@ -35,7 +35,7 @@ done [[ -d $ROOT_DIR/build/TGC-GEN ]] || (cd build; git clone --recursive -b develop https://git.minres.com/TGFS/TGC-GEN.git ) -Generate standard cores +# Generate standard cores for core in RV32I RV32IMAC RV32GC RV64I RV64GC; do for backend in ${BACKENDS}; do ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${TMPL_DIR}/../../gen_input/cores.core_desc diff --git a/gen_input/cores.core_desc b/gen_input/cores.core_desc index aeb5f92..d59e0cc 100644 --- a/gen_input/cores.core_desc +++ b/gen_input/cores.core_desc @@ -6,8 +6,6 @@ import "ISA/Zc.core_desc" import "ISA/RVF.core_desc" import "ISA/RVD.core_desc" import "ISA/RVV/RVV.core_desc" -import "ISA/Zvk.core_desc" - Core RV32I provides RVI, Zicsr, Zifencei { architectural_state { diff --git a/gen_input/templates/CORENAME_sysc.cpp.gtl b/gen_input/templates/CORENAME_sysc.cpp.gtl index c387531..016b9f1 100644 --- a/gen_input/templates/CORENAME_sysc.cpp.gtl +++ b/gen_input/templates/CORENAME_sysc.cpp.gtl @@ -43,7 +43,14 @@ def array_count = coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCas namespace iss { namespace interp { using namespace sysc; -volatile std::array ${coreDef.name.toLowerCase()}_init = { +<% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) {%> +volatile std::array ${coreDef.name.toLowerCase()}_init = { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_msu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }),<% } else { %> +volatile std::array ${coreDef.name.toLowerCase()}_init = {<%}%> iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); @@ -58,7 +65,7 @@ volatile std::array ${coreDef.name.toLowerCase()}_init = { auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; - })<%}%> + })<%}}%> }; } #if defined(WITH_LLVM) diff --git a/src/iss/arch/rv64gc.h b/src/iss/arch/rv64gc.h index ae13610..57110b8 100644 --- a/src/iss/arch/rv64gc.h +++ b/src/iss/arch/rv64gc.h @@ -679,6 +679,8 @@ template <> struct traits { C__FSD = 195, C__FLDSP = 196, C__FSDSP = 197, + SFENCE__VMA = 198, + SRET = 199, MAX_OPCODE }; }; diff --git a/src/vm/asmjit/vm_rv64gc.cpp b/src/vm/asmjit/vm_rv64gc.cpp index 4f66aaf..1b6da5a 100644 --- a/src/vm/asmjit/vm_rv64gc.cpp +++ b/src/vm/asmjit/vm_rv64gc.cpp @@ -183,7 +183,7 @@ template class vm_impl : public iss::asmjit::vm_base { compile_func op; }; - const std::array instr_descr = {{ + const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI, encoding '0b00000000000000000000000000110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, @@ -581,6 +581,10 @@ template class vm_impl : public iss::asmjit::vm_base { {16, 0b0010000000000010, 0b1110000000000011, &this_class::__c__fldsp}, /* instruction C__FSDSP, encoding '0b1010000000000010' */ {16, 0b1010000000000010, 0b1110000000000011, &this_class::__c__fsdsp}, + /* instruction SFENCE__VMA, encoding '0b00010010000000000000000001110011' */ + {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence__vma}, + /* instruction SRET, encoding '0b00010000001000000000000001110011' */ + {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, }}; //needs to be declared after instr_descr @@ -12431,6 +12435,82 @@ template class vm_impl : public iss::asmjit::vm_base { return returnValue; } + /* instruction 198: SFENCE__VMA */ + continuation_e __sfence__vma(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t asid = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {asid}", fmt::arg("mnemonic", "sfence.vma"), + fmt::arg("rs1", name(rs1)), fmt::arg("asid", name(asid))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SFENCE__VMA_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 198); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_write_mem(jh, traits::FENCE, static_cast(traits::fencevma), ((uint8_t)rs1<<8)|(uint8_t)asid, 8); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 198); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 199: SRET */ + continuation_e __sret(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "sret"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRET_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 199); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + gen_leave(jh, 1); + auto returnValue = TRAP; + + gen_sync(jh, POST_SYNC, 199); + gen_instr_epilogue(jh); + return returnValue; + } + /**************************************************************************** * end opcode definitions ****************************************************************************/ @@ -12598,7 +12678,17 @@ std::unique_ptr create(arch::rv64gc *core, unsigned short p namespace iss { namespace { -volatile std::array dummy = { +volatile std::array dummy = { + core_factory::instance().register_creator("rv64gc_msu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_msu_vp(); + auto vm = new asmjit::rv64gc::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), core_factory::instance().register_creator("rv64gc_m:asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new asmjit::rv64gc::vm_impl(*cpu, false); diff --git a/src/vm/interp/vm_rv64gc.cpp b/src/vm/interp/vm_rv64gc.cpp index c1c046c..7781643 100644 --- a/src/vm/interp/vm_rv64gc.cpp +++ b/src/vm/interp/vm_rv64gc.cpp @@ -189,7 +189,7 @@ template class vm_impl : public iss::interp::vm_base { typename arch::traits::opcode_e op; }; - const std::array instr_descr = {{ + const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits::opcode_e::LUI}, {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits::opcode_e::AUIPC}, @@ -389,6 +389,8 @@ template class vm_impl : public iss::interp::vm_base { {16, 0b1010000000000000, 0b1110000000000011, arch::traits::opcode_e::C__FSD}, {16, 0b0010000000000010, 0b1110000000000011, arch::traits::opcode_e::C__FLDSP}, {16, 0b1010000000000010, 0b1110000000000011, arch::traits::opcode_e::C__FSDSP}, + {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, arch::traits::opcode_e::SFENCE__VMA}, + {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::SRET}, }}; //needs to be declared after instr_descr @@ -6178,6 +6180,42 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") + case arch::traits::opcode_e::SFENCE__VMA: { + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t asid = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {asid}", fmt::arg("mnemonic", "sfence.vma"), + fmt::arg("rs1", name(rs1)), fmt::arg("asid", name(asid))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fencevma, ((uint16_t)(uint8_t)rs1<<8)|(uint8_t)asid); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRET: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "sret"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + leave(1); + } + break; + }// @suppress("No break at end of case") default: { if(this->disass_enabled){ std::string mnemonic = "Illegal Instruction"; @@ -6229,7 +6267,17 @@ std::unique_ptr create(arch::rv64gc *core, unsigned short p namespace iss { namespace { -volatile std::array dummy = { +volatile std::array dummy = { + core_factory::instance().register_creator("rv64gc_msu:interp", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_msu_vp(); + auto vm = new interp::rv64gc::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), core_factory::instance().register_creator("rv64gc_m:interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::rv64gc::vm_impl(*cpu, false); From 423e8f6499f45661a30b38eed091c8179e23a801 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 16 Sep 2025 07:48:35 +0200 Subject: [PATCH 006/230] fixes templates, generation scripts and missing yamls files --- CMakeLists.txt | 11 + contrib/generate_custom_cores.sh | 83 +- contrib/instr/RV32GC_instr.yaml | 310 ++++--- contrib/instr/RV32IMACF_instr.yaml | 942 ---------------------- contrib/instr/RV64GC_instr.yaml | 372 +++++---- gen_input/templates/CORENAME_sysc.cpp.gtl | 16 +- 6 files changed, 404 insertions(+), 1330 deletions(-) delete mode 100644 contrib/instr/RV32IMACF_instr.yaml diff --git a/CMakeLists.txt b/CMakeLists.txt index 3215b3f..4ac229c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -53,16 +53,20 @@ set(LIB_SOURCES src/iss/arch/rv32imc.cpp src/iss/arch/rv32imac.cpp src/iss/arch/rv32gc.cpp + src/iss/arch/rv32gcv.cpp src/iss/arch/rv64i.cpp src/iss/arch/rv64gc.cpp + src/iss/arch/rv64gcv.cpp src/iss/arch/tgc5c.cpp src/iss/mem/memory_if.cpp src/vm/interp/vm_tgc5c.cpp src/vm/interp/vm_rv32i.cpp src/vm/interp/vm_rv32imac.cpp src/vm/interp/vm_rv32gc.cpp + src/vm/interp/vm_rv32gcv.cpp src/vm/interp/vm_rv64i.cpp src/vm/interp/vm_rv64gc.cpp + src/vm/interp/vm_rv64gcv.cpp src/vm/fp_functions.cpp src/vm/vector_functions.cpp src/iss/debugger/csr_names.cpp @@ -260,6 +264,13 @@ if(TARGET scc-sysc) src/sysc/core_complex.cpp src/sysc/register_cores.cpp ) + if(WITH_ASMJIT) + list(APPEND LIB_SOURCES + src/sysc/register_rv32gcv.cpp + src/sysc/register_rv64gcv.cpp + ) + endif() + if(IS_DIRECTORY "${PROJECT_SOURCE_DIR}/../dbt-rise-custom") FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/../dbt-rise-custom/src/sysc/register_*.cpp) list(APPEND LIB_SOURCES ${GEN_SC_SOURCES}) diff --git a/contrib/generate_custom_cores.sh b/contrib/generate_custom_cores.sh index 17db3cb..b7e7e72 100644 --- a/contrib/generate_custom_cores.sh +++ b/contrib/generate_custom_cores.sh @@ -1,6 +1,8 @@ #!/bin/bash ## +set -euo pipefail + # Absolute path to this script, e.g. /home/user/bin/foo.sh SCRIPT=`readlink -f "$0"` # Absolute path this script is in, thus /home/user/bin @@ -11,11 +13,13 @@ ROOT_DIR=$(realpath $MYSCRIPTDIR/../..) SCRIPTDIR=$ROOT_DIR/build/TGC-GEN/scripts CORE_DSL_DIR=$(realpath ${SCRIPTDIR}/../CoreDSL) +die() { echo "$*" 1>&2 ; exit 1; } + print_help() { echo "Usage: $SCRIPTNAME [-h] -c -v " echo "Generate RTL for TGC & custom cores" echo " -b list of backends to generate code for, default: '$BACKENDS'" - echo " -x use extended list of cores" + echo " -x generate extended list of cores, 1 -> all TGCs, 2 -> set of TGC?X" exit 0 } @@ -24,15 +28,22 @@ TMPL_DIR=${OUTPUT_ROOT}/gen_input/templates BACKENDS="interp asmjit" EXT_LIST=0 -while getopts 'b:hx' c; do +while getopts 'b:x:h' c; do case $c in - x) EXT_LIST=1 ;; + x) EXT_LIST=$OPTARG ;; b) BACKENDS=$OPTARG ;; h) print_help ;; ?) die "Unknown CLI option!" 255 esac done +case $EXT_LIST in + 0) ;; + 1) ;; + 2) ;; + ?) die "-x can only take value of 0, 1, or 2" 1 +esac + [[ -d $ROOT_DIR/build/TGC-GEN ]] || (cd build; git clone --recursive -b develop https://git.minres.com/TGFS/TGC-GEN.git ) # Generate standard cores @@ -40,49 +51,51 @@ for core in RV32I RV32IMAC RV32GC RV64I RV64GC; do for backend in ${BACKENDS}; do ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${TMPL_DIR}/../../gen_input/cores.core_desc done - python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast - python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow + #python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast + #python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow +done +for core in RV32GCV RV64GCV; do + echo ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b interp ${TMPL_DIR}/../../gen_input/cores.core_desc + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b interp ${TMPL_DIR}/../../gen_input/cores.core_desc + #python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast + #python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow done # Generate for TGC5C core=TGC5C for backend in ${BACKENDS}; do - echo ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc - ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc + echo ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc done unset core python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/TGC5C_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/TGC5C_fast.yaml -s fast python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/TGC5C_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/TGC5C_slow.yaml -s slow -exit -# Generate for other TGCs -OUTPUT_ROOT=${ROOT_DIR}/dbt-rise-custom -for core in TGC5A TGC5B TGC5D TGC5E TGC6B TGC6C TGC6D TGC6E; do - for backend in ${BACKENDS}; do - ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc - done - python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast - python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow -done -for core in TGC5C_XRB_NN; do - for backend in interp; do - ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc - python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast - python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow - done -done -for core in RV32GCV RV64GCV; do - echo ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b interp ${TMPL_DIR}/../../gen_input/cores.core_desc - ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b interp ${TMPL_DIR}/../../gen_input/cores.core_desc - python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast - python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow -done -# Generate extended list -if [ $EXT_LIST -ne 0 ]; then - for core in TGC5Xe TGC5Xi TGC5Xec TGC5Xic TGC5Xem TGC5Xim TGC5Xemc TGC5Ximc; do + +if [ $EXT_LIST -gt 0 ]; then + # Generate for other TGCs + OUTPUT_ROOT=${ROOT_DIR}/dbt-rise-custom + for core in TGC5A TGC5B TGC5D TGC5E TGC6B TGC6C TGC6D TGC6E; do for backend in ${BACKENDS}; do - ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -c $core -b ${backend} ${CORE_DSL_DIR}/TGC5.core_desc + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc done python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow done -fi + for core in TGC5C_XRB_NN; do + for backend in interp; do + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow + done + done + # Generate extended list + if [ $EXT_LIST -gt 1 ]; then + for core in TGC5Xe TGC5Xi TGC5Xec TGC5Xic TGC5Xem TGC5Xim TGC5Xemc TGC5Ximc; do + for backend in ${BACKENDS}; do + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -c $core -b ${backend} ${CORE_DSL_DIR}/TGC5.core_desc + done + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast + python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow + done + fi +fi \ No newline at end of file diff --git a/contrib/instr/RV32GC_instr.yaml b/contrib/instr/RV32GC_instr.yaml index a8e09f2..e98330e 100644 --- a/contrib/instr/RV32GC_instr.yaml +++ b/contrib/instr/RV32GC_instr.yaml @@ -704,7 +704,6 @@ RVF: index: 98 encoding: 0b00000000000000000010000000000111 mask: 0b00000000000000000111000001111111 - attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 @@ -715,194 +714,171 @@ RVF: size: 32 branch: false delay: 1 - FMADD__S: + FADD__S: index: 100 - encoding: 0b00000000000000000000000001000011 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00000000000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FMSUB__S: + FSUB__S: index: 101 - encoding: 0b00000000000000000000000001000111 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00001000000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FNMADD__S: + FMUL__S: index: 102 - encoding: 0b00000000000000000000000001001111 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00010000000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FNMSUB__S: + FDIV__S: index: 103 - encoding: 0b00000000000000000000000001001011 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00011000000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FADD__S: + FMIN__S: index: 104 - encoding: 0b00000000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00101000000000000000000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FSUB__S: + FMAX__S: index: 105 - encoding: 0b00001000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00101000000000000001000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FMUL__S: + FSQRT__S: index: 106 - encoding: 0b00010000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b01011000000000000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FDIV__S: + FMADD__S: index: 107 - encoding: 0b00011000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00000000000000000000000001000011 + mask: 0b00000110000000000000000001111111 size: 32 branch: false delay: 1 - FSQRT__S: + FMSUB__S: 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value:1]] + encoding: 0b11000000000000000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FMIN__S: + FCVT__WU__S: index: 112 - encoding: 0b00101000000000000000000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b11000000000100000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FMAX__S: + FCVT__S__W: index: 113 - encoding: 0b00101000000000000001000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b11010000000000000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FCVT__W__S: + FCVT__S__WU: index: 114 - encoding: 0b11000000000000000000000001010011 + encoding: 0b11010000000100000000000001010011 mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCVT__WU__S: + FSGNJ__S: index: 115 - encoding: 0b11000000000100000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00100000000000000000000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FEQ__S: + FSGNJN__S: index: 116 - encoding: 0b10100000000000000010000001010011 + encoding: 0b00100000000000000001000001010011 mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FLT__S: + FSGNJX__S: index: 117 - encoding: 0b10100000000000000001000001010011 + encoding: 0b00100000000000000010000001010011 mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FLE__S: + FMV__X__W: index: 118 - encoding: 0b10100000000000000000000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b11100000000000000000000001010011 + mask: 0b11111111111100000111000001111111 size: 32 branch: false delay: 1 - FCLASS__S: + FMV__W__X: index: 119 - encoding: 0b11100000000000000001000001010011 + encoding: 0b11110000000000000000000001010011 mask: 0b11111111111100000111000001111111 - attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCVT__S__W: + FEQ__S: index: 120 - encoding: 0b11010000000000000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b10100000000000000010000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT__S__WU: + FLT__S: index: 121 - encoding: 0b11010000000100000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b10100000000000000001000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FMV__X__W: + FLE__S: index: 122 - encoding: 0b11100000000000000000000001010011 - mask: 0b11111111111100000111000001111111 + encoding: 0b10100000000000000000000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FMV__W__X: + FCLASS__S: index: 123 - encoding: 0b11110000000000000000000001010011 + encoding: 0b11100000000000000001000001010011 mask: 0b11111111111100000111000001111111 - attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 @@ -954,171 +930,171 @@ RVD: size: 32 branch: false delay: 1 - FMADD_D: + FADD__D: index: 130 - encoding: 0b00000010000000000000000001000011 - mask: 0b00000110000000000000000001111111 + encoding: 0b00000010000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FMSUB_D: + FSUB__D: index: 131 - encoding: 0b00000010000000000000000001000111 - mask: 0b00000110000000000000000001111111 + encoding: 0b00001010000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FNMADD_D: + FMUL__D: index: 132 - encoding: 0b00000010000000000000000001001111 - mask: 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0b11010010000100000000000001010011 mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FCVT_D_S: + FCVT__S__D: index: 145 - encoding: 0b01000010000000000000000001010011 + encoding: 0b01000000000100000000000001010011 mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FEQ_D: + FCVT__D__S: index: 146 - encoding: 0b10100010000000000010000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b01000010000000000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FLT_D: + FSGNJ__D: index: 147 - encoding: 0b10100010000000000001000001010011 + encoding: 0b00100010000000000000000001010011 mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FLE_D: + FSGNJN__D: index: 148 - encoding: 0b10100010000000000000000001010011 + encoding: 0b00100010000000000001000001010011 mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCLASS_D: + FSGNJX__D: index: 149 - encoding: 0b11100010000000000001000001010011 - mask: 0b11111111111100000111000001111111 + encoding: 0b00100010000000000010000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_W_D: + FEQ__D: index: 150 - encoding: 0b11000010000000000000000001010011 - mask: 0b11111111111100000000000001111111 + encoding: 0b10100010000000000010000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_WU_D: + FLT__D: index: 151 - encoding: 0b11000010000100000000000001010011 - mask: 0b11111111111100000000000001111111 + encoding: 0b10100010000000000001000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_D_W: + FLE__D: index: 152 - encoding: 0b11010010000000000000000001010011 - mask: 0b11111111111100000000000001111111 + encoding: 0b10100010000000000000000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_D_WU: + FCLASS__D: index: 153 - encoding: 0b11010010000100000000000001010011 - mask: 0b11111111111100000000000001111111 + encoding: 0b11100010000000000001000001010011 + mask: 0b11111111111100000111000001111111 size: 32 branch: false delay: 1 @@ -1151,4 +1127,20 @@ Zcd: size: 16 branch: false delay: 1 +RVSMode: + SFENCE__VMA: + index: 158 + encoding: 0b00010010000000000000000001110011 + mask: 0b11111110000000000111111111111111 + size: 32 + branch: false + delay: 1 + SRET: + index: 159 + encoding: 0b00010000001000000000000001110011 + mask: 0b11111111111111111111111111111111 + attributes: [[name:no_cont]] + size: 32 + branch: false + delay: 1 diff --git a/contrib/instr/RV32IMACF_instr.yaml b/contrib/instr/RV32IMACF_instr.yaml deleted file mode 100644 index 1f4961b..0000000 --- a/contrib/instr/RV32IMACF_instr.yaml +++ /dev/null @@ -1,942 +0,0 @@ - -RVI: - LUI: - index: 0 - encoding: 0b00000000000000000000000000110111 - mask: 0b00000000000000000000000001111111 - size: 32 - branch: false - delay: 1 - AUIPC: - index: 1 - encoding: 0b00000000000000000000000000010111 - mask: 0b00000000000000000000000001111111 - size: 32 - branch: false - delay: 1 - JAL: - index: 2 - encoding: 0b00000000000000000000000001101111 - mask: 0b00000000000000000000000001111111 - size: 32 - branch: true - delay: 1 - JALR: - index: 3 - encoding: 0b00000000000000000000000001100111 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: true - delay: [1,1] - BEQ: - index: 4 - encoding: 0b00000000000000000000000001100011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: true - delay: [1,1] - BNE: - index: 5 - encoding: 0b00000000000000000001000001100011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: true - delay: [1,1] - BLT: - index: 6 - encoding: 0b00000000000000000100000001100011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: true - delay: [1,1] - BGE: - index: 7 - encoding: 0b00000000000000000101000001100011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: true - delay: [1,1] - BLTU: - index: 8 - encoding: 0b00000000000000000110000001100011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: true - delay: [1,1] - BGEU: - index: 9 - encoding: 0b00000000000000000111000001100011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: true - delay: [1,1] - LB: - index: 10 - encoding: 0b00000000000000000000000000000011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - LH: - index: 11 - encoding: 0b00000000000000000001000000000011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - LW: - index: 12 - encoding: 0b00000000000000000010000000000011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - LBU: - index: 13 - encoding: 0b00000000000000000100000000000011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - LHU: - index: 14 - encoding: 0b00000000000000000101000000000011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - SB: - index: 15 - encoding: 0b00000000000000000000000000100011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - SH: - index: 16 - encoding: 0b00000000000000000001000000100011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - SW: - index: 17 - encoding: 0b00000000000000000010000000100011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - ADDI: - index: 18 - encoding: 0b00000000000000000000000000010011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - SLTI: - index: 19 - encoding: 0b00000000000000000010000000010011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - SLTIU: - index: 20 - encoding: 0b00000000000000000011000000010011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - XORI: - index: 21 - encoding: 0b00000000000000000100000000010011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - ORI: - index: 22 - encoding: 0b00000000000000000110000000010011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - ANDI: - index: 23 - encoding: 0b00000000000000000111000000010011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - SLLI: - index: 24 - encoding: 0b00000000000000000001000000010011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - SRLI: - index: 25 - encoding: 0b00000000000000000101000000010011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - SRAI: - index: 26 - encoding: 0b01000000000000000101000000010011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - ADD: - index: 27 - encoding: 0b00000000000000000000000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - SUB: - index: 28 - encoding: 0b01000000000000000000000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - SLL: - index: 29 - encoding: 0b00000000000000000001000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - SLT: - index: 30 - encoding: 0b00000000000000000010000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - SLTU: - index: 31 - encoding: 0b00000000000000000011000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - XOR: - index: 32 - encoding: 0b00000000000000000100000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - SRL: - index: 33 - encoding: 0b00000000000000000101000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - SRA: - index: 34 - encoding: 0b01000000000000000101000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - OR: - index: 35 - encoding: 0b00000000000000000110000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - AND: - index: 36 - encoding: 0b00000000000000000111000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - FENCE: - index: 37 - encoding: 0b00000000000000000000000000001111 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - ECALL: - index: 38 - encoding: 0b00000000000000000000000001110011 - mask: 0b11111111111111111111111111111111 - attributes: [[name:no_cont]] - size: 32 - branch: false - delay: 1 - EBREAK: - index: 39 - encoding: 0b00000000000100000000000001110011 - mask: 0b11111111111111111111111111111111 - attributes: [[name:no_cont]] - size: 32 - branch: false - delay: 1 - MRET: - index: 40 - encoding: 0b00110000001000000000000001110011 - mask: 0b11111111111111111111111111111111 - attributes: [[name:no_cont]] - size: 32 - branch: false - delay: 1 - WFI: - index: 41 - encoding: 0b00010000010100000000000001110011 - mask: 0b11111111111111111111111111111111 - size: 32 - branch: false - delay: 1 -Zicsr: - CSRRW: - index: 42 - encoding: 0b00000000000000000001000001110011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - CSRRS: - index: 43 - encoding: 0b00000000000000000010000001110011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - CSRRC: - index: 44 - encoding: 0b00000000000000000011000001110011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - CSRRWI: - index: 45 - encoding: 0b00000000000000000101000001110011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - CSRRSI: - index: 46 - encoding: 0b00000000000000000110000001110011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - CSRRCI: - index: 47 - encoding: 0b00000000000000000111000001110011 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 -Zifencei: - FENCE_I: - index: 48 - encoding: 0b00000000000000000001000000001111 - mask: 0b00000000000000000111000001111111 - attributes: [[name:flush]] - size: 32 - branch: false - delay: 1 -RVM: - MUL: - index: 49 - encoding: 0b00000010000000000000000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - MULH: - index: 50 - encoding: 0b00000010000000000001000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - MULHSU: - index: 51 - encoding: 0b00000010000000000010000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - MULHU: - index: 52 - encoding: 0b00000010000000000011000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - DIV: - index: 53 - encoding: 0b00000010000000000100000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - DIVU: - index: 54 - encoding: 0b00000010000000000101000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - REM: - index: 55 - encoding: 0b00000010000000000110000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 - REMU: - index: 56 - encoding: 0b00000010000000000111000000110011 - mask: 0b11111110000000000111000001111111 - size: 32 - branch: false - delay: 1 -RVA: - LRW: - index: 57 - encoding: 0b00010000000000000010000000101111 - mask: 0b11111001111100000111000001111111 - size: 32 - branch: false - delay: 1 - SCW: - index: 58 - encoding: 0b00011000000000000010000000101111 - mask: 0b11111000000000000111000001111111 - size: 32 - branch: false - delay: 1 - AMOSWAPW: - index: 59 - encoding: 0b00001000000000000010000000101111 - mask: 0b11111000000000000111000001111111 - size: 32 - branch: false - delay: 1 - AMOADDW: - index: 60 - encoding: 0b00000000000000000010000000101111 - mask: 0b11111000000000000111000001111111 - size: 32 - branch: false - delay: 1 - AMOXORW: - index: 61 - encoding: 0b00100000000000000010000000101111 - mask: 0b11111000000000000111000001111111 - size: 32 - branch: false - delay: 1 - AMOANDW: - index: 62 - encoding: 0b01100000000000000010000000101111 - mask: 0b11111000000000000111000001111111 - size: 32 - branch: false - delay: 1 - AMOORW: - index: 63 - encoding: 0b01000000000000000010000000101111 - mask: 0b11111000000000000111000001111111 - size: 32 - branch: false - delay: 1 - AMOMINW: - index: 64 - encoding: 0b10000000000000000010000000101111 - mask: 0b11111000000000000111000001111111 - size: 32 - branch: false - delay: 1 - AMOMAXW: - index: 65 - encoding: 0b10100000000000000010000000101111 - mask: 0b11111000000000000111000001111111 - size: 32 - branch: false - delay: 1 - AMOMINUW: - index: 66 - encoding: 0b11000000000000000010000000101111 - mask: 0b11111000000000000111000001111111 - size: 32 - branch: false - delay: 1 - AMOMAXUW: - index: 67 - encoding: 0b11100000000000000010000000101111 - mask: 0b11111000000000000111000001111111 - size: 32 - branch: false - delay: 1 -Zca: - C__ADDI4SPN: - index: 68 - encoding: 0b0000000000000000 - mask: 0b1110000000000011 - size: 16 - branch: false - delay: 1 - C__LW: - index: 69 - encoding: 0b0100000000000000 - mask: 0b1110000000000011 - size: 16 - branch: false - delay: 1 - C__SW: - index: 70 - encoding: 0b1100000000000000 - mask: 0b1110000000000011 - size: 16 - branch: false - delay: 1 - C__ADDI: - index: 71 - encoding: 0b0000000000000001 - mask: 0b1110000000000011 - size: 16 - branch: false - delay: 1 - C__NOP: - index: 72 - encoding: 0b0000000000000001 - mask: 0b1110111110000011 - size: 16 - branch: false - delay: 1 - C__JAL: - index: 73 - encoding: 0b0010000000000001 - mask: 0b1110000000000011 - attributes: [[name:enable, value:1]] - size: 16 - branch: true - delay: 1 - C__LI: - index: 74 - encoding: 0b0100000000000001 - mask: 0b1110000000000011 - size: 16 - branch: false - delay: 1 - C__LUI: - index: 75 - encoding: 0b0110000000000001 - mask: 0b1110000000000011 - size: 16 - branch: false - delay: 1 - C__ADDI16SP: - index: 76 - encoding: 0b0110000100000001 - mask: 0b1110111110000011 - size: 16 - branch: false - delay: 1 - __reserved_clui: - index: 77 - encoding: 0b0110000000000001 - mask: 0b1111000001111111 - size: 16 - branch: false - delay: 1 - C__SRLI: - index: 78 - encoding: 0b1000000000000001 - mask: 0b1111110000000011 - attributes: [[name:enable, value:1]] - size: 16 - branch: false - delay: 1 - C__SRAI: - index: 79 - encoding: 0b1000010000000001 - mask: 0b1111110000000011 - attributes: [[name:enable, value:1]] - size: 16 - branch: false - delay: 1 - C__ANDI: - index: 80 - encoding: 0b1000100000000001 - mask: 0b1110110000000011 - size: 16 - branch: false - delay: 1 - C__SUB: - index: 81 - encoding: 0b1000110000000001 - mask: 0b1111110001100011 - size: 16 - branch: false - delay: 1 - C__XOR: - index: 82 - encoding: 0b1000110000100001 - mask: 0b1111110001100011 - size: 16 - branch: false - delay: 1 - C__OR: - index: 83 - encoding: 0b1000110001000001 - mask: 0b1111110001100011 - size: 16 - branch: false - delay: 1 - C__AND: - index: 84 - encoding: 0b1000110001100001 - mask: 0b1111110001100011 - size: 16 - branch: false - delay: 1 - C__J: - index: 85 - encoding: 0b1010000000000001 - mask: 0b1110000000000011 - size: 16 - branch: true - delay: 1 - C__BEQZ: - index: 86 - encoding: 0b1100000000000001 - mask: 0b1110000000000011 - size: 16 - branch: true - delay: [1,1] - C__BNEZ: - index: 87 - encoding: 0b1110000000000001 - mask: 0b1110000000000011 - size: 16 - branch: true - delay: [1,1] - C__SLLI: - index: 88 - encoding: 0b0000000000000010 - mask: 0b1111000000000011 - attributes: [[name:enable, value:1]] - size: 16 - branch: false - delay: 1 - C__LWSP: - index: 89 - encoding: 0b0100000000000010 - mask: 0b1110000000000011 - size: 16 - branch: false - delay: 1 - C__MV: - index: 90 - encoding: 0b1000000000000010 - mask: 0b1111000000000011 - size: 16 - branch: false - delay: 1 - C__JR: - index: 91 - encoding: 0b1000000000000010 - mask: 0b1111000001111111 - size: 16 - branch: true - delay: 1 - __reserved_cmv: - index: 92 - encoding: 0b1000000000000010 - mask: 0b1111111111111111 - size: 16 - branch: false - delay: 1 - C__ADD: - index: 93 - encoding: 0b1001000000000010 - mask: 0b1111000000000011 - size: 16 - branch: false - delay: 1 - C__JALR: - index: 94 - encoding: 0b1001000000000010 - mask: 0b1111000001111111 - size: 16 - branch: true - delay: 1 - C__EBREAK: - index: 95 - encoding: 0b1001000000000010 - mask: 0b1111111111111111 - size: 16 - branch: false - delay: 1 - C__SWSP: - index: 96 - encoding: 0b1100000000000010 - mask: 0b1110000000000011 - size: 16 - branch: false - delay: 1 - DII: - index: 97 - encoding: 0b0000000000000000 - mask: 0b1111111111111111 - size: 16 - branch: false - delay: 1 -RVF: - FLW: - index: 98 - encoding: 0b00000000000000000010000000000111 - mask: 0b00000000000000000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FSW: - index: 99 - encoding: 0b00000000000000000010000000100111 - mask: 0b00000000000000000111000001111111 - size: 32 - branch: false - delay: 1 - FMADD__S: - index: 100 - encoding: 0b00000000000000000000000001000011 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FMSUB__S: - index: 101 - encoding: 0b00000000000000000000000001000111 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FNMADD__S: - index: 102 - encoding: 0b00000000000000000000000001001111 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FNMSUB__S: - index: 103 - encoding: 0b00000000000000000000000001001011 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FADD__S: - index: 104 - encoding: 0b00000000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FSUB__S: - index: 105 - encoding: 0b00001000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FMUL__S: - index: 106 - encoding: 0b00010000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FDIV__S: - index: 107 - encoding: 0b00011000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FSQRT__S: - index: 108 - encoding: 0b01011000000000000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FSGNJ__S: - index: 109 - encoding: 0b00100000000000000000000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FSGNJN__S: - index: 110 - encoding: 0b00100000000000000001000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FSGNJX__S: - index: 111 - encoding: 0b00100000000000000010000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FMIN__S: - index: 112 - encoding: 0b00101000000000000000000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FMAX__S: - index: 113 - encoding: 0b00101000000000000001000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FCVT__W__S: - index: 114 - encoding: 0b11000000000000000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FCVT__WU__S: - index: 115 - encoding: 0b11000000000100000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FEQ__S: - index: 116 - encoding: 0b10100000000000000010000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FLT__S: - index: 117 - encoding: 0b10100000000000000001000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FLE__S: - index: 118 - encoding: 0b10100000000000000000000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FCLASS__S: - index: 119 - encoding: 0b11100000000000000001000001010011 - mask: 0b11111111111100000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FCVT__S__W: - index: 120 - encoding: 0b11010000000000000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FCVT__S__WU: - index: 121 - encoding: 0b11010000000100000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 - FMV__X__W: - index: 122 - encoding: 0b11100000000000000000000001010011 - mask: 0b11111111111100000111000001111111 - size: 32 - branch: false - delay: 1 - FMV__W__X: - index: 123 - encoding: 0b11110000000000000000000001010011 - mask: 0b11111111111100000111000001111111 - attributes: [[name:enable, value:1]] - size: 32 - branch: false - delay: 1 -Zcf: - C__FLW: - index: 124 - encoding: 0b0110000000000000 - mask: 0b1110000000000011 - attributes: [[name:enable, value:1]] - size: 16 - branch: false - delay: 1 - C__FSW: - index: 125 - encoding: 0b1110000000000000 - mask: 0b1110000000000011 - attributes: [[name:enable, value:1]] - size: 16 - branch: false - delay: 1 - C__FLWSP: - index: 126 - encoding: 0b0110000000000010 - mask: 0b1110000000000011 - attributes: [[name:enable, value:1]] - size: 16 - branch: false - delay: 1 - C__FSWSP: - index: 127 - encoding: 0b1110000000000010 - mask: 0b1110000000000011 - attributes: [[name:enable, value:1]] - size: 16 - branch: false - delay: 1 - diff --git a/contrib/instr/RV64GC_instr.yaml b/contrib/instr/RV64GC_instr.yaml index 5b507b4..c0374b9 100644 --- a/contrib/instr/RV64GC_instr.yaml +++ b/contrib/instr/RV64GC_instr.yaml @@ -979,7 +979,6 @@ RVF: index: 132 encoding: 0b00000000000000000010000000000111 mask: 0b00000000000000000111000001111111 - attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 @@ -990,179 +989,161 @@ RVF: size: 32 branch: false delay: 1 - FMADD__S: + FADD__S: index: 134 - encoding: 0b00000000000000000000000001000011 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00000000000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FMSUB__S: + FSUB__S: index: 135 - encoding: 0b00000000000000000000000001000111 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00001000000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FNMADD__S: + FMUL__S: index: 136 - encoding: 0b00000000000000000000000001001111 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00010000000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FNMSUB__S: + FDIV__S: index: 137 - encoding: 0b00000000000000000000000001001011 - mask: 0b00000110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00011000000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FADD__S: + FMIN__S: index: 138 - encoding: 0b00000000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00101000000000000000000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FSUB__S: + FMAX__S: index: 139 - encoding: 0b00001000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00101000000000000001000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FMUL__S: + FSQRT__S: index: 140 - encoding: 0b00010000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b01011000000000000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FDIV__S: + FMADD__S: index: 141 - encoding: 0b00011000000000000000000001010011 - mask: 0b11111110000000000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00000000000000000000000001000011 + mask: 0b00000110000000000000000001111111 size: 32 branch: false delay: 1 - FSQRT__S: + FMSUB__S: index: 142 - encoding: 0b01011000000000000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00000000000000000000000001000111 + mask: 0b00000110000000000000000001111111 size: 32 branch: false delay: 1 - FSGNJ__S: + FNMADD__S: index: 143 - encoding: 0b00100000000000000000000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00000000000000000000000001001111 + mask: 0b00000110000000000000000001111111 size: 32 branch: false delay: 1 - FSGNJN__S: + FNMSUB__S: index: 144 - encoding: 0b00100000000000000001000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00000000000000000000000001001011 + mask: 0b00000110000000000000000001111111 size: 32 branch: false delay: 1 - FSGNJX__S: + FCVT__W__S: index: 145 - encoding: 0b00100000000000000010000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b11000000000000000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FMIN__S: + FCVT__WU__S: index: 146 - encoding: 0b00101000000000000000000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b11000000000100000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FMAX__S: + FCVT__L__S: index: 147 - encoding: 0b00101000000000000001000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b11000000001000000000000001010011 + mask: 0b11111111111100000000000001111111 attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCVT__W__S: + FCVT__LU__S: index: 148 - encoding: 0b11000000000000000000000001010011 + encoding: 0b11000000001100000000000001010011 mask: 0b11111111111100000000000001111111 attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCVT__WU__S: + FCVT__S__W: index: 149 - encoding: 0b11000000000100000000000001010011 + encoding: 0b11010000000000000000000001010011 mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FEQ__S: + FCVT__S__WU: index: 150 - encoding: 0b10100000000000000010000001010011 - mask: 0b11111110000000000111000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b11010000000100000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FLT__S: + FCVT__S__L: index: 151 - encoding: 0b10100000000000000001000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b11010000001000000000000001010011 + mask: 0b11111111111100000000000001111111 attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FLE__S: + FCVT__S__LU: index: 152 - encoding: 0b10100000000000000000000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b11010000001100000000000001010011 + mask: 0b11111111111100000000000001111111 attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCLASS__S: + FSGNJ__S: index: 153 - encoding: 0b11100000000000000001000001010011 - mask: 0b11111111111100000111000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00100000000000000000000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT__S__W: + FSGNJN__S: index: 154 - encoding: 0b11010000000000000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00100000000000000001000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT__S__WU: + FSGNJX__S: index: 155 - encoding: 0b11010000000100000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b00100000000000000010000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 @@ -1177,39 +1158,34 @@ RVF: index: 157 encoding: 0b11110000000000000000000001010011 mask: 0b11111111111100000111000001111111 - attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCVT_L_S: + FEQ__S: index: 158 - encoding: 0b11000000001000000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b10100000000000000010000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_LU_S: + FLT__S: index: 159 - encoding: 0b11000000001100000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b10100000000000000001000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_S_L: + FLE__S: index: 160 - encoding: 0b11010000001000000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b10100000000000000000000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_S_LU: + FCLASS__S: index: 161 - encoding: 0b11010000001100000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b11100000000000000001000001010011 + mask: 0b11111111111100000111000001111111 size: 32 branch: false delay: 1 @@ -1228,219 +1204,219 @@ RVD: size: 32 branch: false delay: 1 - FMADD_D: + FADD__D: index: 164 - encoding: 0b00000010000000000000000001000011 - mask: 0b00000110000000000000000001111111 + encoding: 0b00000010000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FMSUB_D: + FSUB__D: index: 165 - encoding: 0b00000010000000000000000001000111 - mask: 0b00000110000000000000000001111111 + encoding: 0b00001010000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FNMADD_D: + FMUL__D: index: 166 - encoding: 0b00000010000000000000000001001111 - mask: 0b00000110000000000000000001111111 + encoding: 0b00010010000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FNMSUB_D: + FDIV__D: index: 167 - encoding: 0b00000010000000000000000001001011 - mask: 0b00000110000000000000000001111111 + encoding: 0b00011010000000000000000001010011 + mask: 0b11111110000000000000000001111111 size: 32 branch: false delay: 1 - FADD_D: + FMIN__D: index: 168 - encoding: 0b00000010000000000000000001010011 - mask: 0b11111110000000000000000001111111 + encoding: 0b00101010000000000000000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FSUB_D: + FMAX__D: index: 169 - encoding: 0b00001010000000000000000001010011 - mask: 0b11111110000000000000000001111111 + encoding: 0b00101010000000000001000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FMUL_D: + FSQRT__D: index: 170 - encoding: 0b00010010000000000000000001010011 - mask: 0b11111110000000000000000001111111 + encoding: 0b01011010000000000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FDIV_D: + FMADD__D: index: 171 - encoding: 0b00011010000000000000000001010011 - mask: 0b11111110000000000000000001111111 + encoding: 0b00000010000000000000000001000011 + mask: 0b00000110000000000000000001111111 size: 32 branch: false delay: 1 - FSQRT_D: + FMSUB__D: index: 172 - encoding: 0b01011010000000000000000001010011 - mask: 0b11111111111100000000000001111111 + encoding: 0b00000010000000000000000001000111 + mask: 0b00000110000000000000000001111111 size: 32 branch: false delay: 1 - FSGNJ_D: + FNMADD__D: index: 173 - encoding: 0b00100010000000000000000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b00000010000000000000000001001111 + mask: 0b00000110000000000000000001111111 size: 32 branch: false delay: 1 - FSGNJN_D: + FNMSUB__D: index: 174 - encoding: 0b00100010000000000001000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b00000010000000000000000001001011 + mask: 0b00000110000000000000000001111111 size: 32 branch: false delay: 1 - FSGNJX_D: + FCVT__W__D: index: 175 - encoding: 0b00100010000000000010000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b11000010000000000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FMIN_D: + FCVT__WU__D: index: 176 - encoding: 0b00101010000000000000000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b11000010000100000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FMAX_D: + FCVT__L__D: index: 177 - encoding: 0b00101010000000000001000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b11000010001000000000000001010011 + mask: 0b11111111111100000000000001111111 + attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCVT_S_D: + FCVT__LU__D: index: 178 - encoding: 0b01000000000100000000000001010011 + encoding: 0b11000010001100000000000001010011 mask: 0b11111111111100000000000001111111 + attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCVT_D_S: + FCVT__D__W: index: 179 - encoding: 0b01000010000000000000000001010011 + encoding: 0b11010010000000000000000001010011 mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FEQ_D: + FCVT__D__WU: index: 180 - encoding: 0b10100010000000000010000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b11010010000100000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FLT_D: + FCVT__D__L: index: 181 - encoding: 0b10100010000000000001000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b11010010001000000000000001010011 + mask: 0b11111111111100000000000001111111 + attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FLE_D: + FCVT__D__LU: index: 182 - encoding: 0b10100010000000000000000001010011 - mask: 0b11111110000000000111000001111111 + encoding: 0b11010010001100000000000001010011 + mask: 0b11111111111100000000000001111111 + attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCLASS_D: + FCVT__S__D: index: 183 - encoding: 0b11100010000000000001000001010011 - mask: 0b11111111111100000111000001111111 + encoding: 0b01000000000100000000000001010011 + mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FCVT_W_D: + FCVT__D__S: index: 184 - encoding: 0b11000010000000000000000001010011 + encoding: 0b01000010000000000000000001010011 mask: 0b11111111111100000000000001111111 size: 32 branch: false delay: 1 - FCVT_WU_D: + FSGNJ__D: index: 185 - encoding: 0b11000010000100000000000001010011 - mask: 0b11111111111100000000000001111111 + encoding: 0b00100010000000000000000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_D_W: + FSGNJN__D: index: 186 - encoding: 0b11010010000000000000000001010011 - mask: 0b11111111111100000000000001111111 + encoding: 0b00100010000000000001000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_D_WU: + FSGNJX__D: index: 187 - encoding: 0b11010010000100000000000001010011 - mask: 0b11111111111100000000000001111111 + encoding: 0b00100010000000000010000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_L_D: + FMV__X__D: index: 188 - encoding: 0b11000010001000000000000001010011 - mask: 0b11111111111100000000000001111111 + encoding: 0b11100010000000000000000001010011 + mask: 0b11111111111100000111000001111111 attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCVT_LU_D: + FMV__D__X: index: 189 - encoding: 0b11000010001100000000000001010011 - mask: 0b11111111111100000000000001111111 + encoding: 0b11110010000000000000000001010011 + mask: 0b11111111111100000111000001111111 attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 - FCVT_D_L: + FEQ__D: index: 190 - encoding: 0b11010010001000000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b10100010000000000010000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FCVT_D_LU: + FLT__D: index: 191 - encoding: 0b11010010001100000000000001010011 - mask: 0b11111111111100000000000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b10100010000000000001000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FMV_X_D: + FLE__D: index: 192 - encoding: 0b11100010000000000000000001010011 - mask: 0b11111111111100000111000001111111 - attributes: [[name:enable, value:1]] + encoding: 0b10100010000000000000000001010011 + mask: 0b11111110000000000111000001111111 size: 32 branch: false delay: 1 - FMV_D_X: + FCLASS__D: index: 193 - encoding: 0b11110010000000000000000001010011 + encoding: 0b11100010000000000001000001010011 mask: 0b11111111111100000111000001111111 - attributes: [[name:enable, value:1]] size: 32 branch: false delay: 1 @@ -1473,4 +1449,20 @@ Zcd: size: 16 branch: false delay: 1 +RVSMode: + SFENCE__VMA: + index: 198 + encoding: 0b00010010000000000000000001110011 + mask: 0b11111110000000000111111111111111 + size: 32 + branch: false + delay: 1 + SRET: + index: 199 + encoding: 0b00010000001000000000000001110011 + mask: 0b11111111111111111111111111111111 + attributes: [[name:no_cont]] + size: 32 + branch: false + delay: 1 diff --git a/gen_input/templates/CORENAME_sysc.cpp.gtl b/gen_input/templates/CORENAME_sysc.cpp.gtl index 016b9f1..5d9e1d7 100644 --- a/gen_input/templates/CORENAME_sysc.cpp.gtl +++ b/gen_input/templates/CORENAME_sysc.cpp.gtl @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -43,14 +44,14 @@ def array_count = coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCas namespace iss { namespace interp { using namespace sysc; -<% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) {%> +<% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) { %> volatile std::array ${coreDef.name.toLowerCase()}_init = { iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_msu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }),<% } else { %> -volatile std::array ${coreDef.name.toLowerCase()}_init = {<%}%> +volatile std::array ${coreDef.name.toLowerCase()}_init = {<% } %> iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); @@ -65,7 +66,7 @@ volatile std::array ${coreDef.name.toLowerCase()}_init = { auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; - })<%}}%> + })<%}%> }; } #if defined(WITH_LLVM) @@ -115,7 +116,14 @@ volatile std::array ${coreDef.name.toLowerCase()}_init = { #if defined(WITH_ASMJIT) namespace asmjit { using namespace sysc; -volatile std::array ${coreDef.name.toLowerCase()}_init = { +<% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) {%> +volatile std::array ${coreDef.name.toLowerCase()}_init = { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_msu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }),<% } else { %> +volatile std::array ${coreDef.name.toLowerCase()}_init = {<% } %> iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); auto* cpu = new sc_core_adapter>(cc); From 02fc8c4f8c6a4e1079ed07302dfe8b8dea764d84 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 16 Sep 2025 07:49:06 +0200 Subject: [PATCH 007/230] adds RV32GCV isa --- contrib/instr/RV32GCV_instr.yaml | 5545 ++++++ src/iss/arch/rv32gcv.cpp | 70 + src/iss/arch/rv32gcv.h | 1391 ++ src/sysc/register_rv32gcv.cpp | 99 + src/vm/interp/vm_rv32gcv.cpp | 30566 +++++++++++++++++++++++++++++ 5 files changed, 37671 insertions(+) create mode 100644 contrib/instr/RV32GCV_instr.yaml create mode 100644 src/iss/arch/rv32gcv.cpp create mode 100644 src/iss/arch/rv32gcv.h create mode 100644 src/sysc/register_rv32gcv.cpp create mode 100644 src/vm/interp/vm_rv32gcv.cpp diff --git a/contrib/instr/RV32GCV_instr.yaml b/contrib/instr/RV32GCV_instr.yaml new file mode 100644 index 0000000..7f230a6 --- /dev/null +++ b/contrib/instr/RV32GCV_instr.yaml @@ -0,0 +1,5545 @@ + +RVI: + LUI: + index: 0 + encoding: 0b00000000000000000000000000110111 + mask: 0b00000000000000000000000001111111 + size: 32 + branch: false + delay: 1 + AUIPC: + index: 1 + encoding: 0b00000000000000000000000000010111 + mask: 0b00000000000000000000000001111111 + size: 32 + branch: false + delay: 1 + JAL: + index: 2 + encoding: 0b00000000000000000000000001101111 + mask: 0b00000000000000000000000001111111 + size: 32 + branch: true + delay: 1 + JALR: + index: 3 + encoding: 0b00000000000000000000000001100111 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BEQ: + index: 4 + encoding: 0b00000000000000000000000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BNE: + index: 5 + encoding: 0b00000000000000000001000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BLT: + index: 6 + encoding: 0b00000000000000000100000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BGE: + index: 7 + encoding: 0b00000000000000000101000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BLTU: + index: 8 + encoding: 0b00000000000000000110000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BGEU: + index: 9 + encoding: 0b00000000000000000111000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + LB: + index: 10 + encoding: 0b00000000000000000000000000000011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + LH: + index: 11 + encoding: 0b00000000000000000001000000000011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + LW: + index: 12 + encoding: 0b00000000000000000010000000000011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + LBU: + index: 13 + encoding: 0b00000000000000000100000000000011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + LHU: + index: 14 + encoding: 0b00000000000000000101000000000011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SB: + index: 15 + encoding: 0b00000000000000000000000000100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SH: + index: 16 + encoding: 0b00000000000000000001000000100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SW: + index: 17 + encoding: 0b00000000000000000010000000100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + ADDI: + index: 18 + encoding: 0b00000000000000000000000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLTI: + index: 19 + encoding: 0b00000000000000000010000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLTIU: + index: 20 + encoding: 0b00000000000000000011000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + XORI: + index: 21 + encoding: 0b00000000000000000100000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + ORI: + index: 22 + encoding: 0b00000000000000000110000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + ANDI: + index: 23 + encoding: 0b00000000000000000111000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLLI: + index: 24 + encoding: 0b00000000000000000001000000010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SRLI: + index: 25 + encoding: 0b00000000000000000101000000010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SRAI: + index: 26 + encoding: 0b01000000000000000101000000010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + ADD: + index: 27 + encoding: 0b00000000000000000000000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SUB: + index: 28 + encoding: 0b01000000000000000000000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLL: + index: 29 + encoding: 0b00000000000000000001000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLT: + index: 30 + encoding: 0b00000000000000000010000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLTU: + index: 31 + encoding: 0b00000000000000000011000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + XOR: + index: 32 + encoding: 0b00000000000000000100000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SRL: + index: 33 + encoding: 0b00000000000000000101000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SRA: + index: 34 + encoding: 0b01000000000000000101000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + OR: + index: 35 + encoding: 0b00000000000000000110000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + AND: + index: 36 + encoding: 0b00000000000000000111000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FENCE: + index: 37 + encoding: 0b00000000000000000000000000001111 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + ECALL: + index: 38 + encoding: 0b00000000000000000000000001110011 + mask: 0b11111111111111111111111111111111 + attributes: [[name:no_cont]] + size: 32 + branch: false + delay: 1 + EBREAK: + index: 39 + encoding: 0b00000000000100000000000001110011 + mask: 0b11111111111111111111111111111111 + attributes: [[name:no_cont]] + size: 32 + branch: false + delay: 1 + MRET: + index: 40 + encoding: 0b00110000001000000000000001110011 + mask: 0b11111111111111111111111111111111 + attributes: [[name:no_cont]] + size: 32 + branch: false + delay: 1 + WFI: + index: 41 + encoding: 0b00010000010100000000000001110011 + mask: 0b11111111111111111111111111111111 + size: 32 + branch: false + delay: 1 +Zicsr: + CSRRW: + index: 42 + encoding: 0b00000000000000000001000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + CSRRS: + index: 43 + encoding: 0b00000000000000000010000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + CSRRC: + index: 44 + encoding: 0b00000000000000000011000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + CSRRWI: + index: 45 + encoding: 0b00000000000000000101000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + CSRRSI: + index: 46 + encoding: 0b00000000000000000110000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + CSRRCI: + index: 47 + encoding: 0b00000000000000000111000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 +Zifencei: + FENCE_I: + index: 48 + encoding: 0b00000000000000000001000000001111 + mask: 0b00000000000000000111000001111111 + attributes: [[name:flush]] + size: 32 + branch: false + delay: 1 +RVM: + MUL: + index: 49 + encoding: 0b00000010000000000000000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + MULH: + index: 50 + encoding: 0b00000010000000000001000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + MULHSU: + index: 51 + encoding: 0b00000010000000000010000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + MULHU: + index: 52 + encoding: 0b00000010000000000011000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + DIV: + index: 53 + encoding: 0b00000010000000000100000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + DIVU: + index: 54 + encoding: 0b00000010000000000101000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + REM: + index: 55 + encoding: 0b00000010000000000110000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + REMU: + index: 56 + encoding: 0b00000010000000000111000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 +RVA: + LRW: + index: 57 + encoding: 0b00010000000000000010000000101111 + mask: 0b11111001111100000111000001111111 + size: 32 + branch: false + delay: 1 + SCW: + index: 58 + encoding: 0b00011000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOSWAPW: + index: 59 + encoding: 0b00001000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOADDW: + index: 60 + encoding: 0b00000000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOXORW: + index: 61 + encoding: 0b00100000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOANDW: + index: 62 + encoding: 0b01100000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOORW: + index: 63 + encoding: 0b01000000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOMINW: + index: 64 + encoding: 0b10000000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOMAXW: + index: 65 + encoding: 0b10100000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOMINUW: + index: 66 + encoding: 0b11000000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOMAXUW: + index: 67 + encoding: 0b11100000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 +Zca: + C__ADDI4SPN: + index: 68 + encoding: 0b0000000000000000 + mask: 0b1110000000000011 + size: 16 + branch: false + delay: 1 + C__LW: + index: 69 + encoding: 0b0100000000000000 + mask: 0b1110000000000011 + size: 16 + branch: false + delay: 1 + C__SW: + index: 70 + encoding: 0b1100000000000000 + mask: 0b1110000000000011 + size: 16 + branch: false + delay: 1 + C__ADDI: + index: 71 + encoding: 0b0000000000000001 + mask: 0b1110000000000011 + size: 16 + branch: false + delay: 1 + C__NOP: + index: 72 + encoding: 0b0000000000000001 + mask: 0b1110111110000011 + size: 16 + branch: false + delay: 1 + C__JAL: + index: 73 + encoding: 0b0010000000000001 + mask: 0b1110000000000011 + attributes: [[name:enable, value:1]] + size: 16 + branch: true + delay: 1 + C__LI: + index: 74 + encoding: 0b0100000000000001 + mask: 0b1110000000000011 + size: 16 + branch: false + delay: 1 + C__LUI: + index: 75 + encoding: 0b0110000000000001 + mask: 0b1110000000000011 + size: 16 + branch: false + delay: 1 + C__ADDI16SP: + index: 76 + encoding: 0b0110000100000001 + mask: 0b1110111110000011 + size: 16 + branch: false + delay: 1 + __reserved_clui: + index: 77 + encoding: 0b0110000000000001 + mask: 0b1111000001111111 + size: 16 + branch: false + delay: 1 + C__SRLI: + index: 78 + encoding: 0b1000000000000001 + mask: 0b1111110000000011 + attributes: [[name:enable, value:1]] + size: 16 + branch: false + delay: 1 + C__SRAI: + index: 79 + encoding: 0b1000010000000001 + mask: 0b1111110000000011 + attributes: [[name:enable, value:1]] + size: 16 + branch: false + delay: 1 + C__ANDI: + index: 80 + encoding: 0b1000100000000001 + mask: 0b1110110000000011 + size: 16 + branch: false + delay: 1 + C__SUB: + index: 81 + encoding: 0b1000110000000001 + mask: 0b1111110001100011 + size: 16 + branch: false + delay: 1 + C__XOR: + index: 82 + encoding: 0b1000110000100001 + mask: 0b1111110001100011 + size: 16 + branch: false + delay: 1 + C__OR: + index: 83 + encoding: 0b1000110001000001 + mask: 0b1111110001100011 + size: 16 + branch: false + delay: 1 + C__AND: + index: 84 + encoding: 0b1000110001100001 + mask: 0b1111110001100011 + size: 16 + branch: false + delay: 1 + C__J: + index: 85 + encoding: 0b1010000000000001 + mask: 0b1110000000000011 + size: 16 + branch: true + delay: 1 + C__BEQZ: + index: 86 + encoding: 0b1100000000000001 + mask: 0b1110000000000011 + size: 16 + branch: true + delay: [1,1] + C__BNEZ: + index: 87 + encoding: 0b1110000000000001 + mask: 0b1110000000000011 + size: 16 + branch: true + delay: [1,1] + C__SLLI: + index: 88 + encoding: 0b0000000000000010 + mask: 0b1111000000000011 + attributes: [[name:enable, value:1]] + size: 16 + branch: false + delay: 1 + C__LWSP: + index: 89 + encoding: 0b0100000000000010 + mask: 0b1110000000000011 + size: 16 + branch: false + delay: 1 + C__MV: + index: 90 + encoding: 0b1000000000000010 + mask: 0b1111000000000011 + size: 16 + branch: false + delay: 1 + C__JR: + index: 91 + encoding: 0b1000000000000010 + mask: 0b1111000001111111 + size: 16 + branch: true + delay: 1 + __reserved_cmv: + index: 92 + encoding: 0b1000000000000010 + mask: 0b1111111111111111 + size: 16 + branch: false + delay: 1 + C__ADD: + index: 93 + encoding: 0b1001000000000010 + mask: 0b1111000000000011 + size: 16 + branch: false + delay: 1 + C__JALR: + index: 94 + encoding: 0b1001000000000010 + mask: 0b1111000001111111 + size: 16 + branch: true + delay: 1 + C__EBREAK: + index: 95 + encoding: 0b1001000000000010 + mask: 0b1111111111111111 + size: 16 + branch: false + delay: 1 + C__SWSP: + index: 96 + encoding: 0b1100000000000010 + mask: 0b1110000000000011 + size: 16 + branch: false + delay: 1 + DII: + index: 97 + encoding: 0b0000000000000000 + mask: 0b1111111111111111 + size: 16 + branch: false + delay: 1 +RVF: + FLW: + index: 98 + encoding: 0b00000000000000000010000000000111 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + FSW: + index: 99 + encoding: 0b00000000000000000010000000100111 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + FADD__S: + index: 100 + encoding: 0b00000000000000000000000001010011 + mask: 0b11111110000000000000000001111111 + size: 32 + branch: false + delay: 1 + FSUB__S: + index: 101 + encoding: 0b00001000000000000000000001010011 + mask: 0b11111110000000000000000001111111 + size: 32 + branch: false + delay: 1 + FMUL__S: + index: 102 + encoding: 0b00010000000000000000000001010011 + mask: 0b11111110000000000000000001111111 + size: 32 + branch: false + delay: 1 + FDIV__S: + index: 103 + encoding: 0b00011000000000000000000001010011 + mask: 0b11111110000000000000000001111111 + size: 32 + branch: false + delay: 1 + FMIN__S: + index: 104 + encoding: 0b00101000000000000000000001010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FMAX__S: + index: 105 + encoding: 0b00101000000000000001000001010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FSQRT__S: + index: 106 + encoding: 0b01011000000000000000000001010011 + mask: 0b11111111111100000000000001111111 + size: 32 + branch: false + delay: 1 + FMADD__S: + index: 107 + encoding: 0b00000000000000000000000001000011 + mask: 0b00000110000000000000000001111111 + size: 32 + branch: false + delay: 1 + FMSUB__S: + index: 108 + encoding: 0b00000000000000000000000001000111 + mask: 0b00000110000000000000000001111111 + size: 32 + branch: false + delay: 1 + FNMADD__S: + index: 109 + encoding: 0b00000000000000000000000001001111 + mask: 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1 + FSGNJN__S: + index: 116 + encoding: 0b00100000000000000001000001010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FSGNJX__S: + index: 117 + encoding: 0b00100000000000000010000001010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FMV__X__W: + index: 118 + encoding: 0b11100000000000000000000001010011 + mask: 0b11111111111100000111000001111111 + size: 32 + branch: false + delay: 1 + FMV__W__X: + index: 119 + encoding: 0b11110000000000000000000001010011 + mask: 0b11111111111100000111000001111111 + size: 32 + branch: false + delay: 1 + FEQ__S: + index: 120 + encoding: 0b10100000000000000010000001010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FLT__S: + index: 121 + encoding: 0b10100000000000000001000001010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FLE__S: + index: 122 + encoding: 0b10100000000000000000000001010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FCLASS__S: + index: 123 + encoding: 0b11100000000000000001000001010011 + mask: 0b11111111111100000111000001111111 + size: 32 + branch: false + delay: 1 +Zcf: + C__FLW: + index: 124 + encoding: 0b0110000000000000 + mask: 0b1110000000000011 + attributes: [[name:enable, value:1]] + size: 16 + branch: false + delay: 1 + C__FSW: + index: 125 + encoding: 0b1110000000000000 + mask: 0b1110000000000011 + attributes: [[name:enable, value:1]] + size: 16 + branch: false + delay: 1 + C__FLWSP: + index: 126 + encoding: 0b0110000000000010 + mask: 0b1110000000000011 + attributes: [[name:enable, value:1]] + size: 16 + branch: false + delay: 1 + C__FSWSP: + index: 127 + encoding: 0b1110000000000010 + mask: 0b1110000000000011 + attributes: [[name:enable, value:1]] + size: 16 + branch: false + delay: 1 +RVD: + FLD: + index: 128 + encoding: 0b00000000000000000011000000000111 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + FSD: + index: 129 + encoding: 0b00000000000000000011000000100111 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + FADD__D: + index: 130 + encoding: 0b00000010000000000000000001010011 + mask: 0b11111110000000000000000001111111 + size: 32 + branch: false + delay: 1 + FSUB__D: + index: 131 + encoding: 0b00001010000000000000000001010011 + mask: 0b11111110000000000000000001111111 + size: 32 + branch: false + delay: 1 + FMUL__D: + index: 132 + encoding: 0b00010010000000000000000001010011 + mask: 0b11111110000000000000000001111111 + size: 32 + branch: false + delay: 1 + FDIV__D: + index: 133 + encoding: 0b00011010000000000000000001010011 + mask: 0b11111110000000000000000001111111 + size: 32 + branch: false + delay: 1 + FMIN__D: + index: 134 + encoding: 0b00101010000000000000000001010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FMAX__D: + index: 135 + encoding: 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+ size: 32 + branch: false + delay: 1 + FCVT__WU__D: + index: 142 + encoding: 0b11000010000100000000000001010011 + mask: 0b11111111111100000000000001111111 + size: 32 + branch: false + delay: 1 + FCVT__D__W: + index: 143 + encoding: 0b11010010000000000000000001010011 + mask: 0b11111111111100000000000001111111 + size: 32 + branch: false + delay: 1 + FCVT__D__WU: + index: 144 + encoding: 0b11010010000100000000000001010011 + mask: 0b11111111111100000000000001111111 + size: 32 + branch: false + delay: 1 + FCVT__S__D: + index: 145 + encoding: 0b01000000000100000000000001010011 + mask: 0b11111111111100000000000001111111 + size: 32 + branch: false + delay: 1 + FCVT__D__S: + index: 146 + encoding: 0b01000010000000000000000001010011 + mask: 0b11111111111100000000000001111111 + size: 32 + branch: false + delay: 1 + FSGNJ__D: + index: 147 + encoding: 0b00100010000000000000000001010011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FSGNJN__D: + index: 148 + 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mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWSUBU__WV: + index: 490 + encoding: 0b11011000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWSUBU__WX: + index: 491 + encoding: 0b11011000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWADD__WV: + index: 492 + encoding: 0b11010100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWADD__WX: + index: 493 + encoding: 0b11010100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWSUB__WV: + index: 494 + encoding: 0b11011100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWSUB__WX: + index: 495 + encoding: 0b11011100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VZEXT__VF2: + index: 496 + encoding: 0b01001000000000110010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VSEXT__VF2: + index: 497 + encoding: 0b01001000000000111010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VZEXT__VF4: + index: 498 + encoding: 0b01001000000000100010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VSEXT__VF4: + index: 499 + encoding: 0b01001000000000101010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VZEXT__VF8: + index: 500 + encoding: 0b01001000000000010010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VSEXT__VF8: + index: 501 + encoding: 0b01001000000000011010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VADC__VVM: + index: 502 + encoding: 0b01000000000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VADC__VXM: + index: 503 + encoding: 0b01000000000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VADC__VIM: + index: 504 + encoding: 0b01000000000000000011000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VVM: + index: 505 + encoding: 0b01000100000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VXM: + index: 506 + encoding: 0b01000100000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VIM: + index: 507 + encoding: 0b01000100000000000011000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VV: + index: 508 + encoding: 0b01000110000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VX: + index: 509 + encoding: 0b01000110000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VI: + index: 510 + encoding: 0b01000110000000000011000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSBC__VVM: + index: 511 + encoding: 0b01001000000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSBC__VXM: + index: 512 + encoding: 0b01001000000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSBC__VVM: + index: 513 + encoding: 0b01001100000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSBC__VXM: + index: 514 + encoding: 0b01001100000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSBC__VV: + index: 515 + encoding: 0b01001110000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSBC__VX: + index: 516 + encoding: 0b01001110000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAND__VI: + index: 517 + encoding: 0b00100100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAND__VV: + index: 518 + encoding: 0b00100100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAND__VX: + index: 519 + encoding: 0b00100100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VOR__VI: + index: 520 + encoding: 0b00101000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VOR__VV: + index: 521 + encoding: 0b00101000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VOR__VX: + index: 522 + encoding: 0b00101000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VXOR__VI: + index: 523 + encoding: 0b00101100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VXOR__VV: + index: 524 + encoding: 0b00101100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VXOR__VX: + index: 525 + encoding: 0b00101100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSLL__VI: + index: 526 + encoding: 0b10010100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSLL__VV: + index: 527 + encoding: 0b10010100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSLL__VX: + index: 528 + encoding: 0b10010100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRL__VI: + index: 529 + encoding: 0b10100000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRL__VV: + index: 530 + encoding: 0b10100000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRL__VX: + index: 531 + encoding: 0b10100000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRA__VI: + index: 532 + encoding: 0b10100100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRA__VV: + index: 533 + encoding: 0b10100100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRA__VX: + index: 534 + encoding: 0b10100100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRL__WI: + index: 535 + encoding: 0b10110000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRL__WV: + index: 536 + encoding: 0b10110000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRL__WX: + index: 537 + encoding: 0b10110000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRA__WI: + index: 538 + encoding: 0b10110100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRA__WV: + index: 539 + encoding: 0b10110100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRA__WX: + index: 540 + encoding: 0b10110100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSEQ__VI: + index: 541 + encoding: 0b01100000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSEQ__VV: + index: 542 + encoding: 0b01100000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSEQ__VX: + index: 543 + encoding: 0b01100000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSNE__VI: + index: 544 + encoding: 0b01100100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSNE__VV: + index: 545 + encoding: 0b01100100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSNE__VX: + index: 546 + encoding: 0b01100100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLTU__VV: + index: 547 + encoding: 0b01101000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLTU__VX: + index: 548 + encoding: 0b01101000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLT__VV: + index: 549 + encoding: 0b01101100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLT__VX: + index: 550 + encoding: 0b01101100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLEU__VI: + index: 551 + encoding: 0b01110000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLEU__VV: + index: 552 + encoding: 0b01110000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLEU__VX: + index: 553 + encoding: 0b01110000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + 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0b01111100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMINU__VV: + index: 561 + encoding: 0b00010000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMINU__VX: + index: 562 + encoding: 0b00010000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMIN__VV: + index: 563 + encoding: 0b00010100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMIN__VX: + index: 564 + encoding: 0b00010100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMAXU__VV: + index: 565 + encoding: 0b00011000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMAXU__VX: + index: 566 + encoding: 0b00011000000000000100000001010111 + mask: 0b11111100000000000111000001111111 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0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VDIV__VX: + index: 580 + encoding: 0b10000100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREMU__VV: + index: 581 + encoding: 0b10001000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREMU__VX: + index: 582 + encoding: 0b10001000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREM__VV: + index: 583 + encoding: 0b10001100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREM__VX: + index: 584 + encoding: 0b10001100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMUL__VV: + index: 585 + encoding: 0b11101100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMUL__VX: + index: 586 + encoding: 0b11101100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMULU__VV: + index: 587 + encoding: 0b11100000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMULU__VX: + index: 588 + encoding: 0b11100000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMULSU__VV: + index: 589 + encoding: 0b11101000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMULSU__VX: + index: 590 + encoding: 0b11101000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMACC__VV: + index: 591 + encoding: 0b10110100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMACC__VX: + index: 592 + encoding: 0b10110100000000000110000001010111 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0b11111000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMERGE__VIM: + index: 606 + encoding: 0b01011100000000000011000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMERGE__VVM: + index: 607 + encoding: 0b01011100000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMERGE__VXM: + index: 608 + encoding: 0b01011100000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMV__V__I: + index: 609 + encoding: 0b01011110000000000011000001010111 + mask: 0b11111111111100000111000001111111 + size: 32 + branch: false + delay: 1 + VMV__V__V: + index: 610 + encoding: 0b01011110000000000000000001010111 + mask: 0b11111111111100000111000001111111 + size: 32 + branch: false + delay: 1 + VMV__V__X: + index: 611 + encoding: 0b01011110000000000100000001010111 + mask: 0b11111111111100000111000001111111 + size: 32 + branch: false + delay: 1 +RVVBase_fixed: + VSADDU__VI: + index: 612 + encoding: 0b10000000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSADDU__VV: + index: 613 + encoding: 0b10000000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSADDU__VX: + index: 614 + encoding: 0b10000000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSADD__VI: + index: 615 + encoding: 0b10000100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSADD__VV: + index: 616 + encoding: 0b10000100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSADD__VX: + index: 617 + encoding: 0b10000100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSUBU__VV: + index: 618 + encoding: 0b10001000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSUBU__VX: + index: 619 + encoding: 0b10001000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSUB__VV: + index: 620 + encoding: 0b10001100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSUB__VX: + index: 621 + encoding: 0b10001100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAADDU__VV: + index: 622 + encoding: 0b00100000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAADDU__VX: + index: 623 + encoding: 0b00100000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAADD__VV: + index: 624 + encoding: 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0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSMUL__VX: + index: 631 + encoding: 0b10011100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRL__VI: + index: 632 + encoding: 0b10101000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRL__VV: + index: 633 + encoding: 0b10101000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRL__VX: + index: 634 + encoding: 0b10101000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRA__VI: + index: 635 + encoding: 0b10101100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRA__VV: + index: 636 + encoding: 0b10101100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + 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0b00111000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSLIDE1DOWN__VX: + index: 682 + encoding: 0b00111100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VRGATHER__VI: + index: 683 + encoding: 0b00110000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VRGATHER__VV: + index: 684 + encoding: 0b00110000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VRGATHER__VX: + index: 685 + encoding: 0b00110000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VRGATHEREI16__VV: + index: 686 + encoding: 0b00111000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VCOMPRESS__VM: + index: 687 + encoding: 0b01011110000000000010000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMV1R__V: + index: 688 + encoding: 0b10011110000000000011000001010111 + mask: 0b11111110000011111111000001111111 + size: 32 + branch: false + delay: 1 + VMV2R__V: + index: 689 + encoding: 0b10011110000000001011000001010111 + mask: 0b11111110000011111111000001111111 + size: 32 + branch: false + delay: 1 + VMV4R__V: + index: 690 + encoding: 0b10011110000000011011000001010111 + mask: 0b11111110000011111111000001111111 + size: 32 + branch: false + delay: 1 + VMV8R__V: + index: 691 + encoding: 0b10011110000000111011000001010111 + mask: 0b11111110000011111111000001111111 + size: 32 + branch: false + delay: 1 +RVVBase_perm_fp: + VFMV__S__F: + index: 692 + encoding: 0b01000010000000000101000001010111 + mask: 0b11111111111100000111000001111111 + size: 32 + branch: false + delay: 1 + VFMV__F__S: + index: 693 + encoding: 0b01000010000000000001000001010111 + mask: 0b11111110000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFSLIDE1UP__VF: + index: 694 + encoding: 0b00111000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSLIDE1DOWN__VF: + index: 695 + encoding: 0b00111100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 +RVVBase_fp: + VFADD__VF: + index: 696 + encoding: 0b00000000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFADD__VV: + index: 697 + encoding: 0b00000000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSUB__VF: + index: 698 + encoding: 0b00001000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSUB__VV: + index: 699 + encoding: 0b00001000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFRSUB__VF: + index: 700 + encoding: 0b10011100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWADD__VF: + index: 701 + encoding: 0b11000000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWADD__VV: + index: 702 + encoding: 0b11000000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWSUB__VF: + index: 703 + encoding: 0b11001000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWSUB__VV: + index: 704 + encoding: 0b11001000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWADD__WF: + index: 705 + encoding: 0b11010000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWADD__WV: + index: 706 + encoding: 0b11010000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWSUB__WF: + index: 707 + encoding: 0b11011000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWSUB__WV: + index: 708 + encoding: 0b11011000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMUL__VF: + index: 709 + encoding: 0b10010000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMUL__VV: + index: 710 + encoding: 0b10010000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFDIV__VF: + index: 711 + encoding: 0b10000000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFDIV__VV: + index: 712 + encoding: 0b10000000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFRDIV__VF: + index: 713 + encoding: 0b10000100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMUL__VF: + index: 714 + encoding: 0b11100000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMUL__VV: + index: 715 + encoding: 0b11100000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMACC__VF: + index: 716 + encoding: 0b10110000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMACC__VV: + index: 717 + encoding: 0b10110000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMACC__VF: + index: 718 + encoding: 0b10110100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMACC__VV: + index: 719 + encoding: 0b10110100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMSAC__VF: + index: 720 + encoding: 0b10111000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMSAC__VV: + index: 721 + encoding: 0b10111000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMSAC__VF: + index: 722 + encoding: 0b10111100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMSAC__VV: + index: 723 + encoding: 0b10111100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMADD__VF: + index: 724 + encoding: 0b10100000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMADD__VV: + index: 725 + encoding: 0b10100000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMADD__VF: + index: 726 + encoding: 0b10100100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMADD__VV: + index: 727 + encoding: 0b10100100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMSUB__VF: + index: 728 + encoding: 0b10101000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMSUB__VV: + index: 729 + encoding: 0b10101000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMSUB__VF: + index: 730 + encoding: 0b10101100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMSUB__VV: + index: 731 + encoding: 0b10101100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMACC__VF: + index: 732 + encoding: 0b11110000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMACC__VV: + index: 733 + encoding: 0b11110000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWNMACC__VF: + index: 734 + encoding: 0b11110100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWNMACC__VV: + index: 735 + encoding: 0b11110100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMSAC__VF: + index: 736 + encoding: 0b11111000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMSAC__VV: + index: 737 + encoding: 0b11111000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWNMSAC__VF: + index: 738 + encoding: 0b11111100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWNMSAC__VV: + index: 739 + encoding: 0b11111100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSQRT__V: + index: 740 + encoding: 0b01001100000000000001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFRSQRT7__V: + index: 741 + encoding: 0b01001100000000100001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFREC7__V: + index: 742 + encoding: 0b01001100000000101001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFMIN__VF: + index: 743 + encoding: 0b00010000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMIN__VV: + index: 744 + encoding: 0b00010000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMAX__VF: + index: 745 + encoding: 0b00011000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMAX__VV: + index: 746 + encoding: 0b00011000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJ__VF: + index: 747 + encoding: 0b00100000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJ__VV: + index: 748 + encoding: 0b00100000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJN__VF: + index: 749 + encoding: 0b00100100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJN__VV: + index: 750 + encoding: 0b00100100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJX__VF: + index: 751 + encoding: 0b00101000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJX__VV: + index: 752 + encoding: 0b00101000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFEQ__VF: + index: 753 + encoding: 0b01100000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFEQ__VV: + index: 754 + encoding: 0b01100000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFNE__VF: + index: 755 + encoding: 0b01110000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFNE__VV: + index: 756 + encoding: 0b01110000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFLT__VF: + index: 757 + encoding: 0b01101100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFLT__VV: + index: 758 + encoding: 0b01101100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFLE__VF: + index: 759 + encoding: 0b01100100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFLE__VV: + index: 760 + encoding: 0b01100100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFGT__VF: + index: 761 + encoding: 0b01110100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFGE__VF: + index: 762 + encoding: 0b01111100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFCLASS__V: + index: 763 + encoding: 0b01001100000010000001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFMERGE__VFM: + index: 764 + encoding: 0b01011100000000000101000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMV__V__F: + index: 765 + encoding: 0b01011110000000000101000001010111 + mask: 0b11111111111100000111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__XU__F__V: + index: 766 + encoding: 0b01001000000000000001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__X__F__V: + index: 767 + encoding: 0b01001000000000001001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__RTZ__XU__F__V: + index: 768 + encoding: 0b01001000000000110001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__RTZ__X__F__V: + index: 769 + encoding: 0b01001000000000111001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__F__XU__V: + index: 770 + encoding: 0b01001000000000010001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__F__X__V: + index: 771 + encoding: 0b01001000000000011001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__XU__F__V: + index: 772 + encoding: 0b01001000000001000001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__X__F__V: + index: 773 + encoding: 0b01001000000001001001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__RTZ__XU__F__V: + index: 774 + encoding: 0b01001000000001110001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__RTZ__X__F__V: + index: 775 + encoding: 0b01001000000001111001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__F__XU__V: + index: 776 + encoding: 0b01001000000001010001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__F__X__V: + index: 777 + encoding: 0b01001000000001011001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__F__F__V: + index: 778 + encoding: 0b01001000000001100001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__X__F__W: + index: 779 + encoding: 0b01001000000010001001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__XU__F__W: + index: 780 + encoding: 0b01001000000010000001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__RTZ__XU__F__W: + index: 781 + encoding: 0b01001000000010110001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__RTZ__X__F__W: + index: 782 + encoding: 0b01001000000010111001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__F__XU__W: + index: 783 + encoding: 0b01001000000010010001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__F__X__W: + index: 784 + encoding: 0b01001000000010011001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__F__F__W: + index: 785 + encoding: 0b01001000000010100001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__ROD__F__F__W: + index: 786 + encoding: 0b01001000000010101001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + diff --git a/src/iss/arch/rv32gcv.cpp b/src/iss/arch/rv32gcv.cpp new file mode 100644 index 0000000..ffd5b8e --- /dev/null +++ b/src/iss/arch/rv32gcv.cpp @@ -0,0 +1,70 @@ +/******************************************************************************* + * Copyright (C) 2024 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +// clang-format off +#include "rv32gcv.h" +#include "util/ities.h" +#include +#include +#include +#include + +using namespace iss::arch; + +constexpr std::array iss::arch::traits::reg_names; +constexpr std::array iss::arch::traits::reg_aliases; +constexpr std::array iss::arch::traits::reg_bit_widths; +constexpr std::array iss::arch::traits::reg_byte_offsets; + +rv32gcv::rv32gcv() = default; + +rv32gcv::~rv32gcv() = default; + +void rv32gcv::reset(uint64_t address) { + auto base_ptr = reinterpret_cast::reg_t*>(get_regs_base_ptr()); + for(size_t i=0; i::NUM_REGS; ++i) + *(base_ptr+i)=0; + reg.PC=address; + reg.NEXT_PC=reg.PC; + reg.PRIV=0x3; + reg.trap_state=0; + reg.icount=0; +} + +uint8_t *rv32gcv::get_regs_base_ptr() { + return reinterpret_cast(®); +} + +rv32gcv::phys_addr_t rv32gcv::virt2phys(const iss::addr_t &addr) { + return phys_addr_t(addr.access, addr.space, addr.val&traits::addr_mask); +} +// clang-format on diff --git a/src/iss/arch/rv32gcv.h b/src/iss/arch/rv32gcv.h new file mode 100644 index 0000000..d087ca2 --- /dev/null +++ b/src/iss/arch/rv32gcv.h @@ -0,0 +1,1391 @@ +/******************************************************************************* + * Copyright (C) 2024 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +#ifndef _RV32GCV_H_ +#define _RV32GCV_H_ +// clang-format off +#include +#include +#include +#include + +namespace iss { +namespace arch { + +struct rv32gcv: public arch_if { + + using reg_t = uint32_t; + + using virt_addr_t = iss::virt_addr_t; + + using phys_addr_t = iss::phys_addr_t; + + rv32gcv(); + ~rv32gcv(); + + void reset(uint64_t address=0) override; + + uint8_t* get_regs_base_ptr() override; + + inline bool should_stop() { return interrupt_sim; } + + inline uint64_t stop_code() { return interrupt_sim; } + + virtual phys_addr_t virt2phys(const iss::addr_t& addr); + + virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } + + +#pragma pack(push, 1) + struct RV32GCV_regs { + uint32_t X0 = 0; + uint32_t X1 = 0; + uint32_t X2 = 0; + uint32_t X3 = 0; + uint32_t X4 = 0; + uint32_t X5 = 0; + uint32_t X6 = 0; + uint32_t X7 = 0; + uint32_t X8 = 0; + uint32_t X9 = 0; + uint32_t X10 = 0; + uint32_t X11 = 0; + uint32_t X12 = 0; + uint32_t X13 = 0; + uint32_t X14 = 0; + uint32_t X15 = 0; + uint32_t X16 = 0; + uint32_t X17 = 0; + uint32_t X18 = 0; + uint32_t X19 = 0; + uint32_t X20 = 0; + uint32_t X21 = 0; + uint32_t X22 = 0; + uint32_t X23 = 0; + uint32_t X24 = 0; + uint32_t X25 = 0; + uint32_t X26 = 0; + uint32_t X27 = 0; + uint32_t X28 = 0; + uint32_t X29 = 0; + uint32_t X30 = 0; + uint32_t X31 = 0; + uint32_t PC = 0; + uint32_t NEXT_PC = 0; + uint8_t PRIV = 0; + uint32_t DPC = 0; + uint64_t F0 = 0; + uint64_t F1 = 0; + uint64_t F2 = 0; + uint64_t F3 = 0; + uint64_t F4 = 0; + uint64_t F5 = 0; + uint64_t F6 = 0; + uint64_t F7 = 0; + uint64_t F8 = 0; + uint64_t F9 = 0; + uint64_t F10 = 0; + uint64_t F11 = 0; + uint64_t F12 = 0; + uint64_t F13 = 0; + uint64_t F14 = 0; + uint64_t F15 = 0; + uint64_t F16 = 0; + uint64_t F17 = 0; + uint64_t F18 = 0; + uint64_t F19 = 0; + uint64_t F20 = 0; + uint64_t F21 = 0; + uint64_t F22 = 0; + uint64_t F23 = 0; + uint64_t F24 = 0; + uint64_t F25 = 0; + uint64_t F26 = 0; + uint64_t F27 = 0; + uint64_t F28 = 0; + uint64_t F29 = 0; + uint64_t F30 = 0; + uint64_t F31 = 0; + uint32_t FCSR = 0; + uint8_t V0[32] = {0}; + uint8_t V1[32] = {0}; + uint8_t V2[32] = {0}; + uint8_t V3[32] = {0}; + uint8_t V4[32] = {0}; + uint8_t V5[32] = {0}; + uint8_t V6[32] = {0}; + uint8_t V7[32] = {0}; + uint8_t V8[32] = {0}; + uint8_t V9[32] = {0}; + uint8_t V10[32] = {0}; + uint8_t V11[32] = {0}; + uint8_t V12[32] = {0}; + uint8_t V13[32] = {0}; + uint8_t V14[32] = {0}; + uint8_t V15[32] = {0}; + uint8_t V16[32] = {0}; + uint8_t V17[32] = {0}; + uint8_t V18[32] = {0}; + uint8_t V19[32] = {0}; + uint8_t V20[32] = {0}; + uint8_t V21[32] = {0}; + uint8_t V22[32] = {0}; + uint8_t V23[32] = {0}; + uint8_t V24[32] = {0}; + uint8_t V25[32] = {0}; + uint8_t V26[32] = {0}; + uint8_t V27[32] = {0}; + uint8_t V28[32] = {0}; + uint8_t V29[32] = {0}; + uint8_t V30[32] = {0}; + uint8_t V31[32] = {0}; + uint32_t vstart = 0; + uint32_t vxsat = 0; + uint32_t vxrm = 0; + uint32_t vl = 0; + uint32_t vtype = 0; + uint32_t trap_state = 0, pending_trap = 0; + uint64_t icount = 0; + uint64_t cycle = 0; + uint64_t instret = 0; + uint32_t instruction = 0; + uint32_t last_branch = 0; + } reg; +#pragma pack(pop) + std::array addr_mode; + + uint64_t interrupt_sim=0; + + uint32_t get_fcsr(){return reg.FCSR;} + void set_fcsr(uint32_t val){reg.FCSR = val;} + + uint32_t get_vstart(){return reg.vstart;} + void set_vstart(uint32_t val){reg.vstart = val;} + uint32_t get_vl(){return reg.vl;} + uint32_t get_vtype(){return reg.vtype;} + uint32_t get_vxsat(){return reg.vxsat;} + void set_vxsat(uint32_t val){reg.vxsat = val;} + uint32_t get_vxrm(){return reg.vxrm;} + void set_vxrm(uint32_t val){reg.vxrm = val;} + +}; + +struct rv32gcv; + +template <> struct traits { + + constexpr static char const* const core_type = "RV32GCV"; + + static constexpr std::array reg_names{ + {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "vstart", "vxsat", "vxrm", "vl", "vtype"}}; + + static constexpr std::array reg_aliases{ + {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "vstart", "vxsat", "vxrm", "vl", "vtype"}}; + + enum constants { + RV_CSR_FFLAGS=1ULL, RV_CSR_FRM=2ULL, RV_CSR_FCSR=3ULL, RV_CSR_UTVT=7ULL, + RV_CSR_VSTART=8ULL, RV_CSR_VXSAT=9ULL, RV_CSR_VXRM=10ULL, RV_CSR_VCSR=15ULL, + RV_CSR_SEED=21ULL, RV_CSR_UNXTI=69ULL, RV_CSR_UINTSTATUS=70ULL, RV_CSR_USCRATCHCSW=72ULL, + RV_CSR_USCRATCHCSWL=73ULL, RV_CSR_SSTATUS=256ULL, RV_CSR_SEDELEG=258ULL, RV_CSR_SIDELEG=259ULL, + RV_CSR_SIE=260ULL, RV_CSR_STVEC=261ULL, RV_CSR_SCOUNTEREN=262ULL, RV_CSR_STVT=263ULL, + RV_CSR_SENVCFG=266ULL, RV_CSR_SSTATEEN0=268ULL, RV_CSR_SSTATEEN1=269ULL, RV_CSR_SSTATEEN2=270ULL, + RV_CSR_SSTATEEN3=271ULL, RV_CSR_SSCRATCH=320ULL, RV_CSR_SEPC=321ULL, RV_CSR_SCAUSE=322ULL, + RV_CSR_STVAL=323ULL, RV_CSR_SIP=324ULL, RV_CSR_SNXTI=325ULL, RV_CSR_SINTSTATUS=326ULL, + RV_CSR_SSCRATCHCSW=328ULL, RV_CSR_SSCRATCHCSWL=329ULL, RV_CSR_STIMECMP=333ULL, RV_CSR_STIMECMPH=349ULL, + RV_CSR_SATP=384ULL, RV_CSR_VSSTATUS=512ULL, RV_CSR_VSIE=516ULL, RV_CSR_VSTVEC=517ULL, + RV_CSR_VSSCRATCH=576ULL, RV_CSR_VSEPC=577ULL, RV_CSR_VSCAUSE=578ULL, RV_CSR_VSTVAL=579ULL, + RV_CSR_VSIP=580ULL, RV_CSR_VSTIMECMP=589ULL, RV_CSR_VSTIMECMPH=605ULL, RV_CSR_VSATP=640ULL, + RV_CSR_MSTATUS=768ULL, RV_CSR_MISA=769ULL, RV_CSR_MEDELEG=770ULL, RV_CSR_MIDELEG=771ULL, + RV_CSR_MIE=772ULL, RV_CSR_MTVEC=773ULL, RV_CSR_MCOUNTEREN=774ULL, RV_CSR_MTVT=775ULL, + RV_CSR_MENVCFG=778ULL, RV_CSR_MSTATEEN0=780ULL, RV_CSR_MSTATEEN1=781ULL, RV_CSR_MSTATEEN2=782ULL, + RV_CSR_MSTATEEN3=783ULL, RV_CSR_MSTATUSH=784ULL, RV_CSR_MENVCFGH=794ULL, RV_CSR_MSTATEEN0H=796ULL, + RV_CSR_MSTATEEN1H=797ULL, RV_CSR_MSTATEEN2H=798ULL, RV_CSR_MSTATEEN3H=799ULL, RV_CSR_MCOUNTINHIBIT=800ULL, + RV_CSR_MHPMEVENT3=803ULL, RV_CSR_MHPMEVENT4=804ULL, RV_CSR_MHPMEVENT5=805ULL, RV_CSR_MHPMEVENT6=806ULL, + RV_CSR_MHPMEVENT7=807ULL, RV_CSR_MHPMEVENT8=808ULL, RV_CSR_MHPMEVENT9=809ULL, RV_CSR_MHPMEVENT10=810ULL, + RV_CSR_MHPMEVENT11=811ULL, RV_CSR_MHPMEVENT12=812ULL, RV_CSR_MHPMEVENT13=813ULL, RV_CSR_MHPMEVENT14=814ULL, + RV_CSR_MHPMEVENT15=815ULL, RV_CSR_MHPMEVENT16=816ULL, RV_CSR_MHPMEVENT17=817ULL, RV_CSR_MHPMEVENT18=818ULL, + RV_CSR_MHPMEVENT19=819ULL, RV_CSR_MHPMEVENT20=820ULL, RV_CSR_MHPMEVENT21=821ULL, RV_CSR_MHPMEVENT22=822ULL, + RV_CSR_MHPMEVENT23=823ULL, RV_CSR_MHPMEVENT24=824ULL, RV_CSR_MHPMEVENT25=825ULL, RV_CSR_MHPMEVENT26=826ULL, + RV_CSR_MHPMEVENT27=827ULL, RV_CSR_MHPMEVENT28=828ULL, RV_CSR_MHPMEVENT29=829ULL, RV_CSR_MHPMEVENT30=830ULL, + RV_CSR_MHPMEVENT31=831ULL, RV_CSR_MSCRATCH=832ULL, RV_CSR_MEPC=833ULL, RV_CSR_MCAUSE=834ULL, + RV_CSR_MTVAL=835ULL, RV_CSR_MIP=836ULL, RV_CSR_MNXTI=837ULL, RV_CSR_MINTSTATUS=838ULL, + RV_CSR_MSCRATCHCSW=840ULL, RV_CSR_MSCRATCHCSWL=841ULL, RV_CSR_MTINST=842ULL, RV_CSR_MTVAL2=843ULL, + RV_CSR_PMPCFG0=928ULL, RV_CSR_PMPCFG1=929ULL, RV_CSR_PMPCFG2=930ULL, RV_CSR_PMPCFG3=931ULL, + RV_CSR_PMPCFG4=932ULL, RV_CSR_PMPCFG5=933ULL, RV_CSR_PMPCFG6=934ULL, RV_CSR_PMPCFG7=935ULL, + RV_CSR_PMPCFG8=936ULL, RV_CSR_PMPCFG9=937ULL, RV_CSR_PMPCFG10=938ULL, RV_CSR_PMPCFG11=939ULL, + RV_CSR_PMPCFG12=940ULL, RV_CSR_PMPCFG13=941ULL, RV_CSR_PMPCFG14=942ULL, RV_CSR_PMPCFG15=943ULL, + RV_CSR_PMPADDR0=944ULL, RV_CSR_PMPADDR1=945ULL, RV_CSR_PMPADDR2=946ULL, RV_CSR_PMPADDR3=947ULL, + RV_CSR_PMPADDR4=948ULL, RV_CSR_PMPADDR5=949ULL, RV_CSR_PMPADDR6=950ULL, RV_CSR_PMPADDR7=951ULL, + RV_CSR_PMPADDR8=952ULL, RV_CSR_PMPADDR9=953ULL, RV_CSR_PMPADDR10=954ULL, RV_CSR_PMPADDR11=955ULL, + RV_CSR_PMPADDR12=956ULL, RV_CSR_PMPADDR13=957ULL, RV_CSR_PMPADDR14=958ULL, RV_CSR_PMPADDR15=959ULL, + RV_CSR_PMPADDR16=960ULL, RV_CSR_PMPADDR17=961ULL, RV_CSR_PMPADDR18=962ULL, RV_CSR_PMPADDR19=963ULL, + RV_CSR_PMPADDR20=964ULL, RV_CSR_PMPADDR21=965ULL, RV_CSR_PMPADDR22=966ULL, RV_CSR_PMPADDR23=967ULL, + RV_CSR_PMPADDR24=968ULL, RV_CSR_PMPADDR25=969ULL, RV_CSR_PMPADDR26=970ULL, RV_CSR_PMPADDR27=971ULL, + RV_CSR_PMPADDR28=972ULL, RV_CSR_PMPADDR29=973ULL, RV_CSR_PMPADDR30=974ULL, RV_CSR_PMPADDR31=975ULL, + RV_CSR_PMPADDR32=976ULL, RV_CSR_PMPADDR33=977ULL, RV_CSR_PMPADDR34=978ULL, RV_CSR_PMPADDR35=979ULL, + RV_CSR_PMPADDR36=980ULL, RV_CSR_PMPADDR37=981ULL, RV_CSR_PMPADDR38=982ULL, RV_CSR_PMPADDR39=983ULL, + RV_CSR_PMPADDR40=984ULL, RV_CSR_PMPADDR41=985ULL, RV_CSR_PMPADDR42=986ULL, RV_CSR_PMPADDR43=987ULL, + RV_CSR_PMPADDR44=988ULL, RV_CSR_PMPADDR45=989ULL, RV_CSR_PMPADDR46=990ULL, RV_CSR_PMPADDR47=991ULL, + RV_CSR_PMPADDR48=992ULL, RV_CSR_PMPADDR49=993ULL, RV_CSR_PMPADDR50=994ULL, RV_CSR_PMPADDR51=995ULL, + RV_CSR_PMPADDR52=996ULL, RV_CSR_PMPADDR53=997ULL, RV_CSR_PMPADDR54=998ULL, RV_CSR_PMPADDR55=999ULL, + RV_CSR_PMPADDR56=1000ULL, RV_CSR_PMPADDR57=1001ULL, RV_CSR_PMPADDR58=1002ULL, RV_CSR_PMPADDR59=1003ULL, + RV_CSR_PMPADDR60=1004ULL, RV_CSR_PMPADDR61=1005ULL, RV_CSR_PMPADDR62=1006ULL, RV_CSR_PMPADDR63=1007ULL, + RV_CSR_SCONTEXT=1448ULL, RV_CSR_HSTATUS=1536ULL, RV_CSR_HEDELEG=1538ULL, RV_CSR_HIDELEG=1539ULL, + RV_CSR_HIE=1540ULL, RV_CSR_HTIMEDELTA=1541ULL, RV_CSR_HCOUNTEREN=1542ULL, RV_CSR_HGEIE=1543ULL, + RV_CSR_HENVCFG=1546ULL, RV_CSR_HSTATEEN0=1548ULL, RV_CSR_HSTATEEN1=1549ULL, RV_CSR_HSTATEEN2=1550ULL, + RV_CSR_HSTATEEN3=1551ULL, RV_CSR_HTIMEDELTAH=1557ULL, RV_CSR_HENVCFGH=1562ULL, RV_CSR_HSTATEEN0H=1564ULL, + RV_CSR_HSTATEEN1H=1565ULL, RV_CSR_HSTATEEN2H=1566ULL, RV_CSR_HSTATEEN3H=1567ULL, RV_CSR_HTVAL=1603ULL, + RV_CSR_HIP=1604ULL, RV_CSR_HVIP=1605ULL, RV_CSR_HTINST=1610ULL, RV_CSR_HGATP=1664ULL, + RV_CSR_HCONTEXT=1704ULL, RV_CSR_MHPMEVENT3H=1827ULL, RV_CSR_MHPMEVENT4H=1828ULL, RV_CSR_MHPMEVENT5H=1829ULL, + RV_CSR_MHPMEVENT6H=1830ULL, RV_CSR_MHPMEVENT7H=1831ULL, RV_CSR_MHPMEVENT8H=1832ULL, RV_CSR_MHPMEVENT9H=1833ULL, + RV_CSR_MHPMEVENT10H=1834ULL, RV_CSR_MHPMEVENT11H=1835ULL, RV_CSR_MHPMEVENT12H=1836ULL, RV_CSR_MHPMEVENT13H=1837ULL, + RV_CSR_MHPMEVENT14H=1838ULL, RV_CSR_MHPMEVENT15H=1839ULL, RV_CSR_MHPMEVENT16H=1840ULL, RV_CSR_MHPMEVENT17H=1841ULL, + RV_CSR_MHPMEVENT18H=1842ULL, RV_CSR_MHPMEVENT19H=1843ULL, RV_CSR_MHPMEVENT20H=1844ULL, RV_CSR_MHPMEVENT21H=1845ULL, + RV_CSR_MHPMEVENT22H=1846ULL, RV_CSR_MHPMEVENT23H=1847ULL, RV_CSR_MHPMEVENT24H=1848ULL, RV_CSR_MHPMEVENT25H=1849ULL, + RV_CSR_MHPMEVENT26H=1850ULL, RV_CSR_MHPMEVENT27H=1851ULL, RV_CSR_MHPMEVENT28H=1852ULL, RV_CSR_MHPMEVENT29H=1853ULL, + RV_CSR_MHPMEVENT30H=1854ULL, RV_CSR_MHPMEVENT31H=1855ULL, RV_CSR_MSECCFG=1863ULL, RV_CSR_MSECCFGH=1879ULL, + RV_CSR_TSELECT=1952ULL, RV_CSR_TDATA1=1953ULL, RV_CSR_TDATA2=1954ULL, RV_CSR_TDATA3=1955ULL, + RV_CSR_TINFO=1956ULL, RV_CSR_TCONTROL=1957ULL, RV_CSR_MCONTEXT=1960ULL, RV_CSR_MSCONTEXT=1962ULL, + RV_CSR_DCSR=1968ULL, RV_CSR_DPC=1969ULL, RV_CSR_DSCRATCH0=1970ULL, RV_CSR_DSCRATCH1=1971ULL, + RV_CSR_MCYCLE=2816ULL, RV_CSR_MINSTRET=2818ULL, RV_CSR_MHPMCOUNTER3=2819ULL, RV_CSR_MHPMCOUNTER4=2820ULL, + RV_CSR_MHPMCOUNTER5=2821ULL, RV_CSR_MHPMCOUNTER6=2822ULL, RV_CSR_MHPMCOUNTER7=2823ULL, RV_CSR_MHPMCOUNTER8=2824ULL, + RV_CSR_MHPMCOUNTER9=2825ULL, RV_CSR_MHPMCOUNTER10=2826ULL, RV_CSR_MHPMCOUNTER11=2827ULL, RV_CSR_MHPMCOUNTER12=2828ULL, + RV_CSR_MHPMCOUNTER13=2829ULL, RV_CSR_MHPMCOUNTER14=2830ULL, RV_CSR_MHPMCOUNTER15=2831ULL, RV_CSR_MHPMCOUNTER16=2832ULL, + RV_CSR_MHPMCOUNTER17=2833ULL, RV_CSR_MHPMCOUNTER18=2834ULL, RV_CSR_MHPMCOUNTER19=2835ULL, RV_CSR_MHPMCOUNTER20=2836ULL, + RV_CSR_MHPMCOUNTER21=2837ULL, RV_CSR_MHPMCOUNTER22=2838ULL, RV_CSR_MHPMCOUNTER23=2839ULL, RV_CSR_MHPMCOUNTER24=2840ULL, + RV_CSR_MHPMCOUNTER25=2841ULL, RV_CSR_MHPMCOUNTER26=2842ULL, RV_CSR_MHPMCOUNTER27=2843ULL, RV_CSR_MHPMCOUNTER28=2844ULL, + RV_CSR_MHPMCOUNTER29=2845ULL, RV_CSR_MHPMCOUNTER30=2846ULL, RV_CSR_MHPMCOUNTER31=2847ULL, RV_CSR_MCYCLEH=2944ULL, + RV_CSR_MINSTRETH=2946ULL, RV_CSR_MHPMCOUNTER3H=2947ULL, RV_CSR_MHPMCOUNTER4H=2948ULL, RV_CSR_MHPMCOUNTER5H=2949ULL, + RV_CSR_MHPMCOUNTER6H=2950ULL, RV_CSR_MHPMCOUNTER7H=2951ULL, RV_CSR_MHPMCOUNTER8H=2952ULL, RV_CSR_MHPMCOUNTER9H=2953ULL, + RV_CSR_MHPMCOUNTER10H=2954ULL, RV_CSR_MHPMCOUNTER11H=2955ULL, RV_CSR_MHPMCOUNTER12H=2956ULL, RV_CSR_MHPMCOUNTER13H=2957ULL, + RV_CSR_MHPMCOUNTER14H=2958ULL, RV_CSR_MHPMCOUNTER15H=2959ULL, RV_CSR_MHPMCOUNTER16H=2960ULL, RV_CSR_MHPMCOUNTER17H=2961ULL, + RV_CSR_MHPMCOUNTER18H=2962ULL, RV_CSR_MHPMCOUNTER19H=2963ULL, RV_CSR_MHPMCOUNTER20H=2964ULL, RV_CSR_MHPMCOUNTER21H=2965ULL, + RV_CSR_MHPMCOUNTER22H=2966ULL, RV_CSR_MHPMCOUNTER23H=2967ULL, RV_CSR_MHPMCOUNTER24H=2968ULL, RV_CSR_MHPMCOUNTER25H=2969ULL, + RV_CSR_MHPMCOUNTER26H=2970ULL, RV_CSR_MHPMCOUNTER27H=2971ULL, RV_CSR_MHPMCOUNTER28H=2972ULL, RV_CSR_MHPMCOUNTER29H=2973ULL, + RV_CSR_MHPMCOUNTER30H=2974ULL, RV_CSR_MHPMCOUNTER31H=2975ULL, RV_CSR_CYCLE=3072ULL, RV_CSR_TIME=3073ULL, + RV_CSR_INSTRET=3074ULL, RV_CSR_HPMCOUNTER3=3075ULL, RV_CSR_HPMCOUNTER4=3076ULL, RV_CSR_HPMCOUNTER5=3077ULL, + RV_CSR_HPMCOUNTER6=3078ULL, RV_CSR_HPMCOUNTER7=3079ULL, RV_CSR_HPMCOUNTER8=3080ULL, RV_CSR_HPMCOUNTER9=3081ULL, + RV_CSR_HPMCOUNTER10=3082ULL, RV_CSR_HPMCOUNTER11=3083ULL, RV_CSR_HPMCOUNTER12=3084ULL, RV_CSR_HPMCOUNTER13=3085ULL, + RV_CSR_HPMCOUNTER14=3086ULL, RV_CSR_HPMCOUNTER15=3087ULL, RV_CSR_HPMCOUNTER16=3088ULL, RV_CSR_HPMCOUNTER17=3089ULL, + RV_CSR_HPMCOUNTER18=3090ULL, RV_CSR_HPMCOUNTER19=3091ULL, RV_CSR_HPMCOUNTER20=3092ULL, RV_CSR_HPMCOUNTER21=3093ULL, + RV_CSR_HPMCOUNTER22=3094ULL, RV_CSR_HPMCOUNTER23=3095ULL, RV_CSR_HPMCOUNTER24=3096ULL, RV_CSR_HPMCOUNTER25=3097ULL, + RV_CSR_HPMCOUNTER26=3098ULL, RV_CSR_HPMCOUNTER27=3099ULL, RV_CSR_HPMCOUNTER28=3100ULL, RV_CSR_HPMCOUNTER29=3101ULL, + RV_CSR_HPMCOUNTER30=3102ULL, RV_CSR_HPMCOUNTER31=3103ULL, RV_CSR_VL=3104ULL, RV_CSR_VTYPE=3105ULL, + RV_CSR_VLENB=3106ULL, RV_CSR_CYCLEH=3200ULL, RV_CSR_TIMEH=3201ULL, RV_CSR_INSTRETH=3202ULL, + RV_CSR_HPMCOUNTER3H=3203ULL, RV_CSR_HPMCOUNTER4H=3204ULL, RV_CSR_HPMCOUNTER5H=3205ULL, RV_CSR_HPMCOUNTER6H=3206ULL, + RV_CSR_HPMCOUNTER7H=3207ULL, RV_CSR_HPMCOUNTER8H=3208ULL, RV_CSR_HPMCOUNTER9H=3209ULL, RV_CSR_HPMCOUNTER10H=3210ULL, + RV_CSR_HPMCOUNTER11H=3211ULL, RV_CSR_HPMCOUNTER12H=3212ULL, RV_CSR_HPMCOUNTER13H=3213ULL, RV_CSR_HPMCOUNTER14H=3214ULL, + RV_CSR_HPMCOUNTER15H=3215ULL, RV_CSR_HPMCOUNTER16H=3216ULL, RV_CSR_HPMCOUNTER17H=3217ULL, RV_CSR_HPMCOUNTER18H=3218ULL, + RV_CSR_HPMCOUNTER19H=3219ULL, RV_CSR_HPMCOUNTER20H=3220ULL, RV_CSR_HPMCOUNTER21H=3221ULL, RV_CSR_HPMCOUNTER22H=3222ULL, + RV_CSR_HPMCOUNTER23H=3223ULL, RV_CSR_HPMCOUNTER24H=3224ULL, RV_CSR_HPMCOUNTER25H=3225ULL, RV_CSR_HPMCOUNTER26H=3226ULL, + RV_CSR_HPMCOUNTER27H=3227ULL, RV_CSR_HPMCOUNTER28H=3228ULL, RV_CSR_HPMCOUNTER29H=3229ULL, RV_CSR_HPMCOUNTER30H=3230ULL, + RV_CSR_HPMCOUNTER31H=3231ULL, RV_CSR_SCOUNTOVF=3488ULL, RV_CSR_HGEIP=3602ULL, RV_CSR_MVENDORID=3857ULL, + RV_CSR_MARCHID=3858ULL, RV_CSR_MIMPID=3859ULL, RV_CSR_MHARTID=3860ULL, RV_CSR_MCONFIGPTR=3861ULL, + RV_CAUSE_MISALIGNED_FETCH=0ULL, RV_CAUSE_FETCH_ACCESS=1ULL, RV_CAUSE_ILLEGAL_INSTRUCTION=2ULL, RV_CAUSE_BREAKPOINT=3ULL, + RV_CAUSE_MISALIGNED_LOAD=4ULL, RV_CAUSE_LOAD_ACCESS=5ULL, RV_CAUSE_MISALIGNED_STORE=6ULL, RV_CAUSE_STORE_ACCESS=7ULL, + RV_CAUSE_USER_ECALL=8ULL, RV_CAUSE_SUPERVISOR_ECALL=9ULL, RV_CAUSE_VIRTUAL_SUPERVISOR_ECALL=10ULL, RV_CAUSE_MACHINE_ECALL=11ULL, + RV_CAUSE_FETCH_PAGE_FAULT=12ULL, RV_CAUSE_LOAD_PAGE_FAULT=13ULL, RV_CAUSE_STORE_PAGE_FAULT=15ULL, RV_CAUSE_FETCH_GUEST_PAGE_FAULT=20ULL, + RV_CAUSE_LOAD_GUEST_PAGE_FAULT=21ULL, RV_CAUSE_VIRTUAL_INSTRUCTION=22ULL, RV_CAUSE_STORE_GUEST_PAGE_FAULT=23ULL, RV_MSTATUS_UIE=1ULL, + RV_MSTATUS_SIE=2ULL, RV_MSTATUS_HIE=4ULL, RV_MSTATUS_MIE=8ULL, RV_MSTATUS_UPIE=16ULL, + RV_MSTATUS_SPIE=32ULL, RV_MSTATUS_UBE=64ULL, RV_MSTATUS_MPIE=128ULL, RV_MSTATUS_SPP=256ULL, + RV_MSTATUS_VS=1536ULL, RV_MSTATUS_MPP=6144ULL, RV_MSTATUS_FS=24576ULL, RV_MSTATUS_XS=98304ULL, + RV_MSTATUS_MPRV=131072ULL, RV_MSTATUS_SUM=262144ULL, RV_MSTATUS_MXR=524288ULL, RV_MSTATUS_TVM=1048576ULL, + RV_MSTATUS_TW=2097152ULL, RV_MSTATUS_TSR=4194304ULL, RV_MSTATUS32_SD=2147483648ULL, RV_MSTATUS_UXL=12884901888ULL, + RV_MSTATUS_SXL=51539607552ULL, RV_MSTATUS_SBE=68719476736ULL, RV_MSTATUS_MBE=137438953472ULL, RV_MSTATUS_GVA=274877906944ULL, + RV_MSTATUS_MPV=549755813888ULL, RV_MSTATUS64_SD=9223372036854775808ULL, RV_PRV_U=0ULL, RV_PRV_S=1ULL, + RV_PRV_H=2ULL, RV_PRV_M=3ULL, RV_IRQ_U_SOFT=0ULL, RV_IRQ_S_SOFT=1ULL, + RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL, + RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL, + RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL, + RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL, + RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL, + RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL, + RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=32ULL, + FLEN=64ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, + fencei=1ULL, fencevma=2ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL, + FFLAG_MASK=31ULL, VLEN=256ULL, ELEN=32ULL, EEW_MAX=32ULL, + FP_SEW_MIN=32ULL, FP_SEW_MAX=64ULL, VSTART_ADDR=8ULL, VXSAT_ADDR=9ULL, + VXRM_ADDR=10ULL, VCSR_ADDR=15ULL, VL_ADDR=3104ULL, VTYPE_ADDR=3105ULL, + VLENB_ADDR=3106ULL, MISA_VAL=1073746221ULL, MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL + }; + + constexpr static unsigned FP_REGS_SIZE = 64; + constexpr static unsigned V_REGS_SIZE = 256; + + + enum reg_e { + X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31, FCSR, V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31, vstart, vxsat, vxrm, vl, vtype, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH + }; + + using reg_t = uint32_t; + + using addr_t = uint32_t; + + using code_word_t = uint32_t; //TODO: check removal + + using virt_addr_t = iss::virt_addr_t; + + using phys_addr_t = iss::phys_addr_t; + + static constexpr std::array reg_bit_widths{{ + sizeof(rv32gcv::RV32GCV_regs::X0) * 8, + sizeof(rv32gcv::RV32GCV_regs::X1) * 8, + sizeof(rv32gcv::RV32GCV_regs::X2) * 8, + sizeof(rv32gcv::RV32GCV_regs::X3) * 8, + sizeof(rv32gcv::RV32GCV_regs::X4) * 8, + sizeof(rv32gcv::RV32GCV_regs::X5) * 8, + sizeof(rv32gcv::RV32GCV_regs::X6) * 8, + sizeof(rv32gcv::RV32GCV_regs::X7) * 8, + sizeof(rv32gcv::RV32GCV_regs::X8) * 8, + sizeof(rv32gcv::RV32GCV_regs::X9) * 8, + sizeof(rv32gcv::RV32GCV_regs::X10) * 8, + sizeof(rv32gcv::RV32GCV_regs::X11) * 8, + sizeof(rv32gcv::RV32GCV_regs::X12) * 8, + sizeof(rv32gcv::RV32GCV_regs::X13) * 8, + sizeof(rv32gcv::RV32GCV_regs::X14) * 8, + sizeof(rv32gcv::RV32GCV_regs::X15) * 8, + sizeof(rv32gcv::RV32GCV_regs::X16) * 8, + sizeof(rv32gcv::RV32GCV_regs::X17) * 8, + sizeof(rv32gcv::RV32GCV_regs::X18) * 8, + sizeof(rv32gcv::RV32GCV_regs::X19) * 8, + sizeof(rv32gcv::RV32GCV_regs::X20) * 8, + sizeof(rv32gcv::RV32GCV_regs::X21) * 8, + sizeof(rv32gcv::RV32GCV_regs::X22) * 8, + sizeof(rv32gcv::RV32GCV_regs::X23) * 8, + sizeof(rv32gcv::RV32GCV_regs::X24) * 8, + sizeof(rv32gcv::RV32GCV_regs::X25) * 8, + sizeof(rv32gcv::RV32GCV_regs::X26) * 8, + sizeof(rv32gcv::RV32GCV_regs::X27) * 8, + sizeof(rv32gcv::RV32GCV_regs::X28) * 8, + sizeof(rv32gcv::RV32GCV_regs::X29) * 8, + sizeof(rv32gcv::RV32GCV_regs::X30) * 8, + sizeof(rv32gcv::RV32GCV_regs::X31) * 8, + sizeof(rv32gcv::RV32GCV_regs::PC) * 8, + sizeof(rv32gcv::RV32GCV_regs::NEXT_PC) * 8, + sizeof(rv32gcv::RV32GCV_regs::PRIV) * 8, + sizeof(rv32gcv::RV32GCV_regs::DPC) * 8, + sizeof(rv32gcv::RV32GCV_regs::F0) * 8, + sizeof(rv32gcv::RV32GCV_regs::F1) * 8, + sizeof(rv32gcv::RV32GCV_regs::F2) * 8, + sizeof(rv32gcv::RV32GCV_regs::F3) * 8, + sizeof(rv32gcv::RV32GCV_regs::F4) * 8, + sizeof(rv32gcv::RV32GCV_regs::F5) * 8, + sizeof(rv32gcv::RV32GCV_regs::F6) * 8, + sizeof(rv32gcv::RV32GCV_regs::F7) * 8, + sizeof(rv32gcv::RV32GCV_regs::F8) * 8, + sizeof(rv32gcv::RV32GCV_regs::F9) * 8, + sizeof(rv32gcv::RV32GCV_regs::F10) * 8, + sizeof(rv32gcv::RV32GCV_regs::F11) * 8, + sizeof(rv32gcv::RV32GCV_regs::F12) * 8, + sizeof(rv32gcv::RV32GCV_regs::F13) * 8, + sizeof(rv32gcv::RV32GCV_regs::F14) * 8, + sizeof(rv32gcv::RV32GCV_regs::F15) * 8, + sizeof(rv32gcv::RV32GCV_regs::F16) * 8, + sizeof(rv32gcv::RV32GCV_regs::F17) * 8, + sizeof(rv32gcv::RV32GCV_regs::F18) * 8, + sizeof(rv32gcv::RV32GCV_regs::F19) * 8, + sizeof(rv32gcv::RV32GCV_regs::F20) * 8, + sizeof(rv32gcv::RV32GCV_regs::F21) * 8, + sizeof(rv32gcv::RV32GCV_regs::F22) * 8, + sizeof(rv32gcv::RV32GCV_regs::F23) * 8, + sizeof(rv32gcv::RV32GCV_regs::F24) * 8, + sizeof(rv32gcv::RV32GCV_regs::F25) * 8, + sizeof(rv32gcv::RV32GCV_regs::F26) * 8, + sizeof(rv32gcv::RV32GCV_regs::F27) * 8, + sizeof(rv32gcv::RV32GCV_regs::F28) * 8, + sizeof(rv32gcv::RV32GCV_regs::F29) * 8, + sizeof(rv32gcv::RV32GCV_regs::F30) * 8, + sizeof(rv32gcv::RV32GCV_regs::F31) * 8, + sizeof(rv32gcv::RV32GCV_regs::FCSR) * 8, + sizeof(rv32gcv::RV32GCV_regs::V0) * 8, + sizeof(rv32gcv::RV32GCV_regs::V1) * 8, + sizeof(rv32gcv::RV32GCV_regs::V2) * 8, + sizeof(rv32gcv::RV32GCV_regs::V3) * 8, + sizeof(rv32gcv::RV32GCV_regs::V4) * 8, + sizeof(rv32gcv::RV32GCV_regs::V5) * 8, + sizeof(rv32gcv::RV32GCV_regs::V6) * 8, + sizeof(rv32gcv::RV32GCV_regs::V7) * 8, + sizeof(rv32gcv::RV32GCV_regs::V8) * 8, + sizeof(rv32gcv::RV32GCV_regs::V9) * 8, + sizeof(rv32gcv::RV32GCV_regs::V10) * 8, + sizeof(rv32gcv::RV32GCV_regs::V11) * 8, + sizeof(rv32gcv::RV32GCV_regs::V12) * 8, + sizeof(rv32gcv::RV32GCV_regs::V13) * 8, + sizeof(rv32gcv::RV32GCV_regs::V14) * 8, + sizeof(rv32gcv::RV32GCV_regs::V15) * 8, + sizeof(rv32gcv::RV32GCV_regs::V16) * 8, + sizeof(rv32gcv::RV32GCV_regs::V17) * 8, + sizeof(rv32gcv::RV32GCV_regs::V18) * 8, + sizeof(rv32gcv::RV32GCV_regs::V19) * 8, + sizeof(rv32gcv::RV32GCV_regs::V20) * 8, + sizeof(rv32gcv::RV32GCV_regs::V21) * 8, + sizeof(rv32gcv::RV32GCV_regs::V22) * 8, + sizeof(rv32gcv::RV32GCV_regs::V23) * 8, + sizeof(rv32gcv::RV32GCV_regs::V24) * 8, + sizeof(rv32gcv::RV32GCV_regs::V25) * 8, + sizeof(rv32gcv::RV32GCV_regs::V26) * 8, + sizeof(rv32gcv::RV32GCV_regs::V27) * 8, + sizeof(rv32gcv::RV32GCV_regs::V28) * 8, + sizeof(rv32gcv::RV32GCV_regs::V29) * 8, + sizeof(rv32gcv::RV32GCV_regs::V30) * 8, + sizeof(rv32gcv::RV32GCV_regs::V31) * 8, + sizeof(rv32gcv::RV32GCV_regs::vstart) * 8, + sizeof(rv32gcv::RV32GCV_regs::vxsat) * 8, + sizeof(rv32gcv::RV32GCV_regs::vxrm) * 8, + sizeof(rv32gcv::RV32GCV_regs::vl) * 8, + sizeof(rv32gcv::RV32GCV_regs::vtype) * 8, + sizeof(rv32gcv::RV32GCV_regs::trap_state) * 8, + sizeof(rv32gcv::RV32GCV_regs::pending_trap) * 8, + sizeof(rv32gcv::RV32GCV_regs::icount) * 8, + sizeof(rv32gcv::RV32GCV_regs::cycle) * 8, + sizeof(rv32gcv::RV32GCV_regs::instret) * 8, + sizeof(rv32gcv::RV32GCV_regs::instruction) * 8, + sizeof(rv32gcv::RV32GCV_regs::last_branch) * 8, + }}; + + static constexpr std::array reg_byte_offsets{{ + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X0), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X1), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X2), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X3), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X4), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X5), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X6), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X7), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X8), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X9), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X10), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X11), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X12), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X13), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X14), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X15), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X16), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X17), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X18), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X19), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X20), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X21), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X22), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X23), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X24), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X25), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X26), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X27), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X28), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X29), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X30), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::X31), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::PC), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::NEXT_PC), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::PRIV), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::DPC), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F0), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F1), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F2), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F3), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F4), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F5), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F6), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F7), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F8), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F9), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F10), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F11), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F12), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F13), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F14), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F15), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F16), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F17), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F18), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F19), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F20), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F21), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F22), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F23), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F24), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F25), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F26), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F27), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F28), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F29), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F30), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::F31), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::FCSR), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V0), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V1), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V2), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V3), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V4), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V5), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V6), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V7), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V8), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V9), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V10), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V11), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V12), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V13), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V14), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V15), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V16), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V17), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V18), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V19), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V20), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V21), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V22), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V23), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V24), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V25), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V26), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V27), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V28), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V29), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V30), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::V31), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::vstart), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::vxsat), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::vxrm), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::vl), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::vtype), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::trap_state), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::pending_trap), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::icount), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::cycle), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::instret), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::instruction), + offsetof(rv32gcv::RV32GCV_regs, rv32gcv::RV32GCV_regs::last_branch), + }}; + + static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); + + enum sreg_flag_e { FLAGS }; + + enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM }; + + enum class opcode_e { + LUI = 0, + AUIPC = 1, + JAL = 2, + JALR = 3, + BEQ = 4, + BNE = 5, + BLT = 6, + BGE = 7, + BLTU = 8, + BGEU = 9, + LB = 10, + LH = 11, + LW = 12, + LBU = 13, + LHU = 14, + SB = 15, + SH = 16, + SW = 17, + ADDI = 18, + SLTI = 19, + SLTIU = 20, + XORI = 21, + ORI = 22, + ANDI = 23, + SLLI = 24, + SRLI = 25, + SRAI = 26, + ADD = 27, + SUB = 28, + SLL = 29, + SLT = 30, + SLTU = 31, + XOR = 32, + SRL = 33, + SRA = 34, + OR = 35, + AND = 36, + FENCE = 37, + ECALL = 38, + EBREAK = 39, + MRET = 40, + WFI = 41, + CSRRW = 42, + CSRRS = 43, + CSRRC = 44, + CSRRWI = 45, + CSRRSI = 46, + CSRRCI = 47, + FENCE_I = 48, + MUL = 49, + MULH = 50, + MULHSU = 51, + MULHU = 52, + DIV = 53, + DIVU = 54, + REM = 55, + REMU = 56, + LRW = 57, + SCW = 58, + AMOSWAPW = 59, + AMOADDW = 60, + AMOXORW = 61, + AMOANDW = 62, + AMOORW = 63, + AMOMINW = 64, + AMOMAXW = 65, + AMOMINUW = 66, + AMOMAXUW = 67, + C__ADDI4SPN = 68, + C__LW = 69, + C__SW = 70, + C__ADDI = 71, + C__NOP = 72, + C__JAL = 73, + C__LI = 74, + C__LUI = 75, + C__ADDI16SP = 76, + __reserved_clui = 77, + C__SRLI = 78, + C__SRAI = 79, + C__ANDI = 80, + C__SUB = 81, + C__XOR = 82, + C__OR = 83, + C__AND = 84, + C__J = 85, + C__BEQZ = 86, + C__BNEZ = 87, + C__SLLI = 88, + C__LWSP = 89, + C__MV = 90, + C__JR = 91, + __reserved_cmv = 92, + C__ADD = 93, + C__JALR = 94, + C__EBREAK = 95, + C__SWSP = 96, + DII = 97, + FLW = 98, + FSW = 99, + FADD__S = 100, + FSUB__S = 101, + FMUL__S = 102, + FDIV__S = 103, + FMIN__S = 104, + FMAX__S = 105, + FSQRT__S = 106, + FMADD__S = 107, + FMSUB__S = 108, + FNMADD__S = 109, + FNMSUB__S = 110, + FCVT__W__S = 111, + FCVT__WU__S = 112, + FCVT__S__W = 113, + FCVT__S__WU = 114, + FSGNJ__S = 115, + FSGNJN__S = 116, + FSGNJX__S = 117, + FMV__X__W = 118, + FMV__W__X = 119, + FEQ__S = 120, + FLT__S = 121, + FLE__S = 122, + FCLASS__S = 123, + C__FLW = 124, + C__FSW = 125, + C__FLWSP = 126, + C__FSWSP = 127, + FLD = 128, + FSD = 129, + FADD__D = 130, + FSUB__D = 131, + FMUL__D = 132, + FDIV__D = 133, + FMIN__D = 134, + FMAX__D = 135, + FSQRT__D = 136, + FMADD__D = 137, + FMSUB__D = 138, + FNMADD__D = 139, + FNMSUB__D = 140, + FCVT__W__D = 141, + FCVT__WU__D = 142, + FCVT__D__W = 143, + FCVT__D__WU = 144, + FCVT__S__D = 145, + FCVT__D__S = 146, + FSGNJ__D = 147, + FSGNJN__D = 148, + FSGNJX__D = 149, + FEQ__D = 150, + FLT__D = 151, + FLE__D = 152, + FCLASS__D = 153, + C__FLD = 154, + C__FSD = 155, + C__FLDSP = 156, + C__FSDSP = 157, + SFENCE__VMA = 158, + SRET = 159, + VSETVLI = 160, + VSETIVLI = 161, + VSETVL = 162, + VLE8__V = 163, + VLE16__V = 164, + VLE32__V = 165, + VLE64__V = 166, + VLSEG2E8__V = 167, + VLSEG2E16__V = 168, + VLSEG2E32__V = 169, + VLSEG2E64__V = 170, + VLSEG3E8__V = 171, + VLSEG3E16__V = 172, + VLSEG3E32__V = 173, + VLSEG3E64__V = 174, + VLSEG4E8__V = 175, + VLSEG4E16__V = 176, + VLSEG4E32__V = 177, + VLSEG4E64__V = 178, + VLSEG5E8__V = 179, + VLSEG5E16__V = 180, + VLSEG5E32__V = 181, + VLSEG5E64__V = 182, + VLSEG6E8__V = 183, + VLSEG6E16__V = 184, + VLSEG6E32__V = 185, + VLSEG6E64__V = 186, + VLSEG7E8__V = 187, + VLSEG7E16__V = 188, + VLSEG7E32__V = 189, + VLSEG7E64__V = 190, + VLSEG8E8__V = 191, + VLSEG8E16__V = 192, + VLSEG8E32__V = 193, + VLSEG8E64__V = 194, + VSE8__V = 195, + VSE16__V = 196, + VSE32__V = 197, + VSE64__V = 198, + VSSEG2E8__V = 199, + VSSEG2E16__V = 200, + VSSEG2E32__V = 201, + VSSEG2E64__V = 202, + VSSEG3E8__V = 203, + VSSEG3E16__V = 204, + VSSEG3E32__V = 205, + VSSEG3E64__V = 206, + VSSEG4E8__V = 207, + VSSEG4E16__V = 208, + VSSEG4E32__V = 209, + VSSEG4E64__V = 210, + VSSEG5E8__V = 211, + VSSEG5E16__V = 212, + VSSEG5E32__V = 213, + VSSEG5E64__V = 214, + VSSEG6E8__V = 215, + VSSEG6E16__V = 216, + VSSEG6E32__V = 217, + VSSEG6E64__V = 218, + VSSEG7E8__V = 219, + VSSEG7E16__V = 220, + VSSEG7E32__V = 221, + VSSEG7E64__V = 222, + VSSEG8E8__V = 223, + VSSEG8E16__V = 224, + VSSEG8E32__V = 225, + VSSEG8E64__V = 226, + VLSE8__V = 227, + VLSE16__V = 228, + VLSE32__V = 229, + VLSE64__V = 230, + VLSSEG2E8__V = 231, + VLSSEG2E16__V = 232, + VLSSEG2E32__V = 233, + VLSSEG2E64__V = 234, + VLSSEG3E8__V = 235, + VLSSEG3E16__V = 236, + VLSSEG3E32__V = 237, + VLSSEG3E64__V = 238, + VLSSEG4E8__V = 239, + VLSSEG4E16__V = 240, + VLSSEG4E32__V = 241, + VLSSEG4E64__V = 242, + VLSSEG5E8__V = 243, + VLSSEG5E16__V = 244, + VLSSEG5E32__V = 245, + VLSSEG5E64__V = 246, + VLSSEG6E8__V = 247, + VLSSEG6E16__V = 248, + VLSSEG6E32__V = 249, + VLSSEG6E64__V = 250, + VLSSEG7E8__V = 251, + VLSSEG7E16__V = 252, + VLSSEG7E32__V = 253, + VLSSEG7E64__V = 254, + VLSSEG8E8__V = 255, + VLSSEG8E16__V = 256, + VLSSEG8E32__V = 257, + VLSSEG8E64__V = 258, + VSSE8__V = 259, + VSSE16__V = 260, + VSSE32__V = 261, + VSSE64__V = 262, + VSSSEG2E8__V = 263, + VSSSEG2E16__V = 264, + VSSSEG2E32__V = 265, + VSSSEG2E64__V = 266, + VSSSEG3E8__V = 267, + VSSSEG3E16__V = 268, + VSSSEG3E32__V = 269, + VSSSEG3E64__V = 270, + VSSSEG4E8__V = 271, + VSSSEG4E16__V = 272, + VSSSEG4E32__V = 273, + VSSSEG4E64__V = 274, + VSSSEG5E8__V = 275, + VSSSEG5E16__V = 276, + VSSSEG5E32__V = 277, + VSSSEG5E64__V = 278, + VSSSEG6E8__V = 279, + VSSSEG6E16__V = 280, + VSSSEG6E32__V = 281, + VSSSEG6E64__V = 282, + VSSSEG7E8__V = 283, + VSSSEG7E16__V = 284, + VSSSEG7E32__V = 285, + VSSSEG7E64__V = 286, + VSSSEG8E8__V = 287, + VSSSEG8E16__V = 288, + VSSSEG8E32__V = 289, + VSSSEG8E64__V = 290, + VLE8FF__V = 291, + VLE16FF__V = 292, + VLE32FF__V = 293, + VLE64FF__V = 294, + VLSEG2E8FF__V = 295, + VLSEG2E16FF__V = 296, + VLSEG2E32FF__V = 297, + VLSEG2E64FF__V = 298, + VLSEG3E8FF__V = 299, + VLSEG3E16FF__V = 300, + VLSEG3E32FF__V = 301, + VLSEG3E64FF__V = 302, + VLSEG4E8FF__V = 303, + VLSEG4E16FF__V = 304, + VLSEG4E32FF__V = 305, + VLSEG4E64FF__V = 306, + VLSEG5E8FF__V = 307, + VLSEG5E16FF__V = 308, + VLSEG5E32FF__V = 309, + VLSEG5E64FF__V = 310, + VLSEG6E8FF__V = 311, + VLSEG6E16FF__V = 312, + VLSEG6E32FF__V = 313, + VLSEG6E64FF__V = 314, + VLSEG7E8FF__V = 315, + VLSEG7E16FF__V = 316, + VLSEG7E32FF__V = 317, + VLSEG7E64FF__V = 318, + VLSEG8E8FF__V = 319, + VLSEG8E16FF__V = 320, + VLSEG8E32FF__V = 321, + VLSEG8E64FF__V = 322, + VSM__V = 323, + VLM__V = 324, + VL1RE8__V = 325, + VL1RE16__V = 326, + VL1RE32__V = 327, + VL1RE64__V = 328, + VL2RE8__V = 329, + VL2RE16__V = 330, + VL2RE32__V = 331, + VL2RE64__V = 332, + VL4RE8__V = 333, + VL4RE16__V = 334, + VL4RE32__V = 335, + VL4RE64__V = 336, + VL8RE8__V = 337, + VL8RE16__V = 338, + VL8RE32__V = 339, + VL8RE64__V = 340, + VS1RE64__V = 341, + VS2RE64__V = 342, + VS4RE64__V = 343, + VS8RE64__V = 344, + VLOXEI8__V = 345, + VLOXEI16__V = 346, + VLOXEI32__V = 347, + VLOXEI64__V = 348, + VLOXSEG2EI8__V = 349, + VLOXSEG2EI16__V = 350, + VLOXSEG2EI32__V = 351, + VLOXSEG2EI64__V = 352, + VLOXSEG3EI8__V = 353, + VLOXSEG3EI16__V = 354, + VLOXSEG3EI32__V = 355, + VLOXSEG3EI64__V = 356, + VLOXSEG4EI8__V = 357, + VLOXSEG4EI16__V = 358, + VLOXSEG4EI32__V = 359, + VLOXSEG4EI64__V = 360, + VLOXSEG5EI8__V = 361, + VLOXSEG5EI16__V = 362, + VLOXSEG5EI32__V = 363, + VLOXSEG5EI64__V = 364, + VLOXSEG6EI8__V = 365, + VLOXSEG6EI16__V = 366, + VLOXSEG6EI32__V = 367, + VLOXSEG6EI64__V = 368, + VLOXSEG7EI8__V = 369, + VLOXSEG7EI16__V = 370, + VLOXSEG7EI32__V = 371, + VLOXSEG7EI64__V = 372, + VLOXSEG8EI8__V = 373, + VLOXSEG8EI16__V = 374, + VLOXSEG8EI32__V = 375, + VLOXSEG8EI64__V = 376, + VSOXEI8__V = 377, + VSOXEI16__V = 378, + VSOXEI32__V = 379, + VSOXEI64__V = 380, + VSOXSEG2EI8__V = 381, + VSOXSEG2EI16__V = 382, + VSOXSEG2EI32__V = 383, + VSOXSEG2EI64__V = 384, + VSOXSEG3EI8__V = 385, + VSOXSEG3EI16__V = 386, + VSOXSEG3EI32__V = 387, + VSOXSEG3EI64__V = 388, + VSOXSEG4EI8__V = 389, + VSOXSEG4EI16__V = 390, + VSOXSEG4EI32__V = 391, + VSOXSEG4EI64__V = 392, + VSOXSEG5EI8__V = 393, + VSOXSEG5EI16__V = 394, + VSOXSEG5EI32__V = 395, + VSOXSEG5EI64__V = 396, + VSOXSEG6EI8__V = 397, + VSOXSEG6EI16__V = 398, + VSOXSEG6EI32__V = 399, + VSOXSEG6EI64__V = 400, + VSOXSEG7EI8__V = 401, + VSOXSEG7EI16__V = 402, + VSOXSEG7EI32__V = 403, + VSOXSEG7EI64__V = 404, + VSOXSEG8EI8__V = 405, + VSOXSEG8EI16__V = 406, + VSOXSEG8EI32__V = 407, + VSOXSEG8EI64__V = 408, + VLUXEI8__V = 409, + VLUXEI16__V = 410, + VLUXEI32__V = 411, + VLUXEI64__V = 412, + VLUXSEG2EI8__V = 413, + VLUXSEG2EI16__V = 414, + VLUXSEG2EI32__V = 415, + VLUXSEG2EI64__V = 416, + VLUXSEG3EI8__V = 417, + VLUXSEG3EI16__V = 418, + VLUXSEG3EI32__V = 419, + VLUXSEG3EI64__V = 420, + VLUXSEG4EI8__V = 421, + VLUXSEG4EI16__V = 422, + VLUXSEG4EI32__V = 423, + VLUXSEG4EI64__V = 424, + VLUXSEG5EI8__V = 425, + VLUXSEG5EI16__V = 426, + VLUXSEG5EI32__V = 427, + VLUXSEG5EI64__V = 428, + VLUXSEG6EI8__V = 429, + VLUXSEG6EI16__V = 430, + VLUXSEG6EI32__V = 431, + VLUXSEG6EI64__V = 432, + VLUXSEG7EI8__V = 433, + VLUXSEG7EI16__V = 434, + VLUXSEG7EI32__V = 435, + VLUXSEG7EI64__V = 436, + VLUXSEG8EI8__V = 437, + VLUXSEG8EI16__V = 438, + VLUXSEG8EI32__V = 439, + VLUXSEG8EI64__V = 440, + VSUXEI8__V = 441, + VSUXEI16__V = 442, + VSUXEI32__V = 443, + VSUXEI64__V = 444, + VSUXSEG2EI8__V = 445, + VSUXSEG2EI16__V = 446, + VSUXSEG2EI32__V = 447, + VSUXSEG2EI64__V = 448, + VSUXSEG3EI8__V = 449, + VSUXSEG3EI16__V = 450, + VSUXSEG3EI32__V = 451, + VSUXSEG3EI64__V = 452, + VSUXSEG4EI8__V = 453, + VSUXSEG4EI16__V = 454, + VSUXSEG4EI32__V = 455, + VSUXSEG4EI64__V = 456, + VSUXSEG5EI8__V = 457, + VSUXSEG5EI16__V = 458, + VSUXSEG5EI32__V = 459, + VSUXSEG5EI64__V = 460, + VSUXSEG6EI8__V = 461, + VSUXSEG6EI16__V = 462, + VSUXSEG6EI32__V = 463, + VSUXSEG6EI64__V = 464, + VSUXSEG7EI8__V = 465, + VSUXSEG7EI16__V = 466, + VSUXSEG7EI32__V = 467, + VSUXSEG7EI64__V = 468, + VSUXSEG8EI8__V = 469, + VSUXSEG8EI16__V = 470, + VSUXSEG8EI32__V = 471, + VSUXSEG8EI64__V = 472, + VADD__VI = 473, + VADD__VV = 474, + VADD__VX = 475, + VSUB__VV = 476, + VSUB__VX = 477, + VRSUB__VI = 478, + VRSUB__VX = 479, + VWADDU__VV = 480, + VWADDU__VX = 481, + VWSUBU__VV = 482, + VWSUBU__VX = 483, + VWADD__VV = 484, + VWADD__VX = 485, + VWSUB__VV = 486, + VWSUB__VX = 487, + VWADDU__WV = 488, + VWADDU__WX = 489, + VWSUBU__WV = 490, + VWSUBU__WX = 491, + VWADD__WV = 492, + VWADD__WX = 493, + VWSUB__WV = 494, + VWSUB__WX = 495, + VZEXT__VF2 = 496, + VSEXT__VF2 = 497, + VZEXT__VF4 = 498, + VSEXT__VF4 = 499, + VZEXT__VF8 = 500, + VSEXT__VF8 = 501, + VADC__VVM = 502, + VADC__VXM = 503, + VADC__VIM = 504, + VMADC__VVM = 505, + VMADC__VXM = 506, + VMADC__VIM = 507, + VMADC__VV = 508, + VMADC__VX = 509, + VMADC__VI = 510, + VSBC__VVM = 511, + VSBC__VXM = 512, + VMSBC__VVM = 513, + VMSBC__VXM = 514, + VMSBC__VV = 515, + VMSBC__VX = 516, + VAND__VI = 517, + VAND__VV = 518, + VAND__VX = 519, + VOR__VI = 520, + VOR__VV = 521, + VOR__VX = 522, + VXOR__VI = 523, + VXOR__VV = 524, + VXOR__VX = 525, + VSLL__VI = 526, + VSLL__VV = 527, + VSLL__VX = 528, + VSRL__VI = 529, + VSRL__VV = 530, + VSRL__VX = 531, + VSRA__VI = 532, + VSRA__VV = 533, + VSRA__VX = 534, + VNSRL__WI = 535, + VNSRL__WV = 536, + VNSRL__WX = 537, + VNSRA__WI = 538, + VNSRA__WV = 539, + VNSRA__WX = 540, + VMSEQ__VI = 541, + VMSEQ__VV = 542, + VMSEQ__VX = 543, + VMSNE__VI = 544, + VMSNE__VV = 545, + VMSNE__VX = 546, + VMSLTU__VV = 547, + VMSLTU__VX = 548, + VMSLT__VV = 549, + VMSLT__VX = 550, + VMSLEU__VI = 551, + VMSLEU__VV = 552, + VMSLEU__VX = 553, + VMSLE__VI = 554, + VMSLE__VV = 555, + VMSLE__VX = 556, + VMSGTU__VI = 557, + VMSGTU__VX = 558, + VMSGT__VI = 559, + VMSGT__VX = 560, + VMINU__VV = 561, + VMINU__VX = 562, + VMIN__VV = 563, + VMIN__VX = 564, + VMAXU__VV = 565, + VMAXU__VX = 566, + VMAX__VV = 567, + VMAX__VX = 568, + VMUL__VV = 569, + VMUL__VX = 570, + VMULH__VV = 571, + VMULH__VX = 572, + VMULHU__VV = 573, + VMULHU__VX = 574, + VMULHSU__VV = 575, + VMULHSU__VX = 576, + VDIVU__VV = 577, + VDIVU__VX = 578, + VDIV__VV = 579, + VDIV__VX = 580, + VREMU__VV = 581, + VREMU__VX = 582, + VREM__VV = 583, + VREM__VX = 584, + VWMUL__VV = 585, + VWMUL__VX = 586, + VWMULU__VV = 587, + VWMULU__VX = 588, + VWMULSU__VV = 589, + VWMULSU__VX = 590, + VMACC__VV = 591, + VMACC__VX = 592, + VNMSAC__VV = 593, + VNMSAC__VX = 594, + VMADD__VV = 595, + VMADD__VX = 596, + VNMSUB__VV = 597, + VNMSUB__VX = 598, + VWMACCU__VV = 599, + VWMACCU__VX = 600, + VWMACC__VV = 601, + VWMACC__VX = 602, + VWMACCSU__VV = 603, + VWMACCSU__VX = 604, + VWMACCUS__VX = 605, + VMERGE__VIM = 606, + VMERGE__VVM = 607, + VMERGE__VXM = 608, + VMV__V__I = 609, + VMV__V__V = 610, + VMV__V__X = 611, + VSADDU__VI = 612, + VSADDU__VV = 613, + VSADDU__VX = 614, + VSADD__VI = 615, + VSADD__VV = 616, + VSADD__VX = 617, + VSSUBU__VV = 618, + VSSUBU__VX = 619, + VSSUB__VV = 620, + VSSUB__VX = 621, + VAADDU__VV = 622, + VAADDU__VX = 623, + VAADD__VV = 624, + VAADD__VX = 625, + VASUBU__VV = 626, + VASUBU__VX = 627, + VASUB__VV = 628, + VASUB__VX = 629, + VSMUL__VV = 630, + VSMUL__VX = 631, + VSSRL__VI = 632, + VSSRL__VV = 633, + VSSRL__VX = 634, + VSSRA__VI = 635, + VSSRA__VV = 636, + VSSRA__VX = 637, + VNCLIPU__WI = 638, + VNCLIPU__WV = 639, + VNCLIPU__WX = 640, + VNCLIP__WI = 641, + VNCLIP__WV = 642, + VNCLIP__WX = 643, + VREDSUM__VS = 644, + VREDMAXU__VS = 645, + VREDMAX__VS = 646, + VREDMINU__VS = 647, + VREDMIN__VS = 648, + VREDAND__VS = 649, + VREDOR__VS = 650, + VREDXOR__VS = 651, + VWREDSUMU__VS = 652, + VWREDSUM__VS = 653, + VFREDOSUM__VS = 654, + VFREDUSUM__VS = 655, + VFREDMAX__VS = 656, + VFREDMIN__VS = 657, + VFWREDOSUM__VS = 658, + VFWREDUSUM__VS = 659, + VMAND__MM = 660, + VMNAND__MM = 661, + VMANDN__MM = 662, + VMXOR__MM = 663, + VMOR__MM = 664, + VMNOR__MM = 665, + VMORN__MM = 666, + VMXNOR__MM = 667, + VCPOP__M = 668, + VFIRST__M = 669, + VMSBF__M = 670, + VMSIF__M = 671, + VMSOF__M = 672, + VIOTA__M = 673, + VID__V = 674, + VMV__S__X = 675, + VMV__X__S = 676, + VSLIDEUP__VI = 677, + VSLIDEUP__VX = 678, + VSLIDEDOWN__VI = 679, + VSLIDEDOWN__VX = 680, + VSLIDE1UP__VX = 681, + VSLIDE1DOWN__VX = 682, + VRGATHER__VI = 683, + VRGATHER__VV = 684, + VRGATHER__VX = 685, + VRGATHEREI16__VV = 686, + VCOMPRESS__VM = 687, + VMV1R__V = 688, + VMV2R__V = 689, + VMV4R__V = 690, + VMV8R__V = 691, + VFMV__S__F = 692, + VFMV__F__S = 693, + VFSLIDE1UP__VF = 694, + VFSLIDE1DOWN__VF = 695, + VFADD__VF = 696, + VFADD__VV = 697, + VFSUB__VF = 698, + VFSUB__VV = 699, + VFRSUB__VF = 700, + VFWADD__VF = 701, + VFWADD__VV = 702, + VFWSUB__VF = 703, + VFWSUB__VV = 704, + VFWADD__WF = 705, + VFWADD__WV = 706, + VFWSUB__WF = 707, + VFWSUB__WV = 708, + VFMUL__VF = 709, + VFMUL__VV = 710, + VFDIV__VF = 711, + VFDIV__VV = 712, + VFRDIV__VF = 713, + VFWMUL__VF = 714, + VFWMUL__VV = 715, + VFMACC__VF = 716, + VFMACC__VV = 717, + VFNMACC__VF = 718, + VFNMACC__VV = 719, + VFMSAC__VF = 720, + VFMSAC__VV = 721, + VFNMSAC__VF = 722, + VFNMSAC__VV = 723, + VFMADD__VF = 724, + VFMADD__VV = 725, + VFNMADD__VF = 726, + VFNMADD__VV = 727, + VFMSUB__VF = 728, + VFMSUB__VV = 729, + VFNMSUB__VF = 730, + VFNMSUB__VV = 731, + VFWMACC__VF = 732, + VFWMACC__VV = 733, + VFWNMACC__VF = 734, + VFWNMACC__VV = 735, + VFWMSAC__VF = 736, + VFWMSAC__VV = 737, + VFWNMSAC__VF = 738, + VFWNMSAC__VV = 739, + VFSQRT__V = 740, + VFRSQRT7__V = 741, + VFREC7__V = 742, + VFMIN__VF = 743, + VFMIN__VV = 744, + VFMAX__VF = 745, + VFMAX__VV = 746, + VFSGNJ__VF = 747, + VFSGNJ__VV = 748, + VFSGNJN__VF = 749, + VFSGNJN__VV = 750, + VFSGNJX__VF = 751, + VFSGNJX__VV = 752, + VMFEQ__VF = 753, + VMFEQ__VV = 754, + VMFNE__VF = 755, + VMFNE__VV = 756, + VMFLT__VF = 757, + VMFLT__VV = 758, + VMFLE__VF = 759, + VMFLE__VV = 760, + VMFGT__VF = 761, + VMFGE__VF = 762, + VFCLASS__V = 763, + VFMERGE__VFM = 764, + VFMV__V__F = 765, + VFCVT__XU__F__V = 766, + VFCVT__X__F__V = 767, + VFCVT__RTZ__XU__F__V = 768, + VFCVT__RTZ__X__F__V = 769, + VFCVT__F__XU__V = 770, + VFCVT__F__X__V = 771, + VFWCVT__XU__F__V = 772, + VFWCVT__X__F__V = 773, + VFWCVT__RTZ__XU__F__V = 774, + VFWCVT__RTZ__X__F__V = 775, + VFWCVT__F__XU__V = 776, + VFWCVT__F__X__V = 777, + VFWCVT__F__F__V = 778, + VFNCVT__X__F__W = 779, + VFNCVT__XU__F__W = 780, + VFNCVT__RTZ__XU__F__W = 781, + VFNCVT__RTZ__X__F__W = 782, + VFNCVT__F__XU__W = 783, + VFNCVT__F__X__W = 784, + VFNCVT__F__F__W = 785, + VFNCVT__ROD__F__F__W = 786, + MAX_OPCODE + }; +}; +} +} +#endif /* _RV32GCV_H_ */ +// clang-format on diff --git a/src/sysc/register_rv32gcv.cpp b/src/sysc/register_rv32gcv.cpp new file mode 100644 index 0000000..2047e08 --- /dev/null +++ b/src/sysc/register_rv32gcv.cpp @@ -0,0 +1,99 @@ +/******************************************************************************* + * Copyright (C) 2024 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ +// clang-format off +#include +#include +#include +#include +#include +#include +#include +#include + +namespace iss { +namespace interp { +using namespace sysc; + +volatile std::array rv32gcv_init = { + iss_factory::instance().register_creator("rv32gcv_msu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv32gcv_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv32gcv_mu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }) +}; +} +#if defined(WITH_LLVM) +namespace llvm { +using namespace sysc; +volatile std::array rv32gcv_init = { + iss_factory::instance().register_creator("rv32gcv_m:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv32gcv_mu:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }) +}; +} +#endif +#if defined(WITH_TCC) +namespace tcc { +using namespace sysc; +volatile std::array rv32gcv_init = { + iss_factory::instance().register_creator("rv32gcv_m:tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv32gcv_mu:tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }) +}; +} +#endif +} +// clang-format on diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp new file mode 100644 index 0000000..69a8fbb --- /dev/null +++ b/src/vm/interp/vm_rv32gcv.cpp @@ -0,0 +1,30566 @@ +/******************************************************************************* + * Copyright (C) 2024 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +// clang-format off +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + + +#ifndef FMT_HEADER_ONLY +#define FMT_HEADER_ONLY +#endif +#include + +#include +#include + +namespace iss { +namespace interp { +namespace rv32gcv { +using namespace iss::arch; +using namespace iss::debugger; +using namespace std::placeholders; + +struct memory_access_exception : public std::exception{ + memory_access_exception(){} +}; + +template class vm_impl : public iss::interp::vm_base { +public: + using traits = arch::traits; + using super = typename iss::interp::vm_base; + using virt_addr_t = typename super::virt_addr_t; + using phys_addr_t = typename super::phys_addr_t; + using code_word_t = typename super::code_word_t; + using addr_t = typename super::addr_t; + using reg_t = typename traits::reg_t; + using mem_type_e = typename traits::mem_type_e; + using opcode_e = typename traits::opcode_e; + + vm_impl(); + + vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); + + void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } + + target_adapter_if *accquire_target_adapter(server_if *srv) override { + debugger_if::dbg_enabled = true; + if (super::tgt_adapter == nullptr) + super::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); + return super::tgt_adapter; + } + +protected: + using this_class = vm_impl; + using compile_ret_t = virt_addr_t; + using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr); + + inline const char *name(size_t index){return traits::reg_aliases.at(index);} + + inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";} + + inline const char* vname(size_t index) { return index < 32 ? name(index + traits::V0) : "illegal"; } + inline const char* sew_name(size_t bits) { + switch(bits) { + case 0b000: + return "e8"; + case 0b001: + return "e16"; + case 0b010: + return "e32"; + case 0b011: + return "e64"; + default: + return "illegal"; + } + } + inline const char* lmul_name(size_t bits) { + switch(bits) { + case 0b101: + return "mf8"; + case 0b110: + return "mf4"; + case 0b111: + return "mf2"; + case 0b000: + return "m1"; + case 0b001: + return "m2"; + case 0b010: + return "m4"; + case 0b011: + return "m8"; + default: + return "illegal"; + } + } + inline const char* ma_name(bool ma) { return ma ? "ma" : "mu"; } + inline const char* ta_name(bool ta) { return ta ? "ta" : "tu"; } + + + virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override; + + // some compile time constants + + inline void raise(uint16_t trap_id, uint16_t cause){ + auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id; + this->core.reg.trap_state = trap_val; + } + + inline void leave(unsigned lvl){ + this->core.leave_trap(lvl); + } + + inline void wait(unsigned type){ + this->core.wait_until(type); + } + + inline void set_tval(uint64_t new_tval){ + tval = new_tval; + } + + inline void lower(){ + this->core.reg.trap_state = 0; + } + uint64_t vlseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ + switch(width_val){ + case 0b000: + return softvector::vector_load_store<256, uint8_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b101: + return softvector::vector_load_store<256, uint16_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b110: + return softvector::vector_load_store<256, uint32_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b111: + return softvector::vector_load_store<256, uint64_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + default: + throw new std::runtime_error("Unsupported width bit value"); + } + } + uint64_t vsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ + switch(width_val){ + case 0b000: + return softvector::vector_load_store<256, uint8_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b101: + return softvector::vector_load_store<256, uint16_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b110: + return softvector::vector_load_store<256, uint32_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b111: + return softvector::vector_load_store<256, uint64_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + default: + throw new std::runtime_error("Unsupported width bit value"); + } + } + uint64_t vlsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ + switch(width_val){ + case 0b000: + return softvector::vector_load_store<256, uint8_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b101: + return softvector::vector_load_store<256, uint16_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b110: + return softvector::vector_load_store<256, uint32_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b111: + return softvector::vector_load_store<256, uint64_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + default: + throw new std::runtime_error("Unsupported width bit value"); + } + } + uint64_t vssseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ + switch(width_val){ + case 0b000: + return softvector::vector_load_store<256, uint8_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b101: + return softvector::vector_load_store<256, uint16_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b110: + return softvector::vector_load_store<256, uint32_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b111: + return softvector::vector_load_store<256, uint64_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + default: + throw new std::runtime_error("Unsupported width bit value"); + } + } + + using indexed_load_store_t = std::function, uint8_t*, uint64_t, uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; + template indexed_load_store_t getFunction() { + return [this](void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, + uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, uint8_t segment_size) { + return softvector::vector_load_store_index<32, 256, T1, T2>(core, load_store_fn, V, vl, vstart, vtype, vm, vd, rs1, vs2, segment_size); + }; + } + + const std::array, 4> functionTable = {{ + {getFunction(), getFunction(), getFunction(), getFunction()}, + {getFunction(), getFunction(), getFunction(), getFunction()}, + {getFunction(), getFunction(), getFunction(), getFunction()}, + {getFunction(), getFunction(), getFunction(), getFunction()} + }}; + const size_t map_index_size[9] = { 0, 0, 1, 0, 2, 0, 0, 0, 3 }; // translate number of bytes to index in functionTable + uint64_t vlxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ + return functionTable[map_index_size[index_byte_size]][data_byte_size](this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size); + } + uint64_t vsxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ + return functionTable[map_index_size[index_byte_size]][data_byte_size](this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size); + } + void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_op<256, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op<256, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op<256, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_op<256, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op<256, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op<256, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_op<256, uint16_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op<256, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op<256, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_op<256, uint16_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op<256, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op<256, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t target_sew_pow, uint8_t frac_pow){ + switch(target_sew_pow){ + case 4: // uint16_t target + if(frac_pow != 1) throw new std::runtime_error("Unsupported frac_pow"); + return softvector::vector_unary_op<256, uint16_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 5: // uint32_t target + switch(frac_pow){ + case 1: + return softvector::vector_unary_op<256, uint32_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 2: + return softvector::vector_unary_op<256, uint32_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported frac_pow"); + } + case 6: // uint64_t target + switch(frac_pow){ + case 1: + return softvector::vector_unary_op<256, uint64_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 2: + return softvector::vector_unary_op<256, uint64_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 3: + return softvector::vector_unary_op<256, uint64_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported frac_pow"); + } + default: + throw new std::runtime_error("Unsupported target_sew_pow"); + } + } + void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_carry<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b001: + return softvector::vector_vector_carry<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b010: + return softvector::vector_vector_carry<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b011: + return softvector::vector_vector_carry<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } } + void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_carry<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b001: + return softvector::vector_imm_carry<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b010: + return softvector::vector_imm_carry<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b011: + return softvector::vector_imm_carry<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::carry_vector_vector_op<256, uint8_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::carry_vector_vector_op<256, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::carry_vector_vector_op<256, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::carry_vector_vector_op<256, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::carry_vector_imm_op<256, uint8_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::carry_vector_imm_op<256, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::carry_vector_imm_op<256, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::carry_vector_imm_op<256, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::mask_vector_vector_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::mask_vector_vector_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::mask_vector_vector_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::mask_vector_vector_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::mask_vector_imm_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::mask_vector_imm_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::mask_vector_imm_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::mask_vector_imm_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_op<256, uint8_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op<256, uint16_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op<256, uint32_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_op<256, uint8_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op<256, uint16_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op<256, uint32_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_merge<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_merge<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_merge<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_merge<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_merge<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_merge<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_merge<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_merge<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::sat_vector_vector_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b001: + return softvector::sat_vector_vector_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b010: + return softvector::sat_vector_vector_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b011: + return softvector::sat_vector_vector_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::sat_vector_imm_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b001: + return softvector::sat_vector_imm_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b010: + return softvector::sat_vector_imm_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b011: + return softvector::sat_vector_imm_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::sat_vector_vector_op<256, uint8_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b001: + return softvector::sat_vector_vector_op<256, uint16_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b010: + return softvector::sat_vector_vector_op<256, uint32_t, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::sat_vector_imm_op<256, uint8_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b001: + return softvector::sat_vector_imm_op<256, uint16_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b010: + return softvector::sat_vector_imm_op<256, uint32_t, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_red_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_red_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_red_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_red_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_red_op<256, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_red_op<256, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_red_op<256, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1){ + return softvector::mask_mask_op<256>(V, funct6, funct3, vl, vstart, vd, vs2, vs1); + } + uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2){ + return softvector::vcpop<256>(V, vl, vstart, vm, vs2); + } + int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2){ + return softvector::vfirst<256>(V, vl, vstart, vm, vs2); + } + void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2){ + return softvector::mask_set_op<256>(V, enc, vl, vstart, vm, vd, vs2); + } + void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::viota<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2); + case 0b001: + return softvector::viota<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2); + case 0b010: + return softvector::viota<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2); + case 0b011: + return softvector::viota<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vid<256, uint8_t>(V, vl, vstart, vtype, vm, vd); + case 0b001: + return softvector::vid<256, uint16_t>(V, vl, vstart, vtype, vm, vd); + case 0b010: + return softvector::vid<256, uint32_t>(V, vl, vstart, vtype, vm, vd); + case 0b011: + return softvector::vid<256, uint64_t>(V, vl, vstart, vtype, vm, vd); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + softvector::scalar_move<256, uint8_t>(V, vtype, vd, val, true); + break; + case 0b001: + softvector::scalar_move<256, uint16_t>(V, vtype, vd, val, true); + break; + case 0b010: + softvector::scalar_move<256, uint32_t>(V, vtype, vd, val, true); + break; + case 0b011: + softvector::scalar_move<256, uint64_t>(V, vtype, vd, val, true); + break; + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::scalar_move<256, uint8_t>(V, vtype, vd, 0, false); + case 0b001: + return softvector::scalar_move<256, uint16_t>(V, vtype, vd, 0, false); + case 0b010: + return softvector::scalar_move<256, uint32_t>(V, vtype, vd, 0, false); + case 0b011: + return softvector::scalar_move<256, uint64_t>(V, vtype, vd, 0, false); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + switch(sew_val){ + case 0b000: + return softvector::vector_slideup<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slideup<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slideup<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slideup<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + switch(sew_val){ + case 0b000: + return softvector::vector_slidedown<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slidedown<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slidedown<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slidedown<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + switch(sew_val){ + case 0b000: + return softvector::vector_slide1up<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slide1up<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slide1up<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slide1up<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + switch(sew_val){ + case 0b000: + return softvector::vector_slide1down<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slide1down<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slide1down<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slide1down<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_gather<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_gather<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_gather<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_gather<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_gather<256, uint8_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_gather<256, uint16_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_gather<256, uint32_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_gather<256, uint64_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_gather<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_gather<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_gather<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_gather<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_compress<256, uint8_t>(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b001: + return softvector::vector_compress<256, uint16_t>(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b010: + return softvector::vector_compress<256, uint32_t>(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b011: + return softvector::vector_compress<256, uint64_t>(V, vl, vstart, vtype, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count){ + return softvector::vector_whole_move<256>(V, vd, vs2, count); + } + uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val){ + return scalar_from_vector(V, vtype, vd, sew_val); + } + void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + return vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); + } + void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + return vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); + } + void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_red_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_red_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::fp_vector_red_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::fp_vector_red_op<256, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b001: + return softvector::fp_vector_red_op<256, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_red_op<256, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::fp_vector_vector_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: + return softvector::fp_vector_imm_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op<256, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op<256, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op<256, uint32_t, uint16_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op<256, uint64_t, uint32_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op<256, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op<256, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op<256, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op<256, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_unary_op<256, uint16_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_op<256, uint32_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: + return softvector::fp_vector_unary_op<256, uint64_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::mask_fp_vector_vector_op<256, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::mask_fp_vector_vector_op<256, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::mask_fp_vector_vector_op<256, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::mask_fp_vector_imm_op<256, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::mask_fp_vector_imm_op<256, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: + return softvector::mask_fp_vector_imm_op<256, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t sew_val){ + vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); + } + void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::fp_vector_unary_w<256, uint16_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b001: + return softvector::fp_vector_unary_w<256, uint32_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_w<256, uint64_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::fp_vector_unary_n<256, uint8_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b001: + return softvector::fp_vector_unary_n<256, uint16_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_n<256, uint32_t, uint64_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: // would require 128 bit value to narrow + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_unary_op<256, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b001: + return softvector::vector_unary_op<256, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b010: + return softvector::vector_unary_op<256, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b011: + return softvector::vector_unary_op<256, uint64_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported sew_val"); + } + } + + uint64_t fetch_count{0}; + uint64_t tval{0}; + + using yield_t = boost::coroutines2::coroutine::push_type; + using coro_t = boost::coroutines2::coroutine::pull_type; + std::vector spawn_blocks; + + template::type> + inline S sext(U from) { + auto mask = (1ULL<(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::FCSR]); + uint8_t rm_eff = rm == 7? bit_sub<5, 7-5+1>(*FCSR) : rm; + if(rm_eff > 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return rm_eff; + } + + uint64_t NaNBox64(uint64_t val){ + if(traits::FLEN == 64) { + return (uint64_t)val; + } + else { + uint64_t box = ~((uint64_t)0); + return (uint64_t)(((uint128_t)box<<64)|val); + } + } + + uint8_t get_pow(uint32_t val){ + switch(val){ + case 8: + return 3; + case 16: + return 4; + case 32: + return 5; + case 64: + return 6; + case 128: + return 7; + case 256: + return 8; + case 512: + return 9; + case 1024: + return 10; + case 2048: + return 11; + case 4096: + return 12; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + + uint8_t lmul(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub<0, 2-0+1>(*vtype); + } + + uint8_t sew(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub<3, 5-3+1>(*vtype); + } + + int8_t get_lmul_pow(){ + switch(lmul()){ + case 5: + return - 3; + case 6: + return - 2; + case 7: + return - 1; + case 0: + return 0; + case 1: + return 1; + case 2: + return 2; + case 3: + return 3; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + + uint8_t get_sew_pow(){ + switch(sew()){ + case 0: + return 3; + case 1: + return 4; + case 2: + return 5; + case 3: + return 6; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + + uint16_t get_elem_count(){ + uint8_t total_pow = (uint8_t)((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow())); + return (uint16_t)(1 << total_pow) & ~1; + } + + uint8_t valid_vtype(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub(*vtype, (uint64_t)(traits::XLEN) - (uint64_t)(1), 1) == 0; + } + + uint8_t valid_rd_mask(uint8_t rd, uint8_t vm){ + return rd != 0 || vm != 0; + } + + uint8_t valid_eew_emul(uint8_t EEW, int8_t EMUL_pow){ + return EEW >= 8 && EEW <= traits::ELEN && EEW <= traits::EEW_MAX && EMUL_pow >= - 3 && EMUL_pow <= 3; + } + + uint8_t valid_segment(uint8_t nf, int8_t EMUL_pow){ + if(EMUL_pow < 0) { + uint8_t neg_EMUL = (uint8_t)(1 << - EMUL_pow) & ~1; + return nf / neg_EMUL <= 8; + } + else { + uint8_t EMUL = (uint8_t)(1 << EMUL_pow) & ~1; + return (uint16_t)(nf) * (uint16_t)(EMUL) <= 8; + } + } + + uint8_t illegal_vd_unmasked(){ + return ! valid_vtype(); + } + + uint8_t illegal_variable_width(uint8_t vd, uint8_t vm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_eew_emul(SEW_new, LMUL_pow_new)); + } + + uint8_t valid_reg_overlap(uint8_t rs, uint8_t rd, int8_t EMUL_pow_rs, int8_t EMUL_pow_rd){ + uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& (1ULL << 4) : 1; + uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& (1ULL << 4) : 1; + if(EMUL_pow_rs < EMUL_pow_rd) { + return (rs + rs_group <= rd) || (rs >= rd + rd_group) || ((rs + rs_group == rd + rd_group) & (EMUL_pow_rs >= 0)); + } + else { + if(EMUL_pow_rs > EMUL_pow_rd) { + return (rd <= rs) || (rd >= rs + rs_group); + } + else { + return true; + } + } + } + + uint8_t illegal_vd_masked(uint8_t vd){ + return ! (valid_vtype()) || vd == 0; + } + + uint8_t illegal_normal(uint8_t vd, uint8_t vm){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)); + } + + uint8_t valid_fp_op(uint8_t SEW, uint8_t rm){ + int8_t valid_sew = (traits::FP_SEW_MIN >= 32 & SEW <= traits::FP_SEW_MAX); + int8_t valid_rm = ! (rm == 5 | rm == 6 | rm == 7); + return valid_sew && valid_rm; + } + + uint8_t illegal_fp_vd_unmasked(uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || ! (valid_fp_op(SEW, rm)); + } + + uint8_t illegal_fp_normal(uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_fp_op(SEW, rm)); + } + + uint8_t valid_sew_lmul(){ + return get_sew_pow() <= (uint16_t)(get_pow(traits::ELEN)) + (int16_t)(get_lmul_pow()); + } + + uint16_t calculate_new_vl(uint32_t avl, uint16_t vlmax){ + if(avl <= vlmax) { + return ((uint16_t)avl); + } + else { + if(avl < ((uint32_t)(2) * (uint32_t)(vlmax))) { + return vlmax; + } + else { + return vlmax; + } + } + } + + void handle_illegal_vtype(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + auto* vl = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vl]); + *vtype = (uint32_t)1 << ((uint64_t)(traits::XLEN) - (uint64_t)(1)); + *vl = (uint32_t)0; + } + + uint8_t convert_width(uint8_t width){ + switch(width){ + case (0): + return 1; + case (5): + return 2; + case (6): + return 4; + case (7): + return 8; + } + return 0; + } + + uint8_t illegal_load(uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return ! valid_vtype() || ! valid_rd_mask(vd, vm) || ! valid_eew_emul(EEW, EMUL_pow) || ! valid_segment(nf, EMUL_pow); + } + + uint8_t illegal_store(uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return ! valid_vtype() || ! valid_eew_emul(EEW, EMUL_pow) || ! valid_segment(nf, EMUL_pow); + } + + uint8_t illegal_indexed_load(uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return ! valid_vtype() || ! valid_rd_mask(vd, vm) || ! valid_eew_emul(EEW_index, EMUL_pow_index) || ! valid_segment(nf, EMUL_pow_data); + } + + uint8_t illegal_indexed_store(uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return ! valid_vtype() || ! valid_eew_emul(EEW_index, EMUL_pow_index) || ! valid_segment(nf, EMUL_pow_data); + } + + uint8_t illegal_reduction(){ + auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); + return ! valid_vtype() || *vstart != 0; + } + + uint8_t illegal_reduction_widen(uint8_t EEW, int8_t EMUL_pow){ + return illegal_reduction() || ! valid_eew_emul(EEW, EMUL_pow); + } + + uint8_t illegal_fp_reduction(uint8_t SEW, uint8_t rm){ + auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); + return ! valid_vtype() || *vstart != 0 || ! valid_fp_op(SEW, rm); + } + + uint8_t illegal_fp_variable_width(uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_fp_op(SEW, rm)) || ! (valid_eew_emul(SEW_new, LMUL_pow_new)); + } + + uint8_t illegal_fp_vd_masked(uint8_t vd, uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || vd == 0 || ! (valid_fp_op(SEW, rm)); + } + + +private: + /**************************************************************************** + * start opcode definitions + ****************************************************************************/ + struct instruction_descriptor { + uint32_t length; + uint32_t value; + uint32_t mask; + typename arch::traits::opcode_e op; + }; + + const std::array instr_descr = {{ + /* entries are: size, valid value, valid mask, function ptr */ + {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits::opcode_e::LUI}, + {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits::opcode_e::AUIPC}, + {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits::opcode_e::JAL}, + {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::JALR}, + {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BEQ}, + {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BNE}, + {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLT}, + {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGE}, + {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLTU}, + {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGEU}, + {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LB}, + {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LH}, + {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LW}, + {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LBU}, + {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LHU}, + {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SB}, + {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SH}, + {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SW}, + {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ADDI}, + {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTI}, + {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTIU}, + {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::XORI}, + {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ORI}, + {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ANDI}, + {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLLI}, + {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRLI}, + {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRAI}, + {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::ADD}, + {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SUB}, + {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLL}, + {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLT}, + {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLTU}, + {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::XOR}, + {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRL}, + {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRA}, + {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::OR}, + {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::AND}, + {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE}, + {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::ECALL}, + {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::EBREAK}, + {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::MRET}, + {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::WFI}, + {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRW}, + {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRS}, + {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRC}, + {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRWI}, + {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRSI}, + {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRCI}, + {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE_I}, + {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MUL}, + {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULH}, + {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULHSU}, + {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULHU}, + {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIV}, + {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIVU}, + {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REM}, + {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REMU}, + {32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, arch::traits::opcode_e::LRW}, + {32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::SCW}, + {32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOSWAPW}, + {32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOADDW}, + {32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOXORW}, + {32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOANDW}, + {32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOORW}, + {32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMINW}, + {32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMAXW}, + {32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMINUW}, + {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMAXUW}, + {16, 0b0000000000000000, 0b1110000000000011, arch::traits::opcode_e::C__ADDI4SPN}, + {16, 0b0100000000000000, 0b1110000000000011, arch::traits::opcode_e::C__LW}, + {16, 0b1100000000000000, 0b1110000000000011, arch::traits::opcode_e::C__SW}, + {16, 0b0000000000000001, 0b1110000000000011, arch::traits::opcode_e::C__ADDI}, + {16, 0b0000000000000001, 0b1110111110000011, arch::traits::opcode_e::C__NOP}, + {16, 0b0010000000000001, 0b1110000000000011, arch::traits::opcode_e::C__JAL}, + {16, 0b0100000000000001, 0b1110000000000011, arch::traits::opcode_e::C__LI}, + {16, 0b0110000000000001, 0b1110000000000011, arch::traits::opcode_e::C__LUI}, + {16, 0b0110000100000001, 0b1110111110000011, arch::traits::opcode_e::C__ADDI16SP}, + {16, 0b0110000000000001, 0b1111000001111111, arch::traits::opcode_e::__reserved_clui}, + {16, 0b1000000000000001, 0b1111110000000011, arch::traits::opcode_e::C__SRLI}, + {16, 0b1000010000000001, 0b1111110000000011, arch::traits::opcode_e::C__SRAI}, + {16, 0b1000100000000001, 0b1110110000000011, arch::traits::opcode_e::C__ANDI}, + {16, 0b1000110000000001, 0b1111110001100011, arch::traits::opcode_e::C__SUB}, + {16, 0b1000110000100001, 0b1111110001100011, arch::traits::opcode_e::C__XOR}, + {16, 0b1000110001000001, 0b1111110001100011, arch::traits::opcode_e::C__OR}, + {16, 0b1000110001100001, 0b1111110001100011, arch::traits::opcode_e::C__AND}, + {16, 0b1010000000000001, 0b1110000000000011, arch::traits::opcode_e::C__J}, + {16, 0b1100000000000001, 0b1110000000000011, arch::traits::opcode_e::C__BEQZ}, + {16, 0b1110000000000001, 0b1110000000000011, arch::traits::opcode_e::C__BNEZ}, + {16, 0b0000000000000010, 0b1111000000000011, arch::traits::opcode_e::C__SLLI}, + {16, 0b0100000000000010, 0b1110000000000011, arch::traits::opcode_e::C__LWSP}, + {16, 0b1000000000000010, 0b1111000000000011, arch::traits::opcode_e::C__MV}, + {16, 0b1000000000000010, 0b1111000001111111, arch::traits::opcode_e::C__JR}, + {16, 0b1000000000000010, 0b1111111111111111, arch::traits::opcode_e::__reserved_cmv}, + {16, 0b1001000000000010, 0b1111000000000011, arch::traits::opcode_e::C__ADD}, + {16, 0b1001000000000010, 0b1111000001111111, arch::traits::opcode_e::C__JALR}, + {16, 0b1001000000000010, 0b1111111111111111, arch::traits::opcode_e::C__EBREAK}, + {16, 0b1100000000000010, 0b1110000000000011, arch::traits::opcode_e::C__SWSP}, + {16, 0b0000000000000000, 0b1111111111111111, arch::traits::opcode_e::DII}, + {32, 0b00000000000000000010000000000111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FLW}, + {32, 0b00000000000000000010000000100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FSW}, + {32, 0b00000000000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FADD__S}, + {32, 0b00001000000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FSUB__S}, + {32, 0b00010000000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FMUL__S}, + {32, 0b00011000000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FDIV__S}, + {32, 0b00101000000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FMIN__S}, + {32, 0b00101000000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FMAX__S}, + {32, 0b01011000000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FSQRT__S}, + {32, 0b00000000000000000000000001000011, 0b00000110000000000000000001111111, arch::traits::opcode_e::FMADD__S}, + {32, 0b00000000000000000000000001000111, 0b00000110000000000000000001111111, arch::traits::opcode_e::FMSUB__S}, + {32, 0b00000000000000000000000001001111, 0b00000110000000000000000001111111, arch::traits::opcode_e::FNMADD__S}, + {32, 0b00000000000000000000000001001011, 0b00000110000000000000000001111111, arch::traits::opcode_e::FNMSUB__S}, + {32, 0b11000000000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__W__S}, + {32, 0b11000000000100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__WU__S}, + {32, 0b11010000000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__S__W}, + {32, 0b11010000000100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__S__WU}, + {32, 0b00100000000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJ__S}, + {32, 0b00100000000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJN__S}, + {32, 0b00100000000000000010000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJX__S}, + {32, 0b11100000000000000000000001010011, 0b11111111111100000111000001111111, arch::traits::opcode_e::FMV__X__W}, + {32, 0b11110000000000000000000001010011, 0b11111111111100000111000001111111, arch::traits::opcode_e::FMV__W__X}, + {32, 0b10100000000000000010000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FEQ__S}, + {32, 0b10100000000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FLT__S}, + {32, 0b10100000000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FLE__S}, + {32, 0b11100000000000000001000001010011, 0b11111111111100000111000001111111, arch::traits::opcode_e::FCLASS__S}, + {16, 0b0110000000000000, 0b1110000000000011, arch::traits::opcode_e::C__FLW}, + {16, 0b1110000000000000, 0b1110000000000011, arch::traits::opcode_e::C__FSW}, + {16, 0b0110000000000010, 0b1110000000000011, arch::traits::opcode_e::C__FLWSP}, + {16, 0b1110000000000010, 0b1110000000000011, arch::traits::opcode_e::C__FSWSP}, + {32, 0b00000000000000000011000000000111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FLD}, + {32, 0b00000000000000000011000000100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FSD}, + {32, 0b00000010000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FADD__D}, + {32, 0b00001010000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FSUB__D}, + {32, 0b00010010000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FMUL__D}, + {32, 0b00011010000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FDIV__D}, + {32, 0b00101010000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FMIN__D}, + {32, 0b00101010000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FMAX__D}, + {32, 0b01011010000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FSQRT__D}, + {32, 0b00000010000000000000000001000011, 0b00000110000000000000000001111111, arch::traits::opcode_e::FMADD__D}, + {32, 0b00000010000000000000000001000111, 0b00000110000000000000000001111111, arch::traits::opcode_e::FMSUB__D}, + {32, 0b00000010000000000000000001001111, 0b00000110000000000000000001111111, arch::traits::opcode_e::FNMADD__D}, + {32, 0b00000010000000000000000001001011, 0b00000110000000000000000001111111, arch::traits::opcode_e::FNMSUB__D}, + {32, 0b11000010000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__W__D}, + {32, 0b11000010000100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__WU__D}, + {32, 0b11010010000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__D__W}, + {32, 0b11010010000100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__D__WU}, + {32, 0b01000000000100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__S__D}, + {32, 0b01000010000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__D__S}, + {32, 0b00100010000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJ__D}, + {32, 0b00100010000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJN__D}, + {32, 0b00100010000000000010000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJX__D}, + {32, 0b10100010000000000010000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FEQ__D}, + {32, 0b10100010000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FLT__D}, + {32, 0b10100010000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FLE__D}, + {32, 0b11100010000000000001000001010011, 0b11111111111100000111000001111111, arch::traits::opcode_e::FCLASS__D}, + {16, 0b0010000000000000, 0b1110000000000011, arch::traits::opcode_e::C__FLD}, + {16, 0b1010000000000000, 0b1110000000000011, arch::traits::opcode_e::C__FSD}, + {16, 0b0010000000000010, 0b1110000000000011, arch::traits::opcode_e::C__FLDSP}, + {16, 0b1010000000000010, 0b1110000000000011, arch::traits::opcode_e::C__FSDSP}, + {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, arch::traits::opcode_e::SFENCE__VMA}, + {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::SRET}, + {32, 0b00000000000000000111000001010111, 0b11110000000000000111000001111111, arch::traits::opcode_e::VSETVLI}, + {32, 0b11000000000000000111000001010111, 0b11110000000000000111000001111111, arch::traits::opcode_e::VSETIVLI}, + {32, 0b10000000000000000111000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VSETVL}, + {32, 0b00000000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE8__V}, + {32, 0b00000000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE16__V}, + {32, 0b00000000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE32__V}, + {32, 0b00000000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE64__V}, + {32, 0b00100000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E8__V}, + {32, 0b00100000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E16__V}, + {32, 0b00100000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E32__V}, + {32, 0b00100000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E64__V}, + {32, 0b01000000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E8__V}, + {32, 0b01000000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E16__V}, + {32, 0b01000000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E32__V}, + {32, 0b01000000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E64__V}, + {32, 0b01100000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E8__V}, + {32, 0b01100000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E16__V}, + {32, 0b01100000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E32__V}, + {32, 0b01100000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E64__V}, + {32, 0b10000000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E8__V}, + {32, 0b10000000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E16__V}, + {32, 0b10000000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E32__V}, + {32, 0b10000000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E64__V}, + {32, 0b10100000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E8__V}, + {32, 0b10100000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E16__V}, + {32, 0b10100000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E32__V}, + {32, 0b10100000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E64__V}, + {32, 0b11000000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E8__V}, + {32, 0b11000000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E16__V}, + {32, 0b11000000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E32__V}, + {32, 0b11000000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E64__V}, + {32, 0b11100000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E8__V}, + {32, 0b11100000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E16__V}, + {32, 0b11100000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E32__V}, + {32, 0b11100000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E64__V}, + {32, 0b00000000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSE8__V}, + {32, 0b00000000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSE16__V}, + {32, 0b00000000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSE32__V}, + {32, 0b00000000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSE64__V}, + {32, 0b00100000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG2E8__V}, + {32, 0b00100000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG2E16__V}, + {32, 0b00100000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG2E32__V}, + {32, 0b00100000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG2E64__V}, + {32, 0b01000000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG3E8__V}, + {32, 0b01000000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG3E16__V}, + {32, 0b01000000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG3E32__V}, + {32, 0b01000000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG3E64__V}, + {32, 0b01100000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG4E8__V}, + {32, 0b01100000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG4E16__V}, + {32, 0b01100000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG4E32__V}, + {32, 0b01100000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG4E64__V}, + {32, 0b10000000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG5E8__V}, + {32, 0b10000000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG5E16__V}, + {32, 0b10000000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG5E32__V}, + {32, 0b10000000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG5E64__V}, + {32, 0b10100000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG6E8__V}, + {32, 0b10100000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG6E16__V}, + {32, 0b10100000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG6E32__V}, + {32, 0b10100000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG6E64__V}, + {32, 0b11000000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG7E8__V}, + {32, 0b11000000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG7E16__V}, + {32, 0b11000000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG7E32__V}, + {32, 0b11000000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG7E64__V}, + {32, 0b11100000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG8E8__V}, + {32, 0b11100000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG8E16__V}, + {32, 0b11100000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG8E32__V}, + {32, 0b11100000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG8E64__V}, + {32, 0b00001000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSE8__V}, + {32, 0b00001000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSE16__V}, + {32, 0b00001000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSE32__V}, + {32, 0b00001000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSE64__V}, + {32, 0b00101000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG2E8__V}, + {32, 0b00101000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG2E16__V}, + {32, 0b00101000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG2E32__V}, + {32, 0b00101000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG2E64__V}, + {32, 0b01001000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG3E8__V}, + {32, 0b01001000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG3E16__V}, + {32, 0b01001000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG3E32__V}, + {32, 0b01001000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG3E64__V}, + {32, 0b01101000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG4E8__V}, + {32, 0b01101000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG4E16__V}, + {32, 0b01101000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG4E32__V}, + {32, 0b01101000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG4E64__V}, + {32, 0b10001000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG5E8__V}, + {32, 0b10001000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG5E16__V}, + {32, 0b10001000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG5E32__V}, + {32, 0b10001000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG5E64__V}, + {32, 0b10101000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG6E8__V}, + {32, 0b10101000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG6E16__V}, + {32, 0b10101000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG6E32__V}, + {32, 0b10101000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG6E64__V}, + {32, 0b11001000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG7E8__V}, + {32, 0b11001000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG7E16__V}, + {32, 0b11001000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG7E32__V}, + {32, 0b11001000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG7E64__V}, + {32, 0b11101000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG8E8__V}, + {32, 0b11101000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG8E16__V}, + {32, 0b11101000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG8E32__V}, + {32, 0b11101000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG8E64__V}, + {32, 0b00001000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSE8__V}, + {32, 0b00001000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSE16__V}, + {32, 0b00001000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSE32__V}, + {32, 0b00001000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSE64__V}, + {32, 0b00101000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG2E8__V}, + {32, 0b00101000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG2E16__V}, + {32, 0b00101000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG2E32__V}, + {32, 0b00101000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG2E64__V}, + {32, 0b01001000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG3E8__V}, + {32, 0b01001000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG3E16__V}, + {32, 0b01001000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG3E32__V}, + {32, 0b01001000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG3E64__V}, + {32, 0b01101000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG4E8__V}, + {32, 0b01101000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG4E16__V}, + {32, 0b01101000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG4E32__V}, + {32, 0b01101000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG4E64__V}, + {32, 0b10001000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG5E8__V}, + {32, 0b10001000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG5E16__V}, + {32, 0b10001000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG5E32__V}, + {32, 0b10001000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG5E64__V}, + {32, 0b10101000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG6E8__V}, + {32, 0b10101000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG6E16__V}, + {32, 0b10101000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG6E32__V}, + {32, 0b10101000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG6E64__V}, + {32, 0b11001000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG7E8__V}, + {32, 0b11001000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG7E16__V}, + {32, 0b11001000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG7E32__V}, + {32, 0b11001000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG7E64__V}, + {32, 0b11101000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG8E8__V}, + {32, 0b11101000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG8E16__V}, + {32, 0b11101000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG8E32__V}, + {32, 0b11101000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG8E64__V}, + {32, 0b00000001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE8FF__V}, + {32, 0b00000001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE16FF__V}, + {32, 0b00000001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE32FF__V}, + {32, 0b00000001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE64FF__V}, + {32, 0b00100001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E8FF__V}, + {32, 0b00100001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E16FF__V}, + {32, 0b00100001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E32FF__V}, + {32, 0b00100001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E64FF__V}, + {32, 0b01000001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E8FF__V}, + {32, 0b01000001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E16FF__V}, + {32, 0b01000001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E32FF__V}, + {32, 0b01000001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E64FF__V}, + {32, 0b01100001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E8FF__V}, + {32, 0b01100001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E16FF__V}, + {32, 0b01100001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E32FF__V}, + {32, 0b01100001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E64FF__V}, + {32, 0b10000001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E8FF__V}, + {32, 0b10000001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E16FF__V}, + {32, 0b10000001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E32FF__V}, + {32, 0b10000001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E64FF__V}, + {32, 0b10100001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E8FF__V}, + {32, 0b10100001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E16FF__V}, + {32, 0b10100001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E32FF__V}, + {32, 0b10100001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E64FF__V}, + {32, 0b11000001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E8FF__V}, + {32, 0b11000001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E16FF__V}, + {32, 0b11000001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E32FF__V}, + {32, 0b11000001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E64FF__V}, + {32, 0b11100001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E8FF__V}, + {32, 0b11100001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E16FF__V}, + {32, 0b11100001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E32FF__V}, + {32, 0b11100001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E64FF__V}, + {32, 0b00000010101100000000000000100111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VSM__V}, + {32, 0b00000010101100000000000000000111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VLM__V}, + {32, 0b00000010100000000000000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL1RE8__V}, + {32, 0b00000010100000000101000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL1RE16__V}, + {32, 0b00000010100000000110000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL1RE32__V}, + {32, 0b00000010100000000111000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL1RE64__V}, + {32, 0b00100010100000000000000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL2RE8__V}, + {32, 0b00100010100000000101000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL2RE16__V}, + {32, 0b00100010100000000110000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL2RE32__V}, + {32, 0b00100010100000000111000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL2RE64__V}, + {32, 0b01100010100000000000000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL4RE8__V}, + {32, 0b01100010100000000101000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL4RE16__V}, + {32, 0b01100010100000000110000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL4RE32__V}, + {32, 0b01100010100000000111000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL4RE64__V}, + {32, 0b11100010100000000000000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL8RE8__V}, + {32, 0b11100010100000000101000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL8RE16__V}, + {32, 0b11100010100000000110000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL8RE32__V}, + {32, 0b11100010100000000111000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL8RE64__V}, + {32, 0b00000010100000000000000000100111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VS1RE64__V}, + {32, 0b00100010100000000000000000100111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VS2RE64__V}, + {32, 0b01100010100000000000000000100111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VS4RE64__V}, + {32, 0b11100010100000000000000000100111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VS8RE64__V}, + {32, 0b00001100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXEI8__V}, + {32, 0b00001100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXEI16__V}, + {32, 0b00001100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXEI32__V}, + {32, 0b00001100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXEI64__V}, + {32, 0b00101100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG2EI8__V}, + {32, 0b00101100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG2EI16__V}, + {32, 0b00101100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG2EI32__V}, + {32, 0b00101100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG2EI64__V}, + {32, 0b01001100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG3EI8__V}, + {32, 0b01001100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG3EI16__V}, + {32, 0b01001100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG3EI32__V}, + {32, 0b01001100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG3EI64__V}, + {32, 0b01101100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG4EI8__V}, + {32, 0b01101100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG4EI16__V}, + {32, 0b01101100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG4EI32__V}, + {32, 0b01101100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG4EI64__V}, + {32, 0b10001100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG5EI8__V}, + {32, 0b10001100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG5EI16__V}, + {32, 0b10001100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG5EI32__V}, + {32, 0b10001100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG5EI64__V}, + {32, 0b10101100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG6EI8__V}, + {32, 0b10101100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG6EI16__V}, + {32, 0b10101100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG6EI32__V}, + {32, 0b10101100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG6EI64__V}, + {32, 0b11001100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG7EI8__V}, + {32, 0b11001100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG7EI16__V}, + {32, 0b11001100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG7EI32__V}, + {32, 0b11001100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG7EI64__V}, + {32, 0b11101100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG8EI8__V}, + {32, 0b11101100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG8EI16__V}, + {32, 0b11101100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG8EI32__V}, + {32, 0b11101100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG8EI64__V}, + {32, 0b00001100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXEI8__V}, + {32, 0b00001100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXEI16__V}, + {32, 0b00001100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXEI32__V}, + {32, 0b00001100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXEI64__V}, + {32, 0b00101100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG2EI8__V}, + {32, 0b00101100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG2EI16__V}, + {32, 0b00101100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG2EI32__V}, + {32, 0b00101100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG2EI64__V}, + {32, 0b01001100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG3EI8__V}, + {32, 0b01001100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG3EI16__V}, + {32, 0b01001100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG3EI32__V}, + {32, 0b01001100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG3EI64__V}, + {32, 0b01101100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG4EI8__V}, + {32, 0b01101100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG4EI16__V}, + {32, 0b01101100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG4EI32__V}, + {32, 0b01101100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG4EI64__V}, + {32, 0b10001100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG5EI8__V}, + {32, 0b10001100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG5EI16__V}, + {32, 0b10001100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG5EI32__V}, + {32, 0b10001100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG5EI64__V}, + {32, 0b10101100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG6EI8__V}, + {32, 0b10101100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG6EI16__V}, + {32, 0b10101100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG6EI32__V}, + {32, 0b10101100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG6EI64__V}, + {32, 0b11001100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG7EI8__V}, + {32, 0b11001100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG7EI16__V}, + {32, 0b11001100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG7EI32__V}, + {32, 0b11001100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG7EI64__V}, + {32, 0b11101100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG8EI8__V}, + {32, 0b11101100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG8EI16__V}, + {32, 0b11101100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG8EI32__V}, + {32, 0b11101100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG8EI64__V}, + {32, 0b00000100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXEI8__V}, + {32, 0b00000100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXEI16__V}, + {32, 0b00000100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXEI32__V}, + {32, 0b00000100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXEI64__V}, + {32, 0b00100100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG2EI8__V}, + {32, 0b00100100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG2EI16__V}, + {32, 0b00100100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG2EI32__V}, + {32, 0b00100100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG2EI64__V}, + {32, 0b01000100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG3EI8__V}, + {32, 0b01000100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG3EI16__V}, + {32, 0b01000100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG3EI32__V}, + {32, 0b01000100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG3EI64__V}, + {32, 0b01100100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG4EI8__V}, + {32, 0b01100100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG4EI16__V}, + {32, 0b01100100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG4EI32__V}, + {32, 0b01100100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG4EI64__V}, + {32, 0b10000100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG5EI8__V}, + {32, 0b10000100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG5EI16__V}, + {32, 0b10000100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG5EI32__V}, + {32, 0b10000100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG5EI64__V}, + {32, 0b10100100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG6EI8__V}, + {32, 0b10100100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG6EI16__V}, + {32, 0b10100100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG6EI32__V}, + {32, 0b10100100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG6EI64__V}, + {32, 0b11000100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG7EI8__V}, + {32, 0b11000100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG7EI16__V}, + {32, 0b11000100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG7EI32__V}, + {32, 0b11000100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG7EI64__V}, + {32, 0b11100100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG8EI8__V}, + {32, 0b11100100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG8EI16__V}, + {32, 0b11100100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG8EI32__V}, + {32, 0b11100100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG8EI64__V}, + {32, 0b00000100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXEI8__V}, + {32, 0b00000100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXEI16__V}, + {32, 0b00000100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXEI32__V}, + {32, 0b00000100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXEI64__V}, + {32, 0b00100100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG2EI8__V}, + {32, 0b00100100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG2EI16__V}, + {32, 0b00100100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG2EI32__V}, + {32, 0b00100100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG2EI64__V}, + {32, 0b01000100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG3EI8__V}, + {32, 0b01000100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG3EI16__V}, + {32, 0b01000100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG3EI32__V}, + {32, 0b01000100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG3EI64__V}, + {32, 0b01100100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG4EI8__V}, + {32, 0b01100100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG4EI16__V}, + {32, 0b01100100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG4EI32__V}, + {32, 0b01100100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG4EI64__V}, + {32, 0b10000100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG5EI8__V}, + {32, 0b10000100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG5EI16__V}, + {32, 0b10000100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG5EI32__V}, + {32, 0b10000100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG5EI64__V}, + {32, 0b10100100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG6EI8__V}, + {32, 0b10100100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG6EI16__V}, + {32, 0b10100100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG6EI32__V}, + {32, 0b10100100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG6EI64__V}, + {32, 0b11000100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG7EI8__V}, + {32, 0b11000100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG7EI16__V}, + {32, 0b11000100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG7EI32__V}, + {32, 0b11000100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG7EI64__V}, + {32, 0b11100100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG8EI8__V}, + {32, 0b11100100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG8EI16__V}, + {32, 0b11100100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG8EI32__V}, + {32, 0b11100100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG8EI64__V}, + {32, 0b00000000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VADD__VI}, + {32, 0b00000000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VADD__VV}, + {32, 0b00000000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VADD__VX}, + {32, 0b00001000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSUB__VV}, + {32, 0b00001000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSUB__VX}, + {32, 0b00001100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRSUB__VI}, + {32, 0b00001100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRSUB__VX}, + {32, 0b11000000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADDU__VV}, + {32, 0b11000000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADDU__VX}, + {32, 0b11001000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUBU__VV}, + {32, 0b11001000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUBU__VX}, + {32, 0b11000100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADD__VV}, + {32, 0b11000100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADD__VX}, + {32, 0b11001100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUB__VV}, + {32, 0b11001100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUB__VX}, + {32, 0b11010000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADDU__WV}, + {32, 0b11010000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADDU__WX}, + {32, 0b11011000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUBU__WV}, + {32, 0b11011000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUBU__WX}, + {32, 0b11010100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADD__WV}, + {32, 0b11010100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADD__WX}, + {32, 0b11011100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUB__WV}, + {32, 0b11011100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUB__WX}, + {32, 0b01001000000000110010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VZEXT__VF2}, + {32, 0b01001000000000111010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VSEXT__VF2}, + {32, 0b01001000000000100010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VZEXT__VF4}, + {32, 0b01001000000000101010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VSEXT__VF4}, + {32, 0b01001000000000010010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VZEXT__VF8}, + {32, 0b01001000000000011010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VSEXT__VF8}, + {32, 0b01000000000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VADC__VVM}, + {32, 0b01000000000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VADC__VXM}, + {32, 0b01000000000000000011000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VADC__VIM}, + {32, 0b01000100000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VVM}, + {32, 0b01000100000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VXM}, + {32, 0b01000100000000000011000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VIM}, + {32, 0b01000110000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VV}, + {32, 0b01000110000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VX}, + {32, 0b01000110000000000011000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VI}, + {32, 0b01001000000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VSBC__VVM}, + {32, 0b01001000000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VSBC__VXM}, + {32, 0b01001100000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMSBC__VVM}, + {32, 0b01001100000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMSBC__VXM}, + {32, 0b01001110000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMSBC__VV}, + {32, 0b01001110000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMSBC__VX}, + {32, 0b00100100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAND__VI}, + {32, 0b00100100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAND__VV}, + {32, 0b00100100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAND__VX}, + {32, 0b00101000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VOR__VI}, + {32, 0b00101000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VOR__VV}, + {32, 0b00101000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VOR__VX}, + {32, 0b00101100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VXOR__VI}, + {32, 0b00101100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VXOR__VV}, + {32, 0b00101100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VXOR__VX}, + {32, 0b10010100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLL__VI}, + {32, 0b10010100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLL__VV}, + {32, 0b10010100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLL__VX}, + {32, 0b10100000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRL__VI}, + {32, 0b10100000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRL__VV}, + {32, 0b10100000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRL__VX}, + {32, 0b10100100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRA__VI}, + {32, 0b10100100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRA__VV}, + {32, 0b10100100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRA__VX}, + {32, 0b10110000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRL__WI}, + {32, 0b10110000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRL__WV}, + {32, 0b10110000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRL__WX}, + {32, 0b10110100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRA__WI}, + {32, 0b10110100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRA__WV}, + {32, 0b10110100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRA__WX}, + {32, 0b01100000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSEQ__VI}, + {32, 0b01100000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSEQ__VV}, + {32, 0b01100000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSEQ__VX}, + {32, 0b01100100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSNE__VI}, + {32, 0b01100100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSNE__VV}, + {32, 0b01100100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSNE__VX}, + {32, 0b01101000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLTU__VV}, + {32, 0b01101000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLTU__VX}, + {32, 0b01101100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLT__VV}, + {32, 0b01101100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLT__VX}, + {32, 0b01110000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLEU__VI}, + {32, 0b01110000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLEU__VV}, + {32, 0b01110000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLEU__VX}, + {32, 0b01110100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLE__VI}, + {32, 0b01110100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLE__VV}, + {32, 0b01110100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLE__VX}, + {32, 0b01111000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSGTU__VI}, + {32, 0b01111000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSGTU__VX}, + {32, 0b01111100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSGT__VI}, + {32, 0b01111100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSGT__VX}, + {32, 0b00010000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMINU__VV}, + {32, 0b00010000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMINU__VX}, + {32, 0b00010100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMIN__VV}, + {32, 0b00010100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMIN__VX}, + {32, 0b00011000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMAXU__VV}, + {32, 0b00011000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMAXU__VX}, + {32, 0b00011100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMAX__VV}, + {32, 0b00011100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMAX__VX}, + {32, 0b10010100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMUL__VV}, + {32, 0b10010100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMUL__VX}, + {32, 0b10011100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULH__VV}, + {32, 0b10011100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULH__VX}, + {32, 0b10010000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULHU__VV}, + {32, 0b10010000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULHU__VX}, + {32, 0b10011000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULHSU__VV}, + {32, 0b10011000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULHSU__VX}, + {32, 0b10000000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VDIVU__VV}, + {32, 0b10000000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VDIVU__VX}, + {32, 0b10000100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VDIV__VV}, + {32, 0b10000100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VDIV__VX}, + {32, 0b10001000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREMU__VV}, + {32, 0b10001000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREMU__VX}, + {32, 0b10001100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREM__VV}, + {32, 0b10001100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREM__VX}, + {32, 0b11101100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMUL__VV}, + {32, 0b11101100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMUL__VX}, + {32, 0b11100000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMULU__VV}, + {32, 0b11100000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMULU__VX}, + {32, 0b11101000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMULSU__VV}, + {32, 0b11101000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMULSU__VX}, + {32, 0b10110100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMACC__VV}, + {32, 0b10110100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMACC__VX}, + {32, 0b10111100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNMSAC__VV}, + {32, 0b10111100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNMSAC__VX}, + {32, 0b10100100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMADD__VV}, + {32, 0b10100100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMADD__VX}, + {32, 0b10101100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNMSUB__VV}, + {32, 0b10101100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNMSUB__VX}, + {32, 0b11110000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACCU__VV}, + {32, 0b11110000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACCU__VX}, + {32, 0b11110100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACC__VV}, + {32, 0b11110100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACC__VX}, + {32, 0b11111100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACCSU__VV}, + {32, 0b11111100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACCSU__VX}, + {32, 0b11111000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACCUS__VX}, + {32, 0b01011100000000000011000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMERGE__VIM}, + {32, 0b01011100000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMERGE__VVM}, + {32, 0b01011100000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMERGE__VXM}, + {32, 0b01011110000000000011000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VMV__V__I}, + {32, 0b01011110000000000000000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VMV__V__V}, + {32, 0b01011110000000000100000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VMV__V__X}, + {32, 0b10000000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADDU__VI}, + {32, 0b10000000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADDU__VV}, + {32, 0b10000000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADDU__VX}, + {32, 0b10000100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADD__VI}, + {32, 0b10000100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADD__VV}, + {32, 0b10000100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADD__VX}, + {32, 0b10001000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSUBU__VV}, + {32, 0b10001000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSUBU__VX}, + {32, 0b10001100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSUB__VV}, + {32, 0b10001100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSUB__VX}, + {32, 0b00100000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAADDU__VV}, + {32, 0b00100000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAADDU__VX}, + {32, 0b00100100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAADD__VV}, + {32, 0b00100100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAADD__VX}, + {32, 0b00101000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VASUBU__VV}, + {32, 0b00101000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VASUBU__VX}, + {32, 0b00101100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VASUB__VV}, + {32, 0b00101100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VASUB__VX}, + {32, 0b10011100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSMUL__VV}, + {32, 0b10011100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSMUL__VX}, + {32, 0b10101000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRL__VI}, + {32, 0b10101000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRL__VV}, + {32, 0b10101000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRL__VX}, + {32, 0b10101100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRA__VI}, + {32, 0b10101100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRA__VV}, + {32, 0b10101100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRA__VX}, + {32, 0b10111000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIPU__WI}, + {32, 0b10111000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIPU__WV}, + {32, 0b10111000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIPU__WX}, + {32, 0b10111100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIP__WI}, + {32, 0b10111100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIP__WV}, + {32, 0b10111100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIP__WX}, + {32, 0b00000000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDSUM__VS}, + {32, 0b00011000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDMAXU__VS}, + {32, 0b00011100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDMAX__VS}, + {32, 0b00010000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDMINU__VS}, + {32, 0b00010100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDMIN__VS}, + {32, 0b00000100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDAND__VS}, + {32, 0b00001000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDOR__VS}, + {32, 0b00001100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDXOR__VS}, + {32, 0b11000000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWREDSUMU__VS}, + {32, 0b11000100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWREDSUM__VS}, + {32, 0b00001100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFREDOSUM__VS}, + {32, 0b00000100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFREDUSUM__VS}, + {32, 0b00011100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFREDMAX__VS}, + {32, 0b00010100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFREDMIN__VS}, + {32, 0b11001100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWREDOSUM__VS}, + {32, 0b11000100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWREDUSUM__VS}, + {32, 0b01100110000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMAND__MM}, + {32, 0b01110110000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMNAND__MM}, + {32, 0b01100010000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMANDN__MM}, + {32, 0b01101110000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMXOR__MM}, + {32, 0b01101010000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMOR__MM}, + {32, 0b01111010000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMNOR__MM}, + {32, 0b01110010000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMORN__MM}, + {32, 0b01111110000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMXNOR__MM}, + {32, 0b01000000000010000010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VCPOP__M}, + {32, 0b01000000000010001010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFIRST__M}, + {32, 0b01010000000000001010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VMSBF__M}, + {32, 0b01010000000000011010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VMSIF__M}, + {32, 0b01010000000000010010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VMSOF__M}, + {32, 0b01010000000010000010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VIOTA__M}, + {32, 0b01010000000010001010000001010111, 0b11111101111111111111000001111111, arch::traits::opcode_e::VID__V}, + {32, 0b01000010000000000110000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VMV__S__X}, + {32, 0b01000010000000000010000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VMV__X__S}, + {32, 0b00111000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDEUP__VI}, + {32, 0b00111000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDEUP__VX}, + {32, 0b00111100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDEDOWN__VI}, + {32, 0b00111100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDEDOWN__VX}, + {32, 0b00111000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDE1UP__VX}, + {32, 0b00111100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDE1DOWN__VX}, + {32, 0b00110000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRGATHER__VI}, + {32, 0b00110000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRGATHER__VV}, + {32, 0b00110000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRGATHER__VX}, + {32, 0b00111000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRGATHEREI16__VV}, + {32, 0b01011110000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VCOMPRESS__VM}, + {32, 0b10011110000000000011000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VMV1R__V}, + {32, 0b10011110000000001011000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VMV2R__V}, + {32, 0b10011110000000011011000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VMV4R__V}, + {32, 0b10011110000000111011000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VMV8R__V}, + {32, 0b01000010000000000101000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VFMV__S__F}, + {32, 0b01000010000000000001000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VFMV__F__S}, + {32, 0b00111000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSLIDE1UP__VF}, + {32, 0b00111100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSLIDE1DOWN__VF}, + {32, 0b00000000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFADD__VF}, + {32, 0b00000000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFADD__VV}, + {32, 0b00001000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSUB__VF}, + {32, 0b00001000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSUB__VV}, + {32, 0b10011100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFRSUB__VF}, + {32, 0b11000000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWADD__VF}, + {32, 0b11000000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWADD__VV}, + {32, 0b11001000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWSUB__VF}, + {32, 0b11001000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWSUB__VV}, + {32, 0b11010000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWADD__WF}, + {32, 0b11010000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWADD__WV}, + {32, 0b11011000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWSUB__WF}, + {32, 0b11011000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWSUB__WV}, + {32, 0b10010000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMUL__VF}, + {32, 0b10010000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMUL__VV}, + {32, 0b10000000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFDIV__VF}, + {32, 0b10000000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFDIV__VV}, + {32, 0b10000100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFRDIV__VF}, + {32, 0b11100000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMUL__VF}, + {32, 0b11100000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMUL__VV}, + {32, 0b10110000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMACC__VF}, + {32, 0b10110000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMACC__VV}, + {32, 0b10110100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMACC__VF}, + {32, 0b10110100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMACC__VV}, + {32, 0b10111000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMSAC__VF}, + {32, 0b10111000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMSAC__VV}, + {32, 0b10111100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMSAC__VF}, + {32, 0b10111100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMSAC__VV}, + {32, 0b10100000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMADD__VF}, + {32, 0b10100000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMADD__VV}, + {32, 0b10100100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMADD__VF}, + {32, 0b10100100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMADD__VV}, + {32, 0b10101000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMSUB__VF}, + {32, 0b10101000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMSUB__VV}, + {32, 0b10101100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMSUB__VF}, + {32, 0b10101100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMSUB__VV}, + {32, 0b11110000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMACC__VF}, + {32, 0b11110000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMACC__VV}, + {32, 0b11110100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWNMACC__VF}, + {32, 0b11110100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWNMACC__VV}, + {32, 0b11111000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMSAC__VF}, + {32, 0b11111000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMSAC__VV}, + {32, 0b11111100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWNMSAC__VF}, + {32, 0b11111100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWNMSAC__VV}, + {32, 0b01001100000000000001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFSQRT__V}, + {32, 0b01001100000000100001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFRSQRT7__V}, + {32, 0b01001100000000101001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFREC7__V}, + {32, 0b00010000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMIN__VF}, + {32, 0b00010000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMIN__VV}, + {32, 0b00011000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMAX__VF}, + {32, 0b00011000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMAX__VV}, + {32, 0b00100000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJ__VF}, + {32, 0b00100000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJ__VV}, + {32, 0b00100100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJN__VF}, + {32, 0b00100100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJN__VV}, + {32, 0b00101000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJX__VF}, + {32, 0b00101000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJX__VV}, + {32, 0b01100000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFEQ__VF}, + {32, 0b01100000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFEQ__VV}, + {32, 0b01110000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFNE__VF}, + {32, 0b01110000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFNE__VV}, + {32, 0b01101100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFLT__VF}, + {32, 0b01101100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFLT__VV}, + {32, 0b01100100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFLE__VF}, + {32, 0b01100100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFLE__VV}, + {32, 0b01110100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFGT__VF}, + {32, 0b01111100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFGE__VF}, + {32, 0b01001100000010000001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCLASS__V}, + {32, 0b01011100000000000101000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VFMERGE__VFM}, + {32, 0b01011110000000000101000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VFMV__V__F}, + {32, 0b01001000000000000001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__XU__F__V}, + {32, 0b01001000000000001001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__X__F__V}, + {32, 0b01001000000000110001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__RTZ__XU__F__V}, + {32, 0b01001000000000111001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__RTZ__X__F__V}, + {32, 0b01001000000000010001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__F__XU__V}, + {32, 0b01001000000000011001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__F__X__V}, + {32, 0b01001000000001000001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__XU__F__V}, + {32, 0b01001000000001001001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__X__F__V}, + {32, 0b01001000000001110001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__RTZ__XU__F__V}, + {32, 0b01001000000001111001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__RTZ__X__F__V}, + {32, 0b01001000000001010001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__F__XU__V}, + {32, 0b01001000000001011001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__F__X__V}, + {32, 0b01001000000001100001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__F__F__V}, + {32, 0b01001000000010001001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__X__F__W}, + {32, 0b01001000000010000001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__XU__F__W}, + {32, 0b01001000000010110001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__RTZ__XU__F__W}, + {32, 0b01001000000010111001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__RTZ__X__F__W}, + {32, 0b01001000000010010001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__F__XU__W}, + {32, 0b01001000000010011001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__F__X__W}, + {32, 0b01001000000010100001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__F__F__W}, + {32, 0b01001000000010101001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__ROD__F__F__W}, + }}; + + //needs to be declared after instr_descr + decoder instr_decoder; + + iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ + if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok) + return iss::Err; + return iss::Ok; + } +}; + +template void debug_fn(CODE_WORD insn) { + volatile CODE_WORD x = insn; + insn = 2 * x; +} +// according to +// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation +#ifdef __GCC__ +constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); } +#elif __cplusplus < 201402L +constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); } +constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; } +#else +constexpr size_t bit_count(uint32_t u) { + size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); + return ((uCount + (uCount >> 3)) & 030707070707) % 63; +} +#endif + +template +vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) +: vm_base(core, core_id, cluster_id) +, instr_decoder([this]() { + std::vector g_instr_descr; + g_instr_descr.reserve(instr_descr.size()); + for (uint32_t i = 0; i < instr_descr.size(); ++i) { + generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i}; + g_instr_descr.push_back(new_instr_descr); + } + return std::move(g_instr_descr); + }()) {} + +inline bool is_icount_limit_enabled(finish_cond_e cond){ + return (cond & finish_cond_e::ICOUNT_LIMIT) == finish_cond_e::ICOUNT_LIMIT; +} + +inline bool is_fcount_limit_enabled(finish_cond_e cond){ + return (cond & finish_cond_e::FCOUNT_LIMIT) == finish_cond_e::FCOUNT_LIMIT; +} + +inline bool is_jump_to_self_enabled(finish_cond_e cond){ + return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF; +} + +template +typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t count_limit){ + auto pc=start; + auto* PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PC]); + auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); + auto& trap_state = this->core.reg.trap_state; + auto& icount = this->core.reg.icount; + auto& cycle = this->core.reg.cycle; + auto& instret = this->core.reg.instret; + auto& instr = this->core.reg.instruction; + // we fetch at max 4 byte, alignment is 2 + auto *const data = reinterpret_cast(&instr); + + while(!this->core.should_stop() && + !(is_icount_limit_enabled(cond) && icount >= count_limit) && + !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){ + if(this->debugging_enabled()) + this->tgt_adapter->check_continue(*PC); + pc.val=*PC; + if(fetch_ins(pc, data)!=iss::Ok){ + if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits::max()); + process_spawn_blocks(); + if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits::max()); + *PC = super::core.enter_trap(trap_state, pc.val, instr); + } else { + if (is_jump_to_self_enabled(cond) && + (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' + uint32_t inst_index = instr_decoder.decode_instr(instr); + opcode_e inst_id = arch::traits::opcode_e::MAX_OPCODE;; + if(inst_index core.reg.last_branch = 0; + if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); + try{ + switch(inst_id){ + case arch::traits::opcode_e::LUI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((int32_t)imm); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AUIPC: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((uint64_t)(*PC) + (int64_t)((int32_t)imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::JAL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t new_pc = (uint32_t)((uint64_t)(*PC) + (int64_t)((int32_t)sext<21>(imm))); + if(new_pc % traits::INSTR_ALIGNMENT) { + set_tval(new_pc); + raise(0, 0); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((uint64_t)(*PC) + (uint64_t)(4)); + } + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::JALR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t addr_mask = (uint32_t)- 2; + uint32_t new_pc = (uint32_t)(((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))) & (uint64_t)(addr_mask)); + if(new_pc % traits::INSTR_ALIGNMENT) { + set_tval(new_pc); + raise(0, 0); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((uint64_t)(*PC) + (uint64_t)(4)); + } + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BEQ: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs1) == *(X+rs2)) { + uint32_t new_pc = (uint32_t)((uint64_t)(*PC) + (int64_t)((int16_t)sext<13>(imm))); + if(new_pc % traits::INSTR_ALIGNMENT) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BNE: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs1) != *(X+rs2)) { + uint32_t new_pc = (uint32_t)((uint64_t)(*PC) + (int64_t)((int16_t)sext<13>(imm))); + if(new_pc % traits::INSTR_ALIGNMENT) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BLT: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) { + uint32_t new_pc = (uint32_t)((uint64_t)(*PC) + (int64_t)((int16_t)sext<13>(imm))); + if(new_pc % traits::INSTR_ALIGNMENT) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BGE: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) { + uint32_t new_pc = (uint32_t)((uint64_t)(*PC) + (int64_t)((int16_t)sext<13>(imm))); + if(new_pc % traits::INSTR_ALIGNMENT) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BLTU: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs1) < *(X+rs2)) { + uint32_t new_pc = (uint32_t)((uint64_t)(*PC) + (int64_t)((int16_t)sext<13>(imm))); + if(new_pc % traits::INSTR_ALIGNMENT) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BGEU: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs1) >= *(X+rs2)) { + uint32_t new_pc = (uint32_t)((uint64_t)(*PC) + (int64_t)((int16_t)sext<13>(imm))); + if(new_pc % traits::INSTR_ALIGNMENT) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LB: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + int8_t res_1 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int8_t res = (int8_t)res_1; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LH: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + int16_t res_2 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int16_t res = (int16_t)res_2; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + int32_t res_3 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int32_t res = (int32_t)res_3; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LBU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + uint8_t res_4 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint8_t res = res_4; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LHU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + uint16_t res_5 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint16_t res = res_5; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SB: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, store_address, (uint8_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SH: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, store_address, (uint16_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SW: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, store_address, (uint32_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ADDI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTIU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::XORI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ORI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ANDI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) << shamt; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) >> shamt; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRAI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = ((uint32_t)((int32_t)*(X+rs1) >> shamt)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ADD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1)) + (uint64_t)(*(X+rs2))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SUB: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1)) - (uint64_t)(*(X+rs2))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) << ((uint64_t)(*(X+rs2)) & ((uint64_t)(traits::XLEN) - (uint64_t)(1))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLT: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::XOR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) ^ *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) >> ((uint64_t)(*(X+rs2)) & ((uint64_t)(traits::XLEN) - (uint64_t)(1))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRA: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> ((uint64_t)(*(X+rs2)) & ((uint64_t)(traits::XLEN) - (uint64_t)(1)))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::OR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) | *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AND: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) & *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FENCE: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + uint8_t fm = ((bit_sub<28,4>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ECALL: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "ecall"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + raise(0, 11); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::EBREAK: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "ebreak"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + raise(0, 3); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MRET: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "mret"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + leave(3); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::WFI: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "wfi"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + wait(1); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t xrs1 = *(X+rs1); + if(rd != 0) { + uint32_t res_6 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_6; + super::template write_mem(traits::CSR, csr, xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = xrd; + } + else { + super::template write_mem(traits::CSR, csr, xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRS: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res_7 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_7; + uint32_t xrs1 = *(X+rs1); + if(rs1 != 0) { + super::template write_mem(traits::CSR, csr, xrd | xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRC: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res_8 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_8; + uint32_t xrs1 = *(X+rs1); + if(rs1 != 0) { + super::template write_mem(traits::CSR, csr, xrd & ~xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRWI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res_9 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_9; + super::template write_mem(traits::CSR, csr, (uint32_t)zimm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRSI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res_10 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_10; + if(zimm != 0) { + super::template write_mem(traits::CSR, csr, xrd | (uint32_t)zimm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRCI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res_11 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_11; + if(zimm != 0) { + super::template write_mem(traits::CSR, csr, xrd & ~((uint32_t)zimm)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FENCE_I: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fencei, imm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MUL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int64_t res = (int64_t)((int32_t)*(X+rs1)) * (int64_t)((int32_t)*(X+rs2)); + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MULH: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int64_t res = (int64_t)((int32_t)*(X+rs1)) * (int64_t)((int32_t)*(X+rs2)); + if(rd != 0) { + *(X+rd) = (uint32_t)(res >> traits::XLEN); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MULHSU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int64_t res = (int64_t)((int32_t)*(X+rs1)) * (uint64_t)(*(X+rs2)); + if(rd != 0) { + *(X+rd) = (uint32_t)(res >> traits::XLEN); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MULHU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = (uint64_t)(*(X+rs1)) * (uint64_t)(*(X+rs2)); + if(rd != 0) { + *(X+rd) = (uint32_t)(res >> traits::XLEN); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::DIV: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int32_t dividend = (int32_t)*(X+rs1); + int32_t divisor = (int32_t)*(X+rs2); + if(rd != 0) { + if(divisor != 0) { + uint32_t MMIN = ((uint32_t)1) << ((uint64_t)(traits::XLEN) - (uint64_t)(1)); + if(*(X+rs1) == MMIN && divisor == - 1) { + *(X+rd) = MMIN; + } + else { + *(X+rd) = (uint32_t)(dividend / divisor); + } + } + else { + *(X+rd) = (uint32_t)- 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::DIVU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs2) != 0) { + if(rd != 0) { + *(X+rd) = *(X+rs1) / *(X+rs2); + } + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)- 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::REM: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs2) != 0) { + uint32_t MMIN = (uint32_t)1 << ((uint64_t)(traits::XLEN) - (uint64_t)(1)); + if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) { + if(rd != 0) { + *(X+rd) = 0; + } + } + else { + if(rd != 0) { + *(X+rd) = ((uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2))); + } + } + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::REMU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs2) != 0) { + if(rd != 0) { + *(X+rd) = *(X+rs1) % *(X+rs2); + } + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LRW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {aq}, {rl}", fmt::arg("mnemonic", "lrw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("aq", name(aq)), fmt::arg("rl", name(rl))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + uint32_t offs = *(X+rs1); + int32_t res_12 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = (uint32_t)((int32_t)res_12); + super::template write_mem(traits::RES, offs, (uint8_t)- 1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SCW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {aq}, {rl}", fmt::arg("mnemonic", "scw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", name(aq)), fmt::arg("rl", name(rl))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = *(X+rs1); + uint8_t res_13 = super::template read_mem(traits::RES, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_13; + if(res1 != 0) { + super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = res1? 0 : 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOSWAPW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoswapw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = *(X+rs1); + uint32_t res = *(X+rs2); + if(rd != 0) { + int32_t res_14 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = (uint32_t)((int32_t)res_14); + } + super::template write_mem(traits::MEM, offs, (uint32_t)res); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOADDW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoaddw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = *(X+rs1); + int32_t res_15 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int32_t res1 = (int32_t)res_15; + int64_t res2 = (int64_t)(res1) + (int64_t)((int32_t)*(X+rs2)); + if(rd != 0) { + *(X+rd) = (uint32_t)res1; + } + super::template write_mem(traits::MEM, offs, (uint32_t)res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOXORW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoxorw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = *(X+rs1); + uint32_t res_16 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_16; + uint32_t res2 = res1 ^ (uint32_t)*(X+rs2); + if(rd != 0) { + *(X+rd) = ((uint32_t)(int32_t)(int32_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOANDW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoandw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = *(X+rs1); + uint32_t res_17 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_17; + uint32_t res2 = res1 & (uint32_t)*(X+rs2); + if(rd != 0) { + *(X+rd) = ((uint32_t)(int32_t)(int32_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOORW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoorw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = *(X+rs1); + uint32_t res_18 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_18; + uint32_t res2 = res1 | (uint32_t)*(X+rs2); + if(rd != 0) { + *(X+rd) = ((uint32_t)(int32_t)(int32_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMINW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amominw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = *(X+rs1); + int32_t res_19 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int32_t res1 = (int32_t)res_19; + uint32_t res2 = res1 > (int32_t)*(X+rs2)? (uint32_t)*(X+rs2) : ((uint32_t)res1); + if(rd != 0) { + *(X+rd) = (uint32_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMAXW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = *(X+rs1); + int32_t res_20 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int32_t res1 = (int32_t)res_20; + uint32_t res2 = res1 < (int32_t)*(X+rs2)? (uint32_t)*(X+rs2) : ((uint32_t)res1); + if(rd != 0) { + *(X+rd) = (uint32_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMINUW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amominuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = *(X+rs1); + uint32_t res_21 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_21; + uint32_t res2 = res1 > (uint32_t)*(X+rs2)? (uint32_t)*(X+rs2) : res1; + if(rd != 0) { + *(X+rd) = ((uint32_t)(int32_t)(int32_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMAXUW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = *(X+rs1); + uint32_t res_22 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_22; + uint32_t res2 = res1 < (int32_t)*(X+rs2)? (uint32_t)*(X+rs2) : res1; + if(rd != 0) { + *(X+rd) = ((uint32_t)(int32_t)(int32_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ADDI4SPN: { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"), + fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(imm) { + *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2)) + (uint64_t)(imm)); + } + else { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__LW: { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8)) + (uint64_t)(uimm)); + int32_t res_23 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd + 8) = (uint32_t)(int32_t)res_23; + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SW: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8)) + (uint64_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2 + 8)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ADDI: { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rs1 != 0) { + *(X+rs1) = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int8_t)sext<6>(imm))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__NOP: { + uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "c.nop"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__JAL: { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"), + fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+1) = (uint32_t)((uint64_t)(*PC) + (uint64_t)(2)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC) + (int64_t)((int16_t)sext<12>(imm))); + this->core.reg.last_branch = 1; + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__LI: { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((int8_t)sext<6>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__LUI: { + uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(imm == 0 || rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + if(rd != 0) { + *(X+rd) = (uint32_t)((int32_t)sext<18>(imm)); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ADDI16SP: { + uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"), + fmt::arg("nzimm", nzimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(nzimm) { + *(X+2) = (uint32_t)((uint64_t)(*(X+2)) + (int64_t)((int16_t)sext<10>(nzimm))); + } + else { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::__reserved_clui: { + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = ".reserved_clui"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SRLI: { + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt; + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SRAI: { + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(shamt) { + *(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> shamt); + } + else { + if(traits::XLEN == 128) { + *(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> 64); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ANDI: { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (int32_t)((int8_t)sext<6>(imm))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SUB: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+rd + 8)) - (uint64_t)(*(X+rs2 + 8))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__XOR: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rd + 8) = *(X+rd + 8) ^ *(X+rs2 + 8); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__OR: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rd + 8) = *(X+rd + 8) | *(X+rs2 + 8); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__AND: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rd + 8) = *(X+rd + 8) & *(X+rs2 + 8); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__J: { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"), + fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *NEXT_PC = (uint32_t)((uint64_t)(*PC) + (int64_t)((int16_t)sext<12>(imm))); + this->core.reg.last_branch = 1; + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__BEQZ: { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(*(X+rs1 + 8) == 0) { + *NEXT_PC = (uint32_t)((uint64_t)(*PC) + (int64_t)((int16_t)sext<9>(imm))); + this->core.reg.last_branch = 1; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__BNEZ: { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(*(X+rs1 + 8) != 0) { + *NEXT_PC = (uint32_t)((uint64_t)(*PC) + (int64_t)((int16_t)sext<9>(imm))); + this->core.reg.last_branch = 1; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SLLI: { + uint8_t nzuimm = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rs1 != 0) { + *(X+rs1) = *(X+rs1) << nzuimm; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__LWSP: { + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rd >= traits::RFS || rd == 0) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = (uint32_t)((uint64_t)(*(X+2)) + (uint64_t)(uimm)); + int32_t res_24 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = (uint32_t)(int32_t)res_24; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__MV: { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__JR: { + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"), + fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs1 && rs1 < traits::RFS) { + uint32_t addr_mask = (uint32_t)- 2; + *NEXT_PC = *(X+(uint32_t)(rs1) % traits::RFS) & addr_mask; + this->core.reg.last_branch = 1; + } + else { + raise(0, 2); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::__reserved_cmv: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = ".reserved_cmv"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + raise(0, 2); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ADD: { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((uint64_t)(*(X+rd)) + (uint64_t)(*(X+rs2))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__JALR: { + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"), + fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t addr_mask = (uint32_t)- 2; + uint32_t new_pc = *(X+rs1); + *(X+1) = (uint32_t)((uint64_t)(*PC) + (uint64_t)(2)); + *NEXT_PC = new_pc & addr_mask; + this->core.reg.last_branch = 1; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__EBREAK: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "c.ebreak"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + raise(0, 3); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SWSP: { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = (uint32_t)((uint64_t)(*(X+2)) + (uint64_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::DII: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "dii"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "flw"), + fmt::arg("rd", fname(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + uint32_t res_25 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(F+rd) = NaNBox32(res_25); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSW: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "fsw"), + fmt::arg("rs2", fname(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, offs, (uint32_t)*(F+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FADD__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fadd_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSUB__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fsub_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMUL__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fmul.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fmul_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FDIV__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fdiv.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fdiv_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMIN__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmin.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fsel_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), 0)); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMAX__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmax.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fsel_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), 1)); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSQRT__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fsqrt.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fsqrt_s(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMADD__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fmadd_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), unbox_s(traits::FLEN, *(F+rs3)), 0, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMSUB__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fmadd_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), unbox_s(traits::FLEN, *(F+rs3)), 1, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FNMADD__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fmadd_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), unbox_s(traits::FLEN, *(F+rs3)), 2, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FNMSUB__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fmadd_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), unbox_s(traits::FLEN, *(F+rs3)), 3, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__W__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.w.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int32_t res = (int32_t)(int32_t)f32toi32(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__WU__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.wu.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int32_t res = (int32_t)(int32_t)f32toui32(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__S__W: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.w"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox32(i32tof32((uint32_t)*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__S__WU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.wu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox32(ui32tof32((uint32_t)*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJ__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnj.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(((uint32_t)bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2)))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1)))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJN__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjn.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& (1ULL << 0)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1)))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJX__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjx.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32((unbox_s(traits::FLEN, *(F+rs2)) & ((uint32_t)1 << 31)) ^ unbox_s(traits::FLEN, *(F+rs1))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMV__X__W: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.x.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(int32_t)(int32_t)*(F+rs1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMV__W__X: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.w.x"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox32((uint32_t)*(X+rs1)); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FEQ__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "feq.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res = fcmp_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), 0); + if(rd != 0) { + *(X+rd) = res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLT__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "flt.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res = fcmp_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), 2); + if(rd != 0) { + *(X+rd) = res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLE__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fle.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res = fcmp_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), 1); + if(rd != 0) { + *(X+rd) = res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCLASS__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fclass.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res = fclass_s(unbox_s(traits::FLEN, *(F+rs1))); + if(rd != 0) { + *(X+rd) = res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FLW: { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rd}), {uimm}({rs1})", fmt::arg("mnemonic", "c.flw"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8)) + (uint64_t)(uimm)); + uint32_t res_26 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res = (uint32_t)res_26; + *(F+rd + 8) = NaNBox32(res); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FSW: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rs2}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fsw"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8)) + (uint64_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint32_t)*(F+rs2 + 8)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FLWSP: { + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f {rd}, {uimm}(x2)", fmt::arg("mnemonic", "c.flwsp"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint32_t offs = (uint32_t)((uint64_t)(*(X+2)) + (uint64_t)(uimm)); + uint32_t res_27 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res = (uint32_t)res_27; + *(F+rd) = NaNBox32(res); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FSWSP: { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f {rs2}, {uimm}(x2), ", fmt::arg("mnemonic", "c.fswsp"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint32_t offs = (uint32_t)((uint64_t)(*(X+2)) + (uint64_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint32_t)*(F+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "fld"), + fmt::arg("rd", fname(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + uint64_t res_28 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(F+rd) = NaNBox64(res_28); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSD: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "fsd"), + fmt::arg("rs2", fname(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1)) + (int64_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, offs, (uint64_t)*(F+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FADD__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSUB__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fsub_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMUL__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fmul.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fmul_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FDIV__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fdiv.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fdiv_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMIN__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmin.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fsel_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), 0)); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMAX__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmax.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fsel_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), 1)); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSQRT__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fsqrt.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fsqrt_d(unbox_d(traits::FLEN, *(F+rs1)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMADD__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 0, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMSUB__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint64_t res = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm))); + *(F+rd) = res; + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FNMADD__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 2, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FNMSUB__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 3, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__W__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.w.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int32_t res = (int32_t)(int32_t)f64toi32(unbox_d(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__WU__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.wu.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int32_t res = (int32_t)(int32_t)f64toui32(unbox_d(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__D__W: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.w"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox64(i32tof64((uint32_t)*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__D__WU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.wu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox64(ui32tof64((uint32_t)*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__S__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(f64tof32(unbox_d(traits::FLEN, *(F+rs1)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__D__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(f32tof64(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJ__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnj.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(((uint64_t)bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2)))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1)))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJN__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjn.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& (1ULL << 0)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1)))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJX__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjx.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64((unbox_d(traits::FLEN, *(F+rs2)) & ((uint64_t)1 << 63)) ^ unbox_d(traits::FLEN, *(F+rs1))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FEQ__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "feq.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = fcmp_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), 0); + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLT__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "flt.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = fcmp_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), 2); + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLE__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fle.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = fcmp_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), 1); + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCLASS__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fclass.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = fclass_d(unbox_d(traits::FLEN, *(F+rs1))); + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FLD: { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rd}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fld"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8)) + (uint64_t)(uimm)); + uint64_t res_29 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res = (uint64_t)res_29; + *(F+rd + 8) = NaNBox64(res); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FSD: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rs2}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fsd"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8)) + (uint64_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint64_t)*(F+rs2 + 8)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FLDSP: { + uint16_t uimm = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f {rd}, {uimm}(x2)", fmt::arg("mnemonic", "c.fldsp"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint32_t offs = (uint32_t)((uint64_t)(*(X+2)) + (uint64_t)(uimm)); + uint64_t res_30 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res = (uint64_t)res_30; + *(F+rd) = NaNBox64(res); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FSDSP: { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint16_t uimm = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f {rs2}, {uimm}(x2), ", fmt::arg("mnemonic", "c.fsdsp"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint32_t offs = (uint32_t)((uint64_t)(*(X+2)) + (uint64_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint64_t)*(F+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SFENCE__VMA: { + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t asid = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {asid}", fmt::arg("mnemonic", "sfence.vma"), + fmt::arg("rs1", name(rs1)), fmt::arg("asid", name(asid))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fencevma, ((uint16_t)(uint8_t)rs1<<8)|(uint8_t)asid); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRET: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "sret"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + leave(1); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSETVLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t lmul = ((bit_sub<20,3>(instr))); + uint8_t sew = ((bit_sub<23,3>(instr))); + uint8_t ta = ((bit_sub<26,1>(instr))); + uint8_t ma = ((bit_sub<27,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {sew}, {lmul}, {ta}, {ma}", fmt::arg("mnemonic", "vsetvli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("sew", sew_name(sew)), fmt::arg("lmul", lmul_name(lmul)), fmt::arg("ta", ta_name(ta)), fmt::arg("ma", ma_name(ma))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t orig_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow()); + uint32_t orig_vstart = *vstart; + *vstart = 0; + *vtype = (uint32_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul); + if(! valid_sew_lmul()) { + handle_illegal_vtype(); + *vstart = orig_vstart; + } + else { + uint16_t VLMAX = (uint16_t)(1 << ((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow()))) & ~1; + if(rs1 != 0) { + uint32_t AVL = *(X+rs1); + *vl = (uint32_t)calculate_new_vl(AVL, VLMAX); + if(rd != 0) { + *(X+rd) = *vl; + } + } + else { + if(rd != 0) { + *vl = VLMAX; + *(X+rd) = (uint32_t)VLMAX; + } + else { + uint8_t new_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow()); + if(orig_ratio != new_ratio) { + handle_illegal_vtype(); + *vstart = orig_vstart; + } + } + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSETIVLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t uimm = ((bit_sub<15,5>(instr))); + uint8_t lmul = ((bit_sub<20,3>(instr))); + uint8_t sew = ((bit_sub<23,3>(instr))); + uint8_t ta = ((bit_sub<26,1>(instr))); + uint8_t ma = ((bit_sub<27,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm}, {sew}, {lmul}, {ta}, {ma}", fmt::arg("mnemonic", "vsetivli"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm), fmt::arg("sew", sew_name(sew)), fmt::arg("lmul", lmul_name(lmul)), fmt::arg("ta", ta_name(ta)), fmt::arg("ma", ma_name(ma))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *vtype = (uint32_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul); + if(! valid_sew_lmul()) { + handle_illegal_vtype(); + } + else { + uint16_t VLMAX = (uint16_t)(1 << ((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow()))) & ~1; + *vl = calculate_new_vl(uimm, VLMAX); + *(X+rd) = *vl; + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSETVL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "vsetvl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t orig_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow()); + uint32_t orig_vstart = *vstart; + *vstart = 0; + if(bit_sub(*(X+rs2), 8, ((uint64_t)(traits::XLEN) - (uint64_t)(2))-8+1)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + *vtype = *(X+rs2); + if(! valid_sew_lmul()) { + handle_illegal_vtype(); + *vstart = orig_vstart; + } + else { + uint16_t VLMAX = (uint16_t)(1 << ((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow()))) & ~1; + if(rs1 != 0) { + uint32_t AVL = *(X+rs1); + *vl = (uint32_t)calculate_new_vl(AVL, VLMAX); + if(rd != 0) { + *(X+rd) = *vl; + } + } + else { + if(rd != 0) { + *vl = VLMAX; + *(X+rd) = (uint32_t)VLMAX; + } + else { + uint8_t new_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow()); + uint8_t vill = bit_sub(*vtype, (uint64_t)(traits::XLEN) - (uint64_t)(1), 1); + if(vill || (orig_ratio != new_ratio)) { + handle_illegal_vtype(); + *vstart = orig_vstart; + } + } + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSE8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSE16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSE32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG2E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG2E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG2E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG2E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG3E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG3E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG3E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG3E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG4E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG4E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG4E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG4E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG5E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG5E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG5E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG5E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG6E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG6E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG6E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG6E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG7E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG7E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG7E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG7E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG8E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG8E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG8E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG8E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG2E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG2E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG2E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG2E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG3E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG3E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG3E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG3E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG4E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG4E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG4E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG4E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG5E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG5E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG5E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG5E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG6E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG6E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG6E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG6E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG7E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG7E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG7E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG7E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG8E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG8E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG8E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG8E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSE8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSE16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSE32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG2E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG2E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG2E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG2E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG3E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG3E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG3E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG3E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG4E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG4E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG4E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG4E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG5E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG5E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG5E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG5E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG6E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG6E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG6E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG6E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG7E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG7E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG7E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG7E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG8E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG8E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG8E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG8E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8, (int32_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); + if(trapped_idx != 1) { + *vl = (uint32_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSM__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {vs3}", fmt::arg("mnemonic", "vsm.v"), + fmt::arg("rs1", name(rs1)), fmt::arg("vs3", vname(vs3))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = *vl % (uint32_t)(8) == 0? *vl / (uint32_t)(8) : (uint32_t)((uint64_t)(*vl / (uint32_t)(8)) + (uint64_t)(1)); + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + uint32_t _vtype = (bit_sub(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint32_t)1<<6)|((uint32_t)0<<3)|bit_sub<0, 2-0+1>(*vtype); + *vstart = (uint32_t)vsseg((uint8_t*)V, evl, *vstart, _vtype, 1, vs3, *(X+rs1), 0, 1); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLM__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {vd}", fmt::arg("mnemonic", "vlm.v"), + fmt::arg("rs1", name(rs1)), fmt::arg("vd", vname(vd))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = *vl % (uint32_t)(8) == 0? *vl / (uint32_t)(8) : (uint32_t)((uint64_t)(*vl / (uint32_t)(8)) + (uint64_t)(1)); + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + uint32_t _vtype = (bit_sub(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint32_t)1<<6)|((uint32_t)0<<3)|bit_sub<0, 2-0+1>(*vtype); + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, _vtype, 1, vd, *(X+rs1), 0, 1); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL1RE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL1RE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(16)); + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL1RE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(32)); + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL1RE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(64)); + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL2RE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(2) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vd % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL2RE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(2) * (uint64_t)(traits::VLEN) / (uint64_t)(16)); + if(vd % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL2RE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(2) * (uint64_t)(traits::VLEN) / (uint64_t)(32)); + if(vd % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL2RE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(2) * (uint64_t)(traits::VLEN) / (uint64_t)(64)); + if(vd % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL4RE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(4) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vd % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL4RE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(4) * (uint64_t)(traits::VLEN) / (uint64_t)(16)); + if(vd % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL4RE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(4) * (uint64_t)(traits::VLEN) / (uint64_t)(32)); + if(vd % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL4RE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(4) * (uint64_t)(traits::VLEN) / (uint64_t)(64)); + if(vd % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL8RE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(8) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vd % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL8RE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(8) * (uint64_t)(traits::VLEN) / (uint64_t)(16)); + if(vd % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL8RE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(8) * (uint64_t)(traits::VLEN) / (uint64_t)(32)); + if(vd % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL8RE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(8) * (uint64_t)(traits::VLEN) / (uint64_t)(64)); + if(vd % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VS1RE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs1re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(evl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VS2RE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs2re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(2) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vs3 % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VS4RE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs4re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(4) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vs3 % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VS8RE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs8re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t evl = (uint32_t)((uint64_t)(8) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vs3 % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint32_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXEI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXEI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXEI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXEI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG2EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG2EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG2EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG2EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG3EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG3EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG3EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG3EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG4EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG4EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG4EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG4EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG5EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG5EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG5EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG5EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG6EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG6EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG6EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG6EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG7EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG7EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG7EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG7EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG8EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG8EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG8EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG8EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXEI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXEI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXEI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXEI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG2EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG2EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG2EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG2EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG3EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG3EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG3EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG3EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG4EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG4EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG4EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG4EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG5EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG5EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG5EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG5EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG6EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG6EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG6EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG6EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG7EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG7EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG7EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG7EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG8EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG8EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG8EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG8EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXEI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXEI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXEI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXEI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG2EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG2EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG2EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG2EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG3EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG3EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG3EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG3EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG4EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG4EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG4EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG4EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG5EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG5EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG5EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG5EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG6EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG6EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG6EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG6EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG7EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG7EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG7EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG7EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG8EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG8EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG8EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG8EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXEI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXEI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXEI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXEI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG2EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG2EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG2EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG2EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG3EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG3EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG3EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG3EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG4EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG4EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG4EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG4EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG5EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG5EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG5EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG5EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG6EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG6EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG6EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG6EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG7EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG7EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG7EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG7EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG8EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG8EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG8EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG8EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADD__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vadd.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 0, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 0, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADD__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 0, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 2, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 2, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRSUB__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vrsub.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 3, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRSUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 3, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADDU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 48, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADDU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 48, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUBU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 50, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUBU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 50, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 49, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADD__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 49, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 51, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 51, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADDU__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwaddu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_ww((uint8_t*)V, 52, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADDU__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwaddu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_ww((uint8_t*)V, 52, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUBU__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsubu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_ww((uint8_t*)V, 54, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUBU__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsubu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_ww((uint8_t*)V, 54, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADD__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwadd.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_ww((uint8_t*)V, 53, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADD__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwadd.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_ww((uint8_t*)V, 53, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUB__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsub.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_ww((uint8_t*)V, 55, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUB__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsub.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_ww((uint8_t*)V, 55, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VZEXT__VF2: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf2"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 2; + int8_t LMUL_pow_target = LMUL_pow - 1; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 6, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSEXT__VF2: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf2"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 2; + int8_t LMUL_pow_target = LMUL_pow - 1; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 7, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VZEXT__VF4: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf4"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 4; + int8_t LMUL_pow_target = LMUL_pow - 2; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 4, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 2); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSEXT__VF4: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf4"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 4; + int8_t LMUL_pow_target = LMUL_pow - 2; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 5, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 2); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VZEXT__VF8: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf8"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 8; + int8_t LMUL_pow_target = LMUL_pow - 3; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 2, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 3); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSEXT__VF8: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf8"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 8; + int8_t LMUL_pow_target = LMUL_pow - 3; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 3, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 3); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADC__VVM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vadc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_carry((uint8_t*)V, 16, 0, *vl, *vstart, *vtype, vd, vs2, vs1, sew(), 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADC__VXM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vadc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_carry((uint8_t*)V, 16, 4, *vl, *vstart, *vtype, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew(), 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADC__VIM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, v0", fmt::arg("mnemonic", "vadc.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_carry((uint8_t*)V, 16, 3, *vl, *vstart, *vtype, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew(), 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VVM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vmadc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_vector_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 0, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VXM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vmadc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 0, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VIM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, v0", fmt::arg("mnemonic", "vmadc.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 0, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmadc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_vector_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 1, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmadc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 1, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}", fmt::arg("mnemonic", "vmadc.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 1, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSBC__VVM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vsbc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_carry((uint8_t*)V, 18, 0, *vl, *vstart, *vtype, vd, vs2, vs1, sew(), - 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSBC__VXM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vsbc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_carry((uint8_t*)V, 18, 4, *vl, *vstart, *vtype, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew(), - 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSBC__VVM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vmsbc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_vector_op((uint8_t*)V, 19, *vl, *vstart, *vtype, 0, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSBC__VXM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vmsbc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 19, *vl, *vstart, *vtype, 0, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSBC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmsbc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_vector_op((uint8_t*)V, 19, *vl, *vstart, *vtype, 1, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSBC__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmsbc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 19, *vl, *vstart, *vtype, 1, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAND__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vand.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 9, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAND__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vand.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 9, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAND__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vand.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 9, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VOR__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vor.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 10, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VOR__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vor.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 10, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VOR__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vor.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 10, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VXOR__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vxor.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 11, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VXOR__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vxor.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 11, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VXOR__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vxor.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 11, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLL__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsll.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 37, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(uint32_t)imm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsll.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 37, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsll.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 37, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(uint32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRL__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsrl.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 40, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(uint32_t)imm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsrl.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 40, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsrl.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 40, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(uint32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRA__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsra.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 41, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(uint32_t)imm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRA__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsra.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 41, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRA__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsra.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 41, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(uint32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRL__WI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnsrl.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_vw((uint8_t*)V, 44, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(uint32_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRL__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnsrl.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_vw((uint8_t*)V, 44, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRL__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnsrl.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_vw((uint8_t*)V, 44, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(uint32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRA__WI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnsra.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_vw((uint8_t*)V, 45, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(uint32_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRA__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnsra.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_vw((uint8_t*)V, 45, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRA__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnsra.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_vw((uint8_t*)V, 45, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(uint32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSEQ__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmseq.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 24, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSEQ__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmseq.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 24, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSEQ__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmseq.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 24, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSNE__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsne.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 25, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSNE__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsne.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 25, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSNE__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsne.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 25, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLTU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsltu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 26, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLTU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsltu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 26, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLT__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmslt.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 27, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLT__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmslt.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 27, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLEU__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsleu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 28, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLEU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsleu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 28, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLEU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsleu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 28, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLE__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsle.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 29, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLE__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsle.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 29, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLE__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsle.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 29, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSGTU__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsgtu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 30, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSGTU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsgtu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 30, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSGT__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsgt.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 31, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSGT__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsgt.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 31, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMINU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vminu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 4, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMINU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vminu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 4, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMIN__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmin.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 5, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMIN__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmin.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 5, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMAXU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmaxu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 6, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMAXU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmaxu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 6, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMAX__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmax.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 7, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMAX__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmax.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 7, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMUL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 37, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMUL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 37, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULH__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulh.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 39, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULH__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulh.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 39, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULHU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulhu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 36, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULHU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulhu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 36, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULHSU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulhsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 38, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULHSU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulhsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 38, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VDIVU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vdivu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 32, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VDIVU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vdivu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 32, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VDIV__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vdiv.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 33, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VDIV__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vdiv.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 33, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREMU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vremu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 34, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREMU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vremu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 34, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREM__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrem.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 35, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREM__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrem.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 35, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMUL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 59, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMUL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 59, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMULU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmulu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 56, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMULU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmulu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 56, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMULSU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmulsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 58, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMULSU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmulsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 58, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 45, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMACC__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmacc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 45, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNMSAC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 47, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNMSAC__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnmsac.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 47, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 41, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADD__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 41, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNMSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 43, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNMSUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnmsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 43, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACCU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmaccu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 60, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACCU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 60, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 61, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACC__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmacc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 61, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACCSU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmaccsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 63, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACCSU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 63, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACCUS__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccus.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)(SEW * 2); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 62, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMERGE__VIM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}", fmt::arg("mnemonic", "vmerge.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 0, vd, vs2, (uint32_t)(int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMERGE__VVM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmerge.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_merge((uint8_t*)V, *vl, *vstart, *vtype, 0, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMERGE__VXM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmerge.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 0, vd, vs2, (uint32_t)(int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV__V__I: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {simm}", fmt::arg("mnemonic", "vmv.v.i"), + fmt::arg("vd", vname(vd)), fmt::arg("simm", simm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 1, vd, 0, (uint32_t)(int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV__V__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs1}", fmt::arg("mnemonic", "vmv.v.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_merge((uint8_t*)V, *vl, *vstart, *vtype, 1, vd, 0, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV__V__X: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vmv.v.x"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 1, vd, 0, (uint32_t)(int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADDU__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vsaddu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 32, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADDU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_op((uint8_t*)V, 32, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADDU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 32, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADD__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vsadd.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 33, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_op((uint8_t*)V, 33, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADD__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 33, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSUBU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_op((uint8_t*)V, 34, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSUBU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 34, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_op((uint8_t*)V, 35, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 35, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAADDU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vaaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 8, 2, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAADDU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vaaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 8, 6, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vaadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 9, 2, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAADD__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vaadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 9, 6, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VASUBU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vasubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 10, 2, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VASUBU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vasubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 10, 6, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VASUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vasub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 11, 2, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VASUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vasub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 11, 6, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSMUL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_op((uint8_t*)V, 39, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSMUL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 39, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRL__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vssrl.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 42, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(uint32_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssrl.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 42, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssrl.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 42, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(uint32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRA__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vssra.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 43, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(uint32_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRA__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssra.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 43, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRA__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssra.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 43, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(uint32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIPU__WI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnclipu.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_vw((uint8_t*)V, 46, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(uint32_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIPU__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnclipu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_vw((uint8_t*)V, 46, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIPU__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnclipu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_vw((uint8_t*)V, 46, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(uint32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIP__WI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnclip.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_vw((uint8_t*)V, 47, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(uint32_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIP__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnclip.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_vw((uint8_t*)V, 47, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIP__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnclip.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_vw((uint8_t*)V, 47, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int32_t)(uint32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredsum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 0, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDMAXU__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmaxu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 6, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDMAX__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmax.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 7, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDMINU__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredminu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 4, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDMIN__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmin.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 5, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDAND__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredand.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 1, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDOR__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredor.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 2, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDXOR__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredxor.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 3, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWREDSUMU__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwredsumu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_reduction_widen(SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_wv((uint8_t*)V, 48, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWREDSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwredsum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_reduction_widen(SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_wv((uint8_t*)V, 49, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFREDOSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredosum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_op((uint8_t*)V, 3, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFREDUSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredusum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_op((uint8_t*)V, 1, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFREDMAX__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredmax.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_op((uint8_t*)V, 7, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFREDMIN__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredmin.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_op((uint8_t*)V, 5, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWREDOSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwredosum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_wv((uint8_t*)V, 51, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWREDUSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwredusum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_wv((uint8_t*)V, 49, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMAND__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmand.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 25, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMNAND__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmnand.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 29, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMANDN__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmandn.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 24, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMXOR__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmxor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 27, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMOR__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 26, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMNOR__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmnor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 30, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMORN__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmorn.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 28, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMXNOR__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmxnor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 31, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VCPOP__M: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}, {vm},", fmt::arg("mnemonic", "vcpop.m"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || illegal_vd_unmasked() || *vstart != 0) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = vcpop((uint8_t*)V, *vl, *vstart, vm, vs2); + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFIRST__M: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}, {vm},", fmt::arg("mnemonic", "vfirst.m"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || illegal_vd_unmasked() || *vstart != 0) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = vfirst((uint8_t*)V, *vl, *vstart, vm, vs2); + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSBF__M: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsbf.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked() || *vstart != 0 || vd == vs2 || (vm && vd == 0)) { + raise(0, 2); + } + else { + mask_set_op((uint8_t*)V, 1, *vl, *vstart, vm, vd, vs2); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSIF__M: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsif.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked() || *vstart != 0 || vd == vs2 || (vm && vd == 0)) { + raise(0, 2); + } + else { + mask_set_op((uint8_t*)V, 3, *vl, *vstart, vm, vd, vs2); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSOF__M: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsof.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked() || *vstart != 0 || vd == vs2 || (vm && vd == 0)) { + raise(0, 2); + } + else { + mask_set_op((uint8_t*)V, 2, *vl, *vstart, vm, vd, vs2); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VIOTA__M: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "viota.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked() || *vstart != 0 || vd == vs2 || (vm && vd == 0)) { + raise(0, 2); + } + else { + viota((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VID__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vm},", fmt::arg("mnemonic", "vid.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vid((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV__S__X: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vmv.s.x"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + scalar_to_vector((uint8_t*)V, *vtype, vd, (int32_t)(int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV__X__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}", fmt::arg("mnemonic", "vmv.x.s"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = scalar_from_vector((uint8_t*)V, *vtype, vs2, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDEUP__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vslideup.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm) || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slideup((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDEUP__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslideup.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm) || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slideup((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, *(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDEDOWN__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vslidedown.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slidedown((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDEDOWN__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslidedown.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slidedown((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, *(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDE1UP__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslide1up.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm) || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slide1up((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDE1DOWN__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslide1down.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slide1down((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, (int32_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRGATHER__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vrgather.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm) || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_imm_gather((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)simm, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRGATHER__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrgather.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm) || vs1 == vd || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_vector_gather((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRGATHER__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrgather.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm) || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_imm_gather((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, *(X+rs1), sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRGATHEREI16__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrgatherei16.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm) || vs1 == vd || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_vector_gatherei16((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VCOMPRESS__VM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vcompress.vm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(*vstart != 0 | vs1 == vd | vs2 == vd | illegal_vd_unmasked()) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + vector_compress((uint8_t*)V, *vl, *vstart, *vtype, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV1R__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv1r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + vector_whole_move((uint8_t*)V, vd, vs2, 1); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV2R__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv2r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(vd % 2 || vs2 % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_whole_move((uint8_t*)V, vd, vs2, 2); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV4R__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv4r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(vd % 4 || vs2 % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_whole_move((uint8_t*)V, vd, vs2, 4); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV8R__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv8r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(vd % 8 || vs2 % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_whole_move((uint8_t*)V, vd, vs2, 8); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMV__S__F: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vfmv.s.f"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + scalar_to_vector((uint8_t*)V, *vtype, vd, (int32_t)(uint32_t)*(F+rs1), sew()); + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMV__F__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}", fmt::arg("mnemonic", "vfmv.f.s"), + fmt::arg("rd", fname(rd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm) || SEW > traits::FLEN) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = fp_scalar_from_vector((uint8_t*)V, *vtype, vs2, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSLIDE1UP__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfslide1up.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_slide1up((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, *(F+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSLIDE1DOWN__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfslide1down.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_slide1down((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, *(F+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFADD__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 0, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 0, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSUB__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 2, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 2, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFRSUB__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfrsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 39, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWADD__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 48, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 48, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWSUB__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 50, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 50, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWADD__WF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwadd.wf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_ww((uint8_t*)V, 52, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWADD__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwadd.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_ww((uint8_t*)V, 52, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWSUB__WF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwsub.wf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_ww((uint8_t*)V, 54, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWSUB__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwsub.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_ww((uint8_t*)V, 54, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMUL__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmul.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 36, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMUL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vfmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 36, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFDIV__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfdiv.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 32, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFDIV__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vfdiv.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 32, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFRDIV__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfrdiv.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 33, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMUL__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmul.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 56, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMUL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 56, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMACC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 44, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 44, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMACC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 45, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 45, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMSAC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 46, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMSAC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 46, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMSAC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 47, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMSAC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 47, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMADD__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 40, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 40, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMADD__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 41, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 41, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMSUB__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 42, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 42, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMSUB__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 43, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 43, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMACC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 60, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 60, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWNMACC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwnmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 61, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWNMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwnmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 61, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMSAC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 62, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMSAC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 62, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWNMSAC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwnmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 63, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWNMSAC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 63, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSQRT__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfsqrt.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 19, 0, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFRSQRT7__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfrsqrt7.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 19, 4, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFREC7__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfrec7.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 19, 5, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMIN__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmin.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 4, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMIN__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmin.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 4, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMAX__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmax.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 6, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMAX__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmax.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 6, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJ__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnj.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 8, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJ__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnj.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 8, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJN__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnjn.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 9, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJN__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnjn.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 9, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJX__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnjx.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 10, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJX__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnjx.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 10, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFEQ__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfeq.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 24, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFEQ__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfeq.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_vector_op((uint8_t*)V, 24, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFNE__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfne.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 28, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFNE__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfne.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_vector_op((uint8_t*)V, 28, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFLT__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmflt.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 27, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFLT__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmflt.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_vector_op((uint8_t*)V, 27, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFLE__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfle.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 25, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFLE__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfle.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_vector_op((uint8_t*)V, 25, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFGT__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfgt.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 29, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFGE__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfge.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 31, *vl, *vstart, *vtype, vm, vd, vs2, (uint32_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCLASS__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfclass.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 19, 16, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMERGE__VFM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vfmerge.vfm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_masked(vd, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 0, vd, vs2, (uint32_t)*(F+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMV__V__F: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vfmv.v.f"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 1, vd, 0, (uint32_t)*(F+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__XU__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 0, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__X__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 1, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__RTZ__XU__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.rtz.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = 1; + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 6, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__RTZ__X__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.rtz.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = 1; + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 7, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__F__XU__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.f.xu.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 2, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__F__X__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.f.x.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 3, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__XU__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 8, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__X__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 9, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__RTZ__XU__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = 1; + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 14, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__RTZ__X__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = 1; + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 15, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__F__XU__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.xu.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 10, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__F__X__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.x.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 11, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__F__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 12, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__X__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.x.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 17, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__XU__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.xu.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 16, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__RTZ__XU__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.xu.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = 1; + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 22, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__RTZ__X__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.x.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = 1; + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 23, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__F__XU__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.xu.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 18, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__F__X__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.x.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 19, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__F__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 20, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__ROD__F__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rod.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 21, *vl, *vstart, *vtype, vm, vd, vs2, 6, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + default: { + if(this->disass_enabled){ + std::string mnemonic = "Illegal Instruction"; + this->core.disass_output(pc.val, mnemonic); + } + *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2); + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + } + }catch(memory_access_exception& e){} + // post execution stuff + process_spawn_blocks(); + if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast(inst_id)); + // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt + // this->core.reg.trap_state = this->core.reg.pending_trap; + // trap check + if(trap_state!=0){ + //In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval) + auto mcause = (trap_state>>16) & 0xff; + super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval); + } else { + icount++; + instret++; + } + *PC = *NEXT_PC; + this->core.reg.trap_state = this->core.reg.pending_trap; + } + fetch_count++; + cycle++; + } + return pc; +} + +} // namespace rv32gcv + +template <> +std::unique_ptr create(arch::rv32gcv *core, unsigned short port, bool dump) { + auto ret = new rv32gcv::vm_impl(*core, dump); + if (port != 0) debugger::server::run_server(ret, port); + return std::unique_ptr(ret); +} +} // namespace interp +} // namespace iss + +#include +#include +#include +#include +namespace iss { +namespace { + +volatile std::array dummy = { + core_factory::instance().register_creator("rv32gcv_msu:interp", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_msu_vp(); + auto vm = new interp::rv32gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("rv32gcv_m:interp", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_m_p(); + auto vm = new interp::rv32gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("rv32gcv_mu:interp", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_mu_p(); + auto vm = new interp::rv32gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }) +}; +} +} +// clang-format on From b164eea33ab98968e61b83a980b218e34ad48b97 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 16 Sep 2025 07:49:32 +0200 Subject: [PATCH 008/230] adds RV64GCV isa --- contrib/instr/RV64GCV_instr.yaml | 5867 ++++++ src/iss/arch/rv64gcv.cpp | 70 + src/iss/arch/rv64gcv.h | 1431 ++ src/sysc/register_rv64gcv.cpp | 99 + src/vm/interp/vm_rv64gcv.cpp | 31909 +++++++++++++++++++++++++++++ 5 files changed, 39376 insertions(+) create mode 100644 contrib/instr/RV64GCV_instr.yaml create mode 100644 src/iss/arch/rv64gcv.cpp create mode 100644 src/iss/arch/rv64gcv.h create mode 100644 src/sysc/register_rv64gcv.cpp create mode 100644 src/vm/interp/vm_rv64gcv.cpp diff --git a/contrib/instr/RV64GCV_instr.yaml b/contrib/instr/RV64GCV_instr.yaml new file mode 100644 index 0000000..6d9c0cd --- /dev/null +++ b/contrib/instr/RV64GCV_instr.yaml @@ -0,0 +1,5867 @@ + +RVI: + LUI: + index: 0 + encoding: 0b00000000000000000000000000110111 + mask: 0b00000000000000000000000001111111 + size: 32 + branch: false + delay: 1 + AUIPC: + index: 1 + encoding: 0b00000000000000000000000000010111 + mask: 0b00000000000000000000000001111111 + size: 32 + branch: false + delay: 1 + JAL: + index: 2 + encoding: 0b00000000000000000000000001101111 + mask: 0b00000000000000000000000001111111 + size: 32 + branch: true + delay: 1 + JALR: + index: 3 + encoding: 0b00000000000000000000000001100111 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BEQ: + index: 4 + encoding: 0b00000000000000000000000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BNE: + index: 5 + encoding: 0b00000000000000000001000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BLT: + index: 6 + encoding: 0b00000000000000000100000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BGE: + index: 7 + encoding: 0b00000000000000000101000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BLTU: + index: 8 + encoding: 0b00000000000000000110000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + BGEU: + index: 9 + encoding: 0b00000000000000000111000001100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: true + delay: [1,1] + LB: + index: 10 + encoding: 0b00000000000000000000000000000011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + LH: + index: 11 + encoding: 0b00000000000000000001000000000011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + LW: + index: 12 + encoding: 0b00000000000000000010000000000011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + LBU: + index: 13 + encoding: 0b00000000000000000100000000000011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + LHU: + index: 14 + encoding: 0b00000000000000000101000000000011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SB: + index: 15 + encoding: 0b00000000000000000000000000100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SH: + index: 16 + encoding: 0b00000000000000000001000000100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SW: + index: 17 + encoding: 0b00000000000000000010000000100011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + ADDI: + index: 18 + encoding: 0b00000000000000000000000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLTI: + index: 19 + encoding: 0b00000000000000000010000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLTIU: + index: 20 + encoding: 0b00000000000000000011000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + XORI: + index: 21 + encoding: 0b00000000000000000100000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + ORI: + index: 22 + encoding: 0b00000000000000000110000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + ANDI: + index: 23 + encoding: 0b00000000000000000111000000010011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLLI: + index: 24 + encoding: 0b00000000000000000001000000010011 + mask: 0b11111100000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SRLI: + index: 25 + encoding: 0b00000000000000000101000000010011 + mask: 0b11111100000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SRAI: + index: 26 + encoding: 0b01000000000000000101000000010011 + mask: 0b11111100000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + ADD: + index: 27 + encoding: 0b00000000000000000000000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SUB: + index: 28 + encoding: 0b01000000000000000000000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLL: + index: 29 + encoding: 0b00000000000000000001000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLT: + index: 30 + encoding: 0b00000000000000000010000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SLTU: + index: 31 + encoding: 0b00000000000000000011000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + XOR: + index: 32 + encoding: 0b00000000000000000100000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SRL: + index: 33 + encoding: 0b00000000000000000101000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + SRA: + index: 34 + encoding: 0b01000000000000000101000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + OR: + index: 35 + encoding: 0b00000000000000000110000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + AND: + index: 36 + encoding: 0b00000000000000000111000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + FENCE: + index: 37 + encoding: 0b00000000000000000000000000001111 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + ECALL: + index: 38 + encoding: 0b00000000000000000000000001110011 + mask: 0b11111111111111111111111111111111 + attributes: [[name:no_cont]] + size: 32 + branch: false + delay: 1 + EBREAK: + index: 39 + encoding: 0b00000000000100000000000001110011 + mask: 0b11111111111111111111111111111111 + attributes: [[name:no_cont]] + size: 32 + branch: false + delay: 1 + MRET: + index: 40 + encoding: 0b00110000001000000000000001110011 + mask: 0b11111111111111111111111111111111 + attributes: [[name:no_cont]] + size: 32 + branch: false + delay: 1 + WFI: + index: 41 + encoding: 0b00010000010100000000000001110011 + mask: 0b11111111111111111111111111111111 + size: 32 + branch: false + delay: 1 + LWU: + index: 42 + encoding: 0b00000000000000000110000000000011 + mask: 0b00000000000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + LD: + index: 43 + encoding: 0b00000000000000000011000000000011 + mask: 0b00000000000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SD: + index: 44 + encoding: 0b00000000000000000011000000100011 + mask: 0b00000000000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + ADDIW: + index: 45 + encoding: 0b00000000000000000000000000011011 + mask: 0b00000000000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SLLIW: + index: 46 + encoding: 0b00000000000000000001000000011011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SRLIW: + index: 47 + encoding: 0b00000000000000000101000000011011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SRAIW: + index: 48 + encoding: 0b01000000000000000101000000011011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + ADDW: + index: 49 + encoding: 0b00000000000000000000000000111011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SUBW: + index: 50 + encoding: 0b01000000000000000000000000111011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SLLW: + index: 51 + encoding: 0b00000000000000000001000000111011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SRLW: + index: 52 + encoding: 0b00000000000000000101000000111011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SRAW: + index: 53 + encoding: 0b01000000000000000101000000111011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 +Zicsr: + CSRRW: + index: 54 + encoding: 0b00000000000000000001000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + CSRRS: + index: 55 + encoding: 0b00000000000000000010000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + CSRRC: + index: 56 + encoding: 0b00000000000000000011000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + CSRRWI: + index: 57 + encoding: 0b00000000000000000101000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + CSRRSI: + index: 58 + encoding: 0b00000000000000000110000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 + CSRRCI: + index: 59 + encoding: 0b00000000000000000111000001110011 + mask: 0b00000000000000000111000001111111 + size: 32 + branch: false + delay: 1 +Zifencei: + FENCE_I: + index: 60 + encoding: 0b00000000000000000001000000001111 + mask: 0b00000000000000000111000001111111 + attributes: [[name:flush]] + size: 32 + branch: false + delay: 1 +RVM: + MUL: + index: 61 + encoding: 0b00000010000000000000000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + MULH: + index: 62 + encoding: 0b00000010000000000001000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + MULHSU: + index: 63 + encoding: 0b00000010000000000010000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + MULHU: + index: 64 + encoding: 0b00000010000000000011000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + DIV: + index: 65 + encoding: 0b00000010000000000100000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + DIVU: + index: 66 + encoding: 0b00000010000000000101000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + REM: + index: 67 + encoding: 0b00000010000000000110000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + REMU: + index: 68 + encoding: 0b00000010000000000111000000110011 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + MULW: + index: 69 + encoding: 0b00000010000000000000000000111011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + DIVW: + index: 70 + encoding: 0b00000010000000000100000000111011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + DIVUW: + index: 71 + encoding: 0b00000010000000000101000000111011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + REMW: + index: 72 + encoding: 0b00000010000000000110000000111011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + REMUW: + index: 73 + encoding: 0b00000010000000000111000000111011 + mask: 0b11111110000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 +RVA: + LRW: + index: 74 + encoding: 0b00010000000000000010000000101111 + mask: 0b11111001111100000111000001111111 + size: 32 + branch: false + delay: 1 + SCW: + index: 75 + encoding: 0b00011000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOSWAPW: + index: 76 + encoding: 0b00001000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOADDW: + index: 77 + encoding: 0b00000000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOXORW: + index: 78 + encoding: 0b00100000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOANDW: + index: 79 + encoding: 0b01100000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOORW: + index: 80 + encoding: 0b01000000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOMINW: + index: 81 + encoding: 0b10000000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOMAXW: + index: 82 + encoding: 0b10100000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOMINUW: + index: 83 + encoding: 0b11000000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + AMOMAXUW: + index: 84 + encoding: 0b11100000000000000010000000101111 + mask: 0b11111000000000000111000001111111 + size: 32 + branch: false + delay: 1 + LRD: + index: 85 + encoding: 0b00010000000000000011000000101111 + mask: 0b11111001111100000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + SCD: + index: 86 + encoding: 0b00011000000000000011000000101111 + mask: 0b11111000000000000111000001111111 + attributes: [[name:enable, value:1]] + size: 32 + branch: false + delay: 1 + AMOSWAPD: + index: 87 + encoding: 0b00001000000000000011000000101111 + mask: 0b11111000000000000111000001111111 + attributes: [[name:enable, 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delay: 1 + VZEXT__VF8: + index: 540 + encoding: 0b01001000000000010010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VSEXT__VF8: + index: 541 + encoding: 0b01001000000000011010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VADC__VVM: + index: 542 + encoding: 0b01000000000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VADC__VXM: + index: 543 + encoding: 0b01000000000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VADC__VIM: + index: 544 + encoding: 0b01000000000000000011000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VVM: + index: 545 + encoding: 0b01000100000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VXM: + index: 546 + encoding: 0b01000100000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VIM: + index: 547 + encoding: 0b01000100000000000011000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VV: + index: 548 + encoding: 0b01000110000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VX: + index: 549 + encoding: 0b01000110000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMADC__VI: + index: 550 + encoding: 0b01000110000000000011000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSBC__VVM: + index: 551 + encoding: 0b01001000000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSBC__VXM: + index: 552 + encoding: 0b01001000000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSBC__VVM: + index: 553 + encoding: 0b01001100000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSBC__VXM: + index: 554 + encoding: 0b01001100000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSBC__VV: + index: 555 + encoding: 0b01001110000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSBC__VX: + index: 556 + encoding: 0b01001110000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAND__VI: + index: 557 + encoding: 0b00100100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAND__VV: + index: 558 + encoding: 0b00100100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAND__VX: + index: 559 + encoding: 0b00100100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VOR__VI: + index: 560 + encoding: 0b00101000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VOR__VV: + index: 561 + encoding: 0b00101000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VOR__VX: + index: 562 + encoding: 0b00101000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VXOR__VI: + index: 563 + encoding: 0b00101100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VXOR__VV: + index: 564 + encoding: 0b00101100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VXOR__VX: + index: 565 + encoding: 0b00101100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSLL__VI: + index: 566 + encoding: 0b10010100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSLL__VV: + index: 567 + encoding: 0b10010100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSLL__VX: + index: 568 + encoding: 0b10010100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRL__VI: + index: 569 + encoding: 0b10100000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRL__VV: + index: 570 + encoding: 0b10100000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRL__VX: + index: 571 + encoding: 0b10100000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRA__VI: + index: 572 + encoding: 0b10100100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRA__VV: + index: 573 + encoding: 0b10100100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSRA__VX: + index: 574 + encoding: 0b10100100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRL__WI: + index: 575 + encoding: 0b10110000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRL__WV: + index: 576 + encoding: 0b10110000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRL__WX: + index: 577 + encoding: 0b10110000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRA__WI: + index: 578 + encoding: 0b10110100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRA__WV: + index: 579 + encoding: 0b10110100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNSRA__WX: + index: 580 + encoding: 0b10110100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSEQ__VI: + index: 581 + encoding: 0b01100000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSEQ__VV: + index: 582 + encoding: 0b01100000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSEQ__VX: + index: 583 + encoding: 0b01100000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSNE__VI: + index: 584 + encoding: 0b01100100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSNE__VV: + index: 585 + encoding: 0b01100100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSNE__VX: + index: 586 + encoding: 0b01100100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLTU__VV: + index: 587 + encoding: 0b01101000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLTU__VX: + index: 588 + encoding: 0b01101000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLT__VV: + index: 589 + encoding: 0b01101100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLT__VX: + index: 590 + encoding: 0b01101100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLEU__VI: + index: 591 + encoding: 0b01110000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLEU__VV: + index: 592 + encoding: 0b01110000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLEU__VX: + index: 593 + encoding: 0b01110000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLE__VI: + index: 594 + encoding: 0b01110100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLE__VV: + index: 595 + encoding: 0b01110100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSLE__VX: + index: 596 + encoding: 0b01110100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMSGTU__VI: + index: 597 + encoding: 0b01111000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + 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size: 32 + branch: false + delay: 1 + VMULH__VV: + index: 611 + encoding: 0b10011100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMULH__VX: + index: 612 + encoding: 0b10011100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMULHU__VV: + index: 613 + encoding: 0b10010000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMULHU__VX: + index: 614 + encoding: 0b10010000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMULHSU__VV: + index: 615 + encoding: 0b10011000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMULHSU__VX: + index: 616 + encoding: 0b10011000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VDIVU__VV: + index: 617 + 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0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREM__VX: + index: 624 + encoding: 0b10001100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMUL__VV: + index: 625 + encoding: 0b11101100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMUL__VX: + index: 626 + encoding: 0b11101100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMULU__VV: + index: 627 + encoding: 0b11100000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMULU__VX: + index: 628 + encoding: 0b11100000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMULSU__VV: + index: 629 + encoding: 0b11101000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 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false + delay: 1 + VWMACCSU__VV: + index: 643 + encoding: 0b11111100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMACCSU__VX: + index: 644 + encoding: 0b11111100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWMACCUS__VX: + index: 645 + encoding: 0b11111000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMERGE__VIM: + index: 646 + encoding: 0b01011100000000000011000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMERGE__VVM: + index: 647 + encoding: 0b01011100000000000000000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMERGE__VXM: + index: 648 + encoding: 0b01011100000000000100000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMV__V__I: + index: 649 + encoding: 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0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSADD__VV: + index: 656 + encoding: 0b10000100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSADD__VX: + index: 657 + encoding: 0b10000100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSUBU__VV: + index: 658 + encoding: 0b10001000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSUBU__VX: + index: 659 + encoding: 0b10001000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSUB__VV: + index: 660 + encoding: 0b10001100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSUB__VX: + index: 661 + encoding: 0b10001100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAADDU__VV: + index: 662 + encoding: 0b00100000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAADDU__VX: + index: 663 + encoding: 0b00100000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAADD__VV: + index: 664 + encoding: 0b00100100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VAADD__VX: + index: 665 + encoding: 0b00100100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VASUBU__VV: + index: 666 + encoding: 0b00101000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VASUBU__VX: + index: 667 + encoding: 0b00101000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VASUB__VV: + index: 668 + encoding: 0b00101100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VASUB__VX: + index: 669 + encoding: 0b00101100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSMUL__VV: + index: 670 + encoding: 0b10011100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSMUL__VX: + index: 671 + encoding: 0b10011100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRL__VI: + index: 672 + encoding: 0b10101000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRL__VV: + index: 673 + encoding: 0b10101000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRL__VX: + index: 674 + encoding: 0b10101000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRA__VI: + index: 675 + encoding: 0b10101100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRA__VV: + index: 676 + encoding: 0b10101100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSSRA__VX: + index: 677 + encoding: 0b10101100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNCLIPU__WI: + index: 678 + encoding: 0b10111000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNCLIPU__WV: + index: 679 + encoding: 0b10111000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNCLIPU__WX: + index: 680 + encoding: 0b10111000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNCLIP__WI: + index: 681 + encoding: 0b10111100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNCLIP__WV: + index: 682 + encoding: 0b10111100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VNCLIP__WX: + index: 683 + encoding: 0b10111100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 +RVVBase_red: + VREDSUM__VS: + index: 684 + encoding: 0b00000000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREDMAXU__VS: + index: 685 + encoding: 0b00011000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREDMAX__VS: + index: 686 + encoding: 0b00011100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREDMINU__VS: + index: 687 + encoding: 0b00010000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREDMIN__VS: + index: 688 + encoding: 0b00010100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREDAND__VS: + index: 689 + encoding: 0b00000100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREDOR__VS: + index: 690 + encoding: 0b00001000000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VREDXOR__VS: + index: 691 + encoding: 0b00001100000000000010000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWREDSUMU__VS: + index: 692 + encoding: 0b11000000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VWREDSUM__VS: + index: 693 + encoding: 0b11000100000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false 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VMAND__MM: + index: 700 + encoding: 0b01100110000000000010000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMNAND__MM: + index: 701 + encoding: 0b01110110000000000010000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMANDN__MM: + index: 702 + encoding: 0b01100010000000000010000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMXOR__MM: + index: 703 + encoding: 0b01101110000000000010000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMOR__MM: + index: 704 + encoding: 0b01101010000000000010000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMNOR__MM: + index: 705 + encoding: 0b01111010000000000010000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMORN__MM: + index: 706 + encoding: 0b01110010000000000010000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMXNOR__MM: + index: 707 + encoding: 0b01111110000000000010000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VCPOP__M: + index: 708 + encoding: 0b01000000000010000010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFIRST__M: + index: 709 + encoding: 0b01000000000010001010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VMSBF__M: + index: 710 + encoding: 0b01010000000000001010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VMSIF__M: + index: 711 + encoding: 0b01010000000000011010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VMSOF__M: + index: 712 + encoding: 0b01010000000000010010000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 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0b00111100000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSLIDEDOWN__VX: + index: 720 + encoding: 0b00111100000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSLIDE1UP__VX: + index: 721 + encoding: 0b00111000000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VSLIDE1DOWN__VX: + index: 722 + encoding: 0b00111100000000000110000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VRGATHER__VI: + index: 723 + encoding: 0b00110000000000000011000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VRGATHER__VV: + index: 724 + encoding: 0b00110000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VRGATHER__VX: + index: 725 + encoding: 0b00110000000000000100000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VRGATHEREI16__VV: + index: 726 + encoding: 0b00111000000000000000000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VCOMPRESS__VM: + index: 727 + encoding: 0b01011110000000000010000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMV1R__V: + index: 728 + encoding: 0b10011110000000000011000001010111 + mask: 0b11111110000011111111000001111111 + size: 32 + branch: false + delay: 1 + VMV2R__V: + index: 729 + encoding: 0b10011110000000001011000001010111 + mask: 0b11111110000011111111000001111111 + size: 32 + branch: false + delay: 1 + VMV4R__V: + index: 730 + encoding: 0b10011110000000011011000001010111 + mask: 0b11111110000011111111000001111111 + size: 32 + branch: false + delay: 1 + VMV8R__V: + index: 731 + encoding: 0b10011110000000111011000001010111 + mask: 0b11111110000011111111000001111111 + size: 32 + branch: false + delay: 1 +RVVBase_perm_fp: + VFMV__S__F: + index: 732 + encoding: 0b01000010000000000101000001010111 + mask: 0b11111111111100000111000001111111 + size: 32 + branch: false + delay: 1 + VFMV__F__S: + index: 733 + encoding: 0b01000010000000000001000001010111 + mask: 0b11111110000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFSLIDE1UP__VF: + index: 734 + encoding: 0b00111000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSLIDE1DOWN__VF: + index: 735 + encoding: 0b00111100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 +RVVBase_fp: + VFADD__VF: + index: 736 + encoding: 0b00000000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFADD__VV: + index: 737 + encoding: 0b00000000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSUB__VF: + index: 738 + encoding: 0b00001000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSUB__VV: + index: 739 + encoding: 0b00001000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFRSUB__VF: + index: 740 + encoding: 0b10011100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWADD__VF: + index: 741 + encoding: 0b11000000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWADD__VV: + index: 742 + encoding: 0b11000000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWSUB__VF: + index: 743 + encoding: 0b11001000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWSUB__VV: + index: 744 + encoding: 0b11001000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWADD__WF: + index: 745 + encoding: 0b11010000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWADD__WV: + index: 746 + encoding: 0b11010000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWSUB__WF: + index: 747 + encoding: 0b11011000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWSUB__WV: + index: 748 + encoding: 0b11011000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMUL__VF: + index: 749 + encoding: 0b10010000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMUL__VV: + index: 750 + encoding: 0b10010000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFDIV__VF: + index: 751 + encoding: 0b10000000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFDIV__VV: + index: 752 + encoding: 0b10000000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFRDIV__VF: + index: 753 + encoding: 0b10000100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMUL__VF: + index: 754 + encoding: 0b11100000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMUL__VV: + index: 755 + encoding: 0b11100000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMACC__VF: + index: 756 + encoding: 0b10110000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMACC__VV: + index: 757 + encoding: 0b10110000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMACC__VF: + index: 758 + encoding: 0b10110100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMACC__VV: + index: 759 + encoding: 0b10110100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMSAC__VF: + index: 760 + encoding: 0b10111000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMSAC__VV: + index: 761 + encoding: 0b10111000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMSAC__VF: + index: 762 + encoding: 0b10111100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMSAC__VV: + index: 763 + encoding: 0b10111100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMADD__VF: + index: 764 + encoding: 0b10100000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMADD__VV: + index: 765 + encoding: 0b10100000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMADD__VF: + index: 766 + encoding: 0b10100100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMADD__VV: + index: 767 + encoding: 0b10100100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMSUB__VF: + index: 768 + encoding: 0b10101000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMSUB__VV: + index: 769 + encoding: 0b10101000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMSUB__VF: + index: 770 + encoding: 0b10101100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFNMSUB__VV: + index: 771 + encoding: 0b10101100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMACC__VF: + index: 772 + encoding: 0b11110000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMACC__VV: + index: 773 + encoding: 0b11110000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWNMACC__VF: + index: 774 + encoding: 0b11110100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWNMACC__VV: + index: 775 + encoding: 0b11110100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMSAC__VF: + index: 776 + encoding: 0b11111000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWMSAC__VV: + index: 777 + encoding: 0b11111000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWNMSAC__VF: + index: 778 + encoding: 0b11111100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFWNMSAC__VV: + index: 779 + encoding: 0b11111100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSQRT__V: + index: 780 + encoding: 0b01001100000000000001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFRSQRT7__V: + index: 781 + encoding: 0b01001100000000100001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFREC7__V: + index: 782 + encoding: 0b01001100000000101001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFMIN__VF: + index: 783 + encoding: 0b00010000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMIN__VV: + index: 784 + encoding: 0b00010000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMAX__VF: + index: 785 + encoding: 0b00011000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMAX__VV: + index: 786 + encoding: 0b00011000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJ__VF: + index: 787 + encoding: 0b00100000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJ__VV: + index: 788 + encoding: 0b00100000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJN__VF: + index: 789 + encoding: 0b00100100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJN__VV: + index: 790 + encoding: 0b00100100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJX__VF: + index: 791 + encoding: 0b00101000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFSGNJX__VV: + index: 792 + encoding: 0b00101000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFEQ__VF: + index: 793 + encoding: 0b01100000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFEQ__VV: + index: 794 + encoding: 0b01100000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFNE__VF: + index: 795 + encoding: 0b01110000000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFNE__VV: + index: 796 + encoding: 0b01110000000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFLT__VF: + index: 797 + encoding: 0b01101100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFLT__VV: + index: 798 + encoding: 0b01101100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFLE__VF: + index: 799 + encoding: 0b01100100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFLE__VV: + index: 800 + encoding: 0b01100100000000000001000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFGT__VF: + index: 801 + encoding: 0b01110100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VMFGE__VF: + index: 802 + encoding: 0b01111100000000000101000001010111 + mask: 0b11111100000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFCLASS__V: + index: 803 + encoding: 0b01001100000010000001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFMERGE__VFM: + index: 804 + encoding: 0b01011100000000000101000001010111 + mask: 0b11111110000000000111000001111111 + size: 32 + branch: false + delay: 1 + VFMV__V__F: + index: 805 + encoding: 0b01011110000000000101000001010111 + mask: 0b11111111111100000111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__XU__F__V: + index: 806 + encoding: 0b01001000000000000001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__X__F__V: + index: 807 + encoding: 0b01001000000000001001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__RTZ__XU__F__V: + index: 808 + encoding: 0b01001000000000110001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__RTZ__X__F__V: + index: 809 + encoding: 0b01001000000000111001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__F__XU__V: + index: 810 + encoding: 0b01001000000000010001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFCVT__F__X__V: + index: 811 + encoding: 0b01001000000000011001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__XU__F__V: + index: 812 + encoding: 0b01001000000001000001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__X__F__V: + index: 813 + encoding: 0b01001000000001001001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__RTZ__XU__F__V: + index: 814 + encoding: 0b01001000000001110001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__RTZ__X__F__V: + index: 815 + encoding: 0b01001000000001111001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__F__XU__V: + index: 816 + encoding: 0b01001000000001010001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__F__X__V: + index: 817 + encoding: 0b01001000000001011001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFWCVT__F__F__V: + index: 818 + encoding: 0b01001000000001100001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__X__F__W: + index: 819 + encoding: 0b01001000000010001001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__XU__F__W: + index: 820 + encoding: 0b01001000000010000001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__RTZ__XU__F__W: + index: 821 + encoding: 0b01001000000010110001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__RTZ__X__F__W: + index: 822 + encoding: 0b01001000000010111001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__F__XU__W: + index: 823 + encoding: 0b01001000000010010001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__F__X__W: + index: 824 + encoding: 0b01001000000010011001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__F__F__W: + index: 825 + encoding: 0b01001000000010100001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + VFNCVT__ROD__F__F__W: + index: 826 + encoding: 0b01001000000010101001000001010111 + mask: 0b11111100000011111111000001111111 + size: 32 + branch: false + delay: 1 + diff --git a/src/iss/arch/rv64gcv.cpp b/src/iss/arch/rv64gcv.cpp new file mode 100644 index 0000000..3264c79 --- /dev/null +++ b/src/iss/arch/rv64gcv.cpp @@ -0,0 +1,70 @@ +/******************************************************************************* + * Copyright (C) 2024 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +// clang-format off +#include "rv64gcv.h" +#include "util/ities.h" +#include +#include +#include +#include + +using namespace iss::arch; + +constexpr std::array iss::arch::traits::reg_names; +constexpr std::array iss::arch::traits::reg_aliases; +constexpr std::array iss::arch::traits::reg_bit_widths; +constexpr std::array iss::arch::traits::reg_byte_offsets; + +rv64gcv::rv64gcv() = default; + +rv64gcv::~rv64gcv() = default; + +void rv64gcv::reset(uint64_t address) { + auto base_ptr = reinterpret_cast::reg_t*>(get_regs_base_ptr()); + for(size_t i=0; i::NUM_REGS; ++i) + *(base_ptr+i)=0; + reg.PC=address; + reg.NEXT_PC=reg.PC; + reg.PRIV=0x3; + reg.trap_state=0; + reg.icount=0; +} + +uint8_t *rv64gcv::get_regs_base_ptr() { + return reinterpret_cast(®); +} + +rv64gcv::phys_addr_t rv64gcv::virt2phys(const iss::addr_t &addr) { + return phys_addr_t(addr.access, addr.space, addr.val&traits::addr_mask); +} +// clang-format on diff --git a/src/iss/arch/rv64gcv.h b/src/iss/arch/rv64gcv.h new file mode 100644 index 0000000..76289bf --- /dev/null +++ b/src/iss/arch/rv64gcv.h @@ -0,0 +1,1431 @@ +/******************************************************************************* + * Copyright (C) 2024 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +#ifndef _RV64GCV_H_ +#define _RV64GCV_H_ +// clang-format off +#include +#include +#include +#include + +namespace iss { +namespace arch { + +struct rv64gcv: public arch_if { + + using reg_t = uint64_t; + + using virt_addr_t = iss::virt_addr_t; + + using phys_addr_t = iss::phys_addr_t; + + rv64gcv(); + ~rv64gcv(); + + void reset(uint64_t address=0) override; + + uint8_t* get_regs_base_ptr() override; + + inline bool should_stop() { return interrupt_sim; } + + inline uint64_t stop_code() { return interrupt_sim; } + + virtual phys_addr_t virt2phys(const iss::addr_t& addr); + + virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } + + +#pragma pack(push, 1) + struct RV64GCV_regs { + uint64_t X0 = 0; + uint64_t X1 = 0; + uint64_t X2 = 0; + uint64_t X3 = 0; + uint64_t X4 = 0; + uint64_t X5 = 0; + uint64_t X6 = 0; + uint64_t X7 = 0; + uint64_t X8 = 0; + uint64_t X9 = 0; + uint64_t X10 = 0; + uint64_t X11 = 0; + uint64_t X12 = 0; + uint64_t X13 = 0; + uint64_t X14 = 0; + uint64_t X15 = 0; + uint64_t X16 = 0; + uint64_t X17 = 0; + uint64_t X18 = 0; + uint64_t X19 = 0; + uint64_t X20 = 0; + uint64_t X21 = 0; + uint64_t X22 = 0; + uint64_t X23 = 0; + uint64_t X24 = 0; + uint64_t X25 = 0; + uint64_t X26 = 0; + uint64_t X27 = 0; + uint64_t X28 = 0; + uint64_t X29 = 0; + uint64_t X30 = 0; + uint64_t X31 = 0; + uint64_t PC = 0; + uint64_t NEXT_PC = 0; + uint8_t PRIV = 0; + uint64_t DPC = 0; + uint64_t F0 = 0; + uint64_t F1 = 0; + uint64_t F2 = 0; + uint64_t F3 = 0; + uint64_t F4 = 0; + uint64_t F5 = 0; + uint64_t F6 = 0; + uint64_t F7 = 0; + uint64_t F8 = 0; + uint64_t F9 = 0; + uint64_t F10 = 0; + uint64_t F11 = 0; + uint64_t F12 = 0; + uint64_t F13 = 0; + uint64_t F14 = 0; + uint64_t F15 = 0; + uint64_t F16 = 0; + uint64_t F17 = 0; + uint64_t F18 = 0; + uint64_t F19 = 0; + uint64_t F20 = 0; + uint64_t F21 = 0; + uint64_t F22 = 0; + uint64_t F23 = 0; + uint64_t F24 = 0; + uint64_t F25 = 0; + uint64_t F26 = 0; + uint64_t F27 = 0; + uint64_t F28 = 0; + uint64_t F29 = 0; + uint64_t F30 = 0; + uint64_t F31 = 0; + uint32_t FCSR = 0; + uint8_t V0[64] = {0}; + uint8_t V1[64] = {0}; + uint8_t V2[64] = {0}; + uint8_t V3[64] = {0}; + uint8_t V4[64] = {0}; + uint8_t V5[64] = {0}; + uint8_t V6[64] = {0}; + uint8_t V7[64] = {0}; + uint8_t V8[64] = {0}; + uint8_t V9[64] = {0}; + uint8_t V10[64] = {0}; + uint8_t V11[64] = {0}; + uint8_t V12[64] = {0}; + uint8_t V13[64] = {0}; + uint8_t V14[64] = {0}; + uint8_t V15[64] = {0}; + uint8_t V16[64] = {0}; + uint8_t V17[64] = {0}; + uint8_t V18[64] = {0}; + uint8_t V19[64] = {0}; + uint8_t V20[64] = {0}; + uint8_t V21[64] = {0}; + uint8_t V22[64] = {0}; + uint8_t V23[64] = {0}; + uint8_t V24[64] = {0}; + uint8_t V25[64] = {0}; + uint8_t V26[64] = {0}; + uint8_t V27[64] = {0}; + uint8_t V28[64] = {0}; + uint8_t V29[64] = {0}; + uint8_t V30[64] = {0}; + uint8_t V31[64] = {0}; + uint64_t vstart = 0; + uint64_t vxsat = 0; + uint64_t vxrm = 0; + uint64_t vl = 0; + uint64_t vtype = 0; + uint32_t trap_state = 0, pending_trap = 0; + uint64_t icount = 0; + uint64_t cycle = 0; + uint64_t instret = 0; + uint32_t instruction = 0; + uint32_t last_branch = 0; + } reg; +#pragma pack(pop) + std::array addr_mode; + + uint64_t interrupt_sim=0; + + uint32_t get_fcsr(){return reg.FCSR;} + void set_fcsr(uint32_t val){reg.FCSR = val;} + + uint64_t get_vstart(){return reg.vstart;} + void set_vstart(uint64_t val){reg.vstart = val;} + uint64_t get_vl(){return reg.vl;} + uint64_t get_vtype(){return reg.vtype;} + uint64_t get_vxsat(){return reg.vxsat;} + void set_vxsat(uint64_t val){reg.vxsat = val;} + uint64_t get_vxrm(){return reg.vxrm;} + void set_vxrm(uint64_t val){reg.vxrm = val;} + +}; + +struct rv64gcv; + +template <> struct traits { + + constexpr static char const* const core_type = "RV64GCV"; + + static constexpr std::array reg_names{ + {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "vstart", "vxsat", "vxrm", "vl", "vtype"}}; + + static constexpr std::array reg_aliases{ + {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "vstart", "vxsat", "vxrm", "vl", "vtype"}}; + + enum constants { + RV_CSR_FFLAGS=1ULL, RV_CSR_FRM=2ULL, RV_CSR_FCSR=3ULL, RV_CSR_UTVT=7ULL, + RV_CSR_VSTART=8ULL, RV_CSR_VXSAT=9ULL, RV_CSR_VXRM=10ULL, RV_CSR_VCSR=15ULL, + RV_CSR_SEED=21ULL, RV_CSR_UNXTI=69ULL, RV_CSR_UINTSTATUS=70ULL, RV_CSR_USCRATCHCSW=72ULL, + RV_CSR_USCRATCHCSWL=73ULL, RV_CSR_SSTATUS=256ULL, RV_CSR_SEDELEG=258ULL, RV_CSR_SIDELEG=259ULL, + RV_CSR_SIE=260ULL, RV_CSR_STVEC=261ULL, RV_CSR_SCOUNTEREN=262ULL, RV_CSR_STVT=263ULL, + RV_CSR_SENVCFG=266ULL, RV_CSR_SSTATEEN0=268ULL, RV_CSR_SSTATEEN1=269ULL, RV_CSR_SSTATEEN2=270ULL, + RV_CSR_SSTATEEN3=271ULL, RV_CSR_SSCRATCH=320ULL, RV_CSR_SEPC=321ULL, RV_CSR_SCAUSE=322ULL, + RV_CSR_STVAL=323ULL, RV_CSR_SIP=324ULL, RV_CSR_SNXTI=325ULL, RV_CSR_SINTSTATUS=326ULL, + RV_CSR_SSCRATCHCSW=328ULL, RV_CSR_SSCRATCHCSWL=329ULL, RV_CSR_STIMECMP=333ULL, RV_CSR_STIMECMPH=349ULL, + RV_CSR_SATP=384ULL, RV_CSR_VSSTATUS=512ULL, RV_CSR_VSIE=516ULL, RV_CSR_VSTVEC=517ULL, + RV_CSR_VSSCRATCH=576ULL, RV_CSR_VSEPC=577ULL, RV_CSR_VSCAUSE=578ULL, RV_CSR_VSTVAL=579ULL, + RV_CSR_VSIP=580ULL, RV_CSR_VSTIMECMP=589ULL, RV_CSR_VSTIMECMPH=605ULL, RV_CSR_VSATP=640ULL, + RV_CSR_MSTATUS=768ULL, RV_CSR_MISA=769ULL, RV_CSR_MEDELEG=770ULL, RV_CSR_MIDELEG=771ULL, + RV_CSR_MIE=772ULL, RV_CSR_MTVEC=773ULL, RV_CSR_MCOUNTEREN=774ULL, RV_CSR_MTVT=775ULL, + RV_CSR_MENVCFG=778ULL, RV_CSR_MSTATEEN0=780ULL, RV_CSR_MSTATEEN1=781ULL, RV_CSR_MSTATEEN2=782ULL, + RV_CSR_MSTATEEN3=783ULL, RV_CSR_MSTATUSH=784ULL, RV_CSR_MENVCFGH=794ULL, RV_CSR_MSTATEEN0H=796ULL, + RV_CSR_MSTATEEN1H=797ULL, RV_CSR_MSTATEEN2H=798ULL, RV_CSR_MSTATEEN3H=799ULL, RV_CSR_MCOUNTINHIBIT=800ULL, + RV_CSR_MHPMEVENT3=803ULL, RV_CSR_MHPMEVENT4=804ULL, RV_CSR_MHPMEVENT5=805ULL, RV_CSR_MHPMEVENT6=806ULL, + RV_CSR_MHPMEVENT7=807ULL, RV_CSR_MHPMEVENT8=808ULL, RV_CSR_MHPMEVENT9=809ULL, RV_CSR_MHPMEVENT10=810ULL, + RV_CSR_MHPMEVENT11=811ULL, RV_CSR_MHPMEVENT12=812ULL, RV_CSR_MHPMEVENT13=813ULL, RV_CSR_MHPMEVENT14=814ULL, + RV_CSR_MHPMEVENT15=815ULL, RV_CSR_MHPMEVENT16=816ULL, RV_CSR_MHPMEVENT17=817ULL, RV_CSR_MHPMEVENT18=818ULL, + RV_CSR_MHPMEVENT19=819ULL, RV_CSR_MHPMEVENT20=820ULL, RV_CSR_MHPMEVENT21=821ULL, RV_CSR_MHPMEVENT22=822ULL, + RV_CSR_MHPMEVENT23=823ULL, RV_CSR_MHPMEVENT24=824ULL, RV_CSR_MHPMEVENT25=825ULL, RV_CSR_MHPMEVENT26=826ULL, + RV_CSR_MHPMEVENT27=827ULL, RV_CSR_MHPMEVENT28=828ULL, RV_CSR_MHPMEVENT29=829ULL, RV_CSR_MHPMEVENT30=830ULL, + RV_CSR_MHPMEVENT31=831ULL, RV_CSR_MSCRATCH=832ULL, RV_CSR_MEPC=833ULL, RV_CSR_MCAUSE=834ULL, + RV_CSR_MTVAL=835ULL, RV_CSR_MIP=836ULL, RV_CSR_MNXTI=837ULL, RV_CSR_MINTSTATUS=838ULL, + RV_CSR_MSCRATCHCSW=840ULL, RV_CSR_MSCRATCHCSWL=841ULL, RV_CSR_MTINST=842ULL, RV_CSR_MTVAL2=843ULL, + RV_CSR_PMPCFG0=928ULL, RV_CSR_PMPCFG1=929ULL, RV_CSR_PMPCFG2=930ULL, RV_CSR_PMPCFG3=931ULL, + RV_CSR_PMPCFG4=932ULL, RV_CSR_PMPCFG5=933ULL, RV_CSR_PMPCFG6=934ULL, RV_CSR_PMPCFG7=935ULL, + RV_CSR_PMPCFG8=936ULL, RV_CSR_PMPCFG9=937ULL, RV_CSR_PMPCFG10=938ULL, RV_CSR_PMPCFG11=939ULL, + RV_CSR_PMPCFG12=940ULL, RV_CSR_PMPCFG13=941ULL, RV_CSR_PMPCFG14=942ULL, RV_CSR_PMPCFG15=943ULL, + RV_CSR_PMPADDR0=944ULL, RV_CSR_PMPADDR1=945ULL, RV_CSR_PMPADDR2=946ULL, RV_CSR_PMPADDR3=947ULL, + RV_CSR_PMPADDR4=948ULL, RV_CSR_PMPADDR5=949ULL, RV_CSR_PMPADDR6=950ULL, RV_CSR_PMPADDR7=951ULL, + RV_CSR_PMPADDR8=952ULL, RV_CSR_PMPADDR9=953ULL, RV_CSR_PMPADDR10=954ULL, RV_CSR_PMPADDR11=955ULL, + RV_CSR_PMPADDR12=956ULL, RV_CSR_PMPADDR13=957ULL, RV_CSR_PMPADDR14=958ULL, RV_CSR_PMPADDR15=959ULL, + RV_CSR_PMPADDR16=960ULL, RV_CSR_PMPADDR17=961ULL, RV_CSR_PMPADDR18=962ULL, RV_CSR_PMPADDR19=963ULL, + RV_CSR_PMPADDR20=964ULL, RV_CSR_PMPADDR21=965ULL, RV_CSR_PMPADDR22=966ULL, RV_CSR_PMPADDR23=967ULL, + RV_CSR_PMPADDR24=968ULL, RV_CSR_PMPADDR25=969ULL, RV_CSR_PMPADDR26=970ULL, RV_CSR_PMPADDR27=971ULL, + RV_CSR_PMPADDR28=972ULL, RV_CSR_PMPADDR29=973ULL, RV_CSR_PMPADDR30=974ULL, RV_CSR_PMPADDR31=975ULL, + RV_CSR_PMPADDR32=976ULL, RV_CSR_PMPADDR33=977ULL, RV_CSR_PMPADDR34=978ULL, RV_CSR_PMPADDR35=979ULL, + RV_CSR_PMPADDR36=980ULL, RV_CSR_PMPADDR37=981ULL, RV_CSR_PMPADDR38=982ULL, RV_CSR_PMPADDR39=983ULL, + RV_CSR_PMPADDR40=984ULL, RV_CSR_PMPADDR41=985ULL, RV_CSR_PMPADDR42=986ULL, RV_CSR_PMPADDR43=987ULL, + RV_CSR_PMPADDR44=988ULL, RV_CSR_PMPADDR45=989ULL, RV_CSR_PMPADDR46=990ULL, RV_CSR_PMPADDR47=991ULL, + RV_CSR_PMPADDR48=992ULL, RV_CSR_PMPADDR49=993ULL, RV_CSR_PMPADDR50=994ULL, RV_CSR_PMPADDR51=995ULL, + RV_CSR_PMPADDR52=996ULL, RV_CSR_PMPADDR53=997ULL, RV_CSR_PMPADDR54=998ULL, RV_CSR_PMPADDR55=999ULL, + RV_CSR_PMPADDR56=1000ULL, RV_CSR_PMPADDR57=1001ULL, RV_CSR_PMPADDR58=1002ULL, RV_CSR_PMPADDR59=1003ULL, + RV_CSR_PMPADDR60=1004ULL, RV_CSR_PMPADDR61=1005ULL, RV_CSR_PMPADDR62=1006ULL, RV_CSR_PMPADDR63=1007ULL, + RV_CSR_SCONTEXT=1448ULL, RV_CSR_HSTATUS=1536ULL, RV_CSR_HEDELEG=1538ULL, RV_CSR_HIDELEG=1539ULL, + RV_CSR_HIE=1540ULL, RV_CSR_HTIMEDELTA=1541ULL, RV_CSR_HCOUNTEREN=1542ULL, RV_CSR_HGEIE=1543ULL, + RV_CSR_HENVCFG=1546ULL, RV_CSR_HSTATEEN0=1548ULL, RV_CSR_HSTATEEN1=1549ULL, RV_CSR_HSTATEEN2=1550ULL, + RV_CSR_HSTATEEN3=1551ULL, RV_CSR_HTIMEDELTAH=1557ULL, RV_CSR_HENVCFGH=1562ULL, RV_CSR_HSTATEEN0H=1564ULL, + RV_CSR_HSTATEEN1H=1565ULL, RV_CSR_HSTATEEN2H=1566ULL, RV_CSR_HSTATEEN3H=1567ULL, RV_CSR_HTVAL=1603ULL, + RV_CSR_HIP=1604ULL, RV_CSR_HVIP=1605ULL, RV_CSR_HTINST=1610ULL, RV_CSR_HGATP=1664ULL, + RV_CSR_HCONTEXT=1704ULL, RV_CSR_MHPMEVENT3H=1827ULL, RV_CSR_MHPMEVENT4H=1828ULL, RV_CSR_MHPMEVENT5H=1829ULL, + RV_CSR_MHPMEVENT6H=1830ULL, RV_CSR_MHPMEVENT7H=1831ULL, RV_CSR_MHPMEVENT8H=1832ULL, RV_CSR_MHPMEVENT9H=1833ULL, + RV_CSR_MHPMEVENT10H=1834ULL, RV_CSR_MHPMEVENT11H=1835ULL, RV_CSR_MHPMEVENT12H=1836ULL, RV_CSR_MHPMEVENT13H=1837ULL, + RV_CSR_MHPMEVENT14H=1838ULL, RV_CSR_MHPMEVENT15H=1839ULL, RV_CSR_MHPMEVENT16H=1840ULL, RV_CSR_MHPMEVENT17H=1841ULL, + RV_CSR_MHPMEVENT18H=1842ULL, RV_CSR_MHPMEVENT19H=1843ULL, RV_CSR_MHPMEVENT20H=1844ULL, RV_CSR_MHPMEVENT21H=1845ULL, + RV_CSR_MHPMEVENT22H=1846ULL, RV_CSR_MHPMEVENT23H=1847ULL, RV_CSR_MHPMEVENT24H=1848ULL, RV_CSR_MHPMEVENT25H=1849ULL, + RV_CSR_MHPMEVENT26H=1850ULL, RV_CSR_MHPMEVENT27H=1851ULL, RV_CSR_MHPMEVENT28H=1852ULL, RV_CSR_MHPMEVENT29H=1853ULL, + RV_CSR_MHPMEVENT30H=1854ULL, RV_CSR_MHPMEVENT31H=1855ULL, RV_CSR_MSECCFG=1863ULL, RV_CSR_MSECCFGH=1879ULL, + RV_CSR_TSELECT=1952ULL, RV_CSR_TDATA1=1953ULL, RV_CSR_TDATA2=1954ULL, RV_CSR_TDATA3=1955ULL, + RV_CSR_TINFO=1956ULL, RV_CSR_TCONTROL=1957ULL, RV_CSR_MCONTEXT=1960ULL, RV_CSR_MSCONTEXT=1962ULL, + RV_CSR_DCSR=1968ULL, RV_CSR_DPC=1969ULL, RV_CSR_DSCRATCH0=1970ULL, RV_CSR_DSCRATCH1=1971ULL, + RV_CSR_MCYCLE=2816ULL, RV_CSR_MINSTRET=2818ULL, RV_CSR_MHPMCOUNTER3=2819ULL, RV_CSR_MHPMCOUNTER4=2820ULL, + RV_CSR_MHPMCOUNTER5=2821ULL, RV_CSR_MHPMCOUNTER6=2822ULL, RV_CSR_MHPMCOUNTER7=2823ULL, RV_CSR_MHPMCOUNTER8=2824ULL, + RV_CSR_MHPMCOUNTER9=2825ULL, RV_CSR_MHPMCOUNTER10=2826ULL, RV_CSR_MHPMCOUNTER11=2827ULL, RV_CSR_MHPMCOUNTER12=2828ULL, + RV_CSR_MHPMCOUNTER13=2829ULL, RV_CSR_MHPMCOUNTER14=2830ULL, RV_CSR_MHPMCOUNTER15=2831ULL, RV_CSR_MHPMCOUNTER16=2832ULL, + RV_CSR_MHPMCOUNTER17=2833ULL, RV_CSR_MHPMCOUNTER18=2834ULL, RV_CSR_MHPMCOUNTER19=2835ULL, RV_CSR_MHPMCOUNTER20=2836ULL, + RV_CSR_MHPMCOUNTER21=2837ULL, RV_CSR_MHPMCOUNTER22=2838ULL, RV_CSR_MHPMCOUNTER23=2839ULL, RV_CSR_MHPMCOUNTER24=2840ULL, + RV_CSR_MHPMCOUNTER25=2841ULL, RV_CSR_MHPMCOUNTER26=2842ULL, RV_CSR_MHPMCOUNTER27=2843ULL, RV_CSR_MHPMCOUNTER28=2844ULL, + RV_CSR_MHPMCOUNTER29=2845ULL, RV_CSR_MHPMCOUNTER30=2846ULL, RV_CSR_MHPMCOUNTER31=2847ULL, RV_CSR_MCYCLEH=2944ULL, + RV_CSR_MINSTRETH=2946ULL, RV_CSR_MHPMCOUNTER3H=2947ULL, RV_CSR_MHPMCOUNTER4H=2948ULL, RV_CSR_MHPMCOUNTER5H=2949ULL, + RV_CSR_MHPMCOUNTER6H=2950ULL, RV_CSR_MHPMCOUNTER7H=2951ULL, RV_CSR_MHPMCOUNTER8H=2952ULL, RV_CSR_MHPMCOUNTER9H=2953ULL, + RV_CSR_MHPMCOUNTER10H=2954ULL, RV_CSR_MHPMCOUNTER11H=2955ULL, RV_CSR_MHPMCOUNTER12H=2956ULL, RV_CSR_MHPMCOUNTER13H=2957ULL, + RV_CSR_MHPMCOUNTER14H=2958ULL, RV_CSR_MHPMCOUNTER15H=2959ULL, RV_CSR_MHPMCOUNTER16H=2960ULL, RV_CSR_MHPMCOUNTER17H=2961ULL, + RV_CSR_MHPMCOUNTER18H=2962ULL, RV_CSR_MHPMCOUNTER19H=2963ULL, RV_CSR_MHPMCOUNTER20H=2964ULL, RV_CSR_MHPMCOUNTER21H=2965ULL, + RV_CSR_MHPMCOUNTER22H=2966ULL, RV_CSR_MHPMCOUNTER23H=2967ULL, RV_CSR_MHPMCOUNTER24H=2968ULL, RV_CSR_MHPMCOUNTER25H=2969ULL, + RV_CSR_MHPMCOUNTER26H=2970ULL, RV_CSR_MHPMCOUNTER27H=2971ULL, RV_CSR_MHPMCOUNTER28H=2972ULL, RV_CSR_MHPMCOUNTER29H=2973ULL, + RV_CSR_MHPMCOUNTER30H=2974ULL, RV_CSR_MHPMCOUNTER31H=2975ULL, RV_CSR_CYCLE=3072ULL, RV_CSR_TIME=3073ULL, + RV_CSR_INSTRET=3074ULL, RV_CSR_HPMCOUNTER3=3075ULL, RV_CSR_HPMCOUNTER4=3076ULL, RV_CSR_HPMCOUNTER5=3077ULL, + RV_CSR_HPMCOUNTER6=3078ULL, RV_CSR_HPMCOUNTER7=3079ULL, RV_CSR_HPMCOUNTER8=3080ULL, RV_CSR_HPMCOUNTER9=3081ULL, + RV_CSR_HPMCOUNTER10=3082ULL, RV_CSR_HPMCOUNTER11=3083ULL, RV_CSR_HPMCOUNTER12=3084ULL, RV_CSR_HPMCOUNTER13=3085ULL, + RV_CSR_HPMCOUNTER14=3086ULL, RV_CSR_HPMCOUNTER15=3087ULL, RV_CSR_HPMCOUNTER16=3088ULL, RV_CSR_HPMCOUNTER17=3089ULL, + RV_CSR_HPMCOUNTER18=3090ULL, RV_CSR_HPMCOUNTER19=3091ULL, RV_CSR_HPMCOUNTER20=3092ULL, RV_CSR_HPMCOUNTER21=3093ULL, + RV_CSR_HPMCOUNTER22=3094ULL, RV_CSR_HPMCOUNTER23=3095ULL, RV_CSR_HPMCOUNTER24=3096ULL, RV_CSR_HPMCOUNTER25=3097ULL, + RV_CSR_HPMCOUNTER26=3098ULL, RV_CSR_HPMCOUNTER27=3099ULL, RV_CSR_HPMCOUNTER28=3100ULL, RV_CSR_HPMCOUNTER29=3101ULL, + RV_CSR_HPMCOUNTER30=3102ULL, RV_CSR_HPMCOUNTER31=3103ULL, RV_CSR_VL=3104ULL, RV_CSR_VTYPE=3105ULL, + RV_CSR_VLENB=3106ULL, RV_CSR_CYCLEH=3200ULL, RV_CSR_TIMEH=3201ULL, RV_CSR_INSTRETH=3202ULL, + RV_CSR_HPMCOUNTER3H=3203ULL, RV_CSR_HPMCOUNTER4H=3204ULL, RV_CSR_HPMCOUNTER5H=3205ULL, RV_CSR_HPMCOUNTER6H=3206ULL, + RV_CSR_HPMCOUNTER7H=3207ULL, RV_CSR_HPMCOUNTER8H=3208ULL, RV_CSR_HPMCOUNTER9H=3209ULL, RV_CSR_HPMCOUNTER10H=3210ULL, + RV_CSR_HPMCOUNTER11H=3211ULL, RV_CSR_HPMCOUNTER12H=3212ULL, RV_CSR_HPMCOUNTER13H=3213ULL, RV_CSR_HPMCOUNTER14H=3214ULL, + RV_CSR_HPMCOUNTER15H=3215ULL, RV_CSR_HPMCOUNTER16H=3216ULL, RV_CSR_HPMCOUNTER17H=3217ULL, RV_CSR_HPMCOUNTER18H=3218ULL, + RV_CSR_HPMCOUNTER19H=3219ULL, RV_CSR_HPMCOUNTER20H=3220ULL, RV_CSR_HPMCOUNTER21H=3221ULL, RV_CSR_HPMCOUNTER22H=3222ULL, + RV_CSR_HPMCOUNTER23H=3223ULL, RV_CSR_HPMCOUNTER24H=3224ULL, RV_CSR_HPMCOUNTER25H=3225ULL, RV_CSR_HPMCOUNTER26H=3226ULL, + RV_CSR_HPMCOUNTER27H=3227ULL, RV_CSR_HPMCOUNTER28H=3228ULL, RV_CSR_HPMCOUNTER29H=3229ULL, RV_CSR_HPMCOUNTER30H=3230ULL, + RV_CSR_HPMCOUNTER31H=3231ULL, RV_CSR_SCOUNTOVF=3488ULL, RV_CSR_HGEIP=3602ULL, RV_CSR_MVENDORID=3857ULL, + RV_CSR_MARCHID=3858ULL, RV_CSR_MIMPID=3859ULL, RV_CSR_MHARTID=3860ULL, RV_CSR_MCONFIGPTR=3861ULL, + RV_CAUSE_MISALIGNED_FETCH=0ULL, RV_CAUSE_FETCH_ACCESS=1ULL, RV_CAUSE_ILLEGAL_INSTRUCTION=2ULL, RV_CAUSE_BREAKPOINT=3ULL, + RV_CAUSE_MISALIGNED_LOAD=4ULL, RV_CAUSE_LOAD_ACCESS=5ULL, RV_CAUSE_MISALIGNED_STORE=6ULL, RV_CAUSE_STORE_ACCESS=7ULL, + RV_CAUSE_USER_ECALL=8ULL, RV_CAUSE_SUPERVISOR_ECALL=9ULL, RV_CAUSE_VIRTUAL_SUPERVISOR_ECALL=10ULL, RV_CAUSE_MACHINE_ECALL=11ULL, + RV_CAUSE_FETCH_PAGE_FAULT=12ULL, RV_CAUSE_LOAD_PAGE_FAULT=13ULL, RV_CAUSE_STORE_PAGE_FAULT=15ULL, RV_CAUSE_FETCH_GUEST_PAGE_FAULT=20ULL, + RV_CAUSE_LOAD_GUEST_PAGE_FAULT=21ULL, RV_CAUSE_VIRTUAL_INSTRUCTION=22ULL, RV_CAUSE_STORE_GUEST_PAGE_FAULT=23ULL, RV_MSTATUS_UIE=1ULL, + RV_MSTATUS_SIE=2ULL, RV_MSTATUS_HIE=4ULL, RV_MSTATUS_MIE=8ULL, RV_MSTATUS_UPIE=16ULL, + RV_MSTATUS_SPIE=32ULL, RV_MSTATUS_UBE=64ULL, RV_MSTATUS_MPIE=128ULL, RV_MSTATUS_SPP=256ULL, + RV_MSTATUS_VS=1536ULL, RV_MSTATUS_MPP=6144ULL, RV_MSTATUS_FS=24576ULL, RV_MSTATUS_XS=98304ULL, + RV_MSTATUS_MPRV=131072ULL, RV_MSTATUS_SUM=262144ULL, RV_MSTATUS_MXR=524288ULL, RV_MSTATUS_TVM=1048576ULL, + RV_MSTATUS_TW=2097152ULL, RV_MSTATUS_TSR=4194304ULL, RV_MSTATUS32_SD=2147483648ULL, RV_MSTATUS_UXL=12884901888ULL, + RV_MSTATUS_SXL=51539607552ULL, RV_MSTATUS_SBE=68719476736ULL, RV_MSTATUS_MBE=137438953472ULL, RV_MSTATUS_GVA=274877906944ULL, + RV_MSTATUS_MPV=549755813888ULL, RV_MSTATUS64_SD=9223372036854775808ULL, RV_PRV_U=0ULL, RV_PRV_S=1ULL, + RV_PRV_H=2ULL, RV_PRV_M=3ULL, RV_IRQ_U_SOFT=0ULL, RV_IRQ_S_SOFT=1ULL, + RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL, + RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL, + RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL, + RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL, + RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL, + RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL, + RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=64ULL, + FLEN=64ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, + fencei=1ULL, fencevma=2ULL, CSR_SIZE=4096ULL, MUL_LEN=128ULL, + FFLAG_MASK=31ULL, VLEN=512ULL, ELEN=64ULL, EEW_MAX=64ULL, + FP_SEW_MIN=32ULL, FP_SEW_MAX=64ULL, VSTART_ADDR=8ULL, VXSAT_ADDR=9ULL, + VXRM_ADDR=10ULL, VCSR_ADDR=15ULL, VL_ADDR=3104ULL, VTYPE_ADDR=3105ULL, + VLENB_ADDR=3106ULL, MISA_VAL=9223372036854780205ULL, MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL + }; + + constexpr static unsigned FP_REGS_SIZE = 64; + constexpr static unsigned V_REGS_SIZE = 512; + + + enum reg_e { + X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31, FCSR, V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31, vstart, vxsat, vxrm, vl, vtype, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH + }; + + using reg_t = uint64_t; + + using addr_t = uint64_t; + + using code_word_t = uint64_t; //TODO: check removal + + using virt_addr_t = iss::virt_addr_t; + + using phys_addr_t = iss::phys_addr_t; + + static constexpr std::array reg_bit_widths{{ + sizeof(rv64gcv::RV64GCV_regs::X0) * 8, + sizeof(rv64gcv::RV64GCV_regs::X1) * 8, + sizeof(rv64gcv::RV64GCV_regs::X2) * 8, + sizeof(rv64gcv::RV64GCV_regs::X3) * 8, + sizeof(rv64gcv::RV64GCV_regs::X4) * 8, + sizeof(rv64gcv::RV64GCV_regs::X5) * 8, + sizeof(rv64gcv::RV64GCV_regs::X6) * 8, + sizeof(rv64gcv::RV64GCV_regs::X7) * 8, + sizeof(rv64gcv::RV64GCV_regs::X8) * 8, + sizeof(rv64gcv::RV64GCV_regs::X9) * 8, + sizeof(rv64gcv::RV64GCV_regs::X10) * 8, + sizeof(rv64gcv::RV64GCV_regs::X11) * 8, + sizeof(rv64gcv::RV64GCV_regs::X12) * 8, + sizeof(rv64gcv::RV64GCV_regs::X13) * 8, + sizeof(rv64gcv::RV64GCV_regs::X14) * 8, + sizeof(rv64gcv::RV64GCV_regs::X15) * 8, + sizeof(rv64gcv::RV64GCV_regs::X16) * 8, + sizeof(rv64gcv::RV64GCV_regs::X17) * 8, + sizeof(rv64gcv::RV64GCV_regs::X18) * 8, + sizeof(rv64gcv::RV64GCV_regs::X19) * 8, + sizeof(rv64gcv::RV64GCV_regs::X20) * 8, + sizeof(rv64gcv::RV64GCV_regs::X21) * 8, + sizeof(rv64gcv::RV64GCV_regs::X22) * 8, + sizeof(rv64gcv::RV64GCV_regs::X23) * 8, + sizeof(rv64gcv::RV64GCV_regs::X24) * 8, + sizeof(rv64gcv::RV64GCV_regs::X25) * 8, + sizeof(rv64gcv::RV64GCV_regs::X26) * 8, + sizeof(rv64gcv::RV64GCV_regs::X27) * 8, + sizeof(rv64gcv::RV64GCV_regs::X28) * 8, + sizeof(rv64gcv::RV64GCV_regs::X29) * 8, + sizeof(rv64gcv::RV64GCV_regs::X30) * 8, + sizeof(rv64gcv::RV64GCV_regs::X31) * 8, + sizeof(rv64gcv::RV64GCV_regs::PC) * 8, + sizeof(rv64gcv::RV64GCV_regs::NEXT_PC) * 8, + sizeof(rv64gcv::RV64GCV_regs::PRIV) * 8, + sizeof(rv64gcv::RV64GCV_regs::DPC) * 8, + sizeof(rv64gcv::RV64GCV_regs::F0) * 8, + sizeof(rv64gcv::RV64GCV_regs::F1) * 8, + sizeof(rv64gcv::RV64GCV_regs::F2) * 8, + sizeof(rv64gcv::RV64GCV_regs::F3) * 8, + sizeof(rv64gcv::RV64GCV_regs::F4) * 8, + sizeof(rv64gcv::RV64GCV_regs::F5) * 8, + sizeof(rv64gcv::RV64GCV_regs::F6) * 8, + sizeof(rv64gcv::RV64GCV_regs::F7) * 8, + sizeof(rv64gcv::RV64GCV_regs::F8) * 8, + sizeof(rv64gcv::RV64GCV_regs::F9) * 8, + sizeof(rv64gcv::RV64GCV_regs::F10) * 8, + sizeof(rv64gcv::RV64GCV_regs::F11) * 8, + sizeof(rv64gcv::RV64GCV_regs::F12) * 8, + sizeof(rv64gcv::RV64GCV_regs::F13) * 8, + sizeof(rv64gcv::RV64GCV_regs::F14) * 8, + sizeof(rv64gcv::RV64GCV_regs::F15) * 8, + sizeof(rv64gcv::RV64GCV_regs::F16) * 8, + sizeof(rv64gcv::RV64GCV_regs::F17) * 8, + sizeof(rv64gcv::RV64GCV_regs::F18) * 8, + sizeof(rv64gcv::RV64GCV_regs::F19) * 8, + sizeof(rv64gcv::RV64GCV_regs::F20) * 8, + sizeof(rv64gcv::RV64GCV_regs::F21) * 8, + sizeof(rv64gcv::RV64GCV_regs::F22) * 8, + sizeof(rv64gcv::RV64GCV_regs::F23) * 8, + sizeof(rv64gcv::RV64GCV_regs::F24) * 8, + sizeof(rv64gcv::RV64GCV_regs::F25) * 8, + sizeof(rv64gcv::RV64GCV_regs::F26) * 8, + sizeof(rv64gcv::RV64GCV_regs::F27) * 8, + sizeof(rv64gcv::RV64GCV_regs::F28) * 8, + sizeof(rv64gcv::RV64GCV_regs::F29) * 8, + sizeof(rv64gcv::RV64GCV_regs::F30) * 8, + sizeof(rv64gcv::RV64GCV_regs::F31) * 8, + sizeof(rv64gcv::RV64GCV_regs::FCSR) * 8, + sizeof(rv64gcv::RV64GCV_regs::V0) * 8, + sizeof(rv64gcv::RV64GCV_regs::V1) * 8, + sizeof(rv64gcv::RV64GCV_regs::V2) * 8, + sizeof(rv64gcv::RV64GCV_regs::V3) * 8, + sizeof(rv64gcv::RV64GCV_regs::V4) * 8, + sizeof(rv64gcv::RV64GCV_regs::V5) * 8, + sizeof(rv64gcv::RV64GCV_regs::V6) * 8, + sizeof(rv64gcv::RV64GCV_regs::V7) * 8, + sizeof(rv64gcv::RV64GCV_regs::V8) * 8, + sizeof(rv64gcv::RV64GCV_regs::V9) * 8, + sizeof(rv64gcv::RV64GCV_regs::V10) * 8, + sizeof(rv64gcv::RV64GCV_regs::V11) * 8, + sizeof(rv64gcv::RV64GCV_regs::V12) * 8, + sizeof(rv64gcv::RV64GCV_regs::V13) * 8, + sizeof(rv64gcv::RV64GCV_regs::V14) * 8, + sizeof(rv64gcv::RV64GCV_regs::V15) * 8, + sizeof(rv64gcv::RV64GCV_regs::V16) * 8, + sizeof(rv64gcv::RV64GCV_regs::V17) * 8, + sizeof(rv64gcv::RV64GCV_regs::V18) * 8, + sizeof(rv64gcv::RV64GCV_regs::V19) * 8, + sizeof(rv64gcv::RV64GCV_regs::V20) * 8, + sizeof(rv64gcv::RV64GCV_regs::V21) * 8, + sizeof(rv64gcv::RV64GCV_regs::V22) * 8, + sizeof(rv64gcv::RV64GCV_regs::V23) * 8, + sizeof(rv64gcv::RV64GCV_regs::V24) * 8, + sizeof(rv64gcv::RV64GCV_regs::V25) * 8, + sizeof(rv64gcv::RV64GCV_regs::V26) * 8, + sizeof(rv64gcv::RV64GCV_regs::V27) * 8, + sizeof(rv64gcv::RV64GCV_regs::V28) * 8, + sizeof(rv64gcv::RV64GCV_regs::V29) * 8, + sizeof(rv64gcv::RV64GCV_regs::V30) * 8, + sizeof(rv64gcv::RV64GCV_regs::V31) * 8, + sizeof(rv64gcv::RV64GCV_regs::vstart) * 8, + sizeof(rv64gcv::RV64GCV_regs::vxsat) * 8, + sizeof(rv64gcv::RV64GCV_regs::vxrm) * 8, + sizeof(rv64gcv::RV64GCV_regs::vl) * 8, + sizeof(rv64gcv::RV64GCV_regs::vtype) * 8, + sizeof(rv64gcv::RV64GCV_regs::trap_state) * 8, + sizeof(rv64gcv::RV64GCV_regs::pending_trap) * 8, + sizeof(rv64gcv::RV64GCV_regs::icount) * 8, + sizeof(rv64gcv::RV64GCV_regs::cycle) * 8, + sizeof(rv64gcv::RV64GCV_regs::instret) * 8, + sizeof(rv64gcv::RV64GCV_regs::instruction) * 8, + sizeof(rv64gcv::RV64GCV_regs::last_branch) * 8, + }}; + + static constexpr std::array reg_byte_offsets{{ + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X0), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X1), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X2), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X3), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X4), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X5), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X6), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X7), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X8), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X9), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X10), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X11), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X12), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X13), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X14), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X15), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X16), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X17), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X18), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X19), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X20), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X21), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X22), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X23), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X24), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X25), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X26), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X27), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X28), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X29), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X30), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::X31), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::PC), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::NEXT_PC), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::PRIV), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::DPC), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F0), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F1), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F2), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F3), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F4), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F5), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F6), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F7), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F8), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F9), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F10), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F11), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F12), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F13), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F14), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F15), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F16), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F17), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F18), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F19), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F20), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F21), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F22), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F23), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F24), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F25), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F26), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F27), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F28), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F29), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F30), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::F31), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::FCSR), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V0), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V1), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V2), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V3), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V4), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V5), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V6), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V7), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V8), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V9), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V10), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V11), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V12), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V13), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V14), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V15), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V16), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V17), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V18), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V19), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V20), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V21), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V22), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V23), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V24), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V25), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V26), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V27), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V28), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V29), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V30), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::V31), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::vstart), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::vxsat), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::vxrm), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::vl), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::vtype), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::trap_state), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::pending_trap), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::icount), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::cycle), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::instret), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::instruction), + offsetof(rv64gcv::RV64GCV_regs, rv64gcv::RV64GCV_regs::last_branch), + }}; + + static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); + + enum sreg_flag_e { FLAGS }; + + enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM }; + + enum class opcode_e { + LUI = 0, + AUIPC = 1, + JAL = 2, + JALR = 3, + BEQ = 4, + BNE = 5, + BLT = 6, + BGE = 7, + BLTU = 8, + BGEU = 9, + LB = 10, + LH = 11, + LW = 12, + LBU = 13, + LHU = 14, + SB = 15, + SH = 16, + SW = 17, + ADDI = 18, + SLTI = 19, + SLTIU = 20, + XORI = 21, + ORI = 22, + ANDI = 23, + SLLI = 24, + SRLI = 25, + SRAI = 26, + ADD = 27, + SUB = 28, + SLL = 29, + SLT = 30, + SLTU = 31, + XOR = 32, + SRL = 33, + SRA = 34, + OR = 35, + AND = 36, + FENCE = 37, + ECALL = 38, + EBREAK = 39, + MRET = 40, + WFI = 41, + LWU = 42, + LD = 43, + SD = 44, + ADDIW = 45, + SLLIW = 46, + SRLIW = 47, + SRAIW = 48, + ADDW = 49, + SUBW = 50, + SLLW = 51, + SRLW = 52, + SRAW = 53, + CSRRW = 54, + CSRRS = 55, + CSRRC = 56, + CSRRWI = 57, + CSRRSI = 58, + CSRRCI = 59, + FENCE_I = 60, + MUL = 61, + MULH = 62, + MULHSU = 63, + MULHU = 64, + DIV = 65, + DIVU = 66, + REM = 67, + REMU = 68, + MULW = 69, + DIVW = 70, + DIVUW = 71, + REMW = 72, + REMUW = 73, + LRW = 74, + SCW = 75, + AMOSWAPW = 76, + AMOADDW = 77, + AMOXORW = 78, + AMOANDW = 79, + AMOORW = 80, + AMOMINW = 81, + AMOMAXW = 82, + AMOMINUW = 83, + AMOMAXUW = 84, + LRD = 85, + SCD = 86, + AMOSWAPD = 87, + AMOADDD = 88, + AMOXORD = 89, + AMOANDD = 90, + AMOORD = 91, + AMOMIND = 92, + AMOMAXD = 93, + AMOMINUD = 94, + AMOMAXUD = 95, + C__ADDI4SPN = 96, + C__LW = 97, + C__LD = 98, + C__SW = 99, + C__SD = 100, + C__ADDI = 101, + C__NOP = 102, + C__ADDIW = 103, + C__LI = 104, + C__LUI = 105, + C__ADDI16SP = 106, + __reserved_clui = 107, + C__SRLI = 108, + C__SRAI = 109, + C__ANDI = 110, + C__SUB = 111, + C__XOR = 112, + C__OR = 113, + C__AND = 114, + C__SUBW = 115, + C__ADDW = 116, + C__J = 117, + C__BEQZ = 118, + C__BNEZ = 119, + C__SLLI = 120, + C__LWSP = 121, + C__LDSP = 122, + C__MV = 123, + C__JR = 124, + __reserved_cmv = 125, + C__ADD = 126, + C__JALR = 127, + C__EBREAK = 128, + C__SWSP = 129, + C__SDSP = 130, + DII = 131, + FLW = 132, + FSW = 133, + FADD__S = 134, + FSUB__S = 135, + FMUL__S = 136, + FDIV__S = 137, + FMIN__S = 138, + FMAX__S = 139, + FSQRT__S = 140, + FMADD__S = 141, + FMSUB__S = 142, + FNMADD__S = 143, + FNMSUB__S = 144, + FCVT__W__S = 145, + FCVT__WU__S = 146, + FCVT__L__S = 147, + FCVT__LU__S = 148, + FCVT__S__W = 149, + FCVT__S__WU = 150, + FCVT__S__L = 151, + FCVT__S__LU = 152, + FSGNJ__S = 153, + FSGNJN__S = 154, + FSGNJX__S = 155, + FMV__X__W = 156, + FMV__W__X = 157, + FEQ__S = 158, + FLT__S = 159, + FLE__S = 160, + FCLASS__S = 161, + FLD = 162, + FSD = 163, + FADD__D = 164, + FSUB__D = 165, + FMUL__D = 166, + FDIV__D = 167, + FMIN__D = 168, + FMAX__D = 169, + FSQRT__D = 170, + FMADD__D = 171, + FMSUB__D = 172, + FNMADD__D = 173, + FNMSUB__D = 174, + FCVT__W__D = 175, + FCVT__WU__D = 176, + FCVT__L__D = 177, + FCVT__LU__D = 178, + FCVT__D__W = 179, + FCVT__D__WU = 180, + FCVT__D__L = 181, + FCVT__D__LU = 182, + FCVT__S__D = 183, + FCVT__D__S = 184, + FSGNJ__D = 185, + FSGNJN__D = 186, + FSGNJX__D = 187, + FMV__X__D = 188, + FMV__D__X = 189, + FEQ__D = 190, + FLT__D = 191, + FLE__D = 192, + FCLASS__D = 193, + C__FLD = 194, + C__FSD = 195, + C__FLDSP = 196, + C__FSDSP = 197, + SFENCE__VMA = 198, + SRET = 199, + VSETVLI = 200, + VSETIVLI = 201, + VSETVL = 202, + VLE8__V = 203, + VLE16__V = 204, + VLE32__V = 205, + VLE64__V = 206, + VLSEG2E8__V = 207, + VLSEG2E16__V = 208, + VLSEG2E32__V = 209, + VLSEG2E64__V = 210, + VLSEG3E8__V = 211, + VLSEG3E16__V = 212, + VLSEG3E32__V = 213, + VLSEG3E64__V = 214, + VLSEG4E8__V = 215, + VLSEG4E16__V = 216, + VLSEG4E32__V = 217, + VLSEG4E64__V = 218, + VLSEG5E8__V = 219, + VLSEG5E16__V = 220, + VLSEG5E32__V = 221, + VLSEG5E64__V = 222, + VLSEG6E8__V = 223, + VLSEG6E16__V = 224, + VLSEG6E32__V = 225, + VLSEG6E64__V = 226, + VLSEG7E8__V = 227, + VLSEG7E16__V = 228, + VLSEG7E32__V = 229, + VLSEG7E64__V = 230, + VLSEG8E8__V = 231, + VLSEG8E16__V = 232, + VLSEG8E32__V = 233, + VLSEG8E64__V = 234, + VSE8__V = 235, + VSE16__V = 236, + VSE32__V = 237, + VSE64__V = 238, + VSSEG2E8__V = 239, + VSSEG2E16__V = 240, + VSSEG2E32__V = 241, + VSSEG2E64__V = 242, + VSSEG3E8__V = 243, + VSSEG3E16__V = 244, + VSSEG3E32__V = 245, + VSSEG3E64__V = 246, + VSSEG4E8__V = 247, + VSSEG4E16__V = 248, + VSSEG4E32__V = 249, + VSSEG4E64__V = 250, + VSSEG5E8__V = 251, + VSSEG5E16__V = 252, + VSSEG5E32__V = 253, + VSSEG5E64__V = 254, + VSSEG6E8__V = 255, + VSSEG6E16__V = 256, + VSSEG6E32__V = 257, + VSSEG6E64__V = 258, + VSSEG7E8__V = 259, + VSSEG7E16__V = 260, + VSSEG7E32__V = 261, + VSSEG7E64__V = 262, + VSSEG8E8__V = 263, + VSSEG8E16__V = 264, + VSSEG8E32__V = 265, + VSSEG8E64__V = 266, + VLSE8__V = 267, + VLSE16__V = 268, + VLSE32__V = 269, + VLSE64__V = 270, + VLSSEG2E8__V = 271, + VLSSEG2E16__V = 272, + VLSSEG2E32__V = 273, + VLSSEG2E64__V = 274, + VLSSEG3E8__V = 275, + VLSSEG3E16__V = 276, + VLSSEG3E32__V = 277, + VLSSEG3E64__V = 278, + VLSSEG4E8__V = 279, + VLSSEG4E16__V = 280, + VLSSEG4E32__V = 281, + VLSSEG4E64__V = 282, + VLSSEG5E8__V = 283, + VLSSEG5E16__V = 284, + VLSSEG5E32__V = 285, + VLSSEG5E64__V = 286, + VLSSEG6E8__V = 287, + VLSSEG6E16__V = 288, + VLSSEG6E32__V = 289, + VLSSEG6E64__V = 290, + VLSSEG7E8__V = 291, + VLSSEG7E16__V = 292, + VLSSEG7E32__V = 293, + VLSSEG7E64__V = 294, + VLSSEG8E8__V = 295, + VLSSEG8E16__V = 296, + VLSSEG8E32__V = 297, + VLSSEG8E64__V = 298, + VSSE8__V = 299, + VSSE16__V = 300, + VSSE32__V = 301, + VSSE64__V = 302, + VSSSEG2E8__V = 303, + VSSSEG2E16__V = 304, + VSSSEG2E32__V = 305, + VSSSEG2E64__V = 306, + VSSSEG3E8__V = 307, + VSSSEG3E16__V = 308, + VSSSEG3E32__V = 309, + VSSSEG3E64__V = 310, + VSSSEG4E8__V = 311, + VSSSEG4E16__V = 312, + VSSSEG4E32__V = 313, + VSSSEG4E64__V = 314, + VSSSEG5E8__V = 315, + VSSSEG5E16__V = 316, + VSSSEG5E32__V = 317, + VSSSEG5E64__V = 318, + VSSSEG6E8__V = 319, + VSSSEG6E16__V = 320, + VSSSEG6E32__V = 321, + VSSSEG6E64__V = 322, + VSSSEG7E8__V = 323, + VSSSEG7E16__V = 324, + VSSSEG7E32__V = 325, + VSSSEG7E64__V = 326, + VSSSEG8E8__V = 327, + VSSSEG8E16__V = 328, + VSSSEG8E32__V = 329, + VSSSEG8E64__V = 330, + VLE8FF__V = 331, + VLE16FF__V = 332, + VLE32FF__V = 333, + VLE64FF__V = 334, + VLSEG2E8FF__V = 335, + VLSEG2E16FF__V = 336, + VLSEG2E32FF__V = 337, + VLSEG2E64FF__V = 338, + VLSEG3E8FF__V = 339, + VLSEG3E16FF__V = 340, + VLSEG3E32FF__V = 341, + VLSEG3E64FF__V = 342, + VLSEG4E8FF__V = 343, + VLSEG4E16FF__V = 344, + VLSEG4E32FF__V = 345, + VLSEG4E64FF__V = 346, + VLSEG5E8FF__V = 347, + VLSEG5E16FF__V = 348, + VLSEG5E32FF__V = 349, + VLSEG5E64FF__V = 350, + VLSEG6E8FF__V = 351, + VLSEG6E16FF__V = 352, + VLSEG6E32FF__V = 353, + VLSEG6E64FF__V = 354, + VLSEG7E8FF__V = 355, + VLSEG7E16FF__V = 356, + VLSEG7E32FF__V = 357, + VLSEG7E64FF__V = 358, + VLSEG8E8FF__V = 359, + VLSEG8E16FF__V = 360, + VLSEG8E32FF__V = 361, + VLSEG8E64FF__V = 362, + VSM__V = 363, + VLM__V = 364, + VL1RE8__V = 365, + VL1RE16__V = 366, + VL1RE32__V = 367, + VL1RE64__V = 368, + VL2RE8__V = 369, + VL2RE16__V = 370, + VL2RE32__V = 371, + VL2RE64__V = 372, + VL4RE8__V = 373, + VL4RE16__V = 374, + VL4RE32__V = 375, + VL4RE64__V = 376, + VL8RE8__V = 377, + VL8RE16__V = 378, + VL8RE32__V = 379, + VL8RE64__V = 380, + VS1RE64__V = 381, + VS2RE64__V = 382, + VS4RE64__V = 383, + VS8RE64__V = 384, + VLOXEI8__V = 385, + VLOXEI16__V = 386, + VLOXEI32__V = 387, + VLOXEI64__V = 388, + VLOXSEG2EI8__V = 389, + VLOXSEG2EI16__V = 390, + VLOXSEG2EI32__V = 391, + VLOXSEG2EI64__V = 392, + VLOXSEG3EI8__V = 393, + VLOXSEG3EI16__V = 394, + VLOXSEG3EI32__V = 395, + VLOXSEG3EI64__V = 396, + VLOXSEG4EI8__V = 397, + VLOXSEG4EI16__V = 398, + VLOXSEG4EI32__V = 399, + VLOXSEG4EI64__V = 400, + VLOXSEG5EI8__V = 401, + VLOXSEG5EI16__V = 402, + VLOXSEG5EI32__V = 403, + VLOXSEG5EI64__V = 404, + VLOXSEG6EI8__V = 405, + VLOXSEG6EI16__V = 406, + VLOXSEG6EI32__V = 407, + VLOXSEG6EI64__V = 408, + VLOXSEG7EI8__V = 409, + VLOXSEG7EI16__V = 410, + VLOXSEG7EI32__V = 411, + VLOXSEG7EI64__V = 412, + VLOXSEG8EI8__V = 413, + VLOXSEG8EI16__V = 414, + VLOXSEG8EI32__V = 415, + VLOXSEG8EI64__V = 416, + VSOXEI8__V = 417, + VSOXEI16__V = 418, + VSOXEI32__V = 419, + VSOXEI64__V = 420, + VSOXSEG2EI8__V = 421, + VSOXSEG2EI16__V = 422, + VSOXSEG2EI32__V = 423, + VSOXSEG2EI64__V = 424, + VSOXSEG3EI8__V = 425, + VSOXSEG3EI16__V = 426, + VSOXSEG3EI32__V = 427, + VSOXSEG3EI64__V = 428, + VSOXSEG4EI8__V = 429, + VSOXSEG4EI16__V = 430, + VSOXSEG4EI32__V = 431, + VSOXSEG4EI64__V = 432, + VSOXSEG5EI8__V = 433, + VSOXSEG5EI16__V = 434, + VSOXSEG5EI32__V = 435, + VSOXSEG5EI64__V = 436, + VSOXSEG6EI8__V = 437, + VSOXSEG6EI16__V = 438, + VSOXSEG6EI32__V = 439, + VSOXSEG6EI64__V = 440, + VSOXSEG7EI8__V = 441, + VSOXSEG7EI16__V = 442, + VSOXSEG7EI32__V = 443, + VSOXSEG7EI64__V = 444, + VSOXSEG8EI8__V = 445, + VSOXSEG8EI16__V = 446, + VSOXSEG8EI32__V = 447, + VSOXSEG8EI64__V = 448, + VLUXEI8__V = 449, + VLUXEI16__V = 450, + VLUXEI32__V = 451, + VLUXEI64__V = 452, + VLUXSEG2EI8__V = 453, + VLUXSEG2EI16__V = 454, + VLUXSEG2EI32__V = 455, + VLUXSEG2EI64__V = 456, + VLUXSEG3EI8__V = 457, + VLUXSEG3EI16__V = 458, + VLUXSEG3EI32__V = 459, + VLUXSEG3EI64__V = 460, + VLUXSEG4EI8__V = 461, + VLUXSEG4EI16__V = 462, + VLUXSEG4EI32__V = 463, + VLUXSEG4EI64__V = 464, + VLUXSEG5EI8__V = 465, + VLUXSEG5EI16__V = 466, + VLUXSEG5EI32__V = 467, + VLUXSEG5EI64__V = 468, + VLUXSEG6EI8__V = 469, + VLUXSEG6EI16__V = 470, + VLUXSEG6EI32__V = 471, + VLUXSEG6EI64__V = 472, + VLUXSEG7EI8__V = 473, + VLUXSEG7EI16__V = 474, + VLUXSEG7EI32__V = 475, + VLUXSEG7EI64__V = 476, + VLUXSEG8EI8__V = 477, + VLUXSEG8EI16__V = 478, + VLUXSEG8EI32__V = 479, + VLUXSEG8EI64__V = 480, + VSUXEI8__V = 481, + VSUXEI16__V = 482, + VSUXEI32__V = 483, + VSUXEI64__V = 484, + VSUXSEG2EI8__V = 485, + VSUXSEG2EI16__V = 486, + VSUXSEG2EI32__V = 487, + VSUXSEG2EI64__V = 488, + VSUXSEG3EI8__V = 489, + VSUXSEG3EI16__V = 490, + VSUXSEG3EI32__V = 491, + VSUXSEG3EI64__V = 492, + VSUXSEG4EI8__V = 493, + VSUXSEG4EI16__V = 494, + VSUXSEG4EI32__V = 495, + VSUXSEG4EI64__V = 496, + VSUXSEG5EI8__V = 497, + VSUXSEG5EI16__V = 498, + VSUXSEG5EI32__V = 499, + VSUXSEG5EI64__V = 500, + VSUXSEG6EI8__V = 501, + VSUXSEG6EI16__V = 502, + VSUXSEG6EI32__V = 503, + VSUXSEG6EI64__V = 504, + VSUXSEG7EI8__V = 505, + VSUXSEG7EI16__V = 506, + VSUXSEG7EI32__V = 507, + VSUXSEG7EI64__V = 508, + VSUXSEG8EI8__V = 509, + VSUXSEG8EI16__V = 510, + VSUXSEG8EI32__V = 511, + VSUXSEG8EI64__V = 512, + VADD__VI = 513, + VADD__VV = 514, + VADD__VX = 515, + VSUB__VV = 516, + VSUB__VX = 517, + VRSUB__VI = 518, + VRSUB__VX = 519, + VWADDU__VV = 520, + VWADDU__VX = 521, + VWSUBU__VV = 522, + VWSUBU__VX = 523, + VWADD__VV = 524, + VWADD__VX = 525, + VWSUB__VV = 526, + VWSUB__VX = 527, + VWADDU__WV = 528, + VWADDU__WX = 529, + VWSUBU__WV = 530, + VWSUBU__WX = 531, + VWADD__WV = 532, + VWADD__WX = 533, + VWSUB__WV = 534, + VWSUB__WX = 535, + VZEXT__VF2 = 536, + VSEXT__VF2 = 537, + VZEXT__VF4 = 538, + VSEXT__VF4 = 539, + VZEXT__VF8 = 540, + VSEXT__VF8 = 541, + VADC__VVM = 542, + VADC__VXM = 543, + VADC__VIM = 544, + VMADC__VVM = 545, + VMADC__VXM = 546, + VMADC__VIM = 547, + VMADC__VV = 548, + VMADC__VX = 549, + VMADC__VI = 550, + VSBC__VVM = 551, + VSBC__VXM = 552, + VMSBC__VVM = 553, + VMSBC__VXM = 554, + VMSBC__VV = 555, + VMSBC__VX = 556, + VAND__VI = 557, + VAND__VV = 558, + VAND__VX = 559, + VOR__VI = 560, + VOR__VV = 561, + VOR__VX = 562, + VXOR__VI = 563, + VXOR__VV = 564, + VXOR__VX = 565, + VSLL__VI = 566, + VSLL__VV = 567, + VSLL__VX = 568, + VSRL__VI = 569, + VSRL__VV = 570, + VSRL__VX = 571, + VSRA__VI = 572, + VSRA__VV = 573, + VSRA__VX = 574, + VNSRL__WI = 575, + VNSRL__WV = 576, + VNSRL__WX = 577, + VNSRA__WI = 578, + VNSRA__WV = 579, + VNSRA__WX = 580, + VMSEQ__VI = 581, + VMSEQ__VV = 582, + VMSEQ__VX = 583, + VMSNE__VI = 584, + VMSNE__VV = 585, + VMSNE__VX = 586, + VMSLTU__VV = 587, + VMSLTU__VX = 588, + VMSLT__VV = 589, + VMSLT__VX = 590, + VMSLEU__VI = 591, + VMSLEU__VV = 592, + VMSLEU__VX = 593, + VMSLE__VI = 594, + VMSLE__VV = 595, + VMSLE__VX = 596, + VMSGTU__VI = 597, + VMSGTU__VX = 598, + VMSGT__VI = 599, + VMSGT__VX = 600, + VMINU__VV = 601, + VMINU__VX = 602, + VMIN__VV = 603, + VMIN__VX = 604, + VMAXU__VV = 605, + VMAXU__VX = 606, + VMAX__VV = 607, + VMAX__VX = 608, + VMUL__VV = 609, + VMUL__VX = 610, + VMULH__VV = 611, + VMULH__VX = 612, + VMULHU__VV = 613, + VMULHU__VX = 614, + VMULHSU__VV = 615, + VMULHSU__VX = 616, + VDIVU__VV = 617, + VDIVU__VX = 618, + VDIV__VV = 619, + VDIV__VX = 620, + VREMU__VV = 621, + VREMU__VX = 622, + VREM__VV = 623, + VREM__VX = 624, + VWMUL__VV = 625, + VWMUL__VX = 626, + VWMULU__VV = 627, + VWMULU__VX = 628, + VWMULSU__VV = 629, + VWMULSU__VX = 630, + VMACC__VV = 631, + VMACC__VX = 632, + VNMSAC__VV = 633, + VNMSAC__VX = 634, + VMADD__VV = 635, + VMADD__VX = 636, + VNMSUB__VV = 637, + VNMSUB__VX = 638, + VWMACCU__VV = 639, + VWMACCU__VX = 640, + VWMACC__VV = 641, + VWMACC__VX = 642, + VWMACCSU__VV = 643, + VWMACCSU__VX = 644, + VWMACCUS__VX = 645, + VMERGE__VIM = 646, + VMERGE__VVM = 647, + VMERGE__VXM = 648, + VMV__V__I = 649, + VMV__V__V = 650, + VMV__V__X = 651, + VSADDU__VI = 652, + VSADDU__VV = 653, + VSADDU__VX = 654, + VSADD__VI = 655, + VSADD__VV = 656, + VSADD__VX = 657, + VSSUBU__VV = 658, + VSSUBU__VX = 659, + VSSUB__VV = 660, + VSSUB__VX = 661, + VAADDU__VV = 662, + VAADDU__VX = 663, + VAADD__VV = 664, + VAADD__VX = 665, + VASUBU__VV = 666, + VASUBU__VX = 667, + VASUB__VV = 668, + VASUB__VX = 669, + VSMUL__VV = 670, + VSMUL__VX = 671, + VSSRL__VI = 672, + VSSRL__VV = 673, + VSSRL__VX = 674, + VSSRA__VI = 675, + VSSRA__VV = 676, + VSSRA__VX = 677, + VNCLIPU__WI = 678, + VNCLIPU__WV = 679, + VNCLIPU__WX = 680, + VNCLIP__WI = 681, + VNCLIP__WV = 682, + VNCLIP__WX = 683, + VREDSUM__VS = 684, + VREDMAXU__VS = 685, + VREDMAX__VS = 686, + VREDMINU__VS = 687, + VREDMIN__VS = 688, + VREDAND__VS = 689, + VREDOR__VS = 690, + VREDXOR__VS = 691, + VWREDSUMU__VS = 692, + VWREDSUM__VS = 693, + VFREDOSUM__VS = 694, + VFREDUSUM__VS = 695, + VFREDMAX__VS = 696, + VFREDMIN__VS = 697, + VFWREDOSUM__VS = 698, + VFWREDUSUM__VS = 699, + VMAND__MM = 700, + VMNAND__MM = 701, + VMANDN__MM = 702, + VMXOR__MM = 703, + VMOR__MM = 704, + VMNOR__MM = 705, + VMORN__MM = 706, + VMXNOR__MM = 707, + VCPOP__M = 708, + VFIRST__M = 709, + VMSBF__M = 710, + VMSIF__M = 711, + VMSOF__M = 712, + VIOTA__M = 713, + VID__V = 714, + VMV__S__X = 715, + VMV__X__S = 716, + VSLIDEUP__VI = 717, + VSLIDEUP__VX = 718, + VSLIDEDOWN__VI = 719, + VSLIDEDOWN__VX = 720, + VSLIDE1UP__VX = 721, + VSLIDE1DOWN__VX = 722, + VRGATHER__VI = 723, + VRGATHER__VV = 724, + VRGATHER__VX = 725, + VRGATHEREI16__VV = 726, + VCOMPRESS__VM = 727, + VMV1R__V = 728, + VMV2R__V = 729, + VMV4R__V = 730, + VMV8R__V = 731, + VFMV__S__F = 732, + VFMV__F__S = 733, + VFSLIDE1UP__VF = 734, + VFSLIDE1DOWN__VF = 735, + VFADD__VF = 736, + VFADD__VV = 737, + VFSUB__VF = 738, + VFSUB__VV = 739, + VFRSUB__VF = 740, + VFWADD__VF = 741, + VFWADD__VV = 742, + VFWSUB__VF = 743, + VFWSUB__VV = 744, + VFWADD__WF = 745, + VFWADD__WV = 746, + VFWSUB__WF = 747, + VFWSUB__WV = 748, + VFMUL__VF = 749, + VFMUL__VV = 750, + VFDIV__VF = 751, + VFDIV__VV = 752, + VFRDIV__VF = 753, + VFWMUL__VF = 754, + VFWMUL__VV = 755, + VFMACC__VF = 756, + VFMACC__VV = 757, + VFNMACC__VF = 758, + VFNMACC__VV = 759, + VFMSAC__VF = 760, + VFMSAC__VV = 761, + VFNMSAC__VF = 762, + VFNMSAC__VV = 763, + VFMADD__VF = 764, + VFMADD__VV = 765, + VFNMADD__VF = 766, + VFNMADD__VV = 767, + VFMSUB__VF = 768, + VFMSUB__VV = 769, + VFNMSUB__VF = 770, + VFNMSUB__VV = 771, + VFWMACC__VF = 772, + VFWMACC__VV = 773, + VFWNMACC__VF = 774, + VFWNMACC__VV = 775, + VFWMSAC__VF = 776, + VFWMSAC__VV = 777, + VFWNMSAC__VF = 778, + VFWNMSAC__VV = 779, + VFSQRT__V = 780, + VFRSQRT7__V = 781, + VFREC7__V = 782, + VFMIN__VF = 783, + VFMIN__VV = 784, + VFMAX__VF = 785, + VFMAX__VV = 786, + VFSGNJ__VF = 787, + VFSGNJ__VV = 788, + VFSGNJN__VF = 789, + VFSGNJN__VV = 790, + VFSGNJX__VF = 791, + VFSGNJX__VV = 792, + VMFEQ__VF = 793, + VMFEQ__VV = 794, + VMFNE__VF = 795, + VMFNE__VV = 796, + VMFLT__VF = 797, + VMFLT__VV = 798, + VMFLE__VF = 799, + VMFLE__VV = 800, + VMFGT__VF = 801, + VMFGE__VF = 802, + VFCLASS__V = 803, + VFMERGE__VFM = 804, + VFMV__V__F = 805, + VFCVT__XU__F__V = 806, + VFCVT__X__F__V = 807, + VFCVT__RTZ__XU__F__V = 808, + VFCVT__RTZ__X__F__V = 809, + VFCVT__F__XU__V = 810, + VFCVT__F__X__V = 811, + VFWCVT__XU__F__V = 812, + VFWCVT__X__F__V = 813, + VFWCVT__RTZ__XU__F__V = 814, + VFWCVT__RTZ__X__F__V = 815, + VFWCVT__F__XU__V = 816, + VFWCVT__F__X__V = 817, + VFWCVT__F__F__V = 818, + VFNCVT__X__F__W = 819, + VFNCVT__XU__F__W = 820, + VFNCVT__RTZ__XU__F__W = 821, + VFNCVT__RTZ__X__F__W = 822, + VFNCVT__F__XU__W = 823, + VFNCVT__F__X__W = 824, + VFNCVT__F__F__W = 825, + VFNCVT__ROD__F__F__W = 826, + MAX_OPCODE + }; +}; +} +} +#endif /* _RV64GCV_H_ */ +// clang-format on diff --git a/src/sysc/register_rv64gcv.cpp b/src/sysc/register_rv64gcv.cpp new file mode 100644 index 0000000..92b54fe --- /dev/null +++ b/src/sysc/register_rv64gcv.cpp @@ -0,0 +1,99 @@ +/******************************************************************************* + * Copyright (C) 2024 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ +// clang-format off +#include +#include +#include +#include +#include +#include +#include +#include + +namespace iss { +namespace interp { +using namespace sysc; + +volatile std::array rv64gcv_init = { + iss_factory::instance().register_creator("rv64gcv_msu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv64gcv_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv64gcv_mu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }) +}; +} +#if defined(WITH_LLVM) +namespace llvm { +using namespace sysc; +volatile std::array rv64gcv_init = { + iss_factory::instance().register_creator("rv64gcv_m:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv64gcv_mu:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }) +}; +} +#endif +#if defined(WITH_TCC) +namespace tcc { +using namespace sysc; +volatile std::array rv64gcv_init = { + iss_factory::instance().register_creator("rv64gcv_m:tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv64gcv_mu:tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }) +}; +} +#endif +} +// clang-format on diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp new file mode 100644 index 0000000..efd9915 --- /dev/null +++ b/src/vm/interp/vm_rv64gcv.cpp @@ -0,0 +1,31909 @@ +/******************************************************************************* + * Copyright (C) 2024 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +// clang-format off +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + + +#ifndef FMT_HEADER_ONLY +#define FMT_HEADER_ONLY +#endif +#include + +#include +#include + +namespace iss { +namespace interp { +namespace rv64gcv { +using namespace iss::arch; +using namespace iss::debugger; +using namespace std::placeholders; + +struct memory_access_exception : public std::exception{ + memory_access_exception(){} +}; + +template class vm_impl : public iss::interp::vm_base { +public: + using traits = arch::traits; + using super = typename iss::interp::vm_base; + using virt_addr_t = typename super::virt_addr_t; + using phys_addr_t = typename super::phys_addr_t; + using code_word_t = typename super::code_word_t; + using addr_t = typename super::addr_t; + using reg_t = typename traits::reg_t; + using mem_type_e = typename traits::mem_type_e; + using opcode_e = typename traits::opcode_e; + + vm_impl(); + + vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); + + void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } + + target_adapter_if *accquire_target_adapter(server_if *srv) override { + debugger_if::dbg_enabled = true; + if (super::tgt_adapter == nullptr) + super::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); + return super::tgt_adapter; + } + +protected: + using this_class = vm_impl; + using compile_ret_t = virt_addr_t; + using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr); + + inline const char *name(size_t index){return traits::reg_aliases.at(index);} + + inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";} + + inline const char* vname(size_t index) { return index < 32 ? name(index + traits::V0) : "illegal"; } + inline const char* sew_name(size_t bits) { + switch(bits) { + case 0b000: + return "e8"; + case 0b001: + return "e16"; + case 0b010: + return "e32"; + case 0b011: + return "e64"; + default: + return "illegal"; + } + } + inline const char* lmul_name(size_t bits) { + switch(bits) { + case 0b101: + return "mf8"; + case 0b110: + return "mf4"; + case 0b111: + return "mf2"; + case 0b000: + return "m1"; + case 0b001: + return "m2"; + case 0b010: + return "m4"; + case 0b011: + return "m8"; + default: + return "illegal"; + } + } + inline const char* ma_name(bool ma) { return ma ? "ma" : "mu"; } + inline const char* ta_name(bool ta) { return ta ? "ta" : "tu"; } + + + virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override; + + // some compile time constants + + inline void raise(uint16_t trap_id, uint16_t cause){ + auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id; + this->core.reg.trap_state = trap_val; + } + + inline void leave(unsigned lvl){ + this->core.leave_trap(lvl); + } + + inline void wait(unsigned type){ + this->core.wait_until(type); + } + + inline void set_tval(uint64_t new_tval){ + tval = new_tval; + } + + inline void lower(){ + this->core.reg.trap_state = 0; + } + uint64_t vlseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ + switch(width_val){ + case 0b000: + return softvector::vector_load_store<512, uint8_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b101: + return softvector::vector_load_store<512, uint16_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b110: + return softvector::vector_load_store<512, uint32_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b111: + return softvector::vector_load_store<512, uint64_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + default: + throw new std::runtime_error("Unsupported width bit value"); + } + } + uint64_t vsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ + switch(width_val){ + case 0b000: + return softvector::vector_load_store<512, uint8_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b101: + return softvector::vector_load_store<512, uint16_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b110: + return softvector::vector_load_store<512, uint32_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b111: + return softvector::vector_load_store<512, uint64_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + default: + throw new std::runtime_error("Unsupported width bit value"); + } + } + uint64_t vlsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ + switch(width_val){ + case 0b000: + return softvector::vector_load_store<512, uint8_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b101: + return softvector::vector_load_store<512, uint16_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b110: + return softvector::vector_load_store<512, uint32_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b111: + return softvector::vector_load_store<512, uint64_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + default: + throw new std::runtime_error("Unsupported width bit value"); + } + } + uint64_t vssseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ + switch(width_val){ + case 0b000: + return softvector::vector_load_store<512, uint8_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b101: + return softvector::vector_load_store<512, uint16_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b110: + return softvector::vector_load_store<512, uint32_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + case 0b111: + return softvector::vector_load_store<512, uint64_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); + default: + throw new std::runtime_error("Unsupported width bit value"); + } + } + + using indexed_load_store_t = std::function, uint8_t*, uint64_t, uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; + template indexed_load_store_t getFunction() { + return [this](void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, + uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, uint8_t segment_size) { + return softvector::vector_load_store_index<64, 512, T1, T2>(core, load_store_fn, V, vl, vstart, vtype, vm, vd, rs1, vs2, segment_size); + }; + } + + const std::array, 4> functionTable = {{ + {getFunction(), getFunction(), getFunction(), getFunction()}, + {getFunction(), getFunction(), getFunction(), getFunction()}, + {getFunction(), getFunction(), getFunction(), getFunction()}, + {getFunction(), getFunction(), getFunction(), getFunction()} + }}; + const size_t map_index_size[9] = { 0, 0, 1, 0, 2, 0, 0, 0, 3 }; // translate number of bytes to index in functionTable + uint64_t vlxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ + return functionTable[map_index_size[index_byte_size]][data_byte_size](this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size); + } + uint64_t vsxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ + return functionTable[map_index_size[index_byte_size]][data_byte_size](this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size); + } + void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_op<512, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op<512, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op<512, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_op<512, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op<512, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op<512, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_op<512, uint16_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op<512, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op<512, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_op<512, uint16_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op<512, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op<512, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t target_sew_pow, uint8_t frac_pow){ + switch(target_sew_pow){ + case 4: // uint16_t target + if(frac_pow != 1) throw new std::runtime_error("Unsupported frac_pow"); + return softvector::vector_unary_op<512, uint16_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 5: // uint32_t target + switch(frac_pow){ + case 1: + return softvector::vector_unary_op<512, uint32_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 2: + return softvector::vector_unary_op<512, uint32_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported frac_pow"); + } + case 6: // uint64_t target + switch(frac_pow){ + case 1: + return softvector::vector_unary_op<512, uint64_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 2: + return softvector::vector_unary_op<512, uint64_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 3: + return softvector::vector_unary_op<512, uint64_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported frac_pow"); + } + default: + throw new std::runtime_error("Unsupported target_sew_pow"); + } + } + void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_carry<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b001: + return softvector::vector_vector_carry<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b010: + return softvector::vector_vector_carry<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b011: + return softvector::vector_vector_carry<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } } + void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_carry<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b001: + return softvector::vector_imm_carry<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b010: + return softvector::vector_imm_carry<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b011: + return softvector::vector_imm_carry<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::carry_vector_vector_op<512, uint8_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::carry_vector_vector_op<512, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::carry_vector_vector_op<512, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::carry_vector_vector_op<512, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::carry_vector_imm_op<512, uint8_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::carry_vector_imm_op<512, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::carry_vector_imm_op<512, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::carry_vector_imm_op<512, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::mask_vector_vector_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::mask_vector_vector_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::mask_vector_vector_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::mask_vector_vector_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::mask_vector_imm_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::mask_vector_imm_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::mask_vector_imm_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::mask_vector_imm_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_op<512, uint8_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op<512, uint16_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op<512, uint32_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_op<512, uint8_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op<512, uint16_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op<512, uint32_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_merge<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_merge<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_merge<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_merge<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_merge<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_merge<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_merge<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_merge<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::sat_vector_vector_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b001: + return softvector::sat_vector_vector_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b010: + return softvector::sat_vector_vector_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b011: + return softvector::sat_vector_vector_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::sat_vector_imm_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b001: + return softvector::sat_vector_imm_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b010: + return softvector::sat_vector_imm_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b011: + return softvector::sat_vector_imm_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::sat_vector_vector_op<512, uint8_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b001: + return softvector::sat_vector_vector_op<512, uint16_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b010: + return softvector::sat_vector_vector_op<512, uint32_t, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::sat_vector_imm_op<512, uint8_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b001: + return softvector::sat_vector_imm_op<512, uint16_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b010: + return softvector::sat_vector_imm_op<512, uint32_t, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_red_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_red_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_red_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_red_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_red_op<512, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_red_op<512, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_red_op<512, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1){ + return softvector::mask_mask_op<512>(V, funct6, funct3, vl, vstart, vd, vs2, vs1); + } + uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2){ + return softvector::vcpop<512>(V, vl, vstart, vm, vs2); + } + int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2){ + return softvector::vfirst<512>(V, vl, vstart, vm, vs2); + } + void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2){ + return softvector::mask_set_op<512>(V, enc, vl, vstart, vm, vd, vs2); + } + void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::viota<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2); + case 0b001: + return softvector::viota<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2); + case 0b010: + return softvector::viota<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2); + case 0b011: + return softvector::viota<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vid<512, uint8_t>(V, vl, vstart, vtype, vm, vd); + case 0b001: + return softvector::vid<512, uint16_t>(V, vl, vstart, vtype, vm, vd); + case 0b010: + return softvector::vid<512, uint32_t>(V, vl, vstart, vtype, vm, vd); + case 0b011: + return softvector::vid<512, uint64_t>(V, vl, vstart, vtype, vm, vd); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + softvector::scalar_move<512, uint8_t>(V, vtype, vd, val, true); + break; + case 0b001: + softvector::scalar_move<512, uint16_t>(V, vtype, vd, val, true); + break; + case 0b010: + softvector::scalar_move<512, uint32_t>(V, vtype, vd, val, true); + break; + case 0b011: + softvector::scalar_move<512, uint64_t>(V, vtype, vd, val, true); + break; + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::scalar_move<512, uint8_t>(V, vtype, vd, 0, false); + case 0b001: + return softvector::scalar_move<512, uint16_t>(V, vtype, vd, 0, false); + case 0b010: + return softvector::scalar_move<512, uint32_t>(V, vtype, vd, 0, false); + case 0b011: + return softvector::scalar_move<512, uint64_t>(V, vtype, vd, 0, false); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + switch(sew_val){ + case 0b000: + return softvector::vector_slideup<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slideup<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slideup<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slideup<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + switch(sew_val){ + case 0b000: + return softvector::vector_slidedown<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slidedown<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slidedown<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slidedown<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + switch(sew_val){ + case 0b000: + return softvector::vector_slide1up<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slide1up<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slide1up<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slide1up<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + switch(sew_val){ + case 0b000: + return softvector::vector_slide1down<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slide1down<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slide1down<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slide1down<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_gather<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_gather<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_gather<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_gather<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_vector_gather<512, uint8_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_gather<512, uint16_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_gather<512, uint32_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_gather<512, uint64_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_imm_gather<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_gather<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_gather<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_gather<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_compress<512, uint8_t>(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b001: + return softvector::vector_compress<512, uint16_t>(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b010: + return softvector::vector_compress<512, uint32_t>(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b011: + return softvector::vector_compress<512, uint64_t>(V, vl, vstart, vtype, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count){ + return softvector::vector_whole_move<512>(V, vd, vs2, count); + } + uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val){ + return scalar_from_vector(V, vtype, vd, sew_val); + } + void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + return vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); + } + void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { + return vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); + } + void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_red_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_red_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::fp_vector_red_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::fp_vector_red_op<512, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b001: + return softvector::fp_vector_red_op<512, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_red_op<512, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::fp_vector_vector_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: + return softvector::fp_vector_imm_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op<512, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op<512, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op<512, uint32_t, uint16_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op<512, uint64_t, uint32_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op<512, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op<512, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op<512, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op<512, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_unary_op<512, uint16_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_op<512, uint32_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: + return softvector::fp_vector_unary_op<512, uint64_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::mask_fp_vector_vector_op<512, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::mask_fp_vector_vector_op<512, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::mask_fp_vector_vector_op<512, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::mask_fp_vector_imm_op<512, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::mask_fp_vector_imm_op<512, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: + return softvector::mask_fp_vector_imm_op<512, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t sew_val){ + vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); + } + void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::fp_vector_unary_w<512, uint16_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b001: + return softvector::fp_vector_unary_w<512, uint32_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_w<512, uint64_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::fp_vector_unary_n<512, uint8_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b001: + return softvector::fp_vector_unary_n<512, uint16_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_n<512, uint32_t, uint64_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: // would require 128 bit value to narrow + default: + throw new std::runtime_error("Unsupported sew bit value"); + } + } + void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val){ + switch(sew_val){ + case 0b000: + return softvector::vector_unary_op<512, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b001: + return softvector::vector_unary_op<512, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b010: + return softvector::vector_unary_op<512, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b011: + return softvector::vector_unary_op<512, uint64_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported sew_val"); + } + } + + uint64_t fetch_count{0}; + uint64_t tval{0}; + + using yield_t = boost::coroutines2::coroutine::push_type; + using coro_t = boost::coroutines2::coroutine::pull_type; + std::vector spawn_blocks; + + template::type> + inline S sext(U from) { + auto mask = (1ULL<(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::FCSR]); + uint8_t rm_eff = rm == 7? bit_sub<5, 7-5+1>(*FCSR) : rm; + if(rm_eff > 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return rm_eff; + } + + uint64_t NaNBox64(uint64_t val){ + if(traits::FLEN == 64) { + return (uint64_t)val; + } + else { + uint64_t box = ~((uint64_t)0); + return (uint64_t)(((uint128_t)box<<64)|val); + } + } + + uint8_t get_pow(uint32_t val){ + switch(val){ + case 8: + return 3; + case 16: + return 4; + case 32: + return 5; + case 64: + return 6; + case 128: + return 7; + case 256: + return 8; + case 512: + return 9; + case 1024: + return 10; + case 2048: + return 11; + case 4096: + return 12; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + + uint8_t lmul(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub<0, 2-0+1>(*vtype); + } + + uint8_t sew(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub<3, 5-3+1>(*vtype); + } + + int8_t get_lmul_pow(){ + switch(lmul()){ + case 5: + return - 3; + case 6: + return - 2; + case 7: + return - 1; + case 0: + return 0; + case 1: + return 1; + case 2: + return 2; + case 3: + return 3; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + + uint8_t get_sew_pow(){ + switch(sew()){ + case 0: + return 3; + case 1: + return 4; + case 2: + return 5; + case 3: + return 6; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + + uint16_t get_elem_count(){ + uint8_t total_pow = (uint8_t)((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow())); + return (uint16_t)(1 << total_pow) & ~1; + } + + uint8_t valid_vtype(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub(*vtype, (uint64_t)(traits::XLEN) - (uint64_t)(1), 1) == 0; + } + + uint8_t valid_rd_mask(uint8_t rd, uint8_t vm){ + return rd != 0 || vm != 0; + } + + uint8_t valid_eew_emul(uint8_t EEW, int8_t EMUL_pow){ + return EEW >= 8 && EEW <= traits::ELEN && EEW <= traits::EEW_MAX && EMUL_pow >= - 3 && EMUL_pow <= 3; + } + + uint8_t valid_segment(uint8_t nf, int8_t EMUL_pow){ + if(EMUL_pow < 0) { + uint8_t neg_EMUL = (uint8_t)(1 << - EMUL_pow) & ~1; + return nf / neg_EMUL <= 8; + } + else { + uint8_t EMUL = (uint8_t)(1 << EMUL_pow) & ~1; + return (uint16_t)(nf) * (uint16_t)(EMUL) <= 8; + } + } + + uint8_t illegal_vd_unmasked(){ + return ! valid_vtype(); + } + + uint8_t illegal_variable_width(uint8_t vd, uint8_t vm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_eew_emul(SEW_new, LMUL_pow_new)); + } + + uint8_t valid_reg_overlap(uint8_t rs, uint8_t rd, int8_t EMUL_pow_rs, int8_t EMUL_pow_rd){ + uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& (1ULL << 4) : 1; + uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& (1ULL << 4) : 1; + if(EMUL_pow_rs < EMUL_pow_rd) { + return (rs + rs_group <= rd) || (rs >= rd + rd_group) || ((rs + rs_group == rd + rd_group) & (EMUL_pow_rs >= 0)); + } + else { + if(EMUL_pow_rs > EMUL_pow_rd) { + return (rd <= rs) || (rd >= rs + rs_group); + } + else { + return true; + } + } + } + + uint8_t illegal_vd_masked(uint8_t vd){ + return ! (valid_vtype()) || vd == 0; + } + + uint8_t illegal_normal(uint8_t vd, uint8_t vm){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)); + } + + uint8_t valid_fp_op(uint8_t SEW, uint8_t rm){ + int8_t valid_sew = (traits::FP_SEW_MIN >= 32 & SEW <= traits::FP_SEW_MAX); + int8_t valid_rm = ! (rm == 5 | rm == 6 | rm == 7); + return valid_sew && valid_rm; + } + + uint8_t illegal_fp_vd_unmasked(uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || ! (valid_fp_op(SEW, rm)); + } + + uint8_t illegal_fp_normal(uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_fp_op(SEW, rm)); + } + + uint8_t valid_sew_lmul(){ + return get_sew_pow() <= (uint16_t)(get_pow(traits::ELEN)) + (int16_t)(get_lmul_pow()); + } + + uint16_t calculate_new_vl(uint64_t avl, uint16_t vlmax){ + if(avl <= vlmax) { + return ((uint16_t)avl); + } + else { + if(avl < ((uint32_t)(2) * (uint32_t)(vlmax))) { + return vlmax; + } + else { + return vlmax; + } + } + } + + void handle_illegal_vtype(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + auto* vl = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vl]); + *vtype = (uint64_t)1 << ((uint64_t)(traits::XLEN) - (uint64_t)(1)); + *vl = (uint64_t)0; + } + + uint8_t convert_width(uint8_t width){ + switch(width){ + case (0): + return 1; + case (5): + return 2; + case (6): + return 4; + case (7): + return 8; + } + return 0; + } + + uint8_t illegal_load(uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return ! valid_vtype() || ! valid_rd_mask(vd, vm) || ! valid_eew_emul(EEW, EMUL_pow) || ! valid_segment(nf, EMUL_pow); + } + + uint8_t illegal_store(uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return ! valid_vtype() || ! valid_eew_emul(EEW, EMUL_pow) || ! valid_segment(nf, EMUL_pow); + } + + uint8_t illegal_indexed_load(uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return ! valid_vtype() || ! valid_rd_mask(vd, vm) || ! valid_eew_emul(EEW_index, EMUL_pow_index) || ! valid_segment(nf, EMUL_pow_data); + } + + uint8_t illegal_indexed_store(uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return ! valid_vtype() || ! valid_eew_emul(EEW_index, EMUL_pow_index) || ! valid_segment(nf, EMUL_pow_data); + } + + uint8_t illegal_reduction(){ + auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); + return ! valid_vtype() || *vstart != 0; + } + + uint8_t illegal_reduction_widen(uint8_t EEW, int8_t EMUL_pow){ + return illegal_reduction() || ! valid_eew_emul(EEW, EMUL_pow); + } + + uint8_t illegal_fp_reduction(uint8_t SEW, uint8_t rm){ + auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); + return ! valid_vtype() || *vstart != 0 || ! valid_fp_op(SEW, rm); + } + + uint8_t illegal_fp_variable_width(uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_fp_op(SEW, rm)) || ! (valid_eew_emul(SEW_new, LMUL_pow_new)); + } + + uint8_t illegal_fp_vd_masked(uint8_t vd, uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || vd == 0 || ! (valid_fp_op(SEW, rm)); + } + + +private: + /**************************************************************************** + * start opcode definitions + ****************************************************************************/ + struct instruction_descriptor { + uint32_t length; + uint32_t value; + uint32_t mask; + typename arch::traits::opcode_e op; + }; + + const std::array instr_descr = {{ + /* entries are: size, valid value, valid mask, function ptr */ + {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits::opcode_e::LUI}, + {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits::opcode_e::AUIPC}, + {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits::opcode_e::JAL}, + {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::JALR}, + {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BEQ}, + {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BNE}, + {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLT}, + {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGE}, + {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLTU}, + {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGEU}, + {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LB}, + {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LH}, + {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LW}, + {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LBU}, + {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LHU}, + {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SB}, + {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SH}, + {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SW}, + {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ADDI}, + {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTI}, + {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTIU}, + {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::XORI}, + {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ORI}, + {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ANDI}, + {32, 0b00000000000000000001000000010011, 0b11111100000000000111000001111111, arch::traits::opcode_e::SLLI}, + {32, 0b00000000000000000101000000010011, 0b11111100000000000111000001111111, arch::traits::opcode_e::SRLI}, + {32, 0b01000000000000000101000000010011, 0b11111100000000000111000001111111, arch::traits::opcode_e::SRAI}, + {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::ADD}, + {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SUB}, + {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLL}, + {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLT}, + {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLTU}, + {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::XOR}, + {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRL}, + {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRA}, + {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::OR}, + {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::AND}, + {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE}, + {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::ECALL}, + {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::EBREAK}, + {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::MRET}, + {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::WFI}, + {32, 0b00000000000000000110000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LWU}, + {32, 0b00000000000000000011000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LD}, + {32, 0b00000000000000000011000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SD}, + {32, 0b00000000000000000000000000011011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ADDIW}, + {32, 0b00000000000000000001000000011011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLLIW}, + {32, 0b00000000000000000101000000011011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRLIW}, + {32, 0b01000000000000000101000000011011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRAIW}, + {32, 0b00000000000000000000000000111011, 0b11111110000000000111000001111111, arch::traits::opcode_e::ADDW}, + {32, 0b01000000000000000000000000111011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SUBW}, + {32, 0b00000000000000000001000000111011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLLW}, + {32, 0b00000000000000000101000000111011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRLW}, + {32, 0b01000000000000000101000000111011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRAW}, + {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRW}, + {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRS}, + {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRC}, + {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRWI}, + {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRSI}, + {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRCI}, + {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE_I}, + {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MUL}, + {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULH}, + {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULHSU}, + {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULHU}, + {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIV}, + {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIVU}, + {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REM}, + {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REMU}, + {32, 0b00000010000000000000000000111011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULW}, + {32, 0b00000010000000000100000000111011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIVW}, + {32, 0b00000010000000000101000000111011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIVUW}, + {32, 0b00000010000000000110000000111011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REMW}, + {32, 0b00000010000000000111000000111011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REMUW}, + {32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, arch::traits::opcode_e::LRW}, + {32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::SCW}, + {32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOSWAPW}, + {32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOADDW}, + {32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOXORW}, + {32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOANDW}, + {32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOORW}, + {32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMINW}, + {32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMAXW}, + {32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMINUW}, + {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMAXUW}, + {32, 0b00010000000000000011000000101111, 0b11111001111100000111000001111111, arch::traits::opcode_e::LRD}, + {32, 0b00011000000000000011000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::SCD}, + {32, 0b00001000000000000011000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOSWAPD}, + {32, 0b00000000000000000011000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOADDD}, + {32, 0b00100000000000000011000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOXORD}, + {32, 0b01100000000000000011000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOANDD}, + {32, 0b01000000000000000011000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOORD}, + {32, 0b10000000000000000011000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMIND}, + {32, 0b10100000000000000011000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMAXD}, + {32, 0b11000000000000000011000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMINUD}, + {32, 0b11100000000000000011000000101111, 0b11111000000000000111000001111111, arch::traits::opcode_e::AMOMAXUD}, + {16, 0b0000000000000000, 0b1110000000000011, arch::traits::opcode_e::C__ADDI4SPN}, + {16, 0b0100000000000000, 0b1110000000000011, arch::traits::opcode_e::C__LW}, + {16, 0b0110000000000000, 0b1110000000000011, arch::traits::opcode_e::C__LD}, + {16, 0b1100000000000000, 0b1110000000000011, arch::traits::opcode_e::C__SW}, + {16, 0b1110000000000000, 0b1110000000000011, arch::traits::opcode_e::C__SD}, + {16, 0b0000000000000001, 0b1110000000000011, arch::traits::opcode_e::C__ADDI}, + {16, 0b0000000000000001, 0b1110111110000011, arch::traits::opcode_e::C__NOP}, + {16, 0b0010000000000001, 0b1110000000000011, arch::traits::opcode_e::C__ADDIW}, + {16, 0b0100000000000001, 0b1110000000000011, arch::traits::opcode_e::C__LI}, + {16, 0b0110000000000001, 0b1110000000000011, arch::traits::opcode_e::C__LUI}, + {16, 0b0110000100000001, 0b1110111110000011, arch::traits::opcode_e::C__ADDI16SP}, + {16, 0b0110000000000001, 0b1111000001111111, arch::traits::opcode_e::__reserved_clui}, + {16, 0b1000000000000001, 0b1110110000000011, arch::traits::opcode_e::C__SRLI}, + {16, 0b1000010000000001, 0b1110110000000011, arch::traits::opcode_e::C__SRAI}, + {16, 0b1000100000000001, 0b1110110000000011, arch::traits::opcode_e::C__ANDI}, + {16, 0b1000110000000001, 0b1111110001100011, arch::traits::opcode_e::C__SUB}, + {16, 0b1000110000100001, 0b1111110001100011, arch::traits::opcode_e::C__XOR}, + {16, 0b1000110001000001, 0b1111110001100011, arch::traits::opcode_e::C__OR}, + {16, 0b1000110001100001, 0b1111110001100011, arch::traits::opcode_e::C__AND}, + {16, 0b1001110000000001, 0b1111110001100011, arch::traits::opcode_e::C__SUBW}, + {16, 0b1001110000100001, 0b1111110001100011, arch::traits::opcode_e::C__ADDW}, + {16, 0b1010000000000001, 0b1110000000000011, arch::traits::opcode_e::C__J}, + {16, 0b1100000000000001, 0b1110000000000011, arch::traits::opcode_e::C__BEQZ}, + {16, 0b1110000000000001, 0b1110000000000011, arch::traits::opcode_e::C__BNEZ}, + {16, 0b0000000000000010, 0b1110000000000011, arch::traits::opcode_e::C__SLLI}, + {16, 0b0100000000000010, 0b1110000000000011, arch::traits::opcode_e::C__LWSP}, + {16, 0b0110000000000010, 0b1110000000000011, arch::traits::opcode_e::C__LDSP}, + {16, 0b1000000000000010, 0b1111000000000011, arch::traits::opcode_e::C__MV}, + {16, 0b1000000000000010, 0b1111000001111111, arch::traits::opcode_e::C__JR}, + {16, 0b1000000000000010, 0b1111111111111111, arch::traits::opcode_e::__reserved_cmv}, + {16, 0b1001000000000010, 0b1111000000000011, arch::traits::opcode_e::C__ADD}, + {16, 0b1001000000000010, 0b1111000001111111, arch::traits::opcode_e::C__JALR}, + {16, 0b1001000000000010, 0b1111111111111111, arch::traits::opcode_e::C__EBREAK}, + {16, 0b1100000000000010, 0b1110000000000011, arch::traits::opcode_e::C__SWSP}, + {16, 0b1110000000000010, 0b1110000000000011, arch::traits::opcode_e::C__SDSP}, + {16, 0b0000000000000000, 0b1111111111111111, arch::traits::opcode_e::DII}, + {32, 0b00000000000000000010000000000111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FLW}, + {32, 0b00000000000000000010000000100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FSW}, + {32, 0b00000000000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FADD__S}, + {32, 0b00001000000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FSUB__S}, + {32, 0b00010000000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FMUL__S}, + {32, 0b00011000000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FDIV__S}, + {32, 0b00101000000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FMIN__S}, + {32, 0b00101000000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FMAX__S}, + {32, 0b01011000000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FSQRT__S}, + {32, 0b00000000000000000000000001000011, 0b00000110000000000000000001111111, arch::traits::opcode_e::FMADD__S}, + {32, 0b00000000000000000000000001000111, 0b00000110000000000000000001111111, arch::traits::opcode_e::FMSUB__S}, + {32, 0b00000000000000000000000001001111, 0b00000110000000000000000001111111, arch::traits::opcode_e::FNMADD__S}, + {32, 0b00000000000000000000000001001011, 0b00000110000000000000000001111111, arch::traits::opcode_e::FNMSUB__S}, + {32, 0b11000000000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__W__S}, + {32, 0b11000000000100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__WU__S}, + {32, 0b11000000001000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__L__S}, + {32, 0b11000000001100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__LU__S}, + {32, 0b11010000000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__S__W}, + {32, 0b11010000000100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__S__WU}, + {32, 0b11010000001000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__S__L}, + {32, 0b11010000001100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__S__LU}, + {32, 0b00100000000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJ__S}, + {32, 0b00100000000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJN__S}, + {32, 0b00100000000000000010000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJX__S}, + {32, 0b11100000000000000000000001010011, 0b11111111111100000111000001111111, arch::traits::opcode_e::FMV__X__W}, + {32, 0b11110000000000000000000001010011, 0b11111111111100000111000001111111, arch::traits::opcode_e::FMV__W__X}, + {32, 0b10100000000000000010000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FEQ__S}, + {32, 0b10100000000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FLT__S}, + {32, 0b10100000000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FLE__S}, + {32, 0b11100000000000000001000001010011, 0b11111111111100000111000001111111, arch::traits::opcode_e::FCLASS__S}, + {32, 0b00000000000000000011000000000111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FLD}, + {32, 0b00000000000000000011000000100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FSD}, + {32, 0b00000010000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FADD__D}, + {32, 0b00001010000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FSUB__D}, + {32, 0b00010010000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FMUL__D}, + {32, 0b00011010000000000000000001010011, 0b11111110000000000000000001111111, arch::traits::opcode_e::FDIV__D}, + {32, 0b00101010000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FMIN__D}, + {32, 0b00101010000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FMAX__D}, + {32, 0b01011010000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FSQRT__D}, + {32, 0b00000010000000000000000001000011, 0b00000110000000000000000001111111, arch::traits::opcode_e::FMADD__D}, + {32, 0b00000010000000000000000001000111, 0b00000110000000000000000001111111, arch::traits::opcode_e::FMSUB__D}, + {32, 0b00000010000000000000000001001111, 0b00000110000000000000000001111111, arch::traits::opcode_e::FNMADD__D}, + {32, 0b00000010000000000000000001001011, 0b00000110000000000000000001111111, arch::traits::opcode_e::FNMSUB__D}, + {32, 0b11000010000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__W__D}, + {32, 0b11000010000100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__WU__D}, + {32, 0b11000010001000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__L__D}, + {32, 0b11000010001100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__LU__D}, + {32, 0b11010010000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__D__W}, + {32, 0b11010010000100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__D__WU}, + {32, 0b11010010001000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__D__L}, + {32, 0b11010010001100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__D__LU}, + {32, 0b01000000000100000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__S__D}, + {32, 0b01000010000000000000000001010011, 0b11111111111100000000000001111111, arch::traits::opcode_e::FCVT__D__S}, + {32, 0b00100010000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJ__D}, + {32, 0b00100010000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJN__D}, + {32, 0b00100010000000000010000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FSGNJX__D}, + {32, 0b11100010000000000000000001010011, 0b11111111111100000111000001111111, arch::traits::opcode_e::FMV__X__D}, + {32, 0b11110010000000000000000001010011, 0b11111111111100000111000001111111, arch::traits::opcode_e::FMV__D__X}, + {32, 0b10100010000000000010000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FEQ__D}, + {32, 0b10100010000000000001000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FLT__D}, + {32, 0b10100010000000000000000001010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::FLE__D}, + {32, 0b11100010000000000001000001010011, 0b11111111111100000111000001111111, arch::traits::opcode_e::FCLASS__D}, + {16, 0b0010000000000000, 0b1110000000000011, arch::traits::opcode_e::C__FLD}, + {16, 0b1010000000000000, 0b1110000000000011, arch::traits::opcode_e::C__FSD}, + {16, 0b0010000000000010, 0b1110000000000011, arch::traits::opcode_e::C__FLDSP}, + {16, 0b1010000000000010, 0b1110000000000011, arch::traits::opcode_e::C__FSDSP}, + {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, arch::traits::opcode_e::SFENCE__VMA}, + {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::SRET}, + {32, 0b00000000000000000111000001010111, 0b11110000000000000111000001111111, arch::traits::opcode_e::VSETVLI}, + {32, 0b11000000000000000111000001010111, 0b11110000000000000111000001111111, arch::traits::opcode_e::VSETIVLI}, + {32, 0b10000000000000000111000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VSETVL}, + {32, 0b00000000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE8__V}, + {32, 0b00000000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE16__V}, + {32, 0b00000000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE32__V}, + {32, 0b00000000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE64__V}, + {32, 0b00100000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E8__V}, + {32, 0b00100000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E16__V}, + {32, 0b00100000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E32__V}, + {32, 0b00100000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E64__V}, + {32, 0b01000000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E8__V}, + {32, 0b01000000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E16__V}, + {32, 0b01000000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E32__V}, + {32, 0b01000000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E64__V}, + {32, 0b01100000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E8__V}, + {32, 0b01100000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E16__V}, + {32, 0b01100000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E32__V}, + {32, 0b01100000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E64__V}, + {32, 0b10000000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E8__V}, + {32, 0b10000000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E16__V}, + {32, 0b10000000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E32__V}, + {32, 0b10000000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E64__V}, + {32, 0b10100000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E8__V}, + {32, 0b10100000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E16__V}, + {32, 0b10100000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E32__V}, + {32, 0b10100000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E64__V}, + {32, 0b11000000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E8__V}, + {32, 0b11000000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E16__V}, + {32, 0b11000000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E32__V}, + {32, 0b11000000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E64__V}, + {32, 0b11100000000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E8__V}, + {32, 0b11100000000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E16__V}, + {32, 0b11100000000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E32__V}, + {32, 0b11100000000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E64__V}, + {32, 0b00000000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSE8__V}, + {32, 0b00000000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSE16__V}, + {32, 0b00000000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSE32__V}, + {32, 0b00000000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSE64__V}, + {32, 0b00100000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG2E8__V}, + {32, 0b00100000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG2E16__V}, + {32, 0b00100000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG2E32__V}, + {32, 0b00100000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG2E64__V}, + {32, 0b01000000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG3E8__V}, + {32, 0b01000000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG3E16__V}, + {32, 0b01000000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG3E32__V}, + {32, 0b01000000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG3E64__V}, + {32, 0b01100000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG4E8__V}, + {32, 0b01100000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG4E16__V}, + {32, 0b01100000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG4E32__V}, + {32, 0b01100000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG4E64__V}, + {32, 0b10000000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG5E8__V}, + {32, 0b10000000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG5E16__V}, + {32, 0b10000000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG5E32__V}, + {32, 0b10000000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG5E64__V}, + {32, 0b10100000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG6E8__V}, + {32, 0b10100000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG6E16__V}, + {32, 0b10100000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG6E32__V}, + {32, 0b10100000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG6E64__V}, + {32, 0b11000000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG7E8__V}, + {32, 0b11000000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG7E16__V}, + {32, 0b11000000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG7E32__V}, + {32, 0b11000000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG7E64__V}, + {32, 0b11100000000000000000000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG8E8__V}, + {32, 0b11100000000000000101000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG8E16__V}, + {32, 0b11100000000000000110000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG8E32__V}, + {32, 0b11100000000000000111000000100111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VSSEG8E64__V}, + {32, 0b00001000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSE8__V}, + {32, 0b00001000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSE16__V}, + {32, 0b00001000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSE32__V}, + {32, 0b00001000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSE64__V}, + {32, 0b00101000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG2E8__V}, + {32, 0b00101000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG2E16__V}, + {32, 0b00101000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG2E32__V}, + {32, 0b00101000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG2E64__V}, + {32, 0b01001000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG3E8__V}, + {32, 0b01001000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG3E16__V}, + {32, 0b01001000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG3E32__V}, + {32, 0b01001000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG3E64__V}, + {32, 0b01101000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG4E8__V}, + {32, 0b01101000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG4E16__V}, + {32, 0b01101000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG4E32__V}, + {32, 0b01101000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG4E64__V}, + {32, 0b10001000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG5E8__V}, + {32, 0b10001000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG5E16__V}, + {32, 0b10001000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG5E32__V}, + {32, 0b10001000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG5E64__V}, + {32, 0b10101000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG6E8__V}, + {32, 0b10101000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG6E16__V}, + {32, 0b10101000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG6E32__V}, + {32, 0b10101000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG6E64__V}, + {32, 0b11001000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG7E8__V}, + {32, 0b11001000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG7E16__V}, + {32, 0b11001000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG7E32__V}, + {32, 0b11001000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG7E64__V}, + {32, 0b11101000000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG8E8__V}, + {32, 0b11101000000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG8E16__V}, + {32, 0b11101000000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG8E32__V}, + {32, 0b11101000000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLSSEG8E64__V}, + {32, 0b00001000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSE8__V}, + {32, 0b00001000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSE16__V}, + {32, 0b00001000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSE32__V}, + {32, 0b00001000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSE64__V}, + {32, 0b00101000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG2E8__V}, + {32, 0b00101000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG2E16__V}, + {32, 0b00101000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG2E32__V}, + {32, 0b00101000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG2E64__V}, + {32, 0b01001000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG3E8__V}, + {32, 0b01001000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG3E16__V}, + {32, 0b01001000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG3E32__V}, + {32, 0b01001000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG3E64__V}, + {32, 0b01101000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG4E8__V}, + {32, 0b01101000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG4E16__V}, + {32, 0b01101000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG4E32__V}, + {32, 0b01101000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG4E64__V}, + {32, 0b10001000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG5E8__V}, + {32, 0b10001000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG5E16__V}, + {32, 0b10001000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG5E32__V}, + {32, 0b10001000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG5E64__V}, + {32, 0b10101000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG6E8__V}, + {32, 0b10101000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG6E16__V}, + {32, 0b10101000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG6E32__V}, + {32, 0b10101000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG6E64__V}, + {32, 0b11001000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG7E8__V}, + {32, 0b11001000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG7E16__V}, + {32, 0b11001000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG7E32__V}, + {32, 0b11001000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG7E64__V}, + {32, 0b11101000000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG8E8__V}, + {32, 0b11101000000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG8E16__V}, + {32, 0b11101000000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG8E32__V}, + {32, 0b11101000000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSSSEG8E64__V}, + {32, 0b00000001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE8FF__V}, + {32, 0b00000001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE16FF__V}, + {32, 0b00000001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE32FF__V}, + {32, 0b00000001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLE64FF__V}, + {32, 0b00100001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E8FF__V}, + {32, 0b00100001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E16FF__V}, + {32, 0b00100001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E32FF__V}, + {32, 0b00100001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG2E64FF__V}, + {32, 0b01000001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E8FF__V}, + {32, 0b01000001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E16FF__V}, + {32, 0b01000001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E32FF__V}, + {32, 0b01000001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG3E64FF__V}, + {32, 0b01100001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E8FF__V}, + {32, 0b01100001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E16FF__V}, + {32, 0b01100001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E32FF__V}, + {32, 0b01100001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG4E64FF__V}, + {32, 0b10000001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E8FF__V}, + {32, 0b10000001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E16FF__V}, + {32, 0b10000001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E32FF__V}, + {32, 0b10000001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG5E64FF__V}, + {32, 0b10100001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E8FF__V}, + {32, 0b10100001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E16FF__V}, + {32, 0b10100001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E32FF__V}, + {32, 0b10100001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG6E64FF__V}, + {32, 0b11000001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E8FF__V}, + {32, 0b11000001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E16FF__V}, + {32, 0b11000001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E32FF__V}, + {32, 0b11000001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG7E64FF__V}, + {32, 0b11100001000000000000000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E8FF__V}, + {32, 0b11100001000000000101000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E16FF__V}, + {32, 0b11100001000000000110000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E32FF__V}, + {32, 0b11100001000000000111000000000111, 0b11101101111100000111000001111111, arch::traits::opcode_e::VLSEG8E64FF__V}, + {32, 0b00000010101100000000000000100111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VSM__V}, + {32, 0b00000010101100000000000000000111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VLM__V}, + {32, 0b00000010100000000000000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL1RE8__V}, + {32, 0b00000010100000000101000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL1RE16__V}, + {32, 0b00000010100000000110000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL1RE32__V}, + {32, 0b00000010100000000111000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL1RE64__V}, + {32, 0b00100010100000000000000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL2RE8__V}, + {32, 0b00100010100000000101000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL2RE16__V}, + {32, 0b00100010100000000110000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL2RE32__V}, + {32, 0b00100010100000000111000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL2RE64__V}, + {32, 0b01100010100000000000000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL4RE8__V}, + {32, 0b01100010100000000101000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL4RE16__V}, + {32, 0b01100010100000000110000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL4RE32__V}, + {32, 0b01100010100000000111000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL4RE64__V}, + {32, 0b11100010100000000000000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL8RE8__V}, + {32, 0b11100010100000000101000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL8RE16__V}, + {32, 0b11100010100000000110000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL8RE32__V}, + {32, 0b11100010100000000111000000000111, 0b11101111111100000111000001111111, arch::traits::opcode_e::VL8RE64__V}, + {32, 0b00000010100000000000000000100111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VS1RE64__V}, + {32, 0b00100010100000000000000000100111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VS2RE64__V}, + {32, 0b01100010100000000000000000100111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VS4RE64__V}, + {32, 0b11100010100000000000000000100111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VS8RE64__V}, + {32, 0b00001100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXEI8__V}, + {32, 0b00001100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXEI16__V}, + {32, 0b00001100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXEI32__V}, + {32, 0b00001100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXEI64__V}, + {32, 0b00101100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG2EI8__V}, + {32, 0b00101100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG2EI16__V}, + {32, 0b00101100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG2EI32__V}, + {32, 0b00101100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG2EI64__V}, + {32, 0b01001100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG3EI8__V}, + {32, 0b01001100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG3EI16__V}, + {32, 0b01001100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG3EI32__V}, + {32, 0b01001100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG3EI64__V}, + {32, 0b01101100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG4EI8__V}, + {32, 0b01101100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG4EI16__V}, + {32, 0b01101100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG4EI32__V}, + {32, 0b01101100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG4EI64__V}, + {32, 0b10001100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG5EI8__V}, + {32, 0b10001100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG5EI16__V}, + {32, 0b10001100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG5EI32__V}, + {32, 0b10001100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG5EI64__V}, + {32, 0b10101100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG6EI8__V}, + {32, 0b10101100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG6EI16__V}, + {32, 0b10101100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG6EI32__V}, + {32, 0b10101100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG6EI64__V}, + {32, 0b11001100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG7EI8__V}, + {32, 0b11001100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG7EI16__V}, + {32, 0b11001100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG7EI32__V}, + {32, 0b11001100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG7EI64__V}, + {32, 0b11101100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG8EI8__V}, + {32, 0b11101100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG8EI16__V}, + {32, 0b11101100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG8EI32__V}, + {32, 0b11101100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLOXSEG8EI64__V}, + {32, 0b00001100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXEI8__V}, + {32, 0b00001100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXEI16__V}, + {32, 0b00001100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXEI32__V}, + {32, 0b00001100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXEI64__V}, + {32, 0b00101100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG2EI8__V}, + {32, 0b00101100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG2EI16__V}, + {32, 0b00101100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG2EI32__V}, + {32, 0b00101100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG2EI64__V}, + {32, 0b01001100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG3EI8__V}, + {32, 0b01001100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG3EI16__V}, + {32, 0b01001100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG3EI32__V}, + {32, 0b01001100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG3EI64__V}, + {32, 0b01101100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG4EI8__V}, + {32, 0b01101100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG4EI16__V}, + {32, 0b01101100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG4EI32__V}, + {32, 0b01101100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG4EI64__V}, + {32, 0b10001100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG5EI8__V}, + {32, 0b10001100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG5EI16__V}, + {32, 0b10001100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG5EI32__V}, + {32, 0b10001100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG5EI64__V}, + {32, 0b10101100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG6EI8__V}, + {32, 0b10101100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG6EI16__V}, + {32, 0b10101100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG6EI32__V}, + {32, 0b10101100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG6EI64__V}, + {32, 0b11001100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG7EI8__V}, + {32, 0b11001100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG7EI16__V}, + {32, 0b11001100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG7EI32__V}, + {32, 0b11001100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG7EI64__V}, + {32, 0b11101100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG8EI8__V}, + {32, 0b11101100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG8EI16__V}, + {32, 0b11101100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG8EI32__V}, + {32, 0b11101100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSOXSEG8EI64__V}, + {32, 0b00000100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXEI8__V}, + {32, 0b00000100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXEI16__V}, + {32, 0b00000100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXEI32__V}, + {32, 0b00000100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXEI64__V}, + {32, 0b00100100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG2EI8__V}, + {32, 0b00100100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG2EI16__V}, + {32, 0b00100100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG2EI32__V}, + {32, 0b00100100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG2EI64__V}, + {32, 0b01000100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG3EI8__V}, + {32, 0b01000100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG3EI16__V}, + {32, 0b01000100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG3EI32__V}, + {32, 0b01000100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG3EI64__V}, + {32, 0b01100100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG4EI8__V}, + {32, 0b01100100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG4EI16__V}, + {32, 0b01100100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG4EI32__V}, + {32, 0b01100100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG4EI64__V}, + {32, 0b10000100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG5EI8__V}, + {32, 0b10000100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG5EI16__V}, + {32, 0b10000100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG5EI32__V}, + {32, 0b10000100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG5EI64__V}, + {32, 0b10100100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG6EI8__V}, + {32, 0b10100100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG6EI16__V}, + {32, 0b10100100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG6EI32__V}, + {32, 0b10100100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG6EI64__V}, + {32, 0b11000100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG7EI8__V}, + {32, 0b11000100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG7EI16__V}, + {32, 0b11000100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG7EI32__V}, + {32, 0b11000100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG7EI64__V}, + {32, 0b11100100000000000000000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG8EI8__V}, + {32, 0b11100100000000000101000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG8EI16__V}, + {32, 0b11100100000000000110000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG8EI32__V}, + {32, 0b11100100000000000111000000000111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VLUXSEG8EI64__V}, + {32, 0b00000100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXEI8__V}, + {32, 0b00000100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXEI16__V}, + {32, 0b00000100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXEI32__V}, + {32, 0b00000100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXEI64__V}, + {32, 0b00100100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG2EI8__V}, + {32, 0b00100100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG2EI16__V}, + {32, 0b00100100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG2EI32__V}, + {32, 0b00100100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG2EI64__V}, + {32, 0b01000100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG3EI8__V}, + {32, 0b01000100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG3EI16__V}, + {32, 0b01000100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG3EI32__V}, + {32, 0b01000100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG3EI64__V}, + {32, 0b01100100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG4EI8__V}, + {32, 0b01100100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG4EI16__V}, + {32, 0b01100100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG4EI32__V}, + {32, 0b01100100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG4EI64__V}, + {32, 0b10000100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG5EI8__V}, + {32, 0b10000100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG5EI16__V}, + {32, 0b10000100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG5EI32__V}, + {32, 0b10000100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG5EI64__V}, + {32, 0b10100100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG6EI8__V}, + {32, 0b10100100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG6EI16__V}, + {32, 0b10100100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG6EI32__V}, + {32, 0b10100100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG6EI64__V}, + {32, 0b11000100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG7EI8__V}, + {32, 0b11000100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG7EI16__V}, + {32, 0b11000100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG7EI32__V}, + {32, 0b11000100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG7EI64__V}, + {32, 0b11100100000000000000000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG8EI8__V}, + {32, 0b11100100000000000101000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG8EI16__V}, + {32, 0b11100100000000000110000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG8EI32__V}, + {32, 0b11100100000000000111000000100111, 0b11101100000000000111000001111111, arch::traits::opcode_e::VSUXSEG8EI64__V}, + {32, 0b00000000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VADD__VI}, + {32, 0b00000000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VADD__VV}, + {32, 0b00000000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VADD__VX}, + {32, 0b00001000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSUB__VV}, + {32, 0b00001000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSUB__VX}, + {32, 0b00001100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRSUB__VI}, + {32, 0b00001100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRSUB__VX}, + {32, 0b11000000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADDU__VV}, + {32, 0b11000000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADDU__VX}, + {32, 0b11001000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUBU__VV}, + {32, 0b11001000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUBU__VX}, + {32, 0b11000100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADD__VV}, + {32, 0b11000100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADD__VX}, + {32, 0b11001100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUB__VV}, + {32, 0b11001100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUB__VX}, + {32, 0b11010000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADDU__WV}, + {32, 0b11010000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADDU__WX}, + {32, 0b11011000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUBU__WV}, + {32, 0b11011000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUBU__WX}, + {32, 0b11010100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADD__WV}, + {32, 0b11010100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWADD__WX}, + {32, 0b11011100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUB__WV}, + {32, 0b11011100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWSUB__WX}, + {32, 0b01001000000000110010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VZEXT__VF2}, + {32, 0b01001000000000111010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VSEXT__VF2}, + {32, 0b01001000000000100010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VZEXT__VF4}, + {32, 0b01001000000000101010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VSEXT__VF4}, + {32, 0b01001000000000010010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VZEXT__VF8}, + {32, 0b01001000000000011010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VSEXT__VF8}, + {32, 0b01000000000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VADC__VVM}, + {32, 0b01000000000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VADC__VXM}, + {32, 0b01000000000000000011000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VADC__VIM}, + {32, 0b01000100000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VVM}, + {32, 0b01000100000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VXM}, + {32, 0b01000100000000000011000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VIM}, + {32, 0b01000110000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VV}, + {32, 0b01000110000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VX}, + {32, 0b01000110000000000011000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMADC__VI}, + {32, 0b01001000000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VSBC__VVM}, + {32, 0b01001000000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VSBC__VXM}, + {32, 0b01001100000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMSBC__VVM}, + {32, 0b01001100000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMSBC__VXM}, + {32, 0b01001110000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMSBC__VV}, + {32, 0b01001110000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMSBC__VX}, + {32, 0b00100100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAND__VI}, + {32, 0b00100100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAND__VV}, + {32, 0b00100100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAND__VX}, + {32, 0b00101000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VOR__VI}, + {32, 0b00101000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VOR__VV}, + {32, 0b00101000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VOR__VX}, + {32, 0b00101100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VXOR__VI}, + {32, 0b00101100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VXOR__VV}, + {32, 0b00101100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VXOR__VX}, + {32, 0b10010100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLL__VI}, + {32, 0b10010100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLL__VV}, + {32, 0b10010100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLL__VX}, + {32, 0b10100000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRL__VI}, + {32, 0b10100000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRL__VV}, + {32, 0b10100000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRL__VX}, + {32, 0b10100100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRA__VI}, + {32, 0b10100100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRA__VV}, + {32, 0b10100100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSRA__VX}, + {32, 0b10110000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRL__WI}, + {32, 0b10110000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRL__WV}, + {32, 0b10110000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRL__WX}, + {32, 0b10110100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRA__WI}, + {32, 0b10110100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRA__WV}, + {32, 0b10110100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNSRA__WX}, + {32, 0b01100000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSEQ__VI}, + {32, 0b01100000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSEQ__VV}, + {32, 0b01100000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSEQ__VX}, + {32, 0b01100100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSNE__VI}, + {32, 0b01100100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSNE__VV}, + {32, 0b01100100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSNE__VX}, + {32, 0b01101000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLTU__VV}, + {32, 0b01101000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLTU__VX}, + {32, 0b01101100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLT__VV}, + {32, 0b01101100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLT__VX}, + {32, 0b01110000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLEU__VI}, + {32, 0b01110000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLEU__VV}, + {32, 0b01110000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLEU__VX}, + {32, 0b01110100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLE__VI}, + {32, 0b01110100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLE__VV}, + {32, 0b01110100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSLE__VX}, + {32, 0b01111000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSGTU__VI}, + {32, 0b01111000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSGTU__VX}, + {32, 0b01111100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSGT__VI}, + {32, 0b01111100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMSGT__VX}, + {32, 0b00010000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMINU__VV}, + {32, 0b00010000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMINU__VX}, + {32, 0b00010100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMIN__VV}, + {32, 0b00010100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMIN__VX}, + {32, 0b00011000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMAXU__VV}, + {32, 0b00011000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMAXU__VX}, + {32, 0b00011100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMAX__VV}, + {32, 0b00011100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMAX__VX}, + {32, 0b10010100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMUL__VV}, + {32, 0b10010100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMUL__VX}, + {32, 0b10011100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULH__VV}, + {32, 0b10011100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULH__VX}, + {32, 0b10010000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULHU__VV}, + {32, 0b10010000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULHU__VX}, + {32, 0b10011000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULHSU__VV}, + {32, 0b10011000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMULHSU__VX}, + {32, 0b10000000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VDIVU__VV}, + {32, 0b10000000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VDIVU__VX}, + {32, 0b10000100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VDIV__VV}, + {32, 0b10000100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VDIV__VX}, + {32, 0b10001000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREMU__VV}, + {32, 0b10001000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREMU__VX}, + {32, 0b10001100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREM__VV}, + {32, 0b10001100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREM__VX}, + {32, 0b11101100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMUL__VV}, + {32, 0b11101100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMUL__VX}, + {32, 0b11100000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMULU__VV}, + {32, 0b11100000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMULU__VX}, + {32, 0b11101000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMULSU__VV}, + {32, 0b11101000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMULSU__VX}, + {32, 0b10110100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMACC__VV}, + {32, 0b10110100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMACC__VX}, + {32, 0b10111100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNMSAC__VV}, + {32, 0b10111100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNMSAC__VX}, + {32, 0b10100100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMADD__VV}, + {32, 0b10100100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMADD__VX}, + {32, 0b10101100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNMSUB__VV}, + {32, 0b10101100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNMSUB__VX}, + {32, 0b11110000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACCU__VV}, + {32, 0b11110000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACCU__VX}, + {32, 0b11110100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACC__VV}, + {32, 0b11110100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACC__VX}, + {32, 0b11111100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACCSU__VV}, + {32, 0b11111100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACCSU__VX}, + {32, 0b11111000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWMACCUS__VX}, + {32, 0b01011100000000000011000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMERGE__VIM}, + {32, 0b01011100000000000000000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMERGE__VVM}, + {32, 0b01011100000000000100000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMERGE__VXM}, + {32, 0b01011110000000000011000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VMV__V__I}, + {32, 0b01011110000000000000000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VMV__V__V}, + {32, 0b01011110000000000100000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VMV__V__X}, + {32, 0b10000000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADDU__VI}, + {32, 0b10000000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADDU__VV}, + {32, 0b10000000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADDU__VX}, + {32, 0b10000100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADD__VI}, + {32, 0b10000100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADD__VV}, + {32, 0b10000100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSADD__VX}, + {32, 0b10001000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSUBU__VV}, + {32, 0b10001000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSUBU__VX}, + {32, 0b10001100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSUB__VV}, + {32, 0b10001100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSUB__VX}, + {32, 0b00100000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAADDU__VV}, + {32, 0b00100000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAADDU__VX}, + {32, 0b00100100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAADD__VV}, + {32, 0b00100100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VAADD__VX}, + {32, 0b00101000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VASUBU__VV}, + {32, 0b00101000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VASUBU__VX}, + {32, 0b00101100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VASUB__VV}, + {32, 0b00101100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VASUB__VX}, + {32, 0b10011100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSMUL__VV}, + {32, 0b10011100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSMUL__VX}, + {32, 0b10101000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRL__VI}, + {32, 0b10101000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRL__VV}, + {32, 0b10101000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRL__VX}, + {32, 0b10101100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRA__VI}, + {32, 0b10101100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRA__VV}, + {32, 0b10101100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSSRA__VX}, + {32, 0b10111000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIPU__WI}, + {32, 0b10111000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIPU__WV}, + {32, 0b10111000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIPU__WX}, + {32, 0b10111100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIP__WI}, + {32, 0b10111100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIP__WV}, + {32, 0b10111100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VNCLIP__WX}, + {32, 0b00000000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDSUM__VS}, + {32, 0b00011000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDMAXU__VS}, + {32, 0b00011100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDMAX__VS}, + {32, 0b00010000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDMINU__VS}, + {32, 0b00010100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDMIN__VS}, + {32, 0b00000100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDAND__VS}, + {32, 0b00001000000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDOR__VS}, + {32, 0b00001100000000000010000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VREDXOR__VS}, + {32, 0b11000000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWREDSUMU__VS}, + {32, 0b11000100000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VWREDSUM__VS}, + {32, 0b00001100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFREDOSUM__VS}, + {32, 0b00000100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFREDUSUM__VS}, + {32, 0b00011100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFREDMAX__VS}, + {32, 0b00010100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFREDMIN__VS}, + {32, 0b11001100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWREDOSUM__VS}, + {32, 0b11000100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWREDUSUM__VS}, + {32, 0b01100110000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMAND__MM}, + {32, 0b01110110000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMNAND__MM}, + {32, 0b01100010000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMANDN__MM}, + {32, 0b01101110000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMXOR__MM}, + {32, 0b01101010000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMOR__MM}, + {32, 0b01111010000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMNOR__MM}, + {32, 0b01110010000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMORN__MM}, + {32, 0b01111110000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VMXNOR__MM}, + {32, 0b01000000000010000010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VCPOP__M}, + {32, 0b01000000000010001010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFIRST__M}, + {32, 0b01010000000000001010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VMSBF__M}, + {32, 0b01010000000000011010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VMSIF__M}, + {32, 0b01010000000000010010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VMSOF__M}, + {32, 0b01010000000010000010000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VIOTA__M}, + {32, 0b01010000000010001010000001010111, 0b11111101111111111111000001111111, arch::traits::opcode_e::VID__V}, + {32, 0b01000010000000000110000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VMV__S__X}, + {32, 0b01000010000000000010000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VMV__X__S}, + {32, 0b00111000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDEUP__VI}, + {32, 0b00111000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDEUP__VX}, + {32, 0b00111100000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDEDOWN__VI}, + {32, 0b00111100000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDEDOWN__VX}, + {32, 0b00111000000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDE1UP__VX}, + {32, 0b00111100000000000110000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VSLIDE1DOWN__VX}, + {32, 0b00110000000000000011000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRGATHER__VI}, + {32, 0b00110000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRGATHER__VV}, + {32, 0b00110000000000000100000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRGATHER__VX}, + {32, 0b00111000000000000000000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VRGATHEREI16__VV}, + {32, 0b01011110000000000010000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VCOMPRESS__VM}, + {32, 0b10011110000000000011000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VMV1R__V}, + {32, 0b10011110000000001011000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VMV2R__V}, + {32, 0b10011110000000011011000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VMV4R__V}, + {32, 0b10011110000000111011000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VMV8R__V}, + {32, 0b01000010000000000101000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VFMV__S__F}, + {32, 0b01000010000000000001000001010111, 0b11111110000011111111000001111111, arch::traits::opcode_e::VFMV__F__S}, + {32, 0b00111000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSLIDE1UP__VF}, + {32, 0b00111100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSLIDE1DOWN__VF}, + {32, 0b00000000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFADD__VF}, + {32, 0b00000000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFADD__VV}, + {32, 0b00001000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSUB__VF}, + {32, 0b00001000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSUB__VV}, + {32, 0b10011100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFRSUB__VF}, + {32, 0b11000000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWADD__VF}, + {32, 0b11000000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWADD__VV}, + {32, 0b11001000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWSUB__VF}, + {32, 0b11001000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWSUB__VV}, + {32, 0b11010000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWADD__WF}, + {32, 0b11010000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWADD__WV}, + {32, 0b11011000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWSUB__WF}, + {32, 0b11011000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWSUB__WV}, + {32, 0b10010000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMUL__VF}, + {32, 0b10010000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMUL__VV}, + {32, 0b10000000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFDIV__VF}, + {32, 0b10000000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFDIV__VV}, + {32, 0b10000100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFRDIV__VF}, + {32, 0b11100000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMUL__VF}, + {32, 0b11100000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMUL__VV}, + {32, 0b10110000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMACC__VF}, + {32, 0b10110000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMACC__VV}, + {32, 0b10110100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMACC__VF}, + {32, 0b10110100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMACC__VV}, + {32, 0b10111000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMSAC__VF}, + {32, 0b10111000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMSAC__VV}, + {32, 0b10111100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMSAC__VF}, + {32, 0b10111100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMSAC__VV}, + {32, 0b10100000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMADD__VF}, + {32, 0b10100000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMADD__VV}, + {32, 0b10100100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMADD__VF}, + {32, 0b10100100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMADD__VV}, + {32, 0b10101000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMSUB__VF}, + {32, 0b10101000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMSUB__VV}, + {32, 0b10101100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMSUB__VF}, + {32, 0b10101100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFNMSUB__VV}, + {32, 0b11110000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMACC__VF}, + {32, 0b11110000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMACC__VV}, + {32, 0b11110100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWNMACC__VF}, + {32, 0b11110100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWNMACC__VV}, + {32, 0b11111000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMSAC__VF}, + {32, 0b11111000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWMSAC__VV}, + {32, 0b11111100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWNMSAC__VF}, + {32, 0b11111100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFWNMSAC__VV}, + {32, 0b01001100000000000001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFSQRT__V}, + {32, 0b01001100000000100001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFRSQRT7__V}, + {32, 0b01001100000000101001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFREC7__V}, + {32, 0b00010000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMIN__VF}, + {32, 0b00010000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMIN__VV}, + {32, 0b00011000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMAX__VF}, + {32, 0b00011000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFMAX__VV}, + {32, 0b00100000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJ__VF}, + {32, 0b00100000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJ__VV}, + {32, 0b00100100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJN__VF}, + {32, 0b00100100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJN__VV}, + {32, 0b00101000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJX__VF}, + {32, 0b00101000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VFSGNJX__VV}, + {32, 0b01100000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFEQ__VF}, + {32, 0b01100000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFEQ__VV}, + {32, 0b01110000000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFNE__VF}, + {32, 0b01110000000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFNE__VV}, + {32, 0b01101100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFLT__VF}, + {32, 0b01101100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFLT__VV}, + {32, 0b01100100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFLE__VF}, + {32, 0b01100100000000000001000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFLE__VV}, + {32, 0b01110100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFGT__VF}, + {32, 0b01111100000000000101000001010111, 0b11111100000000000111000001111111, arch::traits::opcode_e::VMFGE__VF}, + {32, 0b01001100000010000001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCLASS__V}, + {32, 0b01011100000000000101000001010111, 0b11111110000000000111000001111111, arch::traits::opcode_e::VFMERGE__VFM}, + {32, 0b01011110000000000101000001010111, 0b11111111111100000111000001111111, arch::traits::opcode_e::VFMV__V__F}, + {32, 0b01001000000000000001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__XU__F__V}, + {32, 0b01001000000000001001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__X__F__V}, + {32, 0b01001000000000110001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__RTZ__XU__F__V}, + {32, 0b01001000000000111001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__RTZ__X__F__V}, + {32, 0b01001000000000010001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__F__XU__V}, + {32, 0b01001000000000011001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFCVT__F__X__V}, + {32, 0b01001000000001000001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__XU__F__V}, + {32, 0b01001000000001001001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__X__F__V}, + {32, 0b01001000000001110001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__RTZ__XU__F__V}, + {32, 0b01001000000001111001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__RTZ__X__F__V}, + {32, 0b01001000000001010001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__F__XU__V}, + {32, 0b01001000000001011001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__F__X__V}, + {32, 0b01001000000001100001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFWCVT__F__F__V}, + {32, 0b01001000000010001001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__X__F__W}, + {32, 0b01001000000010000001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__XU__F__W}, + {32, 0b01001000000010110001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__RTZ__XU__F__W}, + {32, 0b01001000000010111001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__RTZ__X__F__W}, + {32, 0b01001000000010010001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__F__XU__W}, + {32, 0b01001000000010011001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__F__X__W}, + {32, 0b01001000000010100001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__F__F__W}, + {32, 0b01001000000010101001000001010111, 0b11111100000011111111000001111111, arch::traits::opcode_e::VFNCVT__ROD__F__F__W}, + }}; + + //needs to be declared after instr_descr + decoder instr_decoder; + + iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ + if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok) + return iss::Err; + return iss::Ok; + } +}; + +template void debug_fn(CODE_WORD insn) { + volatile CODE_WORD x = insn; + insn = 2 * x; +} +// according to +// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation +#ifdef __GCC__ +constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); } +#elif __cplusplus < 201402L +constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); } +constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; } +#else +constexpr size_t bit_count(uint32_t u) { + size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); + return ((uCount + (uCount >> 3)) & 030707070707) % 63; +} +#endif + +template +vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) +: vm_base(core, core_id, cluster_id) +, instr_decoder([this]() { + std::vector g_instr_descr; + g_instr_descr.reserve(instr_descr.size()); + for (uint32_t i = 0; i < instr_descr.size(); ++i) { + generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i}; + g_instr_descr.push_back(new_instr_descr); + } + return std::move(g_instr_descr); + }()) {} + +inline bool is_icount_limit_enabled(finish_cond_e cond){ + return (cond & finish_cond_e::ICOUNT_LIMIT) == finish_cond_e::ICOUNT_LIMIT; +} + +inline bool is_fcount_limit_enabled(finish_cond_e cond){ + return (cond & finish_cond_e::FCOUNT_LIMIT) == finish_cond_e::FCOUNT_LIMIT; +} + +inline bool is_jump_to_self_enabled(finish_cond_e cond){ + return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF; +} + +template +typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t count_limit){ + auto pc=start; + auto* PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PC]); + auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); + auto& trap_state = this->core.reg.trap_state; + auto& icount = this->core.reg.icount; + auto& cycle = this->core.reg.cycle; + auto& instret = this->core.reg.instret; + auto& instr = this->core.reg.instruction; + // we fetch at max 4 byte, alignment is 2 + auto *const data = reinterpret_cast(&instr); + + while(!this->core.should_stop() && + !(is_icount_limit_enabled(cond) && icount >= count_limit) && + !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){ + if(this->debugging_enabled()) + this->tgt_adapter->check_continue(*PC); + pc.val=*PC; + if(fetch_ins(pc, data)!=iss::Ok){ + if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits::max()); + process_spawn_blocks(); + if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits::max()); + *PC = super::core.enter_trap(trap_state, pc.val, instr); + } else { + if (is_jump_to_self_enabled(cond) && + (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' + uint32_t inst_index = instr_decoder.decode_instr(instr); + opcode_e inst_id = arch::traits::opcode_e::MAX_OPCODE;; + if(inst_index core.reg.last_branch = 0; + if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); + try{ + switch(inst_id){ + case arch::traits::opcode_e::LUI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((int32_t)imm); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AUIPC: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((uint128_t)(*PC) + (int128_t)((int32_t)imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::JAL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t new_pc = (uint64_t)((uint128_t)(*PC) + (int128_t)((int32_t)sext<21>(imm))); + if(new_pc % (uint64_t)(traits::INSTR_ALIGNMENT)) { + set_tval(new_pc); + raise(0, 0); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((uint128_t)(*PC) + (uint128_t)(4)); + } + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::JALR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t addr_mask = (uint64_t)- 2; + uint64_t new_pc = (uint64_t)(((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))) & (uint128_t)(addr_mask)); + if(new_pc % (uint64_t)(traits::INSTR_ALIGNMENT)) { + set_tval(new_pc); + raise(0, 0); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((uint128_t)(*PC) + (uint128_t)(4)); + } + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BEQ: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs1) == *(X+rs2)) { + uint64_t new_pc = (uint64_t)((uint128_t)(*PC) + (int128_t)((int16_t)sext<13>(imm))); + if(new_pc % (uint64_t)(traits::INSTR_ALIGNMENT)) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BNE: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs1) != *(X+rs2)) { + uint64_t new_pc = (uint64_t)((uint128_t)(*PC) + (int128_t)((int16_t)sext<13>(imm))); + if(new_pc % (uint64_t)(traits::INSTR_ALIGNMENT)) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BLT: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if((int64_t)*(X+rs1) < (int64_t)*(X+rs2)) { + uint64_t new_pc = (uint64_t)((uint128_t)(*PC) + (int128_t)((int16_t)sext<13>(imm))); + if(new_pc % (uint64_t)(traits::INSTR_ALIGNMENT)) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BGE: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if((int64_t)*(X+rs1) >= (int64_t)*(X+rs2)) { + uint64_t new_pc = (uint64_t)((uint128_t)(*PC) + (int128_t)((int16_t)sext<13>(imm))); + if(new_pc % (uint64_t)(traits::INSTR_ALIGNMENT)) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BLTU: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs1) < *(X+rs2)) { + uint64_t new_pc = (uint64_t)((uint128_t)(*PC) + (int128_t)((int16_t)sext<13>(imm))); + if(new_pc % (uint64_t)(traits::INSTR_ALIGNMENT)) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BGEU: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs1) >= *(X+rs2)) { + uint64_t new_pc = (uint64_t)((uint128_t)(*PC) + (int128_t)((int16_t)sext<13>(imm))); + if(new_pc % (uint64_t)(traits::INSTR_ALIGNMENT)) { + set_tval(new_pc); + raise(0, 0); + } + else { + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LB: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t load_address = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + int8_t res_1 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int8_t res = (int8_t)res_1; + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LH: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t load_address = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + int16_t res_2 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int16_t res = (int16_t)res_2; + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t load_address = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + int32_t res_3 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int32_t res = (int32_t)res_3; + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LBU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t load_address = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + uint8_t res_4 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint8_t res = res_4; + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LHU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t load_address = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + uint16_t res_5 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint16_t res = res_5; + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SB: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t store_address = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, store_address, (uint8_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SH: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t store_address = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, store_address, (uint16_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SW: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t store_address = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, store_address, (uint32_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ADDI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = ((int64_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTIU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (*(X+rs1) < (uint64_t)((int16_t)sext<12>(imm)))? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::XORI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) ^ (uint64_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ORI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) | (uint64_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ANDI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) & (uint64_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) << shamt; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) >> shamt; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRAI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)(((int64_t)*(X+rs1)) >> shamt); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ADD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((uint128_t)(*(X+rs1)) + (uint128_t)(*(X+rs2))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SUB: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((uint128_t)(*(X+rs1)) - (uint128_t)(*(X+rs2))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) << (*(X+rs2) & ((uint64_t)(traits::XLEN) - (uint64_t)(1))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLT: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (int64_t)*(X+rs1) < (int64_t)*(X+rs2)? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::XOR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) ^ *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) >> (*(X+rs2) & ((uint64_t)(traits::XLEN) - (uint64_t)(1))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRA: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((int64_t)*(X+rs1) >> (*(X+rs2) & ((uint64_t)(traits::XLEN) - (uint64_t)(1)))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::OR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) | *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AND: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) & *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FENCE: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + uint8_t fm = ((bit_sub<28,4>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ECALL: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "ecall"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + raise(0, 11); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::EBREAK: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "ebreak"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + raise(0, 3); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MRET: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "mret"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + leave(3); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::WFI: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "wfi"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + wait(1); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LWU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lwu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + uint32_t res_6 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res = (uint32_t)res_6; + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "ld"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + int64_t res_7 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int64_t res = (int64_t)res_7; + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SD: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sd"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, offs, (uint64_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ADDIW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addiw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + int32_t res = (int32_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLLIW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slliw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + uint32_t sh_val = ((uint32_t)*(X+rs1)) << shamt; + *(X+rd) = (uint64_t)(int32_t)sh_val; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRLIW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srliw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + uint32_t sh_val = ((uint32_t)*(X+rs1)) >> shamt; + *(X+rd) = (uint64_t)(int32_t)sh_val; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRAIW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "sraiw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + int32_t sh_val = ((int32_t)*(X+rs1)) >> shamt; + *(X+rd) = (uint64_t)sh_val; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ADDW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "addw"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + int32_t res = (int32_t)((int64_t)((int32_t)*(X+rs1)) + (int64_t)((int32_t)*(X+rs2))); + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SUBW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "subw"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + int32_t res = (int32_t)((int64_t)((int32_t)*(X+rs1)) - (int64_t)((int32_t)*(X+rs2))); + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLLW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sllw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + uint32_t count = (uint32_t)*(X+rs2) & (uint32_t)(31); + uint32_t sh_val = ((uint32_t)*(X+rs1)) << count; + *(X+rd) = (uint64_t)(int32_t)sh_val; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRLW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srlw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + uint32_t count = (uint32_t)*(X+rs2) & (uint32_t)(31); + uint32_t sh_val = ((uint32_t)*(X+rs1)) >> count; + *(X+rd) = (uint64_t)(int32_t)sh_val; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRAW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sraw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + uint32_t count = (uint32_t)*(X+rs2) & (uint32_t)(31); + int32_t sh_val = ((int32_t)*(X+rs1)) >> count; + *(X+rd) = (uint64_t)sh_val; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t xrs1 = *(X+rs1); + if(rd != 0) { + uint64_t res_8 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t xrd = res_8; + super::template write_mem(traits::CSR, csr, xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = xrd; + } + else { + super::template write_mem(traits::CSR, csr, xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRS: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res_9 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t xrd = res_9; + uint64_t xrs1 = *(X+rs1); + if(rs1 != 0) { + super::template write_mem(traits::CSR, csr, xrd | xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRC: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res_10 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t xrd = res_10; + uint64_t xrs1 = *(X+rs1); + if(rs1 != 0) { + super::template write_mem(traits::CSR, csr, xrd & ~xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRWI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res_11 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t xrd = res_11; + super::template write_mem(traits::CSR, csr, (uint64_t)zimm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRSI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res_12 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t xrd = res_12; + if(zimm != 0) { + super::template write_mem(traits::CSR, csr, xrd | (uint64_t)zimm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRCI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res_13 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t xrd = res_13; + if(zimm != 0) { + super::template write_mem(traits::CSR, csr, xrd & ~((uint64_t)zimm)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FENCE_I: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fencei, imm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MUL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int128_t res = (int128_t)((int64_t)*(X+rs1)) * (int128_t)((int64_t)*(X+rs2)); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MULH: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int128_t res = (int128_t)((int64_t)*(X+rs1)) * (int128_t)((int64_t)*(X+rs2)); + if(rd != 0) { + *(X+rd) = (uint64_t)(res >> traits::XLEN); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MULHSU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int128_t res = (int128_t)((int64_t)*(X+rs1)) * (uint128_t)(*(X+rs2)); + if(rd != 0) { + *(X+rd) = (uint64_t)(res >> traits::XLEN); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MULHU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint128_t res = (uint128_t)(*(X+rs1)) * (uint128_t)(*(X+rs2)); + if(rd != 0) { + *(X+rd) = (uint64_t)(res >> traits::XLEN); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::DIV: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int64_t dividend = (int64_t)*(X+rs1); + int64_t divisor = (int64_t)*(X+rs2); + if(rd != 0) { + if(divisor != 0) { + uint64_t MMIN = ((uint64_t)1) << ((uint64_t)(traits::XLEN) - (uint64_t)(1)); + if(*(X+rs1) == MMIN && divisor == - 1) { + *(X+rd) = MMIN; + } + else { + *(X+rd) = (uint64_t)(dividend / divisor); + } + } + else { + *(X+rd) = (uint64_t)- 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::DIVU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs2) != 0) { + if(rd != 0) { + *(X+rd) = *(X+rs1) / *(X+rs2); + } + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)- 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::REM: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs2) != 0) { + uint64_t MMIN = (uint64_t)1 << ((uint64_t)(traits::XLEN) - (uint64_t)(1)); + if(*(X+rs1) == MMIN && (int64_t)*(X+rs2) == - 1) { + if(rd != 0) { + *(X+rd) = 0; + } + } + else { + if(rd != 0) { + *(X+rd) = ((uint64_t)((int64_t)*(X+rs1) % (int64_t)*(X+rs2))); + } + } + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::REMU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*(X+rs2) != 0) { + if(rd != 0) { + *(X+rd) = *(X+rs1) % *(X+rs2); + } + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MULW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + int32_t resw = (int32_t)((int64_t)((int32_t)*(X+rs1)) * (int64_t)((int32_t)*(X+rs2))); + *(X+rd) = ((uint64_t)(int64_t)resw); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::DIVW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int32_t dividend = (int32_t)*(X+rs1); + int32_t divisor = (int32_t)*(X+rs2); + if(divisor != 0) { + int32_t MMIN = (int32_t)1 << 31; + if(dividend == MMIN && divisor == - 1) { + if(rd != 0) { + *(X+rd) = (uint64_t)- 1 << 31; + } + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)(dividend / divisor); + } + } + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)- 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::DIVUW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t divisor = (uint32_t)*(X+rs2); + if(divisor != 0) { + int32_t res = (int32_t)((uint32_t)*(X+rs1) / divisor); + if(rd != 0) { + *(X+rd) = ((uint64_t)(int64_t)res); + } + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)- 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::REMW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(((int32_t)*(X+rs2)) != 0) { + int32_t SMIN = (int32_t)1 << 31; + if((int32_t)*(X+rs1) == SMIN && (int32_t)*(X+rs2) == - 1) { + if(rd != 0) { + *(X+rd) = 0; + } + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2)); + } + } + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((int32_t)*(X+rs1)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::REMUW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t divisor = (uint32_t)*(X+rs2); + if(divisor != 0) { + int32_t res = (int32_t)((uint32_t)*(X+rs1) % divisor); + if(rd != 0) { + *(X+rd) = ((uint64_t)(int64_t)res); + } + } + else { + int32_t res = (int32_t)*(X+rs1); + if(rd != 0) { + *(X+rd) = ((uint64_t)(int64_t)res); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LRW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {aq}, {rl}", fmt::arg("mnemonic", "lrw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("aq", name(aq)), fmt::arg("rl", name(rl))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + uint64_t offs = *(X+rs1); + int32_t res_14 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = (uint64_t)((int32_t)res_14); + super::template write_mem(traits::RES, offs, (uint8_t)- 1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SCW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {aq}, {rl}", fmt::arg("mnemonic", "scw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", name(aq)), fmt::arg("rl", name(rl))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint8_t res_15 = super::template read_mem(traits::RES, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_15; + if(res1 != 0) { + super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = res1? 0 : 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOSWAPW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoswapw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint64_t res = *(X+rs2); + if(rd != 0) { + int32_t res_16 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = (uint64_t)((int32_t)res_16); + } + super::template write_mem(traits::MEM, offs, (uint32_t)res); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOADDW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoaddw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + int32_t res_17 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int32_t res1 = (int32_t)res_17; + int64_t res2 = (int64_t)(res1) + (int64_t)((int32_t)*(X+rs2)); + if(rd != 0) { + *(X+rd) = (uint64_t)res1; + } + super::template write_mem(traits::MEM, offs, (uint32_t)res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOXORW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoxorw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint32_t res_18 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_18; + uint32_t res2 = res1 ^ (uint32_t)*(X+rs2); + if(rd != 0) { + *(X+rd) = ((uint64_t)(int64_t)(int32_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOANDW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoandw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint32_t res_19 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_19; + uint32_t res2 = res1 & (uint32_t)*(X+rs2); + if(rd != 0) { + *(X+rd) = ((uint64_t)(int64_t)(int32_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOORW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoorw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint32_t res_20 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_20; + uint32_t res2 = res1 | (uint32_t)*(X+rs2); + if(rd != 0) { + *(X+rd) = ((uint64_t)(int64_t)(int32_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMINW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amominw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + int32_t res_21 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int32_t res1 = (int32_t)res_21; + uint32_t res2 = res1 > (int32_t)*(X+rs2)? (uint32_t)*(X+rs2) : ((uint32_t)res1); + if(rd != 0) { + *(X+rd) = (uint64_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMAXW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + int32_t res_22 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int32_t res1 = (int32_t)res_22; + uint32_t res2 = res1 < (int32_t)*(X+rs2)? (uint32_t)*(X+rs2) : ((uint32_t)res1); + if(rd != 0) { + *(X+rd) = (uint64_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMINUW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amominuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint32_t res_23 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_23; + uint32_t res2 = res1 > (uint32_t)*(X+rs2)? (uint32_t)*(X+rs2) : res1; + if(rd != 0) { + *(X+rd) = ((uint64_t)(int64_t)(int32_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMAXUW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint32_t res_24 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t res1 = res_24; + uint32_t res2 = res1 < (int32_t)*(X+rs2)? (uint32_t)*(X+rs2) : res1; + if(rd != 0) { + *(X+rd) = ((uint64_t)(int64_t)(int32_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LRD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "lrd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + uint64_t offs = *(X+rs1); + int64_t res_25 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = (uint64_t)((int64_t)res_25); + super::template write_mem(traits::RES, offs, (uint8_t)- 1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SCD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "scd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint8_t res_26 = super::template read_mem(traits::RES, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res = res_26; + if(res != 0) { + super::template write_mem(traits::MEM, offs, *(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = res? 0 : 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOSWAPD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoswapd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint64_t res = *(X+rs2); + if(rd != 0) { + int64_t res_27 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = (uint64_t)((int64_t)res_27); + } + super::template write_mem(traits::MEM, offs, (uint64_t)res); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOADDD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoaddd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint64_t res_28 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res1 = res_28; + uint64_t res2 = (uint64_t)((uint128_t)(res1) + (uint128_t)(*(X+rs2))); + if(rd != 0) { + *(X+rd) = (uint64_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOXORD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoxord"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint64_t res_29 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res1 = res_29; + uint64_t res2 = res1 ^ *(X+rs2); + if(rd != 0) { + *(X+rd) = ((uint64_t)(int64_t)res1); + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOANDD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoandd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint64_t res_30 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res1 = res_30; + uint64_t res2 = res1 & *(X+rs2); + if(rd != 0) { + *(X+rd) = (uint64_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOORD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoord"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint64_t res_31 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res1 = res_31; + uint64_t res2 = res1 | *(X+rs2); + if(rd != 0) { + *(X+rd) = (uint64_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMIND: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomind"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + int64_t res_32 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int64_t res1 = (int64_t)res_32; + uint64_t res2 = res1 > (int64_t)*(X+rs2)? (uint64_t)*(X+rs2) : ((uint64_t)res1); + if(rd != 0) { + *(X+rd) = (uint64_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMAXD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + int64_t res_33 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int64_t res1 = (int64_t)res_33; + uint64_t res2 = res1 < (int64_t)*(X+rs2)? (uint64_t)*(X+rs2) : ((uint64_t)res1); + if(rd != 0) { + *(X+rd) = (uint64_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMINUD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amominud"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint64_t res_34 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res1 = res_34; + uint64_t res2 = res1 > *(X+rs2)? *(X+rs2) : res1; + if(rd != 0) { + *(X+rd) = (uint64_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AMOMAXUD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxud"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = *(X+rs1); + uint64_t res_35 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res1 = res_35; + uint64_t res2 = res1 < *(X+rs2)? (uint64_t)*(X+rs2) : res1; + if(rd != 0) { + *(X+rd) = (uint64_t)res1; + } + super::template write_mem(traits::MEM, offs, res2); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ADDI4SPN: { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"), + fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(imm) { + *(X+rd + 8) = (uint64_t)((uint128_t)(*(X+2)) + (uint128_t)(imm)); + } + else { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__LW: { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1 + 8)) + (uint128_t)(uimm)); + int32_t res_36 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd + 8) = (uint64_t)(int32_t)res_36; + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__LD: { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm},({rs1})", fmt::arg("mnemonic", "c.ld"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1 + 8)) + (uint128_t)(uimm)); + uint64_t res_37 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd + 8) = (uint64_t)res_37; + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SW: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1 + 8)) + (uint128_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2 + 8)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SD: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm},({rs1})", fmt::arg("mnemonic", "c.sd"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1 + 8)) + (uint128_t)(uimm)); + super::template write_mem(traits::MEM, offs, *(X+rs2 + 8)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ADDI: { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rs1 != 0) { + *(X+rs1) = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int8_t)sext<6>(imm))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__NOP: { + uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "c.nop"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ADDIW: { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addiw"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs1 >= traits::RFS || rs1 == 0) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rs1 != 0) { + int32_t res = (int32_t)((int64_t)((int32_t)*(X+rs1)) + (int64_t)((int8_t)sext<6>(imm))); + *(X+rs1) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__LI: { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((int8_t)sext<6>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__LUI: { + uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(imm == 0 || rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + if(rd != 0) { + *(X+rd) = (uint64_t)((int32_t)sext<18>(imm)); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ADDI16SP: { + uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"), + fmt::arg("nzimm", nzimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(nzimm) { + *(X+2) = (uint64_t)((uint128_t)(*(X+2)) + (int128_t)((int16_t)sext<10>(nzimm))); + } + else { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::__reserved_clui: { + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = ".reserved_clui"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SRLI: { + uint8_t nzuimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("nzuimm", nzuimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rs1 + 8) = *(X+rs1 + 8) >> nzuimm; + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SRAI: { + uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rs1 + 8) = (uint64_t)(((int64_t)*(X+rs1 + 8)) >> shamt); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ANDI: { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rs1 + 8) = (uint64_t)(*(X+rs1 + 8) & (int64_t)((int8_t)sext<6>(imm))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SUB: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rd + 8) = (uint64_t)((uint128_t)(*(X+rd + 8)) - (uint128_t)(*(X+rs2 + 8))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__XOR: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rd + 8) = *(X+rd + 8) ^ *(X+rs2 + 8); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__OR: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rd + 8) = *(X+rd + 8) | *(X+rs2 + 8); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__AND: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *(X+rd + 8) = *(X+rd + 8) & *(X+rs2 + 8); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SUBW: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rd}, {rs2}", fmt::arg("mnemonic", "c.subw"), + fmt::arg("rd", name(8+rd)), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + int32_t res = (int32_t)((int64_t)((int32_t)*(X+rd + 8)) - (int64_t)((int32_t)*(X+rs2 + 8))); + *(X+rd + 8) = (uint64_t)res; + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ADDW: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rd}, {rs2}", fmt::arg("mnemonic", "c.addw"), + fmt::arg("rd", name(8+rd)), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + int32_t res = (int32_t)((int64_t)((int32_t)*(X+rd + 8)) + (int64_t)((int32_t)*(X+rs2 + 8))); + *(X+rd + 8) = (uint64_t)res; + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__J: { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"), + fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + *NEXT_PC = (uint64_t)((uint128_t)(*PC) + (int128_t)((int16_t)sext<12>(imm))); + this->core.reg.last_branch = 1; + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__BEQZ: { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(*(X+rs1 + 8) == 0) { + *NEXT_PC = (uint64_t)((uint128_t)(*PC) + (int128_t)((int16_t)sext<9>(imm))); + this->core.reg.last_branch = 1; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__BNEZ: { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(*(X+rs1 + 8) != 0) { + *NEXT_PC = (uint64_t)((uint128_t)(*PC) + (int128_t)((int16_t)sext<9>(imm))); + this->core.reg.last_branch = 1; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SLLI: { + uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rs1 != 0) { + *(X+rs1) = *(X+rs1) << shamt; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__LWSP: { + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rd >= traits::RFS || rd == 0) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint64_t)((uint128_t)(*(X+2)) + (uint128_t)(uimm)); + int32_t res_38 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = (uint64_t)(int32_t)res_38; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__LDSP: { + uint16_t uimm = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm}(sp)", fmt::arg("mnemonic", "c.ldsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rd >= traits::RFS || rd == 0) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint64_t)((uint128_t)(*(X+2)) + (uint128_t)(uimm)); + uint64_t res_39 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res = (uint64_t)res_39; + *(X+rd) = res; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__MV: { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__JR: { + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"), + fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs1 && rs1 < traits::RFS) { + uint64_t addr_mask = (uint64_t)- 2; + *NEXT_PC = *(X+(uint32_t)(rs1) % traits::RFS) & addr_mask; + this->core.reg.last_branch = 1; + } + else { + raise(0, 2); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::__reserved_cmv: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = ".reserved_cmv"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + raise(0, 2); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__ADD: { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)((uint128_t)(*(X+rd)) + (uint128_t)(*(X+rs2))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__JALR: { + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"), + fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t addr_mask = (uint64_t)- 2; + uint64_t new_pc = *(X+rs1); + *(X+1) = (uint64_t)((uint128_t)(*PC) + (uint128_t)(2)); + *NEXT_PC = new_pc & addr_mask; + this->core.reg.last_branch = 1; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__EBREAK: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "c.ebreak"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + raise(0, 3); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SWSP: { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint64_t)((uint128_t)(*(X+2)) + (uint128_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__SDSP: { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint16_t uimm = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm}(sp)", fmt::arg("mnemonic", "c.sdsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + if(rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint64_t)((uint128_t)(*(X+2)) + (uint128_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint64_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::DII: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "dii"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "flw"), + fmt::arg("rd", fname(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint32_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + uint32_t res_40 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(F+rd) = NaNBox32(res_40); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSW: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "fsw"), + fmt::arg("rs2", fname(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint32_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, offs, (uint32_t)*(F+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FADD__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fadd_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSUB__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fsub_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMUL__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fmul.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fmul_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FDIV__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fdiv.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fdiv_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMIN__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmin.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fsel_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), 0)); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMAX__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmax.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fsel_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), 1)); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSQRT__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fsqrt.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fsqrt_s(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMADD__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fmadd_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), unbox_s(traits::FLEN, *(F+rs3)), 0, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMSUB__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fmadd_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), unbox_s(traits::FLEN, *(F+rs3)), 1, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FNMADD__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fmadd_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), unbox_s(traits::FLEN, *(F+rs3)), 2, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FNMSUB__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(fmadd_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), unbox_s(traits::FLEN, *(F+rs3)), 3, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__W__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.w.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int64_t res = (int64_t)(int32_t)f32toi32(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__WU__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.wu.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int64_t res = (int64_t)(int32_t)f32toui32(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__L__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.l.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int64_t res = (int64_t)(int64_t)f32toi64(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__LU__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.lu.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = f32toui64(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__S__W: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.w"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox32(i32tof32((uint32_t)*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__S__WU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.wu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox32(ui32tof32((uint32_t)*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__S__L: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.l"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox32(i64tof32(*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__S__LU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.lu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox32(ui64tof32(*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJ__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnj.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(((uint32_t)bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2)))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1)))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJN__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjn.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& (1ULL << 0)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1)))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJX__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjx.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32((unbox_s(traits::FLEN, *(F+rs2)) & ((uint32_t)1 << 31)) ^ unbox_s(traits::FLEN, *(F+rs1))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMV__X__W: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.x.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)(int64_t)(int32_t)*(F+rs1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMV__W__X: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.w.x"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox32((uint32_t)*(X+rs1)); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FEQ__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "feq.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res = fcmp_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), 0); + if(rd != 0) { + *(X+rd) = res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLT__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "flt.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res = fcmp_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), 2); + if(rd != 0) { + *(X+rd) = res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLE__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fle.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res = fcmp_s(unbox_s(traits::FLEN, *(F+rs1)), unbox_s(traits::FLEN, *(F+rs2)), 1); + if(rd != 0) { + *(X+rd) = res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCLASS__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fclass.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint32_t res = fclass_s(unbox_s(traits::FLEN, *(F+rs1))); + if(rd != 0) { + *(X+rd) = res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "fld"), + fmt::arg("rd", fname(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + uint64_t res_41 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(F+rd) = NaNBox64(res_41); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSD: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "fsd"), + fmt::arg("rs2", fname(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1)) + (int128_t)((int16_t)sext<12>(imm))); + super::template write_mem(traits::MEM, offs, (uint64_t)*(F+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FADD__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSUB__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fsub_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMUL__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fmul.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fmul_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FDIV__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fdiv.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fdiv_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMIN__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmin.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fsel_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), 0)); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMAX__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmax.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fsel_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), 1)); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSQRT__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fsqrt.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fsqrt_d(unbox_d(traits::FLEN, *(F+rs1)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMADD__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 0, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMSUB__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint64_t res = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm))); + *(F+rd) = res; + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FNMADD__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 2, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FNMSUB__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 3, get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__W__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.w.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int64_t res = (int64_t)(int32_t)f64toi32(unbox_d(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__WU__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.wu.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int64_t res = (int64_t)(int32_t)f64toui32(unbox_d(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__L__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.l.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + int64_t res = (int64_t)(int64_t)f64toi64(unbox_d(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__LU__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.lu.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = f64toui64(unbox_d(traits::FLEN, *(F+rs1)), get_rm(rm)); + if(rd != 0) { + *(X+rd) = res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__D__W: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.w"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox64(i32tof64((uint32_t)*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__D__WU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.wu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox64(ui32tof64((uint32_t)*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__D__L: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.l"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox64(i64tof64(*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__D__LU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.lu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox64(ui64tof64(*(X+rs1), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__S__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox32(f64tof32(unbox_d(traits::FLEN, *(F+rs1)), get_rm(rm))); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCVT__D__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(f32tof64(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJ__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnj.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(((uint64_t)bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2)))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1)))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJN__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjn.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& (1ULL << 0)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1)))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FSGNJX__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjx.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + *(F+rd) = NaNBox64((unbox_d(traits::FLEN, *(F+rs2)) & ((uint64_t)1 << 63)) ^ unbox_d(traits::FLEN, *(F+rs1))); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMV__X__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.x.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = (uint64_t)(int64_t)(int64_t)*(F+rs1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FMV__D__X: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.d.x"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = NaNBox64((uint64_t)*(X+rs1)); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FEQ__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "feq.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = fcmp_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), 0); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLT__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "flt.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = fcmp_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), 2); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FLE__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fle.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = fcmp_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), 1); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FCLASS__D: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fclass.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t res = fclass_d(unbox_d(traits::FLEN, *(F+rs1))); + if(rd != 0) { + *(X+rd) = (uint64_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FLD: { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rd}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fld"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1 + 8)) + (uint128_t)(uimm)); + uint64_t res_42 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res = (uint64_t)res_42; + *(F+rd + 8) = NaNBox64(res); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FSD: { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rs2}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fsd"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint64_t offs = (uint64_t)((uint128_t)(*(X+rs1 + 8)) + (uint128_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint64_t)*(F+rs2 + 8)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FLDSP: { + uint16_t uimm = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f {rd}, {uimm}(x2)", fmt::arg("mnemonic", "c.fldsp"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint64_t offs = (uint64_t)((uint128_t)(*(X+2)) + (uint128_t)(uimm)); + uint64_t res_43 = super::template read_mem(traits::MEM, offs); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint64_t res = (uint64_t)res_43; + *(F+rd) = NaNBox64(res); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::C__FSDSP: { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint16_t uimm = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} f {rs2}, {uimm}(x2), ", fmt::arg("mnemonic", "c.fsdsp"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 2; + // execute instruction + { + uint64_t offs = (uint64_t)((uint128_t)(*(X+2)) + (uint128_t)(uimm)); + super::template write_mem(traits::MEM, offs, (uint64_t)*(F+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SFENCE__VMA: { + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t asid = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {asid}", fmt::arg("mnemonic", "sfence.vma"), + fmt::arg("rs1", name(rs1)), fmt::arg("asid", name(asid))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fencevma, ((uint16_t)(uint8_t)rs1<<8)|(uint8_t)asid); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRET: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + //No disass specified, using instruction name + std::string mnemonic = "sret"; + this->core.disass_output(pc.val, mnemonic); + } + // used registers + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + leave(1); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSETVLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t lmul = ((bit_sub<20,3>(instr))); + uint8_t sew = ((bit_sub<23,3>(instr))); + uint8_t ta = ((bit_sub<26,1>(instr))); + uint8_t ma = ((bit_sub<27,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {sew}, {lmul}, {ta}, {ma}", fmt::arg("mnemonic", "vsetvli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("sew", sew_name(sew)), fmt::arg("lmul", lmul_name(lmul)), fmt::arg("ta", ta_name(ta)), fmt::arg("ma", ma_name(ma))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t orig_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow()); + uint64_t orig_vstart = *vstart; + *vstart = 0; + *vtype = (uint64_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul); + if(! valid_sew_lmul()) { + handle_illegal_vtype(); + *vstart = orig_vstart; + } + else { + uint16_t VLMAX = (uint16_t)(1 << ((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow()))) & ~1; + if(rs1 != 0) { + uint64_t AVL = *(X+rs1); + *vl = (uint64_t)calculate_new_vl(AVL, VLMAX); + if(rd != 0) { + *(X+rd) = *vl; + } + } + else { + if(rd != 0) { + *vl = VLMAX; + *(X+rd) = (uint64_t)VLMAX; + } + else { + uint8_t new_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow()); + if(orig_ratio != new_ratio) { + handle_illegal_vtype(); + *vstart = orig_vstart; + } + } + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSETIVLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t uimm = ((bit_sub<15,5>(instr))); + uint8_t lmul = ((bit_sub<20,3>(instr))); + uint8_t sew = ((bit_sub<23,3>(instr))); + uint8_t ta = ((bit_sub<26,1>(instr))); + uint8_t ma = ((bit_sub<27,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm}, {sew}, {lmul}, {ta}, {ma}", fmt::arg("mnemonic", "vsetivli"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm), fmt::arg("sew", sew_name(sew)), fmt::arg("lmul", lmul_name(lmul)), fmt::arg("ta", ta_name(ta)), fmt::arg("ma", ma_name(ma))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *vtype = (uint64_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul); + if(! valid_sew_lmul()) { + handle_illegal_vtype(); + } + else { + uint16_t VLMAX = (uint16_t)(1 << ((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow()))) & ~1; + *vl = calculate_new_vl(uimm, VLMAX); + *(X+rd) = *vl; + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSETVL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "vsetvl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t orig_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow()); + uint64_t orig_vstart = *vstart; + *vstart = 0; + if(bit_sub(*(X+rs2), 8, ((uint64_t)(traits::XLEN) - (uint64_t)(2))-8+1)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + *vtype = *(X+rs2); + if(! valid_sew_lmul()) { + handle_illegal_vtype(); + *vstart = orig_vstart; + } + else { + uint16_t VLMAX = (uint16_t)(1 << ((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow()))) & ~1; + if(rs1 != 0) { + uint64_t AVL = *(X+rs1); + *vl = (uint64_t)calculate_new_vl(AVL, VLMAX); + if(rd != 0) { + *(X+rd) = *vl; + } + } + else { + if(rd != 0) { + *vl = VLMAX; + *(X+rd) = (uint64_t)VLMAX; + } + else { + uint8_t new_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow()); + uint8_t vill = bit_sub(*vtype, (uint64_t)(traits::XLEN) - (uint64_t)(1), 1); + if(vill || (orig_ratio != new_ratio)) { + handle_illegal_vtype(); + *vstart = orig_vstart; + } + } + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSE8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSE16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSE32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG2E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG2E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG2E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG2E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG3E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG3E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG3E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG3E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG4E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG4E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG4E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG4E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG5E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG5E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG5E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG5E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG6E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG6E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG6E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG6E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG7E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG7E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG7E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG7E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG8E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG8E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG8E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSEG8E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG2E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG2E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG2E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG2E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG3E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG3E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG3E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG3E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG4E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG4E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG4E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG4E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG5E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG5E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG5E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG5E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG6E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG6E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG6E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG6E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG7E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG7E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG7E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG7E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG8E8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG8E16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG8E32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSSEG8E64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSE8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSE16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSE32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG2E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG2E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG2E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG2E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG3E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG3E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG3E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG3E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG4E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG4E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG4E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG4E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG5E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG5E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG5E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG5E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG6E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG6E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG6E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG6E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG7E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG7E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG7E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG7E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG8E8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG8E16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG8E32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSSEG8E64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_store(8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8, (int64_t)*(X+rs2)); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLE64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 1, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG2E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 2, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG3E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 3, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG4E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 4, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG5E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 5, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG6E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 6, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG7E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 7, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E8FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E16FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E32FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLSEG8E64FF__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_load(vd, vm, 8, EEW, EMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); + if(trapped_idx != 1) { + *vl = (uint64_t)trapped_idx; + lower(); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSM__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {vs3}", fmt::arg("mnemonic", "vsm.v"), + fmt::arg("rs1", name(rs1)), fmt::arg("vs3", vname(vs3))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = *vl % (uint64_t)(8) == 0? *vl / (uint64_t)(8) : (uint64_t)((uint128_t)(*vl / (uint64_t)(8)) + (uint128_t)(1)); + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + uint64_t _vtype = (bit_sub(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint64_t)1<<6)|((uint64_t)0<<3)|bit_sub<0, 2-0+1>(*vtype); + *vstart = (uint64_t)vsseg((uint8_t*)V, evl, *vstart, _vtype, 1, vs3, *(X+rs1), 0, 1); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLM__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {vd}", fmt::arg("mnemonic", "vlm.v"), + fmt::arg("rs1", name(rs1)), fmt::arg("vd", vname(vd))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = *vl % (uint64_t)(8) == 0? *vl / (uint64_t)(8) : (uint64_t)((uint128_t)(*vl / (uint64_t)(8)) + (uint128_t)(1)); + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + uint64_t _vtype = (bit_sub(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint64_t)1<<6)|((uint64_t)0<<3)|bit_sub<0, 2-0+1>(*vtype); + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, _vtype, 1, vd, *(X+rs1), 0, 1); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL1RE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL1RE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(16)); + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL1RE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(32)); + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL1RE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(64)); + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL2RE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(2) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vd % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL2RE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(2) * (uint64_t)(traits::VLEN) / (uint64_t)(16)); + if(vd % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL2RE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(2) * (uint64_t)(traits::VLEN) / (uint64_t)(32)); + if(vd % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL2RE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(2) * (uint64_t)(traits::VLEN) / (uint64_t)(64)); + if(vd % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL4RE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(4) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vd % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL4RE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(4) * (uint64_t)(traits::VLEN) / (uint64_t)(16)); + if(vd % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL4RE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(4) * (uint64_t)(traits::VLEN) / (uint64_t)(32)); + if(vd % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL4RE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(4) * (uint64_t)(traits::VLEN) / (uint64_t)(64)); + if(vd % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL8RE8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(8) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vd % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL8RE16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(8) * (uint64_t)(traits::VLEN) / (uint64_t)(16)); + if(vd % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL8RE32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(8) * (uint64_t)(traits::VLEN) / (uint64_t)(32)); + if(vd % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VL8RE64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(8) * (uint64_t)(traits::VLEN) / (uint64_t)(64)); + if(vd % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VS1RE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs1re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(evl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VS2RE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs2re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(2) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vs3 % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VS4RE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs4re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(4) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vs3 % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VS8RE64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs8re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint64_t evl = (uint64_t)((uint64_t)(8) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); + if(vs3 % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(evl > *vstart) { + *vstart = (uint64_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXEI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXEI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXEI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXEI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG2EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG2EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG2EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG2EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG3EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG3EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG3EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG3EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG4EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG4EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG4EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG4EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG5EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG5EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG5EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG5EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG6EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG6EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG6EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG6EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG7EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG7EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG7EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG7EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG8EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG8EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG8EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLOXSEG8EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXEI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXEI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXEI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXEI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG2EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG2EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG2EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG2EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG3EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG3EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG3EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG3EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG4EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG4EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG4EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG4EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG5EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG5EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG5EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG5EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG6EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG6EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG6EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG6EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG7EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG7EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG7EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG7EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG8EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG8EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG8EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSOXSEG8EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 1); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXEI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXEI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXEI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXEI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG2EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG2EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG2EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG2EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG3EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG3EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG3EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG3EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG4EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG4EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG4EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG4EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG5EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG5EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG5EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG5EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG6EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG6EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG6EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG6EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG7EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG7EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG7EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG7EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG8EI8__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG8EI16__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG8EI32__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VLUXSEG8EI64__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_load(vd, vm, 8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXEI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXEI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXEI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXEI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(1, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG2EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG2EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG2EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG2EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(2, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG3EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG3EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG3EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG3EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(3, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG4EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG4EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG4EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG4EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(4, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG5EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG5EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG5EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG5EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(5, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG6EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG6EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG6EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG6EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(6, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG7EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG7EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG7EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG7EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(7, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG8EI8__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 8; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG8EI16__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 16; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG8EI32__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 32; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUXSEG8EI64__V: { + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t EEW = 64; + int8_t EMUL_pow = (int8_t)sext<3>(((uint16_t)(get_pow(EEW)) - (uint16_t)(get_sew_pow()) + (int16_t)(get_lmul_pow()))); + if(illegal_indexed_store(8, EEW, EMUL_pow, get_lmul_pow())) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 0); + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADD__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vadd.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 0, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 0, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADD__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 0, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 2, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 2, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRSUB__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vrsub.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 3, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRSUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 3, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADDU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 48, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADDU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 48, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUBU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 50, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUBU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 50, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 49, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADD__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 49, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 51, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 51, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADDU__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwaddu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_ww((uint8_t*)V, 52, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADDU__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwaddu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_ww((uint8_t*)V, 52, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUBU__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsubu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_ww((uint8_t*)V, 54, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUBU__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsubu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_ww((uint8_t*)V, 54, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADD__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwadd.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_ww((uint8_t*)V, 53, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWADD__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwadd.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_ww((uint8_t*)V, 53, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUB__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsub.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_ww((uint8_t*)V, 55, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWSUB__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsub.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_ww((uint8_t*)V, 55, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VZEXT__VF2: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf2"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 2; + int8_t LMUL_pow_target = LMUL_pow - 1; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 6, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSEXT__VF2: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf2"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 2; + int8_t LMUL_pow_target = LMUL_pow - 1; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 7, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VZEXT__VF4: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf4"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 4; + int8_t LMUL_pow_target = LMUL_pow - 2; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 4, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 2); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSEXT__VF4: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf4"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 4; + int8_t LMUL_pow_target = LMUL_pow - 2; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 5, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 2); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VZEXT__VF8: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf8"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 8; + int8_t LMUL_pow_target = LMUL_pow - 3; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 2, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 3); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSEXT__VF8: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf8"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW_pow = get_sew_pow(); + uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_target = SEW / 8; + int8_t LMUL_pow_target = LMUL_pow - 3; + if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_extend((uint8_t*)V, 3, *vl, *vstart, *vtype, vm, vd, vs2, SEW_pow, 3); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADC__VVM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vadc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_carry((uint8_t*)V, 16, 0, *vl, *vstart, *vtype, vd, vs2, vs1, sew(), 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADC__VXM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vadc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_carry((uint8_t*)V, 16, 4, *vl, *vstart, *vtype, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew(), 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VADC__VIM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, v0", fmt::arg("mnemonic", "vadc.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_carry((uint8_t*)V, 16, 3, *vl, *vstart, *vtype, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew(), 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VVM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vmadc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_vector_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 0, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VXM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vmadc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 0, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VIM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, v0", fmt::arg("mnemonic", "vmadc.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 0, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmadc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_vector_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 1, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmadc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 1, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADC__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}", fmt::arg("mnemonic", "vmadc.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 17, *vl, *vstart, *vtype, 1, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSBC__VVM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vsbc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_carry((uint8_t*)V, 18, 0, *vl, *vstart, *vtype, vd, vs2, vs1, sew(), - 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSBC__VXM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vsbc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_carry((uint8_t*)V, 18, 4, *vl, *vstart, *vtype, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew(), - 1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSBC__VVM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vmsbc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_vector_op((uint8_t*)V, 19, *vl, *vstart, *vtype, 0, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSBC__VXM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vmsbc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 19, *vl, *vstart, *vtype, 0, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSBC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmsbc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_vector_op((uint8_t*)V, 19, *vl, *vstart, *vtype, 1, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSBC__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmsbc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + carry_vector_imm_op((uint8_t*)V, 19, *vl, *vstart, *vtype, 1, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAND__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vand.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 9, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAND__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vand.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 9, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAND__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vand.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 9, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VOR__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vor.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 10, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VOR__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vor.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 10, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VOR__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vor.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 10, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VXOR__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vxor.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 11, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VXOR__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vxor.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 11, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VXOR__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vxor.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 11, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLL__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsll.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 37, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(uint64_t)imm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsll.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 37, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsll.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 37, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(uint64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRL__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsrl.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 40, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(uint64_t)imm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsrl.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 40, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsrl.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 40, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(uint64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRA__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsra.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 41, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(uint64_t)imm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRA__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsra.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 41, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSRA__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsra.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 41, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(uint64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRL__WI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnsrl.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_vw((uint8_t*)V, 44, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(uint64_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRL__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnsrl.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_vw((uint8_t*)V, 44, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRL__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnsrl.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_vw((uint8_t*)V, 44, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(uint64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRA__WI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnsra.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_vw((uint8_t*)V, 45, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(uint64_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRA__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnsra.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_vw((uint8_t*)V, 45, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNSRA__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnsra.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_vw((uint8_t*)V, 45, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(uint64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSEQ__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmseq.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 24, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSEQ__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmseq.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 24, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSEQ__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmseq.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 24, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSNE__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsne.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 25, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSNE__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsne.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 25, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSNE__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsne.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 25, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLTU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsltu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 26, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLTU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsltu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 26, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLT__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmslt.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 27, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLT__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmslt.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 27, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLEU__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsleu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 28, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLEU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsleu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 28, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLEU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsleu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 28, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLE__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsle.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 29, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLE__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsle.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_vector_op((uint8_t*)V, 29, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSLE__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsle.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 29, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSGTU__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsgtu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 30, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSGTU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsgtu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 30, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSGT__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsgt.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 31, 3, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSGT__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsgt.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_vector_imm_op((uint8_t*)V, 31, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMINU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vminu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 4, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMINU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vminu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 4, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMIN__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmin.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 5, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMIN__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmin.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 5, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMAXU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmaxu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 6, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMAXU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmaxu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 6, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMAX__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmax.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 7, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMAX__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmax.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 7, 4, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMUL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 37, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMUL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 37, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULH__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulh.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 39, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULH__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulh.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 39, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULHU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulhu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 36, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULHU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulhu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 36, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULHSU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulhsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 38, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMULHSU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulhsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 38, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VDIVU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vdivu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 32, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VDIVU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vdivu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 32, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VDIV__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vdiv.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 33, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VDIV__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vdiv.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 33, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREMU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vremu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 34, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREMU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vremu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 34, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREM__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrem.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 35, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREM__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrem.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 35, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMUL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 59, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMUL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 59, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMULU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmulu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 56, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMULU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmulu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 56, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMULSU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmulsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 58, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMULSU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmulsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 58, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 45, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMACC__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmacc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 45, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNMSAC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 47, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNMSAC__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnmsac.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 47, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 41, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMADD__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 41, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNMSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_op((uint8_t*)V, 43, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNMSUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnmsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_op((uint8_t*)V, 43, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACCU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmaccu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 60, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACCU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 60, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 61, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACC__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmacc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 61, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACCSU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmaccsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_wv((uint8_t*)V, 63, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACCSU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 63, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWMACCUS__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccus.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & (~1)& (1ULL << 4); + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)(SEW * 2); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_wv((uint8_t*)V, 62, 6, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMERGE__VIM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}", fmt::arg("mnemonic", "vmerge.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 0, vd, vs2, (uint64_t)(int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMERGE__VVM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmerge.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_merge((uint8_t*)V, *vl, *vstart, *vtype, 0, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMERGE__VXM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmerge.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_masked(vd)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 0, vd, vs2, (uint64_t)(int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV__V__I: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {simm}", fmt::arg("mnemonic", "vmv.v.i"), + fmt::arg("vd", vname(vd)), fmt::arg("simm", simm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 1, vd, 0, (uint64_t)(int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV__V__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs1}", fmt::arg("mnemonic", "vmv.v.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_vector_merge((uint8_t*)V, *vl, *vstart, *vtype, 1, vd, 0, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV__V__X: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vmv.v.x"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 1, vd, 0, (uint64_t)(int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADDU__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vsaddu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 32, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADDU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_op((uint8_t*)V, 32, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADDU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 32, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADD__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vsadd.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 33, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int8_t)sext<5>(simm), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_op((uint8_t*)V, 33, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSADD__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 33, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSUBU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_op((uint8_t*)V, 34, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSUBU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 34, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_op((uint8_t*)V, 35, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 35, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAADDU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vaaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 8, 2, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAADDU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vaaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 8, 6, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vaadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 9, 2, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VAADD__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vaadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 9, 6, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VASUBU__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vasubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 10, 2, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VASUBU__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vasubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 10, 6, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VASUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vasub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 11, 2, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VASUB__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vasub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 11, 6, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSMUL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_op((uint8_t*)V, 39, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSMUL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_op((uint8_t*)V, 39, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRL__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vssrl.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 42, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(uint64_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssrl.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 42, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRL__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssrl.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 42, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(uint64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRA__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vssra.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 43, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(uint64_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRA__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssra.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_vector_op((uint8_t*)V, 43, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSSRA__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssra.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + sat_vector_imm_op((uint8_t*)V, 43, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(uint64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIPU__WI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnclipu.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_vw((uint8_t*)V, 46, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(uint64_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIPU__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnclipu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_vw((uint8_t*)V, 46, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIPU__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnclipu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_vw((uint8_t*)V, 46, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(uint64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIP__WI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnclip.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_vw((uint8_t*)V, 47, 3, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(uint64_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIP__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnclip.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_vector_vw((uint8_t*)V, 47, 0, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VNCLIP__WX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnclip.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vxsat = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxsat]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vxrm = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vxrm]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! (valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + *vxsat |= sat_vector_imm_vw((uint8_t*)V, 47, 4, *vl, *vstart, *vtype, *vxrm, vm, vd, vs2, (int64_t)(uint64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredsum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 0, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDMAXU__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmaxu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 6, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDMAX__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmax.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 7, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDMINU__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredminu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 4, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDMIN__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmin.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 5, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDAND__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredand.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 1, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDOR__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredor.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 2, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VREDXOR__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredxor.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_reduction()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_op((uint8_t*)V, 3, 2, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWREDSUMU__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwredsumu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_reduction_widen(SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_wv((uint8_t*)V, 48, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VWREDSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwredsum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + if(illegal_reduction_widen(SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_red_wv((uint8_t*)V, 49, 0, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFREDOSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredosum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_op((uint8_t*)V, 3, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFREDUSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredusum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_op((uint8_t*)V, 1, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFREDMAX__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredmax.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_op((uint8_t*)V, 7, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFREDMIN__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredmin.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_op((uint8_t*)V, 5, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWREDOSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwredosum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_wv((uint8_t*)V, 51, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWREDUSUM__VS: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwredusum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_reduction(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_red_wv((uint8_t*)V, 49, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMAND__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmand.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 25, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMNAND__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmnand.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 29, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMANDN__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmandn.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 24, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMXOR__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmxor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 27, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMOR__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 26, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMNOR__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmnor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 30, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMORN__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmorn.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 28, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMXNOR__MM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmxnor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_mask_op((uint8_t*)V, 31, 2, *vl, *vstart, vd, vs2, vs1); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VCPOP__M: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}, {vm},", fmt::arg("mnemonic", "vcpop.m"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || illegal_vd_unmasked() || *vstart != 0) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = vcpop((uint8_t*)V, *vl, *vstart, vm, vs2); + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFIRST__M: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}, {vm},", fmt::arg("mnemonic", "vfirst.m"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || illegal_vd_unmasked() || *vstart != 0) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = vfirst((uint8_t*)V, *vl, *vstart, vm, vs2); + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSBF__M: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsbf.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked() || *vstart != 0 || vd == vs2 || (vm && vd == 0)) { + raise(0, 2); + } + else { + mask_set_op((uint8_t*)V, 1, *vl, *vstart, vm, vd, vs2); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSIF__M: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsif.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked() || *vstart != 0 || vd == vs2 || (vm && vd == 0)) { + raise(0, 2); + } + else { + mask_set_op((uint8_t*)V, 3, *vl, *vstart, vm, vd, vs2); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMSOF__M: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsof.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked() || *vstart != 0 || vd == vs2 || (vm && vd == 0)) { + raise(0, 2); + } + else { + mask_set_op((uint8_t*)V, 2, *vl, *vstart, vm, vd, vs2); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VIOTA__M: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "viota.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_vd_unmasked() || *vstart != 0 || vd == vs2 || (vm && vd == 0)) { + raise(0, 2); + } + else { + viota((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VID__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vm},", fmt::arg("mnemonic", "vid.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vid((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV__S__X: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vmv.s.x"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + scalar_to_vector((uint8_t*)V, *vtype, vd, (int64_t)(int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV__X__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}", fmt::arg("mnemonic", "vmv.x.s"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || illegal_vd_unmasked()) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(rd != 0) { + *(X+rd) = scalar_from_vector((uint8_t*)V, *vtype, vs2, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDEUP__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vslideup.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm) || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slideup((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDEUP__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslideup.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm) || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slideup((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, *(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDEDOWN__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vslidedown.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slidedown((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)simm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDEDOWN__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslidedown.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slidedown((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, *(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDE1UP__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslide1up.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm) || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slide1up((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VSLIDE1DOWN__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslide1down.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_slide1down((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, (int64_t)*(X+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRGATHER__VI: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vrgather.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm) || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_imm_gather((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)simm, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRGATHER__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrgather.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm) || vs1 == vd || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_vector_gather((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRGATHER__VX: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrgather.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs1 >= traits::RFS || illegal_normal(vd, vm) || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_imm_gather((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, *(X+rs1), sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VRGATHEREI16__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrgatherei16.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(illegal_normal(vd, vm) || vs1 == vd || vs2 == vd) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_vector_gatherei16((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, vs1, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VCOMPRESS__VM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vcompress.vm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(*vstart != 0 | vs1 == vd | vs2 == vd | illegal_vd_unmasked()) { + raise(0, 2); + } + else { + if(*vl > *vstart) { + vector_compress((uint8_t*)V, *vl, *vstart, *vtype, vd, vs2, vs1, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV1R__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv1r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + vector_whole_move((uint8_t*)V, vd, vs2, 1); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV2R__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv2r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(vd % 2 || vs2 % 2) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_whole_move((uint8_t*)V, vd, vs2, 2); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV4R__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv4r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(vd % 4 || vs2 % 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_whole_move((uint8_t*)V, vd, vs2, 4); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMV8R__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv8r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(vd % 8 || vs2 % 8) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + vector_whole_move((uint8_t*)V, vd, vs2, 8); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMV__S__F: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vfmv.s.f"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + scalar_to_vector((uint8_t*)V, *vtype, vd, (int64_t)(uint64_t)*(F+rs1), sew()); + *vstart = 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMV__F__S: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}", fmt::arg("mnemonic", "vfmv.f.s"), + fmt::arg("rd", fname(rd)), fmt::arg("vs2", vname(vs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm) || SEW > traits::FLEN) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + *(F+rd) = fp_scalar_from_vector((uint8_t*)V, *vtype, vs2, sew()); + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSLIDE1UP__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfslide1up.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_slide1up((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, *(F+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSLIDE1DOWN__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfslide1down.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_slide1down((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, vs2, *(F+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFADD__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 0, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 0, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSUB__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 2, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 2, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFRSUB__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfrsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 39, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWADD__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 48, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 48, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWSUB__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 50, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 50, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWADD__WF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwadd.wf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_ww((uint8_t*)V, 52, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWADD__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwadd.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_ww((uint8_t*)V, 52, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWSUB__WF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwsub.wf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_ww((uint8_t*)V, 54, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWSUB__WV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwsub.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_ww((uint8_t*)V, 54, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMUL__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmul.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 36, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMUL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vfmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 36, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFDIV__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfdiv.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 32, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFDIV__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vfdiv.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 32, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFRDIV__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfrdiv.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 33, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMUL__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmul.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 56, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMUL__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 56, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMACC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 44, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 44, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMACC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 45, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 45, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMSAC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 46, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMSAC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 46, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMSAC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 47, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMSAC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 47, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMADD__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 40, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 40, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMADD__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 41, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMADD__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 41, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMSUB__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 42, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 42, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMSUB__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 43, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNMSUB__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 43, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMACC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 60, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 60, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWNMACC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwnmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 61, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWNMACC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwnmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 61, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMSAC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 62, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWMSAC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 62, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWNMSAC__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwnmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_wv((uint8_t*)V, 63, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWNMSAC__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_wv((uint8_t*)V, 63, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSQRT__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfsqrt.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 19, 0, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFRSQRT7__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfrsqrt7.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 19, 4, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFREC7__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfrec7.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 19, 5, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMIN__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmin.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 4, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMIN__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmin.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 4, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMAX__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmax.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 6, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMAX__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmax.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 6, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJ__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnj.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 8, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJ__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnj.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 8, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJN__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnjn.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 9, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJN__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnjn.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 9, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJX__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnjx.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_imm_op((uint8_t*)V, 10, 5, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFSGNJX__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnjx.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_vector_op((uint8_t*)V, 10, 1, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFEQ__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfeq.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 24, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFEQ__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfeq.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_vector_op((uint8_t*)V, 24, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFNE__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfne.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 28, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFNE__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfne.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_vector_op((uint8_t*)V, 28, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFLT__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmflt.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 27, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFLT__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmflt.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_vector_op((uint8_t*)V, 27, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFLE__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfle.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 25, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFLE__VV: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfle.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_vector_op((uint8_t*)V, 25, *vl, *vstart, *vtype, vm, vd, vs2, vs1, rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFGT__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfgt.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 29, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VMFGE__VF: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfge.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + mask_fp_vector_imm_op((uint8_t*)V, 31, *vl, *vstart, *vtype, vm, vd, vs2, (uint64_t)*(F+rs1), rm, sew()); + uint32_t flags = fget_flags(); + *FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCLASS__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfclass.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 19, 16, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMERGE__VFM: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vfmerge.vfm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_masked(vd, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 0, vd, vs2, (uint64_t)*(F+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFMV__V__F: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vfmv.v.f"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", fname(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + auto* F = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::F0]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_vd_unmasked(SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + vector_imm_merge((uint8_t*)V, *vl, *vstart, *vtype, 1, vd, 0, (uint64_t)*(F+rs1), sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__XU__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 0, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__X__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 1, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__RTZ__XU__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.rtz.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = 1; + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 6, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__RTZ__X__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.rtz.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = 1; + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 7, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__F__XU__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.f.xu.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 2, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFCVT__F__X__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.f.x.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_normal(vd, vm, SEW, rm)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_op((uint8_t*)V, 18, 3, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__XU__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 8, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__X__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 9, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__RTZ__XU__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = 1; + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 14, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__RTZ__X__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = 1; + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 15, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__F__XU__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.xu.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 10, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__F__X__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.x.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 11, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFWCVT__F__F__V: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_w((uint8_t*)V, 12, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__X__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.x.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 17, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__XU__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.xu.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 16, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__RTZ__XU__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.xu.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = 1; + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 22, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__RTZ__X__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.x.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = 1; + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 23, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__F__XU__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.xu.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 18, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__F__X__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.x.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 19, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__F__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 20, *vl, *vstart, *vtype, vm, vd, vs2, rm, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::VFNCVT__ROD__F__F__W: { + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rod.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* FCSR = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::FCSR]); + auto* vl = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vl]); + auto* vstart = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vstart]); + auto* V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + auto* vtype = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::vtype]); + // calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; + int8_t LMUL_pow = get_lmul_pow(); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + int8_t LMUL_pow_widen = LMUL_pow + 1; + uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); + if(illegal_fp_variable_width(vd, vm, SEW, rm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + else { + if(*vl > *vstart) { + fp_vector_unary_n((uint8_t*)V, 21, *vl, *vstart, *vtype, vm, vd, vs2, 6, sew()); + } + *vstart = 0; + } + } + break; + }// @suppress("No break at end of case") + default: { + if(this->disass_enabled){ + std::string mnemonic = "Illegal Instruction"; + this->core.disass_output(pc.val, mnemonic); + } + *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2); + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + } + }catch(memory_access_exception& e){} + // post execution stuff + process_spawn_blocks(); + if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast(inst_id)); + // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt + // this->core.reg.trap_state = this->core.reg.pending_trap; + // trap check + if(trap_state!=0){ + //In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval) + auto mcause = (trap_state>>16) & 0xff; + super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval); + } else { + icount++; + instret++; + } + *PC = *NEXT_PC; + this->core.reg.trap_state = this->core.reg.pending_trap; + } + fetch_count++; + cycle++; + } + return pc; +} + +} // namespace rv64gcv + +template <> +std::unique_ptr create(arch::rv64gcv *core, unsigned short port, bool dump) { + auto ret = new rv64gcv::vm_impl(*core, dump); + if (port != 0) debugger::server::run_server(ret, port); + return std::unique_ptr(ret); +} +} // namespace interp +} // namespace iss + +#include +#include +#include +#include +namespace iss { +namespace { + +volatile std::array dummy = { + core_factory::instance().register_creator("rv64gcv_msu:interp", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_msu_vp(); + auto vm = new interp::rv64gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("rv64gcv_m:interp", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_m_p(); + auto vm = new interp::rv64gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("rv64gcv_mu:interp", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_mu_p(); + auto vm = new interp::rv64gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }) +}; +} +} +// clang-format on From f28f783551be231ec755925e14b349622febde73 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 16 Sep 2025 19:19:11 +0200 Subject: [PATCH 009/230] fixes wrong isa default and cleans up geneation script --- contrib/generate_custom_cores.sh | 10 ++++------ src/main.cpp | 2 +- src/sysc/core_complex.h | 2 +- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/contrib/generate_custom_cores.sh b/contrib/generate_custom_cores.sh index b7e7e72..5f4b25a 100644 --- a/contrib/generate_custom_cores.sh +++ b/contrib/generate_custom_cores.sh @@ -55,8 +55,7 @@ for core in RV32I RV32IMAC RV32GC RV64I RV64GC; do #python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow done for core in RV32GCV RV64GCV; do - echo ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b interp ${TMPL_DIR}/../../gen_input/cores.core_desc - ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b interp ${TMPL_DIR}/../../gen_input/cores.core_desc + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b interp ${TMPL_DIR}/../../gen_input/cores.core_desc #python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast #python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow done @@ -64,7 +63,6 @@ done # Generate for TGC5C core=TGC5C for backend in ${BACKENDS}; do - echo ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -c $core -b ${backend} ${CORE_DSL_DIR}/${core}.core_desc done unset core @@ -92,10 +90,10 @@ if [ $EXT_LIST -gt 0 ]; then if [ $EXT_LIST -gt 1 ]; then for core in TGC5Xe TGC5Xi TGC5Xec TGC5Xic TGC5Xem TGC5Xim TGC5Xemc TGC5Ximc; do for backend in ${BACKENDS}; do - ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -c $core -b ${backend} ${CORE_DSL_DIR}/TGC5.core_desc + ${SCRIPTDIR}/generate_iss.sh -o ${OUTPUT_ROOT} -t ${TMPL_DIR} -m src -s -c $core -b ${backend} ${CORE_DSL_DIR}/TGC5.core_desc done - python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast - python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow + #python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_fast.yaml -s fast + #python3 ${SCRIPTDIR}/update_cycle_yaml.py -i ${OUTPUT_ROOT}/contrib/instr/${core}_instr.yaml -o ${OUTPUT_ROOT}/contrib/instr/${core}_slow.yaml -s slow done fi fi \ No newline at end of file diff --git a/src/main.cpp b/src/main.cpp index 46d7347..d76f163 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -80,7 +80,7 @@ int main(int argc, char* argv[]) { ("mem,m", po::value(), "the memory input file") ("plugin,p", po::value>(), "plugin to activate") ("backend", po::value()->default_value("interp"), "the ISS backend to use, options are: interp, llvm, tcc, asmjit") - ("isa", po::value()->default_value("tgc5c"), "core or isa name to use for simulation, use '?' to get list"); + ("isa", po::value()->default_value("rv32imac_m"), "core or isa name to use for simulation, use '?' to get list"); // clang-format on auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run(); try { diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h index d9ee353..918f974 100644 --- a/src/sysc/core_complex.h +++ b/src/sysc/core_complex.h @@ -127,7 +127,7 @@ template class core_complex : public sc_core:: cci::cci_param reset_address{"reset_address", 0ULL}; - cci::cci_param core_type{"core_type", "rv32imac"}; + cci::cci_param core_type{"core_type", "rv32imac_m"}; cci::cci_param backend{"backend", "interp"}; From 2b5ace20f23e4570e4d1cba851990523dd20aa89 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Mon, 22 Sep 2025 18:57:57 +0200 Subject: [PATCH 010/230] corrects include guard for fp_functions --- src/vm/fp_functions.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vm/fp_functions.h b/src/vm/fp_functions.h index 021a91e..50a108b 100644 --- a/src/vm/fp_functions.h +++ b/src/vm/fp_functions.h @@ -32,8 +32,8 @@ // eyck@minres.com - initial API and implementation //////////////////////////////////////////////////////////////////////////////// -#ifndef _VM_FP_FUNCTIONS_H_ -#define _VM_FP_FUNCTIONS_H_ +#ifndef RISCV_SRC_VM_FP_FUNCTIONS_H_ +#define RISCV_SRC_VM_FP_FUNCTIONS_H_ #include From 574e7e82e8e432093fb6944f4711a1fcdda6ee3d Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Mon, 22 Sep 2025 18:58:45 +0200 Subject: [PATCH 011/230] cleans up vector functions, wrt includes --- src/vm/vector_functions.cpp | 15 +-------------- src/vm/vector_functions.h | 6 ------ src/vm/vector_functions.hpp | 1 - 3 files changed, 1 insertion(+), 21 deletions(-) diff --git a/src/vm/vector_functions.cpp b/src/vm/vector_functions.cpp index e0b21e6..9e008d0 100644 --- a/src/vm/vector_functions.cpp +++ b/src/vm/vector_functions.cpp @@ -33,7 +33,6 @@ //////////////////////////////////////////////////////////////////////////////// #include "vector_functions.h" -#include "iss/vm_types.h" #include "vm/aes_sbox.h" #include #include @@ -43,23 +42,11 @@ #include #include #include +#include #include namespace softvector { -bool softvec_read(void* core, uint64_t addr, uint64_t length, uint8_t* data) { - // Read length bytes from addr into *data - iss::status status = static_cast(core)->read(iss::address_type::PHYSICAL, iss::access_type::READ, - 0 /*traits::MEM*/, addr, length, data); - return status == iss::Ok; -} -bool softvec_write(void* core, uint64_t addr, uint64_t length, uint8_t* data) { - // Write length bytes from addr into *data - iss::status status = static_cast(core)->write(iss::address_type::PHYSICAL, iss::access_type::READ, - 0 /*traits::MEM*/, addr, length, data); - return status == iss::Ok; -} - vtype_t::vtype_t(uint32_t vtype_val) { underlying = (vtype_val & 0x8000) << 32 | (vtype_val & ~0x8000); } vtype_t::vtype_t(uint64_t vtype_val) { underlying = vtype_val; } bool vtype_t::vill() { return underlying >> 63; } diff --git a/src/vm/vector_functions.h b/src/vm/vector_functions.h index 9343b70..38e3be5 100644 --- a/src/vm/vector_functions.h +++ b/src/vm/vector_functions.h @@ -34,9 +34,6 @@ #ifndef _VM_VECTOR_FUNCTIONS_H_ #define _VM_VECTOR_FUNCTIONS_H_ - -#include "iss/arch_if.h" -#include "iss/vm_types.h" #include #include #include @@ -79,9 +76,6 @@ std::function get_crypto_funct(unsig template dest_elem_t brev(src_elem_t vs2); template dest_elem_t brev8(src_elem_t vs2); -bool softvec_read(void* core, uint64_t addr, uint64_t length, uint8_t* data); -bool softvec_write(void* core, uint64_t addr, uint64_t length, uint8_t* data); - template uint64_t vector_load_store(void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t segment_size, int64_t stride = 0, diff --git a/src/vm/vector_functions.hpp b/src/vm/vector_functions.hpp index 396c2c4..e9df5aa 100644 --- a/src/vm/vector_functions.hpp +++ b/src/vm/vector_functions.hpp @@ -32,7 +32,6 @@ // alex@minres.com - initial API and implementation //////////////////////////////////////////////////////////////////////////////// #pragma once -#include "iss/interp/vm_base.h" extern "C" { #include } From 052cda4865a814cf156c4d772716aba6eea7018d Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Mon, 22 Sep 2025 18:59:40 +0200 Subject: [PATCH 012/230] cleans up interp template, introducing trampoline for vector functions --- CMakeLists.txt | 1 + gen_input/templates/interp/CORENAME.cpp.gtl | 804 +---------------- src/vm/interp/vm_rv32gcv.cpp | 798 +---------------- src/vm/interp/vm_rv64gcv.cpp | 796 +---------------- src/vm/new_vector_functions.cpp | 934 ++++++++++++++++++++ src/vm/new_vector_functions.h | 167 ++++ 6 files changed, 1143 insertions(+), 2357 deletions(-) create mode 100644 src/vm/new_vector_functions.cpp create mode 100644 src/vm/new_vector_functions.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 4ac229c..a1cf9e7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -69,6 +69,7 @@ set(LIB_SOURCES src/vm/interp/vm_rv64gcv.cpp src/vm/fp_functions.cpp src/vm/vector_functions.cpp + src/vm/new_vector_functions.cpp src/iss/debugger/csr_names.cpp src/iss/semihosting/semihosting.cpp ) diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 4dcab0e..82083f2 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -48,8 +48,13 @@ def nativeTypeSize(int size){ if(floating_point) {%> #include <%} -if(vector) {%> +if(vector) { +def xlen = constants.find { it.name == 'XLEN' }?.value ?: 0 +def vlen = constants.find { it.name == 'VLEN' }?.value ?: 0 %> +#define CUR_VLEN ${vlen} +#define CUR_XLEN ${xlen} #include +#include <%} if(aes) {%> #include @@ -155,6 +160,9 @@ if(vector) {%> } inline const char* ma_name(bool ma) { return ma ? "ma" : "mu"; } inline const char* ta_name(bool ta) { return ta ? "ta" : "tu"; } + inline void lower(){ + this->core.reg.trap_state = 0; + } <%}%> virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override; @@ -177,804 +185,24 @@ if(vector) {%> inline void set_tval(uint64_t new_tval){ tval = new_tval; } -<%if(vector) { - def xlen = constants.find { it.name == 'XLEN' }?.value ?: 0 - def vlen = constants.find { it.name == 'VLEN' }?.value ?: 0 %> - inline void lower(){ - this->core.reg.trap_state = 0; - } +<%if(vector) { %> uint64_t vlseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<${vlen}, uint8_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b101: - return softvector::vector_load_store<${vlen}, uint16_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b110: - return softvector::vector_load_store<${vlen}, uint32_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b111: - return softvector::vector_load_store<${vlen}, uint64_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vlseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); } uint64_t vsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<${vlen}, uint8_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b101: - return softvector::vector_load_store<${vlen}, uint16_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b110: - return softvector::vector_load_store<${vlen}, uint32_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b111: - return softvector::vector_load_store<${vlen}, uint64_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); } uint64_t vlsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<${vlen}, uint8_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b101: - return softvector::vector_load_store<${vlen}, uint16_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b110: - return softvector::vector_load_store<${vlen}, uint32_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b111: - return softvector::vector_load_store<${vlen}, uint64_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vlsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); } uint64_t vssseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<${vlen}, uint8_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b101: - return softvector::vector_load_store<${vlen}, uint16_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b110: - return softvector::vector_load_store<${vlen}, uint32_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b111: - return softvector::vector_load_store<${vlen}, uint64_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - default: - throw new std::runtime_error("Unsupported width bit value"); - } - } - - using indexed_load_store_t = std::function, uint8_t*, uint64_t, uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; - template indexed_load_store_t getFunction() { - return [this](void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, - uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, uint8_t segment_size) { - return softvector::vector_load_store_index<${xlen}, ${vlen}, T1, T2>(core, load_store_fn, V, vl, vstart, vtype, vm, vd, rs1, vs2, segment_size); - }; + return ::vssseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); } - - const std::array, 4> functionTable = {{ - {getFunction(), getFunction(), getFunction(), getFunction()}, - {getFunction(), getFunction(), getFunction(), getFunction()}, - {getFunction(), getFunction(), getFunction(), getFunction()}, - {getFunction(), getFunction(), getFunction(), getFunction()} - }}; - const size_t map_index_size[9] = { 0, 0, 1, 0, 2, 0, 0, 0, 3 }; // translate number of bytes to index in functionTable uint64_t vlxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return functionTable[map_index_size[index_byte_size]][data_byte_size](this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size); + return ::vlxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); } uint64_t vsxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return functionTable[map_index_size[index_byte_size]][data_byte_size](this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size); - } - void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<${vlen}, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_op<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<${vlen}, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_op<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<${vlen}, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<${vlen}, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<${vlen}, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<${vlen}, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<${vlen}, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<${vlen}, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<${vlen}, uint16_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<${vlen}, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<${vlen}, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<${vlen}, uint16_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<${vlen}, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<${vlen}, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t target_sew_pow, uint8_t frac_pow){ - switch(target_sew_pow){ - case 4: // uint16_t target - if(frac_pow != 1) throw new std::runtime_error("Unsupported frac_pow"); - return softvector::vector_unary_op<${vlen}, uint16_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 5: // uint32_t target - switch(frac_pow){ - case 1: - return softvector::vector_unary_op<${vlen}, uint32_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 2: - return softvector::vector_unary_op<${vlen}, uint32_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported frac_pow"); - } - case 6: // uint64_t target - switch(frac_pow){ - case 1: - return softvector::vector_unary_op<${vlen}, uint64_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 2: - return softvector::vector_unary_op<${vlen}, uint64_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 3: - return softvector::vector_unary_op<${vlen}, uint64_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported frac_pow"); - } - default: - throw new std::runtime_error("Unsupported target_sew_pow"); - } - } - void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_carry<${vlen}, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b001: - return softvector::vector_vector_carry<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b010: - return softvector::vector_vector_carry<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b011: - return softvector::vector_vector_carry<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } } - void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_carry<${vlen}, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b001: - return softvector::vector_imm_carry<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b010: - return softvector::vector_imm_carry<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b011: - return softvector::vector_imm_carry<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::carry_vector_vector_op<${vlen}, uint8_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::carry_vector_vector_op<${vlen}, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::carry_vector_vector_op<${vlen}, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::carry_vector_vector_op<${vlen}, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::carry_vector_imm_op<${vlen}, uint8_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::carry_vector_imm_op<${vlen}, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::carry_vector_imm_op<${vlen}, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::carry_vector_imm_op<${vlen}, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::mask_vector_vector_op<${vlen}, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::mask_vector_vector_op<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::mask_vector_vector_op<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::mask_vector_vector_op<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::mask_vector_imm_op<${vlen}, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::mask_vector_imm_op<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::mask_vector_imm_op<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::mask_vector_imm_op<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<${vlen}, uint8_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<${vlen}, uint16_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<${vlen}, uint32_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<${vlen}, uint8_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<${vlen}, uint16_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<${vlen}, uint32_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_merge<${vlen}, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_merge<${vlen}, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_merge<${vlen}, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_merge<${vlen}, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_merge<${vlen}, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_merge<${vlen}, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_merge<${vlen}, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_merge<${vlen}, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_vector_op<${vlen}, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b001: - return softvector::sat_vector_vector_op<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b010: - return softvector::sat_vector_vector_op<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b011: - return softvector::sat_vector_vector_op<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_imm_op<${vlen}, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b001: - return softvector::sat_vector_imm_op<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b010: - return softvector::sat_vector_imm_op<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b011: - return softvector::sat_vector_imm_op<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_vector_op<${vlen}, uint8_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b001: - return softvector::sat_vector_vector_op<${vlen}, uint16_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b010: - return softvector::sat_vector_vector_op<${vlen}, uint32_t, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_imm_op<${vlen}, uint8_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b001: - return softvector::sat_vector_imm_op<${vlen}, uint16_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b010: - return softvector::sat_vector_imm_op<${vlen}, uint32_t, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_red_op<${vlen}, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_red_op<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_red_op<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_red_op<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_red_op<${vlen}, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_red_op<${vlen}, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_red_op<${vlen}, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1){ - return softvector::mask_mask_op<${vlen}>(V, funct6, funct3, vl, vstart, vd, vs2, vs1); - } - uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2){ - return softvector::vcpop<${vlen}>(V, vl, vstart, vm, vs2); - } - int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2){ - return softvector::vfirst<${vlen}>(V, vl, vstart, vm, vs2); - } - void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2){ - return softvector::mask_set_op<${vlen}>(V, enc, vl, vstart, vm, vd, vs2); - } - void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::viota<${vlen}, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2); - case 0b001: - return softvector::viota<${vlen}, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2); - case 0b010: - return softvector::viota<${vlen}, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2); - case 0b011: - return softvector::viota<${vlen}, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vid<${vlen}, uint8_t>(V, vl, vstart, vtype, vm, vd); - case 0b001: - return softvector::vid<${vlen}, uint16_t>(V, vl, vstart, vtype, vm, vd); - case 0b010: - return softvector::vid<${vlen}, uint32_t>(V, vl, vstart, vtype, vm, vd); - case 0b011: - return softvector::vid<${vlen}, uint64_t>(V, vl, vstart, vtype, vm, vd); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - softvector::scalar_move<${vlen}, uint8_t>(V, vtype, vd, val, true); - break; - case 0b001: - softvector::scalar_move<${vlen}, uint16_t>(V, vtype, vd, val, true); - break; - case 0b010: - softvector::scalar_move<${vlen}, uint32_t>(V, vtype, vd, val, true); - break; - case 0b011: - softvector::scalar_move<${vlen}, uint64_t>(V, vtype, vd, val, true); - break; - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::scalar_move<${vlen}, uint8_t>(V, vtype, vd, 0, false); - case 0b001: - return softvector::scalar_move<${vlen}, uint16_t>(V, vtype, vd, 0, false); - case 0b010: - return softvector::scalar_move<${vlen}, uint32_t>(V, vtype, vd, 0, false); - case 0b011: - return softvector::scalar_move<${vlen}, uint64_t>(V, vtype, vd, 0, false); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slideup<${vlen}, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slideup<${vlen}, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slideup<${vlen}, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slideup<${vlen}, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slidedown<${vlen}, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slidedown<${vlen}, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slidedown<${vlen}, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slidedown<${vlen}, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slide1up<${vlen}, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slide1up<${vlen}, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slide1up<${vlen}, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slide1up<${vlen}, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slide1down<${vlen}, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slide1down<${vlen}, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slide1down<${vlen}, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slide1down<${vlen}, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_gather<${vlen}, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_gather<${vlen}, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_gather<${vlen}, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_gather<${vlen}, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_gather<${vlen}, uint8_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_gather<${vlen}, uint16_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_gather<${vlen}, uint32_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_gather<${vlen}, uint64_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_gather<${vlen}, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_gather<${vlen}, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_gather<${vlen}, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_gather<${vlen}, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_compress<${vlen}, uint8_t>(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b001: - return softvector::vector_compress<${vlen}, uint16_t>(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b010: - return softvector::vector_compress<${vlen}, uint32_t>(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b011: - return softvector::vector_compress<${vlen}, uint64_t>(V, vl, vstart, vtype, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count){ - return softvector::vector_whole_move<${vlen}>(V, vd, vs2, count); - } - uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val){ - return scalar_from_vector(V, vtype, vd, sew_val); - } - void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - return vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); - } - void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - return vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); - } - void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_red_op<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_red_op<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::fp_vector_red_op<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::fp_vector_red_op<${vlen}, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b001: - return softvector::fp_vector_red_op<${vlen}, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_red_op<${vlen}, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::fp_vector_vector_op<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op<${vlen}, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op<${vlen}, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: - return softvector::fp_vector_imm_op<${vlen}, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op<${vlen}, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op<${vlen}, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op<${vlen}, uint32_t, uint16_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op<${vlen}, uint64_t, uint32_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op<${vlen}, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op<${vlen}, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op<${vlen}, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op<${vlen}, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_unary_op<${vlen}, uint16_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_op<${vlen}, uint32_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: - return softvector::fp_vector_unary_op<${vlen}, uint64_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::mask_fp_vector_vector_op<${vlen}, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::mask_fp_vector_vector_op<${vlen}, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::mask_fp_vector_vector_op<${vlen}, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::mask_fp_vector_imm_op<${vlen}, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::mask_fp_vector_imm_op<${vlen}, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: - return softvector::mask_fp_vector_imm_op<${vlen}, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t sew_val){ - vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); - } - void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::fp_vector_unary_w<${vlen}, uint16_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b001: - return softvector::fp_vector_unary_w<${vlen}, uint32_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_w<${vlen}, uint64_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::fp_vector_unary_n<${vlen}, uint8_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b001: - return softvector::fp_vector_unary_n<${vlen}, uint16_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_n<${vlen}, uint32_t, uint64_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: // would require 128 bit value to narrow - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_unary_op<${vlen}, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b001: - return softvector::vector_unary_op<${vlen}, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b010: - return softvector::vector_unary_op<${vlen}, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b011: - return softvector::vector_unary_op<${vlen}, uint64_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported sew_val"); - } + return ::vsxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); } <%}%> uint64_t fetch_count{0}; diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp index 69a8fbb..fc06c6b 100644 --- a/src/vm/interp/vm_rv32gcv.cpp +++ b/src/vm/interp/vm_rv32gcv.cpp @@ -40,7 +40,10 @@ #include +#define CUR_VLEN 256 +#define CUR_XLEN 32 #include +#include #include #include @@ -141,6 +144,9 @@ template class vm_impl : public iss::interp::vm_base { } inline const char* ma_name(bool ma) { return ma ? "ma" : "mu"; } inline const char* ta_name(bool ta) { return ta ? "ta" : "tu"; } + inline void lower(){ + this->core.reg.trap_state = 0; + } virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override; @@ -164,801 +170,23 @@ template class vm_impl : public iss::interp::vm_base { tval = new_tval; } - inline void lower(){ - this->core.reg.trap_state = 0; - } uint64_t vlseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<256, uint8_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b101: - return softvector::vector_load_store<256, uint16_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b110: - return softvector::vector_load_store<256, uint32_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b111: - return softvector::vector_load_store<256, uint64_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vlseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); } uint64_t vsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<256, uint8_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b101: - return softvector::vector_load_store<256, uint16_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b110: - return softvector::vector_load_store<256, uint32_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b111: - return softvector::vector_load_store<256, uint64_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); } uint64_t vlsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<256, uint8_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b101: - return softvector::vector_load_store<256, uint16_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b110: - return softvector::vector_load_store<256, uint32_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b111: - return softvector::vector_load_store<256, uint64_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vlsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); } uint64_t vssseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<256, uint8_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b101: - return softvector::vector_load_store<256, uint16_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b110: - return softvector::vector_load_store<256, uint32_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b111: - return softvector::vector_load_store<256, uint64_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vssseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); } - - using indexed_load_store_t = std::function, uint8_t*, uint64_t, uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; - template indexed_load_store_t getFunction() { - return [this](void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, - uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, uint8_t segment_size) { - return softvector::vector_load_store_index<32, 256, T1, T2>(core, load_store_fn, V, vl, vstart, vtype, vm, vd, rs1, vs2, segment_size); - }; - } - - const std::array, 4> functionTable = {{ - {getFunction(), getFunction(), getFunction(), getFunction()}, - {getFunction(), getFunction(), getFunction(), getFunction()}, - {getFunction(), getFunction(), getFunction(), getFunction()}, - {getFunction(), getFunction(), getFunction(), getFunction()} - }}; - const size_t map_index_size[9] = { 0, 0, 1, 0, 2, 0, 0, 0, 3 }; // translate number of bytes to index in functionTable uint64_t vlxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return functionTable[map_index_size[index_byte_size]][data_byte_size](this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size); + return ::vlxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); } uint64_t vsxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return functionTable[map_index_size[index_byte_size]][data_byte_size](this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size); - } - void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<256, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<256, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<256, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<256, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<256, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<256, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<256, uint16_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<256, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<256, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<256, uint16_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<256, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<256, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t target_sew_pow, uint8_t frac_pow){ - switch(target_sew_pow){ - case 4: // uint16_t target - if(frac_pow != 1) throw new std::runtime_error("Unsupported frac_pow"); - return softvector::vector_unary_op<256, uint16_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 5: // uint32_t target - switch(frac_pow){ - case 1: - return softvector::vector_unary_op<256, uint32_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 2: - return softvector::vector_unary_op<256, uint32_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported frac_pow"); - } - case 6: // uint64_t target - switch(frac_pow){ - case 1: - return softvector::vector_unary_op<256, uint64_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 2: - return softvector::vector_unary_op<256, uint64_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 3: - return softvector::vector_unary_op<256, uint64_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported frac_pow"); - } - default: - throw new std::runtime_error("Unsupported target_sew_pow"); - } - } - void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_carry<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b001: - return softvector::vector_vector_carry<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b010: - return softvector::vector_vector_carry<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b011: - return softvector::vector_vector_carry<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } } - void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_carry<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b001: - return softvector::vector_imm_carry<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b010: - return softvector::vector_imm_carry<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b011: - return softvector::vector_imm_carry<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::carry_vector_vector_op<256, uint8_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::carry_vector_vector_op<256, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::carry_vector_vector_op<256, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::carry_vector_vector_op<256, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::carry_vector_imm_op<256, uint8_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::carry_vector_imm_op<256, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::carry_vector_imm_op<256, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::carry_vector_imm_op<256, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::mask_vector_vector_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::mask_vector_vector_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::mask_vector_vector_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::mask_vector_vector_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::mask_vector_imm_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::mask_vector_imm_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::mask_vector_imm_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::mask_vector_imm_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<256, uint8_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<256, uint16_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<256, uint32_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<256, uint8_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<256, uint16_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<256, uint32_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_merge<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_merge<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_merge<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_merge<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_merge<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_merge<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_merge<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_merge<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_vector_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b001: - return softvector::sat_vector_vector_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b010: - return softvector::sat_vector_vector_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b011: - return softvector::sat_vector_vector_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_imm_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b001: - return softvector::sat_vector_imm_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b010: - return softvector::sat_vector_imm_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b011: - return softvector::sat_vector_imm_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_vector_op<256, uint8_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b001: - return softvector::sat_vector_vector_op<256, uint16_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b010: - return softvector::sat_vector_vector_op<256, uint32_t, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_imm_op<256, uint8_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b001: - return softvector::sat_vector_imm_op<256, uint16_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b010: - return softvector::sat_vector_imm_op<256, uint32_t, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_red_op<256, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_red_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_red_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_red_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_red_op<256, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_red_op<256, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_red_op<256, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1){ - return softvector::mask_mask_op<256>(V, funct6, funct3, vl, vstart, vd, vs2, vs1); - } - uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2){ - return softvector::vcpop<256>(V, vl, vstart, vm, vs2); - } - int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2){ - return softvector::vfirst<256>(V, vl, vstart, vm, vs2); - } - void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2){ - return softvector::mask_set_op<256>(V, enc, vl, vstart, vm, vd, vs2); - } - void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::viota<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2); - case 0b001: - return softvector::viota<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2); - case 0b010: - return softvector::viota<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2); - case 0b011: - return softvector::viota<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vid<256, uint8_t>(V, vl, vstart, vtype, vm, vd); - case 0b001: - return softvector::vid<256, uint16_t>(V, vl, vstart, vtype, vm, vd); - case 0b010: - return softvector::vid<256, uint32_t>(V, vl, vstart, vtype, vm, vd); - case 0b011: - return softvector::vid<256, uint64_t>(V, vl, vstart, vtype, vm, vd); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - softvector::scalar_move<256, uint8_t>(V, vtype, vd, val, true); - break; - case 0b001: - softvector::scalar_move<256, uint16_t>(V, vtype, vd, val, true); - break; - case 0b010: - softvector::scalar_move<256, uint32_t>(V, vtype, vd, val, true); - break; - case 0b011: - softvector::scalar_move<256, uint64_t>(V, vtype, vd, val, true); - break; - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::scalar_move<256, uint8_t>(V, vtype, vd, 0, false); - case 0b001: - return softvector::scalar_move<256, uint16_t>(V, vtype, vd, 0, false); - case 0b010: - return softvector::scalar_move<256, uint32_t>(V, vtype, vd, 0, false); - case 0b011: - return softvector::scalar_move<256, uint64_t>(V, vtype, vd, 0, false); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slideup<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slideup<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slideup<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slideup<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slidedown<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slidedown<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slidedown<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slidedown<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slide1up<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slide1up<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slide1up<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slide1up<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slide1down<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slide1down<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slide1down<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slide1down<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_gather<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_gather<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_gather<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_gather<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_gather<256, uint8_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_gather<256, uint16_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_gather<256, uint32_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_gather<256, uint64_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_gather<256, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_gather<256, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_gather<256, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_gather<256, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_compress<256, uint8_t>(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b001: - return softvector::vector_compress<256, uint16_t>(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b010: - return softvector::vector_compress<256, uint32_t>(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b011: - return softvector::vector_compress<256, uint64_t>(V, vl, vstart, vtype, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count){ - return softvector::vector_whole_move<256>(V, vd, vs2, count); - } - uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val){ - return scalar_from_vector(V, vtype, vd, sew_val); - } - void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - return vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); - } - void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - return vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); - } - void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_red_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_red_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::fp_vector_red_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::fp_vector_red_op<256, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b001: - return softvector::fp_vector_red_op<256, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_red_op<256, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::fp_vector_vector_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op<256, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op<256, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: - return softvector::fp_vector_imm_op<256, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op<256, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op<256, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op<256, uint32_t, uint16_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op<256, uint64_t, uint32_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op<256, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op<256, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op<256, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op<256, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_unary_op<256, uint16_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_op<256, uint32_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: - return softvector::fp_vector_unary_op<256, uint64_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::mask_fp_vector_vector_op<256, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::mask_fp_vector_vector_op<256, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::mask_fp_vector_vector_op<256, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::mask_fp_vector_imm_op<256, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::mask_fp_vector_imm_op<256, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: - return softvector::mask_fp_vector_imm_op<256, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t sew_val){ - vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); - } - void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::fp_vector_unary_w<256, uint16_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b001: - return softvector::fp_vector_unary_w<256, uint32_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_w<256, uint64_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::fp_vector_unary_n<256, uint8_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b001: - return softvector::fp_vector_unary_n<256, uint16_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_n<256, uint32_t, uint64_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: // would require 128 bit value to narrow - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_unary_op<256, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b001: - return softvector::vector_unary_op<256, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b010: - return softvector::vector_unary_op<256, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b011: - return softvector::vector_unary_op<256, uint64_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported sew_val"); - } + return ::vsxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); } uint64_t fetch_count{0}; @@ -30523,8 +29751,8 @@ std::unique_ptr create(arch::rv32gcv *core, unsigned short } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp index efd9915..9446c51 100644 --- a/src/vm/interp/vm_rv64gcv.cpp +++ b/src/vm/interp/vm_rv64gcv.cpp @@ -40,7 +40,10 @@ #include +#define CUR_VLEN 512 +#define CUR_XLEN 64 #include +#include #include #include @@ -141,6 +144,9 @@ template class vm_impl : public iss::interp::vm_base { } inline const char* ma_name(bool ma) { return ma ? "ma" : "mu"; } inline const char* ta_name(bool ta) { return ta ? "ta" : "tu"; } + inline void lower(){ + this->core.reg.trap_state = 0; + } virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override; @@ -164,801 +170,23 @@ template class vm_impl : public iss::interp::vm_base { tval = new_tval; } - inline void lower(){ - this->core.reg.trap_state = 0; - } uint64_t vlseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<512, uint8_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b101: - return softvector::vector_load_store<512, uint16_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b110: - return softvector::vector_load_store<512, uint32_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b111: - return softvector::vector_load_store<512, uint64_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vlseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); } uint64_t vsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<512, uint8_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b101: - return softvector::vector_load_store<512, uint16_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b110: - return softvector::vector_load_store<512, uint32_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b111: - return softvector::vector_load_store<512, uint64_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); } uint64_t vlsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<512, uint8_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b101: - return softvector::vector_load_store<512, uint16_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b110: - return softvector::vector_load_store<512, uint32_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b111: - return softvector::vector_load_store<512, uint64_t>(this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vlsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); } uint64_t vssseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - switch(width_val){ - case 0b000: - return softvector::vector_load_store<512, uint8_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b101: - return softvector::vector_load_store<512, uint16_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b110: - return softvector::vector_load_store<512, uint32_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - case 0b111: - return softvector::vector_load_store<512, uint64_t>(this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, true); - default: - throw new std::runtime_error("Unsupported width bit value"); - } + return ::vssseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); } - - using indexed_load_store_t = std::function, uint8_t*, uint64_t, uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; - template indexed_load_store_t getFunction() { - return [this](void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, - uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, uint8_t segment_size) { - return softvector::vector_load_store_index<64, 512, T1, T2>(core, load_store_fn, V, vl, vstart, vtype, vm, vd, rs1, vs2, segment_size); - }; - } - - const std::array, 4> functionTable = {{ - {getFunction(), getFunction(), getFunction(), getFunction()}, - {getFunction(), getFunction(), getFunction(), getFunction()}, - {getFunction(), getFunction(), getFunction(), getFunction()}, - {getFunction(), getFunction(), getFunction(), getFunction()} - }}; - const size_t map_index_size[9] = { 0, 0, 1, 0, 2, 0, 0, 0, 3 }; // translate number of bytes to index in functionTable uint64_t vlxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return functionTable[map_index_size[index_byte_size]][data_byte_size](this->get_arch(), softvector::softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size); + return ::vlxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); } uint64_t vsxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return functionTable[map_index_size[index_byte_size]][data_byte_size](this->get_arch(), softvector::softvec_write, V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size); - } - void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<512, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<512, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<512, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<512, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<512, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<512, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<512, uint16_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<512, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<512, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<512, uint16_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<512, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<512, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t target_sew_pow, uint8_t frac_pow){ - switch(target_sew_pow){ - case 4: // uint16_t target - if(frac_pow != 1) throw new std::runtime_error("Unsupported frac_pow"); - return softvector::vector_unary_op<512, uint16_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 5: // uint32_t target - switch(frac_pow){ - case 1: - return softvector::vector_unary_op<512, uint32_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 2: - return softvector::vector_unary_op<512, uint32_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported frac_pow"); - } - case 6: // uint64_t target - switch(frac_pow){ - case 1: - return softvector::vector_unary_op<512, uint64_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 2: - return softvector::vector_unary_op<512, uint64_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 3: - return softvector::vector_unary_op<512, uint64_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported frac_pow"); - } - default: - throw new std::runtime_error("Unsupported target_sew_pow"); - } - } - void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_carry<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b001: - return softvector::vector_vector_carry<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b010: - return softvector::vector_vector_carry<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b011: - return softvector::vector_vector_carry<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } } - void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_carry<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b001: - return softvector::vector_imm_carry<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b010: - return softvector::vector_imm_carry<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b011: - return softvector::vector_imm_carry<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::carry_vector_vector_op<512, uint8_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::carry_vector_vector_op<512, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::carry_vector_vector_op<512, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::carry_vector_vector_op<512, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::carry_vector_imm_op<512, uint8_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::carry_vector_imm_op<512, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::carry_vector_imm_op<512, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::carry_vector_imm_op<512, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::mask_vector_vector_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::mask_vector_vector_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::mask_vector_vector_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::mask_vector_vector_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::mask_vector_imm_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::mask_vector_imm_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::mask_vector_imm_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::mask_vector_imm_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_op<512, uint8_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op<512, uint16_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op<512, uint32_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_op<512, uint8_t, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op<512, uint16_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op<512, uint32_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_merge<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_merge<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_merge<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_merge<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_merge<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_merge<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_merge<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_merge<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_vector_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b001: - return softvector::sat_vector_vector_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b010: - return softvector::sat_vector_vector_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b011: - return softvector::sat_vector_vector_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_imm_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b001: - return softvector::sat_vector_imm_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b010: - return softvector::sat_vector_imm_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b011: - return softvector::sat_vector_imm_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_vector_op<512, uint8_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b001: - return softvector::sat_vector_vector_op<512, uint16_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b010: - return softvector::sat_vector_vector_op<512, uint32_t, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::sat_vector_imm_op<512, uint8_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b001: - return softvector::sat_vector_imm_op<512, uint16_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b010: - return softvector::sat_vector_imm_op<512, uint32_t, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_red_op<512, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_red_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_red_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_red_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_red_op<512, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_red_op<512, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_red_op<512, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1){ - return softvector::mask_mask_op<512>(V, funct6, funct3, vl, vstart, vd, vs2, vs1); - } - uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2){ - return softvector::vcpop<512>(V, vl, vstart, vm, vs2); - } - int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2){ - return softvector::vfirst<512>(V, vl, vstart, vm, vs2); - } - void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2){ - return softvector::mask_set_op<512>(V, enc, vl, vstart, vm, vd, vs2); - } - void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::viota<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2); - case 0b001: - return softvector::viota<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2); - case 0b010: - return softvector::viota<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2); - case 0b011: - return softvector::viota<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vid<512, uint8_t>(V, vl, vstart, vtype, vm, vd); - case 0b001: - return softvector::vid<512, uint16_t>(V, vl, vstart, vtype, vm, vd); - case 0b010: - return softvector::vid<512, uint32_t>(V, vl, vstart, vtype, vm, vd); - case 0b011: - return softvector::vid<512, uint64_t>(V, vl, vstart, vtype, vm, vd); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - softvector::scalar_move<512, uint8_t>(V, vtype, vd, val, true); - break; - case 0b001: - softvector::scalar_move<512, uint16_t>(V, vtype, vd, val, true); - break; - case 0b010: - softvector::scalar_move<512, uint32_t>(V, vtype, vd, val, true); - break; - case 0b011: - softvector::scalar_move<512, uint64_t>(V, vtype, vd, val, true); - break; - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::scalar_move<512, uint8_t>(V, vtype, vd, 0, false); - case 0b001: - return softvector::scalar_move<512, uint16_t>(V, vtype, vd, 0, false); - case 0b010: - return softvector::scalar_move<512, uint32_t>(V, vtype, vd, 0, false); - case 0b011: - return softvector::scalar_move<512, uint64_t>(V, vtype, vd, 0, false); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slideup<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slideup<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slideup<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slideup<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slidedown<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slidedown<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slidedown<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slidedown<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slide1up<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slide1up<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slide1up<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slide1up<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - switch(sew_val){ - case 0b000: - return softvector::vector_slide1down<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slide1down<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slide1down<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slide1down<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_gather<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_gather<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_gather<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_gather<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_vector_gather<512, uint8_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_gather<512, uint16_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_gather<512, uint32_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_gather<512, uint64_t, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_imm_gather<512, uint8_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_gather<512, uint16_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_gather<512, uint32_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_gather<512, uint64_t>(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_compress<512, uint8_t>(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b001: - return softvector::vector_compress<512, uint16_t>(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b010: - return softvector::vector_compress<512, uint32_t>(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b011: - return softvector::vector_compress<512, uint64_t>(V, vl, vstart, vtype, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count){ - return softvector::vector_whole_move<512>(V, vd, vs2, count); - } - uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val){ - return scalar_from_vector(V, vtype, vd, sew_val); - } - void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - return vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); - } - void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, uint8_t sew_val) { - return vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); - } - void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_red_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_red_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::fp_vector_red_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::fp_vector_red_op<512, uint16_t, uint8_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b001: - return softvector::fp_vector_red_op<512, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_red_op<512, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::fp_vector_vector_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op<512, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op<512, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: - return softvector::fp_vector_imm_op<512, uint64_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op<512, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op<512, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op<512, uint32_t, uint16_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op<512, uint64_t, uint32_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op<512, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op<512, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op<512, uint32_t, uint32_t, uint16_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op<512, uint64_t, uint64_t, uint32_t>(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_unary_op<512, uint16_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_op<512, uint32_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: - return softvector::fp_vector_unary_op<512, uint64_t>(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::mask_fp_vector_vector_op<512, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::mask_fp_vector_vector_op<512, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::mask_fp_vector_vector_op<512, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::mask_fp_vector_imm_op<512, uint16_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::mask_fp_vector_imm_op<512, uint32_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: - return softvector::mask_fp_vector_imm_op<512, uint64_t>(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t sew_val){ - vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); - } - void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::fp_vector_unary_w<512, uint16_t, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b001: - return softvector::fp_vector_unary_w<512, uint32_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_w<512, uint64_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::fp_vector_unary_n<512, uint8_t, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b001: - return softvector::fp_vector_unary_n<512, uint16_t, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_n<512, uint32_t, uint64_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: // would require 128 bit value to narrow - default: - throw new std::runtime_error("Unsupported sew bit value"); - } - } - void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val){ - switch(sew_val){ - case 0b000: - return softvector::vector_unary_op<512, uint8_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b001: - return softvector::vector_unary_op<512, uint16_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b010: - return softvector::vector_unary_op<512, uint32_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b011: - return softvector::vector_unary_op<512, uint64_t>(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported sew_val"); - } + return ::vsxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); } uint64_t fetch_count{0}; diff --git a/src/vm/new_vector_functions.cpp b/src/vm/new_vector_functions.cpp new file mode 100644 index 0000000..1bd7fdb --- /dev/null +++ b/src/vm/new_vector_functions.cpp @@ -0,0 +1,934 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2025, MINRES Technologies GmbH +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Contributors: +// alex@minres.com - initial API and implementation +//////////////////////////////////////////////////////////////////////////////// + +#include +#include + +#include "iss/arch_if.h" +#include "iss/vm_types.h" +#include +#include + +using indexed_load_store_t = std::function, uint8_t*, uint64_t, + uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; +template indexed_load_store_t getFunction() { + return [](void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, + uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, uint8_t segment_size) { + return softvector::vector_load_store_index(core, load_store_fn, V, vl, vstart, vtype, vm, vd, rs1, vs2, + segment_size); + }; +} + +const std::array, 4> functionTable = { + {{getFunction(), getFunction(), getFunction(), + getFunction()}, + {getFunction(), getFunction(), getFunction(), + getFunction()}, + {getFunction(), getFunction(), getFunction(), + getFunction()}, + {getFunction(), getFunction(), getFunction(), + getFunction()}}}; +constexpr size_t map_index_size[9] = {0, + std::numeric_limits::max(), + 1, + std::numeric_limits::max(), + 2, + std::numeric_limits::max(), + std::numeric_limits::max(), + std::numeric_limits::max(), + 3}; + +bool softvec_read(void* core, uint64_t addr, uint64_t length, uint8_t* data) { + // Read length bytes from addr into *data + iss::status status = static_cast(core)->read(iss::address_type::PHYSICAL, iss::access_type::READ, + 0 /*traits::MEM*/, addr, length, data); + return status == iss::Ok; +} +bool softvec_write(void* core, uint64_t addr, uint64_t length, uint8_t* data) { + // Write length bytes from addr into *data + iss::status status = static_cast(core)->write(iss::address_type::PHYSICAL, iss::access_type::READ, + 0 /*traits::MEM*/, addr, length, data); + return status == iss::Ok; +} +extern "C" { +uint64_t vlseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b101: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b110: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b111: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +uint64_t vsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b101: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b110: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b111: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +uint64_t vlsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size, int64_t stride) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b101: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b110: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b111: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +uint64_t vssseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size, int64_t stride) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b101: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b110: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b111: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +uint64_t vlxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered) { + return functionTable[map_index_size[index_byte_size]][data_byte_size](core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, vs2, + segment_size); +} +uint64_t vsxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, + uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered) { + return functionTable[map_index_size[index_byte_size]][data_byte_size](core, softvec_write, V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, + segment_size); +} +void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint8_t target_sew_pow, uint8_t frac_pow) { + switch(target_sew_pow) { + case 4: // uint16_t target + if(frac_pow != 1) + throw new std::runtime_error("Unsupported frac_pow"); + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 5: // uint32_t target + switch(frac_pow) { + case 1: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 2: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported frac_pow"); + } + case 6: // uint64_t target + switch(frac_pow) { + case 1: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 2: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 3: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported frac_pow"); + } + default: + throw new std::runtime_error("Unsupported target_sew_pow"); + } +} +void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b001: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b010: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b011: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b001: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b010: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b011: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, + unsigned vs2, unsigned vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, + unsigned vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, + uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b001: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b010: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b011: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, + bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b001: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b010: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b011: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, + uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b001: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b010: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, + bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b001: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b010: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1) { + return softvector::mask_mask_op(V, funct6, funct3, vl, vstart, vd, vs2, vs1); +} +uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { + return softvector::vcpop(V, vl, vstart, vm, vs2); +} +int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { + return softvector::vfirst(V, vl, vstart, vm, vs2); +} +void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2) { + return softvector::mask_set_op(V, enc, vl, vstart, vm, vd, vs2); +} +void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + case 0b001: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + case 0b010: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + case 0b011: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + case 0b001: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + case 0b010: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + case 0b011: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + softvector::scalar_move(V, vtype, vd, val, true); + break; + case 0b001: + softvector::scalar_move(V, vtype, vd, val, true); + break; + case 0b010: + softvector::scalar_move(V, vtype, vd, val, true); + break; + case 0b011: + softvector::scalar_move(V, vtype, vd, val, true); + break; + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::scalar_move(V, vtype, vd, 0, false); + case 0b001: + return softvector::scalar_move(V, vtype, vd, 0, false); + case 0b010: + return softvector::scalar_move(V, vtype, vd, 0, false); + case 0b011: + return softvector::scalar_move(V, vtype, vd, 0, false); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, + uint64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b001: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b010: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b011: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count) { + return softvector::vector_whole_move(V, vd, vs2, count); +} +uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val) { + return scalar_from_vector(V, vtype, vd, sew_val); +} +void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, + uint64_t imm, uint8_t sew_val) { + return vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); +} +void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, + uint64_t imm, uint8_t sew_val) { + return vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); +} +void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b001: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, + rm); + case 0b010: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, + rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, + vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, + vs1, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, + rm); + case 0b010: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, + rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, + bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: + return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: + return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint64_t imm, uint8_t sew_val) { + vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); +} +void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b001: + return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b001: + return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: // would require 128 bit value to narrow + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b001: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b010: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b011: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported sew_val"); + } +} +} \ No newline at end of file diff --git a/src/vm/new_vector_functions.h b/src/vm/new_vector_functions.h new file mode 100644 index 0000000..8710ee3 --- /dev/null +++ b/src/vm/new_vector_functions.h @@ -0,0 +1,167 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2025, MINRES Technologies GmbH +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Contributors: +// alex@minres.com - initial API and implementation +//////////////////////////////////////////////////////////////////////////////// + +#ifndef RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ +#define RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ +#include +#include + +// To make the language server happy +#ifndef CUR_VLEN +#define CUR_VLEN 0 +#endif +#ifndef CUR_XLEN +#define CUR_XLEN 0 +#endif +extern "C" { +uint64_t vlseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size); +uint64_t vsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size); +uint64_t vlsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size, int64_t stride); +uint64_t vssseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size, int64_t stride); +uint64_t vlxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered); +uint64_t vsxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, + uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered); +void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); +void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val); +void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); +void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val); +void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); +void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val); +void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint8_t target_sew_pow, uint8_t frac_pow); +void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry); +void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry); +void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, + unsigned vs2, unsigned vs1, uint8_t sew_val); +void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, + unsigned vs2, int64_t imm, uint8_t sew_val); +void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val); +void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val); +void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); +void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val); +void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, + uint8_t sew_val); +void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, + uint8_t sew_val); +bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, + uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); +bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, + bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val); +bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, + uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); +bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, + bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val); +void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t sew_val); +void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t sew_val); +void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1); +uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2); +int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2); +void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2); +void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val); +void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val); +void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val); +uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val); +void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, + uint8_t sew_val); +void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, + uint8_t sew_val); +void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, + uint8_t sew_val); +void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, + uint64_t imm, uint8_t sew_val); +void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint8_t vs1, uint8_t sew_val); +void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint8_t vs1, uint8_t sew_val); +void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, + uint8_t sew_val); +void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, + uint8_t sew_val); +void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count); +uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val); +void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, + uint64_t imm, uint8_t sew_val); +void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, + uint64_t imm, uint8_t sew_val); +void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); +void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); +void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); +void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val); +void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); +void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val); +void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); +void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val); +void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, + bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val); +void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); +void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val); +void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint64_t imm, uint8_t sew_val); +void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t rm, uint8_t sew_val); +void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t rm, uint8_t sew_val); +void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t sew_val); +} +#endif /* RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ */ From 8a26c58ad80bebacc99bdffb6e0dc7a88c61e32e Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Tue, 23 Sep 2025 12:03:26 +0200 Subject: [PATCH 013/230] updates interp rvgcv Implementation --- gen_input/templates/interp/CORENAME.cpp.gtl | 20 - src/vm/interp/vm_rv32gcv.cpp | 642 ++++++++++---------- src/vm/interp/vm_rv64gcv.cpp | 640 ++++++++++--------- 3 files changed, 621 insertions(+), 681 deletions(-) diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 82083f2..7e10961 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -185,26 +185,6 @@ if(vector) {%> inline void set_tval(uint64_t new_tval){ tval = new_tval; } -<%if(vector) { %> - uint64_t vlseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - return ::vlseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); - } - uint64_t vsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - return ::vsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); - } - uint64_t vlsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - return ::vlsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); - } - uint64_t vssseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - return ::vssseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); - } - uint64_t vlxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return ::vlxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); - } - uint64_t vsxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return ::vsxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); - } -<%}%> uint64_t fetch_count{0}; uint64_t tval{0}; diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp index fc06c6b..3e6fbaa 100644 --- a/src/vm/interp/vm_rv32gcv.cpp +++ b/src/vm/interp/vm_rv32gcv.cpp @@ -169,26 +169,6 @@ template class vm_impl : public iss::interp::vm_base { inline void set_tval(uint64_t new_tval){ tval = new_tval; } - - uint64_t vlseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - return ::vlseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); - } - uint64_t vsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - return ::vsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); - } - uint64_t vlsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - return ::vlsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); - } - uint64_t vssseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - return ::vssseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); - } - uint64_t vlxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return ::vlxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); - } - uint64_t vsxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return ::vsxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); - } - uint64_t fetch_count{0}; uint64_t tval{0}; @@ -5992,7 +5972,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); } } } @@ -6032,7 +6012,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); } } } @@ -6072,7 +6052,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); } } } @@ -6112,7 +6092,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); } } } @@ -6152,7 +6132,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); } } } @@ -6192,7 +6172,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); } } } @@ -6232,7 +6212,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); } } } @@ -6272,7 +6252,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); } } } @@ -6312,7 +6292,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); } } } @@ -6352,7 +6332,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); } } } @@ -6392,7 +6372,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); } } } @@ -6432,7 +6412,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); } } } @@ -6472,7 +6452,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); } } } @@ -6512,7 +6492,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); } } } @@ -6552,7 +6532,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); } } } @@ -6592,7 +6572,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); } } } @@ -6632,7 +6612,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); } } } @@ -6672,7 +6652,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); } } } @@ -6712,7 +6692,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); } } } @@ -6752,7 +6732,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); } } } @@ -6792,7 +6772,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); } } } @@ -6832,7 +6812,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); } } } @@ -6872,7 +6852,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); } } } @@ -6912,7 +6892,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); } } } @@ -6952,7 +6932,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); } } } @@ -6992,7 +6972,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); } } } @@ -7032,7 +7012,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); } } } @@ -7072,7 +7052,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); } } } @@ -7112,7 +7092,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); } } } @@ -7152,7 +7132,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); } } } @@ -7192,7 +7172,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); } } } @@ -7232,7 +7212,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); } } } @@ -7272,7 +7252,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1); } } } @@ -7312,7 +7292,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1); } } } @@ -7352,7 +7332,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1); } } } @@ -7392,7 +7372,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1); } } } @@ -7432,7 +7412,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2); } } } @@ -7472,7 +7452,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2); } } } @@ -7512,7 +7492,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2); } } } @@ -7552,7 +7532,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2); } } } @@ -7592,7 +7572,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3); } } } @@ -7632,7 +7612,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3); } } } @@ -7672,7 +7652,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3); } } } @@ -7712,7 +7692,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3); } } } @@ -7752,7 +7732,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4); } } } @@ -7792,7 +7772,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4); } } } @@ -7832,7 +7812,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4); } } } @@ -7872,7 +7852,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4); } } } @@ -7912,7 +7892,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5); } } } @@ -7952,7 +7932,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5); } } } @@ -7992,7 +7972,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5); } } } @@ -8032,7 +8012,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5); } } } @@ -8072,7 +8052,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6); } } } @@ -8112,7 +8092,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6); } } } @@ -8152,7 +8132,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6); } } } @@ -8192,7 +8172,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6); } } } @@ -8232,7 +8212,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7); } } } @@ -8272,7 +8252,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7); } } } @@ -8312,7 +8292,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7); } } } @@ -8352,7 +8332,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7); } } } @@ -8392,7 +8372,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8); } } } @@ -8432,7 +8412,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8); } } } @@ -8472,7 +8452,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8); } } } @@ -8512,7 +8492,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8); } } } @@ -8553,7 +8533,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1, (int32_t)*(X+rs2)); } } } @@ -8594,7 +8574,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1, (int32_t)*(X+rs2)); } } } @@ -8635,7 +8615,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1, (int32_t)*(X+rs2)); } } } @@ -8676,7 +8656,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1, (int32_t)*(X+rs2)); } } } @@ -8717,7 +8697,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2, (int32_t)*(X+rs2)); } } } @@ -8758,7 +8738,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2, (int32_t)*(X+rs2)); } } } @@ -8799,7 +8779,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2, (int32_t)*(X+rs2)); } } } @@ -8840,7 +8820,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2, (int32_t)*(X+rs2)); } } } @@ -8881,7 +8861,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3, (int32_t)*(X+rs2)); } } } @@ -8922,7 +8902,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3, (int32_t)*(X+rs2)); } } } @@ -8963,7 +8943,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3, (int32_t)*(X+rs2)); } } } @@ -9004,7 +8984,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3, (int32_t)*(X+rs2)); } } } @@ -9045,7 +9025,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4, (int32_t)*(X+rs2)); } } } @@ -9086,7 +9066,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4, (int32_t)*(X+rs2)); } } } @@ -9127,7 +9107,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4, (int32_t)*(X+rs2)); } } } @@ -9168,7 +9148,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4, (int32_t)*(X+rs2)); } } } @@ -9209,7 +9189,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5, (int32_t)*(X+rs2)); } } } @@ -9250,7 +9230,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5, (int32_t)*(X+rs2)); } } } @@ -9291,7 +9271,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5, (int32_t)*(X+rs2)); } } } @@ -9332,7 +9312,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5, (int32_t)*(X+rs2)); } } } @@ -9373,7 +9353,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6, (int32_t)*(X+rs2)); } } } @@ -9414,7 +9394,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6, (int32_t)*(X+rs2)); } } } @@ -9455,7 +9435,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6, (int32_t)*(X+rs2)); } } } @@ -9496,7 +9476,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6, (int32_t)*(X+rs2)); } } } @@ -9537,7 +9517,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7, (int32_t)*(X+rs2)); } } } @@ -9578,7 +9558,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7, (int32_t)*(X+rs2)); } } } @@ -9619,7 +9599,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7, (int32_t)*(X+rs2)); } } } @@ -9660,7 +9640,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7, (int32_t)*(X+rs2)); } } } @@ -9701,7 +9681,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8, (int32_t)*(X+rs2)); } } } @@ -9742,7 +9722,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8, (int32_t)*(X+rs2)); } } } @@ -9783,7 +9763,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8, (int32_t)*(X+rs2)); } } } @@ -9824,7 +9804,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8, (int32_t)*(X+rs2)); } } } @@ -9865,7 +9845,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1, (int32_t)*(X+rs2)); } } } @@ -9906,7 +9886,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1, (int32_t)*(X+rs2)); } } } @@ -9947,7 +9927,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1, (int32_t)*(X+rs2)); } } } @@ -9988,7 +9968,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1, (int32_t)*(X+rs2)); } } } @@ -10029,7 +10009,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2, (int32_t)*(X+rs2)); } } } @@ -10070,7 +10050,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2, (int32_t)*(X+rs2)); } } } @@ -10111,7 +10091,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2, (int32_t)*(X+rs2)); } } } @@ -10152,7 +10132,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2, (int32_t)*(X+rs2)); } } } @@ -10193,7 +10173,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3, (int32_t)*(X+rs2)); } } } @@ -10234,7 +10214,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3, (int32_t)*(X+rs2)); } } } @@ -10275,7 +10255,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3, (int32_t)*(X+rs2)); } } } @@ -10316,7 +10296,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3, (int32_t)*(X+rs2)); } } } @@ -10357,7 +10337,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4, (int32_t)*(X+rs2)); } } } @@ -10398,7 +10378,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4, (int32_t)*(X+rs2)); } } } @@ -10439,7 +10419,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4, (int32_t)*(X+rs2)); } } } @@ -10480,7 +10460,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4, (int32_t)*(X+rs2)); } } } @@ -10521,7 +10501,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5, (int32_t)*(X+rs2)); } } } @@ -10562,7 +10542,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5, (int32_t)*(X+rs2)); } } } @@ -10603,7 +10583,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5, (int32_t)*(X+rs2)); } } } @@ -10644,7 +10624,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5, (int32_t)*(X+rs2)); } } } @@ -10685,7 +10665,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6, (int32_t)*(X+rs2)); } } } @@ -10726,7 +10706,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6, (int32_t)*(X+rs2)); } } } @@ -10767,7 +10747,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6, (int32_t)*(X+rs2)); } } } @@ -10808,7 +10788,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6, (int32_t)*(X+rs2)); } } } @@ -10849,7 +10829,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7, (int32_t)*(X+rs2)); } } } @@ -10890,7 +10870,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7, (int32_t)*(X+rs2)); } } } @@ -10931,7 +10911,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7, (int32_t)*(X+rs2)); } } } @@ -10972,7 +10952,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7, (int32_t)*(X+rs2)); } } } @@ -11013,7 +10993,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8, (int32_t)*(X+rs2)); } } } @@ -11054,7 +11034,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8, (int32_t)*(X+rs2)); } } } @@ -11095,7 +11075,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8, (int32_t)*(X+rs2)); } } } @@ -11136,7 +11116,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8, (int32_t)*(X+rs2)); + *vstart = (uint32_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8, (int32_t)*(X+rs2)); } } } @@ -11175,7 +11155,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11217,7 +11197,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11259,7 +11239,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11301,7 +11281,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11343,7 +11323,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11385,7 +11365,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11427,7 +11407,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11469,7 +11449,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11511,7 +11491,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11553,7 +11533,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11595,7 +11575,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11637,7 +11617,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11679,7 +11659,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11721,7 +11701,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11763,7 +11743,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11805,7 +11785,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11847,7 +11827,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11889,7 +11869,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11931,7 +11911,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -11973,7 +11953,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12015,7 +11995,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12057,7 +12037,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12099,7 +12079,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12141,7 +12121,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12183,7 +12163,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12225,7 +12205,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12267,7 +12247,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12309,7 +12289,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12351,7 +12331,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12393,7 +12373,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12435,7 +12415,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12477,7 +12457,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint32_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); + uint64_t trapped_idx = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); if(trapped_idx != 1) { *vl = (uint32_t)trapped_idx; lower(); @@ -12516,7 +12496,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } uint32_t _vtype = (bit_sub(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint32_t)1<<6)|((uint32_t)0<<3)|bit_sub<0, 2-0+1>(*vtype); - *vstart = (uint32_t)vsseg((uint8_t*)V, evl, *vstart, _vtype, 1, vs3, *(X+rs1), 0, 1); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, _vtype, 1, vs3, *(X+rs1), 0, 1); } } break; @@ -12550,7 +12530,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } uint32_t _vtype = (bit_sub(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint32_t)1<<6)|((uint32_t)0<<3)|bit_sub<0, 2-0+1>(*vtype); - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, _vtype, 1, vd, *(X+rs1), 0, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, _vtype, 1, vd, *(X+rs1), 0, 1); } } break; @@ -12581,7 +12561,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint32_t evl = (uint32_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); } } } @@ -12613,7 +12593,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint32_t evl = (uint32_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(16)); if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); } } } @@ -12645,7 +12625,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint32_t evl = (uint32_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(32)); if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); } } } @@ -12677,7 +12657,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint32_t evl = (uint32_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(64)); if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); } } } @@ -12713,7 +12693,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); } } } @@ -12750,7 +12730,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); } } } @@ -12787,7 +12767,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); } } } @@ -12824,7 +12804,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); } } } @@ -12861,7 +12841,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); } } } @@ -12898,7 +12878,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); } } } @@ -12935,7 +12915,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); } } } @@ -12972,7 +12952,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); } } } @@ -13009,7 +12989,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); } } } @@ -13046,7 +13026,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); } } } @@ -13083,7 +13063,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); } } } @@ -13120,7 +13100,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + *vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); } } } @@ -13152,7 +13132,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint32_t evl = (uint32_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); if(evl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); } } } @@ -13187,7 +13167,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); } } } @@ -13223,7 +13203,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); } } } @@ -13259,7 +13239,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint32_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + *vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); } } } @@ -13300,7 +13280,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 1); } } } @@ -13341,7 +13321,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 1); } } } @@ -13382,7 +13362,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 1); } } } @@ -13423,7 +13403,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 1); } } } @@ -13464,7 +13444,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 1); } } } @@ -13505,7 +13485,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 1); } } } @@ -13546,7 +13526,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 1); } } } @@ -13587,7 +13567,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 1); } } } @@ -13628,7 +13608,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 1); } } } @@ -13669,7 +13649,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 1); } } } @@ -13710,7 +13690,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 1); } } } @@ -13751,7 +13731,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 1); } } } @@ -13792,7 +13772,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 1); } } } @@ -13833,7 +13813,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 1); } } } @@ -13874,7 +13854,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 1); } } } @@ -13915,7 +13895,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 1); } } } @@ -13956,7 +13936,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 1); } } } @@ -13997,7 +13977,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 1); } } } @@ -14038,7 +14018,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 1); } } } @@ -14079,7 +14059,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 1); } } } @@ -14120,7 +14100,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 1); } } } @@ -14161,7 +14141,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 1); } } } @@ -14202,7 +14182,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 1); } } } @@ -14243,7 +14223,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 1); } } } @@ -14284,7 +14264,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 1); } } } @@ -14325,7 +14305,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 1); } } } @@ -14366,7 +14346,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 1); } } } @@ -14407,7 +14387,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 1); } } } @@ -14448,7 +14428,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 1); } } } @@ -14489,7 +14469,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 1); } } } @@ -14530,7 +14510,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 1); } } } @@ -14571,7 +14551,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 1); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 1); } } } @@ -14612,7 +14592,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 1); } } } @@ -14653,7 +14633,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 1); } } } @@ -14694,7 +14674,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 1); } } } @@ -14735,7 +14715,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 1); } } } @@ -14776,7 +14756,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 1); } } } @@ -14817,7 +14797,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 1); } } } @@ -14858,7 +14838,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 1); } } } @@ -14899,7 +14879,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 1); } } } @@ -14940,7 +14920,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 1); } } } @@ -14981,7 +14961,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 1); } } } @@ -15022,7 +15002,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 1); } } } @@ -15063,7 +15043,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 1); } } } @@ -15104,7 +15084,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 1); } } } @@ -15145,7 +15125,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 1); } } } @@ -15186,7 +15166,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 1); } } } @@ -15227,7 +15207,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 1); } } } @@ -15268,7 +15248,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 1); } } } @@ -15309,7 +15289,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 1); } } } @@ -15350,7 +15330,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 1); } } } @@ -15391,7 +15371,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 1); } } } @@ -15432,7 +15412,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 1); } } } @@ -15473,7 +15453,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 1); } } } @@ -15514,7 +15494,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 1); } } } @@ -15555,7 +15535,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 1); } } } @@ -15596,7 +15576,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 1); } } } @@ -15637,7 +15617,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 1); } } } @@ -15678,7 +15658,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 1); } } } @@ -15719,7 +15699,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 1); } } } @@ -15760,7 +15740,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 1); } } } @@ -15801,7 +15781,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 1); } } } @@ -15842,7 +15822,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 1); } } } @@ -15883,7 +15863,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 1); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 1); } } } @@ -15924,7 +15904,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 0); } } } @@ -15965,7 +15945,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 0); } } } @@ -16006,7 +15986,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 0); } } } @@ -16047,7 +16027,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 0); } } } @@ -16088,7 +16068,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 0); } } } @@ -16129,7 +16109,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 0); } } } @@ -16170,7 +16150,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 0); } } } @@ -16211,7 +16191,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 0); } } } @@ -16252,7 +16232,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 0); } } } @@ -16293,7 +16273,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 0); } } } @@ -16334,7 +16314,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 0); } } } @@ -16375,7 +16355,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 0); } } } @@ -16416,7 +16396,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 0); } } } @@ -16457,7 +16437,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 0); } } } @@ -16498,7 +16478,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 0); } } } @@ -16539,7 +16519,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 0); } } } @@ -16580,7 +16560,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 0); } } } @@ -16621,7 +16601,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 0); } } } @@ -16662,7 +16642,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 0); } } } @@ -16703,7 +16683,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 0); } } } @@ -16744,7 +16724,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 0); } } } @@ -16785,7 +16765,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 0); } } } @@ -16826,7 +16806,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 0); } } } @@ -16867,7 +16847,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 0); } } } @@ -16908,7 +16888,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 0); } } } @@ -16949,7 +16929,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 0); } } } @@ -16990,7 +16970,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 0); } } } @@ -17031,7 +17011,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 0); } } } @@ -17072,7 +17052,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 0); } } } @@ -17113,7 +17093,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 0); } } } @@ -17154,7 +17134,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 0); } } } @@ -17195,7 +17175,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 0); + *vstart = (uint32_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 0); } } } @@ -17236,7 +17216,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 0); } } } @@ -17277,7 +17257,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 0); } } } @@ -17318,7 +17298,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 0); } } } @@ -17359,7 +17339,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 0); } } } @@ -17400,7 +17380,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 0); } } } @@ -17441,7 +17421,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 0); } } } @@ -17482,7 +17462,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 0); } } } @@ -17523,7 +17503,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 0); } } } @@ -17564,7 +17544,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 0); } } } @@ -17605,7 +17585,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 0); } } } @@ -17646,7 +17626,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 0); } } } @@ -17687,7 +17667,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 0); } } } @@ -17728,7 +17708,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 0); } } } @@ -17769,7 +17749,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 0); } } } @@ -17810,7 +17790,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 0); } } } @@ -17851,7 +17831,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 0); } } } @@ -17892,7 +17872,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 0); } } } @@ -17933,7 +17913,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 0); } } } @@ -17974,7 +17954,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 0); } } } @@ -18015,7 +17995,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 0); } } } @@ -18056,7 +18036,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 0); } } } @@ -18097,7 +18077,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 0); } } } @@ -18138,7 +18118,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 0); } } } @@ -18179,7 +18159,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 0); } } } @@ -18220,7 +18200,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 0); } } } @@ -18261,7 +18241,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 0); } } } @@ -18302,7 +18282,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 0); } } } @@ -18343,7 +18323,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 0); } } } @@ -18384,7 +18364,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 0); } } } @@ -18425,7 +18405,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 0); } } } @@ -18466,7 +18446,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 0); } } } @@ -18507,7 +18487,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint32_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 0); + *vstart = (uint32_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 0); } } } @@ -29751,8 +29731,8 @@ std::unique_ptr create(arch::rv32gcv *core, unsigned short } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp index 9446c51..7157a7b 100644 --- a/src/vm/interp/vm_rv64gcv.cpp +++ b/src/vm/interp/vm_rv64gcv.cpp @@ -169,26 +169,6 @@ template class vm_impl : public iss::interp::vm_base { inline void set_tval(uint64_t new_tval){ tval = new_tval; } - - uint64_t vlseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - return ::vlseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); - } - uint64_t vsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size){ - return ::vsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size); - } - uint64_t vlsseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - return ::vlsseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); - } - uint64_t vssseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t width_val, uint8_t segment_size, int64_t stride){ - return ::vssseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, width_val, segment_size, stride); - } - uint64_t vlxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return ::vlxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vd, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); - } - uint64_t vsxseg(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered){ - return ::vsxseg(static_cast(this->get_arch()), V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, segment_size, index_byte_size, data_byte_size, ordered); - } - uint64_t fetch_count{0}; uint64_t tval{0}; @@ -7335,7 +7315,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); } } } @@ -7375,7 +7355,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); } } } @@ -7415,7 +7395,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); } } } @@ -7455,7 +7435,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); } } } @@ -7495,7 +7475,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); } } } @@ -7535,7 +7515,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); } } } @@ -7575,7 +7555,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); } } } @@ -7615,7 +7595,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); } } } @@ -7655,7 +7635,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); } } } @@ -7695,7 +7675,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); } } } @@ -7735,7 +7715,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); } } } @@ -7775,7 +7755,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); } } } @@ -7815,7 +7795,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); } } } @@ -7855,7 +7835,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); } } } @@ -7895,7 +7875,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); } } } @@ -7935,7 +7915,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); } } } @@ -7975,7 +7955,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); } } } @@ -8015,7 +7995,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); } } } @@ -8055,7 +8035,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); } } } @@ -8095,7 +8075,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); } } } @@ -8135,7 +8115,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); } } } @@ -8175,7 +8155,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); } } } @@ -8215,7 +8195,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); } } } @@ -8255,7 +8235,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); } } } @@ -8295,7 +8275,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); } } } @@ -8335,7 +8315,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); } } } @@ -8375,7 +8355,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); } } } @@ -8415,7 +8395,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); } } } @@ -8455,7 +8435,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); } } } @@ -8495,7 +8475,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); } } } @@ -8535,7 +8515,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); } } } @@ -8575,7 +8555,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); } } } @@ -8615,7 +8595,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1); } } } @@ -8655,7 +8635,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1); } } } @@ -8695,7 +8675,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1); } } } @@ -8735,7 +8715,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1); } } } @@ -8775,7 +8755,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2); } } } @@ -8815,7 +8795,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2); } } } @@ -8855,7 +8835,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2); } } } @@ -8895,7 +8875,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2); } } } @@ -8935,7 +8915,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3); } } } @@ -8975,7 +8955,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3); } } } @@ -9015,7 +8995,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3); } } } @@ -9055,7 +9035,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3); } } } @@ -9095,7 +9075,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4); } } } @@ -9135,7 +9115,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4); } } } @@ -9175,7 +9155,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4); } } } @@ -9215,7 +9195,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4); } } } @@ -9255,7 +9235,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5); } } } @@ -9295,7 +9275,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5); } } } @@ -9335,7 +9315,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5); } } } @@ -9375,7 +9355,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5); } } } @@ -9415,7 +9395,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6); } } } @@ -9455,7 +9435,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6); } } } @@ -9495,7 +9475,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6); } } } @@ -9535,7 +9515,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6); } } } @@ -9575,7 +9555,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7); } } } @@ -9615,7 +9595,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7); } } } @@ -9655,7 +9635,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7); } } } @@ -9695,7 +9675,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7); } } } @@ -9735,7 +9715,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8); } } } @@ -9775,7 +9755,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8); } } } @@ -9815,7 +9795,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8); } } } @@ -9855,7 +9835,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8); } } } @@ -9896,7 +9876,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1, (int64_t)*(X+rs2)); } } } @@ -9937,7 +9917,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1, (int64_t)*(X+rs2)); } } } @@ -9978,7 +9958,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1, (int64_t)*(X+rs2)); } } } @@ -10019,7 +9999,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1, (int64_t)*(X+rs2)); } } } @@ -10060,7 +10040,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2, (int64_t)*(X+rs2)); } } } @@ -10101,7 +10081,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2, (int64_t)*(X+rs2)); } } } @@ -10142,7 +10122,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2, (int64_t)*(X+rs2)); } } } @@ -10183,7 +10163,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2, (int64_t)*(X+rs2)); } } } @@ -10224,7 +10204,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3, (int64_t)*(X+rs2)); } } } @@ -10265,7 +10245,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3, (int64_t)*(X+rs2)); } } } @@ -10306,7 +10286,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3, (int64_t)*(X+rs2)); } } } @@ -10347,7 +10327,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3, (int64_t)*(X+rs2)); } } } @@ -10388,7 +10368,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4, (int64_t)*(X+rs2)); } } } @@ -10429,7 +10409,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4, (int64_t)*(X+rs2)); } } } @@ -10470,7 +10450,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4, (int64_t)*(X+rs2)); } } } @@ -10511,7 +10491,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4, (int64_t)*(X+rs2)); } } } @@ -10552,7 +10532,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5, (int64_t)*(X+rs2)); } } } @@ -10593,7 +10573,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5, (int64_t)*(X+rs2)); } } } @@ -10634,7 +10614,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5, (int64_t)*(X+rs2)); } } } @@ -10675,7 +10655,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5, (int64_t)*(X+rs2)); } } } @@ -10716,7 +10696,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6, (int64_t)*(X+rs2)); } } } @@ -10757,7 +10737,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6, (int64_t)*(X+rs2)); } } } @@ -10798,7 +10778,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6, (int64_t)*(X+rs2)); } } } @@ -10839,7 +10819,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6, (int64_t)*(X+rs2)); } } } @@ -10880,7 +10860,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7, (int64_t)*(X+rs2)); } } } @@ -10921,7 +10901,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7, (int64_t)*(X+rs2)); } } } @@ -10962,7 +10942,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7, (int64_t)*(X+rs2)); } } } @@ -11003,7 +10983,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7, (int64_t)*(X+rs2)); } } } @@ -11044,7 +11024,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8, (int64_t)*(X+rs2)); } } } @@ -11085,7 +11065,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8, (int64_t)*(X+rs2)); } } } @@ -11126,7 +11106,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8, (int64_t)*(X+rs2)); } } } @@ -11167,7 +11147,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlsseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vlsseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8, (int64_t)*(X+rs2)); } } } @@ -11208,7 +11188,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 1, (int64_t)*(X+rs2)); } } } @@ -11249,7 +11229,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 1, (int64_t)*(X+rs2)); } } } @@ -11290,7 +11270,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 1, (int64_t)*(X+rs2)); } } } @@ -11331,7 +11311,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 1, (int64_t)*(X+rs2)); } } } @@ -11372,7 +11352,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 2, (int64_t)*(X+rs2)); } } } @@ -11413,7 +11393,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 2, (int64_t)*(X+rs2)); } } } @@ -11454,7 +11434,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 2, (int64_t)*(X+rs2)); } } } @@ -11495,7 +11475,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 2, (int64_t)*(X+rs2)); } } } @@ -11536,7 +11516,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 3, (int64_t)*(X+rs2)); } } } @@ -11577,7 +11557,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 3, (int64_t)*(X+rs2)); } } } @@ -11618,7 +11598,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 3, (int64_t)*(X+rs2)); } } } @@ -11659,7 +11639,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 3, (int64_t)*(X+rs2)); } } } @@ -11700,7 +11680,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 4, (int64_t)*(X+rs2)); } } } @@ -11741,7 +11721,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 4, (int64_t)*(X+rs2)); } } } @@ -11782,7 +11762,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 4, (int64_t)*(X+rs2)); } } } @@ -11823,7 +11803,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 4, (int64_t)*(X+rs2)); } } } @@ -11864,7 +11844,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 5, (int64_t)*(X+rs2)); } } } @@ -11905,7 +11885,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 5, (int64_t)*(X+rs2)); } } } @@ -11946,7 +11926,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 5, (int64_t)*(X+rs2)); } } } @@ -11987,7 +11967,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 5, (int64_t)*(X+rs2)); } } } @@ -12028,7 +12008,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 6, (int64_t)*(X+rs2)); } } } @@ -12069,7 +12049,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 6, (int64_t)*(X+rs2)); } } } @@ -12110,7 +12090,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 6, (int64_t)*(X+rs2)); } } } @@ -12151,7 +12131,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 6, (int64_t)*(X+rs2)); } } } @@ -12192,7 +12172,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 7, (int64_t)*(X+rs2)); } } } @@ -12233,7 +12213,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 7, (int64_t)*(X+rs2)); } } } @@ -12274,7 +12254,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 7, (int64_t)*(X+rs2)); } } } @@ -12315,7 +12295,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 7, (int64_t)*(X+rs2)); } } } @@ -12356,7 +12336,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 0, 8, (int64_t)*(X+rs2)); } } } @@ -12397,7 +12377,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 5, 8, (int64_t)*(X+rs2)); } } } @@ -12438,7 +12418,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 6, 8, (int64_t)*(X+rs2)); } } } @@ -12479,7 +12459,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vssseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8, (int64_t)*(X+rs2)); + *vstart = (uint64_t)vssseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), 7, 8, (int64_t)*(X+rs2)); } } } @@ -12518,7 +12498,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 1); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12560,7 +12540,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 1); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12602,7 +12582,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 1); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12644,7 +12624,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 1); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12686,7 +12666,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 2); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12728,7 +12708,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 2); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12770,7 +12750,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 2); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12812,7 +12792,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 2); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12854,7 +12834,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 3); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12896,7 +12876,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 3); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12938,7 +12918,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 3); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -12980,7 +12960,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 3); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13022,7 +13002,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 4); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13064,7 +13044,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 4); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13106,7 +13086,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 4); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13148,7 +13128,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 4); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13190,7 +13170,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 5); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13232,7 +13212,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 5); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13274,7 +13254,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 5); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13316,7 +13296,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 5); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13358,7 +13338,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 6); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13400,7 +13380,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 6); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13442,7 +13422,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 6); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13484,7 +13464,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 6); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13526,7 +13506,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 7); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13568,7 +13548,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 7); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13610,7 +13590,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 7); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13652,7 +13632,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 7); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13694,7 +13674,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 0, 8); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13736,7 +13716,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 5, 8); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13778,7 +13758,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 6, 8); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13820,7 +13800,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint64_t trapped_idx = (uint64_t)vlseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); + uint64_t trapped_idx = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), 7, 8); if(trapped_idx != 1) { *vl = (uint64_t)trapped_idx; lower(); @@ -13859,7 +13839,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } uint64_t _vtype = (bit_sub(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint64_t)1<<6)|((uint64_t)0<<3)|bit_sub<0, 2-0+1>(*vtype); - *vstart = (uint64_t)vsseg((uint8_t*)V, evl, *vstart, _vtype, 1, vs3, *(X+rs1), 0, 1); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, _vtype, 1, vs3, *(X+rs1), 0, 1); } } break; @@ -13893,7 +13873,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } uint64_t _vtype = (bit_sub(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint64_t)1<<6)|((uint64_t)0<<3)|bit_sub<0, 2-0+1>(*vtype); - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, _vtype, 1, vd, *(X+rs1), 0, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, _vtype, 1, vd, *(X+rs1), 0, 1); } } break; @@ -13924,7 +13904,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint64_t evl = (uint64_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); } } } @@ -13956,7 +13936,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint64_t evl = (uint64_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(16)); if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); } } } @@ -13988,7 +13968,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint64_t evl = (uint64_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(32)); if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); } } } @@ -14020,7 +14000,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint64_t evl = (uint64_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(64)); if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); } } } @@ -14056,7 +14036,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); } } } @@ -14093,7 +14073,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); } } } @@ -14130,7 +14110,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); } } } @@ -14167,7 +14147,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); } } } @@ -14204,7 +14184,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); } } } @@ -14241,7 +14221,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); } } } @@ -14278,7 +14258,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); } } } @@ -14315,7 +14295,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); } } } @@ -14352,7 +14332,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 0, 1); } } } @@ -14389,7 +14369,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 5, 1); } } } @@ -14426,7 +14406,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 6, 1); } } } @@ -14463,7 +14443,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vlseg((uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); + *vstart = (uint64_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vd, *(X+rs1), 7, 1); } } } @@ -14495,7 +14475,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint64_t evl = (uint64_t)((uint64_t)(1) * (uint64_t)(traits::VLEN) / (uint64_t)(8)); if(evl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); } } } @@ -14530,7 +14510,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); } } } @@ -14566,7 +14546,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); } } } @@ -14602,7 +14582,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(evl > *vstart) { - *vstart = (uint64_t)vsseg((uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); + *vstart = (uint64_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, *vtype, 1, vs3, *(X+rs1), 0, 1); } } } @@ -14643,7 +14623,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 1); } } } @@ -14684,7 +14664,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 1); } } } @@ -14725,7 +14705,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 1); } } } @@ -14766,7 +14746,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 1); } } } @@ -14807,7 +14787,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 1); } } } @@ -14848,7 +14828,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 1); } } } @@ -14889,7 +14869,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 1); } } } @@ -14930,7 +14910,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 1); } } } @@ -14971,7 +14951,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 1); } } } @@ -15012,7 +14992,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 1); } } } @@ -15053,7 +15033,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 1); } } } @@ -15094,7 +15074,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 1); } } } @@ -15135,7 +15115,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 1); } } } @@ -15176,7 +15156,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 1); } } } @@ -15217,7 +15197,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 1); } } } @@ -15258,7 +15238,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 1); } } } @@ -15299,7 +15279,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 1); } } } @@ -15340,7 +15320,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 1); } } } @@ -15381,7 +15361,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 1); } } } @@ -15422,7 +15402,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 1); } } } @@ -15463,7 +15443,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 1); } } } @@ -15504,7 +15484,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 1); } } } @@ -15545,7 +15525,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 1); } } } @@ -15586,7 +15566,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 1); } } } @@ -15627,7 +15607,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 1); } } } @@ -15668,7 +15648,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 1); } } } @@ -15709,7 +15689,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 1); } } } @@ -15750,7 +15730,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 1); } } } @@ -15791,7 +15771,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 1); } } } @@ -15832,7 +15812,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 1); } } } @@ -15873,7 +15853,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 1); } } } @@ -15914,7 +15894,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 1); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 1); } } } @@ -15955,7 +15935,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 1); } } } @@ -15996,7 +15976,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 1); } } } @@ -16037,7 +16017,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 1); } } } @@ -16078,7 +16058,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 1); } } } @@ -16119,7 +16099,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 1); } } } @@ -16160,7 +16140,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 1); } } } @@ -16201,7 +16181,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 1); } } } @@ -16242,7 +16222,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 1); } } } @@ -16283,7 +16263,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 1); } } } @@ -16324,7 +16304,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 1); } } } @@ -16365,7 +16345,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 1); } } } @@ -16406,7 +16386,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 1); } } } @@ -16447,7 +16427,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 1); } } } @@ -16488,7 +16468,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 1); } } } @@ -16529,7 +16509,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 1); } } } @@ -16570,7 +16550,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 1); } } } @@ -16611,7 +16591,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 1); } } } @@ -16652,7 +16632,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 1); } } } @@ -16693,7 +16673,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 1); } } } @@ -16734,7 +16714,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 1); } } } @@ -16775,7 +16755,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 1); } } } @@ -16816,7 +16796,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 1); } } } @@ -16857,7 +16837,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 1); } } } @@ -16898,7 +16878,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 1); } } } @@ -16939,7 +16919,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 1); } } } @@ -16980,7 +16960,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 1); } } } @@ -17021,7 +17001,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 1); } } } @@ -17062,7 +17042,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 1); } } } @@ -17103,7 +17083,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 1); } } } @@ -17144,7 +17124,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 1); } } } @@ -17185,7 +17165,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 1); } } } @@ -17226,7 +17206,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 1); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 1); } } } @@ -17267,7 +17247,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 1, sew(), 0); } } } @@ -17308,7 +17288,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 2, sew(), 0); } } } @@ -17349,7 +17329,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 4, sew(), 0); } } } @@ -17390,7 +17370,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 1, 8, sew(), 0); } } } @@ -17431,7 +17411,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 1, sew(), 0); } } } @@ -17472,7 +17452,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 2, sew(), 0); } } } @@ -17513,7 +17493,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 4, sew(), 0); } } } @@ -17554,7 +17534,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 2, 8, sew(), 0); } } } @@ -17595,7 +17575,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 1, sew(), 0); } } } @@ -17636,7 +17616,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 2, sew(), 0); } } } @@ -17677,7 +17657,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 4, sew(), 0); } } } @@ -17718,7 +17698,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 3, 8, sew(), 0); } } } @@ -17759,7 +17739,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 1, sew(), 0); } } } @@ -17800,7 +17780,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 2, sew(), 0); } } } @@ -17841,7 +17821,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 4, sew(), 0); } } } @@ -17882,7 +17862,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 4, 8, sew(), 0); } } } @@ -17923,7 +17903,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 1, sew(), 0); } } } @@ -17964,7 +17944,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 2, sew(), 0); } } } @@ -18005,7 +17985,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 4, sew(), 0); } } } @@ -18046,7 +18026,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 5, 8, sew(), 0); } } } @@ -18087,7 +18067,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 1, sew(), 0); } } } @@ -18128,7 +18108,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 2, sew(), 0); } } } @@ -18169,7 +18149,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 4, sew(), 0); } } } @@ -18210,7 +18190,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 6, 8, sew(), 0); } } } @@ -18251,7 +18231,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 1, sew(), 0); } } } @@ -18292,7 +18272,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 2, sew(), 0); } } } @@ -18333,7 +18313,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 4, sew(), 0); } } } @@ -18374,7 +18354,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 7, 8, sew(), 0); } } } @@ -18415,7 +18395,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 1, sew(), 0); } } } @@ -18456,7 +18436,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 2, sew(), 0); } } } @@ -18497,7 +18477,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 4, sew(), 0); } } } @@ -18538,7 +18518,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vlxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 0); + *vstart = (uint64_t)vlxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vd, *(X+rs1), vs2, 8, 8, sew(), 0); } } } @@ -18579,7 +18559,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 1, sew(), 0); } } } @@ -18620,7 +18600,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 2, sew(), 0); } } } @@ -18661,7 +18641,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 4, sew(), 0); } } } @@ -18702,7 +18682,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 1, 8, sew(), 0); } } } @@ -18743,7 +18723,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 1, sew(), 0); } } } @@ -18784,7 +18764,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 2, sew(), 0); } } } @@ -18825,7 +18805,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 4, sew(), 0); } } } @@ -18866,7 +18846,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 2, 8, sew(), 0); } } } @@ -18907,7 +18887,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 1, sew(), 0); } } } @@ -18948,7 +18928,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 2, sew(), 0); } } } @@ -18989,7 +18969,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 4, sew(), 0); } } } @@ -19030,7 +19010,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 3, 8, sew(), 0); } } } @@ -19071,7 +19051,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 1, sew(), 0); } } } @@ -19112,7 +19092,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 2, sew(), 0); } } } @@ -19153,7 +19133,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 4, sew(), 0); } } } @@ -19194,7 +19174,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 4, 8, sew(), 0); } } } @@ -19235,7 +19215,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 1, sew(), 0); } } } @@ -19276,7 +19256,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 2, sew(), 0); } } } @@ -19317,7 +19297,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 4, sew(), 0); } } } @@ -19358,7 +19338,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 5, 8, sew(), 0); } } } @@ -19399,7 +19379,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 1, sew(), 0); } } } @@ -19440,7 +19420,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 2, sew(), 0); } } } @@ -19481,7 +19461,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 4, sew(), 0); } } } @@ -19522,7 +19502,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 6, 8, sew(), 0); } } } @@ -19563,7 +19543,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 1, sew(), 0); } } } @@ -19604,7 +19584,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 2, sew(), 0); } } } @@ -19645,7 +19625,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 4, sew(), 0); } } } @@ -19686,7 +19666,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 7, 8, sew(), 0); } } } @@ -19727,7 +19707,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 1, sew(), 0); } } } @@ -19768,7 +19748,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 2, sew(), 0); } } } @@ -19809,7 +19789,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 4, sew(), 0); } } } @@ -19850,7 +19830,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*vl > *vstart) { - *vstart = (uint64_t)vsxseg((uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 0); + *vstart = (uint64_t)vsxseg(this->get_arch(), (uint8_t*)V, *vl, *vstart, *vtype, vm, vs3, *(X+rs1), vs2, 8, 8, sew(), 0); } } } From 4553fdc29e29336b0948e00a0244ad6b72cba37f Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Tue, 23 Sep 2025 12:03:42 +0200 Subject: [PATCH 014/230] adds asmjit rvgcv --- CMakeLists.txt | 2 + gen_input/templates/asmjit/CORENAME.cpp.gtl | 76 +- src/sysc/register_rv64gcv.cpp | 22 + src/vm/asmjit/vm_rv32gcv.cpp | 86126 +++++++++++++++++ src/vm/asmjit/vm_rv64gcv.cpp | 88707 ++++++++++++++++++ 5 files changed, 174927 insertions(+), 6 deletions(-) create mode 100644 src/vm/asmjit/vm_rv32gcv.cpp create mode 100644 src/vm/asmjit/vm_rv64gcv.cpp diff --git a/CMakeLists.txt b/CMakeLists.txt index a1cf9e7..cca601e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -104,8 +104,10 @@ if(WITH_ASMJIT) src/vm/asmjit/vm_rv32i.cpp src/vm/asmjit/vm_rv32imac.cpp src/vm/asmjit/vm_rv32gc.cpp + src/vm/asmjit/vm_rv32gcv.cpp src/vm/asmjit/vm_rv64i.cpp src/vm/asmjit/vm_rv64gc.cpp + src/vm/asmjit/vm_rv64gcv.cpp ) endif() diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index bc583bb..5e48a0e 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -29,6 +29,14 @@ * POSSIBILITY OF SUCH DAMAGE. * *******************************************************************************/ + <% +def floating_point = registers.find {it.name=='FCSR'} != null +def vector = registers.find {it.name=='vtype'} != null +def aes = functions.find { it.contains('aes') } != null +def nativeTypeSize(int size){ + if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64; +} +%> // clang-format off #include #include @@ -38,11 +46,19 @@ #include #include #include -<%def fcsr = registers.find {it.name=='FCSR'} -if(fcsr != null) {%> -#include <%} -def aes = functions.find { it.contains('aes') } -if(aes != null) {%> +<% +if(floating_point) {%> +#include +<%} +if(vector) { +def xlen = constants.find { it.name == 'XLEN' }?.value ?: 0 +def vlen = constants.find { it.name == 'VLEN' }?.value ?: 0 %> +#define CUR_VLEN ${vlen} +#define CUR_XLEN ${xlen} +#include +#include +<%} +if(aes) {%> #include <%}%> #ifndef FMT_HEADER_ONLY @@ -121,12 +137,52 @@ protected: void gen_block_prologue(jit_holder& jh) override; void gen_block_epilogue(jit_holder& jh) override; inline const char *name(size_t index){return traits::reg_aliases.at(index);} -<%if(fcsr != null) {%> +<%if(floating_point) {%> inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";} +<%} +if(vector) {%> + inline const char* vname(size_t index) { return index < 32 ? name(index + traits::V0) : "illegal"; } + inline const char* sew_name(size_t bits) { + switch(bits) { + case 0b000: + return "e8"; + case 0b001: + return "e16"; + case 0b010: + return "e32"; + case 0b011: + return "e64"; + default: + return "illegal"; + } + } + inline const char* lmul_name(size_t bits) { + switch(bits) { + case 0b101: + return "mf8"; + case 0b110: + return "mf4"; + case 0b111: + return "mf2"; + case 0b000: + return "m1"; + case 0b001: + return "m2"; + case 0b010: + return "m4"; + case 0b011: + return "m8"; + default: + return "illegal"; + } + } + inline const char* ma_name(bool ma) { return ma ? "ma" : "mu"; } + inline const char* ta_name(bool ta) { return ta ? "ta" : "tu"; } <%}%> void gen_instr_prologue(jit_holder& jh); void gen_instr_epilogue(jit_holder& jh); inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause); + inline void gen_lower(jit_holder& jh); template ::value>::type> void gen_set_tval(jit_holder& jh, T new_tval) ; void gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) ; @@ -333,6 +389,14 @@ inline void vm_impl::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cc.jmp(jh.trap_entry); } template +inline void vm_impl::gen_lower(jit_holder& jh) { + auto& cc = jh.cc; + auto tmp1 = get_reg_for(cc, traits::TRAP_STATE); + mov(cc, tmp1, 0); + mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1); + cc.jmp(jh.trap_entry); +} +template template void vm_impl::gen_set_tval(jit_holder& jh, T new_tval) { mov(jh.cc, jh.globals[TVAL], new_tval); diff --git a/src/sysc/register_rv64gcv.cpp b/src/sysc/register_rv64gcv.cpp index 92b54fe..0e7878e 100644 --- a/src/sysc/register_rv64gcv.cpp +++ b/src/sysc/register_rv64gcv.cpp @@ -95,5 +95,27 @@ volatile std::array rv64gcv_init = { }; } #endif +#if defined(WITH_ASMJIT) +namespace asmjit { +using namespace sysc; +volatile std::array rv64gcv_init = { + iss_factory::instance().register_creator("rv64gcv_msu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv64gcv_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv64gcv_mu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }) +}; +} +#endif } // clang-format on diff --git a/src/vm/asmjit/vm_rv32gcv.cpp b/src/vm/asmjit/vm_rv32gcv.cpp new file mode 100644 index 0000000..2474b96 --- /dev/null +++ b/src/vm/asmjit/vm_rv32gcv.cpp @@ -0,0 +1,86126 @@ +/******************************************************************************* + * Copyright (C) 2024 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +// clang-format off +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define CUR_VLEN 256 +#define CUR_XLEN 32 +#include +#include + +#ifndef FMT_HEADER_ONLY +#define FMT_HEADER_ONLY +#endif +#include + +#include +#include + +#ifndef _MSC_VER +using int128_t = __int128; +using uint128_t = unsigned __int128; +namespace std { +template <> struct make_unsigned<__int128> { typedef unsigned __int128 type; }; +template <> class __make_unsigned_selector<__int128 unsigned, false, false> { +public: + typedef unsigned __int128 __type; +}; +template <> struct is_signed { static constexpr bool value = true; }; +template <> struct is_signed { static constexpr bool value = false; }; +template <> struct is_unsigned { static constexpr bool value = false; }; +template <> struct is_unsigned { static constexpr bool value = true; }; +} // namespace std +#endif + +namespace iss { +namespace asmjit { + + +namespace rv32gcv { +using namespace ::asmjit; +using namespace iss::arch; +using namespace iss::debugger; + +template class vm_impl : public iss::asmjit::vm_base { +public: + using traits = arch::traits; + using super = typename iss::asmjit::vm_base; + using virt_addr_t = typename super::virt_addr_t; + using phys_addr_t = typename super::phys_addr_t; + using code_word_t = typename super::code_word_t; + using mem_type_e = typename super::mem_type_e; + using addr_t = typename super::addr_t; + + vm_impl(); + + vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); + + void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } + + target_adapter_if *accquire_target_adapter(server_if *srv) override { + debugger_if::dbg_enabled = true; + if (vm_base::tgt_adapter == nullptr) + vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); + return vm_base::tgt_adapter; + } + +protected: + using super::get_ptr_for; + using super::get_reg_for; + using super::get_reg_for_Gp; + using super::load_reg_from_mem; + using super::load_reg_from_mem_Gp; + using super::write_reg_to_mem; + using super::gen_read_mem; + using super::gen_write_mem; + using super::gen_leave; + using super::gen_sync; + + using this_class = vm_impl; + using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&); + + continuation_e gen_single_inst_behavior(virt_addr_t&, jit_holder&) override; + enum globals_e {TVAL = 0, GLOBALS_SIZE}; + void gen_block_prologue(jit_holder& jh) override; + void gen_block_epilogue(jit_holder& jh) override; + inline const char *name(size_t index){return traits::reg_aliases.at(index);} + + inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";} + + inline const char* vname(size_t index) { return index < 32 ? name(index + traits::V0) : "illegal"; } + inline const char* sew_name(size_t bits) { + switch(bits) { + case 0b000: + return "e8"; + case 0b001: + return "e16"; + case 0b010: + return "e32"; + case 0b011: + return "e64"; + default: + return "illegal"; + } + } + inline const char* lmul_name(size_t bits) { + switch(bits) { + case 0b101: + return "mf8"; + case 0b110: + return "mf4"; + case 0b111: + return "mf2"; + case 0b000: + return "m1"; + case 0b001: + return "m2"; + case 0b010: + return "m4"; + case 0b011: + return "m8"; + default: + return "illegal"; + } + } + inline const char* ma_name(bool ma) { return ma ? "ma" : "mu"; } + inline const char* ta_name(bool ta) { return ta ? "ta" : "tu"; } + + void gen_instr_prologue(jit_holder& jh); + void gen_instr_epilogue(jit_holder& jh); + inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause); + inline void gen_lower(jit_holder& jh); + template ::value>::type> void gen_set_tval(jit_holder& jh, T new_tval) ; + void gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) ; + + template::type> + inline S sext(U from) { + auto mask = (1ULL<core.reg.trap_state = trap_val; + } + + + static uint64_t _NaNBox32(void* vm_impl_ptr , uint32_t val){ + return reinterpret_cast(vm_impl_ptr)->NaNBox32(val); + } + uint64_t NaNBox32(uint32_t val){ + if(traits::FLEN == 32) { + return (uint64_t)val; + } + else { + uint64_t box = ~((uint64_t)0); + return (uint64_t)(((uint128_t)box<<32)|val); + } + } + static uint8_t _get_rm(void* vm_impl_ptr , uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->get_rm(rm); + } + uint8_t get_rm(uint8_t rm){ + auto* FCSR = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::FCSR]); + uint8_t rm_eff = rm == 7? bit_sub<5, 7-5+1>(*FCSR) : rm; + if(rm_eff > 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return rm_eff; + } + static uint64_t _NaNBox64(void* vm_impl_ptr , uint64_t val){ + return reinterpret_cast(vm_impl_ptr)->NaNBox64(val); + } + uint64_t NaNBox64(uint64_t val){ + if(traits::FLEN == 64) { + return (uint64_t)val; + } + else { + uint64_t box = ~((uint64_t)0); + return (uint64_t)(((uint128_t)box<<64)|val); + } + } + static uint8_t _get_pow(void* vm_impl_ptr , uint32_t val){ + return reinterpret_cast(vm_impl_ptr)->get_pow(val); + } + uint8_t get_pow(uint32_t val){ + switch(val){ + case 8: + return 3; + case 16: + return 4; + case 32: + return 5; + case 64: + return 6; + case 128: + return 7; + case 256: + return 8; + case 512: + return 9; + case 1024: + return 10; + case 2048: + return 11; + case 4096: + return 12; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + static uint8_t _lmul(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->lmul(); + } + uint8_t lmul(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub<0, 2-0+1>(*vtype); + } + static uint8_t _sew(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->sew(); + } + uint8_t sew(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub<3, 5-3+1>(*vtype); + } + static int8_t _get_lmul_pow(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->get_lmul_pow(); + } + int8_t get_lmul_pow(){ + switch(lmul()){ + case 5: + return - 3; + case 6: + return - 2; + case 7: + return - 1; + case 0: + return 0; + case 1: + return 1; + case 2: + return 2; + case 3: + return 3; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + static uint8_t _get_sew_pow(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->get_sew_pow(); + } + uint8_t get_sew_pow(){ + switch(sew()){ + case 0: + return 3; + case 1: + return 4; + case 2: + return 5; + case 3: + return 6; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + static uint16_t _get_elem_count(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->get_elem_count(); + } + uint16_t get_elem_count(){ + uint8_t total_pow = (uint8_t)((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow())); + return (uint16_t)(1 << total_pow) & ~1; + } + static uint8_t _valid_vtype(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->valid_vtype(); + } + uint8_t valid_vtype(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub(*vtype, (uint64_t)(traits::XLEN) - (uint64_t)(1), 1) == 0; + } + static uint8_t _valid_rd_mask(void* vm_impl_ptr , uint8_t rd, uint8_t vm){ + return reinterpret_cast(vm_impl_ptr)->valid_rd_mask(rd,vm); + } + uint8_t valid_rd_mask(uint8_t rd, uint8_t vm){ + return rd != 0 || vm != 0; + } + static uint8_t _valid_eew_emul(void* vm_impl_ptr , uint8_t EEW, int8_t EMUL_pow){ + return reinterpret_cast(vm_impl_ptr)->valid_eew_emul(EEW,EMUL_pow); + } + uint8_t valid_eew_emul(uint8_t EEW, int8_t EMUL_pow){ + return EEW >= 8 && EEW <= traits::ELEN && EEW <= traits::EEW_MAX && EMUL_pow >= - 3 && EMUL_pow <= 3; + } + static uint8_t _valid_segment(void* vm_impl_ptr , uint8_t nf, int8_t EMUL_pow){ + return reinterpret_cast(vm_impl_ptr)->valid_segment(nf,EMUL_pow); + } + uint8_t valid_segment(uint8_t nf, int8_t EMUL_pow){ + if(EMUL_pow < 0) { + uint8_t neg_EMUL = (uint8_t)(1 << - EMUL_pow) & ~1; + return nf / neg_EMUL <= 8; + } + else { + uint8_t EMUL = (uint8_t)(1 << EMUL_pow) & ~1; + return (uint16_t)(nf) * (uint16_t)(EMUL) <= 8; + } + } + static uint8_t _illegal_vd_unmasked(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->illegal_vd_unmasked(); + } + uint8_t illegal_vd_unmasked(){ + return ! valid_vtype(); + } + static uint8_t _illegal_variable_width(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return reinterpret_cast(vm_impl_ptr)->illegal_variable_width(vd,vm,SEW_new,LMUL_pow_new); + } + uint8_t illegal_variable_width(uint8_t vd, uint8_t vm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_eew_emul(SEW_new, LMUL_pow_new)); + } + static uint8_t _valid_reg_overlap(void* vm_impl_ptr , uint8_t rs, uint8_t rd, int8_t EMUL_pow_rs, int8_t EMUL_pow_rd){ + return reinterpret_cast(vm_impl_ptr)->valid_reg_overlap(rs,rd,EMUL_pow_rs,EMUL_pow_rd); + } + uint8_t valid_reg_overlap(uint8_t rs, uint8_t rd, int8_t EMUL_pow_rs, int8_t EMUL_pow_rd){ + uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& (1ULL << 4) : 1; + uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& (1ULL << 4) : 1; + if(EMUL_pow_rs < EMUL_pow_rd) { + return (rs + rs_group <= rd) || (rs >= rd + rd_group) || ((rs + rs_group == rd + rd_group) & (EMUL_pow_rs >= 0)); + } + else { + if(EMUL_pow_rs > EMUL_pow_rd) { + return (rd <= rs) || (rd >= rs + rs_group); + } + else { + return true; + } + } + } + static uint8_t _illegal_vd_masked(void* vm_impl_ptr , uint8_t vd){ + return reinterpret_cast(vm_impl_ptr)->illegal_vd_masked(vd); + } + uint8_t illegal_vd_masked(uint8_t vd){ + return ! (valid_vtype()) || vd == 0; + } + static uint8_t _illegal_normal(void* vm_impl_ptr , uint8_t vd, uint8_t vm){ + return reinterpret_cast(vm_impl_ptr)->illegal_normal(vd,vm); + } + uint8_t illegal_normal(uint8_t vd, uint8_t vm){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)); + } + static uint8_t _valid_fp_op(void* vm_impl_ptr , uint8_t SEW, uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->valid_fp_op(SEW,rm); + } + uint8_t valid_fp_op(uint8_t SEW, uint8_t rm){ + int8_t valid_sew = (traits::FP_SEW_MIN >= 32 & SEW <= traits::FP_SEW_MAX); + int8_t valid_rm = ! (rm == 5 | rm == 6 | rm == 7); + return valid_sew && valid_rm; + } + static uint8_t _illegal_fp_vd_unmasked(void* vm_impl_ptr , uint8_t SEW, uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_vd_unmasked(SEW,rm); + } + uint8_t illegal_fp_vd_unmasked(uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || ! (valid_fp_op(SEW, rm)); + } + static uint8_t _illegal_fp_normal(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_normal(vd,vm,SEW,rm); + } + uint8_t illegal_fp_normal(uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_fp_op(SEW, rm)); + } + static uint8_t _valid_sew_lmul(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->valid_sew_lmul(); + } + uint8_t valid_sew_lmul(){ + return get_sew_pow() <= (uint16_t)(get_pow(traits::ELEN)) + (int16_t)(get_lmul_pow()); + } + static uint16_t _calculate_new_vl(void* vm_impl_ptr , uint32_t avl, uint16_t vlmax){ + return reinterpret_cast(vm_impl_ptr)->calculate_new_vl(avl,vlmax); + } + uint16_t calculate_new_vl(uint32_t avl, uint16_t vlmax){ + if(avl <= vlmax) { + return ((uint16_t)avl); + } + else { + if(avl < ((uint32_t)(2) * (uint32_t)(vlmax))) { + return vlmax; + } + else { + return vlmax; + } + } + } + static + void _handle_illegal_vtype(void* vm_impl_ptr ){ + reinterpret_cast(vm_impl_ptr)->handle_illegal_vtype(); + } + void handle_illegal_vtype(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + auto* vl = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vl]); + *vtype = (uint32_t)1 << ((uint64_t)(traits::XLEN) - (uint64_t)(1)); + *vl = (uint32_t)0; + } + static uint8_t _convert_width(void* vm_impl_ptr , uint8_t width){ + return reinterpret_cast(vm_impl_ptr)->convert_width(width); + } + uint8_t convert_width(uint8_t width){ + switch(width){ + case (0): + return 1; + case (5): + return 2; + case (6): + return 4; + case (7): + return 8; + } + return 0; + } + static uint8_t _illegal_load(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return reinterpret_cast(vm_impl_ptr)->illegal_load(vd,vm,nf,EEW,EMUL_pow); + } + uint8_t illegal_load(uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return ! valid_vtype() || ! valid_rd_mask(vd, vm) || ! valid_eew_emul(EEW, EMUL_pow) || ! valid_segment(nf, EMUL_pow); + } + static uint8_t _illegal_store(void* vm_impl_ptr , uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return reinterpret_cast(vm_impl_ptr)->illegal_store(nf,EEW,EMUL_pow); + } + uint8_t illegal_store(uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return ! valid_vtype() || ! valid_eew_emul(EEW, EMUL_pow) || ! valid_segment(nf, EMUL_pow); + } + static uint8_t _illegal_indexed_load(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return reinterpret_cast(vm_impl_ptr)->illegal_indexed_load(vd,vm,nf,EEW_index,EMUL_pow_index,EMUL_pow_data); + } + uint8_t illegal_indexed_load(uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return ! valid_vtype() || ! valid_rd_mask(vd, vm) || ! valid_eew_emul(EEW_index, EMUL_pow_index) || ! valid_segment(nf, EMUL_pow_data); + } + static uint8_t _illegal_indexed_store(void* vm_impl_ptr , uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return reinterpret_cast(vm_impl_ptr)->illegal_indexed_store(nf,EEW_index,EMUL_pow_index,EMUL_pow_data); + } + uint8_t illegal_indexed_store(uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return ! valid_vtype() || ! valid_eew_emul(EEW_index, EMUL_pow_index) || ! valid_segment(nf, EMUL_pow_data); + } + static uint8_t _illegal_reduction(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->illegal_reduction(); + } + uint8_t illegal_reduction(){ + auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); + return ! valid_vtype() || *vstart != 0; + } + static uint8_t _illegal_reduction_widen(void* vm_impl_ptr , uint8_t EEW, int8_t EMUL_pow){ + return reinterpret_cast(vm_impl_ptr)->illegal_reduction_widen(EEW,EMUL_pow); + } + uint8_t illegal_reduction_widen(uint8_t EEW, int8_t EMUL_pow){ + return illegal_reduction() || ! valid_eew_emul(EEW, EMUL_pow); + } + static uint8_t _illegal_fp_reduction(void* vm_impl_ptr , uint8_t SEW, uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_reduction(SEW,rm); + } + uint8_t illegal_fp_reduction(uint8_t SEW, uint8_t rm){ + auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); + return ! valid_vtype() || *vstart != 0 || ! valid_fp_op(SEW, rm); + } + static uint8_t _illegal_fp_variable_width(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_variable_width(vd,vm,SEW,rm,SEW_new,LMUL_pow_new); + } + uint8_t illegal_fp_variable_width(uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_fp_op(SEW, rm)) || ! (valid_eew_emul(SEW_new, LMUL_pow_new)); + } + static uint8_t _illegal_fp_vd_masked(void* vm_impl_ptr , uint8_t vd, uint8_t SEW, uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_vd_masked(vd,SEW,rm); + } + uint8_t illegal_fp_vd_masked(uint8_t vd, uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || vd == 0 || ! (valid_fp_op(SEW, rm)); + } +private: + /**************************************************************************** + * start opcode definitions + ****************************************************************************/ + struct instruction_descriptor { + uint32_t length; + uint32_t value; + uint32_t mask; + compile_func op; + }; + + const std::array instr_descr = {{ + /* entries are: size, valid value, valid mask, function ptr */ + /* instruction LUI, encoding '0b00000000000000000000000000110111' */ + {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, + /* instruction AUIPC, encoding '0b00000000000000000000000000010111' */ + {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, + /* instruction JAL, encoding '0b00000000000000000000000001101111' */ + {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, + /* instruction JALR, encoding '0b00000000000000000000000001100111' */ + {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, + /* instruction BEQ, encoding '0b00000000000000000000000001100011' */ + {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, + /* instruction BNE, encoding '0b00000000000000000001000001100011' */ + {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne}, + /* instruction BLT, encoding '0b00000000000000000100000001100011' */ + {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt}, + /* instruction BGE, encoding '0b00000000000000000101000001100011' */ + {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge}, + /* instruction BLTU, encoding '0b00000000000000000110000001100011' */ + {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu}, + /* instruction BGEU, encoding '0b00000000000000000111000001100011' */ + {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu}, + /* instruction LB, encoding '0b00000000000000000000000000000011' */ + {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb}, + /* instruction LH, encoding '0b00000000000000000001000000000011' */ + {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh}, + /* instruction LW, encoding '0b00000000000000000010000000000011' */ + {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw}, + /* instruction LBU, encoding '0b00000000000000000100000000000011' */ + {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu}, + /* instruction LHU, encoding '0b00000000000000000101000000000011' */ + {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu}, + /* instruction SB, encoding '0b00000000000000000000000000100011' */ + {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb}, + /* instruction SH, encoding '0b00000000000000000001000000100011' */ + {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh}, + /* instruction SW, encoding '0b00000000000000000010000000100011' */ + {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw}, + /* instruction ADDI, encoding '0b00000000000000000000000000010011' */ + {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi}, + /* instruction SLTI, encoding '0b00000000000000000010000000010011' */ + {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti}, + /* instruction SLTIU, encoding '0b00000000000000000011000000010011' */ + {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu}, + /* instruction XORI, encoding '0b00000000000000000100000000010011' */ + {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori}, + /* instruction ORI, encoding '0b00000000000000000110000000010011' */ + {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, + /* instruction ANDI, encoding '0b00000000000000000111000000010011' */ + {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, + /* instruction SLLI, encoding '0b00000000000000000001000000010011' */ + {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli}, + /* instruction SRLI, encoding '0b00000000000000000101000000010011' */ + {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli}, + /* instruction SRAI, encoding '0b01000000000000000101000000010011' */ + {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai}, + /* instruction ADD, encoding '0b00000000000000000000000000110011' */ + {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, + /* instruction SUB, encoding '0b01000000000000000000000000110011' */ + {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub}, + /* instruction SLL, encoding '0b00000000000000000001000000110011' */ + {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll}, + /* instruction SLT, encoding '0b00000000000000000010000000110011' */ + {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt}, + /* instruction SLTU, encoding '0b00000000000000000011000000110011' */ + {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu}, + /* instruction XOR, encoding '0b00000000000000000100000000110011' */ + {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor}, + /* instruction SRL, encoding '0b00000000000000000101000000110011' */ + {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl}, + /* instruction SRA, encoding '0b01000000000000000101000000110011' */ + {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra}, + /* instruction OR, encoding '0b00000000000000000110000000110011' */ + {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or}, + /* instruction AND, encoding '0b00000000000000000111000000110011' */ + {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and}, + /* instruction FENCE, encoding '0b00000000000000000000000000001111' */ + {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, &this_class::__fence}, + /* instruction ECALL, encoding '0b00000000000000000000000001110011' */ + {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall}, + /* instruction EBREAK, encoding '0b00000000000100000000000001110011' */ + {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak}, + /* instruction MRET, encoding '0b00110000001000000000000001110011' */ + {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret}, + /* instruction WFI, encoding '0b00010000010100000000000001110011' */ + {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi}, + /* instruction CSRRW, encoding '0b00000000000000000001000001110011' */ + {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw}, + /* instruction CSRRS, encoding '0b00000000000000000010000001110011' */ + {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs}, + /* instruction CSRRC, encoding '0b00000000000000000011000001110011' */ + {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc}, + /* instruction CSRRWI, encoding '0b00000000000000000101000001110011' */ + {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi}, + /* instruction CSRRSI, encoding '0b00000000000000000110000001110011' */ + {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi}, + /* instruction CSRRCI, encoding '0b00000000000000000111000001110011' */ + {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci}, + /* instruction FENCE_I, encoding '0b00000000000000000001000000001111' */ + {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i}, + /* instruction MUL, encoding '0b00000010000000000000000000110011' */ + {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul}, + /* instruction MULH, encoding '0b00000010000000000001000000110011' */ + {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh}, + /* instruction MULHSU, encoding '0b00000010000000000010000000110011' */ + {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu}, + /* instruction MULHU, encoding '0b00000010000000000011000000110011' */ + {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu}, + /* instruction DIV, encoding '0b00000010000000000100000000110011' */ + {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div}, + /* instruction DIVU, encoding '0b00000010000000000101000000110011' */ + {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu}, + /* instruction REM, encoding '0b00000010000000000110000000110011' */ + {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem}, + /* instruction REMU, encoding '0b00000010000000000111000000110011' */ + {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu}, + /* instruction LRW, encoding '0b00010000000000000010000000101111' */ + {32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, &this_class::__lrw}, + /* instruction SCW, encoding '0b00011000000000000010000000101111' */ + {32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__scw}, + /* instruction AMOSWAPW, encoding '0b00001000000000000010000000101111' */ + {32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoswapw}, + /* instruction AMOADDW, encoding '0b00000000000000000010000000101111' */ + {32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoaddw}, + /* instruction AMOXORW, encoding '0b00100000000000000010000000101111' */ + {32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoxorw}, + /* instruction AMOANDW, encoding '0b01100000000000000010000000101111' */ + {32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoandw}, + /* instruction AMOORW, encoding '0b01000000000000000010000000101111' */ + {32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoorw}, + /* instruction AMOMINW, encoding '0b10000000000000000010000000101111' */ + {32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominw}, + /* instruction AMOMAXW, encoding '0b10100000000000000010000000101111' */ + {32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxw}, + /* instruction AMOMINUW, encoding '0b11000000000000000010000000101111' */ + {32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominuw}, + /* instruction AMOMAXUW, encoding '0b11100000000000000010000000101111' */ + {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxuw}, + /* instruction C__ADDI4SPN, encoding '0b0000000000000000' */ + {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c__addi4spn}, + /* instruction C__LW, encoding '0b0100000000000000' */ + {16, 0b0100000000000000, 0b1110000000000011, &this_class::__c__lw}, + /* instruction C__SW, encoding '0b1100000000000000' */ + {16, 0b1100000000000000, 0b1110000000000011, &this_class::__c__sw}, + /* instruction C__ADDI, encoding '0b0000000000000001' */ + {16, 0b0000000000000001, 0b1110000000000011, &this_class::__c__addi}, + /* instruction C__NOP, encoding '0b0000000000000001' */ + {16, 0b0000000000000001, 0b1110111110000011, &this_class::__c__nop}, + /* instruction C__JAL, encoding '0b0010000000000001' */ + {16, 0b0010000000000001, 0b1110000000000011, &this_class::__c__jal}, + /* instruction C__LI, encoding '0b0100000000000001' */ + {16, 0b0100000000000001, 0b1110000000000011, &this_class::__c__li}, + /* instruction C__LUI, encoding '0b0110000000000001' */ + {16, 0b0110000000000001, 0b1110000000000011, &this_class::__c__lui}, + /* instruction C__ADDI16SP, encoding '0b0110000100000001' */ + {16, 0b0110000100000001, 0b1110111110000011, &this_class::__c__addi16sp}, + /* instruction __reserved_clui, encoding '0b0110000000000001' */ + {16, 0b0110000000000001, 0b1111000001111111, &this_class::____reserved_clui}, + /* instruction C__SRLI, encoding '0b1000000000000001' */ + {16, 0b1000000000000001, 0b1111110000000011, &this_class::__c__srli}, + /* instruction C__SRAI, encoding '0b1000010000000001' */ + {16, 0b1000010000000001, 0b1111110000000011, &this_class::__c__srai}, + /* instruction C__ANDI, encoding '0b1000100000000001' */ + {16, 0b1000100000000001, 0b1110110000000011, &this_class::__c__andi}, + /* instruction C__SUB, encoding '0b1000110000000001' */ + {16, 0b1000110000000001, 0b1111110001100011, &this_class::__c__sub}, + /* instruction C__XOR, encoding '0b1000110000100001' */ + {16, 0b1000110000100001, 0b1111110001100011, &this_class::__c__xor}, + /* instruction C__OR, encoding '0b1000110001000001' */ + {16, 0b1000110001000001, 0b1111110001100011, &this_class::__c__or}, + /* instruction C__AND, encoding '0b1000110001100001' */ + {16, 0b1000110001100001, 0b1111110001100011, &this_class::__c__and}, + /* instruction C__J, encoding '0b1010000000000001' */ + {16, 0b1010000000000001, 0b1110000000000011, &this_class::__c__j}, + /* instruction C__BEQZ, encoding '0b1100000000000001' */ + {16, 0b1100000000000001, 0b1110000000000011, &this_class::__c__beqz}, + /* instruction C__BNEZ, encoding '0b1110000000000001' */ + {16, 0b1110000000000001, 0b1110000000000011, &this_class::__c__bnez}, + /* instruction C__SLLI, encoding '0b0000000000000010' */ + {16, 0b0000000000000010, 0b1111000000000011, &this_class::__c__slli}, + /* instruction C__LWSP, encoding '0b0100000000000010' */ + {16, 0b0100000000000010, 0b1110000000000011, &this_class::__c__lwsp}, + /* instruction C__MV, encoding '0b1000000000000010' */ + {16, 0b1000000000000010, 0b1111000000000011, &this_class::__c__mv}, + /* instruction C__JR, encoding '0b1000000000000010' */ + {16, 0b1000000000000010, 0b1111000001111111, &this_class::__c__jr}, + /* instruction __reserved_cmv, encoding '0b1000000000000010' */ + {16, 0b1000000000000010, 0b1111111111111111, &this_class::____reserved_cmv}, + /* instruction C__ADD, encoding '0b1001000000000010' */ + {16, 0b1001000000000010, 0b1111000000000011, &this_class::__c__add}, + /* instruction C__JALR, encoding '0b1001000000000010' */ + {16, 0b1001000000000010, 0b1111000001111111, &this_class::__c__jalr}, + /* instruction C__EBREAK, encoding '0b1001000000000010' */ + {16, 0b1001000000000010, 0b1111111111111111, &this_class::__c__ebreak}, + /* instruction C__SWSP, encoding '0b1100000000000010' */ + {16, 0b1100000000000010, 0b1110000000000011, &this_class::__c__swsp}, + /* instruction DII, encoding '0b0000000000000000' */ + {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, + /* instruction FLW, encoding '0b00000000000000000010000000000111' */ + {32, 0b00000000000000000010000000000111, 0b00000000000000000111000001111111, &this_class::__flw}, + /* instruction FSW, encoding '0b00000000000000000010000000100111' */ + {32, 0b00000000000000000010000000100111, 0b00000000000000000111000001111111, &this_class::__fsw}, + /* instruction FADD__S, encoding '0b00000000000000000000000001010011' */ + {32, 0b00000000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fadd__s}, + /* instruction FSUB__S, encoding '0b00001000000000000000000001010011' */ + {32, 0b00001000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fsub__s}, + /* instruction FMUL__S, encoding '0b00010000000000000000000001010011' */ + {32, 0b00010000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fmul__s}, + /* instruction FDIV__S, encoding '0b00011000000000000000000001010011' */ + {32, 0b00011000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fdiv__s}, + /* instruction FMIN__S, encoding '0b00101000000000000000000001010011' */ + {32, 0b00101000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fmin__s}, + /* instruction FMAX__S, encoding '0b00101000000000000001000001010011' */ + {32, 0b00101000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fmax__s}, + /* instruction FSQRT__S, encoding '0b01011000000000000000000001010011' */ + {32, 0b01011000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fsqrt__s}, + /* instruction FMADD__S, encoding '0b00000000000000000000000001000011' */ + {32, 0b00000000000000000000000001000011, 0b00000110000000000000000001111111, &this_class::__fmadd__s}, + /* instruction FMSUB__S, encoding '0b00000000000000000000000001000111' */ + {32, 0b00000000000000000000000001000111, 0b00000110000000000000000001111111, &this_class::__fmsub__s}, + /* instruction FNMADD__S, encoding '0b00000000000000000000000001001111' */ + {32, 0b00000000000000000000000001001111, 0b00000110000000000000000001111111, &this_class::__fnmadd__s}, + /* instruction FNMSUB__S, encoding '0b00000000000000000000000001001011' */ + {32, 0b00000000000000000000000001001011, 0b00000110000000000000000001111111, &this_class::__fnmsub__s}, + /* instruction FCVT__W__S, encoding '0b11000000000000000000000001010011' */ + {32, 0b11000000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__w__s}, + /* instruction FCVT__WU__S, encoding '0b11000000000100000000000001010011' */ + {32, 0b11000000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__wu__s}, + /* instruction FCVT__S__W, encoding '0b11010000000000000000000001010011' */ + {32, 0b11010000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__s__w}, + /* instruction FCVT__S__WU, encoding '0b11010000000100000000000001010011' */ + {32, 0b11010000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__s__wu}, + /* instruction FSGNJ__S, encoding '0b00100000000000000000000001010011' */ + {32, 0b00100000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnj__s}, + /* instruction FSGNJN__S, encoding '0b00100000000000000001000001010011' */ + {32, 0b00100000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjn__s}, + /* instruction FSGNJX__S, encoding '0b00100000000000000010000001010011' */ + {32, 0b00100000000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjx__s}, + /* instruction FMV__X__W, encoding '0b11100000000000000000000001010011' */ + {32, 0b11100000000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv__x__w}, + /* instruction FMV__W__X, encoding '0b11110000000000000000000001010011' */ + {32, 0b11110000000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv__w__x}, + /* instruction FEQ__S, encoding '0b10100000000000000010000001010011' */ + {32, 0b10100000000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__feq__s}, + /* instruction FLT__S, encoding '0b10100000000000000001000001010011' */ + {32, 0b10100000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__flt__s}, + /* instruction FLE__S, encoding '0b10100000000000000000000001010011' */ + {32, 0b10100000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fle__s}, + /* instruction FCLASS__S, encoding '0b11100000000000000001000001010011' */ + {32, 0b11100000000000000001000001010011, 0b11111111111100000111000001111111, &this_class::__fclass__s}, + /* instruction C__FLW, encoding '0b0110000000000000' */ + {16, 0b0110000000000000, 0b1110000000000011, &this_class::__c__flw}, + /* instruction C__FSW, encoding '0b1110000000000000' */ + {16, 0b1110000000000000, 0b1110000000000011, &this_class::__c__fsw}, + /* instruction C__FLWSP, encoding '0b0110000000000010' */ + {16, 0b0110000000000010, 0b1110000000000011, &this_class::__c__flwsp}, + /* instruction C__FSWSP, encoding '0b1110000000000010' */ + {16, 0b1110000000000010, 0b1110000000000011, &this_class::__c__fswsp}, + /* instruction FLD, encoding '0b00000000000000000011000000000111' */ + {32, 0b00000000000000000011000000000111, 0b00000000000000000111000001111111, &this_class::__fld}, + /* instruction FSD, encoding '0b00000000000000000011000000100111' */ + {32, 0b00000000000000000011000000100111, 0b00000000000000000111000001111111, &this_class::__fsd}, + /* instruction FADD__D, encoding '0b00000010000000000000000001010011' */ + {32, 0b00000010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fadd__d}, + /* instruction FSUB__D, encoding '0b00001010000000000000000001010011' */ + {32, 0b00001010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fsub__d}, + /* instruction FMUL__D, encoding '0b00010010000000000000000001010011' */ + {32, 0b00010010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fmul__d}, + /* instruction FDIV__D, encoding '0b00011010000000000000000001010011' */ + {32, 0b00011010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fdiv__d}, + /* instruction FMIN__D, encoding '0b00101010000000000000000001010011' */ + {32, 0b00101010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fmin__d}, + /* instruction FMAX__D, encoding '0b00101010000000000001000001010011' */ + {32, 0b00101010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fmax__d}, + /* instruction FSQRT__D, encoding '0b01011010000000000000000001010011' */ + {32, 0b01011010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fsqrt__d}, + /* instruction FMADD__D, encoding '0b00000010000000000000000001000011' */ + {32, 0b00000010000000000000000001000011, 0b00000110000000000000000001111111, &this_class::__fmadd__d}, + /* instruction FMSUB__D, encoding '0b00000010000000000000000001000111' */ + {32, 0b00000010000000000000000001000111, 0b00000110000000000000000001111111, &this_class::__fmsub__d}, + /* instruction FNMADD__D, encoding '0b00000010000000000000000001001111' */ + {32, 0b00000010000000000000000001001111, 0b00000110000000000000000001111111, &this_class::__fnmadd__d}, + /* instruction FNMSUB__D, encoding '0b00000010000000000000000001001011' */ + {32, 0b00000010000000000000000001001011, 0b00000110000000000000000001111111, &this_class::__fnmsub__d}, + /* instruction FCVT__W__D, encoding '0b11000010000000000000000001010011' */ + {32, 0b11000010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__w__d}, + /* instruction FCVT__WU__D, encoding '0b11000010000100000000000001010011' */ + {32, 0b11000010000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__wu__d}, + /* instruction FCVT__D__W, encoding '0b11010010000000000000000001010011' */ + {32, 0b11010010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__d__w}, + /* instruction FCVT__D__WU, encoding '0b11010010000100000000000001010011' */ + {32, 0b11010010000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__d__wu}, + /* instruction FCVT__S__D, encoding '0b01000000000100000000000001010011' */ + {32, 0b01000000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__s__d}, + /* instruction FCVT__D__S, encoding '0b01000010000000000000000001010011' */ + {32, 0b01000010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__d__s}, + /* instruction FSGNJ__D, encoding '0b00100010000000000000000001010011' */ + {32, 0b00100010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnj__d}, + /* instruction FSGNJN__D, encoding '0b00100010000000000001000001010011' */ + {32, 0b00100010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjn__d}, + /* instruction FSGNJX__D, encoding '0b00100010000000000010000001010011' */ + {32, 0b00100010000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjx__d}, + /* instruction FEQ__D, encoding '0b10100010000000000010000001010011' */ + {32, 0b10100010000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__feq__d}, + /* instruction FLT__D, encoding '0b10100010000000000001000001010011' */ + {32, 0b10100010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__flt__d}, + /* instruction FLE__D, encoding '0b10100010000000000000000001010011' */ + {32, 0b10100010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fle__d}, + /* instruction FCLASS__D, encoding '0b11100010000000000001000001010011' */ + {32, 0b11100010000000000001000001010011, 0b11111111111100000111000001111111, &this_class::__fclass__d}, + /* instruction C__FLD, encoding '0b0010000000000000' */ + {16, 0b0010000000000000, 0b1110000000000011, &this_class::__c__fld}, + /* instruction C__FSD, encoding '0b1010000000000000' */ + {16, 0b1010000000000000, 0b1110000000000011, &this_class::__c__fsd}, + /* instruction C__FLDSP, encoding '0b0010000000000010' */ + {16, 0b0010000000000010, 0b1110000000000011, &this_class::__c__fldsp}, + /* instruction C__FSDSP, encoding '0b1010000000000010' */ + {16, 0b1010000000000010, 0b1110000000000011, &this_class::__c__fsdsp}, + /* instruction SFENCE__VMA, encoding '0b00010010000000000000000001110011' */ + {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence__vma}, + /* instruction SRET, encoding '0b00010000001000000000000001110011' */ + {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, + /* instruction VSETVLI, encoding '0b00000000000000000111000001010111' */ + {32, 0b00000000000000000111000001010111, 0b11110000000000000111000001111111, &this_class::__vsetvli}, + /* instruction VSETIVLI, encoding '0b11000000000000000111000001010111' */ + {32, 0b11000000000000000111000001010111, 0b11110000000000000111000001111111, &this_class::__vsetivli}, + /* instruction VSETVL, encoding '0b10000000000000000111000001010111' */ + {32, 0b10000000000000000111000001010111, 0b11111110000000000111000001111111, &this_class::__vsetvl}, + /* instruction VLE8__V, encoding '0b00000000000000000000000000000111' */ + {32, 0b00000000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vle8__v}, + /* instruction VLE16__V, encoding '0b00000000000000000101000000000111' */ + {32, 0b00000000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vle16__v}, + /* instruction VLE32__V, encoding '0b00000000000000000110000000000111' */ + {32, 0b00000000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vle32__v}, + /* instruction VLE64__V, encoding '0b00000000000000000111000000000111' */ + {32, 0b00000000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vle64__v}, + /* instruction VLSEG2E8__V, encoding '0b00100000000000000000000000000111' */ + {32, 0b00100000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e8__v}, + /* instruction VLSEG2E16__V, encoding '0b00100000000000000101000000000111' */ + {32, 0b00100000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e16__v}, + /* instruction VLSEG2E32__V, encoding '0b00100000000000000110000000000111' */ + {32, 0b00100000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e32__v}, + /* instruction VLSEG2E64__V, encoding '0b00100000000000000111000000000111' */ + {32, 0b00100000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e64__v}, + /* instruction VLSEG3E8__V, encoding '0b01000000000000000000000000000111' */ + {32, 0b01000000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e8__v}, + /* instruction VLSEG3E16__V, encoding '0b01000000000000000101000000000111' */ + {32, 0b01000000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e16__v}, + /* instruction VLSEG3E32__V, encoding '0b01000000000000000110000000000111' */ + {32, 0b01000000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e32__v}, + /* instruction VLSEG3E64__V, encoding '0b01000000000000000111000000000111' */ + {32, 0b01000000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e64__v}, + /* instruction VLSEG4E8__V, encoding '0b01100000000000000000000000000111' */ + {32, 0b01100000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e8__v}, + /* instruction VLSEG4E16__V, encoding '0b01100000000000000101000000000111' */ + {32, 0b01100000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e16__v}, + /* instruction VLSEG4E32__V, encoding '0b01100000000000000110000000000111' */ + {32, 0b01100000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e32__v}, + /* instruction VLSEG4E64__V, encoding '0b01100000000000000111000000000111' */ + {32, 0b01100000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e64__v}, + /* instruction VLSEG5E8__V, encoding '0b10000000000000000000000000000111' */ + {32, 0b10000000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e8__v}, + /* instruction VLSEG5E16__V, encoding '0b10000000000000000101000000000111' */ + {32, 0b10000000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e16__v}, + /* instruction VLSEG5E32__V, encoding '0b10000000000000000110000000000111' */ + {32, 0b10000000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e32__v}, + /* instruction VLSEG5E64__V, encoding '0b10000000000000000111000000000111' */ + {32, 0b10000000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e64__v}, + /* instruction VLSEG6E8__V, encoding '0b10100000000000000000000000000111' */ + {32, 0b10100000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e8__v}, + /* instruction VLSEG6E16__V, encoding '0b10100000000000000101000000000111' */ + {32, 0b10100000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e16__v}, + /* instruction VLSEG6E32__V, encoding '0b10100000000000000110000000000111' */ + {32, 0b10100000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e32__v}, + /* instruction VLSEG6E64__V, encoding '0b10100000000000000111000000000111' */ + {32, 0b10100000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e64__v}, + /* instruction VLSEG7E8__V, encoding '0b11000000000000000000000000000111' */ + {32, 0b11000000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e8__v}, + /* instruction VLSEG7E16__V, encoding '0b11000000000000000101000000000111' */ + {32, 0b11000000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e16__v}, + /* instruction VLSEG7E32__V, encoding '0b11000000000000000110000000000111' */ + {32, 0b11000000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e32__v}, + /* instruction VLSEG7E64__V, encoding '0b11000000000000000111000000000111' */ + {32, 0b11000000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e64__v}, + /* instruction VLSEG8E8__V, encoding '0b11100000000000000000000000000111' */ + {32, 0b11100000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e8__v}, + /* instruction VLSEG8E16__V, encoding '0b11100000000000000101000000000111' */ + {32, 0b11100000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e16__v}, + /* instruction VLSEG8E32__V, encoding '0b11100000000000000110000000000111' */ + {32, 0b11100000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e32__v}, + /* instruction VLSEG8E64__V, encoding '0b11100000000000000111000000000111' */ + {32, 0b11100000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e64__v}, + /* instruction VSE8__V, encoding '0b00000000000000000000000000100111' */ + {32, 0b00000000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vse8__v}, + /* instruction VSE16__V, encoding '0b00000000000000000101000000100111' */ + {32, 0b00000000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vse16__v}, + /* instruction VSE32__V, encoding '0b00000000000000000110000000100111' */ + {32, 0b00000000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vse32__v}, + /* instruction VSE64__V, encoding '0b00000000000000000111000000100111' */ + {32, 0b00000000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vse64__v}, + /* instruction VSSEG2E8__V, encoding '0b00100000000000000000000000100111' */ + {32, 0b00100000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg2e8__v}, + /* instruction VSSEG2E16__V, encoding '0b00100000000000000101000000100111' */ + {32, 0b00100000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg2e16__v}, + /* instruction VSSEG2E32__V, encoding '0b00100000000000000110000000100111' */ + {32, 0b00100000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg2e32__v}, + /* instruction VSSEG2E64__V, encoding '0b00100000000000000111000000100111' */ + {32, 0b00100000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg2e64__v}, + /* instruction VSSEG3E8__V, encoding '0b01000000000000000000000000100111' */ + {32, 0b01000000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg3e8__v}, + /* instruction VSSEG3E16__V, encoding '0b01000000000000000101000000100111' */ + {32, 0b01000000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg3e16__v}, + /* instruction VSSEG3E32__V, encoding '0b01000000000000000110000000100111' */ + {32, 0b01000000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg3e32__v}, + /* instruction VSSEG3E64__V, encoding '0b01000000000000000111000000100111' */ + {32, 0b01000000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg3e64__v}, + /* instruction VSSEG4E8__V, encoding '0b01100000000000000000000000100111' */ + {32, 0b01100000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg4e8__v}, + /* instruction VSSEG4E16__V, encoding '0b01100000000000000101000000100111' */ + {32, 0b01100000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg4e16__v}, + /* instruction VSSEG4E32__V, encoding '0b01100000000000000110000000100111' */ + {32, 0b01100000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg4e32__v}, + /* instruction VSSEG4E64__V, encoding '0b01100000000000000111000000100111' */ + {32, 0b01100000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg4e64__v}, + /* instruction VSSEG5E8__V, encoding '0b10000000000000000000000000100111' */ + {32, 0b10000000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg5e8__v}, + /* instruction VSSEG5E16__V, encoding '0b10000000000000000101000000100111' */ + {32, 0b10000000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg5e16__v}, + /* instruction VSSEG5E32__V, encoding '0b10000000000000000110000000100111' */ + {32, 0b10000000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg5e32__v}, + /* instruction VSSEG5E64__V, encoding '0b10000000000000000111000000100111' */ + {32, 0b10000000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg5e64__v}, + /* instruction VSSEG6E8__V, encoding '0b10100000000000000000000000100111' */ + {32, 0b10100000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg6e8__v}, + /* instruction VSSEG6E16__V, encoding '0b10100000000000000101000000100111' */ + {32, 0b10100000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg6e16__v}, + /* instruction VSSEG6E32__V, encoding '0b10100000000000000110000000100111' */ + {32, 0b10100000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg6e32__v}, + /* instruction VSSEG6E64__V, encoding '0b10100000000000000111000000100111' */ + {32, 0b10100000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg6e64__v}, + /* instruction VSSEG7E8__V, encoding '0b11000000000000000000000000100111' */ + {32, 0b11000000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg7e8__v}, + /* instruction VSSEG7E16__V, encoding '0b11000000000000000101000000100111' */ + {32, 0b11000000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg7e16__v}, + /* instruction VSSEG7E32__V, encoding '0b11000000000000000110000000100111' */ + {32, 0b11000000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg7e32__v}, + /* instruction VSSEG7E64__V, encoding '0b11000000000000000111000000100111' */ + {32, 0b11000000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg7e64__v}, + /* instruction VSSEG8E8__V, encoding '0b11100000000000000000000000100111' */ + {32, 0b11100000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg8e8__v}, + /* instruction VSSEG8E16__V, encoding '0b11100000000000000101000000100111' */ + {32, 0b11100000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg8e16__v}, + /* instruction VSSEG8E32__V, encoding '0b11100000000000000110000000100111' */ + {32, 0b11100000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg8e32__v}, + /* instruction VSSEG8E64__V, encoding '0b11100000000000000111000000100111' */ + {32, 0b11100000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg8e64__v}, + /* instruction VLSE8__V, encoding '0b00001000000000000000000000000111' */ + {32, 0b00001000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlse8__v}, + /* instruction VLSE16__V, encoding '0b00001000000000000101000000000111' */ + {32, 0b00001000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlse16__v}, + /* instruction VLSE32__V, encoding '0b00001000000000000110000000000111' */ + {32, 0b00001000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlse32__v}, + /* instruction VLSE64__V, encoding '0b00001000000000000111000000000111' */ + {32, 0b00001000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlse64__v}, + /* instruction VLSSEG2E8__V, encoding '0b00101000000000000000000000000111' */ + {32, 0b00101000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg2e8__v}, + /* instruction VLSSEG2E16__V, encoding '0b00101000000000000101000000000111' */ + {32, 0b00101000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg2e16__v}, + /* instruction VLSSEG2E32__V, encoding '0b00101000000000000110000000000111' */ + {32, 0b00101000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg2e32__v}, + /* instruction VLSSEG2E64__V, encoding '0b00101000000000000111000000000111' */ + {32, 0b00101000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg2e64__v}, + /* instruction VLSSEG3E8__V, encoding '0b01001000000000000000000000000111' */ + {32, 0b01001000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg3e8__v}, + /* instruction VLSSEG3E16__V, encoding '0b01001000000000000101000000000111' */ + {32, 0b01001000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg3e16__v}, + /* instruction VLSSEG3E32__V, encoding '0b01001000000000000110000000000111' */ + {32, 0b01001000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg3e32__v}, + /* instruction VLSSEG3E64__V, encoding '0b01001000000000000111000000000111' */ + {32, 0b01001000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg3e64__v}, + /* instruction VLSSEG4E8__V, encoding '0b01101000000000000000000000000111' */ + {32, 0b01101000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg4e8__v}, + /* instruction VLSSEG4E16__V, encoding '0b01101000000000000101000000000111' */ + {32, 0b01101000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg4e16__v}, + /* instruction VLSSEG4E32__V, encoding '0b01101000000000000110000000000111' */ + {32, 0b01101000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg4e32__v}, + /* instruction VLSSEG4E64__V, encoding '0b01101000000000000111000000000111' */ + {32, 0b01101000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg4e64__v}, + /* instruction VLSSEG5E8__V, encoding '0b10001000000000000000000000000111' */ + {32, 0b10001000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg5e8__v}, + /* instruction VLSSEG5E16__V, encoding '0b10001000000000000101000000000111' */ + {32, 0b10001000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg5e16__v}, + /* instruction VLSSEG5E32__V, encoding '0b10001000000000000110000000000111' */ + {32, 0b10001000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg5e32__v}, + /* instruction VLSSEG5E64__V, encoding '0b10001000000000000111000000000111' */ + {32, 0b10001000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg5e64__v}, + /* instruction VLSSEG6E8__V, encoding '0b10101000000000000000000000000111' */ + {32, 0b10101000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg6e8__v}, + /* instruction VLSSEG6E16__V, encoding '0b10101000000000000101000000000111' */ + {32, 0b10101000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg6e16__v}, + /* instruction VLSSEG6E32__V, encoding '0b10101000000000000110000000000111' */ + {32, 0b10101000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg6e32__v}, + /* instruction VLSSEG6E64__V, encoding '0b10101000000000000111000000000111' */ + {32, 0b10101000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg6e64__v}, + /* instruction VLSSEG7E8__V, encoding '0b11001000000000000000000000000111' */ + {32, 0b11001000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg7e8__v}, + /* instruction VLSSEG7E16__V, encoding '0b11001000000000000101000000000111' */ + {32, 0b11001000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg7e16__v}, + /* instruction VLSSEG7E32__V, encoding '0b11001000000000000110000000000111' */ + {32, 0b11001000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg7e32__v}, + /* instruction VLSSEG7E64__V, encoding '0b11001000000000000111000000000111' */ + {32, 0b11001000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg7e64__v}, + /* instruction VLSSEG8E8__V, encoding '0b11101000000000000000000000000111' */ + {32, 0b11101000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg8e8__v}, + /* instruction VLSSEG8E16__V, encoding '0b11101000000000000101000000000111' */ + {32, 0b11101000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg8e16__v}, + /* instruction VLSSEG8E32__V, encoding '0b11101000000000000110000000000111' */ + {32, 0b11101000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg8e32__v}, + /* instruction VLSSEG8E64__V, encoding '0b11101000000000000111000000000111' */ + {32, 0b11101000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg8e64__v}, + /* instruction VSSE8__V, encoding '0b00001000000000000000000000100111' */ + {32, 0b00001000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsse8__v}, + /* instruction VSSE16__V, encoding '0b00001000000000000101000000100111' */ + {32, 0b00001000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsse16__v}, + /* instruction VSSE32__V, encoding '0b00001000000000000110000000100111' */ + {32, 0b00001000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsse32__v}, + /* instruction VSSE64__V, encoding '0b00001000000000000111000000100111' */ + {32, 0b00001000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsse64__v}, + /* instruction VSSSEG2E8__V, encoding '0b00101000000000000000000000100111' */ + {32, 0b00101000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg2e8__v}, + /* instruction VSSSEG2E16__V, encoding '0b00101000000000000101000000100111' */ + {32, 0b00101000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg2e16__v}, + /* instruction VSSSEG2E32__V, encoding '0b00101000000000000110000000100111' */ + {32, 0b00101000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg2e32__v}, + /* instruction VSSSEG2E64__V, encoding '0b00101000000000000111000000100111' */ + {32, 0b00101000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg2e64__v}, + /* instruction VSSSEG3E8__V, encoding '0b01001000000000000000000000100111' */ + {32, 0b01001000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg3e8__v}, + /* instruction VSSSEG3E16__V, encoding '0b01001000000000000101000000100111' */ + {32, 0b01001000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg3e16__v}, + /* instruction VSSSEG3E32__V, encoding '0b01001000000000000110000000100111' */ + {32, 0b01001000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg3e32__v}, + /* instruction VSSSEG3E64__V, encoding '0b01001000000000000111000000100111' */ + {32, 0b01001000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg3e64__v}, + /* instruction VSSSEG4E8__V, encoding '0b01101000000000000000000000100111' */ + {32, 0b01101000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg4e8__v}, + /* instruction VSSSEG4E16__V, encoding '0b01101000000000000101000000100111' */ + {32, 0b01101000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg4e16__v}, + /* instruction VSSSEG4E32__V, encoding '0b01101000000000000110000000100111' */ + {32, 0b01101000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg4e32__v}, + /* instruction VSSSEG4E64__V, encoding '0b01101000000000000111000000100111' */ + {32, 0b01101000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg4e64__v}, + /* instruction VSSSEG5E8__V, encoding '0b10001000000000000000000000100111' */ + {32, 0b10001000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg5e8__v}, + /* instruction VSSSEG5E16__V, encoding '0b10001000000000000101000000100111' */ + {32, 0b10001000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg5e16__v}, + /* instruction VSSSEG5E32__V, encoding '0b10001000000000000110000000100111' */ + {32, 0b10001000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg5e32__v}, + /* instruction VSSSEG5E64__V, encoding '0b10001000000000000111000000100111' */ + {32, 0b10001000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg5e64__v}, + /* instruction VSSSEG6E8__V, encoding '0b10101000000000000000000000100111' */ + {32, 0b10101000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg6e8__v}, + /* instruction VSSSEG6E16__V, encoding '0b10101000000000000101000000100111' */ + {32, 0b10101000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg6e16__v}, + /* instruction VSSSEG6E32__V, encoding '0b10101000000000000110000000100111' */ + {32, 0b10101000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg6e32__v}, + /* instruction VSSSEG6E64__V, encoding '0b10101000000000000111000000100111' */ + {32, 0b10101000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg6e64__v}, + /* instruction VSSSEG7E8__V, encoding '0b11001000000000000000000000100111' */ + {32, 0b11001000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg7e8__v}, + /* instruction VSSSEG7E16__V, encoding '0b11001000000000000101000000100111' */ + {32, 0b11001000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg7e16__v}, + /* instruction VSSSEG7E32__V, encoding '0b11001000000000000110000000100111' */ + {32, 0b11001000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg7e32__v}, + /* instruction VSSSEG7E64__V, encoding '0b11001000000000000111000000100111' */ + {32, 0b11001000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg7e64__v}, + /* instruction VSSSEG8E8__V, encoding '0b11101000000000000000000000100111' */ + {32, 0b11101000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg8e8__v}, + /* instruction VSSSEG8E16__V, encoding '0b11101000000000000101000000100111' */ + {32, 0b11101000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg8e16__v}, + /* instruction VSSSEG8E32__V, encoding '0b11101000000000000110000000100111' */ + {32, 0b11101000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg8e32__v}, + /* instruction VSSSEG8E64__V, encoding '0b11101000000000000111000000100111' */ + {32, 0b11101000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg8e64__v}, + /* instruction VLE8FF__V, encoding '0b00000001000000000000000000000111' */ + {32, 0b00000001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vle8ff__v}, + /* instruction VLE16FF__V, encoding '0b00000001000000000101000000000111' */ + {32, 0b00000001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vle16ff__v}, + /* instruction VLE32FF__V, encoding '0b00000001000000000110000000000111' */ + {32, 0b00000001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vle32ff__v}, + /* instruction VLE64FF__V, encoding '0b00000001000000000111000000000111' */ + {32, 0b00000001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vle64ff__v}, + /* instruction VLSEG2E8FF__V, encoding '0b00100001000000000000000000000111' */ + {32, 0b00100001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e8ff__v}, + /* instruction VLSEG2E16FF__V, encoding '0b00100001000000000101000000000111' */ + {32, 0b00100001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e16ff__v}, + /* instruction VLSEG2E32FF__V, encoding '0b00100001000000000110000000000111' */ + {32, 0b00100001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e32ff__v}, + /* instruction VLSEG2E64FF__V, encoding '0b00100001000000000111000000000111' */ + {32, 0b00100001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e64ff__v}, + /* instruction VLSEG3E8FF__V, encoding '0b01000001000000000000000000000111' */ + {32, 0b01000001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e8ff__v}, + /* instruction VLSEG3E16FF__V, encoding '0b01000001000000000101000000000111' */ + {32, 0b01000001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e16ff__v}, + /* instruction VLSEG3E32FF__V, encoding '0b01000001000000000110000000000111' */ + {32, 0b01000001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e32ff__v}, + /* instruction VLSEG3E64FF__V, encoding '0b01000001000000000111000000000111' */ + {32, 0b01000001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e64ff__v}, + /* instruction VLSEG4E8FF__V, encoding '0b01100001000000000000000000000111' */ + {32, 0b01100001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e8ff__v}, + /* instruction VLSEG4E16FF__V, encoding '0b01100001000000000101000000000111' */ + {32, 0b01100001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e16ff__v}, + /* instruction VLSEG4E32FF__V, encoding '0b01100001000000000110000000000111' */ + {32, 0b01100001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e32ff__v}, + /* instruction VLSEG4E64FF__V, encoding '0b01100001000000000111000000000111' */ + {32, 0b01100001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e64ff__v}, + /* instruction VLSEG5E8FF__V, encoding '0b10000001000000000000000000000111' */ + {32, 0b10000001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e8ff__v}, + /* instruction VLSEG5E16FF__V, encoding '0b10000001000000000101000000000111' */ + {32, 0b10000001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e16ff__v}, + /* instruction VLSEG5E32FF__V, encoding '0b10000001000000000110000000000111' */ + {32, 0b10000001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e32ff__v}, + /* instruction VLSEG5E64FF__V, encoding '0b10000001000000000111000000000111' */ + {32, 0b10000001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e64ff__v}, + /* instruction VLSEG6E8FF__V, encoding '0b10100001000000000000000000000111' */ + {32, 0b10100001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e8ff__v}, + /* instruction VLSEG6E16FF__V, encoding '0b10100001000000000101000000000111' */ + {32, 0b10100001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e16ff__v}, + /* instruction VLSEG6E32FF__V, encoding '0b10100001000000000110000000000111' */ + {32, 0b10100001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e32ff__v}, + /* instruction VLSEG6E64FF__V, encoding '0b10100001000000000111000000000111' */ + {32, 0b10100001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e64ff__v}, + /* instruction VLSEG7E8FF__V, encoding '0b11000001000000000000000000000111' */ + {32, 0b11000001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e8ff__v}, + /* instruction VLSEG7E16FF__V, encoding '0b11000001000000000101000000000111' */ + {32, 0b11000001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e16ff__v}, + /* instruction VLSEG7E32FF__V, encoding '0b11000001000000000110000000000111' */ + {32, 0b11000001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e32ff__v}, + /* instruction VLSEG7E64FF__V, encoding '0b11000001000000000111000000000111' */ + {32, 0b11000001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e64ff__v}, + /* instruction VLSEG8E8FF__V, encoding '0b11100001000000000000000000000111' */ + {32, 0b11100001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e8ff__v}, + /* instruction VLSEG8E16FF__V, encoding '0b11100001000000000101000000000111' */ + {32, 0b11100001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e16ff__v}, + /* instruction VLSEG8E32FF__V, encoding '0b11100001000000000110000000000111' */ + {32, 0b11100001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e32ff__v}, + /* instruction VLSEG8E64FF__V, encoding '0b11100001000000000111000000000111' */ + {32, 0b11100001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e64ff__v}, + /* instruction VSM__V, encoding '0b00000010101100000000000000100111' */ + {32, 0b00000010101100000000000000100111, 0b11111111111100000111000001111111, &this_class::__vsm__v}, + /* instruction VLM__V, encoding '0b00000010101100000000000000000111' */ + {32, 0b00000010101100000000000000000111, 0b11111111111100000111000001111111, &this_class::__vlm__v}, + /* instruction VL1RE8__V, encoding '0b00000010100000000000000000000111' */ + {32, 0b00000010100000000000000000000111, 0b11101111111100000111000001111111, &this_class::__vl1re8__v}, + /* instruction VL1RE16__V, encoding '0b00000010100000000101000000000111' */ + {32, 0b00000010100000000101000000000111, 0b11101111111100000111000001111111, &this_class::__vl1re16__v}, + /* instruction VL1RE32__V, encoding '0b00000010100000000110000000000111' */ + {32, 0b00000010100000000110000000000111, 0b11101111111100000111000001111111, &this_class::__vl1re32__v}, + /* instruction VL1RE64__V, encoding '0b00000010100000000111000000000111' */ + {32, 0b00000010100000000111000000000111, 0b11101111111100000111000001111111, &this_class::__vl1re64__v}, + /* instruction VL2RE8__V, encoding '0b00100010100000000000000000000111' */ + {32, 0b00100010100000000000000000000111, 0b11101111111100000111000001111111, &this_class::__vl2re8__v}, + /* instruction VL2RE16__V, encoding '0b00100010100000000101000000000111' */ + {32, 0b00100010100000000101000000000111, 0b11101111111100000111000001111111, &this_class::__vl2re16__v}, + /* instruction VL2RE32__V, encoding '0b00100010100000000110000000000111' */ + {32, 0b00100010100000000110000000000111, 0b11101111111100000111000001111111, &this_class::__vl2re32__v}, + /* instruction VL2RE64__V, encoding '0b00100010100000000111000000000111' */ + {32, 0b00100010100000000111000000000111, 0b11101111111100000111000001111111, &this_class::__vl2re64__v}, + /* instruction VL4RE8__V, encoding '0b01100010100000000000000000000111' */ + {32, 0b01100010100000000000000000000111, 0b11101111111100000111000001111111, &this_class::__vl4re8__v}, + /* instruction VL4RE16__V, encoding '0b01100010100000000101000000000111' */ + {32, 0b01100010100000000101000000000111, 0b11101111111100000111000001111111, &this_class::__vl4re16__v}, + /* instruction VL4RE32__V, encoding '0b01100010100000000110000000000111' */ + {32, 0b01100010100000000110000000000111, 0b11101111111100000111000001111111, &this_class::__vl4re32__v}, + /* instruction VL4RE64__V, encoding '0b01100010100000000111000000000111' */ + {32, 0b01100010100000000111000000000111, 0b11101111111100000111000001111111, &this_class::__vl4re64__v}, + /* instruction VL8RE8__V, encoding '0b11100010100000000000000000000111' */ + {32, 0b11100010100000000000000000000111, 0b11101111111100000111000001111111, &this_class::__vl8re8__v}, + /* instruction VL8RE16__V, encoding '0b11100010100000000101000000000111' */ + {32, 0b11100010100000000101000000000111, 0b11101111111100000111000001111111, &this_class::__vl8re16__v}, + /* instruction VL8RE32__V, encoding '0b11100010100000000110000000000111' */ + {32, 0b11100010100000000110000000000111, 0b11101111111100000111000001111111, &this_class::__vl8re32__v}, + /* instruction VL8RE64__V, encoding '0b11100010100000000111000000000111' */ + {32, 0b11100010100000000111000000000111, 0b11101111111100000111000001111111, &this_class::__vl8re64__v}, + /* instruction VS1RE64__V, encoding '0b00000010100000000000000000100111' */ + {32, 0b00000010100000000000000000100111, 0b11111111111100000111000001111111, &this_class::__vs1re64__v}, + /* instruction VS2RE64__V, encoding '0b00100010100000000000000000100111' */ + {32, 0b00100010100000000000000000100111, 0b11111111111100000111000001111111, &this_class::__vs2re64__v}, + /* instruction VS4RE64__V, encoding '0b01100010100000000000000000100111' */ + {32, 0b01100010100000000000000000100111, 0b11111111111100000111000001111111, &this_class::__vs4re64__v}, + /* instruction VS8RE64__V, encoding '0b11100010100000000000000000100111' */ + {32, 0b11100010100000000000000000100111, 0b11111111111100000111000001111111, &this_class::__vs8re64__v}, + /* instruction VLOXEI8__V, encoding '0b00001100000000000000000000000111' */ + {32, 0b00001100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxei8__v}, + /* instruction VLOXEI16__V, encoding '0b00001100000000000101000000000111' */ + {32, 0b00001100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxei16__v}, + /* instruction VLOXEI32__V, encoding '0b00001100000000000110000000000111' */ + {32, 0b00001100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxei32__v}, + /* instruction VLOXEI64__V, encoding '0b00001100000000000111000000000111' */ + {32, 0b00001100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxei64__v}, + /* instruction VLOXSEG2EI8__V, encoding '0b00101100000000000000000000000111' */ + {32, 0b00101100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg2ei8__v}, + /* instruction VLOXSEG2EI16__V, encoding '0b00101100000000000101000000000111' */ + {32, 0b00101100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg2ei16__v}, + /* instruction VLOXSEG2EI32__V, encoding '0b00101100000000000110000000000111' */ + {32, 0b00101100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg2ei32__v}, + /* instruction VLOXSEG2EI64__V, encoding '0b00101100000000000111000000000111' */ + {32, 0b00101100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg2ei64__v}, + /* instruction VLOXSEG3EI8__V, encoding '0b01001100000000000000000000000111' */ + {32, 0b01001100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg3ei8__v}, + /* instruction VLOXSEG3EI16__V, encoding '0b01001100000000000101000000000111' */ + {32, 0b01001100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg3ei16__v}, + /* instruction VLOXSEG3EI32__V, encoding '0b01001100000000000110000000000111' */ + {32, 0b01001100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg3ei32__v}, + /* instruction VLOXSEG3EI64__V, encoding '0b01001100000000000111000000000111' */ + {32, 0b01001100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg3ei64__v}, + /* instruction VLOXSEG4EI8__V, encoding '0b01101100000000000000000000000111' */ + {32, 0b01101100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg4ei8__v}, + /* instruction VLOXSEG4EI16__V, encoding '0b01101100000000000101000000000111' */ + {32, 0b01101100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg4ei16__v}, + /* instruction VLOXSEG4EI32__V, encoding '0b01101100000000000110000000000111' */ + {32, 0b01101100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg4ei32__v}, + /* instruction VLOXSEG4EI64__V, encoding '0b01101100000000000111000000000111' */ + {32, 0b01101100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg4ei64__v}, + /* instruction VLOXSEG5EI8__V, encoding '0b10001100000000000000000000000111' */ + {32, 0b10001100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg5ei8__v}, + /* instruction VLOXSEG5EI16__V, encoding '0b10001100000000000101000000000111' */ + {32, 0b10001100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg5ei16__v}, + /* instruction VLOXSEG5EI32__V, encoding '0b10001100000000000110000000000111' */ + {32, 0b10001100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg5ei32__v}, + /* instruction VLOXSEG5EI64__V, encoding '0b10001100000000000111000000000111' */ + {32, 0b10001100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg5ei64__v}, + /* instruction VLOXSEG6EI8__V, encoding '0b10101100000000000000000000000111' */ + {32, 0b10101100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg6ei8__v}, + /* instruction VLOXSEG6EI16__V, encoding '0b10101100000000000101000000000111' */ + {32, 0b10101100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg6ei16__v}, + /* instruction VLOXSEG6EI32__V, encoding '0b10101100000000000110000000000111' */ + {32, 0b10101100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg6ei32__v}, + /* instruction VLOXSEG6EI64__V, encoding '0b10101100000000000111000000000111' */ + {32, 0b10101100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg6ei64__v}, + /* instruction VLOXSEG7EI8__V, encoding '0b11001100000000000000000000000111' */ + {32, 0b11001100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg7ei8__v}, + /* instruction VLOXSEG7EI16__V, encoding '0b11001100000000000101000000000111' */ + {32, 0b11001100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg7ei16__v}, + /* instruction VLOXSEG7EI32__V, encoding '0b11001100000000000110000000000111' */ + {32, 0b11001100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg7ei32__v}, + /* instruction VLOXSEG7EI64__V, encoding '0b11001100000000000111000000000111' */ + {32, 0b11001100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg7ei64__v}, + /* instruction VLOXSEG8EI8__V, encoding '0b11101100000000000000000000000111' */ + {32, 0b11101100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg8ei8__v}, + /* instruction VLOXSEG8EI16__V, encoding '0b11101100000000000101000000000111' */ + {32, 0b11101100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg8ei16__v}, + /* instruction VLOXSEG8EI32__V, encoding '0b11101100000000000110000000000111' */ + {32, 0b11101100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg8ei32__v}, + /* instruction VLOXSEG8EI64__V, encoding '0b11101100000000000111000000000111' */ + {32, 0b11101100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg8ei64__v}, + /* instruction VSOXEI8__V, encoding '0b00001100000000000000000000100111' */ + {32, 0b00001100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxei8__v}, + /* instruction VSOXEI16__V, encoding '0b00001100000000000101000000100111' */ + {32, 0b00001100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxei16__v}, + /* instruction VSOXEI32__V, encoding '0b00001100000000000110000000100111' */ + {32, 0b00001100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxei32__v}, + /* instruction VSOXEI64__V, encoding '0b00001100000000000111000000100111' */ + {32, 0b00001100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxei64__v}, + /* instruction VSOXSEG2EI8__V, encoding '0b00101100000000000000000000100111' */ + {32, 0b00101100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg2ei8__v}, + /* instruction VSOXSEG2EI16__V, encoding '0b00101100000000000101000000100111' */ + {32, 0b00101100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg2ei16__v}, + /* instruction VSOXSEG2EI32__V, encoding '0b00101100000000000110000000100111' */ + {32, 0b00101100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg2ei32__v}, + /* instruction VSOXSEG2EI64__V, encoding '0b00101100000000000111000000100111' */ + {32, 0b00101100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg2ei64__v}, + /* instruction VSOXSEG3EI8__V, encoding '0b01001100000000000000000000100111' */ + {32, 0b01001100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg3ei8__v}, + /* instruction VSOXSEG3EI16__V, encoding '0b01001100000000000101000000100111' */ + {32, 0b01001100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg3ei16__v}, + /* instruction VSOXSEG3EI32__V, encoding '0b01001100000000000110000000100111' */ + {32, 0b01001100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg3ei32__v}, + /* instruction VSOXSEG3EI64__V, encoding '0b01001100000000000111000000100111' */ + {32, 0b01001100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg3ei64__v}, + /* instruction VSOXSEG4EI8__V, encoding '0b01101100000000000000000000100111' */ + {32, 0b01101100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg4ei8__v}, + /* instruction VSOXSEG4EI16__V, encoding '0b01101100000000000101000000100111' */ + {32, 0b01101100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg4ei16__v}, + /* instruction VSOXSEG4EI32__V, encoding '0b01101100000000000110000000100111' */ + {32, 0b01101100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg4ei32__v}, + /* instruction VSOXSEG4EI64__V, encoding '0b01101100000000000111000000100111' */ + {32, 0b01101100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg4ei64__v}, + /* instruction VSOXSEG5EI8__V, encoding '0b10001100000000000000000000100111' */ + {32, 0b10001100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg5ei8__v}, + /* instruction VSOXSEG5EI16__V, encoding '0b10001100000000000101000000100111' */ + {32, 0b10001100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg5ei16__v}, + /* instruction VSOXSEG5EI32__V, encoding '0b10001100000000000110000000100111' */ + {32, 0b10001100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg5ei32__v}, + /* instruction VSOXSEG5EI64__V, encoding '0b10001100000000000111000000100111' */ + {32, 0b10001100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg5ei64__v}, + /* instruction VSOXSEG6EI8__V, encoding '0b10101100000000000000000000100111' */ + {32, 0b10101100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg6ei8__v}, + /* instruction VSOXSEG6EI16__V, encoding '0b10101100000000000101000000100111' */ + {32, 0b10101100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg6ei16__v}, + /* instruction VSOXSEG6EI32__V, encoding '0b10101100000000000110000000100111' */ + {32, 0b10101100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg6ei32__v}, + /* instruction VSOXSEG6EI64__V, encoding '0b10101100000000000111000000100111' */ + {32, 0b10101100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg6ei64__v}, + /* instruction VSOXSEG7EI8__V, encoding '0b11001100000000000000000000100111' */ + {32, 0b11001100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg7ei8__v}, + /* instruction VSOXSEG7EI16__V, encoding '0b11001100000000000101000000100111' */ + {32, 0b11001100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg7ei16__v}, + /* instruction VSOXSEG7EI32__V, encoding '0b11001100000000000110000000100111' */ + {32, 0b11001100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg7ei32__v}, + /* instruction VSOXSEG7EI64__V, encoding '0b11001100000000000111000000100111' */ + {32, 0b11001100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg7ei64__v}, + /* instruction VSOXSEG8EI8__V, encoding '0b11101100000000000000000000100111' */ + {32, 0b11101100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg8ei8__v}, + /* instruction VSOXSEG8EI16__V, encoding '0b11101100000000000101000000100111' */ + {32, 0b11101100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg8ei16__v}, + /* instruction VSOXSEG8EI32__V, encoding '0b11101100000000000110000000100111' */ + {32, 0b11101100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg8ei32__v}, + /* instruction VSOXSEG8EI64__V, encoding '0b11101100000000000111000000100111' */ + {32, 0b11101100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg8ei64__v}, + /* instruction VLUXEI8__V, encoding '0b00000100000000000000000000000111' */ + {32, 0b00000100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxei8__v}, + /* instruction VLUXEI16__V, encoding '0b00000100000000000101000000000111' */ + {32, 0b00000100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxei16__v}, + /* instruction VLUXEI32__V, encoding '0b00000100000000000110000000000111' */ + {32, 0b00000100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxei32__v}, + /* instruction VLUXEI64__V, encoding '0b00000100000000000111000000000111' */ + {32, 0b00000100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxei64__v}, + /* instruction VLUXSEG2EI8__V, encoding '0b00100100000000000000000000000111' */ + {32, 0b00100100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg2ei8__v}, + /* instruction VLUXSEG2EI16__V, encoding '0b00100100000000000101000000000111' */ + {32, 0b00100100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg2ei16__v}, + /* instruction VLUXSEG2EI32__V, encoding '0b00100100000000000110000000000111' */ + {32, 0b00100100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg2ei32__v}, + /* instruction VLUXSEG2EI64__V, encoding '0b00100100000000000111000000000111' */ + {32, 0b00100100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg2ei64__v}, + /* instruction VLUXSEG3EI8__V, encoding '0b01000100000000000000000000000111' */ + {32, 0b01000100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg3ei8__v}, + /* instruction VLUXSEG3EI16__V, encoding '0b01000100000000000101000000000111' */ + {32, 0b01000100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg3ei16__v}, + /* instruction VLUXSEG3EI32__V, encoding '0b01000100000000000110000000000111' */ + {32, 0b01000100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg3ei32__v}, + /* instruction VLUXSEG3EI64__V, encoding '0b01000100000000000111000000000111' */ + {32, 0b01000100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg3ei64__v}, + /* instruction VLUXSEG4EI8__V, encoding '0b01100100000000000000000000000111' */ + {32, 0b01100100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg4ei8__v}, + /* instruction VLUXSEG4EI16__V, encoding '0b01100100000000000101000000000111' */ + {32, 0b01100100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg4ei16__v}, + /* instruction VLUXSEG4EI32__V, encoding '0b01100100000000000110000000000111' */ + {32, 0b01100100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg4ei32__v}, + /* instruction VLUXSEG4EI64__V, encoding '0b01100100000000000111000000000111' */ + {32, 0b01100100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg4ei64__v}, + /* instruction VLUXSEG5EI8__V, encoding '0b10000100000000000000000000000111' */ + {32, 0b10000100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg5ei8__v}, + /* instruction VLUXSEG5EI16__V, encoding '0b10000100000000000101000000000111' */ + {32, 0b10000100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg5ei16__v}, + /* instruction VLUXSEG5EI32__V, encoding '0b10000100000000000110000000000111' */ + {32, 0b10000100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg5ei32__v}, + /* instruction VLUXSEG5EI64__V, encoding '0b10000100000000000111000000000111' */ + {32, 0b10000100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg5ei64__v}, + /* instruction VLUXSEG6EI8__V, encoding '0b10100100000000000000000000000111' */ + {32, 0b10100100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg6ei8__v}, + /* instruction VLUXSEG6EI16__V, encoding '0b10100100000000000101000000000111' */ + {32, 0b10100100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg6ei16__v}, + /* instruction VLUXSEG6EI32__V, encoding '0b10100100000000000110000000000111' */ + {32, 0b10100100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg6ei32__v}, + /* instruction VLUXSEG6EI64__V, encoding '0b10100100000000000111000000000111' */ + {32, 0b10100100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg6ei64__v}, + /* instruction VLUXSEG7EI8__V, encoding '0b11000100000000000000000000000111' */ + {32, 0b11000100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg7ei8__v}, + /* instruction VLUXSEG7EI16__V, encoding '0b11000100000000000101000000000111' */ + {32, 0b11000100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg7ei16__v}, + /* instruction VLUXSEG7EI32__V, encoding '0b11000100000000000110000000000111' */ + {32, 0b11000100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg7ei32__v}, + /* instruction VLUXSEG7EI64__V, encoding '0b11000100000000000111000000000111' */ + {32, 0b11000100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg7ei64__v}, + /* instruction VLUXSEG8EI8__V, encoding '0b11100100000000000000000000000111' */ + {32, 0b11100100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg8ei8__v}, + /* instruction VLUXSEG8EI16__V, encoding '0b11100100000000000101000000000111' */ + {32, 0b11100100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg8ei16__v}, + /* instruction VLUXSEG8EI32__V, encoding '0b11100100000000000110000000000111' */ + {32, 0b11100100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg8ei32__v}, + /* instruction VLUXSEG8EI64__V, encoding '0b11100100000000000111000000000111' */ + {32, 0b11100100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg8ei64__v}, + /* instruction VSUXEI8__V, encoding '0b00000100000000000000000000100111' */ + {32, 0b00000100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxei8__v}, + /* instruction VSUXEI16__V, encoding '0b00000100000000000101000000100111' */ + {32, 0b00000100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxei16__v}, + /* instruction VSUXEI32__V, encoding '0b00000100000000000110000000100111' */ + {32, 0b00000100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxei32__v}, + /* instruction VSUXEI64__V, encoding '0b00000100000000000111000000100111' */ + {32, 0b00000100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxei64__v}, + /* instruction VSUXSEG2EI8__V, encoding '0b00100100000000000000000000100111' */ + {32, 0b00100100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg2ei8__v}, + /* instruction VSUXSEG2EI16__V, encoding '0b00100100000000000101000000100111' */ + {32, 0b00100100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg2ei16__v}, + /* instruction VSUXSEG2EI32__V, encoding '0b00100100000000000110000000100111' */ + {32, 0b00100100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg2ei32__v}, + /* instruction VSUXSEG2EI64__V, encoding '0b00100100000000000111000000100111' */ + {32, 0b00100100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg2ei64__v}, + /* instruction VSUXSEG3EI8__V, encoding '0b01000100000000000000000000100111' */ + {32, 0b01000100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg3ei8__v}, + /* instruction VSUXSEG3EI16__V, encoding '0b01000100000000000101000000100111' */ + {32, 0b01000100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg3ei16__v}, + /* instruction VSUXSEG3EI32__V, encoding '0b01000100000000000110000000100111' */ + {32, 0b01000100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg3ei32__v}, + /* instruction VSUXSEG3EI64__V, encoding '0b01000100000000000111000000100111' */ + {32, 0b01000100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg3ei64__v}, + /* instruction VSUXSEG4EI8__V, encoding '0b01100100000000000000000000100111' */ + {32, 0b01100100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg4ei8__v}, + /* instruction VSUXSEG4EI16__V, encoding '0b01100100000000000101000000100111' */ + {32, 0b01100100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg4ei16__v}, + /* instruction VSUXSEG4EI32__V, encoding '0b01100100000000000110000000100111' */ + {32, 0b01100100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg4ei32__v}, + /* instruction VSUXSEG4EI64__V, encoding '0b01100100000000000111000000100111' */ + {32, 0b01100100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg4ei64__v}, + /* instruction VSUXSEG5EI8__V, encoding '0b10000100000000000000000000100111' */ + {32, 0b10000100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg5ei8__v}, + /* instruction VSUXSEG5EI16__V, encoding '0b10000100000000000101000000100111' */ + {32, 0b10000100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg5ei16__v}, + /* instruction VSUXSEG5EI32__V, encoding '0b10000100000000000110000000100111' */ + {32, 0b10000100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg5ei32__v}, + /* instruction VSUXSEG5EI64__V, encoding '0b10000100000000000111000000100111' */ + {32, 0b10000100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg5ei64__v}, + /* instruction VSUXSEG6EI8__V, encoding '0b10100100000000000000000000100111' */ + {32, 0b10100100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg6ei8__v}, + /* instruction VSUXSEG6EI16__V, encoding '0b10100100000000000101000000100111' */ + {32, 0b10100100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg6ei16__v}, + /* instruction VSUXSEG6EI32__V, encoding '0b10100100000000000110000000100111' */ + {32, 0b10100100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg6ei32__v}, + /* instruction VSUXSEG6EI64__V, encoding '0b10100100000000000111000000100111' */ + {32, 0b10100100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg6ei64__v}, + /* instruction VSUXSEG7EI8__V, encoding '0b11000100000000000000000000100111' */ + {32, 0b11000100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg7ei8__v}, + /* instruction VSUXSEG7EI16__V, encoding '0b11000100000000000101000000100111' */ + {32, 0b11000100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg7ei16__v}, + /* instruction VSUXSEG7EI32__V, encoding '0b11000100000000000110000000100111' */ + {32, 0b11000100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg7ei32__v}, + /* instruction VSUXSEG7EI64__V, encoding '0b11000100000000000111000000100111' */ + {32, 0b11000100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg7ei64__v}, + /* instruction VSUXSEG8EI8__V, encoding '0b11100100000000000000000000100111' */ + {32, 0b11100100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg8ei8__v}, + /* instruction VSUXSEG8EI16__V, encoding '0b11100100000000000101000000100111' */ + {32, 0b11100100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg8ei16__v}, + /* instruction VSUXSEG8EI32__V, encoding '0b11100100000000000110000000100111' */ + {32, 0b11100100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg8ei32__v}, + /* instruction VSUXSEG8EI64__V, encoding '0b11100100000000000111000000100111' */ + {32, 0b11100100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg8ei64__v}, + /* instruction VADD__VI, encoding '0b00000000000000000011000001010111' */ + {32, 0b00000000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vadd__vi}, + /* instruction VADD__VV, encoding '0b00000000000000000000000001010111' */ + {32, 0b00000000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vadd__vv}, + /* instruction VADD__VX, encoding '0b00000000000000000100000001010111' */ + {32, 0b00000000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vadd__vx}, + /* instruction VSUB__VV, encoding '0b00001000000000000000000001010111' */ + {32, 0b00001000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsub__vv}, + /* instruction VSUB__VX, encoding '0b00001000000000000100000001010111' */ + {32, 0b00001000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsub__vx}, + /* instruction VRSUB__VI, encoding '0b00001100000000000011000001010111' */ + {32, 0b00001100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vrsub__vi}, + /* instruction VRSUB__VX, encoding '0b00001100000000000100000001010111' */ + {32, 0b00001100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vrsub__vx}, + /* instruction VWADDU__VV, encoding '0b11000000000000000010000001010111' */ + {32, 0b11000000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwaddu__vv}, + /* instruction VWADDU__VX, encoding '0b11000000000000000110000001010111' */ + {32, 0b11000000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwaddu__vx}, + /* instruction VWSUBU__VV, encoding '0b11001000000000000010000001010111' */ + {32, 0b11001000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwsubu__vv}, + /* instruction VWSUBU__VX, encoding '0b11001000000000000110000001010111' */ + {32, 0b11001000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwsubu__vx}, + /* instruction VWADD__VV, encoding '0b11000100000000000010000001010111' */ + {32, 0b11000100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwadd__vv}, + /* instruction VWADD__VX, encoding '0b11000100000000000110000001010111' */ + {32, 0b11000100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwadd__vx}, + /* instruction VWSUB__VV, encoding '0b11001100000000000010000001010111' */ + {32, 0b11001100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwsub__vv}, + /* instruction VWSUB__VX, encoding '0b11001100000000000110000001010111' */ + {32, 0b11001100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwsub__vx}, + /* instruction VWADDU__WV, encoding '0b11010000000000000010000001010111' */ + {32, 0b11010000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwaddu__wv}, + /* instruction VWADDU__WX, encoding '0b11010000000000000110000001010111' */ + {32, 0b11010000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwaddu__wx}, + /* instruction VWSUBU__WV, encoding '0b11011000000000000010000001010111' */ + {32, 0b11011000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwsubu__wv}, + /* instruction VWSUBU__WX, encoding '0b11011000000000000110000001010111' */ + {32, 0b11011000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwsubu__wx}, + /* instruction VWADD__WV, encoding '0b11010100000000000010000001010111' */ + {32, 0b11010100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwadd__wv}, + /* instruction VWADD__WX, encoding '0b11010100000000000110000001010111' */ + {32, 0b11010100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwadd__wx}, + /* instruction VWSUB__WV, encoding '0b11011100000000000010000001010111' */ + {32, 0b11011100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwsub__wv}, + /* instruction VWSUB__WX, encoding '0b11011100000000000110000001010111' */ + {32, 0b11011100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwsub__wx}, + /* instruction VZEXT__VF2, encoding '0b01001000000000110010000001010111' */ + {32, 0b01001000000000110010000001010111, 0b11111100000011111111000001111111, &this_class::__vzext__vf2}, + /* instruction VSEXT__VF2, encoding '0b01001000000000111010000001010111' */ + {32, 0b01001000000000111010000001010111, 0b11111100000011111111000001111111, &this_class::__vsext__vf2}, + /* instruction VZEXT__VF4, encoding '0b01001000000000100010000001010111' */ + {32, 0b01001000000000100010000001010111, 0b11111100000011111111000001111111, &this_class::__vzext__vf4}, + /* instruction VSEXT__VF4, encoding '0b01001000000000101010000001010111' */ + {32, 0b01001000000000101010000001010111, 0b11111100000011111111000001111111, &this_class::__vsext__vf4}, + /* instruction VZEXT__VF8, encoding '0b01001000000000010010000001010111' */ + {32, 0b01001000000000010010000001010111, 0b11111100000011111111000001111111, &this_class::__vzext__vf8}, + /* instruction VSEXT__VF8, encoding '0b01001000000000011010000001010111' */ + {32, 0b01001000000000011010000001010111, 0b11111100000011111111000001111111, &this_class::__vsext__vf8}, + /* instruction VADC__VVM, encoding '0b01000000000000000000000001010111' */ + {32, 0b01000000000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vadc__vvm}, + /* instruction VADC__VXM, encoding '0b01000000000000000100000001010111' */ + {32, 0b01000000000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vadc__vxm}, + /* instruction VADC__VIM, encoding '0b01000000000000000011000001010111' */ + {32, 0b01000000000000000011000001010111, 0b11111110000000000111000001111111, &this_class::__vadc__vim}, + /* instruction VMADC__VVM, encoding '0b01000100000000000000000001010111' */ + {32, 0b01000100000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vvm}, + /* instruction VMADC__VXM, encoding '0b01000100000000000100000001010111' */ + {32, 0b01000100000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vxm}, + /* instruction VMADC__VIM, encoding '0b01000100000000000011000001010111' */ + {32, 0b01000100000000000011000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vim}, + /* instruction VMADC__VV, encoding '0b01000110000000000000000001010111' */ + {32, 0b01000110000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vv}, + /* instruction VMADC__VX, encoding '0b01000110000000000100000001010111' */ + {32, 0b01000110000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vx}, + /* instruction VMADC__VI, encoding '0b01000110000000000011000001010111' */ + {32, 0b01000110000000000011000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vi}, + /* instruction VSBC__VVM, encoding '0b01001000000000000000000001010111' */ + {32, 0b01001000000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vsbc__vvm}, + /* instruction VSBC__VXM, encoding '0b01001000000000000100000001010111' */ + {32, 0b01001000000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vsbc__vxm}, + /* instruction VMSBC__VVM, encoding '0b01001100000000000000000001010111' */ + {32, 0b01001100000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vmsbc__vvm}, + /* instruction VMSBC__VXM, encoding '0b01001100000000000100000001010111' */ + {32, 0b01001100000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vmsbc__vxm}, + /* instruction VMSBC__VV, encoding '0b01001110000000000000000001010111' */ + {32, 0b01001110000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vmsbc__vv}, + /* instruction VMSBC__VX, encoding '0b01001110000000000100000001010111' */ + {32, 0b01001110000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vmsbc__vx}, + /* instruction VAND__VI, encoding '0b00100100000000000011000001010111' */ + {32, 0b00100100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vand__vi}, + /* instruction VAND__VV, encoding '0b00100100000000000000000001010111' */ + {32, 0b00100100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vand__vv}, + /* instruction VAND__VX, encoding '0b00100100000000000100000001010111' */ + {32, 0b00100100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vand__vx}, + /* instruction VOR__VI, encoding '0b00101000000000000011000001010111' */ + {32, 0b00101000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vor__vi}, + /* instruction VOR__VV, encoding '0b00101000000000000000000001010111' */ + {32, 0b00101000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vor__vv}, + /* instruction VOR__VX, encoding '0b00101000000000000100000001010111' */ + {32, 0b00101000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vor__vx}, + /* instruction VXOR__VI, encoding '0b00101100000000000011000001010111' */ + {32, 0b00101100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vxor__vi}, + /* instruction VXOR__VV, encoding '0b00101100000000000000000001010111' */ + {32, 0b00101100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vxor__vv}, + /* instruction VXOR__VX, encoding '0b00101100000000000100000001010111' */ + {32, 0b00101100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vxor__vx}, + /* instruction VSLL__VI, encoding '0b10010100000000000011000001010111' */ + {32, 0b10010100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vsll__vi}, + /* instruction VSLL__VV, encoding '0b10010100000000000000000001010111' */ + {32, 0b10010100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsll__vv}, + /* instruction VSLL__VX, encoding '0b10010100000000000100000001010111' */ + {32, 0b10010100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsll__vx}, + /* instruction VSRL__VI, encoding '0b10100000000000000011000001010111' */ + {32, 0b10100000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vsrl__vi}, + /* instruction VSRL__VV, encoding '0b10100000000000000000000001010111' */ + {32, 0b10100000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsrl__vv}, + /* instruction VSRL__VX, encoding '0b10100000000000000100000001010111' */ + {32, 0b10100000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsrl__vx}, + /* instruction VSRA__VI, encoding '0b10100100000000000011000001010111' */ + {32, 0b10100100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vsra__vi}, + /* instruction VSRA__VV, encoding '0b10100100000000000000000001010111' */ + {32, 0b10100100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsra__vv}, + /* instruction VSRA__VX, encoding '0b10100100000000000100000001010111' */ + {32, 0b10100100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsra__vx}, + /* instruction VNSRL__WI, encoding '0b10110000000000000011000001010111' */ + {32, 0b10110000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vnsrl__wi}, + /* instruction VNSRL__WV, encoding '0b10110000000000000000000001010111' */ + {32, 0b10110000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vnsrl__wv}, + /* instruction VNSRL__WX, encoding '0b10110000000000000100000001010111' */ + {32, 0b10110000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vnsrl__wx}, + /* instruction VNSRA__WI, encoding '0b10110100000000000011000001010111' */ + {32, 0b10110100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vnsra__wi}, + /* instruction VNSRA__WV, encoding '0b10110100000000000000000001010111' */ + {32, 0b10110100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vnsra__wv}, + /* instruction VNSRA__WX, encoding '0b10110100000000000100000001010111' */ + {32, 0b10110100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vnsra__wx}, + /* instruction VMSEQ__VI, encoding '0b01100000000000000011000001010111' */ + {32, 0b01100000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmseq__vi}, + /* instruction VMSEQ__VV, encoding '0b01100000000000000000000001010111' */ + {32, 0b01100000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmseq__vv}, + /* instruction VMSEQ__VX, encoding '0b01100000000000000100000001010111' */ + {32, 0b01100000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmseq__vx}, + /* instruction VMSNE__VI, encoding '0b01100100000000000011000001010111' */ + {32, 0b01100100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmsne__vi}, + /* instruction VMSNE__VV, encoding '0b01100100000000000000000001010111' */ + {32, 0b01100100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmsne__vv}, + /* instruction VMSNE__VX, encoding '0b01100100000000000100000001010111' */ + {32, 0b01100100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsne__vx}, + /* instruction VMSLTU__VV, encoding '0b01101000000000000000000001010111' */ + {32, 0b01101000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmsltu__vv}, + /* instruction VMSLTU__VX, encoding '0b01101000000000000100000001010111' */ + {32, 0b01101000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsltu__vx}, + /* instruction VMSLT__VV, encoding '0b01101100000000000000000001010111' */ + {32, 0b01101100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmslt__vv}, + /* instruction VMSLT__VX, encoding '0b01101100000000000100000001010111' */ + {32, 0b01101100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmslt__vx}, + /* instruction VMSLEU__VI, encoding '0b01110000000000000011000001010111' */ + {32, 0b01110000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmsleu__vi}, + /* instruction VMSLEU__VV, encoding '0b01110000000000000000000001010111' */ + {32, 0b01110000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmsleu__vv}, + /* instruction VMSLEU__VX, encoding '0b01110000000000000100000001010111' */ + {32, 0b01110000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsleu__vx}, + /* instruction VMSLE__VI, encoding '0b01110100000000000011000001010111' */ + {32, 0b01110100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmsle__vi}, + /* instruction VMSLE__VV, encoding '0b01110100000000000000000001010111' */ + {32, 0b01110100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmsle__vv}, + /* instruction VMSLE__VX, encoding '0b01110100000000000100000001010111' */ + {32, 0b01110100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsle__vx}, + /* instruction VMSGTU__VI, encoding '0b01111000000000000011000001010111' */ + {32, 0b01111000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmsgtu__vi}, + /* instruction VMSGTU__VX, encoding '0b01111000000000000100000001010111' */ + {32, 0b01111000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsgtu__vx}, + /* instruction VMSGT__VI, encoding '0b01111100000000000011000001010111' */ + {32, 0b01111100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmsgt__vi}, + /* instruction VMSGT__VX, encoding '0b01111100000000000100000001010111' */ + {32, 0b01111100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsgt__vx}, + /* instruction VMINU__VV, encoding '0b00010000000000000000000001010111' */ + {32, 0b00010000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vminu__vv}, + /* instruction VMINU__VX, encoding '0b00010000000000000100000001010111' */ + {32, 0b00010000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vminu__vx}, + /* instruction VMIN__VV, encoding '0b00010100000000000000000001010111' */ + {32, 0b00010100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmin__vv}, + /* instruction VMIN__VX, encoding '0b00010100000000000100000001010111' */ + {32, 0b00010100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmin__vx}, + /* instruction VMAXU__VV, encoding '0b00011000000000000000000001010111' */ + {32, 0b00011000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmaxu__vv}, + /* instruction VMAXU__VX, encoding '0b00011000000000000100000001010111' */ + {32, 0b00011000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmaxu__vx}, + /* instruction VMAX__VV, encoding '0b00011100000000000000000001010111' */ + {32, 0b00011100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmax__vv}, + /* instruction VMAX__VX, encoding '0b00011100000000000100000001010111' */ + {32, 0b00011100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmax__vx}, + /* instruction VMUL__VV, encoding '0b10010100000000000010000001010111' */ + {32, 0b10010100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmul__vv}, + /* instruction VMUL__VX, encoding '0b10010100000000000110000001010111' */ + {32, 0b10010100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmul__vx}, + /* instruction VMULH__VV, encoding '0b10011100000000000010000001010111' */ + {32, 0b10011100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmulh__vv}, + /* instruction VMULH__VX, encoding '0b10011100000000000110000001010111' */ + {32, 0b10011100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmulh__vx}, + /* instruction VMULHU__VV, encoding '0b10010000000000000010000001010111' */ + {32, 0b10010000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmulhu__vv}, + /* instruction VMULHU__VX, encoding '0b10010000000000000110000001010111' */ + {32, 0b10010000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmulhu__vx}, + /* instruction VMULHSU__VV, encoding '0b10011000000000000010000001010111' */ + {32, 0b10011000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmulhsu__vv}, + /* instruction VMULHSU__VX, encoding '0b10011000000000000110000001010111' */ + {32, 0b10011000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmulhsu__vx}, + /* instruction VDIVU__VV, encoding '0b10000000000000000010000001010111' */ + {32, 0b10000000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vdivu__vv}, + /* instruction VDIVU__VX, encoding '0b10000000000000000110000001010111' */ + {32, 0b10000000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vdivu__vx}, + /* instruction VDIV__VV, encoding '0b10000100000000000010000001010111' */ + {32, 0b10000100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vdiv__vv}, + /* instruction VDIV__VX, encoding '0b10000100000000000110000001010111' */ + {32, 0b10000100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vdiv__vx}, + /* instruction VREMU__VV, encoding '0b10001000000000000010000001010111' */ + {32, 0b10001000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vremu__vv}, + /* instruction VREMU__VX, encoding '0b10001000000000000110000001010111' */ + {32, 0b10001000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vremu__vx}, + /* instruction VREM__VV, encoding '0b10001100000000000010000001010111' */ + {32, 0b10001100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vrem__vv}, + /* instruction VREM__VX, encoding '0b10001100000000000110000001010111' */ + {32, 0b10001100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vrem__vx}, + /* instruction VWMUL__VV, encoding '0b11101100000000000010000001010111' */ + {32, 0b11101100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmul__vv}, + /* instruction VWMUL__VX, encoding '0b11101100000000000110000001010111' */ + {32, 0b11101100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmul__vx}, + /* instruction VWMULU__VV, encoding '0b11100000000000000010000001010111' */ + {32, 0b11100000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmulu__vv}, + /* instruction VWMULU__VX, encoding '0b11100000000000000110000001010111' */ + {32, 0b11100000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmulu__vx}, + /* instruction VWMULSU__VV, encoding '0b11101000000000000010000001010111' */ + {32, 0b11101000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmulsu__vv}, + /* instruction VWMULSU__VX, encoding '0b11101000000000000110000001010111' */ + {32, 0b11101000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmulsu__vx}, + /* instruction VMACC__VV, encoding '0b10110100000000000010000001010111' */ + {32, 0b10110100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmacc__vv}, + /* instruction VMACC__VX, encoding '0b10110100000000000110000001010111' */ + {32, 0b10110100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmacc__vx}, + /* instruction VNMSAC__VV, encoding '0b10111100000000000010000001010111' */ + {32, 0b10111100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vnmsac__vv}, + /* instruction VNMSAC__VX, encoding '0b10111100000000000110000001010111' */ + {32, 0b10111100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vnmsac__vx}, + /* instruction VMADD__VV, encoding '0b10100100000000000010000001010111' */ + {32, 0b10100100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmadd__vv}, + /* instruction VMADD__VX, encoding '0b10100100000000000110000001010111' */ + {32, 0b10100100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmadd__vx}, + /* instruction VNMSUB__VV, encoding '0b10101100000000000010000001010111' */ + {32, 0b10101100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vnmsub__vv}, + /* instruction VNMSUB__VX, encoding '0b10101100000000000110000001010111' */ + {32, 0b10101100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vnmsub__vx}, + /* instruction VWMACCU__VV, encoding '0b11110000000000000010000001010111' */ + {32, 0b11110000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmaccu__vv}, + /* instruction VWMACCU__VX, encoding '0b11110000000000000110000001010111' */ + {32, 0b11110000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmaccu__vx}, + /* instruction VWMACC__VV, encoding '0b11110100000000000010000001010111' */ + {32, 0b11110100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmacc__vv}, + /* instruction VWMACC__VX, encoding '0b11110100000000000110000001010111' */ + {32, 0b11110100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmacc__vx}, + /* instruction VWMACCSU__VV, encoding '0b11111100000000000010000001010111' */ + {32, 0b11111100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmaccsu__vv}, + /* instruction VWMACCSU__VX, encoding '0b11111100000000000110000001010111' */ + {32, 0b11111100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmaccsu__vx}, + /* instruction VWMACCUS__VX, encoding '0b11111000000000000110000001010111' */ + {32, 0b11111000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmaccus__vx}, + /* instruction VMERGE__VIM, encoding '0b01011100000000000011000001010111' */ + {32, 0b01011100000000000011000001010111, 0b11111110000000000111000001111111, &this_class::__vmerge__vim}, + /* instruction VMERGE__VVM, encoding '0b01011100000000000000000001010111' */ + {32, 0b01011100000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vmerge__vvm}, + /* instruction VMERGE__VXM, encoding '0b01011100000000000100000001010111' */ + {32, 0b01011100000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vmerge__vxm}, + /* instruction VMV__V__I, encoding '0b01011110000000000011000001010111' */ + {32, 0b01011110000000000011000001010111, 0b11111111111100000111000001111111, &this_class::__vmv__v__i}, + /* instruction VMV__V__V, encoding '0b01011110000000000000000001010111' */ + {32, 0b01011110000000000000000001010111, 0b11111111111100000111000001111111, &this_class::__vmv__v__v}, + /* instruction VMV__V__X, encoding '0b01011110000000000100000001010111' */ + {32, 0b01011110000000000100000001010111, 0b11111111111100000111000001111111, &this_class::__vmv__v__x}, + /* instruction VSADDU__VI, encoding '0b10000000000000000011000001010111' */ + {32, 0b10000000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vsaddu__vi}, + /* instruction VSADDU__VV, encoding '0b10000000000000000000000001010111' */ + {32, 0b10000000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsaddu__vv}, + /* instruction VSADDU__VX, encoding '0b10000000000000000100000001010111' */ + {32, 0b10000000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsaddu__vx}, + /* instruction VSADD__VI, encoding '0b10000100000000000011000001010111' */ + {32, 0b10000100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vsadd__vi}, + /* instruction VSADD__VV, encoding '0b10000100000000000000000001010111' */ + {32, 0b10000100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsadd__vv}, + /* instruction VSADD__VX, encoding '0b10000100000000000100000001010111' */ + {32, 0b10000100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsadd__vx}, + /* instruction VSSUBU__VV, encoding '0b10001000000000000000000001010111' */ + {32, 0b10001000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vssubu__vv}, + /* instruction VSSUBU__VX, encoding '0b10001000000000000100000001010111' */ + {32, 0b10001000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vssubu__vx}, + /* instruction VSSUB__VV, encoding '0b10001100000000000000000001010111' */ + {32, 0b10001100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vssub__vv}, + /* instruction VSSUB__VX, encoding '0b10001100000000000100000001010111' */ + {32, 0b10001100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vssub__vx}, + /* instruction VAADDU__VV, encoding '0b00100000000000000010000001010111' */ + {32, 0b00100000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vaaddu__vv}, + /* instruction VAADDU__VX, encoding '0b00100000000000000110000001010111' */ + {32, 0b00100000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vaaddu__vx}, + /* instruction VAADD__VV, encoding '0b00100100000000000010000001010111' */ + {32, 0b00100100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vaadd__vv}, + /* instruction VAADD__VX, encoding '0b00100100000000000110000001010111' */ + {32, 0b00100100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vaadd__vx}, + /* instruction VASUBU__VV, encoding '0b00101000000000000010000001010111' */ + {32, 0b00101000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vasubu__vv}, + /* instruction VASUBU__VX, encoding '0b00101000000000000110000001010111' */ + {32, 0b00101000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vasubu__vx}, + /* instruction VASUB__VV, encoding '0b00101100000000000010000001010111' */ + {32, 0b00101100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vasub__vv}, + /* instruction VASUB__VX, encoding '0b00101100000000000110000001010111' */ + {32, 0b00101100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vasub__vx}, + /* instruction VSMUL__VV, encoding '0b10011100000000000000000001010111' */ + {32, 0b10011100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsmul__vv}, + /* instruction VSMUL__VX, encoding '0b10011100000000000100000001010111' */ + {32, 0b10011100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsmul__vx}, + /* instruction VSSRL__VI, encoding '0b10101000000000000011000001010111' */ + {32, 0b10101000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vssrl__vi}, + /* instruction VSSRL__VV, encoding '0b10101000000000000000000001010111' */ + {32, 0b10101000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vssrl__vv}, + /* instruction VSSRL__VX, encoding '0b10101000000000000100000001010111' */ + {32, 0b10101000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vssrl__vx}, + /* instruction VSSRA__VI, encoding '0b10101100000000000011000001010111' */ + {32, 0b10101100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vssra__vi}, + /* instruction VSSRA__VV, encoding '0b10101100000000000000000001010111' */ + {32, 0b10101100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vssra__vv}, + /* instruction VSSRA__VX, encoding '0b10101100000000000100000001010111' */ + {32, 0b10101100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vssra__vx}, + /* instruction VNCLIPU__WI, encoding '0b10111000000000000011000001010111' */ + {32, 0b10111000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vnclipu__wi}, + /* instruction VNCLIPU__WV, encoding '0b10111000000000000000000001010111' */ + {32, 0b10111000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vnclipu__wv}, + /* instruction VNCLIPU__WX, encoding '0b10111000000000000100000001010111' */ + {32, 0b10111000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vnclipu__wx}, + /* instruction VNCLIP__WI, encoding '0b10111100000000000011000001010111' */ + {32, 0b10111100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vnclip__wi}, + /* instruction VNCLIP__WV, encoding '0b10111100000000000000000001010111' */ + {32, 0b10111100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vnclip__wv}, + /* instruction VNCLIP__WX, encoding '0b10111100000000000100000001010111' */ + {32, 0b10111100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vnclip__wx}, + /* instruction VREDSUM__VS, encoding '0b00000000000000000010000001010111' */ + {32, 0b00000000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredsum__vs}, + /* instruction VREDMAXU__VS, encoding '0b00011000000000000010000001010111' */ + {32, 0b00011000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredmaxu__vs}, + /* instruction VREDMAX__VS, encoding '0b00011100000000000010000001010111' */ + {32, 0b00011100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredmax__vs}, + /* instruction VREDMINU__VS, encoding '0b00010000000000000010000001010111' */ + {32, 0b00010000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredminu__vs}, + /* instruction VREDMIN__VS, encoding '0b00010100000000000010000001010111' */ + {32, 0b00010100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredmin__vs}, + /* instruction VREDAND__VS, encoding '0b00000100000000000010000001010111' */ + {32, 0b00000100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredand__vs}, + /* instruction VREDOR__VS, encoding '0b00001000000000000010000001010111' */ + {32, 0b00001000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredor__vs}, + /* instruction VREDXOR__VS, encoding '0b00001100000000000010000001010111' */ + {32, 0b00001100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredxor__vs}, + /* instruction VWREDSUMU__VS, encoding '0b11000000000000000000000001010111' */ + {32, 0b11000000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vwredsumu__vs}, + /* instruction VWREDSUM__VS, encoding '0b11000100000000000000000001010111' */ + {32, 0b11000100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vwredsum__vs}, + /* instruction VFREDOSUM__VS, encoding '0b00001100000000000001000001010111' */ + {32, 0b00001100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfredosum__vs}, + /* instruction VFREDUSUM__VS, encoding '0b00000100000000000001000001010111' */ + {32, 0b00000100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfredusum__vs}, + /* instruction VFREDMAX__VS, encoding '0b00011100000000000001000001010111' */ + {32, 0b00011100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfredmax__vs}, + /* instruction VFREDMIN__VS, encoding '0b00010100000000000001000001010111' */ + {32, 0b00010100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfredmin__vs}, + /* instruction VFWREDOSUM__VS, encoding '0b11001100000000000001000001010111' */ + {32, 0b11001100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwredosum__vs}, + /* instruction VFWREDUSUM__VS, encoding '0b11000100000000000001000001010111' */ + {32, 0b11000100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwredusum__vs}, + /* instruction VMAND__MM, encoding '0b01100110000000000010000001010111' */ + {32, 0b01100110000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmand__mm}, + /* instruction VMNAND__MM, encoding '0b01110110000000000010000001010111' */ + {32, 0b01110110000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmnand__mm}, + /* instruction VMANDN__MM, encoding '0b01100010000000000010000001010111' */ + {32, 0b01100010000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmandn__mm}, + /* instruction VMXOR__MM, encoding '0b01101110000000000010000001010111' */ + {32, 0b01101110000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmxor__mm}, + /* instruction VMOR__MM, encoding '0b01101010000000000010000001010111' */ + {32, 0b01101010000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmor__mm}, + /* instruction VMNOR__MM, encoding '0b01111010000000000010000001010111' */ + {32, 0b01111010000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmnor__mm}, + /* instruction VMORN__MM, encoding '0b01110010000000000010000001010111' */ + {32, 0b01110010000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmorn__mm}, + /* instruction VMXNOR__MM, encoding '0b01111110000000000010000001010111' */ + {32, 0b01111110000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmxnor__mm}, + /* instruction VCPOP__M, encoding '0b01000000000010000010000001010111' */ + {32, 0b01000000000010000010000001010111, 0b11111100000011111111000001111111, &this_class::__vcpop__m}, + /* instruction VFIRST__M, encoding '0b01000000000010001010000001010111' */ + {32, 0b01000000000010001010000001010111, 0b11111100000011111111000001111111, &this_class::__vfirst__m}, + /* instruction VMSBF__M, encoding '0b01010000000000001010000001010111' */ + {32, 0b01010000000000001010000001010111, 0b11111100000011111111000001111111, &this_class::__vmsbf__m}, + /* instruction VMSIF__M, encoding '0b01010000000000011010000001010111' */ + {32, 0b01010000000000011010000001010111, 0b11111100000011111111000001111111, &this_class::__vmsif__m}, + /* instruction VMSOF__M, encoding '0b01010000000000010010000001010111' */ + {32, 0b01010000000000010010000001010111, 0b11111100000011111111000001111111, &this_class::__vmsof__m}, + /* instruction VIOTA__M, encoding '0b01010000000010000010000001010111' */ + {32, 0b01010000000010000010000001010111, 0b11111100000011111111000001111111, &this_class::__viota__m}, + /* instruction VID__V, encoding '0b01010000000010001010000001010111' */ + {32, 0b01010000000010001010000001010111, 0b11111101111111111111000001111111, &this_class::__vid__v}, + /* instruction VMV__S__X, encoding '0b01000010000000000110000001010111' */ + {32, 0b01000010000000000110000001010111, 0b11111111111100000111000001111111, &this_class::__vmv__s__x}, + /* instruction VMV__X__S, encoding '0b01000010000000000010000001010111' */ + {32, 0b01000010000000000010000001010111, 0b11111110000011111111000001111111, &this_class::__vmv__x__s}, + /* instruction VSLIDEUP__VI, encoding '0b00111000000000000011000001010111' */ + {32, 0b00111000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vslideup__vi}, + /* instruction VSLIDEUP__VX, encoding '0b00111000000000000100000001010111' */ + {32, 0b00111000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vslideup__vx}, + /* instruction VSLIDEDOWN__VI, encoding '0b00111100000000000011000001010111' */ + {32, 0b00111100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vslidedown__vi}, + /* instruction VSLIDEDOWN__VX, encoding '0b00111100000000000100000001010111' */ + {32, 0b00111100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vslidedown__vx}, + /* instruction VSLIDE1UP__VX, encoding '0b00111000000000000110000001010111' */ + {32, 0b00111000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vslide1up__vx}, + /* instruction VSLIDE1DOWN__VX, encoding '0b00111100000000000110000001010111' */ + {32, 0b00111100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vslide1down__vx}, + /* instruction VRGATHER__VI, encoding '0b00110000000000000011000001010111' */ + {32, 0b00110000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vrgather__vi}, + /* instruction VRGATHER__VV, encoding '0b00110000000000000000000001010111' */ + {32, 0b00110000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vrgather__vv}, + /* instruction VRGATHER__VX, encoding '0b00110000000000000100000001010111' */ + {32, 0b00110000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vrgather__vx}, + /* instruction VRGATHEREI16__VV, encoding '0b00111000000000000000000001010111' */ + {32, 0b00111000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vrgatherei16__vv}, + /* instruction VCOMPRESS__VM, encoding '0b01011110000000000010000001010111' */ + {32, 0b01011110000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vcompress__vm}, + /* instruction VMV1R__V, encoding '0b10011110000000000011000001010111' */ + {32, 0b10011110000000000011000001010111, 0b11111110000011111111000001111111, &this_class::__vmv1r__v}, + /* instruction VMV2R__V, encoding '0b10011110000000001011000001010111' */ + {32, 0b10011110000000001011000001010111, 0b11111110000011111111000001111111, &this_class::__vmv2r__v}, + /* instruction VMV4R__V, encoding '0b10011110000000011011000001010111' */ + {32, 0b10011110000000011011000001010111, 0b11111110000011111111000001111111, &this_class::__vmv4r__v}, + /* instruction VMV8R__V, encoding '0b10011110000000111011000001010111' */ + {32, 0b10011110000000111011000001010111, 0b11111110000011111111000001111111, &this_class::__vmv8r__v}, + /* instruction VFMV__S__F, encoding '0b01000010000000000101000001010111' */ + {32, 0b01000010000000000101000001010111, 0b11111111111100000111000001111111, &this_class::__vfmv__s__f}, + /* instruction VFMV__F__S, encoding '0b01000010000000000001000001010111' */ + {32, 0b01000010000000000001000001010111, 0b11111110000011111111000001111111, &this_class::__vfmv__f__s}, + /* instruction VFSLIDE1UP__VF, encoding '0b00111000000000000101000001010111' */ + {32, 0b00111000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfslide1up__vf}, + /* instruction VFSLIDE1DOWN__VF, encoding '0b00111100000000000101000001010111' */ + {32, 0b00111100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfslide1down__vf}, + /* instruction VFADD__VF, encoding '0b00000000000000000101000001010111' */ + {32, 0b00000000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfadd__vf}, + /* instruction VFADD__VV, encoding '0b00000000000000000001000001010111' */ + {32, 0b00000000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfadd__vv}, + /* instruction VFSUB__VF, encoding '0b00001000000000000101000001010111' */ + {32, 0b00001000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfsub__vf}, + /* instruction VFSUB__VV, encoding '0b00001000000000000001000001010111' */ + {32, 0b00001000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfsub__vv}, + /* instruction VFRSUB__VF, encoding '0b10011100000000000101000001010111' */ + {32, 0b10011100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfrsub__vf}, + /* instruction VFWADD__VF, encoding '0b11000000000000000101000001010111' */ + {32, 0b11000000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwadd__vf}, + /* instruction VFWADD__VV, encoding '0b11000000000000000001000001010111' */ + {32, 0b11000000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwadd__vv}, + /* instruction VFWSUB__VF, encoding '0b11001000000000000101000001010111' */ + {32, 0b11001000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwsub__vf}, + /* instruction VFWSUB__VV, encoding '0b11001000000000000001000001010111' */ + {32, 0b11001000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwsub__vv}, + /* instruction VFWADD__WF, encoding '0b11010000000000000101000001010111' */ + {32, 0b11010000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwadd__wf}, + /* instruction VFWADD__WV, encoding '0b11010000000000000001000001010111' */ + {32, 0b11010000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwadd__wv}, + /* instruction VFWSUB__WF, encoding '0b11011000000000000101000001010111' */ + {32, 0b11011000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwsub__wf}, + /* instruction VFWSUB__WV, encoding '0b11011000000000000001000001010111' */ + {32, 0b11011000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwsub__wv}, + /* instruction VFMUL__VF, encoding '0b10010000000000000101000001010111' */ + {32, 0b10010000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmul__vf}, + /* instruction VFMUL__VV, encoding '0b10010000000000000001000001010111' */ + {32, 0b10010000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmul__vv}, + /* instruction VFDIV__VF, encoding '0b10000000000000000101000001010111' */ + {32, 0b10000000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfdiv__vf}, + /* instruction VFDIV__VV, encoding '0b10000000000000000001000001010111' */ + {32, 0b10000000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfdiv__vv}, + /* instruction VFRDIV__VF, encoding '0b10000100000000000101000001010111' */ + {32, 0b10000100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfrdiv__vf}, + /* instruction VFWMUL__VF, encoding '0b11100000000000000101000001010111' */ + {32, 0b11100000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmul__vf}, + /* instruction VFWMUL__VV, encoding '0b11100000000000000001000001010111' */ + {32, 0b11100000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmul__vv}, + /* instruction VFMACC__VF, encoding '0b10110000000000000101000001010111' */ + {32, 0b10110000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmacc__vf}, + /* instruction VFMACC__VV, encoding '0b10110000000000000001000001010111' */ + {32, 0b10110000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmacc__vv}, + /* instruction VFNMACC__VF, encoding '0b10110100000000000101000001010111' */ + {32, 0b10110100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmacc__vf}, + /* instruction VFNMACC__VV, encoding '0b10110100000000000001000001010111' */ + {32, 0b10110100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmacc__vv}, + /* instruction VFMSAC__VF, encoding '0b10111000000000000101000001010111' */ + {32, 0b10111000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmsac__vf}, + /* instruction VFMSAC__VV, encoding '0b10111000000000000001000001010111' */ + {32, 0b10111000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmsac__vv}, + /* instruction VFNMSAC__VF, encoding '0b10111100000000000101000001010111' */ + {32, 0b10111100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmsac__vf}, + /* instruction VFNMSAC__VV, encoding '0b10111100000000000001000001010111' */ + {32, 0b10111100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmsac__vv}, + /* instruction VFMADD__VF, encoding '0b10100000000000000101000001010111' */ + {32, 0b10100000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmadd__vf}, + /* instruction VFMADD__VV, encoding '0b10100000000000000001000001010111' */ + {32, 0b10100000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmadd__vv}, + /* instruction VFNMADD__VF, encoding '0b10100100000000000101000001010111' */ + {32, 0b10100100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmadd__vf}, + /* instruction VFNMADD__VV, encoding '0b10100100000000000001000001010111' */ + {32, 0b10100100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmadd__vv}, + /* instruction VFMSUB__VF, encoding '0b10101000000000000101000001010111' */ + {32, 0b10101000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmsub__vf}, + /* instruction VFMSUB__VV, encoding '0b10101000000000000001000001010111' */ + {32, 0b10101000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmsub__vv}, + /* instruction VFNMSUB__VF, encoding '0b10101100000000000101000001010111' */ + {32, 0b10101100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmsub__vf}, + /* instruction VFNMSUB__VV, encoding '0b10101100000000000001000001010111' */ + {32, 0b10101100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmsub__vv}, + /* instruction VFWMACC__VF, encoding '0b11110000000000000101000001010111' */ + {32, 0b11110000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmacc__vf}, + /* instruction VFWMACC__VV, encoding '0b11110000000000000001000001010111' */ + {32, 0b11110000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmacc__vv}, + /* instruction VFWNMACC__VF, encoding '0b11110100000000000101000001010111' */ + {32, 0b11110100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwnmacc__vf}, + /* instruction VFWNMACC__VV, encoding '0b11110100000000000001000001010111' */ + {32, 0b11110100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwnmacc__vv}, + /* instruction VFWMSAC__VF, encoding '0b11111000000000000101000001010111' */ + {32, 0b11111000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmsac__vf}, + /* instruction VFWMSAC__VV, encoding '0b11111000000000000001000001010111' */ + {32, 0b11111000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmsac__vv}, + /* instruction VFWNMSAC__VF, encoding '0b11111100000000000101000001010111' */ + {32, 0b11111100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwnmsac__vf}, + /* instruction VFWNMSAC__VV, encoding '0b11111100000000000001000001010111' */ + {32, 0b11111100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwnmsac__vv}, + /* instruction VFSQRT__V, encoding '0b01001100000000000001000001010111' */ + {32, 0b01001100000000000001000001010111, 0b11111100000011111111000001111111, &this_class::__vfsqrt__v}, + /* instruction VFRSQRT7__V, encoding '0b01001100000000100001000001010111' */ + {32, 0b01001100000000100001000001010111, 0b11111100000011111111000001111111, &this_class::__vfrsqrt7__v}, + /* instruction VFREC7__V, encoding '0b01001100000000101001000001010111' */ + {32, 0b01001100000000101001000001010111, 0b11111100000011111111000001111111, &this_class::__vfrec7__v}, + /* instruction VFMIN__VF, encoding '0b00010000000000000101000001010111' */ + {32, 0b00010000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmin__vf}, + /* instruction VFMIN__VV, encoding '0b00010000000000000001000001010111' */ + {32, 0b00010000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmin__vv}, + /* instruction VFMAX__VF, encoding '0b00011000000000000101000001010111' */ + {32, 0b00011000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmax__vf}, + /* instruction VFMAX__VV, encoding '0b00011000000000000001000001010111' */ + {32, 0b00011000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmax__vv}, + /* instruction VFSGNJ__VF, encoding '0b00100000000000000101000001010111' */ + {32, 0b00100000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnj__vf}, + /* instruction VFSGNJ__VV, encoding '0b00100000000000000001000001010111' */ + {32, 0b00100000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnj__vv}, + /* instruction VFSGNJN__VF, encoding '0b00100100000000000101000001010111' */ + {32, 0b00100100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnjn__vf}, + /* instruction VFSGNJN__VV, encoding '0b00100100000000000001000001010111' */ + {32, 0b00100100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnjn__vv}, + /* instruction VFSGNJX__VF, encoding '0b00101000000000000101000001010111' */ + {32, 0b00101000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnjx__vf}, + /* instruction VFSGNJX__VV, encoding '0b00101000000000000001000001010111' */ + {32, 0b00101000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnjx__vv}, + /* instruction VMFEQ__VF, encoding '0b01100000000000000101000001010111' */ + {32, 0b01100000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmfeq__vf}, + /* instruction VMFEQ__VV, encoding '0b01100000000000000001000001010111' */ + {32, 0b01100000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vmfeq__vv}, + /* instruction VMFNE__VF, encoding '0b01110000000000000101000001010111' */ + {32, 0b01110000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmfne__vf}, + /* instruction VMFNE__VV, encoding '0b01110000000000000001000001010111' */ + {32, 0b01110000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vmfne__vv}, + /* instruction VMFLT__VF, encoding '0b01101100000000000101000001010111' */ + {32, 0b01101100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmflt__vf}, + /* instruction VMFLT__VV, encoding '0b01101100000000000001000001010111' */ + {32, 0b01101100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vmflt__vv}, + /* instruction VMFLE__VF, encoding '0b01100100000000000101000001010111' */ + {32, 0b01100100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmfle__vf}, + /* instruction VMFLE__VV, encoding '0b01100100000000000001000001010111' */ + {32, 0b01100100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vmfle__vv}, + /* instruction VMFGT__VF, encoding '0b01110100000000000101000001010111' */ + {32, 0b01110100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmfgt__vf}, + /* instruction VMFGE__VF, encoding '0b01111100000000000101000001010111' */ + {32, 0b01111100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmfge__vf}, + /* instruction VFCLASS__V, encoding '0b01001100000010000001000001010111' */ + {32, 0b01001100000010000001000001010111, 0b11111100000011111111000001111111, &this_class::__vfclass__v}, + /* instruction VFMERGE__VFM, encoding '0b01011100000000000101000001010111' */ + {32, 0b01011100000000000101000001010111, 0b11111110000000000111000001111111, &this_class::__vfmerge__vfm}, + /* instruction VFMV__V__F, encoding '0b01011110000000000101000001010111' */ + {32, 0b01011110000000000101000001010111, 0b11111111111100000111000001111111, &this_class::__vfmv__v__f}, + /* instruction VFCVT__XU__F__V, encoding '0b01001000000000000001000001010111' */ + {32, 0b01001000000000000001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__xu__f__v}, + /* instruction VFCVT__X__F__V, encoding '0b01001000000000001001000001010111' */ + {32, 0b01001000000000001001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__x__f__v}, + /* instruction VFCVT__RTZ__XU__F__V, encoding '0b01001000000000110001000001010111' */ + {32, 0b01001000000000110001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__rtz__xu__f__v}, + /* instruction VFCVT__RTZ__X__F__V, encoding '0b01001000000000111001000001010111' */ + {32, 0b01001000000000111001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__rtz__x__f__v}, + /* instruction VFCVT__F__XU__V, encoding '0b01001000000000010001000001010111' */ + {32, 0b01001000000000010001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__f__xu__v}, + /* instruction VFCVT__F__X__V, encoding '0b01001000000000011001000001010111' */ + {32, 0b01001000000000011001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__f__x__v}, + /* instruction VFWCVT__XU__F__V, encoding '0b01001000000001000001000001010111' */ + {32, 0b01001000000001000001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__xu__f__v}, + /* instruction VFWCVT__X__F__V, encoding '0b01001000000001001001000001010111' */ + {32, 0b01001000000001001001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__x__f__v}, + /* instruction VFWCVT__RTZ__XU__F__V, encoding '0b01001000000001110001000001010111' */ + {32, 0b01001000000001110001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__rtz__xu__f__v}, + /* instruction VFWCVT__RTZ__X__F__V, encoding '0b01001000000001111001000001010111' */ + {32, 0b01001000000001111001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__rtz__x__f__v}, + /* instruction VFWCVT__F__XU__V, encoding '0b01001000000001010001000001010111' */ + {32, 0b01001000000001010001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__f__xu__v}, + /* instruction VFWCVT__F__X__V, encoding '0b01001000000001011001000001010111' */ + {32, 0b01001000000001011001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__f__x__v}, + /* instruction VFWCVT__F__F__V, encoding '0b01001000000001100001000001010111' */ + {32, 0b01001000000001100001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__f__f__v}, + /* instruction VFNCVT__X__F__W, encoding '0b01001000000010001001000001010111' */ + {32, 0b01001000000010001001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__x__f__w}, + /* instruction VFNCVT__XU__F__W, encoding '0b01001000000010000001000001010111' */ + {32, 0b01001000000010000001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__xu__f__w}, + /* instruction VFNCVT__RTZ__XU__F__W, encoding '0b01001000000010110001000001010111' */ + {32, 0b01001000000010110001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__rtz__xu__f__w}, + /* instruction VFNCVT__RTZ__X__F__W, encoding '0b01001000000010111001000001010111' */ + {32, 0b01001000000010111001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__rtz__x__f__w}, + /* instruction VFNCVT__F__XU__W, encoding '0b01001000000010010001000001010111' */ + {32, 0b01001000000010010001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__f__xu__w}, + /* instruction VFNCVT__F__X__W, encoding '0b01001000000010011001000001010111' */ + {32, 0b01001000000010011001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__f__x__w}, + /* instruction VFNCVT__F__F__W, encoding '0b01001000000010100001000001010111' */ + {32, 0b01001000000010100001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__f__f__w}, + /* instruction VFNCVT__ROD__F__F__W, encoding '0b01001000000010101001000001010111' */ + {32, 0b01001000000010101001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__rod__f__f__w}, + }}; + + //needs to be declared after instr_descr + decoder instr_decoder; + + /* instruction definitions */ + /* instruction 0: LUI */ + continuation_e __lui(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LUI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 0); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + (uint32_t)((int32_t)imm)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 0); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 1: AUIPC */ + continuation_e __auipc(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AUIPC_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 1); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + (uint32_t)(PC+(int32_t)imm)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 1); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 2: JAL */ + continuation_e __jal(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("JAL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 2); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto new_pc = (uint32_t)(PC+(int32_t)sext<21>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + (uint32_t)(PC+4)); + } + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 2); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 3: JALR */ + continuation_e __jalr(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("JALR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 3); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto addr_mask = (uint32_t)- 2; + auto new_pc = gen_ext(cc, + (gen_operation(cc, band, (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), addr_mask)), 32, true); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, urem, new_pc, static_cast(traits::INSTR_ALIGNMENT)); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + (uint32_t)(PC+4)); + } + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(UNKNOWN_JUMP)); + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 3); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 4: BEQ */ + continuation_e __beq(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BEQ_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 4); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, eq, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 4); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 5: BNE */ + continuation_e __bne(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BNE_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 5); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 5); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 6: BLT */ + continuation_e __blt(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BLT_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 6); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, lt, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 6); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 7: BGE */ + continuation_e __bge(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BGE_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 7); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gte, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 7); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 8: BLTU */ + continuation_e __bltu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BLTU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 8); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ltu, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 8); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 9: BGEU */ + continuation_e __bgeu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BGEU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 9); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gteu, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 9); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 10: LB */ + continuation_e __lb(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LB_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 10); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto load_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, load_address, 1), 8, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 10); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 11: LH */ + continuation_e __lh(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LH_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 11); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto load_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, load_address, 2), 16, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 11); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 12: LW */ + continuation_e __lw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 12); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto load_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, load_address, 4), 32, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 12); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 13: LBU */ + continuation_e __lbu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LBU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 13); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto load_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + auto res = gen_read_mem(jh, traits::MEM, load_address, 1); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 13); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 14: LHU */ + continuation_e __lhu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LHU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 14); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto load_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + auto res = gen_read_mem(jh, traits::MEM, load_address, 2); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 14); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 15: SB */ + continuation_e __sb(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SB_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 15); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto store_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + gen_write_mem(jh, traits::MEM, store_address, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 8, false), 1); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 15); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 16: SH */ + continuation_e __sh(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SH_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 16); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto store_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + gen_write_mem(jh, traits::MEM, store_address, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 16, false), 2); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 16); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 17: SW */ + continuation_e __sw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 17); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto store_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + gen_write_mem(jh, traits::MEM, store_address, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 17); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 18: ADDI */ + continuation_e __addi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ADDI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 18); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 18); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 19: SLTI */ + continuation_e __slti(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLTI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 19); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto label_then1 = cc.newLabel(); + auto label_merge1 = cc.newLabel(); + auto tmp_reg1 = get_reg_Gp(cc, 8, false); + cmp(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, true), (int16_t)sext<12>(imm)); + cc.jl(label_then1); + mov(cc, tmp_reg1,0); + cc.jmp(label_merge1); + cc.bind(label_then1); + mov(cc, tmp_reg1, 1); + cc.bind(label_merge1); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg1 + , 32, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 19); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 20: SLTIU */ + continuation_e __sltiu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLTIU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 20); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto label_then2 = cc.newLabel(); + auto label_merge2 = cc.newLabel(); + auto tmp_reg2 = get_reg_Gp(cc, 8, false); + cmp(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))); + cc.jb(label_then2); + mov(cc, tmp_reg2,0); + cc.jmp(label_merge2); + cc.bind(label_then2); + mov(cc, tmp_reg2, 1); + cc.bind(label_merge2); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg2 + , 32, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 20); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 21: XORI */ + continuation_e __xori(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("XORI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 21); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, bxor, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 21); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 22: ORI */ + continuation_e __ori(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ORI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 22); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, bor, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 22); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 23: ANDI */ + continuation_e __andi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ANDI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 23); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 23); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 24: SLLI */ + continuation_e __slli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 24); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, shl, load_reg_from_mem_Gp(jh, traits::X0 + rs1), shamt)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 24); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 25: SRLI */ + continuation_e __srli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 25); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, shr, load_reg_from_mem_Gp(jh, traits::X0 + rs1), shamt)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 25); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 26: SRAI */ + continuation_e __srai(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRAI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 26); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, (gen_operation(cc, sar, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, true), shamt)), 32, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 26); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 27: ADD */ + continuation_e __add(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ADD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 27); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))), 32, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 27); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 28: SUB */ + continuation_e __sub(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SUB_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 28); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sub, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))), 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 28); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 29: SLL */ + continuation_e __sll(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 29); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, shl, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1))))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 29); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 30: SLT */ + continuation_e __slt(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLT_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 30); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto label_then3 = cc.newLabel(); + auto label_merge3 = cc.newLabel(); + auto tmp_reg3 = get_reg_Gp(cc, 8, false); + cmp(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, true), gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true)); + cc.jl(label_then3); + mov(cc, tmp_reg3,0); + cc.jmp(label_merge3); + cc.bind(label_then3); + mov(cc, tmp_reg3, 1); + cc.bind(label_merge3); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg3 + , 32, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 30); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 31: SLTU */ + continuation_e __sltu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLTU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 31); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto label_then4 = cc.newLabel(); + auto label_merge4 = cc.newLabel(); + auto tmp_reg4 = get_reg_Gp(cc, 8, false); + cmp(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cc.jb(label_then4); + mov(cc, tmp_reg4,0); + cc.jmp(label_merge4); + cc.bind(label_then4); + mov(cc, tmp_reg4, 1); + cc.bind(label_merge4); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg4 + , 32, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 31); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 32: XOR */ + continuation_e __xor(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("XOR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 32); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, bxor, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 32); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 33: SRL */ + continuation_e __srl(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 33); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, shr, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1))))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 33); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 34: SRA */ + continuation_e __sra(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRA_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 34); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sar, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, true), (gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1))))), 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 34); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 35: OR */ + continuation_e __or(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("OR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 35); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, bor, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 35); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 36: AND */ + continuation_e __and(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AND_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 36); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 36); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 37: FENCE */ + continuation_e __fence(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + uint8_t fm = ((bit_sub<28,4>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FENCE_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 37); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_write_mem(jh, traits::FENCE, static_cast(traits::fence), (uint8_t)pred<<4|succ, 4); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 37); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 38: ECALL */ + continuation_e __ecall(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "ecall"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ECALL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 38); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + gen_raise(jh, 0, 11); + auto returnValue = TRAP; + + gen_sync(jh, POST_SYNC, 38); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 39: EBREAK */ + continuation_e __ebreak(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "ebreak"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("EBREAK_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 39); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + gen_raise(jh, 0, 3); + auto returnValue = TRAP; + + gen_sync(jh, POST_SYNC, 39); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 40: MRET */ + continuation_e __mret(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "mret"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MRET_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 40); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + gen_leave(jh, 3); + auto returnValue = TRAP; + + gen_sync(jh, POST_SYNC, 40); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 41: WFI */ + continuation_e __wfi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "wfi"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("WFI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 41); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_wait_5; + cc.invoke(&call_wait_5, &wait, FuncSignature::build()); + setArg(call_wait_5, 0, 1); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 41); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 42: CSRRW */ + continuation_e __csrrw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 42); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrs1 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + if(rd!=0){ + auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); + gen_write_mem(jh, traits::CSR, csr, xrs1, 4); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + else { + gen_write_mem(jh, traits::CSR, csr, xrs1, 4); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 42); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 43: CSRRS */ + continuation_e __csrrs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 43); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); + auto xrs1 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + if(rs1!=0){ + gen_write_mem(jh, traits::CSR, csr, gen_operation(cc, bor, xrd, xrs1), 4); + } + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 43); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 44: CSRRC */ + continuation_e __csrrc(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRC_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 44); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); + auto xrs1 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + if(rs1!=0){ + gen_write_mem(jh, traits::CSR, csr, gen_operation(cc, band, xrd, gen_operation(cc, bnot, xrs1)), 4); + } + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 44); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 45: CSRRWI */ + continuation_e __csrrwi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRWI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 45); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); + gen_write_mem(jh, traits::CSR, csr, (uint32_t)zimm, 4); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 45); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 46: CSRRSI */ + continuation_e __csrrsi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRSI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 46); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); + if(zimm!=0){ + gen_write_mem(jh, traits::CSR, csr, gen_operation(cc, bor, xrd, (uint32_t)zimm), 4); + } + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 46); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 47: CSRRCI */ + continuation_e __csrrci(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRCI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 47); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); + if(zimm!=0){ + gen_write_mem(jh, traits::CSR, csr, gen_operation(cc, band, xrd, ~ ((uint32_t)zimm)), 4); + } + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 47); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 48: FENCE_I */ + continuation_e __fence_i(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FENCE_I_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 48); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_write_mem(jh, traits::FENCE, static_cast(traits::fencei), imm, 4); + auto returnValue = FLUSH; + + gen_sync(jh, POST_SYNC, 48); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 49: MUL */ + continuation_e __mul(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MUL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 49); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto res = gen_operation(cc, smul, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, true), gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 49); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 50: MULH */ + continuation_e __mulh(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MULH_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 50); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto res = gen_operation(cc, smul, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, true), gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sar, res, static_cast(traits::XLEN))), 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 50); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 51: MULHSU */ + continuation_e __mulhsu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MULHSU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 51); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto res = gen_operation(cc, sumul, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, true), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sar, res, static_cast(traits::XLEN))), 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 51); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 52: MULHU */ + continuation_e __mulhu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MULHU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 52); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto res = gen_operation(cc, umul, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, shr, res, static_cast(traits::XLEN))), 32, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 52); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 53: DIV */ + continuation_e __div(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("DIV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 53); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto dividend = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, true); + auto divisor = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + if(rd!=0){ + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, divisor, 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + auto MMIN = ((uint32_t)1)<<(static_cast(traits::XLEN)-1); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, land, gen_operation(cc, eq, load_reg_from_mem_Gp(jh, traits::X0 + rs1), MMIN), gen_operation(cc, eq, divisor, - 1)); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + mov(cc, get_ptr_for(jh, traits::X0+ rd), + MMIN); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sdiv, dividend, divisor)), 32, true)); + } + cc.bind(label_merge); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + mov(cc, get_ptr_for(jh, traits::X0+ rd), + (uint32_t)- 1); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 53); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 54: DIVU */ + continuation_e __divu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("DIVU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 54); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, udiv, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + (uint32_t)- 1); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 54); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 55: REM */ + continuation_e __rem(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("REM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 55); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + auto MMIN = (uint32_t)1<<(static_cast(traits::XLEN)-1); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, land, gen_operation(cc, eq, load_reg_from_mem_Gp(jh, traits::X0 + rs1), MMIN), gen_operation(cc, eq, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), - 1)); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, 0, 32, false) + ); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, (gen_operation(cc, srem, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, true), gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true))), 32, false)); + } + } + cc.bind(label_merge); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem_Gp(jh, traits::X0 + rs1)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 55); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 56: REMU */ + continuation_e __remu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("REMU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 56); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, urem, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem_Gp(jh, traits::X0 + rs1)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 56); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 57: LRW */ + continuation_e __lrw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {aq}, {rl}", fmt::arg("mnemonic", "lrw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("aq", name(aq)), fmt::arg("rl", name(rl))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LRW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 57); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false)), 32, true)); + gen_write_mem(jh, traits::RES, offs, (uint8_t)- 1, 1); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 57); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 58: SCW */ + continuation_e __scw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {aq}, {rl}", fmt::arg("mnemonic", "scw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", name(aq)), fmt::arg("rl", name(rl))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SCW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 58); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::RES, offs, 1); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, res1, 0); + cmp(cc, cond, 0); + cc.je(label_merge); + { + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), 4); + } + cc.bind(label_merge); + } + if(rd!=0){ + auto label_then6 = cc.newLabel(); + auto label_merge6 = cc.newLabel(); + auto tmp_reg6 = get_reg_Gp(cc, 8, false); + cmp(cc, res1, 0); + cc.jne(label_then6); + mov(cc, tmp_reg6,1); + cc.jmp(label_merge6); + cc.bind(label_then6); + mov(cc, tmp_reg6, 0); + cc.bind(label_merge6); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg6 + , 32, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 58); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 59: AMOSWAPW */ + continuation_e __amoswapw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoswapw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOSWAPW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 59); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res = load_reg_from_mem_Gp(jh, traits::X0 + rs2); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false)), 32, true)); + } + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + res, 32, false), 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 59); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 60: AMOADDW */ + continuation_e __amoaddw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoaddw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOADDW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 60); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false); + auto res2 = gen_operation(cc, add, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 32, true)); + } + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + res2, 32, true), 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 60); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 61: AMOXORW */ + continuation_e __amoxorw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoxorw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOXORW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 61); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 4); + auto res2 = gen_operation(cc, bxor, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + gen_ext(cc, res1, 32, true), 32, true), 32, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 61); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 62: AMOANDW */ + continuation_e __amoandw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoandw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOANDW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 62); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 4); + auto res2 = gen_operation(cc, band, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + gen_ext(cc, res1, 32, true), 32, true), 32, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 62); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 63: AMOORW */ + continuation_e __amoorw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoorw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOORW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 63); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 4); + auto res2 = gen_operation(cc, bor, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + gen_ext(cc, res1, 32, true), 32, true), 32, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 63); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 64: AMOMINW */ + continuation_e __amominw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amominw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMINW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 64); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false); + auto label_then7 = cc.newLabel(); + auto label_merge7 = cc.newLabel(); + auto tmp_reg7 = get_reg_Gp(cc, 32, false); + cmp(cc, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.jg(label_then7); + mov(cc, tmp_reg7,gen_ext(cc, res1, 32, false)); + cc.jmp(label_merge7); + cc.bind(label_then7); + mov(cc, tmp_reg7, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.bind(label_merge7); + auto res2 = tmp_reg7 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 32, true)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 64); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 65: AMOMAXW */ + continuation_e __amomaxw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMAXW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 65); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false); + auto label_then8 = cc.newLabel(); + auto label_merge8 = cc.newLabel(); + auto tmp_reg8 = get_reg_Gp(cc, 32, false); + cmp(cc, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.jl(label_then8); + mov(cc, tmp_reg8,gen_ext(cc, res1, 32, false)); + cc.jmp(label_merge8); + cc.bind(label_then8); + mov(cc, tmp_reg8, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.bind(label_merge8); + auto res2 = tmp_reg8 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 32, true)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 65); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 66: AMOMINUW */ + continuation_e __amominuw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amominuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMINUW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 66); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 4); + auto label_then9 = cc.newLabel(); + auto label_merge9 = cc.newLabel(); + auto tmp_reg9 = get_reg_Gp(cc, 32, false); + cmp(cc, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.ja(label_then9); + mov(cc, tmp_reg9,res1); + cc.jmp(label_merge9); + cc.bind(label_then9); + mov(cc, tmp_reg9, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.bind(label_merge9); + auto res2 = tmp_reg9 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + gen_ext(cc, res1, 32, true), 32, true), 32, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 66); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 67: AMOMAXUW */ + continuation_e __amomaxuw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMAXUW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 67); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 4); + auto label_then10 = cc.newLabel(); + auto label_merge10 = cc.newLabel(); + auto tmp_reg10 = get_reg_Gp(cc, 32, false); + cmp(cc, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.jb(label_then10); + mov(cc, tmp_reg10,res1); + cc.jmp(label_merge10); + cc.bind(label_then10); + mov(cc, tmp_reg10, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.bind(label_merge10); + auto res2 = tmp_reg10 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + gen_ext(cc, res1, 32, true), 32, true), 32, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 67); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 68: C__ADDI4SPN */ + continuation_e __c__addi4spn(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"), + fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ADDI4SPN_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 68); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(imm){ + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), imm)), 32, false)); + } + else { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 68); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 69: C__LW */ + continuation_e __c__lw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__LW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 69); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 32, false); + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_ext(cc, + gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 69); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 70: C__SW */ + continuation_e __c__sw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 70); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 32, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2+8), 32, false), 4); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 70); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 71: C__ADDI */ + continuation_e __c__addi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ADDI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 71); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rs1!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rs1), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int8_t)sext<6>(imm))), 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 71); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 72: C__NOP */ + continuation_e __c__nop(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "c.nop"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__NOP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 72); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 72); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 73: C__JAL */ + continuation_e __c__jal(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"), + fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__JAL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 73); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + mov(cc, get_ptr_for(jh, traits::X0+ 1), + (uint32_t)(PC+2)); + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 73); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 74: C__LI */ + continuation_e __c__li(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__LI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 74); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + (uint32_t)((int8_t)sext<6>(imm))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 74); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 75: C__LUI */ + continuation_e __c__lui(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__LUI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 75); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(imm==0||rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + (uint32_t)((int32_t)sext<18>(imm))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 75); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 76: C__ADDI16SP */ + continuation_e __c__addi16sp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"), + fmt::arg("nzimm", nzimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ADDI16SP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 76); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(nzimm){ + mov(cc, get_ptr_for(jh, traits::X0+ 2), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), (int16_t)sext<10>(nzimm))), 32, true)); + } + else { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 76); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 77: __reserved_clui */ + continuation_e ____reserved_clui(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = ".reserved_clui"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("__reserved_clui_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 77); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 77); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 78: C__SRLI */ + continuation_e __c__srli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SRLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 78); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rs1+8), + gen_operation(cc, shr, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), shamt)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 78); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 79: C__SRAI */ + continuation_e __c__srai(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SRAI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 79); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(shamt){ + mov(cc, get_ptr_for(jh, traits::X0+ rs1+8), + gen_ext(cc, + (gen_operation(cc, sar, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), 32, false)), shamt)), 32, true)); + } + else { + if(static_cast(traits::XLEN)==128){ + mov(cc, get_ptr_for(jh, traits::X0+ rs1+8), + gen_ext(cc, + (gen_operation(cc, sar, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), 32, false)), 64)), 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 79); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 80: C__ANDI */ + continuation_e __c__andi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ANDI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 80); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rs1+8), + gen_ext(cc, + (gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), (int8_t)sext<6>(imm))), 32, true)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 80); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 81: C__SUB */ + continuation_e __c__sub(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SUB_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 81); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_ext(cc, + (gen_operation(cc, sub, load_reg_from_mem_Gp(jh, traits::X0 + rd+8), load_reg_from_mem_Gp(jh, traits::X0 + rs2+8))), 32, true)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 81); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 82: C__XOR */ + continuation_e __c__xor(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__XOR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 82); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_operation(cc, bxor, load_reg_from_mem_Gp(jh, traits::X0 + rd+8), load_reg_from_mem_Gp(jh, traits::X0 + rs2+8))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 82); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 83: C__OR */ + continuation_e __c__or(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__OR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 83); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_operation(cc, bor, load_reg_from_mem_Gp(jh, traits::X0 + rd+8), load_reg_from_mem_Gp(jh, traits::X0 + rs2+8))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 83); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 84: C__AND */ + continuation_e __c__and(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__AND_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 84); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rd+8), load_reg_from_mem_Gp(jh, traits::X0 + rs2+8))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 84); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 85: C__J */ + continuation_e __c__j(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"), + fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__J_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 85); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 85); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 86: C__BEQZ */ + continuation_e __c__beqz(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__BEQZ_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 86); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, eq, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), 0); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm)); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + cc.bind(label_merge); + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 86); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 87: C__BNEZ */ + continuation_e __c__bnez(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__BNEZ_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 87); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), 0); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm)); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + cc.bind(label_merge); + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 87); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 88: C__SLLI */ + continuation_e __c__slli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t nzuimm = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SLLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 88); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rs1!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rs1), + gen_operation(cc, shl, load_reg_from_mem_Gp(jh, traits::X0 + rs1), nzuimm)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 88); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 89: C__LWSP */ + continuation_e __c__lwsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__LWSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 89); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rd==0){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 32, false); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true)); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 89); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 90: C__MV */ + continuation_e __c__mv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__MV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 90); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 90); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 91: C__JR */ + continuation_e __c__jr(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"), + fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__JR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 91); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs1&&rs1(traits::RFS)){ + auto addr_mask = (uint32_t)- 2; + auto PC_val_v = gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs1%static_cast(traits::RFS)), addr_mask); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(UNKNOWN_JUMP)); + } + else { + gen_raise(jh, 0, 2); + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 91); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 92: __reserved_cmv */ + continuation_e ____reserved_cmv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = ".reserved_cmv"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("__reserved_cmv_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 92); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_raise(jh, 0, 2); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 92); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 93: C__ADD */ + continuation_e __c__add(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ADD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 93); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rd), load_reg_from_mem_Gp(jh, traits::X0 + rs2))), 32, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 93); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 94: C__JALR */ + continuation_e __c__jalr(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"), + fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__JALR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 94); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto addr_mask = (uint32_t)- 2; + auto new_pc = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + mov(cc, get_ptr_for(jh, traits::X0+ 1), + (uint32_t)(PC+2)); + auto PC_val_v = gen_operation(cc, band, new_pc, addr_mask); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(UNKNOWN_JUMP)); + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 94); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 95: C__EBREAK */ + continuation_e __c__ebreak(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "c.ebreak"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__EBREAK_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 95); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_raise(jh, 0, 3); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 95); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 96: C__SWSP */ + continuation_e __c__swsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SWSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 96); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 32, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 96); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 97: DII */ + continuation_e __dii(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "dii"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("DII_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 97); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 97); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 98: FLW */ + continuation_e __flw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "flw"), + fmt::arg("rd", fname(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 98); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + InvokeNode* call_NaNBox32_11; + auto NaNBox32_11_arg0 = gen_read_mem(jh, traits::MEM, offs, 4); + x86::Gp ret_val_NaNBox32_11 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_11, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_11); + setArg(call_NaNBox32_11, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_11, 1, NaNBox32_11_arg0); + setRet(call_NaNBox32_11, 0, ret_val_NaNBox32_11); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 98); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 99: FSW */ + continuation_e __fsw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "fsw"), + fmt::arg("rs2", fname(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 99); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs2), 32, false), 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 99); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 100: FADD__S */ + continuation_e __fadd__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FADD__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 100); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_14; + auto unbox_s_14_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_14 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_14, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_15; + auto unbox_s_15_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_15 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_15, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_16; + x86::Gp ret_val_get_rm_16 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_16, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fadd_s_13; + auto fadd_s_13_arg0 = ret_val_unbox_s_14; + auto fadd_s_13_arg1 = ret_val_unbox_s_15; + auto fadd_s_13_arg2 = ret_val_get_rm_16; + x86::Gp ret_val_fadd_s_13 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fadd_s_13, &fadd_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_12; + auto NaNBox32_12_arg0 = ret_val_fadd_s_13; + x86::Gp ret_val_NaNBox32_12 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_12, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_12); + setArg(call_unbox_s_14, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_14, 1, unbox_s_14_arg1); + setRet(call_unbox_s_14, 0, ret_val_unbox_s_14); + setArg(call_unbox_s_15, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_15, 1, unbox_s_15_arg1); + setRet(call_unbox_s_15, 0, ret_val_unbox_s_15); + setArg(call_get_rm_16, 0, reinterpret_cast(this)); + setArg(call_get_rm_16, 1, rm); + setRet(call_get_rm_16, 0, ret_val_get_rm_16); + setArg(call_fadd_s_13, 0, fadd_s_13_arg0); + setArg(call_fadd_s_13, 1, fadd_s_13_arg1); + setArg(call_fadd_s_13, 2, fadd_s_13_arg2); + setRet(call_fadd_s_13, 0, ret_val_fadd_s_13); + setArg(call_NaNBox32_12, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_12, 1, NaNBox32_12_arg0); + setRet(call_NaNBox32_12, 0, ret_val_NaNBox32_12); + InvokeNode* call_fget_flags_17; + x86::Gp ret_val_fget_flags_17 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_17, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_17; + setRet(call_fget_flags_17, 0, ret_val_fget_flags_17); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 100); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 101: FSUB__S */ + continuation_e __fsub__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSUB__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 101); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_20; + auto unbox_s_20_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_20 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_20, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_21; + auto unbox_s_21_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_21 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_21, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_22; + x86::Gp ret_val_get_rm_22 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_22, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fsub_s_19; + auto fsub_s_19_arg0 = ret_val_unbox_s_20; + auto fsub_s_19_arg1 = ret_val_unbox_s_21; + auto fsub_s_19_arg2 = ret_val_get_rm_22; + x86::Gp ret_val_fsub_s_19 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fsub_s_19, &fsub_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_18; + auto NaNBox32_18_arg0 = ret_val_fsub_s_19; + x86::Gp ret_val_NaNBox32_18 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_18, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_18); + setArg(call_unbox_s_20, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_20, 1, unbox_s_20_arg1); + setRet(call_unbox_s_20, 0, ret_val_unbox_s_20); + setArg(call_unbox_s_21, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_21, 1, unbox_s_21_arg1); + setRet(call_unbox_s_21, 0, ret_val_unbox_s_21); + setArg(call_get_rm_22, 0, reinterpret_cast(this)); + setArg(call_get_rm_22, 1, rm); + setRet(call_get_rm_22, 0, ret_val_get_rm_22); + setArg(call_fsub_s_19, 0, fsub_s_19_arg0); + setArg(call_fsub_s_19, 1, fsub_s_19_arg1); + setArg(call_fsub_s_19, 2, fsub_s_19_arg2); + setRet(call_fsub_s_19, 0, ret_val_fsub_s_19); + setArg(call_NaNBox32_18, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_18, 1, NaNBox32_18_arg0); + setRet(call_NaNBox32_18, 0, ret_val_NaNBox32_18); + InvokeNode* call_fget_flags_23; + x86::Gp ret_val_fget_flags_23 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_23, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_23; + setRet(call_fget_flags_23, 0, ret_val_fget_flags_23); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 101); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 102: FMUL__S */ + continuation_e __fmul__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fmul.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMUL__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 102); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_26; + auto unbox_s_26_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_26 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_26, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_27; + auto unbox_s_27_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_27 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_27, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_28; + x86::Gp ret_val_get_rm_28 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_28, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmul_s_25; + auto fmul_s_25_arg0 = ret_val_unbox_s_26; + auto fmul_s_25_arg1 = ret_val_unbox_s_27; + auto fmul_s_25_arg2 = ret_val_get_rm_28; + x86::Gp ret_val_fmul_s_25 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fmul_s_25, &fmul_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_24; + auto NaNBox32_24_arg0 = ret_val_fmul_s_25; + x86::Gp ret_val_NaNBox32_24 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_24, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_24); + setArg(call_unbox_s_26, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_26, 1, unbox_s_26_arg1); + setRet(call_unbox_s_26, 0, ret_val_unbox_s_26); + setArg(call_unbox_s_27, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_27, 1, unbox_s_27_arg1); + setRet(call_unbox_s_27, 0, ret_val_unbox_s_27); + setArg(call_get_rm_28, 0, reinterpret_cast(this)); + setArg(call_get_rm_28, 1, rm); + setRet(call_get_rm_28, 0, ret_val_get_rm_28); + setArg(call_fmul_s_25, 0, fmul_s_25_arg0); + setArg(call_fmul_s_25, 1, fmul_s_25_arg1); + setArg(call_fmul_s_25, 2, fmul_s_25_arg2); + setRet(call_fmul_s_25, 0, ret_val_fmul_s_25); + setArg(call_NaNBox32_24, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_24, 1, NaNBox32_24_arg0); + setRet(call_NaNBox32_24, 0, ret_val_NaNBox32_24); + InvokeNode* call_fget_flags_29; + x86::Gp ret_val_fget_flags_29 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_29, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_29; + setRet(call_fget_flags_29, 0, ret_val_fget_flags_29); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 102); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 103: FDIV__S */ + continuation_e __fdiv__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fdiv.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FDIV__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 103); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_32; + auto unbox_s_32_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_32 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_32, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_33; + auto unbox_s_33_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_33 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_33, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_34; + x86::Gp ret_val_get_rm_34 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_34, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fdiv_s_31; + auto fdiv_s_31_arg0 = ret_val_unbox_s_32; + auto fdiv_s_31_arg1 = ret_val_unbox_s_33; + auto fdiv_s_31_arg2 = ret_val_get_rm_34; + x86::Gp ret_val_fdiv_s_31 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fdiv_s_31, &fdiv_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_30; + auto NaNBox32_30_arg0 = ret_val_fdiv_s_31; + x86::Gp ret_val_NaNBox32_30 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_30, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_30); + setArg(call_unbox_s_32, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_32, 1, unbox_s_32_arg1); + setRet(call_unbox_s_32, 0, ret_val_unbox_s_32); + setArg(call_unbox_s_33, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_33, 1, unbox_s_33_arg1); + setRet(call_unbox_s_33, 0, ret_val_unbox_s_33); + setArg(call_get_rm_34, 0, reinterpret_cast(this)); + setArg(call_get_rm_34, 1, rm); + setRet(call_get_rm_34, 0, ret_val_get_rm_34); + setArg(call_fdiv_s_31, 0, fdiv_s_31_arg0); + setArg(call_fdiv_s_31, 1, fdiv_s_31_arg1); + setArg(call_fdiv_s_31, 2, fdiv_s_31_arg2); + setRet(call_fdiv_s_31, 0, ret_val_fdiv_s_31); + setArg(call_NaNBox32_30, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_30, 1, NaNBox32_30_arg0); + setRet(call_NaNBox32_30, 0, ret_val_NaNBox32_30); + InvokeNode* call_fget_flags_35; + x86::Gp ret_val_fget_flags_35 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_35, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_35; + setRet(call_fget_flags_35, 0, ret_val_fget_flags_35); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 103); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 104: FMIN__S */ + continuation_e __fmin__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmin.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMIN__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 104); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_38; + auto unbox_s_38_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_38 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_38, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_39; + auto unbox_s_39_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_39 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_39, &unbox_s, FuncSignature::build()); + InvokeNode* call_fsel_s_37; + auto fsel_s_37_arg0 = ret_val_unbox_s_38; + auto fsel_s_37_arg1 = ret_val_unbox_s_39; + x86::Gp ret_val_fsel_s_37 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fsel_s_37, &fsel_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_36; + auto NaNBox32_36_arg0 = ret_val_fsel_s_37; + x86::Gp ret_val_NaNBox32_36 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_36, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_36); + setArg(call_unbox_s_38, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_38, 1, unbox_s_38_arg1); + setRet(call_unbox_s_38, 0, ret_val_unbox_s_38); + setArg(call_unbox_s_39, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_39, 1, unbox_s_39_arg1); + setRet(call_unbox_s_39, 0, ret_val_unbox_s_39); + setArg(call_fsel_s_37, 0, fsel_s_37_arg0); + setArg(call_fsel_s_37, 1, fsel_s_37_arg1); + setArg(call_fsel_s_37, 2, 0); + setRet(call_fsel_s_37, 0, ret_val_fsel_s_37); + setArg(call_NaNBox32_36, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_36, 1, NaNBox32_36_arg0); + setRet(call_NaNBox32_36, 0, ret_val_NaNBox32_36); + InvokeNode* call_fget_flags_40; + x86::Gp ret_val_fget_flags_40 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_40, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_40; + setRet(call_fget_flags_40, 0, ret_val_fget_flags_40); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 104); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 105: FMAX__S */ + continuation_e __fmax__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmax.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMAX__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 105); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_43; + auto unbox_s_43_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_43 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_43, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_44; + auto unbox_s_44_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_44 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_44, &unbox_s, FuncSignature::build()); + InvokeNode* call_fsel_s_42; + auto fsel_s_42_arg0 = ret_val_unbox_s_43; + auto fsel_s_42_arg1 = ret_val_unbox_s_44; + x86::Gp ret_val_fsel_s_42 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fsel_s_42, &fsel_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_41; + auto NaNBox32_41_arg0 = ret_val_fsel_s_42; + x86::Gp ret_val_NaNBox32_41 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_41, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_41); + setArg(call_unbox_s_43, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_43, 1, unbox_s_43_arg1); + setRet(call_unbox_s_43, 0, ret_val_unbox_s_43); + setArg(call_unbox_s_44, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_44, 1, unbox_s_44_arg1); + setRet(call_unbox_s_44, 0, ret_val_unbox_s_44); + setArg(call_fsel_s_42, 0, fsel_s_42_arg0); + setArg(call_fsel_s_42, 1, fsel_s_42_arg1); + setArg(call_fsel_s_42, 2, 1); + setRet(call_fsel_s_42, 0, ret_val_fsel_s_42); + setArg(call_NaNBox32_41, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_41, 1, NaNBox32_41_arg0); + setRet(call_NaNBox32_41, 0, ret_val_NaNBox32_41); + InvokeNode* call_fget_flags_45; + x86::Gp ret_val_fget_flags_45 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_45, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_45; + setRet(call_fget_flags_45, 0, ret_val_fget_flags_45); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 105); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 106: FSQRT__S */ + continuation_e __fsqrt__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fsqrt.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSQRT__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 106); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_48; + auto unbox_s_48_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_48 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_48, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_49; + x86::Gp ret_val_get_rm_49 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_49, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fsqrt_s_47; + auto fsqrt_s_47_arg0 = ret_val_unbox_s_48; + auto fsqrt_s_47_arg1 = ret_val_get_rm_49; + x86::Gp ret_val_fsqrt_s_47 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fsqrt_s_47, &fsqrt_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_46; + auto NaNBox32_46_arg0 = ret_val_fsqrt_s_47; + x86::Gp ret_val_NaNBox32_46 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_46, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_46); + setArg(call_unbox_s_48, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_48, 1, unbox_s_48_arg1); + setRet(call_unbox_s_48, 0, ret_val_unbox_s_48); + setArg(call_get_rm_49, 0, reinterpret_cast(this)); + setArg(call_get_rm_49, 1, rm); + setRet(call_get_rm_49, 0, ret_val_get_rm_49); + setArg(call_fsqrt_s_47, 0, fsqrt_s_47_arg0); + setArg(call_fsqrt_s_47, 1, fsqrt_s_47_arg1); + setRet(call_fsqrt_s_47, 0, ret_val_fsqrt_s_47); + setArg(call_NaNBox32_46, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_46, 1, NaNBox32_46_arg0); + setRet(call_NaNBox32_46, 0, ret_val_NaNBox32_46); + InvokeNode* call_fget_flags_50; + x86::Gp ret_val_fget_flags_50 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_50, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_50; + setRet(call_fget_flags_50, 0, ret_val_fget_flags_50); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 106); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 107: FMADD__S */ + continuation_e __fmadd__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMADD__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 107); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_53; + auto unbox_s_53_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_53 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_53, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_54; + auto unbox_s_54_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_54 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_54, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_55; + auto unbox_s_55_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_s_55 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_55, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_56; + x86::Gp ret_val_get_rm_56 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_56, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_s_52; + auto fmadd_s_52_arg0 = ret_val_unbox_s_53; + auto fmadd_s_52_arg1 = ret_val_unbox_s_54; + auto fmadd_s_52_arg2 = ret_val_unbox_s_55; + auto fmadd_s_52_arg4 = ret_val_get_rm_56; + x86::Gp ret_val_fmadd_s_52 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fmadd_s_52, &fmadd_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_51; + auto NaNBox32_51_arg0 = ret_val_fmadd_s_52; + x86::Gp ret_val_NaNBox32_51 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_51, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_51); + setArg(call_unbox_s_53, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_53, 1, unbox_s_53_arg1); + setRet(call_unbox_s_53, 0, ret_val_unbox_s_53); + setArg(call_unbox_s_54, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_54, 1, unbox_s_54_arg1); + setRet(call_unbox_s_54, 0, ret_val_unbox_s_54); + setArg(call_unbox_s_55, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_55, 1, unbox_s_55_arg1); + setRet(call_unbox_s_55, 0, ret_val_unbox_s_55); + setArg(call_get_rm_56, 0, reinterpret_cast(this)); + setArg(call_get_rm_56, 1, rm); + setRet(call_get_rm_56, 0, ret_val_get_rm_56); + setArg(call_fmadd_s_52, 0, fmadd_s_52_arg0); + setArg(call_fmadd_s_52, 1, fmadd_s_52_arg1); + setArg(call_fmadd_s_52, 2, fmadd_s_52_arg2); + setArg(call_fmadd_s_52, 3, 0); + setArg(call_fmadd_s_52, 4, fmadd_s_52_arg4); + setRet(call_fmadd_s_52, 0, ret_val_fmadd_s_52); + setArg(call_NaNBox32_51, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_51, 1, NaNBox32_51_arg0); + setRet(call_NaNBox32_51, 0, ret_val_NaNBox32_51); + InvokeNode* call_fget_flags_57; + x86::Gp ret_val_fget_flags_57 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_57, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_57; + setRet(call_fget_flags_57, 0, ret_val_fget_flags_57); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 107); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 108: FMSUB__S */ + continuation_e __fmsub__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMSUB__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 108); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_60; + auto unbox_s_60_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_60 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_60, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_61; + auto unbox_s_61_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_61 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_61, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_62; + auto unbox_s_62_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_s_62 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_62, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_63; + x86::Gp ret_val_get_rm_63 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_63, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_s_59; + auto fmadd_s_59_arg0 = ret_val_unbox_s_60; + auto fmadd_s_59_arg1 = ret_val_unbox_s_61; + auto fmadd_s_59_arg2 = ret_val_unbox_s_62; + auto fmadd_s_59_arg4 = ret_val_get_rm_63; + x86::Gp ret_val_fmadd_s_59 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fmadd_s_59, &fmadd_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_58; + auto NaNBox32_58_arg0 = ret_val_fmadd_s_59; + x86::Gp ret_val_NaNBox32_58 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_58, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_58); + setArg(call_unbox_s_60, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_60, 1, unbox_s_60_arg1); + setRet(call_unbox_s_60, 0, ret_val_unbox_s_60); + setArg(call_unbox_s_61, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_61, 1, unbox_s_61_arg1); + setRet(call_unbox_s_61, 0, ret_val_unbox_s_61); + setArg(call_unbox_s_62, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_62, 1, unbox_s_62_arg1); + setRet(call_unbox_s_62, 0, ret_val_unbox_s_62); + setArg(call_get_rm_63, 0, reinterpret_cast(this)); + setArg(call_get_rm_63, 1, rm); + setRet(call_get_rm_63, 0, ret_val_get_rm_63); + setArg(call_fmadd_s_59, 0, fmadd_s_59_arg0); + setArg(call_fmadd_s_59, 1, fmadd_s_59_arg1); + setArg(call_fmadd_s_59, 2, fmadd_s_59_arg2); + setArg(call_fmadd_s_59, 3, 1); + setArg(call_fmadd_s_59, 4, fmadd_s_59_arg4); + setRet(call_fmadd_s_59, 0, ret_val_fmadd_s_59); + setArg(call_NaNBox32_58, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_58, 1, NaNBox32_58_arg0); + setRet(call_NaNBox32_58, 0, ret_val_NaNBox32_58); + InvokeNode* call_fget_flags_64; + x86::Gp ret_val_fget_flags_64 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_64, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_64; + setRet(call_fget_flags_64, 0, ret_val_fget_flags_64); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 108); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 109: FNMADD__S */ + continuation_e __fnmadd__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FNMADD__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 109); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_67; + auto unbox_s_67_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_67 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_67, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_68; + auto unbox_s_68_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_68 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_68, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_69; + auto unbox_s_69_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_s_69 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_69, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_70; + x86::Gp ret_val_get_rm_70 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_70, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_s_66; + auto fmadd_s_66_arg0 = ret_val_unbox_s_67; + auto fmadd_s_66_arg1 = ret_val_unbox_s_68; + auto fmadd_s_66_arg2 = ret_val_unbox_s_69; + auto fmadd_s_66_arg4 = ret_val_get_rm_70; + x86::Gp ret_val_fmadd_s_66 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fmadd_s_66, &fmadd_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_65; + auto NaNBox32_65_arg0 = ret_val_fmadd_s_66; + x86::Gp ret_val_NaNBox32_65 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_65, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_65); + setArg(call_unbox_s_67, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_67, 1, unbox_s_67_arg1); + setRet(call_unbox_s_67, 0, ret_val_unbox_s_67); + setArg(call_unbox_s_68, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_68, 1, unbox_s_68_arg1); + setRet(call_unbox_s_68, 0, ret_val_unbox_s_68); + setArg(call_unbox_s_69, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_69, 1, unbox_s_69_arg1); + setRet(call_unbox_s_69, 0, ret_val_unbox_s_69); + setArg(call_get_rm_70, 0, reinterpret_cast(this)); + setArg(call_get_rm_70, 1, rm); + setRet(call_get_rm_70, 0, ret_val_get_rm_70); + setArg(call_fmadd_s_66, 0, fmadd_s_66_arg0); + setArg(call_fmadd_s_66, 1, fmadd_s_66_arg1); + setArg(call_fmadd_s_66, 2, fmadd_s_66_arg2); + setArg(call_fmadd_s_66, 3, 2); + setArg(call_fmadd_s_66, 4, fmadd_s_66_arg4); + setRet(call_fmadd_s_66, 0, ret_val_fmadd_s_66); + setArg(call_NaNBox32_65, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_65, 1, NaNBox32_65_arg0); + setRet(call_NaNBox32_65, 0, ret_val_NaNBox32_65); + InvokeNode* call_fget_flags_71; + x86::Gp ret_val_fget_flags_71 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_71, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_71; + setRet(call_fget_flags_71, 0, ret_val_fget_flags_71); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 109); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 110: FNMSUB__S */ + continuation_e __fnmsub__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FNMSUB__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 110); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_74; + auto unbox_s_74_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_74 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_74, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_75; + auto unbox_s_75_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_75 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_75, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_76; + auto unbox_s_76_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_s_76 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_76, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_77; + x86::Gp ret_val_get_rm_77 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_77, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_s_73; + auto fmadd_s_73_arg0 = ret_val_unbox_s_74; + auto fmadd_s_73_arg1 = ret_val_unbox_s_75; + auto fmadd_s_73_arg2 = ret_val_unbox_s_76; + auto fmadd_s_73_arg4 = ret_val_get_rm_77; + x86::Gp ret_val_fmadd_s_73 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fmadd_s_73, &fmadd_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_72; + auto NaNBox32_72_arg0 = ret_val_fmadd_s_73; + x86::Gp ret_val_NaNBox32_72 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_72, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_72); + setArg(call_unbox_s_74, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_74, 1, unbox_s_74_arg1); + setRet(call_unbox_s_74, 0, ret_val_unbox_s_74); + setArg(call_unbox_s_75, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_75, 1, unbox_s_75_arg1); + setRet(call_unbox_s_75, 0, ret_val_unbox_s_75); + setArg(call_unbox_s_76, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_76, 1, unbox_s_76_arg1); + setRet(call_unbox_s_76, 0, ret_val_unbox_s_76); + setArg(call_get_rm_77, 0, reinterpret_cast(this)); + setArg(call_get_rm_77, 1, rm); + setRet(call_get_rm_77, 0, ret_val_get_rm_77); + setArg(call_fmadd_s_73, 0, fmadd_s_73_arg0); + setArg(call_fmadd_s_73, 1, fmadd_s_73_arg1); + setArg(call_fmadd_s_73, 2, fmadd_s_73_arg2); + setArg(call_fmadd_s_73, 3, 3); + setArg(call_fmadd_s_73, 4, fmadd_s_73_arg4); + setRet(call_fmadd_s_73, 0, ret_val_fmadd_s_73); + setArg(call_NaNBox32_72, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_72, 1, NaNBox32_72_arg0); + setRet(call_NaNBox32_72, 0, ret_val_NaNBox32_72); + InvokeNode* call_fget_flags_78; + x86::Gp ret_val_fget_flags_78 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_78, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_78; + setRet(call_fget_flags_78, 0, ret_val_fget_flags_78); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 110); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 111: FCVT__W__S */ + continuation_e __fcvt__w__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.w.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__W__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 111); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_80; + auto unbox_s_80_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_80 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_80, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_81; + x86::Gp ret_val_get_rm_81 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_81, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f32toi32_79; + auto f32toi32_79_arg0 = ret_val_unbox_s_80; + auto f32toi32_79_arg1 = ret_val_get_rm_81; + x86::Gp ret_val_f32toi32_79 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_f32toi32_79, &f32toi32, FuncSignature::build()); + auto res = gen_ext(cc, + gen_ext(cc, + ret_val_f32toi32_79, 32, false), 32, true); + setArg(call_unbox_s_80, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_80, 1, unbox_s_80_arg1); + setRet(call_unbox_s_80, 0, ret_val_unbox_s_80); + setArg(call_get_rm_81, 0, reinterpret_cast(this)); + setArg(call_get_rm_81, 1, rm); + setRet(call_get_rm_81, 0, ret_val_get_rm_81); + setArg(call_f32toi32_79, 0, f32toi32_79_arg0); + setArg(call_f32toi32_79, 1, f32toi32_79_arg1); + setRet(call_f32toi32_79, 0, ret_val_f32toi32_79); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, true)); + } + InvokeNode* call_fget_flags_82; + x86::Gp ret_val_fget_flags_82 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_82, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_82; + setRet(call_fget_flags_82, 0, ret_val_fget_flags_82); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 111); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 112: FCVT__WU__S */ + continuation_e __fcvt__wu__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.wu.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__WU__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 112); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_84; + auto unbox_s_84_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_84 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_84, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_85; + x86::Gp ret_val_get_rm_85 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_85, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f32toui32_83; + auto f32toui32_83_arg0 = ret_val_unbox_s_84; + auto f32toui32_83_arg1 = ret_val_get_rm_85; + x86::Gp ret_val_f32toui32_83 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_f32toui32_83, &f32toui32, FuncSignature::build()); + auto res = gen_ext(cc, + gen_ext(cc, + ret_val_f32toui32_83, 32, false), 32, true); + setArg(call_unbox_s_84, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_84, 1, unbox_s_84_arg1); + setRet(call_unbox_s_84, 0, ret_val_unbox_s_84); + setArg(call_get_rm_85, 0, reinterpret_cast(this)); + setArg(call_get_rm_85, 1, rm); + setRet(call_get_rm_85, 0, ret_val_get_rm_85); + setArg(call_f32toui32_83, 0, f32toui32_83_arg0); + setArg(call_f32toui32_83, 1, f32toui32_83_arg1); + setRet(call_f32toui32_83, 0, ret_val_f32toui32_83); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, true)); + } + InvokeNode* call_fget_flags_86; + x86::Gp ret_val_fget_flags_86 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_86, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_86; + setRet(call_fget_flags_86, 0, ret_val_fget_flags_86); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 112); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 113: FCVT__S__W */ + continuation_e __fcvt__s__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.w"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__S__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 113); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_89; + x86::Gp ret_val_get_rm_89 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_89, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_i32tof32_88; + auto i32tof32_88_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto i32tof32_88_arg1 = ret_val_get_rm_89; + x86::Gp ret_val_i32tof32_88 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_i32tof32_88, &i32tof32, FuncSignature::build()); + InvokeNode* call_NaNBox32_87; + auto NaNBox32_87_arg0 = ret_val_i32tof32_88; + x86::Gp ret_val_NaNBox32_87 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_87, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_87); + setArg(call_get_rm_89, 0, reinterpret_cast(this)); + setArg(call_get_rm_89, 1, rm); + setRet(call_get_rm_89, 0, ret_val_get_rm_89); + setArg(call_i32tof32_88, 0, i32tof32_88_arg0); + setArg(call_i32tof32_88, 1, i32tof32_88_arg1); + setRet(call_i32tof32_88, 0, ret_val_i32tof32_88); + setArg(call_NaNBox32_87, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_87, 1, NaNBox32_87_arg0); + setRet(call_NaNBox32_87, 0, ret_val_NaNBox32_87); + InvokeNode* call_fget_flags_90; + x86::Gp ret_val_fget_flags_90 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_90, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_90; + setRet(call_fget_flags_90, 0, ret_val_fget_flags_90); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 113); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 114: FCVT__S__WU */ + continuation_e __fcvt__s__wu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.wu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__S__WU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 114); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_93; + x86::Gp ret_val_get_rm_93 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_93, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_ui32tof32_92; + auto ui32tof32_92_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto ui32tof32_92_arg1 = ret_val_get_rm_93; + x86::Gp ret_val_ui32tof32_92 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_ui32tof32_92, &ui32tof32, FuncSignature::build()); + InvokeNode* call_NaNBox32_91; + auto NaNBox32_91_arg0 = ret_val_ui32tof32_92; + x86::Gp ret_val_NaNBox32_91 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_91, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_91); + setArg(call_get_rm_93, 0, reinterpret_cast(this)); + setArg(call_get_rm_93, 1, rm); + setRet(call_get_rm_93, 0, ret_val_get_rm_93); + setArg(call_ui32tof32_92, 0, ui32tof32_92_arg0); + setArg(call_ui32tof32_92, 1, ui32tof32_92_arg1); + setRet(call_ui32tof32_92, 0, ret_val_ui32tof32_92); + setArg(call_NaNBox32_91, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_91, 1, NaNBox32_91_arg0); + setRet(call_NaNBox32_91, 0, ret_val_NaNBox32_91); + InvokeNode* call_fget_flags_94; + x86::Gp ret_val_fget_flags_94 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_94, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_94; + setRet(call_fget_flags_94, 0, ret_val_fget_flags_94); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 114); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 115: FSGNJ__S */ + continuation_e __fsgnj__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnj.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJ__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 115); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_96; + auto unbox_s_96_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_96 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_96, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_97; + auto unbox_s_97_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_97 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_97, &unbox_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_95; + auto NaNBox32_95_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_s_96, 31, 31-31+1), 32, false), 31), gen_ext(cc, gen_slice(cc, ret_val_unbox_s_97, 0, 30-0+1), 32, false)); + x86::Gp ret_val_NaNBox32_95 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_95, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_95); + setArg(call_unbox_s_96, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_96, 1, unbox_s_96_arg1); + setRet(call_unbox_s_96, 0, ret_val_unbox_s_96); + setArg(call_unbox_s_97, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_97, 1, unbox_s_97_arg1); + setRet(call_unbox_s_97, 0, ret_val_unbox_s_97); + setArg(call_NaNBox32_95, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_95, 1, NaNBox32_95_arg0); + setRet(call_NaNBox32_95, 0, ret_val_NaNBox32_95); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 115); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 116: FSGNJN__S */ + continuation_e __fsgnjn__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjn.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJN__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 116); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_99; + auto unbox_s_99_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_99 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_99, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_100; + auto unbox_s_100_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_100 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_100, &unbox_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_98; + auto NaNBox32_98_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_s_99, 31, 31-31+1)), 32, false), 31), gen_ext(cc, gen_slice(cc, ret_val_unbox_s_100, 0, 30-0+1), 32, false)); + x86::Gp ret_val_NaNBox32_98 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_98, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_98); + setArg(call_unbox_s_99, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_99, 1, unbox_s_99_arg1); + setRet(call_unbox_s_99, 0, ret_val_unbox_s_99); + setArg(call_unbox_s_100, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_100, 1, unbox_s_100_arg1); + setRet(call_unbox_s_100, 0, ret_val_unbox_s_100); + setArg(call_NaNBox32_98, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_98, 1, NaNBox32_98_arg0); + setRet(call_NaNBox32_98, 0, ret_val_NaNBox32_98); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 116); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 117: FSGNJX__S */ + continuation_e __fsgnjx__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjx.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJX__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 117); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_102; + auto unbox_s_102_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_102 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_102, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_103; + auto unbox_s_103_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_103 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_103, &unbox_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_101; + auto NaNBox32_101_arg0 = gen_operation(cc, bxor, (gen_operation(cc, band, ret_val_unbox_s_102, ((uint32_t)1<<31))), ret_val_unbox_s_103); + x86::Gp ret_val_NaNBox32_101 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_101, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_101); + setArg(call_unbox_s_102, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_102, 1, unbox_s_102_arg1); + setRet(call_unbox_s_102, 0, ret_val_unbox_s_102); + setArg(call_unbox_s_103, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_103, 1, unbox_s_103_arg1); + setRet(call_unbox_s_103, 0, ret_val_unbox_s_103); + setArg(call_NaNBox32_101, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_101, 1, NaNBox32_101_arg0); + setRet(call_NaNBox32_101, 0, ret_val_NaNBox32_101); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 117); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 118: FMV__X__W */ + continuation_e __fmv__x__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.x.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMV__X__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 118); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false), 32, true), 32, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 118); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 119: FMV__W__X */ + continuation_e __fmv__w__x(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.w.x"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMV__W__X_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 119); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_NaNBox32_104; + auto NaNBox32_104_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + x86::Gp ret_val_NaNBox32_104 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_104, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_104); + setArg(call_NaNBox32_104, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_104, 1, NaNBox32_104_arg0); + setRet(call_NaNBox32_104, 0, ret_val_NaNBox32_104); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 119); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 120: FEQ__S */ + continuation_e __feq__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "feq.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FEQ__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 120); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_106; + auto unbox_s_106_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_106 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_106, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_107; + auto unbox_s_107_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_107 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_107, &unbox_s, FuncSignature::build()); + InvokeNode* call_fcmp_s_105; + auto fcmp_s_105_arg0 = ret_val_unbox_s_106; + auto fcmp_s_105_arg1 = ret_val_unbox_s_107; + x86::Gp ret_val_fcmp_s_105 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fcmp_s_105, &fcmp_s, FuncSignature::build()); + auto res = ret_val_fcmp_s_105; + setArg(call_unbox_s_106, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_106, 1, unbox_s_106_arg1); + setRet(call_unbox_s_106, 0, ret_val_unbox_s_106); + setArg(call_unbox_s_107, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_107, 1, unbox_s_107_arg1); + setRet(call_unbox_s_107, 0, ret_val_unbox_s_107); + setArg(call_fcmp_s_105, 0, fcmp_s_105_arg0); + setArg(call_fcmp_s_105, 1, fcmp_s_105_arg1); + setArg(call_fcmp_s_105, 2, 0); + setRet(call_fcmp_s_105, 0, ret_val_fcmp_s_105); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + res); + } + InvokeNode* call_fget_flags_108; + x86::Gp ret_val_fget_flags_108 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_108, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_108; + setRet(call_fget_flags_108, 0, ret_val_fget_flags_108); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 120); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 121: FLT__S */ + continuation_e __flt__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "flt.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLT__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 121); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_110; + auto unbox_s_110_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_110 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_110, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_111; + auto unbox_s_111_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_111 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_111, &unbox_s, FuncSignature::build()); + InvokeNode* call_fcmp_s_109; + auto fcmp_s_109_arg0 = ret_val_unbox_s_110; + auto fcmp_s_109_arg1 = ret_val_unbox_s_111; + x86::Gp ret_val_fcmp_s_109 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fcmp_s_109, &fcmp_s, FuncSignature::build()); + auto res = ret_val_fcmp_s_109; + setArg(call_unbox_s_110, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_110, 1, unbox_s_110_arg1); + setRet(call_unbox_s_110, 0, ret_val_unbox_s_110); + setArg(call_unbox_s_111, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_111, 1, unbox_s_111_arg1); + setRet(call_unbox_s_111, 0, ret_val_unbox_s_111); + setArg(call_fcmp_s_109, 0, fcmp_s_109_arg0); + setArg(call_fcmp_s_109, 1, fcmp_s_109_arg1); + setArg(call_fcmp_s_109, 2, 2); + setRet(call_fcmp_s_109, 0, ret_val_fcmp_s_109); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + res); + } + InvokeNode* call_fget_flags_112; + x86::Gp ret_val_fget_flags_112 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_112, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_112; + setRet(call_fget_flags_112, 0, ret_val_fget_flags_112); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 121); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 122: FLE__S */ + continuation_e __fle__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fle.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLE__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 122); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_114; + auto unbox_s_114_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_114 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_114, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_115; + auto unbox_s_115_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_115 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_115, &unbox_s, FuncSignature::build()); + InvokeNode* call_fcmp_s_113; + auto fcmp_s_113_arg0 = ret_val_unbox_s_114; + auto fcmp_s_113_arg1 = ret_val_unbox_s_115; + x86::Gp ret_val_fcmp_s_113 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fcmp_s_113, &fcmp_s, FuncSignature::build()); + auto res = ret_val_fcmp_s_113; + setArg(call_unbox_s_114, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_114, 1, unbox_s_114_arg1); + setRet(call_unbox_s_114, 0, ret_val_unbox_s_114); + setArg(call_unbox_s_115, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_115, 1, unbox_s_115_arg1); + setRet(call_unbox_s_115, 0, ret_val_unbox_s_115); + setArg(call_fcmp_s_113, 0, fcmp_s_113_arg0); + setArg(call_fcmp_s_113, 1, fcmp_s_113_arg1); + setArg(call_fcmp_s_113, 2, 1); + setRet(call_fcmp_s_113, 0, ret_val_fcmp_s_113); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + res); + } + InvokeNode* call_fget_flags_116; + x86::Gp ret_val_fget_flags_116 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_116, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_116; + setRet(call_fget_flags_116, 0, ret_val_fget_flags_116); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 122); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 123: FCLASS__S */ + continuation_e __fclass__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fclass.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCLASS__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 123); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_118; + auto unbox_s_118_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_118 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_118, &unbox_s, FuncSignature::build()); + InvokeNode* call_fclass_s_117; + auto fclass_s_117_arg0 = ret_val_unbox_s_118; + x86::Gp ret_val_fclass_s_117 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fclass_s_117, &fclass_s, FuncSignature::build()); + auto res = ret_val_fclass_s_117; + setArg(call_unbox_s_118, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_118, 1, unbox_s_118_arg1); + setRet(call_unbox_s_118, 0, ret_val_unbox_s_118); + setArg(call_fclass_s_117, 0, fclass_s_117_arg0); + setRet(call_fclass_s_117, 0, ret_val_fclass_s_117); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + res); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 123); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 124: C__FLW */ + continuation_e __c__flw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rd}), {uimm}({rs1})", fmt::arg("mnemonic", "c.flw"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FLW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 124); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 32, false); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false); + InvokeNode* call_NaNBox32_119; + auto NaNBox32_119_arg0 = res; + x86::Gp ret_val_NaNBox32_119 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_119, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd+8), + ret_val_NaNBox32_119); + setArg(call_NaNBox32_119, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_119, 1, NaNBox32_119_arg0); + setRet(call_NaNBox32_119, 0, ret_val_NaNBox32_119); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 124); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 125: C__FSW */ + continuation_e __c__fsw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rs2}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fsw"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FSW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 125); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 32, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs2+8), 32, false), 4); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 125); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 126: C__FLWSP */ + continuation_e __c__flwsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f {rd}, {uimm}(x2)", fmt::arg("mnemonic", "c.flwsp"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FLWSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 126); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 32, false); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false); + InvokeNode* call_NaNBox32_120; + auto NaNBox32_120_arg0 = res; + x86::Gp ret_val_NaNBox32_120 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_120, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_120); + setArg(call_NaNBox32_120, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_120, 1, NaNBox32_120_arg0); + setRet(call_NaNBox32_120, 0, ret_val_NaNBox32_120); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 126); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 127: C__FSWSP */ + continuation_e __c__fswsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f {rs2}, {uimm}(x2), ", fmt::arg("mnemonic", "c.fswsp"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FSWSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 127); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 32, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs2), 32, false), 4); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 127); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 128: FLD */ + continuation_e __fld(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "fld"), + fmt::arg("rd", fname(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 128); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + InvokeNode* call_NaNBox64_121; + auto NaNBox64_121_arg0 = gen_read_mem(jh, traits::MEM, offs, 8); + x86::Gp ret_val_NaNBox64_121 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_121, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_121); + setArg(call_NaNBox64_121, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_121, 1, NaNBox64_121_arg0); + setRet(call_NaNBox64_121, 0, ret_val_NaNBox64_121); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 128); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 129: FSD */ + continuation_e __fsd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "fsd"), + fmt::arg("rs2", fname(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 129); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs2), 64, false), 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 129); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 130: FADD__D */ + continuation_e __fadd__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FADD__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 130); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_124; + auto unbox_d_124_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_124 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_124, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_125; + auto unbox_d_125_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_125 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_125, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_126; + x86::Gp ret_val_get_rm_126 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_126, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fadd_d_123; + auto fadd_d_123_arg0 = ret_val_unbox_d_124; + auto fadd_d_123_arg1 = ret_val_unbox_d_125; + auto fadd_d_123_arg2 = ret_val_get_rm_126; + x86::Gp ret_val_fadd_d_123 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fadd_d_123, &fadd_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_122; + auto NaNBox64_122_arg0 = ret_val_fadd_d_123; + x86::Gp ret_val_NaNBox64_122 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_122, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_122); + setArg(call_unbox_d_124, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_124, 1, unbox_d_124_arg1); + setRet(call_unbox_d_124, 0, ret_val_unbox_d_124); + setArg(call_unbox_d_125, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_125, 1, unbox_d_125_arg1); + setRet(call_unbox_d_125, 0, ret_val_unbox_d_125); + setArg(call_get_rm_126, 0, reinterpret_cast(this)); + setArg(call_get_rm_126, 1, rm); + setRet(call_get_rm_126, 0, ret_val_get_rm_126); + setArg(call_fadd_d_123, 0, fadd_d_123_arg0); + setArg(call_fadd_d_123, 1, fadd_d_123_arg1); + setArg(call_fadd_d_123, 2, fadd_d_123_arg2); + setRet(call_fadd_d_123, 0, ret_val_fadd_d_123); + setArg(call_NaNBox64_122, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_122, 1, NaNBox64_122_arg0); + setRet(call_NaNBox64_122, 0, ret_val_NaNBox64_122); + InvokeNode* call_fget_flags_127; + x86::Gp ret_val_fget_flags_127 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_127, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_127; + setRet(call_fget_flags_127, 0, ret_val_fget_flags_127); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 130); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 131: FSUB__D */ + continuation_e __fsub__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSUB__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 131); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_130; + auto unbox_d_130_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_130 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_130, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_131; + auto unbox_d_131_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_131 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_131, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_132; + x86::Gp ret_val_get_rm_132 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_132, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fsub_d_129; + auto fsub_d_129_arg0 = ret_val_unbox_d_130; + auto fsub_d_129_arg1 = ret_val_unbox_d_131; + auto fsub_d_129_arg2 = ret_val_get_rm_132; + x86::Gp ret_val_fsub_d_129 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fsub_d_129, &fsub_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_128; + auto NaNBox64_128_arg0 = ret_val_fsub_d_129; + x86::Gp ret_val_NaNBox64_128 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_128, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_128); + setArg(call_unbox_d_130, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_130, 1, unbox_d_130_arg1); + setRet(call_unbox_d_130, 0, ret_val_unbox_d_130); + setArg(call_unbox_d_131, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_131, 1, unbox_d_131_arg1); + setRet(call_unbox_d_131, 0, ret_val_unbox_d_131); + setArg(call_get_rm_132, 0, reinterpret_cast(this)); + setArg(call_get_rm_132, 1, rm); + setRet(call_get_rm_132, 0, ret_val_get_rm_132); + setArg(call_fsub_d_129, 0, fsub_d_129_arg0); + setArg(call_fsub_d_129, 1, fsub_d_129_arg1); + setArg(call_fsub_d_129, 2, fsub_d_129_arg2); + setRet(call_fsub_d_129, 0, ret_val_fsub_d_129); + setArg(call_NaNBox64_128, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_128, 1, NaNBox64_128_arg0); + setRet(call_NaNBox64_128, 0, ret_val_NaNBox64_128); + InvokeNode* call_fget_flags_133; + x86::Gp ret_val_fget_flags_133 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_133, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_133; + setRet(call_fget_flags_133, 0, ret_val_fget_flags_133); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 131); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 132: FMUL__D */ + continuation_e __fmul__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fmul.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMUL__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 132); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_136; + auto unbox_d_136_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_136 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_136, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_137; + auto unbox_d_137_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_137 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_137, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_138; + x86::Gp ret_val_get_rm_138 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_138, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmul_d_135; + auto fmul_d_135_arg0 = ret_val_unbox_d_136; + auto fmul_d_135_arg1 = ret_val_unbox_d_137; + auto fmul_d_135_arg2 = ret_val_get_rm_138; + x86::Gp ret_val_fmul_d_135 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fmul_d_135, &fmul_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_134; + auto NaNBox64_134_arg0 = ret_val_fmul_d_135; + x86::Gp ret_val_NaNBox64_134 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_134, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_134); + setArg(call_unbox_d_136, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_136, 1, unbox_d_136_arg1); + setRet(call_unbox_d_136, 0, ret_val_unbox_d_136); + setArg(call_unbox_d_137, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_137, 1, unbox_d_137_arg1); + setRet(call_unbox_d_137, 0, ret_val_unbox_d_137); + setArg(call_get_rm_138, 0, reinterpret_cast(this)); + setArg(call_get_rm_138, 1, rm); + setRet(call_get_rm_138, 0, ret_val_get_rm_138); + setArg(call_fmul_d_135, 0, fmul_d_135_arg0); + setArg(call_fmul_d_135, 1, fmul_d_135_arg1); + setArg(call_fmul_d_135, 2, fmul_d_135_arg2); + setRet(call_fmul_d_135, 0, ret_val_fmul_d_135); + setArg(call_NaNBox64_134, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_134, 1, NaNBox64_134_arg0); + setRet(call_NaNBox64_134, 0, ret_val_NaNBox64_134); + InvokeNode* call_fget_flags_139; + x86::Gp ret_val_fget_flags_139 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_139, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_139; + setRet(call_fget_flags_139, 0, ret_val_fget_flags_139); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 132); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 133: FDIV__D */ + continuation_e __fdiv__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fdiv.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FDIV__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 133); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_142; + auto unbox_d_142_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_142 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_142, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_143; + auto unbox_d_143_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_143 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_143, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_144; + x86::Gp ret_val_get_rm_144 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_144, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fdiv_d_141; + auto fdiv_d_141_arg0 = ret_val_unbox_d_142; + auto fdiv_d_141_arg1 = ret_val_unbox_d_143; + auto fdiv_d_141_arg2 = ret_val_get_rm_144; + x86::Gp ret_val_fdiv_d_141 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fdiv_d_141, &fdiv_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_140; + auto NaNBox64_140_arg0 = ret_val_fdiv_d_141; + x86::Gp ret_val_NaNBox64_140 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_140, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_140); + setArg(call_unbox_d_142, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_142, 1, unbox_d_142_arg1); + setRet(call_unbox_d_142, 0, ret_val_unbox_d_142); + setArg(call_unbox_d_143, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_143, 1, unbox_d_143_arg1); + setRet(call_unbox_d_143, 0, ret_val_unbox_d_143); + setArg(call_get_rm_144, 0, reinterpret_cast(this)); + setArg(call_get_rm_144, 1, rm); + setRet(call_get_rm_144, 0, ret_val_get_rm_144); + setArg(call_fdiv_d_141, 0, fdiv_d_141_arg0); + setArg(call_fdiv_d_141, 1, fdiv_d_141_arg1); + setArg(call_fdiv_d_141, 2, fdiv_d_141_arg2); + setRet(call_fdiv_d_141, 0, ret_val_fdiv_d_141); + setArg(call_NaNBox64_140, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_140, 1, NaNBox64_140_arg0); + setRet(call_NaNBox64_140, 0, ret_val_NaNBox64_140); + InvokeNode* call_fget_flags_145; + x86::Gp ret_val_fget_flags_145 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_145, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_145; + setRet(call_fget_flags_145, 0, ret_val_fget_flags_145); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 133); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 134: FMIN__D */ + continuation_e __fmin__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmin.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMIN__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 134); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_148; + auto unbox_d_148_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_148 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_148, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_149; + auto unbox_d_149_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_149 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_149, &unbox_d, FuncSignature::build()); + InvokeNode* call_fsel_d_147; + auto fsel_d_147_arg0 = ret_val_unbox_d_148; + auto fsel_d_147_arg1 = ret_val_unbox_d_149; + x86::Gp ret_val_fsel_d_147 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fsel_d_147, &fsel_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_146; + auto NaNBox64_146_arg0 = ret_val_fsel_d_147; + x86::Gp ret_val_NaNBox64_146 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_146, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_146); + setArg(call_unbox_d_148, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_148, 1, unbox_d_148_arg1); + setRet(call_unbox_d_148, 0, ret_val_unbox_d_148); + setArg(call_unbox_d_149, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_149, 1, unbox_d_149_arg1); + setRet(call_unbox_d_149, 0, ret_val_unbox_d_149); + setArg(call_fsel_d_147, 0, fsel_d_147_arg0); + setArg(call_fsel_d_147, 1, fsel_d_147_arg1); + setArg(call_fsel_d_147, 2, 0); + setRet(call_fsel_d_147, 0, ret_val_fsel_d_147); + setArg(call_NaNBox64_146, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_146, 1, NaNBox64_146_arg0); + setRet(call_NaNBox64_146, 0, ret_val_NaNBox64_146); + InvokeNode* call_fget_flags_150; + x86::Gp ret_val_fget_flags_150 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_150, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_150; + setRet(call_fget_flags_150, 0, ret_val_fget_flags_150); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 134); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 135: FMAX__D */ + continuation_e __fmax__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmax.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMAX__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 135); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_153; + auto unbox_d_153_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_153 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_153, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_154; + auto unbox_d_154_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_154 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_154, &unbox_d, FuncSignature::build()); + InvokeNode* call_fsel_d_152; + auto fsel_d_152_arg0 = ret_val_unbox_d_153; + auto fsel_d_152_arg1 = ret_val_unbox_d_154; + x86::Gp ret_val_fsel_d_152 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fsel_d_152, &fsel_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_151; + auto NaNBox64_151_arg0 = ret_val_fsel_d_152; + x86::Gp ret_val_NaNBox64_151 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_151, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_151); + setArg(call_unbox_d_153, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_153, 1, unbox_d_153_arg1); + setRet(call_unbox_d_153, 0, ret_val_unbox_d_153); + setArg(call_unbox_d_154, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_154, 1, unbox_d_154_arg1); + setRet(call_unbox_d_154, 0, ret_val_unbox_d_154); + setArg(call_fsel_d_152, 0, fsel_d_152_arg0); + setArg(call_fsel_d_152, 1, fsel_d_152_arg1); + setArg(call_fsel_d_152, 2, 1); + setRet(call_fsel_d_152, 0, ret_val_fsel_d_152); + setArg(call_NaNBox64_151, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_151, 1, NaNBox64_151_arg0); + setRet(call_NaNBox64_151, 0, ret_val_NaNBox64_151); + InvokeNode* call_fget_flags_155; + x86::Gp ret_val_fget_flags_155 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_155, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_155; + setRet(call_fget_flags_155, 0, ret_val_fget_flags_155); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 135); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 136: FSQRT__D */ + continuation_e __fsqrt__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fsqrt.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSQRT__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 136); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_158; + auto unbox_d_158_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_158 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_158, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_159; + x86::Gp ret_val_get_rm_159 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_159, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fsqrt_d_157; + auto fsqrt_d_157_arg0 = ret_val_unbox_d_158; + auto fsqrt_d_157_arg1 = ret_val_get_rm_159; + x86::Gp ret_val_fsqrt_d_157 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fsqrt_d_157, &fsqrt_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_156; + auto NaNBox64_156_arg0 = ret_val_fsqrt_d_157; + x86::Gp ret_val_NaNBox64_156 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_156, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_156); + setArg(call_unbox_d_158, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_158, 1, unbox_d_158_arg1); + setRet(call_unbox_d_158, 0, ret_val_unbox_d_158); + setArg(call_get_rm_159, 0, reinterpret_cast(this)); + setArg(call_get_rm_159, 1, rm); + setRet(call_get_rm_159, 0, ret_val_get_rm_159); + setArg(call_fsqrt_d_157, 0, fsqrt_d_157_arg0); + setArg(call_fsqrt_d_157, 1, fsqrt_d_157_arg1); + setRet(call_fsqrt_d_157, 0, ret_val_fsqrt_d_157); + setArg(call_NaNBox64_156, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_156, 1, NaNBox64_156_arg0); + setRet(call_NaNBox64_156, 0, ret_val_NaNBox64_156); + InvokeNode* call_fget_flags_160; + x86::Gp ret_val_fget_flags_160 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_160, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_160; + setRet(call_fget_flags_160, 0, ret_val_fget_flags_160); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 136); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 137: FMADD__D */ + continuation_e __fmadd__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMADD__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 137); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_163; + auto unbox_d_163_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_163 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_163, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_164; + auto unbox_d_164_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_164 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_164, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_165; + auto unbox_d_165_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_d_165 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_165, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_166; + x86::Gp ret_val_get_rm_166 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_166, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_d_162; + auto fmadd_d_162_arg0 = ret_val_unbox_d_163; + auto fmadd_d_162_arg1 = ret_val_unbox_d_164; + auto fmadd_d_162_arg2 = ret_val_unbox_d_165; + auto fmadd_d_162_arg4 = ret_val_get_rm_166; + x86::Gp ret_val_fmadd_d_162 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fmadd_d_162, &fmadd_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_161; + auto NaNBox64_161_arg0 = ret_val_fmadd_d_162; + x86::Gp ret_val_NaNBox64_161 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_161, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_161); + setArg(call_unbox_d_163, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_163, 1, unbox_d_163_arg1); + setRet(call_unbox_d_163, 0, ret_val_unbox_d_163); + setArg(call_unbox_d_164, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_164, 1, unbox_d_164_arg1); + setRet(call_unbox_d_164, 0, ret_val_unbox_d_164); + setArg(call_unbox_d_165, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_165, 1, unbox_d_165_arg1); + setRet(call_unbox_d_165, 0, ret_val_unbox_d_165); + setArg(call_get_rm_166, 0, reinterpret_cast(this)); + setArg(call_get_rm_166, 1, rm); + setRet(call_get_rm_166, 0, ret_val_get_rm_166); + setArg(call_fmadd_d_162, 0, fmadd_d_162_arg0); + setArg(call_fmadd_d_162, 1, fmadd_d_162_arg1); + setArg(call_fmadd_d_162, 2, fmadd_d_162_arg2); + setArg(call_fmadd_d_162, 3, 0); + setArg(call_fmadd_d_162, 4, fmadd_d_162_arg4); + setRet(call_fmadd_d_162, 0, ret_val_fmadd_d_162); + setArg(call_NaNBox64_161, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_161, 1, NaNBox64_161_arg0); + setRet(call_NaNBox64_161, 0, ret_val_NaNBox64_161); + InvokeNode* call_fget_flags_167; + x86::Gp ret_val_fget_flags_167 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_167, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_167; + setRet(call_fget_flags_167, 0, ret_val_fget_flags_167); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 137); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 138: FMSUB__D */ + continuation_e __fmsub__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMSUB__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 138); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_170; + auto unbox_d_170_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_170 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_170, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_171; + auto unbox_d_171_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_171 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_171, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_172; + auto unbox_d_172_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_d_172 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_172, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_173; + x86::Gp ret_val_get_rm_173 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_173, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_d_169; + auto fmadd_d_169_arg0 = ret_val_unbox_d_170; + auto fmadd_d_169_arg1 = ret_val_unbox_d_171; + auto fmadd_d_169_arg2 = ret_val_unbox_d_172; + auto fmadd_d_169_arg4 = ret_val_get_rm_173; + x86::Gp ret_val_fmadd_d_169 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fmadd_d_169, &fmadd_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_168; + auto NaNBox64_168_arg0 = ret_val_fmadd_d_169; + x86::Gp ret_val_NaNBox64_168 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_168, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + auto res = ret_val_NaNBox64_168; + setArg(call_unbox_d_170, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_170, 1, unbox_d_170_arg1); + setRet(call_unbox_d_170, 0, ret_val_unbox_d_170); + setArg(call_unbox_d_171, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_171, 1, unbox_d_171_arg1); + setRet(call_unbox_d_171, 0, ret_val_unbox_d_171); + setArg(call_unbox_d_172, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_172, 1, unbox_d_172_arg1); + setRet(call_unbox_d_172, 0, ret_val_unbox_d_172); + setArg(call_get_rm_173, 0, reinterpret_cast(this)); + setArg(call_get_rm_173, 1, rm); + setRet(call_get_rm_173, 0, ret_val_get_rm_173); + setArg(call_fmadd_d_169, 0, fmadd_d_169_arg0); + setArg(call_fmadd_d_169, 1, fmadd_d_169_arg1); + setArg(call_fmadd_d_169, 2, fmadd_d_169_arg2); + setArg(call_fmadd_d_169, 3, 1); + setArg(call_fmadd_d_169, 4, fmadd_d_169_arg4); + setRet(call_fmadd_d_169, 0, ret_val_fmadd_d_169); + setArg(call_NaNBox64_168, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_168, 1, NaNBox64_168_arg0); + setRet(call_NaNBox64_168, 0, ret_val_NaNBox64_168); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + res); + InvokeNode* call_fget_flags_174; + x86::Gp ret_val_fget_flags_174 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_174, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_174; + setRet(call_fget_flags_174, 0, ret_val_fget_flags_174); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 138); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 139: FNMADD__D */ + continuation_e __fnmadd__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FNMADD__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 139); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_177; + auto unbox_d_177_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_177 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_177, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_178; + auto unbox_d_178_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_178 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_178, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_179; + auto unbox_d_179_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_d_179 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_179, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_180; + x86::Gp ret_val_get_rm_180 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_180, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_d_176; + auto fmadd_d_176_arg0 = ret_val_unbox_d_177; + auto fmadd_d_176_arg1 = ret_val_unbox_d_178; + auto fmadd_d_176_arg2 = ret_val_unbox_d_179; + auto fmadd_d_176_arg4 = ret_val_get_rm_180; + x86::Gp ret_val_fmadd_d_176 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fmadd_d_176, &fmadd_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_175; + auto NaNBox64_175_arg0 = ret_val_fmadd_d_176; + x86::Gp ret_val_NaNBox64_175 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_175, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_175); + setArg(call_unbox_d_177, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_177, 1, unbox_d_177_arg1); + setRet(call_unbox_d_177, 0, ret_val_unbox_d_177); + setArg(call_unbox_d_178, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_178, 1, unbox_d_178_arg1); + setRet(call_unbox_d_178, 0, ret_val_unbox_d_178); + setArg(call_unbox_d_179, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_179, 1, unbox_d_179_arg1); + setRet(call_unbox_d_179, 0, ret_val_unbox_d_179); + setArg(call_get_rm_180, 0, reinterpret_cast(this)); + setArg(call_get_rm_180, 1, rm); + setRet(call_get_rm_180, 0, ret_val_get_rm_180); + setArg(call_fmadd_d_176, 0, fmadd_d_176_arg0); + setArg(call_fmadd_d_176, 1, fmadd_d_176_arg1); + setArg(call_fmadd_d_176, 2, fmadd_d_176_arg2); + setArg(call_fmadd_d_176, 3, 2); + setArg(call_fmadd_d_176, 4, fmadd_d_176_arg4); + setRet(call_fmadd_d_176, 0, ret_val_fmadd_d_176); + setArg(call_NaNBox64_175, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_175, 1, NaNBox64_175_arg0); + setRet(call_NaNBox64_175, 0, ret_val_NaNBox64_175); + InvokeNode* call_fget_flags_181; + x86::Gp ret_val_fget_flags_181 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_181, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_181; + setRet(call_fget_flags_181, 0, ret_val_fget_flags_181); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 139); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 140: FNMSUB__D */ + continuation_e __fnmsub__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FNMSUB__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 140); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_184; + auto unbox_d_184_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_184 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_184, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_185; + auto unbox_d_185_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_185 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_185, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_186; + auto unbox_d_186_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_d_186 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_186, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_187; + x86::Gp ret_val_get_rm_187 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_187, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_d_183; + auto fmadd_d_183_arg0 = ret_val_unbox_d_184; + auto fmadd_d_183_arg1 = ret_val_unbox_d_185; + auto fmadd_d_183_arg2 = ret_val_unbox_d_186; + auto fmadd_d_183_arg4 = ret_val_get_rm_187; + x86::Gp ret_val_fmadd_d_183 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fmadd_d_183, &fmadd_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_182; + auto NaNBox64_182_arg0 = ret_val_fmadd_d_183; + x86::Gp ret_val_NaNBox64_182 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_182, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_182); + setArg(call_unbox_d_184, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_184, 1, unbox_d_184_arg1); + setRet(call_unbox_d_184, 0, ret_val_unbox_d_184); + setArg(call_unbox_d_185, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_185, 1, unbox_d_185_arg1); + setRet(call_unbox_d_185, 0, ret_val_unbox_d_185); + setArg(call_unbox_d_186, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_186, 1, unbox_d_186_arg1); + setRet(call_unbox_d_186, 0, ret_val_unbox_d_186); + setArg(call_get_rm_187, 0, reinterpret_cast(this)); + setArg(call_get_rm_187, 1, rm); + setRet(call_get_rm_187, 0, ret_val_get_rm_187); + setArg(call_fmadd_d_183, 0, fmadd_d_183_arg0); + setArg(call_fmadd_d_183, 1, fmadd_d_183_arg1); + setArg(call_fmadd_d_183, 2, fmadd_d_183_arg2); + setArg(call_fmadd_d_183, 3, 3); + setArg(call_fmadd_d_183, 4, fmadd_d_183_arg4); + setRet(call_fmadd_d_183, 0, ret_val_fmadd_d_183); + setArg(call_NaNBox64_182, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_182, 1, NaNBox64_182_arg0); + setRet(call_NaNBox64_182, 0, ret_val_NaNBox64_182); + InvokeNode* call_fget_flags_188; + x86::Gp ret_val_fget_flags_188 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_188, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_188; + setRet(call_fget_flags_188, 0, ret_val_fget_flags_188); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 140); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 141: FCVT__W__D */ + continuation_e __fcvt__w__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.w.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__W__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 141); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_190; + auto unbox_d_190_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_190 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_190, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_191; + x86::Gp ret_val_get_rm_191 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_191, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f64toi32_189; + auto f64toi32_189_arg0 = ret_val_unbox_d_190; + auto f64toi32_189_arg1 = ret_val_get_rm_191; + x86::Gp ret_val_f64toi32_189 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_f64toi32_189, &f64toi32, FuncSignature::build()); + auto res = gen_ext(cc, + gen_ext(cc, + ret_val_f64toi32_189, 32, false), 32, true); + setArg(call_unbox_d_190, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_190, 1, unbox_d_190_arg1); + setRet(call_unbox_d_190, 0, ret_val_unbox_d_190); + setArg(call_get_rm_191, 0, reinterpret_cast(this)); + setArg(call_get_rm_191, 1, rm); + setRet(call_get_rm_191, 0, ret_val_get_rm_191); + setArg(call_f64toi32_189, 0, f64toi32_189_arg0); + setArg(call_f64toi32_189, 1, f64toi32_189_arg1); + setRet(call_f64toi32_189, 0, ret_val_f64toi32_189); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, true)); + } + InvokeNode* call_fget_flags_192; + x86::Gp ret_val_fget_flags_192 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_192, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_192; + setRet(call_fget_flags_192, 0, ret_val_fget_flags_192); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 141); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 142: FCVT__WU__D */ + continuation_e __fcvt__wu__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.wu.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__WU__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 142); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_194; + auto unbox_d_194_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_194 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_194, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_195; + x86::Gp ret_val_get_rm_195 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_195, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f64toui32_193; + auto f64toui32_193_arg0 = ret_val_unbox_d_194; + auto f64toui32_193_arg1 = ret_val_get_rm_195; + x86::Gp ret_val_f64toui32_193 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_f64toui32_193, &f64toui32, FuncSignature::build()); + auto res = gen_ext(cc, + gen_ext(cc, + ret_val_f64toui32_193, 32, false), 32, true); + setArg(call_unbox_d_194, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_194, 1, unbox_d_194_arg1); + setRet(call_unbox_d_194, 0, ret_val_unbox_d_194); + setArg(call_get_rm_195, 0, reinterpret_cast(this)); + setArg(call_get_rm_195, 1, rm); + setRet(call_get_rm_195, 0, ret_val_get_rm_195); + setArg(call_f64toui32_193, 0, f64toui32_193_arg0); + setArg(call_f64toui32_193, 1, f64toui32_193_arg1); + setRet(call_f64toui32_193, 0, ret_val_f64toui32_193); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, true)); + } + InvokeNode* call_fget_flags_196; + x86::Gp ret_val_fget_flags_196 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_196, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_196; + setRet(call_fget_flags_196, 0, ret_val_fget_flags_196); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 142); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 143: FCVT__D__W */ + continuation_e __fcvt__d__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.w"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__D__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 143); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_199; + x86::Gp ret_val_get_rm_199 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_199, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_i32tof64_198; + auto i32tof64_198_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto i32tof64_198_arg1 = ret_val_get_rm_199; + x86::Gp ret_val_i32tof64_198 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_i32tof64_198, &i32tof64, FuncSignature::build()); + InvokeNode* call_NaNBox64_197; + auto NaNBox64_197_arg0 = ret_val_i32tof64_198; + x86::Gp ret_val_NaNBox64_197 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_197, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_197); + setArg(call_get_rm_199, 0, reinterpret_cast(this)); + setArg(call_get_rm_199, 1, rm); + setRet(call_get_rm_199, 0, ret_val_get_rm_199); + setArg(call_i32tof64_198, 0, i32tof64_198_arg0); + setArg(call_i32tof64_198, 1, i32tof64_198_arg1); + setRet(call_i32tof64_198, 0, ret_val_i32tof64_198); + setArg(call_NaNBox64_197, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_197, 1, NaNBox64_197_arg0); + setRet(call_NaNBox64_197, 0, ret_val_NaNBox64_197); + InvokeNode* call_fget_flags_200; + x86::Gp ret_val_fget_flags_200 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_200, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_200; + setRet(call_fget_flags_200, 0, ret_val_fget_flags_200); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 143); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 144: FCVT__D__WU */ + continuation_e __fcvt__d__wu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.wu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__D__WU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 144); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_203; + x86::Gp ret_val_get_rm_203 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_203, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_ui32tof64_202; + auto ui32tof64_202_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto ui32tof64_202_arg1 = ret_val_get_rm_203; + x86::Gp ret_val_ui32tof64_202 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_ui32tof64_202, &ui32tof64, FuncSignature::build()); + InvokeNode* call_NaNBox64_201; + auto NaNBox64_201_arg0 = ret_val_ui32tof64_202; + x86::Gp ret_val_NaNBox64_201 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_201, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_201); + setArg(call_get_rm_203, 0, reinterpret_cast(this)); + setArg(call_get_rm_203, 1, rm); + setRet(call_get_rm_203, 0, ret_val_get_rm_203); + setArg(call_ui32tof64_202, 0, ui32tof64_202_arg0); + setArg(call_ui32tof64_202, 1, ui32tof64_202_arg1); + setRet(call_ui32tof64_202, 0, ret_val_ui32tof64_202); + setArg(call_NaNBox64_201, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_201, 1, NaNBox64_201_arg0); + setRet(call_NaNBox64_201, 0, ret_val_NaNBox64_201); + InvokeNode* call_fget_flags_204; + x86::Gp ret_val_fget_flags_204 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_204, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_204; + setRet(call_fget_flags_204, 0, ret_val_fget_flags_204); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 144); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 145: FCVT__S__D */ + continuation_e __fcvt__s__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__S__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 145); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_207; + auto unbox_d_207_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_207 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_207, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_208; + x86::Gp ret_val_get_rm_208 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_208, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f64tof32_206; + auto f64tof32_206_arg0 = ret_val_unbox_d_207; + auto f64tof32_206_arg1 = ret_val_get_rm_208; + x86::Gp ret_val_f64tof32_206 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_f64tof32_206, &f64tof32, FuncSignature::build()); + InvokeNode* call_NaNBox32_205; + auto NaNBox32_205_arg0 = ret_val_f64tof32_206; + x86::Gp ret_val_NaNBox32_205 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_205, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_205); + setArg(call_unbox_d_207, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_207, 1, unbox_d_207_arg1); + setRet(call_unbox_d_207, 0, ret_val_unbox_d_207); + setArg(call_get_rm_208, 0, reinterpret_cast(this)); + setArg(call_get_rm_208, 1, rm); + setRet(call_get_rm_208, 0, ret_val_get_rm_208); + setArg(call_f64tof32_206, 0, f64tof32_206_arg0); + setArg(call_f64tof32_206, 1, f64tof32_206_arg1); + setRet(call_f64tof32_206, 0, ret_val_f64tof32_206); + setArg(call_NaNBox32_205, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_205, 1, NaNBox32_205_arg0); + setRet(call_NaNBox32_205, 0, ret_val_NaNBox32_205); + InvokeNode* call_fget_flags_209; + x86::Gp ret_val_fget_flags_209 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_209, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_209; + setRet(call_fget_flags_209, 0, ret_val_fget_flags_209); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 145); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 146: FCVT__D__S */ + continuation_e __fcvt__d__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__D__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 146); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_212; + auto unbox_s_212_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_212 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_212, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_213; + x86::Gp ret_val_get_rm_213 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_213, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f32tof64_211; + auto f32tof64_211_arg0 = ret_val_unbox_s_212; + auto f32tof64_211_arg1 = ret_val_get_rm_213; + x86::Gp ret_val_f32tof64_211 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_f32tof64_211, &f32tof64, FuncSignature::build()); + InvokeNode* call_NaNBox64_210; + auto NaNBox64_210_arg0 = ret_val_f32tof64_211; + x86::Gp ret_val_NaNBox64_210 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_210, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_210); + setArg(call_unbox_s_212, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_212, 1, unbox_s_212_arg1); + setRet(call_unbox_s_212, 0, ret_val_unbox_s_212); + setArg(call_get_rm_213, 0, reinterpret_cast(this)); + setArg(call_get_rm_213, 1, rm); + setRet(call_get_rm_213, 0, ret_val_get_rm_213); + setArg(call_f32tof64_211, 0, f32tof64_211_arg0); + setArg(call_f32tof64_211, 1, f32tof64_211_arg1); + setRet(call_f32tof64_211, 0, ret_val_f32tof64_211); + setArg(call_NaNBox64_210, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_210, 1, NaNBox64_210_arg0); + setRet(call_NaNBox64_210, 0, ret_val_NaNBox64_210); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 146); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 147: FSGNJ__D */ + continuation_e __fsgnj__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnj.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJ__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 147); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_215; + auto unbox_d_215_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_215 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_215, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_216; + auto unbox_d_216_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_216 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_216, &unbox_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_214; + auto NaNBox64_214_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_d_215, 63, 63-63+1), 64, false), 63), gen_ext(cc, gen_slice(cc, ret_val_unbox_d_216, 0, 62-0+1), 64, false)); + x86::Gp ret_val_NaNBox64_214 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_214, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_214); + setArg(call_unbox_d_215, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_215, 1, unbox_d_215_arg1); + setRet(call_unbox_d_215, 0, ret_val_unbox_d_215); + setArg(call_unbox_d_216, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_216, 1, unbox_d_216_arg1); + setRet(call_unbox_d_216, 0, ret_val_unbox_d_216); + setArg(call_NaNBox64_214, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_214, 1, NaNBox64_214_arg0); + setRet(call_NaNBox64_214, 0, ret_val_NaNBox64_214); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 147); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 148: FSGNJN__D */ + continuation_e __fsgnjn__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjn.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJN__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 148); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_218; + auto unbox_d_218_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_218 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_218, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_219; + auto unbox_d_219_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_219 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_219, &unbox_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_217; + auto NaNBox64_217_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_d_218, 63, 63-63+1)), 64, false), 63), gen_ext(cc, gen_slice(cc, ret_val_unbox_d_219, 0, 62-0+1), 64, false)); + x86::Gp ret_val_NaNBox64_217 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_217, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_217); + setArg(call_unbox_d_218, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_218, 1, unbox_d_218_arg1); + setRet(call_unbox_d_218, 0, ret_val_unbox_d_218); + setArg(call_unbox_d_219, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_219, 1, unbox_d_219_arg1); + setRet(call_unbox_d_219, 0, ret_val_unbox_d_219); + setArg(call_NaNBox64_217, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_217, 1, NaNBox64_217_arg0); + setRet(call_NaNBox64_217, 0, ret_val_NaNBox64_217); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 148); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 149: FSGNJX__D */ + continuation_e __fsgnjx__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjx.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJX__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 149); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_221; + auto unbox_d_221_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_221 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_221, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_222; + auto unbox_d_222_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_222 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_222, &unbox_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_220; + auto NaNBox64_220_arg0 = gen_operation(cc, bxor, (gen_operation(cc, band, ret_val_unbox_d_221, ((uint64_t)1<<63))), ret_val_unbox_d_222); + x86::Gp ret_val_NaNBox64_220 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_220, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_220); + setArg(call_unbox_d_221, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_221, 1, unbox_d_221_arg1); + setRet(call_unbox_d_221, 0, ret_val_unbox_d_221); + setArg(call_unbox_d_222, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_222, 1, unbox_d_222_arg1); + setRet(call_unbox_d_222, 0, ret_val_unbox_d_222); + setArg(call_NaNBox64_220, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_220, 1, NaNBox64_220_arg0); + setRet(call_NaNBox64_220, 0, ret_val_NaNBox64_220); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 149); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 150: FEQ__D */ + continuation_e __feq__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "feq.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FEQ__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 150); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_224; + auto unbox_d_224_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_224 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_224, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_225; + auto unbox_d_225_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_225 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_225, &unbox_d, FuncSignature::build()); + InvokeNode* call_fcmp_d_223; + auto fcmp_d_223_arg0 = ret_val_unbox_d_224; + auto fcmp_d_223_arg1 = ret_val_unbox_d_225; + x86::Gp ret_val_fcmp_d_223 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fcmp_d_223, &fcmp_d, FuncSignature::build()); + auto res = ret_val_fcmp_d_223; + setArg(call_unbox_d_224, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_224, 1, unbox_d_224_arg1); + setRet(call_unbox_d_224, 0, ret_val_unbox_d_224); + setArg(call_unbox_d_225, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_225, 1, unbox_d_225_arg1); + setRet(call_unbox_d_225, 0, ret_val_unbox_d_225); + setArg(call_fcmp_d_223, 0, fcmp_d_223_arg0); + setArg(call_fcmp_d_223, 1, fcmp_d_223_arg1); + setArg(call_fcmp_d_223, 2, 0); + setRet(call_fcmp_d_223, 0, ret_val_fcmp_d_223); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, false)); + } + InvokeNode* call_fget_flags_226; + x86::Gp ret_val_fget_flags_226 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_226, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_226; + setRet(call_fget_flags_226, 0, ret_val_fget_flags_226); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 150); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 151: FLT__D */ + continuation_e __flt__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "flt.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLT__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 151); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_228; + auto unbox_d_228_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_228 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_228, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_229; + auto unbox_d_229_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_229 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_229, &unbox_d, FuncSignature::build()); + InvokeNode* call_fcmp_d_227; + auto fcmp_d_227_arg0 = ret_val_unbox_d_228; + auto fcmp_d_227_arg1 = ret_val_unbox_d_229; + x86::Gp ret_val_fcmp_d_227 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fcmp_d_227, &fcmp_d, FuncSignature::build()); + auto res = ret_val_fcmp_d_227; + setArg(call_unbox_d_228, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_228, 1, unbox_d_228_arg1); + setRet(call_unbox_d_228, 0, ret_val_unbox_d_228); + setArg(call_unbox_d_229, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_229, 1, unbox_d_229_arg1); + setRet(call_unbox_d_229, 0, ret_val_unbox_d_229); + setArg(call_fcmp_d_227, 0, fcmp_d_227_arg0); + setArg(call_fcmp_d_227, 1, fcmp_d_227_arg1); + setArg(call_fcmp_d_227, 2, 2); + setRet(call_fcmp_d_227, 0, ret_val_fcmp_d_227); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, false)); + } + InvokeNode* call_fget_flags_230; + x86::Gp ret_val_fget_flags_230 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_230, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_230; + setRet(call_fget_flags_230, 0, ret_val_fget_flags_230); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 151); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 152: FLE__D */ + continuation_e __fle__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fle.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLE__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 152); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_232; + auto unbox_d_232_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_232 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_232, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_233; + auto unbox_d_233_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_233 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_233, &unbox_d, FuncSignature::build()); + InvokeNode* call_fcmp_d_231; + auto fcmp_d_231_arg0 = ret_val_unbox_d_232; + auto fcmp_d_231_arg1 = ret_val_unbox_d_233; + x86::Gp ret_val_fcmp_d_231 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fcmp_d_231, &fcmp_d, FuncSignature::build()); + auto res = ret_val_fcmp_d_231; + setArg(call_unbox_d_232, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_232, 1, unbox_d_232_arg1); + setRet(call_unbox_d_232, 0, ret_val_unbox_d_232); + setArg(call_unbox_d_233, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_233, 1, unbox_d_233_arg1); + setRet(call_unbox_d_233, 0, ret_val_unbox_d_233); + setArg(call_fcmp_d_231, 0, fcmp_d_231_arg0); + setArg(call_fcmp_d_231, 1, fcmp_d_231_arg1); + setArg(call_fcmp_d_231, 2, 1); + setRet(call_fcmp_d_231, 0, ret_val_fcmp_d_231); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, false)); + } + InvokeNode* call_fget_flags_234; + x86::Gp ret_val_fget_flags_234 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_234, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_234; + setRet(call_fget_flags_234, 0, ret_val_fget_flags_234); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 152); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 153: FCLASS__D */ + continuation_e __fclass__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fclass.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCLASS__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 153); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_236; + auto unbox_d_236_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_236 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_236, &unbox_d, FuncSignature::build()); + InvokeNode* call_fclass_d_235; + auto fclass_d_235_arg0 = ret_val_unbox_d_236; + x86::Gp ret_val_fclass_d_235 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fclass_d_235, &fclass_d, FuncSignature::build()); + auto res = ret_val_fclass_d_235; + setArg(call_unbox_d_236, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_236, 1, unbox_d_236_arg1); + setRet(call_unbox_d_236, 0, ret_val_unbox_d_236); + setArg(call_fclass_d_235, 0, fclass_d_235_arg0); + setRet(call_fclass_d_235, 0, ret_val_fclass_d_235); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 32, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 153); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 154: C__FLD */ + continuation_e __c__fld(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rd}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fld"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FLD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 154); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 32, false); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false); + InvokeNode* call_NaNBox64_237; + auto NaNBox64_237_arg0 = res; + x86::Gp ret_val_NaNBox64_237 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_237, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd+8), + ret_val_NaNBox64_237); + setArg(call_NaNBox64_237, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_237, 1, NaNBox64_237_arg0); + setRet(call_NaNBox64_237, 0, ret_val_NaNBox64_237); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 154); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 155: C__FSD */ + continuation_e __c__fsd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rs2}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fsd"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FSD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 155); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 32, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs2+8), 64, false), 8); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 155); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 156: C__FLDSP */ + continuation_e __c__fldsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t uimm = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f {rd}, {uimm}(x2)", fmt::arg("mnemonic", "c.fldsp"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FLDSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 156); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 32, false); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false); + InvokeNode* call_NaNBox64_238; + auto NaNBox64_238_arg0 = res; + x86::Gp ret_val_NaNBox64_238 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_238, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_238); + setArg(call_NaNBox64_238, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_238, 1, NaNBox64_238_arg0); + setRet(call_NaNBox64_238, 0, ret_val_NaNBox64_238); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 156); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 157: C__FSDSP */ + continuation_e __c__fsdsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint16_t uimm = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f {rs2}, {uimm}(x2), ", fmt::arg("mnemonic", "c.fsdsp"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FSDSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 157); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 32, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs2), 64, false), 8); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 157); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 158: SFENCE__VMA */ + continuation_e __sfence__vma(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t asid = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {asid}", fmt::arg("mnemonic", "sfence.vma"), + fmt::arg("rs1", name(rs1)), fmt::arg("asid", name(asid))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SFENCE__VMA_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 158); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_write_mem(jh, traits::FENCE, static_cast(traits::fencevma), ((uint8_t)rs1<<8)|(uint8_t)asid, 4); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 158); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 159: SRET */ + continuation_e __sret(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "sret"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRET_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 159); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + gen_leave(jh, 1); + auto returnValue = TRAP; + + gen_sync(jh, POST_SYNC, 159); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 160: VSETVLI */ + continuation_e __vsetvli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t lmul = ((bit_sub<20,3>(instr))); + uint8_t sew = ((bit_sub<23,3>(instr))); + uint8_t ta = ((bit_sub<26,1>(instr))); + uint8_t ma = ((bit_sub<27,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {sew}, {lmul}, {ta}, {ma}", fmt::arg("mnemonic", "vsetvli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("sew", sew_name(sew)), fmt::arg("lmul", lmul_name(lmul)), fmt::arg("ta", ta_name(ta)), fmt::arg("ma", ma_name(ma))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSETVLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 160); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_239; + x86::Gp ret_val_get_sew_pow_239 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_239, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_240; + x86::Gp ret_val_get_lmul_pow_240 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_240, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto orig_ratio = gen_ext(cc, + (gen_operation(cc, sub, ret_val_get_sew_pow_239, ret_val_get_lmul_pow_240)), 5, true); + setArg(call_get_sew_pow_239, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_239, 0, ret_val_get_sew_pow_239); + setArg(call_get_lmul_pow_240, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_240, 0, ret_val_get_lmul_pow_240); + auto orig_vstart = load_reg_from_mem(jh, traits::vstart); + auto tmp241 = get_reg_Gp(cc, 8, false); + mov(cc, tmp241, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp241, 32, false) + , traits::vstart); + auto tmp242 = get_reg_Gp(cc, 32, false); + mov(cc, tmp242, (uint32_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul)); + write_reg_to_mem(jh, tmp242, traits::vtype); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_valid_sew_lmul_243; + x86::Gp ret_val_valid_sew_lmul_243 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_sew_lmul_243, (uintptr_t)&vm_impl::_valid_sew_lmul, FuncSignature::build()); + auto cond = gen_operation(cc, lnot, ret_val_valid_sew_lmul_243); + setArg(call_valid_sew_lmul_243, 0, reinterpret_cast(this)); + setRet(call_valid_sew_lmul_243, 0, ret_val_valid_sew_lmul_243); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + InvokeNode* call_handle_illegal_vtype_244; + cc.invoke(&call_handle_illegal_vtype_244, (uintptr_t)&vm_impl::_handle_illegal_vtype, FuncSignature::build()); + setArg(call_handle_illegal_vtype_244, 0, reinterpret_cast(this)); + write_reg_to_mem(jh, orig_vstart, traits::vstart); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_get_pow_245; + x86::Gp ret_val_get_pow_245 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_245, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_246; + x86::Gp ret_val_get_lmul_pow_246 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_246, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_247; + x86::Gp ret_val_get_sew_pow_247 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_247, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp248 = get_reg(cc, 16, false); + mov(cc, tmp248, 1); + auto VLMAX = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp248, (gen_operation(cc, sub, gen_operation(cc, add, ret_val_get_pow_245, ret_val_get_lmul_pow_246), ret_val_get_sew_pow_247)))), 16, false), ~ 1); + setArg(call_get_pow_245, 0, reinterpret_cast(this)); + setArg(call_get_pow_245, 1, static_cast(traits::VLEN)); + setRet(call_get_pow_245, 0, ret_val_get_pow_245); + setArg(call_get_lmul_pow_246, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_246, 0, ret_val_get_lmul_pow_246); + setArg(call_get_sew_pow_247, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_247, 0, ret_val_get_sew_pow_247); + if(rs1!=0){ + auto AVL = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + InvokeNode* call_calculate_new_vl_249; + auto calculate_new_vl_249_arg0 = AVL; + auto calculate_new_vl_249_arg1 = VLMAX; + x86::Gp ret_val_calculate_new_vl_249 = get_reg_Gp(cc, 16, false); + cc.invoke(&call_calculate_new_vl_249, (uintptr_t)&vm_impl::_calculate_new_vl, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_calculate_new_vl_249, 32, false), traits::vl); + setArg(call_calculate_new_vl_249, 0, reinterpret_cast(this)); + setArg(call_calculate_new_vl_249, 1, calculate_new_vl_249_arg0); + setArg(call_calculate_new_vl_249, 2, calculate_new_vl_249_arg1); + setRet(call_calculate_new_vl_249, 0, ret_val_calculate_new_vl_249); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem(jh, traits::vl)); + } + } + else { + if(rd!=0){ + write_reg_to_mem(jh, + gen_ext(cc, VLMAX, 32, false) + , traits::vl); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + VLMAX, 32, false)); + } + else { + InvokeNode* call_get_sew_pow_250; + x86::Gp ret_val_get_sew_pow_250 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_250, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_251; + x86::Gp ret_val_get_lmul_pow_251 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_251, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto new_ratio = gen_ext(cc, + (gen_operation(cc, sub, ret_val_get_sew_pow_250, ret_val_get_lmul_pow_251)), 5, true); + setArg(call_get_sew_pow_250, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_250, 0, ret_val_get_sew_pow_250); + setArg(call_get_lmul_pow_251, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_251, 0, ret_val_get_lmul_pow_251); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, orig_ratio, new_ratio); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_handle_illegal_vtype_252; + cc.invoke(&call_handle_illegal_vtype_252, (uintptr_t)&vm_impl::_handle_illegal_vtype, FuncSignature::build()); + setArg(call_handle_illegal_vtype_252, 0, reinterpret_cast(this)); + write_reg_to_mem(jh, orig_vstart, traits::vstart); + } + cc.bind(label_merge); + } + } + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 160); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 161: VSETIVLI */ + continuation_e __vsetivli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t uimm = ((bit_sub<15,5>(instr))); + uint8_t lmul = ((bit_sub<20,3>(instr))); + uint8_t sew = ((bit_sub<23,3>(instr))); + uint8_t ta = ((bit_sub<26,1>(instr))); + uint8_t ma = ((bit_sub<27,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm}, {sew}, {lmul}, {ta}, {ma}", fmt::arg("mnemonic", "vsetivli"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm), fmt::arg("sew", sew_name(sew)), fmt::arg("lmul", lmul_name(lmul)), fmt::arg("ta", ta_name(ta)), fmt::arg("ma", ma_name(ma))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSETIVLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 161); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto tmp253 = get_reg_Gp(cc, 32, false); + mov(cc, tmp253, (uint32_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul)); + write_reg_to_mem(jh, tmp253, traits::vtype); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_valid_sew_lmul_254; + x86::Gp ret_val_valid_sew_lmul_254 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_sew_lmul_254, (uintptr_t)&vm_impl::_valid_sew_lmul, FuncSignature::build()); + auto cond = gen_operation(cc, lnot, ret_val_valid_sew_lmul_254); + setArg(call_valid_sew_lmul_254, 0, reinterpret_cast(this)); + setRet(call_valid_sew_lmul_254, 0, ret_val_valid_sew_lmul_254); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + InvokeNode* call_handle_illegal_vtype_255; + cc.invoke(&call_handle_illegal_vtype_255, (uintptr_t)&vm_impl::_handle_illegal_vtype, FuncSignature::build()); + setArg(call_handle_illegal_vtype_255, 0, reinterpret_cast(this)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_get_pow_256; + x86::Gp ret_val_get_pow_256 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_256, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_257; + x86::Gp ret_val_get_lmul_pow_257 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_257, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_258; + x86::Gp ret_val_get_sew_pow_258 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_258, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp259 = get_reg(cc, 16, false); + mov(cc, tmp259, 1); + auto VLMAX = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp259, (gen_operation(cc, sub, gen_operation(cc, add, ret_val_get_pow_256, ret_val_get_lmul_pow_257), ret_val_get_sew_pow_258)))), 16, false), ~ 1); + setArg(call_get_pow_256, 0, reinterpret_cast(this)); + setArg(call_get_pow_256, 1, static_cast(traits::VLEN)); + setRet(call_get_pow_256, 0, ret_val_get_pow_256); + setArg(call_get_lmul_pow_257, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_257, 0, ret_val_get_lmul_pow_257); + setArg(call_get_sew_pow_258, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_258, 0, ret_val_get_sew_pow_258); + InvokeNode* call_calculate_new_vl_260; + auto calculate_new_vl_260_arg1 = VLMAX; + x86::Gp ret_val_calculate_new_vl_260 = get_reg_Gp(cc, 16, false); + cc.invoke(&call_calculate_new_vl_260, (uintptr_t)&vm_impl::_calculate_new_vl, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_calculate_new_vl_260, 32, false) + , traits::vl); + setArg(call_calculate_new_vl_260, 0, reinterpret_cast(this)); + setArg(call_calculate_new_vl_260, 1, uimm); + setArg(call_calculate_new_vl_260, 2, calculate_new_vl_260_arg1); + setRet(call_calculate_new_vl_260, 0, ret_val_calculate_new_vl_260); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem(jh, traits::vl)); + auto tmp261 = get_reg_Gp(cc, 8, false); + mov(cc, tmp261, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp261, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 161); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 162: VSETVL */ + continuation_e __vsetvl(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "vsetvl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSETVL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 162); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_262; + x86::Gp ret_val_get_sew_pow_262 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_262, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_263; + x86::Gp ret_val_get_lmul_pow_263 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_263, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto orig_ratio = gen_ext(cc, + (gen_operation(cc, sub, ret_val_get_sew_pow_262, ret_val_get_lmul_pow_263)), 5, true); + setArg(call_get_sew_pow_262, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_262, 0, ret_val_get_sew_pow_262); + setArg(call_get_lmul_pow_263, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_263, 0, ret_val_get_lmul_pow_263); + auto orig_vstart = load_reg_from_mem(jh, traits::vstart); + auto tmp264 = get_reg_Gp(cc, 8, false); + mov(cc, tmp264, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp264, 32, false) + , traits::vstart); + { + auto label_merge = cc.newLabel(); + auto cond = gen_slice(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 8, (static_cast(traits::XLEN)-2)-8+1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.bind(label_merge); + } + write_reg_to_mem(jh, load_reg_from_mem_Gp(jh, traits::X0 + rs2), traits::vtype); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_valid_sew_lmul_265; + x86::Gp ret_val_valid_sew_lmul_265 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_sew_lmul_265, (uintptr_t)&vm_impl::_valid_sew_lmul, FuncSignature::build()); + auto cond = gen_operation(cc, lnot, ret_val_valid_sew_lmul_265); + setArg(call_valid_sew_lmul_265, 0, reinterpret_cast(this)); + setRet(call_valid_sew_lmul_265, 0, ret_val_valid_sew_lmul_265); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + InvokeNode* call_handle_illegal_vtype_266; + cc.invoke(&call_handle_illegal_vtype_266, (uintptr_t)&vm_impl::_handle_illegal_vtype, FuncSignature::build()); + setArg(call_handle_illegal_vtype_266, 0, reinterpret_cast(this)); + write_reg_to_mem(jh, orig_vstart, traits::vstart); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_get_pow_267; + x86::Gp ret_val_get_pow_267 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_267, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_268; + x86::Gp ret_val_get_lmul_pow_268 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_268, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_269; + x86::Gp ret_val_get_sew_pow_269 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_269, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp270 = get_reg(cc, 16, false); + mov(cc, tmp270, 1); + auto VLMAX = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp270, (gen_operation(cc, sub, gen_operation(cc, add, ret_val_get_pow_267, ret_val_get_lmul_pow_268), ret_val_get_sew_pow_269)))), 16, false), ~ 1); + setArg(call_get_pow_267, 0, reinterpret_cast(this)); + setArg(call_get_pow_267, 1, static_cast(traits::VLEN)); + setRet(call_get_pow_267, 0, ret_val_get_pow_267); + setArg(call_get_lmul_pow_268, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_268, 0, ret_val_get_lmul_pow_268); + setArg(call_get_sew_pow_269, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_269, 0, ret_val_get_sew_pow_269); + if(rs1!=0){ + auto AVL = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + InvokeNode* call_calculate_new_vl_271; + auto calculate_new_vl_271_arg0 = AVL; + auto calculate_new_vl_271_arg1 = VLMAX; + x86::Gp ret_val_calculate_new_vl_271 = get_reg_Gp(cc, 16, false); + cc.invoke(&call_calculate_new_vl_271, (uintptr_t)&vm_impl::_calculate_new_vl, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_calculate_new_vl_271, 32, false), traits::vl); + setArg(call_calculate_new_vl_271, 0, reinterpret_cast(this)); + setArg(call_calculate_new_vl_271, 1, calculate_new_vl_271_arg0); + setArg(call_calculate_new_vl_271, 2, calculate_new_vl_271_arg1); + setRet(call_calculate_new_vl_271, 0, ret_val_calculate_new_vl_271); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem(jh, traits::vl)); + } + } + else { + if(rd!=0){ + write_reg_to_mem(jh, + gen_ext(cc, VLMAX, 32, false) + , traits::vl); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + VLMAX, 32, false)); + } + else { + InvokeNode* call_get_sew_pow_272; + x86::Gp ret_val_get_sew_pow_272 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_272, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_273; + x86::Gp ret_val_get_lmul_pow_273 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_273, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto new_ratio = gen_ext(cc, + (gen_operation(cc, sub, ret_val_get_sew_pow_272, ret_val_get_lmul_pow_273)), 5, true); + setArg(call_get_sew_pow_272, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_272, 0, ret_val_get_sew_pow_272); + setArg(call_get_lmul_pow_273, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_273, 0, ret_val_get_lmul_pow_273); + auto vill = gen_slice(cc, load_reg_from_mem(jh, traits::vtype), static_cast(traits::XLEN)-1, 1); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, lor, vill, (gen_operation(cc, ne, orig_ratio, new_ratio))); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_handle_illegal_vtype_274; + cc.invoke(&call_handle_illegal_vtype_274, (uintptr_t)&vm_impl::_handle_illegal_vtype, FuncSignature::build()); + setArg(call_handle_illegal_vtype_274, 0, reinterpret_cast(this)); + write_reg_to_mem(jh, orig_vstart, traits::vstart); + } + cc.bind(label_merge); + } + } + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 162); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 163: VLE8__V */ + continuation_e __vle8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 163); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_275; + x86::Gp ret_val_get_pow_275 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_275, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_276; + x86::Gp ret_val_get_sew_pow_276 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_276, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_277; + x86::Gp ret_val_get_lmul_pow_277 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_277, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_275, ret_val_get_sew_pow_276), ret_val_get_lmul_pow_277)), 3, true); + setArg(call_get_pow_275, 0, reinterpret_cast(this)); + setArg(call_get_pow_275, 1, EEW); + setRet(call_get_pow_275, 0, ret_val_get_pow_275); + setArg(call_get_sew_pow_276, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_276, 0, ret_val_get_sew_pow_276); + setArg(call_get_lmul_pow_277, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_277, 0, ret_val_get_lmul_pow_277); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_278; + auto illegal_load_278_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_278 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_278, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_278; + setArg(call_illegal_load_278, 0, reinterpret_cast(this)); + setArg(call_illegal_load_278, 1, vd); + setArg(call_illegal_load_278, 2, vm); + setArg(call_illegal_load_278, 3, 1); + setArg(call_illegal_load_278, 4, EEW); + setArg(call_illegal_load_278, 5, illegal_load_278_arg4); + setRet(call_illegal_load_278, 0, ret_val_illegal_load_278); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_279; + auto vlseg_279_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_279_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_279_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_279_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_279 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_279, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_279, 32, false), traits::vstart); + setArg(call_vlseg_279, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_279, 1, V); + setArg(call_vlseg_279, 2, vlseg_279_arg1); + setArg(call_vlseg_279, 3, vlseg_279_arg2); + setArg(call_vlseg_279, 4, vlseg_279_arg3); + setArg(call_vlseg_279, 5, vm); + setArg(call_vlseg_279, 6, vd); + setArg(call_vlseg_279, 7, vlseg_279_arg6); + setArg(call_vlseg_279, 8, 0); + setArg(call_vlseg_279, 9, 1); + setRet(call_vlseg_279, 0, ret_val_vlseg_279); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 163); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 164: VLE16__V */ + continuation_e __vle16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 164); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_280; + x86::Gp ret_val_get_pow_280 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_280, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_281; + x86::Gp ret_val_get_sew_pow_281 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_281, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_282; + x86::Gp ret_val_get_lmul_pow_282 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_282, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_280, ret_val_get_sew_pow_281), ret_val_get_lmul_pow_282)), 3, true); + setArg(call_get_pow_280, 0, reinterpret_cast(this)); + setArg(call_get_pow_280, 1, EEW); + setRet(call_get_pow_280, 0, ret_val_get_pow_280); + setArg(call_get_sew_pow_281, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_281, 0, ret_val_get_sew_pow_281); + setArg(call_get_lmul_pow_282, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_282, 0, ret_val_get_lmul_pow_282); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_283; + auto illegal_load_283_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_283 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_283, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_283; + setArg(call_illegal_load_283, 0, reinterpret_cast(this)); + setArg(call_illegal_load_283, 1, vd); + setArg(call_illegal_load_283, 2, vm); + setArg(call_illegal_load_283, 3, 1); + setArg(call_illegal_load_283, 4, EEW); + setArg(call_illegal_load_283, 5, illegal_load_283_arg4); + setRet(call_illegal_load_283, 0, ret_val_illegal_load_283); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_284; + auto vlseg_284_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_284_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_284_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_284_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_284 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_284, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_284, 32, false), traits::vstart); + setArg(call_vlseg_284, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_284, 1, V); + setArg(call_vlseg_284, 2, vlseg_284_arg1); + setArg(call_vlseg_284, 3, vlseg_284_arg2); + setArg(call_vlseg_284, 4, vlseg_284_arg3); + setArg(call_vlseg_284, 5, vm); + setArg(call_vlseg_284, 6, vd); + setArg(call_vlseg_284, 7, vlseg_284_arg6); + setArg(call_vlseg_284, 8, 5); + setArg(call_vlseg_284, 9, 1); + setRet(call_vlseg_284, 0, ret_val_vlseg_284); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 164); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 165: VLE32__V */ + continuation_e __vle32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 165); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_285; + x86::Gp ret_val_get_pow_285 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_285, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_286; + x86::Gp ret_val_get_sew_pow_286 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_286, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_287; + x86::Gp ret_val_get_lmul_pow_287 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_287, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_285, ret_val_get_sew_pow_286), ret_val_get_lmul_pow_287)), 3, true); + setArg(call_get_pow_285, 0, reinterpret_cast(this)); + setArg(call_get_pow_285, 1, EEW); + setRet(call_get_pow_285, 0, ret_val_get_pow_285); + setArg(call_get_sew_pow_286, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_286, 0, ret_val_get_sew_pow_286); + setArg(call_get_lmul_pow_287, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_287, 0, ret_val_get_lmul_pow_287); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_288; + auto illegal_load_288_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_288 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_288, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_288; + setArg(call_illegal_load_288, 0, reinterpret_cast(this)); + setArg(call_illegal_load_288, 1, vd); + setArg(call_illegal_load_288, 2, vm); + setArg(call_illegal_load_288, 3, 1); + setArg(call_illegal_load_288, 4, EEW); + setArg(call_illegal_load_288, 5, illegal_load_288_arg4); + setRet(call_illegal_load_288, 0, ret_val_illegal_load_288); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_289; + auto vlseg_289_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_289_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_289_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_289_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_289 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_289, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_289, 32, false), traits::vstart); + setArg(call_vlseg_289, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_289, 1, V); + setArg(call_vlseg_289, 2, vlseg_289_arg1); + setArg(call_vlseg_289, 3, vlseg_289_arg2); + setArg(call_vlseg_289, 4, vlseg_289_arg3); + setArg(call_vlseg_289, 5, vm); + setArg(call_vlseg_289, 6, vd); + setArg(call_vlseg_289, 7, vlseg_289_arg6); + setArg(call_vlseg_289, 8, 6); + setArg(call_vlseg_289, 9, 1); + setRet(call_vlseg_289, 0, ret_val_vlseg_289); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 165); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 166: VLE64__V */ + continuation_e __vle64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 166); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_290; + x86::Gp ret_val_get_pow_290 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_290, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_291; + x86::Gp ret_val_get_sew_pow_291 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_291, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_292; + x86::Gp ret_val_get_lmul_pow_292 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_292, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_290, ret_val_get_sew_pow_291), ret_val_get_lmul_pow_292)), 3, true); + setArg(call_get_pow_290, 0, reinterpret_cast(this)); + setArg(call_get_pow_290, 1, EEW); + setRet(call_get_pow_290, 0, ret_val_get_pow_290); + setArg(call_get_sew_pow_291, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_291, 0, ret_val_get_sew_pow_291); + setArg(call_get_lmul_pow_292, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_292, 0, ret_val_get_lmul_pow_292); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_293; + auto illegal_load_293_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_293 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_293, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_293; + setArg(call_illegal_load_293, 0, reinterpret_cast(this)); + setArg(call_illegal_load_293, 1, vd); + setArg(call_illegal_load_293, 2, vm); + setArg(call_illegal_load_293, 3, 1); + setArg(call_illegal_load_293, 4, EEW); + setArg(call_illegal_load_293, 5, illegal_load_293_arg4); + setRet(call_illegal_load_293, 0, ret_val_illegal_load_293); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_294; + auto vlseg_294_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_294_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_294_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_294_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_294 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_294, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_294, 32, false), traits::vstart); + setArg(call_vlseg_294, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_294, 1, V); + setArg(call_vlseg_294, 2, vlseg_294_arg1); + setArg(call_vlseg_294, 3, vlseg_294_arg2); + setArg(call_vlseg_294, 4, vlseg_294_arg3); + setArg(call_vlseg_294, 5, vm); + setArg(call_vlseg_294, 6, vd); + setArg(call_vlseg_294, 7, vlseg_294_arg6); + setArg(call_vlseg_294, 8, 7); + setArg(call_vlseg_294, 9, 1); + setRet(call_vlseg_294, 0, ret_val_vlseg_294); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 166); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 167: VLSEG2E8__V */ + continuation_e __vlseg2e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 167); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_295; + x86::Gp ret_val_get_pow_295 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_295, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_296; + x86::Gp ret_val_get_sew_pow_296 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_296, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_297; + x86::Gp ret_val_get_lmul_pow_297 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_297, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_295, ret_val_get_sew_pow_296), ret_val_get_lmul_pow_297)), 3, true); + setArg(call_get_pow_295, 0, reinterpret_cast(this)); + setArg(call_get_pow_295, 1, EEW); + setRet(call_get_pow_295, 0, ret_val_get_pow_295); + setArg(call_get_sew_pow_296, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_296, 0, ret_val_get_sew_pow_296); + setArg(call_get_lmul_pow_297, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_297, 0, ret_val_get_lmul_pow_297); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_298; + auto illegal_load_298_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_298 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_298, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_298; + setArg(call_illegal_load_298, 0, reinterpret_cast(this)); + setArg(call_illegal_load_298, 1, vd); + setArg(call_illegal_load_298, 2, vm); + setArg(call_illegal_load_298, 3, 2); + setArg(call_illegal_load_298, 4, EEW); + setArg(call_illegal_load_298, 5, illegal_load_298_arg4); + setRet(call_illegal_load_298, 0, ret_val_illegal_load_298); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_299; + auto vlseg_299_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_299_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_299_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_299_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_299 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_299, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_299, 32, false), traits::vstart); + setArg(call_vlseg_299, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_299, 1, V); + setArg(call_vlseg_299, 2, vlseg_299_arg1); + setArg(call_vlseg_299, 3, vlseg_299_arg2); + setArg(call_vlseg_299, 4, vlseg_299_arg3); + setArg(call_vlseg_299, 5, vm); + setArg(call_vlseg_299, 6, vd); + setArg(call_vlseg_299, 7, vlseg_299_arg6); + setArg(call_vlseg_299, 8, 0); + setArg(call_vlseg_299, 9, 2); + setRet(call_vlseg_299, 0, ret_val_vlseg_299); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 167); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 168: VLSEG2E16__V */ + continuation_e __vlseg2e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 168); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_300; + x86::Gp ret_val_get_pow_300 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_300, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_301; + x86::Gp ret_val_get_sew_pow_301 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_301, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_302; + x86::Gp ret_val_get_lmul_pow_302 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_302, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_300, ret_val_get_sew_pow_301), ret_val_get_lmul_pow_302)), 3, true); + setArg(call_get_pow_300, 0, reinterpret_cast(this)); + setArg(call_get_pow_300, 1, EEW); + setRet(call_get_pow_300, 0, ret_val_get_pow_300); + setArg(call_get_sew_pow_301, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_301, 0, ret_val_get_sew_pow_301); + setArg(call_get_lmul_pow_302, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_302, 0, ret_val_get_lmul_pow_302); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_303; + auto illegal_load_303_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_303 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_303, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_303; + setArg(call_illegal_load_303, 0, reinterpret_cast(this)); + setArg(call_illegal_load_303, 1, vd); + setArg(call_illegal_load_303, 2, vm); + setArg(call_illegal_load_303, 3, 2); + setArg(call_illegal_load_303, 4, EEW); + setArg(call_illegal_load_303, 5, illegal_load_303_arg4); + setRet(call_illegal_load_303, 0, ret_val_illegal_load_303); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_304; + auto vlseg_304_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_304_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_304_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_304_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_304 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_304, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_304, 32, false), traits::vstart); + setArg(call_vlseg_304, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_304, 1, V); + setArg(call_vlseg_304, 2, vlseg_304_arg1); + setArg(call_vlseg_304, 3, vlseg_304_arg2); + setArg(call_vlseg_304, 4, vlseg_304_arg3); + setArg(call_vlseg_304, 5, vm); + setArg(call_vlseg_304, 6, vd); + setArg(call_vlseg_304, 7, vlseg_304_arg6); + setArg(call_vlseg_304, 8, 5); + setArg(call_vlseg_304, 9, 2); + setRet(call_vlseg_304, 0, ret_val_vlseg_304); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 168); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 169: VLSEG2E32__V */ + continuation_e __vlseg2e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 169); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_305; + x86::Gp ret_val_get_pow_305 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_305, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_306; + x86::Gp ret_val_get_sew_pow_306 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_306, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_307; + x86::Gp ret_val_get_lmul_pow_307 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_307, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_305, ret_val_get_sew_pow_306), ret_val_get_lmul_pow_307)), 3, true); + setArg(call_get_pow_305, 0, reinterpret_cast(this)); + setArg(call_get_pow_305, 1, EEW); + setRet(call_get_pow_305, 0, ret_val_get_pow_305); + setArg(call_get_sew_pow_306, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_306, 0, ret_val_get_sew_pow_306); + setArg(call_get_lmul_pow_307, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_307, 0, ret_val_get_lmul_pow_307); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_308; + auto illegal_load_308_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_308 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_308, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_308; + setArg(call_illegal_load_308, 0, reinterpret_cast(this)); + setArg(call_illegal_load_308, 1, vd); + setArg(call_illegal_load_308, 2, vm); + setArg(call_illegal_load_308, 3, 2); + setArg(call_illegal_load_308, 4, EEW); + setArg(call_illegal_load_308, 5, illegal_load_308_arg4); + setRet(call_illegal_load_308, 0, ret_val_illegal_load_308); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_309; + auto vlseg_309_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_309_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_309_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_309_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_309 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_309, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_309, 32, false), traits::vstart); + setArg(call_vlseg_309, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_309, 1, V); + setArg(call_vlseg_309, 2, vlseg_309_arg1); + setArg(call_vlseg_309, 3, vlseg_309_arg2); + setArg(call_vlseg_309, 4, vlseg_309_arg3); + setArg(call_vlseg_309, 5, vm); + setArg(call_vlseg_309, 6, vd); + setArg(call_vlseg_309, 7, vlseg_309_arg6); + setArg(call_vlseg_309, 8, 6); + setArg(call_vlseg_309, 9, 2); + setRet(call_vlseg_309, 0, ret_val_vlseg_309); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 169); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 170: VLSEG2E64__V */ + continuation_e __vlseg2e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 170); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_310; + x86::Gp ret_val_get_pow_310 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_310, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_311; + x86::Gp ret_val_get_sew_pow_311 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_311, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_312; + x86::Gp ret_val_get_lmul_pow_312 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_312, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_310, ret_val_get_sew_pow_311), ret_val_get_lmul_pow_312)), 3, true); + setArg(call_get_pow_310, 0, reinterpret_cast(this)); + setArg(call_get_pow_310, 1, EEW); + setRet(call_get_pow_310, 0, ret_val_get_pow_310); + setArg(call_get_sew_pow_311, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_311, 0, ret_val_get_sew_pow_311); + setArg(call_get_lmul_pow_312, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_312, 0, ret_val_get_lmul_pow_312); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_313; + auto illegal_load_313_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_313 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_313, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_313; + setArg(call_illegal_load_313, 0, reinterpret_cast(this)); + setArg(call_illegal_load_313, 1, vd); + setArg(call_illegal_load_313, 2, vm); + setArg(call_illegal_load_313, 3, 2); + setArg(call_illegal_load_313, 4, EEW); + setArg(call_illegal_load_313, 5, illegal_load_313_arg4); + setRet(call_illegal_load_313, 0, ret_val_illegal_load_313); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_314; + auto vlseg_314_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_314_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_314_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_314_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_314 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_314, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_314, 32, false), traits::vstart); + setArg(call_vlseg_314, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_314, 1, V); + setArg(call_vlseg_314, 2, vlseg_314_arg1); + setArg(call_vlseg_314, 3, vlseg_314_arg2); + setArg(call_vlseg_314, 4, vlseg_314_arg3); + setArg(call_vlseg_314, 5, vm); + setArg(call_vlseg_314, 6, vd); + setArg(call_vlseg_314, 7, vlseg_314_arg6); + setArg(call_vlseg_314, 8, 7); + setArg(call_vlseg_314, 9, 2); + setRet(call_vlseg_314, 0, ret_val_vlseg_314); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 170); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 171: VLSEG3E8__V */ + continuation_e __vlseg3e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 171); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_315; + x86::Gp ret_val_get_pow_315 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_315, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_316; + x86::Gp ret_val_get_sew_pow_316 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_316, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_317; + x86::Gp ret_val_get_lmul_pow_317 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_317, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_315, ret_val_get_sew_pow_316), ret_val_get_lmul_pow_317)), 3, true); + setArg(call_get_pow_315, 0, reinterpret_cast(this)); + setArg(call_get_pow_315, 1, EEW); + setRet(call_get_pow_315, 0, ret_val_get_pow_315); + setArg(call_get_sew_pow_316, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_316, 0, ret_val_get_sew_pow_316); + setArg(call_get_lmul_pow_317, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_317, 0, ret_val_get_lmul_pow_317); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_318; + auto illegal_load_318_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_318 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_318, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_318; + setArg(call_illegal_load_318, 0, reinterpret_cast(this)); + setArg(call_illegal_load_318, 1, vd); + setArg(call_illegal_load_318, 2, vm); + setArg(call_illegal_load_318, 3, 3); + setArg(call_illegal_load_318, 4, EEW); + setArg(call_illegal_load_318, 5, illegal_load_318_arg4); + setRet(call_illegal_load_318, 0, ret_val_illegal_load_318); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_319; + auto vlseg_319_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_319_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_319_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_319_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_319 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_319, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_319, 32, false), traits::vstart); + setArg(call_vlseg_319, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_319, 1, V); + setArg(call_vlseg_319, 2, vlseg_319_arg1); + setArg(call_vlseg_319, 3, vlseg_319_arg2); + setArg(call_vlseg_319, 4, vlseg_319_arg3); + setArg(call_vlseg_319, 5, vm); + setArg(call_vlseg_319, 6, vd); + setArg(call_vlseg_319, 7, vlseg_319_arg6); + setArg(call_vlseg_319, 8, 0); + setArg(call_vlseg_319, 9, 3); + setRet(call_vlseg_319, 0, ret_val_vlseg_319); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 171); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 172: VLSEG3E16__V */ + continuation_e __vlseg3e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 172); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_320; + x86::Gp ret_val_get_pow_320 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_320, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_321; + x86::Gp ret_val_get_sew_pow_321 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_321, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_322; + x86::Gp ret_val_get_lmul_pow_322 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_322, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_320, ret_val_get_sew_pow_321), ret_val_get_lmul_pow_322)), 3, true); + setArg(call_get_pow_320, 0, reinterpret_cast(this)); + setArg(call_get_pow_320, 1, EEW); + setRet(call_get_pow_320, 0, ret_val_get_pow_320); + setArg(call_get_sew_pow_321, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_321, 0, ret_val_get_sew_pow_321); + setArg(call_get_lmul_pow_322, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_322, 0, ret_val_get_lmul_pow_322); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_323; + auto illegal_load_323_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_323 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_323, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_323; + setArg(call_illegal_load_323, 0, reinterpret_cast(this)); + setArg(call_illegal_load_323, 1, vd); + setArg(call_illegal_load_323, 2, vm); + setArg(call_illegal_load_323, 3, 3); + setArg(call_illegal_load_323, 4, EEW); + setArg(call_illegal_load_323, 5, illegal_load_323_arg4); + setRet(call_illegal_load_323, 0, ret_val_illegal_load_323); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_324; + auto vlseg_324_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_324_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_324_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_324_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_324 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_324, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_324, 32, false), traits::vstart); + setArg(call_vlseg_324, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_324, 1, V); + setArg(call_vlseg_324, 2, vlseg_324_arg1); + setArg(call_vlseg_324, 3, vlseg_324_arg2); + setArg(call_vlseg_324, 4, vlseg_324_arg3); + setArg(call_vlseg_324, 5, vm); + setArg(call_vlseg_324, 6, vd); + setArg(call_vlseg_324, 7, vlseg_324_arg6); + setArg(call_vlseg_324, 8, 5); + setArg(call_vlseg_324, 9, 3); + setRet(call_vlseg_324, 0, ret_val_vlseg_324); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 172); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 173: VLSEG3E32__V */ + continuation_e __vlseg3e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 173); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_325; + x86::Gp ret_val_get_pow_325 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_325, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_326; + x86::Gp ret_val_get_sew_pow_326 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_326, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_327; + x86::Gp ret_val_get_lmul_pow_327 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_327, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_325, ret_val_get_sew_pow_326), ret_val_get_lmul_pow_327)), 3, true); + setArg(call_get_pow_325, 0, reinterpret_cast(this)); + setArg(call_get_pow_325, 1, EEW); + setRet(call_get_pow_325, 0, ret_val_get_pow_325); + setArg(call_get_sew_pow_326, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_326, 0, ret_val_get_sew_pow_326); + setArg(call_get_lmul_pow_327, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_327, 0, ret_val_get_lmul_pow_327); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_328; + auto illegal_load_328_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_328 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_328, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_328; + setArg(call_illegal_load_328, 0, reinterpret_cast(this)); + setArg(call_illegal_load_328, 1, vd); + setArg(call_illegal_load_328, 2, vm); + setArg(call_illegal_load_328, 3, 3); + setArg(call_illegal_load_328, 4, EEW); + setArg(call_illegal_load_328, 5, illegal_load_328_arg4); + setRet(call_illegal_load_328, 0, ret_val_illegal_load_328); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_329; + auto vlseg_329_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_329_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_329_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_329_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_329 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_329, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_329, 32, false), traits::vstart); + setArg(call_vlseg_329, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_329, 1, V); + setArg(call_vlseg_329, 2, vlseg_329_arg1); + setArg(call_vlseg_329, 3, vlseg_329_arg2); + setArg(call_vlseg_329, 4, vlseg_329_arg3); + setArg(call_vlseg_329, 5, vm); + setArg(call_vlseg_329, 6, vd); + setArg(call_vlseg_329, 7, vlseg_329_arg6); + setArg(call_vlseg_329, 8, 6); + setArg(call_vlseg_329, 9, 3); + setRet(call_vlseg_329, 0, ret_val_vlseg_329); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 173); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 174: VLSEG3E64__V */ + continuation_e __vlseg3e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 174); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_330; + x86::Gp ret_val_get_pow_330 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_330, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_331; + x86::Gp ret_val_get_sew_pow_331 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_331, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_332; + x86::Gp ret_val_get_lmul_pow_332 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_332, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_330, ret_val_get_sew_pow_331), ret_val_get_lmul_pow_332)), 3, true); + setArg(call_get_pow_330, 0, reinterpret_cast(this)); + setArg(call_get_pow_330, 1, EEW); + setRet(call_get_pow_330, 0, ret_val_get_pow_330); + setArg(call_get_sew_pow_331, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_331, 0, ret_val_get_sew_pow_331); + setArg(call_get_lmul_pow_332, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_332, 0, ret_val_get_lmul_pow_332); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_333; + auto illegal_load_333_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_333 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_333, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_333; + setArg(call_illegal_load_333, 0, reinterpret_cast(this)); + setArg(call_illegal_load_333, 1, vd); + setArg(call_illegal_load_333, 2, vm); + setArg(call_illegal_load_333, 3, 3); + setArg(call_illegal_load_333, 4, EEW); + setArg(call_illegal_load_333, 5, illegal_load_333_arg4); + setRet(call_illegal_load_333, 0, ret_val_illegal_load_333); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_334; + auto vlseg_334_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_334_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_334_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_334_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_334 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_334, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_334, 32, false), traits::vstart); + setArg(call_vlseg_334, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_334, 1, V); + setArg(call_vlseg_334, 2, vlseg_334_arg1); + setArg(call_vlseg_334, 3, vlseg_334_arg2); + setArg(call_vlseg_334, 4, vlseg_334_arg3); + setArg(call_vlseg_334, 5, vm); + setArg(call_vlseg_334, 6, vd); + setArg(call_vlseg_334, 7, vlseg_334_arg6); + setArg(call_vlseg_334, 8, 7); + setArg(call_vlseg_334, 9, 3); + setRet(call_vlseg_334, 0, ret_val_vlseg_334); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 174); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 175: VLSEG4E8__V */ + continuation_e __vlseg4e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 175); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_335; + x86::Gp ret_val_get_pow_335 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_335, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_336; + x86::Gp ret_val_get_sew_pow_336 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_336, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_337; + x86::Gp ret_val_get_lmul_pow_337 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_337, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_335, ret_val_get_sew_pow_336), ret_val_get_lmul_pow_337)), 3, true); + setArg(call_get_pow_335, 0, reinterpret_cast(this)); + setArg(call_get_pow_335, 1, EEW); + setRet(call_get_pow_335, 0, ret_val_get_pow_335); + setArg(call_get_sew_pow_336, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_336, 0, ret_val_get_sew_pow_336); + setArg(call_get_lmul_pow_337, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_337, 0, ret_val_get_lmul_pow_337); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_338; + auto illegal_load_338_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_338 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_338, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_338; + setArg(call_illegal_load_338, 0, reinterpret_cast(this)); + setArg(call_illegal_load_338, 1, vd); + setArg(call_illegal_load_338, 2, vm); + setArg(call_illegal_load_338, 3, 4); + setArg(call_illegal_load_338, 4, EEW); + setArg(call_illegal_load_338, 5, illegal_load_338_arg4); + setRet(call_illegal_load_338, 0, ret_val_illegal_load_338); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_339; + auto vlseg_339_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_339_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_339_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_339_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_339 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_339, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_339, 32, false), traits::vstart); + setArg(call_vlseg_339, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_339, 1, V); + setArg(call_vlseg_339, 2, vlseg_339_arg1); + setArg(call_vlseg_339, 3, vlseg_339_arg2); + setArg(call_vlseg_339, 4, vlseg_339_arg3); + setArg(call_vlseg_339, 5, vm); + setArg(call_vlseg_339, 6, vd); + setArg(call_vlseg_339, 7, vlseg_339_arg6); + setArg(call_vlseg_339, 8, 0); + setArg(call_vlseg_339, 9, 4); + setRet(call_vlseg_339, 0, ret_val_vlseg_339); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 175); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 176: VLSEG4E16__V */ + continuation_e __vlseg4e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 176); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_340; + x86::Gp ret_val_get_pow_340 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_340, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_341; + x86::Gp ret_val_get_sew_pow_341 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_341, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_342; + x86::Gp ret_val_get_lmul_pow_342 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_342, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_340, ret_val_get_sew_pow_341), ret_val_get_lmul_pow_342)), 3, true); + setArg(call_get_pow_340, 0, reinterpret_cast(this)); + setArg(call_get_pow_340, 1, EEW); + setRet(call_get_pow_340, 0, ret_val_get_pow_340); + setArg(call_get_sew_pow_341, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_341, 0, ret_val_get_sew_pow_341); + setArg(call_get_lmul_pow_342, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_342, 0, ret_val_get_lmul_pow_342); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_343; + auto illegal_load_343_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_343 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_343, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_343; + setArg(call_illegal_load_343, 0, reinterpret_cast(this)); + setArg(call_illegal_load_343, 1, vd); + setArg(call_illegal_load_343, 2, vm); + setArg(call_illegal_load_343, 3, 4); + setArg(call_illegal_load_343, 4, EEW); + setArg(call_illegal_load_343, 5, illegal_load_343_arg4); + setRet(call_illegal_load_343, 0, ret_val_illegal_load_343); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_344; + auto vlseg_344_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_344_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_344_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_344_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_344 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_344, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_344, 32, false), traits::vstart); + setArg(call_vlseg_344, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_344, 1, V); + setArg(call_vlseg_344, 2, vlseg_344_arg1); + setArg(call_vlseg_344, 3, vlseg_344_arg2); + setArg(call_vlseg_344, 4, vlseg_344_arg3); + setArg(call_vlseg_344, 5, vm); + setArg(call_vlseg_344, 6, vd); + setArg(call_vlseg_344, 7, vlseg_344_arg6); + setArg(call_vlseg_344, 8, 5); + setArg(call_vlseg_344, 9, 4); + setRet(call_vlseg_344, 0, ret_val_vlseg_344); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 176); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 177: VLSEG4E32__V */ + continuation_e __vlseg4e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 177); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_345; + x86::Gp ret_val_get_pow_345 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_345, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_346; + x86::Gp ret_val_get_sew_pow_346 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_346, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_347; + x86::Gp ret_val_get_lmul_pow_347 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_347, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_345, ret_val_get_sew_pow_346), ret_val_get_lmul_pow_347)), 3, true); + setArg(call_get_pow_345, 0, reinterpret_cast(this)); + setArg(call_get_pow_345, 1, EEW); + setRet(call_get_pow_345, 0, ret_val_get_pow_345); + setArg(call_get_sew_pow_346, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_346, 0, ret_val_get_sew_pow_346); + setArg(call_get_lmul_pow_347, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_347, 0, ret_val_get_lmul_pow_347); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_348; + auto illegal_load_348_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_348 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_348, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_348; + setArg(call_illegal_load_348, 0, reinterpret_cast(this)); + setArg(call_illegal_load_348, 1, vd); + setArg(call_illegal_load_348, 2, vm); + setArg(call_illegal_load_348, 3, 4); + setArg(call_illegal_load_348, 4, EEW); + setArg(call_illegal_load_348, 5, illegal_load_348_arg4); + setRet(call_illegal_load_348, 0, ret_val_illegal_load_348); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_349; + auto vlseg_349_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_349_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_349_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_349_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_349 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_349, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_349, 32, false), traits::vstart); + setArg(call_vlseg_349, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_349, 1, V); + setArg(call_vlseg_349, 2, vlseg_349_arg1); + setArg(call_vlseg_349, 3, vlseg_349_arg2); + setArg(call_vlseg_349, 4, vlseg_349_arg3); + setArg(call_vlseg_349, 5, vm); + setArg(call_vlseg_349, 6, vd); + setArg(call_vlseg_349, 7, vlseg_349_arg6); + setArg(call_vlseg_349, 8, 6); + setArg(call_vlseg_349, 9, 4); + setRet(call_vlseg_349, 0, ret_val_vlseg_349); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 177); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 178: VLSEG4E64__V */ + continuation_e __vlseg4e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 178); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_350; + x86::Gp ret_val_get_pow_350 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_350, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_351; + x86::Gp ret_val_get_sew_pow_351 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_351, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_352; + x86::Gp ret_val_get_lmul_pow_352 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_352, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_350, ret_val_get_sew_pow_351), ret_val_get_lmul_pow_352)), 3, true); + setArg(call_get_pow_350, 0, reinterpret_cast(this)); + setArg(call_get_pow_350, 1, EEW); + setRet(call_get_pow_350, 0, ret_val_get_pow_350); + setArg(call_get_sew_pow_351, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_351, 0, ret_val_get_sew_pow_351); + setArg(call_get_lmul_pow_352, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_352, 0, ret_val_get_lmul_pow_352); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_353; + auto illegal_load_353_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_353 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_353, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_353; + setArg(call_illegal_load_353, 0, reinterpret_cast(this)); + setArg(call_illegal_load_353, 1, vd); + setArg(call_illegal_load_353, 2, vm); + setArg(call_illegal_load_353, 3, 4); + setArg(call_illegal_load_353, 4, EEW); + setArg(call_illegal_load_353, 5, illegal_load_353_arg4); + setRet(call_illegal_load_353, 0, ret_val_illegal_load_353); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_354; + auto vlseg_354_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_354_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_354_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_354_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_354 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_354, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_354, 32, false), traits::vstart); + setArg(call_vlseg_354, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_354, 1, V); + setArg(call_vlseg_354, 2, vlseg_354_arg1); + setArg(call_vlseg_354, 3, vlseg_354_arg2); + setArg(call_vlseg_354, 4, vlseg_354_arg3); + setArg(call_vlseg_354, 5, vm); + setArg(call_vlseg_354, 6, vd); + setArg(call_vlseg_354, 7, vlseg_354_arg6); + setArg(call_vlseg_354, 8, 7); + setArg(call_vlseg_354, 9, 4); + setRet(call_vlseg_354, 0, ret_val_vlseg_354); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 178); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 179: VLSEG5E8__V */ + continuation_e __vlseg5e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 179); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_355; + x86::Gp ret_val_get_pow_355 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_355, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_356; + x86::Gp ret_val_get_sew_pow_356 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_356, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_357; + x86::Gp ret_val_get_lmul_pow_357 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_357, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_355, ret_val_get_sew_pow_356), ret_val_get_lmul_pow_357)), 3, true); + setArg(call_get_pow_355, 0, reinterpret_cast(this)); + setArg(call_get_pow_355, 1, EEW); + setRet(call_get_pow_355, 0, ret_val_get_pow_355); + setArg(call_get_sew_pow_356, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_356, 0, ret_val_get_sew_pow_356); + setArg(call_get_lmul_pow_357, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_357, 0, ret_val_get_lmul_pow_357); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_358; + auto illegal_load_358_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_358 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_358, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_358; + setArg(call_illegal_load_358, 0, reinterpret_cast(this)); + setArg(call_illegal_load_358, 1, vd); + setArg(call_illegal_load_358, 2, vm); + setArg(call_illegal_load_358, 3, 5); + setArg(call_illegal_load_358, 4, EEW); + setArg(call_illegal_load_358, 5, illegal_load_358_arg4); + setRet(call_illegal_load_358, 0, ret_val_illegal_load_358); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_359; + auto vlseg_359_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_359_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_359_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_359_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_359 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_359, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_359, 32, false), traits::vstart); + setArg(call_vlseg_359, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_359, 1, V); + setArg(call_vlseg_359, 2, vlseg_359_arg1); + setArg(call_vlseg_359, 3, vlseg_359_arg2); + setArg(call_vlseg_359, 4, vlseg_359_arg3); + setArg(call_vlseg_359, 5, vm); + setArg(call_vlseg_359, 6, vd); + setArg(call_vlseg_359, 7, vlseg_359_arg6); + setArg(call_vlseg_359, 8, 0); + setArg(call_vlseg_359, 9, 5); + setRet(call_vlseg_359, 0, ret_val_vlseg_359); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 179); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 180: VLSEG5E16__V */ + continuation_e __vlseg5e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 180); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_360; + x86::Gp ret_val_get_pow_360 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_360, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_361; + x86::Gp ret_val_get_sew_pow_361 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_361, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_362; + x86::Gp ret_val_get_lmul_pow_362 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_362, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_360, ret_val_get_sew_pow_361), ret_val_get_lmul_pow_362)), 3, true); + setArg(call_get_pow_360, 0, reinterpret_cast(this)); + setArg(call_get_pow_360, 1, EEW); + setRet(call_get_pow_360, 0, ret_val_get_pow_360); + setArg(call_get_sew_pow_361, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_361, 0, ret_val_get_sew_pow_361); + setArg(call_get_lmul_pow_362, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_362, 0, ret_val_get_lmul_pow_362); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_363; + auto illegal_load_363_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_363 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_363, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_363; + setArg(call_illegal_load_363, 0, reinterpret_cast(this)); + setArg(call_illegal_load_363, 1, vd); + setArg(call_illegal_load_363, 2, vm); + setArg(call_illegal_load_363, 3, 5); + setArg(call_illegal_load_363, 4, EEW); + setArg(call_illegal_load_363, 5, illegal_load_363_arg4); + setRet(call_illegal_load_363, 0, ret_val_illegal_load_363); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_364; + auto vlseg_364_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_364_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_364_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_364_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_364 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_364, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_364, 32, false), traits::vstart); + setArg(call_vlseg_364, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_364, 1, V); + setArg(call_vlseg_364, 2, vlseg_364_arg1); + setArg(call_vlseg_364, 3, vlseg_364_arg2); + setArg(call_vlseg_364, 4, vlseg_364_arg3); + setArg(call_vlseg_364, 5, vm); + setArg(call_vlseg_364, 6, vd); + setArg(call_vlseg_364, 7, vlseg_364_arg6); + setArg(call_vlseg_364, 8, 5); + setArg(call_vlseg_364, 9, 5); + setRet(call_vlseg_364, 0, ret_val_vlseg_364); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 180); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 181: VLSEG5E32__V */ + continuation_e __vlseg5e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 181); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_365; + x86::Gp ret_val_get_pow_365 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_365, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_366; + x86::Gp ret_val_get_sew_pow_366 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_366, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_367; + x86::Gp ret_val_get_lmul_pow_367 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_367, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_365, ret_val_get_sew_pow_366), ret_val_get_lmul_pow_367)), 3, true); + setArg(call_get_pow_365, 0, reinterpret_cast(this)); + setArg(call_get_pow_365, 1, EEW); + setRet(call_get_pow_365, 0, ret_val_get_pow_365); + setArg(call_get_sew_pow_366, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_366, 0, ret_val_get_sew_pow_366); + setArg(call_get_lmul_pow_367, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_367, 0, ret_val_get_lmul_pow_367); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_368; + auto illegal_load_368_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_368 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_368, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_368; + setArg(call_illegal_load_368, 0, reinterpret_cast(this)); + setArg(call_illegal_load_368, 1, vd); + setArg(call_illegal_load_368, 2, vm); + setArg(call_illegal_load_368, 3, 5); + setArg(call_illegal_load_368, 4, EEW); + setArg(call_illegal_load_368, 5, illegal_load_368_arg4); + setRet(call_illegal_load_368, 0, ret_val_illegal_load_368); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_369; + auto vlseg_369_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_369_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_369_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_369_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_369 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_369, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_369, 32, false), traits::vstart); + setArg(call_vlseg_369, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_369, 1, V); + setArg(call_vlseg_369, 2, vlseg_369_arg1); + setArg(call_vlseg_369, 3, vlseg_369_arg2); + setArg(call_vlseg_369, 4, vlseg_369_arg3); + setArg(call_vlseg_369, 5, vm); + setArg(call_vlseg_369, 6, vd); + setArg(call_vlseg_369, 7, vlseg_369_arg6); + setArg(call_vlseg_369, 8, 6); + setArg(call_vlseg_369, 9, 5); + setRet(call_vlseg_369, 0, ret_val_vlseg_369); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 181); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 182: VLSEG5E64__V */ + continuation_e __vlseg5e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 182); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_370; + x86::Gp ret_val_get_pow_370 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_370, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_371; + x86::Gp ret_val_get_sew_pow_371 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_371, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_372; + x86::Gp ret_val_get_lmul_pow_372 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_372, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_370, ret_val_get_sew_pow_371), ret_val_get_lmul_pow_372)), 3, true); + setArg(call_get_pow_370, 0, reinterpret_cast(this)); + setArg(call_get_pow_370, 1, EEW); + setRet(call_get_pow_370, 0, ret_val_get_pow_370); + setArg(call_get_sew_pow_371, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_371, 0, ret_val_get_sew_pow_371); + setArg(call_get_lmul_pow_372, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_372, 0, ret_val_get_lmul_pow_372); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_373; + auto illegal_load_373_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_373 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_373, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_373; + setArg(call_illegal_load_373, 0, reinterpret_cast(this)); + setArg(call_illegal_load_373, 1, vd); + setArg(call_illegal_load_373, 2, vm); + setArg(call_illegal_load_373, 3, 5); + setArg(call_illegal_load_373, 4, EEW); + setArg(call_illegal_load_373, 5, illegal_load_373_arg4); + setRet(call_illegal_load_373, 0, ret_val_illegal_load_373); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_374; + auto vlseg_374_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_374_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_374_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_374_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_374 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_374, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_374, 32, false), traits::vstart); + setArg(call_vlseg_374, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_374, 1, V); + setArg(call_vlseg_374, 2, vlseg_374_arg1); + setArg(call_vlseg_374, 3, vlseg_374_arg2); + setArg(call_vlseg_374, 4, vlseg_374_arg3); + setArg(call_vlseg_374, 5, vm); + setArg(call_vlseg_374, 6, vd); + setArg(call_vlseg_374, 7, vlseg_374_arg6); + setArg(call_vlseg_374, 8, 7); + setArg(call_vlseg_374, 9, 5); + setRet(call_vlseg_374, 0, ret_val_vlseg_374); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 182); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 183: VLSEG6E8__V */ + continuation_e __vlseg6e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 183); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_375; + x86::Gp ret_val_get_pow_375 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_375, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_376; + x86::Gp ret_val_get_sew_pow_376 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_376, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_377; + x86::Gp ret_val_get_lmul_pow_377 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_377, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_375, ret_val_get_sew_pow_376), ret_val_get_lmul_pow_377)), 3, true); + setArg(call_get_pow_375, 0, reinterpret_cast(this)); + setArg(call_get_pow_375, 1, EEW); + setRet(call_get_pow_375, 0, ret_val_get_pow_375); + setArg(call_get_sew_pow_376, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_376, 0, ret_val_get_sew_pow_376); + setArg(call_get_lmul_pow_377, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_377, 0, ret_val_get_lmul_pow_377); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_378; + auto illegal_load_378_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_378 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_378, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_378; + setArg(call_illegal_load_378, 0, reinterpret_cast(this)); + setArg(call_illegal_load_378, 1, vd); + setArg(call_illegal_load_378, 2, vm); + setArg(call_illegal_load_378, 3, 6); + setArg(call_illegal_load_378, 4, EEW); + setArg(call_illegal_load_378, 5, illegal_load_378_arg4); + setRet(call_illegal_load_378, 0, ret_val_illegal_load_378); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_379; + auto vlseg_379_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_379_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_379_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_379_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_379 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_379, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_379, 32, false), traits::vstart); + setArg(call_vlseg_379, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_379, 1, V); + setArg(call_vlseg_379, 2, vlseg_379_arg1); + setArg(call_vlseg_379, 3, vlseg_379_arg2); + setArg(call_vlseg_379, 4, vlseg_379_arg3); + setArg(call_vlseg_379, 5, vm); + setArg(call_vlseg_379, 6, vd); + setArg(call_vlseg_379, 7, vlseg_379_arg6); + setArg(call_vlseg_379, 8, 0); + setArg(call_vlseg_379, 9, 6); + setRet(call_vlseg_379, 0, ret_val_vlseg_379); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 183); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 184: VLSEG6E16__V */ + continuation_e __vlseg6e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 184); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_380; + x86::Gp ret_val_get_pow_380 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_380, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_381; + x86::Gp ret_val_get_sew_pow_381 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_381, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_382; + x86::Gp ret_val_get_lmul_pow_382 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_382, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_380, ret_val_get_sew_pow_381), ret_val_get_lmul_pow_382)), 3, true); + setArg(call_get_pow_380, 0, reinterpret_cast(this)); + setArg(call_get_pow_380, 1, EEW); + setRet(call_get_pow_380, 0, ret_val_get_pow_380); + setArg(call_get_sew_pow_381, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_381, 0, ret_val_get_sew_pow_381); + setArg(call_get_lmul_pow_382, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_382, 0, ret_val_get_lmul_pow_382); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_383; + auto illegal_load_383_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_383 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_383, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_383; + setArg(call_illegal_load_383, 0, reinterpret_cast(this)); + setArg(call_illegal_load_383, 1, vd); + setArg(call_illegal_load_383, 2, vm); + setArg(call_illegal_load_383, 3, 6); + setArg(call_illegal_load_383, 4, EEW); + setArg(call_illegal_load_383, 5, illegal_load_383_arg4); + setRet(call_illegal_load_383, 0, ret_val_illegal_load_383); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_384; + auto vlseg_384_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_384_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_384_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_384_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_384 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_384, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_384, 32, false), traits::vstart); + setArg(call_vlseg_384, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_384, 1, V); + setArg(call_vlseg_384, 2, vlseg_384_arg1); + setArg(call_vlseg_384, 3, vlseg_384_arg2); + setArg(call_vlseg_384, 4, vlseg_384_arg3); + setArg(call_vlseg_384, 5, vm); + setArg(call_vlseg_384, 6, vd); + setArg(call_vlseg_384, 7, vlseg_384_arg6); + setArg(call_vlseg_384, 8, 5); + setArg(call_vlseg_384, 9, 6); + setRet(call_vlseg_384, 0, ret_val_vlseg_384); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 184); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 185: VLSEG6E32__V */ + continuation_e __vlseg6e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 185); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_385; + x86::Gp ret_val_get_pow_385 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_385, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_386; + x86::Gp ret_val_get_sew_pow_386 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_386, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_387; + x86::Gp ret_val_get_lmul_pow_387 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_387, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_385, ret_val_get_sew_pow_386), ret_val_get_lmul_pow_387)), 3, true); + setArg(call_get_pow_385, 0, reinterpret_cast(this)); + setArg(call_get_pow_385, 1, EEW); + setRet(call_get_pow_385, 0, ret_val_get_pow_385); + setArg(call_get_sew_pow_386, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_386, 0, ret_val_get_sew_pow_386); + setArg(call_get_lmul_pow_387, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_387, 0, ret_val_get_lmul_pow_387); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_388; + auto illegal_load_388_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_388 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_388, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_388; + setArg(call_illegal_load_388, 0, reinterpret_cast(this)); + setArg(call_illegal_load_388, 1, vd); + setArg(call_illegal_load_388, 2, vm); + setArg(call_illegal_load_388, 3, 6); + setArg(call_illegal_load_388, 4, EEW); + setArg(call_illegal_load_388, 5, illegal_load_388_arg4); + setRet(call_illegal_load_388, 0, ret_val_illegal_load_388); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_389; + auto vlseg_389_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_389_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_389_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_389_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_389 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_389, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_389, 32, false), traits::vstart); + setArg(call_vlseg_389, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_389, 1, V); + setArg(call_vlseg_389, 2, vlseg_389_arg1); + setArg(call_vlseg_389, 3, vlseg_389_arg2); + setArg(call_vlseg_389, 4, vlseg_389_arg3); + setArg(call_vlseg_389, 5, vm); + setArg(call_vlseg_389, 6, vd); + setArg(call_vlseg_389, 7, vlseg_389_arg6); + setArg(call_vlseg_389, 8, 6); + setArg(call_vlseg_389, 9, 6); + setRet(call_vlseg_389, 0, ret_val_vlseg_389); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 185); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 186: VLSEG6E64__V */ + continuation_e __vlseg6e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 186); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_390; + x86::Gp ret_val_get_pow_390 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_390, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_391; + x86::Gp ret_val_get_sew_pow_391 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_391, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_392; + x86::Gp ret_val_get_lmul_pow_392 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_392, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_390, ret_val_get_sew_pow_391), ret_val_get_lmul_pow_392)), 3, true); + setArg(call_get_pow_390, 0, reinterpret_cast(this)); + setArg(call_get_pow_390, 1, EEW); + setRet(call_get_pow_390, 0, ret_val_get_pow_390); + setArg(call_get_sew_pow_391, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_391, 0, ret_val_get_sew_pow_391); + setArg(call_get_lmul_pow_392, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_392, 0, ret_val_get_lmul_pow_392); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_393; + auto illegal_load_393_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_393 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_393, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_393; + setArg(call_illegal_load_393, 0, reinterpret_cast(this)); + setArg(call_illegal_load_393, 1, vd); + setArg(call_illegal_load_393, 2, vm); + setArg(call_illegal_load_393, 3, 6); + setArg(call_illegal_load_393, 4, EEW); + setArg(call_illegal_load_393, 5, illegal_load_393_arg4); + setRet(call_illegal_load_393, 0, ret_val_illegal_load_393); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_394; + auto vlseg_394_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_394_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_394_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_394_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_394 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_394, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_394, 32, false), traits::vstart); + setArg(call_vlseg_394, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_394, 1, V); + setArg(call_vlseg_394, 2, vlseg_394_arg1); + setArg(call_vlseg_394, 3, vlseg_394_arg2); + setArg(call_vlseg_394, 4, vlseg_394_arg3); + setArg(call_vlseg_394, 5, vm); + setArg(call_vlseg_394, 6, vd); + setArg(call_vlseg_394, 7, vlseg_394_arg6); + setArg(call_vlseg_394, 8, 7); + setArg(call_vlseg_394, 9, 6); + setRet(call_vlseg_394, 0, ret_val_vlseg_394); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 186); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 187: VLSEG7E8__V */ + continuation_e __vlseg7e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 187); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_395; + x86::Gp ret_val_get_pow_395 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_395, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_396; + x86::Gp ret_val_get_sew_pow_396 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_396, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_397; + x86::Gp ret_val_get_lmul_pow_397 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_397, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_395, ret_val_get_sew_pow_396), ret_val_get_lmul_pow_397)), 3, true); + setArg(call_get_pow_395, 0, reinterpret_cast(this)); + setArg(call_get_pow_395, 1, EEW); + setRet(call_get_pow_395, 0, ret_val_get_pow_395); + setArg(call_get_sew_pow_396, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_396, 0, ret_val_get_sew_pow_396); + setArg(call_get_lmul_pow_397, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_397, 0, ret_val_get_lmul_pow_397); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_398; + auto illegal_load_398_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_398 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_398, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_398; + setArg(call_illegal_load_398, 0, reinterpret_cast(this)); + setArg(call_illegal_load_398, 1, vd); + setArg(call_illegal_load_398, 2, vm); + setArg(call_illegal_load_398, 3, 7); + setArg(call_illegal_load_398, 4, EEW); + setArg(call_illegal_load_398, 5, illegal_load_398_arg4); + setRet(call_illegal_load_398, 0, ret_val_illegal_load_398); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_399; + auto vlseg_399_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_399_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_399_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_399_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_399 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_399, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_399, 32, false), traits::vstart); + setArg(call_vlseg_399, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_399, 1, V); + setArg(call_vlseg_399, 2, vlseg_399_arg1); + setArg(call_vlseg_399, 3, vlseg_399_arg2); + setArg(call_vlseg_399, 4, vlseg_399_arg3); + setArg(call_vlseg_399, 5, vm); + setArg(call_vlseg_399, 6, vd); + setArg(call_vlseg_399, 7, vlseg_399_arg6); + setArg(call_vlseg_399, 8, 0); + setArg(call_vlseg_399, 9, 7); + setRet(call_vlseg_399, 0, ret_val_vlseg_399); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 187); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 188: VLSEG7E16__V */ + continuation_e __vlseg7e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 188); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_400; + x86::Gp ret_val_get_pow_400 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_400, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_401; + x86::Gp ret_val_get_sew_pow_401 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_401, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_402; + x86::Gp ret_val_get_lmul_pow_402 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_402, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_400, ret_val_get_sew_pow_401), ret_val_get_lmul_pow_402)), 3, true); + setArg(call_get_pow_400, 0, reinterpret_cast(this)); + setArg(call_get_pow_400, 1, EEW); + setRet(call_get_pow_400, 0, ret_val_get_pow_400); + setArg(call_get_sew_pow_401, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_401, 0, ret_val_get_sew_pow_401); + setArg(call_get_lmul_pow_402, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_402, 0, ret_val_get_lmul_pow_402); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_403; + auto illegal_load_403_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_403 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_403, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_403; + setArg(call_illegal_load_403, 0, reinterpret_cast(this)); + setArg(call_illegal_load_403, 1, vd); + setArg(call_illegal_load_403, 2, vm); + setArg(call_illegal_load_403, 3, 7); + setArg(call_illegal_load_403, 4, EEW); + setArg(call_illegal_load_403, 5, illegal_load_403_arg4); + setRet(call_illegal_load_403, 0, ret_val_illegal_load_403); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_404; + auto vlseg_404_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_404_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_404_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_404_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_404 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_404, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_404, 32, false), traits::vstart); + setArg(call_vlseg_404, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_404, 1, V); + setArg(call_vlseg_404, 2, vlseg_404_arg1); + setArg(call_vlseg_404, 3, vlseg_404_arg2); + setArg(call_vlseg_404, 4, vlseg_404_arg3); + setArg(call_vlseg_404, 5, vm); + setArg(call_vlseg_404, 6, vd); + setArg(call_vlseg_404, 7, vlseg_404_arg6); + setArg(call_vlseg_404, 8, 5); + setArg(call_vlseg_404, 9, 7); + setRet(call_vlseg_404, 0, ret_val_vlseg_404); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 188); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 189: VLSEG7E32__V */ + continuation_e __vlseg7e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 189); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_405; + x86::Gp ret_val_get_pow_405 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_405, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_406; + x86::Gp ret_val_get_sew_pow_406 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_406, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_407; + x86::Gp ret_val_get_lmul_pow_407 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_407, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_405, ret_val_get_sew_pow_406), ret_val_get_lmul_pow_407)), 3, true); + setArg(call_get_pow_405, 0, reinterpret_cast(this)); + setArg(call_get_pow_405, 1, EEW); + setRet(call_get_pow_405, 0, ret_val_get_pow_405); + setArg(call_get_sew_pow_406, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_406, 0, ret_val_get_sew_pow_406); + setArg(call_get_lmul_pow_407, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_407, 0, ret_val_get_lmul_pow_407); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_408; + auto illegal_load_408_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_408 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_408, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_408; + setArg(call_illegal_load_408, 0, reinterpret_cast(this)); + setArg(call_illegal_load_408, 1, vd); + setArg(call_illegal_load_408, 2, vm); + setArg(call_illegal_load_408, 3, 7); + setArg(call_illegal_load_408, 4, EEW); + setArg(call_illegal_load_408, 5, illegal_load_408_arg4); + setRet(call_illegal_load_408, 0, ret_val_illegal_load_408); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_409; + auto vlseg_409_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_409_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_409_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_409_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_409 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_409, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_409, 32, false), traits::vstart); + setArg(call_vlseg_409, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_409, 1, V); + setArg(call_vlseg_409, 2, vlseg_409_arg1); + setArg(call_vlseg_409, 3, vlseg_409_arg2); + setArg(call_vlseg_409, 4, vlseg_409_arg3); + setArg(call_vlseg_409, 5, vm); + setArg(call_vlseg_409, 6, vd); + setArg(call_vlseg_409, 7, vlseg_409_arg6); + setArg(call_vlseg_409, 8, 6); + setArg(call_vlseg_409, 9, 7); + setRet(call_vlseg_409, 0, ret_val_vlseg_409); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 189); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 190: VLSEG7E64__V */ + continuation_e __vlseg7e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 190); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_410; + x86::Gp ret_val_get_pow_410 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_410, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_411; + x86::Gp ret_val_get_sew_pow_411 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_411, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_412; + x86::Gp ret_val_get_lmul_pow_412 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_412, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_410, ret_val_get_sew_pow_411), ret_val_get_lmul_pow_412)), 3, true); + setArg(call_get_pow_410, 0, reinterpret_cast(this)); + setArg(call_get_pow_410, 1, EEW); + setRet(call_get_pow_410, 0, ret_val_get_pow_410); + setArg(call_get_sew_pow_411, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_411, 0, ret_val_get_sew_pow_411); + setArg(call_get_lmul_pow_412, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_412, 0, ret_val_get_lmul_pow_412); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_413; + auto illegal_load_413_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_413 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_413, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_413; + setArg(call_illegal_load_413, 0, reinterpret_cast(this)); + setArg(call_illegal_load_413, 1, vd); + setArg(call_illegal_load_413, 2, vm); + setArg(call_illegal_load_413, 3, 7); + setArg(call_illegal_load_413, 4, EEW); + setArg(call_illegal_load_413, 5, illegal_load_413_arg4); + setRet(call_illegal_load_413, 0, ret_val_illegal_load_413); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_414; + auto vlseg_414_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_414_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_414_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_414_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_414 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_414, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_414, 32, false), traits::vstart); + setArg(call_vlseg_414, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_414, 1, V); + setArg(call_vlseg_414, 2, vlseg_414_arg1); + setArg(call_vlseg_414, 3, vlseg_414_arg2); + setArg(call_vlseg_414, 4, vlseg_414_arg3); + setArg(call_vlseg_414, 5, vm); + setArg(call_vlseg_414, 6, vd); + setArg(call_vlseg_414, 7, vlseg_414_arg6); + setArg(call_vlseg_414, 8, 7); + setArg(call_vlseg_414, 9, 7); + setRet(call_vlseg_414, 0, ret_val_vlseg_414); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 190); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 191: VLSEG8E8__V */ + continuation_e __vlseg8e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 191); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_415; + x86::Gp ret_val_get_pow_415 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_415, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_416; + x86::Gp ret_val_get_sew_pow_416 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_416, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_417; + x86::Gp ret_val_get_lmul_pow_417 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_417, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_415, ret_val_get_sew_pow_416), ret_val_get_lmul_pow_417)), 3, true); + setArg(call_get_pow_415, 0, reinterpret_cast(this)); + setArg(call_get_pow_415, 1, EEW); + setRet(call_get_pow_415, 0, ret_val_get_pow_415); + setArg(call_get_sew_pow_416, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_416, 0, ret_val_get_sew_pow_416); + setArg(call_get_lmul_pow_417, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_417, 0, ret_val_get_lmul_pow_417); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_418; + auto illegal_load_418_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_418 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_418, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_418; + setArg(call_illegal_load_418, 0, reinterpret_cast(this)); + setArg(call_illegal_load_418, 1, vd); + setArg(call_illegal_load_418, 2, vm); + setArg(call_illegal_load_418, 3, 8); + setArg(call_illegal_load_418, 4, EEW); + setArg(call_illegal_load_418, 5, illegal_load_418_arg4); + setRet(call_illegal_load_418, 0, ret_val_illegal_load_418); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_419; + auto vlseg_419_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_419_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_419_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_419_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_419 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_419, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_419, 32, false), traits::vstart); + setArg(call_vlseg_419, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_419, 1, V); + setArg(call_vlseg_419, 2, vlseg_419_arg1); + setArg(call_vlseg_419, 3, vlseg_419_arg2); + setArg(call_vlseg_419, 4, vlseg_419_arg3); + setArg(call_vlseg_419, 5, vm); + setArg(call_vlseg_419, 6, vd); + setArg(call_vlseg_419, 7, vlseg_419_arg6); + setArg(call_vlseg_419, 8, 0); + setArg(call_vlseg_419, 9, 8); + setRet(call_vlseg_419, 0, ret_val_vlseg_419); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 191); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 192: VLSEG8E16__V */ + continuation_e __vlseg8e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 192); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_420; + x86::Gp ret_val_get_pow_420 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_420, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_421; + x86::Gp ret_val_get_sew_pow_421 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_421, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_422; + x86::Gp ret_val_get_lmul_pow_422 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_422, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_420, ret_val_get_sew_pow_421), ret_val_get_lmul_pow_422)), 3, true); + setArg(call_get_pow_420, 0, reinterpret_cast(this)); + setArg(call_get_pow_420, 1, EEW); + setRet(call_get_pow_420, 0, ret_val_get_pow_420); + setArg(call_get_sew_pow_421, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_421, 0, ret_val_get_sew_pow_421); + setArg(call_get_lmul_pow_422, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_422, 0, ret_val_get_lmul_pow_422); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_423; + auto illegal_load_423_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_423 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_423, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_423; + setArg(call_illegal_load_423, 0, reinterpret_cast(this)); + setArg(call_illegal_load_423, 1, vd); + setArg(call_illegal_load_423, 2, vm); + setArg(call_illegal_load_423, 3, 8); + setArg(call_illegal_load_423, 4, EEW); + setArg(call_illegal_load_423, 5, illegal_load_423_arg4); + setRet(call_illegal_load_423, 0, ret_val_illegal_load_423); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_424; + auto vlseg_424_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_424_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_424_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_424_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_424 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_424, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_424, 32, false), traits::vstart); + setArg(call_vlseg_424, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_424, 1, V); + setArg(call_vlseg_424, 2, vlseg_424_arg1); + setArg(call_vlseg_424, 3, vlseg_424_arg2); + setArg(call_vlseg_424, 4, vlseg_424_arg3); + setArg(call_vlseg_424, 5, vm); + setArg(call_vlseg_424, 6, vd); + setArg(call_vlseg_424, 7, vlseg_424_arg6); + setArg(call_vlseg_424, 8, 5); + setArg(call_vlseg_424, 9, 8); + setRet(call_vlseg_424, 0, ret_val_vlseg_424); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 192); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 193: VLSEG8E32__V */ + continuation_e __vlseg8e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 193); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_425; + x86::Gp ret_val_get_pow_425 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_425, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_426; + x86::Gp ret_val_get_sew_pow_426 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_426, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_427; + x86::Gp ret_val_get_lmul_pow_427 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_427, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_425, ret_val_get_sew_pow_426), ret_val_get_lmul_pow_427)), 3, true); + setArg(call_get_pow_425, 0, reinterpret_cast(this)); + setArg(call_get_pow_425, 1, EEW); + setRet(call_get_pow_425, 0, ret_val_get_pow_425); + setArg(call_get_sew_pow_426, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_426, 0, ret_val_get_sew_pow_426); + setArg(call_get_lmul_pow_427, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_427, 0, ret_val_get_lmul_pow_427); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_428; + auto illegal_load_428_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_428 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_428, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_428; + setArg(call_illegal_load_428, 0, reinterpret_cast(this)); + setArg(call_illegal_load_428, 1, vd); + setArg(call_illegal_load_428, 2, vm); + setArg(call_illegal_load_428, 3, 8); + setArg(call_illegal_load_428, 4, EEW); + setArg(call_illegal_load_428, 5, illegal_load_428_arg4); + setRet(call_illegal_load_428, 0, ret_val_illegal_load_428); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_429; + auto vlseg_429_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_429_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_429_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_429_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_429 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_429, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_429, 32, false), traits::vstart); + setArg(call_vlseg_429, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_429, 1, V); + setArg(call_vlseg_429, 2, vlseg_429_arg1); + setArg(call_vlseg_429, 3, vlseg_429_arg2); + setArg(call_vlseg_429, 4, vlseg_429_arg3); + setArg(call_vlseg_429, 5, vm); + setArg(call_vlseg_429, 6, vd); + setArg(call_vlseg_429, 7, vlseg_429_arg6); + setArg(call_vlseg_429, 8, 6); + setArg(call_vlseg_429, 9, 8); + setRet(call_vlseg_429, 0, ret_val_vlseg_429); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 193); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 194: VLSEG8E64__V */ + continuation_e __vlseg8e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 194); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_430; + x86::Gp ret_val_get_pow_430 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_430, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_431; + x86::Gp ret_val_get_sew_pow_431 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_431, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_432; + x86::Gp ret_val_get_lmul_pow_432 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_432, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_430, ret_val_get_sew_pow_431), ret_val_get_lmul_pow_432)), 3, true); + setArg(call_get_pow_430, 0, reinterpret_cast(this)); + setArg(call_get_pow_430, 1, EEW); + setRet(call_get_pow_430, 0, ret_val_get_pow_430); + setArg(call_get_sew_pow_431, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_431, 0, ret_val_get_sew_pow_431); + setArg(call_get_lmul_pow_432, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_432, 0, ret_val_get_lmul_pow_432); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_433; + auto illegal_load_433_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_433 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_433, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_433; + setArg(call_illegal_load_433, 0, reinterpret_cast(this)); + setArg(call_illegal_load_433, 1, vd); + setArg(call_illegal_load_433, 2, vm); + setArg(call_illegal_load_433, 3, 8); + setArg(call_illegal_load_433, 4, EEW); + setArg(call_illegal_load_433, 5, illegal_load_433_arg4); + setRet(call_illegal_load_433, 0, ret_val_illegal_load_433); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_434; + auto vlseg_434_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_434_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_434_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_434_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_434 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_434, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_434, 32, false), traits::vstart); + setArg(call_vlseg_434, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_434, 1, V); + setArg(call_vlseg_434, 2, vlseg_434_arg1); + setArg(call_vlseg_434, 3, vlseg_434_arg2); + setArg(call_vlseg_434, 4, vlseg_434_arg3); + setArg(call_vlseg_434, 5, vm); + setArg(call_vlseg_434, 6, vd); + setArg(call_vlseg_434, 7, vlseg_434_arg6); + setArg(call_vlseg_434, 8, 7); + setArg(call_vlseg_434, 9, 8); + setRet(call_vlseg_434, 0, ret_val_vlseg_434); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 194); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 195: VSE8__V */ + continuation_e __vse8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 195); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_435; + x86::Gp ret_val_get_pow_435 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_435, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_436; + x86::Gp ret_val_get_sew_pow_436 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_436, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_437; + x86::Gp ret_val_get_lmul_pow_437 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_437, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_435, ret_val_get_sew_pow_436), ret_val_get_lmul_pow_437)), 3, true); + setArg(call_get_pow_435, 0, reinterpret_cast(this)); + setArg(call_get_pow_435, 1, EEW); + setRet(call_get_pow_435, 0, ret_val_get_pow_435); + setArg(call_get_sew_pow_436, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_436, 0, ret_val_get_sew_pow_436); + setArg(call_get_lmul_pow_437, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_437, 0, ret_val_get_lmul_pow_437); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_438; + auto illegal_store_438_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_438 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_438, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_438; + setArg(call_illegal_store_438, 0, reinterpret_cast(this)); + setArg(call_illegal_store_438, 1, 1); + setArg(call_illegal_store_438, 2, EEW); + setArg(call_illegal_store_438, 3, illegal_store_438_arg2); + setRet(call_illegal_store_438, 0, ret_val_illegal_store_438); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_439; + auto vsseg_439_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_439_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_439_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_439_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_439 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_439, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_439, 32, false), traits::vstart); + setArg(call_vsseg_439, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_439, 1, V); + setArg(call_vsseg_439, 2, vsseg_439_arg1); + setArg(call_vsseg_439, 3, vsseg_439_arg2); + setArg(call_vsseg_439, 4, vsseg_439_arg3); + setArg(call_vsseg_439, 5, vm); + setArg(call_vsseg_439, 6, vs3); + setArg(call_vsseg_439, 7, vsseg_439_arg6); + setArg(call_vsseg_439, 8, 0); + setArg(call_vsseg_439, 9, 1); + setRet(call_vsseg_439, 0, ret_val_vsseg_439); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 195); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 196: VSE16__V */ + continuation_e __vse16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 196); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_440; + x86::Gp ret_val_get_pow_440 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_440, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_441; + x86::Gp ret_val_get_sew_pow_441 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_441, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_442; + x86::Gp ret_val_get_lmul_pow_442 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_442, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_440, ret_val_get_sew_pow_441), ret_val_get_lmul_pow_442)), 3, true); + setArg(call_get_pow_440, 0, reinterpret_cast(this)); + setArg(call_get_pow_440, 1, EEW); + setRet(call_get_pow_440, 0, ret_val_get_pow_440); + setArg(call_get_sew_pow_441, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_441, 0, ret_val_get_sew_pow_441); + setArg(call_get_lmul_pow_442, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_442, 0, ret_val_get_lmul_pow_442); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_443; + auto illegal_store_443_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_443 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_443, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_443; + setArg(call_illegal_store_443, 0, reinterpret_cast(this)); + setArg(call_illegal_store_443, 1, 1); + setArg(call_illegal_store_443, 2, EEW); + setArg(call_illegal_store_443, 3, illegal_store_443_arg2); + setRet(call_illegal_store_443, 0, ret_val_illegal_store_443); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_444; + auto vsseg_444_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_444_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_444_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_444_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_444 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_444, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_444, 32, false), traits::vstart); + setArg(call_vsseg_444, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_444, 1, V); + setArg(call_vsseg_444, 2, vsseg_444_arg1); + setArg(call_vsseg_444, 3, vsseg_444_arg2); + setArg(call_vsseg_444, 4, vsseg_444_arg3); + setArg(call_vsseg_444, 5, vm); + setArg(call_vsseg_444, 6, vs3); + setArg(call_vsseg_444, 7, vsseg_444_arg6); + setArg(call_vsseg_444, 8, 5); + setArg(call_vsseg_444, 9, 1); + setRet(call_vsseg_444, 0, ret_val_vsseg_444); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 196); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 197: VSE32__V */ + continuation_e __vse32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 197); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_445; + x86::Gp ret_val_get_pow_445 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_445, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_446; + x86::Gp ret_val_get_sew_pow_446 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_446, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_447; + x86::Gp ret_val_get_lmul_pow_447 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_447, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_445, ret_val_get_sew_pow_446), ret_val_get_lmul_pow_447)), 3, true); + setArg(call_get_pow_445, 0, reinterpret_cast(this)); + setArg(call_get_pow_445, 1, EEW); + setRet(call_get_pow_445, 0, ret_val_get_pow_445); + setArg(call_get_sew_pow_446, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_446, 0, ret_val_get_sew_pow_446); + setArg(call_get_lmul_pow_447, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_447, 0, ret_val_get_lmul_pow_447); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_448; + auto illegal_store_448_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_448 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_448, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_448; + setArg(call_illegal_store_448, 0, reinterpret_cast(this)); + setArg(call_illegal_store_448, 1, 1); + setArg(call_illegal_store_448, 2, EEW); + setArg(call_illegal_store_448, 3, illegal_store_448_arg2); + setRet(call_illegal_store_448, 0, ret_val_illegal_store_448); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_449; + auto vsseg_449_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_449_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_449_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_449_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_449 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_449, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_449, 32, false), traits::vstart); + setArg(call_vsseg_449, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_449, 1, V); + setArg(call_vsseg_449, 2, vsseg_449_arg1); + setArg(call_vsseg_449, 3, vsseg_449_arg2); + setArg(call_vsseg_449, 4, vsseg_449_arg3); + setArg(call_vsseg_449, 5, vm); + setArg(call_vsseg_449, 6, vs3); + setArg(call_vsseg_449, 7, vsseg_449_arg6); + setArg(call_vsseg_449, 8, 6); + setArg(call_vsseg_449, 9, 1); + setRet(call_vsseg_449, 0, ret_val_vsseg_449); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 197); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 198: VSE64__V */ + continuation_e __vse64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 198); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_450; + x86::Gp ret_val_get_pow_450 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_450, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_451; + x86::Gp ret_val_get_sew_pow_451 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_451, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_452; + x86::Gp ret_val_get_lmul_pow_452 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_452, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_450, ret_val_get_sew_pow_451), ret_val_get_lmul_pow_452)), 3, true); + setArg(call_get_pow_450, 0, reinterpret_cast(this)); + setArg(call_get_pow_450, 1, EEW); + setRet(call_get_pow_450, 0, ret_val_get_pow_450); + setArg(call_get_sew_pow_451, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_451, 0, ret_val_get_sew_pow_451); + setArg(call_get_lmul_pow_452, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_452, 0, ret_val_get_lmul_pow_452); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_453; + auto illegal_store_453_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_453 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_453, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_453; + setArg(call_illegal_store_453, 0, reinterpret_cast(this)); + setArg(call_illegal_store_453, 1, 1); + setArg(call_illegal_store_453, 2, EEW); + setArg(call_illegal_store_453, 3, illegal_store_453_arg2); + setRet(call_illegal_store_453, 0, ret_val_illegal_store_453); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_454; + auto vsseg_454_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_454_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_454_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_454_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_454 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_454, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_454, 32, false), traits::vstart); + setArg(call_vsseg_454, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_454, 1, V); + setArg(call_vsseg_454, 2, vsseg_454_arg1); + setArg(call_vsseg_454, 3, vsseg_454_arg2); + setArg(call_vsseg_454, 4, vsseg_454_arg3); + setArg(call_vsseg_454, 5, vm); + setArg(call_vsseg_454, 6, vs3); + setArg(call_vsseg_454, 7, vsseg_454_arg6); + setArg(call_vsseg_454, 8, 7); + setArg(call_vsseg_454, 9, 1); + setRet(call_vsseg_454, 0, ret_val_vsseg_454); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 198); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 199: VSSEG2E8__V */ + continuation_e __vsseg2e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG2E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 199); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_455; + x86::Gp ret_val_get_pow_455 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_455, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_456; + x86::Gp ret_val_get_sew_pow_456 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_456, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_457; + x86::Gp ret_val_get_lmul_pow_457 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_457, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_455, ret_val_get_sew_pow_456), ret_val_get_lmul_pow_457)), 3, true); + setArg(call_get_pow_455, 0, reinterpret_cast(this)); + setArg(call_get_pow_455, 1, EEW); + setRet(call_get_pow_455, 0, ret_val_get_pow_455); + setArg(call_get_sew_pow_456, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_456, 0, ret_val_get_sew_pow_456); + setArg(call_get_lmul_pow_457, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_457, 0, ret_val_get_lmul_pow_457); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_458; + auto illegal_store_458_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_458 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_458, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_458; + setArg(call_illegal_store_458, 0, reinterpret_cast(this)); + setArg(call_illegal_store_458, 1, 2); + setArg(call_illegal_store_458, 2, EEW); + setArg(call_illegal_store_458, 3, illegal_store_458_arg2); + setRet(call_illegal_store_458, 0, ret_val_illegal_store_458); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_459; + auto vsseg_459_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_459_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_459_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_459_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_459 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_459, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_459, 32, false), traits::vstart); + setArg(call_vsseg_459, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_459, 1, V); + setArg(call_vsseg_459, 2, vsseg_459_arg1); + setArg(call_vsseg_459, 3, vsseg_459_arg2); + setArg(call_vsseg_459, 4, vsseg_459_arg3); + setArg(call_vsseg_459, 5, vm); + setArg(call_vsseg_459, 6, vs3); + setArg(call_vsseg_459, 7, vsseg_459_arg6); + setArg(call_vsseg_459, 8, 0); + setArg(call_vsseg_459, 9, 2); + setRet(call_vsseg_459, 0, ret_val_vsseg_459); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 199); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 200: VSSEG2E16__V */ + continuation_e __vsseg2e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG2E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 200); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_460; + x86::Gp ret_val_get_pow_460 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_460, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_461; + x86::Gp ret_val_get_sew_pow_461 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_461, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_462; + x86::Gp ret_val_get_lmul_pow_462 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_462, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_460, ret_val_get_sew_pow_461), ret_val_get_lmul_pow_462)), 3, true); + setArg(call_get_pow_460, 0, reinterpret_cast(this)); + setArg(call_get_pow_460, 1, EEW); + setRet(call_get_pow_460, 0, ret_val_get_pow_460); + setArg(call_get_sew_pow_461, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_461, 0, ret_val_get_sew_pow_461); + setArg(call_get_lmul_pow_462, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_462, 0, ret_val_get_lmul_pow_462); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_463; + auto illegal_store_463_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_463 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_463, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_463; + setArg(call_illegal_store_463, 0, reinterpret_cast(this)); + setArg(call_illegal_store_463, 1, 2); + setArg(call_illegal_store_463, 2, EEW); + setArg(call_illegal_store_463, 3, illegal_store_463_arg2); + setRet(call_illegal_store_463, 0, ret_val_illegal_store_463); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_464; + auto vsseg_464_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_464_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_464_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_464_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_464 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_464, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_464, 32, false), traits::vstart); + setArg(call_vsseg_464, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_464, 1, V); + setArg(call_vsseg_464, 2, vsseg_464_arg1); + setArg(call_vsseg_464, 3, vsseg_464_arg2); + setArg(call_vsseg_464, 4, vsseg_464_arg3); + setArg(call_vsseg_464, 5, vm); + setArg(call_vsseg_464, 6, vs3); + setArg(call_vsseg_464, 7, vsseg_464_arg6); + setArg(call_vsseg_464, 8, 5); + setArg(call_vsseg_464, 9, 2); + setRet(call_vsseg_464, 0, ret_val_vsseg_464); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 200); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 201: VSSEG2E32__V */ + continuation_e __vsseg2e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG2E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 201); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_465; + x86::Gp ret_val_get_pow_465 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_465, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_466; + x86::Gp ret_val_get_sew_pow_466 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_466, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_467; + x86::Gp ret_val_get_lmul_pow_467 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_467, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_465, ret_val_get_sew_pow_466), ret_val_get_lmul_pow_467)), 3, true); + setArg(call_get_pow_465, 0, reinterpret_cast(this)); + setArg(call_get_pow_465, 1, EEW); + setRet(call_get_pow_465, 0, ret_val_get_pow_465); + setArg(call_get_sew_pow_466, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_466, 0, ret_val_get_sew_pow_466); + setArg(call_get_lmul_pow_467, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_467, 0, ret_val_get_lmul_pow_467); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_468; + auto illegal_store_468_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_468 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_468, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_468; + setArg(call_illegal_store_468, 0, reinterpret_cast(this)); + setArg(call_illegal_store_468, 1, 2); + setArg(call_illegal_store_468, 2, EEW); + setArg(call_illegal_store_468, 3, illegal_store_468_arg2); + setRet(call_illegal_store_468, 0, ret_val_illegal_store_468); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_469; + auto vsseg_469_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_469_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_469_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_469_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_469 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_469, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_469, 32, false), traits::vstart); + setArg(call_vsseg_469, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_469, 1, V); + setArg(call_vsseg_469, 2, vsseg_469_arg1); + setArg(call_vsseg_469, 3, vsseg_469_arg2); + setArg(call_vsseg_469, 4, vsseg_469_arg3); + setArg(call_vsseg_469, 5, vm); + setArg(call_vsseg_469, 6, vs3); + setArg(call_vsseg_469, 7, vsseg_469_arg6); + setArg(call_vsseg_469, 8, 6); + setArg(call_vsseg_469, 9, 2); + setRet(call_vsseg_469, 0, ret_val_vsseg_469); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 201); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 202: VSSEG2E64__V */ + continuation_e __vsseg2e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG2E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 202); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_470; + x86::Gp ret_val_get_pow_470 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_470, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_471; + x86::Gp ret_val_get_sew_pow_471 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_471, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_472; + x86::Gp ret_val_get_lmul_pow_472 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_472, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_470, ret_val_get_sew_pow_471), ret_val_get_lmul_pow_472)), 3, true); + setArg(call_get_pow_470, 0, reinterpret_cast(this)); + setArg(call_get_pow_470, 1, EEW); + setRet(call_get_pow_470, 0, ret_val_get_pow_470); + setArg(call_get_sew_pow_471, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_471, 0, ret_val_get_sew_pow_471); + setArg(call_get_lmul_pow_472, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_472, 0, ret_val_get_lmul_pow_472); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_473; + auto illegal_store_473_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_473 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_473, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_473; + setArg(call_illegal_store_473, 0, reinterpret_cast(this)); + setArg(call_illegal_store_473, 1, 2); + setArg(call_illegal_store_473, 2, EEW); + setArg(call_illegal_store_473, 3, illegal_store_473_arg2); + setRet(call_illegal_store_473, 0, ret_val_illegal_store_473); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_474; + auto vsseg_474_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_474_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_474_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_474_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_474 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_474, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_474, 32, false), traits::vstart); + setArg(call_vsseg_474, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_474, 1, V); + setArg(call_vsseg_474, 2, vsseg_474_arg1); + setArg(call_vsseg_474, 3, vsseg_474_arg2); + setArg(call_vsseg_474, 4, vsseg_474_arg3); + setArg(call_vsseg_474, 5, vm); + setArg(call_vsseg_474, 6, vs3); + setArg(call_vsseg_474, 7, vsseg_474_arg6); + setArg(call_vsseg_474, 8, 7); + setArg(call_vsseg_474, 9, 2); + setRet(call_vsseg_474, 0, ret_val_vsseg_474); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 202); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 203: VSSEG3E8__V */ + continuation_e __vsseg3e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG3E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 203); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_475; + x86::Gp ret_val_get_pow_475 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_475, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_476; + x86::Gp ret_val_get_sew_pow_476 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_476, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_477; + x86::Gp ret_val_get_lmul_pow_477 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_477, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_475, ret_val_get_sew_pow_476), ret_val_get_lmul_pow_477)), 3, true); + setArg(call_get_pow_475, 0, reinterpret_cast(this)); + setArg(call_get_pow_475, 1, EEW); + setRet(call_get_pow_475, 0, ret_val_get_pow_475); + setArg(call_get_sew_pow_476, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_476, 0, ret_val_get_sew_pow_476); + setArg(call_get_lmul_pow_477, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_477, 0, ret_val_get_lmul_pow_477); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_478; + auto illegal_store_478_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_478 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_478, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_478; + setArg(call_illegal_store_478, 0, reinterpret_cast(this)); + setArg(call_illegal_store_478, 1, 3); + setArg(call_illegal_store_478, 2, EEW); + setArg(call_illegal_store_478, 3, illegal_store_478_arg2); + setRet(call_illegal_store_478, 0, ret_val_illegal_store_478); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_479; + auto vsseg_479_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_479_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_479_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_479_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_479 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_479, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_479, 32, false), traits::vstart); + setArg(call_vsseg_479, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_479, 1, V); + setArg(call_vsseg_479, 2, vsseg_479_arg1); + setArg(call_vsseg_479, 3, vsseg_479_arg2); + setArg(call_vsseg_479, 4, vsseg_479_arg3); + setArg(call_vsseg_479, 5, vm); + setArg(call_vsseg_479, 6, vs3); + setArg(call_vsseg_479, 7, vsseg_479_arg6); + setArg(call_vsseg_479, 8, 0); + setArg(call_vsseg_479, 9, 3); + setRet(call_vsseg_479, 0, ret_val_vsseg_479); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 203); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 204: VSSEG3E16__V */ + continuation_e __vsseg3e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG3E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 204); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_480; + x86::Gp ret_val_get_pow_480 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_480, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_481; + x86::Gp ret_val_get_sew_pow_481 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_481, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_482; + x86::Gp ret_val_get_lmul_pow_482 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_482, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_480, ret_val_get_sew_pow_481), ret_val_get_lmul_pow_482)), 3, true); + setArg(call_get_pow_480, 0, reinterpret_cast(this)); + setArg(call_get_pow_480, 1, EEW); + setRet(call_get_pow_480, 0, ret_val_get_pow_480); + setArg(call_get_sew_pow_481, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_481, 0, ret_val_get_sew_pow_481); + setArg(call_get_lmul_pow_482, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_482, 0, ret_val_get_lmul_pow_482); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_483; + auto illegal_store_483_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_483 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_483, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_483; + setArg(call_illegal_store_483, 0, reinterpret_cast(this)); + setArg(call_illegal_store_483, 1, 3); + setArg(call_illegal_store_483, 2, EEW); + setArg(call_illegal_store_483, 3, illegal_store_483_arg2); + setRet(call_illegal_store_483, 0, ret_val_illegal_store_483); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_484; + auto vsseg_484_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_484_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_484_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_484_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_484 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_484, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_484, 32, false), traits::vstart); + setArg(call_vsseg_484, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_484, 1, V); + setArg(call_vsseg_484, 2, vsseg_484_arg1); + setArg(call_vsseg_484, 3, vsseg_484_arg2); + setArg(call_vsseg_484, 4, vsseg_484_arg3); + setArg(call_vsseg_484, 5, vm); + setArg(call_vsseg_484, 6, vs3); + setArg(call_vsseg_484, 7, vsseg_484_arg6); + setArg(call_vsseg_484, 8, 5); + setArg(call_vsseg_484, 9, 3); + setRet(call_vsseg_484, 0, ret_val_vsseg_484); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 204); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 205: VSSEG3E32__V */ + continuation_e __vsseg3e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG3E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 205); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_485; + x86::Gp ret_val_get_pow_485 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_485, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_486; + x86::Gp ret_val_get_sew_pow_486 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_486, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_487; + x86::Gp ret_val_get_lmul_pow_487 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_487, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_485, ret_val_get_sew_pow_486), ret_val_get_lmul_pow_487)), 3, true); + setArg(call_get_pow_485, 0, reinterpret_cast(this)); + setArg(call_get_pow_485, 1, EEW); + setRet(call_get_pow_485, 0, ret_val_get_pow_485); + setArg(call_get_sew_pow_486, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_486, 0, ret_val_get_sew_pow_486); + setArg(call_get_lmul_pow_487, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_487, 0, ret_val_get_lmul_pow_487); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_488; + auto illegal_store_488_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_488 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_488, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_488; + setArg(call_illegal_store_488, 0, reinterpret_cast(this)); + setArg(call_illegal_store_488, 1, 3); + setArg(call_illegal_store_488, 2, EEW); + setArg(call_illegal_store_488, 3, illegal_store_488_arg2); + setRet(call_illegal_store_488, 0, ret_val_illegal_store_488); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_489; + auto vsseg_489_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_489_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_489_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_489_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_489 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_489, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_489, 32, false), traits::vstart); + setArg(call_vsseg_489, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_489, 1, V); + setArg(call_vsseg_489, 2, vsseg_489_arg1); + setArg(call_vsseg_489, 3, vsseg_489_arg2); + setArg(call_vsseg_489, 4, vsseg_489_arg3); + setArg(call_vsseg_489, 5, vm); + setArg(call_vsseg_489, 6, vs3); + setArg(call_vsseg_489, 7, vsseg_489_arg6); + setArg(call_vsseg_489, 8, 6); + setArg(call_vsseg_489, 9, 3); + setRet(call_vsseg_489, 0, ret_val_vsseg_489); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 205); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 206: VSSEG3E64__V */ + continuation_e __vsseg3e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG3E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 206); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_490; + x86::Gp ret_val_get_pow_490 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_490, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_491; + x86::Gp ret_val_get_sew_pow_491 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_491, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_492; + x86::Gp ret_val_get_lmul_pow_492 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_492, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_490, ret_val_get_sew_pow_491), ret_val_get_lmul_pow_492)), 3, true); + setArg(call_get_pow_490, 0, reinterpret_cast(this)); + setArg(call_get_pow_490, 1, EEW); + setRet(call_get_pow_490, 0, ret_val_get_pow_490); + setArg(call_get_sew_pow_491, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_491, 0, ret_val_get_sew_pow_491); + setArg(call_get_lmul_pow_492, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_492, 0, ret_val_get_lmul_pow_492); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_493; + auto illegal_store_493_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_493 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_493, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_493; + setArg(call_illegal_store_493, 0, reinterpret_cast(this)); + setArg(call_illegal_store_493, 1, 3); + setArg(call_illegal_store_493, 2, EEW); + setArg(call_illegal_store_493, 3, illegal_store_493_arg2); + setRet(call_illegal_store_493, 0, ret_val_illegal_store_493); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_494; + auto vsseg_494_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_494_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_494_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_494_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_494 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_494, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_494, 32, false), traits::vstart); + setArg(call_vsseg_494, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_494, 1, V); + setArg(call_vsseg_494, 2, vsseg_494_arg1); + setArg(call_vsseg_494, 3, vsseg_494_arg2); + setArg(call_vsseg_494, 4, vsseg_494_arg3); + setArg(call_vsseg_494, 5, vm); + setArg(call_vsseg_494, 6, vs3); + setArg(call_vsseg_494, 7, vsseg_494_arg6); + setArg(call_vsseg_494, 8, 7); + setArg(call_vsseg_494, 9, 3); + setRet(call_vsseg_494, 0, ret_val_vsseg_494); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 206); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 207: VSSEG4E8__V */ + continuation_e __vsseg4e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG4E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 207); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_495; + x86::Gp ret_val_get_pow_495 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_495, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_496; + x86::Gp ret_val_get_sew_pow_496 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_496, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_497; + x86::Gp ret_val_get_lmul_pow_497 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_497, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_495, ret_val_get_sew_pow_496), ret_val_get_lmul_pow_497)), 3, true); + setArg(call_get_pow_495, 0, reinterpret_cast(this)); + setArg(call_get_pow_495, 1, EEW); + setRet(call_get_pow_495, 0, ret_val_get_pow_495); + setArg(call_get_sew_pow_496, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_496, 0, ret_val_get_sew_pow_496); + setArg(call_get_lmul_pow_497, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_497, 0, ret_val_get_lmul_pow_497); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_498; + auto illegal_store_498_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_498 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_498, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_498; + setArg(call_illegal_store_498, 0, reinterpret_cast(this)); + setArg(call_illegal_store_498, 1, 4); + setArg(call_illegal_store_498, 2, EEW); + setArg(call_illegal_store_498, 3, illegal_store_498_arg2); + setRet(call_illegal_store_498, 0, ret_val_illegal_store_498); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_499; + auto vsseg_499_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_499_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_499_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_499_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_499 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_499, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_499, 32, false), traits::vstart); + setArg(call_vsseg_499, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_499, 1, V); + setArg(call_vsseg_499, 2, vsseg_499_arg1); + setArg(call_vsseg_499, 3, vsseg_499_arg2); + setArg(call_vsseg_499, 4, vsseg_499_arg3); + setArg(call_vsseg_499, 5, vm); + setArg(call_vsseg_499, 6, vs3); + setArg(call_vsseg_499, 7, vsseg_499_arg6); + setArg(call_vsseg_499, 8, 0); + setArg(call_vsseg_499, 9, 4); + setRet(call_vsseg_499, 0, ret_val_vsseg_499); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 207); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 208: VSSEG4E16__V */ + continuation_e __vsseg4e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG4E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 208); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_500; + x86::Gp ret_val_get_pow_500 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_500, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_501; + x86::Gp ret_val_get_sew_pow_501 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_501, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_502; + x86::Gp ret_val_get_lmul_pow_502 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_502, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_500, ret_val_get_sew_pow_501), ret_val_get_lmul_pow_502)), 3, true); + setArg(call_get_pow_500, 0, reinterpret_cast(this)); + setArg(call_get_pow_500, 1, EEW); + setRet(call_get_pow_500, 0, ret_val_get_pow_500); + setArg(call_get_sew_pow_501, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_501, 0, ret_val_get_sew_pow_501); + setArg(call_get_lmul_pow_502, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_502, 0, ret_val_get_lmul_pow_502); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_503; + auto illegal_store_503_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_503 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_503, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_503; + setArg(call_illegal_store_503, 0, reinterpret_cast(this)); + setArg(call_illegal_store_503, 1, 4); + setArg(call_illegal_store_503, 2, EEW); + setArg(call_illegal_store_503, 3, illegal_store_503_arg2); + setRet(call_illegal_store_503, 0, ret_val_illegal_store_503); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_504; + auto vsseg_504_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_504_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_504_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_504_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_504 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_504, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_504, 32, false), traits::vstart); + setArg(call_vsseg_504, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_504, 1, V); + setArg(call_vsseg_504, 2, vsseg_504_arg1); + setArg(call_vsseg_504, 3, vsseg_504_arg2); + setArg(call_vsseg_504, 4, vsseg_504_arg3); + setArg(call_vsseg_504, 5, vm); + setArg(call_vsseg_504, 6, vs3); + setArg(call_vsseg_504, 7, vsseg_504_arg6); + setArg(call_vsseg_504, 8, 5); + setArg(call_vsseg_504, 9, 4); + setRet(call_vsseg_504, 0, ret_val_vsseg_504); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 208); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 209: VSSEG4E32__V */ + continuation_e __vsseg4e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG4E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 209); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_505; + x86::Gp ret_val_get_pow_505 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_505, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_506; + x86::Gp ret_val_get_sew_pow_506 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_506, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_507; + x86::Gp ret_val_get_lmul_pow_507 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_507, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_505, ret_val_get_sew_pow_506), ret_val_get_lmul_pow_507)), 3, true); + setArg(call_get_pow_505, 0, reinterpret_cast(this)); + setArg(call_get_pow_505, 1, EEW); + setRet(call_get_pow_505, 0, ret_val_get_pow_505); + setArg(call_get_sew_pow_506, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_506, 0, ret_val_get_sew_pow_506); + setArg(call_get_lmul_pow_507, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_507, 0, ret_val_get_lmul_pow_507); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_508; + auto illegal_store_508_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_508 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_508, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_508; + setArg(call_illegal_store_508, 0, reinterpret_cast(this)); + setArg(call_illegal_store_508, 1, 4); + setArg(call_illegal_store_508, 2, EEW); + setArg(call_illegal_store_508, 3, illegal_store_508_arg2); + setRet(call_illegal_store_508, 0, ret_val_illegal_store_508); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_509; + auto vsseg_509_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_509_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_509_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_509_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_509 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_509, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_509, 32, false), traits::vstart); + setArg(call_vsseg_509, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_509, 1, V); + setArg(call_vsseg_509, 2, vsseg_509_arg1); + setArg(call_vsseg_509, 3, vsseg_509_arg2); + setArg(call_vsseg_509, 4, vsseg_509_arg3); + setArg(call_vsseg_509, 5, vm); + setArg(call_vsseg_509, 6, vs3); + setArg(call_vsseg_509, 7, vsseg_509_arg6); + setArg(call_vsseg_509, 8, 6); + setArg(call_vsseg_509, 9, 4); + setRet(call_vsseg_509, 0, ret_val_vsseg_509); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 209); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 210: VSSEG4E64__V */ + continuation_e __vsseg4e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG4E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 210); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_510; + x86::Gp ret_val_get_pow_510 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_510, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_511; + x86::Gp ret_val_get_sew_pow_511 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_511, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_512; + x86::Gp ret_val_get_lmul_pow_512 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_512, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_510, ret_val_get_sew_pow_511), ret_val_get_lmul_pow_512)), 3, true); + setArg(call_get_pow_510, 0, reinterpret_cast(this)); + setArg(call_get_pow_510, 1, EEW); + setRet(call_get_pow_510, 0, ret_val_get_pow_510); + setArg(call_get_sew_pow_511, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_511, 0, ret_val_get_sew_pow_511); + setArg(call_get_lmul_pow_512, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_512, 0, ret_val_get_lmul_pow_512); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_513; + auto illegal_store_513_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_513 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_513, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_513; + setArg(call_illegal_store_513, 0, reinterpret_cast(this)); + setArg(call_illegal_store_513, 1, 4); + setArg(call_illegal_store_513, 2, EEW); + setArg(call_illegal_store_513, 3, illegal_store_513_arg2); + setRet(call_illegal_store_513, 0, ret_val_illegal_store_513); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_514; + auto vsseg_514_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_514_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_514_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_514_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_514 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_514, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_514, 32, false), traits::vstart); + setArg(call_vsseg_514, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_514, 1, V); + setArg(call_vsseg_514, 2, vsseg_514_arg1); + setArg(call_vsseg_514, 3, vsseg_514_arg2); + setArg(call_vsseg_514, 4, vsseg_514_arg3); + setArg(call_vsseg_514, 5, vm); + setArg(call_vsseg_514, 6, vs3); + setArg(call_vsseg_514, 7, vsseg_514_arg6); + setArg(call_vsseg_514, 8, 7); + setArg(call_vsseg_514, 9, 4); + setRet(call_vsseg_514, 0, ret_val_vsseg_514); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 210); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 211: VSSEG5E8__V */ + continuation_e __vsseg5e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG5E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 211); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_515; + x86::Gp ret_val_get_pow_515 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_515, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_516; + x86::Gp ret_val_get_sew_pow_516 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_516, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_517; + x86::Gp ret_val_get_lmul_pow_517 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_517, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_515, ret_val_get_sew_pow_516), ret_val_get_lmul_pow_517)), 3, true); + setArg(call_get_pow_515, 0, reinterpret_cast(this)); + setArg(call_get_pow_515, 1, EEW); + setRet(call_get_pow_515, 0, ret_val_get_pow_515); + setArg(call_get_sew_pow_516, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_516, 0, ret_val_get_sew_pow_516); + setArg(call_get_lmul_pow_517, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_517, 0, ret_val_get_lmul_pow_517); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_518; + auto illegal_store_518_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_518 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_518, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_518; + setArg(call_illegal_store_518, 0, reinterpret_cast(this)); + setArg(call_illegal_store_518, 1, 5); + setArg(call_illegal_store_518, 2, EEW); + setArg(call_illegal_store_518, 3, illegal_store_518_arg2); + setRet(call_illegal_store_518, 0, ret_val_illegal_store_518); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_519; + auto vsseg_519_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_519_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_519_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_519_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_519 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_519, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_519, 32, false), traits::vstart); + setArg(call_vsseg_519, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_519, 1, V); + setArg(call_vsseg_519, 2, vsseg_519_arg1); + setArg(call_vsseg_519, 3, vsseg_519_arg2); + setArg(call_vsseg_519, 4, vsseg_519_arg3); + setArg(call_vsseg_519, 5, vm); + setArg(call_vsseg_519, 6, vs3); + setArg(call_vsseg_519, 7, vsseg_519_arg6); + setArg(call_vsseg_519, 8, 0); + setArg(call_vsseg_519, 9, 5); + setRet(call_vsseg_519, 0, ret_val_vsseg_519); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 211); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 212: VSSEG5E16__V */ + continuation_e __vsseg5e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG5E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 212); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_520; + x86::Gp ret_val_get_pow_520 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_520, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_521; + x86::Gp ret_val_get_sew_pow_521 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_521, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_522; + x86::Gp ret_val_get_lmul_pow_522 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_522, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_520, ret_val_get_sew_pow_521), ret_val_get_lmul_pow_522)), 3, true); + setArg(call_get_pow_520, 0, reinterpret_cast(this)); + setArg(call_get_pow_520, 1, EEW); + setRet(call_get_pow_520, 0, ret_val_get_pow_520); + setArg(call_get_sew_pow_521, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_521, 0, ret_val_get_sew_pow_521); + setArg(call_get_lmul_pow_522, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_522, 0, ret_val_get_lmul_pow_522); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_523; + auto illegal_store_523_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_523 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_523, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_523; + setArg(call_illegal_store_523, 0, reinterpret_cast(this)); + setArg(call_illegal_store_523, 1, 5); + setArg(call_illegal_store_523, 2, EEW); + setArg(call_illegal_store_523, 3, illegal_store_523_arg2); + setRet(call_illegal_store_523, 0, ret_val_illegal_store_523); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_524; + auto vsseg_524_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_524_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_524_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_524_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_524 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_524, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_524, 32, false), traits::vstart); + setArg(call_vsseg_524, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_524, 1, V); + setArg(call_vsseg_524, 2, vsseg_524_arg1); + setArg(call_vsseg_524, 3, vsseg_524_arg2); + setArg(call_vsseg_524, 4, vsseg_524_arg3); + setArg(call_vsseg_524, 5, vm); + setArg(call_vsseg_524, 6, vs3); + setArg(call_vsseg_524, 7, vsseg_524_arg6); + setArg(call_vsseg_524, 8, 5); + setArg(call_vsseg_524, 9, 5); + setRet(call_vsseg_524, 0, ret_val_vsseg_524); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 212); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 213: VSSEG5E32__V */ + continuation_e __vsseg5e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG5E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 213); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_525; + x86::Gp ret_val_get_pow_525 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_525, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_526; + x86::Gp ret_val_get_sew_pow_526 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_526, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_527; + x86::Gp ret_val_get_lmul_pow_527 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_527, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_525, ret_val_get_sew_pow_526), ret_val_get_lmul_pow_527)), 3, true); + setArg(call_get_pow_525, 0, reinterpret_cast(this)); + setArg(call_get_pow_525, 1, EEW); + setRet(call_get_pow_525, 0, ret_val_get_pow_525); + setArg(call_get_sew_pow_526, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_526, 0, ret_val_get_sew_pow_526); + setArg(call_get_lmul_pow_527, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_527, 0, ret_val_get_lmul_pow_527); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_528; + auto illegal_store_528_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_528 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_528, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_528; + setArg(call_illegal_store_528, 0, reinterpret_cast(this)); + setArg(call_illegal_store_528, 1, 5); + setArg(call_illegal_store_528, 2, EEW); + setArg(call_illegal_store_528, 3, illegal_store_528_arg2); + setRet(call_illegal_store_528, 0, ret_val_illegal_store_528); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_529; + auto vsseg_529_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_529_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_529_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_529_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_529 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_529, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_529, 32, false), traits::vstart); + setArg(call_vsseg_529, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_529, 1, V); + setArg(call_vsseg_529, 2, vsseg_529_arg1); + setArg(call_vsseg_529, 3, vsseg_529_arg2); + setArg(call_vsseg_529, 4, vsseg_529_arg3); + setArg(call_vsseg_529, 5, vm); + setArg(call_vsseg_529, 6, vs3); + setArg(call_vsseg_529, 7, vsseg_529_arg6); + setArg(call_vsseg_529, 8, 6); + setArg(call_vsseg_529, 9, 5); + setRet(call_vsseg_529, 0, ret_val_vsseg_529); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 213); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 214: VSSEG5E64__V */ + continuation_e __vsseg5e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG5E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 214); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_530; + x86::Gp ret_val_get_pow_530 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_530, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_531; + x86::Gp ret_val_get_sew_pow_531 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_531, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_532; + x86::Gp ret_val_get_lmul_pow_532 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_532, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_530, ret_val_get_sew_pow_531), ret_val_get_lmul_pow_532)), 3, true); + setArg(call_get_pow_530, 0, reinterpret_cast(this)); + setArg(call_get_pow_530, 1, EEW); + setRet(call_get_pow_530, 0, ret_val_get_pow_530); + setArg(call_get_sew_pow_531, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_531, 0, ret_val_get_sew_pow_531); + setArg(call_get_lmul_pow_532, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_532, 0, ret_val_get_lmul_pow_532); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_533; + auto illegal_store_533_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_533 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_533, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_533; + setArg(call_illegal_store_533, 0, reinterpret_cast(this)); + setArg(call_illegal_store_533, 1, 5); + setArg(call_illegal_store_533, 2, EEW); + setArg(call_illegal_store_533, 3, illegal_store_533_arg2); + setRet(call_illegal_store_533, 0, ret_val_illegal_store_533); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_534; + auto vsseg_534_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_534_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_534_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_534_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_534 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_534, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_534, 32, false), traits::vstart); + setArg(call_vsseg_534, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_534, 1, V); + setArg(call_vsseg_534, 2, vsseg_534_arg1); + setArg(call_vsseg_534, 3, vsseg_534_arg2); + setArg(call_vsseg_534, 4, vsseg_534_arg3); + setArg(call_vsseg_534, 5, vm); + setArg(call_vsseg_534, 6, vs3); + setArg(call_vsseg_534, 7, vsseg_534_arg6); + setArg(call_vsseg_534, 8, 7); + setArg(call_vsseg_534, 9, 5); + setRet(call_vsseg_534, 0, ret_val_vsseg_534); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 214); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 215: VSSEG6E8__V */ + continuation_e __vsseg6e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG6E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 215); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_535; + x86::Gp ret_val_get_pow_535 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_535, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_536; + x86::Gp ret_val_get_sew_pow_536 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_536, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_537; + x86::Gp ret_val_get_lmul_pow_537 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_537, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_535, ret_val_get_sew_pow_536), ret_val_get_lmul_pow_537)), 3, true); + setArg(call_get_pow_535, 0, reinterpret_cast(this)); + setArg(call_get_pow_535, 1, EEW); + setRet(call_get_pow_535, 0, ret_val_get_pow_535); + setArg(call_get_sew_pow_536, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_536, 0, ret_val_get_sew_pow_536); + setArg(call_get_lmul_pow_537, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_537, 0, ret_val_get_lmul_pow_537); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_538; + auto illegal_store_538_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_538 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_538, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_538; + setArg(call_illegal_store_538, 0, reinterpret_cast(this)); + setArg(call_illegal_store_538, 1, 6); + setArg(call_illegal_store_538, 2, EEW); + setArg(call_illegal_store_538, 3, illegal_store_538_arg2); + setRet(call_illegal_store_538, 0, ret_val_illegal_store_538); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_539; + auto vsseg_539_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_539_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_539_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_539_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_539 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_539, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_539, 32, false), traits::vstart); + setArg(call_vsseg_539, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_539, 1, V); + setArg(call_vsseg_539, 2, vsseg_539_arg1); + setArg(call_vsseg_539, 3, vsseg_539_arg2); + setArg(call_vsseg_539, 4, vsseg_539_arg3); + setArg(call_vsseg_539, 5, vm); + setArg(call_vsseg_539, 6, vs3); + setArg(call_vsseg_539, 7, vsseg_539_arg6); + setArg(call_vsseg_539, 8, 0); + setArg(call_vsseg_539, 9, 6); + setRet(call_vsseg_539, 0, ret_val_vsseg_539); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 215); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 216: VSSEG6E16__V */ + continuation_e __vsseg6e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG6E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 216); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_540; + x86::Gp ret_val_get_pow_540 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_540, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_541; + x86::Gp ret_val_get_sew_pow_541 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_541, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_542; + x86::Gp ret_val_get_lmul_pow_542 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_542, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_540, ret_val_get_sew_pow_541), ret_val_get_lmul_pow_542)), 3, true); + setArg(call_get_pow_540, 0, reinterpret_cast(this)); + setArg(call_get_pow_540, 1, EEW); + setRet(call_get_pow_540, 0, ret_val_get_pow_540); + setArg(call_get_sew_pow_541, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_541, 0, ret_val_get_sew_pow_541); + setArg(call_get_lmul_pow_542, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_542, 0, ret_val_get_lmul_pow_542); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_543; + auto illegal_store_543_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_543 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_543, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_543; + setArg(call_illegal_store_543, 0, reinterpret_cast(this)); + setArg(call_illegal_store_543, 1, 6); + setArg(call_illegal_store_543, 2, EEW); + setArg(call_illegal_store_543, 3, illegal_store_543_arg2); + setRet(call_illegal_store_543, 0, ret_val_illegal_store_543); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_544; + auto vsseg_544_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_544_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_544_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_544_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_544 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_544, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_544, 32, false), traits::vstart); + setArg(call_vsseg_544, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_544, 1, V); + setArg(call_vsseg_544, 2, vsseg_544_arg1); + setArg(call_vsseg_544, 3, vsseg_544_arg2); + setArg(call_vsseg_544, 4, vsseg_544_arg3); + setArg(call_vsseg_544, 5, vm); + setArg(call_vsseg_544, 6, vs3); + setArg(call_vsseg_544, 7, vsseg_544_arg6); + setArg(call_vsseg_544, 8, 5); + setArg(call_vsseg_544, 9, 6); + setRet(call_vsseg_544, 0, ret_val_vsseg_544); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 216); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 217: VSSEG6E32__V */ + continuation_e __vsseg6e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG6E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 217); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_545; + x86::Gp ret_val_get_pow_545 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_545, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_546; + x86::Gp ret_val_get_sew_pow_546 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_546, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_547; + x86::Gp ret_val_get_lmul_pow_547 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_547, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_545, ret_val_get_sew_pow_546), ret_val_get_lmul_pow_547)), 3, true); + setArg(call_get_pow_545, 0, reinterpret_cast(this)); + setArg(call_get_pow_545, 1, EEW); + setRet(call_get_pow_545, 0, ret_val_get_pow_545); + setArg(call_get_sew_pow_546, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_546, 0, ret_val_get_sew_pow_546); + setArg(call_get_lmul_pow_547, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_547, 0, ret_val_get_lmul_pow_547); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_548; + auto illegal_store_548_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_548 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_548, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_548; + setArg(call_illegal_store_548, 0, reinterpret_cast(this)); + setArg(call_illegal_store_548, 1, 6); + setArg(call_illegal_store_548, 2, EEW); + setArg(call_illegal_store_548, 3, illegal_store_548_arg2); + setRet(call_illegal_store_548, 0, ret_val_illegal_store_548); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_549; + auto vsseg_549_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_549_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_549_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_549_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_549 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_549, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_549, 32, false), traits::vstart); + setArg(call_vsseg_549, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_549, 1, V); + setArg(call_vsseg_549, 2, vsseg_549_arg1); + setArg(call_vsseg_549, 3, vsseg_549_arg2); + setArg(call_vsseg_549, 4, vsseg_549_arg3); + setArg(call_vsseg_549, 5, vm); + setArg(call_vsseg_549, 6, vs3); + setArg(call_vsseg_549, 7, vsseg_549_arg6); + setArg(call_vsseg_549, 8, 6); + setArg(call_vsseg_549, 9, 6); + setRet(call_vsseg_549, 0, ret_val_vsseg_549); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 217); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 218: VSSEG6E64__V */ + continuation_e __vsseg6e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG6E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 218); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_550; + x86::Gp ret_val_get_pow_550 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_550, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_551; + x86::Gp ret_val_get_sew_pow_551 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_551, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_552; + x86::Gp ret_val_get_lmul_pow_552 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_552, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_550, ret_val_get_sew_pow_551), ret_val_get_lmul_pow_552)), 3, true); + setArg(call_get_pow_550, 0, reinterpret_cast(this)); + setArg(call_get_pow_550, 1, EEW); + setRet(call_get_pow_550, 0, ret_val_get_pow_550); + setArg(call_get_sew_pow_551, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_551, 0, ret_val_get_sew_pow_551); + setArg(call_get_lmul_pow_552, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_552, 0, ret_val_get_lmul_pow_552); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_553; + auto illegal_store_553_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_553 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_553, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_553; + setArg(call_illegal_store_553, 0, reinterpret_cast(this)); + setArg(call_illegal_store_553, 1, 6); + setArg(call_illegal_store_553, 2, EEW); + setArg(call_illegal_store_553, 3, illegal_store_553_arg2); + setRet(call_illegal_store_553, 0, ret_val_illegal_store_553); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_554; + auto vsseg_554_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_554_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_554_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_554_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_554 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_554, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_554, 32, false), traits::vstart); + setArg(call_vsseg_554, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_554, 1, V); + setArg(call_vsseg_554, 2, vsseg_554_arg1); + setArg(call_vsseg_554, 3, vsseg_554_arg2); + setArg(call_vsseg_554, 4, vsseg_554_arg3); + setArg(call_vsseg_554, 5, vm); + setArg(call_vsseg_554, 6, vs3); + setArg(call_vsseg_554, 7, vsseg_554_arg6); + setArg(call_vsseg_554, 8, 7); + setArg(call_vsseg_554, 9, 6); + setRet(call_vsseg_554, 0, ret_val_vsseg_554); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 218); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 219: VSSEG7E8__V */ + continuation_e __vsseg7e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG7E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 219); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_555; + x86::Gp ret_val_get_pow_555 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_555, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_556; + x86::Gp ret_val_get_sew_pow_556 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_556, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_557; + x86::Gp ret_val_get_lmul_pow_557 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_557, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_555, ret_val_get_sew_pow_556), ret_val_get_lmul_pow_557)), 3, true); + setArg(call_get_pow_555, 0, reinterpret_cast(this)); + setArg(call_get_pow_555, 1, EEW); + setRet(call_get_pow_555, 0, ret_val_get_pow_555); + setArg(call_get_sew_pow_556, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_556, 0, ret_val_get_sew_pow_556); + setArg(call_get_lmul_pow_557, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_557, 0, ret_val_get_lmul_pow_557); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_558; + auto illegal_store_558_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_558 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_558, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_558; + setArg(call_illegal_store_558, 0, reinterpret_cast(this)); + setArg(call_illegal_store_558, 1, 7); + setArg(call_illegal_store_558, 2, EEW); + setArg(call_illegal_store_558, 3, illegal_store_558_arg2); + setRet(call_illegal_store_558, 0, ret_val_illegal_store_558); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_559; + auto vsseg_559_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_559_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_559_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_559_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_559 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_559, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_559, 32, false), traits::vstart); + setArg(call_vsseg_559, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_559, 1, V); + setArg(call_vsseg_559, 2, vsseg_559_arg1); + setArg(call_vsseg_559, 3, vsseg_559_arg2); + setArg(call_vsseg_559, 4, vsseg_559_arg3); + setArg(call_vsseg_559, 5, vm); + setArg(call_vsseg_559, 6, vs3); + setArg(call_vsseg_559, 7, vsseg_559_arg6); + setArg(call_vsseg_559, 8, 0); + setArg(call_vsseg_559, 9, 7); + setRet(call_vsseg_559, 0, ret_val_vsseg_559); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 219); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 220: VSSEG7E16__V */ + continuation_e __vsseg7e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG7E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 220); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_560; + x86::Gp ret_val_get_pow_560 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_560, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_561; + x86::Gp ret_val_get_sew_pow_561 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_561, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_562; + x86::Gp ret_val_get_lmul_pow_562 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_562, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_560, ret_val_get_sew_pow_561), ret_val_get_lmul_pow_562)), 3, true); + setArg(call_get_pow_560, 0, reinterpret_cast(this)); + setArg(call_get_pow_560, 1, EEW); + setRet(call_get_pow_560, 0, ret_val_get_pow_560); + setArg(call_get_sew_pow_561, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_561, 0, ret_val_get_sew_pow_561); + setArg(call_get_lmul_pow_562, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_562, 0, ret_val_get_lmul_pow_562); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_563; + auto illegal_store_563_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_563 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_563, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_563; + setArg(call_illegal_store_563, 0, reinterpret_cast(this)); + setArg(call_illegal_store_563, 1, 7); + setArg(call_illegal_store_563, 2, EEW); + setArg(call_illegal_store_563, 3, illegal_store_563_arg2); + setRet(call_illegal_store_563, 0, ret_val_illegal_store_563); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_564; + auto vsseg_564_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_564_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_564_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_564_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_564 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_564, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_564, 32, false), traits::vstart); + setArg(call_vsseg_564, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_564, 1, V); + setArg(call_vsseg_564, 2, vsseg_564_arg1); + setArg(call_vsseg_564, 3, vsseg_564_arg2); + setArg(call_vsseg_564, 4, vsseg_564_arg3); + setArg(call_vsseg_564, 5, vm); + setArg(call_vsseg_564, 6, vs3); + setArg(call_vsseg_564, 7, vsseg_564_arg6); + setArg(call_vsseg_564, 8, 5); + setArg(call_vsseg_564, 9, 7); + setRet(call_vsseg_564, 0, ret_val_vsseg_564); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 220); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 221: VSSEG7E32__V */ + continuation_e __vsseg7e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG7E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 221); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_565; + x86::Gp ret_val_get_pow_565 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_565, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_566; + x86::Gp ret_val_get_sew_pow_566 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_566, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_567; + x86::Gp ret_val_get_lmul_pow_567 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_567, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_565, ret_val_get_sew_pow_566), ret_val_get_lmul_pow_567)), 3, true); + setArg(call_get_pow_565, 0, reinterpret_cast(this)); + setArg(call_get_pow_565, 1, EEW); + setRet(call_get_pow_565, 0, ret_val_get_pow_565); + setArg(call_get_sew_pow_566, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_566, 0, ret_val_get_sew_pow_566); + setArg(call_get_lmul_pow_567, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_567, 0, ret_val_get_lmul_pow_567); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_568; + auto illegal_store_568_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_568 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_568, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_568; + setArg(call_illegal_store_568, 0, reinterpret_cast(this)); + setArg(call_illegal_store_568, 1, 7); + setArg(call_illegal_store_568, 2, EEW); + setArg(call_illegal_store_568, 3, illegal_store_568_arg2); + setRet(call_illegal_store_568, 0, ret_val_illegal_store_568); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_569; + auto vsseg_569_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_569_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_569_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_569_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_569 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_569, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_569, 32, false), traits::vstart); + setArg(call_vsseg_569, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_569, 1, V); + setArg(call_vsseg_569, 2, vsseg_569_arg1); + setArg(call_vsseg_569, 3, vsseg_569_arg2); + setArg(call_vsseg_569, 4, vsseg_569_arg3); + setArg(call_vsseg_569, 5, vm); + setArg(call_vsseg_569, 6, vs3); + setArg(call_vsseg_569, 7, vsseg_569_arg6); + setArg(call_vsseg_569, 8, 6); + setArg(call_vsseg_569, 9, 7); + setRet(call_vsseg_569, 0, ret_val_vsseg_569); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 221); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 222: VSSEG7E64__V */ + continuation_e __vsseg7e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG7E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 222); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_570; + x86::Gp ret_val_get_pow_570 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_570, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_571; + x86::Gp ret_val_get_sew_pow_571 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_571, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_572; + x86::Gp ret_val_get_lmul_pow_572 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_572, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_570, ret_val_get_sew_pow_571), ret_val_get_lmul_pow_572)), 3, true); + setArg(call_get_pow_570, 0, reinterpret_cast(this)); + setArg(call_get_pow_570, 1, EEW); + setRet(call_get_pow_570, 0, ret_val_get_pow_570); + setArg(call_get_sew_pow_571, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_571, 0, ret_val_get_sew_pow_571); + setArg(call_get_lmul_pow_572, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_572, 0, ret_val_get_lmul_pow_572); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_573; + auto illegal_store_573_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_573 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_573, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_573; + setArg(call_illegal_store_573, 0, reinterpret_cast(this)); + setArg(call_illegal_store_573, 1, 7); + setArg(call_illegal_store_573, 2, EEW); + setArg(call_illegal_store_573, 3, illegal_store_573_arg2); + setRet(call_illegal_store_573, 0, ret_val_illegal_store_573); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_574; + auto vsseg_574_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_574_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_574_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_574_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_574 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_574, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_574, 32, false), traits::vstart); + setArg(call_vsseg_574, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_574, 1, V); + setArg(call_vsseg_574, 2, vsseg_574_arg1); + setArg(call_vsseg_574, 3, vsseg_574_arg2); + setArg(call_vsseg_574, 4, vsseg_574_arg3); + setArg(call_vsseg_574, 5, vm); + setArg(call_vsseg_574, 6, vs3); + setArg(call_vsseg_574, 7, vsseg_574_arg6); + setArg(call_vsseg_574, 8, 7); + setArg(call_vsseg_574, 9, 7); + setRet(call_vsseg_574, 0, ret_val_vsseg_574); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 222); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 223: VSSEG8E8__V */ + continuation_e __vsseg8e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG8E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 223); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_575; + x86::Gp ret_val_get_pow_575 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_575, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_576; + x86::Gp ret_val_get_sew_pow_576 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_576, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_577; + x86::Gp ret_val_get_lmul_pow_577 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_577, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_575, ret_val_get_sew_pow_576), ret_val_get_lmul_pow_577)), 3, true); + setArg(call_get_pow_575, 0, reinterpret_cast(this)); + setArg(call_get_pow_575, 1, EEW); + setRet(call_get_pow_575, 0, ret_val_get_pow_575); + setArg(call_get_sew_pow_576, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_576, 0, ret_val_get_sew_pow_576); + setArg(call_get_lmul_pow_577, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_577, 0, ret_val_get_lmul_pow_577); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_578; + auto illegal_store_578_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_578 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_578, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_578; + setArg(call_illegal_store_578, 0, reinterpret_cast(this)); + setArg(call_illegal_store_578, 1, 8); + setArg(call_illegal_store_578, 2, EEW); + setArg(call_illegal_store_578, 3, illegal_store_578_arg2); + setRet(call_illegal_store_578, 0, ret_val_illegal_store_578); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_579; + auto vsseg_579_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_579_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_579_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_579_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_579 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_579, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_579, 32, false), traits::vstart); + setArg(call_vsseg_579, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_579, 1, V); + setArg(call_vsseg_579, 2, vsseg_579_arg1); + setArg(call_vsseg_579, 3, vsseg_579_arg2); + setArg(call_vsseg_579, 4, vsseg_579_arg3); + setArg(call_vsseg_579, 5, vm); + setArg(call_vsseg_579, 6, vs3); + setArg(call_vsseg_579, 7, vsseg_579_arg6); + setArg(call_vsseg_579, 8, 0); + setArg(call_vsseg_579, 9, 8); + setRet(call_vsseg_579, 0, ret_val_vsseg_579); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 223); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 224: VSSEG8E16__V */ + continuation_e __vsseg8e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG8E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 224); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_580; + x86::Gp ret_val_get_pow_580 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_580, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_581; + x86::Gp ret_val_get_sew_pow_581 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_581, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_582; + x86::Gp ret_val_get_lmul_pow_582 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_582, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_580, ret_val_get_sew_pow_581), ret_val_get_lmul_pow_582)), 3, true); + setArg(call_get_pow_580, 0, reinterpret_cast(this)); + setArg(call_get_pow_580, 1, EEW); + setRet(call_get_pow_580, 0, ret_val_get_pow_580); + setArg(call_get_sew_pow_581, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_581, 0, ret_val_get_sew_pow_581); + setArg(call_get_lmul_pow_582, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_582, 0, ret_val_get_lmul_pow_582); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_583; + auto illegal_store_583_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_583 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_583, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_583; + setArg(call_illegal_store_583, 0, reinterpret_cast(this)); + setArg(call_illegal_store_583, 1, 8); + setArg(call_illegal_store_583, 2, EEW); + setArg(call_illegal_store_583, 3, illegal_store_583_arg2); + setRet(call_illegal_store_583, 0, ret_val_illegal_store_583); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_584; + auto vsseg_584_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_584_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_584_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_584_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_584 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_584, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_584, 32, false), traits::vstart); + setArg(call_vsseg_584, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_584, 1, V); + setArg(call_vsseg_584, 2, vsseg_584_arg1); + setArg(call_vsseg_584, 3, vsseg_584_arg2); + setArg(call_vsseg_584, 4, vsseg_584_arg3); + setArg(call_vsseg_584, 5, vm); + setArg(call_vsseg_584, 6, vs3); + setArg(call_vsseg_584, 7, vsseg_584_arg6); + setArg(call_vsseg_584, 8, 5); + setArg(call_vsseg_584, 9, 8); + setRet(call_vsseg_584, 0, ret_val_vsseg_584); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 224); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 225: VSSEG8E32__V */ + continuation_e __vsseg8e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG8E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 225); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_585; + x86::Gp ret_val_get_pow_585 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_585, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_586; + x86::Gp ret_val_get_sew_pow_586 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_586, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_587; + x86::Gp ret_val_get_lmul_pow_587 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_587, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_585, ret_val_get_sew_pow_586), ret_val_get_lmul_pow_587)), 3, true); + setArg(call_get_pow_585, 0, reinterpret_cast(this)); + setArg(call_get_pow_585, 1, EEW); + setRet(call_get_pow_585, 0, ret_val_get_pow_585); + setArg(call_get_sew_pow_586, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_586, 0, ret_val_get_sew_pow_586); + setArg(call_get_lmul_pow_587, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_587, 0, ret_val_get_lmul_pow_587); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_588; + auto illegal_store_588_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_588 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_588, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_588; + setArg(call_illegal_store_588, 0, reinterpret_cast(this)); + setArg(call_illegal_store_588, 1, 8); + setArg(call_illegal_store_588, 2, EEW); + setArg(call_illegal_store_588, 3, illegal_store_588_arg2); + setRet(call_illegal_store_588, 0, ret_val_illegal_store_588); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_589; + auto vsseg_589_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_589_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_589_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_589_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_589 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_589, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_589, 32, false), traits::vstart); + setArg(call_vsseg_589, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_589, 1, V); + setArg(call_vsseg_589, 2, vsseg_589_arg1); + setArg(call_vsseg_589, 3, vsseg_589_arg2); + setArg(call_vsseg_589, 4, vsseg_589_arg3); + setArg(call_vsseg_589, 5, vm); + setArg(call_vsseg_589, 6, vs3); + setArg(call_vsseg_589, 7, vsseg_589_arg6); + setArg(call_vsseg_589, 8, 6); + setArg(call_vsseg_589, 9, 8); + setRet(call_vsseg_589, 0, ret_val_vsseg_589); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 225); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 226: VSSEG8E64__V */ + continuation_e __vsseg8e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG8E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 226); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_590; + x86::Gp ret_val_get_pow_590 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_590, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_591; + x86::Gp ret_val_get_sew_pow_591 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_591, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_592; + x86::Gp ret_val_get_lmul_pow_592 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_592, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_590, ret_val_get_sew_pow_591), ret_val_get_lmul_pow_592)), 3, true); + setArg(call_get_pow_590, 0, reinterpret_cast(this)); + setArg(call_get_pow_590, 1, EEW); + setRet(call_get_pow_590, 0, ret_val_get_pow_590); + setArg(call_get_sew_pow_591, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_591, 0, ret_val_get_sew_pow_591); + setArg(call_get_lmul_pow_592, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_592, 0, ret_val_get_lmul_pow_592); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_593; + auto illegal_store_593_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_593 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_593, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_593; + setArg(call_illegal_store_593, 0, reinterpret_cast(this)); + setArg(call_illegal_store_593, 1, 8); + setArg(call_illegal_store_593, 2, EEW); + setArg(call_illegal_store_593, 3, illegal_store_593_arg2); + setRet(call_illegal_store_593, 0, ret_val_illegal_store_593); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_594; + auto vsseg_594_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_594_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_594_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_594_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_594 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_594, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_594, 32, false), traits::vstart); + setArg(call_vsseg_594, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_594, 1, V); + setArg(call_vsseg_594, 2, vsseg_594_arg1); + setArg(call_vsseg_594, 3, vsseg_594_arg2); + setArg(call_vsseg_594, 4, vsseg_594_arg3); + setArg(call_vsseg_594, 5, vm); + setArg(call_vsseg_594, 6, vs3); + setArg(call_vsseg_594, 7, vsseg_594_arg6); + setArg(call_vsseg_594, 8, 7); + setArg(call_vsseg_594, 9, 8); + setRet(call_vsseg_594, 0, ret_val_vsseg_594); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 226); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 227: VLSE8__V */ + continuation_e __vlse8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 227); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_595; + x86::Gp ret_val_get_pow_595 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_595, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_596; + x86::Gp ret_val_get_sew_pow_596 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_596, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_597; + x86::Gp ret_val_get_lmul_pow_597 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_597, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_595, ret_val_get_sew_pow_596), ret_val_get_lmul_pow_597)), 3, true); + setArg(call_get_pow_595, 0, reinterpret_cast(this)); + setArg(call_get_pow_595, 1, EEW); + setRet(call_get_pow_595, 0, ret_val_get_pow_595); + setArg(call_get_sew_pow_596, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_596, 0, ret_val_get_sew_pow_596); + setArg(call_get_lmul_pow_597, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_597, 0, ret_val_get_lmul_pow_597); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_598; + auto illegal_load_598_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_598 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_598, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_598; + setArg(call_illegal_load_598, 0, reinterpret_cast(this)); + setArg(call_illegal_load_598, 1, vd); + setArg(call_illegal_load_598, 2, vm); + setArg(call_illegal_load_598, 3, 1); + setArg(call_illegal_load_598, 4, EEW); + setArg(call_illegal_load_598, 5, illegal_load_598_arg4); + setRet(call_illegal_load_598, 0, ret_val_illegal_load_598); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_599; + auto vlsseg_599_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_599_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_599_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_599_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_599_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_599 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_599, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_599, 32, false), traits::vstart); + setArg(call_vlsseg_599, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_599, 1, V); + setArg(call_vlsseg_599, 2, vlsseg_599_arg1); + setArg(call_vlsseg_599, 3, vlsseg_599_arg2); + setArg(call_vlsseg_599, 4, vlsseg_599_arg3); + setArg(call_vlsseg_599, 5, vm); + setArg(call_vlsseg_599, 6, vd); + setArg(call_vlsseg_599, 7, vlsseg_599_arg6); + setArg(call_vlsseg_599, 8, 0); + setArg(call_vlsseg_599, 9, 1); + setArg(call_vlsseg_599, 10, vlsseg_599_arg9); + setRet(call_vlsseg_599, 0, ret_val_vlsseg_599); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 227); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 228: VLSE16__V */ + continuation_e __vlse16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 228); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_600; + x86::Gp ret_val_get_pow_600 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_600, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_601; + x86::Gp ret_val_get_sew_pow_601 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_601, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_602; + x86::Gp ret_val_get_lmul_pow_602 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_602, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_600, ret_val_get_sew_pow_601), ret_val_get_lmul_pow_602)), 3, true); + setArg(call_get_pow_600, 0, reinterpret_cast(this)); + setArg(call_get_pow_600, 1, EEW); + setRet(call_get_pow_600, 0, ret_val_get_pow_600); + setArg(call_get_sew_pow_601, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_601, 0, ret_val_get_sew_pow_601); + setArg(call_get_lmul_pow_602, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_602, 0, ret_val_get_lmul_pow_602); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_603; + auto illegal_load_603_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_603 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_603, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_603; + setArg(call_illegal_load_603, 0, reinterpret_cast(this)); + setArg(call_illegal_load_603, 1, vd); + setArg(call_illegal_load_603, 2, vm); + setArg(call_illegal_load_603, 3, 1); + setArg(call_illegal_load_603, 4, EEW); + setArg(call_illegal_load_603, 5, illegal_load_603_arg4); + setRet(call_illegal_load_603, 0, ret_val_illegal_load_603); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_604; + auto vlsseg_604_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_604_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_604_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_604_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_604_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_604 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_604, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_604, 32, false), traits::vstart); + setArg(call_vlsseg_604, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_604, 1, V); + setArg(call_vlsseg_604, 2, vlsseg_604_arg1); + setArg(call_vlsseg_604, 3, vlsseg_604_arg2); + setArg(call_vlsseg_604, 4, vlsseg_604_arg3); + setArg(call_vlsseg_604, 5, vm); + setArg(call_vlsseg_604, 6, vd); + setArg(call_vlsseg_604, 7, vlsseg_604_arg6); + setArg(call_vlsseg_604, 8, 5); + setArg(call_vlsseg_604, 9, 1); + setArg(call_vlsseg_604, 10, vlsseg_604_arg9); + setRet(call_vlsseg_604, 0, ret_val_vlsseg_604); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 228); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 229: VLSE32__V */ + continuation_e __vlse32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 229); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_605; + x86::Gp ret_val_get_pow_605 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_605, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_606; + x86::Gp ret_val_get_sew_pow_606 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_606, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_607; + x86::Gp ret_val_get_lmul_pow_607 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_607, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_605, ret_val_get_sew_pow_606), ret_val_get_lmul_pow_607)), 3, true); + setArg(call_get_pow_605, 0, reinterpret_cast(this)); + setArg(call_get_pow_605, 1, EEW); + setRet(call_get_pow_605, 0, ret_val_get_pow_605); + setArg(call_get_sew_pow_606, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_606, 0, ret_val_get_sew_pow_606); + setArg(call_get_lmul_pow_607, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_607, 0, ret_val_get_lmul_pow_607); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_608; + auto illegal_load_608_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_608 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_608, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_608; + setArg(call_illegal_load_608, 0, reinterpret_cast(this)); + setArg(call_illegal_load_608, 1, vd); + setArg(call_illegal_load_608, 2, vm); + setArg(call_illegal_load_608, 3, 1); + setArg(call_illegal_load_608, 4, EEW); + setArg(call_illegal_load_608, 5, illegal_load_608_arg4); + setRet(call_illegal_load_608, 0, ret_val_illegal_load_608); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_609; + auto vlsseg_609_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_609_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_609_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_609_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_609_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_609 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_609, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_609, 32, false), traits::vstart); + setArg(call_vlsseg_609, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_609, 1, V); + setArg(call_vlsseg_609, 2, vlsseg_609_arg1); + setArg(call_vlsseg_609, 3, vlsseg_609_arg2); + setArg(call_vlsseg_609, 4, vlsseg_609_arg3); + setArg(call_vlsseg_609, 5, vm); + setArg(call_vlsseg_609, 6, vd); + setArg(call_vlsseg_609, 7, vlsseg_609_arg6); + setArg(call_vlsseg_609, 8, 6); + setArg(call_vlsseg_609, 9, 1); + setArg(call_vlsseg_609, 10, vlsseg_609_arg9); + setRet(call_vlsseg_609, 0, ret_val_vlsseg_609); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 229); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 230: VLSE64__V */ + continuation_e __vlse64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 230); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_610; + x86::Gp ret_val_get_pow_610 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_610, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_611; + x86::Gp ret_val_get_sew_pow_611 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_611, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_612; + x86::Gp ret_val_get_lmul_pow_612 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_612, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_610, ret_val_get_sew_pow_611), ret_val_get_lmul_pow_612)), 3, true); + setArg(call_get_pow_610, 0, reinterpret_cast(this)); + setArg(call_get_pow_610, 1, EEW); + setRet(call_get_pow_610, 0, ret_val_get_pow_610); + setArg(call_get_sew_pow_611, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_611, 0, ret_val_get_sew_pow_611); + setArg(call_get_lmul_pow_612, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_612, 0, ret_val_get_lmul_pow_612); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_613; + auto illegal_load_613_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_613 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_613, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_613; + setArg(call_illegal_load_613, 0, reinterpret_cast(this)); + setArg(call_illegal_load_613, 1, vd); + setArg(call_illegal_load_613, 2, vm); + setArg(call_illegal_load_613, 3, 1); + setArg(call_illegal_load_613, 4, EEW); + setArg(call_illegal_load_613, 5, illegal_load_613_arg4); + setRet(call_illegal_load_613, 0, ret_val_illegal_load_613); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_614; + auto vlsseg_614_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_614_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_614_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_614_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_614_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_614 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_614, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_614, 32, false), traits::vstart); + setArg(call_vlsseg_614, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_614, 1, V); + setArg(call_vlsseg_614, 2, vlsseg_614_arg1); + setArg(call_vlsseg_614, 3, vlsseg_614_arg2); + setArg(call_vlsseg_614, 4, vlsseg_614_arg3); + setArg(call_vlsseg_614, 5, vm); + setArg(call_vlsseg_614, 6, vd); + setArg(call_vlsseg_614, 7, vlsseg_614_arg6); + setArg(call_vlsseg_614, 8, 7); + setArg(call_vlsseg_614, 9, 1); + setArg(call_vlsseg_614, 10, vlsseg_614_arg9); + setRet(call_vlsseg_614, 0, ret_val_vlsseg_614); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 230); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 231: VLSSEG2E8__V */ + continuation_e __vlsseg2e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG2E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 231); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_615; + x86::Gp ret_val_get_pow_615 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_615, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_616; + x86::Gp ret_val_get_sew_pow_616 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_616, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_617; + x86::Gp ret_val_get_lmul_pow_617 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_617, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_615, ret_val_get_sew_pow_616), ret_val_get_lmul_pow_617)), 3, true); + setArg(call_get_pow_615, 0, reinterpret_cast(this)); + setArg(call_get_pow_615, 1, EEW); + setRet(call_get_pow_615, 0, ret_val_get_pow_615); + setArg(call_get_sew_pow_616, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_616, 0, ret_val_get_sew_pow_616); + setArg(call_get_lmul_pow_617, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_617, 0, ret_val_get_lmul_pow_617); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_618; + auto illegal_load_618_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_618 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_618, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_618; + setArg(call_illegal_load_618, 0, reinterpret_cast(this)); + setArg(call_illegal_load_618, 1, vd); + setArg(call_illegal_load_618, 2, vm); + setArg(call_illegal_load_618, 3, 2); + setArg(call_illegal_load_618, 4, EEW); + setArg(call_illegal_load_618, 5, illegal_load_618_arg4); + setRet(call_illegal_load_618, 0, ret_val_illegal_load_618); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_619; + auto vlsseg_619_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_619_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_619_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_619_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_619_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_619 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_619, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_619, 32, false), traits::vstart); + setArg(call_vlsseg_619, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_619, 1, V); + setArg(call_vlsseg_619, 2, vlsseg_619_arg1); + setArg(call_vlsseg_619, 3, vlsseg_619_arg2); + setArg(call_vlsseg_619, 4, vlsseg_619_arg3); + setArg(call_vlsseg_619, 5, vm); + setArg(call_vlsseg_619, 6, vd); + setArg(call_vlsseg_619, 7, vlsseg_619_arg6); + setArg(call_vlsseg_619, 8, 0); + setArg(call_vlsseg_619, 9, 2); + setArg(call_vlsseg_619, 10, vlsseg_619_arg9); + setRet(call_vlsseg_619, 0, ret_val_vlsseg_619); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 231); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 232: VLSSEG2E16__V */ + continuation_e __vlsseg2e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG2E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 232); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_620; + x86::Gp ret_val_get_pow_620 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_620, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_621; + x86::Gp ret_val_get_sew_pow_621 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_621, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_622; + x86::Gp ret_val_get_lmul_pow_622 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_622, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_620, ret_val_get_sew_pow_621), ret_val_get_lmul_pow_622)), 3, true); + setArg(call_get_pow_620, 0, reinterpret_cast(this)); + setArg(call_get_pow_620, 1, EEW); + setRet(call_get_pow_620, 0, ret_val_get_pow_620); + setArg(call_get_sew_pow_621, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_621, 0, ret_val_get_sew_pow_621); + setArg(call_get_lmul_pow_622, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_622, 0, ret_val_get_lmul_pow_622); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_623; + auto illegal_load_623_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_623 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_623, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_623; + setArg(call_illegal_load_623, 0, reinterpret_cast(this)); + setArg(call_illegal_load_623, 1, vd); + setArg(call_illegal_load_623, 2, vm); + setArg(call_illegal_load_623, 3, 2); + setArg(call_illegal_load_623, 4, EEW); + setArg(call_illegal_load_623, 5, illegal_load_623_arg4); + setRet(call_illegal_load_623, 0, ret_val_illegal_load_623); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_624; + auto vlsseg_624_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_624_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_624_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_624_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_624_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_624 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_624, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_624, 32, false), traits::vstart); + setArg(call_vlsseg_624, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_624, 1, V); + setArg(call_vlsseg_624, 2, vlsseg_624_arg1); + setArg(call_vlsseg_624, 3, vlsseg_624_arg2); + setArg(call_vlsseg_624, 4, vlsseg_624_arg3); + setArg(call_vlsseg_624, 5, vm); + setArg(call_vlsseg_624, 6, vd); + setArg(call_vlsseg_624, 7, vlsseg_624_arg6); + setArg(call_vlsseg_624, 8, 5); + setArg(call_vlsseg_624, 9, 2); + setArg(call_vlsseg_624, 10, vlsseg_624_arg9); + setRet(call_vlsseg_624, 0, ret_val_vlsseg_624); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 232); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 233: VLSSEG2E32__V */ + continuation_e __vlsseg2e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG2E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 233); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_625; + x86::Gp ret_val_get_pow_625 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_625, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_626; + x86::Gp ret_val_get_sew_pow_626 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_626, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_627; + x86::Gp ret_val_get_lmul_pow_627 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_627, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_625, ret_val_get_sew_pow_626), ret_val_get_lmul_pow_627)), 3, true); + setArg(call_get_pow_625, 0, reinterpret_cast(this)); + setArg(call_get_pow_625, 1, EEW); + setRet(call_get_pow_625, 0, ret_val_get_pow_625); + setArg(call_get_sew_pow_626, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_626, 0, ret_val_get_sew_pow_626); + setArg(call_get_lmul_pow_627, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_627, 0, ret_val_get_lmul_pow_627); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_628; + auto illegal_load_628_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_628 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_628, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_628; + setArg(call_illegal_load_628, 0, reinterpret_cast(this)); + setArg(call_illegal_load_628, 1, vd); + setArg(call_illegal_load_628, 2, vm); + setArg(call_illegal_load_628, 3, 2); + setArg(call_illegal_load_628, 4, EEW); + setArg(call_illegal_load_628, 5, illegal_load_628_arg4); + setRet(call_illegal_load_628, 0, ret_val_illegal_load_628); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_629; + auto vlsseg_629_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_629_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_629_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_629_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_629_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_629 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_629, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_629, 32, false), traits::vstart); + setArg(call_vlsseg_629, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_629, 1, V); + setArg(call_vlsseg_629, 2, vlsseg_629_arg1); + setArg(call_vlsseg_629, 3, vlsseg_629_arg2); + setArg(call_vlsseg_629, 4, vlsseg_629_arg3); + setArg(call_vlsseg_629, 5, vm); + setArg(call_vlsseg_629, 6, vd); + setArg(call_vlsseg_629, 7, vlsseg_629_arg6); + setArg(call_vlsseg_629, 8, 6); + setArg(call_vlsseg_629, 9, 2); + setArg(call_vlsseg_629, 10, vlsseg_629_arg9); + setRet(call_vlsseg_629, 0, ret_val_vlsseg_629); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 233); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 234: VLSSEG2E64__V */ + continuation_e __vlsseg2e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG2E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 234); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_630; + x86::Gp ret_val_get_pow_630 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_630, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_631; + x86::Gp ret_val_get_sew_pow_631 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_631, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_632; + x86::Gp ret_val_get_lmul_pow_632 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_632, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_630, ret_val_get_sew_pow_631), ret_val_get_lmul_pow_632)), 3, true); + setArg(call_get_pow_630, 0, reinterpret_cast(this)); + setArg(call_get_pow_630, 1, EEW); + setRet(call_get_pow_630, 0, ret_val_get_pow_630); + setArg(call_get_sew_pow_631, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_631, 0, ret_val_get_sew_pow_631); + setArg(call_get_lmul_pow_632, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_632, 0, ret_val_get_lmul_pow_632); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_633; + auto illegal_load_633_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_633 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_633, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_633; + setArg(call_illegal_load_633, 0, reinterpret_cast(this)); + setArg(call_illegal_load_633, 1, vd); + setArg(call_illegal_load_633, 2, vm); + setArg(call_illegal_load_633, 3, 2); + setArg(call_illegal_load_633, 4, EEW); + setArg(call_illegal_load_633, 5, illegal_load_633_arg4); + setRet(call_illegal_load_633, 0, ret_val_illegal_load_633); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_634; + auto vlsseg_634_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_634_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_634_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_634_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_634_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_634 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_634, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_634, 32, false), traits::vstart); + setArg(call_vlsseg_634, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_634, 1, V); + setArg(call_vlsseg_634, 2, vlsseg_634_arg1); + setArg(call_vlsseg_634, 3, vlsseg_634_arg2); + setArg(call_vlsseg_634, 4, vlsseg_634_arg3); + setArg(call_vlsseg_634, 5, vm); + setArg(call_vlsseg_634, 6, vd); + setArg(call_vlsseg_634, 7, vlsseg_634_arg6); + setArg(call_vlsseg_634, 8, 7); + setArg(call_vlsseg_634, 9, 2); + setArg(call_vlsseg_634, 10, vlsseg_634_arg9); + setRet(call_vlsseg_634, 0, ret_val_vlsseg_634); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 234); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 235: VLSSEG3E8__V */ + continuation_e __vlsseg3e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG3E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 235); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_635; + x86::Gp ret_val_get_pow_635 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_635, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_636; + x86::Gp ret_val_get_sew_pow_636 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_636, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_637; + x86::Gp ret_val_get_lmul_pow_637 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_637, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_635, ret_val_get_sew_pow_636), ret_val_get_lmul_pow_637)), 3, true); + setArg(call_get_pow_635, 0, reinterpret_cast(this)); + setArg(call_get_pow_635, 1, EEW); + setRet(call_get_pow_635, 0, ret_val_get_pow_635); + setArg(call_get_sew_pow_636, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_636, 0, ret_val_get_sew_pow_636); + setArg(call_get_lmul_pow_637, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_637, 0, ret_val_get_lmul_pow_637); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_638; + auto illegal_load_638_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_638 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_638, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_638; + setArg(call_illegal_load_638, 0, reinterpret_cast(this)); + setArg(call_illegal_load_638, 1, vd); + setArg(call_illegal_load_638, 2, vm); + setArg(call_illegal_load_638, 3, 3); + setArg(call_illegal_load_638, 4, EEW); + setArg(call_illegal_load_638, 5, illegal_load_638_arg4); + setRet(call_illegal_load_638, 0, ret_val_illegal_load_638); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_639; + auto vlsseg_639_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_639_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_639_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_639_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_639_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_639 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_639, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_639, 32, false), traits::vstart); + setArg(call_vlsseg_639, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_639, 1, V); + setArg(call_vlsseg_639, 2, vlsseg_639_arg1); + setArg(call_vlsseg_639, 3, vlsseg_639_arg2); + setArg(call_vlsseg_639, 4, vlsseg_639_arg3); + setArg(call_vlsseg_639, 5, vm); + setArg(call_vlsseg_639, 6, vd); + setArg(call_vlsseg_639, 7, vlsseg_639_arg6); + setArg(call_vlsseg_639, 8, 0); + setArg(call_vlsseg_639, 9, 3); + setArg(call_vlsseg_639, 10, vlsseg_639_arg9); + setRet(call_vlsseg_639, 0, ret_val_vlsseg_639); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 235); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 236: VLSSEG3E16__V */ + continuation_e __vlsseg3e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG3E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 236); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_640; + x86::Gp ret_val_get_pow_640 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_640, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_641; + x86::Gp ret_val_get_sew_pow_641 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_641, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_642; + x86::Gp ret_val_get_lmul_pow_642 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_642, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_640, ret_val_get_sew_pow_641), ret_val_get_lmul_pow_642)), 3, true); + setArg(call_get_pow_640, 0, reinterpret_cast(this)); + setArg(call_get_pow_640, 1, EEW); + setRet(call_get_pow_640, 0, ret_val_get_pow_640); + setArg(call_get_sew_pow_641, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_641, 0, ret_val_get_sew_pow_641); + setArg(call_get_lmul_pow_642, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_642, 0, ret_val_get_lmul_pow_642); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_643; + auto illegal_load_643_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_643 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_643, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_643; + setArg(call_illegal_load_643, 0, reinterpret_cast(this)); + setArg(call_illegal_load_643, 1, vd); + setArg(call_illegal_load_643, 2, vm); + setArg(call_illegal_load_643, 3, 3); + setArg(call_illegal_load_643, 4, EEW); + setArg(call_illegal_load_643, 5, illegal_load_643_arg4); + setRet(call_illegal_load_643, 0, ret_val_illegal_load_643); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_644; + auto vlsseg_644_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_644_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_644_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_644_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_644_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_644 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_644, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_644, 32, false), traits::vstart); + setArg(call_vlsseg_644, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_644, 1, V); + setArg(call_vlsseg_644, 2, vlsseg_644_arg1); + setArg(call_vlsseg_644, 3, vlsseg_644_arg2); + setArg(call_vlsseg_644, 4, vlsseg_644_arg3); + setArg(call_vlsseg_644, 5, vm); + setArg(call_vlsseg_644, 6, vd); + setArg(call_vlsseg_644, 7, vlsseg_644_arg6); + setArg(call_vlsseg_644, 8, 5); + setArg(call_vlsseg_644, 9, 3); + setArg(call_vlsseg_644, 10, vlsseg_644_arg9); + setRet(call_vlsseg_644, 0, ret_val_vlsseg_644); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 236); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 237: VLSSEG3E32__V */ + continuation_e __vlsseg3e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG3E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 237); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_645; + x86::Gp ret_val_get_pow_645 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_645, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_646; + x86::Gp ret_val_get_sew_pow_646 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_646, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_647; + x86::Gp ret_val_get_lmul_pow_647 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_647, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_645, ret_val_get_sew_pow_646), ret_val_get_lmul_pow_647)), 3, true); + setArg(call_get_pow_645, 0, reinterpret_cast(this)); + setArg(call_get_pow_645, 1, EEW); + setRet(call_get_pow_645, 0, ret_val_get_pow_645); + setArg(call_get_sew_pow_646, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_646, 0, ret_val_get_sew_pow_646); + setArg(call_get_lmul_pow_647, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_647, 0, ret_val_get_lmul_pow_647); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_648; + auto illegal_load_648_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_648 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_648, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_648; + setArg(call_illegal_load_648, 0, reinterpret_cast(this)); + setArg(call_illegal_load_648, 1, vd); + setArg(call_illegal_load_648, 2, vm); + setArg(call_illegal_load_648, 3, 3); + setArg(call_illegal_load_648, 4, EEW); + setArg(call_illegal_load_648, 5, illegal_load_648_arg4); + setRet(call_illegal_load_648, 0, ret_val_illegal_load_648); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_649; + auto vlsseg_649_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_649_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_649_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_649_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_649_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_649 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_649, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_649, 32, false), traits::vstart); + setArg(call_vlsseg_649, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_649, 1, V); + setArg(call_vlsseg_649, 2, vlsseg_649_arg1); + setArg(call_vlsseg_649, 3, vlsseg_649_arg2); + setArg(call_vlsseg_649, 4, vlsseg_649_arg3); + setArg(call_vlsseg_649, 5, vm); + setArg(call_vlsseg_649, 6, vd); + setArg(call_vlsseg_649, 7, vlsseg_649_arg6); + setArg(call_vlsseg_649, 8, 6); + setArg(call_vlsseg_649, 9, 3); + setArg(call_vlsseg_649, 10, vlsseg_649_arg9); + setRet(call_vlsseg_649, 0, ret_val_vlsseg_649); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 237); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 238: VLSSEG3E64__V */ + continuation_e __vlsseg3e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG3E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 238); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_650; + x86::Gp ret_val_get_pow_650 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_650, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_651; + x86::Gp ret_val_get_sew_pow_651 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_651, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_652; + x86::Gp ret_val_get_lmul_pow_652 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_652, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_650, ret_val_get_sew_pow_651), ret_val_get_lmul_pow_652)), 3, true); + setArg(call_get_pow_650, 0, reinterpret_cast(this)); + setArg(call_get_pow_650, 1, EEW); + setRet(call_get_pow_650, 0, ret_val_get_pow_650); + setArg(call_get_sew_pow_651, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_651, 0, ret_val_get_sew_pow_651); + setArg(call_get_lmul_pow_652, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_652, 0, ret_val_get_lmul_pow_652); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_653; + auto illegal_load_653_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_653 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_653, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_653; + setArg(call_illegal_load_653, 0, reinterpret_cast(this)); + setArg(call_illegal_load_653, 1, vd); + setArg(call_illegal_load_653, 2, vm); + setArg(call_illegal_load_653, 3, 3); + setArg(call_illegal_load_653, 4, EEW); + setArg(call_illegal_load_653, 5, illegal_load_653_arg4); + setRet(call_illegal_load_653, 0, ret_val_illegal_load_653); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_654; + auto vlsseg_654_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_654_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_654_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_654_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_654_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_654 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_654, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_654, 32, false), traits::vstart); + setArg(call_vlsseg_654, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_654, 1, V); + setArg(call_vlsseg_654, 2, vlsseg_654_arg1); + setArg(call_vlsseg_654, 3, vlsseg_654_arg2); + setArg(call_vlsseg_654, 4, vlsseg_654_arg3); + setArg(call_vlsseg_654, 5, vm); + setArg(call_vlsseg_654, 6, vd); + setArg(call_vlsseg_654, 7, vlsseg_654_arg6); + setArg(call_vlsseg_654, 8, 7); + setArg(call_vlsseg_654, 9, 3); + setArg(call_vlsseg_654, 10, vlsseg_654_arg9); + setRet(call_vlsseg_654, 0, ret_val_vlsseg_654); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 238); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 239: VLSSEG4E8__V */ + continuation_e __vlsseg4e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG4E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 239); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_655; + x86::Gp ret_val_get_pow_655 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_655, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_656; + x86::Gp ret_val_get_sew_pow_656 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_656, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_657; + x86::Gp ret_val_get_lmul_pow_657 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_657, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_655, ret_val_get_sew_pow_656), ret_val_get_lmul_pow_657)), 3, true); + setArg(call_get_pow_655, 0, reinterpret_cast(this)); + setArg(call_get_pow_655, 1, EEW); + setRet(call_get_pow_655, 0, ret_val_get_pow_655); + setArg(call_get_sew_pow_656, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_656, 0, ret_val_get_sew_pow_656); + setArg(call_get_lmul_pow_657, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_657, 0, ret_val_get_lmul_pow_657); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_658; + auto illegal_load_658_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_658 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_658, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_658; + setArg(call_illegal_load_658, 0, reinterpret_cast(this)); + setArg(call_illegal_load_658, 1, vd); + setArg(call_illegal_load_658, 2, vm); + setArg(call_illegal_load_658, 3, 4); + setArg(call_illegal_load_658, 4, EEW); + setArg(call_illegal_load_658, 5, illegal_load_658_arg4); + setRet(call_illegal_load_658, 0, ret_val_illegal_load_658); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_659; + auto vlsseg_659_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_659_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_659_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_659_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_659_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_659 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_659, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_659, 32, false), traits::vstart); + setArg(call_vlsseg_659, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_659, 1, V); + setArg(call_vlsseg_659, 2, vlsseg_659_arg1); + setArg(call_vlsseg_659, 3, vlsseg_659_arg2); + setArg(call_vlsseg_659, 4, vlsseg_659_arg3); + setArg(call_vlsseg_659, 5, vm); + setArg(call_vlsseg_659, 6, vd); + setArg(call_vlsseg_659, 7, vlsseg_659_arg6); + setArg(call_vlsseg_659, 8, 0); + setArg(call_vlsseg_659, 9, 4); + setArg(call_vlsseg_659, 10, vlsseg_659_arg9); + setRet(call_vlsseg_659, 0, ret_val_vlsseg_659); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 239); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 240: VLSSEG4E16__V */ + continuation_e __vlsseg4e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG4E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 240); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_660; + x86::Gp ret_val_get_pow_660 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_660, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_661; + x86::Gp ret_val_get_sew_pow_661 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_661, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_662; + x86::Gp ret_val_get_lmul_pow_662 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_662, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_660, ret_val_get_sew_pow_661), ret_val_get_lmul_pow_662)), 3, true); + setArg(call_get_pow_660, 0, reinterpret_cast(this)); + setArg(call_get_pow_660, 1, EEW); + setRet(call_get_pow_660, 0, ret_val_get_pow_660); + setArg(call_get_sew_pow_661, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_661, 0, ret_val_get_sew_pow_661); + setArg(call_get_lmul_pow_662, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_662, 0, ret_val_get_lmul_pow_662); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_663; + auto illegal_load_663_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_663 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_663, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_663; + setArg(call_illegal_load_663, 0, reinterpret_cast(this)); + setArg(call_illegal_load_663, 1, vd); + setArg(call_illegal_load_663, 2, vm); + setArg(call_illegal_load_663, 3, 4); + setArg(call_illegal_load_663, 4, EEW); + setArg(call_illegal_load_663, 5, illegal_load_663_arg4); + setRet(call_illegal_load_663, 0, ret_val_illegal_load_663); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_664; + auto vlsseg_664_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_664_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_664_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_664_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_664_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_664 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_664, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_664, 32, false), traits::vstart); + setArg(call_vlsseg_664, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_664, 1, V); + setArg(call_vlsseg_664, 2, vlsseg_664_arg1); + setArg(call_vlsseg_664, 3, vlsseg_664_arg2); + setArg(call_vlsseg_664, 4, vlsseg_664_arg3); + setArg(call_vlsseg_664, 5, vm); + setArg(call_vlsseg_664, 6, vd); + setArg(call_vlsseg_664, 7, vlsseg_664_arg6); + setArg(call_vlsseg_664, 8, 5); + setArg(call_vlsseg_664, 9, 4); + setArg(call_vlsseg_664, 10, vlsseg_664_arg9); + setRet(call_vlsseg_664, 0, ret_val_vlsseg_664); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 240); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 241: VLSSEG4E32__V */ + continuation_e __vlsseg4e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG4E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 241); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_665; + x86::Gp ret_val_get_pow_665 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_665, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_666; + x86::Gp ret_val_get_sew_pow_666 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_666, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_667; + x86::Gp ret_val_get_lmul_pow_667 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_667, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_665, ret_val_get_sew_pow_666), ret_val_get_lmul_pow_667)), 3, true); + setArg(call_get_pow_665, 0, reinterpret_cast(this)); + setArg(call_get_pow_665, 1, EEW); + setRet(call_get_pow_665, 0, ret_val_get_pow_665); + setArg(call_get_sew_pow_666, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_666, 0, ret_val_get_sew_pow_666); + setArg(call_get_lmul_pow_667, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_667, 0, ret_val_get_lmul_pow_667); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_668; + auto illegal_load_668_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_668 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_668, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_668; + setArg(call_illegal_load_668, 0, reinterpret_cast(this)); + setArg(call_illegal_load_668, 1, vd); + setArg(call_illegal_load_668, 2, vm); + setArg(call_illegal_load_668, 3, 4); + setArg(call_illegal_load_668, 4, EEW); + setArg(call_illegal_load_668, 5, illegal_load_668_arg4); + setRet(call_illegal_load_668, 0, ret_val_illegal_load_668); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_669; + auto vlsseg_669_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_669_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_669_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_669_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_669_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_669 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_669, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_669, 32, false), traits::vstart); + setArg(call_vlsseg_669, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_669, 1, V); + setArg(call_vlsseg_669, 2, vlsseg_669_arg1); + setArg(call_vlsseg_669, 3, vlsseg_669_arg2); + setArg(call_vlsseg_669, 4, vlsseg_669_arg3); + setArg(call_vlsseg_669, 5, vm); + setArg(call_vlsseg_669, 6, vd); + setArg(call_vlsseg_669, 7, vlsseg_669_arg6); + setArg(call_vlsseg_669, 8, 6); + setArg(call_vlsseg_669, 9, 4); + setArg(call_vlsseg_669, 10, vlsseg_669_arg9); + setRet(call_vlsseg_669, 0, ret_val_vlsseg_669); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 241); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 242: VLSSEG4E64__V */ + continuation_e __vlsseg4e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG4E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 242); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_670; + x86::Gp ret_val_get_pow_670 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_670, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_671; + x86::Gp ret_val_get_sew_pow_671 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_671, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_672; + x86::Gp ret_val_get_lmul_pow_672 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_672, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_670, ret_val_get_sew_pow_671), ret_val_get_lmul_pow_672)), 3, true); + setArg(call_get_pow_670, 0, reinterpret_cast(this)); + setArg(call_get_pow_670, 1, EEW); + setRet(call_get_pow_670, 0, ret_val_get_pow_670); + setArg(call_get_sew_pow_671, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_671, 0, ret_val_get_sew_pow_671); + setArg(call_get_lmul_pow_672, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_672, 0, ret_val_get_lmul_pow_672); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_673; + auto illegal_load_673_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_673 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_673, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_673; + setArg(call_illegal_load_673, 0, reinterpret_cast(this)); + setArg(call_illegal_load_673, 1, vd); + setArg(call_illegal_load_673, 2, vm); + setArg(call_illegal_load_673, 3, 4); + setArg(call_illegal_load_673, 4, EEW); + setArg(call_illegal_load_673, 5, illegal_load_673_arg4); + setRet(call_illegal_load_673, 0, ret_val_illegal_load_673); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_674; + auto vlsseg_674_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_674_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_674_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_674_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_674_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_674 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_674, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_674, 32, false), traits::vstart); + setArg(call_vlsseg_674, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_674, 1, V); + setArg(call_vlsseg_674, 2, vlsseg_674_arg1); + setArg(call_vlsseg_674, 3, vlsseg_674_arg2); + setArg(call_vlsseg_674, 4, vlsseg_674_arg3); + setArg(call_vlsseg_674, 5, vm); + setArg(call_vlsseg_674, 6, vd); + setArg(call_vlsseg_674, 7, vlsseg_674_arg6); + setArg(call_vlsseg_674, 8, 7); + setArg(call_vlsseg_674, 9, 4); + setArg(call_vlsseg_674, 10, vlsseg_674_arg9); + setRet(call_vlsseg_674, 0, ret_val_vlsseg_674); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 242); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 243: VLSSEG5E8__V */ + continuation_e __vlsseg5e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG5E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 243); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_675; + x86::Gp ret_val_get_pow_675 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_675, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_676; + x86::Gp ret_val_get_sew_pow_676 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_676, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_677; + x86::Gp ret_val_get_lmul_pow_677 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_677, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_675, ret_val_get_sew_pow_676), ret_val_get_lmul_pow_677)), 3, true); + setArg(call_get_pow_675, 0, reinterpret_cast(this)); + setArg(call_get_pow_675, 1, EEW); + setRet(call_get_pow_675, 0, ret_val_get_pow_675); + setArg(call_get_sew_pow_676, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_676, 0, ret_val_get_sew_pow_676); + setArg(call_get_lmul_pow_677, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_677, 0, ret_val_get_lmul_pow_677); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_678; + auto illegal_load_678_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_678 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_678, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_678; + setArg(call_illegal_load_678, 0, reinterpret_cast(this)); + setArg(call_illegal_load_678, 1, vd); + setArg(call_illegal_load_678, 2, vm); + setArg(call_illegal_load_678, 3, 5); + setArg(call_illegal_load_678, 4, EEW); + setArg(call_illegal_load_678, 5, illegal_load_678_arg4); + setRet(call_illegal_load_678, 0, ret_val_illegal_load_678); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_679; + auto vlsseg_679_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_679_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_679_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_679_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_679_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_679 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_679, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_679, 32, false), traits::vstart); + setArg(call_vlsseg_679, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_679, 1, V); + setArg(call_vlsseg_679, 2, vlsseg_679_arg1); + setArg(call_vlsseg_679, 3, vlsseg_679_arg2); + setArg(call_vlsseg_679, 4, vlsseg_679_arg3); + setArg(call_vlsseg_679, 5, vm); + setArg(call_vlsseg_679, 6, vd); + setArg(call_vlsseg_679, 7, vlsseg_679_arg6); + setArg(call_vlsseg_679, 8, 0); + setArg(call_vlsseg_679, 9, 5); + setArg(call_vlsseg_679, 10, vlsseg_679_arg9); + setRet(call_vlsseg_679, 0, ret_val_vlsseg_679); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 243); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 244: VLSSEG5E16__V */ + continuation_e __vlsseg5e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG5E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 244); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_680; + x86::Gp ret_val_get_pow_680 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_680, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_681; + x86::Gp ret_val_get_sew_pow_681 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_681, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_682; + x86::Gp ret_val_get_lmul_pow_682 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_682, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_680, ret_val_get_sew_pow_681), ret_val_get_lmul_pow_682)), 3, true); + setArg(call_get_pow_680, 0, reinterpret_cast(this)); + setArg(call_get_pow_680, 1, EEW); + setRet(call_get_pow_680, 0, ret_val_get_pow_680); + setArg(call_get_sew_pow_681, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_681, 0, ret_val_get_sew_pow_681); + setArg(call_get_lmul_pow_682, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_682, 0, ret_val_get_lmul_pow_682); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_683; + auto illegal_load_683_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_683 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_683, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_683; + setArg(call_illegal_load_683, 0, reinterpret_cast(this)); + setArg(call_illegal_load_683, 1, vd); + setArg(call_illegal_load_683, 2, vm); + setArg(call_illegal_load_683, 3, 5); + setArg(call_illegal_load_683, 4, EEW); + setArg(call_illegal_load_683, 5, illegal_load_683_arg4); + setRet(call_illegal_load_683, 0, ret_val_illegal_load_683); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_684; + auto vlsseg_684_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_684_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_684_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_684_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_684_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_684 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_684, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_684, 32, false), traits::vstart); + setArg(call_vlsseg_684, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_684, 1, V); + setArg(call_vlsseg_684, 2, vlsseg_684_arg1); + setArg(call_vlsseg_684, 3, vlsseg_684_arg2); + setArg(call_vlsseg_684, 4, vlsseg_684_arg3); + setArg(call_vlsseg_684, 5, vm); + setArg(call_vlsseg_684, 6, vd); + setArg(call_vlsseg_684, 7, vlsseg_684_arg6); + setArg(call_vlsseg_684, 8, 5); + setArg(call_vlsseg_684, 9, 5); + setArg(call_vlsseg_684, 10, vlsseg_684_arg9); + setRet(call_vlsseg_684, 0, ret_val_vlsseg_684); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 244); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 245: VLSSEG5E32__V */ + continuation_e __vlsseg5e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG5E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 245); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_685; + x86::Gp ret_val_get_pow_685 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_685, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_686; + x86::Gp ret_val_get_sew_pow_686 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_686, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_687; + x86::Gp ret_val_get_lmul_pow_687 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_687, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_685, ret_val_get_sew_pow_686), ret_val_get_lmul_pow_687)), 3, true); + setArg(call_get_pow_685, 0, reinterpret_cast(this)); + setArg(call_get_pow_685, 1, EEW); + setRet(call_get_pow_685, 0, ret_val_get_pow_685); + setArg(call_get_sew_pow_686, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_686, 0, ret_val_get_sew_pow_686); + setArg(call_get_lmul_pow_687, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_687, 0, ret_val_get_lmul_pow_687); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_688; + auto illegal_load_688_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_688 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_688, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_688; + setArg(call_illegal_load_688, 0, reinterpret_cast(this)); + setArg(call_illegal_load_688, 1, vd); + setArg(call_illegal_load_688, 2, vm); + setArg(call_illegal_load_688, 3, 5); + setArg(call_illegal_load_688, 4, EEW); + setArg(call_illegal_load_688, 5, illegal_load_688_arg4); + setRet(call_illegal_load_688, 0, ret_val_illegal_load_688); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_689; + auto vlsseg_689_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_689_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_689_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_689_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_689_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_689 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_689, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_689, 32, false), traits::vstart); + setArg(call_vlsseg_689, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_689, 1, V); + setArg(call_vlsseg_689, 2, vlsseg_689_arg1); + setArg(call_vlsseg_689, 3, vlsseg_689_arg2); + setArg(call_vlsseg_689, 4, vlsseg_689_arg3); + setArg(call_vlsseg_689, 5, vm); + setArg(call_vlsseg_689, 6, vd); + setArg(call_vlsseg_689, 7, vlsseg_689_arg6); + setArg(call_vlsseg_689, 8, 6); + setArg(call_vlsseg_689, 9, 5); + setArg(call_vlsseg_689, 10, vlsseg_689_arg9); + setRet(call_vlsseg_689, 0, ret_val_vlsseg_689); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 245); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 246: VLSSEG5E64__V */ + continuation_e __vlsseg5e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG5E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 246); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_690; + x86::Gp ret_val_get_pow_690 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_690, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_691; + x86::Gp ret_val_get_sew_pow_691 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_691, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_692; + x86::Gp ret_val_get_lmul_pow_692 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_692, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_690, ret_val_get_sew_pow_691), ret_val_get_lmul_pow_692)), 3, true); + setArg(call_get_pow_690, 0, reinterpret_cast(this)); + setArg(call_get_pow_690, 1, EEW); + setRet(call_get_pow_690, 0, ret_val_get_pow_690); + setArg(call_get_sew_pow_691, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_691, 0, ret_val_get_sew_pow_691); + setArg(call_get_lmul_pow_692, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_692, 0, ret_val_get_lmul_pow_692); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_693; + auto illegal_load_693_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_693 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_693, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_693; + setArg(call_illegal_load_693, 0, reinterpret_cast(this)); + setArg(call_illegal_load_693, 1, vd); + setArg(call_illegal_load_693, 2, vm); + setArg(call_illegal_load_693, 3, 5); + setArg(call_illegal_load_693, 4, EEW); + setArg(call_illegal_load_693, 5, illegal_load_693_arg4); + setRet(call_illegal_load_693, 0, ret_val_illegal_load_693); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_694; + auto vlsseg_694_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_694_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_694_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_694_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_694_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_694 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_694, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_694, 32, false), traits::vstart); + setArg(call_vlsseg_694, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_694, 1, V); + setArg(call_vlsseg_694, 2, vlsseg_694_arg1); + setArg(call_vlsseg_694, 3, vlsseg_694_arg2); + setArg(call_vlsseg_694, 4, vlsseg_694_arg3); + setArg(call_vlsseg_694, 5, vm); + setArg(call_vlsseg_694, 6, vd); + setArg(call_vlsseg_694, 7, vlsseg_694_arg6); + setArg(call_vlsseg_694, 8, 7); + setArg(call_vlsseg_694, 9, 5); + setArg(call_vlsseg_694, 10, vlsseg_694_arg9); + setRet(call_vlsseg_694, 0, ret_val_vlsseg_694); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 246); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 247: VLSSEG6E8__V */ + continuation_e __vlsseg6e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG6E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 247); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_695; + x86::Gp ret_val_get_pow_695 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_695, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_696; + x86::Gp ret_val_get_sew_pow_696 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_696, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_697; + x86::Gp ret_val_get_lmul_pow_697 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_697, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_695, ret_val_get_sew_pow_696), ret_val_get_lmul_pow_697)), 3, true); + setArg(call_get_pow_695, 0, reinterpret_cast(this)); + setArg(call_get_pow_695, 1, EEW); + setRet(call_get_pow_695, 0, ret_val_get_pow_695); + setArg(call_get_sew_pow_696, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_696, 0, ret_val_get_sew_pow_696); + setArg(call_get_lmul_pow_697, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_697, 0, ret_val_get_lmul_pow_697); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_698; + auto illegal_load_698_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_698 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_698, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_698; + setArg(call_illegal_load_698, 0, reinterpret_cast(this)); + setArg(call_illegal_load_698, 1, vd); + setArg(call_illegal_load_698, 2, vm); + setArg(call_illegal_load_698, 3, 6); + setArg(call_illegal_load_698, 4, EEW); + setArg(call_illegal_load_698, 5, illegal_load_698_arg4); + setRet(call_illegal_load_698, 0, ret_val_illegal_load_698); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_699; + auto vlsseg_699_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_699_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_699_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_699_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_699_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_699 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_699, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_699, 32, false), traits::vstart); + setArg(call_vlsseg_699, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_699, 1, V); + setArg(call_vlsseg_699, 2, vlsseg_699_arg1); + setArg(call_vlsseg_699, 3, vlsseg_699_arg2); + setArg(call_vlsseg_699, 4, vlsseg_699_arg3); + setArg(call_vlsseg_699, 5, vm); + setArg(call_vlsseg_699, 6, vd); + setArg(call_vlsseg_699, 7, vlsseg_699_arg6); + setArg(call_vlsseg_699, 8, 0); + setArg(call_vlsseg_699, 9, 6); + setArg(call_vlsseg_699, 10, vlsseg_699_arg9); + setRet(call_vlsseg_699, 0, ret_val_vlsseg_699); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 247); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 248: VLSSEG6E16__V */ + continuation_e __vlsseg6e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG6E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 248); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_700; + x86::Gp ret_val_get_pow_700 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_700, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_701; + x86::Gp ret_val_get_sew_pow_701 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_701, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_702; + x86::Gp ret_val_get_lmul_pow_702 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_702, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_700, ret_val_get_sew_pow_701), ret_val_get_lmul_pow_702)), 3, true); + setArg(call_get_pow_700, 0, reinterpret_cast(this)); + setArg(call_get_pow_700, 1, EEW); + setRet(call_get_pow_700, 0, ret_val_get_pow_700); + setArg(call_get_sew_pow_701, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_701, 0, ret_val_get_sew_pow_701); + setArg(call_get_lmul_pow_702, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_702, 0, ret_val_get_lmul_pow_702); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_703; + auto illegal_load_703_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_703 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_703, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_703; + setArg(call_illegal_load_703, 0, reinterpret_cast(this)); + setArg(call_illegal_load_703, 1, vd); + setArg(call_illegal_load_703, 2, vm); + setArg(call_illegal_load_703, 3, 6); + setArg(call_illegal_load_703, 4, EEW); + setArg(call_illegal_load_703, 5, illegal_load_703_arg4); + setRet(call_illegal_load_703, 0, ret_val_illegal_load_703); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_704; + auto vlsseg_704_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_704_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_704_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_704_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_704_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_704 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_704, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_704, 32, false), traits::vstart); + setArg(call_vlsseg_704, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_704, 1, V); + setArg(call_vlsseg_704, 2, vlsseg_704_arg1); + setArg(call_vlsseg_704, 3, vlsseg_704_arg2); + setArg(call_vlsseg_704, 4, vlsseg_704_arg3); + setArg(call_vlsseg_704, 5, vm); + setArg(call_vlsseg_704, 6, vd); + setArg(call_vlsseg_704, 7, vlsseg_704_arg6); + setArg(call_vlsseg_704, 8, 5); + setArg(call_vlsseg_704, 9, 6); + setArg(call_vlsseg_704, 10, vlsseg_704_arg9); + setRet(call_vlsseg_704, 0, ret_val_vlsseg_704); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 248); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 249: VLSSEG6E32__V */ + continuation_e __vlsseg6e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG6E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 249); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_705; + x86::Gp ret_val_get_pow_705 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_705, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_706; + x86::Gp ret_val_get_sew_pow_706 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_706, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_707; + x86::Gp ret_val_get_lmul_pow_707 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_707, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_705, ret_val_get_sew_pow_706), ret_val_get_lmul_pow_707)), 3, true); + setArg(call_get_pow_705, 0, reinterpret_cast(this)); + setArg(call_get_pow_705, 1, EEW); + setRet(call_get_pow_705, 0, ret_val_get_pow_705); + setArg(call_get_sew_pow_706, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_706, 0, ret_val_get_sew_pow_706); + setArg(call_get_lmul_pow_707, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_707, 0, ret_val_get_lmul_pow_707); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_708; + auto illegal_load_708_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_708 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_708, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_708; + setArg(call_illegal_load_708, 0, reinterpret_cast(this)); + setArg(call_illegal_load_708, 1, vd); + setArg(call_illegal_load_708, 2, vm); + setArg(call_illegal_load_708, 3, 6); + setArg(call_illegal_load_708, 4, EEW); + setArg(call_illegal_load_708, 5, illegal_load_708_arg4); + setRet(call_illegal_load_708, 0, ret_val_illegal_load_708); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_709; + auto vlsseg_709_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_709_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_709_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_709_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_709_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_709 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_709, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_709, 32, false), traits::vstart); + setArg(call_vlsseg_709, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_709, 1, V); + setArg(call_vlsseg_709, 2, vlsseg_709_arg1); + setArg(call_vlsseg_709, 3, vlsseg_709_arg2); + setArg(call_vlsseg_709, 4, vlsseg_709_arg3); + setArg(call_vlsseg_709, 5, vm); + setArg(call_vlsseg_709, 6, vd); + setArg(call_vlsseg_709, 7, vlsseg_709_arg6); + setArg(call_vlsseg_709, 8, 6); + setArg(call_vlsseg_709, 9, 6); + setArg(call_vlsseg_709, 10, vlsseg_709_arg9); + setRet(call_vlsseg_709, 0, ret_val_vlsseg_709); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 249); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 250: VLSSEG6E64__V */ + continuation_e __vlsseg6e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG6E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 250); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_710; + x86::Gp ret_val_get_pow_710 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_710, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_711; + x86::Gp ret_val_get_sew_pow_711 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_711, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_712; + x86::Gp ret_val_get_lmul_pow_712 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_712, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_710, ret_val_get_sew_pow_711), ret_val_get_lmul_pow_712)), 3, true); + setArg(call_get_pow_710, 0, reinterpret_cast(this)); + setArg(call_get_pow_710, 1, EEW); + setRet(call_get_pow_710, 0, ret_val_get_pow_710); + setArg(call_get_sew_pow_711, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_711, 0, ret_val_get_sew_pow_711); + setArg(call_get_lmul_pow_712, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_712, 0, ret_val_get_lmul_pow_712); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_713; + auto illegal_load_713_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_713 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_713, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_713; + setArg(call_illegal_load_713, 0, reinterpret_cast(this)); + setArg(call_illegal_load_713, 1, vd); + setArg(call_illegal_load_713, 2, vm); + setArg(call_illegal_load_713, 3, 6); + setArg(call_illegal_load_713, 4, EEW); + setArg(call_illegal_load_713, 5, illegal_load_713_arg4); + setRet(call_illegal_load_713, 0, ret_val_illegal_load_713); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_714; + auto vlsseg_714_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_714_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_714_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_714_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_714_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_714 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_714, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_714, 32, false), traits::vstart); + setArg(call_vlsseg_714, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_714, 1, V); + setArg(call_vlsseg_714, 2, vlsseg_714_arg1); + setArg(call_vlsseg_714, 3, vlsseg_714_arg2); + setArg(call_vlsseg_714, 4, vlsseg_714_arg3); + setArg(call_vlsseg_714, 5, vm); + setArg(call_vlsseg_714, 6, vd); + setArg(call_vlsseg_714, 7, vlsseg_714_arg6); + setArg(call_vlsseg_714, 8, 7); + setArg(call_vlsseg_714, 9, 6); + setArg(call_vlsseg_714, 10, vlsseg_714_arg9); + setRet(call_vlsseg_714, 0, ret_val_vlsseg_714); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 250); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 251: VLSSEG7E8__V */ + continuation_e __vlsseg7e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG7E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 251); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_715; + x86::Gp ret_val_get_pow_715 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_715, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_716; + x86::Gp ret_val_get_sew_pow_716 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_716, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_717; + x86::Gp ret_val_get_lmul_pow_717 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_717, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_715, ret_val_get_sew_pow_716), ret_val_get_lmul_pow_717)), 3, true); + setArg(call_get_pow_715, 0, reinterpret_cast(this)); + setArg(call_get_pow_715, 1, EEW); + setRet(call_get_pow_715, 0, ret_val_get_pow_715); + setArg(call_get_sew_pow_716, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_716, 0, ret_val_get_sew_pow_716); + setArg(call_get_lmul_pow_717, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_717, 0, ret_val_get_lmul_pow_717); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_718; + auto illegal_load_718_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_718 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_718, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_718; + setArg(call_illegal_load_718, 0, reinterpret_cast(this)); + setArg(call_illegal_load_718, 1, vd); + setArg(call_illegal_load_718, 2, vm); + setArg(call_illegal_load_718, 3, 7); + setArg(call_illegal_load_718, 4, EEW); + setArg(call_illegal_load_718, 5, illegal_load_718_arg4); + setRet(call_illegal_load_718, 0, ret_val_illegal_load_718); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_719; + auto vlsseg_719_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_719_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_719_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_719_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_719_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_719 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_719, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_719, 32, false), traits::vstart); + setArg(call_vlsseg_719, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_719, 1, V); + setArg(call_vlsseg_719, 2, vlsseg_719_arg1); + setArg(call_vlsseg_719, 3, vlsseg_719_arg2); + setArg(call_vlsseg_719, 4, vlsseg_719_arg3); + setArg(call_vlsseg_719, 5, vm); + setArg(call_vlsseg_719, 6, vd); + setArg(call_vlsseg_719, 7, vlsseg_719_arg6); + setArg(call_vlsseg_719, 8, 0); + setArg(call_vlsseg_719, 9, 7); + setArg(call_vlsseg_719, 10, vlsseg_719_arg9); + setRet(call_vlsseg_719, 0, ret_val_vlsseg_719); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 251); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 252: VLSSEG7E16__V */ + continuation_e __vlsseg7e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG7E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 252); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_720; + x86::Gp ret_val_get_pow_720 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_720, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_721; + x86::Gp ret_val_get_sew_pow_721 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_721, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_722; + x86::Gp ret_val_get_lmul_pow_722 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_722, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_720, ret_val_get_sew_pow_721), ret_val_get_lmul_pow_722)), 3, true); + setArg(call_get_pow_720, 0, reinterpret_cast(this)); + setArg(call_get_pow_720, 1, EEW); + setRet(call_get_pow_720, 0, ret_val_get_pow_720); + setArg(call_get_sew_pow_721, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_721, 0, ret_val_get_sew_pow_721); + setArg(call_get_lmul_pow_722, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_722, 0, ret_val_get_lmul_pow_722); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_723; + auto illegal_load_723_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_723 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_723, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_723; + setArg(call_illegal_load_723, 0, reinterpret_cast(this)); + setArg(call_illegal_load_723, 1, vd); + setArg(call_illegal_load_723, 2, vm); + setArg(call_illegal_load_723, 3, 7); + setArg(call_illegal_load_723, 4, EEW); + setArg(call_illegal_load_723, 5, illegal_load_723_arg4); + setRet(call_illegal_load_723, 0, ret_val_illegal_load_723); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_724; + auto vlsseg_724_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_724_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_724_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_724_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_724_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_724 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_724, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_724, 32, false), traits::vstart); + setArg(call_vlsseg_724, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_724, 1, V); + setArg(call_vlsseg_724, 2, vlsseg_724_arg1); + setArg(call_vlsseg_724, 3, vlsseg_724_arg2); + setArg(call_vlsseg_724, 4, vlsseg_724_arg3); + setArg(call_vlsseg_724, 5, vm); + setArg(call_vlsseg_724, 6, vd); + setArg(call_vlsseg_724, 7, vlsseg_724_arg6); + setArg(call_vlsseg_724, 8, 5); + setArg(call_vlsseg_724, 9, 7); + setArg(call_vlsseg_724, 10, vlsseg_724_arg9); + setRet(call_vlsseg_724, 0, ret_val_vlsseg_724); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 252); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 253: VLSSEG7E32__V */ + continuation_e __vlsseg7e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG7E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 253); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_725; + x86::Gp ret_val_get_pow_725 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_725, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_726; + x86::Gp ret_val_get_sew_pow_726 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_726, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_727; + x86::Gp ret_val_get_lmul_pow_727 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_727, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_725, ret_val_get_sew_pow_726), ret_val_get_lmul_pow_727)), 3, true); + setArg(call_get_pow_725, 0, reinterpret_cast(this)); + setArg(call_get_pow_725, 1, EEW); + setRet(call_get_pow_725, 0, ret_val_get_pow_725); + setArg(call_get_sew_pow_726, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_726, 0, ret_val_get_sew_pow_726); + setArg(call_get_lmul_pow_727, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_727, 0, ret_val_get_lmul_pow_727); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_728; + auto illegal_load_728_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_728 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_728, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_728; + setArg(call_illegal_load_728, 0, reinterpret_cast(this)); + setArg(call_illegal_load_728, 1, vd); + setArg(call_illegal_load_728, 2, vm); + setArg(call_illegal_load_728, 3, 7); + setArg(call_illegal_load_728, 4, EEW); + setArg(call_illegal_load_728, 5, illegal_load_728_arg4); + setRet(call_illegal_load_728, 0, ret_val_illegal_load_728); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_729; + auto vlsseg_729_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_729_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_729_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_729_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_729_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_729 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_729, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_729, 32, false), traits::vstart); + setArg(call_vlsseg_729, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_729, 1, V); + setArg(call_vlsseg_729, 2, vlsseg_729_arg1); + setArg(call_vlsseg_729, 3, vlsseg_729_arg2); + setArg(call_vlsseg_729, 4, vlsseg_729_arg3); + setArg(call_vlsseg_729, 5, vm); + setArg(call_vlsseg_729, 6, vd); + setArg(call_vlsseg_729, 7, vlsseg_729_arg6); + setArg(call_vlsseg_729, 8, 6); + setArg(call_vlsseg_729, 9, 7); + setArg(call_vlsseg_729, 10, vlsseg_729_arg9); + setRet(call_vlsseg_729, 0, ret_val_vlsseg_729); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 253); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 254: VLSSEG7E64__V */ + continuation_e __vlsseg7e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG7E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 254); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_730; + x86::Gp ret_val_get_pow_730 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_730, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_731; + x86::Gp ret_val_get_sew_pow_731 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_731, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_732; + x86::Gp ret_val_get_lmul_pow_732 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_732, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_730, ret_val_get_sew_pow_731), ret_val_get_lmul_pow_732)), 3, true); + setArg(call_get_pow_730, 0, reinterpret_cast(this)); + setArg(call_get_pow_730, 1, EEW); + setRet(call_get_pow_730, 0, ret_val_get_pow_730); + setArg(call_get_sew_pow_731, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_731, 0, ret_val_get_sew_pow_731); + setArg(call_get_lmul_pow_732, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_732, 0, ret_val_get_lmul_pow_732); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_733; + auto illegal_load_733_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_733 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_733, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_733; + setArg(call_illegal_load_733, 0, reinterpret_cast(this)); + setArg(call_illegal_load_733, 1, vd); + setArg(call_illegal_load_733, 2, vm); + setArg(call_illegal_load_733, 3, 7); + setArg(call_illegal_load_733, 4, EEW); + setArg(call_illegal_load_733, 5, illegal_load_733_arg4); + setRet(call_illegal_load_733, 0, ret_val_illegal_load_733); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_734; + auto vlsseg_734_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_734_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_734_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_734_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_734_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_734 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_734, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_734, 32, false), traits::vstart); + setArg(call_vlsseg_734, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_734, 1, V); + setArg(call_vlsseg_734, 2, vlsseg_734_arg1); + setArg(call_vlsseg_734, 3, vlsseg_734_arg2); + setArg(call_vlsseg_734, 4, vlsseg_734_arg3); + setArg(call_vlsseg_734, 5, vm); + setArg(call_vlsseg_734, 6, vd); + setArg(call_vlsseg_734, 7, vlsseg_734_arg6); + setArg(call_vlsseg_734, 8, 7); + setArg(call_vlsseg_734, 9, 7); + setArg(call_vlsseg_734, 10, vlsseg_734_arg9); + setRet(call_vlsseg_734, 0, ret_val_vlsseg_734); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 254); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 255: VLSSEG8E8__V */ + continuation_e __vlsseg8e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG8E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 255); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_735; + x86::Gp ret_val_get_pow_735 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_735, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_736; + x86::Gp ret_val_get_sew_pow_736 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_736, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_737; + x86::Gp ret_val_get_lmul_pow_737 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_737, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_735, ret_val_get_sew_pow_736), ret_val_get_lmul_pow_737)), 3, true); + setArg(call_get_pow_735, 0, reinterpret_cast(this)); + setArg(call_get_pow_735, 1, EEW); + setRet(call_get_pow_735, 0, ret_val_get_pow_735); + setArg(call_get_sew_pow_736, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_736, 0, ret_val_get_sew_pow_736); + setArg(call_get_lmul_pow_737, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_737, 0, ret_val_get_lmul_pow_737); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_738; + auto illegal_load_738_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_738 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_738, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_738; + setArg(call_illegal_load_738, 0, reinterpret_cast(this)); + setArg(call_illegal_load_738, 1, vd); + setArg(call_illegal_load_738, 2, vm); + setArg(call_illegal_load_738, 3, 8); + setArg(call_illegal_load_738, 4, EEW); + setArg(call_illegal_load_738, 5, illegal_load_738_arg4); + setRet(call_illegal_load_738, 0, ret_val_illegal_load_738); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_739; + auto vlsseg_739_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_739_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_739_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_739_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_739_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_739 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_739, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_739, 32, false), traits::vstart); + setArg(call_vlsseg_739, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_739, 1, V); + setArg(call_vlsseg_739, 2, vlsseg_739_arg1); + setArg(call_vlsseg_739, 3, vlsseg_739_arg2); + setArg(call_vlsseg_739, 4, vlsseg_739_arg3); + setArg(call_vlsseg_739, 5, vm); + setArg(call_vlsseg_739, 6, vd); + setArg(call_vlsseg_739, 7, vlsseg_739_arg6); + setArg(call_vlsseg_739, 8, 0); + setArg(call_vlsseg_739, 9, 8); + setArg(call_vlsseg_739, 10, vlsseg_739_arg9); + setRet(call_vlsseg_739, 0, ret_val_vlsseg_739); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 255); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 256: VLSSEG8E16__V */ + continuation_e __vlsseg8e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG8E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 256); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_740; + x86::Gp ret_val_get_pow_740 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_740, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_741; + x86::Gp ret_val_get_sew_pow_741 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_741, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_742; + x86::Gp ret_val_get_lmul_pow_742 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_742, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_740, ret_val_get_sew_pow_741), ret_val_get_lmul_pow_742)), 3, true); + setArg(call_get_pow_740, 0, reinterpret_cast(this)); + setArg(call_get_pow_740, 1, EEW); + setRet(call_get_pow_740, 0, ret_val_get_pow_740); + setArg(call_get_sew_pow_741, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_741, 0, ret_val_get_sew_pow_741); + setArg(call_get_lmul_pow_742, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_742, 0, ret_val_get_lmul_pow_742); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_743; + auto illegal_load_743_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_743 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_743, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_743; + setArg(call_illegal_load_743, 0, reinterpret_cast(this)); + setArg(call_illegal_load_743, 1, vd); + setArg(call_illegal_load_743, 2, vm); + setArg(call_illegal_load_743, 3, 8); + setArg(call_illegal_load_743, 4, EEW); + setArg(call_illegal_load_743, 5, illegal_load_743_arg4); + setRet(call_illegal_load_743, 0, ret_val_illegal_load_743); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_744; + auto vlsseg_744_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_744_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_744_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_744_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_744_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_744 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_744, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_744, 32, false), traits::vstart); + setArg(call_vlsseg_744, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_744, 1, V); + setArg(call_vlsseg_744, 2, vlsseg_744_arg1); + setArg(call_vlsseg_744, 3, vlsseg_744_arg2); + setArg(call_vlsseg_744, 4, vlsseg_744_arg3); + setArg(call_vlsseg_744, 5, vm); + setArg(call_vlsseg_744, 6, vd); + setArg(call_vlsseg_744, 7, vlsseg_744_arg6); + setArg(call_vlsseg_744, 8, 5); + setArg(call_vlsseg_744, 9, 8); + setArg(call_vlsseg_744, 10, vlsseg_744_arg9); + setRet(call_vlsseg_744, 0, ret_val_vlsseg_744); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 256); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 257: VLSSEG8E32__V */ + continuation_e __vlsseg8e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG8E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 257); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_745; + x86::Gp ret_val_get_pow_745 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_745, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_746; + x86::Gp ret_val_get_sew_pow_746 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_746, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_747; + x86::Gp ret_val_get_lmul_pow_747 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_747, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_745, ret_val_get_sew_pow_746), ret_val_get_lmul_pow_747)), 3, true); + setArg(call_get_pow_745, 0, reinterpret_cast(this)); + setArg(call_get_pow_745, 1, EEW); + setRet(call_get_pow_745, 0, ret_val_get_pow_745); + setArg(call_get_sew_pow_746, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_746, 0, ret_val_get_sew_pow_746); + setArg(call_get_lmul_pow_747, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_747, 0, ret_val_get_lmul_pow_747); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_748; + auto illegal_load_748_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_748 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_748, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_748; + setArg(call_illegal_load_748, 0, reinterpret_cast(this)); + setArg(call_illegal_load_748, 1, vd); + setArg(call_illegal_load_748, 2, vm); + setArg(call_illegal_load_748, 3, 8); + setArg(call_illegal_load_748, 4, EEW); + setArg(call_illegal_load_748, 5, illegal_load_748_arg4); + setRet(call_illegal_load_748, 0, ret_val_illegal_load_748); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_749; + auto vlsseg_749_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_749_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_749_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_749_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_749_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_749 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_749, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_749, 32, false), traits::vstart); + setArg(call_vlsseg_749, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_749, 1, V); + setArg(call_vlsseg_749, 2, vlsseg_749_arg1); + setArg(call_vlsseg_749, 3, vlsseg_749_arg2); + setArg(call_vlsseg_749, 4, vlsseg_749_arg3); + setArg(call_vlsseg_749, 5, vm); + setArg(call_vlsseg_749, 6, vd); + setArg(call_vlsseg_749, 7, vlsseg_749_arg6); + setArg(call_vlsseg_749, 8, 6); + setArg(call_vlsseg_749, 9, 8); + setArg(call_vlsseg_749, 10, vlsseg_749_arg9); + setRet(call_vlsseg_749, 0, ret_val_vlsseg_749); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 257); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 258: VLSSEG8E64__V */ + continuation_e __vlsseg8e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG8E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 258); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_750; + x86::Gp ret_val_get_pow_750 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_750, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_751; + x86::Gp ret_val_get_sew_pow_751 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_751, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_752; + x86::Gp ret_val_get_lmul_pow_752 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_752, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_750, ret_val_get_sew_pow_751), ret_val_get_lmul_pow_752)), 3, true); + setArg(call_get_pow_750, 0, reinterpret_cast(this)); + setArg(call_get_pow_750, 1, EEW); + setRet(call_get_pow_750, 0, ret_val_get_pow_750); + setArg(call_get_sew_pow_751, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_751, 0, ret_val_get_sew_pow_751); + setArg(call_get_lmul_pow_752, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_752, 0, ret_val_get_lmul_pow_752); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_753; + auto illegal_load_753_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_753 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_753, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_753; + setArg(call_illegal_load_753, 0, reinterpret_cast(this)); + setArg(call_illegal_load_753, 1, vd); + setArg(call_illegal_load_753, 2, vm); + setArg(call_illegal_load_753, 3, 8); + setArg(call_illegal_load_753, 4, EEW); + setArg(call_illegal_load_753, 5, illegal_load_753_arg4); + setRet(call_illegal_load_753, 0, ret_val_illegal_load_753); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_754; + auto vlsseg_754_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_754_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_754_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_754_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_754_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_754 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_754, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_754, 32, false), traits::vstart); + setArg(call_vlsseg_754, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_754, 1, V); + setArg(call_vlsseg_754, 2, vlsseg_754_arg1); + setArg(call_vlsseg_754, 3, vlsseg_754_arg2); + setArg(call_vlsseg_754, 4, vlsseg_754_arg3); + setArg(call_vlsseg_754, 5, vm); + setArg(call_vlsseg_754, 6, vd); + setArg(call_vlsseg_754, 7, vlsseg_754_arg6); + setArg(call_vlsseg_754, 8, 7); + setArg(call_vlsseg_754, 9, 8); + setArg(call_vlsseg_754, 10, vlsseg_754_arg9); + setRet(call_vlsseg_754, 0, ret_val_vlsseg_754); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 258); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 259: VSSE8__V */ + continuation_e __vsse8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 259); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_755; + x86::Gp ret_val_get_pow_755 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_755, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_756; + x86::Gp ret_val_get_sew_pow_756 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_756, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_757; + x86::Gp ret_val_get_lmul_pow_757 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_757, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_755, ret_val_get_sew_pow_756), ret_val_get_lmul_pow_757)), 3, true); + setArg(call_get_pow_755, 0, reinterpret_cast(this)); + setArg(call_get_pow_755, 1, EEW); + setRet(call_get_pow_755, 0, ret_val_get_pow_755); + setArg(call_get_sew_pow_756, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_756, 0, ret_val_get_sew_pow_756); + setArg(call_get_lmul_pow_757, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_757, 0, ret_val_get_lmul_pow_757); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_758; + auto illegal_store_758_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_758 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_758, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_758; + setArg(call_illegal_store_758, 0, reinterpret_cast(this)); + setArg(call_illegal_store_758, 1, 1); + setArg(call_illegal_store_758, 2, EEW); + setArg(call_illegal_store_758, 3, illegal_store_758_arg2); + setRet(call_illegal_store_758, 0, ret_val_illegal_store_758); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_759; + auto vssseg_759_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_759_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_759_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_759_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_759_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_759 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_759, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_759, 32, false), traits::vstart); + setArg(call_vssseg_759, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_759, 1, V); + setArg(call_vssseg_759, 2, vssseg_759_arg1); + setArg(call_vssseg_759, 3, vssseg_759_arg2); + setArg(call_vssseg_759, 4, vssseg_759_arg3); + setArg(call_vssseg_759, 5, vm); + setArg(call_vssseg_759, 6, vs3); + setArg(call_vssseg_759, 7, vssseg_759_arg6); + setArg(call_vssseg_759, 8, 0); + setArg(call_vssseg_759, 9, 1); + setArg(call_vssseg_759, 10, vssseg_759_arg9); + setRet(call_vssseg_759, 0, ret_val_vssseg_759); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 259); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 260: VSSE16__V */ + continuation_e __vsse16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 260); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_760; + x86::Gp ret_val_get_pow_760 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_760, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_761; + x86::Gp ret_val_get_sew_pow_761 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_761, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_762; + x86::Gp ret_val_get_lmul_pow_762 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_762, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_760, ret_val_get_sew_pow_761), ret_val_get_lmul_pow_762)), 3, true); + setArg(call_get_pow_760, 0, reinterpret_cast(this)); + setArg(call_get_pow_760, 1, EEW); + setRet(call_get_pow_760, 0, ret_val_get_pow_760); + setArg(call_get_sew_pow_761, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_761, 0, ret_val_get_sew_pow_761); + setArg(call_get_lmul_pow_762, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_762, 0, ret_val_get_lmul_pow_762); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_763; + auto illegal_store_763_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_763 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_763, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_763; + setArg(call_illegal_store_763, 0, reinterpret_cast(this)); + setArg(call_illegal_store_763, 1, 1); + setArg(call_illegal_store_763, 2, EEW); + setArg(call_illegal_store_763, 3, illegal_store_763_arg2); + setRet(call_illegal_store_763, 0, ret_val_illegal_store_763); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_764; + auto vssseg_764_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_764_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_764_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_764_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_764_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_764 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_764, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_764, 32, false), traits::vstart); + setArg(call_vssseg_764, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_764, 1, V); + setArg(call_vssseg_764, 2, vssseg_764_arg1); + setArg(call_vssseg_764, 3, vssseg_764_arg2); + setArg(call_vssseg_764, 4, vssseg_764_arg3); + setArg(call_vssseg_764, 5, vm); + setArg(call_vssseg_764, 6, vs3); + setArg(call_vssseg_764, 7, vssseg_764_arg6); + setArg(call_vssseg_764, 8, 5); + setArg(call_vssseg_764, 9, 1); + setArg(call_vssseg_764, 10, vssseg_764_arg9); + setRet(call_vssseg_764, 0, ret_val_vssseg_764); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 260); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 261: VSSE32__V */ + continuation_e __vsse32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 261); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_765; + x86::Gp ret_val_get_pow_765 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_765, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_766; + x86::Gp ret_val_get_sew_pow_766 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_766, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_767; + x86::Gp ret_val_get_lmul_pow_767 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_767, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_765, ret_val_get_sew_pow_766), ret_val_get_lmul_pow_767)), 3, true); + setArg(call_get_pow_765, 0, reinterpret_cast(this)); + setArg(call_get_pow_765, 1, EEW); + setRet(call_get_pow_765, 0, ret_val_get_pow_765); + setArg(call_get_sew_pow_766, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_766, 0, ret_val_get_sew_pow_766); + setArg(call_get_lmul_pow_767, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_767, 0, ret_val_get_lmul_pow_767); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_768; + auto illegal_store_768_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_768 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_768, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_768; + setArg(call_illegal_store_768, 0, reinterpret_cast(this)); + setArg(call_illegal_store_768, 1, 1); + setArg(call_illegal_store_768, 2, EEW); + setArg(call_illegal_store_768, 3, illegal_store_768_arg2); + setRet(call_illegal_store_768, 0, ret_val_illegal_store_768); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_769; + auto vssseg_769_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_769_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_769_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_769_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_769_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_769 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_769, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_769, 32, false), traits::vstart); + setArg(call_vssseg_769, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_769, 1, V); + setArg(call_vssseg_769, 2, vssseg_769_arg1); + setArg(call_vssseg_769, 3, vssseg_769_arg2); + setArg(call_vssseg_769, 4, vssseg_769_arg3); + setArg(call_vssseg_769, 5, vm); + setArg(call_vssseg_769, 6, vs3); + setArg(call_vssseg_769, 7, vssseg_769_arg6); + setArg(call_vssseg_769, 8, 6); + setArg(call_vssseg_769, 9, 1); + setArg(call_vssseg_769, 10, vssseg_769_arg9); + setRet(call_vssseg_769, 0, ret_val_vssseg_769); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 261); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 262: VSSE64__V */ + continuation_e __vsse64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 262); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_770; + x86::Gp ret_val_get_pow_770 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_770, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_771; + x86::Gp ret_val_get_sew_pow_771 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_771, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_772; + x86::Gp ret_val_get_lmul_pow_772 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_772, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_770, ret_val_get_sew_pow_771), ret_val_get_lmul_pow_772)), 3, true); + setArg(call_get_pow_770, 0, reinterpret_cast(this)); + setArg(call_get_pow_770, 1, EEW); + setRet(call_get_pow_770, 0, ret_val_get_pow_770); + setArg(call_get_sew_pow_771, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_771, 0, ret_val_get_sew_pow_771); + setArg(call_get_lmul_pow_772, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_772, 0, ret_val_get_lmul_pow_772); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_773; + auto illegal_store_773_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_773 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_773, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_773; + setArg(call_illegal_store_773, 0, reinterpret_cast(this)); + setArg(call_illegal_store_773, 1, 1); + setArg(call_illegal_store_773, 2, EEW); + setArg(call_illegal_store_773, 3, illegal_store_773_arg2); + setRet(call_illegal_store_773, 0, ret_val_illegal_store_773); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_774; + auto vssseg_774_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_774_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_774_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_774_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_774_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_774 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_774, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_774, 32, false), traits::vstart); + setArg(call_vssseg_774, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_774, 1, V); + setArg(call_vssseg_774, 2, vssseg_774_arg1); + setArg(call_vssseg_774, 3, vssseg_774_arg2); + setArg(call_vssseg_774, 4, vssseg_774_arg3); + setArg(call_vssseg_774, 5, vm); + setArg(call_vssseg_774, 6, vs3); + setArg(call_vssseg_774, 7, vssseg_774_arg6); + setArg(call_vssseg_774, 8, 7); + setArg(call_vssseg_774, 9, 1); + setArg(call_vssseg_774, 10, vssseg_774_arg9); + setRet(call_vssseg_774, 0, ret_val_vssseg_774); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 262); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 263: VSSSEG2E8__V */ + continuation_e __vssseg2e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG2E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 263); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_775; + x86::Gp ret_val_get_pow_775 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_775, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_776; + x86::Gp ret_val_get_sew_pow_776 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_776, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_777; + x86::Gp ret_val_get_lmul_pow_777 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_777, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_775, ret_val_get_sew_pow_776), ret_val_get_lmul_pow_777)), 3, true); + setArg(call_get_pow_775, 0, reinterpret_cast(this)); + setArg(call_get_pow_775, 1, EEW); + setRet(call_get_pow_775, 0, ret_val_get_pow_775); + setArg(call_get_sew_pow_776, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_776, 0, ret_val_get_sew_pow_776); + setArg(call_get_lmul_pow_777, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_777, 0, ret_val_get_lmul_pow_777); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_778; + auto illegal_store_778_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_778 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_778, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_778; + setArg(call_illegal_store_778, 0, reinterpret_cast(this)); + setArg(call_illegal_store_778, 1, 2); + setArg(call_illegal_store_778, 2, EEW); + setArg(call_illegal_store_778, 3, illegal_store_778_arg2); + setRet(call_illegal_store_778, 0, ret_val_illegal_store_778); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_779; + auto vssseg_779_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_779_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_779_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_779_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_779_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_779 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_779, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_779, 32, false), traits::vstart); + setArg(call_vssseg_779, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_779, 1, V); + setArg(call_vssseg_779, 2, vssseg_779_arg1); + setArg(call_vssseg_779, 3, vssseg_779_arg2); + setArg(call_vssseg_779, 4, vssseg_779_arg3); + setArg(call_vssseg_779, 5, vm); + setArg(call_vssseg_779, 6, vs3); + setArg(call_vssseg_779, 7, vssseg_779_arg6); + setArg(call_vssseg_779, 8, 0); + setArg(call_vssseg_779, 9, 2); + setArg(call_vssseg_779, 10, vssseg_779_arg9); + setRet(call_vssseg_779, 0, ret_val_vssseg_779); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 263); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 264: VSSSEG2E16__V */ + continuation_e __vssseg2e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG2E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 264); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_780; + x86::Gp ret_val_get_pow_780 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_780, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_781; + x86::Gp ret_val_get_sew_pow_781 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_781, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_782; + x86::Gp ret_val_get_lmul_pow_782 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_782, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_780, ret_val_get_sew_pow_781), ret_val_get_lmul_pow_782)), 3, true); + setArg(call_get_pow_780, 0, reinterpret_cast(this)); + setArg(call_get_pow_780, 1, EEW); + setRet(call_get_pow_780, 0, ret_val_get_pow_780); + setArg(call_get_sew_pow_781, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_781, 0, ret_val_get_sew_pow_781); + setArg(call_get_lmul_pow_782, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_782, 0, ret_val_get_lmul_pow_782); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_783; + auto illegal_store_783_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_783 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_783, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_783; + setArg(call_illegal_store_783, 0, reinterpret_cast(this)); + setArg(call_illegal_store_783, 1, 2); + setArg(call_illegal_store_783, 2, EEW); + setArg(call_illegal_store_783, 3, illegal_store_783_arg2); + setRet(call_illegal_store_783, 0, ret_val_illegal_store_783); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_784; + auto vssseg_784_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_784_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_784_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_784_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_784_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_784 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_784, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_784, 32, false), traits::vstart); + setArg(call_vssseg_784, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_784, 1, V); + setArg(call_vssseg_784, 2, vssseg_784_arg1); + setArg(call_vssseg_784, 3, vssseg_784_arg2); + setArg(call_vssseg_784, 4, vssseg_784_arg3); + setArg(call_vssseg_784, 5, vm); + setArg(call_vssseg_784, 6, vs3); + setArg(call_vssseg_784, 7, vssseg_784_arg6); + setArg(call_vssseg_784, 8, 5); + setArg(call_vssseg_784, 9, 2); + setArg(call_vssseg_784, 10, vssseg_784_arg9); + setRet(call_vssseg_784, 0, ret_val_vssseg_784); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 264); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 265: VSSSEG2E32__V */ + continuation_e __vssseg2e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG2E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 265); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_785; + x86::Gp ret_val_get_pow_785 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_785, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_786; + x86::Gp ret_val_get_sew_pow_786 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_786, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_787; + x86::Gp ret_val_get_lmul_pow_787 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_787, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_785, ret_val_get_sew_pow_786), ret_val_get_lmul_pow_787)), 3, true); + setArg(call_get_pow_785, 0, reinterpret_cast(this)); + setArg(call_get_pow_785, 1, EEW); + setRet(call_get_pow_785, 0, ret_val_get_pow_785); + setArg(call_get_sew_pow_786, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_786, 0, ret_val_get_sew_pow_786); + setArg(call_get_lmul_pow_787, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_787, 0, ret_val_get_lmul_pow_787); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_788; + auto illegal_store_788_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_788 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_788, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_788; + setArg(call_illegal_store_788, 0, reinterpret_cast(this)); + setArg(call_illegal_store_788, 1, 2); + setArg(call_illegal_store_788, 2, EEW); + setArg(call_illegal_store_788, 3, illegal_store_788_arg2); + setRet(call_illegal_store_788, 0, ret_val_illegal_store_788); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_789; + auto vssseg_789_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_789_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_789_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_789_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_789_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_789 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_789, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_789, 32, false), traits::vstart); + setArg(call_vssseg_789, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_789, 1, V); + setArg(call_vssseg_789, 2, vssseg_789_arg1); + setArg(call_vssseg_789, 3, vssseg_789_arg2); + setArg(call_vssseg_789, 4, vssseg_789_arg3); + setArg(call_vssseg_789, 5, vm); + setArg(call_vssseg_789, 6, vs3); + setArg(call_vssseg_789, 7, vssseg_789_arg6); + setArg(call_vssseg_789, 8, 6); + setArg(call_vssseg_789, 9, 2); + setArg(call_vssseg_789, 10, vssseg_789_arg9); + setRet(call_vssseg_789, 0, ret_val_vssseg_789); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 265); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 266: VSSSEG2E64__V */ + continuation_e __vssseg2e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG2E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 266); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_790; + x86::Gp ret_val_get_pow_790 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_790, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_791; + x86::Gp ret_val_get_sew_pow_791 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_791, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_792; + x86::Gp ret_val_get_lmul_pow_792 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_792, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_790, ret_val_get_sew_pow_791), ret_val_get_lmul_pow_792)), 3, true); + setArg(call_get_pow_790, 0, reinterpret_cast(this)); + setArg(call_get_pow_790, 1, EEW); + setRet(call_get_pow_790, 0, ret_val_get_pow_790); + setArg(call_get_sew_pow_791, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_791, 0, ret_val_get_sew_pow_791); + setArg(call_get_lmul_pow_792, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_792, 0, ret_val_get_lmul_pow_792); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_793; + auto illegal_store_793_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_793 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_793, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_793; + setArg(call_illegal_store_793, 0, reinterpret_cast(this)); + setArg(call_illegal_store_793, 1, 2); + setArg(call_illegal_store_793, 2, EEW); + setArg(call_illegal_store_793, 3, illegal_store_793_arg2); + setRet(call_illegal_store_793, 0, ret_val_illegal_store_793); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_794; + auto vssseg_794_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_794_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_794_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_794_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_794_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_794 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_794, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_794, 32, false), traits::vstart); + setArg(call_vssseg_794, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_794, 1, V); + setArg(call_vssseg_794, 2, vssseg_794_arg1); + setArg(call_vssseg_794, 3, vssseg_794_arg2); + setArg(call_vssseg_794, 4, vssseg_794_arg3); + setArg(call_vssseg_794, 5, vm); + setArg(call_vssseg_794, 6, vs3); + setArg(call_vssseg_794, 7, vssseg_794_arg6); + setArg(call_vssseg_794, 8, 7); + setArg(call_vssseg_794, 9, 2); + setArg(call_vssseg_794, 10, vssseg_794_arg9); + setRet(call_vssseg_794, 0, ret_val_vssseg_794); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 266); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 267: VSSSEG3E8__V */ + continuation_e __vssseg3e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG3E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 267); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_795; + x86::Gp ret_val_get_pow_795 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_795, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_796; + x86::Gp ret_val_get_sew_pow_796 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_796, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_797; + x86::Gp ret_val_get_lmul_pow_797 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_797, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_795, ret_val_get_sew_pow_796), ret_val_get_lmul_pow_797)), 3, true); + setArg(call_get_pow_795, 0, reinterpret_cast(this)); + setArg(call_get_pow_795, 1, EEW); + setRet(call_get_pow_795, 0, ret_val_get_pow_795); + setArg(call_get_sew_pow_796, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_796, 0, ret_val_get_sew_pow_796); + setArg(call_get_lmul_pow_797, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_797, 0, ret_val_get_lmul_pow_797); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_798; + auto illegal_store_798_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_798 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_798, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_798; + setArg(call_illegal_store_798, 0, reinterpret_cast(this)); + setArg(call_illegal_store_798, 1, 3); + setArg(call_illegal_store_798, 2, EEW); + setArg(call_illegal_store_798, 3, illegal_store_798_arg2); + setRet(call_illegal_store_798, 0, ret_val_illegal_store_798); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_799; + auto vssseg_799_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_799_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_799_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_799_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_799_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_799 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_799, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_799, 32, false), traits::vstart); + setArg(call_vssseg_799, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_799, 1, V); + setArg(call_vssseg_799, 2, vssseg_799_arg1); + setArg(call_vssseg_799, 3, vssseg_799_arg2); + setArg(call_vssseg_799, 4, vssseg_799_arg3); + setArg(call_vssseg_799, 5, vm); + setArg(call_vssseg_799, 6, vs3); + setArg(call_vssseg_799, 7, vssseg_799_arg6); + setArg(call_vssseg_799, 8, 0); + setArg(call_vssseg_799, 9, 3); + setArg(call_vssseg_799, 10, vssseg_799_arg9); + setRet(call_vssseg_799, 0, ret_val_vssseg_799); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 267); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 268: VSSSEG3E16__V */ + continuation_e __vssseg3e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG3E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 268); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_800; + x86::Gp ret_val_get_pow_800 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_800, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_801; + x86::Gp ret_val_get_sew_pow_801 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_801, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_802; + x86::Gp ret_val_get_lmul_pow_802 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_802, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_800, ret_val_get_sew_pow_801), ret_val_get_lmul_pow_802)), 3, true); + setArg(call_get_pow_800, 0, reinterpret_cast(this)); + setArg(call_get_pow_800, 1, EEW); + setRet(call_get_pow_800, 0, ret_val_get_pow_800); + setArg(call_get_sew_pow_801, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_801, 0, ret_val_get_sew_pow_801); + setArg(call_get_lmul_pow_802, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_802, 0, ret_val_get_lmul_pow_802); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_803; + auto illegal_store_803_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_803 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_803, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_803; + setArg(call_illegal_store_803, 0, reinterpret_cast(this)); + setArg(call_illegal_store_803, 1, 3); + setArg(call_illegal_store_803, 2, EEW); + setArg(call_illegal_store_803, 3, illegal_store_803_arg2); + setRet(call_illegal_store_803, 0, ret_val_illegal_store_803); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_804; + auto vssseg_804_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_804_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_804_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_804_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_804_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_804 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_804, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_804, 32, false), traits::vstart); + setArg(call_vssseg_804, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_804, 1, V); + setArg(call_vssseg_804, 2, vssseg_804_arg1); + setArg(call_vssseg_804, 3, vssseg_804_arg2); + setArg(call_vssseg_804, 4, vssseg_804_arg3); + setArg(call_vssseg_804, 5, vm); + setArg(call_vssseg_804, 6, vs3); + setArg(call_vssseg_804, 7, vssseg_804_arg6); + setArg(call_vssseg_804, 8, 5); + setArg(call_vssseg_804, 9, 3); + setArg(call_vssseg_804, 10, vssseg_804_arg9); + setRet(call_vssseg_804, 0, ret_val_vssseg_804); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 268); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 269: VSSSEG3E32__V */ + continuation_e __vssseg3e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG3E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 269); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_805; + x86::Gp ret_val_get_pow_805 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_805, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_806; + x86::Gp ret_val_get_sew_pow_806 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_806, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_807; + x86::Gp ret_val_get_lmul_pow_807 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_807, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_805, ret_val_get_sew_pow_806), ret_val_get_lmul_pow_807)), 3, true); + setArg(call_get_pow_805, 0, reinterpret_cast(this)); + setArg(call_get_pow_805, 1, EEW); + setRet(call_get_pow_805, 0, ret_val_get_pow_805); + setArg(call_get_sew_pow_806, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_806, 0, ret_val_get_sew_pow_806); + setArg(call_get_lmul_pow_807, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_807, 0, ret_val_get_lmul_pow_807); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_808; + auto illegal_store_808_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_808 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_808, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_808; + setArg(call_illegal_store_808, 0, reinterpret_cast(this)); + setArg(call_illegal_store_808, 1, 3); + setArg(call_illegal_store_808, 2, EEW); + setArg(call_illegal_store_808, 3, illegal_store_808_arg2); + setRet(call_illegal_store_808, 0, ret_val_illegal_store_808); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_809; + auto vssseg_809_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_809_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_809_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_809_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_809_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_809 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_809, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_809, 32, false), traits::vstart); + setArg(call_vssseg_809, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_809, 1, V); + setArg(call_vssseg_809, 2, vssseg_809_arg1); + setArg(call_vssseg_809, 3, vssseg_809_arg2); + setArg(call_vssseg_809, 4, vssseg_809_arg3); + setArg(call_vssseg_809, 5, vm); + setArg(call_vssseg_809, 6, vs3); + setArg(call_vssseg_809, 7, vssseg_809_arg6); + setArg(call_vssseg_809, 8, 6); + setArg(call_vssseg_809, 9, 3); + setArg(call_vssseg_809, 10, vssseg_809_arg9); + setRet(call_vssseg_809, 0, ret_val_vssseg_809); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 269); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 270: VSSSEG3E64__V */ + continuation_e __vssseg3e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG3E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 270); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_810; + x86::Gp ret_val_get_pow_810 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_810, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_811; + x86::Gp ret_val_get_sew_pow_811 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_811, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_812; + x86::Gp ret_val_get_lmul_pow_812 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_812, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_810, ret_val_get_sew_pow_811), ret_val_get_lmul_pow_812)), 3, true); + setArg(call_get_pow_810, 0, reinterpret_cast(this)); + setArg(call_get_pow_810, 1, EEW); + setRet(call_get_pow_810, 0, ret_val_get_pow_810); + setArg(call_get_sew_pow_811, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_811, 0, ret_val_get_sew_pow_811); + setArg(call_get_lmul_pow_812, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_812, 0, ret_val_get_lmul_pow_812); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_813; + auto illegal_store_813_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_813 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_813, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_813; + setArg(call_illegal_store_813, 0, reinterpret_cast(this)); + setArg(call_illegal_store_813, 1, 3); + setArg(call_illegal_store_813, 2, EEW); + setArg(call_illegal_store_813, 3, illegal_store_813_arg2); + setRet(call_illegal_store_813, 0, ret_val_illegal_store_813); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_814; + auto vssseg_814_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_814_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_814_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_814_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_814_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_814 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_814, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_814, 32, false), traits::vstart); + setArg(call_vssseg_814, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_814, 1, V); + setArg(call_vssseg_814, 2, vssseg_814_arg1); + setArg(call_vssseg_814, 3, vssseg_814_arg2); + setArg(call_vssseg_814, 4, vssseg_814_arg3); + setArg(call_vssseg_814, 5, vm); + setArg(call_vssseg_814, 6, vs3); + setArg(call_vssseg_814, 7, vssseg_814_arg6); + setArg(call_vssseg_814, 8, 7); + setArg(call_vssseg_814, 9, 3); + setArg(call_vssseg_814, 10, vssseg_814_arg9); + setRet(call_vssseg_814, 0, ret_val_vssseg_814); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 270); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 271: VSSSEG4E8__V */ + continuation_e __vssseg4e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG4E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 271); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_815; + x86::Gp ret_val_get_pow_815 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_815, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_816; + x86::Gp ret_val_get_sew_pow_816 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_816, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_817; + x86::Gp ret_val_get_lmul_pow_817 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_817, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_815, ret_val_get_sew_pow_816), ret_val_get_lmul_pow_817)), 3, true); + setArg(call_get_pow_815, 0, reinterpret_cast(this)); + setArg(call_get_pow_815, 1, EEW); + setRet(call_get_pow_815, 0, ret_val_get_pow_815); + setArg(call_get_sew_pow_816, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_816, 0, ret_val_get_sew_pow_816); + setArg(call_get_lmul_pow_817, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_817, 0, ret_val_get_lmul_pow_817); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_818; + auto illegal_store_818_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_818 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_818, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_818; + setArg(call_illegal_store_818, 0, reinterpret_cast(this)); + setArg(call_illegal_store_818, 1, 4); + setArg(call_illegal_store_818, 2, EEW); + setArg(call_illegal_store_818, 3, illegal_store_818_arg2); + setRet(call_illegal_store_818, 0, ret_val_illegal_store_818); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_819; + auto vssseg_819_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_819_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_819_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_819_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_819_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_819 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_819, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_819, 32, false), traits::vstart); + setArg(call_vssseg_819, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_819, 1, V); + setArg(call_vssseg_819, 2, vssseg_819_arg1); + setArg(call_vssseg_819, 3, vssseg_819_arg2); + setArg(call_vssseg_819, 4, vssseg_819_arg3); + setArg(call_vssseg_819, 5, vm); + setArg(call_vssseg_819, 6, vs3); + setArg(call_vssseg_819, 7, vssseg_819_arg6); + setArg(call_vssseg_819, 8, 0); + setArg(call_vssseg_819, 9, 4); + setArg(call_vssseg_819, 10, vssseg_819_arg9); + setRet(call_vssseg_819, 0, ret_val_vssseg_819); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 271); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 272: VSSSEG4E16__V */ + continuation_e __vssseg4e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG4E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 272); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_820; + x86::Gp ret_val_get_pow_820 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_820, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_821; + x86::Gp ret_val_get_sew_pow_821 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_821, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_822; + x86::Gp ret_val_get_lmul_pow_822 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_822, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_820, ret_val_get_sew_pow_821), ret_val_get_lmul_pow_822)), 3, true); + setArg(call_get_pow_820, 0, reinterpret_cast(this)); + setArg(call_get_pow_820, 1, EEW); + setRet(call_get_pow_820, 0, ret_val_get_pow_820); + setArg(call_get_sew_pow_821, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_821, 0, ret_val_get_sew_pow_821); + setArg(call_get_lmul_pow_822, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_822, 0, ret_val_get_lmul_pow_822); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_823; + auto illegal_store_823_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_823 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_823, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_823; + setArg(call_illegal_store_823, 0, reinterpret_cast(this)); + setArg(call_illegal_store_823, 1, 4); + setArg(call_illegal_store_823, 2, EEW); + setArg(call_illegal_store_823, 3, illegal_store_823_arg2); + setRet(call_illegal_store_823, 0, ret_val_illegal_store_823); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_824; + auto vssseg_824_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_824_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_824_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_824_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_824_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_824 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_824, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_824, 32, false), traits::vstart); + setArg(call_vssseg_824, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_824, 1, V); + setArg(call_vssseg_824, 2, vssseg_824_arg1); + setArg(call_vssseg_824, 3, vssseg_824_arg2); + setArg(call_vssseg_824, 4, vssseg_824_arg3); + setArg(call_vssseg_824, 5, vm); + setArg(call_vssseg_824, 6, vs3); + setArg(call_vssseg_824, 7, vssseg_824_arg6); + setArg(call_vssseg_824, 8, 5); + setArg(call_vssseg_824, 9, 4); + setArg(call_vssseg_824, 10, vssseg_824_arg9); + setRet(call_vssseg_824, 0, ret_val_vssseg_824); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 272); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 273: VSSSEG4E32__V */ + continuation_e __vssseg4e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG4E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 273); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_825; + x86::Gp ret_val_get_pow_825 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_825, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_826; + x86::Gp ret_val_get_sew_pow_826 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_826, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_827; + x86::Gp ret_val_get_lmul_pow_827 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_827, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_825, ret_val_get_sew_pow_826), ret_val_get_lmul_pow_827)), 3, true); + setArg(call_get_pow_825, 0, reinterpret_cast(this)); + setArg(call_get_pow_825, 1, EEW); + setRet(call_get_pow_825, 0, ret_val_get_pow_825); + setArg(call_get_sew_pow_826, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_826, 0, ret_val_get_sew_pow_826); + setArg(call_get_lmul_pow_827, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_827, 0, ret_val_get_lmul_pow_827); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_828; + auto illegal_store_828_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_828 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_828, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_828; + setArg(call_illegal_store_828, 0, reinterpret_cast(this)); + setArg(call_illegal_store_828, 1, 4); + setArg(call_illegal_store_828, 2, EEW); + setArg(call_illegal_store_828, 3, illegal_store_828_arg2); + setRet(call_illegal_store_828, 0, ret_val_illegal_store_828); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_829; + auto vssseg_829_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_829_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_829_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_829_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_829_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_829 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_829, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_829, 32, false), traits::vstart); + setArg(call_vssseg_829, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_829, 1, V); + setArg(call_vssseg_829, 2, vssseg_829_arg1); + setArg(call_vssseg_829, 3, vssseg_829_arg2); + setArg(call_vssseg_829, 4, vssseg_829_arg3); + setArg(call_vssseg_829, 5, vm); + setArg(call_vssseg_829, 6, vs3); + setArg(call_vssseg_829, 7, vssseg_829_arg6); + setArg(call_vssseg_829, 8, 6); + setArg(call_vssseg_829, 9, 4); + setArg(call_vssseg_829, 10, vssseg_829_arg9); + setRet(call_vssseg_829, 0, ret_val_vssseg_829); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 273); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 274: VSSSEG4E64__V */ + continuation_e __vssseg4e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG4E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 274); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_830; + x86::Gp ret_val_get_pow_830 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_830, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_831; + x86::Gp ret_val_get_sew_pow_831 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_831, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_832; + x86::Gp ret_val_get_lmul_pow_832 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_832, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_830, ret_val_get_sew_pow_831), ret_val_get_lmul_pow_832)), 3, true); + setArg(call_get_pow_830, 0, reinterpret_cast(this)); + setArg(call_get_pow_830, 1, EEW); + setRet(call_get_pow_830, 0, ret_val_get_pow_830); + setArg(call_get_sew_pow_831, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_831, 0, ret_val_get_sew_pow_831); + setArg(call_get_lmul_pow_832, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_832, 0, ret_val_get_lmul_pow_832); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_833; + auto illegal_store_833_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_833 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_833, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_833; + setArg(call_illegal_store_833, 0, reinterpret_cast(this)); + setArg(call_illegal_store_833, 1, 4); + setArg(call_illegal_store_833, 2, EEW); + setArg(call_illegal_store_833, 3, illegal_store_833_arg2); + setRet(call_illegal_store_833, 0, ret_val_illegal_store_833); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_834; + auto vssseg_834_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_834_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_834_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_834_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_834_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_834 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_834, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_834, 32, false), traits::vstart); + setArg(call_vssseg_834, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_834, 1, V); + setArg(call_vssseg_834, 2, vssseg_834_arg1); + setArg(call_vssseg_834, 3, vssseg_834_arg2); + setArg(call_vssseg_834, 4, vssseg_834_arg3); + setArg(call_vssseg_834, 5, vm); + setArg(call_vssseg_834, 6, vs3); + setArg(call_vssseg_834, 7, vssseg_834_arg6); + setArg(call_vssseg_834, 8, 7); + setArg(call_vssseg_834, 9, 4); + setArg(call_vssseg_834, 10, vssseg_834_arg9); + setRet(call_vssseg_834, 0, ret_val_vssseg_834); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 274); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 275: VSSSEG5E8__V */ + continuation_e __vssseg5e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG5E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 275); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_835; + x86::Gp ret_val_get_pow_835 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_835, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_836; + x86::Gp ret_val_get_sew_pow_836 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_836, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_837; + x86::Gp ret_val_get_lmul_pow_837 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_837, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_835, ret_val_get_sew_pow_836), ret_val_get_lmul_pow_837)), 3, true); + setArg(call_get_pow_835, 0, reinterpret_cast(this)); + setArg(call_get_pow_835, 1, EEW); + setRet(call_get_pow_835, 0, ret_val_get_pow_835); + setArg(call_get_sew_pow_836, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_836, 0, ret_val_get_sew_pow_836); + setArg(call_get_lmul_pow_837, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_837, 0, ret_val_get_lmul_pow_837); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_838; + auto illegal_store_838_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_838 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_838, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_838; + setArg(call_illegal_store_838, 0, reinterpret_cast(this)); + setArg(call_illegal_store_838, 1, 5); + setArg(call_illegal_store_838, 2, EEW); + setArg(call_illegal_store_838, 3, illegal_store_838_arg2); + setRet(call_illegal_store_838, 0, ret_val_illegal_store_838); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_839; + auto vssseg_839_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_839_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_839_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_839_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_839_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_839 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_839, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_839, 32, false), traits::vstart); + setArg(call_vssseg_839, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_839, 1, V); + setArg(call_vssseg_839, 2, vssseg_839_arg1); + setArg(call_vssseg_839, 3, vssseg_839_arg2); + setArg(call_vssseg_839, 4, vssseg_839_arg3); + setArg(call_vssseg_839, 5, vm); + setArg(call_vssseg_839, 6, vs3); + setArg(call_vssseg_839, 7, vssseg_839_arg6); + setArg(call_vssseg_839, 8, 0); + setArg(call_vssseg_839, 9, 5); + setArg(call_vssseg_839, 10, vssseg_839_arg9); + setRet(call_vssseg_839, 0, ret_val_vssseg_839); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 275); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 276: VSSSEG5E16__V */ + continuation_e __vssseg5e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG5E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 276); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_840; + x86::Gp ret_val_get_pow_840 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_840, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_841; + x86::Gp ret_val_get_sew_pow_841 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_841, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_842; + x86::Gp ret_val_get_lmul_pow_842 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_842, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_840, ret_val_get_sew_pow_841), ret_val_get_lmul_pow_842)), 3, true); + setArg(call_get_pow_840, 0, reinterpret_cast(this)); + setArg(call_get_pow_840, 1, EEW); + setRet(call_get_pow_840, 0, ret_val_get_pow_840); + setArg(call_get_sew_pow_841, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_841, 0, ret_val_get_sew_pow_841); + setArg(call_get_lmul_pow_842, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_842, 0, ret_val_get_lmul_pow_842); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_843; + auto illegal_store_843_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_843 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_843, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_843; + setArg(call_illegal_store_843, 0, reinterpret_cast(this)); + setArg(call_illegal_store_843, 1, 5); + setArg(call_illegal_store_843, 2, EEW); + setArg(call_illegal_store_843, 3, illegal_store_843_arg2); + setRet(call_illegal_store_843, 0, ret_val_illegal_store_843); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_844; + auto vssseg_844_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_844_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_844_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_844_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_844_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_844 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_844, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_844, 32, false), traits::vstart); + setArg(call_vssseg_844, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_844, 1, V); + setArg(call_vssseg_844, 2, vssseg_844_arg1); + setArg(call_vssseg_844, 3, vssseg_844_arg2); + setArg(call_vssseg_844, 4, vssseg_844_arg3); + setArg(call_vssseg_844, 5, vm); + setArg(call_vssseg_844, 6, vs3); + setArg(call_vssseg_844, 7, vssseg_844_arg6); + setArg(call_vssseg_844, 8, 5); + setArg(call_vssseg_844, 9, 5); + setArg(call_vssseg_844, 10, vssseg_844_arg9); + setRet(call_vssseg_844, 0, ret_val_vssseg_844); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 276); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 277: VSSSEG5E32__V */ + continuation_e __vssseg5e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG5E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 277); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_845; + x86::Gp ret_val_get_pow_845 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_845, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_846; + x86::Gp ret_val_get_sew_pow_846 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_846, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_847; + x86::Gp ret_val_get_lmul_pow_847 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_847, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_845, ret_val_get_sew_pow_846), ret_val_get_lmul_pow_847)), 3, true); + setArg(call_get_pow_845, 0, reinterpret_cast(this)); + setArg(call_get_pow_845, 1, EEW); + setRet(call_get_pow_845, 0, ret_val_get_pow_845); + setArg(call_get_sew_pow_846, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_846, 0, ret_val_get_sew_pow_846); + setArg(call_get_lmul_pow_847, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_847, 0, ret_val_get_lmul_pow_847); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_848; + auto illegal_store_848_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_848 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_848, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_848; + setArg(call_illegal_store_848, 0, reinterpret_cast(this)); + setArg(call_illegal_store_848, 1, 5); + setArg(call_illegal_store_848, 2, EEW); + setArg(call_illegal_store_848, 3, illegal_store_848_arg2); + setRet(call_illegal_store_848, 0, ret_val_illegal_store_848); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_849; + auto vssseg_849_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_849_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_849_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_849_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_849_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_849 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_849, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_849, 32, false), traits::vstart); + setArg(call_vssseg_849, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_849, 1, V); + setArg(call_vssseg_849, 2, vssseg_849_arg1); + setArg(call_vssseg_849, 3, vssseg_849_arg2); + setArg(call_vssseg_849, 4, vssseg_849_arg3); + setArg(call_vssseg_849, 5, vm); + setArg(call_vssseg_849, 6, vs3); + setArg(call_vssseg_849, 7, vssseg_849_arg6); + setArg(call_vssseg_849, 8, 6); + setArg(call_vssseg_849, 9, 5); + setArg(call_vssseg_849, 10, vssseg_849_arg9); + setRet(call_vssseg_849, 0, ret_val_vssseg_849); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 277); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 278: VSSSEG5E64__V */ + continuation_e __vssseg5e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG5E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 278); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_850; + x86::Gp ret_val_get_pow_850 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_850, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_851; + x86::Gp ret_val_get_sew_pow_851 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_851, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_852; + x86::Gp ret_val_get_lmul_pow_852 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_852, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_850, ret_val_get_sew_pow_851), ret_val_get_lmul_pow_852)), 3, true); + setArg(call_get_pow_850, 0, reinterpret_cast(this)); + setArg(call_get_pow_850, 1, EEW); + setRet(call_get_pow_850, 0, ret_val_get_pow_850); + setArg(call_get_sew_pow_851, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_851, 0, ret_val_get_sew_pow_851); + setArg(call_get_lmul_pow_852, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_852, 0, ret_val_get_lmul_pow_852); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_853; + auto illegal_store_853_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_853 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_853, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_853; + setArg(call_illegal_store_853, 0, reinterpret_cast(this)); + setArg(call_illegal_store_853, 1, 5); + setArg(call_illegal_store_853, 2, EEW); + setArg(call_illegal_store_853, 3, illegal_store_853_arg2); + setRet(call_illegal_store_853, 0, ret_val_illegal_store_853); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_854; + auto vssseg_854_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_854_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_854_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_854_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_854_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_854 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_854, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_854, 32, false), traits::vstart); + setArg(call_vssseg_854, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_854, 1, V); + setArg(call_vssseg_854, 2, vssseg_854_arg1); + setArg(call_vssseg_854, 3, vssseg_854_arg2); + setArg(call_vssseg_854, 4, vssseg_854_arg3); + setArg(call_vssseg_854, 5, vm); + setArg(call_vssseg_854, 6, vs3); + setArg(call_vssseg_854, 7, vssseg_854_arg6); + setArg(call_vssseg_854, 8, 7); + setArg(call_vssseg_854, 9, 5); + setArg(call_vssseg_854, 10, vssseg_854_arg9); + setRet(call_vssseg_854, 0, ret_val_vssseg_854); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 278); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 279: VSSSEG6E8__V */ + continuation_e __vssseg6e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG6E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 279); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_855; + x86::Gp ret_val_get_pow_855 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_855, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_856; + x86::Gp ret_val_get_sew_pow_856 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_856, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_857; + x86::Gp ret_val_get_lmul_pow_857 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_857, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_855, ret_val_get_sew_pow_856), ret_val_get_lmul_pow_857)), 3, true); + setArg(call_get_pow_855, 0, reinterpret_cast(this)); + setArg(call_get_pow_855, 1, EEW); + setRet(call_get_pow_855, 0, ret_val_get_pow_855); + setArg(call_get_sew_pow_856, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_856, 0, ret_val_get_sew_pow_856); + setArg(call_get_lmul_pow_857, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_857, 0, ret_val_get_lmul_pow_857); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_858; + auto illegal_store_858_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_858 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_858, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_858; + setArg(call_illegal_store_858, 0, reinterpret_cast(this)); + setArg(call_illegal_store_858, 1, 6); + setArg(call_illegal_store_858, 2, EEW); + setArg(call_illegal_store_858, 3, illegal_store_858_arg2); + setRet(call_illegal_store_858, 0, ret_val_illegal_store_858); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_859; + auto vssseg_859_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_859_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_859_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_859_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_859_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_859 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_859, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_859, 32, false), traits::vstart); + setArg(call_vssseg_859, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_859, 1, V); + setArg(call_vssseg_859, 2, vssseg_859_arg1); + setArg(call_vssseg_859, 3, vssseg_859_arg2); + setArg(call_vssseg_859, 4, vssseg_859_arg3); + setArg(call_vssseg_859, 5, vm); + setArg(call_vssseg_859, 6, vs3); + setArg(call_vssseg_859, 7, vssseg_859_arg6); + setArg(call_vssseg_859, 8, 0); + setArg(call_vssseg_859, 9, 6); + setArg(call_vssseg_859, 10, vssseg_859_arg9); + setRet(call_vssseg_859, 0, ret_val_vssseg_859); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 279); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 280: VSSSEG6E16__V */ + continuation_e __vssseg6e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG6E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 280); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_860; + x86::Gp ret_val_get_pow_860 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_860, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_861; + x86::Gp ret_val_get_sew_pow_861 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_861, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_862; + x86::Gp ret_val_get_lmul_pow_862 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_862, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_860, ret_val_get_sew_pow_861), ret_val_get_lmul_pow_862)), 3, true); + setArg(call_get_pow_860, 0, reinterpret_cast(this)); + setArg(call_get_pow_860, 1, EEW); + setRet(call_get_pow_860, 0, ret_val_get_pow_860); + setArg(call_get_sew_pow_861, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_861, 0, ret_val_get_sew_pow_861); + setArg(call_get_lmul_pow_862, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_862, 0, ret_val_get_lmul_pow_862); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_863; + auto illegal_store_863_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_863 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_863, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_863; + setArg(call_illegal_store_863, 0, reinterpret_cast(this)); + setArg(call_illegal_store_863, 1, 6); + setArg(call_illegal_store_863, 2, EEW); + setArg(call_illegal_store_863, 3, illegal_store_863_arg2); + setRet(call_illegal_store_863, 0, ret_val_illegal_store_863); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_864; + auto vssseg_864_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_864_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_864_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_864_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_864_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_864 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_864, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_864, 32, false), traits::vstart); + setArg(call_vssseg_864, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_864, 1, V); + setArg(call_vssseg_864, 2, vssseg_864_arg1); + setArg(call_vssseg_864, 3, vssseg_864_arg2); + setArg(call_vssseg_864, 4, vssseg_864_arg3); + setArg(call_vssseg_864, 5, vm); + setArg(call_vssseg_864, 6, vs3); + setArg(call_vssseg_864, 7, vssseg_864_arg6); + setArg(call_vssseg_864, 8, 5); + setArg(call_vssseg_864, 9, 6); + setArg(call_vssseg_864, 10, vssseg_864_arg9); + setRet(call_vssseg_864, 0, ret_val_vssseg_864); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 280); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 281: VSSSEG6E32__V */ + continuation_e __vssseg6e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG6E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 281); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_865; + x86::Gp ret_val_get_pow_865 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_865, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_866; + x86::Gp ret_val_get_sew_pow_866 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_866, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_867; + x86::Gp ret_val_get_lmul_pow_867 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_867, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_865, ret_val_get_sew_pow_866), ret_val_get_lmul_pow_867)), 3, true); + setArg(call_get_pow_865, 0, reinterpret_cast(this)); + setArg(call_get_pow_865, 1, EEW); + setRet(call_get_pow_865, 0, ret_val_get_pow_865); + setArg(call_get_sew_pow_866, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_866, 0, ret_val_get_sew_pow_866); + setArg(call_get_lmul_pow_867, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_867, 0, ret_val_get_lmul_pow_867); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_868; + auto illegal_store_868_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_868 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_868, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_868; + setArg(call_illegal_store_868, 0, reinterpret_cast(this)); + setArg(call_illegal_store_868, 1, 6); + setArg(call_illegal_store_868, 2, EEW); + setArg(call_illegal_store_868, 3, illegal_store_868_arg2); + setRet(call_illegal_store_868, 0, ret_val_illegal_store_868); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_869; + auto vssseg_869_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_869_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_869_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_869_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_869_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_869 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_869, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_869, 32, false), traits::vstart); + setArg(call_vssseg_869, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_869, 1, V); + setArg(call_vssseg_869, 2, vssseg_869_arg1); + setArg(call_vssseg_869, 3, vssseg_869_arg2); + setArg(call_vssseg_869, 4, vssseg_869_arg3); + setArg(call_vssseg_869, 5, vm); + setArg(call_vssseg_869, 6, vs3); + setArg(call_vssseg_869, 7, vssseg_869_arg6); + setArg(call_vssseg_869, 8, 6); + setArg(call_vssseg_869, 9, 6); + setArg(call_vssseg_869, 10, vssseg_869_arg9); + setRet(call_vssseg_869, 0, ret_val_vssseg_869); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 281); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 282: VSSSEG6E64__V */ + continuation_e __vssseg6e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG6E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 282); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_870; + x86::Gp ret_val_get_pow_870 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_870, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_871; + x86::Gp ret_val_get_sew_pow_871 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_871, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_872; + x86::Gp ret_val_get_lmul_pow_872 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_872, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_870, ret_val_get_sew_pow_871), ret_val_get_lmul_pow_872)), 3, true); + setArg(call_get_pow_870, 0, reinterpret_cast(this)); + setArg(call_get_pow_870, 1, EEW); + setRet(call_get_pow_870, 0, ret_val_get_pow_870); + setArg(call_get_sew_pow_871, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_871, 0, ret_val_get_sew_pow_871); + setArg(call_get_lmul_pow_872, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_872, 0, ret_val_get_lmul_pow_872); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_873; + auto illegal_store_873_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_873 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_873, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_873; + setArg(call_illegal_store_873, 0, reinterpret_cast(this)); + setArg(call_illegal_store_873, 1, 6); + setArg(call_illegal_store_873, 2, EEW); + setArg(call_illegal_store_873, 3, illegal_store_873_arg2); + setRet(call_illegal_store_873, 0, ret_val_illegal_store_873); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_874; + auto vssseg_874_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_874_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_874_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_874_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_874_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_874 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_874, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_874, 32, false), traits::vstart); + setArg(call_vssseg_874, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_874, 1, V); + setArg(call_vssseg_874, 2, vssseg_874_arg1); + setArg(call_vssseg_874, 3, vssseg_874_arg2); + setArg(call_vssseg_874, 4, vssseg_874_arg3); + setArg(call_vssseg_874, 5, vm); + setArg(call_vssseg_874, 6, vs3); + setArg(call_vssseg_874, 7, vssseg_874_arg6); + setArg(call_vssseg_874, 8, 7); + setArg(call_vssseg_874, 9, 6); + setArg(call_vssseg_874, 10, vssseg_874_arg9); + setRet(call_vssseg_874, 0, ret_val_vssseg_874); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 282); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 283: VSSSEG7E8__V */ + continuation_e __vssseg7e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG7E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 283); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_875; + x86::Gp ret_val_get_pow_875 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_875, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_876; + x86::Gp ret_val_get_sew_pow_876 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_876, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_877; + x86::Gp ret_val_get_lmul_pow_877 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_877, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_875, ret_val_get_sew_pow_876), ret_val_get_lmul_pow_877)), 3, true); + setArg(call_get_pow_875, 0, reinterpret_cast(this)); + setArg(call_get_pow_875, 1, EEW); + setRet(call_get_pow_875, 0, ret_val_get_pow_875); + setArg(call_get_sew_pow_876, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_876, 0, ret_val_get_sew_pow_876); + setArg(call_get_lmul_pow_877, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_877, 0, ret_val_get_lmul_pow_877); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_878; + auto illegal_store_878_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_878 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_878, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_878; + setArg(call_illegal_store_878, 0, reinterpret_cast(this)); + setArg(call_illegal_store_878, 1, 7); + setArg(call_illegal_store_878, 2, EEW); + setArg(call_illegal_store_878, 3, illegal_store_878_arg2); + setRet(call_illegal_store_878, 0, ret_val_illegal_store_878); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_879; + auto vssseg_879_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_879_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_879_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_879_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_879_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_879 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_879, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_879, 32, false), traits::vstart); + setArg(call_vssseg_879, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_879, 1, V); + setArg(call_vssseg_879, 2, vssseg_879_arg1); + setArg(call_vssseg_879, 3, vssseg_879_arg2); + setArg(call_vssseg_879, 4, vssseg_879_arg3); + setArg(call_vssseg_879, 5, vm); + setArg(call_vssseg_879, 6, vs3); + setArg(call_vssseg_879, 7, vssseg_879_arg6); + setArg(call_vssseg_879, 8, 0); + setArg(call_vssseg_879, 9, 7); + setArg(call_vssseg_879, 10, vssseg_879_arg9); + setRet(call_vssseg_879, 0, ret_val_vssseg_879); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 283); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 284: VSSSEG7E16__V */ + continuation_e __vssseg7e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG7E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 284); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_880; + x86::Gp ret_val_get_pow_880 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_880, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_881; + x86::Gp ret_val_get_sew_pow_881 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_881, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_882; + x86::Gp ret_val_get_lmul_pow_882 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_882, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_880, ret_val_get_sew_pow_881), ret_val_get_lmul_pow_882)), 3, true); + setArg(call_get_pow_880, 0, reinterpret_cast(this)); + setArg(call_get_pow_880, 1, EEW); + setRet(call_get_pow_880, 0, ret_val_get_pow_880); + setArg(call_get_sew_pow_881, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_881, 0, ret_val_get_sew_pow_881); + setArg(call_get_lmul_pow_882, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_882, 0, ret_val_get_lmul_pow_882); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_883; + auto illegal_store_883_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_883 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_883, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_883; + setArg(call_illegal_store_883, 0, reinterpret_cast(this)); + setArg(call_illegal_store_883, 1, 7); + setArg(call_illegal_store_883, 2, EEW); + setArg(call_illegal_store_883, 3, illegal_store_883_arg2); + setRet(call_illegal_store_883, 0, ret_val_illegal_store_883); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_884; + auto vssseg_884_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_884_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_884_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_884_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_884_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_884 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_884, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_884, 32, false), traits::vstart); + setArg(call_vssseg_884, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_884, 1, V); + setArg(call_vssseg_884, 2, vssseg_884_arg1); + setArg(call_vssseg_884, 3, vssseg_884_arg2); + setArg(call_vssseg_884, 4, vssseg_884_arg3); + setArg(call_vssseg_884, 5, vm); + setArg(call_vssseg_884, 6, vs3); + setArg(call_vssseg_884, 7, vssseg_884_arg6); + setArg(call_vssseg_884, 8, 5); + setArg(call_vssseg_884, 9, 7); + setArg(call_vssseg_884, 10, vssseg_884_arg9); + setRet(call_vssseg_884, 0, ret_val_vssseg_884); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 284); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 285: VSSSEG7E32__V */ + continuation_e __vssseg7e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG7E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 285); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_885; + x86::Gp ret_val_get_pow_885 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_885, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_886; + x86::Gp ret_val_get_sew_pow_886 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_886, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_887; + x86::Gp ret_val_get_lmul_pow_887 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_887, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_885, ret_val_get_sew_pow_886), ret_val_get_lmul_pow_887)), 3, true); + setArg(call_get_pow_885, 0, reinterpret_cast(this)); + setArg(call_get_pow_885, 1, EEW); + setRet(call_get_pow_885, 0, ret_val_get_pow_885); + setArg(call_get_sew_pow_886, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_886, 0, ret_val_get_sew_pow_886); + setArg(call_get_lmul_pow_887, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_887, 0, ret_val_get_lmul_pow_887); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_888; + auto illegal_store_888_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_888 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_888, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_888; + setArg(call_illegal_store_888, 0, reinterpret_cast(this)); + setArg(call_illegal_store_888, 1, 7); + setArg(call_illegal_store_888, 2, EEW); + setArg(call_illegal_store_888, 3, illegal_store_888_arg2); + setRet(call_illegal_store_888, 0, ret_val_illegal_store_888); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_889; + auto vssseg_889_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_889_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_889_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_889_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_889_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_889 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_889, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_889, 32, false), traits::vstart); + setArg(call_vssseg_889, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_889, 1, V); + setArg(call_vssseg_889, 2, vssseg_889_arg1); + setArg(call_vssseg_889, 3, vssseg_889_arg2); + setArg(call_vssseg_889, 4, vssseg_889_arg3); + setArg(call_vssseg_889, 5, vm); + setArg(call_vssseg_889, 6, vs3); + setArg(call_vssseg_889, 7, vssseg_889_arg6); + setArg(call_vssseg_889, 8, 6); + setArg(call_vssseg_889, 9, 7); + setArg(call_vssseg_889, 10, vssseg_889_arg9); + setRet(call_vssseg_889, 0, ret_val_vssseg_889); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 285); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 286: VSSSEG7E64__V */ + continuation_e __vssseg7e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG7E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 286); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_890; + x86::Gp ret_val_get_pow_890 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_890, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_891; + x86::Gp ret_val_get_sew_pow_891 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_891, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_892; + x86::Gp ret_val_get_lmul_pow_892 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_892, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_890, ret_val_get_sew_pow_891), ret_val_get_lmul_pow_892)), 3, true); + setArg(call_get_pow_890, 0, reinterpret_cast(this)); + setArg(call_get_pow_890, 1, EEW); + setRet(call_get_pow_890, 0, ret_val_get_pow_890); + setArg(call_get_sew_pow_891, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_891, 0, ret_val_get_sew_pow_891); + setArg(call_get_lmul_pow_892, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_892, 0, ret_val_get_lmul_pow_892); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_893; + auto illegal_store_893_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_893 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_893, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_893; + setArg(call_illegal_store_893, 0, reinterpret_cast(this)); + setArg(call_illegal_store_893, 1, 7); + setArg(call_illegal_store_893, 2, EEW); + setArg(call_illegal_store_893, 3, illegal_store_893_arg2); + setRet(call_illegal_store_893, 0, ret_val_illegal_store_893); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_894; + auto vssseg_894_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_894_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_894_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_894_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_894_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_894 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_894, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_894, 32, false), traits::vstart); + setArg(call_vssseg_894, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_894, 1, V); + setArg(call_vssseg_894, 2, vssseg_894_arg1); + setArg(call_vssseg_894, 3, vssseg_894_arg2); + setArg(call_vssseg_894, 4, vssseg_894_arg3); + setArg(call_vssseg_894, 5, vm); + setArg(call_vssseg_894, 6, vs3); + setArg(call_vssseg_894, 7, vssseg_894_arg6); + setArg(call_vssseg_894, 8, 7); + setArg(call_vssseg_894, 9, 7); + setArg(call_vssseg_894, 10, vssseg_894_arg9); + setRet(call_vssseg_894, 0, ret_val_vssseg_894); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 286); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 287: VSSSEG8E8__V */ + continuation_e __vssseg8e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG8E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 287); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_895; + x86::Gp ret_val_get_pow_895 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_895, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_896; + x86::Gp ret_val_get_sew_pow_896 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_896, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_897; + x86::Gp ret_val_get_lmul_pow_897 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_897, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_895, ret_val_get_sew_pow_896), ret_val_get_lmul_pow_897)), 3, true); + setArg(call_get_pow_895, 0, reinterpret_cast(this)); + setArg(call_get_pow_895, 1, EEW); + setRet(call_get_pow_895, 0, ret_val_get_pow_895); + setArg(call_get_sew_pow_896, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_896, 0, ret_val_get_sew_pow_896); + setArg(call_get_lmul_pow_897, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_897, 0, ret_val_get_lmul_pow_897); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_898; + auto illegal_store_898_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_898 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_898, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_898; + setArg(call_illegal_store_898, 0, reinterpret_cast(this)); + setArg(call_illegal_store_898, 1, 8); + setArg(call_illegal_store_898, 2, EEW); + setArg(call_illegal_store_898, 3, illegal_store_898_arg2); + setRet(call_illegal_store_898, 0, ret_val_illegal_store_898); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_899; + auto vssseg_899_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_899_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_899_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_899_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_899_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_899 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_899, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_899, 32, false), traits::vstart); + setArg(call_vssseg_899, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_899, 1, V); + setArg(call_vssseg_899, 2, vssseg_899_arg1); + setArg(call_vssseg_899, 3, vssseg_899_arg2); + setArg(call_vssseg_899, 4, vssseg_899_arg3); + setArg(call_vssseg_899, 5, vm); + setArg(call_vssseg_899, 6, vs3); + setArg(call_vssseg_899, 7, vssseg_899_arg6); + setArg(call_vssseg_899, 8, 0); + setArg(call_vssseg_899, 9, 8); + setArg(call_vssseg_899, 10, vssseg_899_arg9); + setRet(call_vssseg_899, 0, ret_val_vssseg_899); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 287); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 288: VSSSEG8E16__V */ + continuation_e __vssseg8e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG8E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 288); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_900; + x86::Gp ret_val_get_pow_900 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_900, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_901; + x86::Gp ret_val_get_sew_pow_901 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_901, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_902; + x86::Gp ret_val_get_lmul_pow_902 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_902, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_900, ret_val_get_sew_pow_901), ret_val_get_lmul_pow_902)), 3, true); + setArg(call_get_pow_900, 0, reinterpret_cast(this)); + setArg(call_get_pow_900, 1, EEW); + setRet(call_get_pow_900, 0, ret_val_get_pow_900); + setArg(call_get_sew_pow_901, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_901, 0, ret_val_get_sew_pow_901); + setArg(call_get_lmul_pow_902, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_902, 0, ret_val_get_lmul_pow_902); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_903; + auto illegal_store_903_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_903 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_903, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_903; + setArg(call_illegal_store_903, 0, reinterpret_cast(this)); + setArg(call_illegal_store_903, 1, 8); + setArg(call_illegal_store_903, 2, EEW); + setArg(call_illegal_store_903, 3, illegal_store_903_arg2); + setRet(call_illegal_store_903, 0, ret_val_illegal_store_903); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_904; + auto vssseg_904_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_904_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_904_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_904_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_904_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_904 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_904, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_904, 32, false), traits::vstart); + setArg(call_vssseg_904, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_904, 1, V); + setArg(call_vssseg_904, 2, vssseg_904_arg1); + setArg(call_vssseg_904, 3, vssseg_904_arg2); + setArg(call_vssseg_904, 4, vssseg_904_arg3); + setArg(call_vssseg_904, 5, vm); + setArg(call_vssseg_904, 6, vs3); + setArg(call_vssseg_904, 7, vssseg_904_arg6); + setArg(call_vssseg_904, 8, 5); + setArg(call_vssseg_904, 9, 8); + setArg(call_vssseg_904, 10, vssseg_904_arg9); + setRet(call_vssseg_904, 0, ret_val_vssseg_904); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 288); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 289: VSSSEG8E32__V */ + continuation_e __vssseg8e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG8E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 289); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_905; + x86::Gp ret_val_get_pow_905 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_905, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_906; + x86::Gp ret_val_get_sew_pow_906 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_906, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_907; + x86::Gp ret_val_get_lmul_pow_907 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_907, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_905, ret_val_get_sew_pow_906), ret_val_get_lmul_pow_907)), 3, true); + setArg(call_get_pow_905, 0, reinterpret_cast(this)); + setArg(call_get_pow_905, 1, EEW); + setRet(call_get_pow_905, 0, ret_val_get_pow_905); + setArg(call_get_sew_pow_906, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_906, 0, ret_val_get_sew_pow_906); + setArg(call_get_lmul_pow_907, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_907, 0, ret_val_get_lmul_pow_907); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_908; + auto illegal_store_908_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_908 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_908, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_908; + setArg(call_illegal_store_908, 0, reinterpret_cast(this)); + setArg(call_illegal_store_908, 1, 8); + setArg(call_illegal_store_908, 2, EEW); + setArg(call_illegal_store_908, 3, illegal_store_908_arg2); + setRet(call_illegal_store_908, 0, ret_val_illegal_store_908); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_909; + auto vssseg_909_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_909_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_909_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_909_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_909_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_909 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_909, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_909, 32, false), traits::vstart); + setArg(call_vssseg_909, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_909, 1, V); + setArg(call_vssseg_909, 2, vssseg_909_arg1); + setArg(call_vssseg_909, 3, vssseg_909_arg2); + setArg(call_vssseg_909, 4, vssseg_909_arg3); + setArg(call_vssseg_909, 5, vm); + setArg(call_vssseg_909, 6, vs3); + setArg(call_vssseg_909, 7, vssseg_909_arg6); + setArg(call_vssseg_909, 8, 6); + setArg(call_vssseg_909, 9, 8); + setArg(call_vssseg_909, 10, vssseg_909_arg9); + setRet(call_vssseg_909, 0, ret_val_vssseg_909); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 289); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 290: VSSSEG8E64__V */ + continuation_e __vssseg8e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG8E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 290); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_910; + x86::Gp ret_val_get_pow_910 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_910, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_911; + x86::Gp ret_val_get_sew_pow_911 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_911, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_912; + x86::Gp ret_val_get_lmul_pow_912 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_912, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_910, ret_val_get_sew_pow_911), ret_val_get_lmul_pow_912)), 3, true); + setArg(call_get_pow_910, 0, reinterpret_cast(this)); + setArg(call_get_pow_910, 1, EEW); + setRet(call_get_pow_910, 0, ret_val_get_pow_910); + setArg(call_get_sew_pow_911, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_911, 0, ret_val_get_sew_pow_911); + setArg(call_get_lmul_pow_912, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_912, 0, ret_val_get_lmul_pow_912); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_913; + auto illegal_store_913_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_913 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_913, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_913; + setArg(call_illegal_store_913, 0, reinterpret_cast(this)); + setArg(call_illegal_store_913, 1, 8); + setArg(call_illegal_store_913, 2, EEW); + setArg(call_illegal_store_913, 3, illegal_store_913_arg2); + setRet(call_illegal_store_913, 0, ret_val_illegal_store_913); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_914; + auto vssseg_914_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_914_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_914_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_914_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_914_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_914 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_914, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_914, 32, false), traits::vstart); + setArg(call_vssseg_914, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_914, 1, V); + setArg(call_vssseg_914, 2, vssseg_914_arg1); + setArg(call_vssseg_914, 3, vssseg_914_arg2); + setArg(call_vssseg_914, 4, vssseg_914_arg3); + setArg(call_vssseg_914, 5, vm); + setArg(call_vssseg_914, 6, vs3); + setArg(call_vssseg_914, 7, vssseg_914_arg6); + setArg(call_vssseg_914, 8, 7); + setArg(call_vssseg_914, 9, 8); + setArg(call_vssseg_914, 10, vssseg_914_arg9); + setRet(call_vssseg_914, 0, ret_val_vssseg_914); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 290); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 291: VLE8FF__V */ + continuation_e __vle8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 291); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_915; + x86::Gp ret_val_get_pow_915 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_915, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_916; + x86::Gp ret_val_get_sew_pow_916 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_916, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_917; + x86::Gp ret_val_get_lmul_pow_917 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_917, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_915, ret_val_get_sew_pow_916), ret_val_get_lmul_pow_917)), 3, true); + setArg(call_get_pow_915, 0, reinterpret_cast(this)); + setArg(call_get_pow_915, 1, EEW); + setRet(call_get_pow_915, 0, ret_val_get_pow_915); + setArg(call_get_sew_pow_916, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_916, 0, ret_val_get_sew_pow_916); + setArg(call_get_lmul_pow_917, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_917, 0, ret_val_get_lmul_pow_917); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_918; + auto illegal_load_918_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_918 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_918, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_918; + setArg(call_illegal_load_918, 0, reinterpret_cast(this)); + setArg(call_illegal_load_918, 1, vd); + setArg(call_illegal_load_918, 2, vm); + setArg(call_illegal_load_918, 3, 1); + setArg(call_illegal_load_918, 4, EEW); + setArg(call_illegal_load_918, 5, illegal_load_918_arg4); + setRet(call_illegal_load_918, 0, ret_val_illegal_load_918); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_919; + auto vlseg_919_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_919_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_919_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_919_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_919 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_919, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_919, 32, false); + setArg(call_vlseg_919, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_919, 1, V); + setArg(call_vlseg_919, 2, vlseg_919_arg1); + setArg(call_vlseg_919, 3, vlseg_919_arg2); + setArg(call_vlseg_919, 4, vlseg_919_arg3); + setArg(call_vlseg_919, 5, vm); + setArg(call_vlseg_919, 6, vd); + setArg(call_vlseg_919, 7, vlseg_919_arg6); + setArg(call_vlseg_919, 8, 0); + setArg(call_vlseg_919, 9, 1); + setRet(call_vlseg_919, 0, ret_val_vlseg_919); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 291); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 292: VLE16FF__V */ + continuation_e __vle16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 292); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_920; + x86::Gp ret_val_get_pow_920 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_920, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_921; + x86::Gp ret_val_get_sew_pow_921 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_921, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_922; + x86::Gp ret_val_get_lmul_pow_922 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_922, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_920, ret_val_get_sew_pow_921), ret_val_get_lmul_pow_922)), 3, true); + setArg(call_get_pow_920, 0, reinterpret_cast(this)); + setArg(call_get_pow_920, 1, EEW); + setRet(call_get_pow_920, 0, ret_val_get_pow_920); + setArg(call_get_sew_pow_921, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_921, 0, ret_val_get_sew_pow_921); + setArg(call_get_lmul_pow_922, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_922, 0, ret_val_get_lmul_pow_922); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_923; + auto illegal_load_923_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_923 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_923, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_923; + setArg(call_illegal_load_923, 0, reinterpret_cast(this)); + setArg(call_illegal_load_923, 1, vd); + setArg(call_illegal_load_923, 2, vm); + setArg(call_illegal_load_923, 3, 1); + setArg(call_illegal_load_923, 4, EEW); + setArg(call_illegal_load_923, 5, illegal_load_923_arg4); + setRet(call_illegal_load_923, 0, ret_val_illegal_load_923); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_924; + auto vlseg_924_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_924_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_924_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_924_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_924 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_924, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_924, 32, false); + setArg(call_vlseg_924, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_924, 1, V); + setArg(call_vlseg_924, 2, vlseg_924_arg1); + setArg(call_vlseg_924, 3, vlseg_924_arg2); + setArg(call_vlseg_924, 4, vlseg_924_arg3); + setArg(call_vlseg_924, 5, vm); + setArg(call_vlseg_924, 6, vd); + setArg(call_vlseg_924, 7, vlseg_924_arg6); + setArg(call_vlseg_924, 8, 5); + setArg(call_vlseg_924, 9, 1); + setRet(call_vlseg_924, 0, ret_val_vlseg_924); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 292); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 293: VLE32FF__V */ + continuation_e __vle32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 293); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_925; + x86::Gp ret_val_get_pow_925 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_925, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_926; + x86::Gp ret_val_get_sew_pow_926 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_926, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_927; + x86::Gp ret_val_get_lmul_pow_927 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_927, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_925, ret_val_get_sew_pow_926), ret_val_get_lmul_pow_927)), 3, true); + setArg(call_get_pow_925, 0, reinterpret_cast(this)); + setArg(call_get_pow_925, 1, EEW); + setRet(call_get_pow_925, 0, ret_val_get_pow_925); + setArg(call_get_sew_pow_926, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_926, 0, ret_val_get_sew_pow_926); + setArg(call_get_lmul_pow_927, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_927, 0, ret_val_get_lmul_pow_927); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_928; + auto illegal_load_928_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_928 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_928, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_928; + setArg(call_illegal_load_928, 0, reinterpret_cast(this)); + setArg(call_illegal_load_928, 1, vd); + setArg(call_illegal_load_928, 2, vm); + setArg(call_illegal_load_928, 3, 1); + setArg(call_illegal_load_928, 4, EEW); + setArg(call_illegal_load_928, 5, illegal_load_928_arg4); + setRet(call_illegal_load_928, 0, ret_val_illegal_load_928); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_929; + auto vlseg_929_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_929_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_929_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_929_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_929 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_929, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_929, 32, false); + setArg(call_vlseg_929, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_929, 1, V); + setArg(call_vlseg_929, 2, vlseg_929_arg1); + setArg(call_vlseg_929, 3, vlseg_929_arg2); + setArg(call_vlseg_929, 4, vlseg_929_arg3); + setArg(call_vlseg_929, 5, vm); + setArg(call_vlseg_929, 6, vd); + setArg(call_vlseg_929, 7, vlseg_929_arg6); + setArg(call_vlseg_929, 8, 6); + setArg(call_vlseg_929, 9, 1); + setRet(call_vlseg_929, 0, ret_val_vlseg_929); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 293); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 294: VLE64FF__V */ + continuation_e __vle64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 294); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_930; + x86::Gp ret_val_get_pow_930 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_930, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_931; + x86::Gp ret_val_get_sew_pow_931 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_931, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_932; + x86::Gp ret_val_get_lmul_pow_932 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_932, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_930, ret_val_get_sew_pow_931), ret_val_get_lmul_pow_932)), 3, true); + setArg(call_get_pow_930, 0, reinterpret_cast(this)); + setArg(call_get_pow_930, 1, EEW); + setRet(call_get_pow_930, 0, ret_val_get_pow_930); + setArg(call_get_sew_pow_931, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_931, 0, ret_val_get_sew_pow_931); + setArg(call_get_lmul_pow_932, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_932, 0, ret_val_get_lmul_pow_932); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_933; + auto illegal_load_933_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_933 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_933, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_933; + setArg(call_illegal_load_933, 0, reinterpret_cast(this)); + setArg(call_illegal_load_933, 1, vd); + setArg(call_illegal_load_933, 2, vm); + setArg(call_illegal_load_933, 3, 1); + setArg(call_illegal_load_933, 4, EEW); + setArg(call_illegal_load_933, 5, illegal_load_933_arg4); + setRet(call_illegal_load_933, 0, ret_val_illegal_load_933); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_934; + auto vlseg_934_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_934_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_934_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_934_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_934 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_934, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_934, 32, false); + setArg(call_vlseg_934, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_934, 1, V); + setArg(call_vlseg_934, 2, vlseg_934_arg1); + setArg(call_vlseg_934, 3, vlseg_934_arg2); + setArg(call_vlseg_934, 4, vlseg_934_arg3); + setArg(call_vlseg_934, 5, vm); + setArg(call_vlseg_934, 6, vd); + setArg(call_vlseg_934, 7, vlseg_934_arg6); + setArg(call_vlseg_934, 8, 7); + setArg(call_vlseg_934, 9, 1); + setRet(call_vlseg_934, 0, ret_val_vlseg_934); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 294); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 295: VLSEG2E8FF__V */ + continuation_e __vlseg2e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 295); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_935; + x86::Gp ret_val_get_pow_935 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_935, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_936; + x86::Gp ret_val_get_sew_pow_936 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_936, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_937; + x86::Gp ret_val_get_lmul_pow_937 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_937, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_935, ret_val_get_sew_pow_936), ret_val_get_lmul_pow_937)), 3, true); + setArg(call_get_pow_935, 0, reinterpret_cast(this)); + setArg(call_get_pow_935, 1, EEW); + setRet(call_get_pow_935, 0, ret_val_get_pow_935); + setArg(call_get_sew_pow_936, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_936, 0, ret_val_get_sew_pow_936); + setArg(call_get_lmul_pow_937, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_937, 0, ret_val_get_lmul_pow_937); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_938; + auto illegal_load_938_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_938 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_938, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_938; + setArg(call_illegal_load_938, 0, reinterpret_cast(this)); + setArg(call_illegal_load_938, 1, vd); + setArg(call_illegal_load_938, 2, vm); + setArg(call_illegal_load_938, 3, 2); + setArg(call_illegal_load_938, 4, EEW); + setArg(call_illegal_load_938, 5, illegal_load_938_arg4); + setRet(call_illegal_load_938, 0, ret_val_illegal_load_938); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_939; + auto vlseg_939_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_939_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_939_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_939_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_939 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_939, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_939, 32, false); + setArg(call_vlseg_939, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_939, 1, V); + setArg(call_vlseg_939, 2, vlseg_939_arg1); + setArg(call_vlseg_939, 3, vlseg_939_arg2); + setArg(call_vlseg_939, 4, vlseg_939_arg3); + setArg(call_vlseg_939, 5, vm); + setArg(call_vlseg_939, 6, vd); + setArg(call_vlseg_939, 7, vlseg_939_arg6); + setArg(call_vlseg_939, 8, 0); + setArg(call_vlseg_939, 9, 2); + setRet(call_vlseg_939, 0, ret_val_vlseg_939); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 295); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 296: VLSEG2E16FF__V */ + continuation_e __vlseg2e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 296); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_940; + x86::Gp ret_val_get_pow_940 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_940, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_941; + x86::Gp ret_val_get_sew_pow_941 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_941, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_942; + x86::Gp ret_val_get_lmul_pow_942 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_942, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_940, ret_val_get_sew_pow_941), ret_val_get_lmul_pow_942)), 3, true); + setArg(call_get_pow_940, 0, reinterpret_cast(this)); + setArg(call_get_pow_940, 1, EEW); + setRet(call_get_pow_940, 0, ret_val_get_pow_940); + setArg(call_get_sew_pow_941, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_941, 0, ret_val_get_sew_pow_941); + setArg(call_get_lmul_pow_942, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_942, 0, ret_val_get_lmul_pow_942); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_943; + auto illegal_load_943_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_943 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_943, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_943; + setArg(call_illegal_load_943, 0, reinterpret_cast(this)); + setArg(call_illegal_load_943, 1, vd); + setArg(call_illegal_load_943, 2, vm); + setArg(call_illegal_load_943, 3, 2); + setArg(call_illegal_load_943, 4, EEW); + setArg(call_illegal_load_943, 5, illegal_load_943_arg4); + setRet(call_illegal_load_943, 0, ret_val_illegal_load_943); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_944; + auto vlseg_944_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_944_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_944_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_944_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_944 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_944, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_944, 32, false); + setArg(call_vlseg_944, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_944, 1, V); + setArg(call_vlseg_944, 2, vlseg_944_arg1); + setArg(call_vlseg_944, 3, vlseg_944_arg2); + setArg(call_vlseg_944, 4, vlseg_944_arg3); + setArg(call_vlseg_944, 5, vm); + setArg(call_vlseg_944, 6, vd); + setArg(call_vlseg_944, 7, vlseg_944_arg6); + setArg(call_vlseg_944, 8, 5); + setArg(call_vlseg_944, 9, 2); + setRet(call_vlseg_944, 0, ret_val_vlseg_944); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 296); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 297: VLSEG2E32FF__V */ + continuation_e __vlseg2e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 297); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_945; + x86::Gp ret_val_get_pow_945 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_945, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_946; + x86::Gp ret_val_get_sew_pow_946 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_946, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_947; + x86::Gp ret_val_get_lmul_pow_947 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_947, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_945, ret_val_get_sew_pow_946), ret_val_get_lmul_pow_947)), 3, true); + setArg(call_get_pow_945, 0, reinterpret_cast(this)); + setArg(call_get_pow_945, 1, EEW); + setRet(call_get_pow_945, 0, ret_val_get_pow_945); + setArg(call_get_sew_pow_946, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_946, 0, ret_val_get_sew_pow_946); + setArg(call_get_lmul_pow_947, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_947, 0, ret_val_get_lmul_pow_947); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_948; + auto illegal_load_948_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_948 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_948, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_948; + setArg(call_illegal_load_948, 0, reinterpret_cast(this)); + setArg(call_illegal_load_948, 1, vd); + setArg(call_illegal_load_948, 2, vm); + setArg(call_illegal_load_948, 3, 2); + setArg(call_illegal_load_948, 4, EEW); + setArg(call_illegal_load_948, 5, illegal_load_948_arg4); + setRet(call_illegal_load_948, 0, ret_val_illegal_load_948); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_949; + auto vlseg_949_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_949_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_949_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_949_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_949 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_949, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_949, 32, false); + setArg(call_vlseg_949, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_949, 1, V); + setArg(call_vlseg_949, 2, vlseg_949_arg1); + setArg(call_vlseg_949, 3, vlseg_949_arg2); + setArg(call_vlseg_949, 4, vlseg_949_arg3); + setArg(call_vlseg_949, 5, vm); + setArg(call_vlseg_949, 6, vd); + setArg(call_vlseg_949, 7, vlseg_949_arg6); + setArg(call_vlseg_949, 8, 6); + setArg(call_vlseg_949, 9, 2); + setRet(call_vlseg_949, 0, ret_val_vlseg_949); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 297); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 298: VLSEG2E64FF__V */ + continuation_e __vlseg2e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 298); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_950; + x86::Gp ret_val_get_pow_950 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_950, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_951; + x86::Gp ret_val_get_sew_pow_951 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_951, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_952; + x86::Gp ret_val_get_lmul_pow_952 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_952, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_950, ret_val_get_sew_pow_951), ret_val_get_lmul_pow_952)), 3, true); + setArg(call_get_pow_950, 0, reinterpret_cast(this)); + setArg(call_get_pow_950, 1, EEW); + setRet(call_get_pow_950, 0, ret_val_get_pow_950); + setArg(call_get_sew_pow_951, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_951, 0, ret_val_get_sew_pow_951); + setArg(call_get_lmul_pow_952, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_952, 0, ret_val_get_lmul_pow_952); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_953; + auto illegal_load_953_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_953 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_953, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_953; + setArg(call_illegal_load_953, 0, reinterpret_cast(this)); + setArg(call_illegal_load_953, 1, vd); + setArg(call_illegal_load_953, 2, vm); + setArg(call_illegal_load_953, 3, 2); + setArg(call_illegal_load_953, 4, EEW); + setArg(call_illegal_load_953, 5, illegal_load_953_arg4); + setRet(call_illegal_load_953, 0, ret_val_illegal_load_953); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_954; + auto vlseg_954_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_954_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_954_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_954_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_954 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_954, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_954, 32, false); + setArg(call_vlseg_954, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_954, 1, V); + setArg(call_vlseg_954, 2, vlseg_954_arg1); + setArg(call_vlseg_954, 3, vlseg_954_arg2); + setArg(call_vlseg_954, 4, vlseg_954_arg3); + setArg(call_vlseg_954, 5, vm); + setArg(call_vlseg_954, 6, vd); + setArg(call_vlseg_954, 7, vlseg_954_arg6); + setArg(call_vlseg_954, 8, 7); + setArg(call_vlseg_954, 9, 2); + setRet(call_vlseg_954, 0, ret_val_vlseg_954); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 298); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 299: VLSEG3E8FF__V */ + continuation_e __vlseg3e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 299); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_955; + x86::Gp ret_val_get_pow_955 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_955, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_956; + x86::Gp ret_val_get_sew_pow_956 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_956, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_957; + x86::Gp ret_val_get_lmul_pow_957 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_957, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_955, ret_val_get_sew_pow_956), ret_val_get_lmul_pow_957)), 3, true); + setArg(call_get_pow_955, 0, reinterpret_cast(this)); + setArg(call_get_pow_955, 1, EEW); + setRet(call_get_pow_955, 0, ret_val_get_pow_955); + setArg(call_get_sew_pow_956, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_956, 0, ret_val_get_sew_pow_956); + setArg(call_get_lmul_pow_957, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_957, 0, ret_val_get_lmul_pow_957); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_958; + auto illegal_load_958_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_958 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_958, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_958; + setArg(call_illegal_load_958, 0, reinterpret_cast(this)); + setArg(call_illegal_load_958, 1, vd); + setArg(call_illegal_load_958, 2, vm); + setArg(call_illegal_load_958, 3, 3); + setArg(call_illegal_load_958, 4, EEW); + setArg(call_illegal_load_958, 5, illegal_load_958_arg4); + setRet(call_illegal_load_958, 0, ret_val_illegal_load_958); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_959; + auto vlseg_959_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_959_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_959_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_959_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_959 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_959, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_959, 32, false); + setArg(call_vlseg_959, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_959, 1, V); + setArg(call_vlseg_959, 2, vlseg_959_arg1); + setArg(call_vlseg_959, 3, vlseg_959_arg2); + setArg(call_vlseg_959, 4, vlseg_959_arg3); + setArg(call_vlseg_959, 5, vm); + setArg(call_vlseg_959, 6, vd); + setArg(call_vlseg_959, 7, vlseg_959_arg6); + setArg(call_vlseg_959, 8, 0); + setArg(call_vlseg_959, 9, 3); + setRet(call_vlseg_959, 0, ret_val_vlseg_959); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 299); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 300: VLSEG3E16FF__V */ + continuation_e __vlseg3e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 300); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_960; + x86::Gp ret_val_get_pow_960 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_960, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_961; + x86::Gp ret_val_get_sew_pow_961 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_961, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_962; + x86::Gp ret_val_get_lmul_pow_962 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_962, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_960, ret_val_get_sew_pow_961), ret_val_get_lmul_pow_962)), 3, true); + setArg(call_get_pow_960, 0, reinterpret_cast(this)); + setArg(call_get_pow_960, 1, EEW); + setRet(call_get_pow_960, 0, ret_val_get_pow_960); + setArg(call_get_sew_pow_961, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_961, 0, ret_val_get_sew_pow_961); + setArg(call_get_lmul_pow_962, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_962, 0, ret_val_get_lmul_pow_962); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_963; + auto illegal_load_963_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_963 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_963, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_963; + setArg(call_illegal_load_963, 0, reinterpret_cast(this)); + setArg(call_illegal_load_963, 1, vd); + setArg(call_illegal_load_963, 2, vm); + setArg(call_illegal_load_963, 3, 3); + setArg(call_illegal_load_963, 4, EEW); + setArg(call_illegal_load_963, 5, illegal_load_963_arg4); + setRet(call_illegal_load_963, 0, ret_val_illegal_load_963); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_964; + auto vlseg_964_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_964_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_964_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_964_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_964 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_964, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_964, 32, false); + setArg(call_vlseg_964, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_964, 1, V); + setArg(call_vlseg_964, 2, vlseg_964_arg1); + setArg(call_vlseg_964, 3, vlseg_964_arg2); + setArg(call_vlseg_964, 4, vlseg_964_arg3); + setArg(call_vlseg_964, 5, vm); + setArg(call_vlseg_964, 6, vd); + setArg(call_vlseg_964, 7, vlseg_964_arg6); + setArg(call_vlseg_964, 8, 5); + setArg(call_vlseg_964, 9, 3); + setRet(call_vlseg_964, 0, ret_val_vlseg_964); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 300); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 301: VLSEG3E32FF__V */ + continuation_e __vlseg3e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 301); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_965; + x86::Gp ret_val_get_pow_965 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_965, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_966; + x86::Gp ret_val_get_sew_pow_966 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_966, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_967; + x86::Gp ret_val_get_lmul_pow_967 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_967, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_965, ret_val_get_sew_pow_966), ret_val_get_lmul_pow_967)), 3, true); + setArg(call_get_pow_965, 0, reinterpret_cast(this)); + setArg(call_get_pow_965, 1, EEW); + setRet(call_get_pow_965, 0, ret_val_get_pow_965); + setArg(call_get_sew_pow_966, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_966, 0, ret_val_get_sew_pow_966); + setArg(call_get_lmul_pow_967, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_967, 0, ret_val_get_lmul_pow_967); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_968; + auto illegal_load_968_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_968 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_968, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_968; + setArg(call_illegal_load_968, 0, reinterpret_cast(this)); + setArg(call_illegal_load_968, 1, vd); + setArg(call_illegal_load_968, 2, vm); + setArg(call_illegal_load_968, 3, 3); + setArg(call_illegal_load_968, 4, EEW); + setArg(call_illegal_load_968, 5, illegal_load_968_arg4); + setRet(call_illegal_load_968, 0, ret_val_illegal_load_968); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_969; + auto vlseg_969_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_969_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_969_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_969_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_969 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_969, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_969, 32, false); + setArg(call_vlseg_969, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_969, 1, V); + setArg(call_vlseg_969, 2, vlseg_969_arg1); + setArg(call_vlseg_969, 3, vlseg_969_arg2); + setArg(call_vlseg_969, 4, vlseg_969_arg3); + setArg(call_vlseg_969, 5, vm); + setArg(call_vlseg_969, 6, vd); + setArg(call_vlseg_969, 7, vlseg_969_arg6); + setArg(call_vlseg_969, 8, 6); + setArg(call_vlseg_969, 9, 3); + setRet(call_vlseg_969, 0, ret_val_vlseg_969); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 301); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 302: VLSEG3E64FF__V */ + continuation_e __vlseg3e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 302); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_970; + x86::Gp ret_val_get_pow_970 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_970, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_971; + x86::Gp ret_val_get_sew_pow_971 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_971, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_972; + x86::Gp ret_val_get_lmul_pow_972 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_972, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_970, ret_val_get_sew_pow_971), ret_val_get_lmul_pow_972)), 3, true); + setArg(call_get_pow_970, 0, reinterpret_cast(this)); + setArg(call_get_pow_970, 1, EEW); + setRet(call_get_pow_970, 0, ret_val_get_pow_970); + setArg(call_get_sew_pow_971, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_971, 0, ret_val_get_sew_pow_971); + setArg(call_get_lmul_pow_972, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_972, 0, ret_val_get_lmul_pow_972); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_973; + auto illegal_load_973_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_973 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_973, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_973; + setArg(call_illegal_load_973, 0, reinterpret_cast(this)); + setArg(call_illegal_load_973, 1, vd); + setArg(call_illegal_load_973, 2, vm); + setArg(call_illegal_load_973, 3, 3); + setArg(call_illegal_load_973, 4, EEW); + setArg(call_illegal_load_973, 5, illegal_load_973_arg4); + setRet(call_illegal_load_973, 0, ret_val_illegal_load_973); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_974; + auto vlseg_974_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_974_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_974_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_974_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_974 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_974, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_974, 32, false); + setArg(call_vlseg_974, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_974, 1, V); + setArg(call_vlseg_974, 2, vlseg_974_arg1); + setArg(call_vlseg_974, 3, vlseg_974_arg2); + setArg(call_vlseg_974, 4, vlseg_974_arg3); + setArg(call_vlseg_974, 5, vm); + setArg(call_vlseg_974, 6, vd); + setArg(call_vlseg_974, 7, vlseg_974_arg6); + setArg(call_vlseg_974, 8, 7); + setArg(call_vlseg_974, 9, 3); + setRet(call_vlseg_974, 0, ret_val_vlseg_974); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 302); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 303: VLSEG4E8FF__V */ + continuation_e __vlseg4e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 303); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_975; + x86::Gp ret_val_get_pow_975 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_975, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_976; + x86::Gp ret_val_get_sew_pow_976 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_976, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_977; + x86::Gp ret_val_get_lmul_pow_977 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_977, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_975, ret_val_get_sew_pow_976), ret_val_get_lmul_pow_977)), 3, true); + setArg(call_get_pow_975, 0, reinterpret_cast(this)); + setArg(call_get_pow_975, 1, EEW); + setRet(call_get_pow_975, 0, ret_val_get_pow_975); + setArg(call_get_sew_pow_976, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_976, 0, ret_val_get_sew_pow_976); + setArg(call_get_lmul_pow_977, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_977, 0, ret_val_get_lmul_pow_977); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_978; + auto illegal_load_978_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_978 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_978, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_978; + setArg(call_illegal_load_978, 0, reinterpret_cast(this)); + setArg(call_illegal_load_978, 1, vd); + setArg(call_illegal_load_978, 2, vm); + setArg(call_illegal_load_978, 3, 4); + setArg(call_illegal_load_978, 4, EEW); + setArg(call_illegal_load_978, 5, illegal_load_978_arg4); + setRet(call_illegal_load_978, 0, ret_val_illegal_load_978); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_979; + auto vlseg_979_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_979_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_979_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_979_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_979 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_979, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_979, 32, false); + setArg(call_vlseg_979, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_979, 1, V); + setArg(call_vlseg_979, 2, vlseg_979_arg1); + setArg(call_vlseg_979, 3, vlseg_979_arg2); + setArg(call_vlseg_979, 4, vlseg_979_arg3); + setArg(call_vlseg_979, 5, vm); + setArg(call_vlseg_979, 6, vd); + setArg(call_vlseg_979, 7, vlseg_979_arg6); + setArg(call_vlseg_979, 8, 0); + setArg(call_vlseg_979, 9, 4); + setRet(call_vlseg_979, 0, ret_val_vlseg_979); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 303); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 304: VLSEG4E16FF__V */ + continuation_e __vlseg4e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 304); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_980; + x86::Gp ret_val_get_pow_980 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_980, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_981; + x86::Gp ret_val_get_sew_pow_981 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_981, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_982; + x86::Gp ret_val_get_lmul_pow_982 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_982, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_980, ret_val_get_sew_pow_981), ret_val_get_lmul_pow_982)), 3, true); + setArg(call_get_pow_980, 0, reinterpret_cast(this)); + setArg(call_get_pow_980, 1, EEW); + setRet(call_get_pow_980, 0, ret_val_get_pow_980); + setArg(call_get_sew_pow_981, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_981, 0, ret_val_get_sew_pow_981); + setArg(call_get_lmul_pow_982, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_982, 0, ret_val_get_lmul_pow_982); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_983; + auto illegal_load_983_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_983 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_983, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_983; + setArg(call_illegal_load_983, 0, reinterpret_cast(this)); + setArg(call_illegal_load_983, 1, vd); + setArg(call_illegal_load_983, 2, vm); + setArg(call_illegal_load_983, 3, 4); + setArg(call_illegal_load_983, 4, EEW); + setArg(call_illegal_load_983, 5, illegal_load_983_arg4); + setRet(call_illegal_load_983, 0, ret_val_illegal_load_983); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_984; + auto vlseg_984_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_984_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_984_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_984_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_984 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_984, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_984, 32, false); + setArg(call_vlseg_984, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_984, 1, V); + setArg(call_vlseg_984, 2, vlseg_984_arg1); + setArg(call_vlseg_984, 3, vlseg_984_arg2); + setArg(call_vlseg_984, 4, vlseg_984_arg3); + setArg(call_vlseg_984, 5, vm); + setArg(call_vlseg_984, 6, vd); + setArg(call_vlseg_984, 7, vlseg_984_arg6); + setArg(call_vlseg_984, 8, 5); + setArg(call_vlseg_984, 9, 4); + setRet(call_vlseg_984, 0, ret_val_vlseg_984); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 304); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 305: VLSEG4E32FF__V */ + continuation_e __vlseg4e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 305); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_985; + x86::Gp ret_val_get_pow_985 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_985, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_986; + x86::Gp ret_val_get_sew_pow_986 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_986, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_987; + x86::Gp ret_val_get_lmul_pow_987 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_987, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_985, ret_val_get_sew_pow_986), ret_val_get_lmul_pow_987)), 3, true); + setArg(call_get_pow_985, 0, reinterpret_cast(this)); + setArg(call_get_pow_985, 1, EEW); + setRet(call_get_pow_985, 0, ret_val_get_pow_985); + setArg(call_get_sew_pow_986, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_986, 0, ret_val_get_sew_pow_986); + setArg(call_get_lmul_pow_987, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_987, 0, ret_val_get_lmul_pow_987); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_988; + auto illegal_load_988_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_988 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_988, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_988; + setArg(call_illegal_load_988, 0, reinterpret_cast(this)); + setArg(call_illegal_load_988, 1, vd); + setArg(call_illegal_load_988, 2, vm); + setArg(call_illegal_load_988, 3, 4); + setArg(call_illegal_load_988, 4, EEW); + setArg(call_illegal_load_988, 5, illegal_load_988_arg4); + setRet(call_illegal_load_988, 0, ret_val_illegal_load_988); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_989; + auto vlseg_989_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_989_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_989_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_989_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_989 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_989, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_989, 32, false); + setArg(call_vlseg_989, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_989, 1, V); + setArg(call_vlseg_989, 2, vlseg_989_arg1); + setArg(call_vlseg_989, 3, vlseg_989_arg2); + setArg(call_vlseg_989, 4, vlseg_989_arg3); + setArg(call_vlseg_989, 5, vm); + setArg(call_vlseg_989, 6, vd); + setArg(call_vlseg_989, 7, vlseg_989_arg6); + setArg(call_vlseg_989, 8, 6); + setArg(call_vlseg_989, 9, 4); + setRet(call_vlseg_989, 0, ret_val_vlseg_989); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 305); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 306: VLSEG4E64FF__V */ + continuation_e __vlseg4e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 306); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_990; + x86::Gp ret_val_get_pow_990 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_990, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_991; + x86::Gp ret_val_get_sew_pow_991 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_991, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_992; + x86::Gp ret_val_get_lmul_pow_992 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_992, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_990, ret_val_get_sew_pow_991), ret_val_get_lmul_pow_992)), 3, true); + setArg(call_get_pow_990, 0, reinterpret_cast(this)); + setArg(call_get_pow_990, 1, EEW); + setRet(call_get_pow_990, 0, ret_val_get_pow_990); + setArg(call_get_sew_pow_991, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_991, 0, ret_val_get_sew_pow_991); + setArg(call_get_lmul_pow_992, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_992, 0, ret_val_get_lmul_pow_992); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_993; + auto illegal_load_993_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_993 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_993, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_993; + setArg(call_illegal_load_993, 0, reinterpret_cast(this)); + setArg(call_illegal_load_993, 1, vd); + setArg(call_illegal_load_993, 2, vm); + setArg(call_illegal_load_993, 3, 4); + setArg(call_illegal_load_993, 4, EEW); + setArg(call_illegal_load_993, 5, illegal_load_993_arg4); + setRet(call_illegal_load_993, 0, ret_val_illegal_load_993); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_994; + auto vlseg_994_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_994_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_994_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_994_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_994 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_994, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_994, 32, false); + setArg(call_vlseg_994, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_994, 1, V); + setArg(call_vlseg_994, 2, vlseg_994_arg1); + setArg(call_vlseg_994, 3, vlseg_994_arg2); + setArg(call_vlseg_994, 4, vlseg_994_arg3); + setArg(call_vlseg_994, 5, vm); + setArg(call_vlseg_994, 6, vd); + setArg(call_vlseg_994, 7, vlseg_994_arg6); + setArg(call_vlseg_994, 8, 7); + setArg(call_vlseg_994, 9, 4); + setRet(call_vlseg_994, 0, ret_val_vlseg_994); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 306); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 307: VLSEG5E8FF__V */ + continuation_e __vlseg5e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 307); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_995; + x86::Gp ret_val_get_pow_995 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_995, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_996; + x86::Gp ret_val_get_sew_pow_996 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_996, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_997; + x86::Gp ret_val_get_lmul_pow_997 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_997, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_995, ret_val_get_sew_pow_996), ret_val_get_lmul_pow_997)), 3, true); + setArg(call_get_pow_995, 0, reinterpret_cast(this)); + setArg(call_get_pow_995, 1, EEW); + setRet(call_get_pow_995, 0, ret_val_get_pow_995); + setArg(call_get_sew_pow_996, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_996, 0, ret_val_get_sew_pow_996); + setArg(call_get_lmul_pow_997, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_997, 0, ret_val_get_lmul_pow_997); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_998; + auto illegal_load_998_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_998 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_998, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_998; + setArg(call_illegal_load_998, 0, reinterpret_cast(this)); + setArg(call_illegal_load_998, 1, vd); + setArg(call_illegal_load_998, 2, vm); + setArg(call_illegal_load_998, 3, 5); + setArg(call_illegal_load_998, 4, EEW); + setArg(call_illegal_load_998, 5, illegal_load_998_arg4); + setRet(call_illegal_load_998, 0, ret_val_illegal_load_998); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_999; + auto vlseg_999_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_999_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_999_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_999_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_999 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_999, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_999, 32, false); + setArg(call_vlseg_999, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_999, 1, V); + setArg(call_vlseg_999, 2, vlseg_999_arg1); + setArg(call_vlseg_999, 3, vlseg_999_arg2); + setArg(call_vlseg_999, 4, vlseg_999_arg3); + setArg(call_vlseg_999, 5, vm); + setArg(call_vlseg_999, 6, vd); + setArg(call_vlseg_999, 7, vlseg_999_arg6); + setArg(call_vlseg_999, 8, 0); + setArg(call_vlseg_999, 9, 5); + setRet(call_vlseg_999, 0, ret_val_vlseg_999); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 307); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 308: VLSEG5E16FF__V */ + continuation_e __vlseg5e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 308); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1000; + x86::Gp ret_val_get_pow_1000 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1000, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1001; + x86::Gp ret_val_get_sew_pow_1001 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1001, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1002; + x86::Gp ret_val_get_lmul_pow_1002 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1002, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1000, ret_val_get_sew_pow_1001), ret_val_get_lmul_pow_1002)), 3, true); + setArg(call_get_pow_1000, 0, reinterpret_cast(this)); + setArg(call_get_pow_1000, 1, EEW); + setRet(call_get_pow_1000, 0, ret_val_get_pow_1000); + setArg(call_get_sew_pow_1001, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1001, 0, ret_val_get_sew_pow_1001); + setArg(call_get_lmul_pow_1002, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1002, 0, ret_val_get_lmul_pow_1002); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1003; + auto illegal_load_1003_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1003 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1003, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1003; + setArg(call_illegal_load_1003, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1003, 1, vd); + setArg(call_illegal_load_1003, 2, vm); + setArg(call_illegal_load_1003, 3, 5); + setArg(call_illegal_load_1003, 4, EEW); + setArg(call_illegal_load_1003, 5, illegal_load_1003_arg4); + setRet(call_illegal_load_1003, 0, ret_val_illegal_load_1003); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1004; + auto vlseg_1004_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1004_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1004_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1004_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1004 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1004, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1004, 32, false); + setArg(call_vlseg_1004, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1004, 1, V); + setArg(call_vlseg_1004, 2, vlseg_1004_arg1); + setArg(call_vlseg_1004, 3, vlseg_1004_arg2); + setArg(call_vlseg_1004, 4, vlseg_1004_arg3); + setArg(call_vlseg_1004, 5, vm); + setArg(call_vlseg_1004, 6, vd); + setArg(call_vlseg_1004, 7, vlseg_1004_arg6); + setArg(call_vlseg_1004, 8, 5); + setArg(call_vlseg_1004, 9, 5); + setRet(call_vlseg_1004, 0, ret_val_vlseg_1004); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 308); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 309: VLSEG5E32FF__V */ + continuation_e __vlseg5e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 309); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1005; + x86::Gp ret_val_get_pow_1005 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1005, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1006; + x86::Gp ret_val_get_sew_pow_1006 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1006, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1007; + x86::Gp ret_val_get_lmul_pow_1007 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1007, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1005, ret_val_get_sew_pow_1006), ret_val_get_lmul_pow_1007)), 3, true); + setArg(call_get_pow_1005, 0, reinterpret_cast(this)); + setArg(call_get_pow_1005, 1, EEW); + setRet(call_get_pow_1005, 0, ret_val_get_pow_1005); + setArg(call_get_sew_pow_1006, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1006, 0, ret_val_get_sew_pow_1006); + setArg(call_get_lmul_pow_1007, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1007, 0, ret_val_get_lmul_pow_1007); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1008; + auto illegal_load_1008_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1008 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1008, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1008; + setArg(call_illegal_load_1008, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1008, 1, vd); + setArg(call_illegal_load_1008, 2, vm); + setArg(call_illegal_load_1008, 3, 5); + setArg(call_illegal_load_1008, 4, EEW); + setArg(call_illegal_load_1008, 5, illegal_load_1008_arg4); + setRet(call_illegal_load_1008, 0, ret_val_illegal_load_1008); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1009; + auto vlseg_1009_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1009_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1009_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1009_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1009 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1009, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1009, 32, false); + setArg(call_vlseg_1009, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1009, 1, V); + setArg(call_vlseg_1009, 2, vlseg_1009_arg1); + setArg(call_vlseg_1009, 3, vlseg_1009_arg2); + setArg(call_vlseg_1009, 4, vlseg_1009_arg3); + setArg(call_vlseg_1009, 5, vm); + setArg(call_vlseg_1009, 6, vd); + setArg(call_vlseg_1009, 7, vlseg_1009_arg6); + setArg(call_vlseg_1009, 8, 6); + setArg(call_vlseg_1009, 9, 5); + setRet(call_vlseg_1009, 0, ret_val_vlseg_1009); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 309); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 310: VLSEG5E64FF__V */ + continuation_e __vlseg5e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 310); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1010; + x86::Gp ret_val_get_pow_1010 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1010, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1011; + x86::Gp ret_val_get_sew_pow_1011 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1011, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1012; + x86::Gp ret_val_get_lmul_pow_1012 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1012, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1010, ret_val_get_sew_pow_1011), ret_val_get_lmul_pow_1012)), 3, true); + setArg(call_get_pow_1010, 0, reinterpret_cast(this)); + setArg(call_get_pow_1010, 1, EEW); + setRet(call_get_pow_1010, 0, ret_val_get_pow_1010); + setArg(call_get_sew_pow_1011, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1011, 0, ret_val_get_sew_pow_1011); + setArg(call_get_lmul_pow_1012, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1012, 0, ret_val_get_lmul_pow_1012); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1013; + auto illegal_load_1013_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1013 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1013, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1013; + setArg(call_illegal_load_1013, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1013, 1, vd); + setArg(call_illegal_load_1013, 2, vm); + setArg(call_illegal_load_1013, 3, 5); + setArg(call_illegal_load_1013, 4, EEW); + setArg(call_illegal_load_1013, 5, illegal_load_1013_arg4); + setRet(call_illegal_load_1013, 0, ret_val_illegal_load_1013); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1014; + auto vlseg_1014_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1014_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1014_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1014_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1014 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1014, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1014, 32, false); + setArg(call_vlseg_1014, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1014, 1, V); + setArg(call_vlseg_1014, 2, vlseg_1014_arg1); + setArg(call_vlseg_1014, 3, vlseg_1014_arg2); + setArg(call_vlseg_1014, 4, vlseg_1014_arg3); + setArg(call_vlseg_1014, 5, vm); + setArg(call_vlseg_1014, 6, vd); + setArg(call_vlseg_1014, 7, vlseg_1014_arg6); + setArg(call_vlseg_1014, 8, 7); + setArg(call_vlseg_1014, 9, 5); + setRet(call_vlseg_1014, 0, ret_val_vlseg_1014); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 310); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 311: VLSEG6E8FF__V */ + continuation_e __vlseg6e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 311); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1015; + x86::Gp ret_val_get_pow_1015 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1015, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1016; + x86::Gp ret_val_get_sew_pow_1016 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1016, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1017; + x86::Gp ret_val_get_lmul_pow_1017 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1017, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1015, ret_val_get_sew_pow_1016), ret_val_get_lmul_pow_1017)), 3, true); + setArg(call_get_pow_1015, 0, reinterpret_cast(this)); + setArg(call_get_pow_1015, 1, EEW); + setRet(call_get_pow_1015, 0, ret_val_get_pow_1015); + setArg(call_get_sew_pow_1016, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1016, 0, ret_val_get_sew_pow_1016); + setArg(call_get_lmul_pow_1017, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1017, 0, ret_val_get_lmul_pow_1017); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1018; + auto illegal_load_1018_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1018 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1018, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1018; + setArg(call_illegal_load_1018, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1018, 1, vd); + setArg(call_illegal_load_1018, 2, vm); + setArg(call_illegal_load_1018, 3, 6); + setArg(call_illegal_load_1018, 4, EEW); + setArg(call_illegal_load_1018, 5, illegal_load_1018_arg4); + setRet(call_illegal_load_1018, 0, ret_val_illegal_load_1018); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1019; + auto vlseg_1019_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1019_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1019_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1019_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1019 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1019, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1019, 32, false); + setArg(call_vlseg_1019, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1019, 1, V); + setArg(call_vlseg_1019, 2, vlseg_1019_arg1); + setArg(call_vlseg_1019, 3, vlseg_1019_arg2); + setArg(call_vlseg_1019, 4, vlseg_1019_arg3); + setArg(call_vlseg_1019, 5, vm); + setArg(call_vlseg_1019, 6, vd); + setArg(call_vlseg_1019, 7, vlseg_1019_arg6); + setArg(call_vlseg_1019, 8, 0); + setArg(call_vlseg_1019, 9, 6); + setRet(call_vlseg_1019, 0, ret_val_vlseg_1019); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 311); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 312: VLSEG6E16FF__V */ + continuation_e __vlseg6e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 312); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1020; + x86::Gp ret_val_get_pow_1020 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1020, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1021; + x86::Gp ret_val_get_sew_pow_1021 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1021, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1022; + x86::Gp ret_val_get_lmul_pow_1022 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1022, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1020, ret_val_get_sew_pow_1021), ret_val_get_lmul_pow_1022)), 3, true); + setArg(call_get_pow_1020, 0, reinterpret_cast(this)); + setArg(call_get_pow_1020, 1, EEW); + setRet(call_get_pow_1020, 0, ret_val_get_pow_1020); + setArg(call_get_sew_pow_1021, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1021, 0, ret_val_get_sew_pow_1021); + setArg(call_get_lmul_pow_1022, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1022, 0, ret_val_get_lmul_pow_1022); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1023; + auto illegal_load_1023_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1023 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1023, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1023; + setArg(call_illegal_load_1023, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1023, 1, vd); + setArg(call_illegal_load_1023, 2, vm); + setArg(call_illegal_load_1023, 3, 6); + setArg(call_illegal_load_1023, 4, EEW); + setArg(call_illegal_load_1023, 5, illegal_load_1023_arg4); + setRet(call_illegal_load_1023, 0, ret_val_illegal_load_1023); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1024; + auto vlseg_1024_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1024_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1024_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1024_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1024 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1024, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1024, 32, false); + setArg(call_vlseg_1024, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1024, 1, V); + setArg(call_vlseg_1024, 2, vlseg_1024_arg1); + setArg(call_vlseg_1024, 3, vlseg_1024_arg2); + setArg(call_vlseg_1024, 4, vlseg_1024_arg3); + setArg(call_vlseg_1024, 5, vm); + setArg(call_vlseg_1024, 6, vd); + setArg(call_vlseg_1024, 7, vlseg_1024_arg6); + setArg(call_vlseg_1024, 8, 5); + setArg(call_vlseg_1024, 9, 6); + setRet(call_vlseg_1024, 0, ret_val_vlseg_1024); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 312); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 313: VLSEG6E32FF__V */ + continuation_e __vlseg6e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 313); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1025; + x86::Gp ret_val_get_pow_1025 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1025, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1026; + x86::Gp ret_val_get_sew_pow_1026 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1026, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1027; + x86::Gp ret_val_get_lmul_pow_1027 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1027, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1025, ret_val_get_sew_pow_1026), ret_val_get_lmul_pow_1027)), 3, true); + setArg(call_get_pow_1025, 0, reinterpret_cast(this)); + setArg(call_get_pow_1025, 1, EEW); + setRet(call_get_pow_1025, 0, ret_val_get_pow_1025); + setArg(call_get_sew_pow_1026, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1026, 0, ret_val_get_sew_pow_1026); + setArg(call_get_lmul_pow_1027, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1027, 0, ret_val_get_lmul_pow_1027); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1028; + auto illegal_load_1028_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1028 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1028, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1028; + setArg(call_illegal_load_1028, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1028, 1, vd); + setArg(call_illegal_load_1028, 2, vm); + setArg(call_illegal_load_1028, 3, 6); + setArg(call_illegal_load_1028, 4, EEW); + setArg(call_illegal_load_1028, 5, illegal_load_1028_arg4); + setRet(call_illegal_load_1028, 0, ret_val_illegal_load_1028); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1029; + auto vlseg_1029_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1029_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1029_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1029_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1029 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1029, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1029, 32, false); + setArg(call_vlseg_1029, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1029, 1, V); + setArg(call_vlseg_1029, 2, vlseg_1029_arg1); + setArg(call_vlseg_1029, 3, vlseg_1029_arg2); + setArg(call_vlseg_1029, 4, vlseg_1029_arg3); + setArg(call_vlseg_1029, 5, vm); + setArg(call_vlseg_1029, 6, vd); + setArg(call_vlseg_1029, 7, vlseg_1029_arg6); + setArg(call_vlseg_1029, 8, 6); + setArg(call_vlseg_1029, 9, 6); + setRet(call_vlseg_1029, 0, ret_val_vlseg_1029); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 313); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 314: VLSEG6E64FF__V */ + continuation_e __vlseg6e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 314); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1030; + x86::Gp ret_val_get_pow_1030 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1030, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1031; + x86::Gp ret_val_get_sew_pow_1031 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1031, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1032; + x86::Gp ret_val_get_lmul_pow_1032 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1032, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1030, ret_val_get_sew_pow_1031), ret_val_get_lmul_pow_1032)), 3, true); + setArg(call_get_pow_1030, 0, reinterpret_cast(this)); + setArg(call_get_pow_1030, 1, EEW); + setRet(call_get_pow_1030, 0, ret_val_get_pow_1030); + setArg(call_get_sew_pow_1031, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1031, 0, ret_val_get_sew_pow_1031); + setArg(call_get_lmul_pow_1032, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1032, 0, ret_val_get_lmul_pow_1032); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1033; + auto illegal_load_1033_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1033 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1033, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1033; + setArg(call_illegal_load_1033, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1033, 1, vd); + setArg(call_illegal_load_1033, 2, vm); + setArg(call_illegal_load_1033, 3, 6); + setArg(call_illegal_load_1033, 4, EEW); + setArg(call_illegal_load_1033, 5, illegal_load_1033_arg4); + setRet(call_illegal_load_1033, 0, ret_val_illegal_load_1033); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1034; + auto vlseg_1034_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1034_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1034_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1034_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1034 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1034, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1034, 32, false); + setArg(call_vlseg_1034, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1034, 1, V); + setArg(call_vlseg_1034, 2, vlseg_1034_arg1); + setArg(call_vlseg_1034, 3, vlseg_1034_arg2); + setArg(call_vlseg_1034, 4, vlseg_1034_arg3); + setArg(call_vlseg_1034, 5, vm); + setArg(call_vlseg_1034, 6, vd); + setArg(call_vlseg_1034, 7, vlseg_1034_arg6); + setArg(call_vlseg_1034, 8, 7); + setArg(call_vlseg_1034, 9, 6); + setRet(call_vlseg_1034, 0, ret_val_vlseg_1034); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 314); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 315: VLSEG7E8FF__V */ + continuation_e __vlseg7e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 315); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1035; + x86::Gp ret_val_get_pow_1035 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1035, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1036; + x86::Gp ret_val_get_sew_pow_1036 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1036, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1037; + x86::Gp ret_val_get_lmul_pow_1037 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1037, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1035, ret_val_get_sew_pow_1036), ret_val_get_lmul_pow_1037)), 3, true); + setArg(call_get_pow_1035, 0, reinterpret_cast(this)); + setArg(call_get_pow_1035, 1, EEW); + setRet(call_get_pow_1035, 0, ret_val_get_pow_1035); + setArg(call_get_sew_pow_1036, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1036, 0, ret_val_get_sew_pow_1036); + setArg(call_get_lmul_pow_1037, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1037, 0, ret_val_get_lmul_pow_1037); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1038; + auto illegal_load_1038_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1038 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1038, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1038; + setArg(call_illegal_load_1038, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1038, 1, vd); + setArg(call_illegal_load_1038, 2, vm); + setArg(call_illegal_load_1038, 3, 7); + setArg(call_illegal_load_1038, 4, EEW); + setArg(call_illegal_load_1038, 5, illegal_load_1038_arg4); + setRet(call_illegal_load_1038, 0, ret_val_illegal_load_1038); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1039; + auto vlseg_1039_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1039_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1039_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1039_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1039 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1039, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1039, 32, false); + setArg(call_vlseg_1039, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1039, 1, V); + setArg(call_vlseg_1039, 2, vlseg_1039_arg1); + setArg(call_vlseg_1039, 3, vlseg_1039_arg2); + setArg(call_vlseg_1039, 4, vlseg_1039_arg3); + setArg(call_vlseg_1039, 5, vm); + setArg(call_vlseg_1039, 6, vd); + setArg(call_vlseg_1039, 7, vlseg_1039_arg6); + setArg(call_vlseg_1039, 8, 0); + setArg(call_vlseg_1039, 9, 7); + setRet(call_vlseg_1039, 0, ret_val_vlseg_1039); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 315); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 316: VLSEG7E16FF__V */ + continuation_e __vlseg7e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 316); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1040; + x86::Gp ret_val_get_pow_1040 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1040, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1041; + x86::Gp ret_val_get_sew_pow_1041 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1041, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1042; + x86::Gp ret_val_get_lmul_pow_1042 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1042, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1040, ret_val_get_sew_pow_1041), ret_val_get_lmul_pow_1042)), 3, true); + setArg(call_get_pow_1040, 0, reinterpret_cast(this)); + setArg(call_get_pow_1040, 1, EEW); + setRet(call_get_pow_1040, 0, ret_val_get_pow_1040); + setArg(call_get_sew_pow_1041, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1041, 0, ret_val_get_sew_pow_1041); + setArg(call_get_lmul_pow_1042, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1042, 0, ret_val_get_lmul_pow_1042); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1043; + auto illegal_load_1043_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1043 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1043, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1043; + setArg(call_illegal_load_1043, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1043, 1, vd); + setArg(call_illegal_load_1043, 2, vm); + setArg(call_illegal_load_1043, 3, 7); + setArg(call_illegal_load_1043, 4, EEW); + setArg(call_illegal_load_1043, 5, illegal_load_1043_arg4); + setRet(call_illegal_load_1043, 0, ret_val_illegal_load_1043); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1044; + auto vlseg_1044_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1044_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1044_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1044_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1044 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1044, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1044, 32, false); + setArg(call_vlseg_1044, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1044, 1, V); + setArg(call_vlseg_1044, 2, vlseg_1044_arg1); + setArg(call_vlseg_1044, 3, vlseg_1044_arg2); + setArg(call_vlseg_1044, 4, vlseg_1044_arg3); + setArg(call_vlseg_1044, 5, vm); + setArg(call_vlseg_1044, 6, vd); + setArg(call_vlseg_1044, 7, vlseg_1044_arg6); + setArg(call_vlseg_1044, 8, 5); + setArg(call_vlseg_1044, 9, 7); + setRet(call_vlseg_1044, 0, ret_val_vlseg_1044); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 316); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 317: VLSEG7E32FF__V */ + continuation_e __vlseg7e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 317); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1045; + x86::Gp ret_val_get_pow_1045 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1045, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1046; + x86::Gp ret_val_get_sew_pow_1046 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1046, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1047; + x86::Gp ret_val_get_lmul_pow_1047 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1047, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1045, ret_val_get_sew_pow_1046), ret_val_get_lmul_pow_1047)), 3, true); + setArg(call_get_pow_1045, 0, reinterpret_cast(this)); + setArg(call_get_pow_1045, 1, EEW); + setRet(call_get_pow_1045, 0, ret_val_get_pow_1045); + setArg(call_get_sew_pow_1046, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1046, 0, ret_val_get_sew_pow_1046); + setArg(call_get_lmul_pow_1047, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1047, 0, ret_val_get_lmul_pow_1047); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1048; + auto illegal_load_1048_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1048 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1048, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1048; + setArg(call_illegal_load_1048, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1048, 1, vd); + setArg(call_illegal_load_1048, 2, vm); + setArg(call_illegal_load_1048, 3, 7); + setArg(call_illegal_load_1048, 4, EEW); + setArg(call_illegal_load_1048, 5, illegal_load_1048_arg4); + setRet(call_illegal_load_1048, 0, ret_val_illegal_load_1048); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1049; + auto vlseg_1049_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1049_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1049_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1049_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1049 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1049, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1049, 32, false); + setArg(call_vlseg_1049, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1049, 1, V); + setArg(call_vlseg_1049, 2, vlseg_1049_arg1); + setArg(call_vlseg_1049, 3, vlseg_1049_arg2); + setArg(call_vlseg_1049, 4, vlseg_1049_arg3); + setArg(call_vlseg_1049, 5, vm); + setArg(call_vlseg_1049, 6, vd); + setArg(call_vlseg_1049, 7, vlseg_1049_arg6); + setArg(call_vlseg_1049, 8, 6); + setArg(call_vlseg_1049, 9, 7); + setRet(call_vlseg_1049, 0, ret_val_vlseg_1049); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 317); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 318: VLSEG7E64FF__V */ + continuation_e __vlseg7e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 318); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1050; + x86::Gp ret_val_get_pow_1050 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1050, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1051; + x86::Gp ret_val_get_sew_pow_1051 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1051, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1052; + x86::Gp ret_val_get_lmul_pow_1052 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1052, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1050, ret_val_get_sew_pow_1051), ret_val_get_lmul_pow_1052)), 3, true); + setArg(call_get_pow_1050, 0, reinterpret_cast(this)); + setArg(call_get_pow_1050, 1, EEW); + setRet(call_get_pow_1050, 0, ret_val_get_pow_1050); + setArg(call_get_sew_pow_1051, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1051, 0, ret_val_get_sew_pow_1051); + setArg(call_get_lmul_pow_1052, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1052, 0, ret_val_get_lmul_pow_1052); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1053; + auto illegal_load_1053_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1053 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1053, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1053; + setArg(call_illegal_load_1053, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1053, 1, vd); + setArg(call_illegal_load_1053, 2, vm); + setArg(call_illegal_load_1053, 3, 7); + setArg(call_illegal_load_1053, 4, EEW); + setArg(call_illegal_load_1053, 5, illegal_load_1053_arg4); + setRet(call_illegal_load_1053, 0, ret_val_illegal_load_1053); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1054; + auto vlseg_1054_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1054_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1054_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1054_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1054 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1054, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1054, 32, false); + setArg(call_vlseg_1054, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1054, 1, V); + setArg(call_vlseg_1054, 2, vlseg_1054_arg1); + setArg(call_vlseg_1054, 3, vlseg_1054_arg2); + setArg(call_vlseg_1054, 4, vlseg_1054_arg3); + setArg(call_vlseg_1054, 5, vm); + setArg(call_vlseg_1054, 6, vd); + setArg(call_vlseg_1054, 7, vlseg_1054_arg6); + setArg(call_vlseg_1054, 8, 7); + setArg(call_vlseg_1054, 9, 7); + setRet(call_vlseg_1054, 0, ret_val_vlseg_1054); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 318); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 319: VLSEG8E8FF__V */ + continuation_e __vlseg8e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 319); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1055; + x86::Gp ret_val_get_pow_1055 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1055, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1056; + x86::Gp ret_val_get_sew_pow_1056 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1056, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1057; + x86::Gp ret_val_get_lmul_pow_1057 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1057, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1055, ret_val_get_sew_pow_1056), ret_val_get_lmul_pow_1057)), 3, true); + setArg(call_get_pow_1055, 0, reinterpret_cast(this)); + setArg(call_get_pow_1055, 1, EEW); + setRet(call_get_pow_1055, 0, ret_val_get_pow_1055); + setArg(call_get_sew_pow_1056, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1056, 0, ret_val_get_sew_pow_1056); + setArg(call_get_lmul_pow_1057, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1057, 0, ret_val_get_lmul_pow_1057); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1058; + auto illegal_load_1058_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1058 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1058, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1058; + setArg(call_illegal_load_1058, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1058, 1, vd); + setArg(call_illegal_load_1058, 2, vm); + setArg(call_illegal_load_1058, 3, 8); + setArg(call_illegal_load_1058, 4, EEW); + setArg(call_illegal_load_1058, 5, illegal_load_1058_arg4); + setRet(call_illegal_load_1058, 0, ret_val_illegal_load_1058); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1059; + auto vlseg_1059_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1059_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1059_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1059_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1059 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1059, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1059, 32, false); + setArg(call_vlseg_1059, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1059, 1, V); + setArg(call_vlseg_1059, 2, vlseg_1059_arg1); + setArg(call_vlseg_1059, 3, vlseg_1059_arg2); + setArg(call_vlseg_1059, 4, vlseg_1059_arg3); + setArg(call_vlseg_1059, 5, vm); + setArg(call_vlseg_1059, 6, vd); + setArg(call_vlseg_1059, 7, vlseg_1059_arg6); + setArg(call_vlseg_1059, 8, 0); + setArg(call_vlseg_1059, 9, 8); + setRet(call_vlseg_1059, 0, ret_val_vlseg_1059); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 319); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 320: VLSEG8E16FF__V */ + continuation_e __vlseg8e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 320); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1060; + x86::Gp ret_val_get_pow_1060 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1060, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1061; + x86::Gp ret_val_get_sew_pow_1061 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1061, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1062; + x86::Gp ret_val_get_lmul_pow_1062 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1062, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1060, ret_val_get_sew_pow_1061), ret_val_get_lmul_pow_1062)), 3, true); + setArg(call_get_pow_1060, 0, reinterpret_cast(this)); + setArg(call_get_pow_1060, 1, EEW); + setRet(call_get_pow_1060, 0, ret_val_get_pow_1060); + setArg(call_get_sew_pow_1061, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1061, 0, ret_val_get_sew_pow_1061); + setArg(call_get_lmul_pow_1062, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1062, 0, ret_val_get_lmul_pow_1062); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1063; + auto illegal_load_1063_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1063 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1063, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1063; + setArg(call_illegal_load_1063, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1063, 1, vd); + setArg(call_illegal_load_1063, 2, vm); + setArg(call_illegal_load_1063, 3, 8); + setArg(call_illegal_load_1063, 4, EEW); + setArg(call_illegal_load_1063, 5, illegal_load_1063_arg4); + setRet(call_illegal_load_1063, 0, ret_val_illegal_load_1063); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1064; + auto vlseg_1064_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1064_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1064_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1064_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1064 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1064, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1064, 32, false); + setArg(call_vlseg_1064, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1064, 1, V); + setArg(call_vlseg_1064, 2, vlseg_1064_arg1); + setArg(call_vlseg_1064, 3, vlseg_1064_arg2); + setArg(call_vlseg_1064, 4, vlseg_1064_arg3); + setArg(call_vlseg_1064, 5, vm); + setArg(call_vlseg_1064, 6, vd); + setArg(call_vlseg_1064, 7, vlseg_1064_arg6); + setArg(call_vlseg_1064, 8, 5); + setArg(call_vlseg_1064, 9, 8); + setRet(call_vlseg_1064, 0, ret_val_vlseg_1064); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 320); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 321: VLSEG8E32FF__V */ + continuation_e __vlseg8e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 321); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1065; + x86::Gp ret_val_get_pow_1065 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1065, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1066; + x86::Gp ret_val_get_sew_pow_1066 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1066, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1067; + x86::Gp ret_val_get_lmul_pow_1067 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1067, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1065, ret_val_get_sew_pow_1066), ret_val_get_lmul_pow_1067)), 3, true); + setArg(call_get_pow_1065, 0, reinterpret_cast(this)); + setArg(call_get_pow_1065, 1, EEW); + setRet(call_get_pow_1065, 0, ret_val_get_pow_1065); + setArg(call_get_sew_pow_1066, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1066, 0, ret_val_get_sew_pow_1066); + setArg(call_get_lmul_pow_1067, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1067, 0, ret_val_get_lmul_pow_1067); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1068; + auto illegal_load_1068_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1068 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1068, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1068; + setArg(call_illegal_load_1068, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1068, 1, vd); + setArg(call_illegal_load_1068, 2, vm); + setArg(call_illegal_load_1068, 3, 8); + setArg(call_illegal_load_1068, 4, EEW); + setArg(call_illegal_load_1068, 5, illegal_load_1068_arg4); + setRet(call_illegal_load_1068, 0, ret_val_illegal_load_1068); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1069; + auto vlseg_1069_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1069_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1069_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1069_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1069 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1069, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1069, 32, false); + setArg(call_vlseg_1069, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1069, 1, V); + setArg(call_vlseg_1069, 2, vlseg_1069_arg1); + setArg(call_vlseg_1069, 3, vlseg_1069_arg2); + setArg(call_vlseg_1069, 4, vlseg_1069_arg3); + setArg(call_vlseg_1069, 5, vm); + setArg(call_vlseg_1069, 6, vd); + setArg(call_vlseg_1069, 7, vlseg_1069_arg6); + setArg(call_vlseg_1069, 8, 6); + setArg(call_vlseg_1069, 9, 8); + setRet(call_vlseg_1069, 0, ret_val_vlseg_1069); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 321); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 322: VLSEG8E64FF__V */ + continuation_e __vlseg8e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 322); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1070; + x86::Gp ret_val_get_pow_1070 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1070, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1071; + x86::Gp ret_val_get_sew_pow_1071 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1071, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1072; + x86::Gp ret_val_get_lmul_pow_1072 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1072, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1070, ret_val_get_sew_pow_1071), ret_val_get_lmul_pow_1072)), 3, true); + setArg(call_get_pow_1070, 0, reinterpret_cast(this)); + setArg(call_get_pow_1070, 1, EEW); + setRet(call_get_pow_1070, 0, ret_val_get_pow_1070); + setArg(call_get_sew_pow_1071, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1071, 0, ret_val_get_sew_pow_1071); + setArg(call_get_lmul_pow_1072, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1072, 0, ret_val_get_lmul_pow_1072); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1073; + auto illegal_load_1073_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1073 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1073, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1073; + setArg(call_illegal_load_1073, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1073, 1, vd); + setArg(call_illegal_load_1073, 2, vm); + setArg(call_illegal_load_1073, 3, 8); + setArg(call_illegal_load_1073, 4, EEW); + setArg(call_illegal_load_1073, 5, illegal_load_1073_arg4); + setRet(call_illegal_load_1073, 0, ret_val_illegal_load_1073); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1074; + auto vlseg_1074_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1074_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1074_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1074_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1074 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1074, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1074, 32, false); + setArg(call_vlseg_1074, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1074, 1, V); + setArg(call_vlseg_1074, 2, vlseg_1074_arg1); + setArg(call_vlseg_1074, 3, vlseg_1074_arg2); + setArg(call_vlseg_1074, 4, vlseg_1074_arg3); + setArg(call_vlseg_1074, 5, vm); + setArg(call_vlseg_1074, 6, vd); + setArg(call_vlseg_1074, 7, vlseg_1074_arg6); + setArg(call_vlseg_1074, 8, 7); + setArg(call_vlseg_1074, 9, 8); + setRet(call_vlseg_1074, 0, ret_val_vlseg_1074); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 32, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 322); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 323: VSM__V */ + continuation_e __vsm__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {vs3}", fmt::arg("mnemonic", "vsm.v"), + fmt::arg("rs1", name(rs1)), fmt::arg("vs3", vname(vs3))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSM__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 323); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto label_then1075 = cc.newLabel(); + auto label_merge1075 = cc.newLabel(); + auto tmp_reg1075 = get_reg_Gp(cc, 32, false); + cmp(cc, gen_operation(cc, urem, load_reg_from_mem(jh, traits::vl), 8), 0); + cc.je(label_then1075); + mov(cc, tmp_reg1075,gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, udiv, load_reg_from_mem(jh, traits::vl), 8), 1)), 32, false)); + cc.jmp(label_merge1075); + cc.bind(label_then1075); + mov(cc, tmp_reg1075, gen_operation(cc, udiv, load_reg_from_mem(jh, traits::vl), 8)); + cc.bind(label_merge1075); + auto evl = tmp_reg1075 + ; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_1076; + x86::Gp ret_val_illegal_vd_unmasked_1076 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_1076, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_1076; + setArg(call_illegal_vd_unmasked_1076, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_1076, 0, ret_val_illegal_vd_unmasked_1076); + cmp(cc, cond, 0); + cc.je(label_merge); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.bind(label_merge); + } + auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 7, static_cast(traits::XLEN)-1-7+1), 32, false), 7), gen_operation(cc, shl, gen_ext(cc, 1, 32, false), 6)), gen_operation(cc, shl, gen_ext(cc, 0, 32, false), 3)), gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 0, 2-0+1), 32, false)); + InvokeNode* call_vsseg_1077; + auto vsseg_1077_arg1 = evl; + auto vsseg_1077_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_1077_arg3 = _vtype; + auto vsseg_1077_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_1077 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_1077, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_1077, 32, false), traits::vstart); + setArg(call_vsseg_1077, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_1077, 1, V); + setArg(call_vsseg_1077, 2, vsseg_1077_arg1); + setArg(call_vsseg_1077, 3, vsseg_1077_arg2); + setArg(call_vsseg_1077, 4, vsseg_1077_arg3); + setArg(call_vsseg_1077, 5, 1); + setArg(call_vsseg_1077, 6, vs3); + setArg(call_vsseg_1077, 7, vsseg_1077_arg6); + setArg(call_vsseg_1077, 8, 0); + setArg(call_vsseg_1077, 9, 1); + setRet(call_vsseg_1077, 0, ret_val_vsseg_1077); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 323); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 324: VLM__V */ + continuation_e __vlm__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {vd}", fmt::arg("mnemonic", "vlm.v"), + fmt::arg("rs1", name(rs1)), fmt::arg("vd", vname(vd))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLM__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 324); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto label_then1078 = cc.newLabel(); + auto label_merge1078 = cc.newLabel(); + auto tmp_reg1078 = get_reg_Gp(cc, 32, false); + cmp(cc, gen_operation(cc, urem, load_reg_from_mem(jh, traits::vl), 8), 0); + cc.je(label_then1078); + mov(cc, tmp_reg1078,gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, udiv, load_reg_from_mem(jh, traits::vl), 8), 1)), 32, false)); + cc.jmp(label_merge1078); + cc.bind(label_then1078); + mov(cc, tmp_reg1078, gen_operation(cc, udiv, load_reg_from_mem(jh, traits::vl), 8)); + cc.bind(label_merge1078); + auto evl = tmp_reg1078 + ; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_1079; + x86::Gp ret_val_illegal_vd_unmasked_1079 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_1079, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_1079; + setArg(call_illegal_vd_unmasked_1079, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_1079, 0, ret_val_illegal_vd_unmasked_1079); + cmp(cc, cond, 0); + cc.je(label_merge); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.bind(label_merge); + } + auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 7, static_cast(traits::XLEN)-1-7+1), 32, false), 7), gen_operation(cc, shl, gen_ext(cc, 1, 32, false), 6)), gen_operation(cc, shl, gen_ext(cc, 0, 32, false), 3)), gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 0, 2-0+1), 32, false)); + InvokeNode* call_vlseg_1080; + auto vlseg_1080_arg1 = evl; + auto vlseg_1080_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1080_arg3 = _vtype; + auto vlseg_1080_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1080 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1080, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1080, 32, false), traits::vstart); + setArg(call_vlseg_1080, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1080, 1, V); + setArg(call_vlseg_1080, 2, vlseg_1080_arg1); + setArg(call_vlseg_1080, 3, vlseg_1080_arg2); + setArg(call_vlseg_1080, 4, vlseg_1080_arg3); + setArg(call_vlseg_1080, 5, 1); + setArg(call_vlseg_1080, 6, vd); + setArg(call_vlseg_1080, 7, vlseg_1080_arg6); + setArg(call_vlseg_1080, 8, 0); + setArg(call_vlseg_1080, 9, 1); + setRet(call_vlseg_1080, 0, ret_val_vlseg_1080); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 324); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 325: VL1RE8__V */ + continuation_e __vl1re8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL1RE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 325); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(1*static_cast(traits::VLEN)/8); + { + auto label_merge = cc.newLabel(); + auto tmp1081 = get_reg(cc, 32, false); + mov(cc, tmp1081, evl); + auto cond = gen_operation(cc, gtu, tmp1081, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1082; + auto vlseg_1082_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1082_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1082_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1082 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1082, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1082, 32, false), traits::vstart); + setArg(call_vlseg_1082, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1082, 1, V); + setArg(call_vlseg_1082, 2, evl); + setArg(call_vlseg_1082, 3, vlseg_1082_arg2); + setArg(call_vlseg_1082, 4, vlseg_1082_arg3); + setArg(call_vlseg_1082, 5, 1); + setArg(call_vlseg_1082, 6, vd); + setArg(call_vlseg_1082, 7, vlseg_1082_arg6); + setArg(call_vlseg_1082, 8, 0); + setArg(call_vlseg_1082, 9, 1); + setRet(call_vlseg_1082, 0, ret_val_vlseg_1082); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 325); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 326: VL1RE16__V */ + continuation_e __vl1re16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL1RE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 326); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(1*static_cast(traits::VLEN)/16); + { + auto label_merge = cc.newLabel(); + auto tmp1083 = get_reg(cc, 32, false); + mov(cc, tmp1083, evl); + auto cond = gen_operation(cc, gtu, tmp1083, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1084; + auto vlseg_1084_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1084_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1084_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1084 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1084, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1084, 32, false), traits::vstart); + setArg(call_vlseg_1084, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1084, 1, V); + setArg(call_vlseg_1084, 2, evl); + setArg(call_vlseg_1084, 3, vlseg_1084_arg2); + setArg(call_vlseg_1084, 4, vlseg_1084_arg3); + setArg(call_vlseg_1084, 5, 1); + setArg(call_vlseg_1084, 6, vd); + setArg(call_vlseg_1084, 7, vlseg_1084_arg6); + setArg(call_vlseg_1084, 8, 5); + setArg(call_vlseg_1084, 9, 1); + setRet(call_vlseg_1084, 0, ret_val_vlseg_1084); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 326); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 327: VL1RE32__V */ + continuation_e __vl1re32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL1RE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 327); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(1*static_cast(traits::VLEN)/32); + { + auto label_merge = cc.newLabel(); + auto tmp1085 = get_reg(cc, 32, false); + mov(cc, tmp1085, evl); + auto cond = gen_operation(cc, gtu, tmp1085, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1086; + auto vlseg_1086_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1086_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1086_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1086 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1086, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1086, 32, false), traits::vstart); + setArg(call_vlseg_1086, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1086, 1, V); + setArg(call_vlseg_1086, 2, evl); + setArg(call_vlseg_1086, 3, vlseg_1086_arg2); + setArg(call_vlseg_1086, 4, vlseg_1086_arg3); + setArg(call_vlseg_1086, 5, 1); + setArg(call_vlseg_1086, 6, vd); + setArg(call_vlseg_1086, 7, vlseg_1086_arg6); + setArg(call_vlseg_1086, 8, 6); + setArg(call_vlseg_1086, 9, 1); + setRet(call_vlseg_1086, 0, ret_val_vlseg_1086); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 327); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 328: VL1RE64__V */ + continuation_e __vl1re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL1RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 328); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(1*static_cast(traits::VLEN)/64); + { + auto label_merge = cc.newLabel(); + auto tmp1087 = get_reg(cc, 32, false); + mov(cc, tmp1087, evl); + auto cond = gen_operation(cc, gtu, tmp1087, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1088; + auto vlseg_1088_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1088_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1088_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1088 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1088, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1088, 32, false), traits::vstart); + setArg(call_vlseg_1088, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1088, 1, V); + setArg(call_vlseg_1088, 2, evl); + setArg(call_vlseg_1088, 3, vlseg_1088_arg2); + setArg(call_vlseg_1088, 4, vlseg_1088_arg3); + setArg(call_vlseg_1088, 5, 1); + setArg(call_vlseg_1088, 6, vd); + setArg(call_vlseg_1088, 7, vlseg_1088_arg6); + setArg(call_vlseg_1088, 8, 7); + setArg(call_vlseg_1088, 9, 1); + setRet(call_vlseg_1088, 0, ret_val_vlseg_1088); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 328); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 329: VL2RE8__V */ + continuation_e __vl2re8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL2RE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 329); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(2*static_cast(traits::VLEN)/8); + if(vd%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1089 = get_reg(cc, 32, false); + mov(cc, tmp1089, evl); + auto cond = gen_operation(cc, gtu, tmp1089, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1090; + auto vlseg_1090_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1090_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1090_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1090 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1090, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1090, 32, false), traits::vstart); + setArg(call_vlseg_1090, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1090, 1, V); + setArg(call_vlseg_1090, 2, evl); + setArg(call_vlseg_1090, 3, vlseg_1090_arg2); + setArg(call_vlseg_1090, 4, vlseg_1090_arg3); + setArg(call_vlseg_1090, 5, 1); + setArg(call_vlseg_1090, 6, vd); + setArg(call_vlseg_1090, 7, vlseg_1090_arg6); + setArg(call_vlseg_1090, 8, 0); + setArg(call_vlseg_1090, 9, 1); + setRet(call_vlseg_1090, 0, ret_val_vlseg_1090); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 329); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 330: VL2RE16__V */ + continuation_e __vl2re16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL2RE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 330); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(2*static_cast(traits::VLEN)/16); + if(vd%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1091 = get_reg(cc, 32, false); + mov(cc, tmp1091, evl); + auto cond = gen_operation(cc, gtu, tmp1091, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1092; + auto vlseg_1092_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1092_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1092_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1092 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1092, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1092, 32, false), traits::vstart); + setArg(call_vlseg_1092, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1092, 1, V); + setArg(call_vlseg_1092, 2, evl); + setArg(call_vlseg_1092, 3, vlseg_1092_arg2); + setArg(call_vlseg_1092, 4, vlseg_1092_arg3); + setArg(call_vlseg_1092, 5, 1); + setArg(call_vlseg_1092, 6, vd); + setArg(call_vlseg_1092, 7, vlseg_1092_arg6); + setArg(call_vlseg_1092, 8, 5); + setArg(call_vlseg_1092, 9, 1); + setRet(call_vlseg_1092, 0, ret_val_vlseg_1092); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 330); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 331: VL2RE32__V */ + continuation_e __vl2re32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL2RE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 331); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(2*static_cast(traits::VLEN)/32); + if(vd%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1093 = get_reg(cc, 32, false); + mov(cc, tmp1093, evl); + auto cond = gen_operation(cc, gtu, tmp1093, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1094; + auto vlseg_1094_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1094_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1094_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1094 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1094, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1094, 32, false), traits::vstart); + setArg(call_vlseg_1094, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1094, 1, V); + setArg(call_vlseg_1094, 2, evl); + setArg(call_vlseg_1094, 3, vlseg_1094_arg2); + setArg(call_vlseg_1094, 4, vlseg_1094_arg3); + setArg(call_vlseg_1094, 5, 1); + setArg(call_vlseg_1094, 6, vd); + setArg(call_vlseg_1094, 7, vlseg_1094_arg6); + setArg(call_vlseg_1094, 8, 6); + setArg(call_vlseg_1094, 9, 1); + setRet(call_vlseg_1094, 0, ret_val_vlseg_1094); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 331); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 332: VL2RE64__V */ + continuation_e __vl2re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL2RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 332); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(2*static_cast(traits::VLEN)/64); + if(vd%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1095 = get_reg(cc, 32, false); + mov(cc, tmp1095, evl); + auto cond = gen_operation(cc, gtu, tmp1095, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1096; + auto vlseg_1096_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1096_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1096_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1096 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1096, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1096, 32, false), traits::vstart); + setArg(call_vlseg_1096, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1096, 1, V); + setArg(call_vlseg_1096, 2, evl); + setArg(call_vlseg_1096, 3, vlseg_1096_arg2); + setArg(call_vlseg_1096, 4, vlseg_1096_arg3); + setArg(call_vlseg_1096, 5, 1); + setArg(call_vlseg_1096, 6, vd); + setArg(call_vlseg_1096, 7, vlseg_1096_arg6); + setArg(call_vlseg_1096, 8, 7); + setArg(call_vlseg_1096, 9, 1); + setRet(call_vlseg_1096, 0, ret_val_vlseg_1096); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 332); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 333: VL4RE8__V */ + continuation_e __vl4re8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL4RE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 333); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(4*static_cast(traits::VLEN)/8); + if(vd%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1097 = get_reg(cc, 32, false); + mov(cc, tmp1097, evl); + auto cond = gen_operation(cc, gtu, tmp1097, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1098; + auto vlseg_1098_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1098_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1098_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1098 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1098, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1098, 32, false), traits::vstart); + setArg(call_vlseg_1098, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1098, 1, V); + setArg(call_vlseg_1098, 2, evl); + setArg(call_vlseg_1098, 3, vlseg_1098_arg2); + setArg(call_vlseg_1098, 4, vlseg_1098_arg3); + setArg(call_vlseg_1098, 5, 1); + setArg(call_vlseg_1098, 6, vd); + setArg(call_vlseg_1098, 7, vlseg_1098_arg6); + setArg(call_vlseg_1098, 8, 0); + setArg(call_vlseg_1098, 9, 1); + setRet(call_vlseg_1098, 0, ret_val_vlseg_1098); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 333); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 334: VL4RE16__V */ + continuation_e __vl4re16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL4RE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 334); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(4*static_cast(traits::VLEN)/16); + if(vd%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1099 = get_reg(cc, 32, false); + mov(cc, tmp1099, evl); + auto cond = gen_operation(cc, gtu, tmp1099, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1100; + auto vlseg_1100_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1100_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1100_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1100 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1100, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1100, 32, false), traits::vstart); + setArg(call_vlseg_1100, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1100, 1, V); + setArg(call_vlseg_1100, 2, evl); + setArg(call_vlseg_1100, 3, vlseg_1100_arg2); + setArg(call_vlseg_1100, 4, vlseg_1100_arg3); + setArg(call_vlseg_1100, 5, 1); + setArg(call_vlseg_1100, 6, vd); + setArg(call_vlseg_1100, 7, vlseg_1100_arg6); + setArg(call_vlseg_1100, 8, 5); + setArg(call_vlseg_1100, 9, 1); + setRet(call_vlseg_1100, 0, ret_val_vlseg_1100); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 334); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 335: VL4RE32__V */ + continuation_e __vl4re32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL4RE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 335); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(4*static_cast(traits::VLEN)/32); + if(vd%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1101 = get_reg(cc, 32, false); + mov(cc, tmp1101, evl); + auto cond = gen_operation(cc, gtu, tmp1101, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1102; + auto vlseg_1102_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1102_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1102_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1102 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1102, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1102, 32, false), traits::vstart); + setArg(call_vlseg_1102, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1102, 1, V); + setArg(call_vlseg_1102, 2, evl); + setArg(call_vlseg_1102, 3, vlseg_1102_arg2); + setArg(call_vlseg_1102, 4, vlseg_1102_arg3); + setArg(call_vlseg_1102, 5, 1); + setArg(call_vlseg_1102, 6, vd); + setArg(call_vlseg_1102, 7, vlseg_1102_arg6); + setArg(call_vlseg_1102, 8, 6); + setArg(call_vlseg_1102, 9, 1); + setRet(call_vlseg_1102, 0, ret_val_vlseg_1102); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 335); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 336: VL4RE64__V */ + continuation_e __vl4re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL4RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 336); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(4*static_cast(traits::VLEN)/64); + if(vd%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1103 = get_reg(cc, 32, false); + mov(cc, tmp1103, evl); + auto cond = gen_operation(cc, gtu, tmp1103, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1104; + auto vlseg_1104_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1104_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1104_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1104 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1104, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1104, 32, false), traits::vstart); + setArg(call_vlseg_1104, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1104, 1, V); + setArg(call_vlseg_1104, 2, evl); + setArg(call_vlseg_1104, 3, vlseg_1104_arg2); + setArg(call_vlseg_1104, 4, vlseg_1104_arg3); + setArg(call_vlseg_1104, 5, 1); + setArg(call_vlseg_1104, 6, vd); + setArg(call_vlseg_1104, 7, vlseg_1104_arg6); + setArg(call_vlseg_1104, 8, 7); + setArg(call_vlseg_1104, 9, 1); + setRet(call_vlseg_1104, 0, ret_val_vlseg_1104); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 336); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 337: VL8RE8__V */ + continuation_e __vl8re8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL8RE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 337); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(8*static_cast(traits::VLEN)/8); + if(vd%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1105 = get_reg(cc, 32, false); + mov(cc, tmp1105, evl); + auto cond = gen_operation(cc, gtu, tmp1105, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1106; + auto vlseg_1106_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1106_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1106_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1106 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1106, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1106, 32, false), traits::vstart); + setArg(call_vlseg_1106, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1106, 1, V); + setArg(call_vlseg_1106, 2, evl); + setArg(call_vlseg_1106, 3, vlseg_1106_arg2); + setArg(call_vlseg_1106, 4, vlseg_1106_arg3); + setArg(call_vlseg_1106, 5, 1); + setArg(call_vlseg_1106, 6, vd); + setArg(call_vlseg_1106, 7, vlseg_1106_arg6); + setArg(call_vlseg_1106, 8, 0); + setArg(call_vlseg_1106, 9, 1); + setRet(call_vlseg_1106, 0, ret_val_vlseg_1106); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 337); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 338: VL8RE16__V */ + continuation_e __vl8re16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL8RE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 338); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(8*static_cast(traits::VLEN)/16); + if(vd%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1107 = get_reg(cc, 32, false); + mov(cc, tmp1107, evl); + auto cond = gen_operation(cc, gtu, tmp1107, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1108; + auto vlseg_1108_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1108_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1108_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1108 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1108, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1108, 32, false), traits::vstart); + setArg(call_vlseg_1108, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1108, 1, V); + setArg(call_vlseg_1108, 2, evl); + setArg(call_vlseg_1108, 3, vlseg_1108_arg2); + setArg(call_vlseg_1108, 4, vlseg_1108_arg3); + setArg(call_vlseg_1108, 5, 1); + setArg(call_vlseg_1108, 6, vd); + setArg(call_vlseg_1108, 7, vlseg_1108_arg6); + setArg(call_vlseg_1108, 8, 5); + setArg(call_vlseg_1108, 9, 1); + setRet(call_vlseg_1108, 0, ret_val_vlseg_1108); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 338); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 339: VL8RE32__V */ + continuation_e __vl8re32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL8RE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 339); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(8*static_cast(traits::VLEN)/32); + if(vd%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1109 = get_reg(cc, 32, false); + mov(cc, tmp1109, evl); + auto cond = gen_operation(cc, gtu, tmp1109, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1110; + auto vlseg_1110_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1110_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1110_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1110 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1110, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1110, 32, false), traits::vstart); + setArg(call_vlseg_1110, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1110, 1, V); + setArg(call_vlseg_1110, 2, evl); + setArg(call_vlseg_1110, 3, vlseg_1110_arg2); + setArg(call_vlseg_1110, 4, vlseg_1110_arg3); + setArg(call_vlseg_1110, 5, 1); + setArg(call_vlseg_1110, 6, vd); + setArg(call_vlseg_1110, 7, vlseg_1110_arg6); + setArg(call_vlseg_1110, 8, 6); + setArg(call_vlseg_1110, 9, 1); + setRet(call_vlseg_1110, 0, ret_val_vlseg_1110); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 339); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 340: VL8RE64__V */ + continuation_e __vl8re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL8RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 340); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(8*static_cast(traits::VLEN)/64); + if(vd%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1111 = get_reg(cc, 32, false); + mov(cc, tmp1111, evl); + auto cond = gen_operation(cc, gtu, tmp1111, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1112; + auto vlseg_1112_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1112_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1112_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1112 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1112, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1112, 32, false), traits::vstart); + setArg(call_vlseg_1112, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1112, 1, V); + setArg(call_vlseg_1112, 2, evl); + setArg(call_vlseg_1112, 3, vlseg_1112_arg2); + setArg(call_vlseg_1112, 4, vlseg_1112_arg3); + setArg(call_vlseg_1112, 5, 1); + setArg(call_vlseg_1112, 6, vd); + setArg(call_vlseg_1112, 7, vlseg_1112_arg6); + setArg(call_vlseg_1112, 8, 7); + setArg(call_vlseg_1112, 9, 1); + setRet(call_vlseg_1112, 0, ret_val_vlseg_1112); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 340); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 341: VS1RE64__V */ + continuation_e __vs1re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs1re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VS1RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 341); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(1*static_cast(traits::VLEN)/8); + { + auto label_merge = cc.newLabel(); + auto tmp1113 = get_reg(cc, 32, false); + mov(cc, tmp1113, evl); + auto cond = gen_operation(cc, gtu, tmp1113, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_1114; + auto vsseg_1114_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_1114_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_1114_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_1114 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_1114, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_1114, 32, false), traits::vstart); + setArg(call_vsseg_1114, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_1114, 1, V); + setArg(call_vsseg_1114, 2, evl); + setArg(call_vsseg_1114, 3, vsseg_1114_arg2); + setArg(call_vsseg_1114, 4, vsseg_1114_arg3); + setArg(call_vsseg_1114, 5, 1); + setArg(call_vsseg_1114, 6, vs3); + setArg(call_vsseg_1114, 7, vsseg_1114_arg6); + setArg(call_vsseg_1114, 8, 0); + setArg(call_vsseg_1114, 9, 1); + setRet(call_vsseg_1114, 0, ret_val_vsseg_1114); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 341); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 342: VS2RE64__V */ + continuation_e __vs2re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs2re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VS2RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 342); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(2*static_cast(traits::VLEN)/8); + if(vs3%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1115 = get_reg(cc, 32, false); + mov(cc, tmp1115, evl); + auto cond = gen_operation(cc, gtu, tmp1115, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_1116; + auto vsseg_1116_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_1116_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_1116_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_1116 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_1116, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_1116, 32, false), traits::vstart); + setArg(call_vsseg_1116, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_1116, 1, V); + setArg(call_vsseg_1116, 2, evl); + setArg(call_vsseg_1116, 3, vsseg_1116_arg2); + setArg(call_vsseg_1116, 4, vsseg_1116_arg3); + setArg(call_vsseg_1116, 5, 1); + setArg(call_vsseg_1116, 6, vs3); + setArg(call_vsseg_1116, 7, vsseg_1116_arg6); + setArg(call_vsseg_1116, 8, 0); + setArg(call_vsseg_1116, 9, 1); + setRet(call_vsseg_1116, 0, ret_val_vsseg_1116); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 342); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 343: VS4RE64__V */ + continuation_e __vs4re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs4re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VS4RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 343); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(4*static_cast(traits::VLEN)/8); + if(vs3%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1117 = get_reg(cc, 32, false); + mov(cc, tmp1117, evl); + auto cond = gen_operation(cc, gtu, tmp1117, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_1118; + auto vsseg_1118_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_1118_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_1118_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_1118 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_1118, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_1118, 32, false), traits::vstart); + setArg(call_vsseg_1118, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_1118, 1, V); + setArg(call_vsseg_1118, 2, evl); + setArg(call_vsseg_1118, 3, vsseg_1118_arg2); + setArg(call_vsseg_1118, 4, vsseg_1118_arg3); + setArg(call_vsseg_1118, 5, 1); + setArg(call_vsseg_1118, 6, vs3); + setArg(call_vsseg_1118, 7, vsseg_1118_arg6); + setArg(call_vsseg_1118, 8, 0); + setArg(call_vsseg_1118, 9, 1); + setRet(call_vsseg_1118, 0, ret_val_vsseg_1118); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 343); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 344: VS8RE64__V */ + continuation_e __vs8re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs8re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VS8RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 344); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint32_t)(8*static_cast(traits::VLEN)/8); + if(vs3%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1119 = get_reg(cc, 32, false); + mov(cc, tmp1119, evl); + auto cond = gen_operation(cc, gtu, tmp1119, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_1120; + auto vsseg_1120_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_1120_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_1120_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_1120 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_1120, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_1120, 32, false), traits::vstart); + setArg(call_vsseg_1120, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_1120, 1, V); + setArg(call_vsseg_1120, 2, evl); + setArg(call_vsseg_1120, 3, vsseg_1120_arg2); + setArg(call_vsseg_1120, 4, vsseg_1120_arg3); + setArg(call_vsseg_1120, 5, 1); + setArg(call_vsseg_1120, 6, vs3); + setArg(call_vsseg_1120, 7, vsseg_1120_arg6); + setArg(call_vsseg_1120, 8, 0); + setArg(call_vsseg_1120, 9, 1); + setRet(call_vsseg_1120, 0, ret_val_vsseg_1120); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 344); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 345: VLOXEI8__V */ + continuation_e __vloxei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXEI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 345); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1121; + x86::Gp ret_val_get_pow_1121 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1121, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1122; + x86::Gp ret_val_get_sew_pow_1122 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1122, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1123; + x86::Gp ret_val_get_lmul_pow_1123 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1123, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1121, ret_val_get_sew_pow_1122), ret_val_get_lmul_pow_1123)), 3, true); + setArg(call_get_pow_1121, 0, reinterpret_cast(this)); + setArg(call_get_pow_1121, 1, EEW); + setRet(call_get_pow_1121, 0, ret_val_get_pow_1121); + setArg(call_get_sew_pow_1122, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1122, 0, ret_val_get_sew_pow_1122); + setArg(call_get_lmul_pow_1123, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1123, 0, ret_val_get_lmul_pow_1123); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1125; + x86::Gp ret_val_get_lmul_pow_1125 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1125, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1124; + auto illegal_indexed_load_1124_arg4 = EMUL_pow; + auto illegal_indexed_load_1124_arg5 = ret_val_get_lmul_pow_1125; + x86::Gp ret_val_illegal_indexed_load_1124 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1124, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1124; + setArg(call_get_lmul_pow_1125, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1125, 0, ret_val_get_lmul_pow_1125); + setArg(call_illegal_indexed_load_1124, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1124, 1, vd); + setArg(call_illegal_indexed_load_1124, 2, vm); + setArg(call_illegal_indexed_load_1124, 3, 1); + setArg(call_illegal_indexed_load_1124, 4, EEW); + setArg(call_illegal_indexed_load_1124, 5, illegal_indexed_load_1124_arg4); + setArg(call_illegal_indexed_load_1124, 6, illegal_indexed_load_1124_arg5); + setRet(call_illegal_indexed_load_1124, 0, ret_val_illegal_indexed_load_1124); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1127; + x86::Gp ret_val_sew_1127 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1127, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1126; + auto vlxseg_1126_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1126_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1126_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1126_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1126_arg10 = ret_val_sew_1127; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1126 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1126, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1126, 32, false), traits::vstart); + setArg(call_sew_1127, 0, reinterpret_cast(this)); + setRet(call_sew_1127, 0, ret_val_sew_1127); + setArg(call_vlxseg_1126, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1126, 1, V); + setArg(call_vlxseg_1126, 2, vlxseg_1126_arg1); + setArg(call_vlxseg_1126, 3, vlxseg_1126_arg2); + setArg(call_vlxseg_1126, 4, vlxseg_1126_arg3); + setArg(call_vlxseg_1126, 5, vm); + setArg(call_vlxseg_1126, 6, vd); + setArg(call_vlxseg_1126, 7, vlxseg_1126_arg6); + setArg(call_vlxseg_1126, 8, vs2); + setArg(call_vlxseg_1126, 9, 1); + setArg(call_vlxseg_1126, 10, 1); + setArg(call_vlxseg_1126, 11, vlxseg_1126_arg10); + setArg(call_vlxseg_1126, 12, 1); + setRet(call_vlxseg_1126, 0, ret_val_vlxseg_1126); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 345); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 346: VLOXEI16__V */ + continuation_e __vloxei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXEI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 346); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1128; + x86::Gp ret_val_get_pow_1128 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1128, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1129; + x86::Gp ret_val_get_sew_pow_1129 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1129, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1130; + x86::Gp ret_val_get_lmul_pow_1130 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1130, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1128, ret_val_get_sew_pow_1129), ret_val_get_lmul_pow_1130)), 3, true); + setArg(call_get_pow_1128, 0, reinterpret_cast(this)); + setArg(call_get_pow_1128, 1, EEW); + setRet(call_get_pow_1128, 0, ret_val_get_pow_1128); + setArg(call_get_sew_pow_1129, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1129, 0, ret_val_get_sew_pow_1129); + setArg(call_get_lmul_pow_1130, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1130, 0, ret_val_get_lmul_pow_1130); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1132; + x86::Gp ret_val_get_lmul_pow_1132 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1132, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1131; + auto illegal_indexed_load_1131_arg4 = EMUL_pow; + auto illegal_indexed_load_1131_arg5 = ret_val_get_lmul_pow_1132; + x86::Gp ret_val_illegal_indexed_load_1131 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1131, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1131; + setArg(call_get_lmul_pow_1132, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1132, 0, ret_val_get_lmul_pow_1132); + setArg(call_illegal_indexed_load_1131, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1131, 1, vd); + setArg(call_illegal_indexed_load_1131, 2, vm); + setArg(call_illegal_indexed_load_1131, 3, 1); + setArg(call_illegal_indexed_load_1131, 4, EEW); + setArg(call_illegal_indexed_load_1131, 5, illegal_indexed_load_1131_arg4); + setArg(call_illegal_indexed_load_1131, 6, illegal_indexed_load_1131_arg5); + setRet(call_illegal_indexed_load_1131, 0, ret_val_illegal_indexed_load_1131); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1134; + x86::Gp ret_val_sew_1134 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1134, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1133; + auto vlxseg_1133_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1133_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1133_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1133_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1133_arg10 = ret_val_sew_1134; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1133 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1133, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1133, 32, false), traits::vstart); + setArg(call_sew_1134, 0, reinterpret_cast(this)); + setRet(call_sew_1134, 0, ret_val_sew_1134); + setArg(call_vlxseg_1133, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1133, 1, V); + setArg(call_vlxseg_1133, 2, vlxseg_1133_arg1); + setArg(call_vlxseg_1133, 3, vlxseg_1133_arg2); + setArg(call_vlxseg_1133, 4, vlxseg_1133_arg3); + setArg(call_vlxseg_1133, 5, vm); + setArg(call_vlxseg_1133, 6, vd); + setArg(call_vlxseg_1133, 7, vlxseg_1133_arg6); + setArg(call_vlxseg_1133, 8, vs2); + setArg(call_vlxseg_1133, 9, 1); + setArg(call_vlxseg_1133, 10, 2); + setArg(call_vlxseg_1133, 11, vlxseg_1133_arg10); + setArg(call_vlxseg_1133, 12, 1); + setRet(call_vlxseg_1133, 0, ret_val_vlxseg_1133); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 346); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 347: VLOXEI32__V */ + continuation_e __vloxei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXEI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 347); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1135; + x86::Gp ret_val_get_pow_1135 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1135, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1136; + x86::Gp ret_val_get_sew_pow_1136 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1136, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1137; + x86::Gp ret_val_get_lmul_pow_1137 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1137, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1135, ret_val_get_sew_pow_1136), ret_val_get_lmul_pow_1137)), 3, true); + setArg(call_get_pow_1135, 0, reinterpret_cast(this)); + setArg(call_get_pow_1135, 1, EEW); + setRet(call_get_pow_1135, 0, ret_val_get_pow_1135); + setArg(call_get_sew_pow_1136, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1136, 0, ret_val_get_sew_pow_1136); + setArg(call_get_lmul_pow_1137, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1137, 0, ret_val_get_lmul_pow_1137); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1139; + x86::Gp ret_val_get_lmul_pow_1139 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1139, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1138; + auto illegal_indexed_load_1138_arg4 = EMUL_pow; + auto illegal_indexed_load_1138_arg5 = ret_val_get_lmul_pow_1139; + x86::Gp ret_val_illegal_indexed_load_1138 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1138, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1138; + setArg(call_get_lmul_pow_1139, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1139, 0, ret_val_get_lmul_pow_1139); + setArg(call_illegal_indexed_load_1138, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1138, 1, vd); + setArg(call_illegal_indexed_load_1138, 2, vm); + setArg(call_illegal_indexed_load_1138, 3, 1); + setArg(call_illegal_indexed_load_1138, 4, EEW); + setArg(call_illegal_indexed_load_1138, 5, illegal_indexed_load_1138_arg4); + setArg(call_illegal_indexed_load_1138, 6, illegal_indexed_load_1138_arg5); + setRet(call_illegal_indexed_load_1138, 0, ret_val_illegal_indexed_load_1138); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1141; + x86::Gp ret_val_sew_1141 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1141, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1140; + auto vlxseg_1140_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1140_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1140_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1140_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1140_arg10 = ret_val_sew_1141; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1140 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1140, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1140, 32, false), traits::vstart); + setArg(call_sew_1141, 0, reinterpret_cast(this)); + setRet(call_sew_1141, 0, ret_val_sew_1141); + setArg(call_vlxseg_1140, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1140, 1, V); + setArg(call_vlxseg_1140, 2, vlxseg_1140_arg1); + setArg(call_vlxseg_1140, 3, vlxseg_1140_arg2); + setArg(call_vlxseg_1140, 4, vlxseg_1140_arg3); + setArg(call_vlxseg_1140, 5, vm); + setArg(call_vlxseg_1140, 6, vd); + setArg(call_vlxseg_1140, 7, vlxseg_1140_arg6); + setArg(call_vlxseg_1140, 8, vs2); + setArg(call_vlxseg_1140, 9, 1); + setArg(call_vlxseg_1140, 10, 4); + setArg(call_vlxseg_1140, 11, vlxseg_1140_arg10); + setArg(call_vlxseg_1140, 12, 1); + setRet(call_vlxseg_1140, 0, ret_val_vlxseg_1140); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 347); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 348: VLOXEI64__V */ + continuation_e __vloxei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXEI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 348); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1142; + x86::Gp ret_val_get_pow_1142 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1142, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1143; + x86::Gp ret_val_get_sew_pow_1143 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1143, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1144; + x86::Gp ret_val_get_lmul_pow_1144 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1144, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1142, ret_val_get_sew_pow_1143), ret_val_get_lmul_pow_1144)), 3, true); + setArg(call_get_pow_1142, 0, reinterpret_cast(this)); + setArg(call_get_pow_1142, 1, EEW); + setRet(call_get_pow_1142, 0, ret_val_get_pow_1142); + setArg(call_get_sew_pow_1143, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1143, 0, ret_val_get_sew_pow_1143); + setArg(call_get_lmul_pow_1144, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1144, 0, ret_val_get_lmul_pow_1144); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1146; + x86::Gp ret_val_get_lmul_pow_1146 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1146, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1145; + auto illegal_indexed_load_1145_arg4 = EMUL_pow; + auto illegal_indexed_load_1145_arg5 = ret_val_get_lmul_pow_1146; + x86::Gp ret_val_illegal_indexed_load_1145 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1145, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1145; + setArg(call_get_lmul_pow_1146, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1146, 0, ret_val_get_lmul_pow_1146); + setArg(call_illegal_indexed_load_1145, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1145, 1, vd); + setArg(call_illegal_indexed_load_1145, 2, vm); + setArg(call_illegal_indexed_load_1145, 3, 1); + setArg(call_illegal_indexed_load_1145, 4, EEW); + setArg(call_illegal_indexed_load_1145, 5, illegal_indexed_load_1145_arg4); + setArg(call_illegal_indexed_load_1145, 6, illegal_indexed_load_1145_arg5); + setRet(call_illegal_indexed_load_1145, 0, ret_val_illegal_indexed_load_1145); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1148; + x86::Gp ret_val_sew_1148 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1148, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1147; + auto vlxseg_1147_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1147_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1147_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1147_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1147_arg10 = ret_val_sew_1148; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1147 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1147, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1147, 32, false), traits::vstart); + setArg(call_sew_1148, 0, reinterpret_cast(this)); + setRet(call_sew_1148, 0, ret_val_sew_1148); + setArg(call_vlxseg_1147, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1147, 1, V); + setArg(call_vlxseg_1147, 2, vlxseg_1147_arg1); + setArg(call_vlxseg_1147, 3, vlxseg_1147_arg2); + setArg(call_vlxseg_1147, 4, vlxseg_1147_arg3); + setArg(call_vlxseg_1147, 5, vm); + setArg(call_vlxseg_1147, 6, vd); + setArg(call_vlxseg_1147, 7, vlxseg_1147_arg6); + setArg(call_vlxseg_1147, 8, vs2); + setArg(call_vlxseg_1147, 9, 1); + setArg(call_vlxseg_1147, 10, 8); + setArg(call_vlxseg_1147, 11, vlxseg_1147_arg10); + setArg(call_vlxseg_1147, 12, 1); + setRet(call_vlxseg_1147, 0, ret_val_vlxseg_1147); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 348); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 349: VLOXSEG2EI8__V */ + continuation_e __vloxseg2ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG2EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 349); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1149; + x86::Gp ret_val_get_pow_1149 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1149, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1150; + x86::Gp ret_val_get_sew_pow_1150 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1150, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1151; + x86::Gp ret_val_get_lmul_pow_1151 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1151, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1149, ret_val_get_sew_pow_1150), ret_val_get_lmul_pow_1151)), 3, true); + setArg(call_get_pow_1149, 0, reinterpret_cast(this)); + setArg(call_get_pow_1149, 1, EEW); + setRet(call_get_pow_1149, 0, ret_val_get_pow_1149); + setArg(call_get_sew_pow_1150, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1150, 0, ret_val_get_sew_pow_1150); + setArg(call_get_lmul_pow_1151, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1151, 0, ret_val_get_lmul_pow_1151); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1153; + x86::Gp ret_val_get_lmul_pow_1153 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1153, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1152; + auto illegal_indexed_load_1152_arg4 = EMUL_pow; + auto illegal_indexed_load_1152_arg5 = ret_val_get_lmul_pow_1153; + x86::Gp ret_val_illegal_indexed_load_1152 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1152, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1152; + setArg(call_get_lmul_pow_1153, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1153, 0, ret_val_get_lmul_pow_1153); + setArg(call_illegal_indexed_load_1152, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1152, 1, vd); + setArg(call_illegal_indexed_load_1152, 2, vm); + setArg(call_illegal_indexed_load_1152, 3, 2); + setArg(call_illegal_indexed_load_1152, 4, EEW); + setArg(call_illegal_indexed_load_1152, 5, illegal_indexed_load_1152_arg4); + setArg(call_illegal_indexed_load_1152, 6, illegal_indexed_load_1152_arg5); + setRet(call_illegal_indexed_load_1152, 0, ret_val_illegal_indexed_load_1152); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1155; + x86::Gp ret_val_sew_1155 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1155, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1154; + auto vlxseg_1154_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1154_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1154_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1154_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1154_arg10 = ret_val_sew_1155; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1154 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1154, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1154, 32, false), traits::vstart); + setArg(call_sew_1155, 0, reinterpret_cast(this)); + setRet(call_sew_1155, 0, ret_val_sew_1155); + setArg(call_vlxseg_1154, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1154, 1, V); + setArg(call_vlxseg_1154, 2, vlxseg_1154_arg1); + setArg(call_vlxseg_1154, 3, vlxseg_1154_arg2); + setArg(call_vlxseg_1154, 4, vlxseg_1154_arg3); + setArg(call_vlxseg_1154, 5, vm); + setArg(call_vlxseg_1154, 6, vd); + setArg(call_vlxseg_1154, 7, vlxseg_1154_arg6); + setArg(call_vlxseg_1154, 8, vs2); + setArg(call_vlxseg_1154, 9, 2); + setArg(call_vlxseg_1154, 10, 1); + setArg(call_vlxseg_1154, 11, vlxseg_1154_arg10); + setArg(call_vlxseg_1154, 12, 1); + setRet(call_vlxseg_1154, 0, ret_val_vlxseg_1154); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 349); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 350: VLOXSEG2EI16__V */ + continuation_e __vloxseg2ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG2EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 350); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1156; + x86::Gp ret_val_get_pow_1156 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1156, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1157; + x86::Gp ret_val_get_sew_pow_1157 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1157, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1158; + x86::Gp ret_val_get_lmul_pow_1158 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1158, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1156, ret_val_get_sew_pow_1157), ret_val_get_lmul_pow_1158)), 3, true); + setArg(call_get_pow_1156, 0, reinterpret_cast(this)); + setArg(call_get_pow_1156, 1, EEW); + setRet(call_get_pow_1156, 0, ret_val_get_pow_1156); + setArg(call_get_sew_pow_1157, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1157, 0, ret_val_get_sew_pow_1157); + setArg(call_get_lmul_pow_1158, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1158, 0, ret_val_get_lmul_pow_1158); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1160; + x86::Gp ret_val_get_lmul_pow_1160 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1160, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1159; + auto illegal_indexed_load_1159_arg4 = EMUL_pow; + auto illegal_indexed_load_1159_arg5 = ret_val_get_lmul_pow_1160; + x86::Gp ret_val_illegal_indexed_load_1159 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1159, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1159; + setArg(call_get_lmul_pow_1160, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1160, 0, ret_val_get_lmul_pow_1160); + setArg(call_illegal_indexed_load_1159, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1159, 1, vd); + setArg(call_illegal_indexed_load_1159, 2, vm); + setArg(call_illegal_indexed_load_1159, 3, 2); + setArg(call_illegal_indexed_load_1159, 4, EEW); + setArg(call_illegal_indexed_load_1159, 5, illegal_indexed_load_1159_arg4); + setArg(call_illegal_indexed_load_1159, 6, illegal_indexed_load_1159_arg5); + setRet(call_illegal_indexed_load_1159, 0, ret_val_illegal_indexed_load_1159); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1162; + x86::Gp ret_val_sew_1162 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1162, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1161; + auto vlxseg_1161_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1161_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1161_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1161_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1161_arg10 = ret_val_sew_1162; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1161 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1161, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1161, 32, false), traits::vstart); + setArg(call_sew_1162, 0, reinterpret_cast(this)); + setRet(call_sew_1162, 0, ret_val_sew_1162); + setArg(call_vlxseg_1161, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1161, 1, V); + setArg(call_vlxseg_1161, 2, vlxseg_1161_arg1); + setArg(call_vlxseg_1161, 3, vlxseg_1161_arg2); + setArg(call_vlxseg_1161, 4, vlxseg_1161_arg3); + setArg(call_vlxseg_1161, 5, vm); + setArg(call_vlxseg_1161, 6, vd); + setArg(call_vlxseg_1161, 7, vlxseg_1161_arg6); + setArg(call_vlxseg_1161, 8, vs2); + setArg(call_vlxseg_1161, 9, 2); + setArg(call_vlxseg_1161, 10, 2); + setArg(call_vlxseg_1161, 11, vlxseg_1161_arg10); + setArg(call_vlxseg_1161, 12, 1); + setRet(call_vlxseg_1161, 0, ret_val_vlxseg_1161); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 350); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 351: VLOXSEG2EI32__V */ + continuation_e __vloxseg2ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG2EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 351); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1163; + x86::Gp ret_val_get_pow_1163 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1163, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1164; + x86::Gp ret_val_get_sew_pow_1164 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1164, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1165; + x86::Gp ret_val_get_lmul_pow_1165 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1165, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1163, ret_val_get_sew_pow_1164), ret_val_get_lmul_pow_1165)), 3, true); + setArg(call_get_pow_1163, 0, reinterpret_cast(this)); + setArg(call_get_pow_1163, 1, EEW); + setRet(call_get_pow_1163, 0, ret_val_get_pow_1163); + setArg(call_get_sew_pow_1164, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1164, 0, ret_val_get_sew_pow_1164); + setArg(call_get_lmul_pow_1165, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1165, 0, ret_val_get_lmul_pow_1165); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1167; + x86::Gp ret_val_get_lmul_pow_1167 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1167, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1166; + auto illegal_indexed_load_1166_arg4 = EMUL_pow; + auto illegal_indexed_load_1166_arg5 = ret_val_get_lmul_pow_1167; + x86::Gp ret_val_illegal_indexed_load_1166 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1166, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1166; + setArg(call_get_lmul_pow_1167, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1167, 0, ret_val_get_lmul_pow_1167); + setArg(call_illegal_indexed_load_1166, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1166, 1, vd); + setArg(call_illegal_indexed_load_1166, 2, vm); + setArg(call_illegal_indexed_load_1166, 3, 2); + setArg(call_illegal_indexed_load_1166, 4, EEW); + setArg(call_illegal_indexed_load_1166, 5, illegal_indexed_load_1166_arg4); + setArg(call_illegal_indexed_load_1166, 6, illegal_indexed_load_1166_arg5); + setRet(call_illegal_indexed_load_1166, 0, ret_val_illegal_indexed_load_1166); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1169; + x86::Gp ret_val_sew_1169 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1169, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1168; + auto vlxseg_1168_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1168_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1168_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1168_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1168_arg10 = ret_val_sew_1169; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1168 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1168, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1168, 32, false), traits::vstart); + setArg(call_sew_1169, 0, reinterpret_cast(this)); + setRet(call_sew_1169, 0, ret_val_sew_1169); + setArg(call_vlxseg_1168, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1168, 1, V); + setArg(call_vlxseg_1168, 2, vlxseg_1168_arg1); + setArg(call_vlxseg_1168, 3, vlxseg_1168_arg2); + setArg(call_vlxseg_1168, 4, vlxseg_1168_arg3); + setArg(call_vlxseg_1168, 5, vm); + setArg(call_vlxseg_1168, 6, vd); + setArg(call_vlxseg_1168, 7, vlxseg_1168_arg6); + setArg(call_vlxseg_1168, 8, vs2); + setArg(call_vlxseg_1168, 9, 2); + setArg(call_vlxseg_1168, 10, 4); + setArg(call_vlxseg_1168, 11, vlxseg_1168_arg10); + setArg(call_vlxseg_1168, 12, 1); + setRet(call_vlxseg_1168, 0, ret_val_vlxseg_1168); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 351); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 352: VLOXSEG2EI64__V */ + continuation_e __vloxseg2ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG2EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 352); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1170; + x86::Gp ret_val_get_pow_1170 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1170, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1171; + x86::Gp ret_val_get_sew_pow_1171 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1171, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1172; + x86::Gp ret_val_get_lmul_pow_1172 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1172, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1170, ret_val_get_sew_pow_1171), ret_val_get_lmul_pow_1172)), 3, true); + setArg(call_get_pow_1170, 0, reinterpret_cast(this)); + setArg(call_get_pow_1170, 1, EEW); + setRet(call_get_pow_1170, 0, ret_val_get_pow_1170); + setArg(call_get_sew_pow_1171, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1171, 0, ret_val_get_sew_pow_1171); + setArg(call_get_lmul_pow_1172, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1172, 0, ret_val_get_lmul_pow_1172); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1174; + x86::Gp ret_val_get_lmul_pow_1174 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1174, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1173; + auto illegal_indexed_load_1173_arg4 = EMUL_pow; + auto illegal_indexed_load_1173_arg5 = ret_val_get_lmul_pow_1174; + x86::Gp ret_val_illegal_indexed_load_1173 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1173, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1173; + setArg(call_get_lmul_pow_1174, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1174, 0, ret_val_get_lmul_pow_1174); + setArg(call_illegal_indexed_load_1173, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1173, 1, vd); + setArg(call_illegal_indexed_load_1173, 2, vm); + setArg(call_illegal_indexed_load_1173, 3, 2); + setArg(call_illegal_indexed_load_1173, 4, EEW); + setArg(call_illegal_indexed_load_1173, 5, illegal_indexed_load_1173_arg4); + setArg(call_illegal_indexed_load_1173, 6, illegal_indexed_load_1173_arg5); + setRet(call_illegal_indexed_load_1173, 0, ret_val_illegal_indexed_load_1173); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1176; + x86::Gp ret_val_sew_1176 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1176, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1175; + auto vlxseg_1175_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1175_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1175_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1175_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1175_arg10 = ret_val_sew_1176; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1175 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1175, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1175, 32, false), traits::vstart); + setArg(call_sew_1176, 0, reinterpret_cast(this)); + setRet(call_sew_1176, 0, ret_val_sew_1176); + setArg(call_vlxseg_1175, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1175, 1, V); + setArg(call_vlxseg_1175, 2, vlxseg_1175_arg1); + setArg(call_vlxseg_1175, 3, vlxseg_1175_arg2); + setArg(call_vlxseg_1175, 4, vlxseg_1175_arg3); + setArg(call_vlxseg_1175, 5, vm); + setArg(call_vlxseg_1175, 6, vd); + setArg(call_vlxseg_1175, 7, vlxseg_1175_arg6); + setArg(call_vlxseg_1175, 8, vs2); + setArg(call_vlxseg_1175, 9, 2); + setArg(call_vlxseg_1175, 10, 8); + setArg(call_vlxseg_1175, 11, vlxseg_1175_arg10); + setArg(call_vlxseg_1175, 12, 1); + setRet(call_vlxseg_1175, 0, ret_val_vlxseg_1175); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 352); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 353: VLOXSEG3EI8__V */ + continuation_e __vloxseg3ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG3EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 353); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1177; + x86::Gp ret_val_get_pow_1177 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1177, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1178; + x86::Gp ret_val_get_sew_pow_1178 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1178, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1179; + x86::Gp ret_val_get_lmul_pow_1179 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1179, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1177, ret_val_get_sew_pow_1178), ret_val_get_lmul_pow_1179)), 3, true); + setArg(call_get_pow_1177, 0, reinterpret_cast(this)); + setArg(call_get_pow_1177, 1, EEW); + setRet(call_get_pow_1177, 0, ret_val_get_pow_1177); + setArg(call_get_sew_pow_1178, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1178, 0, ret_val_get_sew_pow_1178); + setArg(call_get_lmul_pow_1179, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1179, 0, ret_val_get_lmul_pow_1179); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1181; + x86::Gp ret_val_get_lmul_pow_1181 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1181, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1180; + auto illegal_indexed_load_1180_arg4 = EMUL_pow; + auto illegal_indexed_load_1180_arg5 = ret_val_get_lmul_pow_1181; + x86::Gp ret_val_illegal_indexed_load_1180 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1180, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1180; + setArg(call_get_lmul_pow_1181, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1181, 0, ret_val_get_lmul_pow_1181); + setArg(call_illegal_indexed_load_1180, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1180, 1, vd); + setArg(call_illegal_indexed_load_1180, 2, vm); + setArg(call_illegal_indexed_load_1180, 3, 3); + setArg(call_illegal_indexed_load_1180, 4, EEW); + setArg(call_illegal_indexed_load_1180, 5, illegal_indexed_load_1180_arg4); + setArg(call_illegal_indexed_load_1180, 6, illegal_indexed_load_1180_arg5); + setRet(call_illegal_indexed_load_1180, 0, ret_val_illegal_indexed_load_1180); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1183; + x86::Gp ret_val_sew_1183 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1183, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1182; + auto vlxseg_1182_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1182_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1182_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1182_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1182_arg10 = ret_val_sew_1183; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1182 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1182, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1182, 32, false), traits::vstart); + setArg(call_sew_1183, 0, reinterpret_cast(this)); + setRet(call_sew_1183, 0, ret_val_sew_1183); + setArg(call_vlxseg_1182, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1182, 1, V); + setArg(call_vlxseg_1182, 2, vlxseg_1182_arg1); + setArg(call_vlxseg_1182, 3, vlxseg_1182_arg2); + setArg(call_vlxseg_1182, 4, vlxseg_1182_arg3); + setArg(call_vlxseg_1182, 5, vm); + setArg(call_vlxseg_1182, 6, vd); + setArg(call_vlxseg_1182, 7, vlxseg_1182_arg6); + setArg(call_vlxseg_1182, 8, vs2); + setArg(call_vlxseg_1182, 9, 3); + setArg(call_vlxseg_1182, 10, 1); + setArg(call_vlxseg_1182, 11, vlxseg_1182_arg10); + setArg(call_vlxseg_1182, 12, 1); + setRet(call_vlxseg_1182, 0, ret_val_vlxseg_1182); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 353); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 354: VLOXSEG3EI16__V */ + continuation_e __vloxseg3ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG3EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 354); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1184; + x86::Gp ret_val_get_pow_1184 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1184, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1185; + x86::Gp ret_val_get_sew_pow_1185 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1185, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1186; + x86::Gp ret_val_get_lmul_pow_1186 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1186, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1184, ret_val_get_sew_pow_1185), ret_val_get_lmul_pow_1186)), 3, true); + setArg(call_get_pow_1184, 0, reinterpret_cast(this)); + setArg(call_get_pow_1184, 1, EEW); + setRet(call_get_pow_1184, 0, ret_val_get_pow_1184); + setArg(call_get_sew_pow_1185, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1185, 0, ret_val_get_sew_pow_1185); + setArg(call_get_lmul_pow_1186, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1186, 0, ret_val_get_lmul_pow_1186); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1188; + x86::Gp ret_val_get_lmul_pow_1188 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1188, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1187; + auto illegal_indexed_load_1187_arg4 = EMUL_pow; + auto illegal_indexed_load_1187_arg5 = ret_val_get_lmul_pow_1188; + x86::Gp ret_val_illegal_indexed_load_1187 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1187, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1187; + setArg(call_get_lmul_pow_1188, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1188, 0, ret_val_get_lmul_pow_1188); + setArg(call_illegal_indexed_load_1187, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1187, 1, vd); + setArg(call_illegal_indexed_load_1187, 2, vm); + setArg(call_illegal_indexed_load_1187, 3, 3); + setArg(call_illegal_indexed_load_1187, 4, EEW); + setArg(call_illegal_indexed_load_1187, 5, illegal_indexed_load_1187_arg4); + setArg(call_illegal_indexed_load_1187, 6, illegal_indexed_load_1187_arg5); + setRet(call_illegal_indexed_load_1187, 0, ret_val_illegal_indexed_load_1187); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1190; + x86::Gp ret_val_sew_1190 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1190, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1189; + auto vlxseg_1189_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1189_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1189_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1189_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1189_arg10 = ret_val_sew_1190; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1189 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1189, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1189, 32, false), traits::vstart); + setArg(call_sew_1190, 0, reinterpret_cast(this)); + setRet(call_sew_1190, 0, ret_val_sew_1190); + setArg(call_vlxseg_1189, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1189, 1, V); + setArg(call_vlxseg_1189, 2, vlxseg_1189_arg1); + setArg(call_vlxseg_1189, 3, vlxseg_1189_arg2); + setArg(call_vlxseg_1189, 4, vlxseg_1189_arg3); + setArg(call_vlxseg_1189, 5, vm); + setArg(call_vlxseg_1189, 6, vd); + setArg(call_vlxseg_1189, 7, vlxseg_1189_arg6); + setArg(call_vlxseg_1189, 8, vs2); + setArg(call_vlxseg_1189, 9, 3); + setArg(call_vlxseg_1189, 10, 2); + setArg(call_vlxseg_1189, 11, vlxseg_1189_arg10); + setArg(call_vlxseg_1189, 12, 1); + setRet(call_vlxseg_1189, 0, ret_val_vlxseg_1189); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 354); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 355: VLOXSEG3EI32__V */ + continuation_e __vloxseg3ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG3EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 355); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1191; + x86::Gp ret_val_get_pow_1191 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1191, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1192; + x86::Gp ret_val_get_sew_pow_1192 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1192, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1193; + x86::Gp ret_val_get_lmul_pow_1193 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1193, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1191, ret_val_get_sew_pow_1192), ret_val_get_lmul_pow_1193)), 3, true); + setArg(call_get_pow_1191, 0, reinterpret_cast(this)); + setArg(call_get_pow_1191, 1, EEW); + setRet(call_get_pow_1191, 0, ret_val_get_pow_1191); + setArg(call_get_sew_pow_1192, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1192, 0, ret_val_get_sew_pow_1192); + setArg(call_get_lmul_pow_1193, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1193, 0, ret_val_get_lmul_pow_1193); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1195; + x86::Gp ret_val_get_lmul_pow_1195 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1195, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1194; + auto illegal_indexed_load_1194_arg4 = EMUL_pow; + auto illegal_indexed_load_1194_arg5 = ret_val_get_lmul_pow_1195; + x86::Gp ret_val_illegal_indexed_load_1194 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1194, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1194; + setArg(call_get_lmul_pow_1195, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1195, 0, ret_val_get_lmul_pow_1195); + setArg(call_illegal_indexed_load_1194, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1194, 1, vd); + setArg(call_illegal_indexed_load_1194, 2, vm); + setArg(call_illegal_indexed_load_1194, 3, 3); + setArg(call_illegal_indexed_load_1194, 4, EEW); + setArg(call_illegal_indexed_load_1194, 5, illegal_indexed_load_1194_arg4); + setArg(call_illegal_indexed_load_1194, 6, illegal_indexed_load_1194_arg5); + setRet(call_illegal_indexed_load_1194, 0, ret_val_illegal_indexed_load_1194); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1197; + x86::Gp ret_val_sew_1197 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1197, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1196; + auto vlxseg_1196_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1196_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1196_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1196_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1196_arg10 = ret_val_sew_1197; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1196 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1196, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1196, 32, false), traits::vstart); + setArg(call_sew_1197, 0, reinterpret_cast(this)); + setRet(call_sew_1197, 0, ret_val_sew_1197); + setArg(call_vlxseg_1196, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1196, 1, V); + setArg(call_vlxseg_1196, 2, vlxseg_1196_arg1); + setArg(call_vlxseg_1196, 3, vlxseg_1196_arg2); + setArg(call_vlxseg_1196, 4, vlxseg_1196_arg3); + setArg(call_vlxseg_1196, 5, vm); + setArg(call_vlxseg_1196, 6, vd); + setArg(call_vlxseg_1196, 7, vlxseg_1196_arg6); + setArg(call_vlxseg_1196, 8, vs2); + setArg(call_vlxseg_1196, 9, 3); + setArg(call_vlxseg_1196, 10, 4); + setArg(call_vlxseg_1196, 11, vlxseg_1196_arg10); + setArg(call_vlxseg_1196, 12, 1); + setRet(call_vlxseg_1196, 0, ret_val_vlxseg_1196); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 355); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 356: VLOXSEG3EI64__V */ + continuation_e __vloxseg3ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG3EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 356); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1198; + x86::Gp ret_val_get_pow_1198 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1198, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1199; + x86::Gp ret_val_get_sew_pow_1199 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1199, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1200; + x86::Gp ret_val_get_lmul_pow_1200 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1200, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1198, ret_val_get_sew_pow_1199), ret_val_get_lmul_pow_1200)), 3, true); + setArg(call_get_pow_1198, 0, reinterpret_cast(this)); + setArg(call_get_pow_1198, 1, EEW); + setRet(call_get_pow_1198, 0, ret_val_get_pow_1198); + setArg(call_get_sew_pow_1199, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1199, 0, ret_val_get_sew_pow_1199); + setArg(call_get_lmul_pow_1200, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1200, 0, ret_val_get_lmul_pow_1200); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1202; + x86::Gp ret_val_get_lmul_pow_1202 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1202, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1201; + auto illegal_indexed_load_1201_arg4 = EMUL_pow; + auto illegal_indexed_load_1201_arg5 = ret_val_get_lmul_pow_1202; + x86::Gp ret_val_illegal_indexed_load_1201 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1201, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1201; + setArg(call_get_lmul_pow_1202, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1202, 0, ret_val_get_lmul_pow_1202); + setArg(call_illegal_indexed_load_1201, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1201, 1, vd); + setArg(call_illegal_indexed_load_1201, 2, vm); + setArg(call_illegal_indexed_load_1201, 3, 3); + setArg(call_illegal_indexed_load_1201, 4, EEW); + setArg(call_illegal_indexed_load_1201, 5, illegal_indexed_load_1201_arg4); + setArg(call_illegal_indexed_load_1201, 6, illegal_indexed_load_1201_arg5); + setRet(call_illegal_indexed_load_1201, 0, ret_val_illegal_indexed_load_1201); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1204; + x86::Gp ret_val_sew_1204 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1204, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1203; + auto vlxseg_1203_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1203_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1203_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1203_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1203_arg10 = ret_val_sew_1204; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1203 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1203, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1203, 32, false), traits::vstart); + setArg(call_sew_1204, 0, reinterpret_cast(this)); + setRet(call_sew_1204, 0, ret_val_sew_1204); + setArg(call_vlxseg_1203, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1203, 1, V); + setArg(call_vlxseg_1203, 2, vlxseg_1203_arg1); + setArg(call_vlxseg_1203, 3, vlxseg_1203_arg2); + setArg(call_vlxseg_1203, 4, vlxseg_1203_arg3); + setArg(call_vlxseg_1203, 5, vm); + setArg(call_vlxseg_1203, 6, vd); + setArg(call_vlxseg_1203, 7, vlxseg_1203_arg6); + setArg(call_vlxseg_1203, 8, vs2); + setArg(call_vlxseg_1203, 9, 3); + setArg(call_vlxseg_1203, 10, 8); + setArg(call_vlxseg_1203, 11, vlxseg_1203_arg10); + setArg(call_vlxseg_1203, 12, 1); + setRet(call_vlxseg_1203, 0, ret_val_vlxseg_1203); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 356); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 357: VLOXSEG4EI8__V */ + continuation_e __vloxseg4ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG4EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 357); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1205; + x86::Gp ret_val_get_pow_1205 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1205, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1206; + x86::Gp ret_val_get_sew_pow_1206 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1206, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1207; + x86::Gp ret_val_get_lmul_pow_1207 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1207, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1205, ret_val_get_sew_pow_1206), ret_val_get_lmul_pow_1207)), 3, true); + setArg(call_get_pow_1205, 0, reinterpret_cast(this)); + setArg(call_get_pow_1205, 1, EEW); + setRet(call_get_pow_1205, 0, ret_val_get_pow_1205); + setArg(call_get_sew_pow_1206, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1206, 0, ret_val_get_sew_pow_1206); + setArg(call_get_lmul_pow_1207, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1207, 0, ret_val_get_lmul_pow_1207); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1209; + x86::Gp ret_val_get_lmul_pow_1209 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1209, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1208; + auto illegal_indexed_load_1208_arg4 = EMUL_pow; + auto illegal_indexed_load_1208_arg5 = ret_val_get_lmul_pow_1209; + x86::Gp ret_val_illegal_indexed_load_1208 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1208, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1208; + setArg(call_get_lmul_pow_1209, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1209, 0, ret_val_get_lmul_pow_1209); + setArg(call_illegal_indexed_load_1208, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1208, 1, vd); + setArg(call_illegal_indexed_load_1208, 2, vm); + setArg(call_illegal_indexed_load_1208, 3, 4); + setArg(call_illegal_indexed_load_1208, 4, EEW); + setArg(call_illegal_indexed_load_1208, 5, illegal_indexed_load_1208_arg4); + setArg(call_illegal_indexed_load_1208, 6, illegal_indexed_load_1208_arg5); + setRet(call_illegal_indexed_load_1208, 0, ret_val_illegal_indexed_load_1208); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1211; + x86::Gp ret_val_sew_1211 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1211, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1210; + auto vlxseg_1210_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1210_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1210_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1210_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1210_arg10 = ret_val_sew_1211; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1210 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1210, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1210, 32, false), traits::vstart); + setArg(call_sew_1211, 0, reinterpret_cast(this)); + setRet(call_sew_1211, 0, ret_val_sew_1211); + setArg(call_vlxseg_1210, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1210, 1, V); + setArg(call_vlxseg_1210, 2, vlxseg_1210_arg1); + setArg(call_vlxseg_1210, 3, vlxseg_1210_arg2); + setArg(call_vlxseg_1210, 4, vlxseg_1210_arg3); + setArg(call_vlxseg_1210, 5, vm); + setArg(call_vlxseg_1210, 6, vd); + setArg(call_vlxseg_1210, 7, vlxseg_1210_arg6); + setArg(call_vlxseg_1210, 8, vs2); + setArg(call_vlxseg_1210, 9, 4); + setArg(call_vlxseg_1210, 10, 1); + setArg(call_vlxseg_1210, 11, vlxseg_1210_arg10); + setArg(call_vlxseg_1210, 12, 1); + setRet(call_vlxseg_1210, 0, ret_val_vlxseg_1210); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 357); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 358: VLOXSEG4EI16__V */ + continuation_e __vloxseg4ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG4EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 358); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1212; + x86::Gp ret_val_get_pow_1212 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1212, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1213; + x86::Gp ret_val_get_sew_pow_1213 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1213, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1214; + x86::Gp ret_val_get_lmul_pow_1214 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1214, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1212, ret_val_get_sew_pow_1213), ret_val_get_lmul_pow_1214)), 3, true); + setArg(call_get_pow_1212, 0, reinterpret_cast(this)); + setArg(call_get_pow_1212, 1, EEW); + setRet(call_get_pow_1212, 0, ret_val_get_pow_1212); + setArg(call_get_sew_pow_1213, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1213, 0, ret_val_get_sew_pow_1213); + setArg(call_get_lmul_pow_1214, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1214, 0, ret_val_get_lmul_pow_1214); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1216; + x86::Gp ret_val_get_lmul_pow_1216 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1216, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1215; + auto illegal_indexed_load_1215_arg4 = EMUL_pow; + auto illegal_indexed_load_1215_arg5 = ret_val_get_lmul_pow_1216; + x86::Gp ret_val_illegal_indexed_load_1215 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1215, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1215; + setArg(call_get_lmul_pow_1216, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1216, 0, ret_val_get_lmul_pow_1216); + setArg(call_illegal_indexed_load_1215, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1215, 1, vd); + setArg(call_illegal_indexed_load_1215, 2, vm); + setArg(call_illegal_indexed_load_1215, 3, 4); + setArg(call_illegal_indexed_load_1215, 4, EEW); + setArg(call_illegal_indexed_load_1215, 5, illegal_indexed_load_1215_arg4); + setArg(call_illegal_indexed_load_1215, 6, illegal_indexed_load_1215_arg5); + setRet(call_illegal_indexed_load_1215, 0, ret_val_illegal_indexed_load_1215); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1218; + x86::Gp ret_val_sew_1218 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1218, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1217; + auto vlxseg_1217_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1217_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1217_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1217_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1217_arg10 = ret_val_sew_1218; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1217 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1217, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1217, 32, false), traits::vstart); + setArg(call_sew_1218, 0, reinterpret_cast(this)); + setRet(call_sew_1218, 0, ret_val_sew_1218); + setArg(call_vlxseg_1217, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1217, 1, V); + setArg(call_vlxseg_1217, 2, vlxseg_1217_arg1); + setArg(call_vlxseg_1217, 3, vlxseg_1217_arg2); + setArg(call_vlxseg_1217, 4, vlxseg_1217_arg3); + setArg(call_vlxseg_1217, 5, vm); + setArg(call_vlxseg_1217, 6, vd); + setArg(call_vlxseg_1217, 7, vlxseg_1217_arg6); + setArg(call_vlxseg_1217, 8, vs2); + setArg(call_vlxseg_1217, 9, 4); + setArg(call_vlxseg_1217, 10, 2); + setArg(call_vlxseg_1217, 11, vlxseg_1217_arg10); + setArg(call_vlxseg_1217, 12, 1); + setRet(call_vlxseg_1217, 0, ret_val_vlxseg_1217); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 358); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 359: VLOXSEG4EI32__V */ + continuation_e __vloxseg4ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG4EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 359); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1219; + x86::Gp ret_val_get_pow_1219 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1219, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1220; + x86::Gp ret_val_get_sew_pow_1220 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1220, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1221; + x86::Gp ret_val_get_lmul_pow_1221 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1221, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1219, ret_val_get_sew_pow_1220), ret_val_get_lmul_pow_1221)), 3, true); + setArg(call_get_pow_1219, 0, reinterpret_cast(this)); + setArg(call_get_pow_1219, 1, EEW); + setRet(call_get_pow_1219, 0, ret_val_get_pow_1219); + setArg(call_get_sew_pow_1220, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1220, 0, ret_val_get_sew_pow_1220); + setArg(call_get_lmul_pow_1221, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1221, 0, ret_val_get_lmul_pow_1221); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1223; + x86::Gp ret_val_get_lmul_pow_1223 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1223, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1222; + auto illegal_indexed_load_1222_arg4 = EMUL_pow; + auto illegal_indexed_load_1222_arg5 = ret_val_get_lmul_pow_1223; + x86::Gp ret_val_illegal_indexed_load_1222 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1222, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1222; + setArg(call_get_lmul_pow_1223, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1223, 0, ret_val_get_lmul_pow_1223); + setArg(call_illegal_indexed_load_1222, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1222, 1, vd); + setArg(call_illegal_indexed_load_1222, 2, vm); + setArg(call_illegal_indexed_load_1222, 3, 4); + setArg(call_illegal_indexed_load_1222, 4, EEW); + setArg(call_illegal_indexed_load_1222, 5, illegal_indexed_load_1222_arg4); + setArg(call_illegal_indexed_load_1222, 6, illegal_indexed_load_1222_arg5); + setRet(call_illegal_indexed_load_1222, 0, ret_val_illegal_indexed_load_1222); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1225; + x86::Gp ret_val_sew_1225 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1225, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1224; + auto vlxseg_1224_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1224_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1224_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1224_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1224_arg10 = ret_val_sew_1225; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1224 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1224, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1224, 32, false), traits::vstart); + setArg(call_sew_1225, 0, reinterpret_cast(this)); + setRet(call_sew_1225, 0, ret_val_sew_1225); + setArg(call_vlxseg_1224, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1224, 1, V); + setArg(call_vlxseg_1224, 2, vlxseg_1224_arg1); + setArg(call_vlxseg_1224, 3, vlxseg_1224_arg2); + setArg(call_vlxseg_1224, 4, vlxseg_1224_arg3); + setArg(call_vlxseg_1224, 5, vm); + setArg(call_vlxseg_1224, 6, vd); + setArg(call_vlxseg_1224, 7, vlxseg_1224_arg6); + setArg(call_vlxseg_1224, 8, vs2); + setArg(call_vlxseg_1224, 9, 4); + setArg(call_vlxseg_1224, 10, 4); + setArg(call_vlxseg_1224, 11, vlxseg_1224_arg10); + setArg(call_vlxseg_1224, 12, 1); + setRet(call_vlxseg_1224, 0, ret_val_vlxseg_1224); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 359); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 360: VLOXSEG4EI64__V */ + continuation_e __vloxseg4ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG4EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 360); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1226; + x86::Gp ret_val_get_pow_1226 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1226, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1227; + x86::Gp ret_val_get_sew_pow_1227 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1227, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1228; + x86::Gp ret_val_get_lmul_pow_1228 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1228, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1226, ret_val_get_sew_pow_1227), ret_val_get_lmul_pow_1228)), 3, true); + setArg(call_get_pow_1226, 0, reinterpret_cast(this)); + setArg(call_get_pow_1226, 1, EEW); + setRet(call_get_pow_1226, 0, ret_val_get_pow_1226); + setArg(call_get_sew_pow_1227, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1227, 0, ret_val_get_sew_pow_1227); + setArg(call_get_lmul_pow_1228, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1228, 0, ret_val_get_lmul_pow_1228); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1230; + x86::Gp ret_val_get_lmul_pow_1230 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1230, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1229; + auto illegal_indexed_load_1229_arg4 = EMUL_pow; + auto illegal_indexed_load_1229_arg5 = ret_val_get_lmul_pow_1230; + x86::Gp ret_val_illegal_indexed_load_1229 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1229, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1229; + setArg(call_get_lmul_pow_1230, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1230, 0, ret_val_get_lmul_pow_1230); + setArg(call_illegal_indexed_load_1229, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1229, 1, vd); + setArg(call_illegal_indexed_load_1229, 2, vm); + setArg(call_illegal_indexed_load_1229, 3, 4); + setArg(call_illegal_indexed_load_1229, 4, EEW); + setArg(call_illegal_indexed_load_1229, 5, illegal_indexed_load_1229_arg4); + setArg(call_illegal_indexed_load_1229, 6, illegal_indexed_load_1229_arg5); + setRet(call_illegal_indexed_load_1229, 0, ret_val_illegal_indexed_load_1229); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1232; + x86::Gp ret_val_sew_1232 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1232, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1231; + auto vlxseg_1231_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1231_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1231_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1231_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1231_arg10 = ret_val_sew_1232; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1231 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1231, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1231, 32, false), traits::vstart); + setArg(call_sew_1232, 0, reinterpret_cast(this)); + setRet(call_sew_1232, 0, ret_val_sew_1232); + setArg(call_vlxseg_1231, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1231, 1, V); + setArg(call_vlxseg_1231, 2, vlxseg_1231_arg1); + setArg(call_vlxseg_1231, 3, vlxseg_1231_arg2); + setArg(call_vlxseg_1231, 4, vlxseg_1231_arg3); + setArg(call_vlxseg_1231, 5, vm); + setArg(call_vlxseg_1231, 6, vd); + setArg(call_vlxseg_1231, 7, vlxseg_1231_arg6); + setArg(call_vlxseg_1231, 8, vs2); + setArg(call_vlxseg_1231, 9, 4); + setArg(call_vlxseg_1231, 10, 8); + setArg(call_vlxseg_1231, 11, vlxseg_1231_arg10); + setArg(call_vlxseg_1231, 12, 1); + setRet(call_vlxseg_1231, 0, ret_val_vlxseg_1231); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 360); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 361: VLOXSEG5EI8__V */ + continuation_e __vloxseg5ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG5EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 361); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1233; + x86::Gp ret_val_get_pow_1233 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1233, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1234; + x86::Gp ret_val_get_sew_pow_1234 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1234, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1235; + x86::Gp ret_val_get_lmul_pow_1235 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1235, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1233, ret_val_get_sew_pow_1234), ret_val_get_lmul_pow_1235)), 3, true); + setArg(call_get_pow_1233, 0, reinterpret_cast(this)); + setArg(call_get_pow_1233, 1, EEW); + setRet(call_get_pow_1233, 0, ret_val_get_pow_1233); + setArg(call_get_sew_pow_1234, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1234, 0, ret_val_get_sew_pow_1234); + setArg(call_get_lmul_pow_1235, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1235, 0, ret_val_get_lmul_pow_1235); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1237; + x86::Gp ret_val_get_lmul_pow_1237 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1237, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1236; + auto illegal_indexed_load_1236_arg4 = EMUL_pow; + auto illegal_indexed_load_1236_arg5 = ret_val_get_lmul_pow_1237; + x86::Gp ret_val_illegal_indexed_load_1236 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1236, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1236; + setArg(call_get_lmul_pow_1237, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1237, 0, ret_val_get_lmul_pow_1237); + setArg(call_illegal_indexed_load_1236, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1236, 1, vd); + setArg(call_illegal_indexed_load_1236, 2, vm); + setArg(call_illegal_indexed_load_1236, 3, 5); + setArg(call_illegal_indexed_load_1236, 4, EEW); + setArg(call_illegal_indexed_load_1236, 5, illegal_indexed_load_1236_arg4); + setArg(call_illegal_indexed_load_1236, 6, illegal_indexed_load_1236_arg5); + setRet(call_illegal_indexed_load_1236, 0, ret_val_illegal_indexed_load_1236); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1239; + x86::Gp ret_val_sew_1239 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1239, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1238; + auto vlxseg_1238_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1238_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1238_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1238_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1238_arg10 = ret_val_sew_1239; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1238 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1238, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1238, 32, false), traits::vstart); + setArg(call_sew_1239, 0, reinterpret_cast(this)); + setRet(call_sew_1239, 0, ret_val_sew_1239); + setArg(call_vlxseg_1238, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1238, 1, V); + setArg(call_vlxseg_1238, 2, vlxseg_1238_arg1); + setArg(call_vlxseg_1238, 3, vlxseg_1238_arg2); + setArg(call_vlxseg_1238, 4, vlxseg_1238_arg3); + setArg(call_vlxseg_1238, 5, vm); + setArg(call_vlxseg_1238, 6, vd); + setArg(call_vlxseg_1238, 7, vlxseg_1238_arg6); + setArg(call_vlxseg_1238, 8, vs2); + setArg(call_vlxseg_1238, 9, 5); + setArg(call_vlxseg_1238, 10, 1); + setArg(call_vlxseg_1238, 11, vlxseg_1238_arg10); + setArg(call_vlxseg_1238, 12, 1); + setRet(call_vlxseg_1238, 0, ret_val_vlxseg_1238); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 361); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 362: VLOXSEG5EI16__V */ + continuation_e __vloxseg5ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG5EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 362); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1240; + x86::Gp ret_val_get_pow_1240 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1240, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1241; + x86::Gp ret_val_get_sew_pow_1241 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1241, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1242; + x86::Gp ret_val_get_lmul_pow_1242 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1242, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1240, ret_val_get_sew_pow_1241), ret_val_get_lmul_pow_1242)), 3, true); + setArg(call_get_pow_1240, 0, reinterpret_cast(this)); + setArg(call_get_pow_1240, 1, EEW); + setRet(call_get_pow_1240, 0, ret_val_get_pow_1240); + setArg(call_get_sew_pow_1241, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1241, 0, ret_val_get_sew_pow_1241); + setArg(call_get_lmul_pow_1242, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1242, 0, ret_val_get_lmul_pow_1242); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1244; + x86::Gp ret_val_get_lmul_pow_1244 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1244, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1243; + auto illegal_indexed_load_1243_arg4 = EMUL_pow; + auto illegal_indexed_load_1243_arg5 = ret_val_get_lmul_pow_1244; + x86::Gp ret_val_illegal_indexed_load_1243 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1243, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1243; + setArg(call_get_lmul_pow_1244, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1244, 0, ret_val_get_lmul_pow_1244); + setArg(call_illegal_indexed_load_1243, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1243, 1, vd); + setArg(call_illegal_indexed_load_1243, 2, vm); + setArg(call_illegal_indexed_load_1243, 3, 5); + setArg(call_illegal_indexed_load_1243, 4, EEW); + setArg(call_illegal_indexed_load_1243, 5, illegal_indexed_load_1243_arg4); + setArg(call_illegal_indexed_load_1243, 6, illegal_indexed_load_1243_arg5); + setRet(call_illegal_indexed_load_1243, 0, ret_val_illegal_indexed_load_1243); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1246; + x86::Gp ret_val_sew_1246 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1246, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1245; + auto vlxseg_1245_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1245_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1245_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1245_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1245_arg10 = ret_val_sew_1246; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1245 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1245, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1245, 32, false), traits::vstart); + setArg(call_sew_1246, 0, reinterpret_cast(this)); + setRet(call_sew_1246, 0, ret_val_sew_1246); + setArg(call_vlxseg_1245, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1245, 1, V); + setArg(call_vlxseg_1245, 2, vlxseg_1245_arg1); + setArg(call_vlxseg_1245, 3, vlxseg_1245_arg2); + setArg(call_vlxseg_1245, 4, vlxseg_1245_arg3); + setArg(call_vlxseg_1245, 5, vm); + setArg(call_vlxseg_1245, 6, vd); + setArg(call_vlxseg_1245, 7, vlxseg_1245_arg6); + setArg(call_vlxseg_1245, 8, vs2); + setArg(call_vlxseg_1245, 9, 5); + setArg(call_vlxseg_1245, 10, 2); + setArg(call_vlxseg_1245, 11, vlxseg_1245_arg10); + setArg(call_vlxseg_1245, 12, 1); + setRet(call_vlxseg_1245, 0, ret_val_vlxseg_1245); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 362); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 363: VLOXSEG5EI32__V */ + continuation_e __vloxseg5ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG5EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 363); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1247; + x86::Gp ret_val_get_pow_1247 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1247, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1248; + x86::Gp ret_val_get_sew_pow_1248 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1248, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1249; + x86::Gp ret_val_get_lmul_pow_1249 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1249, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1247, ret_val_get_sew_pow_1248), ret_val_get_lmul_pow_1249)), 3, true); + setArg(call_get_pow_1247, 0, reinterpret_cast(this)); + setArg(call_get_pow_1247, 1, EEW); + setRet(call_get_pow_1247, 0, ret_val_get_pow_1247); + setArg(call_get_sew_pow_1248, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1248, 0, ret_val_get_sew_pow_1248); + setArg(call_get_lmul_pow_1249, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1249, 0, ret_val_get_lmul_pow_1249); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1251; + x86::Gp ret_val_get_lmul_pow_1251 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1251, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1250; + auto illegal_indexed_load_1250_arg4 = EMUL_pow; + auto illegal_indexed_load_1250_arg5 = ret_val_get_lmul_pow_1251; + x86::Gp ret_val_illegal_indexed_load_1250 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1250, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1250; + setArg(call_get_lmul_pow_1251, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1251, 0, ret_val_get_lmul_pow_1251); + setArg(call_illegal_indexed_load_1250, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1250, 1, vd); + setArg(call_illegal_indexed_load_1250, 2, vm); + setArg(call_illegal_indexed_load_1250, 3, 5); + setArg(call_illegal_indexed_load_1250, 4, EEW); + setArg(call_illegal_indexed_load_1250, 5, illegal_indexed_load_1250_arg4); + setArg(call_illegal_indexed_load_1250, 6, illegal_indexed_load_1250_arg5); + setRet(call_illegal_indexed_load_1250, 0, ret_val_illegal_indexed_load_1250); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1253; + x86::Gp ret_val_sew_1253 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1253, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1252; + auto vlxseg_1252_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1252_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1252_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1252_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1252_arg10 = ret_val_sew_1253; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1252 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1252, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1252, 32, false), traits::vstart); + setArg(call_sew_1253, 0, reinterpret_cast(this)); + setRet(call_sew_1253, 0, ret_val_sew_1253); + setArg(call_vlxseg_1252, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1252, 1, V); + setArg(call_vlxseg_1252, 2, vlxseg_1252_arg1); + setArg(call_vlxseg_1252, 3, vlxseg_1252_arg2); + setArg(call_vlxseg_1252, 4, vlxseg_1252_arg3); + setArg(call_vlxseg_1252, 5, vm); + setArg(call_vlxseg_1252, 6, vd); + setArg(call_vlxseg_1252, 7, vlxseg_1252_arg6); + setArg(call_vlxseg_1252, 8, vs2); + setArg(call_vlxseg_1252, 9, 5); + setArg(call_vlxseg_1252, 10, 4); + setArg(call_vlxseg_1252, 11, vlxseg_1252_arg10); + setArg(call_vlxseg_1252, 12, 1); + setRet(call_vlxseg_1252, 0, ret_val_vlxseg_1252); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 363); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 364: VLOXSEG5EI64__V */ + continuation_e __vloxseg5ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG5EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 364); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1254; + x86::Gp ret_val_get_pow_1254 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1254, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1255; + x86::Gp ret_val_get_sew_pow_1255 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1255, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1256; + x86::Gp ret_val_get_lmul_pow_1256 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1256, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1254, ret_val_get_sew_pow_1255), ret_val_get_lmul_pow_1256)), 3, true); + setArg(call_get_pow_1254, 0, reinterpret_cast(this)); + setArg(call_get_pow_1254, 1, EEW); + setRet(call_get_pow_1254, 0, ret_val_get_pow_1254); + setArg(call_get_sew_pow_1255, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1255, 0, ret_val_get_sew_pow_1255); + setArg(call_get_lmul_pow_1256, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1256, 0, ret_val_get_lmul_pow_1256); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1258; + x86::Gp ret_val_get_lmul_pow_1258 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1258, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1257; + auto illegal_indexed_load_1257_arg4 = EMUL_pow; + auto illegal_indexed_load_1257_arg5 = ret_val_get_lmul_pow_1258; + x86::Gp ret_val_illegal_indexed_load_1257 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1257, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1257; + setArg(call_get_lmul_pow_1258, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1258, 0, ret_val_get_lmul_pow_1258); + setArg(call_illegal_indexed_load_1257, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1257, 1, vd); + setArg(call_illegal_indexed_load_1257, 2, vm); + setArg(call_illegal_indexed_load_1257, 3, 5); + setArg(call_illegal_indexed_load_1257, 4, EEW); + setArg(call_illegal_indexed_load_1257, 5, illegal_indexed_load_1257_arg4); + setArg(call_illegal_indexed_load_1257, 6, illegal_indexed_load_1257_arg5); + setRet(call_illegal_indexed_load_1257, 0, ret_val_illegal_indexed_load_1257); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1260; + x86::Gp ret_val_sew_1260 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1260, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1259; + auto vlxseg_1259_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1259_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1259_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1259_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1259_arg10 = ret_val_sew_1260; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1259 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1259, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1259, 32, false), traits::vstart); + setArg(call_sew_1260, 0, reinterpret_cast(this)); + setRet(call_sew_1260, 0, ret_val_sew_1260); + setArg(call_vlxseg_1259, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1259, 1, V); + setArg(call_vlxseg_1259, 2, vlxseg_1259_arg1); + setArg(call_vlxseg_1259, 3, vlxseg_1259_arg2); + setArg(call_vlxseg_1259, 4, vlxseg_1259_arg3); + setArg(call_vlxseg_1259, 5, vm); + setArg(call_vlxseg_1259, 6, vd); + setArg(call_vlxseg_1259, 7, vlxseg_1259_arg6); + setArg(call_vlxseg_1259, 8, vs2); + setArg(call_vlxseg_1259, 9, 5); + setArg(call_vlxseg_1259, 10, 8); + setArg(call_vlxseg_1259, 11, vlxseg_1259_arg10); + setArg(call_vlxseg_1259, 12, 1); + setRet(call_vlxseg_1259, 0, ret_val_vlxseg_1259); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 364); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 365: VLOXSEG6EI8__V */ + continuation_e __vloxseg6ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG6EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 365); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1261; + x86::Gp ret_val_get_pow_1261 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1261, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1262; + x86::Gp ret_val_get_sew_pow_1262 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1262, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1263; + x86::Gp ret_val_get_lmul_pow_1263 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1263, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1261, ret_val_get_sew_pow_1262), ret_val_get_lmul_pow_1263)), 3, true); + setArg(call_get_pow_1261, 0, reinterpret_cast(this)); + setArg(call_get_pow_1261, 1, EEW); + setRet(call_get_pow_1261, 0, ret_val_get_pow_1261); + setArg(call_get_sew_pow_1262, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1262, 0, ret_val_get_sew_pow_1262); + setArg(call_get_lmul_pow_1263, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1263, 0, ret_val_get_lmul_pow_1263); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1265; + x86::Gp ret_val_get_lmul_pow_1265 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1265, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1264; + auto illegal_indexed_load_1264_arg4 = EMUL_pow; + auto illegal_indexed_load_1264_arg5 = ret_val_get_lmul_pow_1265; + x86::Gp ret_val_illegal_indexed_load_1264 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1264, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1264; + setArg(call_get_lmul_pow_1265, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1265, 0, ret_val_get_lmul_pow_1265); + setArg(call_illegal_indexed_load_1264, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1264, 1, vd); + setArg(call_illegal_indexed_load_1264, 2, vm); + setArg(call_illegal_indexed_load_1264, 3, 6); + setArg(call_illegal_indexed_load_1264, 4, EEW); + setArg(call_illegal_indexed_load_1264, 5, illegal_indexed_load_1264_arg4); + setArg(call_illegal_indexed_load_1264, 6, illegal_indexed_load_1264_arg5); + setRet(call_illegal_indexed_load_1264, 0, ret_val_illegal_indexed_load_1264); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1267; + x86::Gp ret_val_sew_1267 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1267, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1266; + auto vlxseg_1266_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1266_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1266_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1266_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1266_arg10 = ret_val_sew_1267; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1266 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1266, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1266, 32, false), traits::vstart); + setArg(call_sew_1267, 0, reinterpret_cast(this)); + setRet(call_sew_1267, 0, ret_val_sew_1267); + setArg(call_vlxseg_1266, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1266, 1, V); + setArg(call_vlxseg_1266, 2, vlxseg_1266_arg1); + setArg(call_vlxseg_1266, 3, vlxseg_1266_arg2); + setArg(call_vlxseg_1266, 4, vlxseg_1266_arg3); + setArg(call_vlxseg_1266, 5, vm); + setArg(call_vlxseg_1266, 6, vd); + setArg(call_vlxseg_1266, 7, vlxseg_1266_arg6); + setArg(call_vlxseg_1266, 8, vs2); + setArg(call_vlxseg_1266, 9, 6); + setArg(call_vlxseg_1266, 10, 1); + setArg(call_vlxseg_1266, 11, vlxseg_1266_arg10); + setArg(call_vlxseg_1266, 12, 1); + setRet(call_vlxseg_1266, 0, ret_val_vlxseg_1266); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 365); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 366: VLOXSEG6EI16__V */ + continuation_e __vloxseg6ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG6EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 366); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1268; + x86::Gp ret_val_get_pow_1268 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1268, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1269; + x86::Gp ret_val_get_sew_pow_1269 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1269, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1270; + x86::Gp ret_val_get_lmul_pow_1270 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1270, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1268, ret_val_get_sew_pow_1269), ret_val_get_lmul_pow_1270)), 3, true); + setArg(call_get_pow_1268, 0, reinterpret_cast(this)); + setArg(call_get_pow_1268, 1, EEW); + setRet(call_get_pow_1268, 0, ret_val_get_pow_1268); + setArg(call_get_sew_pow_1269, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1269, 0, ret_val_get_sew_pow_1269); + setArg(call_get_lmul_pow_1270, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1270, 0, ret_val_get_lmul_pow_1270); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1272; + x86::Gp ret_val_get_lmul_pow_1272 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1272, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1271; + auto illegal_indexed_load_1271_arg4 = EMUL_pow; + auto illegal_indexed_load_1271_arg5 = ret_val_get_lmul_pow_1272; + x86::Gp ret_val_illegal_indexed_load_1271 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1271, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1271; + setArg(call_get_lmul_pow_1272, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1272, 0, ret_val_get_lmul_pow_1272); + setArg(call_illegal_indexed_load_1271, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1271, 1, vd); + setArg(call_illegal_indexed_load_1271, 2, vm); + setArg(call_illegal_indexed_load_1271, 3, 6); + setArg(call_illegal_indexed_load_1271, 4, EEW); + setArg(call_illegal_indexed_load_1271, 5, illegal_indexed_load_1271_arg4); + setArg(call_illegal_indexed_load_1271, 6, illegal_indexed_load_1271_arg5); + setRet(call_illegal_indexed_load_1271, 0, ret_val_illegal_indexed_load_1271); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1274; + x86::Gp ret_val_sew_1274 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1274, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1273; + auto vlxseg_1273_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1273_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1273_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1273_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1273_arg10 = ret_val_sew_1274; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1273 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1273, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1273, 32, false), traits::vstart); + setArg(call_sew_1274, 0, reinterpret_cast(this)); + setRet(call_sew_1274, 0, ret_val_sew_1274); + setArg(call_vlxseg_1273, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1273, 1, V); + setArg(call_vlxseg_1273, 2, vlxseg_1273_arg1); + setArg(call_vlxseg_1273, 3, vlxseg_1273_arg2); + setArg(call_vlxseg_1273, 4, vlxseg_1273_arg3); + setArg(call_vlxseg_1273, 5, vm); + setArg(call_vlxseg_1273, 6, vd); + setArg(call_vlxseg_1273, 7, vlxseg_1273_arg6); + setArg(call_vlxseg_1273, 8, vs2); + setArg(call_vlxseg_1273, 9, 6); + setArg(call_vlxseg_1273, 10, 2); + setArg(call_vlxseg_1273, 11, vlxseg_1273_arg10); + setArg(call_vlxseg_1273, 12, 1); + setRet(call_vlxseg_1273, 0, ret_val_vlxseg_1273); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 366); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 367: VLOXSEG6EI32__V */ + continuation_e __vloxseg6ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG6EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 367); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1275; + x86::Gp ret_val_get_pow_1275 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1275, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1276; + x86::Gp ret_val_get_sew_pow_1276 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1276, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1277; + x86::Gp ret_val_get_lmul_pow_1277 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1277, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1275, ret_val_get_sew_pow_1276), ret_val_get_lmul_pow_1277)), 3, true); + setArg(call_get_pow_1275, 0, reinterpret_cast(this)); + setArg(call_get_pow_1275, 1, EEW); + setRet(call_get_pow_1275, 0, ret_val_get_pow_1275); + setArg(call_get_sew_pow_1276, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1276, 0, ret_val_get_sew_pow_1276); + setArg(call_get_lmul_pow_1277, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1277, 0, ret_val_get_lmul_pow_1277); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1279; + x86::Gp ret_val_get_lmul_pow_1279 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1279, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1278; + auto illegal_indexed_load_1278_arg4 = EMUL_pow; + auto illegal_indexed_load_1278_arg5 = ret_val_get_lmul_pow_1279; + x86::Gp ret_val_illegal_indexed_load_1278 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1278, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1278; + setArg(call_get_lmul_pow_1279, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1279, 0, ret_val_get_lmul_pow_1279); + setArg(call_illegal_indexed_load_1278, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1278, 1, vd); + setArg(call_illegal_indexed_load_1278, 2, vm); + setArg(call_illegal_indexed_load_1278, 3, 6); + setArg(call_illegal_indexed_load_1278, 4, EEW); + setArg(call_illegal_indexed_load_1278, 5, illegal_indexed_load_1278_arg4); + setArg(call_illegal_indexed_load_1278, 6, illegal_indexed_load_1278_arg5); + setRet(call_illegal_indexed_load_1278, 0, ret_val_illegal_indexed_load_1278); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1281; + x86::Gp ret_val_sew_1281 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1281, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1280; + auto vlxseg_1280_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1280_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1280_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1280_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1280_arg10 = ret_val_sew_1281; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1280 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1280, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1280, 32, false), traits::vstart); + setArg(call_sew_1281, 0, reinterpret_cast(this)); + setRet(call_sew_1281, 0, ret_val_sew_1281); + setArg(call_vlxseg_1280, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1280, 1, V); + setArg(call_vlxseg_1280, 2, vlxseg_1280_arg1); + setArg(call_vlxseg_1280, 3, vlxseg_1280_arg2); + setArg(call_vlxseg_1280, 4, vlxseg_1280_arg3); + setArg(call_vlxseg_1280, 5, vm); + setArg(call_vlxseg_1280, 6, vd); + setArg(call_vlxseg_1280, 7, vlxseg_1280_arg6); + setArg(call_vlxseg_1280, 8, vs2); + setArg(call_vlxseg_1280, 9, 6); + setArg(call_vlxseg_1280, 10, 4); + setArg(call_vlxseg_1280, 11, vlxseg_1280_arg10); + setArg(call_vlxseg_1280, 12, 1); + setRet(call_vlxseg_1280, 0, ret_val_vlxseg_1280); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 367); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 368: VLOXSEG6EI64__V */ + continuation_e __vloxseg6ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG6EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 368); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1282; + x86::Gp ret_val_get_pow_1282 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1282, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1283; + x86::Gp ret_val_get_sew_pow_1283 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1283, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1284; + x86::Gp ret_val_get_lmul_pow_1284 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1284, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1282, ret_val_get_sew_pow_1283), ret_val_get_lmul_pow_1284)), 3, true); + setArg(call_get_pow_1282, 0, reinterpret_cast(this)); + setArg(call_get_pow_1282, 1, EEW); + setRet(call_get_pow_1282, 0, ret_val_get_pow_1282); + setArg(call_get_sew_pow_1283, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1283, 0, ret_val_get_sew_pow_1283); + setArg(call_get_lmul_pow_1284, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1284, 0, ret_val_get_lmul_pow_1284); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1286; + x86::Gp ret_val_get_lmul_pow_1286 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1286, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1285; + auto illegal_indexed_load_1285_arg4 = EMUL_pow; + auto illegal_indexed_load_1285_arg5 = ret_val_get_lmul_pow_1286; + x86::Gp ret_val_illegal_indexed_load_1285 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1285, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1285; + setArg(call_get_lmul_pow_1286, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1286, 0, ret_val_get_lmul_pow_1286); + setArg(call_illegal_indexed_load_1285, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1285, 1, vd); + setArg(call_illegal_indexed_load_1285, 2, vm); + setArg(call_illegal_indexed_load_1285, 3, 6); + setArg(call_illegal_indexed_load_1285, 4, EEW); + setArg(call_illegal_indexed_load_1285, 5, illegal_indexed_load_1285_arg4); + setArg(call_illegal_indexed_load_1285, 6, illegal_indexed_load_1285_arg5); + setRet(call_illegal_indexed_load_1285, 0, ret_val_illegal_indexed_load_1285); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1288; + x86::Gp ret_val_sew_1288 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1288, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1287; + auto vlxseg_1287_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1287_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1287_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1287_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1287_arg10 = ret_val_sew_1288; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1287 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1287, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1287, 32, false), traits::vstart); + setArg(call_sew_1288, 0, reinterpret_cast(this)); + setRet(call_sew_1288, 0, ret_val_sew_1288); + setArg(call_vlxseg_1287, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1287, 1, V); + setArg(call_vlxseg_1287, 2, vlxseg_1287_arg1); + setArg(call_vlxseg_1287, 3, vlxseg_1287_arg2); + setArg(call_vlxseg_1287, 4, vlxseg_1287_arg3); + setArg(call_vlxseg_1287, 5, vm); + setArg(call_vlxseg_1287, 6, vd); + setArg(call_vlxseg_1287, 7, vlxseg_1287_arg6); + setArg(call_vlxseg_1287, 8, vs2); + setArg(call_vlxseg_1287, 9, 6); + setArg(call_vlxseg_1287, 10, 8); + setArg(call_vlxseg_1287, 11, vlxseg_1287_arg10); + setArg(call_vlxseg_1287, 12, 1); + setRet(call_vlxseg_1287, 0, ret_val_vlxseg_1287); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 368); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 369: VLOXSEG7EI8__V */ + continuation_e __vloxseg7ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG7EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 369); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1289; + x86::Gp ret_val_get_pow_1289 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1289, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1290; + x86::Gp ret_val_get_sew_pow_1290 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1290, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1291; + x86::Gp ret_val_get_lmul_pow_1291 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1291, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1289, ret_val_get_sew_pow_1290), ret_val_get_lmul_pow_1291)), 3, true); + setArg(call_get_pow_1289, 0, reinterpret_cast(this)); + setArg(call_get_pow_1289, 1, EEW); + setRet(call_get_pow_1289, 0, ret_val_get_pow_1289); + setArg(call_get_sew_pow_1290, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1290, 0, ret_val_get_sew_pow_1290); + setArg(call_get_lmul_pow_1291, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1291, 0, ret_val_get_lmul_pow_1291); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1293; + x86::Gp ret_val_get_lmul_pow_1293 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1293, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1292; + auto illegal_indexed_load_1292_arg4 = EMUL_pow; + auto illegal_indexed_load_1292_arg5 = ret_val_get_lmul_pow_1293; + x86::Gp ret_val_illegal_indexed_load_1292 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1292, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1292; + setArg(call_get_lmul_pow_1293, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1293, 0, ret_val_get_lmul_pow_1293); + setArg(call_illegal_indexed_load_1292, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1292, 1, vd); + setArg(call_illegal_indexed_load_1292, 2, vm); + setArg(call_illegal_indexed_load_1292, 3, 7); + setArg(call_illegal_indexed_load_1292, 4, EEW); + setArg(call_illegal_indexed_load_1292, 5, illegal_indexed_load_1292_arg4); + setArg(call_illegal_indexed_load_1292, 6, illegal_indexed_load_1292_arg5); + setRet(call_illegal_indexed_load_1292, 0, ret_val_illegal_indexed_load_1292); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1295; + x86::Gp ret_val_sew_1295 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1295, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1294; + auto vlxseg_1294_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1294_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1294_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1294_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1294_arg10 = ret_val_sew_1295; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1294 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1294, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1294, 32, false), traits::vstart); + setArg(call_sew_1295, 0, reinterpret_cast(this)); + setRet(call_sew_1295, 0, ret_val_sew_1295); + setArg(call_vlxseg_1294, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1294, 1, V); + setArg(call_vlxseg_1294, 2, vlxseg_1294_arg1); + setArg(call_vlxseg_1294, 3, vlxseg_1294_arg2); + setArg(call_vlxseg_1294, 4, vlxseg_1294_arg3); + setArg(call_vlxseg_1294, 5, vm); + setArg(call_vlxseg_1294, 6, vd); + setArg(call_vlxseg_1294, 7, vlxseg_1294_arg6); + setArg(call_vlxseg_1294, 8, vs2); + setArg(call_vlxseg_1294, 9, 7); + setArg(call_vlxseg_1294, 10, 1); + setArg(call_vlxseg_1294, 11, vlxseg_1294_arg10); + setArg(call_vlxseg_1294, 12, 1); + setRet(call_vlxseg_1294, 0, ret_val_vlxseg_1294); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 369); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 370: VLOXSEG7EI16__V */ + continuation_e __vloxseg7ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG7EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 370); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1296; + x86::Gp ret_val_get_pow_1296 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1296, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1297; + x86::Gp ret_val_get_sew_pow_1297 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1297, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1298; + x86::Gp ret_val_get_lmul_pow_1298 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1298, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1296, ret_val_get_sew_pow_1297), ret_val_get_lmul_pow_1298)), 3, true); + setArg(call_get_pow_1296, 0, reinterpret_cast(this)); + setArg(call_get_pow_1296, 1, EEW); + setRet(call_get_pow_1296, 0, ret_val_get_pow_1296); + setArg(call_get_sew_pow_1297, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1297, 0, ret_val_get_sew_pow_1297); + setArg(call_get_lmul_pow_1298, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1298, 0, ret_val_get_lmul_pow_1298); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1300; + x86::Gp ret_val_get_lmul_pow_1300 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1300, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1299; + auto illegal_indexed_load_1299_arg4 = EMUL_pow; + auto illegal_indexed_load_1299_arg5 = ret_val_get_lmul_pow_1300; + x86::Gp ret_val_illegal_indexed_load_1299 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1299, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1299; + setArg(call_get_lmul_pow_1300, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1300, 0, ret_val_get_lmul_pow_1300); + setArg(call_illegal_indexed_load_1299, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1299, 1, vd); + setArg(call_illegal_indexed_load_1299, 2, vm); + setArg(call_illegal_indexed_load_1299, 3, 7); + setArg(call_illegal_indexed_load_1299, 4, EEW); + setArg(call_illegal_indexed_load_1299, 5, illegal_indexed_load_1299_arg4); + setArg(call_illegal_indexed_load_1299, 6, illegal_indexed_load_1299_arg5); + setRet(call_illegal_indexed_load_1299, 0, ret_val_illegal_indexed_load_1299); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1302; + x86::Gp ret_val_sew_1302 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1302, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1301; + auto vlxseg_1301_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1301_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1301_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1301_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1301_arg10 = ret_val_sew_1302; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1301 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1301, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1301, 32, false), traits::vstart); + setArg(call_sew_1302, 0, reinterpret_cast(this)); + setRet(call_sew_1302, 0, ret_val_sew_1302); + setArg(call_vlxseg_1301, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1301, 1, V); + setArg(call_vlxseg_1301, 2, vlxseg_1301_arg1); + setArg(call_vlxseg_1301, 3, vlxseg_1301_arg2); + setArg(call_vlxseg_1301, 4, vlxseg_1301_arg3); + setArg(call_vlxseg_1301, 5, vm); + setArg(call_vlxseg_1301, 6, vd); + setArg(call_vlxseg_1301, 7, vlxseg_1301_arg6); + setArg(call_vlxseg_1301, 8, vs2); + setArg(call_vlxseg_1301, 9, 7); + setArg(call_vlxseg_1301, 10, 2); + setArg(call_vlxseg_1301, 11, vlxseg_1301_arg10); + setArg(call_vlxseg_1301, 12, 1); + setRet(call_vlxseg_1301, 0, ret_val_vlxseg_1301); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 370); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 371: VLOXSEG7EI32__V */ + continuation_e __vloxseg7ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG7EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 371); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1303; + x86::Gp ret_val_get_pow_1303 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1303, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1304; + x86::Gp ret_val_get_sew_pow_1304 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1304, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1305; + x86::Gp ret_val_get_lmul_pow_1305 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1305, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1303, ret_val_get_sew_pow_1304), ret_val_get_lmul_pow_1305)), 3, true); + setArg(call_get_pow_1303, 0, reinterpret_cast(this)); + setArg(call_get_pow_1303, 1, EEW); + setRet(call_get_pow_1303, 0, ret_val_get_pow_1303); + setArg(call_get_sew_pow_1304, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1304, 0, ret_val_get_sew_pow_1304); + setArg(call_get_lmul_pow_1305, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1305, 0, ret_val_get_lmul_pow_1305); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1307; + x86::Gp ret_val_get_lmul_pow_1307 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1307, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1306; + auto illegal_indexed_load_1306_arg4 = EMUL_pow; + auto illegal_indexed_load_1306_arg5 = ret_val_get_lmul_pow_1307; + x86::Gp ret_val_illegal_indexed_load_1306 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1306, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1306; + setArg(call_get_lmul_pow_1307, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1307, 0, ret_val_get_lmul_pow_1307); + setArg(call_illegal_indexed_load_1306, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1306, 1, vd); + setArg(call_illegal_indexed_load_1306, 2, vm); + setArg(call_illegal_indexed_load_1306, 3, 7); + setArg(call_illegal_indexed_load_1306, 4, EEW); + setArg(call_illegal_indexed_load_1306, 5, illegal_indexed_load_1306_arg4); + setArg(call_illegal_indexed_load_1306, 6, illegal_indexed_load_1306_arg5); + setRet(call_illegal_indexed_load_1306, 0, ret_val_illegal_indexed_load_1306); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1309; + x86::Gp ret_val_sew_1309 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1309, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1308; + auto vlxseg_1308_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1308_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1308_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1308_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1308_arg10 = ret_val_sew_1309; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1308 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1308, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1308, 32, false), traits::vstart); + setArg(call_sew_1309, 0, reinterpret_cast(this)); + setRet(call_sew_1309, 0, ret_val_sew_1309); + setArg(call_vlxseg_1308, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1308, 1, V); + setArg(call_vlxseg_1308, 2, vlxseg_1308_arg1); + setArg(call_vlxseg_1308, 3, vlxseg_1308_arg2); + setArg(call_vlxseg_1308, 4, vlxseg_1308_arg3); + setArg(call_vlxseg_1308, 5, vm); + setArg(call_vlxseg_1308, 6, vd); + setArg(call_vlxseg_1308, 7, vlxseg_1308_arg6); + setArg(call_vlxseg_1308, 8, vs2); + setArg(call_vlxseg_1308, 9, 7); + setArg(call_vlxseg_1308, 10, 4); + setArg(call_vlxseg_1308, 11, vlxseg_1308_arg10); + setArg(call_vlxseg_1308, 12, 1); + setRet(call_vlxseg_1308, 0, ret_val_vlxseg_1308); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 371); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 372: VLOXSEG7EI64__V */ + continuation_e __vloxseg7ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG7EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 372); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1310; + x86::Gp ret_val_get_pow_1310 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1310, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1311; + x86::Gp ret_val_get_sew_pow_1311 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1311, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1312; + x86::Gp ret_val_get_lmul_pow_1312 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1312, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1310, ret_val_get_sew_pow_1311), ret_val_get_lmul_pow_1312)), 3, true); + setArg(call_get_pow_1310, 0, reinterpret_cast(this)); + setArg(call_get_pow_1310, 1, EEW); + setRet(call_get_pow_1310, 0, ret_val_get_pow_1310); + setArg(call_get_sew_pow_1311, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1311, 0, ret_val_get_sew_pow_1311); + setArg(call_get_lmul_pow_1312, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1312, 0, ret_val_get_lmul_pow_1312); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1314; + x86::Gp ret_val_get_lmul_pow_1314 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1314, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1313; + auto illegal_indexed_load_1313_arg4 = EMUL_pow; + auto illegal_indexed_load_1313_arg5 = ret_val_get_lmul_pow_1314; + x86::Gp ret_val_illegal_indexed_load_1313 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1313, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1313; + setArg(call_get_lmul_pow_1314, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1314, 0, ret_val_get_lmul_pow_1314); + setArg(call_illegal_indexed_load_1313, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1313, 1, vd); + setArg(call_illegal_indexed_load_1313, 2, vm); + setArg(call_illegal_indexed_load_1313, 3, 7); + setArg(call_illegal_indexed_load_1313, 4, EEW); + setArg(call_illegal_indexed_load_1313, 5, illegal_indexed_load_1313_arg4); + setArg(call_illegal_indexed_load_1313, 6, illegal_indexed_load_1313_arg5); + setRet(call_illegal_indexed_load_1313, 0, ret_val_illegal_indexed_load_1313); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1316; + x86::Gp ret_val_sew_1316 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1316, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1315; + auto vlxseg_1315_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1315_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1315_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1315_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1315_arg10 = ret_val_sew_1316; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1315 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1315, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1315, 32, false), traits::vstart); + setArg(call_sew_1316, 0, reinterpret_cast(this)); + setRet(call_sew_1316, 0, ret_val_sew_1316); + setArg(call_vlxseg_1315, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1315, 1, V); + setArg(call_vlxseg_1315, 2, vlxseg_1315_arg1); + setArg(call_vlxseg_1315, 3, vlxseg_1315_arg2); + setArg(call_vlxseg_1315, 4, vlxseg_1315_arg3); + setArg(call_vlxseg_1315, 5, vm); + setArg(call_vlxseg_1315, 6, vd); + setArg(call_vlxseg_1315, 7, vlxseg_1315_arg6); + setArg(call_vlxseg_1315, 8, vs2); + setArg(call_vlxseg_1315, 9, 7); + setArg(call_vlxseg_1315, 10, 8); + setArg(call_vlxseg_1315, 11, vlxseg_1315_arg10); + setArg(call_vlxseg_1315, 12, 1); + setRet(call_vlxseg_1315, 0, ret_val_vlxseg_1315); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 372); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 373: VLOXSEG8EI8__V */ + continuation_e __vloxseg8ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG8EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 373); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1317; + x86::Gp ret_val_get_pow_1317 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1317, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1318; + x86::Gp ret_val_get_sew_pow_1318 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1318, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1319; + x86::Gp ret_val_get_lmul_pow_1319 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1319, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1317, ret_val_get_sew_pow_1318), ret_val_get_lmul_pow_1319)), 3, true); + setArg(call_get_pow_1317, 0, reinterpret_cast(this)); + setArg(call_get_pow_1317, 1, EEW); + setRet(call_get_pow_1317, 0, ret_val_get_pow_1317); + setArg(call_get_sew_pow_1318, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1318, 0, ret_val_get_sew_pow_1318); + setArg(call_get_lmul_pow_1319, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1319, 0, ret_val_get_lmul_pow_1319); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1321; + x86::Gp ret_val_get_lmul_pow_1321 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1321, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1320; + auto illegal_indexed_load_1320_arg4 = EMUL_pow; + auto illegal_indexed_load_1320_arg5 = ret_val_get_lmul_pow_1321; + x86::Gp ret_val_illegal_indexed_load_1320 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1320, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1320; + setArg(call_get_lmul_pow_1321, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1321, 0, ret_val_get_lmul_pow_1321); + setArg(call_illegal_indexed_load_1320, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1320, 1, vd); + setArg(call_illegal_indexed_load_1320, 2, vm); + setArg(call_illegal_indexed_load_1320, 3, 8); + setArg(call_illegal_indexed_load_1320, 4, EEW); + setArg(call_illegal_indexed_load_1320, 5, illegal_indexed_load_1320_arg4); + setArg(call_illegal_indexed_load_1320, 6, illegal_indexed_load_1320_arg5); + setRet(call_illegal_indexed_load_1320, 0, ret_val_illegal_indexed_load_1320); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1323; + x86::Gp ret_val_sew_1323 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1323, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1322; + auto vlxseg_1322_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1322_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1322_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1322_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1322_arg10 = ret_val_sew_1323; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1322 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1322, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1322, 32, false), traits::vstart); + setArg(call_sew_1323, 0, reinterpret_cast(this)); + setRet(call_sew_1323, 0, ret_val_sew_1323); + setArg(call_vlxseg_1322, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1322, 1, V); + setArg(call_vlxseg_1322, 2, vlxseg_1322_arg1); + setArg(call_vlxseg_1322, 3, vlxseg_1322_arg2); + setArg(call_vlxseg_1322, 4, vlxseg_1322_arg3); + setArg(call_vlxseg_1322, 5, vm); + setArg(call_vlxseg_1322, 6, vd); + setArg(call_vlxseg_1322, 7, vlxseg_1322_arg6); + setArg(call_vlxseg_1322, 8, vs2); + setArg(call_vlxseg_1322, 9, 8); + setArg(call_vlxseg_1322, 10, 1); + setArg(call_vlxseg_1322, 11, vlxseg_1322_arg10); + setArg(call_vlxseg_1322, 12, 1); + setRet(call_vlxseg_1322, 0, ret_val_vlxseg_1322); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 373); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 374: VLOXSEG8EI16__V */ + continuation_e __vloxseg8ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG8EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 374); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1324; + x86::Gp ret_val_get_pow_1324 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1324, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1325; + x86::Gp ret_val_get_sew_pow_1325 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1325, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1326; + x86::Gp ret_val_get_lmul_pow_1326 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1326, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1324, ret_val_get_sew_pow_1325), ret_val_get_lmul_pow_1326)), 3, true); + setArg(call_get_pow_1324, 0, reinterpret_cast(this)); + setArg(call_get_pow_1324, 1, EEW); + setRet(call_get_pow_1324, 0, ret_val_get_pow_1324); + setArg(call_get_sew_pow_1325, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1325, 0, ret_val_get_sew_pow_1325); + setArg(call_get_lmul_pow_1326, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1326, 0, ret_val_get_lmul_pow_1326); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1328; + x86::Gp ret_val_get_lmul_pow_1328 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1328, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1327; + auto illegal_indexed_load_1327_arg4 = EMUL_pow; + auto illegal_indexed_load_1327_arg5 = ret_val_get_lmul_pow_1328; + x86::Gp ret_val_illegal_indexed_load_1327 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1327, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1327; + setArg(call_get_lmul_pow_1328, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1328, 0, ret_val_get_lmul_pow_1328); + setArg(call_illegal_indexed_load_1327, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1327, 1, vd); + setArg(call_illegal_indexed_load_1327, 2, vm); + setArg(call_illegal_indexed_load_1327, 3, 8); + setArg(call_illegal_indexed_load_1327, 4, EEW); + setArg(call_illegal_indexed_load_1327, 5, illegal_indexed_load_1327_arg4); + setArg(call_illegal_indexed_load_1327, 6, illegal_indexed_load_1327_arg5); + setRet(call_illegal_indexed_load_1327, 0, ret_val_illegal_indexed_load_1327); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1330; + x86::Gp ret_val_sew_1330 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1330, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1329; + auto vlxseg_1329_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1329_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1329_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1329_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1329_arg10 = ret_val_sew_1330; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1329 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1329, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1329, 32, false), traits::vstart); + setArg(call_sew_1330, 0, reinterpret_cast(this)); + setRet(call_sew_1330, 0, ret_val_sew_1330); + setArg(call_vlxseg_1329, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1329, 1, V); + setArg(call_vlxseg_1329, 2, vlxseg_1329_arg1); + setArg(call_vlxseg_1329, 3, vlxseg_1329_arg2); + setArg(call_vlxseg_1329, 4, vlxseg_1329_arg3); + setArg(call_vlxseg_1329, 5, vm); + setArg(call_vlxseg_1329, 6, vd); + setArg(call_vlxseg_1329, 7, vlxseg_1329_arg6); + setArg(call_vlxseg_1329, 8, vs2); + setArg(call_vlxseg_1329, 9, 8); + setArg(call_vlxseg_1329, 10, 2); + setArg(call_vlxseg_1329, 11, vlxseg_1329_arg10); + setArg(call_vlxseg_1329, 12, 1); + setRet(call_vlxseg_1329, 0, ret_val_vlxseg_1329); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 374); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 375: VLOXSEG8EI32__V */ + continuation_e __vloxseg8ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG8EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 375); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1331; + x86::Gp ret_val_get_pow_1331 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1331, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1332; + x86::Gp ret_val_get_sew_pow_1332 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1332, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1333; + x86::Gp ret_val_get_lmul_pow_1333 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1333, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1331, ret_val_get_sew_pow_1332), ret_val_get_lmul_pow_1333)), 3, true); + setArg(call_get_pow_1331, 0, reinterpret_cast(this)); + setArg(call_get_pow_1331, 1, EEW); + setRet(call_get_pow_1331, 0, ret_val_get_pow_1331); + setArg(call_get_sew_pow_1332, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1332, 0, ret_val_get_sew_pow_1332); + setArg(call_get_lmul_pow_1333, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1333, 0, ret_val_get_lmul_pow_1333); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1335; + x86::Gp ret_val_get_lmul_pow_1335 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1335, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1334; + auto illegal_indexed_load_1334_arg4 = EMUL_pow; + auto illegal_indexed_load_1334_arg5 = ret_val_get_lmul_pow_1335; + x86::Gp ret_val_illegal_indexed_load_1334 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1334, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1334; + setArg(call_get_lmul_pow_1335, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1335, 0, ret_val_get_lmul_pow_1335); + setArg(call_illegal_indexed_load_1334, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1334, 1, vd); + setArg(call_illegal_indexed_load_1334, 2, vm); + setArg(call_illegal_indexed_load_1334, 3, 8); + setArg(call_illegal_indexed_load_1334, 4, EEW); + setArg(call_illegal_indexed_load_1334, 5, illegal_indexed_load_1334_arg4); + setArg(call_illegal_indexed_load_1334, 6, illegal_indexed_load_1334_arg5); + setRet(call_illegal_indexed_load_1334, 0, ret_val_illegal_indexed_load_1334); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1337; + x86::Gp ret_val_sew_1337 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1337, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1336; + auto vlxseg_1336_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1336_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1336_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1336_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1336_arg10 = ret_val_sew_1337; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1336 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1336, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1336, 32, false), traits::vstart); + setArg(call_sew_1337, 0, reinterpret_cast(this)); + setRet(call_sew_1337, 0, ret_val_sew_1337); + setArg(call_vlxseg_1336, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1336, 1, V); + setArg(call_vlxseg_1336, 2, vlxseg_1336_arg1); + setArg(call_vlxseg_1336, 3, vlxseg_1336_arg2); + setArg(call_vlxseg_1336, 4, vlxseg_1336_arg3); + setArg(call_vlxseg_1336, 5, vm); + setArg(call_vlxseg_1336, 6, vd); + setArg(call_vlxseg_1336, 7, vlxseg_1336_arg6); + setArg(call_vlxseg_1336, 8, vs2); + setArg(call_vlxseg_1336, 9, 8); + setArg(call_vlxseg_1336, 10, 4); + setArg(call_vlxseg_1336, 11, vlxseg_1336_arg10); + setArg(call_vlxseg_1336, 12, 1); + setRet(call_vlxseg_1336, 0, ret_val_vlxseg_1336); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 375); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 376: VLOXSEG8EI64__V */ + continuation_e __vloxseg8ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG8EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 376); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1338; + x86::Gp ret_val_get_pow_1338 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1338, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1339; + x86::Gp ret_val_get_sew_pow_1339 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1339, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1340; + x86::Gp ret_val_get_lmul_pow_1340 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1340, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1338, ret_val_get_sew_pow_1339), ret_val_get_lmul_pow_1340)), 3, true); + setArg(call_get_pow_1338, 0, reinterpret_cast(this)); + setArg(call_get_pow_1338, 1, EEW); + setRet(call_get_pow_1338, 0, ret_val_get_pow_1338); + setArg(call_get_sew_pow_1339, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1339, 0, ret_val_get_sew_pow_1339); + setArg(call_get_lmul_pow_1340, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1340, 0, ret_val_get_lmul_pow_1340); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1342; + x86::Gp ret_val_get_lmul_pow_1342 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1342, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1341; + auto illegal_indexed_load_1341_arg4 = EMUL_pow; + auto illegal_indexed_load_1341_arg5 = ret_val_get_lmul_pow_1342; + x86::Gp ret_val_illegal_indexed_load_1341 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1341, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1341; + setArg(call_get_lmul_pow_1342, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1342, 0, ret_val_get_lmul_pow_1342); + setArg(call_illegal_indexed_load_1341, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1341, 1, vd); + setArg(call_illegal_indexed_load_1341, 2, vm); + setArg(call_illegal_indexed_load_1341, 3, 8); + setArg(call_illegal_indexed_load_1341, 4, EEW); + setArg(call_illegal_indexed_load_1341, 5, illegal_indexed_load_1341_arg4); + setArg(call_illegal_indexed_load_1341, 6, illegal_indexed_load_1341_arg5); + setRet(call_illegal_indexed_load_1341, 0, ret_val_illegal_indexed_load_1341); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1344; + x86::Gp ret_val_sew_1344 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1344, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1343; + auto vlxseg_1343_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1343_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1343_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1343_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1343_arg10 = ret_val_sew_1344; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1343 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1343, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1343, 32, false), traits::vstart); + setArg(call_sew_1344, 0, reinterpret_cast(this)); + setRet(call_sew_1344, 0, ret_val_sew_1344); + setArg(call_vlxseg_1343, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1343, 1, V); + setArg(call_vlxseg_1343, 2, vlxseg_1343_arg1); + setArg(call_vlxseg_1343, 3, vlxseg_1343_arg2); + setArg(call_vlxseg_1343, 4, vlxseg_1343_arg3); + setArg(call_vlxseg_1343, 5, vm); + setArg(call_vlxseg_1343, 6, vd); + setArg(call_vlxseg_1343, 7, vlxseg_1343_arg6); + setArg(call_vlxseg_1343, 8, vs2); + setArg(call_vlxseg_1343, 9, 8); + setArg(call_vlxseg_1343, 10, 8); + setArg(call_vlxseg_1343, 11, vlxseg_1343_arg10); + setArg(call_vlxseg_1343, 12, 1); + setRet(call_vlxseg_1343, 0, ret_val_vlxseg_1343); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 376); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 377: VSOXEI8__V */ + continuation_e __vsoxei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXEI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 377); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1345; + x86::Gp ret_val_get_pow_1345 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1345, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1346; + x86::Gp ret_val_get_sew_pow_1346 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1346, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1347; + x86::Gp ret_val_get_lmul_pow_1347 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1347, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1345, ret_val_get_sew_pow_1346), ret_val_get_lmul_pow_1347)), 3, true); + setArg(call_get_pow_1345, 0, reinterpret_cast(this)); + setArg(call_get_pow_1345, 1, EEW); + setRet(call_get_pow_1345, 0, ret_val_get_pow_1345); + setArg(call_get_sew_pow_1346, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1346, 0, ret_val_get_sew_pow_1346); + setArg(call_get_lmul_pow_1347, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1347, 0, ret_val_get_lmul_pow_1347); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1349; + x86::Gp ret_val_get_lmul_pow_1349 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1349, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1348; + auto illegal_indexed_store_1348_arg2 = EMUL_pow; + auto illegal_indexed_store_1348_arg3 = ret_val_get_lmul_pow_1349; + x86::Gp ret_val_illegal_indexed_store_1348 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1348, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1348; + setArg(call_get_lmul_pow_1349, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1349, 0, ret_val_get_lmul_pow_1349); + setArg(call_illegal_indexed_store_1348, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1348, 1, 1); + setArg(call_illegal_indexed_store_1348, 2, EEW); + setArg(call_illegal_indexed_store_1348, 3, illegal_indexed_store_1348_arg2); + setArg(call_illegal_indexed_store_1348, 4, illegal_indexed_store_1348_arg3); + setRet(call_illegal_indexed_store_1348, 0, ret_val_illegal_indexed_store_1348); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1351; + x86::Gp ret_val_sew_1351 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1351, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1350; + auto vsxseg_1350_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1350_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1350_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1350_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1350_arg10 = ret_val_sew_1351; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1350 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1350, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1350, 32, false), traits::vstart); + setArg(call_sew_1351, 0, reinterpret_cast(this)); + setRet(call_sew_1351, 0, ret_val_sew_1351); + setArg(call_vsxseg_1350, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1350, 1, V); + setArg(call_vsxseg_1350, 2, vsxseg_1350_arg1); + setArg(call_vsxseg_1350, 3, vsxseg_1350_arg2); + setArg(call_vsxseg_1350, 4, vsxseg_1350_arg3); + setArg(call_vsxseg_1350, 5, vm); + setArg(call_vsxseg_1350, 6, vs3); + setArg(call_vsxseg_1350, 7, vsxseg_1350_arg6); + setArg(call_vsxseg_1350, 8, vs2); + setArg(call_vsxseg_1350, 9, 1); + setArg(call_vsxseg_1350, 10, 1); + setArg(call_vsxseg_1350, 11, vsxseg_1350_arg10); + setArg(call_vsxseg_1350, 12, 1); + setRet(call_vsxseg_1350, 0, ret_val_vsxseg_1350); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 377); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 378: VSOXEI16__V */ + continuation_e __vsoxei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXEI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 378); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1352; + x86::Gp ret_val_get_pow_1352 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1352, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1353; + x86::Gp ret_val_get_sew_pow_1353 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1353, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1354; + x86::Gp ret_val_get_lmul_pow_1354 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1354, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1352, ret_val_get_sew_pow_1353), ret_val_get_lmul_pow_1354)), 3, true); + setArg(call_get_pow_1352, 0, reinterpret_cast(this)); + setArg(call_get_pow_1352, 1, EEW); + setRet(call_get_pow_1352, 0, ret_val_get_pow_1352); + setArg(call_get_sew_pow_1353, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1353, 0, ret_val_get_sew_pow_1353); + setArg(call_get_lmul_pow_1354, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1354, 0, ret_val_get_lmul_pow_1354); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1356; + x86::Gp ret_val_get_lmul_pow_1356 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1356, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1355; + auto illegal_indexed_store_1355_arg2 = EMUL_pow; + auto illegal_indexed_store_1355_arg3 = ret_val_get_lmul_pow_1356; + x86::Gp ret_val_illegal_indexed_store_1355 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1355, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1355; + setArg(call_get_lmul_pow_1356, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1356, 0, ret_val_get_lmul_pow_1356); + setArg(call_illegal_indexed_store_1355, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1355, 1, 1); + setArg(call_illegal_indexed_store_1355, 2, EEW); + setArg(call_illegal_indexed_store_1355, 3, illegal_indexed_store_1355_arg2); + setArg(call_illegal_indexed_store_1355, 4, illegal_indexed_store_1355_arg3); + setRet(call_illegal_indexed_store_1355, 0, ret_val_illegal_indexed_store_1355); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1358; + x86::Gp ret_val_sew_1358 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1358, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1357; + auto vsxseg_1357_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1357_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1357_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1357_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1357_arg10 = ret_val_sew_1358; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1357 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1357, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1357, 32, false), traits::vstart); + setArg(call_sew_1358, 0, reinterpret_cast(this)); + setRet(call_sew_1358, 0, ret_val_sew_1358); + setArg(call_vsxseg_1357, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1357, 1, V); + setArg(call_vsxseg_1357, 2, vsxseg_1357_arg1); + setArg(call_vsxseg_1357, 3, vsxseg_1357_arg2); + setArg(call_vsxseg_1357, 4, vsxseg_1357_arg3); + setArg(call_vsxseg_1357, 5, vm); + setArg(call_vsxseg_1357, 6, vs3); + setArg(call_vsxseg_1357, 7, vsxseg_1357_arg6); + setArg(call_vsxseg_1357, 8, vs2); + setArg(call_vsxseg_1357, 9, 1); + setArg(call_vsxseg_1357, 10, 2); + setArg(call_vsxseg_1357, 11, vsxseg_1357_arg10); + setArg(call_vsxseg_1357, 12, 1); + setRet(call_vsxseg_1357, 0, ret_val_vsxseg_1357); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 378); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 379: VSOXEI32__V */ + continuation_e __vsoxei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXEI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 379); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1359; + x86::Gp ret_val_get_pow_1359 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1359, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1360; + x86::Gp ret_val_get_sew_pow_1360 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1360, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1361; + x86::Gp ret_val_get_lmul_pow_1361 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1361, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1359, ret_val_get_sew_pow_1360), ret_val_get_lmul_pow_1361)), 3, true); + setArg(call_get_pow_1359, 0, reinterpret_cast(this)); + setArg(call_get_pow_1359, 1, EEW); + setRet(call_get_pow_1359, 0, ret_val_get_pow_1359); + setArg(call_get_sew_pow_1360, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1360, 0, ret_val_get_sew_pow_1360); + setArg(call_get_lmul_pow_1361, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1361, 0, ret_val_get_lmul_pow_1361); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1363; + x86::Gp ret_val_get_lmul_pow_1363 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1363, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1362; + auto illegal_indexed_store_1362_arg2 = EMUL_pow; + auto illegal_indexed_store_1362_arg3 = ret_val_get_lmul_pow_1363; + x86::Gp ret_val_illegal_indexed_store_1362 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1362, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1362; + setArg(call_get_lmul_pow_1363, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1363, 0, ret_val_get_lmul_pow_1363); + setArg(call_illegal_indexed_store_1362, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1362, 1, 1); + setArg(call_illegal_indexed_store_1362, 2, EEW); + setArg(call_illegal_indexed_store_1362, 3, illegal_indexed_store_1362_arg2); + setArg(call_illegal_indexed_store_1362, 4, illegal_indexed_store_1362_arg3); + setRet(call_illegal_indexed_store_1362, 0, ret_val_illegal_indexed_store_1362); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1365; + x86::Gp ret_val_sew_1365 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1365, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1364; + auto vsxseg_1364_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1364_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1364_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1364_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1364_arg10 = ret_val_sew_1365; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1364 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1364, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1364, 32, false), traits::vstart); + setArg(call_sew_1365, 0, reinterpret_cast(this)); + setRet(call_sew_1365, 0, ret_val_sew_1365); + setArg(call_vsxseg_1364, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1364, 1, V); + setArg(call_vsxseg_1364, 2, vsxseg_1364_arg1); + setArg(call_vsxseg_1364, 3, vsxseg_1364_arg2); + setArg(call_vsxseg_1364, 4, vsxseg_1364_arg3); + setArg(call_vsxseg_1364, 5, vm); + setArg(call_vsxseg_1364, 6, vs3); + setArg(call_vsxseg_1364, 7, vsxseg_1364_arg6); + setArg(call_vsxseg_1364, 8, vs2); + setArg(call_vsxseg_1364, 9, 1); + setArg(call_vsxseg_1364, 10, 4); + setArg(call_vsxseg_1364, 11, vsxseg_1364_arg10); + setArg(call_vsxseg_1364, 12, 1); + setRet(call_vsxseg_1364, 0, ret_val_vsxseg_1364); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 379); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 380: VSOXEI64__V */ + continuation_e __vsoxei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXEI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 380); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1366; + x86::Gp ret_val_get_pow_1366 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1366, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1367; + x86::Gp ret_val_get_sew_pow_1367 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1367, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1368; + x86::Gp ret_val_get_lmul_pow_1368 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1368, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1366, ret_val_get_sew_pow_1367), ret_val_get_lmul_pow_1368)), 3, true); + setArg(call_get_pow_1366, 0, reinterpret_cast(this)); + setArg(call_get_pow_1366, 1, EEW); + setRet(call_get_pow_1366, 0, ret_val_get_pow_1366); + setArg(call_get_sew_pow_1367, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1367, 0, ret_val_get_sew_pow_1367); + setArg(call_get_lmul_pow_1368, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1368, 0, ret_val_get_lmul_pow_1368); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1370; + x86::Gp ret_val_get_lmul_pow_1370 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1370, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1369; + auto illegal_indexed_store_1369_arg2 = EMUL_pow; + auto illegal_indexed_store_1369_arg3 = ret_val_get_lmul_pow_1370; + x86::Gp ret_val_illegal_indexed_store_1369 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1369, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1369; + setArg(call_get_lmul_pow_1370, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1370, 0, ret_val_get_lmul_pow_1370); + setArg(call_illegal_indexed_store_1369, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1369, 1, 1); + setArg(call_illegal_indexed_store_1369, 2, EEW); + setArg(call_illegal_indexed_store_1369, 3, illegal_indexed_store_1369_arg2); + setArg(call_illegal_indexed_store_1369, 4, illegal_indexed_store_1369_arg3); + setRet(call_illegal_indexed_store_1369, 0, ret_val_illegal_indexed_store_1369); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1372; + x86::Gp ret_val_sew_1372 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1372, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1371; + auto vsxseg_1371_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1371_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1371_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1371_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1371_arg10 = ret_val_sew_1372; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1371 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1371, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1371, 32, false), traits::vstart); + setArg(call_sew_1372, 0, reinterpret_cast(this)); + setRet(call_sew_1372, 0, ret_val_sew_1372); + setArg(call_vsxseg_1371, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1371, 1, V); + setArg(call_vsxseg_1371, 2, vsxseg_1371_arg1); + setArg(call_vsxseg_1371, 3, vsxseg_1371_arg2); + setArg(call_vsxseg_1371, 4, vsxseg_1371_arg3); + setArg(call_vsxseg_1371, 5, vm); + setArg(call_vsxseg_1371, 6, vs3); + setArg(call_vsxseg_1371, 7, vsxseg_1371_arg6); + setArg(call_vsxseg_1371, 8, vs2); + setArg(call_vsxseg_1371, 9, 1); + setArg(call_vsxseg_1371, 10, 8); + setArg(call_vsxseg_1371, 11, vsxseg_1371_arg10); + setArg(call_vsxseg_1371, 12, 1); + setRet(call_vsxseg_1371, 0, ret_val_vsxseg_1371); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 380); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 381: VSOXSEG2EI8__V */ + continuation_e __vsoxseg2ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG2EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 381); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1373; + x86::Gp ret_val_get_pow_1373 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1373, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1374; + x86::Gp ret_val_get_sew_pow_1374 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1374, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1375; + x86::Gp ret_val_get_lmul_pow_1375 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1375, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1373, ret_val_get_sew_pow_1374), ret_val_get_lmul_pow_1375)), 3, true); + setArg(call_get_pow_1373, 0, reinterpret_cast(this)); + setArg(call_get_pow_1373, 1, EEW); + setRet(call_get_pow_1373, 0, ret_val_get_pow_1373); + setArg(call_get_sew_pow_1374, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1374, 0, ret_val_get_sew_pow_1374); + setArg(call_get_lmul_pow_1375, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1375, 0, ret_val_get_lmul_pow_1375); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1377; + x86::Gp ret_val_get_lmul_pow_1377 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1377, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1376; + auto illegal_indexed_store_1376_arg2 = EMUL_pow; + auto illegal_indexed_store_1376_arg3 = ret_val_get_lmul_pow_1377; + x86::Gp ret_val_illegal_indexed_store_1376 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1376, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1376; + setArg(call_get_lmul_pow_1377, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1377, 0, ret_val_get_lmul_pow_1377); + setArg(call_illegal_indexed_store_1376, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1376, 1, 2); + setArg(call_illegal_indexed_store_1376, 2, EEW); + setArg(call_illegal_indexed_store_1376, 3, illegal_indexed_store_1376_arg2); + setArg(call_illegal_indexed_store_1376, 4, illegal_indexed_store_1376_arg3); + setRet(call_illegal_indexed_store_1376, 0, ret_val_illegal_indexed_store_1376); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1379; + x86::Gp ret_val_sew_1379 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1379, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1378; + auto vsxseg_1378_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1378_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1378_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1378_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1378_arg10 = ret_val_sew_1379; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1378 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1378, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1378, 32, false), traits::vstart); + setArg(call_sew_1379, 0, reinterpret_cast(this)); + setRet(call_sew_1379, 0, ret_val_sew_1379); + setArg(call_vsxseg_1378, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1378, 1, V); + setArg(call_vsxseg_1378, 2, vsxseg_1378_arg1); + setArg(call_vsxseg_1378, 3, vsxseg_1378_arg2); + setArg(call_vsxseg_1378, 4, vsxseg_1378_arg3); + setArg(call_vsxseg_1378, 5, vm); + setArg(call_vsxseg_1378, 6, vs3); + setArg(call_vsxseg_1378, 7, vsxseg_1378_arg6); + setArg(call_vsxseg_1378, 8, vs2); + setArg(call_vsxseg_1378, 9, 2); + setArg(call_vsxseg_1378, 10, 1); + setArg(call_vsxseg_1378, 11, vsxseg_1378_arg10); + setArg(call_vsxseg_1378, 12, 1); + setRet(call_vsxseg_1378, 0, ret_val_vsxseg_1378); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 381); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 382: VSOXSEG2EI16__V */ + continuation_e __vsoxseg2ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG2EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 382); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1380; + x86::Gp ret_val_get_pow_1380 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1380, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1381; + x86::Gp ret_val_get_sew_pow_1381 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1381, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1382; + x86::Gp ret_val_get_lmul_pow_1382 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1382, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1380, ret_val_get_sew_pow_1381), ret_val_get_lmul_pow_1382)), 3, true); + setArg(call_get_pow_1380, 0, reinterpret_cast(this)); + setArg(call_get_pow_1380, 1, EEW); + setRet(call_get_pow_1380, 0, ret_val_get_pow_1380); + setArg(call_get_sew_pow_1381, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1381, 0, ret_val_get_sew_pow_1381); + setArg(call_get_lmul_pow_1382, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1382, 0, ret_val_get_lmul_pow_1382); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1384; + x86::Gp ret_val_get_lmul_pow_1384 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1384, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1383; + auto illegal_indexed_store_1383_arg2 = EMUL_pow; + auto illegal_indexed_store_1383_arg3 = ret_val_get_lmul_pow_1384; + x86::Gp ret_val_illegal_indexed_store_1383 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1383, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1383; + setArg(call_get_lmul_pow_1384, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1384, 0, ret_val_get_lmul_pow_1384); + setArg(call_illegal_indexed_store_1383, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1383, 1, 2); + setArg(call_illegal_indexed_store_1383, 2, EEW); + setArg(call_illegal_indexed_store_1383, 3, illegal_indexed_store_1383_arg2); + setArg(call_illegal_indexed_store_1383, 4, illegal_indexed_store_1383_arg3); + setRet(call_illegal_indexed_store_1383, 0, ret_val_illegal_indexed_store_1383); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1386; + x86::Gp ret_val_sew_1386 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1386, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1385; + auto vsxseg_1385_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1385_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1385_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1385_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1385_arg10 = ret_val_sew_1386; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1385 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1385, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1385, 32, false), traits::vstart); + setArg(call_sew_1386, 0, reinterpret_cast(this)); + setRet(call_sew_1386, 0, ret_val_sew_1386); + setArg(call_vsxseg_1385, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1385, 1, V); + setArg(call_vsxseg_1385, 2, vsxseg_1385_arg1); + setArg(call_vsxseg_1385, 3, vsxseg_1385_arg2); + setArg(call_vsxseg_1385, 4, vsxseg_1385_arg3); + setArg(call_vsxseg_1385, 5, vm); + setArg(call_vsxseg_1385, 6, vs3); + setArg(call_vsxseg_1385, 7, vsxseg_1385_arg6); + setArg(call_vsxseg_1385, 8, vs2); + setArg(call_vsxseg_1385, 9, 2); + setArg(call_vsxseg_1385, 10, 2); + setArg(call_vsxseg_1385, 11, vsxseg_1385_arg10); + setArg(call_vsxseg_1385, 12, 1); + setRet(call_vsxseg_1385, 0, ret_val_vsxseg_1385); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 382); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 383: VSOXSEG2EI32__V */ + continuation_e __vsoxseg2ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG2EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 383); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1387; + x86::Gp ret_val_get_pow_1387 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1387, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1388; + x86::Gp ret_val_get_sew_pow_1388 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1388, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1389; + x86::Gp ret_val_get_lmul_pow_1389 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1389, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1387, ret_val_get_sew_pow_1388), ret_val_get_lmul_pow_1389)), 3, true); + setArg(call_get_pow_1387, 0, reinterpret_cast(this)); + setArg(call_get_pow_1387, 1, EEW); + setRet(call_get_pow_1387, 0, ret_val_get_pow_1387); + setArg(call_get_sew_pow_1388, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1388, 0, ret_val_get_sew_pow_1388); + setArg(call_get_lmul_pow_1389, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1389, 0, ret_val_get_lmul_pow_1389); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1391; + x86::Gp ret_val_get_lmul_pow_1391 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1391, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1390; + auto illegal_indexed_store_1390_arg2 = EMUL_pow; + auto illegal_indexed_store_1390_arg3 = ret_val_get_lmul_pow_1391; + x86::Gp ret_val_illegal_indexed_store_1390 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1390, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1390; + setArg(call_get_lmul_pow_1391, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1391, 0, ret_val_get_lmul_pow_1391); + setArg(call_illegal_indexed_store_1390, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1390, 1, 2); + setArg(call_illegal_indexed_store_1390, 2, EEW); + setArg(call_illegal_indexed_store_1390, 3, illegal_indexed_store_1390_arg2); + setArg(call_illegal_indexed_store_1390, 4, illegal_indexed_store_1390_arg3); + setRet(call_illegal_indexed_store_1390, 0, ret_val_illegal_indexed_store_1390); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1393; + x86::Gp ret_val_sew_1393 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1393, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1392; + auto vsxseg_1392_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1392_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1392_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1392_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1392_arg10 = ret_val_sew_1393; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1392 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1392, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1392, 32, false), traits::vstart); + setArg(call_sew_1393, 0, reinterpret_cast(this)); + setRet(call_sew_1393, 0, ret_val_sew_1393); + setArg(call_vsxseg_1392, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1392, 1, V); + setArg(call_vsxseg_1392, 2, vsxseg_1392_arg1); + setArg(call_vsxseg_1392, 3, vsxseg_1392_arg2); + setArg(call_vsxseg_1392, 4, vsxseg_1392_arg3); + setArg(call_vsxseg_1392, 5, vm); + setArg(call_vsxseg_1392, 6, vs3); + setArg(call_vsxseg_1392, 7, vsxseg_1392_arg6); + setArg(call_vsxseg_1392, 8, vs2); + setArg(call_vsxseg_1392, 9, 2); + setArg(call_vsxseg_1392, 10, 4); + setArg(call_vsxseg_1392, 11, vsxseg_1392_arg10); + setArg(call_vsxseg_1392, 12, 1); + setRet(call_vsxseg_1392, 0, ret_val_vsxseg_1392); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 383); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 384: VSOXSEG2EI64__V */ + continuation_e __vsoxseg2ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG2EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 384); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1394; + x86::Gp ret_val_get_pow_1394 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1394, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1395; + x86::Gp ret_val_get_sew_pow_1395 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1395, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1396; + x86::Gp ret_val_get_lmul_pow_1396 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1396, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1394, ret_val_get_sew_pow_1395), ret_val_get_lmul_pow_1396)), 3, true); + setArg(call_get_pow_1394, 0, reinterpret_cast(this)); + setArg(call_get_pow_1394, 1, EEW); + setRet(call_get_pow_1394, 0, ret_val_get_pow_1394); + setArg(call_get_sew_pow_1395, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1395, 0, ret_val_get_sew_pow_1395); + setArg(call_get_lmul_pow_1396, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1396, 0, ret_val_get_lmul_pow_1396); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1398; + x86::Gp ret_val_get_lmul_pow_1398 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1398, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1397; + auto illegal_indexed_store_1397_arg2 = EMUL_pow; + auto illegal_indexed_store_1397_arg3 = ret_val_get_lmul_pow_1398; + x86::Gp ret_val_illegal_indexed_store_1397 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1397, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1397; + setArg(call_get_lmul_pow_1398, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1398, 0, ret_val_get_lmul_pow_1398); + setArg(call_illegal_indexed_store_1397, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1397, 1, 2); + setArg(call_illegal_indexed_store_1397, 2, EEW); + setArg(call_illegal_indexed_store_1397, 3, illegal_indexed_store_1397_arg2); + setArg(call_illegal_indexed_store_1397, 4, illegal_indexed_store_1397_arg3); + setRet(call_illegal_indexed_store_1397, 0, ret_val_illegal_indexed_store_1397); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1400; + x86::Gp ret_val_sew_1400 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1400, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1399; + auto vsxseg_1399_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1399_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1399_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1399_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1399_arg10 = ret_val_sew_1400; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1399 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1399, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1399, 32, false), traits::vstart); + setArg(call_sew_1400, 0, reinterpret_cast(this)); + setRet(call_sew_1400, 0, ret_val_sew_1400); + setArg(call_vsxseg_1399, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1399, 1, V); + setArg(call_vsxseg_1399, 2, vsxseg_1399_arg1); + setArg(call_vsxseg_1399, 3, vsxseg_1399_arg2); + setArg(call_vsxseg_1399, 4, vsxseg_1399_arg3); + setArg(call_vsxseg_1399, 5, vm); + setArg(call_vsxseg_1399, 6, vs3); + setArg(call_vsxseg_1399, 7, vsxseg_1399_arg6); + setArg(call_vsxseg_1399, 8, vs2); + setArg(call_vsxseg_1399, 9, 2); + setArg(call_vsxseg_1399, 10, 8); + setArg(call_vsxseg_1399, 11, vsxseg_1399_arg10); + setArg(call_vsxseg_1399, 12, 1); + setRet(call_vsxseg_1399, 0, ret_val_vsxseg_1399); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 384); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 385: VSOXSEG3EI8__V */ + continuation_e __vsoxseg3ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG3EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 385); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1401; + x86::Gp ret_val_get_pow_1401 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1401, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1402; + x86::Gp ret_val_get_sew_pow_1402 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1402, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1403; + x86::Gp ret_val_get_lmul_pow_1403 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1403, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1401, ret_val_get_sew_pow_1402), ret_val_get_lmul_pow_1403)), 3, true); + setArg(call_get_pow_1401, 0, reinterpret_cast(this)); + setArg(call_get_pow_1401, 1, EEW); + setRet(call_get_pow_1401, 0, ret_val_get_pow_1401); + setArg(call_get_sew_pow_1402, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1402, 0, ret_val_get_sew_pow_1402); + setArg(call_get_lmul_pow_1403, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1403, 0, ret_val_get_lmul_pow_1403); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1405; + x86::Gp ret_val_get_lmul_pow_1405 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1405, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1404; + auto illegal_indexed_store_1404_arg2 = EMUL_pow; + auto illegal_indexed_store_1404_arg3 = ret_val_get_lmul_pow_1405; + x86::Gp ret_val_illegal_indexed_store_1404 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1404, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1404; + setArg(call_get_lmul_pow_1405, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1405, 0, ret_val_get_lmul_pow_1405); + setArg(call_illegal_indexed_store_1404, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1404, 1, 3); + setArg(call_illegal_indexed_store_1404, 2, EEW); + setArg(call_illegal_indexed_store_1404, 3, illegal_indexed_store_1404_arg2); + setArg(call_illegal_indexed_store_1404, 4, illegal_indexed_store_1404_arg3); + setRet(call_illegal_indexed_store_1404, 0, ret_val_illegal_indexed_store_1404); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1407; + x86::Gp ret_val_sew_1407 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1407, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1406; + auto vsxseg_1406_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1406_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1406_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1406_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1406_arg10 = ret_val_sew_1407; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1406 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1406, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1406, 32, false), traits::vstart); + setArg(call_sew_1407, 0, reinterpret_cast(this)); + setRet(call_sew_1407, 0, ret_val_sew_1407); + setArg(call_vsxseg_1406, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1406, 1, V); + setArg(call_vsxseg_1406, 2, vsxseg_1406_arg1); + setArg(call_vsxseg_1406, 3, vsxseg_1406_arg2); + setArg(call_vsxseg_1406, 4, vsxseg_1406_arg3); + setArg(call_vsxseg_1406, 5, vm); + setArg(call_vsxseg_1406, 6, vs3); + setArg(call_vsxseg_1406, 7, vsxseg_1406_arg6); + setArg(call_vsxseg_1406, 8, vs2); + setArg(call_vsxseg_1406, 9, 3); + setArg(call_vsxseg_1406, 10, 1); + setArg(call_vsxseg_1406, 11, vsxseg_1406_arg10); + setArg(call_vsxseg_1406, 12, 1); + setRet(call_vsxseg_1406, 0, ret_val_vsxseg_1406); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 385); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 386: VSOXSEG3EI16__V */ + continuation_e __vsoxseg3ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG3EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 386); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1408; + x86::Gp ret_val_get_pow_1408 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1408, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1409; + x86::Gp ret_val_get_sew_pow_1409 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1409, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1410; + x86::Gp ret_val_get_lmul_pow_1410 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1410, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1408, ret_val_get_sew_pow_1409), ret_val_get_lmul_pow_1410)), 3, true); + setArg(call_get_pow_1408, 0, reinterpret_cast(this)); + setArg(call_get_pow_1408, 1, EEW); + setRet(call_get_pow_1408, 0, ret_val_get_pow_1408); + setArg(call_get_sew_pow_1409, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1409, 0, ret_val_get_sew_pow_1409); + setArg(call_get_lmul_pow_1410, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1410, 0, ret_val_get_lmul_pow_1410); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1412; + x86::Gp ret_val_get_lmul_pow_1412 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1412, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1411; + auto illegal_indexed_store_1411_arg2 = EMUL_pow; + auto illegal_indexed_store_1411_arg3 = ret_val_get_lmul_pow_1412; + x86::Gp ret_val_illegal_indexed_store_1411 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1411, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1411; + setArg(call_get_lmul_pow_1412, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1412, 0, ret_val_get_lmul_pow_1412); + setArg(call_illegal_indexed_store_1411, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1411, 1, 3); + setArg(call_illegal_indexed_store_1411, 2, EEW); + setArg(call_illegal_indexed_store_1411, 3, illegal_indexed_store_1411_arg2); + setArg(call_illegal_indexed_store_1411, 4, illegal_indexed_store_1411_arg3); + setRet(call_illegal_indexed_store_1411, 0, ret_val_illegal_indexed_store_1411); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1414; + x86::Gp ret_val_sew_1414 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1414, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1413; + auto vsxseg_1413_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1413_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1413_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1413_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1413_arg10 = ret_val_sew_1414; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1413 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1413, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1413, 32, false), traits::vstart); + setArg(call_sew_1414, 0, reinterpret_cast(this)); + setRet(call_sew_1414, 0, ret_val_sew_1414); + setArg(call_vsxseg_1413, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1413, 1, V); + setArg(call_vsxseg_1413, 2, vsxseg_1413_arg1); + setArg(call_vsxseg_1413, 3, vsxseg_1413_arg2); + setArg(call_vsxseg_1413, 4, vsxseg_1413_arg3); + setArg(call_vsxseg_1413, 5, vm); + setArg(call_vsxseg_1413, 6, vs3); + setArg(call_vsxseg_1413, 7, vsxseg_1413_arg6); + setArg(call_vsxseg_1413, 8, vs2); + setArg(call_vsxseg_1413, 9, 3); + setArg(call_vsxseg_1413, 10, 2); + setArg(call_vsxseg_1413, 11, vsxseg_1413_arg10); + setArg(call_vsxseg_1413, 12, 1); + setRet(call_vsxseg_1413, 0, ret_val_vsxseg_1413); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 386); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 387: VSOXSEG3EI32__V */ + continuation_e __vsoxseg3ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG3EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 387); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1415; + x86::Gp ret_val_get_pow_1415 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1415, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1416; + x86::Gp ret_val_get_sew_pow_1416 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1416, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1417; + x86::Gp ret_val_get_lmul_pow_1417 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1417, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1415, ret_val_get_sew_pow_1416), ret_val_get_lmul_pow_1417)), 3, true); + setArg(call_get_pow_1415, 0, reinterpret_cast(this)); + setArg(call_get_pow_1415, 1, EEW); + setRet(call_get_pow_1415, 0, ret_val_get_pow_1415); + setArg(call_get_sew_pow_1416, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1416, 0, ret_val_get_sew_pow_1416); + setArg(call_get_lmul_pow_1417, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1417, 0, ret_val_get_lmul_pow_1417); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1419; + x86::Gp ret_val_get_lmul_pow_1419 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1419, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1418; + auto illegal_indexed_store_1418_arg2 = EMUL_pow; + auto illegal_indexed_store_1418_arg3 = ret_val_get_lmul_pow_1419; + x86::Gp ret_val_illegal_indexed_store_1418 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1418, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1418; + setArg(call_get_lmul_pow_1419, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1419, 0, ret_val_get_lmul_pow_1419); + setArg(call_illegal_indexed_store_1418, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1418, 1, 3); + setArg(call_illegal_indexed_store_1418, 2, EEW); + setArg(call_illegal_indexed_store_1418, 3, illegal_indexed_store_1418_arg2); + setArg(call_illegal_indexed_store_1418, 4, illegal_indexed_store_1418_arg3); + setRet(call_illegal_indexed_store_1418, 0, ret_val_illegal_indexed_store_1418); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1421; + x86::Gp ret_val_sew_1421 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1421, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1420; + auto vsxseg_1420_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1420_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1420_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1420_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1420_arg10 = ret_val_sew_1421; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1420 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1420, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1420, 32, false), traits::vstart); + setArg(call_sew_1421, 0, reinterpret_cast(this)); + setRet(call_sew_1421, 0, ret_val_sew_1421); + setArg(call_vsxseg_1420, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1420, 1, V); + setArg(call_vsxseg_1420, 2, vsxseg_1420_arg1); + setArg(call_vsxseg_1420, 3, vsxseg_1420_arg2); + setArg(call_vsxseg_1420, 4, vsxseg_1420_arg3); + setArg(call_vsxseg_1420, 5, vm); + setArg(call_vsxseg_1420, 6, vs3); + setArg(call_vsxseg_1420, 7, vsxseg_1420_arg6); + setArg(call_vsxseg_1420, 8, vs2); + setArg(call_vsxseg_1420, 9, 3); + setArg(call_vsxseg_1420, 10, 4); + setArg(call_vsxseg_1420, 11, vsxseg_1420_arg10); + setArg(call_vsxseg_1420, 12, 1); + setRet(call_vsxseg_1420, 0, ret_val_vsxseg_1420); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 387); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 388: VSOXSEG3EI64__V */ + continuation_e __vsoxseg3ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG3EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 388); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1422; + x86::Gp ret_val_get_pow_1422 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1422, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1423; + x86::Gp ret_val_get_sew_pow_1423 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1423, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1424; + x86::Gp ret_val_get_lmul_pow_1424 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1424, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1422, ret_val_get_sew_pow_1423), ret_val_get_lmul_pow_1424)), 3, true); + setArg(call_get_pow_1422, 0, reinterpret_cast(this)); + setArg(call_get_pow_1422, 1, EEW); + setRet(call_get_pow_1422, 0, ret_val_get_pow_1422); + setArg(call_get_sew_pow_1423, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1423, 0, ret_val_get_sew_pow_1423); + setArg(call_get_lmul_pow_1424, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1424, 0, ret_val_get_lmul_pow_1424); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1426; + x86::Gp ret_val_get_lmul_pow_1426 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1426, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1425; + auto illegal_indexed_store_1425_arg2 = EMUL_pow; + auto illegal_indexed_store_1425_arg3 = ret_val_get_lmul_pow_1426; + x86::Gp ret_val_illegal_indexed_store_1425 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1425, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1425; + setArg(call_get_lmul_pow_1426, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1426, 0, ret_val_get_lmul_pow_1426); + setArg(call_illegal_indexed_store_1425, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1425, 1, 3); + setArg(call_illegal_indexed_store_1425, 2, EEW); + setArg(call_illegal_indexed_store_1425, 3, illegal_indexed_store_1425_arg2); + setArg(call_illegal_indexed_store_1425, 4, illegal_indexed_store_1425_arg3); + setRet(call_illegal_indexed_store_1425, 0, ret_val_illegal_indexed_store_1425); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1428; + x86::Gp ret_val_sew_1428 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1428, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1427; + auto vsxseg_1427_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1427_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1427_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1427_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1427_arg10 = ret_val_sew_1428; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1427 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1427, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1427, 32, false), traits::vstart); + setArg(call_sew_1428, 0, reinterpret_cast(this)); + setRet(call_sew_1428, 0, ret_val_sew_1428); + setArg(call_vsxseg_1427, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1427, 1, V); + setArg(call_vsxseg_1427, 2, vsxseg_1427_arg1); + setArg(call_vsxseg_1427, 3, vsxseg_1427_arg2); + setArg(call_vsxseg_1427, 4, vsxseg_1427_arg3); + setArg(call_vsxseg_1427, 5, vm); + setArg(call_vsxseg_1427, 6, vs3); + setArg(call_vsxseg_1427, 7, vsxseg_1427_arg6); + setArg(call_vsxseg_1427, 8, vs2); + setArg(call_vsxseg_1427, 9, 3); + setArg(call_vsxseg_1427, 10, 8); + setArg(call_vsxseg_1427, 11, vsxseg_1427_arg10); + setArg(call_vsxseg_1427, 12, 1); + setRet(call_vsxseg_1427, 0, ret_val_vsxseg_1427); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 388); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 389: VSOXSEG4EI8__V */ + continuation_e __vsoxseg4ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG4EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 389); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1429; + x86::Gp ret_val_get_pow_1429 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1429, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1430; + x86::Gp ret_val_get_sew_pow_1430 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1430, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1431; + x86::Gp ret_val_get_lmul_pow_1431 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1431, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1429, ret_val_get_sew_pow_1430), ret_val_get_lmul_pow_1431)), 3, true); + setArg(call_get_pow_1429, 0, reinterpret_cast(this)); + setArg(call_get_pow_1429, 1, EEW); + setRet(call_get_pow_1429, 0, ret_val_get_pow_1429); + setArg(call_get_sew_pow_1430, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1430, 0, ret_val_get_sew_pow_1430); + setArg(call_get_lmul_pow_1431, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1431, 0, ret_val_get_lmul_pow_1431); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1433; + x86::Gp ret_val_get_lmul_pow_1433 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1433, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1432; + auto illegal_indexed_store_1432_arg2 = EMUL_pow; + auto illegal_indexed_store_1432_arg3 = ret_val_get_lmul_pow_1433; + x86::Gp ret_val_illegal_indexed_store_1432 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1432, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1432; + setArg(call_get_lmul_pow_1433, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1433, 0, ret_val_get_lmul_pow_1433); + setArg(call_illegal_indexed_store_1432, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1432, 1, 4); + setArg(call_illegal_indexed_store_1432, 2, EEW); + setArg(call_illegal_indexed_store_1432, 3, illegal_indexed_store_1432_arg2); + setArg(call_illegal_indexed_store_1432, 4, illegal_indexed_store_1432_arg3); + setRet(call_illegal_indexed_store_1432, 0, ret_val_illegal_indexed_store_1432); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1435; + x86::Gp ret_val_sew_1435 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1435, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1434; + auto vsxseg_1434_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1434_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1434_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1434_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1434_arg10 = ret_val_sew_1435; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1434 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1434, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1434, 32, false), traits::vstart); + setArg(call_sew_1435, 0, reinterpret_cast(this)); + setRet(call_sew_1435, 0, ret_val_sew_1435); + setArg(call_vsxseg_1434, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1434, 1, V); + setArg(call_vsxseg_1434, 2, vsxseg_1434_arg1); + setArg(call_vsxseg_1434, 3, vsxseg_1434_arg2); + setArg(call_vsxseg_1434, 4, vsxseg_1434_arg3); + setArg(call_vsxseg_1434, 5, vm); + setArg(call_vsxseg_1434, 6, vs3); + setArg(call_vsxseg_1434, 7, vsxseg_1434_arg6); + setArg(call_vsxseg_1434, 8, vs2); + setArg(call_vsxseg_1434, 9, 4); + setArg(call_vsxseg_1434, 10, 1); + setArg(call_vsxseg_1434, 11, vsxseg_1434_arg10); + setArg(call_vsxseg_1434, 12, 1); + setRet(call_vsxseg_1434, 0, ret_val_vsxseg_1434); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 389); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 390: VSOXSEG4EI16__V */ + continuation_e __vsoxseg4ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG4EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 390); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1436; + x86::Gp ret_val_get_pow_1436 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1436, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1437; + x86::Gp ret_val_get_sew_pow_1437 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1437, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1438; + x86::Gp ret_val_get_lmul_pow_1438 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1438, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1436, ret_val_get_sew_pow_1437), ret_val_get_lmul_pow_1438)), 3, true); + setArg(call_get_pow_1436, 0, reinterpret_cast(this)); + setArg(call_get_pow_1436, 1, EEW); + setRet(call_get_pow_1436, 0, ret_val_get_pow_1436); + setArg(call_get_sew_pow_1437, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1437, 0, ret_val_get_sew_pow_1437); + setArg(call_get_lmul_pow_1438, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1438, 0, ret_val_get_lmul_pow_1438); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1440; + x86::Gp ret_val_get_lmul_pow_1440 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1440, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1439; + auto illegal_indexed_store_1439_arg2 = EMUL_pow; + auto illegal_indexed_store_1439_arg3 = ret_val_get_lmul_pow_1440; + x86::Gp ret_val_illegal_indexed_store_1439 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1439, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1439; + setArg(call_get_lmul_pow_1440, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1440, 0, ret_val_get_lmul_pow_1440); + setArg(call_illegal_indexed_store_1439, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1439, 1, 4); + setArg(call_illegal_indexed_store_1439, 2, EEW); + setArg(call_illegal_indexed_store_1439, 3, illegal_indexed_store_1439_arg2); + setArg(call_illegal_indexed_store_1439, 4, illegal_indexed_store_1439_arg3); + setRet(call_illegal_indexed_store_1439, 0, ret_val_illegal_indexed_store_1439); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1442; + x86::Gp ret_val_sew_1442 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1442, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1441; + auto vsxseg_1441_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1441_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1441_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1441_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1441_arg10 = ret_val_sew_1442; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1441 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1441, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1441, 32, false), traits::vstart); + setArg(call_sew_1442, 0, reinterpret_cast(this)); + setRet(call_sew_1442, 0, ret_val_sew_1442); + setArg(call_vsxseg_1441, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1441, 1, V); + setArg(call_vsxseg_1441, 2, vsxseg_1441_arg1); + setArg(call_vsxseg_1441, 3, vsxseg_1441_arg2); + setArg(call_vsxseg_1441, 4, vsxseg_1441_arg3); + setArg(call_vsxseg_1441, 5, vm); + setArg(call_vsxseg_1441, 6, vs3); + setArg(call_vsxseg_1441, 7, vsxseg_1441_arg6); + setArg(call_vsxseg_1441, 8, vs2); + setArg(call_vsxseg_1441, 9, 4); + setArg(call_vsxseg_1441, 10, 2); + setArg(call_vsxseg_1441, 11, vsxseg_1441_arg10); + setArg(call_vsxseg_1441, 12, 1); + setRet(call_vsxseg_1441, 0, ret_val_vsxseg_1441); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 390); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 391: VSOXSEG4EI32__V */ + continuation_e __vsoxseg4ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG4EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 391); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1443; + x86::Gp ret_val_get_pow_1443 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1443, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1444; + x86::Gp ret_val_get_sew_pow_1444 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1444, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1445; + x86::Gp ret_val_get_lmul_pow_1445 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1445, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1443, ret_val_get_sew_pow_1444), ret_val_get_lmul_pow_1445)), 3, true); + setArg(call_get_pow_1443, 0, reinterpret_cast(this)); + setArg(call_get_pow_1443, 1, EEW); + setRet(call_get_pow_1443, 0, ret_val_get_pow_1443); + setArg(call_get_sew_pow_1444, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1444, 0, ret_val_get_sew_pow_1444); + setArg(call_get_lmul_pow_1445, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1445, 0, ret_val_get_lmul_pow_1445); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1447; + x86::Gp ret_val_get_lmul_pow_1447 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1447, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1446; + auto illegal_indexed_store_1446_arg2 = EMUL_pow; + auto illegal_indexed_store_1446_arg3 = ret_val_get_lmul_pow_1447; + x86::Gp ret_val_illegal_indexed_store_1446 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1446, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1446; + setArg(call_get_lmul_pow_1447, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1447, 0, ret_val_get_lmul_pow_1447); + setArg(call_illegal_indexed_store_1446, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1446, 1, 4); + setArg(call_illegal_indexed_store_1446, 2, EEW); + setArg(call_illegal_indexed_store_1446, 3, illegal_indexed_store_1446_arg2); + setArg(call_illegal_indexed_store_1446, 4, illegal_indexed_store_1446_arg3); + setRet(call_illegal_indexed_store_1446, 0, ret_val_illegal_indexed_store_1446); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1449; + x86::Gp ret_val_sew_1449 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1449, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1448; + auto vsxseg_1448_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1448_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1448_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1448_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1448_arg10 = ret_val_sew_1449; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1448 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1448, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1448, 32, false), traits::vstart); + setArg(call_sew_1449, 0, reinterpret_cast(this)); + setRet(call_sew_1449, 0, ret_val_sew_1449); + setArg(call_vsxseg_1448, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1448, 1, V); + setArg(call_vsxseg_1448, 2, vsxseg_1448_arg1); + setArg(call_vsxseg_1448, 3, vsxseg_1448_arg2); + setArg(call_vsxseg_1448, 4, vsxseg_1448_arg3); + setArg(call_vsxseg_1448, 5, vm); + setArg(call_vsxseg_1448, 6, vs3); + setArg(call_vsxseg_1448, 7, vsxseg_1448_arg6); + setArg(call_vsxseg_1448, 8, vs2); + setArg(call_vsxseg_1448, 9, 4); + setArg(call_vsxseg_1448, 10, 4); + setArg(call_vsxseg_1448, 11, vsxseg_1448_arg10); + setArg(call_vsxseg_1448, 12, 1); + setRet(call_vsxseg_1448, 0, ret_val_vsxseg_1448); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 391); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 392: VSOXSEG4EI64__V */ + continuation_e __vsoxseg4ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG4EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 392); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1450; + x86::Gp ret_val_get_pow_1450 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1450, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1451; + x86::Gp ret_val_get_sew_pow_1451 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1451, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1452; + x86::Gp ret_val_get_lmul_pow_1452 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1452, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1450, ret_val_get_sew_pow_1451), ret_val_get_lmul_pow_1452)), 3, true); + setArg(call_get_pow_1450, 0, reinterpret_cast(this)); + setArg(call_get_pow_1450, 1, EEW); + setRet(call_get_pow_1450, 0, ret_val_get_pow_1450); + setArg(call_get_sew_pow_1451, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1451, 0, ret_val_get_sew_pow_1451); + setArg(call_get_lmul_pow_1452, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1452, 0, ret_val_get_lmul_pow_1452); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1454; + x86::Gp ret_val_get_lmul_pow_1454 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1454, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1453; + auto illegal_indexed_store_1453_arg2 = EMUL_pow; + auto illegal_indexed_store_1453_arg3 = ret_val_get_lmul_pow_1454; + x86::Gp ret_val_illegal_indexed_store_1453 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1453, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1453; + setArg(call_get_lmul_pow_1454, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1454, 0, ret_val_get_lmul_pow_1454); + setArg(call_illegal_indexed_store_1453, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1453, 1, 4); + setArg(call_illegal_indexed_store_1453, 2, EEW); + setArg(call_illegal_indexed_store_1453, 3, illegal_indexed_store_1453_arg2); + setArg(call_illegal_indexed_store_1453, 4, illegal_indexed_store_1453_arg3); + setRet(call_illegal_indexed_store_1453, 0, ret_val_illegal_indexed_store_1453); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1456; + x86::Gp ret_val_sew_1456 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1456, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1455; + auto vsxseg_1455_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1455_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1455_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1455_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1455_arg10 = ret_val_sew_1456; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1455 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1455, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1455, 32, false), traits::vstart); + setArg(call_sew_1456, 0, reinterpret_cast(this)); + setRet(call_sew_1456, 0, ret_val_sew_1456); + setArg(call_vsxseg_1455, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1455, 1, V); + setArg(call_vsxseg_1455, 2, vsxseg_1455_arg1); + setArg(call_vsxseg_1455, 3, vsxseg_1455_arg2); + setArg(call_vsxseg_1455, 4, vsxseg_1455_arg3); + setArg(call_vsxseg_1455, 5, vm); + setArg(call_vsxseg_1455, 6, vs3); + setArg(call_vsxseg_1455, 7, vsxseg_1455_arg6); + setArg(call_vsxseg_1455, 8, vs2); + setArg(call_vsxseg_1455, 9, 4); + setArg(call_vsxseg_1455, 10, 8); + setArg(call_vsxseg_1455, 11, vsxseg_1455_arg10); + setArg(call_vsxseg_1455, 12, 1); + setRet(call_vsxseg_1455, 0, ret_val_vsxseg_1455); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 392); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 393: VSOXSEG5EI8__V */ + continuation_e __vsoxseg5ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG5EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 393); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1457; + x86::Gp ret_val_get_pow_1457 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1457, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1458; + x86::Gp ret_val_get_sew_pow_1458 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1458, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1459; + x86::Gp ret_val_get_lmul_pow_1459 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1459, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1457, ret_val_get_sew_pow_1458), ret_val_get_lmul_pow_1459)), 3, true); + setArg(call_get_pow_1457, 0, reinterpret_cast(this)); + setArg(call_get_pow_1457, 1, EEW); + setRet(call_get_pow_1457, 0, ret_val_get_pow_1457); + setArg(call_get_sew_pow_1458, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1458, 0, ret_val_get_sew_pow_1458); + setArg(call_get_lmul_pow_1459, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1459, 0, ret_val_get_lmul_pow_1459); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1461; + x86::Gp ret_val_get_lmul_pow_1461 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1461, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1460; + auto illegal_indexed_store_1460_arg2 = EMUL_pow; + auto illegal_indexed_store_1460_arg3 = ret_val_get_lmul_pow_1461; + x86::Gp ret_val_illegal_indexed_store_1460 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1460, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1460; + setArg(call_get_lmul_pow_1461, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1461, 0, ret_val_get_lmul_pow_1461); + setArg(call_illegal_indexed_store_1460, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1460, 1, 5); + setArg(call_illegal_indexed_store_1460, 2, EEW); + setArg(call_illegal_indexed_store_1460, 3, illegal_indexed_store_1460_arg2); + setArg(call_illegal_indexed_store_1460, 4, illegal_indexed_store_1460_arg3); + setRet(call_illegal_indexed_store_1460, 0, ret_val_illegal_indexed_store_1460); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1463; + x86::Gp ret_val_sew_1463 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1463, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1462; + auto vsxseg_1462_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1462_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1462_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1462_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1462_arg10 = ret_val_sew_1463; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1462 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1462, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1462, 32, false), traits::vstart); + setArg(call_sew_1463, 0, reinterpret_cast(this)); + setRet(call_sew_1463, 0, ret_val_sew_1463); + setArg(call_vsxseg_1462, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1462, 1, V); + setArg(call_vsxseg_1462, 2, vsxseg_1462_arg1); + setArg(call_vsxseg_1462, 3, vsxseg_1462_arg2); + setArg(call_vsxseg_1462, 4, vsxseg_1462_arg3); + setArg(call_vsxseg_1462, 5, vm); + setArg(call_vsxseg_1462, 6, vs3); + setArg(call_vsxseg_1462, 7, vsxseg_1462_arg6); + setArg(call_vsxseg_1462, 8, vs2); + setArg(call_vsxseg_1462, 9, 5); + setArg(call_vsxseg_1462, 10, 1); + setArg(call_vsxseg_1462, 11, vsxseg_1462_arg10); + setArg(call_vsxseg_1462, 12, 1); + setRet(call_vsxseg_1462, 0, ret_val_vsxseg_1462); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 393); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 394: VSOXSEG5EI16__V */ + continuation_e __vsoxseg5ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG5EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 394); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1464; + x86::Gp ret_val_get_pow_1464 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1464, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1465; + x86::Gp ret_val_get_sew_pow_1465 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1465, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1466; + x86::Gp ret_val_get_lmul_pow_1466 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1466, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1464, ret_val_get_sew_pow_1465), ret_val_get_lmul_pow_1466)), 3, true); + setArg(call_get_pow_1464, 0, reinterpret_cast(this)); + setArg(call_get_pow_1464, 1, EEW); + setRet(call_get_pow_1464, 0, ret_val_get_pow_1464); + setArg(call_get_sew_pow_1465, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1465, 0, ret_val_get_sew_pow_1465); + setArg(call_get_lmul_pow_1466, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1466, 0, ret_val_get_lmul_pow_1466); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1468; + x86::Gp ret_val_get_lmul_pow_1468 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1468, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1467; + auto illegal_indexed_store_1467_arg2 = EMUL_pow; + auto illegal_indexed_store_1467_arg3 = ret_val_get_lmul_pow_1468; + x86::Gp ret_val_illegal_indexed_store_1467 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1467, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1467; + setArg(call_get_lmul_pow_1468, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1468, 0, ret_val_get_lmul_pow_1468); + setArg(call_illegal_indexed_store_1467, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1467, 1, 5); + setArg(call_illegal_indexed_store_1467, 2, EEW); + setArg(call_illegal_indexed_store_1467, 3, illegal_indexed_store_1467_arg2); + setArg(call_illegal_indexed_store_1467, 4, illegal_indexed_store_1467_arg3); + setRet(call_illegal_indexed_store_1467, 0, ret_val_illegal_indexed_store_1467); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1470; + x86::Gp ret_val_sew_1470 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1470, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1469; + auto vsxseg_1469_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1469_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1469_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1469_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1469_arg10 = ret_val_sew_1470; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1469 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1469, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1469, 32, false), traits::vstart); + setArg(call_sew_1470, 0, reinterpret_cast(this)); + setRet(call_sew_1470, 0, ret_val_sew_1470); + setArg(call_vsxseg_1469, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1469, 1, V); + setArg(call_vsxseg_1469, 2, vsxseg_1469_arg1); + setArg(call_vsxseg_1469, 3, vsxseg_1469_arg2); + setArg(call_vsxseg_1469, 4, vsxseg_1469_arg3); + setArg(call_vsxseg_1469, 5, vm); + setArg(call_vsxseg_1469, 6, vs3); + setArg(call_vsxseg_1469, 7, vsxseg_1469_arg6); + setArg(call_vsxseg_1469, 8, vs2); + setArg(call_vsxseg_1469, 9, 5); + setArg(call_vsxseg_1469, 10, 2); + setArg(call_vsxseg_1469, 11, vsxseg_1469_arg10); + setArg(call_vsxseg_1469, 12, 1); + setRet(call_vsxseg_1469, 0, ret_val_vsxseg_1469); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 394); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 395: VSOXSEG5EI32__V */ + continuation_e __vsoxseg5ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG5EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 395); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1471; + x86::Gp ret_val_get_pow_1471 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1471, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1472; + x86::Gp ret_val_get_sew_pow_1472 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1472, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1473; + x86::Gp ret_val_get_lmul_pow_1473 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1473, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1471, ret_val_get_sew_pow_1472), ret_val_get_lmul_pow_1473)), 3, true); + setArg(call_get_pow_1471, 0, reinterpret_cast(this)); + setArg(call_get_pow_1471, 1, EEW); + setRet(call_get_pow_1471, 0, ret_val_get_pow_1471); + setArg(call_get_sew_pow_1472, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1472, 0, ret_val_get_sew_pow_1472); + setArg(call_get_lmul_pow_1473, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1473, 0, ret_val_get_lmul_pow_1473); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1475; + x86::Gp ret_val_get_lmul_pow_1475 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1475, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1474; + auto illegal_indexed_store_1474_arg2 = EMUL_pow; + auto illegal_indexed_store_1474_arg3 = ret_val_get_lmul_pow_1475; + x86::Gp ret_val_illegal_indexed_store_1474 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1474, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1474; + setArg(call_get_lmul_pow_1475, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1475, 0, ret_val_get_lmul_pow_1475); + setArg(call_illegal_indexed_store_1474, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1474, 1, 5); + setArg(call_illegal_indexed_store_1474, 2, EEW); + setArg(call_illegal_indexed_store_1474, 3, illegal_indexed_store_1474_arg2); + setArg(call_illegal_indexed_store_1474, 4, illegal_indexed_store_1474_arg3); + setRet(call_illegal_indexed_store_1474, 0, ret_val_illegal_indexed_store_1474); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1477; + x86::Gp ret_val_sew_1477 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1477, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1476; + auto vsxseg_1476_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1476_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1476_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1476_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1476_arg10 = ret_val_sew_1477; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1476 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1476, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1476, 32, false), traits::vstart); + setArg(call_sew_1477, 0, reinterpret_cast(this)); + setRet(call_sew_1477, 0, ret_val_sew_1477); + setArg(call_vsxseg_1476, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1476, 1, V); + setArg(call_vsxseg_1476, 2, vsxseg_1476_arg1); + setArg(call_vsxseg_1476, 3, vsxseg_1476_arg2); + setArg(call_vsxseg_1476, 4, vsxseg_1476_arg3); + setArg(call_vsxseg_1476, 5, vm); + setArg(call_vsxseg_1476, 6, vs3); + setArg(call_vsxseg_1476, 7, vsxseg_1476_arg6); + setArg(call_vsxseg_1476, 8, vs2); + setArg(call_vsxseg_1476, 9, 5); + setArg(call_vsxseg_1476, 10, 4); + setArg(call_vsxseg_1476, 11, vsxseg_1476_arg10); + setArg(call_vsxseg_1476, 12, 1); + setRet(call_vsxseg_1476, 0, ret_val_vsxseg_1476); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 395); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 396: VSOXSEG5EI64__V */ + continuation_e __vsoxseg5ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG5EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 396); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1478; + x86::Gp ret_val_get_pow_1478 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1478, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1479; + x86::Gp ret_val_get_sew_pow_1479 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1479, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1480; + x86::Gp ret_val_get_lmul_pow_1480 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1480, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1478, ret_val_get_sew_pow_1479), ret_val_get_lmul_pow_1480)), 3, true); + setArg(call_get_pow_1478, 0, reinterpret_cast(this)); + setArg(call_get_pow_1478, 1, EEW); + setRet(call_get_pow_1478, 0, ret_val_get_pow_1478); + setArg(call_get_sew_pow_1479, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1479, 0, ret_val_get_sew_pow_1479); + setArg(call_get_lmul_pow_1480, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1480, 0, ret_val_get_lmul_pow_1480); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1482; + x86::Gp ret_val_get_lmul_pow_1482 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1482, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1481; + auto illegal_indexed_store_1481_arg2 = EMUL_pow; + auto illegal_indexed_store_1481_arg3 = ret_val_get_lmul_pow_1482; + x86::Gp ret_val_illegal_indexed_store_1481 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1481, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1481; + setArg(call_get_lmul_pow_1482, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1482, 0, ret_val_get_lmul_pow_1482); + setArg(call_illegal_indexed_store_1481, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1481, 1, 5); + setArg(call_illegal_indexed_store_1481, 2, EEW); + setArg(call_illegal_indexed_store_1481, 3, illegal_indexed_store_1481_arg2); + setArg(call_illegal_indexed_store_1481, 4, illegal_indexed_store_1481_arg3); + setRet(call_illegal_indexed_store_1481, 0, ret_val_illegal_indexed_store_1481); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1484; + x86::Gp ret_val_sew_1484 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1484, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1483; + auto vsxseg_1483_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1483_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1483_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1483_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1483_arg10 = ret_val_sew_1484; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1483 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1483, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1483, 32, false), traits::vstart); + setArg(call_sew_1484, 0, reinterpret_cast(this)); + setRet(call_sew_1484, 0, ret_val_sew_1484); + setArg(call_vsxseg_1483, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1483, 1, V); + setArg(call_vsxseg_1483, 2, vsxseg_1483_arg1); + setArg(call_vsxseg_1483, 3, vsxseg_1483_arg2); + setArg(call_vsxseg_1483, 4, vsxseg_1483_arg3); + setArg(call_vsxseg_1483, 5, vm); + setArg(call_vsxseg_1483, 6, vs3); + setArg(call_vsxseg_1483, 7, vsxseg_1483_arg6); + setArg(call_vsxseg_1483, 8, vs2); + setArg(call_vsxseg_1483, 9, 5); + setArg(call_vsxseg_1483, 10, 8); + setArg(call_vsxseg_1483, 11, vsxseg_1483_arg10); + setArg(call_vsxseg_1483, 12, 1); + setRet(call_vsxseg_1483, 0, ret_val_vsxseg_1483); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 396); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 397: VSOXSEG6EI8__V */ + continuation_e __vsoxseg6ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG6EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 397); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1485; + x86::Gp ret_val_get_pow_1485 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1485, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1486; + x86::Gp ret_val_get_sew_pow_1486 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1486, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1487; + x86::Gp ret_val_get_lmul_pow_1487 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1487, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1485, ret_val_get_sew_pow_1486), ret_val_get_lmul_pow_1487)), 3, true); + setArg(call_get_pow_1485, 0, reinterpret_cast(this)); + setArg(call_get_pow_1485, 1, EEW); + setRet(call_get_pow_1485, 0, ret_val_get_pow_1485); + setArg(call_get_sew_pow_1486, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1486, 0, ret_val_get_sew_pow_1486); + setArg(call_get_lmul_pow_1487, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1487, 0, ret_val_get_lmul_pow_1487); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1489; + x86::Gp ret_val_get_lmul_pow_1489 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1489, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1488; + auto illegal_indexed_store_1488_arg2 = EMUL_pow; + auto illegal_indexed_store_1488_arg3 = ret_val_get_lmul_pow_1489; + x86::Gp ret_val_illegal_indexed_store_1488 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1488, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1488; + setArg(call_get_lmul_pow_1489, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1489, 0, ret_val_get_lmul_pow_1489); + setArg(call_illegal_indexed_store_1488, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1488, 1, 6); + setArg(call_illegal_indexed_store_1488, 2, EEW); + setArg(call_illegal_indexed_store_1488, 3, illegal_indexed_store_1488_arg2); + setArg(call_illegal_indexed_store_1488, 4, illegal_indexed_store_1488_arg3); + setRet(call_illegal_indexed_store_1488, 0, ret_val_illegal_indexed_store_1488); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1491; + x86::Gp ret_val_sew_1491 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1491, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1490; + auto vsxseg_1490_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1490_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1490_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1490_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1490_arg10 = ret_val_sew_1491; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1490 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1490, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1490, 32, false), traits::vstart); + setArg(call_sew_1491, 0, reinterpret_cast(this)); + setRet(call_sew_1491, 0, ret_val_sew_1491); + setArg(call_vsxseg_1490, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1490, 1, V); + setArg(call_vsxseg_1490, 2, vsxseg_1490_arg1); + setArg(call_vsxseg_1490, 3, vsxseg_1490_arg2); + setArg(call_vsxseg_1490, 4, vsxseg_1490_arg3); + setArg(call_vsxseg_1490, 5, vm); + setArg(call_vsxseg_1490, 6, vs3); + setArg(call_vsxseg_1490, 7, vsxseg_1490_arg6); + setArg(call_vsxseg_1490, 8, vs2); + setArg(call_vsxseg_1490, 9, 6); + setArg(call_vsxseg_1490, 10, 1); + setArg(call_vsxseg_1490, 11, vsxseg_1490_arg10); + setArg(call_vsxseg_1490, 12, 1); + setRet(call_vsxseg_1490, 0, ret_val_vsxseg_1490); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 397); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 398: VSOXSEG6EI16__V */ + continuation_e __vsoxseg6ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG6EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 398); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1492; + x86::Gp ret_val_get_pow_1492 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1492, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1493; + x86::Gp ret_val_get_sew_pow_1493 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1493, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1494; + x86::Gp ret_val_get_lmul_pow_1494 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1494, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1492, ret_val_get_sew_pow_1493), ret_val_get_lmul_pow_1494)), 3, true); + setArg(call_get_pow_1492, 0, reinterpret_cast(this)); + setArg(call_get_pow_1492, 1, EEW); + setRet(call_get_pow_1492, 0, ret_val_get_pow_1492); + setArg(call_get_sew_pow_1493, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1493, 0, ret_val_get_sew_pow_1493); + setArg(call_get_lmul_pow_1494, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1494, 0, ret_val_get_lmul_pow_1494); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1496; + x86::Gp ret_val_get_lmul_pow_1496 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1496, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1495; + auto illegal_indexed_store_1495_arg2 = EMUL_pow; + auto illegal_indexed_store_1495_arg3 = ret_val_get_lmul_pow_1496; + x86::Gp ret_val_illegal_indexed_store_1495 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1495, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1495; + setArg(call_get_lmul_pow_1496, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1496, 0, ret_val_get_lmul_pow_1496); + setArg(call_illegal_indexed_store_1495, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1495, 1, 6); + setArg(call_illegal_indexed_store_1495, 2, EEW); + setArg(call_illegal_indexed_store_1495, 3, illegal_indexed_store_1495_arg2); + setArg(call_illegal_indexed_store_1495, 4, illegal_indexed_store_1495_arg3); + setRet(call_illegal_indexed_store_1495, 0, ret_val_illegal_indexed_store_1495); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1498; + x86::Gp ret_val_sew_1498 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1498, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1497; + auto vsxseg_1497_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1497_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1497_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1497_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1497_arg10 = ret_val_sew_1498; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1497 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1497, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1497, 32, false), traits::vstart); + setArg(call_sew_1498, 0, reinterpret_cast(this)); + setRet(call_sew_1498, 0, ret_val_sew_1498); + setArg(call_vsxseg_1497, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1497, 1, V); + setArg(call_vsxseg_1497, 2, vsxseg_1497_arg1); + setArg(call_vsxseg_1497, 3, vsxseg_1497_arg2); + setArg(call_vsxseg_1497, 4, vsxseg_1497_arg3); + setArg(call_vsxseg_1497, 5, vm); + setArg(call_vsxseg_1497, 6, vs3); + setArg(call_vsxseg_1497, 7, vsxseg_1497_arg6); + setArg(call_vsxseg_1497, 8, vs2); + setArg(call_vsxseg_1497, 9, 6); + setArg(call_vsxseg_1497, 10, 2); + setArg(call_vsxseg_1497, 11, vsxseg_1497_arg10); + setArg(call_vsxseg_1497, 12, 1); + setRet(call_vsxseg_1497, 0, ret_val_vsxseg_1497); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 398); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 399: VSOXSEG6EI32__V */ + continuation_e __vsoxseg6ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG6EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 399); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1499; + x86::Gp ret_val_get_pow_1499 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1499, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1500; + x86::Gp ret_val_get_sew_pow_1500 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1500, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1501; + x86::Gp ret_val_get_lmul_pow_1501 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1501, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1499, ret_val_get_sew_pow_1500), ret_val_get_lmul_pow_1501)), 3, true); + setArg(call_get_pow_1499, 0, reinterpret_cast(this)); + setArg(call_get_pow_1499, 1, EEW); + setRet(call_get_pow_1499, 0, ret_val_get_pow_1499); + setArg(call_get_sew_pow_1500, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1500, 0, ret_val_get_sew_pow_1500); + setArg(call_get_lmul_pow_1501, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1501, 0, ret_val_get_lmul_pow_1501); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1503; + x86::Gp ret_val_get_lmul_pow_1503 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1503, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1502; + auto illegal_indexed_store_1502_arg2 = EMUL_pow; + auto illegal_indexed_store_1502_arg3 = ret_val_get_lmul_pow_1503; + x86::Gp ret_val_illegal_indexed_store_1502 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1502, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1502; + setArg(call_get_lmul_pow_1503, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1503, 0, ret_val_get_lmul_pow_1503); + setArg(call_illegal_indexed_store_1502, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1502, 1, 6); + setArg(call_illegal_indexed_store_1502, 2, EEW); + setArg(call_illegal_indexed_store_1502, 3, illegal_indexed_store_1502_arg2); + setArg(call_illegal_indexed_store_1502, 4, illegal_indexed_store_1502_arg3); + setRet(call_illegal_indexed_store_1502, 0, ret_val_illegal_indexed_store_1502); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1505; + x86::Gp ret_val_sew_1505 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1505, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1504; + auto vsxseg_1504_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1504_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1504_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1504_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1504_arg10 = ret_val_sew_1505; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1504 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1504, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1504, 32, false), traits::vstart); + setArg(call_sew_1505, 0, reinterpret_cast(this)); + setRet(call_sew_1505, 0, ret_val_sew_1505); + setArg(call_vsxseg_1504, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1504, 1, V); + setArg(call_vsxseg_1504, 2, vsxseg_1504_arg1); + setArg(call_vsxseg_1504, 3, vsxseg_1504_arg2); + setArg(call_vsxseg_1504, 4, vsxseg_1504_arg3); + setArg(call_vsxseg_1504, 5, vm); + setArg(call_vsxseg_1504, 6, vs3); + setArg(call_vsxseg_1504, 7, vsxseg_1504_arg6); + setArg(call_vsxseg_1504, 8, vs2); + setArg(call_vsxseg_1504, 9, 6); + setArg(call_vsxseg_1504, 10, 4); + setArg(call_vsxseg_1504, 11, vsxseg_1504_arg10); + setArg(call_vsxseg_1504, 12, 1); + setRet(call_vsxseg_1504, 0, ret_val_vsxseg_1504); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 399); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 400: VSOXSEG6EI64__V */ + continuation_e __vsoxseg6ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG6EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 400); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1506; + x86::Gp ret_val_get_pow_1506 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1506, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1507; + x86::Gp ret_val_get_sew_pow_1507 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1507, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1508; + x86::Gp ret_val_get_lmul_pow_1508 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1508, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1506, ret_val_get_sew_pow_1507), ret_val_get_lmul_pow_1508)), 3, true); + setArg(call_get_pow_1506, 0, reinterpret_cast(this)); + setArg(call_get_pow_1506, 1, EEW); + setRet(call_get_pow_1506, 0, ret_val_get_pow_1506); + setArg(call_get_sew_pow_1507, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1507, 0, ret_val_get_sew_pow_1507); + setArg(call_get_lmul_pow_1508, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1508, 0, ret_val_get_lmul_pow_1508); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1510; + x86::Gp ret_val_get_lmul_pow_1510 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1510, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1509; + auto illegal_indexed_store_1509_arg2 = EMUL_pow; + auto illegal_indexed_store_1509_arg3 = ret_val_get_lmul_pow_1510; + x86::Gp ret_val_illegal_indexed_store_1509 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1509, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1509; + setArg(call_get_lmul_pow_1510, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1510, 0, ret_val_get_lmul_pow_1510); + setArg(call_illegal_indexed_store_1509, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1509, 1, 6); + setArg(call_illegal_indexed_store_1509, 2, EEW); + setArg(call_illegal_indexed_store_1509, 3, illegal_indexed_store_1509_arg2); + setArg(call_illegal_indexed_store_1509, 4, illegal_indexed_store_1509_arg3); + setRet(call_illegal_indexed_store_1509, 0, ret_val_illegal_indexed_store_1509); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1512; + x86::Gp ret_val_sew_1512 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1512, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1511; + auto vsxseg_1511_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1511_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1511_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1511_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1511_arg10 = ret_val_sew_1512; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1511 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1511, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1511, 32, false), traits::vstart); + setArg(call_sew_1512, 0, reinterpret_cast(this)); + setRet(call_sew_1512, 0, ret_val_sew_1512); + setArg(call_vsxseg_1511, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1511, 1, V); + setArg(call_vsxseg_1511, 2, vsxseg_1511_arg1); + setArg(call_vsxseg_1511, 3, vsxseg_1511_arg2); + setArg(call_vsxseg_1511, 4, vsxseg_1511_arg3); + setArg(call_vsxseg_1511, 5, vm); + setArg(call_vsxseg_1511, 6, vs3); + setArg(call_vsxseg_1511, 7, vsxseg_1511_arg6); + setArg(call_vsxseg_1511, 8, vs2); + setArg(call_vsxseg_1511, 9, 6); + setArg(call_vsxseg_1511, 10, 8); + setArg(call_vsxseg_1511, 11, vsxseg_1511_arg10); + setArg(call_vsxseg_1511, 12, 1); + setRet(call_vsxseg_1511, 0, ret_val_vsxseg_1511); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 400); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 401: VSOXSEG7EI8__V */ + continuation_e __vsoxseg7ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG7EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 401); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1513; + x86::Gp ret_val_get_pow_1513 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1513, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1514; + x86::Gp ret_val_get_sew_pow_1514 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1514, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1515; + x86::Gp ret_val_get_lmul_pow_1515 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1515, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1513, ret_val_get_sew_pow_1514), ret_val_get_lmul_pow_1515)), 3, true); + setArg(call_get_pow_1513, 0, reinterpret_cast(this)); + setArg(call_get_pow_1513, 1, EEW); + setRet(call_get_pow_1513, 0, ret_val_get_pow_1513); + setArg(call_get_sew_pow_1514, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1514, 0, ret_val_get_sew_pow_1514); + setArg(call_get_lmul_pow_1515, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1515, 0, ret_val_get_lmul_pow_1515); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1517; + x86::Gp ret_val_get_lmul_pow_1517 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1517, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1516; + auto illegal_indexed_store_1516_arg2 = EMUL_pow; + auto illegal_indexed_store_1516_arg3 = ret_val_get_lmul_pow_1517; + x86::Gp ret_val_illegal_indexed_store_1516 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1516, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1516; + setArg(call_get_lmul_pow_1517, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1517, 0, ret_val_get_lmul_pow_1517); + setArg(call_illegal_indexed_store_1516, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1516, 1, 7); + setArg(call_illegal_indexed_store_1516, 2, EEW); + setArg(call_illegal_indexed_store_1516, 3, illegal_indexed_store_1516_arg2); + setArg(call_illegal_indexed_store_1516, 4, illegal_indexed_store_1516_arg3); + setRet(call_illegal_indexed_store_1516, 0, ret_val_illegal_indexed_store_1516); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1519; + x86::Gp ret_val_sew_1519 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1519, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1518; + auto vsxseg_1518_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1518_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1518_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1518_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1518_arg10 = ret_val_sew_1519; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1518 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1518, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1518, 32, false), traits::vstart); + setArg(call_sew_1519, 0, reinterpret_cast(this)); + setRet(call_sew_1519, 0, ret_val_sew_1519); + setArg(call_vsxseg_1518, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1518, 1, V); + setArg(call_vsxseg_1518, 2, vsxseg_1518_arg1); + setArg(call_vsxseg_1518, 3, vsxseg_1518_arg2); + setArg(call_vsxseg_1518, 4, vsxseg_1518_arg3); + setArg(call_vsxseg_1518, 5, vm); + setArg(call_vsxseg_1518, 6, vs3); + setArg(call_vsxseg_1518, 7, vsxseg_1518_arg6); + setArg(call_vsxseg_1518, 8, vs2); + setArg(call_vsxseg_1518, 9, 7); + setArg(call_vsxseg_1518, 10, 1); + setArg(call_vsxseg_1518, 11, vsxseg_1518_arg10); + setArg(call_vsxseg_1518, 12, 1); + setRet(call_vsxseg_1518, 0, ret_val_vsxseg_1518); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 401); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 402: VSOXSEG7EI16__V */ + continuation_e __vsoxseg7ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG7EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 402); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1520; + x86::Gp ret_val_get_pow_1520 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1520, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1521; + x86::Gp ret_val_get_sew_pow_1521 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1521, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1522; + x86::Gp ret_val_get_lmul_pow_1522 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1522, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1520, ret_val_get_sew_pow_1521), ret_val_get_lmul_pow_1522)), 3, true); + setArg(call_get_pow_1520, 0, reinterpret_cast(this)); + setArg(call_get_pow_1520, 1, EEW); + setRet(call_get_pow_1520, 0, ret_val_get_pow_1520); + setArg(call_get_sew_pow_1521, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1521, 0, ret_val_get_sew_pow_1521); + setArg(call_get_lmul_pow_1522, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1522, 0, ret_val_get_lmul_pow_1522); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1524; + x86::Gp ret_val_get_lmul_pow_1524 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1524, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1523; + auto illegal_indexed_store_1523_arg2 = EMUL_pow; + auto illegal_indexed_store_1523_arg3 = ret_val_get_lmul_pow_1524; + x86::Gp ret_val_illegal_indexed_store_1523 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1523, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1523; + setArg(call_get_lmul_pow_1524, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1524, 0, ret_val_get_lmul_pow_1524); + setArg(call_illegal_indexed_store_1523, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1523, 1, 7); + setArg(call_illegal_indexed_store_1523, 2, EEW); + setArg(call_illegal_indexed_store_1523, 3, illegal_indexed_store_1523_arg2); + setArg(call_illegal_indexed_store_1523, 4, illegal_indexed_store_1523_arg3); + setRet(call_illegal_indexed_store_1523, 0, ret_val_illegal_indexed_store_1523); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1526; + x86::Gp ret_val_sew_1526 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1526, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1525; + auto vsxseg_1525_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1525_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1525_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1525_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1525_arg10 = ret_val_sew_1526; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1525 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1525, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1525, 32, false), traits::vstart); + setArg(call_sew_1526, 0, reinterpret_cast(this)); + setRet(call_sew_1526, 0, ret_val_sew_1526); + setArg(call_vsxseg_1525, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1525, 1, V); + setArg(call_vsxseg_1525, 2, vsxseg_1525_arg1); + setArg(call_vsxseg_1525, 3, vsxseg_1525_arg2); + setArg(call_vsxseg_1525, 4, vsxseg_1525_arg3); + setArg(call_vsxseg_1525, 5, vm); + setArg(call_vsxseg_1525, 6, vs3); + setArg(call_vsxseg_1525, 7, vsxseg_1525_arg6); + setArg(call_vsxseg_1525, 8, vs2); + setArg(call_vsxseg_1525, 9, 7); + setArg(call_vsxseg_1525, 10, 2); + setArg(call_vsxseg_1525, 11, vsxseg_1525_arg10); + setArg(call_vsxseg_1525, 12, 1); + setRet(call_vsxseg_1525, 0, ret_val_vsxseg_1525); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 402); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 403: VSOXSEG7EI32__V */ + continuation_e __vsoxseg7ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG7EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 403); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1527; + x86::Gp ret_val_get_pow_1527 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1527, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1528; + x86::Gp ret_val_get_sew_pow_1528 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1528, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1529; + x86::Gp ret_val_get_lmul_pow_1529 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1529, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1527, ret_val_get_sew_pow_1528), ret_val_get_lmul_pow_1529)), 3, true); + setArg(call_get_pow_1527, 0, reinterpret_cast(this)); + setArg(call_get_pow_1527, 1, EEW); + setRet(call_get_pow_1527, 0, ret_val_get_pow_1527); + setArg(call_get_sew_pow_1528, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1528, 0, ret_val_get_sew_pow_1528); + setArg(call_get_lmul_pow_1529, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1529, 0, ret_val_get_lmul_pow_1529); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1531; + x86::Gp ret_val_get_lmul_pow_1531 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1531, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1530; + auto illegal_indexed_store_1530_arg2 = EMUL_pow; + auto illegal_indexed_store_1530_arg3 = ret_val_get_lmul_pow_1531; + x86::Gp ret_val_illegal_indexed_store_1530 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1530, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1530; + setArg(call_get_lmul_pow_1531, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1531, 0, ret_val_get_lmul_pow_1531); + setArg(call_illegal_indexed_store_1530, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1530, 1, 7); + setArg(call_illegal_indexed_store_1530, 2, EEW); + setArg(call_illegal_indexed_store_1530, 3, illegal_indexed_store_1530_arg2); + setArg(call_illegal_indexed_store_1530, 4, illegal_indexed_store_1530_arg3); + setRet(call_illegal_indexed_store_1530, 0, ret_val_illegal_indexed_store_1530); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1533; + x86::Gp ret_val_sew_1533 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1533, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1532; + auto vsxseg_1532_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1532_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1532_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1532_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1532_arg10 = ret_val_sew_1533; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1532 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1532, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1532, 32, false), traits::vstart); + setArg(call_sew_1533, 0, reinterpret_cast(this)); + setRet(call_sew_1533, 0, ret_val_sew_1533); + setArg(call_vsxseg_1532, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1532, 1, V); + setArg(call_vsxseg_1532, 2, vsxseg_1532_arg1); + setArg(call_vsxseg_1532, 3, vsxseg_1532_arg2); + setArg(call_vsxseg_1532, 4, vsxseg_1532_arg3); + setArg(call_vsxseg_1532, 5, vm); + setArg(call_vsxseg_1532, 6, vs3); + setArg(call_vsxseg_1532, 7, vsxseg_1532_arg6); + setArg(call_vsxseg_1532, 8, vs2); + setArg(call_vsxseg_1532, 9, 7); + setArg(call_vsxseg_1532, 10, 4); + setArg(call_vsxseg_1532, 11, vsxseg_1532_arg10); + setArg(call_vsxseg_1532, 12, 1); + setRet(call_vsxseg_1532, 0, ret_val_vsxseg_1532); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 403); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 404: VSOXSEG7EI64__V */ + continuation_e __vsoxseg7ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG7EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 404); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1534; + x86::Gp ret_val_get_pow_1534 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1534, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1535; + x86::Gp ret_val_get_sew_pow_1535 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1535, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1536; + x86::Gp ret_val_get_lmul_pow_1536 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1536, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1534, ret_val_get_sew_pow_1535), ret_val_get_lmul_pow_1536)), 3, true); + setArg(call_get_pow_1534, 0, reinterpret_cast(this)); + setArg(call_get_pow_1534, 1, EEW); + setRet(call_get_pow_1534, 0, ret_val_get_pow_1534); + setArg(call_get_sew_pow_1535, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1535, 0, ret_val_get_sew_pow_1535); + setArg(call_get_lmul_pow_1536, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1536, 0, ret_val_get_lmul_pow_1536); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1538; + x86::Gp ret_val_get_lmul_pow_1538 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1538, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1537; + auto illegal_indexed_store_1537_arg2 = EMUL_pow; + auto illegal_indexed_store_1537_arg3 = ret_val_get_lmul_pow_1538; + x86::Gp ret_val_illegal_indexed_store_1537 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1537, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1537; + setArg(call_get_lmul_pow_1538, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1538, 0, ret_val_get_lmul_pow_1538); + setArg(call_illegal_indexed_store_1537, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1537, 1, 7); + setArg(call_illegal_indexed_store_1537, 2, EEW); + setArg(call_illegal_indexed_store_1537, 3, illegal_indexed_store_1537_arg2); + setArg(call_illegal_indexed_store_1537, 4, illegal_indexed_store_1537_arg3); + setRet(call_illegal_indexed_store_1537, 0, ret_val_illegal_indexed_store_1537); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1540; + x86::Gp ret_val_sew_1540 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1540, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1539; + auto vsxseg_1539_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1539_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1539_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1539_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1539_arg10 = ret_val_sew_1540; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1539 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1539, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1539, 32, false), traits::vstart); + setArg(call_sew_1540, 0, reinterpret_cast(this)); + setRet(call_sew_1540, 0, ret_val_sew_1540); + setArg(call_vsxseg_1539, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1539, 1, V); + setArg(call_vsxseg_1539, 2, vsxseg_1539_arg1); + setArg(call_vsxseg_1539, 3, vsxseg_1539_arg2); + setArg(call_vsxseg_1539, 4, vsxseg_1539_arg3); + setArg(call_vsxseg_1539, 5, vm); + setArg(call_vsxseg_1539, 6, vs3); + setArg(call_vsxseg_1539, 7, vsxseg_1539_arg6); + setArg(call_vsxseg_1539, 8, vs2); + setArg(call_vsxseg_1539, 9, 7); + setArg(call_vsxseg_1539, 10, 8); + setArg(call_vsxseg_1539, 11, vsxseg_1539_arg10); + setArg(call_vsxseg_1539, 12, 1); + setRet(call_vsxseg_1539, 0, ret_val_vsxseg_1539); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 404); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 405: VSOXSEG8EI8__V */ + continuation_e __vsoxseg8ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG8EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 405); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1541; + x86::Gp ret_val_get_pow_1541 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1541, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1542; + x86::Gp ret_val_get_sew_pow_1542 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1542, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1543; + x86::Gp ret_val_get_lmul_pow_1543 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1543, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1541, ret_val_get_sew_pow_1542), ret_val_get_lmul_pow_1543)), 3, true); + setArg(call_get_pow_1541, 0, reinterpret_cast(this)); + setArg(call_get_pow_1541, 1, EEW); + setRet(call_get_pow_1541, 0, ret_val_get_pow_1541); + setArg(call_get_sew_pow_1542, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1542, 0, ret_val_get_sew_pow_1542); + setArg(call_get_lmul_pow_1543, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1543, 0, ret_val_get_lmul_pow_1543); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1545; + x86::Gp ret_val_get_lmul_pow_1545 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1545, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1544; + auto illegal_indexed_store_1544_arg2 = EMUL_pow; + auto illegal_indexed_store_1544_arg3 = ret_val_get_lmul_pow_1545; + x86::Gp ret_val_illegal_indexed_store_1544 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1544, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1544; + setArg(call_get_lmul_pow_1545, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1545, 0, ret_val_get_lmul_pow_1545); + setArg(call_illegal_indexed_store_1544, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1544, 1, 8); + setArg(call_illegal_indexed_store_1544, 2, EEW); + setArg(call_illegal_indexed_store_1544, 3, illegal_indexed_store_1544_arg2); + setArg(call_illegal_indexed_store_1544, 4, illegal_indexed_store_1544_arg3); + setRet(call_illegal_indexed_store_1544, 0, ret_val_illegal_indexed_store_1544); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1547; + x86::Gp ret_val_sew_1547 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1547, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1546; + auto vsxseg_1546_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1546_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1546_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1546_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1546_arg10 = ret_val_sew_1547; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1546 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1546, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1546, 32, false), traits::vstart); + setArg(call_sew_1547, 0, reinterpret_cast(this)); + setRet(call_sew_1547, 0, ret_val_sew_1547); + setArg(call_vsxseg_1546, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1546, 1, V); + setArg(call_vsxseg_1546, 2, vsxseg_1546_arg1); + setArg(call_vsxseg_1546, 3, vsxseg_1546_arg2); + setArg(call_vsxseg_1546, 4, vsxseg_1546_arg3); + setArg(call_vsxseg_1546, 5, vm); + setArg(call_vsxseg_1546, 6, vs3); + setArg(call_vsxseg_1546, 7, vsxseg_1546_arg6); + setArg(call_vsxseg_1546, 8, vs2); + setArg(call_vsxseg_1546, 9, 8); + setArg(call_vsxseg_1546, 10, 1); + setArg(call_vsxseg_1546, 11, vsxseg_1546_arg10); + setArg(call_vsxseg_1546, 12, 1); + setRet(call_vsxseg_1546, 0, ret_val_vsxseg_1546); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 405); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 406: VSOXSEG8EI16__V */ + continuation_e __vsoxseg8ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG8EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 406); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1548; + x86::Gp ret_val_get_pow_1548 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1548, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1549; + x86::Gp ret_val_get_sew_pow_1549 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1549, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1550; + x86::Gp ret_val_get_lmul_pow_1550 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1550, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1548, ret_val_get_sew_pow_1549), ret_val_get_lmul_pow_1550)), 3, true); + setArg(call_get_pow_1548, 0, reinterpret_cast(this)); + setArg(call_get_pow_1548, 1, EEW); + setRet(call_get_pow_1548, 0, ret_val_get_pow_1548); + setArg(call_get_sew_pow_1549, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1549, 0, ret_val_get_sew_pow_1549); + setArg(call_get_lmul_pow_1550, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1550, 0, ret_val_get_lmul_pow_1550); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1552; + x86::Gp ret_val_get_lmul_pow_1552 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1552, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1551; + auto illegal_indexed_store_1551_arg2 = EMUL_pow; + auto illegal_indexed_store_1551_arg3 = ret_val_get_lmul_pow_1552; + x86::Gp ret_val_illegal_indexed_store_1551 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1551, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1551; + setArg(call_get_lmul_pow_1552, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1552, 0, ret_val_get_lmul_pow_1552); + setArg(call_illegal_indexed_store_1551, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1551, 1, 8); + setArg(call_illegal_indexed_store_1551, 2, EEW); + setArg(call_illegal_indexed_store_1551, 3, illegal_indexed_store_1551_arg2); + setArg(call_illegal_indexed_store_1551, 4, illegal_indexed_store_1551_arg3); + setRet(call_illegal_indexed_store_1551, 0, ret_val_illegal_indexed_store_1551); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1554; + x86::Gp ret_val_sew_1554 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1554, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1553; + auto vsxseg_1553_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1553_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1553_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1553_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1553_arg10 = ret_val_sew_1554; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1553 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1553, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1553, 32, false), traits::vstart); + setArg(call_sew_1554, 0, reinterpret_cast(this)); + setRet(call_sew_1554, 0, ret_val_sew_1554); + setArg(call_vsxseg_1553, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1553, 1, V); + setArg(call_vsxseg_1553, 2, vsxseg_1553_arg1); + setArg(call_vsxseg_1553, 3, vsxseg_1553_arg2); + setArg(call_vsxseg_1553, 4, vsxseg_1553_arg3); + setArg(call_vsxseg_1553, 5, vm); + setArg(call_vsxseg_1553, 6, vs3); + setArg(call_vsxseg_1553, 7, vsxseg_1553_arg6); + setArg(call_vsxseg_1553, 8, vs2); + setArg(call_vsxseg_1553, 9, 8); + setArg(call_vsxseg_1553, 10, 2); + setArg(call_vsxseg_1553, 11, vsxseg_1553_arg10); + setArg(call_vsxseg_1553, 12, 1); + setRet(call_vsxseg_1553, 0, ret_val_vsxseg_1553); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 406); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 407: VSOXSEG8EI32__V */ + continuation_e __vsoxseg8ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG8EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 407); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1555; + x86::Gp ret_val_get_pow_1555 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1555, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1556; + x86::Gp ret_val_get_sew_pow_1556 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1556, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1557; + x86::Gp ret_val_get_lmul_pow_1557 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1557, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1555, ret_val_get_sew_pow_1556), ret_val_get_lmul_pow_1557)), 3, true); + setArg(call_get_pow_1555, 0, reinterpret_cast(this)); + setArg(call_get_pow_1555, 1, EEW); + setRet(call_get_pow_1555, 0, ret_val_get_pow_1555); + setArg(call_get_sew_pow_1556, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1556, 0, ret_val_get_sew_pow_1556); + setArg(call_get_lmul_pow_1557, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1557, 0, ret_val_get_lmul_pow_1557); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1559; + x86::Gp ret_val_get_lmul_pow_1559 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1559, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1558; + auto illegal_indexed_store_1558_arg2 = EMUL_pow; + auto illegal_indexed_store_1558_arg3 = ret_val_get_lmul_pow_1559; + x86::Gp ret_val_illegal_indexed_store_1558 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1558, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1558; + setArg(call_get_lmul_pow_1559, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1559, 0, ret_val_get_lmul_pow_1559); + setArg(call_illegal_indexed_store_1558, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1558, 1, 8); + setArg(call_illegal_indexed_store_1558, 2, EEW); + setArg(call_illegal_indexed_store_1558, 3, illegal_indexed_store_1558_arg2); + setArg(call_illegal_indexed_store_1558, 4, illegal_indexed_store_1558_arg3); + setRet(call_illegal_indexed_store_1558, 0, ret_val_illegal_indexed_store_1558); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1561; + x86::Gp ret_val_sew_1561 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1561, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1560; + auto vsxseg_1560_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1560_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1560_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1560_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1560_arg10 = ret_val_sew_1561; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1560 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1560, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1560, 32, false), traits::vstart); + setArg(call_sew_1561, 0, reinterpret_cast(this)); + setRet(call_sew_1561, 0, ret_val_sew_1561); + setArg(call_vsxseg_1560, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1560, 1, V); + setArg(call_vsxseg_1560, 2, vsxseg_1560_arg1); + setArg(call_vsxseg_1560, 3, vsxseg_1560_arg2); + setArg(call_vsxseg_1560, 4, vsxseg_1560_arg3); + setArg(call_vsxseg_1560, 5, vm); + setArg(call_vsxseg_1560, 6, vs3); + setArg(call_vsxseg_1560, 7, vsxseg_1560_arg6); + setArg(call_vsxseg_1560, 8, vs2); + setArg(call_vsxseg_1560, 9, 8); + setArg(call_vsxseg_1560, 10, 4); + setArg(call_vsxseg_1560, 11, vsxseg_1560_arg10); + setArg(call_vsxseg_1560, 12, 1); + setRet(call_vsxseg_1560, 0, ret_val_vsxseg_1560); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 407); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 408: VSOXSEG8EI64__V */ + continuation_e __vsoxseg8ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG8EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 408); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1562; + x86::Gp ret_val_get_pow_1562 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1562, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1563; + x86::Gp ret_val_get_sew_pow_1563 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1563, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1564; + x86::Gp ret_val_get_lmul_pow_1564 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1564, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1562, ret_val_get_sew_pow_1563), ret_val_get_lmul_pow_1564)), 3, true); + setArg(call_get_pow_1562, 0, reinterpret_cast(this)); + setArg(call_get_pow_1562, 1, EEW); + setRet(call_get_pow_1562, 0, ret_val_get_pow_1562); + setArg(call_get_sew_pow_1563, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1563, 0, ret_val_get_sew_pow_1563); + setArg(call_get_lmul_pow_1564, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1564, 0, ret_val_get_lmul_pow_1564); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1566; + x86::Gp ret_val_get_lmul_pow_1566 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1566, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1565; + auto illegal_indexed_store_1565_arg2 = EMUL_pow; + auto illegal_indexed_store_1565_arg3 = ret_val_get_lmul_pow_1566; + x86::Gp ret_val_illegal_indexed_store_1565 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1565, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1565; + setArg(call_get_lmul_pow_1566, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1566, 0, ret_val_get_lmul_pow_1566); + setArg(call_illegal_indexed_store_1565, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1565, 1, 8); + setArg(call_illegal_indexed_store_1565, 2, EEW); + setArg(call_illegal_indexed_store_1565, 3, illegal_indexed_store_1565_arg2); + setArg(call_illegal_indexed_store_1565, 4, illegal_indexed_store_1565_arg3); + setRet(call_illegal_indexed_store_1565, 0, ret_val_illegal_indexed_store_1565); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1568; + x86::Gp ret_val_sew_1568 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1568, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1567; + auto vsxseg_1567_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1567_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1567_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1567_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1567_arg10 = ret_val_sew_1568; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1567 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1567, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1567, 32, false), traits::vstart); + setArg(call_sew_1568, 0, reinterpret_cast(this)); + setRet(call_sew_1568, 0, ret_val_sew_1568); + setArg(call_vsxseg_1567, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1567, 1, V); + setArg(call_vsxseg_1567, 2, vsxseg_1567_arg1); + setArg(call_vsxseg_1567, 3, vsxseg_1567_arg2); + setArg(call_vsxseg_1567, 4, vsxseg_1567_arg3); + setArg(call_vsxseg_1567, 5, vm); + setArg(call_vsxseg_1567, 6, vs3); + setArg(call_vsxseg_1567, 7, vsxseg_1567_arg6); + setArg(call_vsxseg_1567, 8, vs2); + setArg(call_vsxseg_1567, 9, 8); + setArg(call_vsxseg_1567, 10, 8); + setArg(call_vsxseg_1567, 11, vsxseg_1567_arg10); + setArg(call_vsxseg_1567, 12, 1); + setRet(call_vsxseg_1567, 0, ret_val_vsxseg_1567); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 408); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 409: VLUXEI8__V */ + continuation_e __vluxei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXEI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 409); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1569; + x86::Gp ret_val_get_pow_1569 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1569, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1570; + x86::Gp ret_val_get_sew_pow_1570 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1570, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1571; + x86::Gp ret_val_get_lmul_pow_1571 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1571, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1569, ret_val_get_sew_pow_1570), ret_val_get_lmul_pow_1571)), 3, true); + setArg(call_get_pow_1569, 0, reinterpret_cast(this)); + setArg(call_get_pow_1569, 1, EEW); + setRet(call_get_pow_1569, 0, ret_val_get_pow_1569); + setArg(call_get_sew_pow_1570, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1570, 0, ret_val_get_sew_pow_1570); + setArg(call_get_lmul_pow_1571, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1571, 0, ret_val_get_lmul_pow_1571); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1573; + x86::Gp ret_val_get_lmul_pow_1573 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1573, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1572; + auto illegal_indexed_load_1572_arg4 = EMUL_pow; + auto illegal_indexed_load_1572_arg5 = ret_val_get_lmul_pow_1573; + x86::Gp ret_val_illegal_indexed_load_1572 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1572, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1572; + setArg(call_get_lmul_pow_1573, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1573, 0, ret_val_get_lmul_pow_1573); + setArg(call_illegal_indexed_load_1572, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1572, 1, vd); + setArg(call_illegal_indexed_load_1572, 2, vm); + setArg(call_illegal_indexed_load_1572, 3, 1); + setArg(call_illegal_indexed_load_1572, 4, EEW); + setArg(call_illegal_indexed_load_1572, 5, illegal_indexed_load_1572_arg4); + setArg(call_illegal_indexed_load_1572, 6, illegal_indexed_load_1572_arg5); + setRet(call_illegal_indexed_load_1572, 0, ret_val_illegal_indexed_load_1572); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1575; + x86::Gp ret_val_sew_1575 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1575, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1574; + auto vlxseg_1574_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1574_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1574_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1574_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1574_arg10 = ret_val_sew_1575; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1574 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1574, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1574, 32, false), traits::vstart); + setArg(call_sew_1575, 0, reinterpret_cast(this)); + setRet(call_sew_1575, 0, ret_val_sew_1575); + setArg(call_vlxseg_1574, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1574, 1, V); + setArg(call_vlxseg_1574, 2, vlxseg_1574_arg1); + setArg(call_vlxseg_1574, 3, vlxseg_1574_arg2); + setArg(call_vlxseg_1574, 4, vlxseg_1574_arg3); + setArg(call_vlxseg_1574, 5, vm); + setArg(call_vlxseg_1574, 6, vd); + setArg(call_vlxseg_1574, 7, vlxseg_1574_arg6); + setArg(call_vlxseg_1574, 8, vs2); + setArg(call_vlxseg_1574, 9, 1); + setArg(call_vlxseg_1574, 10, 1); + setArg(call_vlxseg_1574, 11, vlxseg_1574_arg10); + setArg(call_vlxseg_1574, 12, 0); + setRet(call_vlxseg_1574, 0, ret_val_vlxseg_1574); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 409); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 410: VLUXEI16__V */ + continuation_e __vluxei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXEI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 410); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1576; + x86::Gp ret_val_get_pow_1576 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1576, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1577; + x86::Gp ret_val_get_sew_pow_1577 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1577, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1578; + x86::Gp ret_val_get_lmul_pow_1578 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1578, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1576, ret_val_get_sew_pow_1577), ret_val_get_lmul_pow_1578)), 3, true); + setArg(call_get_pow_1576, 0, reinterpret_cast(this)); + setArg(call_get_pow_1576, 1, EEW); + setRet(call_get_pow_1576, 0, ret_val_get_pow_1576); + setArg(call_get_sew_pow_1577, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1577, 0, ret_val_get_sew_pow_1577); + setArg(call_get_lmul_pow_1578, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1578, 0, ret_val_get_lmul_pow_1578); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1580; + x86::Gp ret_val_get_lmul_pow_1580 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1580, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1579; + auto illegal_indexed_load_1579_arg4 = EMUL_pow; + auto illegal_indexed_load_1579_arg5 = ret_val_get_lmul_pow_1580; + x86::Gp ret_val_illegal_indexed_load_1579 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1579, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1579; + setArg(call_get_lmul_pow_1580, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1580, 0, ret_val_get_lmul_pow_1580); + setArg(call_illegal_indexed_load_1579, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1579, 1, vd); + setArg(call_illegal_indexed_load_1579, 2, vm); + setArg(call_illegal_indexed_load_1579, 3, 1); + setArg(call_illegal_indexed_load_1579, 4, EEW); + setArg(call_illegal_indexed_load_1579, 5, illegal_indexed_load_1579_arg4); + setArg(call_illegal_indexed_load_1579, 6, illegal_indexed_load_1579_arg5); + setRet(call_illegal_indexed_load_1579, 0, ret_val_illegal_indexed_load_1579); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1582; + x86::Gp ret_val_sew_1582 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1582, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1581; + auto vlxseg_1581_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1581_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1581_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1581_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1581_arg10 = ret_val_sew_1582; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1581 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1581, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1581, 32, false), traits::vstart); + setArg(call_sew_1582, 0, reinterpret_cast(this)); + setRet(call_sew_1582, 0, ret_val_sew_1582); + setArg(call_vlxseg_1581, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1581, 1, V); + setArg(call_vlxseg_1581, 2, vlxseg_1581_arg1); + setArg(call_vlxseg_1581, 3, vlxseg_1581_arg2); + setArg(call_vlxseg_1581, 4, vlxseg_1581_arg3); + setArg(call_vlxseg_1581, 5, vm); + setArg(call_vlxseg_1581, 6, vd); + setArg(call_vlxseg_1581, 7, vlxseg_1581_arg6); + setArg(call_vlxseg_1581, 8, vs2); + setArg(call_vlxseg_1581, 9, 1); + setArg(call_vlxseg_1581, 10, 2); + setArg(call_vlxseg_1581, 11, vlxseg_1581_arg10); + setArg(call_vlxseg_1581, 12, 0); + setRet(call_vlxseg_1581, 0, ret_val_vlxseg_1581); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 410); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 411: VLUXEI32__V */ + continuation_e __vluxei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXEI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 411); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1583; + x86::Gp ret_val_get_pow_1583 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1583, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1584; + x86::Gp ret_val_get_sew_pow_1584 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1584, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1585; + x86::Gp ret_val_get_lmul_pow_1585 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1585, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1583, ret_val_get_sew_pow_1584), ret_val_get_lmul_pow_1585)), 3, true); + setArg(call_get_pow_1583, 0, reinterpret_cast(this)); + setArg(call_get_pow_1583, 1, EEW); + setRet(call_get_pow_1583, 0, ret_val_get_pow_1583); + setArg(call_get_sew_pow_1584, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1584, 0, ret_val_get_sew_pow_1584); + setArg(call_get_lmul_pow_1585, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1585, 0, ret_val_get_lmul_pow_1585); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1587; + x86::Gp ret_val_get_lmul_pow_1587 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1587, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1586; + auto illegal_indexed_load_1586_arg4 = EMUL_pow; + auto illegal_indexed_load_1586_arg5 = ret_val_get_lmul_pow_1587; + x86::Gp ret_val_illegal_indexed_load_1586 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1586, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1586; + setArg(call_get_lmul_pow_1587, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1587, 0, ret_val_get_lmul_pow_1587); + setArg(call_illegal_indexed_load_1586, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1586, 1, vd); + setArg(call_illegal_indexed_load_1586, 2, vm); + setArg(call_illegal_indexed_load_1586, 3, 1); + setArg(call_illegal_indexed_load_1586, 4, EEW); + setArg(call_illegal_indexed_load_1586, 5, illegal_indexed_load_1586_arg4); + setArg(call_illegal_indexed_load_1586, 6, illegal_indexed_load_1586_arg5); + setRet(call_illegal_indexed_load_1586, 0, ret_val_illegal_indexed_load_1586); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1589; + x86::Gp ret_val_sew_1589 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1589, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1588; + auto vlxseg_1588_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1588_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1588_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1588_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1588_arg10 = ret_val_sew_1589; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1588 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1588, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1588, 32, false), traits::vstart); + setArg(call_sew_1589, 0, reinterpret_cast(this)); + setRet(call_sew_1589, 0, ret_val_sew_1589); + setArg(call_vlxseg_1588, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1588, 1, V); + setArg(call_vlxseg_1588, 2, vlxseg_1588_arg1); + setArg(call_vlxseg_1588, 3, vlxseg_1588_arg2); + setArg(call_vlxseg_1588, 4, vlxseg_1588_arg3); + setArg(call_vlxseg_1588, 5, vm); + setArg(call_vlxseg_1588, 6, vd); + setArg(call_vlxseg_1588, 7, vlxseg_1588_arg6); + setArg(call_vlxseg_1588, 8, vs2); + setArg(call_vlxseg_1588, 9, 1); + setArg(call_vlxseg_1588, 10, 4); + setArg(call_vlxseg_1588, 11, vlxseg_1588_arg10); + setArg(call_vlxseg_1588, 12, 0); + setRet(call_vlxseg_1588, 0, ret_val_vlxseg_1588); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 411); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 412: VLUXEI64__V */ + continuation_e __vluxei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXEI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 412); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1590; + x86::Gp ret_val_get_pow_1590 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1590, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1591; + x86::Gp ret_val_get_sew_pow_1591 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1591, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1592; + x86::Gp ret_val_get_lmul_pow_1592 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1592, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1590, ret_val_get_sew_pow_1591), ret_val_get_lmul_pow_1592)), 3, true); + setArg(call_get_pow_1590, 0, reinterpret_cast(this)); + setArg(call_get_pow_1590, 1, EEW); + setRet(call_get_pow_1590, 0, ret_val_get_pow_1590); + setArg(call_get_sew_pow_1591, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1591, 0, ret_val_get_sew_pow_1591); + setArg(call_get_lmul_pow_1592, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1592, 0, ret_val_get_lmul_pow_1592); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1594; + x86::Gp ret_val_get_lmul_pow_1594 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1594, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1593; + auto illegal_indexed_load_1593_arg4 = EMUL_pow; + auto illegal_indexed_load_1593_arg5 = ret_val_get_lmul_pow_1594; + x86::Gp ret_val_illegal_indexed_load_1593 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1593, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1593; + setArg(call_get_lmul_pow_1594, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1594, 0, ret_val_get_lmul_pow_1594); + setArg(call_illegal_indexed_load_1593, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1593, 1, vd); + setArg(call_illegal_indexed_load_1593, 2, vm); + setArg(call_illegal_indexed_load_1593, 3, 1); + setArg(call_illegal_indexed_load_1593, 4, EEW); + setArg(call_illegal_indexed_load_1593, 5, illegal_indexed_load_1593_arg4); + setArg(call_illegal_indexed_load_1593, 6, illegal_indexed_load_1593_arg5); + setRet(call_illegal_indexed_load_1593, 0, ret_val_illegal_indexed_load_1593); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1596; + x86::Gp ret_val_sew_1596 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1596, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1595; + auto vlxseg_1595_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1595_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1595_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1595_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1595_arg10 = ret_val_sew_1596; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1595 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1595, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1595, 32, false), traits::vstart); + setArg(call_sew_1596, 0, reinterpret_cast(this)); + setRet(call_sew_1596, 0, ret_val_sew_1596); + setArg(call_vlxseg_1595, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1595, 1, V); + setArg(call_vlxseg_1595, 2, vlxseg_1595_arg1); + setArg(call_vlxseg_1595, 3, vlxseg_1595_arg2); + setArg(call_vlxseg_1595, 4, vlxseg_1595_arg3); + setArg(call_vlxseg_1595, 5, vm); + setArg(call_vlxseg_1595, 6, vd); + setArg(call_vlxseg_1595, 7, vlxseg_1595_arg6); + setArg(call_vlxseg_1595, 8, vs2); + setArg(call_vlxseg_1595, 9, 1); + setArg(call_vlxseg_1595, 10, 8); + setArg(call_vlxseg_1595, 11, vlxseg_1595_arg10); + setArg(call_vlxseg_1595, 12, 0); + setRet(call_vlxseg_1595, 0, ret_val_vlxseg_1595); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 412); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 413: VLUXSEG2EI8__V */ + continuation_e __vluxseg2ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG2EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 413); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1597; + x86::Gp ret_val_get_pow_1597 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1597, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1598; + x86::Gp ret_val_get_sew_pow_1598 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1598, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1599; + x86::Gp ret_val_get_lmul_pow_1599 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1599, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1597, ret_val_get_sew_pow_1598), ret_val_get_lmul_pow_1599)), 3, true); + setArg(call_get_pow_1597, 0, reinterpret_cast(this)); + setArg(call_get_pow_1597, 1, EEW); + setRet(call_get_pow_1597, 0, ret_val_get_pow_1597); + setArg(call_get_sew_pow_1598, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1598, 0, ret_val_get_sew_pow_1598); + setArg(call_get_lmul_pow_1599, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1599, 0, ret_val_get_lmul_pow_1599); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1601; + x86::Gp ret_val_get_lmul_pow_1601 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1601, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1600; + auto illegal_indexed_load_1600_arg4 = EMUL_pow; + auto illegal_indexed_load_1600_arg5 = ret_val_get_lmul_pow_1601; + x86::Gp ret_val_illegal_indexed_load_1600 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1600, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1600; + setArg(call_get_lmul_pow_1601, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1601, 0, ret_val_get_lmul_pow_1601); + setArg(call_illegal_indexed_load_1600, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1600, 1, vd); + setArg(call_illegal_indexed_load_1600, 2, vm); + setArg(call_illegal_indexed_load_1600, 3, 2); + setArg(call_illegal_indexed_load_1600, 4, EEW); + setArg(call_illegal_indexed_load_1600, 5, illegal_indexed_load_1600_arg4); + setArg(call_illegal_indexed_load_1600, 6, illegal_indexed_load_1600_arg5); + setRet(call_illegal_indexed_load_1600, 0, ret_val_illegal_indexed_load_1600); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1603; + x86::Gp ret_val_sew_1603 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1603, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1602; + auto vlxseg_1602_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1602_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1602_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1602_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1602_arg10 = ret_val_sew_1603; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1602 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1602, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1602, 32, false), traits::vstart); + setArg(call_sew_1603, 0, reinterpret_cast(this)); + setRet(call_sew_1603, 0, ret_val_sew_1603); + setArg(call_vlxseg_1602, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1602, 1, V); + setArg(call_vlxseg_1602, 2, vlxseg_1602_arg1); + setArg(call_vlxseg_1602, 3, vlxseg_1602_arg2); + setArg(call_vlxseg_1602, 4, vlxseg_1602_arg3); + setArg(call_vlxseg_1602, 5, vm); + setArg(call_vlxseg_1602, 6, vd); + setArg(call_vlxseg_1602, 7, vlxseg_1602_arg6); + setArg(call_vlxseg_1602, 8, vs2); + setArg(call_vlxseg_1602, 9, 2); + setArg(call_vlxseg_1602, 10, 1); + setArg(call_vlxseg_1602, 11, vlxseg_1602_arg10); + setArg(call_vlxseg_1602, 12, 0); + setRet(call_vlxseg_1602, 0, ret_val_vlxseg_1602); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 413); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 414: VLUXSEG2EI16__V */ + continuation_e __vluxseg2ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG2EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 414); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1604; + x86::Gp ret_val_get_pow_1604 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1604, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1605; + x86::Gp ret_val_get_sew_pow_1605 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1605, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1606; + x86::Gp ret_val_get_lmul_pow_1606 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1606, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1604, ret_val_get_sew_pow_1605), ret_val_get_lmul_pow_1606)), 3, true); + setArg(call_get_pow_1604, 0, reinterpret_cast(this)); + setArg(call_get_pow_1604, 1, EEW); + setRet(call_get_pow_1604, 0, ret_val_get_pow_1604); + setArg(call_get_sew_pow_1605, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1605, 0, ret_val_get_sew_pow_1605); + setArg(call_get_lmul_pow_1606, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1606, 0, ret_val_get_lmul_pow_1606); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1608; + x86::Gp ret_val_get_lmul_pow_1608 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1608, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1607; + auto illegal_indexed_load_1607_arg4 = EMUL_pow; + auto illegal_indexed_load_1607_arg5 = ret_val_get_lmul_pow_1608; + x86::Gp ret_val_illegal_indexed_load_1607 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1607, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1607; + setArg(call_get_lmul_pow_1608, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1608, 0, ret_val_get_lmul_pow_1608); + setArg(call_illegal_indexed_load_1607, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1607, 1, vd); + setArg(call_illegal_indexed_load_1607, 2, vm); + setArg(call_illegal_indexed_load_1607, 3, 2); + setArg(call_illegal_indexed_load_1607, 4, EEW); + setArg(call_illegal_indexed_load_1607, 5, illegal_indexed_load_1607_arg4); + setArg(call_illegal_indexed_load_1607, 6, illegal_indexed_load_1607_arg5); + setRet(call_illegal_indexed_load_1607, 0, ret_val_illegal_indexed_load_1607); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1610; + x86::Gp ret_val_sew_1610 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1610, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1609; + auto vlxseg_1609_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1609_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1609_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1609_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1609_arg10 = ret_val_sew_1610; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1609 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1609, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1609, 32, false), traits::vstart); + setArg(call_sew_1610, 0, reinterpret_cast(this)); + setRet(call_sew_1610, 0, ret_val_sew_1610); + setArg(call_vlxseg_1609, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1609, 1, V); + setArg(call_vlxseg_1609, 2, vlxseg_1609_arg1); + setArg(call_vlxseg_1609, 3, vlxseg_1609_arg2); + setArg(call_vlxseg_1609, 4, vlxseg_1609_arg3); + setArg(call_vlxseg_1609, 5, vm); + setArg(call_vlxseg_1609, 6, vd); + setArg(call_vlxseg_1609, 7, vlxseg_1609_arg6); + setArg(call_vlxseg_1609, 8, vs2); + setArg(call_vlxseg_1609, 9, 2); + setArg(call_vlxseg_1609, 10, 2); + setArg(call_vlxseg_1609, 11, vlxseg_1609_arg10); + setArg(call_vlxseg_1609, 12, 0); + setRet(call_vlxseg_1609, 0, ret_val_vlxseg_1609); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 414); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 415: VLUXSEG2EI32__V */ + continuation_e __vluxseg2ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG2EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 415); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1611; + x86::Gp ret_val_get_pow_1611 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1611, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1612; + x86::Gp ret_val_get_sew_pow_1612 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1612, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1613; + x86::Gp ret_val_get_lmul_pow_1613 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1613, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1611, ret_val_get_sew_pow_1612), ret_val_get_lmul_pow_1613)), 3, true); + setArg(call_get_pow_1611, 0, reinterpret_cast(this)); + setArg(call_get_pow_1611, 1, EEW); + setRet(call_get_pow_1611, 0, ret_val_get_pow_1611); + setArg(call_get_sew_pow_1612, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1612, 0, ret_val_get_sew_pow_1612); + setArg(call_get_lmul_pow_1613, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1613, 0, ret_val_get_lmul_pow_1613); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1615; + x86::Gp ret_val_get_lmul_pow_1615 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1615, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1614; + auto illegal_indexed_load_1614_arg4 = EMUL_pow; + auto illegal_indexed_load_1614_arg5 = ret_val_get_lmul_pow_1615; + x86::Gp ret_val_illegal_indexed_load_1614 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1614, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1614; + setArg(call_get_lmul_pow_1615, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1615, 0, ret_val_get_lmul_pow_1615); + setArg(call_illegal_indexed_load_1614, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1614, 1, vd); + setArg(call_illegal_indexed_load_1614, 2, vm); + setArg(call_illegal_indexed_load_1614, 3, 2); + setArg(call_illegal_indexed_load_1614, 4, EEW); + setArg(call_illegal_indexed_load_1614, 5, illegal_indexed_load_1614_arg4); + setArg(call_illegal_indexed_load_1614, 6, illegal_indexed_load_1614_arg5); + setRet(call_illegal_indexed_load_1614, 0, ret_val_illegal_indexed_load_1614); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1617; + x86::Gp ret_val_sew_1617 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1617, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1616; + auto vlxseg_1616_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1616_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1616_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1616_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1616_arg10 = ret_val_sew_1617; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1616 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1616, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1616, 32, false), traits::vstart); + setArg(call_sew_1617, 0, reinterpret_cast(this)); + setRet(call_sew_1617, 0, ret_val_sew_1617); + setArg(call_vlxseg_1616, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1616, 1, V); + setArg(call_vlxseg_1616, 2, vlxseg_1616_arg1); + setArg(call_vlxseg_1616, 3, vlxseg_1616_arg2); + setArg(call_vlxseg_1616, 4, vlxseg_1616_arg3); + setArg(call_vlxseg_1616, 5, vm); + setArg(call_vlxseg_1616, 6, vd); + setArg(call_vlxseg_1616, 7, vlxseg_1616_arg6); + setArg(call_vlxseg_1616, 8, vs2); + setArg(call_vlxseg_1616, 9, 2); + setArg(call_vlxseg_1616, 10, 4); + setArg(call_vlxseg_1616, 11, vlxseg_1616_arg10); + setArg(call_vlxseg_1616, 12, 0); + setRet(call_vlxseg_1616, 0, ret_val_vlxseg_1616); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 415); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 416: VLUXSEG2EI64__V */ + continuation_e __vluxseg2ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG2EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 416); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1618; + x86::Gp ret_val_get_pow_1618 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1618, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1619; + x86::Gp ret_val_get_sew_pow_1619 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1619, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1620; + x86::Gp ret_val_get_lmul_pow_1620 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1620, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1618, ret_val_get_sew_pow_1619), ret_val_get_lmul_pow_1620)), 3, true); + setArg(call_get_pow_1618, 0, reinterpret_cast(this)); + setArg(call_get_pow_1618, 1, EEW); + setRet(call_get_pow_1618, 0, ret_val_get_pow_1618); + setArg(call_get_sew_pow_1619, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1619, 0, ret_val_get_sew_pow_1619); + setArg(call_get_lmul_pow_1620, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1620, 0, ret_val_get_lmul_pow_1620); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1622; + x86::Gp ret_val_get_lmul_pow_1622 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1622, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1621; + auto illegal_indexed_load_1621_arg4 = EMUL_pow; + auto illegal_indexed_load_1621_arg5 = ret_val_get_lmul_pow_1622; + x86::Gp ret_val_illegal_indexed_load_1621 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1621, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1621; + setArg(call_get_lmul_pow_1622, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1622, 0, ret_val_get_lmul_pow_1622); + setArg(call_illegal_indexed_load_1621, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1621, 1, vd); + setArg(call_illegal_indexed_load_1621, 2, vm); + setArg(call_illegal_indexed_load_1621, 3, 2); + setArg(call_illegal_indexed_load_1621, 4, EEW); + setArg(call_illegal_indexed_load_1621, 5, illegal_indexed_load_1621_arg4); + setArg(call_illegal_indexed_load_1621, 6, illegal_indexed_load_1621_arg5); + setRet(call_illegal_indexed_load_1621, 0, ret_val_illegal_indexed_load_1621); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1624; + x86::Gp ret_val_sew_1624 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1624, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1623; + auto vlxseg_1623_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1623_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1623_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1623_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1623_arg10 = ret_val_sew_1624; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1623 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1623, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1623, 32, false), traits::vstart); + setArg(call_sew_1624, 0, reinterpret_cast(this)); + setRet(call_sew_1624, 0, ret_val_sew_1624); + setArg(call_vlxseg_1623, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1623, 1, V); + setArg(call_vlxseg_1623, 2, vlxseg_1623_arg1); + setArg(call_vlxseg_1623, 3, vlxseg_1623_arg2); + setArg(call_vlxseg_1623, 4, vlxseg_1623_arg3); + setArg(call_vlxseg_1623, 5, vm); + setArg(call_vlxseg_1623, 6, vd); + setArg(call_vlxseg_1623, 7, vlxseg_1623_arg6); + setArg(call_vlxseg_1623, 8, vs2); + setArg(call_vlxseg_1623, 9, 2); + setArg(call_vlxseg_1623, 10, 8); + setArg(call_vlxseg_1623, 11, vlxseg_1623_arg10); + setArg(call_vlxseg_1623, 12, 0); + setRet(call_vlxseg_1623, 0, ret_val_vlxseg_1623); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 416); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 417: VLUXSEG3EI8__V */ + continuation_e __vluxseg3ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG3EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 417); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1625; + x86::Gp ret_val_get_pow_1625 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1625, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1626; + x86::Gp ret_val_get_sew_pow_1626 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1626, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1627; + x86::Gp ret_val_get_lmul_pow_1627 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1627, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1625, ret_val_get_sew_pow_1626), ret_val_get_lmul_pow_1627)), 3, true); + setArg(call_get_pow_1625, 0, reinterpret_cast(this)); + setArg(call_get_pow_1625, 1, EEW); + setRet(call_get_pow_1625, 0, ret_val_get_pow_1625); + setArg(call_get_sew_pow_1626, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1626, 0, ret_val_get_sew_pow_1626); + setArg(call_get_lmul_pow_1627, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1627, 0, ret_val_get_lmul_pow_1627); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1629; + x86::Gp ret_val_get_lmul_pow_1629 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1629, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1628; + auto illegal_indexed_load_1628_arg4 = EMUL_pow; + auto illegal_indexed_load_1628_arg5 = ret_val_get_lmul_pow_1629; + x86::Gp ret_val_illegal_indexed_load_1628 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1628, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1628; + setArg(call_get_lmul_pow_1629, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1629, 0, ret_val_get_lmul_pow_1629); + setArg(call_illegal_indexed_load_1628, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1628, 1, vd); + setArg(call_illegal_indexed_load_1628, 2, vm); + setArg(call_illegal_indexed_load_1628, 3, 3); + setArg(call_illegal_indexed_load_1628, 4, EEW); + setArg(call_illegal_indexed_load_1628, 5, illegal_indexed_load_1628_arg4); + setArg(call_illegal_indexed_load_1628, 6, illegal_indexed_load_1628_arg5); + setRet(call_illegal_indexed_load_1628, 0, ret_val_illegal_indexed_load_1628); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1631; + x86::Gp ret_val_sew_1631 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1631, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1630; + auto vlxseg_1630_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1630_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1630_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1630_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1630_arg10 = ret_val_sew_1631; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1630 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1630, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1630, 32, false), traits::vstart); + setArg(call_sew_1631, 0, reinterpret_cast(this)); + setRet(call_sew_1631, 0, ret_val_sew_1631); + setArg(call_vlxseg_1630, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1630, 1, V); + setArg(call_vlxseg_1630, 2, vlxseg_1630_arg1); + setArg(call_vlxseg_1630, 3, vlxseg_1630_arg2); + setArg(call_vlxseg_1630, 4, vlxseg_1630_arg3); + setArg(call_vlxseg_1630, 5, vm); + setArg(call_vlxseg_1630, 6, vd); + setArg(call_vlxseg_1630, 7, vlxseg_1630_arg6); + setArg(call_vlxseg_1630, 8, vs2); + setArg(call_vlxseg_1630, 9, 3); + setArg(call_vlxseg_1630, 10, 1); + setArg(call_vlxseg_1630, 11, vlxseg_1630_arg10); + setArg(call_vlxseg_1630, 12, 0); + setRet(call_vlxseg_1630, 0, ret_val_vlxseg_1630); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 417); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 418: VLUXSEG3EI16__V */ + continuation_e __vluxseg3ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG3EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 418); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1632; + x86::Gp ret_val_get_pow_1632 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1632, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1633; + x86::Gp ret_val_get_sew_pow_1633 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1633, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1634; + x86::Gp ret_val_get_lmul_pow_1634 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1634, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1632, ret_val_get_sew_pow_1633), ret_val_get_lmul_pow_1634)), 3, true); + setArg(call_get_pow_1632, 0, reinterpret_cast(this)); + setArg(call_get_pow_1632, 1, EEW); + setRet(call_get_pow_1632, 0, ret_val_get_pow_1632); + setArg(call_get_sew_pow_1633, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1633, 0, ret_val_get_sew_pow_1633); + setArg(call_get_lmul_pow_1634, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1634, 0, ret_val_get_lmul_pow_1634); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1636; + x86::Gp ret_val_get_lmul_pow_1636 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1636, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1635; + auto illegal_indexed_load_1635_arg4 = EMUL_pow; + auto illegal_indexed_load_1635_arg5 = ret_val_get_lmul_pow_1636; + x86::Gp ret_val_illegal_indexed_load_1635 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1635, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1635; + setArg(call_get_lmul_pow_1636, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1636, 0, ret_val_get_lmul_pow_1636); + setArg(call_illegal_indexed_load_1635, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1635, 1, vd); + setArg(call_illegal_indexed_load_1635, 2, vm); + setArg(call_illegal_indexed_load_1635, 3, 3); + setArg(call_illegal_indexed_load_1635, 4, EEW); + setArg(call_illegal_indexed_load_1635, 5, illegal_indexed_load_1635_arg4); + setArg(call_illegal_indexed_load_1635, 6, illegal_indexed_load_1635_arg5); + setRet(call_illegal_indexed_load_1635, 0, ret_val_illegal_indexed_load_1635); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1638; + x86::Gp ret_val_sew_1638 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1638, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1637; + auto vlxseg_1637_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1637_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1637_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1637_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1637_arg10 = ret_val_sew_1638; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1637 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1637, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1637, 32, false), traits::vstart); + setArg(call_sew_1638, 0, reinterpret_cast(this)); + setRet(call_sew_1638, 0, ret_val_sew_1638); + setArg(call_vlxseg_1637, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1637, 1, V); + setArg(call_vlxseg_1637, 2, vlxseg_1637_arg1); + setArg(call_vlxseg_1637, 3, vlxseg_1637_arg2); + setArg(call_vlxseg_1637, 4, vlxseg_1637_arg3); + setArg(call_vlxseg_1637, 5, vm); + setArg(call_vlxseg_1637, 6, vd); + setArg(call_vlxseg_1637, 7, vlxseg_1637_arg6); + setArg(call_vlxseg_1637, 8, vs2); + setArg(call_vlxseg_1637, 9, 3); + setArg(call_vlxseg_1637, 10, 2); + setArg(call_vlxseg_1637, 11, vlxseg_1637_arg10); + setArg(call_vlxseg_1637, 12, 0); + setRet(call_vlxseg_1637, 0, ret_val_vlxseg_1637); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 418); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 419: VLUXSEG3EI32__V */ + continuation_e __vluxseg3ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG3EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 419); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1639; + x86::Gp ret_val_get_pow_1639 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1639, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1640; + x86::Gp ret_val_get_sew_pow_1640 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1640, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1641; + x86::Gp ret_val_get_lmul_pow_1641 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1641, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1639, ret_val_get_sew_pow_1640), ret_val_get_lmul_pow_1641)), 3, true); + setArg(call_get_pow_1639, 0, reinterpret_cast(this)); + setArg(call_get_pow_1639, 1, EEW); + setRet(call_get_pow_1639, 0, ret_val_get_pow_1639); + setArg(call_get_sew_pow_1640, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1640, 0, ret_val_get_sew_pow_1640); + setArg(call_get_lmul_pow_1641, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1641, 0, ret_val_get_lmul_pow_1641); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1643; + x86::Gp ret_val_get_lmul_pow_1643 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1643, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1642; + auto illegal_indexed_load_1642_arg4 = EMUL_pow; + auto illegal_indexed_load_1642_arg5 = ret_val_get_lmul_pow_1643; + x86::Gp ret_val_illegal_indexed_load_1642 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1642, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1642; + setArg(call_get_lmul_pow_1643, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1643, 0, ret_val_get_lmul_pow_1643); + setArg(call_illegal_indexed_load_1642, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1642, 1, vd); + setArg(call_illegal_indexed_load_1642, 2, vm); + setArg(call_illegal_indexed_load_1642, 3, 3); + setArg(call_illegal_indexed_load_1642, 4, EEW); + setArg(call_illegal_indexed_load_1642, 5, illegal_indexed_load_1642_arg4); + setArg(call_illegal_indexed_load_1642, 6, illegal_indexed_load_1642_arg5); + setRet(call_illegal_indexed_load_1642, 0, ret_val_illegal_indexed_load_1642); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1645; + x86::Gp ret_val_sew_1645 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1645, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1644; + auto vlxseg_1644_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1644_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1644_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1644_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1644_arg10 = ret_val_sew_1645; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1644 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1644, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1644, 32, false), traits::vstart); + setArg(call_sew_1645, 0, reinterpret_cast(this)); + setRet(call_sew_1645, 0, ret_val_sew_1645); + setArg(call_vlxseg_1644, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1644, 1, V); + setArg(call_vlxseg_1644, 2, vlxseg_1644_arg1); + setArg(call_vlxseg_1644, 3, vlxseg_1644_arg2); + setArg(call_vlxseg_1644, 4, vlxseg_1644_arg3); + setArg(call_vlxseg_1644, 5, vm); + setArg(call_vlxseg_1644, 6, vd); + setArg(call_vlxseg_1644, 7, vlxseg_1644_arg6); + setArg(call_vlxseg_1644, 8, vs2); + setArg(call_vlxseg_1644, 9, 3); + setArg(call_vlxseg_1644, 10, 4); + setArg(call_vlxseg_1644, 11, vlxseg_1644_arg10); + setArg(call_vlxseg_1644, 12, 0); + setRet(call_vlxseg_1644, 0, ret_val_vlxseg_1644); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 419); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 420: VLUXSEG3EI64__V */ + continuation_e __vluxseg3ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG3EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 420); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1646; + x86::Gp ret_val_get_pow_1646 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1646, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1647; + x86::Gp ret_val_get_sew_pow_1647 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1647, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1648; + x86::Gp ret_val_get_lmul_pow_1648 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1648, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1646, ret_val_get_sew_pow_1647), ret_val_get_lmul_pow_1648)), 3, true); + setArg(call_get_pow_1646, 0, reinterpret_cast(this)); + setArg(call_get_pow_1646, 1, EEW); + setRet(call_get_pow_1646, 0, ret_val_get_pow_1646); + setArg(call_get_sew_pow_1647, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1647, 0, ret_val_get_sew_pow_1647); + setArg(call_get_lmul_pow_1648, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1648, 0, ret_val_get_lmul_pow_1648); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1650; + x86::Gp ret_val_get_lmul_pow_1650 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1650, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1649; + auto illegal_indexed_load_1649_arg4 = EMUL_pow; + auto illegal_indexed_load_1649_arg5 = ret_val_get_lmul_pow_1650; + x86::Gp ret_val_illegal_indexed_load_1649 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1649, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1649; + setArg(call_get_lmul_pow_1650, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1650, 0, ret_val_get_lmul_pow_1650); + setArg(call_illegal_indexed_load_1649, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1649, 1, vd); + setArg(call_illegal_indexed_load_1649, 2, vm); + setArg(call_illegal_indexed_load_1649, 3, 3); + setArg(call_illegal_indexed_load_1649, 4, EEW); + setArg(call_illegal_indexed_load_1649, 5, illegal_indexed_load_1649_arg4); + setArg(call_illegal_indexed_load_1649, 6, illegal_indexed_load_1649_arg5); + setRet(call_illegal_indexed_load_1649, 0, ret_val_illegal_indexed_load_1649); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1652; + x86::Gp ret_val_sew_1652 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1652, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1651; + auto vlxseg_1651_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1651_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1651_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1651_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1651_arg10 = ret_val_sew_1652; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1651 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1651, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1651, 32, false), traits::vstart); + setArg(call_sew_1652, 0, reinterpret_cast(this)); + setRet(call_sew_1652, 0, ret_val_sew_1652); + setArg(call_vlxseg_1651, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1651, 1, V); + setArg(call_vlxseg_1651, 2, vlxseg_1651_arg1); + setArg(call_vlxseg_1651, 3, vlxseg_1651_arg2); + setArg(call_vlxseg_1651, 4, vlxseg_1651_arg3); + setArg(call_vlxseg_1651, 5, vm); + setArg(call_vlxseg_1651, 6, vd); + setArg(call_vlxseg_1651, 7, vlxseg_1651_arg6); + setArg(call_vlxseg_1651, 8, vs2); + setArg(call_vlxseg_1651, 9, 3); + setArg(call_vlxseg_1651, 10, 8); + setArg(call_vlxseg_1651, 11, vlxseg_1651_arg10); + setArg(call_vlxseg_1651, 12, 0); + setRet(call_vlxseg_1651, 0, ret_val_vlxseg_1651); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 420); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 421: VLUXSEG4EI8__V */ + continuation_e __vluxseg4ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG4EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 421); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1653; + x86::Gp ret_val_get_pow_1653 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1653, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1654; + x86::Gp ret_val_get_sew_pow_1654 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1654, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1655; + x86::Gp ret_val_get_lmul_pow_1655 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1655, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1653, ret_val_get_sew_pow_1654), ret_val_get_lmul_pow_1655)), 3, true); + setArg(call_get_pow_1653, 0, reinterpret_cast(this)); + setArg(call_get_pow_1653, 1, EEW); + setRet(call_get_pow_1653, 0, ret_val_get_pow_1653); + setArg(call_get_sew_pow_1654, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1654, 0, ret_val_get_sew_pow_1654); + setArg(call_get_lmul_pow_1655, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1655, 0, ret_val_get_lmul_pow_1655); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1657; + x86::Gp ret_val_get_lmul_pow_1657 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1657, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1656; + auto illegal_indexed_load_1656_arg4 = EMUL_pow; + auto illegal_indexed_load_1656_arg5 = ret_val_get_lmul_pow_1657; + x86::Gp ret_val_illegal_indexed_load_1656 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1656, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1656; + setArg(call_get_lmul_pow_1657, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1657, 0, ret_val_get_lmul_pow_1657); + setArg(call_illegal_indexed_load_1656, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1656, 1, vd); + setArg(call_illegal_indexed_load_1656, 2, vm); + setArg(call_illegal_indexed_load_1656, 3, 4); + setArg(call_illegal_indexed_load_1656, 4, EEW); + setArg(call_illegal_indexed_load_1656, 5, illegal_indexed_load_1656_arg4); + setArg(call_illegal_indexed_load_1656, 6, illegal_indexed_load_1656_arg5); + setRet(call_illegal_indexed_load_1656, 0, ret_val_illegal_indexed_load_1656); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1659; + x86::Gp ret_val_sew_1659 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1659, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1658; + auto vlxseg_1658_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1658_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1658_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1658_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1658_arg10 = ret_val_sew_1659; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1658 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1658, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1658, 32, false), traits::vstart); + setArg(call_sew_1659, 0, reinterpret_cast(this)); + setRet(call_sew_1659, 0, ret_val_sew_1659); + setArg(call_vlxseg_1658, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1658, 1, V); + setArg(call_vlxseg_1658, 2, vlxseg_1658_arg1); + setArg(call_vlxseg_1658, 3, vlxseg_1658_arg2); + setArg(call_vlxseg_1658, 4, vlxseg_1658_arg3); + setArg(call_vlxseg_1658, 5, vm); + setArg(call_vlxseg_1658, 6, vd); + setArg(call_vlxseg_1658, 7, vlxseg_1658_arg6); + setArg(call_vlxseg_1658, 8, vs2); + setArg(call_vlxseg_1658, 9, 4); + setArg(call_vlxseg_1658, 10, 1); + setArg(call_vlxseg_1658, 11, vlxseg_1658_arg10); + setArg(call_vlxseg_1658, 12, 0); + setRet(call_vlxseg_1658, 0, ret_val_vlxseg_1658); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 421); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 422: VLUXSEG4EI16__V */ + continuation_e __vluxseg4ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG4EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 422); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1660; + x86::Gp ret_val_get_pow_1660 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1660, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1661; + x86::Gp ret_val_get_sew_pow_1661 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1661, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1662; + x86::Gp ret_val_get_lmul_pow_1662 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1662, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1660, ret_val_get_sew_pow_1661), ret_val_get_lmul_pow_1662)), 3, true); + setArg(call_get_pow_1660, 0, reinterpret_cast(this)); + setArg(call_get_pow_1660, 1, EEW); + setRet(call_get_pow_1660, 0, ret_val_get_pow_1660); + setArg(call_get_sew_pow_1661, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1661, 0, ret_val_get_sew_pow_1661); + setArg(call_get_lmul_pow_1662, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1662, 0, ret_val_get_lmul_pow_1662); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1664; + x86::Gp ret_val_get_lmul_pow_1664 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1664, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1663; + auto illegal_indexed_load_1663_arg4 = EMUL_pow; + auto illegal_indexed_load_1663_arg5 = ret_val_get_lmul_pow_1664; + x86::Gp ret_val_illegal_indexed_load_1663 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1663, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1663; + setArg(call_get_lmul_pow_1664, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1664, 0, ret_val_get_lmul_pow_1664); + setArg(call_illegal_indexed_load_1663, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1663, 1, vd); + setArg(call_illegal_indexed_load_1663, 2, vm); + setArg(call_illegal_indexed_load_1663, 3, 4); + setArg(call_illegal_indexed_load_1663, 4, EEW); + setArg(call_illegal_indexed_load_1663, 5, illegal_indexed_load_1663_arg4); + setArg(call_illegal_indexed_load_1663, 6, illegal_indexed_load_1663_arg5); + setRet(call_illegal_indexed_load_1663, 0, ret_val_illegal_indexed_load_1663); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1666; + x86::Gp ret_val_sew_1666 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1666, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1665; + auto vlxseg_1665_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1665_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1665_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1665_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1665_arg10 = ret_val_sew_1666; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1665 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1665, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1665, 32, false), traits::vstart); + setArg(call_sew_1666, 0, reinterpret_cast(this)); + setRet(call_sew_1666, 0, ret_val_sew_1666); + setArg(call_vlxseg_1665, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1665, 1, V); + setArg(call_vlxseg_1665, 2, vlxseg_1665_arg1); + setArg(call_vlxseg_1665, 3, vlxseg_1665_arg2); + setArg(call_vlxseg_1665, 4, vlxseg_1665_arg3); + setArg(call_vlxseg_1665, 5, vm); + setArg(call_vlxseg_1665, 6, vd); + setArg(call_vlxseg_1665, 7, vlxseg_1665_arg6); + setArg(call_vlxseg_1665, 8, vs2); + setArg(call_vlxseg_1665, 9, 4); + setArg(call_vlxseg_1665, 10, 2); + setArg(call_vlxseg_1665, 11, vlxseg_1665_arg10); + setArg(call_vlxseg_1665, 12, 0); + setRet(call_vlxseg_1665, 0, ret_val_vlxseg_1665); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 422); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 423: VLUXSEG4EI32__V */ + continuation_e __vluxseg4ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG4EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 423); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1667; + x86::Gp ret_val_get_pow_1667 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1667, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1668; + x86::Gp ret_val_get_sew_pow_1668 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1668, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1669; + x86::Gp ret_val_get_lmul_pow_1669 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1669, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1667, ret_val_get_sew_pow_1668), ret_val_get_lmul_pow_1669)), 3, true); + setArg(call_get_pow_1667, 0, reinterpret_cast(this)); + setArg(call_get_pow_1667, 1, EEW); + setRet(call_get_pow_1667, 0, ret_val_get_pow_1667); + setArg(call_get_sew_pow_1668, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1668, 0, ret_val_get_sew_pow_1668); + setArg(call_get_lmul_pow_1669, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1669, 0, ret_val_get_lmul_pow_1669); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1671; + x86::Gp ret_val_get_lmul_pow_1671 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1671, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1670; + auto illegal_indexed_load_1670_arg4 = EMUL_pow; + auto illegal_indexed_load_1670_arg5 = ret_val_get_lmul_pow_1671; + x86::Gp ret_val_illegal_indexed_load_1670 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1670, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1670; + setArg(call_get_lmul_pow_1671, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1671, 0, ret_val_get_lmul_pow_1671); + setArg(call_illegal_indexed_load_1670, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1670, 1, vd); + setArg(call_illegal_indexed_load_1670, 2, vm); + setArg(call_illegal_indexed_load_1670, 3, 4); + setArg(call_illegal_indexed_load_1670, 4, EEW); + setArg(call_illegal_indexed_load_1670, 5, illegal_indexed_load_1670_arg4); + setArg(call_illegal_indexed_load_1670, 6, illegal_indexed_load_1670_arg5); + setRet(call_illegal_indexed_load_1670, 0, ret_val_illegal_indexed_load_1670); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1673; + x86::Gp ret_val_sew_1673 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1673, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1672; + auto vlxseg_1672_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1672_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1672_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1672_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1672_arg10 = ret_val_sew_1673; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1672 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1672, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1672, 32, false), traits::vstart); + setArg(call_sew_1673, 0, reinterpret_cast(this)); + setRet(call_sew_1673, 0, ret_val_sew_1673); + setArg(call_vlxseg_1672, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1672, 1, V); + setArg(call_vlxseg_1672, 2, vlxseg_1672_arg1); + setArg(call_vlxseg_1672, 3, vlxseg_1672_arg2); + setArg(call_vlxseg_1672, 4, vlxseg_1672_arg3); + setArg(call_vlxseg_1672, 5, vm); + setArg(call_vlxseg_1672, 6, vd); + setArg(call_vlxseg_1672, 7, vlxseg_1672_arg6); + setArg(call_vlxseg_1672, 8, vs2); + setArg(call_vlxseg_1672, 9, 4); + setArg(call_vlxseg_1672, 10, 4); + setArg(call_vlxseg_1672, 11, vlxseg_1672_arg10); + setArg(call_vlxseg_1672, 12, 0); + setRet(call_vlxseg_1672, 0, ret_val_vlxseg_1672); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 423); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 424: VLUXSEG4EI64__V */ + continuation_e __vluxseg4ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG4EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 424); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1674; + x86::Gp ret_val_get_pow_1674 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1674, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1675; + x86::Gp ret_val_get_sew_pow_1675 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1675, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1676; + x86::Gp ret_val_get_lmul_pow_1676 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1676, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1674, ret_val_get_sew_pow_1675), ret_val_get_lmul_pow_1676)), 3, true); + setArg(call_get_pow_1674, 0, reinterpret_cast(this)); + setArg(call_get_pow_1674, 1, EEW); + setRet(call_get_pow_1674, 0, ret_val_get_pow_1674); + setArg(call_get_sew_pow_1675, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1675, 0, ret_val_get_sew_pow_1675); + setArg(call_get_lmul_pow_1676, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1676, 0, ret_val_get_lmul_pow_1676); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1678; + x86::Gp ret_val_get_lmul_pow_1678 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1678, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1677; + auto illegal_indexed_load_1677_arg4 = EMUL_pow; + auto illegal_indexed_load_1677_arg5 = ret_val_get_lmul_pow_1678; + x86::Gp ret_val_illegal_indexed_load_1677 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1677, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1677; + setArg(call_get_lmul_pow_1678, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1678, 0, ret_val_get_lmul_pow_1678); + setArg(call_illegal_indexed_load_1677, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1677, 1, vd); + setArg(call_illegal_indexed_load_1677, 2, vm); + setArg(call_illegal_indexed_load_1677, 3, 4); + setArg(call_illegal_indexed_load_1677, 4, EEW); + setArg(call_illegal_indexed_load_1677, 5, illegal_indexed_load_1677_arg4); + setArg(call_illegal_indexed_load_1677, 6, illegal_indexed_load_1677_arg5); + setRet(call_illegal_indexed_load_1677, 0, ret_val_illegal_indexed_load_1677); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1680; + x86::Gp ret_val_sew_1680 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1680, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1679; + auto vlxseg_1679_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1679_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1679_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1679_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1679_arg10 = ret_val_sew_1680; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1679 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1679, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1679, 32, false), traits::vstart); + setArg(call_sew_1680, 0, reinterpret_cast(this)); + setRet(call_sew_1680, 0, ret_val_sew_1680); + setArg(call_vlxseg_1679, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1679, 1, V); + setArg(call_vlxseg_1679, 2, vlxseg_1679_arg1); + setArg(call_vlxseg_1679, 3, vlxseg_1679_arg2); + setArg(call_vlxseg_1679, 4, vlxseg_1679_arg3); + setArg(call_vlxseg_1679, 5, vm); + setArg(call_vlxseg_1679, 6, vd); + setArg(call_vlxseg_1679, 7, vlxseg_1679_arg6); + setArg(call_vlxseg_1679, 8, vs2); + setArg(call_vlxseg_1679, 9, 4); + setArg(call_vlxseg_1679, 10, 8); + setArg(call_vlxseg_1679, 11, vlxseg_1679_arg10); + setArg(call_vlxseg_1679, 12, 0); + setRet(call_vlxseg_1679, 0, ret_val_vlxseg_1679); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 424); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 425: VLUXSEG5EI8__V */ + continuation_e __vluxseg5ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG5EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 425); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1681; + x86::Gp ret_val_get_pow_1681 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1681, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1682; + x86::Gp ret_val_get_sew_pow_1682 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1682, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1683; + x86::Gp ret_val_get_lmul_pow_1683 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1683, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1681, ret_val_get_sew_pow_1682), ret_val_get_lmul_pow_1683)), 3, true); + setArg(call_get_pow_1681, 0, reinterpret_cast(this)); + setArg(call_get_pow_1681, 1, EEW); + setRet(call_get_pow_1681, 0, ret_val_get_pow_1681); + setArg(call_get_sew_pow_1682, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1682, 0, ret_val_get_sew_pow_1682); + setArg(call_get_lmul_pow_1683, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1683, 0, ret_val_get_lmul_pow_1683); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1685; + x86::Gp ret_val_get_lmul_pow_1685 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1685, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1684; + auto illegal_indexed_load_1684_arg4 = EMUL_pow; + auto illegal_indexed_load_1684_arg5 = ret_val_get_lmul_pow_1685; + x86::Gp ret_val_illegal_indexed_load_1684 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1684, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1684; + setArg(call_get_lmul_pow_1685, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1685, 0, ret_val_get_lmul_pow_1685); + setArg(call_illegal_indexed_load_1684, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1684, 1, vd); + setArg(call_illegal_indexed_load_1684, 2, vm); + setArg(call_illegal_indexed_load_1684, 3, 5); + setArg(call_illegal_indexed_load_1684, 4, EEW); + setArg(call_illegal_indexed_load_1684, 5, illegal_indexed_load_1684_arg4); + setArg(call_illegal_indexed_load_1684, 6, illegal_indexed_load_1684_arg5); + setRet(call_illegal_indexed_load_1684, 0, ret_val_illegal_indexed_load_1684); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1687; + x86::Gp ret_val_sew_1687 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1687, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1686; + auto vlxseg_1686_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1686_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1686_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1686_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1686_arg10 = ret_val_sew_1687; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1686 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1686, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1686, 32, false), traits::vstart); + setArg(call_sew_1687, 0, reinterpret_cast(this)); + setRet(call_sew_1687, 0, ret_val_sew_1687); + setArg(call_vlxseg_1686, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1686, 1, V); + setArg(call_vlxseg_1686, 2, vlxseg_1686_arg1); + setArg(call_vlxseg_1686, 3, vlxseg_1686_arg2); + setArg(call_vlxseg_1686, 4, vlxseg_1686_arg3); + setArg(call_vlxseg_1686, 5, vm); + setArg(call_vlxseg_1686, 6, vd); + setArg(call_vlxseg_1686, 7, vlxseg_1686_arg6); + setArg(call_vlxseg_1686, 8, vs2); + setArg(call_vlxseg_1686, 9, 5); + setArg(call_vlxseg_1686, 10, 1); + setArg(call_vlxseg_1686, 11, vlxseg_1686_arg10); + setArg(call_vlxseg_1686, 12, 0); + setRet(call_vlxseg_1686, 0, ret_val_vlxseg_1686); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 425); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 426: VLUXSEG5EI16__V */ + continuation_e __vluxseg5ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG5EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 426); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1688; + x86::Gp ret_val_get_pow_1688 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1688, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1689; + x86::Gp ret_val_get_sew_pow_1689 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1689, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1690; + x86::Gp ret_val_get_lmul_pow_1690 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1690, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1688, ret_val_get_sew_pow_1689), ret_val_get_lmul_pow_1690)), 3, true); + setArg(call_get_pow_1688, 0, reinterpret_cast(this)); + setArg(call_get_pow_1688, 1, EEW); + setRet(call_get_pow_1688, 0, ret_val_get_pow_1688); + setArg(call_get_sew_pow_1689, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1689, 0, ret_val_get_sew_pow_1689); + setArg(call_get_lmul_pow_1690, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1690, 0, ret_val_get_lmul_pow_1690); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1692; + x86::Gp ret_val_get_lmul_pow_1692 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1692, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1691; + auto illegal_indexed_load_1691_arg4 = EMUL_pow; + auto illegal_indexed_load_1691_arg5 = ret_val_get_lmul_pow_1692; + x86::Gp ret_val_illegal_indexed_load_1691 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1691, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1691; + setArg(call_get_lmul_pow_1692, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1692, 0, ret_val_get_lmul_pow_1692); + setArg(call_illegal_indexed_load_1691, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1691, 1, vd); + setArg(call_illegal_indexed_load_1691, 2, vm); + setArg(call_illegal_indexed_load_1691, 3, 5); + setArg(call_illegal_indexed_load_1691, 4, EEW); + setArg(call_illegal_indexed_load_1691, 5, illegal_indexed_load_1691_arg4); + setArg(call_illegal_indexed_load_1691, 6, illegal_indexed_load_1691_arg5); + setRet(call_illegal_indexed_load_1691, 0, ret_val_illegal_indexed_load_1691); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1694; + x86::Gp ret_val_sew_1694 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1694, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1693; + auto vlxseg_1693_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1693_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1693_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1693_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1693_arg10 = ret_val_sew_1694; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1693 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1693, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1693, 32, false), traits::vstart); + setArg(call_sew_1694, 0, reinterpret_cast(this)); + setRet(call_sew_1694, 0, ret_val_sew_1694); + setArg(call_vlxseg_1693, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1693, 1, V); + setArg(call_vlxseg_1693, 2, vlxseg_1693_arg1); + setArg(call_vlxseg_1693, 3, vlxseg_1693_arg2); + setArg(call_vlxseg_1693, 4, vlxseg_1693_arg3); + setArg(call_vlxseg_1693, 5, vm); + setArg(call_vlxseg_1693, 6, vd); + setArg(call_vlxseg_1693, 7, vlxseg_1693_arg6); + setArg(call_vlxseg_1693, 8, vs2); + setArg(call_vlxseg_1693, 9, 5); + setArg(call_vlxseg_1693, 10, 2); + setArg(call_vlxseg_1693, 11, vlxseg_1693_arg10); + setArg(call_vlxseg_1693, 12, 0); + setRet(call_vlxseg_1693, 0, ret_val_vlxseg_1693); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 426); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 427: VLUXSEG5EI32__V */ + continuation_e __vluxseg5ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG5EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 427); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1695; + x86::Gp ret_val_get_pow_1695 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1695, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1696; + x86::Gp ret_val_get_sew_pow_1696 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1696, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1697; + x86::Gp ret_val_get_lmul_pow_1697 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1697, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1695, ret_val_get_sew_pow_1696), ret_val_get_lmul_pow_1697)), 3, true); + setArg(call_get_pow_1695, 0, reinterpret_cast(this)); + setArg(call_get_pow_1695, 1, EEW); + setRet(call_get_pow_1695, 0, ret_val_get_pow_1695); + setArg(call_get_sew_pow_1696, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1696, 0, ret_val_get_sew_pow_1696); + setArg(call_get_lmul_pow_1697, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1697, 0, ret_val_get_lmul_pow_1697); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1699; + x86::Gp ret_val_get_lmul_pow_1699 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1699, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1698; + auto illegal_indexed_load_1698_arg4 = EMUL_pow; + auto illegal_indexed_load_1698_arg5 = ret_val_get_lmul_pow_1699; + x86::Gp ret_val_illegal_indexed_load_1698 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1698, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1698; + setArg(call_get_lmul_pow_1699, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1699, 0, ret_val_get_lmul_pow_1699); + setArg(call_illegal_indexed_load_1698, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1698, 1, vd); + setArg(call_illegal_indexed_load_1698, 2, vm); + setArg(call_illegal_indexed_load_1698, 3, 5); + setArg(call_illegal_indexed_load_1698, 4, EEW); + setArg(call_illegal_indexed_load_1698, 5, illegal_indexed_load_1698_arg4); + setArg(call_illegal_indexed_load_1698, 6, illegal_indexed_load_1698_arg5); + setRet(call_illegal_indexed_load_1698, 0, ret_val_illegal_indexed_load_1698); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1701; + x86::Gp ret_val_sew_1701 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1701, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1700; + auto vlxseg_1700_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1700_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1700_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1700_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1700_arg10 = ret_val_sew_1701; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1700 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1700, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1700, 32, false), traits::vstart); + setArg(call_sew_1701, 0, reinterpret_cast(this)); + setRet(call_sew_1701, 0, ret_val_sew_1701); + setArg(call_vlxseg_1700, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1700, 1, V); + setArg(call_vlxseg_1700, 2, vlxseg_1700_arg1); + setArg(call_vlxseg_1700, 3, vlxseg_1700_arg2); + setArg(call_vlxseg_1700, 4, vlxseg_1700_arg3); + setArg(call_vlxseg_1700, 5, vm); + setArg(call_vlxseg_1700, 6, vd); + setArg(call_vlxseg_1700, 7, vlxseg_1700_arg6); + setArg(call_vlxseg_1700, 8, vs2); + setArg(call_vlxseg_1700, 9, 5); + setArg(call_vlxseg_1700, 10, 4); + setArg(call_vlxseg_1700, 11, vlxseg_1700_arg10); + setArg(call_vlxseg_1700, 12, 0); + setRet(call_vlxseg_1700, 0, ret_val_vlxseg_1700); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 427); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 428: VLUXSEG5EI64__V */ + continuation_e __vluxseg5ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG5EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 428); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1702; + x86::Gp ret_val_get_pow_1702 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1702, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1703; + x86::Gp ret_val_get_sew_pow_1703 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1703, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1704; + x86::Gp ret_val_get_lmul_pow_1704 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1704, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1702, ret_val_get_sew_pow_1703), ret_val_get_lmul_pow_1704)), 3, true); + setArg(call_get_pow_1702, 0, reinterpret_cast(this)); + setArg(call_get_pow_1702, 1, EEW); + setRet(call_get_pow_1702, 0, ret_val_get_pow_1702); + setArg(call_get_sew_pow_1703, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1703, 0, ret_val_get_sew_pow_1703); + setArg(call_get_lmul_pow_1704, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1704, 0, ret_val_get_lmul_pow_1704); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1706; + x86::Gp ret_val_get_lmul_pow_1706 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1706, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1705; + auto illegal_indexed_load_1705_arg4 = EMUL_pow; + auto illegal_indexed_load_1705_arg5 = ret_val_get_lmul_pow_1706; + x86::Gp ret_val_illegal_indexed_load_1705 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1705, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1705; + setArg(call_get_lmul_pow_1706, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1706, 0, ret_val_get_lmul_pow_1706); + setArg(call_illegal_indexed_load_1705, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1705, 1, vd); + setArg(call_illegal_indexed_load_1705, 2, vm); + setArg(call_illegal_indexed_load_1705, 3, 5); + setArg(call_illegal_indexed_load_1705, 4, EEW); + setArg(call_illegal_indexed_load_1705, 5, illegal_indexed_load_1705_arg4); + setArg(call_illegal_indexed_load_1705, 6, illegal_indexed_load_1705_arg5); + setRet(call_illegal_indexed_load_1705, 0, ret_val_illegal_indexed_load_1705); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1708; + x86::Gp ret_val_sew_1708 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1708, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1707; + auto vlxseg_1707_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1707_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1707_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1707_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1707_arg10 = ret_val_sew_1708; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1707 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1707, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1707, 32, false), traits::vstart); + setArg(call_sew_1708, 0, reinterpret_cast(this)); + setRet(call_sew_1708, 0, ret_val_sew_1708); + setArg(call_vlxseg_1707, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1707, 1, V); + setArg(call_vlxseg_1707, 2, vlxseg_1707_arg1); + setArg(call_vlxseg_1707, 3, vlxseg_1707_arg2); + setArg(call_vlxseg_1707, 4, vlxseg_1707_arg3); + setArg(call_vlxseg_1707, 5, vm); + setArg(call_vlxseg_1707, 6, vd); + setArg(call_vlxseg_1707, 7, vlxseg_1707_arg6); + setArg(call_vlxseg_1707, 8, vs2); + setArg(call_vlxseg_1707, 9, 5); + setArg(call_vlxseg_1707, 10, 8); + setArg(call_vlxseg_1707, 11, vlxseg_1707_arg10); + setArg(call_vlxseg_1707, 12, 0); + setRet(call_vlxseg_1707, 0, ret_val_vlxseg_1707); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 428); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 429: VLUXSEG6EI8__V */ + continuation_e __vluxseg6ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG6EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 429); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1709; + x86::Gp ret_val_get_pow_1709 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1709, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1710; + x86::Gp ret_val_get_sew_pow_1710 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1710, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1711; + x86::Gp ret_val_get_lmul_pow_1711 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1711, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1709, ret_val_get_sew_pow_1710), ret_val_get_lmul_pow_1711)), 3, true); + setArg(call_get_pow_1709, 0, reinterpret_cast(this)); + setArg(call_get_pow_1709, 1, EEW); + setRet(call_get_pow_1709, 0, ret_val_get_pow_1709); + setArg(call_get_sew_pow_1710, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1710, 0, ret_val_get_sew_pow_1710); + setArg(call_get_lmul_pow_1711, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1711, 0, ret_val_get_lmul_pow_1711); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1713; + x86::Gp ret_val_get_lmul_pow_1713 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1713, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1712; + auto illegal_indexed_load_1712_arg4 = EMUL_pow; + auto illegal_indexed_load_1712_arg5 = ret_val_get_lmul_pow_1713; + x86::Gp ret_val_illegal_indexed_load_1712 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1712, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1712; + setArg(call_get_lmul_pow_1713, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1713, 0, ret_val_get_lmul_pow_1713); + setArg(call_illegal_indexed_load_1712, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1712, 1, vd); + setArg(call_illegal_indexed_load_1712, 2, vm); + setArg(call_illegal_indexed_load_1712, 3, 6); + setArg(call_illegal_indexed_load_1712, 4, EEW); + setArg(call_illegal_indexed_load_1712, 5, illegal_indexed_load_1712_arg4); + setArg(call_illegal_indexed_load_1712, 6, illegal_indexed_load_1712_arg5); + setRet(call_illegal_indexed_load_1712, 0, ret_val_illegal_indexed_load_1712); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1715; + x86::Gp ret_val_sew_1715 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1715, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1714; + auto vlxseg_1714_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1714_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1714_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1714_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1714_arg10 = ret_val_sew_1715; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1714 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1714, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1714, 32, false), traits::vstart); + setArg(call_sew_1715, 0, reinterpret_cast(this)); + setRet(call_sew_1715, 0, ret_val_sew_1715); + setArg(call_vlxseg_1714, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1714, 1, V); + setArg(call_vlxseg_1714, 2, vlxseg_1714_arg1); + setArg(call_vlxseg_1714, 3, vlxseg_1714_arg2); + setArg(call_vlxseg_1714, 4, vlxseg_1714_arg3); + setArg(call_vlxseg_1714, 5, vm); + setArg(call_vlxseg_1714, 6, vd); + setArg(call_vlxseg_1714, 7, vlxseg_1714_arg6); + setArg(call_vlxseg_1714, 8, vs2); + setArg(call_vlxseg_1714, 9, 6); + setArg(call_vlxseg_1714, 10, 1); + setArg(call_vlxseg_1714, 11, vlxseg_1714_arg10); + setArg(call_vlxseg_1714, 12, 0); + setRet(call_vlxseg_1714, 0, ret_val_vlxseg_1714); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 429); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 430: VLUXSEG6EI16__V */ + continuation_e __vluxseg6ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG6EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 430); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1716; + x86::Gp ret_val_get_pow_1716 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1716, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1717; + x86::Gp ret_val_get_sew_pow_1717 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1717, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1718; + x86::Gp ret_val_get_lmul_pow_1718 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1718, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1716, ret_val_get_sew_pow_1717), ret_val_get_lmul_pow_1718)), 3, true); + setArg(call_get_pow_1716, 0, reinterpret_cast(this)); + setArg(call_get_pow_1716, 1, EEW); + setRet(call_get_pow_1716, 0, ret_val_get_pow_1716); + setArg(call_get_sew_pow_1717, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1717, 0, ret_val_get_sew_pow_1717); + setArg(call_get_lmul_pow_1718, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1718, 0, ret_val_get_lmul_pow_1718); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1720; + x86::Gp ret_val_get_lmul_pow_1720 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1720, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1719; + auto illegal_indexed_load_1719_arg4 = EMUL_pow; + auto illegal_indexed_load_1719_arg5 = ret_val_get_lmul_pow_1720; + x86::Gp ret_val_illegal_indexed_load_1719 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1719, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1719; + setArg(call_get_lmul_pow_1720, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1720, 0, ret_val_get_lmul_pow_1720); + setArg(call_illegal_indexed_load_1719, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1719, 1, vd); + setArg(call_illegal_indexed_load_1719, 2, vm); + setArg(call_illegal_indexed_load_1719, 3, 6); + setArg(call_illegal_indexed_load_1719, 4, EEW); + setArg(call_illegal_indexed_load_1719, 5, illegal_indexed_load_1719_arg4); + setArg(call_illegal_indexed_load_1719, 6, illegal_indexed_load_1719_arg5); + setRet(call_illegal_indexed_load_1719, 0, ret_val_illegal_indexed_load_1719); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1722; + x86::Gp ret_val_sew_1722 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1722, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1721; + auto vlxseg_1721_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1721_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1721_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1721_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1721_arg10 = ret_val_sew_1722; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1721 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1721, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1721, 32, false), traits::vstart); + setArg(call_sew_1722, 0, reinterpret_cast(this)); + setRet(call_sew_1722, 0, ret_val_sew_1722); + setArg(call_vlxseg_1721, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1721, 1, V); + setArg(call_vlxseg_1721, 2, vlxseg_1721_arg1); + setArg(call_vlxseg_1721, 3, vlxseg_1721_arg2); + setArg(call_vlxseg_1721, 4, vlxseg_1721_arg3); + setArg(call_vlxseg_1721, 5, vm); + setArg(call_vlxseg_1721, 6, vd); + setArg(call_vlxseg_1721, 7, vlxseg_1721_arg6); + setArg(call_vlxseg_1721, 8, vs2); + setArg(call_vlxseg_1721, 9, 6); + setArg(call_vlxseg_1721, 10, 2); + setArg(call_vlxseg_1721, 11, vlxseg_1721_arg10); + setArg(call_vlxseg_1721, 12, 0); + setRet(call_vlxseg_1721, 0, ret_val_vlxseg_1721); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 430); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 431: VLUXSEG6EI32__V */ + continuation_e __vluxseg6ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG6EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 431); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1723; + x86::Gp ret_val_get_pow_1723 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1723, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1724; + x86::Gp ret_val_get_sew_pow_1724 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1724, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1725; + x86::Gp ret_val_get_lmul_pow_1725 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1725, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1723, ret_val_get_sew_pow_1724), ret_val_get_lmul_pow_1725)), 3, true); + setArg(call_get_pow_1723, 0, reinterpret_cast(this)); + setArg(call_get_pow_1723, 1, EEW); + setRet(call_get_pow_1723, 0, ret_val_get_pow_1723); + setArg(call_get_sew_pow_1724, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1724, 0, ret_val_get_sew_pow_1724); + setArg(call_get_lmul_pow_1725, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1725, 0, ret_val_get_lmul_pow_1725); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1727; + x86::Gp ret_val_get_lmul_pow_1727 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1727, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1726; + auto illegal_indexed_load_1726_arg4 = EMUL_pow; + auto illegal_indexed_load_1726_arg5 = ret_val_get_lmul_pow_1727; + x86::Gp ret_val_illegal_indexed_load_1726 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1726, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1726; + setArg(call_get_lmul_pow_1727, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1727, 0, ret_val_get_lmul_pow_1727); + setArg(call_illegal_indexed_load_1726, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1726, 1, vd); + setArg(call_illegal_indexed_load_1726, 2, vm); + setArg(call_illegal_indexed_load_1726, 3, 6); + setArg(call_illegal_indexed_load_1726, 4, EEW); + setArg(call_illegal_indexed_load_1726, 5, illegal_indexed_load_1726_arg4); + setArg(call_illegal_indexed_load_1726, 6, illegal_indexed_load_1726_arg5); + setRet(call_illegal_indexed_load_1726, 0, ret_val_illegal_indexed_load_1726); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1729; + x86::Gp ret_val_sew_1729 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1729, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1728; + auto vlxseg_1728_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1728_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1728_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1728_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1728_arg10 = ret_val_sew_1729; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1728 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1728, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1728, 32, false), traits::vstart); + setArg(call_sew_1729, 0, reinterpret_cast(this)); + setRet(call_sew_1729, 0, ret_val_sew_1729); + setArg(call_vlxseg_1728, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1728, 1, V); + setArg(call_vlxseg_1728, 2, vlxseg_1728_arg1); + setArg(call_vlxseg_1728, 3, vlxseg_1728_arg2); + setArg(call_vlxseg_1728, 4, vlxseg_1728_arg3); + setArg(call_vlxseg_1728, 5, vm); + setArg(call_vlxseg_1728, 6, vd); + setArg(call_vlxseg_1728, 7, vlxseg_1728_arg6); + setArg(call_vlxseg_1728, 8, vs2); + setArg(call_vlxseg_1728, 9, 6); + setArg(call_vlxseg_1728, 10, 4); + setArg(call_vlxseg_1728, 11, vlxseg_1728_arg10); + setArg(call_vlxseg_1728, 12, 0); + setRet(call_vlxseg_1728, 0, ret_val_vlxseg_1728); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 431); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 432: VLUXSEG6EI64__V */ + continuation_e __vluxseg6ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG6EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 432); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1730; + x86::Gp ret_val_get_pow_1730 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1730, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1731; + x86::Gp ret_val_get_sew_pow_1731 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1731, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1732; + x86::Gp ret_val_get_lmul_pow_1732 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1732, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1730, ret_val_get_sew_pow_1731), ret_val_get_lmul_pow_1732)), 3, true); + setArg(call_get_pow_1730, 0, reinterpret_cast(this)); + setArg(call_get_pow_1730, 1, EEW); + setRet(call_get_pow_1730, 0, ret_val_get_pow_1730); + setArg(call_get_sew_pow_1731, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1731, 0, ret_val_get_sew_pow_1731); + setArg(call_get_lmul_pow_1732, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1732, 0, ret_val_get_lmul_pow_1732); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1734; + x86::Gp ret_val_get_lmul_pow_1734 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1734, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1733; + auto illegal_indexed_load_1733_arg4 = EMUL_pow; + auto illegal_indexed_load_1733_arg5 = ret_val_get_lmul_pow_1734; + x86::Gp ret_val_illegal_indexed_load_1733 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1733, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1733; + setArg(call_get_lmul_pow_1734, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1734, 0, ret_val_get_lmul_pow_1734); + setArg(call_illegal_indexed_load_1733, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1733, 1, vd); + setArg(call_illegal_indexed_load_1733, 2, vm); + setArg(call_illegal_indexed_load_1733, 3, 6); + setArg(call_illegal_indexed_load_1733, 4, EEW); + setArg(call_illegal_indexed_load_1733, 5, illegal_indexed_load_1733_arg4); + setArg(call_illegal_indexed_load_1733, 6, illegal_indexed_load_1733_arg5); + setRet(call_illegal_indexed_load_1733, 0, ret_val_illegal_indexed_load_1733); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1736; + x86::Gp ret_val_sew_1736 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1736, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1735; + auto vlxseg_1735_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1735_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1735_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1735_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1735_arg10 = ret_val_sew_1736; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1735 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1735, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1735, 32, false), traits::vstart); + setArg(call_sew_1736, 0, reinterpret_cast(this)); + setRet(call_sew_1736, 0, ret_val_sew_1736); + setArg(call_vlxseg_1735, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1735, 1, V); + setArg(call_vlxseg_1735, 2, vlxseg_1735_arg1); + setArg(call_vlxseg_1735, 3, vlxseg_1735_arg2); + setArg(call_vlxseg_1735, 4, vlxseg_1735_arg3); + setArg(call_vlxseg_1735, 5, vm); + setArg(call_vlxseg_1735, 6, vd); + setArg(call_vlxseg_1735, 7, vlxseg_1735_arg6); + setArg(call_vlxseg_1735, 8, vs2); + setArg(call_vlxseg_1735, 9, 6); + setArg(call_vlxseg_1735, 10, 8); + setArg(call_vlxseg_1735, 11, vlxseg_1735_arg10); + setArg(call_vlxseg_1735, 12, 0); + setRet(call_vlxseg_1735, 0, ret_val_vlxseg_1735); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 432); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 433: VLUXSEG7EI8__V */ + continuation_e __vluxseg7ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG7EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 433); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1737; + x86::Gp ret_val_get_pow_1737 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1737, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1738; + x86::Gp ret_val_get_sew_pow_1738 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1738, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1739; + x86::Gp ret_val_get_lmul_pow_1739 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1739, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1737, ret_val_get_sew_pow_1738), ret_val_get_lmul_pow_1739)), 3, true); + setArg(call_get_pow_1737, 0, reinterpret_cast(this)); + setArg(call_get_pow_1737, 1, EEW); + setRet(call_get_pow_1737, 0, ret_val_get_pow_1737); + setArg(call_get_sew_pow_1738, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1738, 0, ret_val_get_sew_pow_1738); + setArg(call_get_lmul_pow_1739, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1739, 0, ret_val_get_lmul_pow_1739); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1741; + x86::Gp ret_val_get_lmul_pow_1741 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1741, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1740; + auto illegal_indexed_load_1740_arg4 = EMUL_pow; + auto illegal_indexed_load_1740_arg5 = ret_val_get_lmul_pow_1741; + x86::Gp ret_val_illegal_indexed_load_1740 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1740, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1740; + setArg(call_get_lmul_pow_1741, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1741, 0, ret_val_get_lmul_pow_1741); + setArg(call_illegal_indexed_load_1740, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1740, 1, vd); + setArg(call_illegal_indexed_load_1740, 2, vm); + setArg(call_illegal_indexed_load_1740, 3, 7); + setArg(call_illegal_indexed_load_1740, 4, EEW); + setArg(call_illegal_indexed_load_1740, 5, illegal_indexed_load_1740_arg4); + setArg(call_illegal_indexed_load_1740, 6, illegal_indexed_load_1740_arg5); + setRet(call_illegal_indexed_load_1740, 0, ret_val_illegal_indexed_load_1740); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1743; + x86::Gp ret_val_sew_1743 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1743, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1742; + auto vlxseg_1742_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1742_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1742_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1742_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1742_arg10 = ret_val_sew_1743; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1742 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1742, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1742, 32, false), traits::vstart); + setArg(call_sew_1743, 0, reinterpret_cast(this)); + setRet(call_sew_1743, 0, ret_val_sew_1743); + setArg(call_vlxseg_1742, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1742, 1, V); + setArg(call_vlxseg_1742, 2, vlxseg_1742_arg1); + setArg(call_vlxseg_1742, 3, vlxseg_1742_arg2); + setArg(call_vlxseg_1742, 4, vlxseg_1742_arg3); + setArg(call_vlxseg_1742, 5, vm); + setArg(call_vlxseg_1742, 6, vd); + setArg(call_vlxseg_1742, 7, vlxseg_1742_arg6); + setArg(call_vlxseg_1742, 8, vs2); + setArg(call_vlxseg_1742, 9, 7); + setArg(call_vlxseg_1742, 10, 1); + setArg(call_vlxseg_1742, 11, vlxseg_1742_arg10); + setArg(call_vlxseg_1742, 12, 0); + setRet(call_vlxseg_1742, 0, ret_val_vlxseg_1742); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 433); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 434: VLUXSEG7EI16__V */ + continuation_e __vluxseg7ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG7EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 434); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1744; + x86::Gp ret_val_get_pow_1744 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1744, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1745; + x86::Gp ret_val_get_sew_pow_1745 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1745, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1746; + x86::Gp ret_val_get_lmul_pow_1746 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1746, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1744, ret_val_get_sew_pow_1745), ret_val_get_lmul_pow_1746)), 3, true); + setArg(call_get_pow_1744, 0, reinterpret_cast(this)); + setArg(call_get_pow_1744, 1, EEW); + setRet(call_get_pow_1744, 0, ret_val_get_pow_1744); + setArg(call_get_sew_pow_1745, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1745, 0, ret_val_get_sew_pow_1745); + setArg(call_get_lmul_pow_1746, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1746, 0, ret_val_get_lmul_pow_1746); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1748; + x86::Gp ret_val_get_lmul_pow_1748 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1748, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1747; + auto illegal_indexed_load_1747_arg4 = EMUL_pow; + auto illegal_indexed_load_1747_arg5 = ret_val_get_lmul_pow_1748; + x86::Gp ret_val_illegal_indexed_load_1747 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1747, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1747; + setArg(call_get_lmul_pow_1748, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1748, 0, ret_val_get_lmul_pow_1748); + setArg(call_illegal_indexed_load_1747, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1747, 1, vd); + setArg(call_illegal_indexed_load_1747, 2, vm); + setArg(call_illegal_indexed_load_1747, 3, 7); + setArg(call_illegal_indexed_load_1747, 4, EEW); + setArg(call_illegal_indexed_load_1747, 5, illegal_indexed_load_1747_arg4); + setArg(call_illegal_indexed_load_1747, 6, illegal_indexed_load_1747_arg5); + setRet(call_illegal_indexed_load_1747, 0, ret_val_illegal_indexed_load_1747); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1750; + x86::Gp ret_val_sew_1750 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1750, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1749; + auto vlxseg_1749_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1749_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1749_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1749_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1749_arg10 = ret_val_sew_1750; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1749 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1749, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1749, 32, false), traits::vstart); + setArg(call_sew_1750, 0, reinterpret_cast(this)); + setRet(call_sew_1750, 0, ret_val_sew_1750); + setArg(call_vlxseg_1749, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1749, 1, V); + setArg(call_vlxseg_1749, 2, vlxseg_1749_arg1); + setArg(call_vlxseg_1749, 3, vlxseg_1749_arg2); + setArg(call_vlxseg_1749, 4, vlxseg_1749_arg3); + setArg(call_vlxseg_1749, 5, vm); + setArg(call_vlxseg_1749, 6, vd); + setArg(call_vlxseg_1749, 7, vlxseg_1749_arg6); + setArg(call_vlxseg_1749, 8, vs2); + setArg(call_vlxseg_1749, 9, 7); + setArg(call_vlxseg_1749, 10, 2); + setArg(call_vlxseg_1749, 11, vlxseg_1749_arg10); + setArg(call_vlxseg_1749, 12, 0); + setRet(call_vlxseg_1749, 0, ret_val_vlxseg_1749); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 434); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 435: VLUXSEG7EI32__V */ + continuation_e __vluxseg7ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG7EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 435); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1751; + x86::Gp ret_val_get_pow_1751 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1751, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1752; + x86::Gp ret_val_get_sew_pow_1752 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1752, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1753; + x86::Gp ret_val_get_lmul_pow_1753 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1753, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1751, ret_val_get_sew_pow_1752), ret_val_get_lmul_pow_1753)), 3, true); + setArg(call_get_pow_1751, 0, reinterpret_cast(this)); + setArg(call_get_pow_1751, 1, EEW); + setRet(call_get_pow_1751, 0, ret_val_get_pow_1751); + setArg(call_get_sew_pow_1752, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1752, 0, ret_val_get_sew_pow_1752); + setArg(call_get_lmul_pow_1753, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1753, 0, ret_val_get_lmul_pow_1753); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1755; + x86::Gp ret_val_get_lmul_pow_1755 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1755, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1754; + auto illegal_indexed_load_1754_arg4 = EMUL_pow; + auto illegal_indexed_load_1754_arg5 = ret_val_get_lmul_pow_1755; + x86::Gp ret_val_illegal_indexed_load_1754 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1754, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1754; + setArg(call_get_lmul_pow_1755, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1755, 0, ret_val_get_lmul_pow_1755); + setArg(call_illegal_indexed_load_1754, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1754, 1, vd); + setArg(call_illegal_indexed_load_1754, 2, vm); + setArg(call_illegal_indexed_load_1754, 3, 7); + setArg(call_illegal_indexed_load_1754, 4, EEW); + setArg(call_illegal_indexed_load_1754, 5, illegal_indexed_load_1754_arg4); + setArg(call_illegal_indexed_load_1754, 6, illegal_indexed_load_1754_arg5); + setRet(call_illegal_indexed_load_1754, 0, ret_val_illegal_indexed_load_1754); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1757; + x86::Gp ret_val_sew_1757 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1757, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1756; + auto vlxseg_1756_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1756_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1756_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1756_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1756_arg10 = ret_val_sew_1757; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1756 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1756, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1756, 32, false), traits::vstart); + setArg(call_sew_1757, 0, reinterpret_cast(this)); + setRet(call_sew_1757, 0, ret_val_sew_1757); + setArg(call_vlxseg_1756, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1756, 1, V); + setArg(call_vlxseg_1756, 2, vlxseg_1756_arg1); + setArg(call_vlxseg_1756, 3, vlxseg_1756_arg2); + setArg(call_vlxseg_1756, 4, vlxseg_1756_arg3); + setArg(call_vlxseg_1756, 5, vm); + setArg(call_vlxseg_1756, 6, vd); + setArg(call_vlxseg_1756, 7, vlxseg_1756_arg6); + setArg(call_vlxseg_1756, 8, vs2); + setArg(call_vlxseg_1756, 9, 7); + setArg(call_vlxseg_1756, 10, 4); + setArg(call_vlxseg_1756, 11, vlxseg_1756_arg10); + setArg(call_vlxseg_1756, 12, 0); + setRet(call_vlxseg_1756, 0, ret_val_vlxseg_1756); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 435); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 436: VLUXSEG7EI64__V */ + continuation_e __vluxseg7ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG7EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 436); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1758; + x86::Gp ret_val_get_pow_1758 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1758, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1759; + x86::Gp ret_val_get_sew_pow_1759 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1759, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1760; + x86::Gp ret_val_get_lmul_pow_1760 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1760, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1758, ret_val_get_sew_pow_1759), ret_val_get_lmul_pow_1760)), 3, true); + setArg(call_get_pow_1758, 0, reinterpret_cast(this)); + setArg(call_get_pow_1758, 1, EEW); + setRet(call_get_pow_1758, 0, ret_val_get_pow_1758); + setArg(call_get_sew_pow_1759, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1759, 0, ret_val_get_sew_pow_1759); + setArg(call_get_lmul_pow_1760, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1760, 0, ret_val_get_lmul_pow_1760); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1762; + x86::Gp ret_val_get_lmul_pow_1762 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1762, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1761; + auto illegal_indexed_load_1761_arg4 = EMUL_pow; + auto illegal_indexed_load_1761_arg5 = ret_val_get_lmul_pow_1762; + x86::Gp ret_val_illegal_indexed_load_1761 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1761, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1761; + setArg(call_get_lmul_pow_1762, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1762, 0, ret_val_get_lmul_pow_1762); + setArg(call_illegal_indexed_load_1761, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1761, 1, vd); + setArg(call_illegal_indexed_load_1761, 2, vm); + setArg(call_illegal_indexed_load_1761, 3, 7); + setArg(call_illegal_indexed_load_1761, 4, EEW); + setArg(call_illegal_indexed_load_1761, 5, illegal_indexed_load_1761_arg4); + setArg(call_illegal_indexed_load_1761, 6, illegal_indexed_load_1761_arg5); + setRet(call_illegal_indexed_load_1761, 0, ret_val_illegal_indexed_load_1761); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1764; + x86::Gp ret_val_sew_1764 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1764, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1763; + auto vlxseg_1763_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1763_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1763_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1763_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1763_arg10 = ret_val_sew_1764; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1763 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1763, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1763, 32, false), traits::vstart); + setArg(call_sew_1764, 0, reinterpret_cast(this)); + setRet(call_sew_1764, 0, ret_val_sew_1764); + setArg(call_vlxseg_1763, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1763, 1, V); + setArg(call_vlxseg_1763, 2, vlxseg_1763_arg1); + setArg(call_vlxseg_1763, 3, vlxseg_1763_arg2); + setArg(call_vlxseg_1763, 4, vlxseg_1763_arg3); + setArg(call_vlxseg_1763, 5, vm); + setArg(call_vlxseg_1763, 6, vd); + setArg(call_vlxseg_1763, 7, vlxseg_1763_arg6); + setArg(call_vlxseg_1763, 8, vs2); + setArg(call_vlxseg_1763, 9, 7); + setArg(call_vlxseg_1763, 10, 8); + setArg(call_vlxseg_1763, 11, vlxseg_1763_arg10); + setArg(call_vlxseg_1763, 12, 0); + setRet(call_vlxseg_1763, 0, ret_val_vlxseg_1763); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 436); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 437: VLUXSEG8EI8__V */ + continuation_e __vluxseg8ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG8EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 437); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1765; + x86::Gp ret_val_get_pow_1765 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1765, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1766; + x86::Gp ret_val_get_sew_pow_1766 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1766, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1767; + x86::Gp ret_val_get_lmul_pow_1767 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1767, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1765, ret_val_get_sew_pow_1766), ret_val_get_lmul_pow_1767)), 3, true); + setArg(call_get_pow_1765, 0, reinterpret_cast(this)); + setArg(call_get_pow_1765, 1, EEW); + setRet(call_get_pow_1765, 0, ret_val_get_pow_1765); + setArg(call_get_sew_pow_1766, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1766, 0, ret_val_get_sew_pow_1766); + setArg(call_get_lmul_pow_1767, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1767, 0, ret_val_get_lmul_pow_1767); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1769; + x86::Gp ret_val_get_lmul_pow_1769 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1769, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1768; + auto illegal_indexed_load_1768_arg4 = EMUL_pow; + auto illegal_indexed_load_1768_arg5 = ret_val_get_lmul_pow_1769; + x86::Gp ret_val_illegal_indexed_load_1768 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1768, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1768; + setArg(call_get_lmul_pow_1769, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1769, 0, ret_val_get_lmul_pow_1769); + setArg(call_illegal_indexed_load_1768, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1768, 1, vd); + setArg(call_illegal_indexed_load_1768, 2, vm); + setArg(call_illegal_indexed_load_1768, 3, 8); + setArg(call_illegal_indexed_load_1768, 4, EEW); + setArg(call_illegal_indexed_load_1768, 5, illegal_indexed_load_1768_arg4); + setArg(call_illegal_indexed_load_1768, 6, illegal_indexed_load_1768_arg5); + setRet(call_illegal_indexed_load_1768, 0, ret_val_illegal_indexed_load_1768); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1771; + x86::Gp ret_val_sew_1771 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1771, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1770; + auto vlxseg_1770_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1770_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1770_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1770_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1770_arg10 = ret_val_sew_1771; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1770 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1770, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1770, 32, false), traits::vstart); + setArg(call_sew_1771, 0, reinterpret_cast(this)); + setRet(call_sew_1771, 0, ret_val_sew_1771); + setArg(call_vlxseg_1770, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1770, 1, V); + setArg(call_vlxseg_1770, 2, vlxseg_1770_arg1); + setArg(call_vlxseg_1770, 3, vlxseg_1770_arg2); + setArg(call_vlxseg_1770, 4, vlxseg_1770_arg3); + setArg(call_vlxseg_1770, 5, vm); + setArg(call_vlxseg_1770, 6, vd); + setArg(call_vlxseg_1770, 7, vlxseg_1770_arg6); + setArg(call_vlxseg_1770, 8, vs2); + setArg(call_vlxseg_1770, 9, 8); + setArg(call_vlxseg_1770, 10, 1); + setArg(call_vlxseg_1770, 11, vlxseg_1770_arg10); + setArg(call_vlxseg_1770, 12, 0); + setRet(call_vlxseg_1770, 0, ret_val_vlxseg_1770); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 437); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 438: VLUXSEG8EI16__V */ + continuation_e __vluxseg8ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG8EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 438); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1772; + x86::Gp ret_val_get_pow_1772 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1772, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1773; + x86::Gp ret_val_get_sew_pow_1773 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1773, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1774; + x86::Gp ret_val_get_lmul_pow_1774 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1774, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1772, ret_val_get_sew_pow_1773), ret_val_get_lmul_pow_1774)), 3, true); + setArg(call_get_pow_1772, 0, reinterpret_cast(this)); + setArg(call_get_pow_1772, 1, EEW); + setRet(call_get_pow_1772, 0, ret_val_get_pow_1772); + setArg(call_get_sew_pow_1773, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1773, 0, ret_val_get_sew_pow_1773); + setArg(call_get_lmul_pow_1774, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1774, 0, ret_val_get_lmul_pow_1774); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1776; + x86::Gp ret_val_get_lmul_pow_1776 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1776, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1775; + auto illegal_indexed_load_1775_arg4 = EMUL_pow; + auto illegal_indexed_load_1775_arg5 = ret_val_get_lmul_pow_1776; + x86::Gp ret_val_illegal_indexed_load_1775 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1775, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1775; + setArg(call_get_lmul_pow_1776, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1776, 0, ret_val_get_lmul_pow_1776); + setArg(call_illegal_indexed_load_1775, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1775, 1, vd); + setArg(call_illegal_indexed_load_1775, 2, vm); + setArg(call_illegal_indexed_load_1775, 3, 8); + setArg(call_illegal_indexed_load_1775, 4, EEW); + setArg(call_illegal_indexed_load_1775, 5, illegal_indexed_load_1775_arg4); + setArg(call_illegal_indexed_load_1775, 6, illegal_indexed_load_1775_arg5); + setRet(call_illegal_indexed_load_1775, 0, ret_val_illegal_indexed_load_1775); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1778; + x86::Gp ret_val_sew_1778 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1778, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1777; + auto vlxseg_1777_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1777_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1777_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1777_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1777_arg10 = ret_val_sew_1778; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1777 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1777, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1777, 32, false), traits::vstart); + setArg(call_sew_1778, 0, reinterpret_cast(this)); + setRet(call_sew_1778, 0, ret_val_sew_1778); + setArg(call_vlxseg_1777, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1777, 1, V); + setArg(call_vlxseg_1777, 2, vlxseg_1777_arg1); + setArg(call_vlxseg_1777, 3, vlxseg_1777_arg2); + setArg(call_vlxseg_1777, 4, vlxseg_1777_arg3); + setArg(call_vlxseg_1777, 5, vm); + setArg(call_vlxseg_1777, 6, vd); + setArg(call_vlxseg_1777, 7, vlxseg_1777_arg6); + setArg(call_vlxseg_1777, 8, vs2); + setArg(call_vlxseg_1777, 9, 8); + setArg(call_vlxseg_1777, 10, 2); + setArg(call_vlxseg_1777, 11, vlxseg_1777_arg10); + setArg(call_vlxseg_1777, 12, 0); + setRet(call_vlxseg_1777, 0, ret_val_vlxseg_1777); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 438); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 439: VLUXSEG8EI32__V */ + continuation_e __vluxseg8ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG8EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 439); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1779; + x86::Gp ret_val_get_pow_1779 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1779, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1780; + x86::Gp ret_val_get_sew_pow_1780 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1780, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1781; + x86::Gp ret_val_get_lmul_pow_1781 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1781, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1779, ret_val_get_sew_pow_1780), ret_val_get_lmul_pow_1781)), 3, true); + setArg(call_get_pow_1779, 0, reinterpret_cast(this)); + setArg(call_get_pow_1779, 1, EEW); + setRet(call_get_pow_1779, 0, ret_val_get_pow_1779); + setArg(call_get_sew_pow_1780, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1780, 0, ret_val_get_sew_pow_1780); + setArg(call_get_lmul_pow_1781, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1781, 0, ret_val_get_lmul_pow_1781); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1783; + x86::Gp ret_val_get_lmul_pow_1783 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1783, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1782; + auto illegal_indexed_load_1782_arg4 = EMUL_pow; + auto illegal_indexed_load_1782_arg5 = ret_val_get_lmul_pow_1783; + x86::Gp ret_val_illegal_indexed_load_1782 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1782, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1782; + setArg(call_get_lmul_pow_1783, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1783, 0, ret_val_get_lmul_pow_1783); + setArg(call_illegal_indexed_load_1782, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1782, 1, vd); + setArg(call_illegal_indexed_load_1782, 2, vm); + setArg(call_illegal_indexed_load_1782, 3, 8); + setArg(call_illegal_indexed_load_1782, 4, EEW); + setArg(call_illegal_indexed_load_1782, 5, illegal_indexed_load_1782_arg4); + setArg(call_illegal_indexed_load_1782, 6, illegal_indexed_load_1782_arg5); + setRet(call_illegal_indexed_load_1782, 0, ret_val_illegal_indexed_load_1782); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1785; + x86::Gp ret_val_sew_1785 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1785, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1784; + auto vlxseg_1784_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1784_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1784_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1784_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1784_arg10 = ret_val_sew_1785; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1784 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1784, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1784, 32, false), traits::vstart); + setArg(call_sew_1785, 0, reinterpret_cast(this)); + setRet(call_sew_1785, 0, ret_val_sew_1785); + setArg(call_vlxseg_1784, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1784, 1, V); + setArg(call_vlxseg_1784, 2, vlxseg_1784_arg1); + setArg(call_vlxseg_1784, 3, vlxseg_1784_arg2); + setArg(call_vlxseg_1784, 4, vlxseg_1784_arg3); + setArg(call_vlxseg_1784, 5, vm); + setArg(call_vlxseg_1784, 6, vd); + setArg(call_vlxseg_1784, 7, vlxseg_1784_arg6); + setArg(call_vlxseg_1784, 8, vs2); + setArg(call_vlxseg_1784, 9, 8); + setArg(call_vlxseg_1784, 10, 4); + setArg(call_vlxseg_1784, 11, vlxseg_1784_arg10); + setArg(call_vlxseg_1784, 12, 0); + setRet(call_vlxseg_1784, 0, ret_val_vlxseg_1784); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 439); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 440: VLUXSEG8EI64__V */ + continuation_e __vluxseg8ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG8EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 440); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1786; + x86::Gp ret_val_get_pow_1786 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1786, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1787; + x86::Gp ret_val_get_sew_pow_1787 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1787, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1788; + x86::Gp ret_val_get_lmul_pow_1788 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1788, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1786, ret_val_get_sew_pow_1787), ret_val_get_lmul_pow_1788)), 3, true); + setArg(call_get_pow_1786, 0, reinterpret_cast(this)); + setArg(call_get_pow_1786, 1, EEW); + setRet(call_get_pow_1786, 0, ret_val_get_pow_1786); + setArg(call_get_sew_pow_1787, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1787, 0, ret_val_get_sew_pow_1787); + setArg(call_get_lmul_pow_1788, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1788, 0, ret_val_get_lmul_pow_1788); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1790; + x86::Gp ret_val_get_lmul_pow_1790 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1790, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1789; + auto illegal_indexed_load_1789_arg4 = EMUL_pow; + auto illegal_indexed_load_1789_arg5 = ret_val_get_lmul_pow_1790; + x86::Gp ret_val_illegal_indexed_load_1789 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1789, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1789; + setArg(call_get_lmul_pow_1790, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1790, 0, ret_val_get_lmul_pow_1790); + setArg(call_illegal_indexed_load_1789, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1789, 1, vd); + setArg(call_illegal_indexed_load_1789, 2, vm); + setArg(call_illegal_indexed_load_1789, 3, 8); + setArg(call_illegal_indexed_load_1789, 4, EEW); + setArg(call_illegal_indexed_load_1789, 5, illegal_indexed_load_1789_arg4); + setArg(call_illegal_indexed_load_1789, 6, illegal_indexed_load_1789_arg5); + setRet(call_illegal_indexed_load_1789, 0, ret_val_illegal_indexed_load_1789); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1792; + x86::Gp ret_val_sew_1792 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1792, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1791; + auto vlxseg_1791_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1791_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1791_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1791_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1791_arg10 = ret_val_sew_1792; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1791 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1791, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1791, 32, false), traits::vstart); + setArg(call_sew_1792, 0, reinterpret_cast(this)); + setRet(call_sew_1792, 0, ret_val_sew_1792); + setArg(call_vlxseg_1791, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1791, 1, V); + setArg(call_vlxseg_1791, 2, vlxseg_1791_arg1); + setArg(call_vlxseg_1791, 3, vlxseg_1791_arg2); + setArg(call_vlxseg_1791, 4, vlxseg_1791_arg3); + setArg(call_vlxseg_1791, 5, vm); + setArg(call_vlxseg_1791, 6, vd); + setArg(call_vlxseg_1791, 7, vlxseg_1791_arg6); + setArg(call_vlxseg_1791, 8, vs2); + setArg(call_vlxseg_1791, 9, 8); + setArg(call_vlxseg_1791, 10, 8); + setArg(call_vlxseg_1791, 11, vlxseg_1791_arg10); + setArg(call_vlxseg_1791, 12, 0); + setRet(call_vlxseg_1791, 0, ret_val_vlxseg_1791); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 440); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 441: VSUXEI8__V */ + continuation_e __vsuxei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXEI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 441); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1793; + x86::Gp ret_val_get_pow_1793 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1793, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1794; + x86::Gp ret_val_get_sew_pow_1794 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1794, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1795; + x86::Gp ret_val_get_lmul_pow_1795 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1795, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1793, ret_val_get_sew_pow_1794), ret_val_get_lmul_pow_1795)), 3, true); + setArg(call_get_pow_1793, 0, reinterpret_cast(this)); + setArg(call_get_pow_1793, 1, EEW); + setRet(call_get_pow_1793, 0, ret_val_get_pow_1793); + setArg(call_get_sew_pow_1794, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1794, 0, ret_val_get_sew_pow_1794); + setArg(call_get_lmul_pow_1795, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1795, 0, ret_val_get_lmul_pow_1795); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1797; + x86::Gp ret_val_get_lmul_pow_1797 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1797, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1796; + auto illegal_indexed_store_1796_arg2 = EMUL_pow; + auto illegal_indexed_store_1796_arg3 = ret_val_get_lmul_pow_1797; + x86::Gp ret_val_illegal_indexed_store_1796 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1796, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1796; + setArg(call_get_lmul_pow_1797, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1797, 0, ret_val_get_lmul_pow_1797); + setArg(call_illegal_indexed_store_1796, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1796, 1, 1); + setArg(call_illegal_indexed_store_1796, 2, EEW); + setArg(call_illegal_indexed_store_1796, 3, illegal_indexed_store_1796_arg2); + setArg(call_illegal_indexed_store_1796, 4, illegal_indexed_store_1796_arg3); + setRet(call_illegal_indexed_store_1796, 0, ret_val_illegal_indexed_store_1796); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1799; + x86::Gp ret_val_sew_1799 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1799, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1798; + auto vsxseg_1798_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1798_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1798_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1798_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1798_arg10 = ret_val_sew_1799; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1798 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1798, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1798, 32, false), traits::vstart); + setArg(call_sew_1799, 0, reinterpret_cast(this)); + setRet(call_sew_1799, 0, ret_val_sew_1799); + setArg(call_vsxseg_1798, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1798, 1, V); + setArg(call_vsxseg_1798, 2, vsxseg_1798_arg1); + setArg(call_vsxseg_1798, 3, vsxseg_1798_arg2); + setArg(call_vsxseg_1798, 4, vsxseg_1798_arg3); + setArg(call_vsxseg_1798, 5, vm); + setArg(call_vsxseg_1798, 6, vs3); + setArg(call_vsxseg_1798, 7, vsxseg_1798_arg6); + setArg(call_vsxseg_1798, 8, vs2); + setArg(call_vsxseg_1798, 9, 1); + setArg(call_vsxseg_1798, 10, 1); + setArg(call_vsxseg_1798, 11, vsxseg_1798_arg10); + setArg(call_vsxseg_1798, 12, 0); + setRet(call_vsxseg_1798, 0, ret_val_vsxseg_1798); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 441); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 442: VSUXEI16__V */ + continuation_e __vsuxei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXEI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 442); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1800; + x86::Gp ret_val_get_pow_1800 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1800, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1801; + x86::Gp ret_val_get_sew_pow_1801 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1801, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1802; + x86::Gp ret_val_get_lmul_pow_1802 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1802, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1800, ret_val_get_sew_pow_1801), ret_val_get_lmul_pow_1802)), 3, true); + setArg(call_get_pow_1800, 0, reinterpret_cast(this)); + setArg(call_get_pow_1800, 1, EEW); + setRet(call_get_pow_1800, 0, ret_val_get_pow_1800); + setArg(call_get_sew_pow_1801, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1801, 0, ret_val_get_sew_pow_1801); + setArg(call_get_lmul_pow_1802, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1802, 0, ret_val_get_lmul_pow_1802); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1804; + x86::Gp ret_val_get_lmul_pow_1804 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1804, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1803; + auto illegal_indexed_store_1803_arg2 = EMUL_pow; + auto illegal_indexed_store_1803_arg3 = ret_val_get_lmul_pow_1804; + x86::Gp ret_val_illegal_indexed_store_1803 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1803, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1803; + setArg(call_get_lmul_pow_1804, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1804, 0, ret_val_get_lmul_pow_1804); + setArg(call_illegal_indexed_store_1803, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1803, 1, 1); + setArg(call_illegal_indexed_store_1803, 2, EEW); + setArg(call_illegal_indexed_store_1803, 3, illegal_indexed_store_1803_arg2); + setArg(call_illegal_indexed_store_1803, 4, illegal_indexed_store_1803_arg3); + setRet(call_illegal_indexed_store_1803, 0, ret_val_illegal_indexed_store_1803); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1806; + x86::Gp ret_val_sew_1806 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1806, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1805; + auto vsxseg_1805_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1805_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1805_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1805_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1805_arg10 = ret_val_sew_1806; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1805 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1805, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1805, 32, false), traits::vstart); + setArg(call_sew_1806, 0, reinterpret_cast(this)); + setRet(call_sew_1806, 0, ret_val_sew_1806); + setArg(call_vsxseg_1805, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1805, 1, V); + setArg(call_vsxseg_1805, 2, vsxseg_1805_arg1); + setArg(call_vsxseg_1805, 3, vsxseg_1805_arg2); + setArg(call_vsxseg_1805, 4, vsxseg_1805_arg3); + setArg(call_vsxseg_1805, 5, vm); + setArg(call_vsxseg_1805, 6, vs3); + setArg(call_vsxseg_1805, 7, vsxseg_1805_arg6); + setArg(call_vsxseg_1805, 8, vs2); + setArg(call_vsxseg_1805, 9, 1); + setArg(call_vsxseg_1805, 10, 2); + setArg(call_vsxseg_1805, 11, vsxseg_1805_arg10); + setArg(call_vsxseg_1805, 12, 0); + setRet(call_vsxseg_1805, 0, ret_val_vsxseg_1805); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 442); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 443: VSUXEI32__V */ + continuation_e __vsuxei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXEI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 443); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1807; + x86::Gp ret_val_get_pow_1807 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1807, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1808; + x86::Gp ret_val_get_sew_pow_1808 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1808, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1809; + x86::Gp ret_val_get_lmul_pow_1809 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1809, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1807, ret_val_get_sew_pow_1808), ret_val_get_lmul_pow_1809)), 3, true); + setArg(call_get_pow_1807, 0, reinterpret_cast(this)); + setArg(call_get_pow_1807, 1, EEW); + setRet(call_get_pow_1807, 0, ret_val_get_pow_1807); + setArg(call_get_sew_pow_1808, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1808, 0, ret_val_get_sew_pow_1808); + setArg(call_get_lmul_pow_1809, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1809, 0, ret_val_get_lmul_pow_1809); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1811; + x86::Gp ret_val_get_lmul_pow_1811 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1811, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1810; + auto illegal_indexed_store_1810_arg2 = EMUL_pow; + auto illegal_indexed_store_1810_arg3 = ret_val_get_lmul_pow_1811; + x86::Gp ret_val_illegal_indexed_store_1810 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1810, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1810; + setArg(call_get_lmul_pow_1811, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1811, 0, ret_val_get_lmul_pow_1811); + setArg(call_illegal_indexed_store_1810, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1810, 1, 1); + setArg(call_illegal_indexed_store_1810, 2, EEW); + setArg(call_illegal_indexed_store_1810, 3, illegal_indexed_store_1810_arg2); + setArg(call_illegal_indexed_store_1810, 4, illegal_indexed_store_1810_arg3); + setRet(call_illegal_indexed_store_1810, 0, ret_val_illegal_indexed_store_1810); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1813; + x86::Gp ret_val_sew_1813 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1813, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1812; + auto vsxseg_1812_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1812_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1812_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1812_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1812_arg10 = ret_val_sew_1813; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1812 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1812, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1812, 32, false), traits::vstart); + setArg(call_sew_1813, 0, reinterpret_cast(this)); + setRet(call_sew_1813, 0, ret_val_sew_1813); + setArg(call_vsxseg_1812, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1812, 1, V); + setArg(call_vsxseg_1812, 2, vsxseg_1812_arg1); + setArg(call_vsxseg_1812, 3, vsxseg_1812_arg2); + setArg(call_vsxseg_1812, 4, vsxseg_1812_arg3); + setArg(call_vsxseg_1812, 5, vm); + setArg(call_vsxseg_1812, 6, vs3); + setArg(call_vsxseg_1812, 7, vsxseg_1812_arg6); + setArg(call_vsxseg_1812, 8, vs2); + setArg(call_vsxseg_1812, 9, 1); + setArg(call_vsxseg_1812, 10, 4); + setArg(call_vsxseg_1812, 11, vsxseg_1812_arg10); + setArg(call_vsxseg_1812, 12, 0); + setRet(call_vsxseg_1812, 0, ret_val_vsxseg_1812); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 443); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 444: VSUXEI64__V */ + continuation_e __vsuxei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXEI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 444); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1814; + x86::Gp ret_val_get_pow_1814 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1814, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1815; + x86::Gp ret_val_get_sew_pow_1815 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1815, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1816; + x86::Gp ret_val_get_lmul_pow_1816 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1816, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1814, ret_val_get_sew_pow_1815), ret_val_get_lmul_pow_1816)), 3, true); + setArg(call_get_pow_1814, 0, reinterpret_cast(this)); + setArg(call_get_pow_1814, 1, EEW); + setRet(call_get_pow_1814, 0, ret_val_get_pow_1814); + setArg(call_get_sew_pow_1815, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1815, 0, ret_val_get_sew_pow_1815); + setArg(call_get_lmul_pow_1816, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1816, 0, ret_val_get_lmul_pow_1816); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1818; + x86::Gp ret_val_get_lmul_pow_1818 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1818, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1817; + auto illegal_indexed_store_1817_arg2 = EMUL_pow; + auto illegal_indexed_store_1817_arg3 = ret_val_get_lmul_pow_1818; + x86::Gp ret_val_illegal_indexed_store_1817 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1817, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1817; + setArg(call_get_lmul_pow_1818, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1818, 0, ret_val_get_lmul_pow_1818); + setArg(call_illegal_indexed_store_1817, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1817, 1, 1); + setArg(call_illegal_indexed_store_1817, 2, EEW); + setArg(call_illegal_indexed_store_1817, 3, illegal_indexed_store_1817_arg2); + setArg(call_illegal_indexed_store_1817, 4, illegal_indexed_store_1817_arg3); + setRet(call_illegal_indexed_store_1817, 0, ret_val_illegal_indexed_store_1817); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1820; + x86::Gp ret_val_sew_1820 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1820, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1819; + auto vsxseg_1819_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1819_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1819_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1819_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1819_arg10 = ret_val_sew_1820; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1819 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1819, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1819, 32, false), traits::vstart); + setArg(call_sew_1820, 0, reinterpret_cast(this)); + setRet(call_sew_1820, 0, ret_val_sew_1820); + setArg(call_vsxseg_1819, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1819, 1, V); + setArg(call_vsxseg_1819, 2, vsxseg_1819_arg1); + setArg(call_vsxseg_1819, 3, vsxseg_1819_arg2); + setArg(call_vsxseg_1819, 4, vsxseg_1819_arg3); + setArg(call_vsxseg_1819, 5, vm); + setArg(call_vsxseg_1819, 6, vs3); + setArg(call_vsxseg_1819, 7, vsxseg_1819_arg6); + setArg(call_vsxseg_1819, 8, vs2); + setArg(call_vsxseg_1819, 9, 1); + setArg(call_vsxseg_1819, 10, 8); + setArg(call_vsxseg_1819, 11, vsxseg_1819_arg10); + setArg(call_vsxseg_1819, 12, 0); + setRet(call_vsxseg_1819, 0, ret_val_vsxseg_1819); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 444); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 445: VSUXSEG2EI8__V */ + continuation_e __vsuxseg2ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG2EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 445); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1821; + x86::Gp ret_val_get_pow_1821 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1821, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1822; + x86::Gp ret_val_get_sew_pow_1822 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1822, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1823; + x86::Gp ret_val_get_lmul_pow_1823 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1823, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1821, ret_val_get_sew_pow_1822), ret_val_get_lmul_pow_1823)), 3, true); + setArg(call_get_pow_1821, 0, reinterpret_cast(this)); + setArg(call_get_pow_1821, 1, EEW); + setRet(call_get_pow_1821, 0, ret_val_get_pow_1821); + setArg(call_get_sew_pow_1822, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1822, 0, ret_val_get_sew_pow_1822); + setArg(call_get_lmul_pow_1823, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1823, 0, ret_val_get_lmul_pow_1823); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1825; + x86::Gp ret_val_get_lmul_pow_1825 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1825, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1824; + auto illegal_indexed_store_1824_arg2 = EMUL_pow; + auto illegal_indexed_store_1824_arg3 = ret_val_get_lmul_pow_1825; + x86::Gp ret_val_illegal_indexed_store_1824 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1824, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1824; + setArg(call_get_lmul_pow_1825, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1825, 0, ret_val_get_lmul_pow_1825); + setArg(call_illegal_indexed_store_1824, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1824, 1, 2); + setArg(call_illegal_indexed_store_1824, 2, EEW); + setArg(call_illegal_indexed_store_1824, 3, illegal_indexed_store_1824_arg2); + setArg(call_illegal_indexed_store_1824, 4, illegal_indexed_store_1824_arg3); + setRet(call_illegal_indexed_store_1824, 0, ret_val_illegal_indexed_store_1824); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1827; + x86::Gp ret_val_sew_1827 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1827, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1826; + auto vsxseg_1826_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1826_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1826_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1826_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1826_arg10 = ret_val_sew_1827; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1826 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1826, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1826, 32, false), traits::vstart); + setArg(call_sew_1827, 0, reinterpret_cast(this)); + setRet(call_sew_1827, 0, ret_val_sew_1827); + setArg(call_vsxseg_1826, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1826, 1, V); + setArg(call_vsxseg_1826, 2, vsxseg_1826_arg1); + setArg(call_vsxseg_1826, 3, vsxseg_1826_arg2); + setArg(call_vsxseg_1826, 4, vsxseg_1826_arg3); + setArg(call_vsxseg_1826, 5, vm); + setArg(call_vsxseg_1826, 6, vs3); + setArg(call_vsxseg_1826, 7, vsxseg_1826_arg6); + setArg(call_vsxseg_1826, 8, vs2); + setArg(call_vsxseg_1826, 9, 2); + setArg(call_vsxseg_1826, 10, 1); + setArg(call_vsxseg_1826, 11, vsxseg_1826_arg10); + setArg(call_vsxseg_1826, 12, 0); + setRet(call_vsxseg_1826, 0, ret_val_vsxseg_1826); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 445); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 446: VSUXSEG2EI16__V */ + continuation_e __vsuxseg2ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG2EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 446); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1828; + x86::Gp ret_val_get_pow_1828 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1828, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1829; + x86::Gp ret_val_get_sew_pow_1829 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1829, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1830; + x86::Gp ret_val_get_lmul_pow_1830 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1830, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1828, ret_val_get_sew_pow_1829), ret_val_get_lmul_pow_1830)), 3, true); + setArg(call_get_pow_1828, 0, reinterpret_cast(this)); + setArg(call_get_pow_1828, 1, EEW); + setRet(call_get_pow_1828, 0, ret_val_get_pow_1828); + setArg(call_get_sew_pow_1829, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1829, 0, ret_val_get_sew_pow_1829); + setArg(call_get_lmul_pow_1830, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1830, 0, ret_val_get_lmul_pow_1830); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1832; + x86::Gp ret_val_get_lmul_pow_1832 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1832, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1831; + auto illegal_indexed_store_1831_arg2 = EMUL_pow; + auto illegal_indexed_store_1831_arg3 = ret_val_get_lmul_pow_1832; + x86::Gp ret_val_illegal_indexed_store_1831 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1831, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1831; + setArg(call_get_lmul_pow_1832, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1832, 0, ret_val_get_lmul_pow_1832); + setArg(call_illegal_indexed_store_1831, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1831, 1, 2); + setArg(call_illegal_indexed_store_1831, 2, EEW); + setArg(call_illegal_indexed_store_1831, 3, illegal_indexed_store_1831_arg2); + setArg(call_illegal_indexed_store_1831, 4, illegal_indexed_store_1831_arg3); + setRet(call_illegal_indexed_store_1831, 0, ret_val_illegal_indexed_store_1831); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1834; + x86::Gp ret_val_sew_1834 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1834, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1833; + auto vsxseg_1833_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1833_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1833_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1833_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1833_arg10 = ret_val_sew_1834; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1833 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1833, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1833, 32, false), traits::vstart); + setArg(call_sew_1834, 0, reinterpret_cast(this)); + setRet(call_sew_1834, 0, ret_val_sew_1834); + setArg(call_vsxseg_1833, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1833, 1, V); + setArg(call_vsxseg_1833, 2, vsxseg_1833_arg1); + setArg(call_vsxseg_1833, 3, vsxseg_1833_arg2); + setArg(call_vsxseg_1833, 4, vsxseg_1833_arg3); + setArg(call_vsxseg_1833, 5, vm); + setArg(call_vsxseg_1833, 6, vs3); + setArg(call_vsxseg_1833, 7, vsxseg_1833_arg6); + setArg(call_vsxseg_1833, 8, vs2); + setArg(call_vsxseg_1833, 9, 2); + setArg(call_vsxseg_1833, 10, 2); + setArg(call_vsxseg_1833, 11, vsxseg_1833_arg10); + setArg(call_vsxseg_1833, 12, 0); + setRet(call_vsxseg_1833, 0, ret_val_vsxseg_1833); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 446); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 447: VSUXSEG2EI32__V */ + continuation_e __vsuxseg2ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG2EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 447); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1835; + x86::Gp ret_val_get_pow_1835 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1835, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1836; + x86::Gp ret_val_get_sew_pow_1836 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1836, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1837; + x86::Gp ret_val_get_lmul_pow_1837 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1837, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1835, ret_val_get_sew_pow_1836), ret_val_get_lmul_pow_1837)), 3, true); + setArg(call_get_pow_1835, 0, reinterpret_cast(this)); + setArg(call_get_pow_1835, 1, EEW); + setRet(call_get_pow_1835, 0, ret_val_get_pow_1835); + setArg(call_get_sew_pow_1836, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1836, 0, ret_val_get_sew_pow_1836); + setArg(call_get_lmul_pow_1837, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1837, 0, ret_val_get_lmul_pow_1837); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1839; + x86::Gp ret_val_get_lmul_pow_1839 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1839, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1838; + auto illegal_indexed_store_1838_arg2 = EMUL_pow; + auto illegal_indexed_store_1838_arg3 = ret_val_get_lmul_pow_1839; + x86::Gp ret_val_illegal_indexed_store_1838 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1838, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1838; + setArg(call_get_lmul_pow_1839, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1839, 0, ret_val_get_lmul_pow_1839); + setArg(call_illegal_indexed_store_1838, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1838, 1, 2); + setArg(call_illegal_indexed_store_1838, 2, EEW); + setArg(call_illegal_indexed_store_1838, 3, illegal_indexed_store_1838_arg2); + setArg(call_illegal_indexed_store_1838, 4, illegal_indexed_store_1838_arg3); + setRet(call_illegal_indexed_store_1838, 0, ret_val_illegal_indexed_store_1838); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1841; + x86::Gp ret_val_sew_1841 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1841, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1840; + auto vsxseg_1840_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1840_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1840_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1840_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1840_arg10 = ret_val_sew_1841; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1840 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1840, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1840, 32, false), traits::vstart); + setArg(call_sew_1841, 0, reinterpret_cast(this)); + setRet(call_sew_1841, 0, ret_val_sew_1841); + setArg(call_vsxseg_1840, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1840, 1, V); + setArg(call_vsxseg_1840, 2, vsxseg_1840_arg1); + setArg(call_vsxseg_1840, 3, vsxseg_1840_arg2); + setArg(call_vsxseg_1840, 4, vsxseg_1840_arg3); + setArg(call_vsxseg_1840, 5, vm); + setArg(call_vsxseg_1840, 6, vs3); + setArg(call_vsxseg_1840, 7, vsxseg_1840_arg6); + setArg(call_vsxseg_1840, 8, vs2); + setArg(call_vsxseg_1840, 9, 2); + setArg(call_vsxseg_1840, 10, 4); + setArg(call_vsxseg_1840, 11, vsxseg_1840_arg10); + setArg(call_vsxseg_1840, 12, 0); + setRet(call_vsxseg_1840, 0, ret_val_vsxseg_1840); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 447); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 448: VSUXSEG2EI64__V */ + continuation_e __vsuxseg2ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG2EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 448); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1842; + x86::Gp ret_val_get_pow_1842 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1842, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1843; + x86::Gp ret_val_get_sew_pow_1843 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1843, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1844; + x86::Gp ret_val_get_lmul_pow_1844 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1844, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1842, ret_val_get_sew_pow_1843), ret_val_get_lmul_pow_1844)), 3, true); + setArg(call_get_pow_1842, 0, reinterpret_cast(this)); + setArg(call_get_pow_1842, 1, EEW); + setRet(call_get_pow_1842, 0, ret_val_get_pow_1842); + setArg(call_get_sew_pow_1843, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1843, 0, ret_val_get_sew_pow_1843); + setArg(call_get_lmul_pow_1844, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1844, 0, ret_val_get_lmul_pow_1844); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1846; + x86::Gp ret_val_get_lmul_pow_1846 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1846, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1845; + auto illegal_indexed_store_1845_arg2 = EMUL_pow; + auto illegal_indexed_store_1845_arg3 = ret_val_get_lmul_pow_1846; + x86::Gp ret_val_illegal_indexed_store_1845 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1845, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1845; + setArg(call_get_lmul_pow_1846, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1846, 0, ret_val_get_lmul_pow_1846); + setArg(call_illegal_indexed_store_1845, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1845, 1, 2); + setArg(call_illegal_indexed_store_1845, 2, EEW); + setArg(call_illegal_indexed_store_1845, 3, illegal_indexed_store_1845_arg2); + setArg(call_illegal_indexed_store_1845, 4, illegal_indexed_store_1845_arg3); + setRet(call_illegal_indexed_store_1845, 0, ret_val_illegal_indexed_store_1845); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1848; + x86::Gp ret_val_sew_1848 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1848, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1847; + auto vsxseg_1847_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1847_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1847_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1847_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1847_arg10 = ret_val_sew_1848; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1847 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1847, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1847, 32, false), traits::vstart); + setArg(call_sew_1848, 0, reinterpret_cast(this)); + setRet(call_sew_1848, 0, ret_val_sew_1848); + setArg(call_vsxseg_1847, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1847, 1, V); + setArg(call_vsxseg_1847, 2, vsxseg_1847_arg1); + setArg(call_vsxseg_1847, 3, vsxseg_1847_arg2); + setArg(call_vsxseg_1847, 4, vsxseg_1847_arg3); + setArg(call_vsxseg_1847, 5, vm); + setArg(call_vsxseg_1847, 6, vs3); + setArg(call_vsxseg_1847, 7, vsxseg_1847_arg6); + setArg(call_vsxseg_1847, 8, vs2); + setArg(call_vsxseg_1847, 9, 2); + setArg(call_vsxseg_1847, 10, 8); + setArg(call_vsxseg_1847, 11, vsxseg_1847_arg10); + setArg(call_vsxseg_1847, 12, 0); + setRet(call_vsxseg_1847, 0, ret_val_vsxseg_1847); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 448); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 449: VSUXSEG3EI8__V */ + continuation_e __vsuxseg3ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG3EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 449); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1849; + x86::Gp ret_val_get_pow_1849 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1849, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1850; + x86::Gp ret_val_get_sew_pow_1850 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1850, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1851; + x86::Gp ret_val_get_lmul_pow_1851 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1851, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1849, ret_val_get_sew_pow_1850), ret_val_get_lmul_pow_1851)), 3, true); + setArg(call_get_pow_1849, 0, reinterpret_cast(this)); + setArg(call_get_pow_1849, 1, EEW); + setRet(call_get_pow_1849, 0, ret_val_get_pow_1849); + setArg(call_get_sew_pow_1850, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1850, 0, ret_val_get_sew_pow_1850); + setArg(call_get_lmul_pow_1851, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1851, 0, ret_val_get_lmul_pow_1851); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1853; + x86::Gp ret_val_get_lmul_pow_1853 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1853, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1852; + auto illegal_indexed_store_1852_arg2 = EMUL_pow; + auto illegal_indexed_store_1852_arg3 = ret_val_get_lmul_pow_1853; + x86::Gp ret_val_illegal_indexed_store_1852 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1852, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1852; + setArg(call_get_lmul_pow_1853, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1853, 0, ret_val_get_lmul_pow_1853); + setArg(call_illegal_indexed_store_1852, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1852, 1, 3); + setArg(call_illegal_indexed_store_1852, 2, EEW); + setArg(call_illegal_indexed_store_1852, 3, illegal_indexed_store_1852_arg2); + setArg(call_illegal_indexed_store_1852, 4, illegal_indexed_store_1852_arg3); + setRet(call_illegal_indexed_store_1852, 0, ret_val_illegal_indexed_store_1852); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1855; + x86::Gp ret_val_sew_1855 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1855, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1854; + auto vsxseg_1854_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1854_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1854_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1854_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1854_arg10 = ret_val_sew_1855; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1854 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1854, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1854, 32, false), traits::vstart); + setArg(call_sew_1855, 0, reinterpret_cast(this)); + setRet(call_sew_1855, 0, ret_val_sew_1855); + setArg(call_vsxseg_1854, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1854, 1, V); + setArg(call_vsxseg_1854, 2, vsxseg_1854_arg1); + setArg(call_vsxseg_1854, 3, vsxseg_1854_arg2); + setArg(call_vsxseg_1854, 4, vsxseg_1854_arg3); + setArg(call_vsxseg_1854, 5, vm); + setArg(call_vsxseg_1854, 6, vs3); + setArg(call_vsxseg_1854, 7, vsxseg_1854_arg6); + setArg(call_vsxseg_1854, 8, vs2); + setArg(call_vsxseg_1854, 9, 3); + setArg(call_vsxseg_1854, 10, 1); + setArg(call_vsxseg_1854, 11, vsxseg_1854_arg10); + setArg(call_vsxseg_1854, 12, 0); + setRet(call_vsxseg_1854, 0, ret_val_vsxseg_1854); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 449); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 450: VSUXSEG3EI16__V */ + continuation_e __vsuxseg3ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG3EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 450); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1856; + x86::Gp ret_val_get_pow_1856 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1856, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1857; + x86::Gp ret_val_get_sew_pow_1857 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1857, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1858; + x86::Gp ret_val_get_lmul_pow_1858 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1858, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1856, ret_val_get_sew_pow_1857), ret_val_get_lmul_pow_1858)), 3, true); + setArg(call_get_pow_1856, 0, reinterpret_cast(this)); + setArg(call_get_pow_1856, 1, EEW); + setRet(call_get_pow_1856, 0, ret_val_get_pow_1856); + setArg(call_get_sew_pow_1857, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1857, 0, ret_val_get_sew_pow_1857); + setArg(call_get_lmul_pow_1858, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1858, 0, ret_val_get_lmul_pow_1858); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1860; + x86::Gp ret_val_get_lmul_pow_1860 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1860, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1859; + auto illegal_indexed_store_1859_arg2 = EMUL_pow; + auto illegal_indexed_store_1859_arg3 = ret_val_get_lmul_pow_1860; + x86::Gp ret_val_illegal_indexed_store_1859 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1859, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1859; + setArg(call_get_lmul_pow_1860, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1860, 0, ret_val_get_lmul_pow_1860); + setArg(call_illegal_indexed_store_1859, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1859, 1, 3); + setArg(call_illegal_indexed_store_1859, 2, EEW); + setArg(call_illegal_indexed_store_1859, 3, illegal_indexed_store_1859_arg2); + setArg(call_illegal_indexed_store_1859, 4, illegal_indexed_store_1859_arg3); + setRet(call_illegal_indexed_store_1859, 0, ret_val_illegal_indexed_store_1859); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1862; + x86::Gp ret_val_sew_1862 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1862, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1861; + auto vsxseg_1861_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1861_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1861_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1861_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1861_arg10 = ret_val_sew_1862; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1861 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1861, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1861, 32, false), traits::vstart); + setArg(call_sew_1862, 0, reinterpret_cast(this)); + setRet(call_sew_1862, 0, ret_val_sew_1862); + setArg(call_vsxseg_1861, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1861, 1, V); + setArg(call_vsxseg_1861, 2, vsxseg_1861_arg1); + setArg(call_vsxseg_1861, 3, vsxseg_1861_arg2); + setArg(call_vsxseg_1861, 4, vsxseg_1861_arg3); + setArg(call_vsxseg_1861, 5, vm); + setArg(call_vsxseg_1861, 6, vs3); + setArg(call_vsxseg_1861, 7, vsxseg_1861_arg6); + setArg(call_vsxseg_1861, 8, vs2); + setArg(call_vsxseg_1861, 9, 3); + setArg(call_vsxseg_1861, 10, 2); + setArg(call_vsxseg_1861, 11, vsxseg_1861_arg10); + setArg(call_vsxseg_1861, 12, 0); + setRet(call_vsxseg_1861, 0, ret_val_vsxseg_1861); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 450); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 451: VSUXSEG3EI32__V */ + continuation_e __vsuxseg3ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG3EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 451); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1863; + x86::Gp ret_val_get_pow_1863 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1863, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1864; + x86::Gp ret_val_get_sew_pow_1864 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1864, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1865; + x86::Gp ret_val_get_lmul_pow_1865 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1865, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1863, ret_val_get_sew_pow_1864), ret_val_get_lmul_pow_1865)), 3, true); + setArg(call_get_pow_1863, 0, reinterpret_cast(this)); + setArg(call_get_pow_1863, 1, EEW); + setRet(call_get_pow_1863, 0, ret_val_get_pow_1863); + setArg(call_get_sew_pow_1864, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1864, 0, ret_val_get_sew_pow_1864); + setArg(call_get_lmul_pow_1865, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1865, 0, ret_val_get_lmul_pow_1865); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1867; + x86::Gp ret_val_get_lmul_pow_1867 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1867, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1866; + auto illegal_indexed_store_1866_arg2 = EMUL_pow; + auto illegal_indexed_store_1866_arg3 = ret_val_get_lmul_pow_1867; + x86::Gp ret_val_illegal_indexed_store_1866 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1866, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1866; + setArg(call_get_lmul_pow_1867, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1867, 0, ret_val_get_lmul_pow_1867); + setArg(call_illegal_indexed_store_1866, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1866, 1, 3); + setArg(call_illegal_indexed_store_1866, 2, EEW); + setArg(call_illegal_indexed_store_1866, 3, illegal_indexed_store_1866_arg2); + setArg(call_illegal_indexed_store_1866, 4, illegal_indexed_store_1866_arg3); + setRet(call_illegal_indexed_store_1866, 0, ret_val_illegal_indexed_store_1866); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1869; + x86::Gp ret_val_sew_1869 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1869, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1868; + auto vsxseg_1868_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1868_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1868_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1868_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1868_arg10 = ret_val_sew_1869; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1868 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1868, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1868, 32, false), traits::vstart); + setArg(call_sew_1869, 0, reinterpret_cast(this)); + setRet(call_sew_1869, 0, ret_val_sew_1869); + setArg(call_vsxseg_1868, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1868, 1, V); + setArg(call_vsxseg_1868, 2, vsxseg_1868_arg1); + setArg(call_vsxseg_1868, 3, vsxseg_1868_arg2); + setArg(call_vsxseg_1868, 4, vsxseg_1868_arg3); + setArg(call_vsxseg_1868, 5, vm); + setArg(call_vsxseg_1868, 6, vs3); + setArg(call_vsxseg_1868, 7, vsxseg_1868_arg6); + setArg(call_vsxseg_1868, 8, vs2); + setArg(call_vsxseg_1868, 9, 3); + setArg(call_vsxseg_1868, 10, 4); + setArg(call_vsxseg_1868, 11, vsxseg_1868_arg10); + setArg(call_vsxseg_1868, 12, 0); + setRet(call_vsxseg_1868, 0, ret_val_vsxseg_1868); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 451); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 452: VSUXSEG3EI64__V */ + continuation_e __vsuxseg3ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG3EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 452); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1870; + x86::Gp ret_val_get_pow_1870 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1870, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1871; + x86::Gp ret_val_get_sew_pow_1871 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1871, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1872; + x86::Gp ret_val_get_lmul_pow_1872 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1872, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1870, ret_val_get_sew_pow_1871), ret_val_get_lmul_pow_1872)), 3, true); + setArg(call_get_pow_1870, 0, reinterpret_cast(this)); + setArg(call_get_pow_1870, 1, EEW); + setRet(call_get_pow_1870, 0, ret_val_get_pow_1870); + setArg(call_get_sew_pow_1871, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1871, 0, ret_val_get_sew_pow_1871); + setArg(call_get_lmul_pow_1872, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1872, 0, ret_val_get_lmul_pow_1872); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1874; + x86::Gp ret_val_get_lmul_pow_1874 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1874, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1873; + auto illegal_indexed_store_1873_arg2 = EMUL_pow; + auto illegal_indexed_store_1873_arg3 = ret_val_get_lmul_pow_1874; + x86::Gp ret_val_illegal_indexed_store_1873 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1873, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1873; + setArg(call_get_lmul_pow_1874, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1874, 0, ret_val_get_lmul_pow_1874); + setArg(call_illegal_indexed_store_1873, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1873, 1, 3); + setArg(call_illegal_indexed_store_1873, 2, EEW); + setArg(call_illegal_indexed_store_1873, 3, illegal_indexed_store_1873_arg2); + setArg(call_illegal_indexed_store_1873, 4, illegal_indexed_store_1873_arg3); + setRet(call_illegal_indexed_store_1873, 0, ret_val_illegal_indexed_store_1873); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1876; + x86::Gp ret_val_sew_1876 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1876, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1875; + auto vsxseg_1875_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1875_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1875_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1875_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1875_arg10 = ret_val_sew_1876; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1875 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1875, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1875, 32, false), traits::vstart); + setArg(call_sew_1876, 0, reinterpret_cast(this)); + setRet(call_sew_1876, 0, ret_val_sew_1876); + setArg(call_vsxseg_1875, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1875, 1, V); + setArg(call_vsxseg_1875, 2, vsxseg_1875_arg1); + setArg(call_vsxseg_1875, 3, vsxseg_1875_arg2); + setArg(call_vsxseg_1875, 4, vsxseg_1875_arg3); + setArg(call_vsxseg_1875, 5, vm); + setArg(call_vsxseg_1875, 6, vs3); + setArg(call_vsxseg_1875, 7, vsxseg_1875_arg6); + setArg(call_vsxseg_1875, 8, vs2); + setArg(call_vsxseg_1875, 9, 3); + setArg(call_vsxseg_1875, 10, 8); + setArg(call_vsxseg_1875, 11, vsxseg_1875_arg10); + setArg(call_vsxseg_1875, 12, 0); + setRet(call_vsxseg_1875, 0, ret_val_vsxseg_1875); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 452); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 453: VSUXSEG4EI8__V */ + continuation_e __vsuxseg4ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG4EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 453); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1877; + x86::Gp ret_val_get_pow_1877 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1877, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1878; + x86::Gp ret_val_get_sew_pow_1878 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1878, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1879; + x86::Gp ret_val_get_lmul_pow_1879 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1879, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1877, ret_val_get_sew_pow_1878), ret_val_get_lmul_pow_1879)), 3, true); + setArg(call_get_pow_1877, 0, reinterpret_cast(this)); + setArg(call_get_pow_1877, 1, EEW); + setRet(call_get_pow_1877, 0, ret_val_get_pow_1877); + setArg(call_get_sew_pow_1878, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1878, 0, ret_val_get_sew_pow_1878); + setArg(call_get_lmul_pow_1879, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1879, 0, ret_val_get_lmul_pow_1879); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1881; + x86::Gp ret_val_get_lmul_pow_1881 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1881, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1880; + auto illegal_indexed_store_1880_arg2 = EMUL_pow; + auto illegal_indexed_store_1880_arg3 = ret_val_get_lmul_pow_1881; + x86::Gp ret_val_illegal_indexed_store_1880 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1880, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1880; + setArg(call_get_lmul_pow_1881, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1881, 0, ret_val_get_lmul_pow_1881); + setArg(call_illegal_indexed_store_1880, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1880, 1, 4); + setArg(call_illegal_indexed_store_1880, 2, EEW); + setArg(call_illegal_indexed_store_1880, 3, illegal_indexed_store_1880_arg2); + setArg(call_illegal_indexed_store_1880, 4, illegal_indexed_store_1880_arg3); + setRet(call_illegal_indexed_store_1880, 0, ret_val_illegal_indexed_store_1880); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1883; + x86::Gp ret_val_sew_1883 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1883, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1882; + auto vsxseg_1882_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1882_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1882_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1882_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1882_arg10 = ret_val_sew_1883; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1882 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1882, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1882, 32, false), traits::vstart); + setArg(call_sew_1883, 0, reinterpret_cast(this)); + setRet(call_sew_1883, 0, ret_val_sew_1883); + setArg(call_vsxseg_1882, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1882, 1, V); + setArg(call_vsxseg_1882, 2, vsxseg_1882_arg1); + setArg(call_vsxseg_1882, 3, vsxseg_1882_arg2); + setArg(call_vsxseg_1882, 4, vsxseg_1882_arg3); + setArg(call_vsxseg_1882, 5, vm); + setArg(call_vsxseg_1882, 6, vs3); + setArg(call_vsxseg_1882, 7, vsxseg_1882_arg6); + setArg(call_vsxseg_1882, 8, vs2); + setArg(call_vsxseg_1882, 9, 4); + setArg(call_vsxseg_1882, 10, 1); + setArg(call_vsxseg_1882, 11, vsxseg_1882_arg10); + setArg(call_vsxseg_1882, 12, 0); + setRet(call_vsxseg_1882, 0, ret_val_vsxseg_1882); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 453); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 454: VSUXSEG4EI16__V */ + continuation_e __vsuxseg4ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG4EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 454); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1884; + x86::Gp ret_val_get_pow_1884 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1884, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1885; + x86::Gp ret_val_get_sew_pow_1885 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1885, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1886; + x86::Gp ret_val_get_lmul_pow_1886 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1886, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1884, ret_val_get_sew_pow_1885), ret_val_get_lmul_pow_1886)), 3, true); + setArg(call_get_pow_1884, 0, reinterpret_cast(this)); + setArg(call_get_pow_1884, 1, EEW); + setRet(call_get_pow_1884, 0, ret_val_get_pow_1884); + setArg(call_get_sew_pow_1885, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1885, 0, ret_val_get_sew_pow_1885); + setArg(call_get_lmul_pow_1886, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1886, 0, ret_val_get_lmul_pow_1886); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1888; + x86::Gp ret_val_get_lmul_pow_1888 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1888, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1887; + auto illegal_indexed_store_1887_arg2 = EMUL_pow; + auto illegal_indexed_store_1887_arg3 = ret_val_get_lmul_pow_1888; + x86::Gp ret_val_illegal_indexed_store_1887 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1887, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1887; + setArg(call_get_lmul_pow_1888, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1888, 0, ret_val_get_lmul_pow_1888); + setArg(call_illegal_indexed_store_1887, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1887, 1, 4); + setArg(call_illegal_indexed_store_1887, 2, EEW); + setArg(call_illegal_indexed_store_1887, 3, illegal_indexed_store_1887_arg2); + setArg(call_illegal_indexed_store_1887, 4, illegal_indexed_store_1887_arg3); + setRet(call_illegal_indexed_store_1887, 0, ret_val_illegal_indexed_store_1887); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1890; + x86::Gp ret_val_sew_1890 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1890, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1889; + auto vsxseg_1889_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1889_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1889_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1889_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1889_arg10 = ret_val_sew_1890; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1889 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1889, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1889, 32, false), traits::vstart); + setArg(call_sew_1890, 0, reinterpret_cast(this)); + setRet(call_sew_1890, 0, ret_val_sew_1890); + setArg(call_vsxseg_1889, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1889, 1, V); + setArg(call_vsxseg_1889, 2, vsxseg_1889_arg1); + setArg(call_vsxseg_1889, 3, vsxseg_1889_arg2); + setArg(call_vsxseg_1889, 4, vsxseg_1889_arg3); + setArg(call_vsxseg_1889, 5, vm); + setArg(call_vsxseg_1889, 6, vs3); + setArg(call_vsxseg_1889, 7, vsxseg_1889_arg6); + setArg(call_vsxseg_1889, 8, vs2); + setArg(call_vsxseg_1889, 9, 4); + setArg(call_vsxseg_1889, 10, 2); + setArg(call_vsxseg_1889, 11, vsxseg_1889_arg10); + setArg(call_vsxseg_1889, 12, 0); + setRet(call_vsxseg_1889, 0, ret_val_vsxseg_1889); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 454); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 455: VSUXSEG4EI32__V */ + continuation_e __vsuxseg4ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG4EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 455); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1891; + x86::Gp ret_val_get_pow_1891 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1891, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1892; + x86::Gp ret_val_get_sew_pow_1892 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1892, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1893; + x86::Gp ret_val_get_lmul_pow_1893 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1893, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1891, ret_val_get_sew_pow_1892), ret_val_get_lmul_pow_1893)), 3, true); + setArg(call_get_pow_1891, 0, reinterpret_cast(this)); + setArg(call_get_pow_1891, 1, EEW); + setRet(call_get_pow_1891, 0, ret_val_get_pow_1891); + setArg(call_get_sew_pow_1892, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1892, 0, ret_val_get_sew_pow_1892); + setArg(call_get_lmul_pow_1893, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1893, 0, ret_val_get_lmul_pow_1893); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1895; + x86::Gp ret_val_get_lmul_pow_1895 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1895, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1894; + auto illegal_indexed_store_1894_arg2 = EMUL_pow; + auto illegal_indexed_store_1894_arg3 = ret_val_get_lmul_pow_1895; + x86::Gp ret_val_illegal_indexed_store_1894 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1894, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1894; + setArg(call_get_lmul_pow_1895, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1895, 0, ret_val_get_lmul_pow_1895); + setArg(call_illegal_indexed_store_1894, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1894, 1, 4); + setArg(call_illegal_indexed_store_1894, 2, EEW); + setArg(call_illegal_indexed_store_1894, 3, illegal_indexed_store_1894_arg2); + setArg(call_illegal_indexed_store_1894, 4, illegal_indexed_store_1894_arg3); + setRet(call_illegal_indexed_store_1894, 0, ret_val_illegal_indexed_store_1894); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1897; + x86::Gp ret_val_sew_1897 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1897, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1896; + auto vsxseg_1896_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1896_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1896_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1896_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1896_arg10 = ret_val_sew_1897; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1896 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1896, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1896, 32, false), traits::vstart); + setArg(call_sew_1897, 0, reinterpret_cast(this)); + setRet(call_sew_1897, 0, ret_val_sew_1897); + setArg(call_vsxseg_1896, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1896, 1, V); + setArg(call_vsxseg_1896, 2, vsxseg_1896_arg1); + setArg(call_vsxseg_1896, 3, vsxseg_1896_arg2); + setArg(call_vsxseg_1896, 4, vsxseg_1896_arg3); + setArg(call_vsxseg_1896, 5, vm); + setArg(call_vsxseg_1896, 6, vs3); + setArg(call_vsxseg_1896, 7, vsxseg_1896_arg6); + setArg(call_vsxseg_1896, 8, vs2); + setArg(call_vsxseg_1896, 9, 4); + setArg(call_vsxseg_1896, 10, 4); + setArg(call_vsxseg_1896, 11, vsxseg_1896_arg10); + setArg(call_vsxseg_1896, 12, 0); + setRet(call_vsxseg_1896, 0, ret_val_vsxseg_1896); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 455); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 456: VSUXSEG4EI64__V */ + continuation_e __vsuxseg4ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG4EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 456); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1898; + x86::Gp ret_val_get_pow_1898 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1898, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1899; + x86::Gp ret_val_get_sew_pow_1899 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1899, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1900; + x86::Gp ret_val_get_lmul_pow_1900 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1900, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1898, ret_val_get_sew_pow_1899), ret_val_get_lmul_pow_1900)), 3, true); + setArg(call_get_pow_1898, 0, reinterpret_cast(this)); + setArg(call_get_pow_1898, 1, EEW); + setRet(call_get_pow_1898, 0, ret_val_get_pow_1898); + setArg(call_get_sew_pow_1899, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1899, 0, ret_val_get_sew_pow_1899); + setArg(call_get_lmul_pow_1900, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1900, 0, ret_val_get_lmul_pow_1900); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1902; + x86::Gp ret_val_get_lmul_pow_1902 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1902, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1901; + auto illegal_indexed_store_1901_arg2 = EMUL_pow; + auto illegal_indexed_store_1901_arg3 = ret_val_get_lmul_pow_1902; + x86::Gp ret_val_illegal_indexed_store_1901 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1901, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1901; + setArg(call_get_lmul_pow_1902, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1902, 0, ret_val_get_lmul_pow_1902); + setArg(call_illegal_indexed_store_1901, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1901, 1, 4); + setArg(call_illegal_indexed_store_1901, 2, EEW); + setArg(call_illegal_indexed_store_1901, 3, illegal_indexed_store_1901_arg2); + setArg(call_illegal_indexed_store_1901, 4, illegal_indexed_store_1901_arg3); + setRet(call_illegal_indexed_store_1901, 0, ret_val_illegal_indexed_store_1901); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1904; + x86::Gp ret_val_sew_1904 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1904, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1903; + auto vsxseg_1903_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1903_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1903_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1903_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1903_arg10 = ret_val_sew_1904; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1903 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1903, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1903, 32, false), traits::vstart); + setArg(call_sew_1904, 0, reinterpret_cast(this)); + setRet(call_sew_1904, 0, ret_val_sew_1904); + setArg(call_vsxseg_1903, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1903, 1, V); + setArg(call_vsxseg_1903, 2, vsxseg_1903_arg1); + setArg(call_vsxseg_1903, 3, vsxseg_1903_arg2); + setArg(call_vsxseg_1903, 4, vsxseg_1903_arg3); + setArg(call_vsxseg_1903, 5, vm); + setArg(call_vsxseg_1903, 6, vs3); + setArg(call_vsxseg_1903, 7, vsxseg_1903_arg6); + setArg(call_vsxseg_1903, 8, vs2); + setArg(call_vsxseg_1903, 9, 4); + setArg(call_vsxseg_1903, 10, 8); + setArg(call_vsxseg_1903, 11, vsxseg_1903_arg10); + setArg(call_vsxseg_1903, 12, 0); + setRet(call_vsxseg_1903, 0, ret_val_vsxseg_1903); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 456); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 457: VSUXSEG5EI8__V */ + continuation_e __vsuxseg5ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG5EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 457); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1905; + x86::Gp ret_val_get_pow_1905 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1905, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1906; + x86::Gp ret_val_get_sew_pow_1906 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1906, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1907; + x86::Gp ret_val_get_lmul_pow_1907 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1907, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1905, ret_val_get_sew_pow_1906), ret_val_get_lmul_pow_1907)), 3, true); + setArg(call_get_pow_1905, 0, reinterpret_cast(this)); + setArg(call_get_pow_1905, 1, EEW); + setRet(call_get_pow_1905, 0, ret_val_get_pow_1905); + setArg(call_get_sew_pow_1906, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1906, 0, ret_val_get_sew_pow_1906); + setArg(call_get_lmul_pow_1907, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1907, 0, ret_val_get_lmul_pow_1907); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1909; + x86::Gp ret_val_get_lmul_pow_1909 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1909, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1908; + auto illegal_indexed_store_1908_arg2 = EMUL_pow; + auto illegal_indexed_store_1908_arg3 = ret_val_get_lmul_pow_1909; + x86::Gp ret_val_illegal_indexed_store_1908 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1908, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1908; + setArg(call_get_lmul_pow_1909, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1909, 0, ret_val_get_lmul_pow_1909); + setArg(call_illegal_indexed_store_1908, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1908, 1, 5); + setArg(call_illegal_indexed_store_1908, 2, EEW); + setArg(call_illegal_indexed_store_1908, 3, illegal_indexed_store_1908_arg2); + setArg(call_illegal_indexed_store_1908, 4, illegal_indexed_store_1908_arg3); + setRet(call_illegal_indexed_store_1908, 0, ret_val_illegal_indexed_store_1908); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1911; + x86::Gp ret_val_sew_1911 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1911, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1910; + auto vsxseg_1910_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1910_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1910_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1910_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1910_arg10 = ret_val_sew_1911; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1910 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1910, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1910, 32, false), traits::vstart); + setArg(call_sew_1911, 0, reinterpret_cast(this)); + setRet(call_sew_1911, 0, ret_val_sew_1911); + setArg(call_vsxseg_1910, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1910, 1, V); + setArg(call_vsxseg_1910, 2, vsxseg_1910_arg1); + setArg(call_vsxseg_1910, 3, vsxseg_1910_arg2); + setArg(call_vsxseg_1910, 4, vsxseg_1910_arg3); + setArg(call_vsxseg_1910, 5, vm); + setArg(call_vsxseg_1910, 6, vs3); + setArg(call_vsxseg_1910, 7, vsxseg_1910_arg6); + setArg(call_vsxseg_1910, 8, vs2); + setArg(call_vsxseg_1910, 9, 5); + setArg(call_vsxseg_1910, 10, 1); + setArg(call_vsxseg_1910, 11, vsxseg_1910_arg10); + setArg(call_vsxseg_1910, 12, 0); + setRet(call_vsxseg_1910, 0, ret_val_vsxseg_1910); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 457); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 458: VSUXSEG5EI16__V */ + continuation_e __vsuxseg5ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG5EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 458); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1912; + x86::Gp ret_val_get_pow_1912 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1912, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1913; + x86::Gp ret_val_get_sew_pow_1913 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1913, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1914; + x86::Gp ret_val_get_lmul_pow_1914 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1914, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1912, ret_val_get_sew_pow_1913), ret_val_get_lmul_pow_1914)), 3, true); + setArg(call_get_pow_1912, 0, reinterpret_cast(this)); + setArg(call_get_pow_1912, 1, EEW); + setRet(call_get_pow_1912, 0, ret_val_get_pow_1912); + setArg(call_get_sew_pow_1913, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1913, 0, ret_val_get_sew_pow_1913); + setArg(call_get_lmul_pow_1914, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1914, 0, ret_val_get_lmul_pow_1914); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1916; + x86::Gp ret_val_get_lmul_pow_1916 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1916, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1915; + auto illegal_indexed_store_1915_arg2 = EMUL_pow; + auto illegal_indexed_store_1915_arg3 = ret_val_get_lmul_pow_1916; + x86::Gp ret_val_illegal_indexed_store_1915 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1915, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1915; + setArg(call_get_lmul_pow_1916, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1916, 0, ret_val_get_lmul_pow_1916); + setArg(call_illegal_indexed_store_1915, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1915, 1, 5); + setArg(call_illegal_indexed_store_1915, 2, EEW); + setArg(call_illegal_indexed_store_1915, 3, illegal_indexed_store_1915_arg2); + setArg(call_illegal_indexed_store_1915, 4, illegal_indexed_store_1915_arg3); + setRet(call_illegal_indexed_store_1915, 0, ret_val_illegal_indexed_store_1915); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1918; + x86::Gp ret_val_sew_1918 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1918, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1917; + auto vsxseg_1917_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1917_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1917_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1917_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1917_arg10 = ret_val_sew_1918; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1917 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1917, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1917, 32, false), traits::vstart); + setArg(call_sew_1918, 0, reinterpret_cast(this)); + setRet(call_sew_1918, 0, ret_val_sew_1918); + setArg(call_vsxseg_1917, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1917, 1, V); + setArg(call_vsxseg_1917, 2, vsxseg_1917_arg1); + setArg(call_vsxseg_1917, 3, vsxseg_1917_arg2); + setArg(call_vsxseg_1917, 4, vsxseg_1917_arg3); + setArg(call_vsxseg_1917, 5, vm); + setArg(call_vsxseg_1917, 6, vs3); + setArg(call_vsxseg_1917, 7, vsxseg_1917_arg6); + setArg(call_vsxseg_1917, 8, vs2); + setArg(call_vsxseg_1917, 9, 5); + setArg(call_vsxseg_1917, 10, 2); + setArg(call_vsxseg_1917, 11, vsxseg_1917_arg10); + setArg(call_vsxseg_1917, 12, 0); + setRet(call_vsxseg_1917, 0, ret_val_vsxseg_1917); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 458); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 459: VSUXSEG5EI32__V */ + continuation_e __vsuxseg5ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG5EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 459); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1919; + x86::Gp ret_val_get_pow_1919 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1919, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1920; + x86::Gp ret_val_get_sew_pow_1920 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1920, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1921; + x86::Gp ret_val_get_lmul_pow_1921 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1921, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1919, ret_val_get_sew_pow_1920), ret_val_get_lmul_pow_1921)), 3, true); + setArg(call_get_pow_1919, 0, reinterpret_cast(this)); + setArg(call_get_pow_1919, 1, EEW); + setRet(call_get_pow_1919, 0, ret_val_get_pow_1919); + setArg(call_get_sew_pow_1920, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1920, 0, ret_val_get_sew_pow_1920); + setArg(call_get_lmul_pow_1921, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1921, 0, ret_val_get_lmul_pow_1921); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1923; + x86::Gp ret_val_get_lmul_pow_1923 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1923, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1922; + auto illegal_indexed_store_1922_arg2 = EMUL_pow; + auto illegal_indexed_store_1922_arg3 = ret_val_get_lmul_pow_1923; + x86::Gp ret_val_illegal_indexed_store_1922 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1922, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1922; + setArg(call_get_lmul_pow_1923, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1923, 0, ret_val_get_lmul_pow_1923); + setArg(call_illegal_indexed_store_1922, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1922, 1, 5); + setArg(call_illegal_indexed_store_1922, 2, EEW); + setArg(call_illegal_indexed_store_1922, 3, illegal_indexed_store_1922_arg2); + setArg(call_illegal_indexed_store_1922, 4, illegal_indexed_store_1922_arg3); + setRet(call_illegal_indexed_store_1922, 0, ret_val_illegal_indexed_store_1922); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1925; + x86::Gp ret_val_sew_1925 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1925, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1924; + auto vsxseg_1924_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1924_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1924_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1924_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1924_arg10 = ret_val_sew_1925; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1924 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1924, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1924, 32, false), traits::vstart); + setArg(call_sew_1925, 0, reinterpret_cast(this)); + setRet(call_sew_1925, 0, ret_val_sew_1925); + setArg(call_vsxseg_1924, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1924, 1, V); + setArg(call_vsxseg_1924, 2, vsxseg_1924_arg1); + setArg(call_vsxseg_1924, 3, vsxseg_1924_arg2); + setArg(call_vsxseg_1924, 4, vsxseg_1924_arg3); + setArg(call_vsxseg_1924, 5, vm); + setArg(call_vsxseg_1924, 6, vs3); + setArg(call_vsxseg_1924, 7, vsxseg_1924_arg6); + setArg(call_vsxseg_1924, 8, vs2); + setArg(call_vsxseg_1924, 9, 5); + setArg(call_vsxseg_1924, 10, 4); + setArg(call_vsxseg_1924, 11, vsxseg_1924_arg10); + setArg(call_vsxseg_1924, 12, 0); + setRet(call_vsxseg_1924, 0, ret_val_vsxseg_1924); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 459); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 460: VSUXSEG5EI64__V */ + continuation_e __vsuxseg5ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG5EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 460); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1926; + x86::Gp ret_val_get_pow_1926 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1926, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1927; + x86::Gp ret_val_get_sew_pow_1927 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1927, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1928; + x86::Gp ret_val_get_lmul_pow_1928 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1928, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1926, ret_val_get_sew_pow_1927), ret_val_get_lmul_pow_1928)), 3, true); + setArg(call_get_pow_1926, 0, reinterpret_cast(this)); + setArg(call_get_pow_1926, 1, EEW); + setRet(call_get_pow_1926, 0, ret_val_get_pow_1926); + setArg(call_get_sew_pow_1927, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1927, 0, ret_val_get_sew_pow_1927); + setArg(call_get_lmul_pow_1928, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1928, 0, ret_val_get_lmul_pow_1928); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1930; + x86::Gp ret_val_get_lmul_pow_1930 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1930, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1929; + auto illegal_indexed_store_1929_arg2 = EMUL_pow; + auto illegal_indexed_store_1929_arg3 = ret_val_get_lmul_pow_1930; + x86::Gp ret_val_illegal_indexed_store_1929 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1929, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1929; + setArg(call_get_lmul_pow_1930, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1930, 0, ret_val_get_lmul_pow_1930); + setArg(call_illegal_indexed_store_1929, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1929, 1, 5); + setArg(call_illegal_indexed_store_1929, 2, EEW); + setArg(call_illegal_indexed_store_1929, 3, illegal_indexed_store_1929_arg2); + setArg(call_illegal_indexed_store_1929, 4, illegal_indexed_store_1929_arg3); + setRet(call_illegal_indexed_store_1929, 0, ret_val_illegal_indexed_store_1929); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1932; + x86::Gp ret_val_sew_1932 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1932, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1931; + auto vsxseg_1931_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1931_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1931_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1931_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1931_arg10 = ret_val_sew_1932; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1931 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1931, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1931, 32, false), traits::vstart); + setArg(call_sew_1932, 0, reinterpret_cast(this)); + setRet(call_sew_1932, 0, ret_val_sew_1932); + setArg(call_vsxseg_1931, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1931, 1, V); + setArg(call_vsxseg_1931, 2, vsxseg_1931_arg1); + setArg(call_vsxseg_1931, 3, vsxseg_1931_arg2); + setArg(call_vsxseg_1931, 4, vsxseg_1931_arg3); + setArg(call_vsxseg_1931, 5, vm); + setArg(call_vsxseg_1931, 6, vs3); + setArg(call_vsxseg_1931, 7, vsxseg_1931_arg6); + setArg(call_vsxseg_1931, 8, vs2); + setArg(call_vsxseg_1931, 9, 5); + setArg(call_vsxseg_1931, 10, 8); + setArg(call_vsxseg_1931, 11, vsxseg_1931_arg10); + setArg(call_vsxseg_1931, 12, 0); + setRet(call_vsxseg_1931, 0, ret_val_vsxseg_1931); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 460); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 461: VSUXSEG6EI8__V */ + continuation_e __vsuxseg6ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG6EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 461); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1933; + x86::Gp ret_val_get_pow_1933 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1933, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1934; + x86::Gp ret_val_get_sew_pow_1934 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1934, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1935; + x86::Gp ret_val_get_lmul_pow_1935 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1935, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1933, ret_val_get_sew_pow_1934), ret_val_get_lmul_pow_1935)), 3, true); + setArg(call_get_pow_1933, 0, reinterpret_cast(this)); + setArg(call_get_pow_1933, 1, EEW); + setRet(call_get_pow_1933, 0, ret_val_get_pow_1933); + setArg(call_get_sew_pow_1934, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1934, 0, ret_val_get_sew_pow_1934); + setArg(call_get_lmul_pow_1935, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1935, 0, ret_val_get_lmul_pow_1935); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1937; + x86::Gp ret_val_get_lmul_pow_1937 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1937, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1936; + auto illegal_indexed_store_1936_arg2 = EMUL_pow; + auto illegal_indexed_store_1936_arg3 = ret_val_get_lmul_pow_1937; + x86::Gp ret_val_illegal_indexed_store_1936 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1936, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1936; + setArg(call_get_lmul_pow_1937, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1937, 0, ret_val_get_lmul_pow_1937); + setArg(call_illegal_indexed_store_1936, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1936, 1, 6); + setArg(call_illegal_indexed_store_1936, 2, EEW); + setArg(call_illegal_indexed_store_1936, 3, illegal_indexed_store_1936_arg2); + setArg(call_illegal_indexed_store_1936, 4, illegal_indexed_store_1936_arg3); + setRet(call_illegal_indexed_store_1936, 0, ret_val_illegal_indexed_store_1936); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1939; + x86::Gp ret_val_sew_1939 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1939, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1938; + auto vsxseg_1938_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1938_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1938_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1938_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1938_arg10 = ret_val_sew_1939; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1938 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1938, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1938, 32, false), traits::vstart); + setArg(call_sew_1939, 0, reinterpret_cast(this)); + setRet(call_sew_1939, 0, ret_val_sew_1939); + setArg(call_vsxseg_1938, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1938, 1, V); + setArg(call_vsxseg_1938, 2, vsxseg_1938_arg1); + setArg(call_vsxseg_1938, 3, vsxseg_1938_arg2); + setArg(call_vsxseg_1938, 4, vsxseg_1938_arg3); + setArg(call_vsxseg_1938, 5, vm); + setArg(call_vsxseg_1938, 6, vs3); + setArg(call_vsxseg_1938, 7, vsxseg_1938_arg6); + setArg(call_vsxseg_1938, 8, vs2); + setArg(call_vsxseg_1938, 9, 6); + setArg(call_vsxseg_1938, 10, 1); + setArg(call_vsxseg_1938, 11, vsxseg_1938_arg10); + setArg(call_vsxseg_1938, 12, 0); + setRet(call_vsxseg_1938, 0, ret_val_vsxseg_1938); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 461); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 462: VSUXSEG6EI16__V */ + continuation_e __vsuxseg6ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG6EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 462); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1940; + x86::Gp ret_val_get_pow_1940 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1940, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1941; + x86::Gp ret_val_get_sew_pow_1941 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1941, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1942; + x86::Gp ret_val_get_lmul_pow_1942 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1942, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1940, ret_val_get_sew_pow_1941), ret_val_get_lmul_pow_1942)), 3, true); + setArg(call_get_pow_1940, 0, reinterpret_cast(this)); + setArg(call_get_pow_1940, 1, EEW); + setRet(call_get_pow_1940, 0, ret_val_get_pow_1940); + setArg(call_get_sew_pow_1941, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1941, 0, ret_val_get_sew_pow_1941); + setArg(call_get_lmul_pow_1942, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1942, 0, ret_val_get_lmul_pow_1942); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1944; + x86::Gp ret_val_get_lmul_pow_1944 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1944, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1943; + auto illegal_indexed_store_1943_arg2 = EMUL_pow; + auto illegal_indexed_store_1943_arg3 = ret_val_get_lmul_pow_1944; + x86::Gp ret_val_illegal_indexed_store_1943 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1943, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1943; + setArg(call_get_lmul_pow_1944, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1944, 0, ret_val_get_lmul_pow_1944); + setArg(call_illegal_indexed_store_1943, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1943, 1, 6); + setArg(call_illegal_indexed_store_1943, 2, EEW); + setArg(call_illegal_indexed_store_1943, 3, illegal_indexed_store_1943_arg2); + setArg(call_illegal_indexed_store_1943, 4, illegal_indexed_store_1943_arg3); + setRet(call_illegal_indexed_store_1943, 0, ret_val_illegal_indexed_store_1943); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1946; + x86::Gp ret_val_sew_1946 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1946, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1945; + auto vsxseg_1945_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1945_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1945_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1945_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1945_arg10 = ret_val_sew_1946; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1945 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1945, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1945, 32, false), traits::vstart); + setArg(call_sew_1946, 0, reinterpret_cast(this)); + setRet(call_sew_1946, 0, ret_val_sew_1946); + setArg(call_vsxseg_1945, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1945, 1, V); + setArg(call_vsxseg_1945, 2, vsxseg_1945_arg1); + setArg(call_vsxseg_1945, 3, vsxseg_1945_arg2); + setArg(call_vsxseg_1945, 4, vsxseg_1945_arg3); + setArg(call_vsxseg_1945, 5, vm); + setArg(call_vsxseg_1945, 6, vs3); + setArg(call_vsxseg_1945, 7, vsxseg_1945_arg6); + setArg(call_vsxseg_1945, 8, vs2); + setArg(call_vsxseg_1945, 9, 6); + setArg(call_vsxseg_1945, 10, 2); + setArg(call_vsxseg_1945, 11, vsxseg_1945_arg10); + setArg(call_vsxseg_1945, 12, 0); + setRet(call_vsxseg_1945, 0, ret_val_vsxseg_1945); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 462); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 463: VSUXSEG6EI32__V */ + continuation_e __vsuxseg6ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG6EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 463); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1947; + x86::Gp ret_val_get_pow_1947 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1947, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1948; + x86::Gp ret_val_get_sew_pow_1948 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1948, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1949; + x86::Gp ret_val_get_lmul_pow_1949 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1949, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1947, ret_val_get_sew_pow_1948), ret_val_get_lmul_pow_1949)), 3, true); + setArg(call_get_pow_1947, 0, reinterpret_cast(this)); + setArg(call_get_pow_1947, 1, EEW); + setRet(call_get_pow_1947, 0, ret_val_get_pow_1947); + setArg(call_get_sew_pow_1948, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1948, 0, ret_val_get_sew_pow_1948); + setArg(call_get_lmul_pow_1949, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1949, 0, ret_val_get_lmul_pow_1949); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1951; + x86::Gp ret_val_get_lmul_pow_1951 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1951, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1950; + auto illegal_indexed_store_1950_arg2 = EMUL_pow; + auto illegal_indexed_store_1950_arg3 = ret_val_get_lmul_pow_1951; + x86::Gp ret_val_illegal_indexed_store_1950 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1950, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1950; + setArg(call_get_lmul_pow_1951, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1951, 0, ret_val_get_lmul_pow_1951); + setArg(call_illegal_indexed_store_1950, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1950, 1, 6); + setArg(call_illegal_indexed_store_1950, 2, EEW); + setArg(call_illegal_indexed_store_1950, 3, illegal_indexed_store_1950_arg2); + setArg(call_illegal_indexed_store_1950, 4, illegal_indexed_store_1950_arg3); + setRet(call_illegal_indexed_store_1950, 0, ret_val_illegal_indexed_store_1950); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1953; + x86::Gp ret_val_sew_1953 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1953, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1952; + auto vsxseg_1952_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1952_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1952_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1952_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1952_arg10 = ret_val_sew_1953; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1952 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1952, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1952, 32, false), traits::vstart); + setArg(call_sew_1953, 0, reinterpret_cast(this)); + setRet(call_sew_1953, 0, ret_val_sew_1953); + setArg(call_vsxseg_1952, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1952, 1, V); + setArg(call_vsxseg_1952, 2, vsxseg_1952_arg1); + setArg(call_vsxseg_1952, 3, vsxseg_1952_arg2); + setArg(call_vsxseg_1952, 4, vsxseg_1952_arg3); + setArg(call_vsxseg_1952, 5, vm); + setArg(call_vsxseg_1952, 6, vs3); + setArg(call_vsxseg_1952, 7, vsxseg_1952_arg6); + setArg(call_vsxseg_1952, 8, vs2); + setArg(call_vsxseg_1952, 9, 6); + setArg(call_vsxseg_1952, 10, 4); + setArg(call_vsxseg_1952, 11, vsxseg_1952_arg10); + setArg(call_vsxseg_1952, 12, 0); + setRet(call_vsxseg_1952, 0, ret_val_vsxseg_1952); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 463); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 464: VSUXSEG6EI64__V */ + continuation_e __vsuxseg6ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG6EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 464); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1954; + x86::Gp ret_val_get_pow_1954 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1954, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1955; + x86::Gp ret_val_get_sew_pow_1955 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1955, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1956; + x86::Gp ret_val_get_lmul_pow_1956 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1956, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1954, ret_val_get_sew_pow_1955), ret_val_get_lmul_pow_1956)), 3, true); + setArg(call_get_pow_1954, 0, reinterpret_cast(this)); + setArg(call_get_pow_1954, 1, EEW); + setRet(call_get_pow_1954, 0, ret_val_get_pow_1954); + setArg(call_get_sew_pow_1955, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1955, 0, ret_val_get_sew_pow_1955); + setArg(call_get_lmul_pow_1956, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1956, 0, ret_val_get_lmul_pow_1956); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1958; + x86::Gp ret_val_get_lmul_pow_1958 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1958, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1957; + auto illegal_indexed_store_1957_arg2 = EMUL_pow; + auto illegal_indexed_store_1957_arg3 = ret_val_get_lmul_pow_1958; + x86::Gp ret_val_illegal_indexed_store_1957 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1957, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1957; + setArg(call_get_lmul_pow_1958, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1958, 0, ret_val_get_lmul_pow_1958); + setArg(call_illegal_indexed_store_1957, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1957, 1, 6); + setArg(call_illegal_indexed_store_1957, 2, EEW); + setArg(call_illegal_indexed_store_1957, 3, illegal_indexed_store_1957_arg2); + setArg(call_illegal_indexed_store_1957, 4, illegal_indexed_store_1957_arg3); + setRet(call_illegal_indexed_store_1957, 0, ret_val_illegal_indexed_store_1957); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1960; + x86::Gp ret_val_sew_1960 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1960, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1959; + auto vsxseg_1959_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1959_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1959_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1959_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1959_arg10 = ret_val_sew_1960; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1959 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1959, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1959, 32, false), traits::vstart); + setArg(call_sew_1960, 0, reinterpret_cast(this)); + setRet(call_sew_1960, 0, ret_val_sew_1960); + setArg(call_vsxseg_1959, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1959, 1, V); + setArg(call_vsxseg_1959, 2, vsxseg_1959_arg1); + setArg(call_vsxseg_1959, 3, vsxseg_1959_arg2); + setArg(call_vsxseg_1959, 4, vsxseg_1959_arg3); + setArg(call_vsxseg_1959, 5, vm); + setArg(call_vsxseg_1959, 6, vs3); + setArg(call_vsxseg_1959, 7, vsxseg_1959_arg6); + setArg(call_vsxseg_1959, 8, vs2); + setArg(call_vsxseg_1959, 9, 6); + setArg(call_vsxseg_1959, 10, 8); + setArg(call_vsxseg_1959, 11, vsxseg_1959_arg10); + setArg(call_vsxseg_1959, 12, 0); + setRet(call_vsxseg_1959, 0, ret_val_vsxseg_1959); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 464); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 465: VSUXSEG7EI8__V */ + continuation_e __vsuxseg7ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG7EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 465); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1961; + x86::Gp ret_val_get_pow_1961 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1961, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1962; + x86::Gp ret_val_get_sew_pow_1962 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1962, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1963; + x86::Gp ret_val_get_lmul_pow_1963 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1963, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1961, ret_val_get_sew_pow_1962), ret_val_get_lmul_pow_1963)), 3, true); + setArg(call_get_pow_1961, 0, reinterpret_cast(this)); + setArg(call_get_pow_1961, 1, EEW); + setRet(call_get_pow_1961, 0, ret_val_get_pow_1961); + setArg(call_get_sew_pow_1962, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1962, 0, ret_val_get_sew_pow_1962); + setArg(call_get_lmul_pow_1963, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1963, 0, ret_val_get_lmul_pow_1963); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1965; + x86::Gp ret_val_get_lmul_pow_1965 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1965, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1964; + auto illegal_indexed_store_1964_arg2 = EMUL_pow; + auto illegal_indexed_store_1964_arg3 = ret_val_get_lmul_pow_1965; + x86::Gp ret_val_illegal_indexed_store_1964 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1964, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1964; + setArg(call_get_lmul_pow_1965, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1965, 0, ret_val_get_lmul_pow_1965); + setArg(call_illegal_indexed_store_1964, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1964, 1, 7); + setArg(call_illegal_indexed_store_1964, 2, EEW); + setArg(call_illegal_indexed_store_1964, 3, illegal_indexed_store_1964_arg2); + setArg(call_illegal_indexed_store_1964, 4, illegal_indexed_store_1964_arg3); + setRet(call_illegal_indexed_store_1964, 0, ret_val_illegal_indexed_store_1964); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1967; + x86::Gp ret_val_sew_1967 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1967, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1966; + auto vsxseg_1966_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1966_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1966_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1966_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1966_arg10 = ret_val_sew_1967; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1966 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1966, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1966, 32, false), traits::vstart); + setArg(call_sew_1967, 0, reinterpret_cast(this)); + setRet(call_sew_1967, 0, ret_val_sew_1967); + setArg(call_vsxseg_1966, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1966, 1, V); + setArg(call_vsxseg_1966, 2, vsxseg_1966_arg1); + setArg(call_vsxseg_1966, 3, vsxseg_1966_arg2); + setArg(call_vsxseg_1966, 4, vsxseg_1966_arg3); + setArg(call_vsxseg_1966, 5, vm); + setArg(call_vsxseg_1966, 6, vs3); + setArg(call_vsxseg_1966, 7, vsxseg_1966_arg6); + setArg(call_vsxseg_1966, 8, vs2); + setArg(call_vsxseg_1966, 9, 7); + setArg(call_vsxseg_1966, 10, 1); + setArg(call_vsxseg_1966, 11, vsxseg_1966_arg10); + setArg(call_vsxseg_1966, 12, 0); + setRet(call_vsxseg_1966, 0, ret_val_vsxseg_1966); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 465); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 466: VSUXSEG7EI16__V */ + continuation_e __vsuxseg7ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG7EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 466); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1968; + x86::Gp ret_val_get_pow_1968 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1968, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1969; + x86::Gp ret_val_get_sew_pow_1969 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1969, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1970; + x86::Gp ret_val_get_lmul_pow_1970 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1970, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1968, ret_val_get_sew_pow_1969), ret_val_get_lmul_pow_1970)), 3, true); + setArg(call_get_pow_1968, 0, reinterpret_cast(this)); + setArg(call_get_pow_1968, 1, EEW); + setRet(call_get_pow_1968, 0, ret_val_get_pow_1968); + setArg(call_get_sew_pow_1969, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1969, 0, ret_val_get_sew_pow_1969); + setArg(call_get_lmul_pow_1970, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1970, 0, ret_val_get_lmul_pow_1970); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1972; + x86::Gp ret_val_get_lmul_pow_1972 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1972, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1971; + auto illegal_indexed_store_1971_arg2 = EMUL_pow; + auto illegal_indexed_store_1971_arg3 = ret_val_get_lmul_pow_1972; + x86::Gp ret_val_illegal_indexed_store_1971 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1971, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1971; + setArg(call_get_lmul_pow_1972, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1972, 0, ret_val_get_lmul_pow_1972); + setArg(call_illegal_indexed_store_1971, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1971, 1, 7); + setArg(call_illegal_indexed_store_1971, 2, EEW); + setArg(call_illegal_indexed_store_1971, 3, illegal_indexed_store_1971_arg2); + setArg(call_illegal_indexed_store_1971, 4, illegal_indexed_store_1971_arg3); + setRet(call_illegal_indexed_store_1971, 0, ret_val_illegal_indexed_store_1971); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1974; + x86::Gp ret_val_sew_1974 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1974, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1973; + auto vsxseg_1973_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1973_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1973_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1973_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1973_arg10 = ret_val_sew_1974; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1973 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1973, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1973, 32, false), traits::vstart); + setArg(call_sew_1974, 0, reinterpret_cast(this)); + setRet(call_sew_1974, 0, ret_val_sew_1974); + setArg(call_vsxseg_1973, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1973, 1, V); + setArg(call_vsxseg_1973, 2, vsxseg_1973_arg1); + setArg(call_vsxseg_1973, 3, vsxseg_1973_arg2); + setArg(call_vsxseg_1973, 4, vsxseg_1973_arg3); + setArg(call_vsxseg_1973, 5, vm); + setArg(call_vsxseg_1973, 6, vs3); + setArg(call_vsxseg_1973, 7, vsxseg_1973_arg6); + setArg(call_vsxseg_1973, 8, vs2); + setArg(call_vsxseg_1973, 9, 7); + setArg(call_vsxseg_1973, 10, 2); + setArg(call_vsxseg_1973, 11, vsxseg_1973_arg10); + setArg(call_vsxseg_1973, 12, 0); + setRet(call_vsxseg_1973, 0, ret_val_vsxseg_1973); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 466); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 467: VSUXSEG7EI32__V */ + continuation_e __vsuxseg7ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG7EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 467); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1975; + x86::Gp ret_val_get_pow_1975 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1975, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1976; + x86::Gp ret_val_get_sew_pow_1976 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1976, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1977; + x86::Gp ret_val_get_lmul_pow_1977 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1977, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1975, ret_val_get_sew_pow_1976), ret_val_get_lmul_pow_1977)), 3, true); + setArg(call_get_pow_1975, 0, reinterpret_cast(this)); + setArg(call_get_pow_1975, 1, EEW); + setRet(call_get_pow_1975, 0, ret_val_get_pow_1975); + setArg(call_get_sew_pow_1976, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1976, 0, ret_val_get_sew_pow_1976); + setArg(call_get_lmul_pow_1977, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1977, 0, ret_val_get_lmul_pow_1977); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1979; + x86::Gp ret_val_get_lmul_pow_1979 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1979, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1978; + auto illegal_indexed_store_1978_arg2 = EMUL_pow; + auto illegal_indexed_store_1978_arg3 = ret_val_get_lmul_pow_1979; + x86::Gp ret_val_illegal_indexed_store_1978 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1978, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1978; + setArg(call_get_lmul_pow_1979, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1979, 0, ret_val_get_lmul_pow_1979); + setArg(call_illegal_indexed_store_1978, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1978, 1, 7); + setArg(call_illegal_indexed_store_1978, 2, EEW); + setArg(call_illegal_indexed_store_1978, 3, illegal_indexed_store_1978_arg2); + setArg(call_illegal_indexed_store_1978, 4, illegal_indexed_store_1978_arg3); + setRet(call_illegal_indexed_store_1978, 0, ret_val_illegal_indexed_store_1978); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1981; + x86::Gp ret_val_sew_1981 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1981, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1980; + auto vsxseg_1980_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1980_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1980_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1980_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1980_arg10 = ret_val_sew_1981; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1980 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1980, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1980, 32, false), traits::vstart); + setArg(call_sew_1981, 0, reinterpret_cast(this)); + setRet(call_sew_1981, 0, ret_val_sew_1981); + setArg(call_vsxseg_1980, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1980, 1, V); + setArg(call_vsxseg_1980, 2, vsxseg_1980_arg1); + setArg(call_vsxseg_1980, 3, vsxseg_1980_arg2); + setArg(call_vsxseg_1980, 4, vsxseg_1980_arg3); + setArg(call_vsxseg_1980, 5, vm); + setArg(call_vsxseg_1980, 6, vs3); + setArg(call_vsxseg_1980, 7, vsxseg_1980_arg6); + setArg(call_vsxseg_1980, 8, vs2); + setArg(call_vsxseg_1980, 9, 7); + setArg(call_vsxseg_1980, 10, 4); + setArg(call_vsxseg_1980, 11, vsxseg_1980_arg10); + setArg(call_vsxseg_1980, 12, 0); + setRet(call_vsxseg_1980, 0, ret_val_vsxseg_1980); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 467); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 468: VSUXSEG7EI64__V */ + continuation_e __vsuxseg7ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG7EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 468); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1982; + x86::Gp ret_val_get_pow_1982 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1982, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1983; + x86::Gp ret_val_get_sew_pow_1983 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1983, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1984; + x86::Gp ret_val_get_lmul_pow_1984 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1984, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1982, ret_val_get_sew_pow_1983), ret_val_get_lmul_pow_1984)), 3, true); + setArg(call_get_pow_1982, 0, reinterpret_cast(this)); + setArg(call_get_pow_1982, 1, EEW); + setRet(call_get_pow_1982, 0, ret_val_get_pow_1982); + setArg(call_get_sew_pow_1983, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1983, 0, ret_val_get_sew_pow_1983); + setArg(call_get_lmul_pow_1984, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1984, 0, ret_val_get_lmul_pow_1984); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1986; + x86::Gp ret_val_get_lmul_pow_1986 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1986, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1985; + auto illegal_indexed_store_1985_arg2 = EMUL_pow; + auto illegal_indexed_store_1985_arg3 = ret_val_get_lmul_pow_1986; + x86::Gp ret_val_illegal_indexed_store_1985 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1985, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1985; + setArg(call_get_lmul_pow_1986, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1986, 0, ret_val_get_lmul_pow_1986); + setArg(call_illegal_indexed_store_1985, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1985, 1, 7); + setArg(call_illegal_indexed_store_1985, 2, EEW); + setArg(call_illegal_indexed_store_1985, 3, illegal_indexed_store_1985_arg2); + setArg(call_illegal_indexed_store_1985, 4, illegal_indexed_store_1985_arg3); + setRet(call_illegal_indexed_store_1985, 0, ret_val_illegal_indexed_store_1985); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1988; + x86::Gp ret_val_sew_1988 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1988, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1987; + auto vsxseg_1987_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1987_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1987_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1987_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1987_arg10 = ret_val_sew_1988; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1987 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1987, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1987, 32, false), traits::vstart); + setArg(call_sew_1988, 0, reinterpret_cast(this)); + setRet(call_sew_1988, 0, ret_val_sew_1988); + setArg(call_vsxseg_1987, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1987, 1, V); + setArg(call_vsxseg_1987, 2, vsxseg_1987_arg1); + setArg(call_vsxseg_1987, 3, vsxseg_1987_arg2); + setArg(call_vsxseg_1987, 4, vsxseg_1987_arg3); + setArg(call_vsxseg_1987, 5, vm); + setArg(call_vsxseg_1987, 6, vs3); + setArg(call_vsxseg_1987, 7, vsxseg_1987_arg6); + setArg(call_vsxseg_1987, 8, vs2); + setArg(call_vsxseg_1987, 9, 7); + setArg(call_vsxseg_1987, 10, 8); + setArg(call_vsxseg_1987, 11, vsxseg_1987_arg10); + setArg(call_vsxseg_1987, 12, 0); + setRet(call_vsxseg_1987, 0, ret_val_vsxseg_1987); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 468); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 469: VSUXSEG8EI8__V */ + continuation_e __vsuxseg8ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG8EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 469); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1989; + x86::Gp ret_val_get_pow_1989 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1989, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1990; + x86::Gp ret_val_get_sew_pow_1990 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1990, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1991; + x86::Gp ret_val_get_lmul_pow_1991 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1991, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1989, ret_val_get_sew_pow_1990), ret_val_get_lmul_pow_1991)), 3, true); + setArg(call_get_pow_1989, 0, reinterpret_cast(this)); + setArg(call_get_pow_1989, 1, EEW); + setRet(call_get_pow_1989, 0, ret_val_get_pow_1989); + setArg(call_get_sew_pow_1990, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1990, 0, ret_val_get_sew_pow_1990); + setArg(call_get_lmul_pow_1991, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1991, 0, ret_val_get_lmul_pow_1991); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1993; + x86::Gp ret_val_get_lmul_pow_1993 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1993, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1992; + auto illegal_indexed_store_1992_arg2 = EMUL_pow; + auto illegal_indexed_store_1992_arg3 = ret_val_get_lmul_pow_1993; + x86::Gp ret_val_illegal_indexed_store_1992 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1992, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1992; + setArg(call_get_lmul_pow_1993, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1993, 0, ret_val_get_lmul_pow_1993); + setArg(call_illegal_indexed_store_1992, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1992, 1, 8); + setArg(call_illegal_indexed_store_1992, 2, EEW); + setArg(call_illegal_indexed_store_1992, 3, illegal_indexed_store_1992_arg2); + setArg(call_illegal_indexed_store_1992, 4, illegal_indexed_store_1992_arg3); + setRet(call_illegal_indexed_store_1992, 0, ret_val_illegal_indexed_store_1992); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1995; + x86::Gp ret_val_sew_1995 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1995, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1994; + auto vsxseg_1994_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1994_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1994_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1994_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1994_arg10 = ret_val_sew_1995; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1994 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1994, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1994, 32, false), traits::vstart); + setArg(call_sew_1995, 0, reinterpret_cast(this)); + setRet(call_sew_1995, 0, ret_val_sew_1995); + setArg(call_vsxseg_1994, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1994, 1, V); + setArg(call_vsxseg_1994, 2, vsxseg_1994_arg1); + setArg(call_vsxseg_1994, 3, vsxseg_1994_arg2); + setArg(call_vsxseg_1994, 4, vsxseg_1994_arg3); + setArg(call_vsxseg_1994, 5, vm); + setArg(call_vsxseg_1994, 6, vs3); + setArg(call_vsxseg_1994, 7, vsxseg_1994_arg6); + setArg(call_vsxseg_1994, 8, vs2); + setArg(call_vsxseg_1994, 9, 8); + setArg(call_vsxseg_1994, 10, 1); + setArg(call_vsxseg_1994, 11, vsxseg_1994_arg10); + setArg(call_vsxseg_1994, 12, 0); + setRet(call_vsxseg_1994, 0, ret_val_vsxseg_1994); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 469); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 470: VSUXSEG8EI16__V */ + continuation_e __vsuxseg8ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG8EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 470); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1996; + x86::Gp ret_val_get_pow_1996 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1996, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1997; + x86::Gp ret_val_get_sew_pow_1997 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1997, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1998; + x86::Gp ret_val_get_lmul_pow_1998 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1998, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1996, ret_val_get_sew_pow_1997), ret_val_get_lmul_pow_1998)), 3, true); + setArg(call_get_pow_1996, 0, reinterpret_cast(this)); + setArg(call_get_pow_1996, 1, EEW); + setRet(call_get_pow_1996, 0, ret_val_get_pow_1996); + setArg(call_get_sew_pow_1997, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1997, 0, ret_val_get_sew_pow_1997); + setArg(call_get_lmul_pow_1998, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1998, 0, ret_val_get_lmul_pow_1998); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2000; + x86::Gp ret_val_get_lmul_pow_2000 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2000, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1999; + auto illegal_indexed_store_1999_arg2 = EMUL_pow; + auto illegal_indexed_store_1999_arg3 = ret_val_get_lmul_pow_2000; + x86::Gp ret_val_illegal_indexed_store_1999 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1999, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1999; + setArg(call_get_lmul_pow_2000, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2000, 0, ret_val_get_lmul_pow_2000); + setArg(call_illegal_indexed_store_1999, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1999, 1, 8); + setArg(call_illegal_indexed_store_1999, 2, EEW); + setArg(call_illegal_indexed_store_1999, 3, illegal_indexed_store_1999_arg2); + setArg(call_illegal_indexed_store_1999, 4, illegal_indexed_store_1999_arg3); + setRet(call_illegal_indexed_store_1999, 0, ret_val_illegal_indexed_store_1999); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2002; + x86::Gp ret_val_sew_2002 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2002, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2001; + auto vsxseg_2001_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2001_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2001_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2001_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2001_arg10 = ret_val_sew_2002; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2001 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2001, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2001, 32, false), traits::vstart); + setArg(call_sew_2002, 0, reinterpret_cast(this)); + setRet(call_sew_2002, 0, ret_val_sew_2002); + setArg(call_vsxseg_2001, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2001, 1, V); + setArg(call_vsxseg_2001, 2, vsxseg_2001_arg1); + setArg(call_vsxseg_2001, 3, vsxseg_2001_arg2); + setArg(call_vsxseg_2001, 4, vsxseg_2001_arg3); + setArg(call_vsxseg_2001, 5, vm); + setArg(call_vsxseg_2001, 6, vs3); + setArg(call_vsxseg_2001, 7, vsxseg_2001_arg6); + setArg(call_vsxseg_2001, 8, vs2); + setArg(call_vsxseg_2001, 9, 8); + setArg(call_vsxseg_2001, 10, 2); + setArg(call_vsxseg_2001, 11, vsxseg_2001_arg10); + setArg(call_vsxseg_2001, 12, 0); + setRet(call_vsxseg_2001, 0, ret_val_vsxseg_2001); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 470); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 471: VSUXSEG8EI32__V */ + continuation_e __vsuxseg8ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG8EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 471); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_2003; + x86::Gp ret_val_get_pow_2003 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_2003, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_2004; + x86::Gp ret_val_get_sew_pow_2004 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2004, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_2005; + x86::Gp ret_val_get_lmul_pow_2005 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2005, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2003, ret_val_get_sew_pow_2004), ret_val_get_lmul_pow_2005)), 3, true); + setArg(call_get_pow_2003, 0, reinterpret_cast(this)); + setArg(call_get_pow_2003, 1, EEW); + setRet(call_get_pow_2003, 0, ret_val_get_pow_2003); + setArg(call_get_sew_pow_2004, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2004, 0, ret_val_get_sew_pow_2004); + setArg(call_get_lmul_pow_2005, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2005, 0, ret_val_get_lmul_pow_2005); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2007; + x86::Gp ret_val_get_lmul_pow_2007 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2007, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_2006; + auto illegal_indexed_store_2006_arg2 = EMUL_pow; + auto illegal_indexed_store_2006_arg3 = ret_val_get_lmul_pow_2007; + x86::Gp ret_val_illegal_indexed_store_2006 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_2006, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_2006; + setArg(call_get_lmul_pow_2007, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2007, 0, ret_val_get_lmul_pow_2007); + setArg(call_illegal_indexed_store_2006, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_2006, 1, 8); + setArg(call_illegal_indexed_store_2006, 2, EEW); + setArg(call_illegal_indexed_store_2006, 3, illegal_indexed_store_2006_arg2); + setArg(call_illegal_indexed_store_2006, 4, illegal_indexed_store_2006_arg3); + setRet(call_illegal_indexed_store_2006, 0, ret_val_illegal_indexed_store_2006); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2009; + x86::Gp ret_val_sew_2009 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2009, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2008; + auto vsxseg_2008_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2008_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2008_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2008_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2008_arg10 = ret_val_sew_2009; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2008 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2008, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2008, 32, false), traits::vstart); + setArg(call_sew_2009, 0, reinterpret_cast(this)); + setRet(call_sew_2009, 0, ret_val_sew_2009); + setArg(call_vsxseg_2008, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2008, 1, V); + setArg(call_vsxseg_2008, 2, vsxseg_2008_arg1); + setArg(call_vsxseg_2008, 3, vsxseg_2008_arg2); + setArg(call_vsxseg_2008, 4, vsxseg_2008_arg3); + setArg(call_vsxseg_2008, 5, vm); + setArg(call_vsxseg_2008, 6, vs3); + setArg(call_vsxseg_2008, 7, vsxseg_2008_arg6); + setArg(call_vsxseg_2008, 8, vs2); + setArg(call_vsxseg_2008, 9, 8); + setArg(call_vsxseg_2008, 10, 4); + setArg(call_vsxseg_2008, 11, vsxseg_2008_arg10); + setArg(call_vsxseg_2008, 12, 0); + setRet(call_vsxseg_2008, 0, ret_val_vsxseg_2008); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 471); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 472: VSUXSEG8EI64__V */ + continuation_e __vsuxseg8ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG8EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 472); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_2010; + x86::Gp ret_val_get_pow_2010 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_2010, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_2011; + x86::Gp ret_val_get_sew_pow_2011 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2011, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_2012; + x86::Gp ret_val_get_lmul_pow_2012 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2012, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2010, ret_val_get_sew_pow_2011), ret_val_get_lmul_pow_2012)), 3, true); + setArg(call_get_pow_2010, 0, reinterpret_cast(this)); + setArg(call_get_pow_2010, 1, EEW); + setRet(call_get_pow_2010, 0, ret_val_get_pow_2010); + setArg(call_get_sew_pow_2011, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2011, 0, ret_val_get_sew_pow_2011); + setArg(call_get_lmul_pow_2012, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2012, 0, ret_val_get_lmul_pow_2012); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2014; + x86::Gp ret_val_get_lmul_pow_2014 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2014, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_2013; + auto illegal_indexed_store_2013_arg2 = EMUL_pow; + auto illegal_indexed_store_2013_arg3 = ret_val_get_lmul_pow_2014; + x86::Gp ret_val_illegal_indexed_store_2013 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_2013, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_2013; + setArg(call_get_lmul_pow_2014, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2014, 0, ret_val_get_lmul_pow_2014); + setArg(call_illegal_indexed_store_2013, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_2013, 1, 8); + setArg(call_illegal_indexed_store_2013, 2, EEW); + setArg(call_illegal_indexed_store_2013, 3, illegal_indexed_store_2013_arg2); + setArg(call_illegal_indexed_store_2013, 4, illegal_indexed_store_2013_arg3); + setRet(call_illegal_indexed_store_2013, 0, ret_val_illegal_indexed_store_2013); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2016; + x86::Gp ret_val_sew_2016 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2016, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2015; + auto vsxseg_2015_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2015_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2015_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2015_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2015_arg10 = ret_val_sew_2016; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2015 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2015, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2015, 32, false), traits::vstart); + setArg(call_sew_2016, 0, reinterpret_cast(this)); + setRet(call_sew_2016, 0, ret_val_sew_2016); + setArg(call_vsxseg_2015, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2015, 1, V); + setArg(call_vsxseg_2015, 2, vsxseg_2015_arg1); + setArg(call_vsxseg_2015, 3, vsxseg_2015_arg2); + setArg(call_vsxseg_2015, 4, vsxseg_2015_arg3); + setArg(call_vsxseg_2015, 5, vm); + setArg(call_vsxseg_2015, 6, vs3); + setArg(call_vsxseg_2015, 7, vsxseg_2015_arg6); + setArg(call_vsxseg_2015, 8, vs2); + setArg(call_vsxseg_2015, 9, 8); + setArg(call_vsxseg_2015, 10, 8); + setArg(call_vsxseg_2015, 11, vsxseg_2015_arg10); + setArg(call_vsxseg_2015, 12, 0); + setRet(call_vsxseg_2015, 0, ret_val_vsxseg_2015); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 472); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 473: VADD__VI */ + continuation_e __vadd__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vadd.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADD__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 473); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2017; + x86::Gp ret_val_illegal_normal_2017 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2017, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2017; + setArg(call_illegal_normal_2017, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2017, 1, vd); + setArg(call_illegal_normal_2017, 2, vm); + setRet(call_illegal_normal_2017, 0, ret_val_illegal_normal_2017); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2019; + x86::Gp ret_val_sew_2019 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2019, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2018; + auto vector_imm_op_2018_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2018_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2018_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2018_arg10 = ret_val_sew_2019; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2018, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2019, 0, reinterpret_cast(this)); + setRet(call_sew_2019, 0, ret_val_sew_2019); + setArg(call_vector_imm_op_2018, 0, V); + setArg(call_vector_imm_op_2018, 1, 0); + setArg(call_vector_imm_op_2018, 2, 3); + setArg(call_vector_imm_op_2018, 3, vector_imm_op_2018_arg3); + setArg(call_vector_imm_op_2018, 4, vector_imm_op_2018_arg4); + setArg(call_vector_imm_op_2018, 5, vector_imm_op_2018_arg5); + setArg(call_vector_imm_op_2018, 6, vm); + setArg(call_vector_imm_op_2018, 7, vd); + setArg(call_vector_imm_op_2018, 8, vs2); + setArg(call_vector_imm_op_2018, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_op_2018, 10, vector_imm_op_2018_arg10); + } + cc.bind(label_merge); + } + auto tmp2020 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2020, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2020, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 473); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 474: VADD__VV */ + continuation_e __vadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 474); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2021; + x86::Gp ret_val_illegal_normal_2021 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2021, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2021; + setArg(call_illegal_normal_2021, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2021, 1, vd); + setArg(call_illegal_normal_2021, 2, vm); + setRet(call_illegal_normal_2021, 0, ret_val_illegal_normal_2021); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2023; + x86::Gp ret_val_sew_2023 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2023, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2022; + auto vector_vector_op_2022_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2022_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2022_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2022_arg10 = ret_val_sew_2023; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2022, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2023, 0, reinterpret_cast(this)); + setRet(call_sew_2023, 0, ret_val_sew_2023); + setArg(call_vector_vector_op_2022, 0, V); + setArg(call_vector_vector_op_2022, 1, 0); + setArg(call_vector_vector_op_2022, 2, 0); + setArg(call_vector_vector_op_2022, 3, vector_vector_op_2022_arg3); + setArg(call_vector_vector_op_2022, 4, vector_vector_op_2022_arg4); + setArg(call_vector_vector_op_2022, 5, vector_vector_op_2022_arg5); + setArg(call_vector_vector_op_2022, 6, vm); + setArg(call_vector_vector_op_2022, 7, vd); + setArg(call_vector_vector_op_2022, 8, vs2); + setArg(call_vector_vector_op_2022, 9, vs1); + setArg(call_vector_vector_op_2022, 10, vector_vector_op_2022_arg10); + } + cc.bind(label_merge); + } + auto tmp2024 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2024, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2024, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 474); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 475: VADD__VX */ + continuation_e __vadd__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADD__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 475); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2025; + x86::Gp ret_val_illegal_normal_2025 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2025, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2026 = get_reg(cc, 8, false); + mov(cc, tmp2026, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2026, ret_val_illegal_normal_2025); + setArg(call_illegal_normal_2025, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2025, 1, vd); + setArg(call_illegal_normal_2025, 2, vm); + setRet(call_illegal_normal_2025, 0, ret_val_illegal_normal_2025); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2028; + x86::Gp ret_val_sew_2028 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2028, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2027; + auto vector_imm_op_2027_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2027_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2027_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2027_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2027_arg10 = ret_val_sew_2028; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2027, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2028, 0, reinterpret_cast(this)); + setRet(call_sew_2028, 0, ret_val_sew_2028); + setArg(call_vector_imm_op_2027, 0, V); + setArg(call_vector_imm_op_2027, 1, 0); + setArg(call_vector_imm_op_2027, 2, 4); + setArg(call_vector_imm_op_2027, 3, vector_imm_op_2027_arg3); + setArg(call_vector_imm_op_2027, 4, vector_imm_op_2027_arg4); + setArg(call_vector_imm_op_2027, 5, vector_imm_op_2027_arg5); + setArg(call_vector_imm_op_2027, 6, vm); + setArg(call_vector_imm_op_2027, 7, vd); + setArg(call_vector_imm_op_2027, 8, vs2); + setArg(call_vector_imm_op_2027, 9, vector_imm_op_2027_arg9); + setArg(call_vector_imm_op_2027, 10, vector_imm_op_2027_arg10); + } + cc.bind(label_merge); + } + auto tmp2029 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2029, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2029, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 475); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 476: VSUB__VV */ + continuation_e __vsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 476); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2030; + x86::Gp ret_val_illegal_normal_2030 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2030, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2030; + setArg(call_illegal_normal_2030, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2030, 1, vd); + setArg(call_illegal_normal_2030, 2, vm); + setRet(call_illegal_normal_2030, 0, ret_val_illegal_normal_2030); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2032; + x86::Gp ret_val_sew_2032 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2032, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2031; + auto vector_vector_op_2031_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2031_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2031_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2031_arg10 = ret_val_sew_2032; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2031, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2032, 0, reinterpret_cast(this)); + setRet(call_sew_2032, 0, ret_val_sew_2032); + setArg(call_vector_vector_op_2031, 0, V); + setArg(call_vector_vector_op_2031, 1, 2); + setArg(call_vector_vector_op_2031, 2, 0); + setArg(call_vector_vector_op_2031, 3, vector_vector_op_2031_arg3); + setArg(call_vector_vector_op_2031, 4, vector_vector_op_2031_arg4); + setArg(call_vector_vector_op_2031, 5, vector_vector_op_2031_arg5); + setArg(call_vector_vector_op_2031, 6, vm); + setArg(call_vector_vector_op_2031, 7, vd); + setArg(call_vector_vector_op_2031, 8, vs2); + setArg(call_vector_vector_op_2031, 9, vs1); + setArg(call_vector_vector_op_2031, 10, vector_vector_op_2031_arg10); + } + cc.bind(label_merge); + } + auto tmp2033 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2033, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2033, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 476); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 477: VSUB__VX */ + continuation_e __vsub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 477); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2034; + x86::Gp ret_val_illegal_normal_2034 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2034, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2035 = get_reg(cc, 8, false); + mov(cc, tmp2035, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2035, ret_val_illegal_normal_2034); + setArg(call_illegal_normal_2034, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2034, 1, vd); + setArg(call_illegal_normal_2034, 2, vm); + setRet(call_illegal_normal_2034, 0, ret_val_illegal_normal_2034); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2037; + x86::Gp ret_val_sew_2037 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2037, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2036; + auto vector_imm_op_2036_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2036_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2036_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2036_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2036_arg10 = ret_val_sew_2037; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2036, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2037, 0, reinterpret_cast(this)); + setRet(call_sew_2037, 0, ret_val_sew_2037); + setArg(call_vector_imm_op_2036, 0, V); + setArg(call_vector_imm_op_2036, 1, 2); + setArg(call_vector_imm_op_2036, 2, 4); + setArg(call_vector_imm_op_2036, 3, vector_imm_op_2036_arg3); + setArg(call_vector_imm_op_2036, 4, vector_imm_op_2036_arg4); + setArg(call_vector_imm_op_2036, 5, vector_imm_op_2036_arg5); + setArg(call_vector_imm_op_2036, 6, vm); + setArg(call_vector_imm_op_2036, 7, vd); + setArg(call_vector_imm_op_2036, 8, vs2); + setArg(call_vector_imm_op_2036, 9, vector_imm_op_2036_arg9); + setArg(call_vector_imm_op_2036, 10, vector_imm_op_2036_arg10); + } + cc.bind(label_merge); + } + auto tmp2038 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2038, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2038, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 477); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 478: VRSUB__VI */ + continuation_e __vrsub__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vrsub.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRSUB__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 478); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2039; + x86::Gp ret_val_illegal_normal_2039 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2039, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2039; + setArg(call_illegal_normal_2039, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2039, 1, vd); + setArg(call_illegal_normal_2039, 2, vm); + setRet(call_illegal_normal_2039, 0, ret_val_illegal_normal_2039); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2041; + x86::Gp ret_val_sew_2041 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2041, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2040; + auto vector_imm_op_2040_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2040_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2040_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2040_arg10 = ret_val_sew_2041; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2040, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2041, 0, reinterpret_cast(this)); + setRet(call_sew_2041, 0, ret_val_sew_2041); + setArg(call_vector_imm_op_2040, 0, V); + setArg(call_vector_imm_op_2040, 1, 3); + setArg(call_vector_imm_op_2040, 2, 3); + setArg(call_vector_imm_op_2040, 3, vector_imm_op_2040_arg3); + setArg(call_vector_imm_op_2040, 4, vector_imm_op_2040_arg4); + setArg(call_vector_imm_op_2040, 5, vector_imm_op_2040_arg5); + setArg(call_vector_imm_op_2040, 6, vm); + setArg(call_vector_imm_op_2040, 7, vd); + setArg(call_vector_imm_op_2040, 8, vs2); + setArg(call_vector_imm_op_2040, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_op_2040, 10, vector_imm_op_2040_arg10); + } + cc.bind(label_merge); + } + auto tmp2042 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2042, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2042, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 478); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 479: VRSUB__VX */ + continuation_e __vrsub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRSUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 479); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2043; + x86::Gp ret_val_illegal_normal_2043 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2043, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2044 = get_reg(cc, 8, false); + mov(cc, tmp2044, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2044, ret_val_illegal_normal_2043); + setArg(call_illegal_normal_2043, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2043, 1, vd); + setArg(call_illegal_normal_2043, 2, vm); + setRet(call_illegal_normal_2043, 0, ret_val_illegal_normal_2043); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2046; + x86::Gp ret_val_sew_2046 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2046, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2045; + auto vector_imm_op_2045_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2045_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2045_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2045_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2045_arg10 = ret_val_sew_2046; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2045, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2046, 0, reinterpret_cast(this)); + setRet(call_sew_2046, 0, ret_val_sew_2046); + setArg(call_vector_imm_op_2045, 0, V); + setArg(call_vector_imm_op_2045, 1, 3); + setArg(call_vector_imm_op_2045, 2, 4); + setArg(call_vector_imm_op_2045, 3, vector_imm_op_2045_arg3); + setArg(call_vector_imm_op_2045, 4, vector_imm_op_2045_arg4); + setArg(call_vector_imm_op_2045, 5, vector_imm_op_2045_arg5); + setArg(call_vector_imm_op_2045, 6, vm); + setArg(call_vector_imm_op_2045, 7, vd); + setArg(call_vector_imm_op_2045, 8, vs2); + setArg(call_vector_imm_op_2045, 9, vector_imm_op_2045_arg9); + setArg(call_vector_imm_op_2045, 10, vector_imm_op_2045_arg10); + } + cc.bind(label_merge); + } + auto tmp2047 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2047, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2047, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 479); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 480: VWADDU__VV */ + continuation_e __vwaddu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADDU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 480); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2048; + x86::Gp ret_val_get_sew_pow_2048 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2048, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2049 = get_reg(cc, 8, false); + mov(cc, tmp2049, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2049, ret_val_get_sew_pow_2048)), 8, false), ~ 1); + setArg(call_get_sew_pow_2048, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2048, 0, ret_val_get_sew_pow_2048); + InvokeNode* call_get_lmul_pow_2050; + x86::Gp ret_val_get_lmul_pow_2050 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2050, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2050; + setArg(call_get_lmul_pow_2050, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2050, 0, ret_val_get_lmul_pow_2050); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2051; + auto illegal_variable_width_2051_arg2 = SEW_widen; + auto illegal_variable_width_2051_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2051 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2051, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2052; + auto valid_reg_overlap_2052_arg2 = LMUL_pow; + auto valid_reg_overlap_2052_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2052 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2052, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2053; + auto valid_reg_overlap_2053_arg2 = LMUL_pow; + auto valid_reg_overlap_2053_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2053 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2053, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2051, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2052)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2053)); + setArg(call_illegal_variable_width_2051, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2051, 1, vd); + setArg(call_illegal_variable_width_2051, 2, vm); + setArg(call_illegal_variable_width_2051, 3, illegal_variable_width_2051_arg2); + setArg(call_illegal_variable_width_2051, 4, illegal_variable_width_2051_arg3); + setRet(call_illegal_variable_width_2051, 0, ret_val_illegal_variable_width_2051); + setArg(call_valid_reg_overlap_2052, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2052, 1, vs1); + setArg(call_valid_reg_overlap_2052, 2, vd); + setArg(call_valid_reg_overlap_2052, 3, valid_reg_overlap_2052_arg2); + setArg(call_valid_reg_overlap_2052, 4, valid_reg_overlap_2052_arg3); + setRet(call_valid_reg_overlap_2052, 0, ret_val_valid_reg_overlap_2052); + setArg(call_valid_reg_overlap_2053, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2053, 1, vs2); + setArg(call_valid_reg_overlap_2053, 2, vd); + setArg(call_valid_reg_overlap_2053, 3, valid_reg_overlap_2053_arg2); + setArg(call_valid_reg_overlap_2053, 4, valid_reg_overlap_2053_arg3); + setRet(call_valid_reg_overlap_2053, 0, ret_val_valid_reg_overlap_2053); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2055; + x86::Gp ret_val_sew_2055 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2055, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2054; + auto vector_vector_wv_2054_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2054_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2054_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2054_arg10 = ret_val_sew_2055; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2054, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2055, 0, reinterpret_cast(this)); + setRet(call_sew_2055, 0, ret_val_sew_2055); + setArg(call_vector_vector_wv_2054, 0, V); + setArg(call_vector_vector_wv_2054, 1, 48); + setArg(call_vector_vector_wv_2054, 2, 2); + setArg(call_vector_vector_wv_2054, 3, vector_vector_wv_2054_arg3); + setArg(call_vector_vector_wv_2054, 4, vector_vector_wv_2054_arg4); + setArg(call_vector_vector_wv_2054, 5, vector_vector_wv_2054_arg5); + setArg(call_vector_vector_wv_2054, 6, vm); + setArg(call_vector_vector_wv_2054, 7, vd); + setArg(call_vector_vector_wv_2054, 8, vs2); + setArg(call_vector_vector_wv_2054, 9, vs1); + setArg(call_vector_vector_wv_2054, 10, vector_vector_wv_2054_arg10); + } + cc.bind(label_merge); + } + auto tmp2056 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2056, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2056, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 480); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 481: VWADDU__VX */ + continuation_e __vwaddu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADDU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 481); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2057; + x86::Gp ret_val_get_sew_pow_2057 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2057, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2058 = get_reg(cc, 8, false); + mov(cc, tmp2058, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2058, ret_val_get_sew_pow_2057)), 8, false), ~ 1); + setArg(call_get_sew_pow_2057, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2057, 0, ret_val_get_sew_pow_2057); + InvokeNode* call_get_lmul_pow_2059; + x86::Gp ret_val_get_lmul_pow_2059 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2059, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2059; + setArg(call_get_lmul_pow_2059, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2059, 0, ret_val_get_lmul_pow_2059); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2060; + auto illegal_variable_width_2060_arg2 = SEW_widen; + auto illegal_variable_width_2060_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2060 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2060, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2061; + auto valid_reg_overlap_2061_arg2 = LMUL_pow; + auto valid_reg_overlap_2061_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2061 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2061, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2060, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2061)); + setArg(call_illegal_variable_width_2060, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2060, 1, vd); + setArg(call_illegal_variable_width_2060, 2, vm); + setArg(call_illegal_variable_width_2060, 3, illegal_variable_width_2060_arg2); + setArg(call_illegal_variable_width_2060, 4, illegal_variable_width_2060_arg3); + setRet(call_illegal_variable_width_2060, 0, ret_val_illegal_variable_width_2060); + setArg(call_valid_reg_overlap_2061, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2061, 1, vs2); + setArg(call_valid_reg_overlap_2061, 2, vd); + setArg(call_valid_reg_overlap_2061, 3, valid_reg_overlap_2061_arg2); + setArg(call_valid_reg_overlap_2061, 4, valid_reg_overlap_2061_arg3); + setRet(call_valid_reg_overlap_2061, 0, ret_val_valid_reg_overlap_2061); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2063; + x86::Gp ret_val_sew_2063 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2063, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2062; + auto vector_imm_wv_2062_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2062_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2062_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2062_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2062_arg10 = ret_val_sew_2063; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2062, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2063, 0, reinterpret_cast(this)); + setRet(call_sew_2063, 0, ret_val_sew_2063); + setArg(call_vector_imm_wv_2062, 0, V); + setArg(call_vector_imm_wv_2062, 1, 48); + setArg(call_vector_imm_wv_2062, 2, 6); + setArg(call_vector_imm_wv_2062, 3, vector_imm_wv_2062_arg3); + setArg(call_vector_imm_wv_2062, 4, vector_imm_wv_2062_arg4); + setArg(call_vector_imm_wv_2062, 5, vector_imm_wv_2062_arg5); + setArg(call_vector_imm_wv_2062, 6, vm); + setArg(call_vector_imm_wv_2062, 7, vd); + setArg(call_vector_imm_wv_2062, 8, vs2); + setArg(call_vector_imm_wv_2062, 9, vector_imm_wv_2062_arg9); + setArg(call_vector_imm_wv_2062, 10, vector_imm_wv_2062_arg10); + } + cc.bind(label_merge); + } + auto tmp2064 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2064, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2064, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 481); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 482: VWSUBU__VV */ + continuation_e __vwsubu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUBU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 482); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2065; + x86::Gp ret_val_get_sew_pow_2065 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2065, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2066 = get_reg(cc, 8, false); + mov(cc, tmp2066, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2066, ret_val_get_sew_pow_2065)), 8, false), ~ 1); + setArg(call_get_sew_pow_2065, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2065, 0, ret_val_get_sew_pow_2065); + InvokeNode* call_get_lmul_pow_2067; + x86::Gp ret_val_get_lmul_pow_2067 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2067, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2067; + setArg(call_get_lmul_pow_2067, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2067, 0, ret_val_get_lmul_pow_2067); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2068; + auto illegal_variable_width_2068_arg2 = SEW_widen; + auto illegal_variable_width_2068_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2068 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2068, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2069; + auto valid_reg_overlap_2069_arg2 = LMUL_pow; + auto valid_reg_overlap_2069_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2069 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2069, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2070; + auto valid_reg_overlap_2070_arg2 = LMUL_pow; + auto valid_reg_overlap_2070_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2070 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2070, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2068, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2069)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2070)); + setArg(call_illegal_variable_width_2068, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2068, 1, vd); + setArg(call_illegal_variable_width_2068, 2, vm); + setArg(call_illegal_variable_width_2068, 3, illegal_variable_width_2068_arg2); + setArg(call_illegal_variable_width_2068, 4, illegal_variable_width_2068_arg3); + setRet(call_illegal_variable_width_2068, 0, ret_val_illegal_variable_width_2068); + setArg(call_valid_reg_overlap_2069, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2069, 1, vs1); + setArg(call_valid_reg_overlap_2069, 2, vd); + setArg(call_valid_reg_overlap_2069, 3, valid_reg_overlap_2069_arg2); + setArg(call_valid_reg_overlap_2069, 4, valid_reg_overlap_2069_arg3); + setRet(call_valid_reg_overlap_2069, 0, ret_val_valid_reg_overlap_2069); + setArg(call_valid_reg_overlap_2070, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2070, 1, vs2); + setArg(call_valid_reg_overlap_2070, 2, vd); + setArg(call_valid_reg_overlap_2070, 3, valid_reg_overlap_2070_arg2); + setArg(call_valid_reg_overlap_2070, 4, valid_reg_overlap_2070_arg3); + setRet(call_valid_reg_overlap_2070, 0, ret_val_valid_reg_overlap_2070); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2072; + x86::Gp ret_val_sew_2072 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2072, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2071; + auto vector_vector_wv_2071_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2071_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2071_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2071_arg10 = ret_val_sew_2072; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2071, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2072, 0, reinterpret_cast(this)); + setRet(call_sew_2072, 0, ret_val_sew_2072); + setArg(call_vector_vector_wv_2071, 0, V); + setArg(call_vector_vector_wv_2071, 1, 50); + setArg(call_vector_vector_wv_2071, 2, 2); + setArg(call_vector_vector_wv_2071, 3, vector_vector_wv_2071_arg3); + setArg(call_vector_vector_wv_2071, 4, vector_vector_wv_2071_arg4); + setArg(call_vector_vector_wv_2071, 5, vector_vector_wv_2071_arg5); + setArg(call_vector_vector_wv_2071, 6, vm); + setArg(call_vector_vector_wv_2071, 7, vd); + setArg(call_vector_vector_wv_2071, 8, vs2); + setArg(call_vector_vector_wv_2071, 9, vs1); + setArg(call_vector_vector_wv_2071, 10, vector_vector_wv_2071_arg10); + } + cc.bind(label_merge); + } + auto tmp2073 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2073, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2073, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 482); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 483: VWSUBU__VX */ + continuation_e __vwsubu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUBU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 483); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2074; + x86::Gp ret_val_get_sew_pow_2074 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2074, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2075 = get_reg(cc, 8, false); + mov(cc, tmp2075, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2075, ret_val_get_sew_pow_2074)), 8, false), ~ 1); + setArg(call_get_sew_pow_2074, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2074, 0, ret_val_get_sew_pow_2074); + InvokeNode* call_get_lmul_pow_2076; + x86::Gp ret_val_get_lmul_pow_2076 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2076, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2076; + setArg(call_get_lmul_pow_2076, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2076, 0, ret_val_get_lmul_pow_2076); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2077; + auto illegal_variable_width_2077_arg2 = SEW_widen; + auto illegal_variable_width_2077_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2077 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2077, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2078; + auto valid_reg_overlap_2078_arg2 = LMUL_pow; + auto valid_reg_overlap_2078_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2078 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2078, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2077, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2078)); + setArg(call_illegal_variable_width_2077, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2077, 1, vd); + setArg(call_illegal_variable_width_2077, 2, vm); + setArg(call_illegal_variable_width_2077, 3, illegal_variable_width_2077_arg2); + setArg(call_illegal_variable_width_2077, 4, illegal_variable_width_2077_arg3); + setRet(call_illegal_variable_width_2077, 0, ret_val_illegal_variable_width_2077); + setArg(call_valid_reg_overlap_2078, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2078, 1, vs2); + setArg(call_valid_reg_overlap_2078, 2, vd); + setArg(call_valid_reg_overlap_2078, 3, valid_reg_overlap_2078_arg2); + setArg(call_valid_reg_overlap_2078, 4, valid_reg_overlap_2078_arg3); + setRet(call_valid_reg_overlap_2078, 0, ret_val_valid_reg_overlap_2078); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2080; + x86::Gp ret_val_sew_2080 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2080, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2079; + auto vector_imm_wv_2079_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2079_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2079_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2079_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2079_arg10 = ret_val_sew_2080; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2079, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2080, 0, reinterpret_cast(this)); + setRet(call_sew_2080, 0, ret_val_sew_2080); + setArg(call_vector_imm_wv_2079, 0, V); + setArg(call_vector_imm_wv_2079, 1, 50); + setArg(call_vector_imm_wv_2079, 2, 6); + setArg(call_vector_imm_wv_2079, 3, vector_imm_wv_2079_arg3); + setArg(call_vector_imm_wv_2079, 4, vector_imm_wv_2079_arg4); + setArg(call_vector_imm_wv_2079, 5, vector_imm_wv_2079_arg5); + setArg(call_vector_imm_wv_2079, 6, vm); + setArg(call_vector_imm_wv_2079, 7, vd); + setArg(call_vector_imm_wv_2079, 8, vs2); + setArg(call_vector_imm_wv_2079, 9, vector_imm_wv_2079_arg9); + setArg(call_vector_imm_wv_2079, 10, vector_imm_wv_2079_arg10); + } + cc.bind(label_merge); + } + auto tmp2081 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2081, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2081, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 483); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 484: VWADD__VV */ + continuation_e __vwadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 484); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2082; + x86::Gp ret_val_get_sew_pow_2082 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2082, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2083 = get_reg(cc, 8, false); + mov(cc, tmp2083, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2083, ret_val_get_sew_pow_2082)), 8, false), ~ 1); + setArg(call_get_sew_pow_2082, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2082, 0, ret_val_get_sew_pow_2082); + InvokeNode* call_get_lmul_pow_2084; + x86::Gp ret_val_get_lmul_pow_2084 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2084, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2084; + setArg(call_get_lmul_pow_2084, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2084, 0, ret_val_get_lmul_pow_2084); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2085; + auto illegal_variable_width_2085_arg2 = SEW_widen; + auto illegal_variable_width_2085_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2085 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2085, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2086; + auto valid_reg_overlap_2086_arg2 = LMUL_pow; + auto valid_reg_overlap_2086_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2086 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2086, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2087; + auto valid_reg_overlap_2087_arg2 = LMUL_pow; + auto valid_reg_overlap_2087_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2087 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2087, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2085, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2086)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2087)); + setArg(call_illegal_variable_width_2085, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2085, 1, vd); + setArg(call_illegal_variable_width_2085, 2, vm); + setArg(call_illegal_variable_width_2085, 3, illegal_variable_width_2085_arg2); + setArg(call_illegal_variable_width_2085, 4, illegal_variable_width_2085_arg3); + setRet(call_illegal_variable_width_2085, 0, ret_val_illegal_variable_width_2085); + setArg(call_valid_reg_overlap_2086, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2086, 1, vs1); + setArg(call_valid_reg_overlap_2086, 2, vd); + setArg(call_valid_reg_overlap_2086, 3, valid_reg_overlap_2086_arg2); + setArg(call_valid_reg_overlap_2086, 4, valid_reg_overlap_2086_arg3); + setRet(call_valid_reg_overlap_2086, 0, ret_val_valid_reg_overlap_2086); + setArg(call_valid_reg_overlap_2087, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2087, 1, vs2); + setArg(call_valid_reg_overlap_2087, 2, vd); + setArg(call_valid_reg_overlap_2087, 3, valid_reg_overlap_2087_arg2); + setArg(call_valid_reg_overlap_2087, 4, valid_reg_overlap_2087_arg3); + setRet(call_valid_reg_overlap_2087, 0, ret_val_valid_reg_overlap_2087); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2089; + x86::Gp ret_val_sew_2089 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2089, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2088; + auto vector_vector_wv_2088_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2088_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2088_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2088_arg10 = ret_val_sew_2089; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2088, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2089, 0, reinterpret_cast(this)); + setRet(call_sew_2089, 0, ret_val_sew_2089); + setArg(call_vector_vector_wv_2088, 0, V); + setArg(call_vector_vector_wv_2088, 1, 49); + setArg(call_vector_vector_wv_2088, 2, 2); + setArg(call_vector_vector_wv_2088, 3, vector_vector_wv_2088_arg3); + setArg(call_vector_vector_wv_2088, 4, vector_vector_wv_2088_arg4); + setArg(call_vector_vector_wv_2088, 5, vector_vector_wv_2088_arg5); + setArg(call_vector_vector_wv_2088, 6, vm); + setArg(call_vector_vector_wv_2088, 7, vd); + setArg(call_vector_vector_wv_2088, 8, vs2); + setArg(call_vector_vector_wv_2088, 9, vs1); + setArg(call_vector_vector_wv_2088, 10, vector_vector_wv_2088_arg10); + } + cc.bind(label_merge); + } + auto tmp2090 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2090, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2090, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 484); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 485: VWADD__VX */ + continuation_e __vwadd__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADD__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 485); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2091; + x86::Gp ret_val_get_sew_pow_2091 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2091, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2092 = get_reg(cc, 8, false); + mov(cc, tmp2092, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2092, ret_val_get_sew_pow_2091)), 8, false), ~ 1); + setArg(call_get_sew_pow_2091, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2091, 0, ret_val_get_sew_pow_2091); + InvokeNode* call_get_lmul_pow_2093; + x86::Gp ret_val_get_lmul_pow_2093 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2093, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2093; + setArg(call_get_lmul_pow_2093, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2093, 0, ret_val_get_lmul_pow_2093); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2094; + auto illegal_variable_width_2094_arg2 = SEW_widen; + auto illegal_variable_width_2094_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2094 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2094, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2095; + auto valid_reg_overlap_2095_arg2 = LMUL_pow; + auto valid_reg_overlap_2095_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2095 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2095, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2094, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2095)); + setArg(call_illegal_variable_width_2094, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2094, 1, vd); + setArg(call_illegal_variable_width_2094, 2, vm); + setArg(call_illegal_variable_width_2094, 3, illegal_variable_width_2094_arg2); + setArg(call_illegal_variable_width_2094, 4, illegal_variable_width_2094_arg3); + setRet(call_illegal_variable_width_2094, 0, ret_val_illegal_variable_width_2094); + setArg(call_valid_reg_overlap_2095, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2095, 1, vs2); + setArg(call_valid_reg_overlap_2095, 2, vd); + setArg(call_valid_reg_overlap_2095, 3, valid_reg_overlap_2095_arg2); + setArg(call_valid_reg_overlap_2095, 4, valid_reg_overlap_2095_arg3); + setRet(call_valid_reg_overlap_2095, 0, ret_val_valid_reg_overlap_2095); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2097; + x86::Gp ret_val_sew_2097 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2097, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2096; + auto vector_imm_wv_2096_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2096_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2096_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2096_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2096_arg10 = ret_val_sew_2097; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2096, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2097, 0, reinterpret_cast(this)); + setRet(call_sew_2097, 0, ret_val_sew_2097); + setArg(call_vector_imm_wv_2096, 0, V); + setArg(call_vector_imm_wv_2096, 1, 49); + setArg(call_vector_imm_wv_2096, 2, 6); + setArg(call_vector_imm_wv_2096, 3, vector_imm_wv_2096_arg3); + setArg(call_vector_imm_wv_2096, 4, vector_imm_wv_2096_arg4); + setArg(call_vector_imm_wv_2096, 5, vector_imm_wv_2096_arg5); + setArg(call_vector_imm_wv_2096, 6, vm); + setArg(call_vector_imm_wv_2096, 7, vd); + setArg(call_vector_imm_wv_2096, 8, vs2); + setArg(call_vector_imm_wv_2096, 9, vector_imm_wv_2096_arg9); + setArg(call_vector_imm_wv_2096, 10, vector_imm_wv_2096_arg10); + } + cc.bind(label_merge); + } + auto tmp2098 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2098, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2098, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 485); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 486: VWSUB__VV */ + continuation_e __vwsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 486); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2099; + x86::Gp ret_val_get_sew_pow_2099 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2099, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2100 = get_reg(cc, 8, false); + mov(cc, tmp2100, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2100, ret_val_get_sew_pow_2099)), 8, false), ~ 1); + setArg(call_get_sew_pow_2099, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2099, 0, ret_val_get_sew_pow_2099); + InvokeNode* call_get_lmul_pow_2101; + x86::Gp ret_val_get_lmul_pow_2101 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2101, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2101; + setArg(call_get_lmul_pow_2101, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2101, 0, ret_val_get_lmul_pow_2101); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2102; + auto illegal_variable_width_2102_arg2 = SEW_widen; + auto illegal_variable_width_2102_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2102 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2102, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2103; + auto valid_reg_overlap_2103_arg2 = LMUL_pow; + auto valid_reg_overlap_2103_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2103 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2103, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2104; + auto valid_reg_overlap_2104_arg2 = LMUL_pow; + auto valid_reg_overlap_2104_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2104 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2104, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2102, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2103)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2104)); + setArg(call_illegal_variable_width_2102, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2102, 1, vd); + setArg(call_illegal_variable_width_2102, 2, vm); + setArg(call_illegal_variable_width_2102, 3, illegal_variable_width_2102_arg2); + setArg(call_illegal_variable_width_2102, 4, illegal_variable_width_2102_arg3); + setRet(call_illegal_variable_width_2102, 0, ret_val_illegal_variable_width_2102); + setArg(call_valid_reg_overlap_2103, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2103, 1, vs1); + setArg(call_valid_reg_overlap_2103, 2, vd); + setArg(call_valid_reg_overlap_2103, 3, valid_reg_overlap_2103_arg2); + setArg(call_valid_reg_overlap_2103, 4, valid_reg_overlap_2103_arg3); + setRet(call_valid_reg_overlap_2103, 0, ret_val_valid_reg_overlap_2103); + setArg(call_valid_reg_overlap_2104, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2104, 1, vs2); + setArg(call_valid_reg_overlap_2104, 2, vd); + setArg(call_valid_reg_overlap_2104, 3, valid_reg_overlap_2104_arg2); + setArg(call_valid_reg_overlap_2104, 4, valid_reg_overlap_2104_arg3); + setRet(call_valid_reg_overlap_2104, 0, ret_val_valid_reg_overlap_2104); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2106; + x86::Gp ret_val_sew_2106 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2106, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2105; + auto vector_vector_wv_2105_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2105_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2105_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2105_arg10 = ret_val_sew_2106; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2105, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2106, 0, reinterpret_cast(this)); + setRet(call_sew_2106, 0, ret_val_sew_2106); + setArg(call_vector_vector_wv_2105, 0, V); + setArg(call_vector_vector_wv_2105, 1, 51); + setArg(call_vector_vector_wv_2105, 2, 2); + setArg(call_vector_vector_wv_2105, 3, vector_vector_wv_2105_arg3); + setArg(call_vector_vector_wv_2105, 4, vector_vector_wv_2105_arg4); + setArg(call_vector_vector_wv_2105, 5, vector_vector_wv_2105_arg5); + setArg(call_vector_vector_wv_2105, 6, vm); + setArg(call_vector_vector_wv_2105, 7, vd); + setArg(call_vector_vector_wv_2105, 8, vs2); + setArg(call_vector_vector_wv_2105, 9, vs1); + setArg(call_vector_vector_wv_2105, 10, vector_vector_wv_2105_arg10); + } + cc.bind(label_merge); + } + auto tmp2107 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2107, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2107, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 486); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 487: VWSUB__VX */ + continuation_e __vwsub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 487); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2108; + x86::Gp ret_val_get_sew_pow_2108 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2108, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2109 = get_reg(cc, 8, false); + mov(cc, tmp2109, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2109, ret_val_get_sew_pow_2108)), 8, false), ~ 1); + setArg(call_get_sew_pow_2108, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2108, 0, ret_val_get_sew_pow_2108); + InvokeNode* call_get_lmul_pow_2110; + x86::Gp ret_val_get_lmul_pow_2110 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2110, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2110; + setArg(call_get_lmul_pow_2110, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2110, 0, ret_val_get_lmul_pow_2110); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2111; + auto illegal_variable_width_2111_arg2 = SEW_widen; + auto illegal_variable_width_2111_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2111 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2111, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2112; + auto valid_reg_overlap_2112_arg2 = LMUL_pow; + auto valid_reg_overlap_2112_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2112 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2112, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2111, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2112)); + setArg(call_illegal_variable_width_2111, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2111, 1, vd); + setArg(call_illegal_variable_width_2111, 2, vm); + setArg(call_illegal_variable_width_2111, 3, illegal_variable_width_2111_arg2); + setArg(call_illegal_variable_width_2111, 4, illegal_variable_width_2111_arg3); + setRet(call_illegal_variable_width_2111, 0, ret_val_illegal_variable_width_2111); + setArg(call_valid_reg_overlap_2112, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2112, 1, vs2); + setArg(call_valid_reg_overlap_2112, 2, vd); + setArg(call_valid_reg_overlap_2112, 3, valid_reg_overlap_2112_arg2); + setArg(call_valid_reg_overlap_2112, 4, valid_reg_overlap_2112_arg3); + setRet(call_valid_reg_overlap_2112, 0, ret_val_valid_reg_overlap_2112); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2114; + x86::Gp ret_val_sew_2114 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2114, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2113; + auto vector_imm_wv_2113_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2113_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2113_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2113_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2113_arg10 = ret_val_sew_2114; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2113, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2114, 0, reinterpret_cast(this)); + setRet(call_sew_2114, 0, ret_val_sew_2114); + setArg(call_vector_imm_wv_2113, 0, V); + setArg(call_vector_imm_wv_2113, 1, 51); + setArg(call_vector_imm_wv_2113, 2, 6); + setArg(call_vector_imm_wv_2113, 3, vector_imm_wv_2113_arg3); + setArg(call_vector_imm_wv_2113, 4, vector_imm_wv_2113_arg4); + setArg(call_vector_imm_wv_2113, 5, vector_imm_wv_2113_arg5); + setArg(call_vector_imm_wv_2113, 6, vm); + setArg(call_vector_imm_wv_2113, 7, vd); + setArg(call_vector_imm_wv_2113, 8, vs2); + setArg(call_vector_imm_wv_2113, 9, vector_imm_wv_2113_arg9); + setArg(call_vector_imm_wv_2113, 10, vector_imm_wv_2113_arg10); + } + cc.bind(label_merge); + } + auto tmp2115 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2115, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2115, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 487); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 488: VWADDU__WV */ + continuation_e __vwaddu__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwaddu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADDU__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 488); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2116; + x86::Gp ret_val_get_sew_pow_2116 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2116, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2117 = get_reg(cc, 8, false); + mov(cc, tmp2117, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2117, ret_val_get_sew_pow_2116)), 8, false), ~ 1); + setArg(call_get_sew_pow_2116, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2116, 0, ret_val_get_sew_pow_2116); + InvokeNode* call_get_lmul_pow_2118; + x86::Gp ret_val_get_lmul_pow_2118 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2118, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2118; + setArg(call_get_lmul_pow_2118, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2118, 0, ret_val_get_lmul_pow_2118); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2119; + auto illegal_variable_width_2119_arg2 = SEW_widen; + auto illegal_variable_width_2119_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2119 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2119, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2120; + auto valid_reg_overlap_2120_arg2 = LMUL_pow; + auto valid_reg_overlap_2120_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2120 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2120, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, bor, ret_val_illegal_variable_width_2119, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2120)); + setArg(call_illegal_variable_width_2119, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2119, 1, vd); + setArg(call_illegal_variable_width_2119, 2, vm); + setArg(call_illegal_variable_width_2119, 3, illegal_variable_width_2119_arg2); + setArg(call_illegal_variable_width_2119, 4, illegal_variable_width_2119_arg3); + setRet(call_illegal_variable_width_2119, 0, ret_val_illegal_variable_width_2119); + setArg(call_valid_reg_overlap_2120, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2120, 1, vs1); + setArg(call_valid_reg_overlap_2120, 2, vd); + setArg(call_valid_reg_overlap_2120, 3, valid_reg_overlap_2120_arg2); + setArg(call_valid_reg_overlap_2120, 4, valid_reg_overlap_2120_arg3); + setRet(call_valid_reg_overlap_2120, 0, ret_val_valid_reg_overlap_2120); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2122; + x86::Gp ret_val_sew_2122 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2122, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_ww_2121; + auto vector_vector_ww_2121_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_ww_2121_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_ww_2121_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_ww_2121_arg10 = ret_val_sew_2122; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_ww_2121, &vector_vector_ww, FuncSignature::build()); + setArg(call_sew_2122, 0, reinterpret_cast(this)); + setRet(call_sew_2122, 0, ret_val_sew_2122); + setArg(call_vector_vector_ww_2121, 0, V); + setArg(call_vector_vector_ww_2121, 1, 52); + setArg(call_vector_vector_ww_2121, 2, 2); + setArg(call_vector_vector_ww_2121, 3, vector_vector_ww_2121_arg3); + setArg(call_vector_vector_ww_2121, 4, vector_vector_ww_2121_arg4); + setArg(call_vector_vector_ww_2121, 5, vector_vector_ww_2121_arg5); + setArg(call_vector_vector_ww_2121, 6, vm); + setArg(call_vector_vector_ww_2121, 7, vd); + setArg(call_vector_vector_ww_2121, 8, vs2); + setArg(call_vector_vector_ww_2121, 9, vs1); + setArg(call_vector_vector_ww_2121, 10, vector_vector_ww_2121_arg10); + } + cc.bind(label_merge); + } + auto tmp2123 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2123, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2123, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 488); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 489: VWADDU__WX */ + continuation_e __vwaddu__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwaddu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADDU__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 489); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2124; + x86::Gp ret_val_get_sew_pow_2124 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2124, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2125 = get_reg(cc, 8, false); + mov(cc, tmp2125, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2125, ret_val_get_sew_pow_2124)), 8, false), ~ 1); + setArg(call_get_sew_pow_2124, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2124, 0, ret_val_get_sew_pow_2124); + InvokeNode* call_get_lmul_pow_2126; + x86::Gp ret_val_get_lmul_pow_2126 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2126, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2126; + setArg(call_get_lmul_pow_2126, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2126, 0, ret_val_get_lmul_pow_2126); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2127; + auto illegal_variable_width_2127_arg2 = SEW_widen; + auto illegal_variable_width_2127_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2127 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2127, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_variable_width_2127; + setArg(call_illegal_variable_width_2127, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2127, 1, vd); + setArg(call_illegal_variable_width_2127, 2, vm); + setArg(call_illegal_variable_width_2127, 3, illegal_variable_width_2127_arg2); + setArg(call_illegal_variable_width_2127, 4, illegal_variable_width_2127_arg3); + setRet(call_illegal_variable_width_2127, 0, ret_val_illegal_variable_width_2127); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2129; + x86::Gp ret_val_sew_2129 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2129, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_ww_2128; + auto vector_imm_ww_2128_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_ww_2128_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_ww_2128_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_ww_2128_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_ww_2128_arg10 = ret_val_sew_2129; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_ww_2128, &vector_imm_ww, FuncSignature::build()); + setArg(call_sew_2129, 0, reinterpret_cast(this)); + setRet(call_sew_2129, 0, ret_val_sew_2129); + setArg(call_vector_imm_ww_2128, 0, V); + setArg(call_vector_imm_ww_2128, 1, 52); + setArg(call_vector_imm_ww_2128, 2, 6); + setArg(call_vector_imm_ww_2128, 3, vector_imm_ww_2128_arg3); + setArg(call_vector_imm_ww_2128, 4, vector_imm_ww_2128_arg4); + setArg(call_vector_imm_ww_2128, 5, vector_imm_ww_2128_arg5); + setArg(call_vector_imm_ww_2128, 6, vm); + setArg(call_vector_imm_ww_2128, 7, vd); + setArg(call_vector_imm_ww_2128, 8, vs2); + setArg(call_vector_imm_ww_2128, 9, vector_imm_ww_2128_arg9); + setArg(call_vector_imm_ww_2128, 10, vector_imm_ww_2128_arg10); + } + cc.bind(label_merge); + } + auto tmp2130 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2130, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2130, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 489); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 490: VWSUBU__WV */ + continuation_e __vwsubu__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsubu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUBU__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 490); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2131; + x86::Gp ret_val_get_sew_pow_2131 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2131, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2132 = get_reg(cc, 8, false); + mov(cc, tmp2132, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2132, ret_val_get_sew_pow_2131)), 8, false), ~ 1); + setArg(call_get_sew_pow_2131, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2131, 0, ret_val_get_sew_pow_2131); + InvokeNode* call_get_lmul_pow_2133; + x86::Gp ret_val_get_lmul_pow_2133 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2133, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2133; + setArg(call_get_lmul_pow_2133, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2133, 0, ret_val_get_lmul_pow_2133); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2134; + auto illegal_variable_width_2134_arg2 = SEW_widen; + auto illegal_variable_width_2134_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2134 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2134, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2135; + auto valid_reg_overlap_2135_arg2 = LMUL_pow; + auto valid_reg_overlap_2135_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2135 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2135, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, bor, ret_val_illegal_variable_width_2134, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2135)); + setArg(call_illegal_variable_width_2134, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2134, 1, vd); + setArg(call_illegal_variable_width_2134, 2, vm); + setArg(call_illegal_variable_width_2134, 3, illegal_variable_width_2134_arg2); + setArg(call_illegal_variable_width_2134, 4, illegal_variable_width_2134_arg3); + setRet(call_illegal_variable_width_2134, 0, ret_val_illegal_variable_width_2134); + setArg(call_valid_reg_overlap_2135, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2135, 1, vs1); + setArg(call_valid_reg_overlap_2135, 2, vd); + setArg(call_valid_reg_overlap_2135, 3, valid_reg_overlap_2135_arg2); + setArg(call_valid_reg_overlap_2135, 4, valid_reg_overlap_2135_arg3); + setRet(call_valid_reg_overlap_2135, 0, ret_val_valid_reg_overlap_2135); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2137; + x86::Gp ret_val_sew_2137 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2137, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_ww_2136; + auto vector_vector_ww_2136_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_ww_2136_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_ww_2136_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_ww_2136_arg10 = ret_val_sew_2137; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_ww_2136, &vector_vector_ww, FuncSignature::build()); + setArg(call_sew_2137, 0, reinterpret_cast(this)); + setRet(call_sew_2137, 0, ret_val_sew_2137); + setArg(call_vector_vector_ww_2136, 0, V); + setArg(call_vector_vector_ww_2136, 1, 54); + setArg(call_vector_vector_ww_2136, 2, 2); + setArg(call_vector_vector_ww_2136, 3, vector_vector_ww_2136_arg3); + setArg(call_vector_vector_ww_2136, 4, vector_vector_ww_2136_arg4); + setArg(call_vector_vector_ww_2136, 5, vector_vector_ww_2136_arg5); + setArg(call_vector_vector_ww_2136, 6, vm); + setArg(call_vector_vector_ww_2136, 7, vd); + setArg(call_vector_vector_ww_2136, 8, vs2); + setArg(call_vector_vector_ww_2136, 9, vs1); + setArg(call_vector_vector_ww_2136, 10, vector_vector_ww_2136_arg10); + } + cc.bind(label_merge); + } + auto tmp2138 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2138, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2138, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 490); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 491: VWSUBU__WX */ + continuation_e __vwsubu__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsubu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUBU__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 491); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2139; + x86::Gp ret_val_get_sew_pow_2139 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2139, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2140 = get_reg(cc, 8, false); + mov(cc, tmp2140, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2140, ret_val_get_sew_pow_2139)), 8, false), ~ 1); + setArg(call_get_sew_pow_2139, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2139, 0, ret_val_get_sew_pow_2139); + InvokeNode* call_get_lmul_pow_2141; + x86::Gp ret_val_get_lmul_pow_2141 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2141, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2141; + setArg(call_get_lmul_pow_2141, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2141, 0, ret_val_get_lmul_pow_2141); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2142; + auto illegal_variable_width_2142_arg2 = SEW_widen; + auto illegal_variable_width_2142_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2142 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2142, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_variable_width_2142; + setArg(call_illegal_variable_width_2142, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2142, 1, vd); + setArg(call_illegal_variable_width_2142, 2, vm); + setArg(call_illegal_variable_width_2142, 3, illegal_variable_width_2142_arg2); + setArg(call_illegal_variable_width_2142, 4, illegal_variable_width_2142_arg3); + setRet(call_illegal_variable_width_2142, 0, ret_val_illegal_variable_width_2142); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2144; + x86::Gp ret_val_sew_2144 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2144, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_ww_2143; + auto vector_imm_ww_2143_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_ww_2143_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_ww_2143_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_ww_2143_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_ww_2143_arg10 = ret_val_sew_2144; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_ww_2143, &vector_imm_ww, FuncSignature::build()); + setArg(call_sew_2144, 0, reinterpret_cast(this)); + setRet(call_sew_2144, 0, ret_val_sew_2144); + setArg(call_vector_imm_ww_2143, 0, V); + setArg(call_vector_imm_ww_2143, 1, 54); + setArg(call_vector_imm_ww_2143, 2, 6); + setArg(call_vector_imm_ww_2143, 3, vector_imm_ww_2143_arg3); + setArg(call_vector_imm_ww_2143, 4, vector_imm_ww_2143_arg4); + setArg(call_vector_imm_ww_2143, 5, vector_imm_ww_2143_arg5); + setArg(call_vector_imm_ww_2143, 6, vm); + setArg(call_vector_imm_ww_2143, 7, vd); + setArg(call_vector_imm_ww_2143, 8, vs2); + setArg(call_vector_imm_ww_2143, 9, vector_imm_ww_2143_arg9); + setArg(call_vector_imm_ww_2143, 10, vector_imm_ww_2143_arg10); + } + cc.bind(label_merge); + } + auto tmp2145 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2145, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2145, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 491); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 492: VWADD__WV */ + continuation_e __vwadd__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwadd.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADD__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 492); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2146; + x86::Gp ret_val_get_sew_pow_2146 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2146, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2147 = get_reg(cc, 8, false); + mov(cc, tmp2147, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2147, ret_val_get_sew_pow_2146)), 8, false), ~ 1); + setArg(call_get_sew_pow_2146, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2146, 0, ret_val_get_sew_pow_2146); + InvokeNode* call_get_lmul_pow_2148; + x86::Gp ret_val_get_lmul_pow_2148 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2148, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2148; + setArg(call_get_lmul_pow_2148, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2148, 0, ret_val_get_lmul_pow_2148); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2149; + auto illegal_variable_width_2149_arg2 = SEW_widen; + auto illegal_variable_width_2149_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2149 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2149, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2150; + auto valid_reg_overlap_2150_arg2 = LMUL_pow; + auto valid_reg_overlap_2150_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2150 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2150, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, bor, ret_val_illegal_variable_width_2149, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2150)); + setArg(call_illegal_variable_width_2149, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2149, 1, vd); + setArg(call_illegal_variable_width_2149, 2, vm); + setArg(call_illegal_variable_width_2149, 3, illegal_variable_width_2149_arg2); + setArg(call_illegal_variable_width_2149, 4, illegal_variable_width_2149_arg3); + setRet(call_illegal_variable_width_2149, 0, ret_val_illegal_variable_width_2149); + setArg(call_valid_reg_overlap_2150, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2150, 1, vs1); + setArg(call_valid_reg_overlap_2150, 2, vd); + setArg(call_valid_reg_overlap_2150, 3, valid_reg_overlap_2150_arg2); + setArg(call_valid_reg_overlap_2150, 4, valid_reg_overlap_2150_arg3); + setRet(call_valid_reg_overlap_2150, 0, ret_val_valid_reg_overlap_2150); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2152; + x86::Gp ret_val_sew_2152 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2152, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_ww_2151; + auto vector_vector_ww_2151_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_ww_2151_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_ww_2151_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_ww_2151_arg10 = ret_val_sew_2152; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_ww_2151, &vector_vector_ww, FuncSignature::build()); + setArg(call_sew_2152, 0, reinterpret_cast(this)); + setRet(call_sew_2152, 0, ret_val_sew_2152); + setArg(call_vector_vector_ww_2151, 0, V); + setArg(call_vector_vector_ww_2151, 1, 53); + setArg(call_vector_vector_ww_2151, 2, 2); + setArg(call_vector_vector_ww_2151, 3, vector_vector_ww_2151_arg3); + setArg(call_vector_vector_ww_2151, 4, vector_vector_ww_2151_arg4); + setArg(call_vector_vector_ww_2151, 5, vector_vector_ww_2151_arg5); + setArg(call_vector_vector_ww_2151, 6, vm); + setArg(call_vector_vector_ww_2151, 7, vd); + setArg(call_vector_vector_ww_2151, 8, vs2); + setArg(call_vector_vector_ww_2151, 9, vs1); + setArg(call_vector_vector_ww_2151, 10, vector_vector_ww_2151_arg10); + } + cc.bind(label_merge); + } + auto tmp2153 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2153, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2153, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 492); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 493: VWADD__WX */ + continuation_e __vwadd__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwadd.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADD__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 493); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2154; + x86::Gp ret_val_get_sew_pow_2154 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2154, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2155 = get_reg(cc, 8, false); + mov(cc, tmp2155, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2155, ret_val_get_sew_pow_2154)), 8, false), ~ 1); + setArg(call_get_sew_pow_2154, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2154, 0, ret_val_get_sew_pow_2154); + InvokeNode* call_get_lmul_pow_2156; + x86::Gp ret_val_get_lmul_pow_2156 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2156, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2156; + setArg(call_get_lmul_pow_2156, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2156, 0, ret_val_get_lmul_pow_2156); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2157; + auto illegal_variable_width_2157_arg2 = SEW_widen; + auto illegal_variable_width_2157_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2157 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2157, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_variable_width_2157; + setArg(call_illegal_variable_width_2157, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2157, 1, vd); + setArg(call_illegal_variable_width_2157, 2, vm); + setArg(call_illegal_variable_width_2157, 3, illegal_variable_width_2157_arg2); + setArg(call_illegal_variable_width_2157, 4, illegal_variable_width_2157_arg3); + setRet(call_illegal_variable_width_2157, 0, ret_val_illegal_variable_width_2157); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2159; + x86::Gp ret_val_sew_2159 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2159, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_ww_2158; + auto vector_imm_ww_2158_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_ww_2158_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_ww_2158_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_ww_2158_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_ww_2158_arg10 = ret_val_sew_2159; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_ww_2158, &vector_imm_ww, FuncSignature::build()); + setArg(call_sew_2159, 0, reinterpret_cast(this)); + setRet(call_sew_2159, 0, ret_val_sew_2159); + setArg(call_vector_imm_ww_2158, 0, V); + setArg(call_vector_imm_ww_2158, 1, 53); + setArg(call_vector_imm_ww_2158, 2, 6); + setArg(call_vector_imm_ww_2158, 3, vector_imm_ww_2158_arg3); + setArg(call_vector_imm_ww_2158, 4, vector_imm_ww_2158_arg4); + setArg(call_vector_imm_ww_2158, 5, vector_imm_ww_2158_arg5); + setArg(call_vector_imm_ww_2158, 6, vm); + setArg(call_vector_imm_ww_2158, 7, vd); + setArg(call_vector_imm_ww_2158, 8, vs2); + setArg(call_vector_imm_ww_2158, 9, vector_imm_ww_2158_arg9); + setArg(call_vector_imm_ww_2158, 10, vector_imm_ww_2158_arg10); + } + cc.bind(label_merge); + } + auto tmp2160 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2160, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2160, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 493); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 494: VWSUB__WV */ + continuation_e __vwsub__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsub.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUB__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 494); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2161; + x86::Gp ret_val_get_sew_pow_2161 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2161, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2162 = get_reg(cc, 8, false); + mov(cc, tmp2162, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2162, ret_val_get_sew_pow_2161)), 8, false), ~ 1); + setArg(call_get_sew_pow_2161, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2161, 0, ret_val_get_sew_pow_2161); + InvokeNode* call_get_lmul_pow_2163; + x86::Gp ret_val_get_lmul_pow_2163 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2163, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2163; + setArg(call_get_lmul_pow_2163, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2163, 0, ret_val_get_lmul_pow_2163); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2164; + auto illegal_variable_width_2164_arg2 = SEW_widen; + auto illegal_variable_width_2164_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2164 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2164, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2165; + auto valid_reg_overlap_2165_arg2 = LMUL_pow; + auto valid_reg_overlap_2165_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2165 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2165, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, bor, ret_val_illegal_variable_width_2164, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2165)); + setArg(call_illegal_variable_width_2164, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2164, 1, vd); + setArg(call_illegal_variable_width_2164, 2, vm); + setArg(call_illegal_variable_width_2164, 3, illegal_variable_width_2164_arg2); + setArg(call_illegal_variable_width_2164, 4, illegal_variable_width_2164_arg3); + setRet(call_illegal_variable_width_2164, 0, ret_val_illegal_variable_width_2164); + setArg(call_valid_reg_overlap_2165, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2165, 1, vs1); + setArg(call_valid_reg_overlap_2165, 2, vd); + setArg(call_valid_reg_overlap_2165, 3, valid_reg_overlap_2165_arg2); + setArg(call_valid_reg_overlap_2165, 4, valid_reg_overlap_2165_arg3); + setRet(call_valid_reg_overlap_2165, 0, ret_val_valid_reg_overlap_2165); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2167; + x86::Gp ret_val_sew_2167 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2167, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_ww_2166; + auto vector_vector_ww_2166_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_ww_2166_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_ww_2166_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_ww_2166_arg10 = ret_val_sew_2167; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_ww_2166, &vector_vector_ww, FuncSignature::build()); + setArg(call_sew_2167, 0, reinterpret_cast(this)); + setRet(call_sew_2167, 0, ret_val_sew_2167); + setArg(call_vector_vector_ww_2166, 0, V); + setArg(call_vector_vector_ww_2166, 1, 55); + setArg(call_vector_vector_ww_2166, 2, 2); + setArg(call_vector_vector_ww_2166, 3, vector_vector_ww_2166_arg3); + setArg(call_vector_vector_ww_2166, 4, vector_vector_ww_2166_arg4); + setArg(call_vector_vector_ww_2166, 5, vector_vector_ww_2166_arg5); + setArg(call_vector_vector_ww_2166, 6, vm); + setArg(call_vector_vector_ww_2166, 7, vd); + setArg(call_vector_vector_ww_2166, 8, vs2); + setArg(call_vector_vector_ww_2166, 9, vs1); + setArg(call_vector_vector_ww_2166, 10, vector_vector_ww_2166_arg10); + } + cc.bind(label_merge); + } + auto tmp2168 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2168, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2168, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 494); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 495: VWSUB__WX */ + continuation_e __vwsub__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsub.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUB__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 495); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2169; + x86::Gp ret_val_get_sew_pow_2169 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2169, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2170 = get_reg(cc, 8, false); + mov(cc, tmp2170, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2170, ret_val_get_sew_pow_2169)), 8, false), ~ 1); + setArg(call_get_sew_pow_2169, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2169, 0, ret_val_get_sew_pow_2169); + InvokeNode* call_get_lmul_pow_2171; + x86::Gp ret_val_get_lmul_pow_2171 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2171, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2171; + setArg(call_get_lmul_pow_2171, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2171, 0, ret_val_get_lmul_pow_2171); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2172; + auto illegal_variable_width_2172_arg2 = SEW_widen; + auto illegal_variable_width_2172_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2172 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2172, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_variable_width_2172; + setArg(call_illegal_variable_width_2172, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2172, 1, vd); + setArg(call_illegal_variable_width_2172, 2, vm); + setArg(call_illegal_variable_width_2172, 3, illegal_variable_width_2172_arg2); + setArg(call_illegal_variable_width_2172, 4, illegal_variable_width_2172_arg3); + setRet(call_illegal_variable_width_2172, 0, ret_val_illegal_variable_width_2172); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2174; + x86::Gp ret_val_sew_2174 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2174, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_ww_2173; + auto vector_imm_ww_2173_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_ww_2173_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_ww_2173_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_ww_2173_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_ww_2173_arg10 = ret_val_sew_2174; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_ww_2173, &vector_imm_ww, FuncSignature::build()); + setArg(call_sew_2174, 0, reinterpret_cast(this)); + setRet(call_sew_2174, 0, ret_val_sew_2174); + setArg(call_vector_imm_ww_2173, 0, V); + setArg(call_vector_imm_ww_2173, 1, 55); + setArg(call_vector_imm_ww_2173, 2, 6); + setArg(call_vector_imm_ww_2173, 3, vector_imm_ww_2173_arg3); + setArg(call_vector_imm_ww_2173, 4, vector_imm_ww_2173_arg4); + setArg(call_vector_imm_ww_2173, 5, vector_imm_ww_2173_arg5); + setArg(call_vector_imm_ww_2173, 6, vm); + setArg(call_vector_imm_ww_2173, 7, vd); + setArg(call_vector_imm_ww_2173, 8, vs2); + setArg(call_vector_imm_ww_2173, 9, vector_imm_ww_2173_arg9); + setArg(call_vector_imm_ww_2173, 10, vector_imm_ww_2173_arg10); + } + cc.bind(label_merge); + } + auto tmp2175 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2175, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2175, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 495); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 496: VZEXT__VF2 */ + continuation_e __vzext__vf2(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf2"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VZEXT__VF2_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 496); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2176; + x86::Gp ret_val_get_sew_pow_2176 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2176, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2176; + setArg(call_get_sew_pow_2176, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2176, 0, ret_val_get_sew_pow_2176); + auto tmp2177 = get_reg(cc, 8, false); + mov(cc, tmp2177, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2177, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2178; + x86::Gp ret_val_get_lmul_pow_2178 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2178, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2178; + setArg(call_get_lmul_pow_2178, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2178, 0, ret_val_get_lmul_pow_2178); + auto SEW_target = gen_operation(cc, udiv, SEW, 2); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2179; + auto illegal_variable_width_2179_arg2 = SEW_target; + auto illegal_variable_width_2179_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2179 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2179, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2180; + auto valid_reg_overlap_2180_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2180_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2180 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2180, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2179, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2180)); + setArg(call_illegal_variable_width_2179, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2179, 1, vd); + setArg(call_illegal_variable_width_2179, 2, vm); + setArg(call_illegal_variable_width_2179, 3, illegal_variable_width_2179_arg2); + setArg(call_illegal_variable_width_2179, 4, illegal_variable_width_2179_arg3); + setRet(call_illegal_variable_width_2179, 0, ret_val_illegal_variable_width_2179); + setArg(call_valid_reg_overlap_2180, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2180, 1, vs2); + setArg(call_valid_reg_overlap_2180, 2, vd); + setArg(call_valid_reg_overlap_2180, 3, valid_reg_overlap_2180_arg2); + setArg(call_valid_reg_overlap_2180, 4, valid_reg_overlap_2180_arg3); + setRet(call_valid_reg_overlap_2180, 0, ret_val_valid_reg_overlap_2180); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2181; + auto vector_extend_2181_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2181_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2181_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2181_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2181, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2181, 0, V); + setArg(call_vector_extend_2181, 1, 6); + setArg(call_vector_extend_2181, 2, vector_extend_2181_arg2); + setArg(call_vector_extend_2181, 3, vector_extend_2181_arg3); + setArg(call_vector_extend_2181, 4, vector_extend_2181_arg4); + setArg(call_vector_extend_2181, 5, vm); + setArg(call_vector_extend_2181, 6, vd); + setArg(call_vector_extend_2181, 7, vs2); + setArg(call_vector_extend_2181, 8, vector_extend_2181_arg8); + setArg(call_vector_extend_2181, 9, 1); + } + cc.bind(label_merge); + } + auto tmp2182 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2182, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2182, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 496); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 497: VSEXT__VF2 */ + continuation_e __vsext__vf2(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf2"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSEXT__VF2_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 497); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2183; + x86::Gp ret_val_get_sew_pow_2183 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2183, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2183; + setArg(call_get_sew_pow_2183, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2183, 0, ret_val_get_sew_pow_2183); + auto tmp2184 = get_reg(cc, 8, false); + mov(cc, tmp2184, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2184, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2185; + x86::Gp ret_val_get_lmul_pow_2185 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2185, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2185; + setArg(call_get_lmul_pow_2185, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2185, 0, ret_val_get_lmul_pow_2185); + auto SEW_target = gen_operation(cc, udiv, SEW, 2); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2186; + auto illegal_variable_width_2186_arg2 = SEW_target; + auto illegal_variable_width_2186_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2186 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2186, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2187; + auto valid_reg_overlap_2187_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2187_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2187 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2187, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2186, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2187)); + setArg(call_illegal_variable_width_2186, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2186, 1, vd); + setArg(call_illegal_variable_width_2186, 2, vm); + setArg(call_illegal_variable_width_2186, 3, illegal_variable_width_2186_arg2); + setArg(call_illegal_variable_width_2186, 4, illegal_variable_width_2186_arg3); + setRet(call_illegal_variable_width_2186, 0, ret_val_illegal_variable_width_2186); + setArg(call_valid_reg_overlap_2187, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2187, 1, vs2); + setArg(call_valid_reg_overlap_2187, 2, vd); + setArg(call_valid_reg_overlap_2187, 3, valid_reg_overlap_2187_arg2); + setArg(call_valid_reg_overlap_2187, 4, valid_reg_overlap_2187_arg3); + setRet(call_valid_reg_overlap_2187, 0, ret_val_valid_reg_overlap_2187); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2188; + auto vector_extend_2188_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2188_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2188_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2188_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2188, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2188, 0, V); + setArg(call_vector_extend_2188, 1, 7); + setArg(call_vector_extend_2188, 2, vector_extend_2188_arg2); + setArg(call_vector_extend_2188, 3, vector_extend_2188_arg3); + setArg(call_vector_extend_2188, 4, vector_extend_2188_arg4); + setArg(call_vector_extend_2188, 5, vm); + setArg(call_vector_extend_2188, 6, vd); + setArg(call_vector_extend_2188, 7, vs2); + setArg(call_vector_extend_2188, 8, vector_extend_2188_arg8); + setArg(call_vector_extend_2188, 9, 1); + } + cc.bind(label_merge); + } + auto tmp2189 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2189, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2189, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 497); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 498: VZEXT__VF4 */ + continuation_e __vzext__vf4(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf4"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VZEXT__VF4_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 498); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2190; + x86::Gp ret_val_get_sew_pow_2190 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2190, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2190; + setArg(call_get_sew_pow_2190, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2190, 0, ret_val_get_sew_pow_2190); + auto tmp2191 = get_reg(cc, 8, false); + mov(cc, tmp2191, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2191, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2192; + x86::Gp ret_val_get_lmul_pow_2192 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2192, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2192; + setArg(call_get_lmul_pow_2192, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2192, 0, ret_val_get_lmul_pow_2192); + auto SEW_target = gen_operation(cc, udiv, SEW, 4); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 2); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2193; + auto illegal_variable_width_2193_arg2 = SEW_target; + auto illegal_variable_width_2193_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2193 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2193, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2194; + auto valid_reg_overlap_2194_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2194_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2194 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2194, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2193, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2194)); + setArg(call_illegal_variable_width_2193, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2193, 1, vd); + setArg(call_illegal_variable_width_2193, 2, vm); + setArg(call_illegal_variable_width_2193, 3, illegal_variable_width_2193_arg2); + setArg(call_illegal_variable_width_2193, 4, illegal_variable_width_2193_arg3); + setRet(call_illegal_variable_width_2193, 0, ret_val_illegal_variable_width_2193); + setArg(call_valid_reg_overlap_2194, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2194, 1, vs2); + setArg(call_valid_reg_overlap_2194, 2, vd); + setArg(call_valid_reg_overlap_2194, 3, valid_reg_overlap_2194_arg2); + setArg(call_valid_reg_overlap_2194, 4, valid_reg_overlap_2194_arg3); + setRet(call_valid_reg_overlap_2194, 0, ret_val_valid_reg_overlap_2194); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2195; + auto vector_extend_2195_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2195_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2195_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2195_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2195, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2195, 0, V); + setArg(call_vector_extend_2195, 1, 4); + setArg(call_vector_extend_2195, 2, vector_extend_2195_arg2); + setArg(call_vector_extend_2195, 3, vector_extend_2195_arg3); + setArg(call_vector_extend_2195, 4, vector_extend_2195_arg4); + setArg(call_vector_extend_2195, 5, vm); + setArg(call_vector_extend_2195, 6, vd); + setArg(call_vector_extend_2195, 7, vs2); + setArg(call_vector_extend_2195, 8, vector_extend_2195_arg8); + setArg(call_vector_extend_2195, 9, 2); + } + cc.bind(label_merge); + } + auto tmp2196 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2196, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2196, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 498); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 499: VSEXT__VF4 */ + continuation_e __vsext__vf4(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf4"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSEXT__VF4_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 499); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2197; + x86::Gp ret_val_get_sew_pow_2197 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2197, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2197; + setArg(call_get_sew_pow_2197, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2197, 0, ret_val_get_sew_pow_2197); + auto tmp2198 = get_reg(cc, 8, false); + mov(cc, tmp2198, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2198, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2199; + x86::Gp ret_val_get_lmul_pow_2199 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2199, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2199; + setArg(call_get_lmul_pow_2199, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2199, 0, ret_val_get_lmul_pow_2199); + auto SEW_target = gen_operation(cc, udiv, SEW, 4); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 2); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2200; + auto illegal_variable_width_2200_arg2 = SEW_target; + auto illegal_variable_width_2200_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2200 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2200, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2201; + auto valid_reg_overlap_2201_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2201_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2201 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2201, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2200, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2201)); + setArg(call_illegal_variable_width_2200, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2200, 1, vd); + setArg(call_illegal_variable_width_2200, 2, vm); + setArg(call_illegal_variable_width_2200, 3, illegal_variable_width_2200_arg2); + setArg(call_illegal_variable_width_2200, 4, illegal_variable_width_2200_arg3); + setRet(call_illegal_variable_width_2200, 0, ret_val_illegal_variable_width_2200); + setArg(call_valid_reg_overlap_2201, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2201, 1, vs2); + setArg(call_valid_reg_overlap_2201, 2, vd); + setArg(call_valid_reg_overlap_2201, 3, valid_reg_overlap_2201_arg2); + setArg(call_valid_reg_overlap_2201, 4, valid_reg_overlap_2201_arg3); + setRet(call_valid_reg_overlap_2201, 0, ret_val_valid_reg_overlap_2201); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2202; + auto vector_extend_2202_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2202_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2202_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2202_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2202, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2202, 0, V); + setArg(call_vector_extend_2202, 1, 5); + setArg(call_vector_extend_2202, 2, vector_extend_2202_arg2); + setArg(call_vector_extend_2202, 3, vector_extend_2202_arg3); + setArg(call_vector_extend_2202, 4, vector_extend_2202_arg4); + setArg(call_vector_extend_2202, 5, vm); + setArg(call_vector_extend_2202, 6, vd); + setArg(call_vector_extend_2202, 7, vs2); + setArg(call_vector_extend_2202, 8, vector_extend_2202_arg8); + setArg(call_vector_extend_2202, 9, 2); + } + cc.bind(label_merge); + } + auto tmp2203 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2203, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2203, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 499); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 500: VZEXT__VF8 */ + continuation_e __vzext__vf8(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf8"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VZEXT__VF8_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 500); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2204; + x86::Gp ret_val_get_sew_pow_2204 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2204, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2204; + setArg(call_get_sew_pow_2204, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2204, 0, ret_val_get_sew_pow_2204); + auto tmp2205 = get_reg(cc, 8, false); + mov(cc, tmp2205, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2205, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2206; + x86::Gp ret_val_get_lmul_pow_2206 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2206, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2206; + setArg(call_get_lmul_pow_2206, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2206, 0, ret_val_get_lmul_pow_2206); + auto SEW_target = gen_operation(cc, udiv, SEW, 8); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 3); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2207; + auto illegal_variable_width_2207_arg2 = SEW_target; + auto illegal_variable_width_2207_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2207 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2207, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2208; + auto valid_reg_overlap_2208_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2208_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2208 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2208, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2207, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2208)); + setArg(call_illegal_variable_width_2207, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2207, 1, vd); + setArg(call_illegal_variable_width_2207, 2, vm); + setArg(call_illegal_variable_width_2207, 3, illegal_variable_width_2207_arg2); + setArg(call_illegal_variable_width_2207, 4, illegal_variable_width_2207_arg3); + setRet(call_illegal_variable_width_2207, 0, ret_val_illegal_variable_width_2207); + setArg(call_valid_reg_overlap_2208, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2208, 1, vs2); + setArg(call_valid_reg_overlap_2208, 2, vd); + setArg(call_valid_reg_overlap_2208, 3, valid_reg_overlap_2208_arg2); + setArg(call_valid_reg_overlap_2208, 4, valid_reg_overlap_2208_arg3); + setRet(call_valid_reg_overlap_2208, 0, ret_val_valid_reg_overlap_2208); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2209; + auto vector_extend_2209_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2209_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2209_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2209_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2209, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2209, 0, V); + setArg(call_vector_extend_2209, 1, 2); + setArg(call_vector_extend_2209, 2, vector_extend_2209_arg2); + setArg(call_vector_extend_2209, 3, vector_extend_2209_arg3); + setArg(call_vector_extend_2209, 4, vector_extend_2209_arg4); + setArg(call_vector_extend_2209, 5, vm); + setArg(call_vector_extend_2209, 6, vd); + setArg(call_vector_extend_2209, 7, vs2); + setArg(call_vector_extend_2209, 8, vector_extend_2209_arg8); + setArg(call_vector_extend_2209, 9, 3); + } + cc.bind(label_merge); + } + auto tmp2210 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2210, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2210, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 500); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 501: VSEXT__VF8 */ + continuation_e __vsext__vf8(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf8"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSEXT__VF8_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 501); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2211; + x86::Gp ret_val_get_sew_pow_2211 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2211, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2211; + setArg(call_get_sew_pow_2211, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2211, 0, ret_val_get_sew_pow_2211); + auto tmp2212 = get_reg(cc, 8, false); + mov(cc, tmp2212, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2212, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2213; + x86::Gp ret_val_get_lmul_pow_2213 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2213, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2213; + setArg(call_get_lmul_pow_2213, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2213, 0, ret_val_get_lmul_pow_2213); + auto SEW_target = gen_operation(cc, udiv, SEW, 8); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 3); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2214; + auto illegal_variable_width_2214_arg2 = SEW_target; + auto illegal_variable_width_2214_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2214 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2214, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2215; + auto valid_reg_overlap_2215_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2215_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2215 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2215, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2214, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2215)); + setArg(call_illegal_variable_width_2214, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2214, 1, vd); + setArg(call_illegal_variable_width_2214, 2, vm); + setArg(call_illegal_variable_width_2214, 3, illegal_variable_width_2214_arg2); + setArg(call_illegal_variable_width_2214, 4, illegal_variable_width_2214_arg3); + setRet(call_illegal_variable_width_2214, 0, ret_val_illegal_variable_width_2214); + setArg(call_valid_reg_overlap_2215, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2215, 1, vs2); + setArg(call_valid_reg_overlap_2215, 2, vd); + setArg(call_valid_reg_overlap_2215, 3, valid_reg_overlap_2215_arg2); + setArg(call_valid_reg_overlap_2215, 4, valid_reg_overlap_2215_arg3); + setRet(call_valid_reg_overlap_2215, 0, ret_val_valid_reg_overlap_2215); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2216; + auto vector_extend_2216_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2216_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2216_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2216_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2216, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2216, 0, V); + setArg(call_vector_extend_2216, 1, 3); + setArg(call_vector_extend_2216, 2, vector_extend_2216_arg2); + setArg(call_vector_extend_2216, 3, vector_extend_2216_arg3); + setArg(call_vector_extend_2216, 4, vector_extend_2216_arg4); + setArg(call_vector_extend_2216, 5, vm); + setArg(call_vector_extend_2216, 6, vd); + setArg(call_vector_extend_2216, 7, vs2); + setArg(call_vector_extend_2216, 8, vector_extend_2216_arg8); + setArg(call_vector_extend_2216, 9, 3); + } + cc.bind(label_merge); + } + auto tmp2217 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2217, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2217, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 501); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 502: VADC__VVM */ + continuation_e __vadc__vvm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vadc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADC__VVM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 502); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2218; + x86::Gp ret_val_illegal_vd_masked_2218 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2218, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_masked_2218; + setArg(call_illegal_vd_masked_2218, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2218, 1, vd); + setRet(call_illegal_vd_masked_2218, 0, ret_val_illegal_vd_masked_2218); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2220; + x86::Gp ret_val_sew_2220 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2220, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_carry_2219; + auto vector_vector_carry_2219_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_carry_2219_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_carry_2219_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_carry_2219_arg9 = ret_val_sew_2220; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_carry_2219, &vector_vector_carry, FuncSignature::build()); + setArg(call_sew_2220, 0, reinterpret_cast(this)); + setRet(call_sew_2220, 0, ret_val_sew_2220); + setArg(call_vector_vector_carry_2219, 0, V); + setArg(call_vector_vector_carry_2219, 1, 16); + setArg(call_vector_vector_carry_2219, 2, 0); + setArg(call_vector_vector_carry_2219, 3, vector_vector_carry_2219_arg3); + setArg(call_vector_vector_carry_2219, 4, vector_vector_carry_2219_arg4); + setArg(call_vector_vector_carry_2219, 5, vector_vector_carry_2219_arg5); + setArg(call_vector_vector_carry_2219, 6, vd); + setArg(call_vector_vector_carry_2219, 7, vs2); + setArg(call_vector_vector_carry_2219, 8, vs1); + setArg(call_vector_vector_carry_2219, 9, vector_vector_carry_2219_arg9); + setArg(call_vector_vector_carry_2219, 10, 1); + } + cc.bind(label_merge); + } + auto tmp2221 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2221, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2221, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 502); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 503: VADC__VXM */ + continuation_e __vadc__vxm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vadc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADC__VXM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 503); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2222; + x86::Gp ret_val_illegal_vd_masked_2222 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2222, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto tmp2223 = get_reg(cc, 8, false); + mov(cc, tmp2223, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2223, ret_val_illegal_vd_masked_2222); + setArg(call_illegal_vd_masked_2222, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2222, 1, vd); + setRet(call_illegal_vd_masked_2222, 0, ret_val_illegal_vd_masked_2222); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2225; + x86::Gp ret_val_sew_2225 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2225, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_carry_2224; + auto vector_imm_carry_2224_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_carry_2224_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_carry_2224_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_carry_2224_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_carry_2224_arg9 = ret_val_sew_2225; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_carry_2224, &vector_imm_carry, FuncSignature::build()); + setArg(call_sew_2225, 0, reinterpret_cast(this)); + setRet(call_sew_2225, 0, ret_val_sew_2225); + setArg(call_vector_imm_carry_2224, 0, V); + setArg(call_vector_imm_carry_2224, 1, 16); + setArg(call_vector_imm_carry_2224, 2, 4); + setArg(call_vector_imm_carry_2224, 3, vector_imm_carry_2224_arg3); + setArg(call_vector_imm_carry_2224, 4, vector_imm_carry_2224_arg4); + setArg(call_vector_imm_carry_2224, 5, vector_imm_carry_2224_arg5); + setArg(call_vector_imm_carry_2224, 6, vd); + setArg(call_vector_imm_carry_2224, 7, vs2); + setArg(call_vector_imm_carry_2224, 8, vector_imm_carry_2224_arg8); + setArg(call_vector_imm_carry_2224, 9, vector_imm_carry_2224_arg9); + setArg(call_vector_imm_carry_2224, 10, 1); + } + cc.bind(label_merge); + } + auto tmp2226 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2226, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2226, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 503); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 504: VADC__VIM */ + continuation_e __vadc__vim(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, v0", fmt::arg("mnemonic", "vadc.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADC__VIM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 504); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2227; + x86::Gp ret_val_illegal_vd_unmasked_2227 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2227, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2227; + setArg(call_illegal_vd_unmasked_2227, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2227, 0, ret_val_illegal_vd_unmasked_2227); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2229; + x86::Gp ret_val_sew_2229 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2229, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_carry_2228; + auto vector_imm_carry_2228_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_carry_2228_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_carry_2228_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_carry_2228_arg9 = ret_val_sew_2229; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_carry_2228, &vector_imm_carry, FuncSignature::build()); + setArg(call_sew_2229, 0, reinterpret_cast(this)); + setRet(call_sew_2229, 0, ret_val_sew_2229); + setArg(call_vector_imm_carry_2228, 0, V); + setArg(call_vector_imm_carry_2228, 1, 16); + setArg(call_vector_imm_carry_2228, 2, 3); + setArg(call_vector_imm_carry_2228, 3, vector_imm_carry_2228_arg3); + setArg(call_vector_imm_carry_2228, 4, vector_imm_carry_2228_arg4); + setArg(call_vector_imm_carry_2228, 5, vector_imm_carry_2228_arg5); + setArg(call_vector_imm_carry_2228, 6, vd); + setArg(call_vector_imm_carry_2228, 7, vs2); + setArg(call_vector_imm_carry_2228, 8, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_carry_2228, 9, vector_imm_carry_2228_arg9); + setArg(call_vector_imm_carry_2228, 10, 1); + } + cc.bind(label_merge); + } + auto tmp2230 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2230, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2230, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 504); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 505: VMADC__VVM */ + continuation_e __vmadc__vvm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vmadc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VVM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 505); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2231; + x86::Gp ret_val_illegal_vd_unmasked_2231 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2231, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2231; + setArg(call_illegal_vd_unmasked_2231, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2231, 0, ret_val_illegal_vd_unmasked_2231); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2233; + x86::Gp ret_val_sew_2233 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2233, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_vector_op_2232; + auto carry_vector_vector_op_2232_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_vector_op_2232_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_vector_op_2232_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_vector_op_2232_arg9 = ret_val_sew_2233; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_vector_op_2232, &carry_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2233, 0, reinterpret_cast(this)); + setRet(call_sew_2233, 0, ret_val_sew_2233); + setArg(call_carry_vector_vector_op_2232, 0, V); + setArg(call_carry_vector_vector_op_2232, 1, 17); + setArg(call_carry_vector_vector_op_2232, 2, carry_vector_vector_op_2232_arg2); + setArg(call_carry_vector_vector_op_2232, 3, carry_vector_vector_op_2232_arg3); + setArg(call_carry_vector_vector_op_2232, 4, carry_vector_vector_op_2232_arg4); + setArg(call_carry_vector_vector_op_2232, 5, 0); + setArg(call_carry_vector_vector_op_2232, 6, vd); + setArg(call_carry_vector_vector_op_2232, 7, vs2); + setArg(call_carry_vector_vector_op_2232, 8, vs1); + setArg(call_carry_vector_vector_op_2232, 9, carry_vector_vector_op_2232_arg9); + } + cc.bind(label_merge); + } + auto tmp2234 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2234, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2234, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 505); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 506: VMADC__VXM */ + continuation_e __vmadc__vxm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vmadc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VXM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 506); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2235; + x86::Gp ret_val_illegal_vd_unmasked_2235 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2235, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2236 = get_reg(cc, 8, false); + mov(cc, tmp2236, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2236, ret_val_illegal_vd_unmasked_2235); + setArg(call_illegal_vd_unmasked_2235, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2235, 0, ret_val_illegal_vd_unmasked_2235); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2238; + x86::Gp ret_val_sew_2238 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2238, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2237; + auto carry_vector_imm_op_2237_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2237_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2237_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2237_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto carry_vector_imm_op_2237_arg9 = ret_val_sew_2238; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2237, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2238, 0, reinterpret_cast(this)); + setRet(call_sew_2238, 0, ret_val_sew_2238); + setArg(call_carry_vector_imm_op_2237, 0, V); + setArg(call_carry_vector_imm_op_2237, 1, 17); + setArg(call_carry_vector_imm_op_2237, 2, carry_vector_imm_op_2237_arg2); + setArg(call_carry_vector_imm_op_2237, 3, carry_vector_imm_op_2237_arg3); + setArg(call_carry_vector_imm_op_2237, 4, carry_vector_imm_op_2237_arg4); + setArg(call_carry_vector_imm_op_2237, 5, 0); + setArg(call_carry_vector_imm_op_2237, 6, vd); + setArg(call_carry_vector_imm_op_2237, 7, vs2); + setArg(call_carry_vector_imm_op_2237, 8, carry_vector_imm_op_2237_arg8); + setArg(call_carry_vector_imm_op_2237, 9, carry_vector_imm_op_2237_arg9); + } + cc.bind(label_merge); + } + auto tmp2239 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2239, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2239, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 506); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 507: VMADC__VIM */ + continuation_e __vmadc__vim(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, v0", fmt::arg("mnemonic", "vmadc.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VIM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 507); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2240; + x86::Gp ret_val_illegal_vd_unmasked_2240 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2240, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2240; + setArg(call_illegal_vd_unmasked_2240, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2240, 0, ret_val_illegal_vd_unmasked_2240); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2242; + x86::Gp ret_val_sew_2242 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2242, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2241; + auto carry_vector_imm_op_2241_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2241_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2241_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2241_arg9 = ret_val_sew_2242; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2241, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2242, 0, reinterpret_cast(this)); + setRet(call_sew_2242, 0, ret_val_sew_2242); + setArg(call_carry_vector_imm_op_2241, 0, V); + setArg(call_carry_vector_imm_op_2241, 1, 17); + setArg(call_carry_vector_imm_op_2241, 2, carry_vector_imm_op_2241_arg2); + setArg(call_carry_vector_imm_op_2241, 3, carry_vector_imm_op_2241_arg3); + setArg(call_carry_vector_imm_op_2241, 4, carry_vector_imm_op_2241_arg4); + setArg(call_carry_vector_imm_op_2241, 5, 0); + setArg(call_carry_vector_imm_op_2241, 6, vd); + setArg(call_carry_vector_imm_op_2241, 7, vs2); + setArg(call_carry_vector_imm_op_2241, 8, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_carry_vector_imm_op_2241, 9, carry_vector_imm_op_2241_arg9); + } + cc.bind(label_merge); + } + auto tmp2243 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2243, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2243, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 507); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 508: VMADC__VV */ + continuation_e __vmadc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmadc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 508); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2244; + x86::Gp ret_val_illegal_vd_unmasked_2244 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2244, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2244; + setArg(call_illegal_vd_unmasked_2244, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2244, 0, ret_val_illegal_vd_unmasked_2244); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2246; + x86::Gp ret_val_sew_2246 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2246, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_vector_op_2245; + auto carry_vector_vector_op_2245_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_vector_op_2245_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_vector_op_2245_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_vector_op_2245_arg9 = ret_val_sew_2246; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_vector_op_2245, &carry_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2246, 0, reinterpret_cast(this)); + setRet(call_sew_2246, 0, ret_val_sew_2246); + setArg(call_carry_vector_vector_op_2245, 0, V); + setArg(call_carry_vector_vector_op_2245, 1, 17); + setArg(call_carry_vector_vector_op_2245, 2, carry_vector_vector_op_2245_arg2); + setArg(call_carry_vector_vector_op_2245, 3, carry_vector_vector_op_2245_arg3); + setArg(call_carry_vector_vector_op_2245, 4, carry_vector_vector_op_2245_arg4); + setArg(call_carry_vector_vector_op_2245, 5, 1); + setArg(call_carry_vector_vector_op_2245, 6, vd); + setArg(call_carry_vector_vector_op_2245, 7, vs2); + setArg(call_carry_vector_vector_op_2245, 8, vs1); + setArg(call_carry_vector_vector_op_2245, 9, carry_vector_vector_op_2245_arg9); + } + cc.bind(label_merge); + } + auto tmp2247 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2247, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2247, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 508); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 509: VMADC__VX */ + continuation_e __vmadc__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmadc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 509); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2248; + x86::Gp ret_val_illegal_vd_unmasked_2248 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2248, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2249 = get_reg(cc, 8, false); + mov(cc, tmp2249, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2249, ret_val_illegal_vd_unmasked_2248); + setArg(call_illegal_vd_unmasked_2248, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2248, 0, ret_val_illegal_vd_unmasked_2248); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2251; + x86::Gp ret_val_sew_2251 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2251, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2250; + auto carry_vector_imm_op_2250_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2250_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2250_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2250_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto carry_vector_imm_op_2250_arg9 = ret_val_sew_2251; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2250, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2251, 0, reinterpret_cast(this)); + setRet(call_sew_2251, 0, ret_val_sew_2251); + setArg(call_carry_vector_imm_op_2250, 0, V); + setArg(call_carry_vector_imm_op_2250, 1, 17); + setArg(call_carry_vector_imm_op_2250, 2, carry_vector_imm_op_2250_arg2); + setArg(call_carry_vector_imm_op_2250, 3, carry_vector_imm_op_2250_arg3); + setArg(call_carry_vector_imm_op_2250, 4, carry_vector_imm_op_2250_arg4); + setArg(call_carry_vector_imm_op_2250, 5, 1); + setArg(call_carry_vector_imm_op_2250, 6, vd); + setArg(call_carry_vector_imm_op_2250, 7, vs2); + setArg(call_carry_vector_imm_op_2250, 8, carry_vector_imm_op_2250_arg8); + setArg(call_carry_vector_imm_op_2250, 9, carry_vector_imm_op_2250_arg9); + } + cc.bind(label_merge); + } + auto tmp2252 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2252, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2252, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 509); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 510: VMADC__VI */ + continuation_e __vmadc__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}", fmt::arg("mnemonic", "vmadc.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 510); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2253; + x86::Gp ret_val_illegal_vd_unmasked_2253 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2253, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2253; + setArg(call_illegal_vd_unmasked_2253, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2253, 0, ret_val_illegal_vd_unmasked_2253); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2255; + x86::Gp ret_val_sew_2255 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2255, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2254; + auto carry_vector_imm_op_2254_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2254_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2254_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2254_arg9 = ret_val_sew_2255; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2254, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2255, 0, reinterpret_cast(this)); + setRet(call_sew_2255, 0, ret_val_sew_2255); + setArg(call_carry_vector_imm_op_2254, 0, V); + setArg(call_carry_vector_imm_op_2254, 1, 17); + setArg(call_carry_vector_imm_op_2254, 2, carry_vector_imm_op_2254_arg2); + setArg(call_carry_vector_imm_op_2254, 3, carry_vector_imm_op_2254_arg3); + setArg(call_carry_vector_imm_op_2254, 4, carry_vector_imm_op_2254_arg4); + setArg(call_carry_vector_imm_op_2254, 5, 1); + setArg(call_carry_vector_imm_op_2254, 6, vd); + setArg(call_carry_vector_imm_op_2254, 7, vs2); + setArg(call_carry_vector_imm_op_2254, 8, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_carry_vector_imm_op_2254, 9, carry_vector_imm_op_2254_arg9); + } + cc.bind(label_merge); + } + auto tmp2256 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2256, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2256, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 510); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 511: VSBC__VVM */ + continuation_e __vsbc__vvm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vsbc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSBC__VVM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 511); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2257; + x86::Gp ret_val_illegal_vd_masked_2257 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2257, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_masked_2257; + setArg(call_illegal_vd_masked_2257, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2257, 1, vd); + setRet(call_illegal_vd_masked_2257, 0, ret_val_illegal_vd_masked_2257); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2259; + x86::Gp ret_val_sew_2259 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2259, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_carry_2258; + auto vector_vector_carry_2258_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_carry_2258_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_carry_2258_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_carry_2258_arg9 = ret_val_sew_2259; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_carry_2258, &vector_vector_carry, FuncSignature::build()); + setArg(call_sew_2259, 0, reinterpret_cast(this)); + setRet(call_sew_2259, 0, ret_val_sew_2259); + setArg(call_vector_vector_carry_2258, 0, V); + setArg(call_vector_vector_carry_2258, 1, 18); + setArg(call_vector_vector_carry_2258, 2, 0); + setArg(call_vector_vector_carry_2258, 3, vector_vector_carry_2258_arg3); + setArg(call_vector_vector_carry_2258, 4, vector_vector_carry_2258_arg4); + setArg(call_vector_vector_carry_2258, 5, vector_vector_carry_2258_arg5); + setArg(call_vector_vector_carry_2258, 6, vd); + setArg(call_vector_vector_carry_2258, 7, vs2); + setArg(call_vector_vector_carry_2258, 8, vs1); + setArg(call_vector_vector_carry_2258, 9, vector_vector_carry_2258_arg9); + setArg(call_vector_vector_carry_2258, 10, - 1); + } + cc.bind(label_merge); + } + auto tmp2260 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2260, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2260, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 511); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 512: VSBC__VXM */ + continuation_e __vsbc__vxm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vsbc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSBC__VXM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 512); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2261; + x86::Gp ret_val_illegal_vd_masked_2261 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2261, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto tmp2262 = get_reg(cc, 8, false); + mov(cc, tmp2262, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2262, ret_val_illegal_vd_masked_2261); + setArg(call_illegal_vd_masked_2261, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2261, 1, vd); + setRet(call_illegal_vd_masked_2261, 0, ret_val_illegal_vd_masked_2261); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2264; + x86::Gp ret_val_sew_2264 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2264, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_carry_2263; + auto vector_imm_carry_2263_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_carry_2263_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_carry_2263_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_carry_2263_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_carry_2263_arg9 = ret_val_sew_2264; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_carry_2263, &vector_imm_carry, FuncSignature::build()); + setArg(call_sew_2264, 0, reinterpret_cast(this)); + setRet(call_sew_2264, 0, ret_val_sew_2264); + setArg(call_vector_imm_carry_2263, 0, V); + setArg(call_vector_imm_carry_2263, 1, 18); + setArg(call_vector_imm_carry_2263, 2, 4); + setArg(call_vector_imm_carry_2263, 3, vector_imm_carry_2263_arg3); + setArg(call_vector_imm_carry_2263, 4, vector_imm_carry_2263_arg4); + setArg(call_vector_imm_carry_2263, 5, vector_imm_carry_2263_arg5); + setArg(call_vector_imm_carry_2263, 6, vd); + setArg(call_vector_imm_carry_2263, 7, vs2); + setArg(call_vector_imm_carry_2263, 8, vector_imm_carry_2263_arg8); + setArg(call_vector_imm_carry_2263, 9, vector_imm_carry_2263_arg9); + setArg(call_vector_imm_carry_2263, 10, - 1); + } + cc.bind(label_merge); + } + auto tmp2265 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2265, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2265, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 512); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 513: VMSBC__VVM */ + continuation_e __vmsbc__vvm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vmsbc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSBC__VVM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 513); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2266; + x86::Gp ret_val_illegal_vd_unmasked_2266 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2266, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2266; + setArg(call_illegal_vd_unmasked_2266, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2266, 0, ret_val_illegal_vd_unmasked_2266); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2268; + x86::Gp ret_val_sew_2268 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2268, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_vector_op_2267; + auto carry_vector_vector_op_2267_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_vector_op_2267_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_vector_op_2267_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_vector_op_2267_arg9 = ret_val_sew_2268; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_vector_op_2267, &carry_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2268, 0, reinterpret_cast(this)); + setRet(call_sew_2268, 0, ret_val_sew_2268); + setArg(call_carry_vector_vector_op_2267, 0, V); + setArg(call_carry_vector_vector_op_2267, 1, 19); + setArg(call_carry_vector_vector_op_2267, 2, carry_vector_vector_op_2267_arg2); + setArg(call_carry_vector_vector_op_2267, 3, carry_vector_vector_op_2267_arg3); + setArg(call_carry_vector_vector_op_2267, 4, carry_vector_vector_op_2267_arg4); + setArg(call_carry_vector_vector_op_2267, 5, 0); + setArg(call_carry_vector_vector_op_2267, 6, vd); + setArg(call_carry_vector_vector_op_2267, 7, vs2); + setArg(call_carry_vector_vector_op_2267, 8, vs1); + setArg(call_carry_vector_vector_op_2267, 9, carry_vector_vector_op_2267_arg9); + } + cc.bind(label_merge); + } + auto tmp2269 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2269, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2269, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 513); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 514: VMSBC__VXM */ + continuation_e __vmsbc__vxm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vmsbc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSBC__VXM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 514); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2270; + x86::Gp ret_val_illegal_vd_unmasked_2270 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2270, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2271 = get_reg(cc, 8, false); + mov(cc, tmp2271, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2271, ret_val_illegal_vd_unmasked_2270); + setArg(call_illegal_vd_unmasked_2270, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2270, 0, ret_val_illegal_vd_unmasked_2270); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2273; + x86::Gp ret_val_sew_2273 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2273, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2272; + auto carry_vector_imm_op_2272_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2272_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2272_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2272_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto carry_vector_imm_op_2272_arg9 = ret_val_sew_2273; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2272, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2273, 0, reinterpret_cast(this)); + setRet(call_sew_2273, 0, ret_val_sew_2273); + setArg(call_carry_vector_imm_op_2272, 0, V); + setArg(call_carry_vector_imm_op_2272, 1, 19); + setArg(call_carry_vector_imm_op_2272, 2, carry_vector_imm_op_2272_arg2); + setArg(call_carry_vector_imm_op_2272, 3, carry_vector_imm_op_2272_arg3); + setArg(call_carry_vector_imm_op_2272, 4, carry_vector_imm_op_2272_arg4); + setArg(call_carry_vector_imm_op_2272, 5, 0); + setArg(call_carry_vector_imm_op_2272, 6, vd); + setArg(call_carry_vector_imm_op_2272, 7, vs2); + setArg(call_carry_vector_imm_op_2272, 8, carry_vector_imm_op_2272_arg8); + setArg(call_carry_vector_imm_op_2272, 9, carry_vector_imm_op_2272_arg9); + } + cc.bind(label_merge); + } + auto tmp2274 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2274, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2274, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 514); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 515: VMSBC__VV */ + continuation_e __vmsbc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmsbc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSBC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 515); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2275; + x86::Gp ret_val_illegal_vd_unmasked_2275 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2275, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2275; + setArg(call_illegal_vd_unmasked_2275, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2275, 0, ret_val_illegal_vd_unmasked_2275); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2277; + x86::Gp ret_val_sew_2277 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2277, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_vector_op_2276; + auto carry_vector_vector_op_2276_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_vector_op_2276_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_vector_op_2276_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_vector_op_2276_arg9 = ret_val_sew_2277; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_vector_op_2276, &carry_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2277, 0, reinterpret_cast(this)); + setRet(call_sew_2277, 0, ret_val_sew_2277); + setArg(call_carry_vector_vector_op_2276, 0, V); + setArg(call_carry_vector_vector_op_2276, 1, 19); + setArg(call_carry_vector_vector_op_2276, 2, carry_vector_vector_op_2276_arg2); + setArg(call_carry_vector_vector_op_2276, 3, carry_vector_vector_op_2276_arg3); + setArg(call_carry_vector_vector_op_2276, 4, carry_vector_vector_op_2276_arg4); + setArg(call_carry_vector_vector_op_2276, 5, 1); + setArg(call_carry_vector_vector_op_2276, 6, vd); + setArg(call_carry_vector_vector_op_2276, 7, vs2); + setArg(call_carry_vector_vector_op_2276, 8, vs1); + setArg(call_carry_vector_vector_op_2276, 9, carry_vector_vector_op_2276_arg9); + } + cc.bind(label_merge); + } + auto tmp2278 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2278, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2278, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 515); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 516: VMSBC__VX */ + continuation_e __vmsbc__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmsbc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSBC__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 516); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2279; + x86::Gp ret_val_illegal_vd_unmasked_2279 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2279, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2280 = get_reg(cc, 8, false); + mov(cc, tmp2280, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2280, ret_val_illegal_vd_unmasked_2279); + setArg(call_illegal_vd_unmasked_2279, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2279, 0, ret_val_illegal_vd_unmasked_2279); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2282; + x86::Gp ret_val_sew_2282 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2282, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2281; + auto carry_vector_imm_op_2281_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2281_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2281_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2281_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto carry_vector_imm_op_2281_arg9 = ret_val_sew_2282; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2281, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2282, 0, reinterpret_cast(this)); + setRet(call_sew_2282, 0, ret_val_sew_2282); + setArg(call_carry_vector_imm_op_2281, 0, V); + setArg(call_carry_vector_imm_op_2281, 1, 19); + setArg(call_carry_vector_imm_op_2281, 2, carry_vector_imm_op_2281_arg2); + setArg(call_carry_vector_imm_op_2281, 3, carry_vector_imm_op_2281_arg3); + setArg(call_carry_vector_imm_op_2281, 4, carry_vector_imm_op_2281_arg4); + setArg(call_carry_vector_imm_op_2281, 5, 1); + setArg(call_carry_vector_imm_op_2281, 6, vd); + setArg(call_carry_vector_imm_op_2281, 7, vs2); + setArg(call_carry_vector_imm_op_2281, 8, carry_vector_imm_op_2281_arg8); + setArg(call_carry_vector_imm_op_2281, 9, carry_vector_imm_op_2281_arg9); + } + cc.bind(label_merge); + } + auto tmp2283 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2283, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2283, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 516); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 517: VAND__VI */ + continuation_e __vand__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vand.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAND__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 517); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2284; + x86::Gp ret_val_illegal_normal_2284 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2284, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2284; + setArg(call_illegal_normal_2284, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2284, 1, vd); + setArg(call_illegal_normal_2284, 2, vm); + setRet(call_illegal_normal_2284, 0, ret_val_illegal_normal_2284); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2286; + x86::Gp ret_val_sew_2286 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2286, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2285; + auto vector_imm_op_2285_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2285_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2285_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2285_arg10 = ret_val_sew_2286; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2285, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2286, 0, reinterpret_cast(this)); + setRet(call_sew_2286, 0, ret_val_sew_2286); + setArg(call_vector_imm_op_2285, 0, V); + setArg(call_vector_imm_op_2285, 1, 9); + setArg(call_vector_imm_op_2285, 2, 3); + setArg(call_vector_imm_op_2285, 3, vector_imm_op_2285_arg3); + setArg(call_vector_imm_op_2285, 4, vector_imm_op_2285_arg4); + setArg(call_vector_imm_op_2285, 5, vector_imm_op_2285_arg5); + setArg(call_vector_imm_op_2285, 6, vm); + setArg(call_vector_imm_op_2285, 7, vd); + setArg(call_vector_imm_op_2285, 8, vs2); + setArg(call_vector_imm_op_2285, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_op_2285, 10, vector_imm_op_2285_arg10); + } + cc.bind(label_merge); + } + auto tmp2287 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2287, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2287, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 517); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 518: VAND__VV */ + continuation_e __vand__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vand.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAND__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 518); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2288; + x86::Gp ret_val_illegal_normal_2288 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2288, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2288; + setArg(call_illegal_normal_2288, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2288, 1, vd); + setArg(call_illegal_normal_2288, 2, vm); + setRet(call_illegal_normal_2288, 0, ret_val_illegal_normal_2288); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2290; + x86::Gp ret_val_sew_2290 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2290, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2289; + auto vector_vector_op_2289_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2289_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2289_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2289_arg10 = ret_val_sew_2290; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2289, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2290, 0, reinterpret_cast(this)); + setRet(call_sew_2290, 0, ret_val_sew_2290); + setArg(call_vector_vector_op_2289, 0, V); + setArg(call_vector_vector_op_2289, 1, 9); + setArg(call_vector_vector_op_2289, 2, 0); + setArg(call_vector_vector_op_2289, 3, vector_vector_op_2289_arg3); + setArg(call_vector_vector_op_2289, 4, vector_vector_op_2289_arg4); + setArg(call_vector_vector_op_2289, 5, vector_vector_op_2289_arg5); + setArg(call_vector_vector_op_2289, 6, vm); + setArg(call_vector_vector_op_2289, 7, vd); + setArg(call_vector_vector_op_2289, 8, vs2); + setArg(call_vector_vector_op_2289, 9, vs1); + setArg(call_vector_vector_op_2289, 10, vector_vector_op_2289_arg10); + } + cc.bind(label_merge); + } + auto tmp2291 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2291, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2291, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 518); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 519: VAND__VX */ + continuation_e __vand__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vand.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAND__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 519); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2292; + x86::Gp ret_val_illegal_normal_2292 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2292, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2293 = get_reg(cc, 8, false); + mov(cc, tmp2293, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2293, ret_val_illegal_normal_2292); + setArg(call_illegal_normal_2292, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2292, 1, vd); + setArg(call_illegal_normal_2292, 2, vm); + setRet(call_illegal_normal_2292, 0, ret_val_illegal_normal_2292); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2295; + x86::Gp ret_val_sew_2295 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2295, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2294; + auto vector_imm_op_2294_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2294_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2294_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2294_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2294_arg10 = ret_val_sew_2295; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2294, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2295, 0, reinterpret_cast(this)); + setRet(call_sew_2295, 0, ret_val_sew_2295); + setArg(call_vector_imm_op_2294, 0, V); + setArg(call_vector_imm_op_2294, 1, 9); + setArg(call_vector_imm_op_2294, 2, 4); + setArg(call_vector_imm_op_2294, 3, vector_imm_op_2294_arg3); + setArg(call_vector_imm_op_2294, 4, vector_imm_op_2294_arg4); + setArg(call_vector_imm_op_2294, 5, vector_imm_op_2294_arg5); + setArg(call_vector_imm_op_2294, 6, vm); + setArg(call_vector_imm_op_2294, 7, vd); + setArg(call_vector_imm_op_2294, 8, vs2); + setArg(call_vector_imm_op_2294, 9, vector_imm_op_2294_arg9); + setArg(call_vector_imm_op_2294, 10, vector_imm_op_2294_arg10); + } + cc.bind(label_merge); + } + auto tmp2296 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2296, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2296, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 519); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 520: VOR__VI */ + continuation_e __vor__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vor.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VOR__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 520); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2297; + x86::Gp ret_val_illegal_normal_2297 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2297, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2297; + setArg(call_illegal_normal_2297, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2297, 1, vd); + setArg(call_illegal_normal_2297, 2, vm); + setRet(call_illegal_normal_2297, 0, ret_val_illegal_normal_2297); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2299; + x86::Gp ret_val_sew_2299 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2299, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2298; + auto vector_imm_op_2298_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2298_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2298_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2298_arg10 = ret_val_sew_2299; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2298, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2299, 0, reinterpret_cast(this)); + setRet(call_sew_2299, 0, ret_val_sew_2299); + setArg(call_vector_imm_op_2298, 0, V); + setArg(call_vector_imm_op_2298, 1, 10); + setArg(call_vector_imm_op_2298, 2, 3); + setArg(call_vector_imm_op_2298, 3, vector_imm_op_2298_arg3); + setArg(call_vector_imm_op_2298, 4, vector_imm_op_2298_arg4); + setArg(call_vector_imm_op_2298, 5, vector_imm_op_2298_arg5); + setArg(call_vector_imm_op_2298, 6, vm); + setArg(call_vector_imm_op_2298, 7, vd); + setArg(call_vector_imm_op_2298, 8, vs2); + setArg(call_vector_imm_op_2298, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_op_2298, 10, vector_imm_op_2298_arg10); + } + cc.bind(label_merge); + } + auto tmp2300 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2300, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2300, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 520); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 521: VOR__VV */ + continuation_e __vor__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vor.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VOR__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 521); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2301; + x86::Gp ret_val_illegal_normal_2301 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2301, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2301; + setArg(call_illegal_normal_2301, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2301, 1, vd); + setArg(call_illegal_normal_2301, 2, vm); + setRet(call_illegal_normal_2301, 0, ret_val_illegal_normal_2301); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2303; + x86::Gp ret_val_sew_2303 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2303, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2302; + auto vector_vector_op_2302_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2302_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2302_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2302_arg10 = ret_val_sew_2303; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2302, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2303, 0, reinterpret_cast(this)); + setRet(call_sew_2303, 0, ret_val_sew_2303); + setArg(call_vector_vector_op_2302, 0, V); + setArg(call_vector_vector_op_2302, 1, 10); + setArg(call_vector_vector_op_2302, 2, 0); + setArg(call_vector_vector_op_2302, 3, vector_vector_op_2302_arg3); + setArg(call_vector_vector_op_2302, 4, vector_vector_op_2302_arg4); + setArg(call_vector_vector_op_2302, 5, vector_vector_op_2302_arg5); + setArg(call_vector_vector_op_2302, 6, vm); + setArg(call_vector_vector_op_2302, 7, vd); + setArg(call_vector_vector_op_2302, 8, vs2); + setArg(call_vector_vector_op_2302, 9, vs1); + setArg(call_vector_vector_op_2302, 10, vector_vector_op_2302_arg10); + } + cc.bind(label_merge); + } + auto tmp2304 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2304, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2304, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 521); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 522: VOR__VX */ + continuation_e __vor__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vor.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VOR__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 522); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2305; + x86::Gp ret_val_illegal_normal_2305 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2305, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2306 = get_reg(cc, 8, false); + mov(cc, tmp2306, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2306, ret_val_illegal_normal_2305); + setArg(call_illegal_normal_2305, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2305, 1, vd); + setArg(call_illegal_normal_2305, 2, vm); + setRet(call_illegal_normal_2305, 0, ret_val_illegal_normal_2305); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2308; + x86::Gp ret_val_sew_2308 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2308, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2307; + auto vector_imm_op_2307_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2307_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2307_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2307_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2307_arg10 = ret_val_sew_2308; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2307, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2308, 0, reinterpret_cast(this)); + setRet(call_sew_2308, 0, ret_val_sew_2308); + setArg(call_vector_imm_op_2307, 0, V); + setArg(call_vector_imm_op_2307, 1, 10); + setArg(call_vector_imm_op_2307, 2, 4); + setArg(call_vector_imm_op_2307, 3, vector_imm_op_2307_arg3); + setArg(call_vector_imm_op_2307, 4, vector_imm_op_2307_arg4); + setArg(call_vector_imm_op_2307, 5, vector_imm_op_2307_arg5); + setArg(call_vector_imm_op_2307, 6, vm); + setArg(call_vector_imm_op_2307, 7, vd); + setArg(call_vector_imm_op_2307, 8, vs2); + setArg(call_vector_imm_op_2307, 9, vector_imm_op_2307_arg9); + setArg(call_vector_imm_op_2307, 10, vector_imm_op_2307_arg10); + } + cc.bind(label_merge); + } + auto tmp2309 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2309, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2309, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 522); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 523: VXOR__VI */ + continuation_e __vxor__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vxor.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VXOR__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 523); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2310; + x86::Gp ret_val_illegal_normal_2310 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2310, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2310; + setArg(call_illegal_normal_2310, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2310, 1, vd); + setArg(call_illegal_normal_2310, 2, vm); + setRet(call_illegal_normal_2310, 0, ret_val_illegal_normal_2310); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2312; + x86::Gp ret_val_sew_2312 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2312, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2311; + auto vector_imm_op_2311_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2311_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2311_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2311_arg10 = ret_val_sew_2312; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2311, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2312, 0, reinterpret_cast(this)); + setRet(call_sew_2312, 0, ret_val_sew_2312); + setArg(call_vector_imm_op_2311, 0, V); + setArg(call_vector_imm_op_2311, 1, 11); + setArg(call_vector_imm_op_2311, 2, 3); + setArg(call_vector_imm_op_2311, 3, vector_imm_op_2311_arg3); + setArg(call_vector_imm_op_2311, 4, vector_imm_op_2311_arg4); + setArg(call_vector_imm_op_2311, 5, vector_imm_op_2311_arg5); + setArg(call_vector_imm_op_2311, 6, vm); + setArg(call_vector_imm_op_2311, 7, vd); + setArg(call_vector_imm_op_2311, 8, vs2); + setArg(call_vector_imm_op_2311, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_op_2311, 10, vector_imm_op_2311_arg10); + } + cc.bind(label_merge); + } + auto tmp2313 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2313, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2313, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 523); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 524: VXOR__VV */ + continuation_e __vxor__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vxor.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VXOR__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 524); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2314; + x86::Gp ret_val_illegal_normal_2314 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2314, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2314; + setArg(call_illegal_normal_2314, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2314, 1, vd); + setArg(call_illegal_normal_2314, 2, vm); + setRet(call_illegal_normal_2314, 0, ret_val_illegal_normal_2314); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2316; + x86::Gp ret_val_sew_2316 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2316, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2315; + auto vector_vector_op_2315_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2315_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2315_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2315_arg10 = ret_val_sew_2316; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2315, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2316, 0, reinterpret_cast(this)); + setRet(call_sew_2316, 0, ret_val_sew_2316); + setArg(call_vector_vector_op_2315, 0, V); + setArg(call_vector_vector_op_2315, 1, 11); + setArg(call_vector_vector_op_2315, 2, 0); + setArg(call_vector_vector_op_2315, 3, vector_vector_op_2315_arg3); + setArg(call_vector_vector_op_2315, 4, vector_vector_op_2315_arg4); + setArg(call_vector_vector_op_2315, 5, vector_vector_op_2315_arg5); + setArg(call_vector_vector_op_2315, 6, vm); + setArg(call_vector_vector_op_2315, 7, vd); + setArg(call_vector_vector_op_2315, 8, vs2); + setArg(call_vector_vector_op_2315, 9, vs1); + setArg(call_vector_vector_op_2315, 10, vector_vector_op_2315_arg10); + } + cc.bind(label_merge); + } + auto tmp2317 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2317, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2317, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 524); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 525: VXOR__VX */ + continuation_e __vxor__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vxor.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VXOR__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 525); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2318; + x86::Gp ret_val_illegal_normal_2318 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2318, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2319 = get_reg(cc, 8, false); + mov(cc, tmp2319, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2319, ret_val_illegal_normal_2318); + setArg(call_illegal_normal_2318, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2318, 1, vd); + setArg(call_illegal_normal_2318, 2, vm); + setRet(call_illegal_normal_2318, 0, ret_val_illegal_normal_2318); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2321; + x86::Gp ret_val_sew_2321 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2321, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2320; + auto vector_imm_op_2320_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2320_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2320_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2320_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2320_arg10 = ret_val_sew_2321; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2320, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2321, 0, reinterpret_cast(this)); + setRet(call_sew_2321, 0, ret_val_sew_2321); + setArg(call_vector_imm_op_2320, 0, V); + setArg(call_vector_imm_op_2320, 1, 11); + setArg(call_vector_imm_op_2320, 2, 4); + setArg(call_vector_imm_op_2320, 3, vector_imm_op_2320_arg3); + setArg(call_vector_imm_op_2320, 4, vector_imm_op_2320_arg4); + setArg(call_vector_imm_op_2320, 5, vector_imm_op_2320_arg5); + setArg(call_vector_imm_op_2320, 6, vm); + setArg(call_vector_imm_op_2320, 7, vd); + setArg(call_vector_imm_op_2320, 8, vs2); + setArg(call_vector_imm_op_2320, 9, vector_imm_op_2320_arg9); + setArg(call_vector_imm_op_2320, 10, vector_imm_op_2320_arg10); + } + cc.bind(label_merge); + } + auto tmp2322 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2322, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2322, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 525); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 526: VSLL__VI */ + continuation_e __vsll__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsll.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLL__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 526); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2323; + x86::Gp ret_val_illegal_normal_2323 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2323, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2323; + setArg(call_illegal_normal_2323, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2323, 1, vd); + setArg(call_illegal_normal_2323, 2, vm); + setRet(call_illegal_normal_2323, 0, ret_val_illegal_normal_2323); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2325; + x86::Gp ret_val_sew_2325 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2325, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2324; + auto vector_imm_op_2324_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2324_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2324_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2324_arg10 = ret_val_sew_2325; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2324, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2325, 0, reinterpret_cast(this)); + setRet(call_sew_2325, 0, ret_val_sew_2325); + setArg(call_vector_imm_op_2324, 0, V); + setArg(call_vector_imm_op_2324, 1, 37); + setArg(call_vector_imm_op_2324, 2, 3); + setArg(call_vector_imm_op_2324, 3, vector_imm_op_2324_arg3); + setArg(call_vector_imm_op_2324, 4, vector_imm_op_2324_arg4); + setArg(call_vector_imm_op_2324, 5, vector_imm_op_2324_arg5); + setArg(call_vector_imm_op_2324, 6, vm); + setArg(call_vector_imm_op_2324, 7, vd); + setArg(call_vector_imm_op_2324, 8, vs2); + setArg(call_vector_imm_op_2324, 9, (int32_t)(uint32_t)imm); + setArg(call_vector_imm_op_2324, 10, vector_imm_op_2324_arg10); + } + cc.bind(label_merge); + } + auto tmp2326 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2326, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2326, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 526); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 527: VSLL__VV */ + continuation_e __vsll__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsll.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 527); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2327; + x86::Gp ret_val_illegal_normal_2327 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2327, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2327; + setArg(call_illegal_normal_2327, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2327, 1, vd); + setArg(call_illegal_normal_2327, 2, vm); + setRet(call_illegal_normal_2327, 0, ret_val_illegal_normal_2327); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2329; + x86::Gp ret_val_sew_2329 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2329, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2328; + auto vector_vector_op_2328_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2328_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2328_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2328_arg10 = ret_val_sew_2329; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2328, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2329, 0, reinterpret_cast(this)); + setRet(call_sew_2329, 0, ret_val_sew_2329); + setArg(call_vector_vector_op_2328, 0, V); + setArg(call_vector_vector_op_2328, 1, 37); + setArg(call_vector_vector_op_2328, 2, 0); + setArg(call_vector_vector_op_2328, 3, vector_vector_op_2328_arg3); + setArg(call_vector_vector_op_2328, 4, vector_vector_op_2328_arg4); + setArg(call_vector_vector_op_2328, 5, vector_vector_op_2328_arg5); + setArg(call_vector_vector_op_2328, 6, vm); + setArg(call_vector_vector_op_2328, 7, vd); + setArg(call_vector_vector_op_2328, 8, vs2); + setArg(call_vector_vector_op_2328, 9, vs1); + setArg(call_vector_vector_op_2328, 10, vector_vector_op_2328_arg10); + } + cc.bind(label_merge); + } + auto tmp2330 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2330, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2330, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 527); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 528: VSLL__VX */ + continuation_e __vsll__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsll.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 528); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2331; + x86::Gp ret_val_illegal_normal_2331 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2331, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2332 = get_reg(cc, 8, false); + mov(cc, tmp2332, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2332, ret_val_illegal_normal_2331); + setArg(call_illegal_normal_2331, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2331, 1, vd); + setArg(call_illegal_normal_2331, 2, vm); + setRet(call_illegal_normal_2331, 0, ret_val_illegal_normal_2331); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2334; + x86::Gp ret_val_sew_2334 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2334, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2333; + auto vector_imm_op_2333_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2333_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2333_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2333_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); + auto vector_imm_op_2333_arg10 = ret_val_sew_2334; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2333, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2334, 0, reinterpret_cast(this)); + setRet(call_sew_2334, 0, ret_val_sew_2334); + setArg(call_vector_imm_op_2333, 0, V); + setArg(call_vector_imm_op_2333, 1, 37); + setArg(call_vector_imm_op_2333, 2, 4); + setArg(call_vector_imm_op_2333, 3, vector_imm_op_2333_arg3); + setArg(call_vector_imm_op_2333, 4, vector_imm_op_2333_arg4); + setArg(call_vector_imm_op_2333, 5, vector_imm_op_2333_arg5); + setArg(call_vector_imm_op_2333, 6, vm); + setArg(call_vector_imm_op_2333, 7, vd); + setArg(call_vector_imm_op_2333, 8, vs2); + setArg(call_vector_imm_op_2333, 9, vector_imm_op_2333_arg9); + setArg(call_vector_imm_op_2333, 10, vector_imm_op_2333_arg10); + } + cc.bind(label_merge); + } + auto tmp2335 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2335, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2335, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 528); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 529: VSRL__VI */ + continuation_e __vsrl__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsrl.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRL__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 529); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2336; + x86::Gp ret_val_illegal_normal_2336 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2336, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2336; + setArg(call_illegal_normal_2336, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2336, 1, vd); + setArg(call_illegal_normal_2336, 2, vm); + setRet(call_illegal_normal_2336, 0, ret_val_illegal_normal_2336); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2338; + x86::Gp ret_val_sew_2338 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2338, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2337; + auto vector_imm_op_2337_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2337_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2337_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2337_arg10 = ret_val_sew_2338; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2337, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2338, 0, reinterpret_cast(this)); + setRet(call_sew_2338, 0, ret_val_sew_2338); + setArg(call_vector_imm_op_2337, 0, V); + setArg(call_vector_imm_op_2337, 1, 40); + setArg(call_vector_imm_op_2337, 2, 3); + setArg(call_vector_imm_op_2337, 3, vector_imm_op_2337_arg3); + setArg(call_vector_imm_op_2337, 4, vector_imm_op_2337_arg4); + setArg(call_vector_imm_op_2337, 5, vector_imm_op_2337_arg5); + setArg(call_vector_imm_op_2337, 6, vm); + setArg(call_vector_imm_op_2337, 7, vd); + setArg(call_vector_imm_op_2337, 8, vs2); + setArg(call_vector_imm_op_2337, 9, (int32_t)(uint32_t)imm); + setArg(call_vector_imm_op_2337, 10, vector_imm_op_2337_arg10); + } + cc.bind(label_merge); + } + auto tmp2339 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2339, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2339, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 529); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 530: VSRL__VV */ + continuation_e __vsrl__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsrl.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 530); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2340; + x86::Gp ret_val_illegal_normal_2340 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2340, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2340; + setArg(call_illegal_normal_2340, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2340, 1, vd); + setArg(call_illegal_normal_2340, 2, vm); + setRet(call_illegal_normal_2340, 0, ret_val_illegal_normal_2340); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2342; + x86::Gp ret_val_sew_2342 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2342, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2341; + auto vector_vector_op_2341_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2341_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2341_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2341_arg10 = ret_val_sew_2342; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2341, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2342, 0, reinterpret_cast(this)); + setRet(call_sew_2342, 0, ret_val_sew_2342); + setArg(call_vector_vector_op_2341, 0, V); + setArg(call_vector_vector_op_2341, 1, 40); + setArg(call_vector_vector_op_2341, 2, 0); + setArg(call_vector_vector_op_2341, 3, vector_vector_op_2341_arg3); + setArg(call_vector_vector_op_2341, 4, vector_vector_op_2341_arg4); + setArg(call_vector_vector_op_2341, 5, vector_vector_op_2341_arg5); + setArg(call_vector_vector_op_2341, 6, vm); + setArg(call_vector_vector_op_2341, 7, vd); + setArg(call_vector_vector_op_2341, 8, vs2); + setArg(call_vector_vector_op_2341, 9, vs1); + setArg(call_vector_vector_op_2341, 10, vector_vector_op_2341_arg10); + } + cc.bind(label_merge); + } + auto tmp2343 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2343, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2343, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 530); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 531: VSRL__VX */ + continuation_e __vsrl__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsrl.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 531); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2344; + x86::Gp ret_val_illegal_normal_2344 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2344, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2345 = get_reg(cc, 8, false); + mov(cc, tmp2345, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2345, ret_val_illegal_normal_2344); + setArg(call_illegal_normal_2344, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2344, 1, vd); + setArg(call_illegal_normal_2344, 2, vm); + setRet(call_illegal_normal_2344, 0, ret_val_illegal_normal_2344); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2347; + x86::Gp ret_val_sew_2347 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2347, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2346; + auto vector_imm_op_2346_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2346_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2346_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2346_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); + auto vector_imm_op_2346_arg10 = ret_val_sew_2347; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2346, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2347, 0, reinterpret_cast(this)); + setRet(call_sew_2347, 0, ret_val_sew_2347); + setArg(call_vector_imm_op_2346, 0, V); + setArg(call_vector_imm_op_2346, 1, 40); + setArg(call_vector_imm_op_2346, 2, 4); + setArg(call_vector_imm_op_2346, 3, vector_imm_op_2346_arg3); + setArg(call_vector_imm_op_2346, 4, vector_imm_op_2346_arg4); + setArg(call_vector_imm_op_2346, 5, vector_imm_op_2346_arg5); + setArg(call_vector_imm_op_2346, 6, vm); + setArg(call_vector_imm_op_2346, 7, vd); + setArg(call_vector_imm_op_2346, 8, vs2); + setArg(call_vector_imm_op_2346, 9, vector_imm_op_2346_arg9); + setArg(call_vector_imm_op_2346, 10, vector_imm_op_2346_arg10); + } + cc.bind(label_merge); + } + auto tmp2348 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2348, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2348, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 531); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 532: VSRA__VI */ + continuation_e __vsra__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsra.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRA__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 532); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2349; + x86::Gp ret_val_illegal_normal_2349 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2349, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2349; + setArg(call_illegal_normal_2349, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2349, 1, vd); + setArg(call_illegal_normal_2349, 2, vm); + setRet(call_illegal_normal_2349, 0, ret_val_illegal_normal_2349); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2351; + x86::Gp ret_val_sew_2351 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2351, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2350; + auto vector_imm_op_2350_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2350_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2350_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2350_arg10 = ret_val_sew_2351; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2350, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2351, 0, reinterpret_cast(this)); + setRet(call_sew_2351, 0, ret_val_sew_2351); + setArg(call_vector_imm_op_2350, 0, V); + setArg(call_vector_imm_op_2350, 1, 41); + setArg(call_vector_imm_op_2350, 2, 3); + setArg(call_vector_imm_op_2350, 3, vector_imm_op_2350_arg3); + setArg(call_vector_imm_op_2350, 4, vector_imm_op_2350_arg4); + setArg(call_vector_imm_op_2350, 5, vector_imm_op_2350_arg5); + setArg(call_vector_imm_op_2350, 6, vm); + setArg(call_vector_imm_op_2350, 7, vd); + setArg(call_vector_imm_op_2350, 8, vs2); + setArg(call_vector_imm_op_2350, 9, (int32_t)(uint32_t)imm); + setArg(call_vector_imm_op_2350, 10, vector_imm_op_2350_arg10); + } + cc.bind(label_merge); + } + auto tmp2352 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2352, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2352, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 532); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 533: VSRA__VV */ + continuation_e __vsra__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsra.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRA__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 533); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2353; + x86::Gp ret_val_illegal_normal_2353 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2353, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2353; + setArg(call_illegal_normal_2353, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2353, 1, vd); + setArg(call_illegal_normal_2353, 2, vm); + setRet(call_illegal_normal_2353, 0, ret_val_illegal_normal_2353); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2355; + x86::Gp ret_val_sew_2355 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2355, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2354; + auto vector_vector_op_2354_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2354_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2354_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2354_arg10 = ret_val_sew_2355; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2354, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2355, 0, reinterpret_cast(this)); + setRet(call_sew_2355, 0, ret_val_sew_2355); + setArg(call_vector_vector_op_2354, 0, V); + setArg(call_vector_vector_op_2354, 1, 41); + setArg(call_vector_vector_op_2354, 2, 0); + setArg(call_vector_vector_op_2354, 3, vector_vector_op_2354_arg3); + setArg(call_vector_vector_op_2354, 4, vector_vector_op_2354_arg4); + setArg(call_vector_vector_op_2354, 5, vector_vector_op_2354_arg5); + setArg(call_vector_vector_op_2354, 6, vm); + setArg(call_vector_vector_op_2354, 7, vd); + setArg(call_vector_vector_op_2354, 8, vs2); + setArg(call_vector_vector_op_2354, 9, vs1); + setArg(call_vector_vector_op_2354, 10, vector_vector_op_2354_arg10); + } + cc.bind(label_merge); + } + auto tmp2356 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2356, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2356, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 533); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 534: VSRA__VX */ + continuation_e __vsra__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsra.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRA__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 534); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2357; + x86::Gp ret_val_illegal_normal_2357 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2357, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2358 = get_reg(cc, 8, false); + mov(cc, tmp2358, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2358, ret_val_illegal_normal_2357); + setArg(call_illegal_normal_2357, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2357, 1, vd); + setArg(call_illegal_normal_2357, 2, vm); + setRet(call_illegal_normal_2357, 0, ret_val_illegal_normal_2357); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2360; + x86::Gp ret_val_sew_2360 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2360, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2359; + auto vector_imm_op_2359_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2359_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2359_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2359_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); + auto vector_imm_op_2359_arg10 = ret_val_sew_2360; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2359, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2360, 0, reinterpret_cast(this)); + setRet(call_sew_2360, 0, ret_val_sew_2360); + setArg(call_vector_imm_op_2359, 0, V); + setArg(call_vector_imm_op_2359, 1, 41); + setArg(call_vector_imm_op_2359, 2, 4); + setArg(call_vector_imm_op_2359, 3, vector_imm_op_2359_arg3); + setArg(call_vector_imm_op_2359, 4, vector_imm_op_2359_arg4); + setArg(call_vector_imm_op_2359, 5, vector_imm_op_2359_arg5); + setArg(call_vector_imm_op_2359, 6, vm); + setArg(call_vector_imm_op_2359, 7, vd); + setArg(call_vector_imm_op_2359, 8, vs2); + setArg(call_vector_imm_op_2359, 9, vector_imm_op_2359_arg9); + setArg(call_vector_imm_op_2359, 10, vector_imm_op_2359_arg10); + } + cc.bind(label_merge); + } + auto tmp2361 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2361, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2361, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 534); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 535: VNSRL__WI */ + continuation_e __vnsrl__wi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnsrl.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRL__WI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 535); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2362; + x86::Gp ret_val_get_sew_pow_2362 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2362, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2363 = get_reg(cc, 8, false); + mov(cc, tmp2363, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2363, ret_val_get_sew_pow_2362)), 8, false), ~ 1); + setArg(call_get_sew_pow_2362, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2362, 0, ret_val_get_sew_pow_2362); + InvokeNode* call_get_lmul_pow_2364; + x86::Gp ret_val_get_lmul_pow_2364 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2364, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2364; + setArg(call_get_lmul_pow_2364, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2364, 0, ret_val_get_lmul_pow_2364); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2365; + auto illegal_variable_width_2365_arg2 = SEW_widen; + auto illegal_variable_width_2365_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2365 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2365, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2366; + auto valid_reg_overlap_2366_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2366_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2366 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2366, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2365, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2366))); + setArg(call_illegal_variable_width_2365, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2365, 1, vd); + setArg(call_illegal_variable_width_2365, 2, vm); + setArg(call_illegal_variable_width_2365, 3, illegal_variable_width_2365_arg2); + setArg(call_illegal_variable_width_2365, 4, illegal_variable_width_2365_arg3); + setRet(call_illegal_variable_width_2365, 0, ret_val_illegal_variable_width_2365); + setArg(call_valid_reg_overlap_2366, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2366, 1, vs2); + setArg(call_valid_reg_overlap_2366, 2, vd); + setArg(call_valid_reg_overlap_2366, 3, valid_reg_overlap_2366_arg2); + setArg(call_valid_reg_overlap_2366, 4, valid_reg_overlap_2366_arg3); + setRet(call_valid_reg_overlap_2366, 0, ret_val_valid_reg_overlap_2366); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2368; + x86::Gp ret_val_sew_2368 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2368, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_vw_2367; + auto vector_imm_vw_2367_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_vw_2367_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_vw_2367_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_vw_2367_arg10 = ret_val_sew_2368; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_vw_2367, &vector_imm_vw, FuncSignature::build()); + setArg(call_sew_2368, 0, reinterpret_cast(this)); + setRet(call_sew_2368, 0, ret_val_sew_2368); + setArg(call_vector_imm_vw_2367, 0, V); + setArg(call_vector_imm_vw_2367, 1, 44); + setArg(call_vector_imm_vw_2367, 2, 3); + setArg(call_vector_imm_vw_2367, 3, vector_imm_vw_2367_arg3); + setArg(call_vector_imm_vw_2367, 4, vector_imm_vw_2367_arg4); + setArg(call_vector_imm_vw_2367, 5, vector_imm_vw_2367_arg5); + setArg(call_vector_imm_vw_2367, 6, vm); + setArg(call_vector_imm_vw_2367, 7, vd); + setArg(call_vector_imm_vw_2367, 8, vs2); + setArg(call_vector_imm_vw_2367, 9, (int32_t)(uint32_t)simm); + setArg(call_vector_imm_vw_2367, 10, vector_imm_vw_2367_arg10); + } + cc.bind(label_merge); + } + auto tmp2369 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2369, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2369, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 535); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 536: VNSRL__WV */ + continuation_e __vnsrl__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnsrl.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRL__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 536); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2370; + x86::Gp ret_val_get_sew_pow_2370 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2370, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2371 = get_reg(cc, 8, false); + mov(cc, tmp2371, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2371, ret_val_get_sew_pow_2370)), 8, false), ~ 1); + setArg(call_get_sew_pow_2370, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2370, 0, ret_val_get_sew_pow_2370); + InvokeNode* call_get_lmul_pow_2372; + x86::Gp ret_val_get_lmul_pow_2372 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2372, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2372; + setArg(call_get_lmul_pow_2372, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2372, 0, ret_val_get_lmul_pow_2372); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2373; + auto illegal_variable_width_2373_arg2 = SEW_widen; + auto illegal_variable_width_2373_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2373 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2373, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2374; + auto valid_reg_overlap_2374_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2374_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2374 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2374, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2373, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2374))); + setArg(call_illegal_variable_width_2373, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2373, 1, vd); + setArg(call_illegal_variable_width_2373, 2, vm); + setArg(call_illegal_variable_width_2373, 3, illegal_variable_width_2373_arg2); + setArg(call_illegal_variable_width_2373, 4, illegal_variable_width_2373_arg3); + setRet(call_illegal_variable_width_2373, 0, ret_val_illegal_variable_width_2373); + setArg(call_valid_reg_overlap_2374, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2374, 1, vs2); + setArg(call_valid_reg_overlap_2374, 2, vd); + setArg(call_valid_reg_overlap_2374, 3, valid_reg_overlap_2374_arg2); + setArg(call_valid_reg_overlap_2374, 4, valid_reg_overlap_2374_arg3); + setRet(call_valid_reg_overlap_2374, 0, ret_val_valid_reg_overlap_2374); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2376; + x86::Gp ret_val_sew_2376 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2376, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_vw_2375; + auto vector_vector_vw_2375_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_vw_2375_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_vw_2375_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_vw_2375_arg10 = ret_val_sew_2376; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_vw_2375, &vector_vector_vw, FuncSignature::build()); + setArg(call_sew_2376, 0, reinterpret_cast(this)); + setRet(call_sew_2376, 0, ret_val_sew_2376); + setArg(call_vector_vector_vw_2375, 0, V); + setArg(call_vector_vector_vw_2375, 1, 44); + setArg(call_vector_vector_vw_2375, 2, 0); + setArg(call_vector_vector_vw_2375, 3, vector_vector_vw_2375_arg3); + setArg(call_vector_vector_vw_2375, 4, vector_vector_vw_2375_arg4); + setArg(call_vector_vector_vw_2375, 5, vector_vector_vw_2375_arg5); + setArg(call_vector_vector_vw_2375, 6, vm); + setArg(call_vector_vector_vw_2375, 7, vd); + setArg(call_vector_vector_vw_2375, 8, vs2); + setArg(call_vector_vector_vw_2375, 9, vs1); + setArg(call_vector_vector_vw_2375, 10, vector_vector_vw_2375_arg10); + } + cc.bind(label_merge); + } + auto tmp2377 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2377, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2377, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 536); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 537: VNSRL__WX */ + continuation_e __vnsrl__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnsrl.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRL__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 537); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2378; + x86::Gp ret_val_get_sew_pow_2378 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2378, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2379 = get_reg(cc, 8, false); + mov(cc, tmp2379, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2379, ret_val_get_sew_pow_2378)), 8, false), ~ 1); + setArg(call_get_sew_pow_2378, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2378, 0, ret_val_get_sew_pow_2378); + InvokeNode* call_get_lmul_pow_2380; + x86::Gp ret_val_get_lmul_pow_2380 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2380, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2380; + setArg(call_get_lmul_pow_2380, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2380, 0, ret_val_get_lmul_pow_2380); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2381; + auto illegal_variable_width_2381_arg2 = SEW_widen; + auto illegal_variable_width_2381_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2381 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2381, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2382; + auto valid_reg_overlap_2382_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2382_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2382 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2382, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2381, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2382))); + setArg(call_illegal_variable_width_2381, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2381, 1, vd); + setArg(call_illegal_variable_width_2381, 2, vm); + setArg(call_illegal_variable_width_2381, 3, illegal_variable_width_2381_arg2); + setArg(call_illegal_variable_width_2381, 4, illegal_variable_width_2381_arg3); + setRet(call_illegal_variable_width_2381, 0, ret_val_illegal_variable_width_2381); + setArg(call_valid_reg_overlap_2382, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2382, 1, vs2); + setArg(call_valid_reg_overlap_2382, 2, vd); + setArg(call_valid_reg_overlap_2382, 3, valid_reg_overlap_2382_arg2); + setArg(call_valid_reg_overlap_2382, 4, valid_reg_overlap_2382_arg3); + setRet(call_valid_reg_overlap_2382, 0, ret_val_valid_reg_overlap_2382); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2384; + x86::Gp ret_val_sew_2384 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2384, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_vw_2383; + auto vector_imm_vw_2383_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_vw_2383_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_vw_2383_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_vw_2383_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); + auto vector_imm_vw_2383_arg10 = ret_val_sew_2384; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_vw_2383, &vector_imm_vw, FuncSignature::build()); + setArg(call_sew_2384, 0, reinterpret_cast(this)); + setRet(call_sew_2384, 0, ret_val_sew_2384); + setArg(call_vector_imm_vw_2383, 0, V); + setArg(call_vector_imm_vw_2383, 1, 44); + setArg(call_vector_imm_vw_2383, 2, 4); + setArg(call_vector_imm_vw_2383, 3, vector_imm_vw_2383_arg3); + setArg(call_vector_imm_vw_2383, 4, vector_imm_vw_2383_arg4); + setArg(call_vector_imm_vw_2383, 5, vector_imm_vw_2383_arg5); + setArg(call_vector_imm_vw_2383, 6, vm); + setArg(call_vector_imm_vw_2383, 7, vd); + setArg(call_vector_imm_vw_2383, 8, vs2); + setArg(call_vector_imm_vw_2383, 9, vector_imm_vw_2383_arg9); + setArg(call_vector_imm_vw_2383, 10, vector_imm_vw_2383_arg10); + } + cc.bind(label_merge); + } + auto tmp2385 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2385, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2385, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 537); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 538: VNSRA__WI */ + continuation_e __vnsra__wi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnsra.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRA__WI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 538); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2386; + x86::Gp ret_val_get_sew_pow_2386 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2386, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2387 = get_reg(cc, 8, false); + mov(cc, tmp2387, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2387, ret_val_get_sew_pow_2386)), 8, false), ~ 1); + setArg(call_get_sew_pow_2386, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2386, 0, ret_val_get_sew_pow_2386); + InvokeNode* call_get_lmul_pow_2388; + x86::Gp ret_val_get_lmul_pow_2388 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2388, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2388; + setArg(call_get_lmul_pow_2388, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2388, 0, ret_val_get_lmul_pow_2388); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2389; + auto illegal_variable_width_2389_arg2 = SEW_widen; + auto illegal_variable_width_2389_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2389 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2389, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2390; + auto valid_reg_overlap_2390_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2390_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2390 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2390, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2389, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2390))); + setArg(call_illegal_variable_width_2389, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2389, 1, vd); + setArg(call_illegal_variable_width_2389, 2, vm); + setArg(call_illegal_variable_width_2389, 3, illegal_variable_width_2389_arg2); + setArg(call_illegal_variable_width_2389, 4, illegal_variable_width_2389_arg3); + setRet(call_illegal_variable_width_2389, 0, ret_val_illegal_variable_width_2389); + setArg(call_valid_reg_overlap_2390, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2390, 1, vs2); + setArg(call_valid_reg_overlap_2390, 2, vd); + setArg(call_valid_reg_overlap_2390, 3, valid_reg_overlap_2390_arg2); + setArg(call_valid_reg_overlap_2390, 4, valid_reg_overlap_2390_arg3); + setRet(call_valid_reg_overlap_2390, 0, ret_val_valid_reg_overlap_2390); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2392; + x86::Gp ret_val_sew_2392 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2392, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_vw_2391; + auto vector_imm_vw_2391_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_vw_2391_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_vw_2391_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_vw_2391_arg10 = ret_val_sew_2392; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_vw_2391, &vector_imm_vw, FuncSignature::build()); + setArg(call_sew_2392, 0, reinterpret_cast(this)); + setRet(call_sew_2392, 0, ret_val_sew_2392); + setArg(call_vector_imm_vw_2391, 0, V); + setArg(call_vector_imm_vw_2391, 1, 45); + setArg(call_vector_imm_vw_2391, 2, 3); + setArg(call_vector_imm_vw_2391, 3, vector_imm_vw_2391_arg3); + setArg(call_vector_imm_vw_2391, 4, vector_imm_vw_2391_arg4); + setArg(call_vector_imm_vw_2391, 5, vector_imm_vw_2391_arg5); + setArg(call_vector_imm_vw_2391, 6, vm); + setArg(call_vector_imm_vw_2391, 7, vd); + setArg(call_vector_imm_vw_2391, 8, vs2); + setArg(call_vector_imm_vw_2391, 9, (int32_t)(uint32_t)simm); + setArg(call_vector_imm_vw_2391, 10, vector_imm_vw_2391_arg10); + } + cc.bind(label_merge); + } + auto tmp2393 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2393, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2393, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 538); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 539: VNSRA__WV */ + continuation_e __vnsra__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnsra.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRA__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 539); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2394; + x86::Gp ret_val_get_sew_pow_2394 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2394, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2395 = get_reg(cc, 8, false); + mov(cc, tmp2395, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2395, ret_val_get_sew_pow_2394)), 8, false), ~ 1); + setArg(call_get_sew_pow_2394, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2394, 0, ret_val_get_sew_pow_2394); + InvokeNode* call_get_lmul_pow_2396; + x86::Gp ret_val_get_lmul_pow_2396 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2396, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2396; + setArg(call_get_lmul_pow_2396, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2396, 0, ret_val_get_lmul_pow_2396); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2397; + auto illegal_variable_width_2397_arg2 = SEW_widen; + auto illegal_variable_width_2397_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2397 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2397, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2398; + auto valid_reg_overlap_2398_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2398_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2398 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2398, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2397, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2398))); + setArg(call_illegal_variable_width_2397, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2397, 1, vd); + setArg(call_illegal_variable_width_2397, 2, vm); + setArg(call_illegal_variable_width_2397, 3, illegal_variable_width_2397_arg2); + setArg(call_illegal_variable_width_2397, 4, illegal_variable_width_2397_arg3); + setRet(call_illegal_variable_width_2397, 0, ret_val_illegal_variable_width_2397); + setArg(call_valid_reg_overlap_2398, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2398, 1, vs2); + setArg(call_valid_reg_overlap_2398, 2, vd); + setArg(call_valid_reg_overlap_2398, 3, valid_reg_overlap_2398_arg2); + setArg(call_valid_reg_overlap_2398, 4, valid_reg_overlap_2398_arg3); + setRet(call_valid_reg_overlap_2398, 0, ret_val_valid_reg_overlap_2398); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2400; + x86::Gp ret_val_sew_2400 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2400, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_vw_2399; + auto vector_vector_vw_2399_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_vw_2399_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_vw_2399_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_vw_2399_arg10 = ret_val_sew_2400; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_vw_2399, &vector_vector_vw, FuncSignature::build()); + setArg(call_sew_2400, 0, reinterpret_cast(this)); + setRet(call_sew_2400, 0, ret_val_sew_2400); + setArg(call_vector_vector_vw_2399, 0, V); + setArg(call_vector_vector_vw_2399, 1, 45); + setArg(call_vector_vector_vw_2399, 2, 0); + setArg(call_vector_vector_vw_2399, 3, vector_vector_vw_2399_arg3); + setArg(call_vector_vector_vw_2399, 4, vector_vector_vw_2399_arg4); + setArg(call_vector_vector_vw_2399, 5, vector_vector_vw_2399_arg5); + setArg(call_vector_vector_vw_2399, 6, vm); + setArg(call_vector_vector_vw_2399, 7, vd); + setArg(call_vector_vector_vw_2399, 8, vs2); + setArg(call_vector_vector_vw_2399, 9, vs1); + setArg(call_vector_vector_vw_2399, 10, vector_vector_vw_2399_arg10); + } + cc.bind(label_merge); + } + auto tmp2401 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2401, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2401, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 539); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 540: VNSRA__WX */ + continuation_e __vnsra__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnsra.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRA__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 540); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2402; + x86::Gp ret_val_get_sew_pow_2402 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2402, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2403 = get_reg(cc, 8, false); + mov(cc, tmp2403, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2403, ret_val_get_sew_pow_2402)), 8, false), ~ 1); + setArg(call_get_sew_pow_2402, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2402, 0, ret_val_get_sew_pow_2402); + InvokeNode* call_get_lmul_pow_2404; + x86::Gp ret_val_get_lmul_pow_2404 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2404, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2404; + setArg(call_get_lmul_pow_2404, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2404, 0, ret_val_get_lmul_pow_2404); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2405; + auto illegal_variable_width_2405_arg2 = SEW_widen; + auto illegal_variable_width_2405_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2405 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2405, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2406; + auto valid_reg_overlap_2406_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2406_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2406 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2406, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2405, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2406))); + setArg(call_illegal_variable_width_2405, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2405, 1, vd); + setArg(call_illegal_variable_width_2405, 2, vm); + setArg(call_illegal_variable_width_2405, 3, illegal_variable_width_2405_arg2); + setArg(call_illegal_variable_width_2405, 4, illegal_variable_width_2405_arg3); + setRet(call_illegal_variable_width_2405, 0, ret_val_illegal_variable_width_2405); + setArg(call_valid_reg_overlap_2406, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2406, 1, vs2); + setArg(call_valid_reg_overlap_2406, 2, vd); + setArg(call_valid_reg_overlap_2406, 3, valid_reg_overlap_2406_arg2); + setArg(call_valid_reg_overlap_2406, 4, valid_reg_overlap_2406_arg3); + setRet(call_valid_reg_overlap_2406, 0, ret_val_valid_reg_overlap_2406); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2408; + x86::Gp ret_val_sew_2408 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2408, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_vw_2407; + auto vector_imm_vw_2407_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_vw_2407_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_vw_2407_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_vw_2407_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); + auto vector_imm_vw_2407_arg10 = ret_val_sew_2408; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_vw_2407, &vector_imm_vw, FuncSignature::build()); + setArg(call_sew_2408, 0, reinterpret_cast(this)); + setRet(call_sew_2408, 0, ret_val_sew_2408); + setArg(call_vector_imm_vw_2407, 0, V); + setArg(call_vector_imm_vw_2407, 1, 45); + setArg(call_vector_imm_vw_2407, 2, 4); + setArg(call_vector_imm_vw_2407, 3, vector_imm_vw_2407_arg3); + setArg(call_vector_imm_vw_2407, 4, vector_imm_vw_2407_arg4); + setArg(call_vector_imm_vw_2407, 5, vector_imm_vw_2407_arg5); + setArg(call_vector_imm_vw_2407, 6, vm); + setArg(call_vector_imm_vw_2407, 7, vd); + setArg(call_vector_imm_vw_2407, 8, vs2); + setArg(call_vector_imm_vw_2407, 9, vector_imm_vw_2407_arg9); + setArg(call_vector_imm_vw_2407, 10, vector_imm_vw_2407_arg10); + } + cc.bind(label_merge); + } + auto tmp2409 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2409, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2409, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 540); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 541: VMSEQ__VI */ + continuation_e __vmseq__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmseq.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSEQ__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 541); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2410; + x86::Gp ret_val_illegal_vd_unmasked_2410 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2410, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2410; + setArg(call_illegal_vd_unmasked_2410, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2410, 0, ret_val_illegal_vd_unmasked_2410); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2412; + x86::Gp ret_val_sew_2412 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2412, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2411; + auto mask_vector_imm_op_2411_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2411_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2411_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2411_arg10 = ret_val_sew_2412; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2411, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2412, 0, reinterpret_cast(this)); + setRet(call_sew_2412, 0, ret_val_sew_2412); + setArg(call_mask_vector_imm_op_2411, 0, V); + setArg(call_mask_vector_imm_op_2411, 1, 24); + setArg(call_mask_vector_imm_op_2411, 2, 3); + setArg(call_mask_vector_imm_op_2411, 3, mask_vector_imm_op_2411_arg3); + setArg(call_mask_vector_imm_op_2411, 4, mask_vector_imm_op_2411_arg4); + setArg(call_mask_vector_imm_op_2411, 5, mask_vector_imm_op_2411_arg5); + setArg(call_mask_vector_imm_op_2411, 6, vm); + setArg(call_mask_vector_imm_op_2411, 7, vd); + setArg(call_mask_vector_imm_op_2411, 8, vs2); + setArg(call_mask_vector_imm_op_2411, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2411, 10, mask_vector_imm_op_2411_arg10); + } + cc.bind(label_merge); + } + auto tmp2413 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2413, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2413, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 541); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 542: VMSEQ__VV */ + continuation_e __vmseq__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmseq.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSEQ__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 542); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2414; + x86::Gp ret_val_illegal_vd_unmasked_2414 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2414, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2414; + setArg(call_illegal_vd_unmasked_2414, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2414, 0, ret_val_illegal_vd_unmasked_2414); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2416; + x86::Gp ret_val_sew_2416 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2416, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2415; + auto mask_vector_vector_op_2415_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2415_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2415_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2415_arg10 = ret_val_sew_2416; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2415, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2416, 0, reinterpret_cast(this)); + setRet(call_sew_2416, 0, ret_val_sew_2416); + setArg(call_mask_vector_vector_op_2415, 0, V); + setArg(call_mask_vector_vector_op_2415, 1, 24); + setArg(call_mask_vector_vector_op_2415, 2, 0); + setArg(call_mask_vector_vector_op_2415, 3, mask_vector_vector_op_2415_arg3); + setArg(call_mask_vector_vector_op_2415, 4, mask_vector_vector_op_2415_arg4); + setArg(call_mask_vector_vector_op_2415, 5, mask_vector_vector_op_2415_arg5); + setArg(call_mask_vector_vector_op_2415, 6, vm); + setArg(call_mask_vector_vector_op_2415, 7, vd); + setArg(call_mask_vector_vector_op_2415, 8, vs2); + setArg(call_mask_vector_vector_op_2415, 9, vs1); + setArg(call_mask_vector_vector_op_2415, 10, mask_vector_vector_op_2415_arg10); + } + cc.bind(label_merge); + } + auto tmp2417 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2417, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2417, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 542); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 543: VMSEQ__VX */ + continuation_e __vmseq__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmseq.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSEQ__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 543); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2418; + x86::Gp ret_val_illegal_vd_unmasked_2418 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2418, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2419 = get_reg(cc, 8, false); + mov(cc, tmp2419, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2419, ret_val_illegal_vd_unmasked_2418); + setArg(call_illegal_vd_unmasked_2418, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2418, 0, ret_val_illegal_vd_unmasked_2418); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2421; + x86::Gp ret_val_sew_2421 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2421, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2420; + auto mask_vector_imm_op_2420_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2420_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2420_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2420_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto mask_vector_imm_op_2420_arg10 = ret_val_sew_2421; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2420, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2421, 0, reinterpret_cast(this)); + setRet(call_sew_2421, 0, ret_val_sew_2421); + setArg(call_mask_vector_imm_op_2420, 0, V); + setArg(call_mask_vector_imm_op_2420, 1, 24); + setArg(call_mask_vector_imm_op_2420, 2, 4); + setArg(call_mask_vector_imm_op_2420, 3, mask_vector_imm_op_2420_arg3); + setArg(call_mask_vector_imm_op_2420, 4, mask_vector_imm_op_2420_arg4); + setArg(call_mask_vector_imm_op_2420, 5, mask_vector_imm_op_2420_arg5); + setArg(call_mask_vector_imm_op_2420, 6, vm); + setArg(call_mask_vector_imm_op_2420, 7, vd); + setArg(call_mask_vector_imm_op_2420, 8, vs2); + setArg(call_mask_vector_imm_op_2420, 9, mask_vector_imm_op_2420_arg9); + setArg(call_mask_vector_imm_op_2420, 10, mask_vector_imm_op_2420_arg10); + } + cc.bind(label_merge); + } + auto tmp2422 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2422, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2422, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 543); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 544: VMSNE__VI */ + continuation_e __vmsne__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsne.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSNE__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 544); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2423; + x86::Gp ret_val_illegal_vd_unmasked_2423 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2423, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2423; + setArg(call_illegal_vd_unmasked_2423, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2423, 0, ret_val_illegal_vd_unmasked_2423); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2425; + x86::Gp ret_val_sew_2425 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2425, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2424; + auto mask_vector_imm_op_2424_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2424_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2424_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2424_arg10 = ret_val_sew_2425; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2424, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2425, 0, reinterpret_cast(this)); + setRet(call_sew_2425, 0, ret_val_sew_2425); + setArg(call_mask_vector_imm_op_2424, 0, V); + setArg(call_mask_vector_imm_op_2424, 1, 25); + setArg(call_mask_vector_imm_op_2424, 2, 3); + setArg(call_mask_vector_imm_op_2424, 3, mask_vector_imm_op_2424_arg3); + setArg(call_mask_vector_imm_op_2424, 4, mask_vector_imm_op_2424_arg4); + setArg(call_mask_vector_imm_op_2424, 5, mask_vector_imm_op_2424_arg5); + setArg(call_mask_vector_imm_op_2424, 6, vm); + setArg(call_mask_vector_imm_op_2424, 7, vd); + setArg(call_mask_vector_imm_op_2424, 8, vs2); + setArg(call_mask_vector_imm_op_2424, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2424, 10, mask_vector_imm_op_2424_arg10); + } + cc.bind(label_merge); + } + auto tmp2426 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2426, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2426, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 544); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 545: VMSNE__VV */ + continuation_e __vmsne__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsne.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSNE__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 545); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2427; + x86::Gp ret_val_illegal_vd_unmasked_2427 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2427, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2427; + setArg(call_illegal_vd_unmasked_2427, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2427, 0, ret_val_illegal_vd_unmasked_2427); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2429; + x86::Gp ret_val_sew_2429 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2429, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2428; + auto mask_vector_vector_op_2428_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2428_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2428_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2428_arg10 = ret_val_sew_2429; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2428, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2429, 0, reinterpret_cast(this)); + setRet(call_sew_2429, 0, ret_val_sew_2429); + setArg(call_mask_vector_vector_op_2428, 0, V); + setArg(call_mask_vector_vector_op_2428, 1, 25); + setArg(call_mask_vector_vector_op_2428, 2, 0); + setArg(call_mask_vector_vector_op_2428, 3, mask_vector_vector_op_2428_arg3); + setArg(call_mask_vector_vector_op_2428, 4, mask_vector_vector_op_2428_arg4); + setArg(call_mask_vector_vector_op_2428, 5, mask_vector_vector_op_2428_arg5); + setArg(call_mask_vector_vector_op_2428, 6, vm); + setArg(call_mask_vector_vector_op_2428, 7, vd); + setArg(call_mask_vector_vector_op_2428, 8, vs2); + setArg(call_mask_vector_vector_op_2428, 9, vs1); + setArg(call_mask_vector_vector_op_2428, 10, mask_vector_vector_op_2428_arg10); + } + cc.bind(label_merge); + } + auto tmp2430 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2430, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2430, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 545); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 546: VMSNE__VX */ + continuation_e __vmsne__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsne.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSNE__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 546); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2431; + x86::Gp ret_val_illegal_vd_unmasked_2431 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2431, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2432 = get_reg(cc, 8, false); + mov(cc, tmp2432, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2432, ret_val_illegal_vd_unmasked_2431); + setArg(call_illegal_vd_unmasked_2431, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2431, 0, ret_val_illegal_vd_unmasked_2431); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2434; + x86::Gp ret_val_sew_2434 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2434, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2433; + auto mask_vector_imm_op_2433_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2433_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2433_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2433_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto mask_vector_imm_op_2433_arg10 = ret_val_sew_2434; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2433, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2434, 0, reinterpret_cast(this)); + setRet(call_sew_2434, 0, ret_val_sew_2434); + setArg(call_mask_vector_imm_op_2433, 0, V); + setArg(call_mask_vector_imm_op_2433, 1, 25); + setArg(call_mask_vector_imm_op_2433, 2, 4); + setArg(call_mask_vector_imm_op_2433, 3, mask_vector_imm_op_2433_arg3); + setArg(call_mask_vector_imm_op_2433, 4, mask_vector_imm_op_2433_arg4); + setArg(call_mask_vector_imm_op_2433, 5, mask_vector_imm_op_2433_arg5); + setArg(call_mask_vector_imm_op_2433, 6, vm); + setArg(call_mask_vector_imm_op_2433, 7, vd); + setArg(call_mask_vector_imm_op_2433, 8, vs2); + setArg(call_mask_vector_imm_op_2433, 9, mask_vector_imm_op_2433_arg9); + setArg(call_mask_vector_imm_op_2433, 10, mask_vector_imm_op_2433_arg10); + } + cc.bind(label_merge); + } + auto tmp2435 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2435, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2435, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 546); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 547: VMSLTU__VV */ + continuation_e __vmsltu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsltu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLTU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 547); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2436; + x86::Gp ret_val_illegal_vd_unmasked_2436 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2436, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2436; + setArg(call_illegal_vd_unmasked_2436, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2436, 0, ret_val_illegal_vd_unmasked_2436); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2438; + x86::Gp ret_val_sew_2438 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2438, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2437; + auto mask_vector_vector_op_2437_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2437_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2437_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2437_arg10 = ret_val_sew_2438; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2437, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2438, 0, reinterpret_cast(this)); + setRet(call_sew_2438, 0, ret_val_sew_2438); + setArg(call_mask_vector_vector_op_2437, 0, V); + setArg(call_mask_vector_vector_op_2437, 1, 26); + setArg(call_mask_vector_vector_op_2437, 2, 0); + setArg(call_mask_vector_vector_op_2437, 3, mask_vector_vector_op_2437_arg3); + setArg(call_mask_vector_vector_op_2437, 4, mask_vector_vector_op_2437_arg4); + setArg(call_mask_vector_vector_op_2437, 5, mask_vector_vector_op_2437_arg5); + setArg(call_mask_vector_vector_op_2437, 6, vm); + setArg(call_mask_vector_vector_op_2437, 7, vd); + setArg(call_mask_vector_vector_op_2437, 8, vs2); + setArg(call_mask_vector_vector_op_2437, 9, vs1); + setArg(call_mask_vector_vector_op_2437, 10, mask_vector_vector_op_2437_arg10); + } + cc.bind(label_merge); + } + auto tmp2439 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2439, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2439, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 547); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 548: VMSLTU__VX */ + continuation_e __vmsltu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsltu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLTU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 548); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2440; + x86::Gp ret_val_illegal_vd_unmasked_2440 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2440, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2441 = get_reg(cc, 8, false); + mov(cc, tmp2441, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2441, ret_val_illegal_vd_unmasked_2440); + setArg(call_illegal_vd_unmasked_2440, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2440, 0, ret_val_illegal_vd_unmasked_2440); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2443; + x86::Gp ret_val_sew_2443 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2443, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2442; + auto mask_vector_imm_op_2442_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2442_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2442_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2442_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto mask_vector_imm_op_2442_arg10 = ret_val_sew_2443; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2442, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2443, 0, reinterpret_cast(this)); + setRet(call_sew_2443, 0, ret_val_sew_2443); + setArg(call_mask_vector_imm_op_2442, 0, V); + setArg(call_mask_vector_imm_op_2442, 1, 26); + setArg(call_mask_vector_imm_op_2442, 2, 4); + setArg(call_mask_vector_imm_op_2442, 3, mask_vector_imm_op_2442_arg3); + setArg(call_mask_vector_imm_op_2442, 4, mask_vector_imm_op_2442_arg4); + setArg(call_mask_vector_imm_op_2442, 5, mask_vector_imm_op_2442_arg5); + setArg(call_mask_vector_imm_op_2442, 6, vm); + setArg(call_mask_vector_imm_op_2442, 7, vd); + setArg(call_mask_vector_imm_op_2442, 8, vs2); + setArg(call_mask_vector_imm_op_2442, 9, mask_vector_imm_op_2442_arg9); + setArg(call_mask_vector_imm_op_2442, 10, mask_vector_imm_op_2442_arg10); + } + cc.bind(label_merge); + } + auto tmp2444 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2444, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2444, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 548); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 549: VMSLT__VV */ + continuation_e __vmslt__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmslt.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLT__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 549); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2445; + x86::Gp ret_val_illegal_vd_unmasked_2445 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2445, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2445; + setArg(call_illegal_vd_unmasked_2445, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2445, 0, ret_val_illegal_vd_unmasked_2445); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2447; + x86::Gp ret_val_sew_2447 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2447, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2446; + auto mask_vector_vector_op_2446_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2446_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2446_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2446_arg10 = ret_val_sew_2447; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2446, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2447, 0, reinterpret_cast(this)); + setRet(call_sew_2447, 0, ret_val_sew_2447); + setArg(call_mask_vector_vector_op_2446, 0, V); + setArg(call_mask_vector_vector_op_2446, 1, 27); + setArg(call_mask_vector_vector_op_2446, 2, 0); + setArg(call_mask_vector_vector_op_2446, 3, mask_vector_vector_op_2446_arg3); + setArg(call_mask_vector_vector_op_2446, 4, mask_vector_vector_op_2446_arg4); + setArg(call_mask_vector_vector_op_2446, 5, mask_vector_vector_op_2446_arg5); + setArg(call_mask_vector_vector_op_2446, 6, vm); + setArg(call_mask_vector_vector_op_2446, 7, vd); + setArg(call_mask_vector_vector_op_2446, 8, vs2); + setArg(call_mask_vector_vector_op_2446, 9, vs1); + setArg(call_mask_vector_vector_op_2446, 10, mask_vector_vector_op_2446_arg10); + } + cc.bind(label_merge); + } + auto tmp2448 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2448, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2448, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 549); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 550: VMSLT__VX */ + continuation_e __vmslt__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmslt.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLT__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 550); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2449; + x86::Gp ret_val_illegal_vd_unmasked_2449 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2449, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2450 = get_reg(cc, 8, false); + mov(cc, tmp2450, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2450, ret_val_illegal_vd_unmasked_2449); + setArg(call_illegal_vd_unmasked_2449, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2449, 0, ret_val_illegal_vd_unmasked_2449); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2452; + x86::Gp ret_val_sew_2452 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2452, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2451; + auto mask_vector_imm_op_2451_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2451_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2451_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2451_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto mask_vector_imm_op_2451_arg10 = ret_val_sew_2452; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2451, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2452, 0, reinterpret_cast(this)); + setRet(call_sew_2452, 0, ret_val_sew_2452); + setArg(call_mask_vector_imm_op_2451, 0, V); + setArg(call_mask_vector_imm_op_2451, 1, 27); + setArg(call_mask_vector_imm_op_2451, 2, 4); + setArg(call_mask_vector_imm_op_2451, 3, mask_vector_imm_op_2451_arg3); + setArg(call_mask_vector_imm_op_2451, 4, mask_vector_imm_op_2451_arg4); + setArg(call_mask_vector_imm_op_2451, 5, mask_vector_imm_op_2451_arg5); + setArg(call_mask_vector_imm_op_2451, 6, vm); + setArg(call_mask_vector_imm_op_2451, 7, vd); + setArg(call_mask_vector_imm_op_2451, 8, vs2); + setArg(call_mask_vector_imm_op_2451, 9, mask_vector_imm_op_2451_arg9); + setArg(call_mask_vector_imm_op_2451, 10, mask_vector_imm_op_2451_arg10); + } + cc.bind(label_merge); + } + auto tmp2453 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2453, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2453, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 550); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 551: VMSLEU__VI */ + continuation_e __vmsleu__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsleu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLEU__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 551); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2454; + x86::Gp ret_val_illegal_vd_unmasked_2454 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2454, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2454; + setArg(call_illegal_vd_unmasked_2454, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2454, 0, ret_val_illegal_vd_unmasked_2454); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2456; + x86::Gp ret_val_sew_2456 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2456, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2455; + auto mask_vector_imm_op_2455_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2455_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2455_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2455_arg10 = ret_val_sew_2456; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2455, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2456, 0, reinterpret_cast(this)); + setRet(call_sew_2456, 0, ret_val_sew_2456); + setArg(call_mask_vector_imm_op_2455, 0, V); + setArg(call_mask_vector_imm_op_2455, 1, 28); + setArg(call_mask_vector_imm_op_2455, 2, 3); + setArg(call_mask_vector_imm_op_2455, 3, mask_vector_imm_op_2455_arg3); + setArg(call_mask_vector_imm_op_2455, 4, mask_vector_imm_op_2455_arg4); + setArg(call_mask_vector_imm_op_2455, 5, mask_vector_imm_op_2455_arg5); + setArg(call_mask_vector_imm_op_2455, 6, vm); + setArg(call_mask_vector_imm_op_2455, 7, vd); + setArg(call_mask_vector_imm_op_2455, 8, vs2); + setArg(call_mask_vector_imm_op_2455, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2455, 10, mask_vector_imm_op_2455_arg10); + } + cc.bind(label_merge); + } + auto tmp2457 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2457, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2457, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 551); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 552: VMSLEU__VV */ + continuation_e __vmsleu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsleu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLEU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 552); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2458; + x86::Gp ret_val_illegal_vd_unmasked_2458 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2458, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2458; + setArg(call_illegal_vd_unmasked_2458, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2458, 0, ret_val_illegal_vd_unmasked_2458); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2460; + x86::Gp ret_val_sew_2460 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2460, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2459; + auto mask_vector_vector_op_2459_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2459_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2459_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2459_arg10 = ret_val_sew_2460; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2459, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2460, 0, reinterpret_cast(this)); + setRet(call_sew_2460, 0, ret_val_sew_2460); + setArg(call_mask_vector_vector_op_2459, 0, V); + setArg(call_mask_vector_vector_op_2459, 1, 28); + setArg(call_mask_vector_vector_op_2459, 2, 0); + setArg(call_mask_vector_vector_op_2459, 3, mask_vector_vector_op_2459_arg3); + setArg(call_mask_vector_vector_op_2459, 4, mask_vector_vector_op_2459_arg4); + setArg(call_mask_vector_vector_op_2459, 5, mask_vector_vector_op_2459_arg5); + setArg(call_mask_vector_vector_op_2459, 6, vm); + setArg(call_mask_vector_vector_op_2459, 7, vd); + setArg(call_mask_vector_vector_op_2459, 8, vs2); + setArg(call_mask_vector_vector_op_2459, 9, vs1); + setArg(call_mask_vector_vector_op_2459, 10, mask_vector_vector_op_2459_arg10); + } + cc.bind(label_merge); + } + auto tmp2461 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2461, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2461, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 552); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 553: VMSLEU__VX */ + continuation_e __vmsleu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsleu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLEU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 553); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2462; + x86::Gp ret_val_illegal_vd_unmasked_2462 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2462, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2463 = get_reg(cc, 8, false); + mov(cc, tmp2463, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2463, ret_val_illegal_vd_unmasked_2462); + setArg(call_illegal_vd_unmasked_2462, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2462, 0, ret_val_illegal_vd_unmasked_2462); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2465; + x86::Gp ret_val_sew_2465 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2465, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2464; + auto mask_vector_imm_op_2464_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2464_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2464_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2464_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto mask_vector_imm_op_2464_arg10 = ret_val_sew_2465; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2464, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2465, 0, reinterpret_cast(this)); + setRet(call_sew_2465, 0, ret_val_sew_2465); + setArg(call_mask_vector_imm_op_2464, 0, V); + setArg(call_mask_vector_imm_op_2464, 1, 28); + setArg(call_mask_vector_imm_op_2464, 2, 4); + setArg(call_mask_vector_imm_op_2464, 3, mask_vector_imm_op_2464_arg3); + setArg(call_mask_vector_imm_op_2464, 4, mask_vector_imm_op_2464_arg4); + setArg(call_mask_vector_imm_op_2464, 5, mask_vector_imm_op_2464_arg5); + setArg(call_mask_vector_imm_op_2464, 6, vm); + setArg(call_mask_vector_imm_op_2464, 7, vd); + setArg(call_mask_vector_imm_op_2464, 8, vs2); + setArg(call_mask_vector_imm_op_2464, 9, mask_vector_imm_op_2464_arg9); + setArg(call_mask_vector_imm_op_2464, 10, mask_vector_imm_op_2464_arg10); + } + cc.bind(label_merge); + } + auto tmp2466 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2466, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2466, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 553); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 554: VMSLE__VI */ + continuation_e __vmsle__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsle.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLE__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 554); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2467; + x86::Gp ret_val_illegal_vd_unmasked_2467 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2467, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2467; + setArg(call_illegal_vd_unmasked_2467, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2467, 0, ret_val_illegal_vd_unmasked_2467); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2469; + x86::Gp ret_val_sew_2469 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2469, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2468; + auto mask_vector_imm_op_2468_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2468_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2468_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2468_arg10 = ret_val_sew_2469; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2468, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2469, 0, reinterpret_cast(this)); + setRet(call_sew_2469, 0, ret_val_sew_2469); + setArg(call_mask_vector_imm_op_2468, 0, V); + setArg(call_mask_vector_imm_op_2468, 1, 29); + setArg(call_mask_vector_imm_op_2468, 2, 3); + setArg(call_mask_vector_imm_op_2468, 3, mask_vector_imm_op_2468_arg3); + setArg(call_mask_vector_imm_op_2468, 4, mask_vector_imm_op_2468_arg4); + setArg(call_mask_vector_imm_op_2468, 5, mask_vector_imm_op_2468_arg5); + setArg(call_mask_vector_imm_op_2468, 6, vm); + setArg(call_mask_vector_imm_op_2468, 7, vd); + setArg(call_mask_vector_imm_op_2468, 8, vs2); + setArg(call_mask_vector_imm_op_2468, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2468, 10, mask_vector_imm_op_2468_arg10); + } + cc.bind(label_merge); + } + auto tmp2470 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2470, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2470, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 554); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 555: VMSLE__VV */ + continuation_e __vmsle__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsle.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLE__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 555); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2471; + x86::Gp ret_val_illegal_vd_unmasked_2471 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2471, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2471; + setArg(call_illegal_vd_unmasked_2471, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2471, 0, ret_val_illegal_vd_unmasked_2471); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2473; + x86::Gp ret_val_sew_2473 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2473, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2472; + auto mask_vector_vector_op_2472_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2472_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2472_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2472_arg10 = ret_val_sew_2473; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2472, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2473, 0, reinterpret_cast(this)); + setRet(call_sew_2473, 0, ret_val_sew_2473); + setArg(call_mask_vector_vector_op_2472, 0, V); + setArg(call_mask_vector_vector_op_2472, 1, 29); + setArg(call_mask_vector_vector_op_2472, 2, 0); + setArg(call_mask_vector_vector_op_2472, 3, mask_vector_vector_op_2472_arg3); + setArg(call_mask_vector_vector_op_2472, 4, mask_vector_vector_op_2472_arg4); + setArg(call_mask_vector_vector_op_2472, 5, mask_vector_vector_op_2472_arg5); + setArg(call_mask_vector_vector_op_2472, 6, vm); + setArg(call_mask_vector_vector_op_2472, 7, vd); + setArg(call_mask_vector_vector_op_2472, 8, vs2); + setArg(call_mask_vector_vector_op_2472, 9, vs1); + setArg(call_mask_vector_vector_op_2472, 10, mask_vector_vector_op_2472_arg10); + } + cc.bind(label_merge); + } + auto tmp2474 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2474, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2474, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 555); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 556: VMSLE__VX */ + continuation_e __vmsle__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsle.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLE__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 556); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2475; + x86::Gp ret_val_illegal_vd_unmasked_2475 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2475, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2476 = get_reg(cc, 8, false); + mov(cc, tmp2476, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2476, ret_val_illegal_vd_unmasked_2475); + setArg(call_illegal_vd_unmasked_2475, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2475, 0, ret_val_illegal_vd_unmasked_2475); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2478; + x86::Gp ret_val_sew_2478 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2478, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2477; + auto mask_vector_imm_op_2477_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2477_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2477_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2477_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto mask_vector_imm_op_2477_arg10 = ret_val_sew_2478; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2477, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2478, 0, reinterpret_cast(this)); + setRet(call_sew_2478, 0, ret_val_sew_2478); + setArg(call_mask_vector_imm_op_2477, 0, V); + setArg(call_mask_vector_imm_op_2477, 1, 29); + setArg(call_mask_vector_imm_op_2477, 2, 4); + setArg(call_mask_vector_imm_op_2477, 3, mask_vector_imm_op_2477_arg3); + setArg(call_mask_vector_imm_op_2477, 4, mask_vector_imm_op_2477_arg4); + setArg(call_mask_vector_imm_op_2477, 5, mask_vector_imm_op_2477_arg5); + setArg(call_mask_vector_imm_op_2477, 6, vm); + setArg(call_mask_vector_imm_op_2477, 7, vd); + setArg(call_mask_vector_imm_op_2477, 8, vs2); + setArg(call_mask_vector_imm_op_2477, 9, mask_vector_imm_op_2477_arg9); + setArg(call_mask_vector_imm_op_2477, 10, mask_vector_imm_op_2477_arg10); + } + cc.bind(label_merge); + } + auto tmp2479 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2479, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2479, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 556); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 557: VMSGTU__VI */ + continuation_e __vmsgtu__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsgtu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSGTU__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 557); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2480; + x86::Gp ret_val_illegal_vd_unmasked_2480 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2480, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2480; + setArg(call_illegal_vd_unmasked_2480, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2480, 0, ret_val_illegal_vd_unmasked_2480); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2482; + x86::Gp ret_val_sew_2482 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2482, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2481; + auto mask_vector_imm_op_2481_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2481_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2481_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2481_arg10 = ret_val_sew_2482; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2481, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2482, 0, reinterpret_cast(this)); + setRet(call_sew_2482, 0, ret_val_sew_2482); + setArg(call_mask_vector_imm_op_2481, 0, V); + setArg(call_mask_vector_imm_op_2481, 1, 30); + setArg(call_mask_vector_imm_op_2481, 2, 3); + setArg(call_mask_vector_imm_op_2481, 3, mask_vector_imm_op_2481_arg3); + setArg(call_mask_vector_imm_op_2481, 4, mask_vector_imm_op_2481_arg4); + setArg(call_mask_vector_imm_op_2481, 5, mask_vector_imm_op_2481_arg5); + setArg(call_mask_vector_imm_op_2481, 6, vm); + setArg(call_mask_vector_imm_op_2481, 7, vd); + setArg(call_mask_vector_imm_op_2481, 8, vs2); + setArg(call_mask_vector_imm_op_2481, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2481, 10, mask_vector_imm_op_2481_arg10); + } + cc.bind(label_merge); + } + auto tmp2483 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2483, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2483, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 557); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 558: VMSGTU__VX */ + continuation_e __vmsgtu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsgtu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSGTU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 558); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2484; + x86::Gp ret_val_illegal_vd_unmasked_2484 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2484, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2485 = get_reg(cc, 8, false); + mov(cc, tmp2485, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2485, ret_val_illegal_vd_unmasked_2484); + setArg(call_illegal_vd_unmasked_2484, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2484, 0, ret_val_illegal_vd_unmasked_2484); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2487; + x86::Gp ret_val_sew_2487 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2487, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2486; + auto mask_vector_imm_op_2486_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2486_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2486_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2486_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto mask_vector_imm_op_2486_arg10 = ret_val_sew_2487; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2486, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2487, 0, reinterpret_cast(this)); + setRet(call_sew_2487, 0, ret_val_sew_2487); + setArg(call_mask_vector_imm_op_2486, 0, V); + setArg(call_mask_vector_imm_op_2486, 1, 30); + setArg(call_mask_vector_imm_op_2486, 2, 4); + setArg(call_mask_vector_imm_op_2486, 3, mask_vector_imm_op_2486_arg3); + setArg(call_mask_vector_imm_op_2486, 4, mask_vector_imm_op_2486_arg4); + setArg(call_mask_vector_imm_op_2486, 5, mask_vector_imm_op_2486_arg5); + setArg(call_mask_vector_imm_op_2486, 6, vm); + setArg(call_mask_vector_imm_op_2486, 7, vd); + setArg(call_mask_vector_imm_op_2486, 8, vs2); + setArg(call_mask_vector_imm_op_2486, 9, mask_vector_imm_op_2486_arg9); + setArg(call_mask_vector_imm_op_2486, 10, mask_vector_imm_op_2486_arg10); + } + cc.bind(label_merge); + } + auto tmp2488 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2488, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2488, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 558); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 559: VMSGT__VI */ + continuation_e __vmsgt__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsgt.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSGT__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 559); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2489; + x86::Gp ret_val_illegal_vd_unmasked_2489 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2489, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2489; + setArg(call_illegal_vd_unmasked_2489, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2489, 0, ret_val_illegal_vd_unmasked_2489); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2491; + x86::Gp ret_val_sew_2491 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2491, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2490; + auto mask_vector_imm_op_2490_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2490_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2490_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2490_arg10 = ret_val_sew_2491; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2490, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2491, 0, reinterpret_cast(this)); + setRet(call_sew_2491, 0, ret_val_sew_2491); + setArg(call_mask_vector_imm_op_2490, 0, V); + setArg(call_mask_vector_imm_op_2490, 1, 31); + setArg(call_mask_vector_imm_op_2490, 2, 3); + setArg(call_mask_vector_imm_op_2490, 3, mask_vector_imm_op_2490_arg3); + setArg(call_mask_vector_imm_op_2490, 4, mask_vector_imm_op_2490_arg4); + setArg(call_mask_vector_imm_op_2490, 5, mask_vector_imm_op_2490_arg5); + setArg(call_mask_vector_imm_op_2490, 6, vm); + setArg(call_mask_vector_imm_op_2490, 7, vd); + setArg(call_mask_vector_imm_op_2490, 8, vs2); + setArg(call_mask_vector_imm_op_2490, 9, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2490, 10, mask_vector_imm_op_2490_arg10); + } + cc.bind(label_merge); + } + auto tmp2492 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2492, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2492, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 559); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 560: VMSGT__VX */ + continuation_e __vmsgt__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsgt.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSGT__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 560); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2493; + x86::Gp ret_val_illegal_vd_unmasked_2493 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2493, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2494 = get_reg(cc, 8, false); + mov(cc, tmp2494, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2494, ret_val_illegal_vd_unmasked_2493); + setArg(call_illegal_vd_unmasked_2493, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2493, 0, ret_val_illegal_vd_unmasked_2493); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2496; + x86::Gp ret_val_sew_2496 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2496, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2495; + auto mask_vector_imm_op_2495_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2495_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2495_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2495_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto mask_vector_imm_op_2495_arg10 = ret_val_sew_2496; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2495, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2496, 0, reinterpret_cast(this)); + setRet(call_sew_2496, 0, ret_val_sew_2496); + setArg(call_mask_vector_imm_op_2495, 0, V); + setArg(call_mask_vector_imm_op_2495, 1, 31); + setArg(call_mask_vector_imm_op_2495, 2, 4); + setArg(call_mask_vector_imm_op_2495, 3, mask_vector_imm_op_2495_arg3); + setArg(call_mask_vector_imm_op_2495, 4, mask_vector_imm_op_2495_arg4); + setArg(call_mask_vector_imm_op_2495, 5, mask_vector_imm_op_2495_arg5); + setArg(call_mask_vector_imm_op_2495, 6, vm); + setArg(call_mask_vector_imm_op_2495, 7, vd); + setArg(call_mask_vector_imm_op_2495, 8, vs2); + setArg(call_mask_vector_imm_op_2495, 9, mask_vector_imm_op_2495_arg9); + setArg(call_mask_vector_imm_op_2495, 10, mask_vector_imm_op_2495_arg10); + } + cc.bind(label_merge); + } + auto tmp2497 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2497, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2497, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 560); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 561: VMINU__VV */ + continuation_e __vminu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vminu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMINU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 561); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2498; + x86::Gp ret_val_illegal_normal_2498 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2498, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2498; + setArg(call_illegal_normal_2498, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2498, 1, vd); + setArg(call_illegal_normal_2498, 2, vm); + setRet(call_illegal_normal_2498, 0, ret_val_illegal_normal_2498); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2500; + x86::Gp ret_val_sew_2500 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2500, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2499; + auto vector_vector_op_2499_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2499_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2499_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2499_arg10 = ret_val_sew_2500; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2499, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2500, 0, reinterpret_cast(this)); + setRet(call_sew_2500, 0, ret_val_sew_2500); + setArg(call_vector_vector_op_2499, 0, V); + setArg(call_vector_vector_op_2499, 1, 4); + setArg(call_vector_vector_op_2499, 2, 0); + setArg(call_vector_vector_op_2499, 3, vector_vector_op_2499_arg3); + setArg(call_vector_vector_op_2499, 4, vector_vector_op_2499_arg4); + setArg(call_vector_vector_op_2499, 5, vector_vector_op_2499_arg5); + setArg(call_vector_vector_op_2499, 6, vm); + setArg(call_vector_vector_op_2499, 7, vd); + setArg(call_vector_vector_op_2499, 8, vs2); + setArg(call_vector_vector_op_2499, 9, vs1); + setArg(call_vector_vector_op_2499, 10, vector_vector_op_2499_arg10); + } + cc.bind(label_merge); + } + auto tmp2501 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2501, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2501, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 561); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 562: VMINU__VX */ + continuation_e __vminu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vminu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMINU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 562); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2502; + x86::Gp ret_val_illegal_normal_2502 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2502, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2503 = get_reg(cc, 8, false); + mov(cc, tmp2503, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2503, ret_val_illegal_normal_2502); + setArg(call_illegal_normal_2502, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2502, 1, vd); + setArg(call_illegal_normal_2502, 2, vm); + setRet(call_illegal_normal_2502, 0, ret_val_illegal_normal_2502); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2505; + x86::Gp ret_val_sew_2505 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2505, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2504; + auto vector_imm_op_2504_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2504_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2504_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2504_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2504_arg10 = ret_val_sew_2505; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2504, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2505, 0, reinterpret_cast(this)); + setRet(call_sew_2505, 0, ret_val_sew_2505); + setArg(call_vector_imm_op_2504, 0, V); + setArg(call_vector_imm_op_2504, 1, 4); + setArg(call_vector_imm_op_2504, 2, 4); + setArg(call_vector_imm_op_2504, 3, vector_imm_op_2504_arg3); + setArg(call_vector_imm_op_2504, 4, vector_imm_op_2504_arg4); + setArg(call_vector_imm_op_2504, 5, vector_imm_op_2504_arg5); + setArg(call_vector_imm_op_2504, 6, vm); + setArg(call_vector_imm_op_2504, 7, vd); + setArg(call_vector_imm_op_2504, 8, vs2); + setArg(call_vector_imm_op_2504, 9, vector_imm_op_2504_arg9); + setArg(call_vector_imm_op_2504, 10, vector_imm_op_2504_arg10); + } + cc.bind(label_merge); + } + auto tmp2506 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2506, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2506, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 562); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 563: VMIN__VV */ + continuation_e __vmin__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmin.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMIN__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 563); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2507; + x86::Gp ret_val_illegal_normal_2507 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2507, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2507; + setArg(call_illegal_normal_2507, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2507, 1, vd); + setArg(call_illegal_normal_2507, 2, vm); + setRet(call_illegal_normal_2507, 0, ret_val_illegal_normal_2507); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2509; + x86::Gp ret_val_sew_2509 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2509, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2508; + auto vector_vector_op_2508_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2508_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2508_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2508_arg10 = ret_val_sew_2509; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2508, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2509, 0, reinterpret_cast(this)); + setRet(call_sew_2509, 0, ret_val_sew_2509); + setArg(call_vector_vector_op_2508, 0, V); + setArg(call_vector_vector_op_2508, 1, 5); + setArg(call_vector_vector_op_2508, 2, 0); + setArg(call_vector_vector_op_2508, 3, vector_vector_op_2508_arg3); + setArg(call_vector_vector_op_2508, 4, vector_vector_op_2508_arg4); + setArg(call_vector_vector_op_2508, 5, vector_vector_op_2508_arg5); + setArg(call_vector_vector_op_2508, 6, vm); + setArg(call_vector_vector_op_2508, 7, vd); + setArg(call_vector_vector_op_2508, 8, vs2); + setArg(call_vector_vector_op_2508, 9, vs1); + setArg(call_vector_vector_op_2508, 10, vector_vector_op_2508_arg10); + } + cc.bind(label_merge); + } + auto tmp2510 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2510, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2510, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 563); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 564: VMIN__VX */ + continuation_e __vmin__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmin.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMIN__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 564); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2511; + x86::Gp ret_val_illegal_normal_2511 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2511, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2512 = get_reg(cc, 8, false); + mov(cc, tmp2512, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2512, ret_val_illegal_normal_2511); + setArg(call_illegal_normal_2511, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2511, 1, vd); + setArg(call_illegal_normal_2511, 2, vm); + setRet(call_illegal_normal_2511, 0, ret_val_illegal_normal_2511); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2514; + x86::Gp ret_val_sew_2514 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2514, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2513; + auto vector_imm_op_2513_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2513_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2513_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2513_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2513_arg10 = ret_val_sew_2514; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2513, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2514, 0, reinterpret_cast(this)); + setRet(call_sew_2514, 0, ret_val_sew_2514); + setArg(call_vector_imm_op_2513, 0, V); + setArg(call_vector_imm_op_2513, 1, 5); + setArg(call_vector_imm_op_2513, 2, 4); + setArg(call_vector_imm_op_2513, 3, vector_imm_op_2513_arg3); + setArg(call_vector_imm_op_2513, 4, vector_imm_op_2513_arg4); + setArg(call_vector_imm_op_2513, 5, vector_imm_op_2513_arg5); + setArg(call_vector_imm_op_2513, 6, vm); + setArg(call_vector_imm_op_2513, 7, vd); + setArg(call_vector_imm_op_2513, 8, vs2); + setArg(call_vector_imm_op_2513, 9, vector_imm_op_2513_arg9); + setArg(call_vector_imm_op_2513, 10, vector_imm_op_2513_arg10); + } + cc.bind(label_merge); + } + auto tmp2515 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2515, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2515, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 564); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 565: VMAXU__VV */ + continuation_e __vmaxu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmaxu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMAXU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 565); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2516; + x86::Gp ret_val_illegal_normal_2516 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2516, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2516; + setArg(call_illegal_normal_2516, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2516, 1, vd); + setArg(call_illegal_normal_2516, 2, vm); + setRet(call_illegal_normal_2516, 0, ret_val_illegal_normal_2516); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2518; + x86::Gp ret_val_sew_2518 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2518, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2517; + auto vector_vector_op_2517_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2517_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2517_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2517_arg10 = ret_val_sew_2518; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2517, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2518, 0, reinterpret_cast(this)); + setRet(call_sew_2518, 0, ret_val_sew_2518); + setArg(call_vector_vector_op_2517, 0, V); + setArg(call_vector_vector_op_2517, 1, 6); + setArg(call_vector_vector_op_2517, 2, 0); + setArg(call_vector_vector_op_2517, 3, vector_vector_op_2517_arg3); + setArg(call_vector_vector_op_2517, 4, vector_vector_op_2517_arg4); + setArg(call_vector_vector_op_2517, 5, vector_vector_op_2517_arg5); + setArg(call_vector_vector_op_2517, 6, vm); + setArg(call_vector_vector_op_2517, 7, vd); + setArg(call_vector_vector_op_2517, 8, vs2); + setArg(call_vector_vector_op_2517, 9, vs1); + setArg(call_vector_vector_op_2517, 10, vector_vector_op_2517_arg10); + } + cc.bind(label_merge); + } + auto tmp2519 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2519, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2519, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 565); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 566: VMAXU__VX */ + continuation_e __vmaxu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmaxu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMAXU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 566); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2520; + x86::Gp ret_val_illegal_normal_2520 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2520, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2521 = get_reg(cc, 8, false); + mov(cc, tmp2521, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2521, ret_val_illegal_normal_2520); + setArg(call_illegal_normal_2520, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2520, 1, vd); + setArg(call_illegal_normal_2520, 2, vm); + setRet(call_illegal_normal_2520, 0, ret_val_illegal_normal_2520); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2523; + x86::Gp ret_val_sew_2523 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2523, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2522; + auto vector_imm_op_2522_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2522_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2522_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2522_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2522_arg10 = ret_val_sew_2523; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2522, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2523, 0, reinterpret_cast(this)); + setRet(call_sew_2523, 0, ret_val_sew_2523); + setArg(call_vector_imm_op_2522, 0, V); + setArg(call_vector_imm_op_2522, 1, 6); + setArg(call_vector_imm_op_2522, 2, 4); + setArg(call_vector_imm_op_2522, 3, vector_imm_op_2522_arg3); + setArg(call_vector_imm_op_2522, 4, vector_imm_op_2522_arg4); + setArg(call_vector_imm_op_2522, 5, vector_imm_op_2522_arg5); + setArg(call_vector_imm_op_2522, 6, vm); + setArg(call_vector_imm_op_2522, 7, vd); + setArg(call_vector_imm_op_2522, 8, vs2); + setArg(call_vector_imm_op_2522, 9, vector_imm_op_2522_arg9); + setArg(call_vector_imm_op_2522, 10, vector_imm_op_2522_arg10); + } + cc.bind(label_merge); + } + auto tmp2524 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2524, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2524, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 566); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 567: VMAX__VV */ + continuation_e __vmax__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmax.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMAX__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 567); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2525; + x86::Gp ret_val_illegal_normal_2525 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2525, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2525; + setArg(call_illegal_normal_2525, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2525, 1, vd); + setArg(call_illegal_normal_2525, 2, vm); + setRet(call_illegal_normal_2525, 0, ret_val_illegal_normal_2525); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2527; + x86::Gp ret_val_sew_2527 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2527, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2526; + auto vector_vector_op_2526_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2526_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2526_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2526_arg10 = ret_val_sew_2527; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2526, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2527, 0, reinterpret_cast(this)); + setRet(call_sew_2527, 0, ret_val_sew_2527); + setArg(call_vector_vector_op_2526, 0, V); + setArg(call_vector_vector_op_2526, 1, 7); + setArg(call_vector_vector_op_2526, 2, 0); + setArg(call_vector_vector_op_2526, 3, vector_vector_op_2526_arg3); + setArg(call_vector_vector_op_2526, 4, vector_vector_op_2526_arg4); + setArg(call_vector_vector_op_2526, 5, vector_vector_op_2526_arg5); + setArg(call_vector_vector_op_2526, 6, vm); + setArg(call_vector_vector_op_2526, 7, vd); + setArg(call_vector_vector_op_2526, 8, vs2); + setArg(call_vector_vector_op_2526, 9, vs1); + setArg(call_vector_vector_op_2526, 10, vector_vector_op_2526_arg10); + } + cc.bind(label_merge); + } + auto tmp2528 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2528, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2528, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 567); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 568: VMAX__VX */ + continuation_e __vmax__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmax.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMAX__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 568); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2529; + x86::Gp ret_val_illegal_normal_2529 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2529, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2530 = get_reg(cc, 8, false); + mov(cc, tmp2530, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2530, ret_val_illegal_normal_2529); + setArg(call_illegal_normal_2529, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2529, 1, vd); + setArg(call_illegal_normal_2529, 2, vm); + setRet(call_illegal_normal_2529, 0, ret_val_illegal_normal_2529); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2532; + x86::Gp ret_val_sew_2532 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2532, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2531; + auto vector_imm_op_2531_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2531_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2531_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2531_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2531_arg10 = ret_val_sew_2532; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2531, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2532, 0, reinterpret_cast(this)); + setRet(call_sew_2532, 0, ret_val_sew_2532); + setArg(call_vector_imm_op_2531, 0, V); + setArg(call_vector_imm_op_2531, 1, 7); + setArg(call_vector_imm_op_2531, 2, 4); + setArg(call_vector_imm_op_2531, 3, vector_imm_op_2531_arg3); + setArg(call_vector_imm_op_2531, 4, vector_imm_op_2531_arg4); + setArg(call_vector_imm_op_2531, 5, vector_imm_op_2531_arg5); + setArg(call_vector_imm_op_2531, 6, vm); + setArg(call_vector_imm_op_2531, 7, vd); + setArg(call_vector_imm_op_2531, 8, vs2); + setArg(call_vector_imm_op_2531, 9, vector_imm_op_2531_arg9); + setArg(call_vector_imm_op_2531, 10, vector_imm_op_2531_arg10); + } + cc.bind(label_merge); + } + auto tmp2533 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2533, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2533, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 568); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 569: VMUL__VV */ + continuation_e __vmul__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMUL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 569); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2534; + x86::Gp ret_val_illegal_normal_2534 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2534, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2534; + setArg(call_illegal_normal_2534, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2534, 1, vd); + setArg(call_illegal_normal_2534, 2, vm); + setRet(call_illegal_normal_2534, 0, ret_val_illegal_normal_2534); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2536; + x86::Gp ret_val_sew_2536 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2536, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2535; + auto vector_vector_op_2535_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2535_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2535_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2535_arg10 = ret_val_sew_2536; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2535, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2536, 0, reinterpret_cast(this)); + setRet(call_sew_2536, 0, ret_val_sew_2536); + setArg(call_vector_vector_op_2535, 0, V); + setArg(call_vector_vector_op_2535, 1, 37); + setArg(call_vector_vector_op_2535, 2, 2); + setArg(call_vector_vector_op_2535, 3, vector_vector_op_2535_arg3); + setArg(call_vector_vector_op_2535, 4, vector_vector_op_2535_arg4); + setArg(call_vector_vector_op_2535, 5, vector_vector_op_2535_arg5); + setArg(call_vector_vector_op_2535, 6, vm); + setArg(call_vector_vector_op_2535, 7, vd); + setArg(call_vector_vector_op_2535, 8, vs2); + setArg(call_vector_vector_op_2535, 9, vs1); + setArg(call_vector_vector_op_2535, 10, vector_vector_op_2535_arg10); + } + cc.bind(label_merge); + } + auto tmp2537 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2537, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2537, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 569); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 570: VMUL__VX */ + continuation_e __vmul__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMUL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 570); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2538; + x86::Gp ret_val_illegal_normal_2538 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2538, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2539 = get_reg(cc, 8, false); + mov(cc, tmp2539, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2539, ret_val_illegal_normal_2538); + setArg(call_illegal_normal_2538, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2538, 1, vd); + setArg(call_illegal_normal_2538, 2, vm); + setRet(call_illegal_normal_2538, 0, ret_val_illegal_normal_2538); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2541; + x86::Gp ret_val_sew_2541 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2541, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2540; + auto vector_imm_op_2540_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2540_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2540_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2540_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2540_arg10 = ret_val_sew_2541; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2540, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2541, 0, reinterpret_cast(this)); + setRet(call_sew_2541, 0, ret_val_sew_2541); + setArg(call_vector_imm_op_2540, 0, V); + setArg(call_vector_imm_op_2540, 1, 37); + setArg(call_vector_imm_op_2540, 2, 6); + setArg(call_vector_imm_op_2540, 3, vector_imm_op_2540_arg3); + setArg(call_vector_imm_op_2540, 4, vector_imm_op_2540_arg4); + setArg(call_vector_imm_op_2540, 5, vector_imm_op_2540_arg5); + setArg(call_vector_imm_op_2540, 6, vm); + setArg(call_vector_imm_op_2540, 7, vd); + setArg(call_vector_imm_op_2540, 8, vs2); + setArg(call_vector_imm_op_2540, 9, vector_imm_op_2540_arg9); + setArg(call_vector_imm_op_2540, 10, vector_imm_op_2540_arg10); + } + cc.bind(label_merge); + } + auto tmp2542 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2542, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2542, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 570); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 571: VMULH__VV */ + continuation_e __vmulh__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulh.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULH__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 571); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2543; + x86::Gp ret_val_illegal_normal_2543 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2543, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2543; + setArg(call_illegal_normal_2543, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2543, 1, vd); + setArg(call_illegal_normal_2543, 2, vm); + setRet(call_illegal_normal_2543, 0, ret_val_illegal_normal_2543); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2545; + x86::Gp ret_val_sew_2545 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2545, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2544; + auto vector_vector_op_2544_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2544_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2544_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2544_arg10 = ret_val_sew_2545; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2544, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2545, 0, reinterpret_cast(this)); + setRet(call_sew_2545, 0, ret_val_sew_2545); + setArg(call_vector_vector_op_2544, 0, V); + setArg(call_vector_vector_op_2544, 1, 39); + setArg(call_vector_vector_op_2544, 2, 2); + setArg(call_vector_vector_op_2544, 3, vector_vector_op_2544_arg3); + setArg(call_vector_vector_op_2544, 4, vector_vector_op_2544_arg4); + setArg(call_vector_vector_op_2544, 5, vector_vector_op_2544_arg5); + setArg(call_vector_vector_op_2544, 6, vm); + setArg(call_vector_vector_op_2544, 7, vd); + setArg(call_vector_vector_op_2544, 8, vs2); + setArg(call_vector_vector_op_2544, 9, vs1); + setArg(call_vector_vector_op_2544, 10, vector_vector_op_2544_arg10); + } + cc.bind(label_merge); + } + auto tmp2546 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2546, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2546, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 571); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 572: VMULH__VX */ + continuation_e __vmulh__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulh.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULH__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 572); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2547; + x86::Gp ret_val_illegal_normal_2547 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2547, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2548 = get_reg(cc, 8, false); + mov(cc, tmp2548, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2548, ret_val_illegal_normal_2547); + setArg(call_illegal_normal_2547, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2547, 1, vd); + setArg(call_illegal_normal_2547, 2, vm); + setRet(call_illegal_normal_2547, 0, ret_val_illegal_normal_2547); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2550; + x86::Gp ret_val_sew_2550 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2550, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2549; + auto vector_imm_op_2549_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2549_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2549_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2549_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2549_arg10 = ret_val_sew_2550; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2549, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2550, 0, reinterpret_cast(this)); + setRet(call_sew_2550, 0, ret_val_sew_2550); + setArg(call_vector_imm_op_2549, 0, V); + setArg(call_vector_imm_op_2549, 1, 39); + setArg(call_vector_imm_op_2549, 2, 6); + setArg(call_vector_imm_op_2549, 3, vector_imm_op_2549_arg3); + setArg(call_vector_imm_op_2549, 4, vector_imm_op_2549_arg4); + setArg(call_vector_imm_op_2549, 5, vector_imm_op_2549_arg5); + setArg(call_vector_imm_op_2549, 6, vm); + setArg(call_vector_imm_op_2549, 7, vd); + setArg(call_vector_imm_op_2549, 8, vs2); + setArg(call_vector_imm_op_2549, 9, vector_imm_op_2549_arg9); + setArg(call_vector_imm_op_2549, 10, vector_imm_op_2549_arg10); + } + cc.bind(label_merge); + } + auto tmp2551 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2551, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2551, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 572); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 573: VMULHU__VV */ + continuation_e __vmulhu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulhu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULHU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 573); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2552; + x86::Gp ret_val_illegal_normal_2552 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2552, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2552; + setArg(call_illegal_normal_2552, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2552, 1, vd); + setArg(call_illegal_normal_2552, 2, vm); + setRet(call_illegal_normal_2552, 0, ret_val_illegal_normal_2552); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2554; + x86::Gp ret_val_sew_2554 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2554, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2553; + auto vector_vector_op_2553_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2553_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2553_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2553_arg10 = ret_val_sew_2554; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2553, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2554, 0, reinterpret_cast(this)); + setRet(call_sew_2554, 0, ret_val_sew_2554); + setArg(call_vector_vector_op_2553, 0, V); + setArg(call_vector_vector_op_2553, 1, 36); + setArg(call_vector_vector_op_2553, 2, 2); + setArg(call_vector_vector_op_2553, 3, vector_vector_op_2553_arg3); + setArg(call_vector_vector_op_2553, 4, vector_vector_op_2553_arg4); + setArg(call_vector_vector_op_2553, 5, vector_vector_op_2553_arg5); + setArg(call_vector_vector_op_2553, 6, vm); + setArg(call_vector_vector_op_2553, 7, vd); + setArg(call_vector_vector_op_2553, 8, vs2); + setArg(call_vector_vector_op_2553, 9, vs1); + setArg(call_vector_vector_op_2553, 10, vector_vector_op_2553_arg10); + } + cc.bind(label_merge); + } + auto tmp2555 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2555, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2555, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 573); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 574: VMULHU__VX */ + continuation_e __vmulhu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulhu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULHU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 574); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2556; + x86::Gp ret_val_illegal_normal_2556 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2556, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2557 = get_reg(cc, 8, false); + mov(cc, tmp2557, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2557, ret_val_illegal_normal_2556); + setArg(call_illegal_normal_2556, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2556, 1, vd); + setArg(call_illegal_normal_2556, 2, vm); + setRet(call_illegal_normal_2556, 0, ret_val_illegal_normal_2556); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2559; + x86::Gp ret_val_sew_2559 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2559, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2558; + auto vector_imm_op_2558_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2558_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2558_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2558_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2558_arg10 = ret_val_sew_2559; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2558, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2559, 0, reinterpret_cast(this)); + setRet(call_sew_2559, 0, ret_val_sew_2559); + setArg(call_vector_imm_op_2558, 0, V); + setArg(call_vector_imm_op_2558, 1, 36); + setArg(call_vector_imm_op_2558, 2, 6); + setArg(call_vector_imm_op_2558, 3, vector_imm_op_2558_arg3); + setArg(call_vector_imm_op_2558, 4, vector_imm_op_2558_arg4); + setArg(call_vector_imm_op_2558, 5, vector_imm_op_2558_arg5); + setArg(call_vector_imm_op_2558, 6, vm); + setArg(call_vector_imm_op_2558, 7, vd); + setArg(call_vector_imm_op_2558, 8, vs2); + setArg(call_vector_imm_op_2558, 9, vector_imm_op_2558_arg9); + setArg(call_vector_imm_op_2558, 10, vector_imm_op_2558_arg10); + } + cc.bind(label_merge); + } + auto tmp2560 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2560, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2560, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 574); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 575: VMULHSU__VV */ + continuation_e __vmulhsu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulhsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULHSU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 575); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2561; + x86::Gp ret_val_illegal_normal_2561 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2561, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2561; + setArg(call_illegal_normal_2561, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2561, 1, vd); + setArg(call_illegal_normal_2561, 2, vm); + setRet(call_illegal_normal_2561, 0, ret_val_illegal_normal_2561); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2563; + x86::Gp ret_val_sew_2563 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2563, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2562; + auto vector_vector_op_2562_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2562_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2562_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2562_arg10 = ret_val_sew_2563; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2562, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2563, 0, reinterpret_cast(this)); + setRet(call_sew_2563, 0, ret_val_sew_2563); + setArg(call_vector_vector_op_2562, 0, V); + setArg(call_vector_vector_op_2562, 1, 38); + setArg(call_vector_vector_op_2562, 2, 2); + setArg(call_vector_vector_op_2562, 3, vector_vector_op_2562_arg3); + setArg(call_vector_vector_op_2562, 4, vector_vector_op_2562_arg4); + setArg(call_vector_vector_op_2562, 5, vector_vector_op_2562_arg5); + setArg(call_vector_vector_op_2562, 6, vm); + setArg(call_vector_vector_op_2562, 7, vd); + setArg(call_vector_vector_op_2562, 8, vs2); + setArg(call_vector_vector_op_2562, 9, vs1); + setArg(call_vector_vector_op_2562, 10, vector_vector_op_2562_arg10); + } + cc.bind(label_merge); + } + auto tmp2564 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2564, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2564, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 575); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 576: VMULHSU__VX */ + continuation_e __vmulhsu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulhsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULHSU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 576); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2565; + x86::Gp ret_val_illegal_normal_2565 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2565, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2566 = get_reg(cc, 8, false); + mov(cc, tmp2566, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2566, ret_val_illegal_normal_2565); + setArg(call_illegal_normal_2565, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2565, 1, vd); + setArg(call_illegal_normal_2565, 2, vm); + setRet(call_illegal_normal_2565, 0, ret_val_illegal_normal_2565); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2568; + x86::Gp ret_val_sew_2568 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2568, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2567; + auto vector_imm_op_2567_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2567_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2567_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2567_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2567_arg10 = ret_val_sew_2568; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2567, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2568, 0, reinterpret_cast(this)); + setRet(call_sew_2568, 0, ret_val_sew_2568); + setArg(call_vector_imm_op_2567, 0, V); + setArg(call_vector_imm_op_2567, 1, 38); + setArg(call_vector_imm_op_2567, 2, 6); + setArg(call_vector_imm_op_2567, 3, vector_imm_op_2567_arg3); + setArg(call_vector_imm_op_2567, 4, vector_imm_op_2567_arg4); + setArg(call_vector_imm_op_2567, 5, vector_imm_op_2567_arg5); + setArg(call_vector_imm_op_2567, 6, vm); + setArg(call_vector_imm_op_2567, 7, vd); + setArg(call_vector_imm_op_2567, 8, vs2); + setArg(call_vector_imm_op_2567, 9, vector_imm_op_2567_arg9); + setArg(call_vector_imm_op_2567, 10, vector_imm_op_2567_arg10); + } + cc.bind(label_merge); + } + auto tmp2569 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2569, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2569, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 576); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 577: VDIVU__VV */ + continuation_e __vdivu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vdivu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VDIVU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 577); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2570; + x86::Gp ret_val_illegal_normal_2570 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2570, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2570; + setArg(call_illegal_normal_2570, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2570, 1, vd); + setArg(call_illegal_normal_2570, 2, vm); + setRet(call_illegal_normal_2570, 0, ret_val_illegal_normal_2570); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2572; + x86::Gp ret_val_sew_2572 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2572, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2571; + auto vector_vector_op_2571_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2571_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2571_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2571_arg10 = ret_val_sew_2572; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2571, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2572, 0, reinterpret_cast(this)); + setRet(call_sew_2572, 0, ret_val_sew_2572); + setArg(call_vector_vector_op_2571, 0, V); + setArg(call_vector_vector_op_2571, 1, 32); + setArg(call_vector_vector_op_2571, 2, 2); + setArg(call_vector_vector_op_2571, 3, vector_vector_op_2571_arg3); + setArg(call_vector_vector_op_2571, 4, vector_vector_op_2571_arg4); + setArg(call_vector_vector_op_2571, 5, vector_vector_op_2571_arg5); + setArg(call_vector_vector_op_2571, 6, vm); + setArg(call_vector_vector_op_2571, 7, vd); + setArg(call_vector_vector_op_2571, 8, vs2); + setArg(call_vector_vector_op_2571, 9, vs1); + setArg(call_vector_vector_op_2571, 10, vector_vector_op_2571_arg10); + } + cc.bind(label_merge); + } + auto tmp2573 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2573, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2573, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 577); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 578: VDIVU__VX */ + continuation_e __vdivu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vdivu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VDIVU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 578); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2574; + x86::Gp ret_val_illegal_normal_2574 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2574, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2575 = get_reg(cc, 8, false); + mov(cc, tmp2575, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2575, ret_val_illegal_normal_2574); + setArg(call_illegal_normal_2574, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2574, 1, vd); + setArg(call_illegal_normal_2574, 2, vm); + setRet(call_illegal_normal_2574, 0, ret_val_illegal_normal_2574); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2577; + x86::Gp ret_val_sew_2577 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2577, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2576; + auto vector_imm_op_2576_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2576_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2576_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2576_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2576_arg10 = ret_val_sew_2577; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2576, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2577, 0, reinterpret_cast(this)); + setRet(call_sew_2577, 0, ret_val_sew_2577); + setArg(call_vector_imm_op_2576, 0, V); + setArg(call_vector_imm_op_2576, 1, 32); + setArg(call_vector_imm_op_2576, 2, 6); + setArg(call_vector_imm_op_2576, 3, vector_imm_op_2576_arg3); + setArg(call_vector_imm_op_2576, 4, vector_imm_op_2576_arg4); + setArg(call_vector_imm_op_2576, 5, vector_imm_op_2576_arg5); + setArg(call_vector_imm_op_2576, 6, vm); + setArg(call_vector_imm_op_2576, 7, vd); + setArg(call_vector_imm_op_2576, 8, vs2); + setArg(call_vector_imm_op_2576, 9, vector_imm_op_2576_arg9); + setArg(call_vector_imm_op_2576, 10, vector_imm_op_2576_arg10); + } + cc.bind(label_merge); + } + auto tmp2578 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2578, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2578, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 578); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 579: VDIV__VV */ + continuation_e __vdiv__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vdiv.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VDIV__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 579); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2579; + x86::Gp ret_val_illegal_normal_2579 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2579, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2579; + setArg(call_illegal_normal_2579, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2579, 1, vd); + setArg(call_illegal_normal_2579, 2, vm); + setRet(call_illegal_normal_2579, 0, ret_val_illegal_normal_2579); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2581; + x86::Gp ret_val_sew_2581 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2581, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2580; + auto vector_vector_op_2580_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2580_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2580_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2580_arg10 = ret_val_sew_2581; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2580, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2581, 0, reinterpret_cast(this)); + setRet(call_sew_2581, 0, ret_val_sew_2581); + setArg(call_vector_vector_op_2580, 0, V); + setArg(call_vector_vector_op_2580, 1, 33); + setArg(call_vector_vector_op_2580, 2, 2); + setArg(call_vector_vector_op_2580, 3, vector_vector_op_2580_arg3); + setArg(call_vector_vector_op_2580, 4, vector_vector_op_2580_arg4); + setArg(call_vector_vector_op_2580, 5, vector_vector_op_2580_arg5); + setArg(call_vector_vector_op_2580, 6, vm); + setArg(call_vector_vector_op_2580, 7, vd); + setArg(call_vector_vector_op_2580, 8, vs2); + setArg(call_vector_vector_op_2580, 9, vs1); + setArg(call_vector_vector_op_2580, 10, vector_vector_op_2580_arg10); + } + cc.bind(label_merge); + } + auto tmp2582 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2582, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2582, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 579); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 580: VDIV__VX */ + continuation_e __vdiv__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vdiv.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VDIV__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 580); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2583; + x86::Gp ret_val_illegal_normal_2583 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2583, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2584 = get_reg(cc, 8, false); + mov(cc, tmp2584, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2584, ret_val_illegal_normal_2583); + setArg(call_illegal_normal_2583, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2583, 1, vd); + setArg(call_illegal_normal_2583, 2, vm); + setRet(call_illegal_normal_2583, 0, ret_val_illegal_normal_2583); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2586; + x86::Gp ret_val_sew_2586 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2586, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2585; + auto vector_imm_op_2585_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2585_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2585_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2585_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2585_arg10 = ret_val_sew_2586; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2585, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2586, 0, reinterpret_cast(this)); + setRet(call_sew_2586, 0, ret_val_sew_2586); + setArg(call_vector_imm_op_2585, 0, V); + setArg(call_vector_imm_op_2585, 1, 33); + setArg(call_vector_imm_op_2585, 2, 6); + setArg(call_vector_imm_op_2585, 3, vector_imm_op_2585_arg3); + setArg(call_vector_imm_op_2585, 4, vector_imm_op_2585_arg4); + setArg(call_vector_imm_op_2585, 5, vector_imm_op_2585_arg5); + setArg(call_vector_imm_op_2585, 6, vm); + setArg(call_vector_imm_op_2585, 7, vd); + setArg(call_vector_imm_op_2585, 8, vs2); + setArg(call_vector_imm_op_2585, 9, vector_imm_op_2585_arg9); + setArg(call_vector_imm_op_2585, 10, vector_imm_op_2585_arg10); + } + cc.bind(label_merge); + } + auto tmp2587 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2587, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2587, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 580); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 581: VREMU__VV */ + continuation_e __vremu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vremu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREMU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 581); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2588; + x86::Gp ret_val_illegal_normal_2588 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2588, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2588; + setArg(call_illegal_normal_2588, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2588, 1, vd); + setArg(call_illegal_normal_2588, 2, vm); + setRet(call_illegal_normal_2588, 0, ret_val_illegal_normal_2588); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2590; + x86::Gp ret_val_sew_2590 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2590, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2589; + auto vector_vector_op_2589_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2589_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2589_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2589_arg10 = ret_val_sew_2590; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2589, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2590, 0, reinterpret_cast(this)); + setRet(call_sew_2590, 0, ret_val_sew_2590); + setArg(call_vector_vector_op_2589, 0, V); + setArg(call_vector_vector_op_2589, 1, 34); + setArg(call_vector_vector_op_2589, 2, 2); + setArg(call_vector_vector_op_2589, 3, vector_vector_op_2589_arg3); + setArg(call_vector_vector_op_2589, 4, vector_vector_op_2589_arg4); + setArg(call_vector_vector_op_2589, 5, vector_vector_op_2589_arg5); + setArg(call_vector_vector_op_2589, 6, vm); + setArg(call_vector_vector_op_2589, 7, vd); + setArg(call_vector_vector_op_2589, 8, vs2); + setArg(call_vector_vector_op_2589, 9, vs1); + setArg(call_vector_vector_op_2589, 10, vector_vector_op_2589_arg10); + } + cc.bind(label_merge); + } + auto tmp2591 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2591, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2591, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 581); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 582: VREMU__VX */ + continuation_e __vremu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vremu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREMU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 582); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2592; + x86::Gp ret_val_illegal_normal_2592 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2592, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2593 = get_reg(cc, 8, false); + mov(cc, tmp2593, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2593, ret_val_illegal_normal_2592); + setArg(call_illegal_normal_2592, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2592, 1, vd); + setArg(call_illegal_normal_2592, 2, vm); + setRet(call_illegal_normal_2592, 0, ret_val_illegal_normal_2592); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2595; + x86::Gp ret_val_sew_2595 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2595, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2594; + auto vector_imm_op_2594_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2594_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2594_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2594_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2594_arg10 = ret_val_sew_2595; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2594, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2595, 0, reinterpret_cast(this)); + setRet(call_sew_2595, 0, ret_val_sew_2595); + setArg(call_vector_imm_op_2594, 0, V); + setArg(call_vector_imm_op_2594, 1, 34); + setArg(call_vector_imm_op_2594, 2, 6); + setArg(call_vector_imm_op_2594, 3, vector_imm_op_2594_arg3); + setArg(call_vector_imm_op_2594, 4, vector_imm_op_2594_arg4); + setArg(call_vector_imm_op_2594, 5, vector_imm_op_2594_arg5); + setArg(call_vector_imm_op_2594, 6, vm); + setArg(call_vector_imm_op_2594, 7, vd); + setArg(call_vector_imm_op_2594, 8, vs2); + setArg(call_vector_imm_op_2594, 9, vector_imm_op_2594_arg9); + setArg(call_vector_imm_op_2594, 10, vector_imm_op_2594_arg10); + } + cc.bind(label_merge); + } + auto tmp2596 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2596, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2596, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 582); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 583: VREM__VV */ + continuation_e __vrem__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrem.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREM__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 583); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2597; + x86::Gp ret_val_illegal_normal_2597 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2597, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2597; + setArg(call_illegal_normal_2597, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2597, 1, vd); + setArg(call_illegal_normal_2597, 2, vm); + setRet(call_illegal_normal_2597, 0, ret_val_illegal_normal_2597); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2599; + x86::Gp ret_val_sew_2599 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2599, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2598; + auto vector_vector_op_2598_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2598_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2598_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2598_arg10 = ret_val_sew_2599; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2598, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2599, 0, reinterpret_cast(this)); + setRet(call_sew_2599, 0, ret_val_sew_2599); + setArg(call_vector_vector_op_2598, 0, V); + setArg(call_vector_vector_op_2598, 1, 35); + setArg(call_vector_vector_op_2598, 2, 2); + setArg(call_vector_vector_op_2598, 3, vector_vector_op_2598_arg3); + setArg(call_vector_vector_op_2598, 4, vector_vector_op_2598_arg4); + setArg(call_vector_vector_op_2598, 5, vector_vector_op_2598_arg5); + setArg(call_vector_vector_op_2598, 6, vm); + setArg(call_vector_vector_op_2598, 7, vd); + setArg(call_vector_vector_op_2598, 8, vs2); + setArg(call_vector_vector_op_2598, 9, vs1); + setArg(call_vector_vector_op_2598, 10, vector_vector_op_2598_arg10); + } + cc.bind(label_merge); + } + auto tmp2600 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2600, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2600, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 583); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 584: VREM__VX */ + continuation_e __vrem__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrem.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREM__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 584); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2601; + x86::Gp ret_val_illegal_normal_2601 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2601, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2602 = get_reg(cc, 8, false); + mov(cc, tmp2602, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2602, ret_val_illegal_normal_2601); + setArg(call_illegal_normal_2601, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2601, 1, vd); + setArg(call_illegal_normal_2601, 2, vm); + setRet(call_illegal_normal_2601, 0, ret_val_illegal_normal_2601); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2604; + x86::Gp ret_val_sew_2604 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2604, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2603; + auto vector_imm_op_2603_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2603_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2603_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2603_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2603_arg10 = ret_val_sew_2604; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2603, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2604, 0, reinterpret_cast(this)); + setRet(call_sew_2604, 0, ret_val_sew_2604); + setArg(call_vector_imm_op_2603, 0, V); + setArg(call_vector_imm_op_2603, 1, 35); + setArg(call_vector_imm_op_2603, 2, 6); + setArg(call_vector_imm_op_2603, 3, vector_imm_op_2603_arg3); + setArg(call_vector_imm_op_2603, 4, vector_imm_op_2603_arg4); + setArg(call_vector_imm_op_2603, 5, vector_imm_op_2603_arg5); + setArg(call_vector_imm_op_2603, 6, vm); + setArg(call_vector_imm_op_2603, 7, vd); + setArg(call_vector_imm_op_2603, 8, vs2); + setArg(call_vector_imm_op_2603, 9, vector_imm_op_2603_arg9); + setArg(call_vector_imm_op_2603, 10, vector_imm_op_2603_arg10); + } + cc.bind(label_merge); + } + auto tmp2605 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2605, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2605, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 584); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 585: VWMUL__VV */ + continuation_e __vwmul__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMUL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 585); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2606; + x86::Gp ret_val_get_sew_pow_2606 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2606, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2607 = get_reg(cc, 8, false); + mov(cc, tmp2607, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2607, ret_val_get_sew_pow_2606)), 8, false), ~ 1); + setArg(call_get_sew_pow_2606, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2606, 0, ret_val_get_sew_pow_2606); + InvokeNode* call_get_lmul_pow_2608; + x86::Gp ret_val_get_lmul_pow_2608 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2608, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2608; + setArg(call_get_lmul_pow_2608, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2608, 0, ret_val_get_lmul_pow_2608); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2609; + auto illegal_variable_width_2609_arg2 = SEW_widen; + auto illegal_variable_width_2609_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2609 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2609, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2610; + auto valid_reg_overlap_2610_arg2 = LMUL_pow; + auto valid_reg_overlap_2610_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2610 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2610, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2611; + auto valid_reg_overlap_2611_arg2 = LMUL_pow; + auto valid_reg_overlap_2611_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2611 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2611, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2609, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2610)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2611)); + setArg(call_illegal_variable_width_2609, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2609, 1, vd); + setArg(call_illegal_variable_width_2609, 2, vm); + setArg(call_illegal_variable_width_2609, 3, illegal_variable_width_2609_arg2); + setArg(call_illegal_variable_width_2609, 4, illegal_variable_width_2609_arg3); + setRet(call_illegal_variable_width_2609, 0, ret_val_illegal_variable_width_2609); + setArg(call_valid_reg_overlap_2610, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2610, 1, vs1); + setArg(call_valid_reg_overlap_2610, 2, vd); + setArg(call_valid_reg_overlap_2610, 3, valid_reg_overlap_2610_arg2); + setArg(call_valid_reg_overlap_2610, 4, valid_reg_overlap_2610_arg3); + setRet(call_valid_reg_overlap_2610, 0, ret_val_valid_reg_overlap_2610); + setArg(call_valid_reg_overlap_2611, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2611, 1, vs2); + setArg(call_valid_reg_overlap_2611, 2, vd); + setArg(call_valid_reg_overlap_2611, 3, valid_reg_overlap_2611_arg2); + setArg(call_valid_reg_overlap_2611, 4, valid_reg_overlap_2611_arg3); + setRet(call_valid_reg_overlap_2611, 0, ret_val_valid_reg_overlap_2611); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2613; + x86::Gp ret_val_sew_2613 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2613, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2612; + auto vector_vector_wv_2612_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2612_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2612_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2612_arg10 = ret_val_sew_2613; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2612, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2613, 0, reinterpret_cast(this)); + setRet(call_sew_2613, 0, ret_val_sew_2613); + setArg(call_vector_vector_wv_2612, 0, V); + setArg(call_vector_vector_wv_2612, 1, 59); + setArg(call_vector_vector_wv_2612, 2, 2); + setArg(call_vector_vector_wv_2612, 3, vector_vector_wv_2612_arg3); + setArg(call_vector_vector_wv_2612, 4, vector_vector_wv_2612_arg4); + setArg(call_vector_vector_wv_2612, 5, vector_vector_wv_2612_arg5); + setArg(call_vector_vector_wv_2612, 6, vm); + setArg(call_vector_vector_wv_2612, 7, vd); + setArg(call_vector_vector_wv_2612, 8, vs2); + setArg(call_vector_vector_wv_2612, 9, vs1); + setArg(call_vector_vector_wv_2612, 10, vector_vector_wv_2612_arg10); + } + cc.bind(label_merge); + } + auto tmp2614 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2614, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2614, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 585); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 586: VWMUL__VX */ + continuation_e __vwmul__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMUL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 586); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2615; + x86::Gp ret_val_get_sew_pow_2615 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2615, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2616 = get_reg(cc, 8, false); + mov(cc, tmp2616, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2616, ret_val_get_sew_pow_2615)), 8, false), ~ 1); + setArg(call_get_sew_pow_2615, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2615, 0, ret_val_get_sew_pow_2615); + InvokeNode* call_get_lmul_pow_2617; + x86::Gp ret_val_get_lmul_pow_2617 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2617, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2617; + setArg(call_get_lmul_pow_2617, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2617, 0, ret_val_get_lmul_pow_2617); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2618; + auto illegal_variable_width_2618_arg2 = SEW_widen; + auto illegal_variable_width_2618_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2618 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2618, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2619; + auto valid_reg_overlap_2619_arg2 = LMUL_pow; + auto valid_reg_overlap_2619_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2619 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2619, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2618, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2619)); + setArg(call_illegal_variable_width_2618, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2618, 1, vd); + setArg(call_illegal_variable_width_2618, 2, vm); + setArg(call_illegal_variable_width_2618, 3, illegal_variable_width_2618_arg2); + setArg(call_illegal_variable_width_2618, 4, illegal_variable_width_2618_arg3); + setRet(call_illegal_variable_width_2618, 0, ret_val_illegal_variable_width_2618); + setArg(call_valid_reg_overlap_2619, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2619, 1, vs2); + setArg(call_valid_reg_overlap_2619, 2, vd); + setArg(call_valid_reg_overlap_2619, 3, valid_reg_overlap_2619_arg2); + setArg(call_valid_reg_overlap_2619, 4, valid_reg_overlap_2619_arg3); + setRet(call_valid_reg_overlap_2619, 0, ret_val_valid_reg_overlap_2619); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2621; + x86::Gp ret_val_sew_2621 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2621, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2620; + auto vector_imm_wv_2620_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2620_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2620_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2620_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2620_arg10 = ret_val_sew_2621; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2620, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2621, 0, reinterpret_cast(this)); + setRet(call_sew_2621, 0, ret_val_sew_2621); + setArg(call_vector_imm_wv_2620, 0, V); + setArg(call_vector_imm_wv_2620, 1, 59); + setArg(call_vector_imm_wv_2620, 2, 6); + setArg(call_vector_imm_wv_2620, 3, vector_imm_wv_2620_arg3); + setArg(call_vector_imm_wv_2620, 4, vector_imm_wv_2620_arg4); + setArg(call_vector_imm_wv_2620, 5, vector_imm_wv_2620_arg5); + setArg(call_vector_imm_wv_2620, 6, vm); + setArg(call_vector_imm_wv_2620, 7, vd); + setArg(call_vector_imm_wv_2620, 8, vs2); + setArg(call_vector_imm_wv_2620, 9, vector_imm_wv_2620_arg9); + setArg(call_vector_imm_wv_2620, 10, vector_imm_wv_2620_arg10); + } + cc.bind(label_merge); + } + auto tmp2622 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2622, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2622, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 586); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 587: VWMULU__VV */ + continuation_e __vwmulu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmulu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMULU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 587); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2623; + x86::Gp ret_val_get_sew_pow_2623 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2623, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2624 = get_reg(cc, 8, false); + mov(cc, tmp2624, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2624, ret_val_get_sew_pow_2623)), 8, false), ~ 1); + setArg(call_get_sew_pow_2623, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2623, 0, ret_val_get_sew_pow_2623); + InvokeNode* call_get_lmul_pow_2625; + x86::Gp ret_val_get_lmul_pow_2625 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2625, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2625; + setArg(call_get_lmul_pow_2625, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2625, 0, ret_val_get_lmul_pow_2625); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2626; + auto illegal_variable_width_2626_arg2 = SEW_widen; + auto illegal_variable_width_2626_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2626 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2626, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2627; + auto valid_reg_overlap_2627_arg2 = LMUL_pow; + auto valid_reg_overlap_2627_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2627 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2627, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2628; + auto valid_reg_overlap_2628_arg2 = LMUL_pow; + auto valid_reg_overlap_2628_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2628 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2628, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2626, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2627)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2628)); + setArg(call_illegal_variable_width_2626, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2626, 1, vd); + setArg(call_illegal_variable_width_2626, 2, vm); + setArg(call_illegal_variable_width_2626, 3, illegal_variable_width_2626_arg2); + setArg(call_illegal_variable_width_2626, 4, illegal_variable_width_2626_arg3); + setRet(call_illegal_variable_width_2626, 0, ret_val_illegal_variable_width_2626); + setArg(call_valid_reg_overlap_2627, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2627, 1, vs1); + setArg(call_valid_reg_overlap_2627, 2, vd); + setArg(call_valid_reg_overlap_2627, 3, valid_reg_overlap_2627_arg2); + setArg(call_valid_reg_overlap_2627, 4, valid_reg_overlap_2627_arg3); + setRet(call_valid_reg_overlap_2627, 0, ret_val_valid_reg_overlap_2627); + setArg(call_valid_reg_overlap_2628, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2628, 1, vs2); + setArg(call_valid_reg_overlap_2628, 2, vd); + setArg(call_valid_reg_overlap_2628, 3, valid_reg_overlap_2628_arg2); + setArg(call_valid_reg_overlap_2628, 4, valid_reg_overlap_2628_arg3); + setRet(call_valid_reg_overlap_2628, 0, ret_val_valid_reg_overlap_2628); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2630; + x86::Gp ret_val_sew_2630 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2630, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2629; + auto vector_vector_wv_2629_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2629_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2629_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2629_arg10 = ret_val_sew_2630; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2629, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2630, 0, reinterpret_cast(this)); + setRet(call_sew_2630, 0, ret_val_sew_2630); + setArg(call_vector_vector_wv_2629, 0, V); + setArg(call_vector_vector_wv_2629, 1, 56); + setArg(call_vector_vector_wv_2629, 2, 2); + setArg(call_vector_vector_wv_2629, 3, vector_vector_wv_2629_arg3); + setArg(call_vector_vector_wv_2629, 4, vector_vector_wv_2629_arg4); + setArg(call_vector_vector_wv_2629, 5, vector_vector_wv_2629_arg5); + setArg(call_vector_vector_wv_2629, 6, vm); + setArg(call_vector_vector_wv_2629, 7, vd); + setArg(call_vector_vector_wv_2629, 8, vs2); + setArg(call_vector_vector_wv_2629, 9, vs1); + setArg(call_vector_vector_wv_2629, 10, vector_vector_wv_2629_arg10); + } + cc.bind(label_merge); + } + auto tmp2631 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2631, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2631, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 587); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 588: VWMULU__VX */ + continuation_e __vwmulu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmulu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMULU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 588); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2632; + x86::Gp ret_val_get_sew_pow_2632 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2632, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2633 = get_reg(cc, 8, false); + mov(cc, tmp2633, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2633, ret_val_get_sew_pow_2632)), 8, false), ~ 1); + setArg(call_get_sew_pow_2632, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2632, 0, ret_val_get_sew_pow_2632); + InvokeNode* call_get_lmul_pow_2634; + x86::Gp ret_val_get_lmul_pow_2634 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2634, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2634; + setArg(call_get_lmul_pow_2634, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2634, 0, ret_val_get_lmul_pow_2634); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2635; + auto illegal_variable_width_2635_arg2 = SEW_widen; + auto illegal_variable_width_2635_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2635 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2635, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2636; + auto valid_reg_overlap_2636_arg2 = LMUL_pow; + auto valid_reg_overlap_2636_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2636 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2636, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2635, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2636)); + setArg(call_illegal_variable_width_2635, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2635, 1, vd); + setArg(call_illegal_variable_width_2635, 2, vm); + setArg(call_illegal_variable_width_2635, 3, illegal_variable_width_2635_arg2); + setArg(call_illegal_variable_width_2635, 4, illegal_variable_width_2635_arg3); + setRet(call_illegal_variable_width_2635, 0, ret_val_illegal_variable_width_2635); + setArg(call_valid_reg_overlap_2636, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2636, 1, vs2); + setArg(call_valid_reg_overlap_2636, 2, vd); + setArg(call_valid_reg_overlap_2636, 3, valid_reg_overlap_2636_arg2); + setArg(call_valid_reg_overlap_2636, 4, valid_reg_overlap_2636_arg3); + setRet(call_valid_reg_overlap_2636, 0, ret_val_valid_reg_overlap_2636); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2638; + x86::Gp ret_val_sew_2638 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2638, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2637; + auto vector_imm_wv_2637_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2637_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2637_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2637_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2637_arg10 = ret_val_sew_2638; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2637, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2638, 0, reinterpret_cast(this)); + setRet(call_sew_2638, 0, ret_val_sew_2638); + setArg(call_vector_imm_wv_2637, 0, V); + setArg(call_vector_imm_wv_2637, 1, 56); + setArg(call_vector_imm_wv_2637, 2, 6); + setArg(call_vector_imm_wv_2637, 3, vector_imm_wv_2637_arg3); + setArg(call_vector_imm_wv_2637, 4, vector_imm_wv_2637_arg4); + setArg(call_vector_imm_wv_2637, 5, vector_imm_wv_2637_arg5); + setArg(call_vector_imm_wv_2637, 6, vm); + setArg(call_vector_imm_wv_2637, 7, vd); + setArg(call_vector_imm_wv_2637, 8, vs2); + setArg(call_vector_imm_wv_2637, 9, vector_imm_wv_2637_arg9); + setArg(call_vector_imm_wv_2637, 10, vector_imm_wv_2637_arg10); + } + cc.bind(label_merge); + } + auto tmp2639 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2639, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2639, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 588); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 589: VWMULSU__VV */ + continuation_e __vwmulsu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmulsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMULSU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 589); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2640; + x86::Gp ret_val_get_sew_pow_2640 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2640, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2641 = get_reg(cc, 8, false); + mov(cc, tmp2641, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2641, ret_val_get_sew_pow_2640)), 8, false), ~ 1); + setArg(call_get_sew_pow_2640, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2640, 0, ret_val_get_sew_pow_2640); + InvokeNode* call_get_lmul_pow_2642; + x86::Gp ret_val_get_lmul_pow_2642 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2642, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2642; + setArg(call_get_lmul_pow_2642, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2642, 0, ret_val_get_lmul_pow_2642); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2643; + auto illegal_variable_width_2643_arg2 = SEW_widen; + auto illegal_variable_width_2643_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2643 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2643, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2644; + auto valid_reg_overlap_2644_arg2 = LMUL_pow; + auto valid_reg_overlap_2644_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2644 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2644, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2645; + auto valid_reg_overlap_2645_arg2 = LMUL_pow; + auto valid_reg_overlap_2645_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2645 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2645, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2643, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2644)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2645)); + setArg(call_illegal_variable_width_2643, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2643, 1, vd); + setArg(call_illegal_variable_width_2643, 2, vm); + setArg(call_illegal_variable_width_2643, 3, illegal_variable_width_2643_arg2); + setArg(call_illegal_variable_width_2643, 4, illegal_variable_width_2643_arg3); + setRet(call_illegal_variable_width_2643, 0, ret_val_illegal_variable_width_2643); + setArg(call_valid_reg_overlap_2644, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2644, 1, vs1); + setArg(call_valid_reg_overlap_2644, 2, vd); + setArg(call_valid_reg_overlap_2644, 3, valid_reg_overlap_2644_arg2); + setArg(call_valid_reg_overlap_2644, 4, valid_reg_overlap_2644_arg3); + setRet(call_valid_reg_overlap_2644, 0, ret_val_valid_reg_overlap_2644); + setArg(call_valid_reg_overlap_2645, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2645, 1, vs2); + setArg(call_valid_reg_overlap_2645, 2, vd); + setArg(call_valid_reg_overlap_2645, 3, valid_reg_overlap_2645_arg2); + setArg(call_valid_reg_overlap_2645, 4, valid_reg_overlap_2645_arg3); + setRet(call_valid_reg_overlap_2645, 0, ret_val_valid_reg_overlap_2645); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2647; + x86::Gp ret_val_sew_2647 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2647, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2646; + auto vector_vector_wv_2646_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2646_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2646_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2646_arg10 = ret_val_sew_2647; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2646, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2647, 0, reinterpret_cast(this)); + setRet(call_sew_2647, 0, ret_val_sew_2647); + setArg(call_vector_vector_wv_2646, 0, V); + setArg(call_vector_vector_wv_2646, 1, 58); + setArg(call_vector_vector_wv_2646, 2, 2); + setArg(call_vector_vector_wv_2646, 3, vector_vector_wv_2646_arg3); + setArg(call_vector_vector_wv_2646, 4, vector_vector_wv_2646_arg4); + setArg(call_vector_vector_wv_2646, 5, vector_vector_wv_2646_arg5); + setArg(call_vector_vector_wv_2646, 6, vm); + setArg(call_vector_vector_wv_2646, 7, vd); + setArg(call_vector_vector_wv_2646, 8, vs2); + setArg(call_vector_vector_wv_2646, 9, vs1); + setArg(call_vector_vector_wv_2646, 10, vector_vector_wv_2646_arg10); + } + cc.bind(label_merge); + } + auto tmp2648 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2648, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2648, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 589); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 590: VWMULSU__VX */ + continuation_e __vwmulsu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmulsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMULSU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 590); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2649; + x86::Gp ret_val_get_sew_pow_2649 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2649, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2650 = get_reg(cc, 8, false); + mov(cc, tmp2650, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2650, ret_val_get_sew_pow_2649)), 8, false), ~ 1); + setArg(call_get_sew_pow_2649, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2649, 0, ret_val_get_sew_pow_2649); + InvokeNode* call_get_lmul_pow_2651; + x86::Gp ret_val_get_lmul_pow_2651 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2651, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2651; + setArg(call_get_lmul_pow_2651, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2651, 0, ret_val_get_lmul_pow_2651); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2652; + auto illegal_variable_width_2652_arg2 = SEW_widen; + auto illegal_variable_width_2652_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2652 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2652, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2653; + auto valid_reg_overlap_2653_arg2 = LMUL_pow; + auto valid_reg_overlap_2653_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2653 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2653, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2652, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2653)); + setArg(call_illegal_variable_width_2652, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2652, 1, vd); + setArg(call_illegal_variable_width_2652, 2, vm); + setArg(call_illegal_variable_width_2652, 3, illegal_variable_width_2652_arg2); + setArg(call_illegal_variable_width_2652, 4, illegal_variable_width_2652_arg3); + setRet(call_illegal_variable_width_2652, 0, ret_val_illegal_variable_width_2652); + setArg(call_valid_reg_overlap_2653, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2653, 1, vs2); + setArg(call_valid_reg_overlap_2653, 2, vd); + setArg(call_valid_reg_overlap_2653, 3, valid_reg_overlap_2653_arg2); + setArg(call_valid_reg_overlap_2653, 4, valid_reg_overlap_2653_arg3); + setRet(call_valid_reg_overlap_2653, 0, ret_val_valid_reg_overlap_2653); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2655; + x86::Gp ret_val_sew_2655 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2655, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2654; + auto vector_imm_wv_2654_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2654_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2654_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2654_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2654_arg10 = ret_val_sew_2655; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2654, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2655, 0, reinterpret_cast(this)); + setRet(call_sew_2655, 0, ret_val_sew_2655); + setArg(call_vector_imm_wv_2654, 0, V); + setArg(call_vector_imm_wv_2654, 1, 58); + setArg(call_vector_imm_wv_2654, 2, 6); + setArg(call_vector_imm_wv_2654, 3, vector_imm_wv_2654_arg3); + setArg(call_vector_imm_wv_2654, 4, vector_imm_wv_2654_arg4); + setArg(call_vector_imm_wv_2654, 5, vector_imm_wv_2654_arg5); + setArg(call_vector_imm_wv_2654, 6, vm); + setArg(call_vector_imm_wv_2654, 7, vd); + setArg(call_vector_imm_wv_2654, 8, vs2); + setArg(call_vector_imm_wv_2654, 9, vector_imm_wv_2654_arg9); + setArg(call_vector_imm_wv_2654, 10, vector_imm_wv_2654_arg10); + } + cc.bind(label_merge); + } + auto tmp2656 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2656, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2656, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 590); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 591: VMACC__VV */ + continuation_e __vmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 591); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2657; + x86::Gp ret_val_illegal_normal_2657 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2657, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2657; + setArg(call_illegal_normal_2657, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2657, 1, vd); + setArg(call_illegal_normal_2657, 2, vm); + setRet(call_illegal_normal_2657, 0, ret_val_illegal_normal_2657); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2659; + x86::Gp ret_val_sew_2659 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2659, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2658; + auto vector_vector_op_2658_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2658_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2658_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2658_arg10 = ret_val_sew_2659; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2658, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2659, 0, reinterpret_cast(this)); + setRet(call_sew_2659, 0, ret_val_sew_2659); + setArg(call_vector_vector_op_2658, 0, V); + setArg(call_vector_vector_op_2658, 1, 45); + setArg(call_vector_vector_op_2658, 2, 2); + setArg(call_vector_vector_op_2658, 3, vector_vector_op_2658_arg3); + setArg(call_vector_vector_op_2658, 4, vector_vector_op_2658_arg4); + setArg(call_vector_vector_op_2658, 5, vector_vector_op_2658_arg5); + setArg(call_vector_vector_op_2658, 6, vm); + setArg(call_vector_vector_op_2658, 7, vd); + setArg(call_vector_vector_op_2658, 8, vs2); + setArg(call_vector_vector_op_2658, 9, vs1); + setArg(call_vector_vector_op_2658, 10, vector_vector_op_2658_arg10); + } + cc.bind(label_merge); + } + auto tmp2660 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2660, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2660, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 591); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 592: VMACC__VX */ + continuation_e __vmacc__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmacc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMACC__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 592); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2661; + x86::Gp ret_val_illegal_normal_2661 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2661, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2662 = get_reg(cc, 8, false); + mov(cc, tmp2662, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2662, ret_val_illegal_normal_2661); + setArg(call_illegal_normal_2661, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2661, 1, vd); + setArg(call_illegal_normal_2661, 2, vm); + setRet(call_illegal_normal_2661, 0, ret_val_illegal_normal_2661); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2664; + x86::Gp ret_val_sew_2664 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2664, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2663; + auto vector_imm_op_2663_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2663_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2663_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2663_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2663_arg10 = ret_val_sew_2664; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2663, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2664, 0, reinterpret_cast(this)); + setRet(call_sew_2664, 0, ret_val_sew_2664); + setArg(call_vector_imm_op_2663, 0, V); + setArg(call_vector_imm_op_2663, 1, 45); + setArg(call_vector_imm_op_2663, 2, 6); + setArg(call_vector_imm_op_2663, 3, vector_imm_op_2663_arg3); + setArg(call_vector_imm_op_2663, 4, vector_imm_op_2663_arg4); + setArg(call_vector_imm_op_2663, 5, vector_imm_op_2663_arg5); + setArg(call_vector_imm_op_2663, 6, vm); + setArg(call_vector_imm_op_2663, 7, vd); + setArg(call_vector_imm_op_2663, 8, vs2); + setArg(call_vector_imm_op_2663, 9, vector_imm_op_2663_arg9); + setArg(call_vector_imm_op_2663, 10, vector_imm_op_2663_arg10); + } + cc.bind(label_merge); + } + auto tmp2665 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2665, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2665, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 592); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 593: VNMSAC__VV */ + continuation_e __vnmsac__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNMSAC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 593); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2666; + x86::Gp ret_val_illegal_normal_2666 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2666, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2666; + setArg(call_illegal_normal_2666, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2666, 1, vd); + setArg(call_illegal_normal_2666, 2, vm); + setRet(call_illegal_normal_2666, 0, ret_val_illegal_normal_2666); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2668; + x86::Gp ret_val_sew_2668 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2668, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2667; + auto vector_vector_op_2667_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2667_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2667_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2667_arg10 = ret_val_sew_2668; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2667, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2668, 0, reinterpret_cast(this)); + setRet(call_sew_2668, 0, ret_val_sew_2668); + setArg(call_vector_vector_op_2667, 0, V); + setArg(call_vector_vector_op_2667, 1, 47); + setArg(call_vector_vector_op_2667, 2, 2); + setArg(call_vector_vector_op_2667, 3, vector_vector_op_2667_arg3); + setArg(call_vector_vector_op_2667, 4, vector_vector_op_2667_arg4); + setArg(call_vector_vector_op_2667, 5, vector_vector_op_2667_arg5); + setArg(call_vector_vector_op_2667, 6, vm); + setArg(call_vector_vector_op_2667, 7, vd); + setArg(call_vector_vector_op_2667, 8, vs2); + setArg(call_vector_vector_op_2667, 9, vs1); + setArg(call_vector_vector_op_2667, 10, vector_vector_op_2667_arg10); + } + cc.bind(label_merge); + } + auto tmp2669 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2669, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2669, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 593); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 594: VNMSAC__VX */ + continuation_e __vnmsac__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnmsac.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNMSAC__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 594); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2670; + x86::Gp ret_val_illegal_normal_2670 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2670, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2671 = get_reg(cc, 8, false); + mov(cc, tmp2671, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2671, ret_val_illegal_normal_2670); + setArg(call_illegal_normal_2670, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2670, 1, vd); + setArg(call_illegal_normal_2670, 2, vm); + setRet(call_illegal_normal_2670, 0, ret_val_illegal_normal_2670); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2673; + x86::Gp ret_val_sew_2673 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2673, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2672; + auto vector_imm_op_2672_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2672_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2672_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2672_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2672_arg10 = ret_val_sew_2673; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2672, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2673, 0, reinterpret_cast(this)); + setRet(call_sew_2673, 0, ret_val_sew_2673); + setArg(call_vector_imm_op_2672, 0, V); + setArg(call_vector_imm_op_2672, 1, 47); + setArg(call_vector_imm_op_2672, 2, 6); + setArg(call_vector_imm_op_2672, 3, vector_imm_op_2672_arg3); + setArg(call_vector_imm_op_2672, 4, vector_imm_op_2672_arg4); + setArg(call_vector_imm_op_2672, 5, vector_imm_op_2672_arg5); + setArg(call_vector_imm_op_2672, 6, vm); + setArg(call_vector_imm_op_2672, 7, vd); + setArg(call_vector_imm_op_2672, 8, vs2); + setArg(call_vector_imm_op_2672, 9, vector_imm_op_2672_arg9); + setArg(call_vector_imm_op_2672, 10, vector_imm_op_2672_arg10); + } + cc.bind(label_merge); + } + auto tmp2674 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2674, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2674, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 594); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 595: VMADD__VV */ + continuation_e __vmadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 595); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2675; + x86::Gp ret_val_illegal_normal_2675 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2675, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2675; + setArg(call_illegal_normal_2675, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2675, 1, vd); + setArg(call_illegal_normal_2675, 2, vm); + setRet(call_illegal_normal_2675, 0, ret_val_illegal_normal_2675); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2677; + x86::Gp ret_val_sew_2677 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2677, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2676; + auto vector_vector_op_2676_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2676_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2676_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2676_arg10 = ret_val_sew_2677; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2676, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2677, 0, reinterpret_cast(this)); + setRet(call_sew_2677, 0, ret_val_sew_2677); + setArg(call_vector_vector_op_2676, 0, V); + setArg(call_vector_vector_op_2676, 1, 41); + setArg(call_vector_vector_op_2676, 2, 2); + setArg(call_vector_vector_op_2676, 3, vector_vector_op_2676_arg3); + setArg(call_vector_vector_op_2676, 4, vector_vector_op_2676_arg4); + setArg(call_vector_vector_op_2676, 5, vector_vector_op_2676_arg5); + setArg(call_vector_vector_op_2676, 6, vm); + setArg(call_vector_vector_op_2676, 7, vd); + setArg(call_vector_vector_op_2676, 8, vs2); + setArg(call_vector_vector_op_2676, 9, vs1); + setArg(call_vector_vector_op_2676, 10, vector_vector_op_2676_arg10); + } + cc.bind(label_merge); + } + auto tmp2678 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2678, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2678, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 595); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 596: VMADD__VX */ + continuation_e __vmadd__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADD__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 596); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2679; + x86::Gp ret_val_illegal_normal_2679 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2679, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2680 = get_reg(cc, 8, false); + mov(cc, tmp2680, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2680, ret_val_illegal_normal_2679); + setArg(call_illegal_normal_2679, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2679, 1, vd); + setArg(call_illegal_normal_2679, 2, vm); + setRet(call_illegal_normal_2679, 0, ret_val_illegal_normal_2679); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2682; + x86::Gp ret_val_sew_2682 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2682, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2681; + auto vector_imm_op_2681_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2681_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2681_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2681_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2681_arg10 = ret_val_sew_2682; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2681, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2682, 0, reinterpret_cast(this)); + setRet(call_sew_2682, 0, ret_val_sew_2682); + setArg(call_vector_imm_op_2681, 0, V); + setArg(call_vector_imm_op_2681, 1, 41); + setArg(call_vector_imm_op_2681, 2, 6); + setArg(call_vector_imm_op_2681, 3, vector_imm_op_2681_arg3); + setArg(call_vector_imm_op_2681, 4, vector_imm_op_2681_arg4); + setArg(call_vector_imm_op_2681, 5, vector_imm_op_2681_arg5); + setArg(call_vector_imm_op_2681, 6, vm); + setArg(call_vector_imm_op_2681, 7, vd); + setArg(call_vector_imm_op_2681, 8, vs2); + setArg(call_vector_imm_op_2681, 9, vector_imm_op_2681_arg9); + setArg(call_vector_imm_op_2681, 10, vector_imm_op_2681_arg10); + } + cc.bind(label_merge); + } + auto tmp2683 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2683, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2683, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 596); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 597: VNMSUB__VV */ + continuation_e __vnmsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNMSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 597); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2684; + x86::Gp ret_val_illegal_normal_2684 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2684, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2684; + setArg(call_illegal_normal_2684, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2684, 1, vd); + setArg(call_illegal_normal_2684, 2, vm); + setRet(call_illegal_normal_2684, 0, ret_val_illegal_normal_2684); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2686; + x86::Gp ret_val_sew_2686 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2686, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2685; + auto vector_vector_op_2685_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2685_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2685_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2685_arg10 = ret_val_sew_2686; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2685, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2686, 0, reinterpret_cast(this)); + setRet(call_sew_2686, 0, ret_val_sew_2686); + setArg(call_vector_vector_op_2685, 0, V); + setArg(call_vector_vector_op_2685, 1, 43); + setArg(call_vector_vector_op_2685, 2, 2); + setArg(call_vector_vector_op_2685, 3, vector_vector_op_2685_arg3); + setArg(call_vector_vector_op_2685, 4, vector_vector_op_2685_arg4); + setArg(call_vector_vector_op_2685, 5, vector_vector_op_2685_arg5); + setArg(call_vector_vector_op_2685, 6, vm); + setArg(call_vector_vector_op_2685, 7, vd); + setArg(call_vector_vector_op_2685, 8, vs2); + setArg(call_vector_vector_op_2685, 9, vs1); + setArg(call_vector_vector_op_2685, 10, vector_vector_op_2685_arg10); + } + cc.bind(label_merge); + } + auto tmp2687 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2687, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2687, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 597); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 598: VNMSUB__VX */ + continuation_e __vnmsub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnmsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNMSUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 598); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2688; + x86::Gp ret_val_illegal_normal_2688 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2688, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2689 = get_reg(cc, 8, false); + mov(cc, tmp2689, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2689, ret_val_illegal_normal_2688); + setArg(call_illegal_normal_2688, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2688, 1, vd); + setArg(call_illegal_normal_2688, 2, vm); + setRet(call_illegal_normal_2688, 0, ret_val_illegal_normal_2688); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2691; + x86::Gp ret_val_sew_2691 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2691, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2690; + auto vector_imm_op_2690_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2690_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2690_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2690_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_op_2690_arg10 = ret_val_sew_2691; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2690, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2691, 0, reinterpret_cast(this)); + setRet(call_sew_2691, 0, ret_val_sew_2691); + setArg(call_vector_imm_op_2690, 0, V); + setArg(call_vector_imm_op_2690, 1, 43); + setArg(call_vector_imm_op_2690, 2, 6); + setArg(call_vector_imm_op_2690, 3, vector_imm_op_2690_arg3); + setArg(call_vector_imm_op_2690, 4, vector_imm_op_2690_arg4); + setArg(call_vector_imm_op_2690, 5, vector_imm_op_2690_arg5); + setArg(call_vector_imm_op_2690, 6, vm); + setArg(call_vector_imm_op_2690, 7, vd); + setArg(call_vector_imm_op_2690, 8, vs2); + setArg(call_vector_imm_op_2690, 9, vector_imm_op_2690_arg9); + setArg(call_vector_imm_op_2690, 10, vector_imm_op_2690_arg10); + } + cc.bind(label_merge); + } + auto tmp2692 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2692, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2692, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 598); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 599: VWMACCU__VV */ + continuation_e __vwmaccu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmaccu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACCU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 599); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2693; + x86::Gp ret_val_get_sew_pow_2693 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2693, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2694 = get_reg(cc, 8, false); + mov(cc, tmp2694, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2694, ret_val_get_sew_pow_2693)), 8, false), ~ 1); + setArg(call_get_sew_pow_2693, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2693, 0, ret_val_get_sew_pow_2693); + InvokeNode* call_get_lmul_pow_2695; + x86::Gp ret_val_get_lmul_pow_2695 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2695, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2695; + setArg(call_get_lmul_pow_2695, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2695, 0, ret_val_get_lmul_pow_2695); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2696; + auto illegal_variable_width_2696_arg2 = SEW_widen; + auto illegal_variable_width_2696_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2696 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2696, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2697; + auto valid_reg_overlap_2697_arg2 = LMUL_pow; + auto valid_reg_overlap_2697_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2697 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2697, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2698; + auto valid_reg_overlap_2698_arg2 = LMUL_pow; + auto valid_reg_overlap_2698_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2698 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2698, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2696, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2697)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2698)); + setArg(call_illegal_variable_width_2696, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2696, 1, vd); + setArg(call_illegal_variable_width_2696, 2, vm); + setArg(call_illegal_variable_width_2696, 3, illegal_variable_width_2696_arg2); + setArg(call_illegal_variable_width_2696, 4, illegal_variable_width_2696_arg3); + setRet(call_illegal_variable_width_2696, 0, ret_val_illegal_variable_width_2696); + setArg(call_valid_reg_overlap_2697, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2697, 1, vs1); + setArg(call_valid_reg_overlap_2697, 2, vd); + setArg(call_valid_reg_overlap_2697, 3, valid_reg_overlap_2697_arg2); + setArg(call_valid_reg_overlap_2697, 4, valid_reg_overlap_2697_arg3); + setRet(call_valid_reg_overlap_2697, 0, ret_val_valid_reg_overlap_2697); + setArg(call_valid_reg_overlap_2698, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2698, 1, vs2); + setArg(call_valid_reg_overlap_2698, 2, vd); + setArg(call_valid_reg_overlap_2698, 3, valid_reg_overlap_2698_arg2); + setArg(call_valid_reg_overlap_2698, 4, valid_reg_overlap_2698_arg3); + setRet(call_valid_reg_overlap_2698, 0, ret_val_valid_reg_overlap_2698); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2700; + x86::Gp ret_val_sew_2700 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2700, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2699; + auto vector_vector_wv_2699_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2699_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2699_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2699_arg10 = ret_val_sew_2700; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2699, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2700, 0, reinterpret_cast(this)); + setRet(call_sew_2700, 0, ret_val_sew_2700); + setArg(call_vector_vector_wv_2699, 0, V); + setArg(call_vector_vector_wv_2699, 1, 60); + setArg(call_vector_vector_wv_2699, 2, 2); + setArg(call_vector_vector_wv_2699, 3, vector_vector_wv_2699_arg3); + setArg(call_vector_vector_wv_2699, 4, vector_vector_wv_2699_arg4); + setArg(call_vector_vector_wv_2699, 5, vector_vector_wv_2699_arg5); + setArg(call_vector_vector_wv_2699, 6, vm); + setArg(call_vector_vector_wv_2699, 7, vd); + setArg(call_vector_vector_wv_2699, 8, vs2); + setArg(call_vector_vector_wv_2699, 9, vs1); + setArg(call_vector_vector_wv_2699, 10, vector_vector_wv_2699_arg10); + } + cc.bind(label_merge); + } + auto tmp2701 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2701, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2701, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 599); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 600: VWMACCU__VX */ + continuation_e __vwmaccu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACCU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 600); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2702; + x86::Gp ret_val_get_sew_pow_2702 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2702, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2703 = get_reg(cc, 8, false); + mov(cc, tmp2703, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2703, ret_val_get_sew_pow_2702)), 8, false), ~ 1); + setArg(call_get_sew_pow_2702, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2702, 0, ret_val_get_sew_pow_2702); + InvokeNode* call_get_lmul_pow_2704; + x86::Gp ret_val_get_lmul_pow_2704 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2704, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2704; + setArg(call_get_lmul_pow_2704, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2704, 0, ret_val_get_lmul_pow_2704); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2705; + auto illegal_variable_width_2705_arg2 = SEW_widen; + auto illegal_variable_width_2705_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2705 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2705, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2706; + auto valid_reg_overlap_2706_arg2 = LMUL_pow; + auto valid_reg_overlap_2706_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2706 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2706, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2705, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2706)); + setArg(call_illegal_variable_width_2705, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2705, 1, vd); + setArg(call_illegal_variable_width_2705, 2, vm); + setArg(call_illegal_variable_width_2705, 3, illegal_variable_width_2705_arg2); + setArg(call_illegal_variable_width_2705, 4, illegal_variable_width_2705_arg3); + setRet(call_illegal_variable_width_2705, 0, ret_val_illegal_variable_width_2705); + setArg(call_valid_reg_overlap_2706, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2706, 1, vs2); + setArg(call_valid_reg_overlap_2706, 2, vd); + setArg(call_valid_reg_overlap_2706, 3, valid_reg_overlap_2706_arg2); + setArg(call_valid_reg_overlap_2706, 4, valid_reg_overlap_2706_arg3); + setRet(call_valid_reg_overlap_2706, 0, ret_val_valid_reg_overlap_2706); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2708; + x86::Gp ret_val_sew_2708 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2708, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2707; + auto vector_imm_wv_2707_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2707_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2707_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2707_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2707_arg10 = ret_val_sew_2708; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2707, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2708, 0, reinterpret_cast(this)); + setRet(call_sew_2708, 0, ret_val_sew_2708); + setArg(call_vector_imm_wv_2707, 0, V); + setArg(call_vector_imm_wv_2707, 1, 60); + setArg(call_vector_imm_wv_2707, 2, 6); + setArg(call_vector_imm_wv_2707, 3, vector_imm_wv_2707_arg3); + setArg(call_vector_imm_wv_2707, 4, vector_imm_wv_2707_arg4); + setArg(call_vector_imm_wv_2707, 5, vector_imm_wv_2707_arg5); + setArg(call_vector_imm_wv_2707, 6, vm); + setArg(call_vector_imm_wv_2707, 7, vd); + setArg(call_vector_imm_wv_2707, 8, vs2); + setArg(call_vector_imm_wv_2707, 9, vector_imm_wv_2707_arg9); + setArg(call_vector_imm_wv_2707, 10, vector_imm_wv_2707_arg10); + } + cc.bind(label_merge); + } + auto tmp2709 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2709, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2709, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 600); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 601: VWMACC__VV */ + continuation_e __vwmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 601); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2710; + x86::Gp ret_val_get_sew_pow_2710 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2710, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2711 = get_reg(cc, 8, false); + mov(cc, tmp2711, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2711, ret_val_get_sew_pow_2710)), 8, false), ~ 1); + setArg(call_get_sew_pow_2710, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2710, 0, ret_val_get_sew_pow_2710); + InvokeNode* call_get_lmul_pow_2712; + x86::Gp ret_val_get_lmul_pow_2712 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2712, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2712; + setArg(call_get_lmul_pow_2712, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2712, 0, ret_val_get_lmul_pow_2712); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2713; + auto illegal_variable_width_2713_arg2 = SEW_widen; + auto illegal_variable_width_2713_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2713 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2713, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2714; + auto valid_reg_overlap_2714_arg2 = LMUL_pow; + auto valid_reg_overlap_2714_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2714 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2714, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2715; + auto valid_reg_overlap_2715_arg2 = LMUL_pow; + auto valid_reg_overlap_2715_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2715 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2715, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2713, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2714)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2715)); + setArg(call_illegal_variable_width_2713, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2713, 1, vd); + setArg(call_illegal_variable_width_2713, 2, vm); + setArg(call_illegal_variable_width_2713, 3, illegal_variable_width_2713_arg2); + setArg(call_illegal_variable_width_2713, 4, illegal_variable_width_2713_arg3); + setRet(call_illegal_variable_width_2713, 0, ret_val_illegal_variable_width_2713); + setArg(call_valid_reg_overlap_2714, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2714, 1, vs1); + setArg(call_valid_reg_overlap_2714, 2, vd); + setArg(call_valid_reg_overlap_2714, 3, valid_reg_overlap_2714_arg2); + setArg(call_valid_reg_overlap_2714, 4, valid_reg_overlap_2714_arg3); + setRet(call_valid_reg_overlap_2714, 0, ret_val_valid_reg_overlap_2714); + setArg(call_valid_reg_overlap_2715, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2715, 1, vs2); + setArg(call_valid_reg_overlap_2715, 2, vd); + setArg(call_valid_reg_overlap_2715, 3, valid_reg_overlap_2715_arg2); + setArg(call_valid_reg_overlap_2715, 4, valid_reg_overlap_2715_arg3); + setRet(call_valid_reg_overlap_2715, 0, ret_val_valid_reg_overlap_2715); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2717; + x86::Gp ret_val_sew_2717 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2717, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2716; + auto vector_vector_wv_2716_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2716_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2716_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2716_arg10 = ret_val_sew_2717; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2716, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2717, 0, reinterpret_cast(this)); + setRet(call_sew_2717, 0, ret_val_sew_2717); + setArg(call_vector_vector_wv_2716, 0, V); + setArg(call_vector_vector_wv_2716, 1, 61); + setArg(call_vector_vector_wv_2716, 2, 2); + setArg(call_vector_vector_wv_2716, 3, vector_vector_wv_2716_arg3); + setArg(call_vector_vector_wv_2716, 4, vector_vector_wv_2716_arg4); + setArg(call_vector_vector_wv_2716, 5, vector_vector_wv_2716_arg5); + setArg(call_vector_vector_wv_2716, 6, vm); + setArg(call_vector_vector_wv_2716, 7, vd); + setArg(call_vector_vector_wv_2716, 8, vs2); + setArg(call_vector_vector_wv_2716, 9, vs1); + setArg(call_vector_vector_wv_2716, 10, vector_vector_wv_2716_arg10); + } + cc.bind(label_merge); + } + auto tmp2718 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2718, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2718, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 601); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 602: VWMACC__VX */ + continuation_e __vwmacc__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmacc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACC__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 602); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2719; + x86::Gp ret_val_get_sew_pow_2719 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2719, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2720 = get_reg(cc, 8, false); + mov(cc, tmp2720, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2720, ret_val_get_sew_pow_2719)), 8, false), ~ 1); + setArg(call_get_sew_pow_2719, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2719, 0, ret_val_get_sew_pow_2719); + InvokeNode* call_get_lmul_pow_2721; + x86::Gp ret_val_get_lmul_pow_2721 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2721, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2721; + setArg(call_get_lmul_pow_2721, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2721, 0, ret_val_get_lmul_pow_2721); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2722; + auto illegal_variable_width_2722_arg2 = SEW_widen; + auto illegal_variable_width_2722_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2722 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2722, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2723; + auto valid_reg_overlap_2723_arg2 = LMUL_pow; + auto valid_reg_overlap_2723_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2723 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2723, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2722, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2723)); + setArg(call_illegal_variable_width_2722, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2722, 1, vd); + setArg(call_illegal_variable_width_2722, 2, vm); + setArg(call_illegal_variable_width_2722, 3, illegal_variable_width_2722_arg2); + setArg(call_illegal_variable_width_2722, 4, illegal_variable_width_2722_arg3); + setRet(call_illegal_variable_width_2722, 0, ret_val_illegal_variable_width_2722); + setArg(call_valid_reg_overlap_2723, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2723, 1, vs2); + setArg(call_valid_reg_overlap_2723, 2, vd); + setArg(call_valid_reg_overlap_2723, 3, valid_reg_overlap_2723_arg2); + setArg(call_valid_reg_overlap_2723, 4, valid_reg_overlap_2723_arg3); + setRet(call_valid_reg_overlap_2723, 0, ret_val_valid_reg_overlap_2723); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2725; + x86::Gp ret_val_sew_2725 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2725, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2724; + auto vector_imm_wv_2724_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2724_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2724_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2724_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2724_arg10 = ret_val_sew_2725; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2724, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2725, 0, reinterpret_cast(this)); + setRet(call_sew_2725, 0, ret_val_sew_2725); + setArg(call_vector_imm_wv_2724, 0, V); + setArg(call_vector_imm_wv_2724, 1, 61); + setArg(call_vector_imm_wv_2724, 2, 6); + setArg(call_vector_imm_wv_2724, 3, vector_imm_wv_2724_arg3); + setArg(call_vector_imm_wv_2724, 4, vector_imm_wv_2724_arg4); + setArg(call_vector_imm_wv_2724, 5, vector_imm_wv_2724_arg5); + setArg(call_vector_imm_wv_2724, 6, vm); + setArg(call_vector_imm_wv_2724, 7, vd); + setArg(call_vector_imm_wv_2724, 8, vs2); + setArg(call_vector_imm_wv_2724, 9, vector_imm_wv_2724_arg9); + setArg(call_vector_imm_wv_2724, 10, vector_imm_wv_2724_arg10); + } + cc.bind(label_merge); + } + auto tmp2726 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2726, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2726, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 602); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 603: VWMACCSU__VV */ + continuation_e __vwmaccsu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmaccsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACCSU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 603); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2727; + x86::Gp ret_val_get_sew_pow_2727 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2727, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2728 = get_reg(cc, 8, false); + mov(cc, tmp2728, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2728, ret_val_get_sew_pow_2727)), 8, false), ~ 1); + setArg(call_get_sew_pow_2727, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2727, 0, ret_val_get_sew_pow_2727); + InvokeNode* call_get_lmul_pow_2729; + x86::Gp ret_val_get_lmul_pow_2729 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2729, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2729; + setArg(call_get_lmul_pow_2729, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2729, 0, ret_val_get_lmul_pow_2729); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2730; + auto illegal_variable_width_2730_arg2 = SEW_widen; + auto illegal_variable_width_2730_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2730 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2730, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2731; + auto valid_reg_overlap_2731_arg2 = LMUL_pow; + auto valid_reg_overlap_2731_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2731 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2731, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2732; + auto valid_reg_overlap_2732_arg2 = LMUL_pow; + auto valid_reg_overlap_2732_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2732 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2732, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2730, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2731)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2732)); + setArg(call_illegal_variable_width_2730, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2730, 1, vd); + setArg(call_illegal_variable_width_2730, 2, vm); + setArg(call_illegal_variable_width_2730, 3, illegal_variable_width_2730_arg2); + setArg(call_illegal_variable_width_2730, 4, illegal_variable_width_2730_arg3); + setRet(call_illegal_variable_width_2730, 0, ret_val_illegal_variable_width_2730); + setArg(call_valid_reg_overlap_2731, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2731, 1, vs1); + setArg(call_valid_reg_overlap_2731, 2, vd); + setArg(call_valid_reg_overlap_2731, 3, valid_reg_overlap_2731_arg2); + setArg(call_valid_reg_overlap_2731, 4, valid_reg_overlap_2731_arg3); + setRet(call_valid_reg_overlap_2731, 0, ret_val_valid_reg_overlap_2731); + setArg(call_valid_reg_overlap_2732, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2732, 1, vs2); + setArg(call_valid_reg_overlap_2732, 2, vd); + setArg(call_valid_reg_overlap_2732, 3, valid_reg_overlap_2732_arg2); + setArg(call_valid_reg_overlap_2732, 4, valid_reg_overlap_2732_arg3); + setRet(call_valid_reg_overlap_2732, 0, ret_val_valid_reg_overlap_2732); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2734; + x86::Gp ret_val_sew_2734 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2734, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2733; + auto vector_vector_wv_2733_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2733_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2733_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2733_arg10 = ret_val_sew_2734; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2733, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2734, 0, reinterpret_cast(this)); + setRet(call_sew_2734, 0, ret_val_sew_2734); + setArg(call_vector_vector_wv_2733, 0, V); + setArg(call_vector_vector_wv_2733, 1, 63); + setArg(call_vector_vector_wv_2733, 2, 2); + setArg(call_vector_vector_wv_2733, 3, vector_vector_wv_2733_arg3); + setArg(call_vector_vector_wv_2733, 4, vector_vector_wv_2733_arg4); + setArg(call_vector_vector_wv_2733, 5, vector_vector_wv_2733_arg5); + setArg(call_vector_vector_wv_2733, 6, vm); + setArg(call_vector_vector_wv_2733, 7, vd); + setArg(call_vector_vector_wv_2733, 8, vs2); + setArg(call_vector_vector_wv_2733, 9, vs1); + setArg(call_vector_vector_wv_2733, 10, vector_vector_wv_2733_arg10); + } + cc.bind(label_merge); + } + auto tmp2735 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2735, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2735, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 603); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 604: VWMACCSU__VX */ + continuation_e __vwmaccsu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACCSU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 604); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2736; + x86::Gp ret_val_get_sew_pow_2736 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2736, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2737 = get_reg(cc, 8, false); + mov(cc, tmp2737, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2737, ret_val_get_sew_pow_2736)), 8, false), ~ 1); + setArg(call_get_sew_pow_2736, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2736, 0, ret_val_get_sew_pow_2736); + InvokeNode* call_get_lmul_pow_2738; + x86::Gp ret_val_get_lmul_pow_2738 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2738, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2738; + setArg(call_get_lmul_pow_2738, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2738, 0, ret_val_get_lmul_pow_2738); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2739; + auto illegal_variable_width_2739_arg2 = SEW_widen; + auto illegal_variable_width_2739_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2739 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2739, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2740; + auto valid_reg_overlap_2740_arg2 = LMUL_pow; + auto valid_reg_overlap_2740_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2740 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2740, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2739, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2740)); + setArg(call_illegal_variable_width_2739, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2739, 1, vd); + setArg(call_illegal_variable_width_2739, 2, vm); + setArg(call_illegal_variable_width_2739, 3, illegal_variable_width_2739_arg2); + setArg(call_illegal_variable_width_2739, 4, illegal_variable_width_2739_arg3); + setRet(call_illegal_variable_width_2739, 0, ret_val_illegal_variable_width_2739); + setArg(call_valid_reg_overlap_2740, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2740, 1, vs2); + setArg(call_valid_reg_overlap_2740, 2, vd); + setArg(call_valid_reg_overlap_2740, 3, valid_reg_overlap_2740_arg2); + setArg(call_valid_reg_overlap_2740, 4, valid_reg_overlap_2740_arg3); + setRet(call_valid_reg_overlap_2740, 0, ret_val_valid_reg_overlap_2740); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2742; + x86::Gp ret_val_sew_2742 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2742, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2741; + auto vector_imm_wv_2741_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2741_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2741_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2741_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2741_arg10 = ret_val_sew_2742; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2741, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2742, 0, reinterpret_cast(this)); + setRet(call_sew_2742, 0, ret_val_sew_2742); + setArg(call_vector_imm_wv_2741, 0, V); + setArg(call_vector_imm_wv_2741, 1, 63); + setArg(call_vector_imm_wv_2741, 2, 6); + setArg(call_vector_imm_wv_2741, 3, vector_imm_wv_2741_arg3); + setArg(call_vector_imm_wv_2741, 4, vector_imm_wv_2741_arg4); + setArg(call_vector_imm_wv_2741, 5, vector_imm_wv_2741_arg5); + setArg(call_vector_imm_wv_2741, 6, vm); + setArg(call_vector_imm_wv_2741, 7, vd); + setArg(call_vector_imm_wv_2741, 8, vs2); + setArg(call_vector_imm_wv_2741, 9, vector_imm_wv_2741_arg9); + setArg(call_vector_imm_wv_2741, 10, vector_imm_wv_2741_arg10); + } + cc.bind(label_merge); + } + auto tmp2743 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2743, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2743, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 604); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 605: VWMACCUS__VX */ + continuation_e __vwmaccus__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccus.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACCUS__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 605); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2744; + x86::Gp ret_val_get_sew_pow_2744 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2744, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2745 = get_reg(cc, 8, false); + mov(cc, tmp2745, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2745, ret_val_get_sew_pow_2744)), 5, false), ~ 1); + setArg(call_get_sew_pow_2744, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2744, 0, ret_val_get_sew_pow_2744); + InvokeNode* call_get_lmul_pow_2746; + x86::Gp ret_val_get_lmul_pow_2746 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2746, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2746; + setArg(call_get_lmul_pow_2746, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2746, 0, ret_val_get_lmul_pow_2746); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2747; + auto illegal_variable_width_2747_arg2 = SEW_widen; + auto illegal_variable_width_2747_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2747 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2747, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2748; + auto valid_reg_overlap_2748_arg2 = LMUL_pow; + auto valid_reg_overlap_2748_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2748 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2748, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2747, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2748)); + setArg(call_illegal_variable_width_2747, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2747, 1, vd); + setArg(call_illegal_variable_width_2747, 2, vm); + setArg(call_illegal_variable_width_2747, 3, illegal_variable_width_2747_arg2); + setArg(call_illegal_variable_width_2747, 4, illegal_variable_width_2747_arg3); + setRet(call_illegal_variable_width_2747, 0, ret_val_illegal_variable_width_2747); + setArg(call_valid_reg_overlap_2748, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2748, 1, vs2); + setArg(call_valid_reg_overlap_2748, 2, vd); + setArg(call_valid_reg_overlap_2748, 3, valid_reg_overlap_2748_arg2); + setArg(call_valid_reg_overlap_2748, 4, valid_reg_overlap_2748_arg3); + setRet(call_valid_reg_overlap_2748, 0, ret_val_valid_reg_overlap_2748); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2750; + x86::Gp ret_val_sew_2750 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2750, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2749; + auto vector_imm_wv_2749_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2749_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2749_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2749_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto vector_imm_wv_2749_arg10 = ret_val_sew_2750; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2749, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2750, 0, reinterpret_cast(this)); + setRet(call_sew_2750, 0, ret_val_sew_2750); + setArg(call_vector_imm_wv_2749, 0, V); + setArg(call_vector_imm_wv_2749, 1, 62); + setArg(call_vector_imm_wv_2749, 2, 6); + setArg(call_vector_imm_wv_2749, 3, vector_imm_wv_2749_arg3); + setArg(call_vector_imm_wv_2749, 4, vector_imm_wv_2749_arg4); + setArg(call_vector_imm_wv_2749, 5, vector_imm_wv_2749_arg5); + setArg(call_vector_imm_wv_2749, 6, vm); + setArg(call_vector_imm_wv_2749, 7, vd); + setArg(call_vector_imm_wv_2749, 8, vs2); + setArg(call_vector_imm_wv_2749, 9, vector_imm_wv_2749_arg9); + setArg(call_vector_imm_wv_2749, 10, vector_imm_wv_2749_arg10); + } + cc.bind(label_merge); + } + auto tmp2751 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2751, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2751, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 605); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 606: VMERGE__VIM */ + continuation_e __vmerge__vim(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}", fmt::arg("mnemonic", "vmerge.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMERGE__VIM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 606); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2752; + x86::Gp ret_val_illegal_vd_masked_2752 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2752, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_masked_2752; + setArg(call_illegal_vd_masked_2752, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2752, 1, vd); + setRet(call_illegal_vd_masked_2752, 0, ret_val_illegal_vd_masked_2752); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2754; + x86::Gp ret_val_sew_2754 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2754, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_2753; + auto vector_imm_merge_2753_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_2753_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_2753_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_2753_arg8 = ret_val_sew_2754; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_2753, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_2754, 0, reinterpret_cast(this)); + setRet(call_sew_2754, 0, ret_val_sew_2754); + setArg(call_vector_imm_merge_2753, 0, V); + setArg(call_vector_imm_merge_2753, 1, vector_imm_merge_2753_arg1); + setArg(call_vector_imm_merge_2753, 2, vector_imm_merge_2753_arg2); + setArg(call_vector_imm_merge_2753, 3, vector_imm_merge_2753_arg3); + setArg(call_vector_imm_merge_2753, 4, 0); + setArg(call_vector_imm_merge_2753, 5, vd); + setArg(call_vector_imm_merge_2753, 6, vs2); + setArg(call_vector_imm_merge_2753, 7, (uint32_t)(int32_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_merge_2753, 8, vector_imm_merge_2753_arg8); + } + cc.bind(label_merge); + } + auto tmp2755 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2755, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2755, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 606); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 607: VMERGE__VVM */ + continuation_e __vmerge__vvm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmerge.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMERGE__VVM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 607); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2756; + x86::Gp ret_val_illegal_vd_masked_2756 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2756, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_masked_2756; + setArg(call_illegal_vd_masked_2756, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2756, 1, vd); + setRet(call_illegal_vd_masked_2756, 0, ret_val_illegal_vd_masked_2756); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2758; + x86::Gp ret_val_sew_2758 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2758, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_merge_2757; + auto vector_vector_merge_2757_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_merge_2757_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_merge_2757_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_merge_2757_arg8 = ret_val_sew_2758; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_merge_2757, &vector_vector_merge, FuncSignature::build()); + setArg(call_sew_2758, 0, reinterpret_cast(this)); + setRet(call_sew_2758, 0, ret_val_sew_2758); + setArg(call_vector_vector_merge_2757, 0, V); + setArg(call_vector_vector_merge_2757, 1, vector_vector_merge_2757_arg1); + setArg(call_vector_vector_merge_2757, 2, vector_vector_merge_2757_arg2); + setArg(call_vector_vector_merge_2757, 3, vector_vector_merge_2757_arg3); + setArg(call_vector_vector_merge_2757, 4, 0); + setArg(call_vector_vector_merge_2757, 5, vd); + setArg(call_vector_vector_merge_2757, 6, vs2); + setArg(call_vector_vector_merge_2757, 7, vs1); + setArg(call_vector_vector_merge_2757, 8, vector_vector_merge_2757_arg8); + } + cc.bind(label_merge); + } + auto tmp2759 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2759, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2759, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 607); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 608: VMERGE__VXM */ + continuation_e __vmerge__vxm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmerge.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMERGE__VXM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 608); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2760; + x86::Gp ret_val_illegal_vd_masked_2760 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2760, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto tmp2761 = get_reg(cc, 8, false); + mov(cc, tmp2761, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2761, ret_val_illegal_vd_masked_2760); + setArg(call_illegal_vd_masked_2760, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2760, 1, vd); + setRet(call_illegal_vd_masked_2760, 0, ret_val_illegal_vd_masked_2760); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2763; + x86::Gp ret_val_sew_2763 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2763, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_2762; + auto vector_imm_merge_2762_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_2762_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_2762_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_2762_arg7 = gen_ext(cc, + gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true), 32, true); + auto vector_imm_merge_2762_arg8 = ret_val_sew_2763; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_2762, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_2763, 0, reinterpret_cast(this)); + setRet(call_sew_2763, 0, ret_val_sew_2763); + setArg(call_vector_imm_merge_2762, 0, V); + setArg(call_vector_imm_merge_2762, 1, vector_imm_merge_2762_arg1); + setArg(call_vector_imm_merge_2762, 2, vector_imm_merge_2762_arg2); + setArg(call_vector_imm_merge_2762, 3, vector_imm_merge_2762_arg3); + setArg(call_vector_imm_merge_2762, 4, 0); + setArg(call_vector_imm_merge_2762, 5, vd); + setArg(call_vector_imm_merge_2762, 6, vs2); + setArg(call_vector_imm_merge_2762, 7, vector_imm_merge_2762_arg7); + setArg(call_vector_imm_merge_2762, 8, vector_imm_merge_2762_arg8); + } + cc.bind(label_merge); + } + auto tmp2764 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2764, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2764, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 608); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 609: VMV__V__I */ + continuation_e __vmv__v__i(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {simm}", fmt::arg("mnemonic", "vmv.v.i"), + fmt::arg("vd", vname(vd)), fmt::arg("simm", simm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV__V__I_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 609); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2765; + x86::Gp ret_val_illegal_vd_unmasked_2765 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2765, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2765; + setArg(call_illegal_vd_unmasked_2765, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2765, 0, ret_val_illegal_vd_unmasked_2765); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2767; + x86::Gp ret_val_sew_2767 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2767, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_2766; + auto vector_imm_merge_2766_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_2766_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_2766_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_2766_arg8 = ret_val_sew_2767; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_2766, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_2767, 0, reinterpret_cast(this)); + setRet(call_sew_2767, 0, ret_val_sew_2767); + setArg(call_vector_imm_merge_2766, 0, V); + setArg(call_vector_imm_merge_2766, 1, vector_imm_merge_2766_arg1); + setArg(call_vector_imm_merge_2766, 2, vector_imm_merge_2766_arg2); + setArg(call_vector_imm_merge_2766, 3, vector_imm_merge_2766_arg3); + setArg(call_vector_imm_merge_2766, 4, 1); + setArg(call_vector_imm_merge_2766, 5, vd); + setArg(call_vector_imm_merge_2766, 6, 0); + setArg(call_vector_imm_merge_2766, 7, (uint32_t)(int32_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_merge_2766, 8, vector_imm_merge_2766_arg8); + } + cc.bind(label_merge); + } + auto tmp2768 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2768, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2768, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 609); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 610: VMV__V__V */ + continuation_e __vmv__v__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs1}", fmt::arg("mnemonic", "vmv.v.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV__V__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 610); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2769; + x86::Gp ret_val_illegal_vd_unmasked_2769 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2769, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2769; + setArg(call_illegal_vd_unmasked_2769, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2769, 0, ret_val_illegal_vd_unmasked_2769); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2771; + x86::Gp ret_val_sew_2771 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2771, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_merge_2770; + auto vector_vector_merge_2770_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_merge_2770_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_merge_2770_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_merge_2770_arg8 = ret_val_sew_2771; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_merge_2770, &vector_vector_merge, FuncSignature::build()); + setArg(call_sew_2771, 0, reinterpret_cast(this)); + setRet(call_sew_2771, 0, ret_val_sew_2771); + setArg(call_vector_vector_merge_2770, 0, V); + setArg(call_vector_vector_merge_2770, 1, vector_vector_merge_2770_arg1); + setArg(call_vector_vector_merge_2770, 2, vector_vector_merge_2770_arg2); + setArg(call_vector_vector_merge_2770, 3, vector_vector_merge_2770_arg3); + setArg(call_vector_vector_merge_2770, 4, 1); + setArg(call_vector_vector_merge_2770, 5, vd); + setArg(call_vector_vector_merge_2770, 6, 0); + setArg(call_vector_vector_merge_2770, 7, vs1); + setArg(call_vector_vector_merge_2770, 8, vector_vector_merge_2770_arg8); + } + cc.bind(label_merge); + } + auto tmp2772 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2772, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2772, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 610); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 611: VMV__V__X */ + continuation_e __vmv__v__x(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vmv.v.x"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV__V__X_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 611); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2773; + x86::Gp ret_val_illegal_vd_unmasked_2773 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2773, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2774 = get_reg(cc, 8, false); + mov(cc, tmp2774, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2774, ret_val_illegal_vd_unmasked_2773); + setArg(call_illegal_vd_unmasked_2773, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2773, 0, ret_val_illegal_vd_unmasked_2773); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2776; + x86::Gp ret_val_sew_2776 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2776, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_2775; + auto vector_imm_merge_2775_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_2775_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_2775_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_2775_arg7 = gen_ext(cc, + gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true), 32, true); + auto vector_imm_merge_2775_arg8 = ret_val_sew_2776; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_2775, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_2776, 0, reinterpret_cast(this)); + setRet(call_sew_2776, 0, ret_val_sew_2776); + setArg(call_vector_imm_merge_2775, 0, V); + setArg(call_vector_imm_merge_2775, 1, vector_imm_merge_2775_arg1); + setArg(call_vector_imm_merge_2775, 2, vector_imm_merge_2775_arg2); + setArg(call_vector_imm_merge_2775, 3, vector_imm_merge_2775_arg3); + setArg(call_vector_imm_merge_2775, 4, 1); + setArg(call_vector_imm_merge_2775, 5, vd); + setArg(call_vector_imm_merge_2775, 6, 0); + setArg(call_vector_imm_merge_2775, 7, vector_imm_merge_2775_arg7); + setArg(call_vector_imm_merge_2775, 8, vector_imm_merge_2775_arg8); + } + cc.bind(label_merge); + } + auto tmp2777 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2777, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2777, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 611); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 612: VSADDU__VI */ + continuation_e __vsaddu__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vsaddu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADDU__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 612); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2778; + x86::Gp ret_val_illegal_normal_2778 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2778, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2778; + setArg(call_illegal_normal_2778, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2778, 1, vd); + setArg(call_illegal_normal_2778, 2, vm); + setRet(call_illegal_normal_2778, 0, ret_val_illegal_normal_2778); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2780; + x86::Gp ret_val_sew_2780 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2780, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2779; + auto sat_vector_imm_op_2779_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2779_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2779_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2779_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2779_arg11 = ret_val_sew_2780; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2779 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2779, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2779, 32, false) + , traits::vxsat); + setArg(call_sew_2780, 0, reinterpret_cast(this)); + setRet(call_sew_2780, 0, ret_val_sew_2780); + setArg(call_sat_vector_imm_op_2779, 0, V); + setArg(call_sat_vector_imm_op_2779, 1, 32); + setArg(call_sat_vector_imm_op_2779, 2, 3); + setArg(call_sat_vector_imm_op_2779, 3, sat_vector_imm_op_2779_arg3); + setArg(call_sat_vector_imm_op_2779, 4, sat_vector_imm_op_2779_arg4); + setArg(call_sat_vector_imm_op_2779, 5, sat_vector_imm_op_2779_arg5); + setArg(call_sat_vector_imm_op_2779, 6, sat_vector_imm_op_2779_arg6); + setArg(call_sat_vector_imm_op_2779, 7, vm); + setArg(call_sat_vector_imm_op_2779, 8, vd); + setArg(call_sat_vector_imm_op_2779, 9, vs2); + setArg(call_sat_vector_imm_op_2779, 10, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_sat_vector_imm_op_2779, 11, sat_vector_imm_op_2779_arg11); + setRet(call_sat_vector_imm_op_2779, 0, ret_val_sat_vector_imm_op_2779); + } + cc.bind(label_merge); + } + auto tmp2781 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2781, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2781, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 612); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 613: VSADDU__VV */ + continuation_e __vsaddu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADDU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 613); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2782; + x86::Gp ret_val_illegal_normal_2782 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2782, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2782; + setArg(call_illegal_normal_2782, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2782, 1, vd); + setArg(call_illegal_normal_2782, 2, vm); + setRet(call_illegal_normal_2782, 0, ret_val_illegal_normal_2782); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2784; + x86::Gp ret_val_sew_2784 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2784, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2783; + auto sat_vector_vector_op_2783_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2783_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2783_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2783_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2783_arg11 = ret_val_sew_2784; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2783 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2783, &sat_vector_vector_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_op_2783, 32, false) + , traits::vxsat); + setArg(call_sew_2784, 0, reinterpret_cast(this)); + setRet(call_sew_2784, 0, ret_val_sew_2784); + setArg(call_sat_vector_vector_op_2783, 0, V); + setArg(call_sat_vector_vector_op_2783, 1, 32); + setArg(call_sat_vector_vector_op_2783, 2, 0); + setArg(call_sat_vector_vector_op_2783, 3, sat_vector_vector_op_2783_arg3); + setArg(call_sat_vector_vector_op_2783, 4, sat_vector_vector_op_2783_arg4); + setArg(call_sat_vector_vector_op_2783, 5, sat_vector_vector_op_2783_arg5); + setArg(call_sat_vector_vector_op_2783, 6, sat_vector_vector_op_2783_arg6); + setArg(call_sat_vector_vector_op_2783, 7, vm); + setArg(call_sat_vector_vector_op_2783, 8, vd); + setArg(call_sat_vector_vector_op_2783, 9, vs2); + setArg(call_sat_vector_vector_op_2783, 10, vs1); + setArg(call_sat_vector_vector_op_2783, 11, sat_vector_vector_op_2783_arg11); + setRet(call_sat_vector_vector_op_2783, 0, ret_val_sat_vector_vector_op_2783); + } + cc.bind(label_merge); + } + auto tmp2785 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2785, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2785, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 613); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 614: VSADDU__VX */ + continuation_e __vsaddu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADDU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 614); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2786; + x86::Gp ret_val_illegal_normal_2786 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2786, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2787 = get_reg(cc, 8, false); + mov(cc, tmp2787, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2787, ret_val_illegal_normal_2786); + setArg(call_illegal_normal_2786, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2786, 1, vd); + setArg(call_illegal_normal_2786, 2, vm); + setRet(call_illegal_normal_2786, 0, ret_val_illegal_normal_2786); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2789; + x86::Gp ret_val_sew_2789 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2789, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2788; + auto sat_vector_imm_op_2788_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2788_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2788_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2788_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2788_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto sat_vector_imm_op_2788_arg11 = ret_val_sew_2789; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2788 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2788, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2788, 32, false) + , traits::vxsat); + setArg(call_sew_2789, 0, reinterpret_cast(this)); + setRet(call_sew_2789, 0, ret_val_sew_2789); + setArg(call_sat_vector_imm_op_2788, 0, V); + setArg(call_sat_vector_imm_op_2788, 1, 32); + setArg(call_sat_vector_imm_op_2788, 2, 4); + setArg(call_sat_vector_imm_op_2788, 3, sat_vector_imm_op_2788_arg3); + setArg(call_sat_vector_imm_op_2788, 4, sat_vector_imm_op_2788_arg4); + setArg(call_sat_vector_imm_op_2788, 5, sat_vector_imm_op_2788_arg5); + setArg(call_sat_vector_imm_op_2788, 6, sat_vector_imm_op_2788_arg6); + setArg(call_sat_vector_imm_op_2788, 7, vm); + setArg(call_sat_vector_imm_op_2788, 8, vd); + setArg(call_sat_vector_imm_op_2788, 9, vs2); + setArg(call_sat_vector_imm_op_2788, 10, sat_vector_imm_op_2788_arg10); + setArg(call_sat_vector_imm_op_2788, 11, sat_vector_imm_op_2788_arg11); + setRet(call_sat_vector_imm_op_2788, 0, ret_val_sat_vector_imm_op_2788); + } + cc.bind(label_merge); + } + auto tmp2790 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2790, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2790, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 614); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 615: VSADD__VI */ + continuation_e __vsadd__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vsadd.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADD__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 615); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2791; + x86::Gp ret_val_illegal_normal_2791 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2791, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2791; + setArg(call_illegal_normal_2791, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2791, 1, vd); + setArg(call_illegal_normal_2791, 2, vm); + setRet(call_illegal_normal_2791, 0, ret_val_illegal_normal_2791); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2793; + x86::Gp ret_val_sew_2793 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2793, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2792; + auto sat_vector_imm_op_2792_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2792_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2792_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2792_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2792_arg11 = ret_val_sew_2793; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2792 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2792, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2792, 32, false) + , traits::vxsat); + setArg(call_sew_2793, 0, reinterpret_cast(this)); + setRet(call_sew_2793, 0, ret_val_sew_2793); + setArg(call_sat_vector_imm_op_2792, 0, V); + setArg(call_sat_vector_imm_op_2792, 1, 33); + setArg(call_sat_vector_imm_op_2792, 2, 3); + setArg(call_sat_vector_imm_op_2792, 3, sat_vector_imm_op_2792_arg3); + setArg(call_sat_vector_imm_op_2792, 4, sat_vector_imm_op_2792_arg4); + setArg(call_sat_vector_imm_op_2792, 5, sat_vector_imm_op_2792_arg5); + setArg(call_sat_vector_imm_op_2792, 6, sat_vector_imm_op_2792_arg6); + setArg(call_sat_vector_imm_op_2792, 7, vm); + setArg(call_sat_vector_imm_op_2792, 8, vd); + setArg(call_sat_vector_imm_op_2792, 9, vs2); + setArg(call_sat_vector_imm_op_2792, 10, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_sat_vector_imm_op_2792, 11, sat_vector_imm_op_2792_arg11); + setRet(call_sat_vector_imm_op_2792, 0, ret_val_sat_vector_imm_op_2792); + } + cc.bind(label_merge); + } + auto tmp2794 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2794, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2794, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 615); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 616: VSADD__VV */ + continuation_e __vsadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 616); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2795; + x86::Gp ret_val_illegal_normal_2795 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2795, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2795; + setArg(call_illegal_normal_2795, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2795, 1, vd); + setArg(call_illegal_normal_2795, 2, vm); + setRet(call_illegal_normal_2795, 0, ret_val_illegal_normal_2795); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2797; + x86::Gp ret_val_sew_2797 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2797, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2796; + auto sat_vector_vector_op_2796_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2796_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2796_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2796_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2796_arg11 = ret_val_sew_2797; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2796 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2796, &sat_vector_vector_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_op_2796, 32, false) + , traits::vxsat); + setArg(call_sew_2797, 0, reinterpret_cast(this)); + setRet(call_sew_2797, 0, ret_val_sew_2797); + setArg(call_sat_vector_vector_op_2796, 0, V); + setArg(call_sat_vector_vector_op_2796, 1, 33); + setArg(call_sat_vector_vector_op_2796, 2, 0); + setArg(call_sat_vector_vector_op_2796, 3, sat_vector_vector_op_2796_arg3); + setArg(call_sat_vector_vector_op_2796, 4, sat_vector_vector_op_2796_arg4); + setArg(call_sat_vector_vector_op_2796, 5, sat_vector_vector_op_2796_arg5); + setArg(call_sat_vector_vector_op_2796, 6, sat_vector_vector_op_2796_arg6); + setArg(call_sat_vector_vector_op_2796, 7, vm); + setArg(call_sat_vector_vector_op_2796, 8, vd); + setArg(call_sat_vector_vector_op_2796, 9, vs2); + setArg(call_sat_vector_vector_op_2796, 10, vs1); + setArg(call_sat_vector_vector_op_2796, 11, sat_vector_vector_op_2796_arg11); + setRet(call_sat_vector_vector_op_2796, 0, ret_val_sat_vector_vector_op_2796); + } + cc.bind(label_merge); + } + auto tmp2798 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2798, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2798, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 616); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 617: VSADD__VX */ + continuation_e __vsadd__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADD__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 617); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2799; + x86::Gp ret_val_illegal_normal_2799 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2799, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2800 = get_reg(cc, 8, false); + mov(cc, tmp2800, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2800, ret_val_illegal_normal_2799); + setArg(call_illegal_normal_2799, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2799, 1, vd); + setArg(call_illegal_normal_2799, 2, vm); + setRet(call_illegal_normal_2799, 0, ret_val_illegal_normal_2799); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2802; + x86::Gp ret_val_sew_2802 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2802, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2801; + auto sat_vector_imm_op_2801_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2801_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2801_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2801_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2801_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto sat_vector_imm_op_2801_arg11 = ret_val_sew_2802; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2801 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2801, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2801, 32, false) + , traits::vxsat); + setArg(call_sew_2802, 0, reinterpret_cast(this)); + setRet(call_sew_2802, 0, ret_val_sew_2802); + setArg(call_sat_vector_imm_op_2801, 0, V); + setArg(call_sat_vector_imm_op_2801, 1, 33); + setArg(call_sat_vector_imm_op_2801, 2, 4); + setArg(call_sat_vector_imm_op_2801, 3, sat_vector_imm_op_2801_arg3); + setArg(call_sat_vector_imm_op_2801, 4, sat_vector_imm_op_2801_arg4); + setArg(call_sat_vector_imm_op_2801, 5, sat_vector_imm_op_2801_arg5); + setArg(call_sat_vector_imm_op_2801, 6, sat_vector_imm_op_2801_arg6); + setArg(call_sat_vector_imm_op_2801, 7, vm); + setArg(call_sat_vector_imm_op_2801, 8, vd); + setArg(call_sat_vector_imm_op_2801, 9, vs2); + setArg(call_sat_vector_imm_op_2801, 10, sat_vector_imm_op_2801_arg10); + setArg(call_sat_vector_imm_op_2801, 11, sat_vector_imm_op_2801_arg11); + setRet(call_sat_vector_imm_op_2801, 0, ret_val_sat_vector_imm_op_2801); + } + cc.bind(label_merge); + } + auto tmp2803 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2803, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2803, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 617); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 618: VSSUBU__VV */ + continuation_e __vssubu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSUBU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 618); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2804; + x86::Gp ret_val_illegal_normal_2804 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2804, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2804; + setArg(call_illegal_normal_2804, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2804, 1, vd); + setArg(call_illegal_normal_2804, 2, vm); + setRet(call_illegal_normal_2804, 0, ret_val_illegal_normal_2804); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2806; + x86::Gp ret_val_sew_2806 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2806, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2805; + auto sat_vector_vector_op_2805_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2805_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2805_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2805_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2805_arg11 = ret_val_sew_2806; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2805 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2805, &sat_vector_vector_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_op_2805, 32, false) + , traits::vxsat); + setArg(call_sew_2806, 0, reinterpret_cast(this)); + setRet(call_sew_2806, 0, ret_val_sew_2806); + setArg(call_sat_vector_vector_op_2805, 0, V); + setArg(call_sat_vector_vector_op_2805, 1, 34); + setArg(call_sat_vector_vector_op_2805, 2, 0); + setArg(call_sat_vector_vector_op_2805, 3, sat_vector_vector_op_2805_arg3); + setArg(call_sat_vector_vector_op_2805, 4, sat_vector_vector_op_2805_arg4); + setArg(call_sat_vector_vector_op_2805, 5, sat_vector_vector_op_2805_arg5); + setArg(call_sat_vector_vector_op_2805, 6, sat_vector_vector_op_2805_arg6); + setArg(call_sat_vector_vector_op_2805, 7, vm); + setArg(call_sat_vector_vector_op_2805, 8, vd); + setArg(call_sat_vector_vector_op_2805, 9, vs2); + setArg(call_sat_vector_vector_op_2805, 10, vs1); + setArg(call_sat_vector_vector_op_2805, 11, sat_vector_vector_op_2805_arg11); + setRet(call_sat_vector_vector_op_2805, 0, ret_val_sat_vector_vector_op_2805); + } + cc.bind(label_merge); + } + auto tmp2807 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2807, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2807, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 618); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 619: VSSUBU__VX */ + continuation_e __vssubu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSUBU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 619); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2808; + x86::Gp ret_val_illegal_normal_2808 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2808, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2809 = get_reg(cc, 8, false); + mov(cc, tmp2809, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2809, ret_val_illegal_normal_2808); + setArg(call_illegal_normal_2808, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2808, 1, vd); + setArg(call_illegal_normal_2808, 2, vm); + setRet(call_illegal_normal_2808, 0, ret_val_illegal_normal_2808); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2811; + x86::Gp ret_val_sew_2811 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2811, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2810; + auto sat_vector_imm_op_2810_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2810_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2810_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2810_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2810_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto sat_vector_imm_op_2810_arg11 = ret_val_sew_2811; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2810 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2810, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2810, 32, false) + , traits::vxsat); + setArg(call_sew_2811, 0, reinterpret_cast(this)); + setRet(call_sew_2811, 0, ret_val_sew_2811); + setArg(call_sat_vector_imm_op_2810, 0, V); + setArg(call_sat_vector_imm_op_2810, 1, 34); + setArg(call_sat_vector_imm_op_2810, 2, 4); + setArg(call_sat_vector_imm_op_2810, 3, sat_vector_imm_op_2810_arg3); + setArg(call_sat_vector_imm_op_2810, 4, sat_vector_imm_op_2810_arg4); + setArg(call_sat_vector_imm_op_2810, 5, sat_vector_imm_op_2810_arg5); + setArg(call_sat_vector_imm_op_2810, 6, sat_vector_imm_op_2810_arg6); + setArg(call_sat_vector_imm_op_2810, 7, vm); + setArg(call_sat_vector_imm_op_2810, 8, vd); + setArg(call_sat_vector_imm_op_2810, 9, vs2); + setArg(call_sat_vector_imm_op_2810, 10, sat_vector_imm_op_2810_arg10); + setArg(call_sat_vector_imm_op_2810, 11, sat_vector_imm_op_2810_arg11); + setRet(call_sat_vector_imm_op_2810, 0, ret_val_sat_vector_imm_op_2810); + } + cc.bind(label_merge); + } + auto tmp2812 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2812, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2812, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 619); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 620: VSSUB__VV */ + continuation_e __vssub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 620); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2813; + x86::Gp ret_val_illegal_normal_2813 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2813, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2813; + setArg(call_illegal_normal_2813, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2813, 1, vd); + setArg(call_illegal_normal_2813, 2, vm); + setRet(call_illegal_normal_2813, 0, ret_val_illegal_normal_2813); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2815; + x86::Gp ret_val_sew_2815 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2815, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2814; + auto sat_vector_vector_op_2814_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2814_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2814_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2814_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2814_arg11 = ret_val_sew_2815; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2814 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2814, &sat_vector_vector_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_op_2814, 32, false) + , traits::vxsat); + setArg(call_sew_2815, 0, reinterpret_cast(this)); + setRet(call_sew_2815, 0, ret_val_sew_2815); + setArg(call_sat_vector_vector_op_2814, 0, V); + setArg(call_sat_vector_vector_op_2814, 1, 35); + setArg(call_sat_vector_vector_op_2814, 2, 0); + setArg(call_sat_vector_vector_op_2814, 3, sat_vector_vector_op_2814_arg3); + setArg(call_sat_vector_vector_op_2814, 4, sat_vector_vector_op_2814_arg4); + setArg(call_sat_vector_vector_op_2814, 5, sat_vector_vector_op_2814_arg5); + setArg(call_sat_vector_vector_op_2814, 6, sat_vector_vector_op_2814_arg6); + setArg(call_sat_vector_vector_op_2814, 7, vm); + setArg(call_sat_vector_vector_op_2814, 8, vd); + setArg(call_sat_vector_vector_op_2814, 9, vs2); + setArg(call_sat_vector_vector_op_2814, 10, vs1); + setArg(call_sat_vector_vector_op_2814, 11, sat_vector_vector_op_2814_arg11); + setRet(call_sat_vector_vector_op_2814, 0, ret_val_sat_vector_vector_op_2814); + } + cc.bind(label_merge); + } + auto tmp2816 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2816, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2816, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 620); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 621: VSSUB__VX */ + continuation_e __vssub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 621); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2817; + x86::Gp ret_val_illegal_normal_2817 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2817, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2818 = get_reg(cc, 8, false); + mov(cc, tmp2818, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2818, ret_val_illegal_normal_2817); + setArg(call_illegal_normal_2817, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2817, 1, vd); + setArg(call_illegal_normal_2817, 2, vm); + setRet(call_illegal_normal_2817, 0, ret_val_illegal_normal_2817); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2820; + x86::Gp ret_val_sew_2820 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2820, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2819; + auto sat_vector_imm_op_2819_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2819_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2819_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2819_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2819_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto sat_vector_imm_op_2819_arg11 = ret_val_sew_2820; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2819 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2819, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2819, 32, false) + , traits::vxsat); + setArg(call_sew_2820, 0, reinterpret_cast(this)); + setRet(call_sew_2820, 0, ret_val_sew_2820); + setArg(call_sat_vector_imm_op_2819, 0, V); + setArg(call_sat_vector_imm_op_2819, 1, 35); + setArg(call_sat_vector_imm_op_2819, 2, 4); + setArg(call_sat_vector_imm_op_2819, 3, sat_vector_imm_op_2819_arg3); + setArg(call_sat_vector_imm_op_2819, 4, sat_vector_imm_op_2819_arg4); + setArg(call_sat_vector_imm_op_2819, 5, sat_vector_imm_op_2819_arg5); + setArg(call_sat_vector_imm_op_2819, 6, sat_vector_imm_op_2819_arg6); + setArg(call_sat_vector_imm_op_2819, 7, vm); + setArg(call_sat_vector_imm_op_2819, 8, vd); + setArg(call_sat_vector_imm_op_2819, 9, vs2); + setArg(call_sat_vector_imm_op_2819, 10, sat_vector_imm_op_2819_arg10); + setArg(call_sat_vector_imm_op_2819, 11, sat_vector_imm_op_2819_arg11); + setRet(call_sat_vector_imm_op_2819, 0, ret_val_sat_vector_imm_op_2819); + } + cc.bind(label_merge); + } + auto tmp2821 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2821, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2821, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 621); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 622: VAADDU__VV */ + continuation_e __vaaddu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vaaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAADDU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 622); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2822; + x86::Gp ret_val_illegal_normal_2822 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2822, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2822; + setArg(call_illegal_normal_2822, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2822, 1, vd); + setArg(call_illegal_normal_2822, 2, vm); + setRet(call_illegal_normal_2822, 0, ret_val_illegal_normal_2822); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2824; + x86::Gp ret_val_sew_2824 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2824, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2823; + auto sat_vector_vector_op_2823_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2823_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2823_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2823_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2823_arg11 = ret_val_sew_2824; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2823 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2823, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2823; + setArg(call_sew_2824, 0, reinterpret_cast(this)); + setRet(call_sew_2824, 0, ret_val_sew_2824); + setArg(call_sat_vector_vector_op_2823, 0, V); + setArg(call_sat_vector_vector_op_2823, 1, 8); + setArg(call_sat_vector_vector_op_2823, 2, 2); + setArg(call_sat_vector_vector_op_2823, 3, sat_vector_vector_op_2823_arg3); + setArg(call_sat_vector_vector_op_2823, 4, sat_vector_vector_op_2823_arg4); + setArg(call_sat_vector_vector_op_2823, 5, sat_vector_vector_op_2823_arg5); + setArg(call_sat_vector_vector_op_2823, 6, sat_vector_vector_op_2823_arg6); + setArg(call_sat_vector_vector_op_2823, 7, vm); + setArg(call_sat_vector_vector_op_2823, 8, vd); + setArg(call_sat_vector_vector_op_2823, 9, vs2); + setArg(call_sat_vector_vector_op_2823, 10, vs1); + setArg(call_sat_vector_vector_op_2823, 11, sat_vector_vector_op_2823_arg11); + setRet(call_sat_vector_vector_op_2823, 0, ret_val_sat_vector_vector_op_2823); + } + cc.bind(label_merge); + } + auto tmp2825 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2825, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2825, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 622); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 623: VAADDU__VX */ + continuation_e __vaaddu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vaaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAADDU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 623); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2826; + x86::Gp ret_val_illegal_normal_2826 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2826, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2827 = get_reg(cc, 8, false); + mov(cc, tmp2827, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2827, ret_val_illegal_normal_2826); + setArg(call_illegal_normal_2826, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2826, 1, vd); + setArg(call_illegal_normal_2826, 2, vm); + setRet(call_illegal_normal_2826, 0, ret_val_illegal_normal_2826); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2829; + x86::Gp ret_val_sew_2829 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2829, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2828; + auto sat_vector_imm_op_2828_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2828_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2828_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2828_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2828_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto sat_vector_imm_op_2828_arg11 = ret_val_sew_2829; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2828 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2828, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2828; + setArg(call_sew_2829, 0, reinterpret_cast(this)); + setRet(call_sew_2829, 0, ret_val_sew_2829); + setArg(call_sat_vector_imm_op_2828, 0, V); + setArg(call_sat_vector_imm_op_2828, 1, 8); + setArg(call_sat_vector_imm_op_2828, 2, 6); + setArg(call_sat_vector_imm_op_2828, 3, sat_vector_imm_op_2828_arg3); + setArg(call_sat_vector_imm_op_2828, 4, sat_vector_imm_op_2828_arg4); + setArg(call_sat_vector_imm_op_2828, 5, sat_vector_imm_op_2828_arg5); + setArg(call_sat_vector_imm_op_2828, 6, sat_vector_imm_op_2828_arg6); + setArg(call_sat_vector_imm_op_2828, 7, vm); + setArg(call_sat_vector_imm_op_2828, 8, vd); + setArg(call_sat_vector_imm_op_2828, 9, vs2); + setArg(call_sat_vector_imm_op_2828, 10, sat_vector_imm_op_2828_arg10); + setArg(call_sat_vector_imm_op_2828, 11, sat_vector_imm_op_2828_arg11); + setRet(call_sat_vector_imm_op_2828, 0, ret_val_sat_vector_imm_op_2828); + } + cc.bind(label_merge); + } + auto tmp2830 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2830, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2830, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 623); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 624: VAADD__VV */ + continuation_e __vaadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vaadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 624); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2831; + x86::Gp ret_val_illegal_normal_2831 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2831, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2831; + setArg(call_illegal_normal_2831, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2831, 1, vd); + setArg(call_illegal_normal_2831, 2, vm); + setRet(call_illegal_normal_2831, 0, ret_val_illegal_normal_2831); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2833; + x86::Gp ret_val_sew_2833 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2833, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2832; + auto sat_vector_vector_op_2832_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2832_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2832_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2832_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2832_arg11 = ret_val_sew_2833; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2832 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2832, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2832; + setArg(call_sew_2833, 0, reinterpret_cast(this)); + setRet(call_sew_2833, 0, ret_val_sew_2833); + setArg(call_sat_vector_vector_op_2832, 0, V); + setArg(call_sat_vector_vector_op_2832, 1, 9); + setArg(call_sat_vector_vector_op_2832, 2, 2); + setArg(call_sat_vector_vector_op_2832, 3, sat_vector_vector_op_2832_arg3); + setArg(call_sat_vector_vector_op_2832, 4, sat_vector_vector_op_2832_arg4); + setArg(call_sat_vector_vector_op_2832, 5, sat_vector_vector_op_2832_arg5); + setArg(call_sat_vector_vector_op_2832, 6, sat_vector_vector_op_2832_arg6); + setArg(call_sat_vector_vector_op_2832, 7, vm); + setArg(call_sat_vector_vector_op_2832, 8, vd); + setArg(call_sat_vector_vector_op_2832, 9, vs2); + setArg(call_sat_vector_vector_op_2832, 10, vs1); + setArg(call_sat_vector_vector_op_2832, 11, sat_vector_vector_op_2832_arg11); + setRet(call_sat_vector_vector_op_2832, 0, ret_val_sat_vector_vector_op_2832); + } + cc.bind(label_merge); + } + auto tmp2834 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2834, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2834, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 624); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 625: VAADD__VX */ + continuation_e __vaadd__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vaadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAADD__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 625); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2835; + x86::Gp ret_val_illegal_normal_2835 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2835, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2836 = get_reg(cc, 8, false); + mov(cc, tmp2836, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2836, ret_val_illegal_normal_2835); + setArg(call_illegal_normal_2835, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2835, 1, vd); + setArg(call_illegal_normal_2835, 2, vm); + setRet(call_illegal_normal_2835, 0, ret_val_illegal_normal_2835); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2838; + x86::Gp ret_val_sew_2838 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2838, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2837; + auto sat_vector_imm_op_2837_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2837_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2837_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2837_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2837_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto sat_vector_imm_op_2837_arg11 = ret_val_sew_2838; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2837 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2837, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2837; + setArg(call_sew_2838, 0, reinterpret_cast(this)); + setRet(call_sew_2838, 0, ret_val_sew_2838); + setArg(call_sat_vector_imm_op_2837, 0, V); + setArg(call_sat_vector_imm_op_2837, 1, 9); + setArg(call_sat_vector_imm_op_2837, 2, 6); + setArg(call_sat_vector_imm_op_2837, 3, sat_vector_imm_op_2837_arg3); + setArg(call_sat_vector_imm_op_2837, 4, sat_vector_imm_op_2837_arg4); + setArg(call_sat_vector_imm_op_2837, 5, sat_vector_imm_op_2837_arg5); + setArg(call_sat_vector_imm_op_2837, 6, sat_vector_imm_op_2837_arg6); + setArg(call_sat_vector_imm_op_2837, 7, vm); + setArg(call_sat_vector_imm_op_2837, 8, vd); + setArg(call_sat_vector_imm_op_2837, 9, vs2); + setArg(call_sat_vector_imm_op_2837, 10, sat_vector_imm_op_2837_arg10); + setArg(call_sat_vector_imm_op_2837, 11, sat_vector_imm_op_2837_arg11); + setRet(call_sat_vector_imm_op_2837, 0, ret_val_sat_vector_imm_op_2837); + } + cc.bind(label_merge); + } + auto tmp2839 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2839, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2839, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 625); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 626: VASUBU__VV */ + continuation_e __vasubu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vasubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VASUBU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 626); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2840; + x86::Gp ret_val_illegal_normal_2840 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2840, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2840; + setArg(call_illegal_normal_2840, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2840, 1, vd); + setArg(call_illegal_normal_2840, 2, vm); + setRet(call_illegal_normal_2840, 0, ret_val_illegal_normal_2840); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2842; + x86::Gp ret_val_sew_2842 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2842, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2841; + auto sat_vector_vector_op_2841_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2841_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2841_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2841_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2841_arg11 = ret_val_sew_2842; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2841 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2841, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2841; + setArg(call_sew_2842, 0, reinterpret_cast(this)); + setRet(call_sew_2842, 0, ret_val_sew_2842); + setArg(call_sat_vector_vector_op_2841, 0, V); + setArg(call_sat_vector_vector_op_2841, 1, 10); + setArg(call_sat_vector_vector_op_2841, 2, 2); + setArg(call_sat_vector_vector_op_2841, 3, sat_vector_vector_op_2841_arg3); + setArg(call_sat_vector_vector_op_2841, 4, sat_vector_vector_op_2841_arg4); + setArg(call_sat_vector_vector_op_2841, 5, sat_vector_vector_op_2841_arg5); + setArg(call_sat_vector_vector_op_2841, 6, sat_vector_vector_op_2841_arg6); + setArg(call_sat_vector_vector_op_2841, 7, vm); + setArg(call_sat_vector_vector_op_2841, 8, vd); + setArg(call_sat_vector_vector_op_2841, 9, vs2); + setArg(call_sat_vector_vector_op_2841, 10, vs1); + setArg(call_sat_vector_vector_op_2841, 11, sat_vector_vector_op_2841_arg11); + setRet(call_sat_vector_vector_op_2841, 0, ret_val_sat_vector_vector_op_2841); + } + cc.bind(label_merge); + } + auto tmp2843 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2843, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2843, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 626); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 627: VASUBU__VX */ + continuation_e __vasubu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vasubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VASUBU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 627); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2844; + x86::Gp ret_val_illegal_normal_2844 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2844, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2845 = get_reg(cc, 8, false); + mov(cc, tmp2845, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2845, ret_val_illegal_normal_2844); + setArg(call_illegal_normal_2844, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2844, 1, vd); + setArg(call_illegal_normal_2844, 2, vm); + setRet(call_illegal_normal_2844, 0, ret_val_illegal_normal_2844); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2847; + x86::Gp ret_val_sew_2847 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2847, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2846; + auto sat_vector_imm_op_2846_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2846_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2846_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2846_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2846_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto sat_vector_imm_op_2846_arg11 = ret_val_sew_2847; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2846 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2846, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2846; + setArg(call_sew_2847, 0, reinterpret_cast(this)); + setRet(call_sew_2847, 0, ret_val_sew_2847); + setArg(call_sat_vector_imm_op_2846, 0, V); + setArg(call_sat_vector_imm_op_2846, 1, 10); + setArg(call_sat_vector_imm_op_2846, 2, 6); + setArg(call_sat_vector_imm_op_2846, 3, sat_vector_imm_op_2846_arg3); + setArg(call_sat_vector_imm_op_2846, 4, sat_vector_imm_op_2846_arg4); + setArg(call_sat_vector_imm_op_2846, 5, sat_vector_imm_op_2846_arg5); + setArg(call_sat_vector_imm_op_2846, 6, sat_vector_imm_op_2846_arg6); + setArg(call_sat_vector_imm_op_2846, 7, vm); + setArg(call_sat_vector_imm_op_2846, 8, vd); + setArg(call_sat_vector_imm_op_2846, 9, vs2); + setArg(call_sat_vector_imm_op_2846, 10, sat_vector_imm_op_2846_arg10); + setArg(call_sat_vector_imm_op_2846, 11, sat_vector_imm_op_2846_arg11); + setRet(call_sat_vector_imm_op_2846, 0, ret_val_sat_vector_imm_op_2846); + } + cc.bind(label_merge); + } + auto tmp2848 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2848, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2848, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 627); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 628: VASUB__VV */ + continuation_e __vasub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vasub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VASUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 628); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2849; + x86::Gp ret_val_illegal_normal_2849 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2849, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2849; + setArg(call_illegal_normal_2849, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2849, 1, vd); + setArg(call_illegal_normal_2849, 2, vm); + setRet(call_illegal_normal_2849, 0, ret_val_illegal_normal_2849); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2851; + x86::Gp ret_val_sew_2851 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2851, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2850; + auto sat_vector_vector_op_2850_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2850_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2850_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2850_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2850_arg11 = ret_val_sew_2851; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2850 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2850, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2850; + setArg(call_sew_2851, 0, reinterpret_cast(this)); + setRet(call_sew_2851, 0, ret_val_sew_2851); + setArg(call_sat_vector_vector_op_2850, 0, V); + setArg(call_sat_vector_vector_op_2850, 1, 11); + setArg(call_sat_vector_vector_op_2850, 2, 2); + setArg(call_sat_vector_vector_op_2850, 3, sat_vector_vector_op_2850_arg3); + setArg(call_sat_vector_vector_op_2850, 4, sat_vector_vector_op_2850_arg4); + setArg(call_sat_vector_vector_op_2850, 5, sat_vector_vector_op_2850_arg5); + setArg(call_sat_vector_vector_op_2850, 6, sat_vector_vector_op_2850_arg6); + setArg(call_sat_vector_vector_op_2850, 7, vm); + setArg(call_sat_vector_vector_op_2850, 8, vd); + setArg(call_sat_vector_vector_op_2850, 9, vs2); + setArg(call_sat_vector_vector_op_2850, 10, vs1); + setArg(call_sat_vector_vector_op_2850, 11, sat_vector_vector_op_2850_arg11); + setRet(call_sat_vector_vector_op_2850, 0, ret_val_sat_vector_vector_op_2850); + } + cc.bind(label_merge); + } + auto tmp2852 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2852, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2852, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 628); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 629: VASUB__VX */ + continuation_e __vasub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vasub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VASUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 629); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2853; + x86::Gp ret_val_illegal_normal_2853 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2853, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2854 = get_reg(cc, 8, false); + mov(cc, tmp2854, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2854, ret_val_illegal_normal_2853); + setArg(call_illegal_normal_2853, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2853, 1, vd); + setArg(call_illegal_normal_2853, 2, vm); + setRet(call_illegal_normal_2853, 0, ret_val_illegal_normal_2853); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2856; + x86::Gp ret_val_sew_2856 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2856, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2855; + auto sat_vector_imm_op_2855_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2855_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2855_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2855_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2855_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto sat_vector_imm_op_2855_arg11 = ret_val_sew_2856; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2855 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2855, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2855; + setArg(call_sew_2856, 0, reinterpret_cast(this)); + setRet(call_sew_2856, 0, ret_val_sew_2856); + setArg(call_sat_vector_imm_op_2855, 0, V); + setArg(call_sat_vector_imm_op_2855, 1, 11); + setArg(call_sat_vector_imm_op_2855, 2, 6); + setArg(call_sat_vector_imm_op_2855, 3, sat_vector_imm_op_2855_arg3); + setArg(call_sat_vector_imm_op_2855, 4, sat_vector_imm_op_2855_arg4); + setArg(call_sat_vector_imm_op_2855, 5, sat_vector_imm_op_2855_arg5); + setArg(call_sat_vector_imm_op_2855, 6, sat_vector_imm_op_2855_arg6); + setArg(call_sat_vector_imm_op_2855, 7, vm); + setArg(call_sat_vector_imm_op_2855, 8, vd); + setArg(call_sat_vector_imm_op_2855, 9, vs2); + setArg(call_sat_vector_imm_op_2855, 10, sat_vector_imm_op_2855_arg10); + setArg(call_sat_vector_imm_op_2855, 11, sat_vector_imm_op_2855_arg11); + setRet(call_sat_vector_imm_op_2855, 0, ret_val_sat_vector_imm_op_2855); + } + cc.bind(label_merge); + } + auto tmp2857 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2857, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2857, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 629); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 630: VSMUL__VV */ + continuation_e __vsmul__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSMUL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 630); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2858; + x86::Gp ret_val_illegal_normal_2858 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2858, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2858; + setArg(call_illegal_normal_2858, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2858, 1, vd); + setArg(call_illegal_normal_2858, 2, vm); + setRet(call_illegal_normal_2858, 0, ret_val_illegal_normal_2858); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2860; + x86::Gp ret_val_sew_2860 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2860, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2859; + auto sat_vector_vector_op_2859_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2859_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2859_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2859_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2859_arg11 = ret_val_sew_2860; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2859 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2859, &sat_vector_vector_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_op_2859, 32, false) + , traits::vxsat); + setArg(call_sew_2860, 0, reinterpret_cast(this)); + setRet(call_sew_2860, 0, ret_val_sew_2860); + setArg(call_sat_vector_vector_op_2859, 0, V); + setArg(call_sat_vector_vector_op_2859, 1, 39); + setArg(call_sat_vector_vector_op_2859, 2, 0); + setArg(call_sat_vector_vector_op_2859, 3, sat_vector_vector_op_2859_arg3); + setArg(call_sat_vector_vector_op_2859, 4, sat_vector_vector_op_2859_arg4); + setArg(call_sat_vector_vector_op_2859, 5, sat_vector_vector_op_2859_arg5); + setArg(call_sat_vector_vector_op_2859, 6, sat_vector_vector_op_2859_arg6); + setArg(call_sat_vector_vector_op_2859, 7, vm); + setArg(call_sat_vector_vector_op_2859, 8, vd); + setArg(call_sat_vector_vector_op_2859, 9, vs2); + setArg(call_sat_vector_vector_op_2859, 10, vs1); + setArg(call_sat_vector_vector_op_2859, 11, sat_vector_vector_op_2859_arg11); + setRet(call_sat_vector_vector_op_2859, 0, ret_val_sat_vector_vector_op_2859); + } + cc.bind(label_merge); + } + auto tmp2861 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2861, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2861, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 630); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 631: VSMUL__VX */ + continuation_e __vsmul__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSMUL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 631); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2862; + x86::Gp ret_val_illegal_normal_2862 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2862, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2863 = get_reg(cc, 8, false); + mov(cc, tmp2863, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2863, ret_val_illegal_normal_2862); + setArg(call_illegal_normal_2862, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2862, 1, vd); + setArg(call_illegal_normal_2862, 2, vm); + setRet(call_illegal_normal_2862, 0, ret_val_illegal_normal_2862); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2865; + x86::Gp ret_val_sew_2865 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2865, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2864; + auto sat_vector_imm_op_2864_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2864_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2864_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2864_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2864_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto sat_vector_imm_op_2864_arg11 = ret_val_sew_2865; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2864 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2864, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2864, 32, false) + , traits::vxsat); + setArg(call_sew_2865, 0, reinterpret_cast(this)); + setRet(call_sew_2865, 0, ret_val_sew_2865); + setArg(call_sat_vector_imm_op_2864, 0, V); + setArg(call_sat_vector_imm_op_2864, 1, 39); + setArg(call_sat_vector_imm_op_2864, 2, 4); + setArg(call_sat_vector_imm_op_2864, 3, sat_vector_imm_op_2864_arg3); + setArg(call_sat_vector_imm_op_2864, 4, sat_vector_imm_op_2864_arg4); + setArg(call_sat_vector_imm_op_2864, 5, sat_vector_imm_op_2864_arg5); + setArg(call_sat_vector_imm_op_2864, 6, sat_vector_imm_op_2864_arg6); + setArg(call_sat_vector_imm_op_2864, 7, vm); + setArg(call_sat_vector_imm_op_2864, 8, vd); + setArg(call_sat_vector_imm_op_2864, 9, vs2); + setArg(call_sat_vector_imm_op_2864, 10, sat_vector_imm_op_2864_arg10); + setArg(call_sat_vector_imm_op_2864, 11, sat_vector_imm_op_2864_arg11); + setRet(call_sat_vector_imm_op_2864, 0, ret_val_sat_vector_imm_op_2864); + } + cc.bind(label_merge); + } + auto tmp2866 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2866, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2866, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 631); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 632: VSSRL__VI */ + continuation_e __vssrl__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vssrl.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRL__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 632); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2867; + x86::Gp ret_val_illegal_normal_2867 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2867, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2867; + setArg(call_illegal_normal_2867, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2867, 1, vd); + setArg(call_illegal_normal_2867, 2, vm); + setRet(call_illegal_normal_2867, 0, ret_val_illegal_normal_2867); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2869; + x86::Gp ret_val_sew_2869 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2869, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2868; + auto sat_vector_imm_op_2868_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2868_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2868_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2868_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2868_arg11 = ret_val_sew_2869; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2868 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2868, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2868; + setArg(call_sew_2869, 0, reinterpret_cast(this)); + setRet(call_sew_2869, 0, ret_val_sew_2869); + setArg(call_sat_vector_imm_op_2868, 0, V); + setArg(call_sat_vector_imm_op_2868, 1, 42); + setArg(call_sat_vector_imm_op_2868, 2, 3); + setArg(call_sat_vector_imm_op_2868, 3, sat_vector_imm_op_2868_arg3); + setArg(call_sat_vector_imm_op_2868, 4, sat_vector_imm_op_2868_arg4); + setArg(call_sat_vector_imm_op_2868, 5, sat_vector_imm_op_2868_arg5); + setArg(call_sat_vector_imm_op_2868, 6, sat_vector_imm_op_2868_arg6); + setArg(call_sat_vector_imm_op_2868, 7, vm); + setArg(call_sat_vector_imm_op_2868, 8, vd); + setArg(call_sat_vector_imm_op_2868, 9, vs2); + setArg(call_sat_vector_imm_op_2868, 10, (int32_t)(uint32_t)simm); + setArg(call_sat_vector_imm_op_2868, 11, sat_vector_imm_op_2868_arg11); + setRet(call_sat_vector_imm_op_2868, 0, ret_val_sat_vector_imm_op_2868); + } + cc.bind(label_merge); + } + auto tmp2870 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2870, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2870, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 632); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 633: VSSRL__VV */ + continuation_e __vssrl__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssrl.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 633); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2871; + x86::Gp ret_val_illegal_normal_2871 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2871, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2871; + setArg(call_illegal_normal_2871, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2871, 1, vd); + setArg(call_illegal_normal_2871, 2, vm); + setRet(call_illegal_normal_2871, 0, ret_val_illegal_normal_2871); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2873; + x86::Gp ret_val_sew_2873 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2873, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2872; + auto sat_vector_vector_op_2872_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2872_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2872_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2872_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2872_arg11 = ret_val_sew_2873; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2872 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2872, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2872; + setArg(call_sew_2873, 0, reinterpret_cast(this)); + setRet(call_sew_2873, 0, ret_val_sew_2873); + setArg(call_sat_vector_vector_op_2872, 0, V); + setArg(call_sat_vector_vector_op_2872, 1, 42); + setArg(call_sat_vector_vector_op_2872, 2, 0); + setArg(call_sat_vector_vector_op_2872, 3, sat_vector_vector_op_2872_arg3); + setArg(call_sat_vector_vector_op_2872, 4, sat_vector_vector_op_2872_arg4); + setArg(call_sat_vector_vector_op_2872, 5, sat_vector_vector_op_2872_arg5); + setArg(call_sat_vector_vector_op_2872, 6, sat_vector_vector_op_2872_arg6); + setArg(call_sat_vector_vector_op_2872, 7, vm); + setArg(call_sat_vector_vector_op_2872, 8, vd); + setArg(call_sat_vector_vector_op_2872, 9, vs2); + setArg(call_sat_vector_vector_op_2872, 10, vs1); + setArg(call_sat_vector_vector_op_2872, 11, sat_vector_vector_op_2872_arg11); + setRet(call_sat_vector_vector_op_2872, 0, ret_val_sat_vector_vector_op_2872); + } + cc.bind(label_merge); + } + auto tmp2874 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2874, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2874, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 633); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 634: VSSRL__VX */ + continuation_e __vssrl__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssrl.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 634); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2875; + x86::Gp ret_val_illegal_normal_2875 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2875, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2876 = get_reg(cc, 8, false); + mov(cc, tmp2876, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2876, ret_val_illegal_normal_2875); + setArg(call_illegal_normal_2875, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2875, 1, vd); + setArg(call_illegal_normal_2875, 2, vm); + setRet(call_illegal_normal_2875, 0, ret_val_illegal_normal_2875); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2878; + x86::Gp ret_val_sew_2878 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2878, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2877; + auto sat_vector_imm_op_2877_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2877_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2877_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2877_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2877_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); + auto sat_vector_imm_op_2877_arg11 = ret_val_sew_2878; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2877 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2877, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2877; + setArg(call_sew_2878, 0, reinterpret_cast(this)); + setRet(call_sew_2878, 0, ret_val_sew_2878); + setArg(call_sat_vector_imm_op_2877, 0, V); + setArg(call_sat_vector_imm_op_2877, 1, 42); + setArg(call_sat_vector_imm_op_2877, 2, 4); + setArg(call_sat_vector_imm_op_2877, 3, sat_vector_imm_op_2877_arg3); + setArg(call_sat_vector_imm_op_2877, 4, sat_vector_imm_op_2877_arg4); + setArg(call_sat_vector_imm_op_2877, 5, sat_vector_imm_op_2877_arg5); + setArg(call_sat_vector_imm_op_2877, 6, sat_vector_imm_op_2877_arg6); + setArg(call_sat_vector_imm_op_2877, 7, vm); + setArg(call_sat_vector_imm_op_2877, 8, vd); + setArg(call_sat_vector_imm_op_2877, 9, vs2); + setArg(call_sat_vector_imm_op_2877, 10, sat_vector_imm_op_2877_arg10); + setArg(call_sat_vector_imm_op_2877, 11, sat_vector_imm_op_2877_arg11); + setRet(call_sat_vector_imm_op_2877, 0, ret_val_sat_vector_imm_op_2877); + } + cc.bind(label_merge); + } + auto tmp2879 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2879, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2879, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 634); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 635: VSSRA__VI */ + continuation_e __vssra__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vssra.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRA__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 635); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2880; + x86::Gp ret_val_illegal_normal_2880 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2880, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2880; + setArg(call_illegal_normal_2880, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2880, 1, vd); + setArg(call_illegal_normal_2880, 2, vm); + setRet(call_illegal_normal_2880, 0, ret_val_illegal_normal_2880); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2882; + x86::Gp ret_val_sew_2882 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2882, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2881; + auto sat_vector_imm_op_2881_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2881_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2881_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2881_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2881_arg11 = ret_val_sew_2882; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2881 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2881, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2881; + setArg(call_sew_2882, 0, reinterpret_cast(this)); + setRet(call_sew_2882, 0, ret_val_sew_2882); + setArg(call_sat_vector_imm_op_2881, 0, V); + setArg(call_sat_vector_imm_op_2881, 1, 43); + setArg(call_sat_vector_imm_op_2881, 2, 3); + setArg(call_sat_vector_imm_op_2881, 3, sat_vector_imm_op_2881_arg3); + setArg(call_sat_vector_imm_op_2881, 4, sat_vector_imm_op_2881_arg4); + setArg(call_sat_vector_imm_op_2881, 5, sat_vector_imm_op_2881_arg5); + setArg(call_sat_vector_imm_op_2881, 6, sat_vector_imm_op_2881_arg6); + setArg(call_sat_vector_imm_op_2881, 7, vm); + setArg(call_sat_vector_imm_op_2881, 8, vd); + setArg(call_sat_vector_imm_op_2881, 9, vs2); + setArg(call_sat_vector_imm_op_2881, 10, (int32_t)(uint32_t)simm); + setArg(call_sat_vector_imm_op_2881, 11, sat_vector_imm_op_2881_arg11); + setRet(call_sat_vector_imm_op_2881, 0, ret_val_sat_vector_imm_op_2881); + } + cc.bind(label_merge); + } + auto tmp2883 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2883, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2883, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 635); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 636: VSSRA__VV */ + continuation_e __vssra__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssra.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRA__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 636); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2884; + x86::Gp ret_val_illegal_normal_2884 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2884, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2884; + setArg(call_illegal_normal_2884, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2884, 1, vd); + setArg(call_illegal_normal_2884, 2, vm); + setRet(call_illegal_normal_2884, 0, ret_val_illegal_normal_2884); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2886; + x86::Gp ret_val_sew_2886 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2886, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2885; + auto sat_vector_vector_op_2885_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2885_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2885_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2885_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2885_arg11 = ret_val_sew_2886; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2885 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2885, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2885; + setArg(call_sew_2886, 0, reinterpret_cast(this)); + setRet(call_sew_2886, 0, ret_val_sew_2886); + setArg(call_sat_vector_vector_op_2885, 0, V); + setArg(call_sat_vector_vector_op_2885, 1, 43); + setArg(call_sat_vector_vector_op_2885, 2, 0); + setArg(call_sat_vector_vector_op_2885, 3, sat_vector_vector_op_2885_arg3); + setArg(call_sat_vector_vector_op_2885, 4, sat_vector_vector_op_2885_arg4); + setArg(call_sat_vector_vector_op_2885, 5, sat_vector_vector_op_2885_arg5); + setArg(call_sat_vector_vector_op_2885, 6, sat_vector_vector_op_2885_arg6); + setArg(call_sat_vector_vector_op_2885, 7, vm); + setArg(call_sat_vector_vector_op_2885, 8, vd); + setArg(call_sat_vector_vector_op_2885, 9, vs2); + setArg(call_sat_vector_vector_op_2885, 10, vs1); + setArg(call_sat_vector_vector_op_2885, 11, sat_vector_vector_op_2885_arg11); + setRet(call_sat_vector_vector_op_2885, 0, ret_val_sat_vector_vector_op_2885); + } + cc.bind(label_merge); + } + auto tmp2887 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2887, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2887, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 636); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 637: VSSRA__VX */ + continuation_e __vssra__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssra.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRA__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 637); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2888; + x86::Gp ret_val_illegal_normal_2888 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2888, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2889 = get_reg(cc, 8, false); + mov(cc, tmp2889, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2889, ret_val_illegal_normal_2888); + setArg(call_illegal_normal_2888, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2888, 1, vd); + setArg(call_illegal_normal_2888, 2, vm); + setRet(call_illegal_normal_2888, 0, ret_val_illegal_normal_2888); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2891; + x86::Gp ret_val_sew_2891 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2891, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2890; + auto sat_vector_imm_op_2890_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2890_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2890_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2890_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2890_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); + auto sat_vector_imm_op_2890_arg11 = ret_val_sew_2891; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2890 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2890, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2890; + setArg(call_sew_2891, 0, reinterpret_cast(this)); + setRet(call_sew_2891, 0, ret_val_sew_2891); + setArg(call_sat_vector_imm_op_2890, 0, V); + setArg(call_sat_vector_imm_op_2890, 1, 43); + setArg(call_sat_vector_imm_op_2890, 2, 4); + setArg(call_sat_vector_imm_op_2890, 3, sat_vector_imm_op_2890_arg3); + setArg(call_sat_vector_imm_op_2890, 4, sat_vector_imm_op_2890_arg4); + setArg(call_sat_vector_imm_op_2890, 5, sat_vector_imm_op_2890_arg5); + setArg(call_sat_vector_imm_op_2890, 6, sat_vector_imm_op_2890_arg6); + setArg(call_sat_vector_imm_op_2890, 7, vm); + setArg(call_sat_vector_imm_op_2890, 8, vd); + setArg(call_sat_vector_imm_op_2890, 9, vs2); + setArg(call_sat_vector_imm_op_2890, 10, sat_vector_imm_op_2890_arg10); + setArg(call_sat_vector_imm_op_2890, 11, sat_vector_imm_op_2890_arg11); + setRet(call_sat_vector_imm_op_2890, 0, ret_val_sat_vector_imm_op_2890); + } + cc.bind(label_merge); + } + auto tmp2892 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2892, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2892, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 637); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 638: VNCLIPU__WI */ + continuation_e __vnclipu__wi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnclipu.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIPU__WI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 638); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2893; + x86::Gp ret_val_get_sew_pow_2893 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2893, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2894 = get_reg(cc, 8, false); + mov(cc, tmp2894, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2894, ret_val_get_sew_pow_2893)), 8, false), ~ 1); + setArg(call_get_sew_pow_2893, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2893, 0, ret_val_get_sew_pow_2893); + InvokeNode* call_get_lmul_pow_2895; + x86::Gp ret_val_get_lmul_pow_2895 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2895, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2895; + setArg(call_get_lmul_pow_2895, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2895, 0, ret_val_get_lmul_pow_2895); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2896; + auto illegal_variable_width_2896_arg2 = SEW_widen; + auto illegal_variable_width_2896_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2896 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2896, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2897; + auto valid_reg_overlap_2897_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2897_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2897 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2897, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2896, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2897))); + setArg(call_illegal_variable_width_2896, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2896, 1, vd); + setArg(call_illegal_variable_width_2896, 2, vm); + setArg(call_illegal_variable_width_2896, 3, illegal_variable_width_2896_arg2); + setArg(call_illegal_variable_width_2896, 4, illegal_variable_width_2896_arg3); + setRet(call_illegal_variable_width_2896, 0, ret_val_illegal_variable_width_2896); + setArg(call_valid_reg_overlap_2897, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2897, 1, vs2); + setArg(call_valid_reg_overlap_2897, 2, vd); + setArg(call_valid_reg_overlap_2897, 3, valid_reg_overlap_2897_arg2); + setArg(call_valid_reg_overlap_2897, 4, valid_reg_overlap_2897_arg3); + setRet(call_valid_reg_overlap_2897, 0, ret_val_valid_reg_overlap_2897); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2899; + x86::Gp ret_val_sew_2899 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2899, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2898; + auto sat_vector_imm_vw_2898_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2898_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2898_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2898_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2898_arg11 = ret_val_sew_2899; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_vw_2898 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2898, &sat_vector_imm_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_vw_2898, 32, false) + , traits::vxsat); + setArg(call_sew_2899, 0, reinterpret_cast(this)); + setRet(call_sew_2899, 0, ret_val_sew_2899); + setArg(call_sat_vector_imm_vw_2898, 0, V); + setArg(call_sat_vector_imm_vw_2898, 1, 46); + setArg(call_sat_vector_imm_vw_2898, 2, 3); + setArg(call_sat_vector_imm_vw_2898, 3, sat_vector_imm_vw_2898_arg3); + setArg(call_sat_vector_imm_vw_2898, 4, sat_vector_imm_vw_2898_arg4); + setArg(call_sat_vector_imm_vw_2898, 5, sat_vector_imm_vw_2898_arg5); + setArg(call_sat_vector_imm_vw_2898, 6, sat_vector_imm_vw_2898_arg6); + setArg(call_sat_vector_imm_vw_2898, 7, vm); + setArg(call_sat_vector_imm_vw_2898, 8, vd); + setArg(call_sat_vector_imm_vw_2898, 9, vs2); + setArg(call_sat_vector_imm_vw_2898, 10, (int32_t)(uint32_t)simm); + setArg(call_sat_vector_imm_vw_2898, 11, sat_vector_imm_vw_2898_arg11); + setRet(call_sat_vector_imm_vw_2898, 0, ret_val_sat_vector_imm_vw_2898); + } + cc.bind(label_merge); + } + auto tmp2900 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2900, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2900, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 638); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 639: VNCLIPU__WV */ + continuation_e __vnclipu__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnclipu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIPU__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 639); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2901; + x86::Gp ret_val_get_sew_pow_2901 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2901, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2902 = get_reg(cc, 8, false); + mov(cc, tmp2902, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2902, ret_val_get_sew_pow_2901)), 8, false), ~ 1); + setArg(call_get_sew_pow_2901, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2901, 0, ret_val_get_sew_pow_2901); + InvokeNode* call_get_lmul_pow_2903; + x86::Gp ret_val_get_lmul_pow_2903 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2903, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2903; + setArg(call_get_lmul_pow_2903, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2903, 0, ret_val_get_lmul_pow_2903); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2904; + auto illegal_variable_width_2904_arg2 = SEW_widen; + auto illegal_variable_width_2904_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2904 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2904, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2905; + auto valid_reg_overlap_2905_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2905_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2905 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2905, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2904, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2905))); + setArg(call_illegal_variable_width_2904, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2904, 1, vd); + setArg(call_illegal_variable_width_2904, 2, vm); + setArg(call_illegal_variable_width_2904, 3, illegal_variable_width_2904_arg2); + setArg(call_illegal_variable_width_2904, 4, illegal_variable_width_2904_arg3); + setRet(call_illegal_variable_width_2904, 0, ret_val_illegal_variable_width_2904); + setArg(call_valid_reg_overlap_2905, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2905, 1, vs2); + setArg(call_valid_reg_overlap_2905, 2, vd); + setArg(call_valid_reg_overlap_2905, 3, valid_reg_overlap_2905_arg2); + setArg(call_valid_reg_overlap_2905, 4, valid_reg_overlap_2905_arg3); + setRet(call_valid_reg_overlap_2905, 0, ret_val_valid_reg_overlap_2905); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2907; + x86::Gp ret_val_sew_2907 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2907, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_vw_2906; + auto sat_vector_vector_vw_2906_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_vw_2906_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_vw_2906_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_vw_2906_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_vw_2906_arg11 = ret_val_sew_2907; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_vw_2906 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_vw_2906, &sat_vector_vector_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_vw_2906, 32, false) + , traits::vxsat); + setArg(call_sew_2907, 0, reinterpret_cast(this)); + setRet(call_sew_2907, 0, ret_val_sew_2907); + setArg(call_sat_vector_vector_vw_2906, 0, V); + setArg(call_sat_vector_vector_vw_2906, 1, 46); + setArg(call_sat_vector_vector_vw_2906, 2, 0); + setArg(call_sat_vector_vector_vw_2906, 3, sat_vector_vector_vw_2906_arg3); + setArg(call_sat_vector_vector_vw_2906, 4, sat_vector_vector_vw_2906_arg4); + setArg(call_sat_vector_vector_vw_2906, 5, sat_vector_vector_vw_2906_arg5); + setArg(call_sat_vector_vector_vw_2906, 6, sat_vector_vector_vw_2906_arg6); + setArg(call_sat_vector_vector_vw_2906, 7, vm); + setArg(call_sat_vector_vector_vw_2906, 8, vd); + setArg(call_sat_vector_vector_vw_2906, 9, vs2); + setArg(call_sat_vector_vector_vw_2906, 10, vs1); + setArg(call_sat_vector_vector_vw_2906, 11, sat_vector_vector_vw_2906_arg11); + setRet(call_sat_vector_vector_vw_2906, 0, ret_val_sat_vector_vector_vw_2906); + } + cc.bind(label_merge); + } + auto tmp2908 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2908, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2908, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 639); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 640: VNCLIPU__WX */ + continuation_e __vnclipu__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnclipu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIPU__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 640); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2909; + x86::Gp ret_val_get_sew_pow_2909 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2909, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2910 = get_reg(cc, 8, false); + mov(cc, tmp2910, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2910, ret_val_get_sew_pow_2909)), 8, false), ~ 1); + setArg(call_get_sew_pow_2909, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2909, 0, ret_val_get_sew_pow_2909); + InvokeNode* call_get_lmul_pow_2911; + x86::Gp ret_val_get_lmul_pow_2911 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2911, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2911; + setArg(call_get_lmul_pow_2911, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2911, 0, ret_val_get_lmul_pow_2911); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2912; + auto illegal_variable_width_2912_arg2 = SEW_widen; + auto illegal_variable_width_2912_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2912 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2912, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2913; + auto valid_reg_overlap_2913_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2913_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2913 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2913, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2912, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2913))); + setArg(call_illegal_variable_width_2912, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2912, 1, vd); + setArg(call_illegal_variable_width_2912, 2, vm); + setArg(call_illegal_variable_width_2912, 3, illegal_variable_width_2912_arg2); + setArg(call_illegal_variable_width_2912, 4, illegal_variable_width_2912_arg3); + setRet(call_illegal_variable_width_2912, 0, ret_val_illegal_variable_width_2912); + setArg(call_valid_reg_overlap_2913, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2913, 1, vs2); + setArg(call_valid_reg_overlap_2913, 2, vd); + setArg(call_valid_reg_overlap_2913, 3, valid_reg_overlap_2913_arg2); + setArg(call_valid_reg_overlap_2913, 4, valid_reg_overlap_2913_arg3); + setRet(call_valid_reg_overlap_2913, 0, ret_val_valid_reg_overlap_2913); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2915; + x86::Gp ret_val_sew_2915 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2915, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2914; + auto sat_vector_imm_vw_2914_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2914_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2914_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2914_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2914_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); + auto sat_vector_imm_vw_2914_arg11 = ret_val_sew_2915; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_vw_2914 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2914, &sat_vector_imm_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_vw_2914, 32, false) + , traits::vxsat); + setArg(call_sew_2915, 0, reinterpret_cast(this)); + setRet(call_sew_2915, 0, ret_val_sew_2915); + setArg(call_sat_vector_imm_vw_2914, 0, V); + setArg(call_sat_vector_imm_vw_2914, 1, 46); + setArg(call_sat_vector_imm_vw_2914, 2, 4); + setArg(call_sat_vector_imm_vw_2914, 3, sat_vector_imm_vw_2914_arg3); + setArg(call_sat_vector_imm_vw_2914, 4, sat_vector_imm_vw_2914_arg4); + setArg(call_sat_vector_imm_vw_2914, 5, sat_vector_imm_vw_2914_arg5); + setArg(call_sat_vector_imm_vw_2914, 6, sat_vector_imm_vw_2914_arg6); + setArg(call_sat_vector_imm_vw_2914, 7, vm); + setArg(call_sat_vector_imm_vw_2914, 8, vd); + setArg(call_sat_vector_imm_vw_2914, 9, vs2); + setArg(call_sat_vector_imm_vw_2914, 10, sat_vector_imm_vw_2914_arg10); + setArg(call_sat_vector_imm_vw_2914, 11, sat_vector_imm_vw_2914_arg11); + setRet(call_sat_vector_imm_vw_2914, 0, ret_val_sat_vector_imm_vw_2914); + } + cc.bind(label_merge); + } + auto tmp2916 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2916, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2916, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 640); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 641: VNCLIP__WI */ + continuation_e __vnclip__wi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnclip.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIP__WI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 641); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2917; + x86::Gp ret_val_get_sew_pow_2917 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2917, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2918 = get_reg(cc, 8, false); + mov(cc, tmp2918, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2918, ret_val_get_sew_pow_2917)), 8, false), ~ 1); + setArg(call_get_sew_pow_2917, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2917, 0, ret_val_get_sew_pow_2917); + InvokeNode* call_get_lmul_pow_2919; + x86::Gp ret_val_get_lmul_pow_2919 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2919, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2919; + setArg(call_get_lmul_pow_2919, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2919, 0, ret_val_get_lmul_pow_2919); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2920; + auto illegal_variable_width_2920_arg2 = SEW_widen; + auto illegal_variable_width_2920_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2920 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2920, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2921; + auto valid_reg_overlap_2921_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2921_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2921 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2921, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2920, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2921))); + setArg(call_illegal_variable_width_2920, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2920, 1, vd); + setArg(call_illegal_variable_width_2920, 2, vm); + setArg(call_illegal_variable_width_2920, 3, illegal_variable_width_2920_arg2); + setArg(call_illegal_variable_width_2920, 4, illegal_variable_width_2920_arg3); + setRet(call_illegal_variable_width_2920, 0, ret_val_illegal_variable_width_2920); + setArg(call_valid_reg_overlap_2921, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2921, 1, vs2); + setArg(call_valid_reg_overlap_2921, 2, vd); + setArg(call_valid_reg_overlap_2921, 3, valid_reg_overlap_2921_arg2); + setArg(call_valid_reg_overlap_2921, 4, valid_reg_overlap_2921_arg3); + setRet(call_valid_reg_overlap_2921, 0, ret_val_valid_reg_overlap_2921); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2923; + x86::Gp ret_val_sew_2923 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2923, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2922; + auto sat_vector_imm_vw_2922_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2922_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2922_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2922_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2922_arg11 = ret_val_sew_2923; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_vw_2922 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2922, &sat_vector_imm_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_vw_2922, 32, false) + , traits::vxsat); + setArg(call_sew_2923, 0, reinterpret_cast(this)); + setRet(call_sew_2923, 0, ret_val_sew_2923); + setArg(call_sat_vector_imm_vw_2922, 0, V); + setArg(call_sat_vector_imm_vw_2922, 1, 47); + setArg(call_sat_vector_imm_vw_2922, 2, 3); + setArg(call_sat_vector_imm_vw_2922, 3, sat_vector_imm_vw_2922_arg3); + setArg(call_sat_vector_imm_vw_2922, 4, sat_vector_imm_vw_2922_arg4); + setArg(call_sat_vector_imm_vw_2922, 5, sat_vector_imm_vw_2922_arg5); + setArg(call_sat_vector_imm_vw_2922, 6, sat_vector_imm_vw_2922_arg6); + setArg(call_sat_vector_imm_vw_2922, 7, vm); + setArg(call_sat_vector_imm_vw_2922, 8, vd); + setArg(call_sat_vector_imm_vw_2922, 9, vs2); + setArg(call_sat_vector_imm_vw_2922, 10, (int32_t)(uint32_t)simm); + setArg(call_sat_vector_imm_vw_2922, 11, sat_vector_imm_vw_2922_arg11); + setRet(call_sat_vector_imm_vw_2922, 0, ret_val_sat_vector_imm_vw_2922); + } + cc.bind(label_merge); + } + auto tmp2924 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2924, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2924, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 641); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 642: VNCLIP__WV */ + continuation_e __vnclip__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnclip.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIP__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 642); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2925; + x86::Gp ret_val_get_sew_pow_2925 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2925, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2926 = get_reg(cc, 8, false); + mov(cc, tmp2926, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2926, ret_val_get_sew_pow_2925)), 8, false), ~ 1); + setArg(call_get_sew_pow_2925, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2925, 0, ret_val_get_sew_pow_2925); + InvokeNode* call_get_lmul_pow_2927; + x86::Gp ret_val_get_lmul_pow_2927 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2927, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2927; + setArg(call_get_lmul_pow_2927, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2927, 0, ret_val_get_lmul_pow_2927); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2928; + auto illegal_variable_width_2928_arg2 = SEW_widen; + auto illegal_variable_width_2928_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2928 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2928, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2929; + auto valid_reg_overlap_2929_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2929_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2929 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2929, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2928, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2929))); + setArg(call_illegal_variable_width_2928, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2928, 1, vd); + setArg(call_illegal_variable_width_2928, 2, vm); + setArg(call_illegal_variable_width_2928, 3, illegal_variable_width_2928_arg2); + setArg(call_illegal_variable_width_2928, 4, illegal_variable_width_2928_arg3); + setRet(call_illegal_variable_width_2928, 0, ret_val_illegal_variable_width_2928); + setArg(call_valid_reg_overlap_2929, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2929, 1, vs2); + setArg(call_valid_reg_overlap_2929, 2, vd); + setArg(call_valid_reg_overlap_2929, 3, valid_reg_overlap_2929_arg2); + setArg(call_valid_reg_overlap_2929, 4, valid_reg_overlap_2929_arg3); + setRet(call_valid_reg_overlap_2929, 0, ret_val_valid_reg_overlap_2929); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2931; + x86::Gp ret_val_sew_2931 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2931, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_vw_2930; + auto sat_vector_vector_vw_2930_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_vw_2930_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_vw_2930_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_vw_2930_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_vw_2930_arg11 = ret_val_sew_2931; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_vw_2930 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_vw_2930, &sat_vector_vector_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_vw_2930, 32, false) + , traits::vxsat); + setArg(call_sew_2931, 0, reinterpret_cast(this)); + setRet(call_sew_2931, 0, ret_val_sew_2931); + setArg(call_sat_vector_vector_vw_2930, 0, V); + setArg(call_sat_vector_vector_vw_2930, 1, 47); + setArg(call_sat_vector_vector_vw_2930, 2, 0); + setArg(call_sat_vector_vector_vw_2930, 3, sat_vector_vector_vw_2930_arg3); + setArg(call_sat_vector_vector_vw_2930, 4, sat_vector_vector_vw_2930_arg4); + setArg(call_sat_vector_vector_vw_2930, 5, sat_vector_vector_vw_2930_arg5); + setArg(call_sat_vector_vector_vw_2930, 6, sat_vector_vector_vw_2930_arg6); + setArg(call_sat_vector_vector_vw_2930, 7, vm); + setArg(call_sat_vector_vector_vw_2930, 8, vd); + setArg(call_sat_vector_vector_vw_2930, 9, vs2); + setArg(call_sat_vector_vector_vw_2930, 10, vs1); + setArg(call_sat_vector_vector_vw_2930, 11, sat_vector_vector_vw_2930_arg11); + setRet(call_sat_vector_vector_vw_2930, 0, ret_val_sat_vector_vector_vw_2930); + } + cc.bind(label_merge); + } + auto tmp2932 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2932, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2932, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 642); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 643: VNCLIP__WX */ + continuation_e __vnclip__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnclip.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIP__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 643); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2933; + x86::Gp ret_val_get_sew_pow_2933 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2933, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2934 = get_reg(cc, 8, false); + mov(cc, tmp2934, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2934, ret_val_get_sew_pow_2933)), 8, false), ~ 1); + setArg(call_get_sew_pow_2933, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2933, 0, ret_val_get_sew_pow_2933); + InvokeNode* call_get_lmul_pow_2935; + x86::Gp ret_val_get_lmul_pow_2935 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2935, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2935; + setArg(call_get_lmul_pow_2935, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2935, 0, ret_val_get_lmul_pow_2935); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2936; + auto illegal_variable_width_2936_arg2 = SEW_widen; + auto illegal_variable_width_2936_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2936 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2936, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2937; + auto valid_reg_overlap_2937_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2937_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2937 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2937, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2936, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2937))); + setArg(call_illegal_variable_width_2936, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2936, 1, vd); + setArg(call_illegal_variable_width_2936, 2, vm); + setArg(call_illegal_variable_width_2936, 3, illegal_variable_width_2936_arg2); + setArg(call_illegal_variable_width_2936, 4, illegal_variable_width_2936_arg3); + setRet(call_illegal_variable_width_2936, 0, ret_val_illegal_variable_width_2936); + setArg(call_valid_reg_overlap_2937, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2937, 1, vs2); + setArg(call_valid_reg_overlap_2937, 2, vd); + setArg(call_valid_reg_overlap_2937, 3, valid_reg_overlap_2937_arg2); + setArg(call_valid_reg_overlap_2937, 4, valid_reg_overlap_2937_arg3); + setRet(call_valid_reg_overlap_2937, 0, ret_val_valid_reg_overlap_2937); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2939; + x86::Gp ret_val_sew_2939 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2939, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2938; + auto sat_vector_imm_vw_2938_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2938_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2938_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2938_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2938_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); + auto sat_vector_imm_vw_2938_arg11 = ret_val_sew_2939; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_vw_2938 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2938, &sat_vector_imm_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_vw_2938, 32, false) + , traits::vxsat); + setArg(call_sew_2939, 0, reinterpret_cast(this)); + setRet(call_sew_2939, 0, ret_val_sew_2939); + setArg(call_sat_vector_imm_vw_2938, 0, V); + setArg(call_sat_vector_imm_vw_2938, 1, 47); + setArg(call_sat_vector_imm_vw_2938, 2, 4); + setArg(call_sat_vector_imm_vw_2938, 3, sat_vector_imm_vw_2938_arg3); + setArg(call_sat_vector_imm_vw_2938, 4, sat_vector_imm_vw_2938_arg4); + setArg(call_sat_vector_imm_vw_2938, 5, sat_vector_imm_vw_2938_arg5); + setArg(call_sat_vector_imm_vw_2938, 6, sat_vector_imm_vw_2938_arg6); + setArg(call_sat_vector_imm_vw_2938, 7, vm); + setArg(call_sat_vector_imm_vw_2938, 8, vd); + setArg(call_sat_vector_imm_vw_2938, 9, vs2); + setArg(call_sat_vector_imm_vw_2938, 10, sat_vector_imm_vw_2938_arg10); + setArg(call_sat_vector_imm_vw_2938, 11, sat_vector_imm_vw_2938_arg11); + setRet(call_sat_vector_imm_vw_2938, 0, ret_val_sat_vector_imm_vw_2938); + } + cc.bind(label_merge); + } + auto tmp2940 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2940, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2940, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 643); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 644: VREDSUM__VS */ + continuation_e __vredsum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredsum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 644); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2941; + x86::Gp ret_val_illegal_reduction_2941 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2941, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2941; + setArg(call_illegal_reduction_2941, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2941, 0, ret_val_illegal_reduction_2941); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2943; + x86::Gp ret_val_sew_2943 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2943, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2942; + auto vector_red_op_2942_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2942_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2942_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2942_arg10 = ret_val_sew_2943; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2942, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2943, 0, reinterpret_cast(this)); + setRet(call_sew_2943, 0, ret_val_sew_2943); + setArg(call_vector_red_op_2942, 0, V); + setArg(call_vector_red_op_2942, 1, 0); + setArg(call_vector_red_op_2942, 2, 2); + setArg(call_vector_red_op_2942, 3, vector_red_op_2942_arg3); + setArg(call_vector_red_op_2942, 4, vector_red_op_2942_arg4); + setArg(call_vector_red_op_2942, 5, vector_red_op_2942_arg5); + setArg(call_vector_red_op_2942, 6, vm); + setArg(call_vector_red_op_2942, 7, vd); + setArg(call_vector_red_op_2942, 8, vs2); + setArg(call_vector_red_op_2942, 9, vs1); + setArg(call_vector_red_op_2942, 10, vector_red_op_2942_arg10); + } + cc.bind(label_merge); + } + auto tmp2944 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2944, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2944, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 644); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 645: VREDMAXU__VS */ + continuation_e __vredmaxu__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmaxu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDMAXU__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 645); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2945; + x86::Gp ret_val_illegal_reduction_2945 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2945, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2945; + setArg(call_illegal_reduction_2945, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2945, 0, ret_val_illegal_reduction_2945); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2947; + x86::Gp ret_val_sew_2947 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2947, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2946; + auto vector_red_op_2946_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2946_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2946_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2946_arg10 = ret_val_sew_2947; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2946, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2947, 0, reinterpret_cast(this)); + setRet(call_sew_2947, 0, ret_val_sew_2947); + setArg(call_vector_red_op_2946, 0, V); + setArg(call_vector_red_op_2946, 1, 6); + setArg(call_vector_red_op_2946, 2, 2); + setArg(call_vector_red_op_2946, 3, vector_red_op_2946_arg3); + setArg(call_vector_red_op_2946, 4, vector_red_op_2946_arg4); + setArg(call_vector_red_op_2946, 5, vector_red_op_2946_arg5); + setArg(call_vector_red_op_2946, 6, vm); + setArg(call_vector_red_op_2946, 7, vd); + setArg(call_vector_red_op_2946, 8, vs2); + setArg(call_vector_red_op_2946, 9, vs1); + setArg(call_vector_red_op_2946, 10, vector_red_op_2946_arg10); + } + cc.bind(label_merge); + } + auto tmp2948 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2948, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2948, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 645); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 646: VREDMAX__VS */ + continuation_e __vredmax__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmax.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDMAX__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 646); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2949; + x86::Gp ret_val_illegal_reduction_2949 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2949, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2949; + setArg(call_illegal_reduction_2949, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2949, 0, ret_val_illegal_reduction_2949); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2951; + x86::Gp ret_val_sew_2951 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2951, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2950; + auto vector_red_op_2950_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2950_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2950_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2950_arg10 = ret_val_sew_2951; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2950, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2951, 0, reinterpret_cast(this)); + setRet(call_sew_2951, 0, ret_val_sew_2951); + setArg(call_vector_red_op_2950, 0, V); + setArg(call_vector_red_op_2950, 1, 7); + setArg(call_vector_red_op_2950, 2, 2); + setArg(call_vector_red_op_2950, 3, vector_red_op_2950_arg3); + setArg(call_vector_red_op_2950, 4, vector_red_op_2950_arg4); + setArg(call_vector_red_op_2950, 5, vector_red_op_2950_arg5); + setArg(call_vector_red_op_2950, 6, vm); + setArg(call_vector_red_op_2950, 7, vd); + setArg(call_vector_red_op_2950, 8, vs2); + setArg(call_vector_red_op_2950, 9, vs1); + setArg(call_vector_red_op_2950, 10, vector_red_op_2950_arg10); + } + cc.bind(label_merge); + } + auto tmp2952 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2952, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2952, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 646); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 647: VREDMINU__VS */ + continuation_e __vredminu__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredminu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDMINU__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 647); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2953; + x86::Gp ret_val_illegal_reduction_2953 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2953, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2953; + setArg(call_illegal_reduction_2953, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2953, 0, ret_val_illegal_reduction_2953); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2955; + x86::Gp ret_val_sew_2955 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2955, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2954; + auto vector_red_op_2954_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2954_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2954_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2954_arg10 = ret_val_sew_2955; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2954, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2955, 0, reinterpret_cast(this)); + setRet(call_sew_2955, 0, ret_val_sew_2955); + setArg(call_vector_red_op_2954, 0, V); + setArg(call_vector_red_op_2954, 1, 4); + setArg(call_vector_red_op_2954, 2, 2); + setArg(call_vector_red_op_2954, 3, vector_red_op_2954_arg3); + setArg(call_vector_red_op_2954, 4, vector_red_op_2954_arg4); + setArg(call_vector_red_op_2954, 5, vector_red_op_2954_arg5); + setArg(call_vector_red_op_2954, 6, vm); + setArg(call_vector_red_op_2954, 7, vd); + setArg(call_vector_red_op_2954, 8, vs2); + setArg(call_vector_red_op_2954, 9, vs1); + setArg(call_vector_red_op_2954, 10, vector_red_op_2954_arg10); + } + cc.bind(label_merge); + } + auto tmp2956 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2956, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2956, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 647); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 648: VREDMIN__VS */ + continuation_e __vredmin__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmin.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDMIN__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 648); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2957; + x86::Gp ret_val_illegal_reduction_2957 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2957, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2957; + setArg(call_illegal_reduction_2957, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2957, 0, ret_val_illegal_reduction_2957); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2959; + x86::Gp ret_val_sew_2959 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2959, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2958; + auto vector_red_op_2958_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2958_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2958_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2958_arg10 = ret_val_sew_2959; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2958, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2959, 0, reinterpret_cast(this)); + setRet(call_sew_2959, 0, ret_val_sew_2959); + setArg(call_vector_red_op_2958, 0, V); + setArg(call_vector_red_op_2958, 1, 5); + setArg(call_vector_red_op_2958, 2, 2); + setArg(call_vector_red_op_2958, 3, vector_red_op_2958_arg3); + setArg(call_vector_red_op_2958, 4, vector_red_op_2958_arg4); + setArg(call_vector_red_op_2958, 5, vector_red_op_2958_arg5); + setArg(call_vector_red_op_2958, 6, vm); + setArg(call_vector_red_op_2958, 7, vd); + setArg(call_vector_red_op_2958, 8, vs2); + setArg(call_vector_red_op_2958, 9, vs1); + setArg(call_vector_red_op_2958, 10, vector_red_op_2958_arg10); + } + cc.bind(label_merge); + } + auto tmp2960 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2960, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2960, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 648); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 649: VREDAND__VS */ + continuation_e __vredand__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredand.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDAND__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 649); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2961; + x86::Gp ret_val_illegal_reduction_2961 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2961, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2961; + setArg(call_illegal_reduction_2961, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2961, 0, ret_val_illegal_reduction_2961); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2963; + x86::Gp ret_val_sew_2963 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2963, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2962; + auto vector_red_op_2962_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2962_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2962_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2962_arg10 = ret_val_sew_2963; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2962, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2963, 0, reinterpret_cast(this)); + setRet(call_sew_2963, 0, ret_val_sew_2963); + setArg(call_vector_red_op_2962, 0, V); + setArg(call_vector_red_op_2962, 1, 1); + setArg(call_vector_red_op_2962, 2, 2); + setArg(call_vector_red_op_2962, 3, vector_red_op_2962_arg3); + setArg(call_vector_red_op_2962, 4, vector_red_op_2962_arg4); + setArg(call_vector_red_op_2962, 5, vector_red_op_2962_arg5); + setArg(call_vector_red_op_2962, 6, vm); + setArg(call_vector_red_op_2962, 7, vd); + setArg(call_vector_red_op_2962, 8, vs2); + setArg(call_vector_red_op_2962, 9, vs1); + setArg(call_vector_red_op_2962, 10, vector_red_op_2962_arg10); + } + cc.bind(label_merge); + } + auto tmp2964 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2964, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2964, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 649); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 650: VREDOR__VS */ + continuation_e __vredor__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredor.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDOR__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 650); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2965; + x86::Gp ret_val_illegal_reduction_2965 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2965, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2965; + setArg(call_illegal_reduction_2965, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2965, 0, ret_val_illegal_reduction_2965); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2967; + x86::Gp ret_val_sew_2967 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2967, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2966; + auto vector_red_op_2966_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2966_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2966_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2966_arg10 = ret_val_sew_2967; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2966, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2967, 0, reinterpret_cast(this)); + setRet(call_sew_2967, 0, ret_val_sew_2967); + setArg(call_vector_red_op_2966, 0, V); + setArg(call_vector_red_op_2966, 1, 2); + setArg(call_vector_red_op_2966, 2, 2); + setArg(call_vector_red_op_2966, 3, vector_red_op_2966_arg3); + setArg(call_vector_red_op_2966, 4, vector_red_op_2966_arg4); + setArg(call_vector_red_op_2966, 5, vector_red_op_2966_arg5); + setArg(call_vector_red_op_2966, 6, vm); + setArg(call_vector_red_op_2966, 7, vd); + setArg(call_vector_red_op_2966, 8, vs2); + setArg(call_vector_red_op_2966, 9, vs1); + setArg(call_vector_red_op_2966, 10, vector_red_op_2966_arg10); + } + cc.bind(label_merge); + } + auto tmp2968 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2968, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2968, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 650); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 651: VREDXOR__VS */ + continuation_e __vredxor__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredxor.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDXOR__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 651); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2969; + x86::Gp ret_val_illegal_reduction_2969 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2969, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2969; + setArg(call_illegal_reduction_2969, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2969, 0, ret_val_illegal_reduction_2969); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2971; + x86::Gp ret_val_sew_2971 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2971, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2970; + auto vector_red_op_2970_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2970_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2970_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2970_arg10 = ret_val_sew_2971; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2970, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2971, 0, reinterpret_cast(this)); + setRet(call_sew_2971, 0, ret_val_sew_2971); + setArg(call_vector_red_op_2970, 0, V); + setArg(call_vector_red_op_2970, 1, 3); + setArg(call_vector_red_op_2970, 2, 2); + setArg(call_vector_red_op_2970, 3, vector_red_op_2970_arg3); + setArg(call_vector_red_op_2970, 4, vector_red_op_2970_arg4); + setArg(call_vector_red_op_2970, 5, vector_red_op_2970_arg5); + setArg(call_vector_red_op_2970, 6, vm); + setArg(call_vector_red_op_2970, 7, vd); + setArg(call_vector_red_op_2970, 8, vs2); + setArg(call_vector_red_op_2970, 9, vs1); + setArg(call_vector_red_op_2970, 10, vector_red_op_2970_arg10); + } + cc.bind(label_merge); + } + auto tmp2972 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2972, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2972, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 651); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 652: VWREDSUMU__VS */ + continuation_e __vwredsumu__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwredsumu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWREDSUMU__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 652); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2973; + x86::Gp ret_val_get_sew_pow_2973 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2973, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2974 = get_reg(cc, 8, false); + mov(cc, tmp2974, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2974, ret_val_get_sew_pow_2973)), 8, false), ~ 1); + setArg(call_get_sew_pow_2973, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2973, 0, ret_val_get_sew_pow_2973); + InvokeNode* call_get_lmul_pow_2975; + x86::Gp ret_val_get_lmul_pow_2975 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2975, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2975; + setArg(call_get_lmul_pow_2975, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2975, 0, ret_val_get_lmul_pow_2975); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_widen_2976; + auto illegal_reduction_widen_2976_arg0 = SEW_widen; + auto illegal_reduction_widen_2976_arg1 = LMUL_pow_widen; + x86::Gp ret_val_illegal_reduction_widen_2976 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_widen_2976, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_widen_2976; + setArg(call_illegal_reduction_widen_2976, 0, reinterpret_cast(this)); + setArg(call_illegal_reduction_widen_2976, 1, illegal_reduction_widen_2976_arg0); + setArg(call_illegal_reduction_widen_2976, 2, illegal_reduction_widen_2976_arg1); + setRet(call_illegal_reduction_widen_2976, 0, ret_val_illegal_reduction_widen_2976); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2978; + x86::Gp ret_val_sew_2978 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2978, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_wv_2977; + auto vector_red_wv_2977_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_wv_2977_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_wv_2977_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_wv_2977_arg10 = ret_val_sew_2978; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_wv_2977, &vector_red_wv, FuncSignature::build()); + setArg(call_sew_2978, 0, reinterpret_cast(this)); + setRet(call_sew_2978, 0, ret_val_sew_2978); + setArg(call_vector_red_wv_2977, 0, V); + setArg(call_vector_red_wv_2977, 1, 48); + setArg(call_vector_red_wv_2977, 2, 0); + setArg(call_vector_red_wv_2977, 3, vector_red_wv_2977_arg3); + setArg(call_vector_red_wv_2977, 4, vector_red_wv_2977_arg4); + setArg(call_vector_red_wv_2977, 5, vector_red_wv_2977_arg5); + setArg(call_vector_red_wv_2977, 6, vm); + setArg(call_vector_red_wv_2977, 7, vd); + setArg(call_vector_red_wv_2977, 8, vs2); + setArg(call_vector_red_wv_2977, 9, vs1); + setArg(call_vector_red_wv_2977, 10, vector_red_wv_2977_arg10); + } + cc.bind(label_merge); + } + auto tmp2979 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2979, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2979, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 652); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 653: VWREDSUM__VS */ + continuation_e __vwredsum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwredsum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWREDSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 653); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2980; + x86::Gp ret_val_get_sew_pow_2980 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2980, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2981 = get_reg(cc, 8, false); + mov(cc, tmp2981, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2981, ret_val_get_sew_pow_2980)), 8, false), ~ 1); + setArg(call_get_sew_pow_2980, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2980, 0, ret_val_get_sew_pow_2980); + InvokeNode* call_get_lmul_pow_2982; + x86::Gp ret_val_get_lmul_pow_2982 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2982, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2982; + setArg(call_get_lmul_pow_2982, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2982, 0, ret_val_get_lmul_pow_2982); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_widen_2983; + auto illegal_reduction_widen_2983_arg0 = SEW_widen; + auto illegal_reduction_widen_2983_arg1 = LMUL_pow_widen; + x86::Gp ret_val_illegal_reduction_widen_2983 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_widen_2983, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_widen_2983; + setArg(call_illegal_reduction_widen_2983, 0, reinterpret_cast(this)); + setArg(call_illegal_reduction_widen_2983, 1, illegal_reduction_widen_2983_arg0); + setArg(call_illegal_reduction_widen_2983, 2, illegal_reduction_widen_2983_arg1); + setRet(call_illegal_reduction_widen_2983, 0, ret_val_illegal_reduction_widen_2983); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2985; + x86::Gp ret_val_sew_2985 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2985, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_wv_2984; + auto vector_red_wv_2984_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_wv_2984_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_wv_2984_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_wv_2984_arg10 = ret_val_sew_2985; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_wv_2984, &vector_red_wv, FuncSignature::build()); + setArg(call_sew_2985, 0, reinterpret_cast(this)); + setRet(call_sew_2985, 0, ret_val_sew_2985); + setArg(call_vector_red_wv_2984, 0, V); + setArg(call_vector_red_wv_2984, 1, 49); + setArg(call_vector_red_wv_2984, 2, 0); + setArg(call_vector_red_wv_2984, 3, vector_red_wv_2984_arg3); + setArg(call_vector_red_wv_2984, 4, vector_red_wv_2984_arg4); + setArg(call_vector_red_wv_2984, 5, vector_red_wv_2984_arg5); + setArg(call_vector_red_wv_2984, 6, vm); + setArg(call_vector_red_wv_2984, 7, vd); + setArg(call_vector_red_wv_2984, 8, vs2); + setArg(call_vector_red_wv_2984, 9, vs1); + setArg(call_vector_red_wv_2984, 10, vector_red_wv_2984_arg10); + } + cc.bind(label_merge); + } + auto tmp2986 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2986, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2986, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 653); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 654: VFREDOSUM__VS */ + continuation_e __vfredosum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredosum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFREDOSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 654); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2987; + x86::Gp ret_val_get_sew_pow_2987 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2987, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2988 = get_reg(cc, 8, false); + mov(cc, tmp2988, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2988, (ret_val_get_sew_pow_2987))), 8, false), ~ 1); + setArg(call_get_sew_pow_2987, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2987, 0, ret_val_get_sew_pow_2987); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_2989; + auto illegal_fp_reduction_2989_arg0 = SEW; + auto illegal_fp_reduction_2989_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_2989 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_2989, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_2989; + setArg(call_illegal_fp_reduction_2989, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_2989, 1, illegal_fp_reduction_2989_arg0); + setArg(call_illegal_fp_reduction_2989, 2, illegal_fp_reduction_2989_arg1); + setRet(call_illegal_fp_reduction_2989, 0, ret_val_illegal_fp_reduction_2989); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2991; + x86::Gp ret_val_sew_2991 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2991, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_2990; + auto fp_vector_red_op_2990_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_2990_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_2990_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_2990_arg10 = rm; + auto fp_vector_red_op_2990_arg11 = ret_val_sew_2991; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_op_2990, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_2991, 0, reinterpret_cast(this)); + setRet(call_sew_2991, 0, ret_val_sew_2991); + setArg(call_fp_vector_red_op_2990, 0, V); + setArg(call_fp_vector_red_op_2990, 1, 3); + setArg(call_fp_vector_red_op_2990, 2, 1); + setArg(call_fp_vector_red_op_2990, 3, fp_vector_red_op_2990_arg3); + setArg(call_fp_vector_red_op_2990, 4, fp_vector_red_op_2990_arg4); + setArg(call_fp_vector_red_op_2990, 5, fp_vector_red_op_2990_arg5); + setArg(call_fp_vector_red_op_2990, 6, vm); + setArg(call_fp_vector_red_op_2990, 7, vd); + setArg(call_fp_vector_red_op_2990, 8, vs2); + setArg(call_fp_vector_red_op_2990, 9, vs1); + setArg(call_fp_vector_red_op_2990, 10, fp_vector_red_op_2990_arg10); + setArg(call_fp_vector_red_op_2990, 11, fp_vector_red_op_2990_arg11); + InvokeNode* call_fget_flags_2992; + x86::Gp ret_val_fget_flags_2992 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_2992, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_2992; + setRet(call_fget_flags_2992, 0, ret_val_fget_flags_2992); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp2993 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2993, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2993, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 654); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 655: VFREDUSUM__VS */ + continuation_e __vfredusum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredusum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFREDUSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 655); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2994; + x86::Gp ret_val_get_sew_pow_2994 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2994, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2995 = get_reg(cc, 8, false); + mov(cc, tmp2995, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2995, (ret_val_get_sew_pow_2994))), 8, false), ~ 1); + setArg(call_get_sew_pow_2994, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2994, 0, ret_val_get_sew_pow_2994); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_2996; + auto illegal_fp_reduction_2996_arg0 = SEW; + auto illegal_fp_reduction_2996_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_2996 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_2996, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_2996; + setArg(call_illegal_fp_reduction_2996, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_2996, 1, illegal_fp_reduction_2996_arg0); + setArg(call_illegal_fp_reduction_2996, 2, illegal_fp_reduction_2996_arg1); + setRet(call_illegal_fp_reduction_2996, 0, ret_val_illegal_fp_reduction_2996); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2998; + x86::Gp ret_val_sew_2998 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2998, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_2997; + auto fp_vector_red_op_2997_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_2997_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_2997_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_2997_arg10 = rm; + auto fp_vector_red_op_2997_arg11 = ret_val_sew_2998; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_op_2997, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_2998, 0, reinterpret_cast(this)); + setRet(call_sew_2998, 0, ret_val_sew_2998); + setArg(call_fp_vector_red_op_2997, 0, V); + setArg(call_fp_vector_red_op_2997, 1, 1); + setArg(call_fp_vector_red_op_2997, 2, 1); + setArg(call_fp_vector_red_op_2997, 3, fp_vector_red_op_2997_arg3); + setArg(call_fp_vector_red_op_2997, 4, fp_vector_red_op_2997_arg4); + setArg(call_fp_vector_red_op_2997, 5, fp_vector_red_op_2997_arg5); + setArg(call_fp_vector_red_op_2997, 6, vm); + setArg(call_fp_vector_red_op_2997, 7, vd); + setArg(call_fp_vector_red_op_2997, 8, vs2); + setArg(call_fp_vector_red_op_2997, 9, vs1); + setArg(call_fp_vector_red_op_2997, 10, fp_vector_red_op_2997_arg10); + setArg(call_fp_vector_red_op_2997, 11, fp_vector_red_op_2997_arg11); + InvokeNode* call_fget_flags_2999; + x86::Gp ret_val_fget_flags_2999 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_2999, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_2999; + setRet(call_fget_flags_2999, 0, ret_val_fget_flags_2999); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3000 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3000, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3000, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 655); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 656: VFREDMAX__VS */ + continuation_e __vfredmax__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredmax.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFREDMAX__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 656); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3001; + x86::Gp ret_val_get_sew_pow_3001 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3001, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3002 = get_reg(cc, 8, false); + mov(cc, tmp3002, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3002, (ret_val_get_sew_pow_3001))), 8, false), ~ 1); + setArg(call_get_sew_pow_3001, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3001, 0, ret_val_get_sew_pow_3001); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_3003; + auto illegal_fp_reduction_3003_arg0 = SEW; + auto illegal_fp_reduction_3003_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3003 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3003, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3003; + setArg(call_illegal_fp_reduction_3003, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3003, 1, illegal_fp_reduction_3003_arg0); + setArg(call_illegal_fp_reduction_3003, 2, illegal_fp_reduction_3003_arg1); + setRet(call_illegal_fp_reduction_3003, 0, ret_val_illegal_fp_reduction_3003); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3005; + x86::Gp ret_val_sew_3005 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3005, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3004; + auto fp_vector_red_op_3004_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3004_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3004_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3004_arg10 = rm; + auto fp_vector_red_op_3004_arg11 = ret_val_sew_3005; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_op_3004, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3005, 0, reinterpret_cast(this)); + setRet(call_sew_3005, 0, ret_val_sew_3005); + setArg(call_fp_vector_red_op_3004, 0, V); + setArg(call_fp_vector_red_op_3004, 1, 7); + setArg(call_fp_vector_red_op_3004, 2, 1); + setArg(call_fp_vector_red_op_3004, 3, fp_vector_red_op_3004_arg3); + setArg(call_fp_vector_red_op_3004, 4, fp_vector_red_op_3004_arg4); + setArg(call_fp_vector_red_op_3004, 5, fp_vector_red_op_3004_arg5); + setArg(call_fp_vector_red_op_3004, 6, vm); + setArg(call_fp_vector_red_op_3004, 7, vd); + setArg(call_fp_vector_red_op_3004, 8, vs2); + setArg(call_fp_vector_red_op_3004, 9, vs1); + setArg(call_fp_vector_red_op_3004, 10, fp_vector_red_op_3004_arg10); + setArg(call_fp_vector_red_op_3004, 11, fp_vector_red_op_3004_arg11); + } + cc.bind(label_merge); + } + auto tmp3006 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3006, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3006, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 656); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 657: VFREDMIN__VS */ + continuation_e __vfredmin__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredmin.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFREDMIN__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 657); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3007; + x86::Gp ret_val_get_sew_pow_3007 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3007, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3008 = get_reg(cc, 8, false); + mov(cc, tmp3008, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3008, (ret_val_get_sew_pow_3007))), 8, false), ~ 1); + setArg(call_get_sew_pow_3007, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3007, 0, ret_val_get_sew_pow_3007); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_3009; + auto illegal_fp_reduction_3009_arg0 = SEW; + auto illegal_fp_reduction_3009_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3009 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3009, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3009; + setArg(call_illegal_fp_reduction_3009, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3009, 1, illegal_fp_reduction_3009_arg0); + setArg(call_illegal_fp_reduction_3009, 2, illegal_fp_reduction_3009_arg1); + setRet(call_illegal_fp_reduction_3009, 0, ret_val_illegal_fp_reduction_3009); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3011; + x86::Gp ret_val_sew_3011 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3011, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3010; + auto fp_vector_red_op_3010_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3010_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3010_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3010_arg10 = rm; + auto fp_vector_red_op_3010_arg11 = ret_val_sew_3011; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_op_3010, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3011, 0, reinterpret_cast(this)); + setRet(call_sew_3011, 0, ret_val_sew_3011); + setArg(call_fp_vector_red_op_3010, 0, V); + setArg(call_fp_vector_red_op_3010, 1, 5); + setArg(call_fp_vector_red_op_3010, 2, 1); + setArg(call_fp_vector_red_op_3010, 3, fp_vector_red_op_3010_arg3); + setArg(call_fp_vector_red_op_3010, 4, fp_vector_red_op_3010_arg4); + setArg(call_fp_vector_red_op_3010, 5, fp_vector_red_op_3010_arg5); + setArg(call_fp_vector_red_op_3010, 6, vm); + setArg(call_fp_vector_red_op_3010, 7, vd); + setArg(call_fp_vector_red_op_3010, 8, vs2); + setArg(call_fp_vector_red_op_3010, 9, vs1); + setArg(call_fp_vector_red_op_3010, 10, fp_vector_red_op_3010_arg10); + setArg(call_fp_vector_red_op_3010, 11, fp_vector_red_op_3010_arg11); + } + cc.bind(label_merge); + } + auto tmp3012 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3012, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3012, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 657); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 658: VFWREDOSUM__VS */ + continuation_e __vfwredosum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwredosum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWREDOSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 658); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3013; + x86::Gp ret_val_get_sew_pow_3013 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3013, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3014 = get_reg(cc, 8, false); + mov(cc, tmp3014, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3014, (ret_val_get_sew_pow_3013))), 8, false), ~ 1); + setArg(call_get_sew_pow_3013, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3013, 0, ret_val_get_sew_pow_3013); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_3015; + auto illegal_fp_reduction_3015_arg0 = SEW; + auto illegal_fp_reduction_3015_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3015 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3015, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3015; + setArg(call_illegal_fp_reduction_3015, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3015, 1, illegal_fp_reduction_3015_arg0); + setArg(call_illegal_fp_reduction_3015, 2, illegal_fp_reduction_3015_arg1); + setRet(call_illegal_fp_reduction_3015, 0, ret_val_illegal_fp_reduction_3015); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3017; + x86::Gp ret_val_sew_3017 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3017, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_wv_3016; + auto fp_vector_red_wv_3016_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_wv_3016_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_wv_3016_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_wv_3016_arg10 = rm; + auto fp_vector_red_wv_3016_arg11 = ret_val_sew_3017; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_wv_3016, &fp_vector_red_wv, FuncSignature::build()); + setArg(call_sew_3017, 0, reinterpret_cast(this)); + setRet(call_sew_3017, 0, ret_val_sew_3017); + setArg(call_fp_vector_red_wv_3016, 0, V); + setArg(call_fp_vector_red_wv_3016, 1, 51); + setArg(call_fp_vector_red_wv_3016, 2, 1); + setArg(call_fp_vector_red_wv_3016, 3, fp_vector_red_wv_3016_arg3); + setArg(call_fp_vector_red_wv_3016, 4, fp_vector_red_wv_3016_arg4); + setArg(call_fp_vector_red_wv_3016, 5, fp_vector_red_wv_3016_arg5); + setArg(call_fp_vector_red_wv_3016, 6, vm); + setArg(call_fp_vector_red_wv_3016, 7, vd); + setArg(call_fp_vector_red_wv_3016, 8, vs2); + setArg(call_fp_vector_red_wv_3016, 9, vs1); + setArg(call_fp_vector_red_wv_3016, 10, fp_vector_red_wv_3016_arg10); + setArg(call_fp_vector_red_wv_3016, 11, fp_vector_red_wv_3016_arg11); + InvokeNode* call_fget_flags_3018; + x86::Gp ret_val_fget_flags_3018 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3018, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3018; + setRet(call_fget_flags_3018, 0, ret_val_fget_flags_3018); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3019 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3019, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3019, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 658); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 659: VFWREDUSUM__VS */ + continuation_e __vfwredusum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwredusum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWREDUSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 659); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3020; + x86::Gp ret_val_get_sew_pow_3020 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3020, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3021 = get_reg(cc, 8, false); + mov(cc, tmp3021, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3021, (ret_val_get_sew_pow_3020))), 8, false), ~ 1); + setArg(call_get_sew_pow_3020, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3020, 0, ret_val_get_sew_pow_3020); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_3022; + auto illegal_fp_reduction_3022_arg0 = SEW; + auto illegal_fp_reduction_3022_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3022 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3022, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3022; + setArg(call_illegal_fp_reduction_3022, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3022, 1, illegal_fp_reduction_3022_arg0); + setArg(call_illegal_fp_reduction_3022, 2, illegal_fp_reduction_3022_arg1); + setRet(call_illegal_fp_reduction_3022, 0, ret_val_illegal_fp_reduction_3022); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3024; + x86::Gp ret_val_sew_3024 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3024, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_wv_3023; + auto fp_vector_red_wv_3023_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_wv_3023_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_wv_3023_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_wv_3023_arg10 = rm; + auto fp_vector_red_wv_3023_arg11 = ret_val_sew_3024; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_wv_3023, &fp_vector_red_wv, FuncSignature::build()); + setArg(call_sew_3024, 0, reinterpret_cast(this)); + setRet(call_sew_3024, 0, ret_val_sew_3024); + setArg(call_fp_vector_red_wv_3023, 0, V); + setArg(call_fp_vector_red_wv_3023, 1, 49); + setArg(call_fp_vector_red_wv_3023, 2, 1); + setArg(call_fp_vector_red_wv_3023, 3, fp_vector_red_wv_3023_arg3); + setArg(call_fp_vector_red_wv_3023, 4, fp_vector_red_wv_3023_arg4); + setArg(call_fp_vector_red_wv_3023, 5, fp_vector_red_wv_3023_arg5); + setArg(call_fp_vector_red_wv_3023, 6, vm); + setArg(call_fp_vector_red_wv_3023, 7, vd); + setArg(call_fp_vector_red_wv_3023, 8, vs2); + setArg(call_fp_vector_red_wv_3023, 9, vs1); + setArg(call_fp_vector_red_wv_3023, 10, fp_vector_red_wv_3023_arg10); + setArg(call_fp_vector_red_wv_3023, 11, fp_vector_red_wv_3023_arg11); + InvokeNode* call_fget_flags_3025; + x86::Gp ret_val_fget_flags_3025 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3025, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3025; + setRet(call_fget_flags_3025, 0, ret_val_fget_flags_3025); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3026 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3026, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3026, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 659); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 660: VMAND__MM */ + continuation_e __vmand__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmand.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMAND__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 660); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3027; + x86::Gp ret_val_illegal_vd_unmasked_3027 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3027, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3027; + setArg(call_illegal_vd_unmasked_3027, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3027, 0, ret_val_illegal_vd_unmasked_3027); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3028; + auto mask_mask_op_3028_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3028_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3028, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3028, 0, V); + setArg(call_mask_mask_op_3028, 1, 25); + setArg(call_mask_mask_op_3028, 2, 2); + setArg(call_mask_mask_op_3028, 3, mask_mask_op_3028_arg3); + setArg(call_mask_mask_op_3028, 4, mask_mask_op_3028_arg4); + setArg(call_mask_mask_op_3028, 5, vd); + setArg(call_mask_mask_op_3028, 6, vs2); + setArg(call_mask_mask_op_3028, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3029 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3029, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3029, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 660); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 661: VMNAND__MM */ + continuation_e __vmnand__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmnand.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMNAND__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 661); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3030; + x86::Gp ret_val_illegal_vd_unmasked_3030 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3030, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3030; + setArg(call_illegal_vd_unmasked_3030, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3030, 0, ret_val_illegal_vd_unmasked_3030); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3031; + auto mask_mask_op_3031_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3031_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3031, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3031, 0, V); + setArg(call_mask_mask_op_3031, 1, 29); + setArg(call_mask_mask_op_3031, 2, 2); + setArg(call_mask_mask_op_3031, 3, mask_mask_op_3031_arg3); + setArg(call_mask_mask_op_3031, 4, mask_mask_op_3031_arg4); + setArg(call_mask_mask_op_3031, 5, vd); + setArg(call_mask_mask_op_3031, 6, vs2); + setArg(call_mask_mask_op_3031, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3032 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3032, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3032, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 661); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 662: VMANDN__MM */ + continuation_e __vmandn__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmandn.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMANDN__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 662); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3033; + x86::Gp ret_val_illegal_vd_unmasked_3033 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3033, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3033; + setArg(call_illegal_vd_unmasked_3033, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3033, 0, ret_val_illegal_vd_unmasked_3033); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3034; + auto mask_mask_op_3034_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3034_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3034, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3034, 0, V); + setArg(call_mask_mask_op_3034, 1, 24); + setArg(call_mask_mask_op_3034, 2, 2); + setArg(call_mask_mask_op_3034, 3, mask_mask_op_3034_arg3); + setArg(call_mask_mask_op_3034, 4, mask_mask_op_3034_arg4); + setArg(call_mask_mask_op_3034, 5, vd); + setArg(call_mask_mask_op_3034, 6, vs2); + setArg(call_mask_mask_op_3034, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3035 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3035, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3035, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 662); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 663: VMXOR__MM */ + continuation_e __vmxor__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmxor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMXOR__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 663); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3036; + x86::Gp ret_val_illegal_vd_unmasked_3036 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3036, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3036; + setArg(call_illegal_vd_unmasked_3036, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3036, 0, ret_val_illegal_vd_unmasked_3036); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3037; + auto mask_mask_op_3037_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3037_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3037, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3037, 0, V); + setArg(call_mask_mask_op_3037, 1, 27); + setArg(call_mask_mask_op_3037, 2, 2); + setArg(call_mask_mask_op_3037, 3, mask_mask_op_3037_arg3); + setArg(call_mask_mask_op_3037, 4, mask_mask_op_3037_arg4); + setArg(call_mask_mask_op_3037, 5, vd); + setArg(call_mask_mask_op_3037, 6, vs2); + setArg(call_mask_mask_op_3037, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3038 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3038, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3038, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 663); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 664: VMOR__MM */ + continuation_e __vmor__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMOR__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 664); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3039; + x86::Gp ret_val_illegal_vd_unmasked_3039 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3039, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3039; + setArg(call_illegal_vd_unmasked_3039, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3039, 0, ret_val_illegal_vd_unmasked_3039); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3040; + auto mask_mask_op_3040_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3040_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3040, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3040, 0, V); + setArg(call_mask_mask_op_3040, 1, 26); + setArg(call_mask_mask_op_3040, 2, 2); + setArg(call_mask_mask_op_3040, 3, mask_mask_op_3040_arg3); + setArg(call_mask_mask_op_3040, 4, mask_mask_op_3040_arg4); + setArg(call_mask_mask_op_3040, 5, vd); + setArg(call_mask_mask_op_3040, 6, vs2); + setArg(call_mask_mask_op_3040, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3041 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3041, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3041, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 664); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 665: VMNOR__MM */ + continuation_e __vmnor__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmnor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMNOR__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 665); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3042; + x86::Gp ret_val_illegal_vd_unmasked_3042 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3042, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3042; + setArg(call_illegal_vd_unmasked_3042, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3042, 0, ret_val_illegal_vd_unmasked_3042); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3043; + auto mask_mask_op_3043_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3043_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3043, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3043, 0, V); + setArg(call_mask_mask_op_3043, 1, 30); + setArg(call_mask_mask_op_3043, 2, 2); + setArg(call_mask_mask_op_3043, 3, mask_mask_op_3043_arg3); + setArg(call_mask_mask_op_3043, 4, mask_mask_op_3043_arg4); + setArg(call_mask_mask_op_3043, 5, vd); + setArg(call_mask_mask_op_3043, 6, vs2); + setArg(call_mask_mask_op_3043, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3044 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3044, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3044, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 665); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 666: VMORN__MM */ + continuation_e __vmorn__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmorn.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMORN__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 666); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3045; + x86::Gp ret_val_illegal_vd_unmasked_3045 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3045, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3045; + setArg(call_illegal_vd_unmasked_3045, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3045, 0, ret_val_illegal_vd_unmasked_3045); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3046; + auto mask_mask_op_3046_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3046_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3046, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3046, 0, V); + setArg(call_mask_mask_op_3046, 1, 28); + setArg(call_mask_mask_op_3046, 2, 2); + setArg(call_mask_mask_op_3046, 3, mask_mask_op_3046_arg3); + setArg(call_mask_mask_op_3046, 4, mask_mask_op_3046_arg4); + setArg(call_mask_mask_op_3046, 5, vd); + setArg(call_mask_mask_op_3046, 6, vs2); + setArg(call_mask_mask_op_3046, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3047 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3047, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3047, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 666); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 667: VMXNOR__MM */ + continuation_e __vmxnor__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmxnor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMXNOR__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 667); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3048; + x86::Gp ret_val_illegal_vd_unmasked_3048 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3048, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3048; + setArg(call_illegal_vd_unmasked_3048, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3048, 0, ret_val_illegal_vd_unmasked_3048); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3049; + auto mask_mask_op_3049_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3049_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3049, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3049, 0, V); + setArg(call_mask_mask_op_3049, 1, 31); + setArg(call_mask_mask_op_3049, 2, 2); + setArg(call_mask_mask_op_3049, 3, mask_mask_op_3049_arg3); + setArg(call_mask_mask_op_3049, 4, mask_mask_op_3049_arg4); + setArg(call_mask_mask_op_3049, 5, vd); + setArg(call_mask_mask_op_3049, 6, vs2); + setArg(call_mask_mask_op_3049, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3050 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3050, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3050, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 667); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 668: VCPOP__M */ + continuation_e __vcpop__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}, {vm},", fmt::arg("mnemonic", "vcpop.m"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VCPOP__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 668); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3051; + x86::Gp ret_val_illegal_vd_unmasked_3051 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3051, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3052 = get_reg(cc, 8, false); + mov(cc, tmp3052, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3052, ret_val_illegal_vd_unmasked_3051), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); + setArg(call_illegal_vd_unmasked_3051, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3051, 0, ret_val_illegal_vd_unmasked_3051); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + InvokeNode* call_vcpop_3053; + auto vcpop_3053_arg1 = load_reg_from_mem(jh, traits::vl); + auto vcpop_3053_arg2 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vcpop_3053 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_vcpop_3053, &vcpop, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + ret_val_vcpop_3053); + setArg(call_vcpop_3053, 0, V); + setArg(call_vcpop_3053, 1, vcpop_3053_arg1); + setArg(call_vcpop_3053, 2, vcpop_3053_arg2); + setArg(call_vcpop_3053, 3, vm); + setArg(call_vcpop_3053, 4, vs2); + setRet(call_vcpop_3053, 0, ret_val_vcpop_3053); + auto tmp3054 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3054, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3054, 32, false) + , traits::vstart); + } + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 668); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 669: VFIRST__M */ + continuation_e __vfirst__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}, {vm},", fmt::arg("mnemonic", "vfirst.m"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFIRST__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 669); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3055; + x86::Gp ret_val_illegal_vd_unmasked_3055 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3055, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3056 = get_reg(cc, 8, false); + mov(cc, tmp3056, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3056, ret_val_illegal_vd_unmasked_3055), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); + setArg(call_illegal_vd_unmasked_3055, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3055, 0, ret_val_illegal_vd_unmasked_3055); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + InvokeNode* call_vfirst_3057; + auto vfirst_3057_arg1 = load_reg_from_mem(jh, traits::vl); + auto vfirst_3057_arg2 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vfirst_3057 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_vfirst_3057, &vfirst, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + ret_val_vfirst_3057); + setArg(call_vfirst_3057, 0, V); + setArg(call_vfirst_3057, 1, vfirst_3057_arg1); + setArg(call_vfirst_3057, 2, vfirst_3057_arg2); + setArg(call_vfirst_3057, 3, vm); + setArg(call_vfirst_3057, 4, vs2); + setRet(call_vfirst_3057, 0, ret_val_vfirst_3057); + auto tmp3058 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3058, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3058, 32, false) + , traits::vstart); + } + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 669); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 670: VMSBF__M */ + continuation_e __vmsbf__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsbf.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSBF__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 670); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3059; + x86::Gp ret_val_illegal_vd_unmasked_3059 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3059, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3059, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3059, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3059, 0, ret_val_illegal_vd_unmasked_3059); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_mask_set_op_3060; + auto mask_set_op_3060_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3060_arg3 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_set_op_3060, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3060, 0, V); + setArg(call_mask_set_op_3060, 1, 1); + setArg(call_mask_set_op_3060, 2, mask_set_op_3060_arg2); + setArg(call_mask_set_op_3060, 3, mask_set_op_3060_arg3); + setArg(call_mask_set_op_3060, 4, vm); + setArg(call_mask_set_op_3060, 5, vd); + setArg(call_mask_set_op_3060, 6, vs2); + auto tmp3061 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3061, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3061, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 670); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 671: VMSIF__M */ + continuation_e __vmsif__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsif.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSIF__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 671); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3062; + x86::Gp ret_val_illegal_vd_unmasked_3062 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3062, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3062, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3062, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3062, 0, ret_val_illegal_vd_unmasked_3062); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_mask_set_op_3063; + auto mask_set_op_3063_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3063_arg3 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_set_op_3063, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3063, 0, V); + setArg(call_mask_set_op_3063, 1, 3); + setArg(call_mask_set_op_3063, 2, mask_set_op_3063_arg2); + setArg(call_mask_set_op_3063, 3, mask_set_op_3063_arg3); + setArg(call_mask_set_op_3063, 4, vm); + setArg(call_mask_set_op_3063, 5, vd); + setArg(call_mask_set_op_3063, 6, vs2); + auto tmp3064 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3064, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3064, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 671); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 672: VMSOF__M */ + continuation_e __vmsof__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsof.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSOF__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 672); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3065; + x86::Gp ret_val_illegal_vd_unmasked_3065 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3065, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3065, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3065, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3065, 0, ret_val_illegal_vd_unmasked_3065); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_mask_set_op_3066; + auto mask_set_op_3066_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3066_arg3 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_set_op_3066, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3066, 0, V); + setArg(call_mask_set_op_3066, 1, 2); + setArg(call_mask_set_op_3066, 2, mask_set_op_3066_arg2); + setArg(call_mask_set_op_3066, 3, mask_set_op_3066_arg3); + setArg(call_mask_set_op_3066, 4, vm); + setArg(call_mask_set_op_3066, 5, vd); + setArg(call_mask_set_op_3066, 6, vs2); + auto tmp3067 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3067, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3067, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 672); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 673: VIOTA__M */ + continuation_e __viota__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "viota.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VIOTA__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 673); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3068; + x86::Gp ret_val_illegal_vd_unmasked_3068 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3068, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3068, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3068, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3068, 0, ret_val_illegal_vd_unmasked_3068); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3070; + x86::Gp ret_val_sew_3070 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3070, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_viota_3069; + auto viota_3069_arg1 = load_reg_from_mem(jh, traits::vl); + auto viota_3069_arg2 = load_reg_from_mem(jh, traits::vstart); + auto viota_3069_arg3 = load_reg_from_mem(jh, traits::vtype); + auto viota_3069_arg7 = ret_val_sew_3070; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_viota_3069, &viota, FuncSignature::build()); + setArg(call_sew_3070, 0, reinterpret_cast(this)); + setRet(call_sew_3070, 0, ret_val_sew_3070); + setArg(call_viota_3069, 0, V); + setArg(call_viota_3069, 1, viota_3069_arg1); + setArg(call_viota_3069, 2, viota_3069_arg2); + setArg(call_viota_3069, 3, viota_3069_arg3); + setArg(call_viota_3069, 4, vm); + setArg(call_viota_3069, 5, vd); + setArg(call_viota_3069, 6, vs2); + setArg(call_viota_3069, 7, viota_3069_arg7); + auto tmp3071 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3071, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3071, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 673); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 674: VID__V */ + continuation_e __vid__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vm},", fmt::arg("mnemonic", "vid.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VID__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 674); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3072; + x86::Gp ret_val_illegal_normal_3072 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3072, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_3072; + setArg(call_illegal_normal_3072, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3072, 1, vd); + setArg(call_illegal_normal_3072, 2, vm); + setRet(call_illegal_normal_3072, 0, ret_val_illegal_normal_3072); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3074; + x86::Gp ret_val_sew_3074 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3074, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vid_3073; + auto vid_3073_arg1 = load_reg_from_mem(jh, traits::vl); + auto vid_3073_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vid_3073_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vid_3073_arg6 = ret_val_sew_3074; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vid_3073, &vid, FuncSignature::build()); + setArg(call_sew_3074, 0, reinterpret_cast(this)); + setRet(call_sew_3074, 0, ret_val_sew_3074); + setArg(call_vid_3073, 0, V); + setArg(call_vid_3073, 1, vid_3073_arg1); + setArg(call_vid_3073, 2, vid_3073_arg2); + setArg(call_vid_3073, 3, vid_3073_arg3); + setArg(call_vid_3073, 4, vm); + setArg(call_vid_3073, 5, vd); + setArg(call_vid_3073, 6, vid_3073_arg6); + auto tmp3075 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3075, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3075, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 674); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 675: VMV__S__X */ + continuation_e __vmv__s__x(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vmv.s.x"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV__S__X_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 675); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3076; + x86::Gp ret_val_illegal_vd_unmasked_3076 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3076, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3077 = get_reg(cc, 8, false); + mov(cc, tmp3077, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3077, ret_val_illegal_vd_unmasked_3076); + setArg(call_illegal_vd_unmasked_3076, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3076, 0, ret_val_illegal_vd_unmasked_3076); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3079; + x86::Gp ret_val_sew_3079 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3079, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_to_vector_3078; + auto scalar_to_vector_3078_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_to_vector_3078_arg3 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); + auto scalar_to_vector_3078_arg4 = ret_val_sew_3079; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_scalar_to_vector_3078, &scalar_to_vector, FuncSignature::build()); + setArg(call_sew_3079, 0, reinterpret_cast(this)); + setRet(call_sew_3079, 0, ret_val_sew_3079); + setArg(call_scalar_to_vector_3078, 0, V); + setArg(call_scalar_to_vector_3078, 1, scalar_to_vector_3078_arg1); + setArg(call_scalar_to_vector_3078, 2, vd); + setArg(call_scalar_to_vector_3078, 3, scalar_to_vector_3078_arg3); + setArg(call_scalar_to_vector_3078, 4, scalar_to_vector_3078_arg4); + } + cc.bind(label_merge); + } + auto tmp3080 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3080, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3080, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 675); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 676: VMV__X__S */ + continuation_e __vmv__x__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}", fmt::arg("mnemonic", "vmv.x.s"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV__X__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 676); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3081; + x86::Gp ret_val_illegal_vd_unmasked_3081 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3081, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3082 = get_reg(cc, 8, false); + mov(cc, tmp3082, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3082, ret_val_illegal_vd_unmasked_3081); + setArg(call_illegal_vd_unmasked_3081, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3081, 0, ret_val_illegal_vd_unmasked_3081); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + InvokeNode* call_sew_3084; + x86::Gp ret_val_sew_3084 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3084, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_from_vector_3083; + auto scalar_from_vector_3083_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_from_vector_3083_arg3 = ret_val_sew_3084; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_scalar_from_vector_3083 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_scalar_from_vector_3083, &scalar_from_vector, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + ret_val_scalar_from_vector_3083); + setArg(call_sew_3084, 0, reinterpret_cast(this)); + setRet(call_sew_3084, 0, ret_val_sew_3084); + setArg(call_scalar_from_vector_3083, 0, V); + setArg(call_scalar_from_vector_3083, 1, scalar_from_vector_3083_arg1); + setArg(call_scalar_from_vector_3083, 2, vs2); + setArg(call_scalar_from_vector_3083, 3, scalar_from_vector_3083_arg3); + setRet(call_scalar_from_vector_3083, 0, ret_val_scalar_from_vector_3083); + } + auto tmp3085 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3085, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3085, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 676); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 677: VSLIDEUP__VI */ + continuation_e __vslideup__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vslideup.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDEUP__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 677); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3086; + x86::Gp ret_val_illegal_normal_3086 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3086, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3086, vs2==vd); + setArg(call_illegal_normal_3086, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3086, 1, vd); + setArg(call_illegal_normal_3086, 2, vm); + setRet(call_illegal_normal_3086, 0, ret_val_illegal_normal_3086); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3088; + x86::Gp ret_val_sew_3088 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3088, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slideup_3087; + auto vector_slideup_3087_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slideup_3087_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slideup_3087_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slideup_3087_arg8 = ret_val_sew_3088; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slideup_3087, &vector_slideup, FuncSignature::build()); + setArg(call_sew_3088, 0, reinterpret_cast(this)); + setRet(call_sew_3088, 0, ret_val_sew_3088); + setArg(call_vector_slideup_3087, 0, V); + setArg(call_vector_slideup_3087, 1, vector_slideup_3087_arg1); + setArg(call_vector_slideup_3087, 2, vector_slideup_3087_arg2); + setArg(call_vector_slideup_3087, 3, vector_slideup_3087_arg3); + setArg(call_vector_slideup_3087, 4, vm); + setArg(call_vector_slideup_3087, 5, vd); + setArg(call_vector_slideup_3087, 6, vs2); + setArg(call_vector_slideup_3087, 7, (uint32_t)simm); + setArg(call_vector_slideup_3087, 8, vector_slideup_3087_arg8); + } + cc.bind(label_merge); + } + auto tmp3089 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3089, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3089, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 677); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 678: VSLIDEUP__VX */ + continuation_e __vslideup__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslideup.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDEUP__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 678); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3090; + x86::Gp ret_val_illegal_normal_3090 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3090, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3091 = get_reg(cc, 8, false); + mov(cc, tmp3091, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3091, ret_val_illegal_normal_3090), vs2==vd); + setArg(call_illegal_normal_3090, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3090, 1, vd); + setArg(call_illegal_normal_3090, 2, vm); + setRet(call_illegal_normal_3090, 0, ret_val_illegal_normal_3090); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3093; + x86::Gp ret_val_sew_3093 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3093, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slideup_3092; + auto vector_slideup_3092_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slideup_3092_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slideup_3092_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slideup_3092_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_slideup_3092_arg8 = ret_val_sew_3093; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slideup_3092, &vector_slideup, FuncSignature::build()); + setArg(call_sew_3093, 0, reinterpret_cast(this)); + setRet(call_sew_3093, 0, ret_val_sew_3093); + setArg(call_vector_slideup_3092, 0, V); + setArg(call_vector_slideup_3092, 1, vector_slideup_3092_arg1); + setArg(call_vector_slideup_3092, 2, vector_slideup_3092_arg2); + setArg(call_vector_slideup_3092, 3, vector_slideup_3092_arg3); + setArg(call_vector_slideup_3092, 4, vm); + setArg(call_vector_slideup_3092, 5, vd); + setArg(call_vector_slideup_3092, 6, vs2); + setArg(call_vector_slideup_3092, 7, vector_slideup_3092_arg7); + setArg(call_vector_slideup_3092, 8, vector_slideup_3092_arg8); + } + cc.bind(label_merge); + } + auto tmp3094 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3094, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3094, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 678); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 679: VSLIDEDOWN__VI */ + continuation_e __vslidedown__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vslidedown.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDEDOWN__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 679); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3095; + x86::Gp ret_val_illegal_normal_3095 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3095, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_3095; + setArg(call_illegal_normal_3095, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3095, 1, vd); + setArg(call_illegal_normal_3095, 2, vm); + setRet(call_illegal_normal_3095, 0, ret_val_illegal_normal_3095); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3097; + x86::Gp ret_val_sew_3097 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3097, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slidedown_3096; + auto vector_slidedown_3096_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slidedown_3096_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slidedown_3096_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slidedown_3096_arg8 = ret_val_sew_3097; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slidedown_3096, &vector_slidedown, FuncSignature::build()); + setArg(call_sew_3097, 0, reinterpret_cast(this)); + setRet(call_sew_3097, 0, ret_val_sew_3097); + setArg(call_vector_slidedown_3096, 0, V); + setArg(call_vector_slidedown_3096, 1, vector_slidedown_3096_arg1); + setArg(call_vector_slidedown_3096, 2, vector_slidedown_3096_arg2); + setArg(call_vector_slidedown_3096, 3, vector_slidedown_3096_arg3); + setArg(call_vector_slidedown_3096, 4, vm); + setArg(call_vector_slidedown_3096, 5, vd); + setArg(call_vector_slidedown_3096, 6, vs2); + setArg(call_vector_slidedown_3096, 7, (uint32_t)simm); + setArg(call_vector_slidedown_3096, 8, vector_slidedown_3096_arg8); + } + cc.bind(label_merge); + } + auto tmp3098 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3098, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3098, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 679); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 680: VSLIDEDOWN__VX */ + continuation_e __vslidedown__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslidedown.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDEDOWN__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 680); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3099; + x86::Gp ret_val_illegal_normal_3099 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3099, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3100 = get_reg(cc, 8, false); + mov(cc, tmp3100, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3100, ret_val_illegal_normal_3099); + setArg(call_illegal_normal_3099, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3099, 1, vd); + setArg(call_illegal_normal_3099, 2, vm); + setRet(call_illegal_normal_3099, 0, ret_val_illegal_normal_3099); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3102; + x86::Gp ret_val_sew_3102 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3102, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slidedown_3101; + auto vector_slidedown_3101_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slidedown_3101_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slidedown_3101_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slidedown_3101_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_slidedown_3101_arg8 = ret_val_sew_3102; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slidedown_3101, &vector_slidedown, FuncSignature::build()); + setArg(call_sew_3102, 0, reinterpret_cast(this)); + setRet(call_sew_3102, 0, ret_val_sew_3102); + setArg(call_vector_slidedown_3101, 0, V); + setArg(call_vector_slidedown_3101, 1, vector_slidedown_3101_arg1); + setArg(call_vector_slidedown_3101, 2, vector_slidedown_3101_arg2); + setArg(call_vector_slidedown_3101, 3, vector_slidedown_3101_arg3); + setArg(call_vector_slidedown_3101, 4, vm); + setArg(call_vector_slidedown_3101, 5, vd); + setArg(call_vector_slidedown_3101, 6, vs2); + setArg(call_vector_slidedown_3101, 7, vector_slidedown_3101_arg7); + setArg(call_vector_slidedown_3101, 8, vector_slidedown_3101_arg8); + } + cc.bind(label_merge); + } + auto tmp3103 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3103, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3103, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 680); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 681: VSLIDE1UP__VX */ + continuation_e __vslide1up__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslide1up.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDE1UP__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 681); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3104; + x86::Gp ret_val_illegal_normal_3104 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3104, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3105 = get_reg(cc, 8, false); + mov(cc, tmp3105, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3105, ret_val_illegal_normal_3104), vs2==vd); + setArg(call_illegal_normal_3104, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3104, 1, vd); + setArg(call_illegal_normal_3104, 2, vm); + setRet(call_illegal_normal_3104, 0, ret_val_illegal_normal_3104); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3107; + x86::Gp ret_val_sew_3107 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3107, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slide1up_3106; + auto vector_slide1up_3106_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slide1up_3106_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slide1up_3106_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slide1up_3106_arg7 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto vector_slide1up_3106_arg8 = ret_val_sew_3107; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slide1up_3106, &vector_slide1up, FuncSignature::build()); + setArg(call_sew_3107, 0, reinterpret_cast(this)); + setRet(call_sew_3107, 0, ret_val_sew_3107); + setArg(call_vector_slide1up_3106, 0, V); + setArg(call_vector_slide1up_3106, 1, vector_slide1up_3106_arg1); + setArg(call_vector_slide1up_3106, 2, vector_slide1up_3106_arg2); + setArg(call_vector_slide1up_3106, 3, vector_slide1up_3106_arg3); + setArg(call_vector_slide1up_3106, 4, vm); + setArg(call_vector_slide1up_3106, 5, vd); + setArg(call_vector_slide1up_3106, 6, vs2); + setArg(call_vector_slide1up_3106, 7, vector_slide1up_3106_arg7); + setArg(call_vector_slide1up_3106, 8, vector_slide1up_3106_arg8); + } + cc.bind(label_merge); + } + auto tmp3108 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3108, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3108, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 681); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 682: VSLIDE1DOWN__VX */ + continuation_e __vslide1down__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslide1down.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDE1DOWN__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 682); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3109; + x86::Gp ret_val_illegal_normal_3109 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3109, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3110 = get_reg(cc, 8, false); + mov(cc, tmp3110, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3110, ret_val_illegal_normal_3109); + setArg(call_illegal_normal_3109, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3109, 1, vd); + setArg(call_illegal_normal_3109, 2, vm); + setRet(call_illegal_normal_3109, 0, ret_val_illegal_normal_3109); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3112; + x86::Gp ret_val_sew_3112 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3112, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slide1down_3111; + auto vector_slide1down_3111_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slide1down_3111_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slide1down_3111_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slide1down_3111_arg7 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto vector_slide1down_3111_arg8 = ret_val_sew_3112; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slide1down_3111, &vector_slide1down, FuncSignature::build()); + setArg(call_sew_3112, 0, reinterpret_cast(this)); + setRet(call_sew_3112, 0, ret_val_sew_3112); + setArg(call_vector_slide1down_3111, 0, V); + setArg(call_vector_slide1down_3111, 1, vector_slide1down_3111_arg1); + setArg(call_vector_slide1down_3111, 2, vector_slide1down_3111_arg2); + setArg(call_vector_slide1down_3111, 3, vector_slide1down_3111_arg3); + setArg(call_vector_slide1down_3111, 4, vm); + setArg(call_vector_slide1down_3111, 5, vd); + setArg(call_vector_slide1down_3111, 6, vs2); + setArg(call_vector_slide1down_3111, 7, vector_slide1down_3111_arg7); + setArg(call_vector_slide1down_3111, 8, vector_slide1down_3111_arg8); + } + cc.bind(label_merge); + } + auto tmp3113 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3113, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3113, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 682); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 683: VRGATHER__VI */ + continuation_e __vrgather__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vrgather.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRGATHER__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 683); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3114; + x86::Gp ret_val_illegal_normal_3114 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3114, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3114, vs2==vd); + setArg(call_illegal_normal_3114, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3114, 1, vd); + setArg(call_illegal_normal_3114, 2, vm); + setRet(call_illegal_normal_3114, 0, ret_val_illegal_normal_3114); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3116; + x86::Gp ret_val_sew_3116 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3116, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_gather_3115; + auto vector_imm_gather_3115_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_gather_3115_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_gather_3115_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_gather_3115_arg8 = ret_val_sew_3116; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_gather_3115, &vector_imm_gather, FuncSignature::build()); + setArg(call_sew_3116, 0, reinterpret_cast(this)); + setRet(call_sew_3116, 0, ret_val_sew_3116); + setArg(call_vector_imm_gather_3115, 0, V); + setArg(call_vector_imm_gather_3115, 1, vector_imm_gather_3115_arg1); + setArg(call_vector_imm_gather_3115, 2, vector_imm_gather_3115_arg2); + setArg(call_vector_imm_gather_3115, 3, vector_imm_gather_3115_arg3); + setArg(call_vector_imm_gather_3115, 4, vm); + setArg(call_vector_imm_gather_3115, 5, vd); + setArg(call_vector_imm_gather_3115, 6, vs2); + setArg(call_vector_imm_gather_3115, 7, (uint32_t)simm); + setArg(call_vector_imm_gather_3115, 8, vector_imm_gather_3115_arg8); + auto tmp3117 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3117, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3117, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 683); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 684: VRGATHER__VV */ + continuation_e __vrgather__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrgather.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRGATHER__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 684); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3118; + x86::Gp ret_val_illegal_normal_3118 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3118, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3118, vs1==vd), vs2==vd); + setArg(call_illegal_normal_3118, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3118, 1, vd); + setArg(call_illegal_normal_3118, 2, vm); + setRet(call_illegal_normal_3118, 0, ret_val_illegal_normal_3118); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3120; + x86::Gp ret_val_sew_3120 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3120, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_gather_3119; + auto vector_vector_gather_3119_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_gather_3119_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_gather_3119_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_gather_3119_arg8 = ret_val_sew_3120; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_gather_3119, &vector_vector_gather, FuncSignature::build()); + setArg(call_sew_3120, 0, reinterpret_cast(this)); + setRet(call_sew_3120, 0, ret_val_sew_3120); + setArg(call_vector_vector_gather_3119, 0, V); + setArg(call_vector_vector_gather_3119, 1, vector_vector_gather_3119_arg1); + setArg(call_vector_vector_gather_3119, 2, vector_vector_gather_3119_arg2); + setArg(call_vector_vector_gather_3119, 3, vector_vector_gather_3119_arg3); + setArg(call_vector_vector_gather_3119, 4, vm); + setArg(call_vector_vector_gather_3119, 5, vd); + setArg(call_vector_vector_gather_3119, 6, vs2); + setArg(call_vector_vector_gather_3119, 7, vs1); + setArg(call_vector_vector_gather_3119, 8, vector_vector_gather_3119_arg8); + auto tmp3121 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3121, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3121, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 684); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 685: VRGATHER__VX */ + continuation_e __vrgather__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrgather.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRGATHER__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 685); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3122; + x86::Gp ret_val_illegal_normal_3122 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3122, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3123 = get_reg(cc, 8, false); + mov(cc, tmp3123, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3123, ret_val_illegal_normal_3122), vs2==vd); + setArg(call_illegal_normal_3122, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3122, 1, vd); + setArg(call_illegal_normal_3122, 2, vm); + setRet(call_illegal_normal_3122, 0, ret_val_illegal_normal_3122); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3125; + x86::Gp ret_val_sew_3125 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3125, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_gather_3124; + auto vector_imm_gather_3124_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_gather_3124_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_gather_3124_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_gather_3124_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_imm_gather_3124_arg8 = ret_val_sew_3125; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_gather_3124, &vector_imm_gather, FuncSignature::build()); + setArg(call_sew_3125, 0, reinterpret_cast(this)); + setRet(call_sew_3125, 0, ret_val_sew_3125); + setArg(call_vector_imm_gather_3124, 0, V); + setArg(call_vector_imm_gather_3124, 1, vector_imm_gather_3124_arg1); + setArg(call_vector_imm_gather_3124, 2, vector_imm_gather_3124_arg2); + setArg(call_vector_imm_gather_3124, 3, vector_imm_gather_3124_arg3); + setArg(call_vector_imm_gather_3124, 4, vm); + setArg(call_vector_imm_gather_3124, 5, vd); + setArg(call_vector_imm_gather_3124, 6, vs2); + setArg(call_vector_imm_gather_3124, 7, vector_imm_gather_3124_arg7); + setArg(call_vector_imm_gather_3124, 8, vector_imm_gather_3124_arg8); + auto tmp3126 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3126, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3126, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 685); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 686: VRGATHEREI16__VV */ + continuation_e __vrgatherei16__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrgatherei16.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRGATHEREI16__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 686); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3127; + x86::Gp ret_val_illegal_normal_3127 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3127, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3127, vs1==vd), vs2==vd); + setArg(call_illegal_normal_3127, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3127, 1, vd); + setArg(call_illegal_normal_3127, 2, vm); + setRet(call_illegal_normal_3127, 0, ret_val_illegal_normal_3127); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3129; + x86::Gp ret_val_sew_3129 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3129, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_gatherei16_3128; + auto vector_vector_gatherei16_3128_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_gatherei16_3128_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_gatherei16_3128_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_gatherei16_3128_arg8 = ret_val_sew_3129; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_gatherei16_3128, &vector_vector_gatherei16, FuncSignature::build()); + setArg(call_sew_3129, 0, reinterpret_cast(this)); + setRet(call_sew_3129, 0, ret_val_sew_3129); + setArg(call_vector_vector_gatherei16_3128, 0, V); + setArg(call_vector_vector_gatherei16_3128, 1, vector_vector_gatherei16_3128_arg1); + setArg(call_vector_vector_gatherei16_3128, 2, vector_vector_gatherei16_3128_arg2); + setArg(call_vector_vector_gatherei16_3128, 3, vector_vector_gatherei16_3128_arg3); + setArg(call_vector_vector_gatherei16_3128, 4, vm); + setArg(call_vector_vector_gatherei16_3128, 5, vd); + setArg(call_vector_vector_gatherei16_3128, 6, vs2); + setArg(call_vector_vector_gatherei16_3128, 7, vs1); + setArg(call_vector_vector_gatherei16_3128, 8, vector_vector_gatherei16_3128_arg8); + auto tmp3130 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3130, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3130, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 686); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 687: VCOMPRESS__VM */ + continuation_e __vcompress__vm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vcompress.vm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VCOMPRESS__VM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 687); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3131; + x86::Gp ret_val_illegal_vd_unmasked_3131 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3131, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0), vs1==vd), vs2==vd), ret_val_illegal_vd_unmasked_3131); + setArg(call_illegal_vd_unmasked_3131, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3131, 0, ret_val_illegal_vd_unmasked_3131); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3133; + x86::Gp ret_val_sew_3133 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3133, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_compress_3132; + auto vector_compress_3132_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_compress_3132_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_compress_3132_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_compress_3132_arg7 = ret_val_sew_3133; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_compress_3132, &vector_compress, FuncSignature::build()); + setArg(call_sew_3133, 0, reinterpret_cast(this)); + setRet(call_sew_3133, 0, ret_val_sew_3133); + setArg(call_vector_compress_3132, 0, V); + setArg(call_vector_compress_3132, 1, vector_compress_3132_arg1); + setArg(call_vector_compress_3132, 2, vector_compress_3132_arg2); + setArg(call_vector_compress_3132, 3, vector_compress_3132_arg3); + setArg(call_vector_compress_3132, 4, vd); + setArg(call_vector_compress_3132, 5, vs2); + setArg(call_vector_compress_3132, 6, vs1); + setArg(call_vector_compress_3132, 7, vector_compress_3132_arg7); + } + cc.bind(label_merge); + } + auto tmp3134 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3134, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3134, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 687); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 688: VMV1R__V */ + continuation_e __vmv1r__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv1r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV1R__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 688); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_vector_whole_move_3135; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_whole_move_3135, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3135, 0, V); + setArg(call_vector_whole_move_3135, 1, vd); + setArg(call_vector_whole_move_3135, 2, vs2); + setArg(call_vector_whole_move_3135, 3, 1); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 688); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 689: VMV2R__V */ + continuation_e __vmv2r__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv2r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV2R__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 689); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(vd%2||vs2%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_vector_whole_move_3136; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_whole_move_3136, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3136, 0, V); + setArg(call_vector_whole_move_3136, 1, vd); + setArg(call_vector_whole_move_3136, 2, vs2); + setArg(call_vector_whole_move_3136, 3, 2); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 689); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 690: VMV4R__V */ + continuation_e __vmv4r__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv4r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV4R__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 690); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(vd%4||vs2%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_vector_whole_move_3137; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_whole_move_3137, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3137, 0, V); + setArg(call_vector_whole_move_3137, 1, vd); + setArg(call_vector_whole_move_3137, 2, vs2); + setArg(call_vector_whole_move_3137, 3, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 690); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 691: VMV8R__V */ + continuation_e __vmv8r__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv8r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV8R__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 691); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(vd%8||vs2%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_vector_whole_move_3138; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_whole_move_3138, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3138, 0, V); + setArg(call_vector_whole_move_3138, 1, vd); + setArg(call_vector_whole_move_3138, 2, vs2); + setArg(call_vector_whole_move_3138, 3, 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 691); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 692: VFMV__S__F */ + continuation_e __vfmv__s__f(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vfmv.s.f"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMV__S__F_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 692); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3139; + x86::Gp ret_val_get_sew_pow_3139 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3139, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3140 = get_reg(cc, 8, false); + mov(cc, tmp3140, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3140, (ret_val_get_sew_pow_3139))), 8, false), ~ 1); + setArg(call_get_sew_pow_3139, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3139, 0, ret_val_get_sew_pow_3139); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3141; + auto illegal_fp_vd_unmasked_3141_arg0 = SEW; + auto illegal_fp_vd_unmasked_3141_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3141 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3141, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3141; + setArg(call_illegal_fp_vd_unmasked_3141, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3141, 1, illegal_fp_vd_unmasked_3141_arg0); + setArg(call_illegal_fp_vd_unmasked_3141, 2, illegal_fp_vd_unmasked_3141_arg1); + setRet(call_illegal_fp_vd_unmasked_3141, 0, ret_val_illegal_fp_vd_unmasked_3141); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3143; + x86::Gp ret_val_sew_3143 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3143, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_to_vector_3142; + auto scalar_to_vector_3142_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_to_vector_3142_arg3 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false), 32, false); + auto scalar_to_vector_3142_arg4 = ret_val_sew_3143; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_scalar_to_vector_3142, &scalar_to_vector, FuncSignature::build()); + setArg(call_sew_3143, 0, reinterpret_cast(this)); + setRet(call_sew_3143, 0, ret_val_sew_3143); + setArg(call_scalar_to_vector_3142, 0, V); + setArg(call_scalar_to_vector_3142, 1, scalar_to_vector_3142_arg1); + setArg(call_scalar_to_vector_3142, 2, vd); + setArg(call_scalar_to_vector_3142, 3, scalar_to_vector_3142_arg3); + setArg(call_scalar_to_vector_3142, 4, scalar_to_vector_3142_arg4); + auto tmp3144 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3144, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3144, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 692); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 693: VFMV__F__S */ + continuation_e __vfmv__f__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}", fmt::arg("mnemonic", "vfmv.f.s"), + fmt::arg("rd", fname(rd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMV__F__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 693); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3145; + x86::Gp ret_val_get_sew_pow_3145 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3145, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3146 = get_reg(cc, 8, false); + mov(cc, tmp3146, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3146, (ret_val_get_sew_pow_3145))), 8, false), ~ 1); + setArg(call_get_sew_pow_3145, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3145, 0, ret_val_get_sew_pow_3145); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3147; + auto illegal_fp_vd_unmasked_3147_arg0 = SEW; + auto illegal_fp_vd_unmasked_3147_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3147 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3147, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_vd_unmasked_3147, gen_operation(cc, gtu, SEW, static_cast(traits::FLEN))); + setArg(call_illegal_fp_vd_unmasked_3147, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3147, 1, illegal_fp_vd_unmasked_3147_arg0); + setArg(call_illegal_fp_vd_unmasked_3147, 2, illegal_fp_vd_unmasked_3147_arg1); + setRet(call_illegal_fp_vd_unmasked_3147, 0, ret_val_illegal_fp_vd_unmasked_3147); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3149; + x86::Gp ret_val_sew_3149 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3149, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_scalar_from_vector_3148; + auto fp_scalar_from_vector_3148_arg1 = load_reg_from_mem(jh, traits::vtype); + auto fp_scalar_from_vector_3148_arg3 = ret_val_sew_3149; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_fp_scalar_from_vector_3148 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fp_scalar_from_vector_3148, &fp_scalar_from_vector, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_fp_scalar_from_vector_3148); + setArg(call_sew_3149, 0, reinterpret_cast(this)); + setRet(call_sew_3149, 0, ret_val_sew_3149); + setArg(call_fp_scalar_from_vector_3148, 0, V); + setArg(call_fp_scalar_from_vector_3148, 1, fp_scalar_from_vector_3148_arg1); + setArg(call_fp_scalar_from_vector_3148, 2, vs2); + setArg(call_fp_scalar_from_vector_3148, 3, fp_scalar_from_vector_3148_arg3); + setRet(call_fp_scalar_from_vector_3148, 0, ret_val_fp_scalar_from_vector_3148); + auto tmp3150 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3150, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3150, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 693); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 694: VFSLIDE1UP__VF */ + continuation_e __vfslide1up__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfslide1up.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSLIDE1UP__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 694); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3151; + x86::Gp ret_val_get_sew_pow_3151 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3151, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3152 = get_reg(cc, 8, false); + mov(cc, tmp3152, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3152, (ret_val_get_sew_pow_3151))), 8, false), ~ 1); + setArg(call_get_sew_pow_3151, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3151, 0, ret_val_get_sew_pow_3151); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3153; + auto illegal_fp_normal_3153_arg2 = SEW; + auto illegal_fp_normal_3153_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3153 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3153, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3153; + setArg(call_illegal_fp_normal_3153, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3153, 1, vd); + setArg(call_illegal_fp_normal_3153, 2, vm); + setArg(call_illegal_fp_normal_3153, 3, illegal_fp_normal_3153_arg2); + setArg(call_illegal_fp_normal_3153, 4, illegal_fp_normal_3153_arg3); + setRet(call_illegal_fp_normal_3153, 0, ret_val_illegal_fp_normal_3153); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3155; + x86::Gp ret_val_sew_3155 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3155, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_slide1up_3154; + auto fp_vector_slide1up_3154_arg1 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_slide1up_3154_arg2 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_slide1up_3154_arg3 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_slide1up_3154_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + auto fp_vector_slide1up_3154_arg8 = ret_val_sew_3155; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_slide1up_3154, &fp_vector_slide1up, FuncSignature::build()); + setArg(call_sew_3155, 0, reinterpret_cast(this)); + setRet(call_sew_3155, 0, ret_val_sew_3155); + setArg(call_fp_vector_slide1up_3154, 0, V); + setArg(call_fp_vector_slide1up_3154, 1, fp_vector_slide1up_3154_arg1); + setArg(call_fp_vector_slide1up_3154, 2, fp_vector_slide1up_3154_arg2); + setArg(call_fp_vector_slide1up_3154, 3, fp_vector_slide1up_3154_arg3); + setArg(call_fp_vector_slide1up_3154, 4, vm); + setArg(call_fp_vector_slide1up_3154, 5, vd); + setArg(call_fp_vector_slide1up_3154, 6, vs2); + setArg(call_fp_vector_slide1up_3154, 7, fp_vector_slide1up_3154_arg7); + setArg(call_fp_vector_slide1up_3154, 8, fp_vector_slide1up_3154_arg8); + } + cc.bind(label_merge); + } + auto tmp3156 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3156, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3156, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 694); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 695: VFSLIDE1DOWN__VF */ + continuation_e __vfslide1down__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfslide1down.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSLIDE1DOWN__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 695); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3157; + x86::Gp ret_val_get_sew_pow_3157 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3157, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3158 = get_reg(cc, 8, false); + mov(cc, tmp3158, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3158, (ret_val_get_sew_pow_3157))), 8, false), ~ 1); + setArg(call_get_sew_pow_3157, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3157, 0, ret_val_get_sew_pow_3157); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3159; + auto illegal_fp_normal_3159_arg2 = SEW; + auto illegal_fp_normal_3159_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3159 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3159, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3159; + setArg(call_illegal_fp_normal_3159, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3159, 1, vd); + setArg(call_illegal_fp_normal_3159, 2, vm); + setArg(call_illegal_fp_normal_3159, 3, illegal_fp_normal_3159_arg2); + setArg(call_illegal_fp_normal_3159, 4, illegal_fp_normal_3159_arg3); + setRet(call_illegal_fp_normal_3159, 0, ret_val_illegal_fp_normal_3159); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3161; + x86::Gp ret_val_sew_3161 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3161, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_slide1down_3160; + auto fp_vector_slide1down_3160_arg1 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_slide1down_3160_arg2 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_slide1down_3160_arg3 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_slide1down_3160_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + auto fp_vector_slide1down_3160_arg8 = ret_val_sew_3161; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_slide1down_3160, &fp_vector_slide1down, FuncSignature::build()); + setArg(call_sew_3161, 0, reinterpret_cast(this)); + setRet(call_sew_3161, 0, ret_val_sew_3161); + setArg(call_fp_vector_slide1down_3160, 0, V); + setArg(call_fp_vector_slide1down_3160, 1, fp_vector_slide1down_3160_arg1); + setArg(call_fp_vector_slide1down_3160, 2, fp_vector_slide1down_3160_arg2); + setArg(call_fp_vector_slide1down_3160, 3, fp_vector_slide1down_3160_arg3); + setArg(call_fp_vector_slide1down_3160, 4, vm); + setArg(call_fp_vector_slide1down_3160, 5, vd); + setArg(call_fp_vector_slide1down_3160, 6, vs2); + setArg(call_fp_vector_slide1down_3160, 7, fp_vector_slide1down_3160_arg7); + setArg(call_fp_vector_slide1down_3160, 8, fp_vector_slide1down_3160_arg8); + } + cc.bind(label_merge); + } + auto tmp3162 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3162, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3162, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 695); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 696: VFADD__VF */ + continuation_e __vfadd__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFADD__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 696); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3163; + x86::Gp ret_val_get_sew_pow_3163 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3163, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3164 = get_reg(cc, 8, false); + mov(cc, tmp3164, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3164, (ret_val_get_sew_pow_3163))), 8, false), ~ 1); + setArg(call_get_sew_pow_3163, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3163, 0, ret_val_get_sew_pow_3163); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3165; + auto illegal_fp_normal_3165_arg2 = SEW; + auto illegal_fp_normal_3165_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3165 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3165, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3165; + setArg(call_illegal_fp_normal_3165, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3165, 1, vd); + setArg(call_illegal_fp_normal_3165, 2, vm); + setArg(call_illegal_fp_normal_3165, 3, illegal_fp_normal_3165_arg2); + setArg(call_illegal_fp_normal_3165, 4, illegal_fp_normal_3165_arg3); + setRet(call_illegal_fp_normal_3165, 0, ret_val_illegal_fp_normal_3165); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3167; + x86::Gp ret_val_sew_3167 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3167, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3166; + auto fp_vector_imm_op_3166_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3166_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3166_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3166_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3166_arg10 = rm; + auto fp_vector_imm_op_3166_arg11 = ret_val_sew_3167; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3166, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3167, 0, reinterpret_cast(this)); + setRet(call_sew_3167, 0, ret_val_sew_3167); + setArg(call_fp_vector_imm_op_3166, 0, V); + setArg(call_fp_vector_imm_op_3166, 1, 0); + setArg(call_fp_vector_imm_op_3166, 2, 5); + setArg(call_fp_vector_imm_op_3166, 3, fp_vector_imm_op_3166_arg3); + setArg(call_fp_vector_imm_op_3166, 4, fp_vector_imm_op_3166_arg4); + setArg(call_fp_vector_imm_op_3166, 5, fp_vector_imm_op_3166_arg5); + setArg(call_fp_vector_imm_op_3166, 6, vm); + setArg(call_fp_vector_imm_op_3166, 7, vd); + setArg(call_fp_vector_imm_op_3166, 8, vs2); + setArg(call_fp_vector_imm_op_3166, 9, fp_vector_imm_op_3166_arg9); + setArg(call_fp_vector_imm_op_3166, 10, fp_vector_imm_op_3166_arg10); + setArg(call_fp_vector_imm_op_3166, 11, fp_vector_imm_op_3166_arg11); + InvokeNode* call_fget_flags_3168; + x86::Gp ret_val_fget_flags_3168 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3168, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3168; + setRet(call_fget_flags_3168, 0, ret_val_fget_flags_3168); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3169 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3169, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3169, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 696); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 697: VFADD__VV */ + continuation_e __vfadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 697); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3170; + x86::Gp ret_val_get_sew_pow_3170 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3170, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3171 = get_reg(cc, 8, false); + mov(cc, tmp3171, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3171, (ret_val_get_sew_pow_3170))), 8, false), ~ 1); + setArg(call_get_sew_pow_3170, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3170, 0, ret_val_get_sew_pow_3170); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3172; + auto illegal_fp_normal_3172_arg2 = SEW; + auto illegal_fp_normal_3172_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3172 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3172, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3172; + setArg(call_illegal_fp_normal_3172, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3172, 1, vd); + setArg(call_illegal_fp_normal_3172, 2, vm); + setArg(call_illegal_fp_normal_3172, 3, illegal_fp_normal_3172_arg2); + setArg(call_illegal_fp_normal_3172, 4, illegal_fp_normal_3172_arg3); + setRet(call_illegal_fp_normal_3172, 0, ret_val_illegal_fp_normal_3172); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3174; + x86::Gp ret_val_sew_3174 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3174, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3173; + auto fp_vector_vector_op_3173_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3173_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3173_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3173_arg10 = rm; + auto fp_vector_vector_op_3173_arg11 = ret_val_sew_3174; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3173, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3174, 0, reinterpret_cast(this)); + setRet(call_sew_3174, 0, ret_val_sew_3174); + setArg(call_fp_vector_vector_op_3173, 0, V); + setArg(call_fp_vector_vector_op_3173, 1, 0); + setArg(call_fp_vector_vector_op_3173, 2, 1); + setArg(call_fp_vector_vector_op_3173, 3, fp_vector_vector_op_3173_arg3); + setArg(call_fp_vector_vector_op_3173, 4, fp_vector_vector_op_3173_arg4); + setArg(call_fp_vector_vector_op_3173, 5, fp_vector_vector_op_3173_arg5); + setArg(call_fp_vector_vector_op_3173, 6, vm); + setArg(call_fp_vector_vector_op_3173, 7, vd); + setArg(call_fp_vector_vector_op_3173, 8, vs2); + setArg(call_fp_vector_vector_op_3173, 9, vs1); + setArg(call_fp_vector_vector_op_3173, 10, fp_vector_vector_op_3173_arg10); + setArg(call_fp_vector_vector_op_3173, 11, fp_vector_vector_op_3173_arg11); + InvokeNode* call_fget_flags_3175; + x86::Gp ret_val_fget_flags_3175 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3175, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3175; + setRet(call_fget_flags_3175, 0, ret_val_fget_flags_3175); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3176 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3176, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3176, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 697); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 698: VFSUB__VF */ + continuation_e __vfsub__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSUB__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 698); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3177; + x86::Gp ret_val_get_sew_pow_3177 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3177, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3178 = get_reg(cc, 8, false); + mov(cc, tmp3178, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3178, (ret_val_get_sew_pow_3177))), 8, false), ~ 1); + setArg(call_get_sew_pow_3177, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3177, 0, ret_val_get_sew_pow_3177); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3179; + auto illegal_fp_normal_3179_arg2 = SEW; + auto illegal_fp_normal_3179_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3179 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3179, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3179; + setArg(call_illegal_fp_normal_3179, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3179, 1, vd); + setArg(call_illegal_fp_normal_3179, 2, vm); + setArg(call_illegal_fp_normal_3179, 3, illegal_fp_normal_3179_arg2); + setArg(call_illegal_fp_normal_3179, 4, illegal_fp_normal_3179_arg3); + setRet(call_illegal_fp_normal_3179, 0, ret_val_illegal_fp_normal_3179); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3181; + x86::Gp ret_val_sew_3181 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3181, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3180; + auto fp_vector_imm_op_3180_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3180_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3180_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3180_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3180_arg10 = rm; + auto fp_vector_imm_op_3180_arg11 = ret_val_sew_3181; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3180, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3181, 0, reinterpret_cast(this)); + setRet(call_sew_3181, 0, ret_val_sew_3181); + setArg(call_fp_vector_imm_op_3180, 0, V); + setArg(call_fp_vector_imm_op_3180, 1, 2); + setArg(call_fp_vector_imm_op_3180, 2, 5); + setArg(call_fp_vector_imm_op_3180, 3, fp_vector_imm_op_3180_arg3); + setArg(call_fp_vector_imm_op_3180, 4, fp_vector_imm_op_3180_arg4); + setArg(call_fp_vector_imm_op_3180, 5, fp_vector_imm_op_3180_arg5); + setArg(call_fp_vector_imm_op_3180, 6, vm); + setArg(call_fp_vector_imm_op_3180, 7, vd); + setArg(call_fp_vector_imm_op_3180, 8, vs2); + setArg(call_fp_vector_imm_op_3180, 9, fp_vector_imm_op_3180_arg9); + setArg(call_fp_vector_imm_op_3180, 10, fp_vector_imm_op_3180_arg10); + setArg(call_fp_vector_imm_op_3180, 11, fp_vector_imm_op_3180_arg11); + InvokeNode* call_fget_flags_3182; + x86::Gp ret_val_fget_flags_3182 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3182, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3182; + setRet(call_fget_flags_3182, 0, ret_val_fget_flags_3182); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3183 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3183, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3183, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 698); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 699: VFSUB__VV */ + continuation_e __vfsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 699); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3184; + x86::Gp ret_val_get_sew_pow_3184 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3184, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3185 = get_reg(cc, 8, false); + mov(cc, tmp3185, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3185, (ret_val_get_sew_pow_3184))), 8, false), ~ 1); + setArg(call_get_sew_pow_3184, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3184, 0, ret_val_get_sew_pow_3184); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3186; + auto illegal_fp_normal_3186_arg2 = SEW; + auto illegal_fp_normal_3186_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3186 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3186, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3186; + setArg(call_illegal_fp_normal_3186, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3186, 1, vd); + setArg(call_illegal_fp_normal_3186, 2, vm); + setArg(call_illegal_fp_normal_3186, 3, illegal_fp_normal_3186_arg2); + setArg(call_illegal_fp_normal_3186, 4, illegal_fp_normal_3186_arg3); + setRet(call_illegal_fp_normal_3186, 0, ret_val_illegal_fp_normal_3186); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3188; + x86::Gp ret_val_sew_3188 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3188, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3187; + auto fp_vector_vector_op_3187_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3187_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3187_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3187_arg10 = rm; + auto fp_vector_vector_op_3187_arg11 = ret_val_sew_3188; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3187, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3188, 0, reinterpret_cast(this)); + setRet(call_sew_3188, 0, ret_val_sew_3188); + setArg(call_fp_vector_vector_op_3187, 0, V); + setArg(call_fp_vector_vector_op_3187, 1, 2); + setArg(call_fp_vector_vector_op_3187, 2, 1); + setArg(call_fp_vector_vector_op_3187, 3, fp_vector_vector_op_3187_arg3); + setArg(call_fp_vector_vector_op_3187, 4, fp_vector_vector_op_3187_arg4); + setArg(call_fp_vector_vector_op_3187, 5, fp_vector_vector_op_3187_arg5); + setArg(call_fp_vector_vector_op_3187, 6, vm); + setArg(call_fp_vector_vector_op_3187, 7, vd); + setArg(call_fp_vector_vector_op_3187, 8, vs2); + setArg(call_fp_vector_vector_op_3187, 9, vs1); + setArg(call_fp_vector_vector_op_3187, 10, fp_vector_vector_op_3187_arg10); + setArg(call_fp_vector_vector_op_3187, 11, fp_vector_vector_op_3187_arg11); + InvokeNode* call_fget_flags_3189; + x86::Gp ret_val_fget_flags_3189 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3189, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3189; + setRet(call_fget_flags_3189, 0, ret_val_fget_flags_3189); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3190 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3190, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3190, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 699); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 700: VFRSUB__VF */ + continuation_e __vfrsub__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfrsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFRSUB__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 700); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3191; + x86::Gp ret_val_get_sew_pow_3191 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3191, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3192 = get_reg(cc, 8, false); + mov(cc, tmp3192, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3192, (ret_val_get_sew_pow_3191))), 8, false), ~ 1); + setArg(call_get_sew_pow_3191, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3191, 0, ret_val_get_sew_pow_3191); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3193; + auto illegal_fp_normal_3193_arg2 = SEW; + auto illegal_fp_normal_3193_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3193 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3193, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3193; + setArg(call_illegal_fp_normal_3193, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3193, 1, vd); + setArg(call_illegal_fp_normal_3193, 2, vm); + setArg(call_illegal_fp_normal_3193, 3, illegal_fp_normal_3193_arg2); + setArg(call_illegal_fp_normal_3193, 4, illegal_fp_normal_3193_arg3); + setRet(call_illegal_fp_normal_3193, 0, ret_val_illegal_fp_normal_3193); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3195; + x86::Gp ret_val_sew_3195 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3195, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3194; + auto fp_vector_imm_op_3194_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3194_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3194_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3194_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3194_arg10 = rm; + auto fp_vector_imm_op_3194_arg11 = ret_val_sew_3195; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3194, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3195, 0, reinterpret_cast(this)); + setRet(call_sew_3195, 0, ret_val_sew_3195); + setArg(call_fp_vector_imm_op_3194, 0, V); + setArg(call_fp_vector_imm_op_3194, 1, 39); + setArg(call_fp_vector_imm_op_3194, 2, 5); + setArg(call_fp_vector_imm_op_3194, 3, fp_vector_imm_op_3194_arg3); + setArg(call_fp_vector_imm_op_3194, 4, fp_vector_imm_op_3194_arg4); + setArg(call_fp_vector_imm_op_3194, 5, fp_vector_imm_op_3194_arg5); + setArg(call_fp_vector_imm_op_3194, 6, vm); + setArg(call_fp_vector_imm_op_3194, 7, vd); + setArg(call_fp_vector_imm_op_3194, 8, vs2); + setArg(call_fp_vector_imm_op_3194, 9, fp_vector_imm_op_3194_arg9); + setArg(call_fp_vector_imm_op_3194, 10, fp_vector_imm_op_3194_arg10); + setArg(call_fp_vector_imm_op_3194, 11, fp_vector_imm_op_3194_arg11); + InvokeNode* call_fget_flags_3196; + x86::Gp ret_val_fget_flags_3196 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3196, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3196; + setRet(call_fget_flags_3196, 0, ret_val_fget_flags_3196); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3197 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3197, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3197, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 700); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 701: VFWADD__VF */ + continuation_e __vfwadd__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWADD__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 701); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3198; + x86::Gp ret_val_get_sew_pow_3198 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3198, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3199 = get_reg(cc, 8, false); + mov(cc, tmp3199, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3199, (ret_val_get_sew_pow_3198))), 8, false), ~ 1); + setArg(call_get_sew_pow_3198, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3198, 0, ret_val_get_sew_pow_3198); + InvokeNode* call_get_lmul_pow_3200; + x86::Gp ret_val_get_lmul_pow_3200 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3200, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3200; + setArg(call_get_lmul_pow_3200, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3200, 0, ret_val_get_lmul_pow_3200); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3201; + auto illegal_fp_variable_width_3201_arg2 = SEW; + auto illegal_fp_variable_width_3201_arg3 = rm; + auto illegal_fp_variable_width_3201_arg4 = SEW_widen; + auto illegal_fp_variable_width_3201_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3201 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3201, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3202; + auto valid_reg_overlap_3202_arg2 = LMUL_pow; + auto valid_reg_overlap_3202_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3202 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3202, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3201, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3202)); + setArg(call_illegal_fp_variable_width_3201, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3201, 1, vd); + setArg(call_illegal_fp_variable_width_3201, 2, vm); + setArg(call_illegal_fp_variable_width_3201, 3, illegal_fp_variable_width_3201_arg2); + setArg(call_illegal_fp_variable_width_3201, 4, illegal_fp_variable_width_3201_arg3); + setArg(call_illegal_fp_variable_width_3201, 5, illegal_fp_variable_width_3201_arg4); + setArg(call_illegal_fp_variable_width_3201, 6, illegal_fp_variable_width_3201_arg5); + setRet(call_illegal_fp_variable_width_3201, 0, ret_val_illegal_fp_variable_width_3201); + setArg(call_valid_reg_overlap_3202, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3202, 1, vs2); + setArg(call_valid_reg_overlap_3202, 2, vd); + setArg(call_valid_reg_overlap_3202, 3, valid_reg_overlap_3202_arg2); + setArg(call_valid_reg_overlap_3202, 4, valid_reg_overlap_3202_arg3); + setRet(call_valid_reg_overlap_3202, 0, ret_val_valid_reg_overlap_3202); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3204; + x86::Gp ret_val_sew_3204 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3204, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3203; + auto fp_vector_imm_wv_3203_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3203_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3203_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3203_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_wv_3203_arg10 = rm; + auto fp_vector_imm_wv_3203_arg11 = ret_val_sew_3204; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3203, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3204, 0, reinterpret_cast(this)); + setRet(call_sew_3204, 0, ret_val_sew_3204); + setArg(call_fp_vector_imm_wv_3203, 0, V); + setArg(call_fp_vector_imm_wv_3203, 1, 48); + setArg(call_fp_vector_imm_wv_3203, 2, 5); + setArg(call_fp_vector_imm_wv_3203, 3, fp_vector_imm_wv_3203_arg3); + setArg(call_fp_vector_imm_wv_3203, 4, fp_vector_imm_wv_3203_arg4); + setArg(call_fp_vector_imm_wv_3203, 5, fp_vector_imm_wv_3203_arg5); + setArg(call_fp_vector_imm_wv_3203, 6, vm); + setArg(call_fp_vector_imm_wv_3203, 7, vd); + setArg(call_fp_vector_imm_wv_3203, 8, vs2); + setArg(call_fp_vector_imm_wv_3203, 9, fp_vector_imm_wv_3203_arg9); + setArg(call_fp_vector_imm_wv_3203, 10, fp_vector_imm_wv_3203_arg10); + setArg(call_fp_vector_imm_wv_3203, 11, fp_vector_imm_wv_3203_arg11); + InvokeNode* call_fget_flags_3205; + x86::Gp ret_val_fget_flags_3205 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3205, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3205; + setRet(call_fget_flags_3205, 0, ret_val_fget_flags_3205); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3206 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3206, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3206, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 701); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 702: VFWADD__VV */ + continuation_e __vfwadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 702); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3207; + x86::Gp ret_val_get_sew_pow_3207 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3207, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3208 = get_reg(cc, 8, false); + mov(cc, tmp3208, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3208, (ret_val_get_sew_pow_3207))), 8, false), ~ 1); + setArg(call_get_sew_pow_3207, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3207, 0, ret_val_get_sew_pow_3207); + InvokeNode* call_get_lmul_pow_3209; + x86::Gp ret_val_get_lmul_pow_3209 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3209, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3209; + setArg(call_get_lmul_pow_3209, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3209, 0, ret_val_get_lmul_pow_3209); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3210; + auto illegal_fp_variable_width_3210_arg2 = SEW; + auto illegal_fp_variable_width_3210_arg3 = rm; + auto illegal_fp_variable_width_3210_arg4 = SEW_widen; + auto illegal_fp_variable_width_3210_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3210 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3210, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3211; + auto valid_reg_overlap_3211_arg2 = LMUL_pow; + auto valid_reg_overlap_3211_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3211 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3211, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3212; + auto valid_reg_overlap_3212_arg2 = LMUL_pow; + auto valid_reg_overlap_3212_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3212 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3212, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3210, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3211)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3212)); + setArg(call_illegal_fp_variable_width_3210, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3210, 1, vd); + setArg(call_illegal_fp_variable_width_3210, 2, vm); + setArg(call_illegal_fp_variable_width_3210, 3, illegal_fp_variable_width_3210_arg2); + setArg(call_illegal_fp_variable_width_3210, 4, illegal_fp_variable_width_3210_arg3); + setArg(call_illegal_fp_variable_width_3210, 5, illegal_fp_variable_width_3210_arg4); + setArg(call_illegal_fp_variable_width_3210, 6, illegal_fp_variable_width_3210_arg5); + setRet(call_illegal_fp_variable_width_3210, 0, ret_val_illegal_fp_variable_width_3210); + setArg(call_valid_reg_overlap_3211, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3211, 1, vs1); + setArg(call_valid_reg_overlap_3211, 2, vd); + setArg(call_valid_reg_overlap_3211, 3, valid_reg_overlap_3211_arg2); + setArg(call_valid_reg_overlap_3211, 4, valid_reg_overlap_3211_arg3); + setRet(call_valid_reg_overlap_3211, 0, ret_val_valid_reg_overlap_3211); + setArg(call_valid_reg_overlap_3212, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3212, 1, vs2); + setArg(call_valid_reg_overlap_3212, 2, vd); + setArg(call_valid_reg_overlap_3212, 3, valid_reg_overlap_3212_arg2); + setArg(call_valid_reg_overlap_3212, 4, valid_reg_overlap_3212_arg3); + setRet(call_valid_reg_overlap_3212, 0, ret_val_valid_reg_overlap_3212); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3214; + x86::Gp ret_val_sew_3214 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3214, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3213; + auto fp_vector_vector_wv_3213_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3213_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3213_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3213_arg10 = rm; + auto fp_vector_vector_wv_3213_arg11 = ret_val_sew_3214; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3213, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3214, 0, reinterpret_cast(this)); + setRet(call_sew_3214, 0, ret_val_sew_3214); + setArg(call_fp_vector_vector_wv_3213, 0, V); + setArg(call_fp_vector_vector_wv_3213, 1, 48); + setArg(call_fp_vector_vector_wv_3213, 2, 1); + setArg(call_fp_vector_vector_wv_3213, 3, fp_vector_vector_wv_3213_arg3); + setArg(call_fp_vector_vector_wv_3213, 4, fp_vector_vector_wv_3213_arg4); + setArg(call_fp_vector_vector_wv_3213, 5, fp_vector_vector_wv_3213_arg5); + setArg(call_fp_vector_vector_wv_3213, 6, vm); + setArg(call_fp_vector_vector_wv_3213, 7, vd); + setArg(call_fp_vector_vector_wv_3213, 8, vs2); + setArg(call_fp_vector_vector_wv_3213, 9, vs1); + setArg(call_fp_vector_vector_wv_3213, 10, fp_vector_vector_wv_3213_arg10); + setArg(call_fp_vector_vector_wv_3213, 11, fp_vector_vector_wv_3213_arg11); + InvokeNode* call_fget_flags_3215; + x86::Gp ret_val_fget_flags_3215 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3215, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3215; + setRet(call_fget_flags_3215, 0, ret_val_fget_flags_3215); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3216 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3216, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3216, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 702); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 703: VFWSUB__VF */ + continuation_e __vfwsub__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWSUB__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 703); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3217; + x86::Gp ret_val_get_sew_pow_3217 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3217, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3218 = get_reg(cc, 8, false); + mov(cc, tmp3218, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3218, (ret_val_get_sew_pow_3217))), 8, false), ~ 1); + setArg(call_get_sew_pow_3217, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3217, 0, ret_val_get_sew_pow_3217); + InvokeNode* call_get_lmul_pow_3219; + x86::Gp ret_val_get_lmul_pow_3219 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3219, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3219; + setArg(call_get_lmul_pow_3219, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3219, 0, ret_val_get_lmul_pow_3219); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3220; + auto illegal_fp_variable_width_3220_arg2 = SEW; + auto illegal_fp_variable_width_3220_arg3 = rm; + auto illegal_fp_variable_width_3220_arg4 = SEW_widen; + auto illegal_fp_variable_width_3220_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3220 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3220, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3221; + auto valid_reg_overlap_3221_arg2 = LMUL_pow; + auto valid_reg_overlap_3221_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3221 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3221, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3220, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3221)); + setArg(call_illegal_fp_variable_width_3220, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3220, 1, vd); + setArg(call_illegal_fp_variable_width_3220, 2, vm); + setArg(call_illegal_fp_variable_width_3220, 3, illegal_fp_variable_width_3220_arg2); + setArg(call_illegal_fp_variable_width_3220, 4, illegal_fp_variable_width_3220_arg3); + setArg(call_illegal_fp_variable_width_3220, 5, illegal_fp_variable_width_3220_arg4); + setArg(call_illegal_fp_variable_width_3220, 6, illegal_fp_variable_width_3220_arg5); + setRet(call_illegal_fp_variable_width_3220, 0, ret_val_illegal_fp_variable_width_3220); + setArg(call_valid_reg_overlap_3221, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3221, 1, vs2); + setArg(call_valid_reg_overlap_3221, 2, vd); + setArg(call_valid_reg_overlap_3221, 3, valid_reg_overlap_3221_arg2); + setArg(call_valid_reg_overlap_3221, 4, valid_reg_overlap_3221_arg3); + setRet(call_valid_reg_overlap_3221, 0, ret_val_valid_reg_overlap_3221); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3223; + x86::Gp ret_val_sew_3223 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3223, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3222; + auto fp_vector_imm_wv_3222_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3222_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3222_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3222_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_wv_3222_arg10 = rm; + auto fp_vector_imm_wv_3222_arg11 = ret_val_sew_3223; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3222, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3223, 0, reinterpret_cast(this)); + setRet(call_sew_3223, 0, ret_val_sew_3223); + setArg(call_fp_vector_imm_wv_3222, 0, V); + setArg(call_fp_vector_imm_wv_3222, 1, 50); + setArg(call_fp_vector_imm_wv_3222, 2, 5); + setArg(call_fp_vector_imm_wv_3222, 3, fp_vector_imm_wv_3222_arg3); + setArg(call_fp_vector_imm_wv_3222, 4, fp_vector_imm_wv_3222_arg4); + setArg(call_fp_vector_imm_wv_3222, 5, fp_vector_imm_wv_3222_arg5); + setArg(call_fp_vector_imm_wv_3222, 6, vm); + setArg(call_fp_vector_imm_wv_3222, 7, vd); + setArg(call_fp_vector_imm_wv_3222, 8, vs2); + setArg(call_fp_vector_imm_wv_3222, 9, fp_vector_imm_wv_3222_arg9); + setArg(call_fp_vector_imm_wv_3222, 10, fp_vector_imm_wv_3222_arg10); + setArg(call_fp_vector_imm_wv_3222, 11, fp_vector_imm_wv_3222_arg11); + InvokeNode* call_fget_flags_3224; + x86::Gp ret_val_fget_flags_3224 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3224, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3224; + setRet(call_fget_flags_3224, 0, ret_val_fget_flags_3224); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3225 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3225, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3225, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 703); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 704: VFWSUB__VV */ + continuation_e __vfwsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 704); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3226; + x86::Gp ret_val_get_sew_pow_3226 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3226, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3227 = get_reg(cc, 8, false); + mov(cc, tmp3227, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3227, (ret_val_get_sew_pow_3226))), 8, false), ~ 1); + setArg(call_get_sew_pow_3226, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3226, 0, ret_val_get_sew_pow_3226); + InvokeNode* call_get_lmul_pow_3228; + x86::Gp ret_val_get_lmul_pow_3228 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3228, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3228; + setArg(call_get_lmul_pow_3228, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3228, 0, ret_val_get_lmul_pow_3228); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3229; + auto illegal_fp_variable_width_3229_arg2 = SEW; + auto illegal_fp_variable_width_3229_arg3 = rm; + auto illegal_fp_variable_width_3229_arg4 = SEW_widen; + auto illegal_fp_variable_width_3229_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3229 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3229, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3230; + auto valid_reg_overlap_3230_arg2 = LMUL_pow; + auto valid_reg_overlap_3230_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3230 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3230, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3231; + auto valid_reg_overlap_3231_arg2 = LMUL_pow; + auto valid_reg_overlap_3231_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3231 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3231, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3229, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3230)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3231)); + setArg(call_illegal_fp_variable_width_3229, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3229, 1, vd); + setArg(call_illegal_fp_variable_width_3229, 2, vm); + setArg(call_illegal_fp_variable_width_3229, 3, illegal_fp_variable_width_3229_arg2); + setArg(call_illegal_fp_variable_width_3229, 4, illegal_fp_variable_width_3229_arg3); + setArg(call_illegal_fp_variable_width_3229, 5, illegal_fp_variable_width_3229_arg4); + setArg(call_illegal_fp_variable_width_3229, 6, illegal_fp_variable_width_3229_arg5); + setRet(call_illegal_fp_variable_width_3229, 0, ret_val_illegal_fp_variable_width_3229); + setArg(call_valid_reg_overlap_3230, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3230, 1, vs1); + setArg(call_valid_reg_overlap_3230, 2, vd); + setArg(call_valid_reg_overlap_3230, 3, valid_reg_overlap_3230_arg2); + setArg(call_valid_reg_overlap_3230, 4, valid_reg_overlap_3230_arg3); + setRet(call_valid_reg_overlap_3230, 0, ret_val_valid_reg_overlap_3230); + setArg(call_valid_reg_overlap_3231, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3231, 1, vs2); + setArg(call_valid_reg_overlap_3231, 2, vd); + setArg(call_valid_reg_overlap_3231, 3, valid_reg_overlap_3231_arg2); + setArg(call_valid_reg_overlap_3231, 4, valid_reg_overlap_3231_arg3); + setRet(call_valid_reg_overlap_3231, 0, ret_val_valid_reg_overlap_3231); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3233; + x86::Gp ret_val_sew_3233 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3233, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3232; + auto fp_vector_vector_wv_3232_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3232_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3232_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3232_arg10 = rm; + auto fp_vector_vector_wv_3232_arg11 = ret_val_sew_3233; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3232, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3233, 0, reinterpret_cast(this)); + setRet(call_sew_3233, 0, ret_val_sew_3233); + setArg(call_fp_vector_vector_wv_3232, 0, V); + setArg(call_fp_vector_vector_wv_3232, 1, 50); + setArg(call_fp_vector_vector_wv_3232, 2, 1); + setArg(call_fp_vector_vector_wv_3232, 3, fp_vector_vector_wv_3232_arg3); + setArg(call_fp_vector_vector_wv_3232, 4, fp_vector_vector_wv_3232_arg4); + setArg(call_fp_vector_vector_wv_3232, 5, fp_vector_vector_wv_3232_arg5); + setArg(call_fp_vector_vector_wv_3232, 6, vm); + setArg(call_fp_vector_vector_wv_3232, 7, vd); + setArg(call_fp_vector_vector_wv_3232, 8, vs2); + setArg(call_fp_vector_vector_wv_3232, 9, vs1); + setArg(call_fp_vector_vector_wv_3232, 10, fp_vector_vector_wv_3232_arg10); + setArg(call_fp_vector_vector_wv_3232, 11, fp_vector_vector_wv_3232_arg11); + InvokeNode* call_fget_flags_3234; + x86::Gp ret_val_fget_flags_3234 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3234, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3234; + setRet(call_fget_flags_3234, 0, ret_val_fget_flags_3234); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3235 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3235, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3235, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 704); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 705: VFWADD__WF */ + continuation_e __vfwadd__wf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwadd.wf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWADD__WF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 705); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3236; + x86::Gp ret_val_get_sew_pow_3236 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3236, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3237 = get_reg(cc, 8, false); + mov(cc, tmp3237, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3237, (ret_val_get_sew_pow_3236))), 8, false), ~ 1); + setArg(call_get_sew_pow_3236, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3236, 0, ret_val_get_sew_pow_3236); + InvokeNode* call_get_lmul_pow_3238; + x86::Gp ret_val_get_lmul_pow_3238 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3238, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3238; + setArg(call_get_lmul_pow_3238, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3238, 0, ret_val_get_lmul_pow_3238); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3239; + auto illegal_fp_variable_width_3239_arg2 = SEW; + auto illegal_fp_variable_width_3239_arg3 = rm; + auto illegal_fp_variable_width_3239_arg4 = SEW_widen; + auto illegal_fp_variable_width_3239_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3239 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3239, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_fp_variable_width_3239; + setArg(call_illegal_fp_variable_width_3239, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3239, 1, vd); + setArg(call_illegal_fp_variable_width_3239, 2, vm); + setArg(call_illegal_fp_variable_width_3239, 3, illegal_fp_variable_width_3239_arg2); + setArg(call_illegal_fp_variable_width_3239, 4, illegal_fp_variable_width_3239_arg3); + setArg(call_illegal_fp_variable_width_3239, 5, illegal_fp_variable_width_3239_arg4); + setArg(call_illegal_fp_variable_width_3239, 6, illegal_fp_variable_width_3239_arg5); + setRet(call_illegal_fp_variable_width_3239, 0, ret_val_illegal_fp_variable_width_3239); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3241; + x86::Gp ret_val_sew_3241 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3241, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_ww_3240; + auto fp_vector_imm_ww_3240_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_ww_3240_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_ww_3240_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_ww_3240_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_ww_3240_arg10 = rm; + auto fp_vector_imm_ww_3240_arg11 = ret_val_sew_3241; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_ww_3240, &fp_vector_imm_ww, FuncSignature::build()); + setArg(call_sew_3241, 0, reinterpret_cast(this)); + setRet(call_sew_3241, 0, ret_val_sew_3241); + setArg(call_fp_vector_imm_ww_3240, 0, V); + setArg(call_fp_vector_imm_ww_3240, 1, 52); + setArg(call_fp_vector_imm_ww_3240, 2, 5); + setArg(call_fp_vector_imm_ww_3240, 3, fp_vector_imm_ww_3240_arg3); + setArg(call_fp_vector_imm_ww_3240, 4, fp_vector_imm_ww_3240_arg4); + setArg(call_fp_vector_imm_ww_3240, 5, fp_vector_imm_ww_3240_arg5); + setArg(call_fp_vector_imm_ww_3240, 6, vm); + setArg(call_fp_vector_imm_ww_3240, 7, vd); + setArg(call_fp_vector_imm_ww_3240, 8, vs2); + setArg(call_fp_vector_imm_ww_3240, 9, fp_vector_imm_ww_3240_arg9); + setArg(call_fp_vector_imm_ww_3240, 10, fp_vector_imm_ww_3240_arg10); + setArg(call_fp_vector_imm_ww_3240, 11, fp_vector_imm_ww_3240_arg11); + InvokeNode* call_fget_flags_3242; + x86::Gp ret_val_fget_flags_3242 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3242, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3242; + setRet(call_fget_flags_3242, 0, ret_val_fget_flags_3242); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3243 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3243, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3243, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 705); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 706: VFWADD__WV */ + continuation_e __vfwadd__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwadd.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWADD__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 706); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3244; + x86::Gp ret_val_get_sew_pow_3244 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3244, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3245 = get_reg(cc, 8, false); + mov(cc, tmp3245, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3245, (ret_val_get_sew_pow_3244))), 8, false), ~ 1); + setArg(call_get_sew_pow_3244, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3244, 0, ret_val_get_sew_pow_3244); + InvokeNode* call_get_lmul_pow_3246; + x86::Gp ret_val_get_lmul_pow_3246 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3246, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3246; + setArg(call_get_lmul_pow_3246, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3246, 0, ret_val_get_lmul_pow_3246); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3247; + auto illegal_fp_variable_width_3247_arg2 = SEW; + auto illegal_fp_variable_width_3247_arg3 = rm; + auto illegal_fp_variable_width_3247_arg4 = SEW_widen; + auto illegal_fp_variable_width_3247_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3247 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3247, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3248; + auto valid_reg_overlap_3248_arg2 = LMUL_pow; + auto valid_reg_overlap_3248_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3248 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3248, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3247, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3248)); + setArg(call_illegal_fp_variable_width_3247, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3247, 1, vd); + setArg(call_illegal_fp_variable_width_3247, 2, vm); + setArg(call_illegal_fp_variable_width_3247, 3, illegal_fp_variable_width_3247_arg2); + setArg(call_illegal_fp_variable_width_3247, 4, illegal_fp_variable_width_3247_arg3); + setArg(call_illegal_fp_variable_width_3247, 5, illegal_fp_variable_width_3247_arg4); + setArg(call_illegal_fp_variable_width_3247, 6, illegal_fp_variable_width_3247_arg5); + setRet(call_illegal_fp_variable_width_3247, 0, ret_val_illegal_fp_variable_width_3247); + setArg(call_valid_reg_overlap_3248, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3248, 1, vs1); + setArg(call_valid_reg_overlap_3248, 2, vd); + setArg(call_valid_reg_overlap_3248, 3, valid_reg_overlap_3248_arg2); + setArg(call_valid_reg_overlap_3248, 4, valid_reg_overlap_3248_arg3); + setRet(call_valid_reg_overlap_3248, 0, ret_val_valid_reg_overlap_3248); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3250; + x86::Gp ret_val_sew_3250 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3250, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_ww_3249; + auto fp_vector_vector_ww_3249_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_ww_3249_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_ww_3249_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_ww_3249_arg10 = rm; + auto fp_vector_vector_ww_3249_arg11 = ret_val_sew_3250; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_ww_3249, &fp_vector_vector_ww, FuncSignature::build()); + setArg(call_sew_3250, 0, reinterpret_cast(this)); + setRet(call_sew_3250, 0, ret_val_sew_3250); + setArg(call_fp_vector_vector_ww_3249, 0, V); + setArg(call_fp_vector_vector_ww_3249, 1, 52); + setArg(call_fp_vector_vector_ww_3249, 2, 1); + setArg(call_fp_vector_vector_ww_3249, 3, fp_vector_vector_ww_3249_arg3); + setArg(call_fp_vector_vector_ww_3249, 4, fp_vector_vector_ww_3249_arg4); + setArg(call_fp_vector_vector_ww_3249, 5, fp_vector_vector_ww_3249_arg5); + setArg(call_fp_vector_vector_ww_3249, 6, vm); + setArg(call_fp_vector_vector_ww_3249, 7, vd); + setArg(call_fp_vector_vector_ww_3249, 8, vs2); + setArg(call_fp_vector_vector_ww_3249, 9, vs1); + setArg(call_fp_vector_vector_ww_3249, 10, fp_vector_vector_ww_3249_arg10); + setArg(call_fp_vector_vector_ww_3249, 11, fp_vector_vector_ww_3249_arg11); + InvokeNode* call_fget_flags_3251; + x86::Gp ret_val_fget_flags_3251 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3251, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3251; + setRet(call_fget_flags_3251, 0, ret_val_fget_flags_3251); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3252 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3252, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3252, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 706); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 707: VFWSUB__WF */ + continuation_e __vfwsub__wf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwsub.wf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWSUB__WF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 707); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3253; + x86::Gp ret_val_get_sew_pow_3253 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3253, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3254 = get_reg(cc, 8, false); + mov(cc, tmp3254, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3254, (ret_val_get_sew_pow_3253))), 8, false), ~ 1); + setArg(call_get_sew_pow_3253, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3253, 0, ret_val_get_sew_pow_3253); + InvokeNode* call_get_lmul_pow_3255; + x86::Gp ret_val_get_lmul_pow_3255 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3255, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3255; + setArg(call_get_lmul_pow_3255, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3255, 0, ret_val_get_lmul_pow_3255); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3256; + auto illegal_fp_variable_width_3256_arg2 = SEW; + auto illegal_fp_variable_width_3256_arg3 = rm; + auto illegal_fp_variable_width_3256_arg4 = SEW_widen; + auto illegal_fp_variable_width_3256_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3256 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3256, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_fp_variable_width_3256; + setArg(call_illegal_fp_variable_width_3256, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3256, 1, vd); + setArg(call_illegal_fp_variable_width_3256, 2, vm); + setArg(call_illegal_fp_variable_width_3256, 3, illegal_fp_variable_width_3256_arg2); + setArg(call_illegal_fp_variable_width_3256, 4, illegal_fp_variable_width_3256_arg3); + setArg(call_illegal_fp_variable_width_3256, 5, illegal_fp_variable_width_3256_arg4); + setArg(call_illegal_fp_variable_width_3256, 6, illegal_fp_variable_width_3256_arg5); + setRet(call_illegal_fp_variable_width_3256, 0, ret_val_illegal_fp_variable_width_3256); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3258; + x86::Gp ret_val_sew_3258 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3258, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_ww_3257; + auto fp_vector_imm_ww_3257_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_ww_3257_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_ww_3257_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_ww_3257_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_ww_3257_arg10 = rm; + auto fp_vector_imm_ww_3257_arg11 = ret_val_sew_3258; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_ww_3257, &fp_vector_imm_ww, FuncSignature::build()); + setArg(call_sew_3258, 0, reinterpret_cast(this)); + setRet(call_sew_3258, 0, ret_val_sew_3258); + setArg(call_fp_vector_imm_ww_3257, 0, V); + setArg(call_fp_vector_imm_ww_3257, 1, 54); + setArg(call_fp_vector_imm_ww_3257, 2, 5); + setArg(call_fp_vector_imm_ww_3257, 3, fp_vector_imm_ww_3257_arg3); + setArg(call_fp_vector_imm_ww_3257, 4, fp_vector_imm_ww_3257_arg4); + setArg(call_fp_vector_imm_ww_3257, 5, fp_vector_imm_ww_3257_arg5); + setArg(call_fp_vector_imm_ww_3257, 6, vm); + setArg(call_fp_vector_imm_ww_3257, 7, vd); + setArg(call_fp_vector_imm_ww_3257, 8, vs2); + setArg(call_fp_vector_imm_ww_3257, 9, fp_vector_imm_ww_3257_arg9); + setArg(call_fp_vector_imm_ww_3257, 10, fp_vector_imm_ww_3257_arg10); + setArg(call_fp_vector_imm_ww_3257, 11, fp_vector_imm_ww_3257_arg11); + InvokeNode* call_fget_flags_3259; + x86::Gp ret_val_fget_flags_3259 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3259, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3259; + setRet(call_fget_flags_3259, 0, ret_val_fget_flags_3259); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3260 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3260, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3260, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 707); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 708: VFWSUB__WV */ + continuation_e __vfwsub__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwsub.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWSUB__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 708); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3261; + x86::Gp ret_val_get_sew_pow_3261 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3261, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3262 = get_reg(cc, 8, false); + mov(cc, tmp3262, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3262, (ret_val_get_sew_pow_3261))), 8, false), ~ 1); + setArg(call_get_sew_pow_3261, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3261, 0, ret_val_get_sew_pow_3261); + InvokeNode* call_get_lmul_pow_3263; + x86::Gp ret_val_get_lmul_pow_3263 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3263, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3263; + setArg(call_get_lmul_pow_3263, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3263, 0, ret_val_get_lmul_pow_3263); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3264; + auto illegal_fp_variable_width_3264_arg2 = SEW; + auto illegal_fp_variable_width_3264_arg3 = rm; + auto illegal_fp_variable_width_3264_arg4 = SEW_widen; + auto illegal_fp_variable_width_3264_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3264 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3264, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3265; + auto valid_reg_overlap_3265_arg2 = LMUL_pow; + auto valid_reg_overlap_3265_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3265 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3265, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3264, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3265)); + setArg(call_illegal_fp_variable_width_3264, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3264, 1, vd); + setArg(call_illegal_fp_variable_width_3264, 2, vm); + setArg(call_illegal_fp_variable_width_3264, 3, illegal_fp_variable_width_3264_arg2); + setArg(call_illegal_fp_variable_width_3264, 4, illegal_fp_variable_width_3264_arg3); + setArg(call_illegal_fp_variable_width_3264, 5, illegal_fp_variable_width_3264_arg4); + setArg(call_illegal_fp_variable_width_3264, 6, illegal_fp_variable_width_3264_arg5); + setRet(call_illegal_fp_variable_width_3264, 0, ret_val_illegal_fp_variable_width_3264); + setArg(call_valid_reg_overlap_3265, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3265, 1, vs1); + setArg(call_valid_reg_overlap_3265, 2, vd); + setArg(call_valid_reg_overlap_3265, 3, valid_reg_overlap_3265_arg2); + setArg(call_valid_reg_overlap_3265, 4, valid_reg_overlap_3265_arg3); + setRet(call_valid_reg_overlap_3265, 0, ret_val_valid_reg_overlap_3265); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3267; + x86::Gp ret_val_sew_3267 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3267, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_ww_3266; + auto fp_vector_vector_ww_3266_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_ww_3266_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_ww_3266_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_ww_3266_arg10 = rm; + auto fp_vector_vector_ww_3266_arg11 = ret_val_sew_3267; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_ww_3266, &fp_vector_vector_ww, FuncSignature::build()); + setArg(call_sew_3267, 0, reinterpret_cast(this)); + setRet(call_sew_3267, 0, ret_val_sew_3267); + setArg(call_fp_vector_vector_ww_3266, 0, V); + setArg(call_fp_vector_vector_ww_3266, 1, 54); + setArg(call_fp_vector_vector_ww_3266, 2, 1); + setArg(call_fp_vector_vector_ww_3266, 3, fp_vector_vector_ww_3266_arg3); + setArg(call_fp_vector_vector_ww_3266, 4, fp_vector_vector_ww_3266_arg4); + setArg(call_fp_vector_vector_ww_3266, 5, fp_vector_vector_ww_3266_arg5); + setArg(call_fp_vector_vector_ww_3266, 6, vm); + setArg(call_fp_vector_vector_ww_3266, 7, vd); + setArg(call_fp_vector_vector_ww_3266, 8, vs2); + setArg(call_fp_vector_vector_ww_3266, 9, vs1); + setArg(call_fp_vector_vector_ww_3266, 10, fp_vector_vector_ww_3266_arg10); + setArg(call_fp_vector_vector_ww_3266, 11, fp_vector_vector_ww_3266_arg11); + InvokeNode* call_fget_flags_3268; + x86::Gp ret_val_fget_flags_3268 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3268, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3268; + setRet(call_fget_flags_3268, 0, ret_val_fget_flags_3268); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3269 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3269, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3269, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 708); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 709: VFMUL__VF */ + continuation_e __vfmul__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmul.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMUL__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 709); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3270; + x86::Gp ret_val_get_sew_pow_3270 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3270, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3271 = get_reg(cc, 8, false); + mov(cc, tmp3271, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3271, (ret_val_get_sew_pow_3270))), 8, false), ~ 1); + setArg(call_get_sew_pow_3270, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3270, 0, ret_val_get_sew_pow_3270); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3272; + auto illegal_fp_normal_3272_arg2 = SEW; + auto illegal_fp_normal_3272_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3272 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3272, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3272; + setArg(call_illegal_fp_normal_3272, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3272, 1, vd); + setArg(call_illegal_fp_normal_3272, 2, vm); + setArg(call_illegal_fp_normal_3272, 3, illegal_fp_normal_3272_arg2); + setArg(call_illegal_fp_normal_3272, 4, illegal_fp_normal_3272_arg3); + setRet(call_illegal_fp_normal_3272, 0, ret_val_illegal_fp_normal_3272); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3274; + x86::Gp ret_val_sew_3274 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3274, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3273; + auto fp_vector_imm_op_3273_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3273_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3273_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3273_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3273_arg10 = rm; + auto fp_vector_imm_op_3273_arg11 = ret_val_sew_3274; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3273, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3274, 0, reinterpret_cast(this)); + setRet(call_sew_3274, 0, ret_val_sew_3274); + setArg(call_fp_vector_imm_op_3273, 0, V); + setArg(call_fp_vector_imm_op_3273, 1, 36); + setArg(call_fp_vector_imm_op_3273, 2, 5); + setArg(call_fp_vector_imm_op_3273, 3, fp_vector_imm_op_3273_arg3); + setArg(call_fp_vector_imm_op_3273, 4, fp_vector_imm_op_3273_arg4); + setArg(call_fp_vector_imm_op_3273, 5, fp_vector_imm_op_3273_arg5); + setArg(call_fp_vector_imm_op_3273, 6, vm); + setArg(call_fp_vector_imm_op_3273, 7, vd); + setArg(call_fp_vector_imm_op_3273, 8, vs2); + setArg(call_fp_vector_imm_op_3273, 9, fp_vector_imm_op_3273_arg9); + setArg(call_fp_vector_imm_op_3273, 10, fp_vector_imm_op_3273_arg10); + setArg(call_fp_vector_imm_op_3273, 11, fp_vector_imm_op_3273_arg11); + InvokeNode* call_fget_flags_3275; + x86::Gp ret_val_fget_flags_3275 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3275, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3275; + setRet(call_fget_flags_3275, 0, ret_val_fget_flags_3275); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3276 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3276, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3276, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 709); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 710: VFMUL__VV */ + continuation_e __vfmul__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vfmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMUL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 710); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3277; + x86::Gp ret_val_get_sew_pow_3277 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3277, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3278 = get_reg(cc, 8, false); + mov(cc, tmp3278, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3278, (ret_val_get_sew_pow_3277))), 8, false), ~ 1); + setArg(call_get_sew_pow_3277, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3277, 0, ret_val_get_sew_pow_3277); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3279; + auto illegal_fp_normal_3279_arg2 = SEW; + auto illegal_fp_normal_3279_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3279 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3279, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3279; + setArg(call_illegal_fp_normal_3279, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3279, 1, vd); + setArg(call_illegal_fp_normal_3279, 2, vm); + setArg(call_illegal_fp_normal_3279, 3, illegal_fp_normal_3279_arg2); + setArg(call_illegal_fp_normal_3279, 4, illegal_fp_normal_3279_arg3); + setRet(call_illegal_fp_normal_3279, 0, ret_val_illegal_fp_normal_3279); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3281; + x86::Gp ret_val_sew_3281 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3281, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3280; + auto fp_vector_vector_op_3280_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3280_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3280_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3280_arg10 = rm; + auto fp_vector_vector_op_3280_arg11 = ret_val_sew_3281; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3280, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3281, 0, reinterpret_cast(this)); + setRet(call_sew_3281, 0, ret_val_sew_3281); + setArg(call_fp_vector_vector_op_3280, 0, V); + setArg(call_fp_vector_vector_op_3280, 1, 36); + setArg(call_fp_vector_vector_op_3280, 2, 1); + setArg(call_fp_vector_vector_op_3280, 3, fp_vector_vector_op_3280_arg3); + setArg(call_fp_vector_vector_op_3280, 4, fp_vector_vector_op_3280_arg4); + setArg(call_fp_vector_vector_op_3280, 5, fp_vector_vector_op_3280_arg5); + setArg(call_fp_vector_vector_op_3280, 6, vm); + setArg(call_fp_vector_vector_op_3280, 7, vd); + setArg(call_fp_vector_vector_op_3280, 8, vs2); + setArg(call_fp_vector_vector_op_3280, 9, vs1); + setArg(call_fp_vector_vector_op_3280, 10, fp_vector_vector_op_3280_arg10); + setArg(call_fp_vector_vector_op_3280, 11, fp_vector_vector_op_3280_arg11); + InvokeNode* call_fget_flags_3282; + x86::Gp ret_val_fget_flags_3282 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3282, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3282; + setRet(call_fget_flags_3282, 0, ret_val_fget_flags_3282); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3283 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3283, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3283, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 710); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 711: VFDIV__VF */ + continuation_e __vfdiv__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfdiv.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFDIV__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 711); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3284; + x86::Gp ret_val_get_sew_pow_3284 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3284, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3285 = get_reg(cc, 8, false); + mov(cc, tmp3285, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3285, (ret_val_get_sew_pow_3284))), 8, false), ~ 1); + setArg(call_get_sew_pow_3284, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3284, 0, ret_val_get_sew_pow_3284); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3286; + auto illegal_fp_normal_3286_arg2 = SEW; + auto illegal_fp_normal_3286_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3286 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3286, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3286; + setArg(call_illegal_fp_normal_3286, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3286, 1, vd); + setArg(call_illegal_fp_normal_3286, 2, vm); + setArg(call_illegal_fp_normal_3286, 3, illegal_fp_normal_3286_arg2); + setArg(call_illegal_fp_normal_3286, 4, illegal_fp_normal_3286_arg3); + setRet(call_illegal_fp_normal_3286, 0, ret_val_illegal_fp_normal_3286); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3288; + x86::Gp ret_val_sew_3288 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3288, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3287; + auto fp_vector_imm_op_3287_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3287_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3287_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3287_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3287_arg10 = rm; + auto fp_vector_imm_op_3287_arg11 = ret_val_sew_3288; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3287, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3288, 0, reinterpret_cast(this)); + setRet(call_sew_3288, 0, ret_val_sew_3288); + setArg(call_fp_vector_imm_op_3287, 0, V); + setArg(call_fp_vector_imm_op_3287, 1, 32); + setArg(call_fp_vector_imm_op_3287, 2, 5); + setArg(call_fp_vector_imm_op_3287, 3, fp_vector_imm_op_3287_arg3); + setArg(call_fp_vector_imm_op_3287, 4, fp_vector_imm_op_3287_arg4); + setArg(call_fp_vector_imm_op_3287, 5, fp_vector_imm_op_3287_arg5); + setArg(call_fp_vector_imm_op_3287, 6, vm); + setArg(call_fp_vector_imm_op_3287, 7, vd); + setArg(call_fp_vector_imm_op_3287, 8, vs2); + setArg(call_fp_vector_imm_op_3287, 9, fp_vector_imm_op_3287_arg9); + setArg(call_fp_vector_imm_op_3287, 10, fp_vector_imm_op_3287_arg10); + setArg(call_fp_vector_imm_op_3287, 11, fp_vector_imm_op_3287_arg11); + InvokeNode* call_fget_flags_3289; + x86::Gp ret_val_fget_flags_3289 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3289, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3289; + setRet(call_fget_flags_3289, 0, ret_val_fget_flags_3289); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3290 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3290, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3290, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 711); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 712: VFDIV__VV */ + continuation_e __vfdiv__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vfdiv.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFDIV__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 712); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3291; + x86::Gp ret_val_get_sew_pow_3291 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3291, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3292 = get_reg(cc, 8, false); + mov(cc, tmp3292, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3292, (ret_val_get_sew_pow_3291))), 8, false), ~ 1); + setArg(call_get_sew_pow_3291, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3291, 0, ret_val_get_sew_pow_3291); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3293; + auto illegal_fp_normal_3293_arg2 = SEW; + auto illegal_fp_normal_3293_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3293 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3293, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3293; + setArg(call_illegal_fp_normal_3293, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3293, 1, vd); + setArg(call_illegal_fp_normal_3293, 2, vm); + setArg(call_illegal_fp_normal_3293, 3, illegal_fp_normal_3293_arg2); + setArg(call_illegal_fp_normal_3293, 4, illegal_fp_normal_3293_arg3); + setRet(call_illegal_fp_normal_3293, 0, ret_val_illegal_fp_normal_3293); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3295; + x86::Gp ret_val_sew_3295 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3295, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3294; + auto fp_vector_vector_op_3294_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3294_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3294_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3294_arg10 = rm; + auto fp_vector_vector_op_3294_arg11 = ret_val_sew_3295; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3294, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3295, 0, reinterpret_cast(this)); + setRet(call_sew_3295, 0, ret_val_sew_3295); + setArg(call_fp_vector_vector_op_3294, 0, V); + setArg(call_fp_vector_vector_op_3294, 1, 32); + setArg(call_fp_vector_vector_op_3294, 2, 1); + setArg(call_fp_vector_vector_op_3294, 3, fp_vector_vector_op_3294_arg3); + setArg(call_fp_vector_vector_op_3294, 4, fp_vector_vector_op_3294_arg4); + setArg(call_fp_vector_vector_op_3294, 5, fp_vector_vector_op_3294_arg5); + setArg(call_fp_vector_vector_op_3294, 6, vm); + setArg(call_fp_vector_vector_op_3294, 7, vd); + setArg(call_fp_vector_vector_op_3294, 8, vs2); + setArg(call_fp_vector_vector_op_3294, 9, vs1); + setArg(call_fp_vector_vector_op_3294, 10, fp_vector_vector_op_3294_arg10); + setArg(call_fp_vector_vector_op_3294, 11, fp_vector_vector_op_3294_arg11); + InvokeNode* call_fget_flags_3296; + x86::Gp ret_val_fget_flags_3296 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3296, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3296; + setRet(call_fget_flags_3296, 0, ret_val_fget_flags_3296); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3297 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3297, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3297, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 712); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 713: VFRDIV__VF */ + continuation_e __vfrdiv__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfrdiv.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFRDIV__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 713); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3298; + x86::Gp ret_val_get_sew_pow_3298 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3298, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3299 = get_reg(cc, 8, false); + mov(cc, tmp3299, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3299, (ret_val_get_sew_pow_3298))), 8, false), ~ 1); + setArg(call_get_sew_pow_3298, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3298, 0, ret_val_get_sew_pow_3298); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3300; + auto illegal_fp_normal_3300_arg2 = SEW; + auto illegal_fp_normal_3300_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3300 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3300, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3300; + setArg(call_illegal_fp_normal_3300, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3300, 1, vd); + setArg(call_illegal_fp_normal_3300, 2, vm); + setArg(call_illegal_fp_normal_3300, 3, illegal_fp_normal_3300_arg2); + setArg(call_illegal_fp_normal_3300, 4, illegal_fp_normal_3300_arg3); + setRet(call_illegal_fp_normal_3300, 0, ret_val_illegal_fp_normal_3300); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3302; + x86::Gp ret_val_sew_3302 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3302, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3301; + auto fp_vector_imm_op_3301_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3301_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3301_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3301_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3301_arg10 = rm; + auto fp_vector_imm_op_3301_arg11 = ret_val_sew_3302; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3301, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3302, 0, reinterpret_cast(this)); + setRet(call_sew_3302, 0, ret_val_sew_3302); + setArg(call_fp_vector_imm_op_3301, 0, V); + setArg(call_fp_vector_imm_op_3301, 1, 33); + setArg(call_fp_vector_imm_op_3301, 2, 5); + setArg(call_fp_vector_imm_op_3301, 3, fp_vector_imm_op_3301_arg3); + setArg(call_fp_vector_imm_op_3301, 4, fp_vector_imm_op_3301_arg4); + setArg(call_fp_vector_imm_op_3301, 5, fp_vector_imm_op_3301_arg5); + setArg(call_fp_vector_imm_op_3301, 6, vm); + setArg(call_fp_vector_imm_op_3301, 7, vd); + setArg(call_fp_vector_imm_op_3301, 8, vs2); + setArg(call_fp_vector_imm_op_3301, 9, fp_vector_imm_op_3301_arg9); + setArg(call_fp_vector_imm_op_3301, 10, fp_vector_imm_op_3301_arg10); + setArg(call_fp_vector_imm_op_3301, 11, fp_vector_imm_op_3301_arg11); + InvokeNode* call_fget_flags_3303; + x86::Gp ret_val_fget_flags_3303 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3303, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3303; + setRet(call_fget_flags_3303, 0, ret_val_fget_flags_3303); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3304 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3304, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3304, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 713); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 714: VFWMUL__VF */ + continuation_e __vfwmul__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmul.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMUL__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 714); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3305; + x86::Gp ret_val_get_sew_pow_3305 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3305, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3306 = get_reg(cc, 8, false); + mov(cc, tmp3306, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3306, (ret_val_get_sew_pow_3305))), 8, false), ~ 1); + setArg(call_get_sew_pow_3305, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3305, 0, ret_val_get_sew_pow_3305); + InvokeNode* call_get_lmul_pow_3307; + x86::Gp ret_val_get_lmul_pow_3307 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3307, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3307; + setArg(call_get_lmul_pow_3307, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3307, 0, ret_val_get_lmul_pow_3307); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3308; + auto illegal_fp_variable_width_3308_arg2 = SEW; + auto illegal_fp_variable_width_3308_arg3 = rm; + auto illegal_fp_variable_width_3308_arg4 = SEW_widen; + auto illegal_fp_variable_width_3308_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3308 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3308, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3309; + auto valid_reg_overlap_3309_arg2 = LMUL_pow; + auto valid_reg_overlap_3309_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3309 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3309, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3308, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3309)); + setArg(call_illegal_fp_variable_width_3308, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3308, 1, vd); + setArg(call_illegal_fp_variable_width_3308, 2, vm); + setArg(call_illegal_fp_variable_width_3308, 3, illegal_fp_variable_width_3308_arg2); + setArg(call_illegal_fp_variable_width_3308, 4, illegal_fp_variable_width_3308_arg3); + setArg(call_illegal_fp_variable_width_3308, 5, illegal_fp_variable_width_3308_arg4); + setArg(call_illegal_fp_variable_width_3308, 6, illegal_fp_variable_width_3308_arg5); + setRet(call_illegal_fp_variable_width_3308, 0, ret_val_illegal_fp_variable_width_3308); + setArg(call_valid_reg_overlap_3309, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3309, 1, vs2); + setArg(call_valid_reg_overlap_3309, 2, vd); + setArg(call_valid_reg_overlap_3309, 3, valid_reg_overlap_3309_arg2); + setArg(call_valid_reg_overlap_3309, 4, valid_reg_overlap_3309_arg3); + setRet(call_valid_reg_overlap_3309, 0, ret_val_valid_reg_overlap_3309); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3311; + x86::Gp ret_val_sew_3311 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3311, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3310; + auto fp_vector_imm_wv_3310_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3310_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3310_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3310_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_wv_3310_arg10 = rm; + auto fp_vector_imm_wv_3310_arg11 = ret_val_sew_3311; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3310, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3311, 0, reinterpret_cast(this)); + setRet(call_sew_3311, 0, ret_val_sew_3311); + setArg(call_fp_vector_imm_wv_3310, 0, V); + setArg(call_fp_vector_imm_wv_3310, 1, 56); + setArg(call_fp_vector_imm_wv_3310, 2, 5); + setArg(call_fp_vector_imm_wv_3310, 3, fp_vector_imm_wv_3310_arg3); + setArg(call_fp_vector_imm_wv_3310, 4, fp_vector_imm_wv_3310_arg4); + setArg(call_fp_vector_imm_wv_3310, 5, fp_vector_imm_wv_3310_arg5); + setArg(call_fp_vector_imm_wv_3310, 6, vm); + setArg(call_fp_vector_imm_wv_3310, 7, vd); + setArg(call_fp_vector_imm_wv_3310, 8, vs2); + setArg(call_fp_vector_imm_wv_3310, 9, fp_vector_imm_wv_3310_arg9); + setArg(call_fp_vector_imm_wv_3310, 10, fp_vector_imm_wv_3310_arg10); + setArg(call_fp_vector_imm_wv_3310, 11, fp_vector_imm_wv_3310_arg11); + InvokeNode* call_fget_flags_3312; + x86::Gp ret_val_fget_flags_3312 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3312, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3312; + setRet(call_fget_flags_3312, 0, ret_val_fget_flags_3312); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3313 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3313, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3313, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 714); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 715: VFWMUL__VV */ + continuation_e __vfwmul__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMUL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 715); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3314; + x86::Gp ret_val_get_sew_pow_3314 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3314, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3315 = get_reg(cc, 8, false); + mov(cc, tmp3315, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3315, (ret_val_get_sew_pow_3314))), 8, false), ~ 1); + setArg(call_get_sew_pow_3314, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3314, 0, ret_val_get_sew_pow_3314); + InvokeNode* call_get_lmul_pow_3316; + x86::Gp ret_val_get_lmul_pow_3316 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3316, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3316; + setArg(call_get_lmul_pow_3316, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3316, 0, ret_val_get_lmul_pow_3316); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3317; + auto illegal_fp_variable_width_3317_arg2 = SEW; + auto illegal_fp_variable_width_3317_arg3 = rm; + auto illegal_fp_variable_width_3317_arg4 = SEW_widen; + auto illegal_fp_variable_width_3317_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3317 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3317, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3318; + auto valid_reg_overlap_3318_arg2 = LMUL_pow; + auto valid_reg_overlap_3318_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3318 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3318, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3319; + auto valid_reg_overlap_3319_arg2 = LMUL_pow; + auto valid_reg_overlap_3319_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3319 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3319, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3317, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3318)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3319)); + setArg(call_illegal_fp_variable_width_3317, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3317, 1, vd); + setArg(call_illegal_fp_variable_width_3317, 2, vm); + setArg(call_illegal_fp_variable_width_3317, 3, illegal_fp_variable_width_3317_arg2); + setArg(call_illegal_fp_variable_width_3317, 4, illegal_fp_variable_width_3317_arg3); + setArg(call_illegal_fp_variable_width_3317, 5, illegal_fp_variable_width_3317_arg4); + setArg(call_illegal_fp_variable_width_3317, 6, illegal_fp_variable_width_3317_arg5); + setRet(call_illegal_fp_variable_width_3317, 0, ret_val_illegal_fp_variable_width_3317); + setArg(call_valid_reg_overlap_3318, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3318, 1, vs1); + setArg(call_valid_reg_overlap_3318, 2, vd); + setArg(call_valid_reg_overlap_3318, 3, valid_reg_overlap_3318_arg2); + setArg(call_valid_reg_overlap_3318, 4, valid_reg_overlap_3318_arg3); + setRet(call_valid_reg_overlap_3318, 0, ret_val_valid_reg_overlap_3318); + setArg(call_valid_reg_overlap_3319, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3319, 1, vs2); + setArg(call_valid_reg_overlap_3319, 2, vd); + setArg(call_valid_reg_overlap_3319, 3, valid_reg_overlap_3319_arg2); + setArg(call_valid_reg_overlap_3319, 4, valid_reg_overlap_3319_arg3); + setRet(call_valid_reg_overlap_3319, 0, ret_val_valid_reg_overlap_3319); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3321; + x86::Gp ret_val_sew_3321 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3321, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3320; + auto fp_vector_vector_wv_3320_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3320_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3320_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3320_arg10 = rm; + auto fp_vector_vector_wv_3320_arg11 = ret_val_sew_3321; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3320, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3321, 0, reinterpret_cast(this)); + setRet(call_sew_3321, 0, ret_val_sew_3321); + setArg(call_fp_vector_vector_wv_3320, 0, V); + setArg(call_fp_vector_vector_wv_3320, 1, 56); + setArg(call_fp_vector_vector_wv_3320, 2, 1); + setArg(call_fp_vector_vector_wv_3320, 3, fp_vector_vector_wv_3320_arg3); + setArg(call_fp_vector_vector_wv_3320, 4, fp_vector_vector_wv_3320_arg4); + setArg(call_fp_vector_vector_wv_3320, 5, fp_vector_vector_wv_3320_arg5); + setArg(call_fp_vector_vector_wv_3320, 6, vm); + setArg(call_fp_vector_vector_wv_3320, 7, vd); + setArg(call_fp_vector_vector_wv_3320, 8, vs2); + setArg(call_fp_vector_vector_wv_3320, 9, vs1); + setArg(call_fp_vector_vector_wv_3320, 10, fp_vector_vector_wv_3320_arg10); + setArg(call_fp_vector_vector_wv_3320, 11, fp_vector_vector_wv_3320_arg11); + InvokeNode* call_fget_flags_3322; + x86::Gp ret_val_fget_flags_3322 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3322, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3322; + setRet(call_fget_flags_3322, 0, ret_val_fget_flags_3322); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3323 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3323, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3323, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 715); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 716: VFMACC__VF */ + continuation_e __vfmacc__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMACC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 716); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3324; + x86::Gp ret_val_get_sew_pow_3324 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3324, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3325 = get_reg(cc, 8, false); + mov(cc, tmp3325, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3325, (ret_val_get_sew_pow_3324))), 8, false), ~ 1); + setArg(call_get_sew_pow_3324, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3324, 0, ret_val_get_sew_pow_3324); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3326; + auto illegal_fp_normal_3326_arg2 = SEW; + auto illegal_fp_normal_3326_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3326 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3326, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3326; + setArg(call_illegal_fp_normal_3326, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3326, 1, vd); + setArg(call_illegal_fp_normal_3326, 2, vm); + setArg(call_illegal_fp_normal_3326, 3, illegal_fp_normal_3326_arg2); + setArg(call_illegal_fp_normal_3326, 4, illegal_fp_normal_3326_arg3); + setRet(call_illegal_fp_normal_3326, 0, ret_val_illegal_fp_normal_3326); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3328; + x86::Gp ret_val_sew_3328 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3328, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3327; + auto fp_vector_imm_op_3327_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3327_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3327_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3327_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3327_arg10 = rm; + auto fp_vector_imm_op_3327_arg11 = ret_val_sew_3328; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3327, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3328, 0, reinterpret_cast(this)); + setRet(call_sew_3328, 0, ret_val_sew_3328); + setArg(call_fp_vector_imm_op_3327, 0, V); + setArg(call_fp_vector_imm_op_3327, 1, 44); + setArg(call_fp_vector_imm_op_3327, 2, 5); + setArg(call_fp_vector_imm_op_3327, 3, fp_vector_imm_op_3327_arg3); + setArg(call_fp_vector_imm_op_3327, 4, fp_vector_imm_op_3327_arg4); + setArg(call_fp_vector_imm_op_3327, 5, fp_vector_imm_op_3327_arg5); + setArg(call_fp_vector_imm_op_3327, 6, vm); + setArg(call_fp_vector_imm_op_3327, 7, vd); + setArg(call_fp_vector_imm_op_3327, 8, vs2); + setArg(call_fp_vector_imm_op_3327, 9, fp_vector_imm_op_3327_arg9); + setArg(call_fp_vector_imm_op_3327, 10, fp_vector_imm_op_3327_arg10); + setArg(call_fp_vector_imm_op_3327, 11, fp_vector_imm_op_3327_arg11); + InvokeNode* call_fget_flags_3329; + x86::Gp ret_val_fget_flags_3329 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3329, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3329; + setRet(call_fget_flags_3329, 0, ret_val_fget_flags_3329); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3330 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3330, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3330, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 716); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 717: VFMACC__VV */ + continuation_e __vfmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 717); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3331; + x86::Gp ret_val_get_sew_pow_3331 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3331, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3332 = get_reg(cc, 8, false); + mov(cc, tmp3332, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3332, (ret_val_get_sew_pow_3331))), 8, false), ~ 1); + setArg(call_get_sew_pow_3331, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3331, 0, ret_val_get_sew_pow_3331); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3333; + auto illegal_fp_normal_3333_arg2 = SEW; + auto illegal_fp_normal_3333_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3333 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3333, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3333; + setArg(call_illegal_fp_normal_3333, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3333, 1, vd); + setArg(call_illegal_fp_normal_3333, 2, vm); + setArg(call_illegal_fp_normal_3333, 3, illegal_fp_normal_3333_arg2); + setArg(call_illegal_fp_normal_3333, 4, illegal_fp_normal_3333_arg3); + setRet(call_illegal_fp_normal_3333, 0, ret_val_illegal_fp_normal_3333); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3335; + x86::Gp ret_val_sew_3335 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3335, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3334; + auto fp_vector_vector_op_3334_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3334_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3334_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3334_arg10 = rm; + auto fp_vector_vector_op_3334_arg11 = ret_val_sew_3335; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3334, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3335, 0, reinterpret_cast(this)); + setRet(call_sew_3335, 0, ret_val_sew_3335); + setArg(call_fp_vector_vector_op_3334, 0, V); + setArg(call_fp_vector_vector_op_3334, 1, 44); + setArg(call_fp_vector_vector_op_3334, 2, 1); + setArg(call_fp_vector_vector_op_3334, 3, fp_vector_vector_op_3334_arg3); + setArg(call_fp_vector_vector_op_3334, 4, fp_vector_vector_op_3334_arg4); + setArg(call_fp_vector_vector_op_3334, 5, fp_vector_vector_op_3334_arg5); + setArg(call_fp_vector_vector_op_3334, 6, vm); + setArg(call_fp_vector_vector_op_3334, 7, vd); + setArg(call_fp_vector_vector_op_3334, 8, vs2); + setArg(call_fp_vector_vector_op_3334, 9, vs1); + setArg(call_fp_vector_vector_op_3334, 10, fp_vector_vector_op_3334_arg10); + setArg(call_fp_vector_vector_op_3334, 11, fp_vector_vector_op_3334_arg11); + InvokeNode* call_fget_flags_3336; + x86::Gp ret_val_fget_flags_3336 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3336, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3336; + setRet(call_fget_flags_3336, 0, ret_val_fget_flags_3336); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3337 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3337, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3337, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 717); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 718: VFNMACC__VF */ + continuation_e __vfnmacc__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMACC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 718); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3338; + x86::Gp ret_val_get_sew_pow_3338 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3338, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3339 = get_reg(cc, 8, false); + mov(cc, tmp3339, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3339, (ret_val_get_sew_pow_3338))), 8, false), ~ 1); + setArg(call_get_sew_pow_3338, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3338, 0, ret_val_get_sew_pow_3338); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3340; + auto illegal_fp_normal_3340_arg2 = SEW; + auto illegal_fp_normal_3340_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3340 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3340, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3340; + setArg(call_illegal_fp_normal_3340, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3340, 1, vd); + setArg(call_illegal_fp_normal_3340, 2, vm); + setArg(call_illegal_fp_normal_3340, 3, illegal_fp_normal_3340_arg2); + setArg(call_illegal_fp_normal_3340, 4, illegal_fp_normal_3340_arg3); + setRet(call_illegal_fp_normal_3340, 0, ret_val_illegal_fp_normal_3340); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3342; + x86::Gp ret_val_sew_3342 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3342, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3341; + auto fp_vector_imm_op_3341_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3341_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3341_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3341_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3341_arg10 = rm; + auto fp_vector_imm_op_3341_arg11 = ret_val_sew_3342; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3341, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3342, 0, reinterpret_cast(this)); + setRet(call_sew_3342, 0, ret_val_sew_3342); + setArg(call_fp_vector_imm_op_3341, 0, V); + setArg(call_fp_vector_imm_op_3341, 1, 45); + setArg(call_fp_vector_imm_op_3341, 2, 5); + setArg(call_fp_vector_imm_op_3341, 3, fp_vector_imm_op_3341_arg3); + setArg(call_fp_vector_imm_op_3341, 4, fp_vector_imm_op_3341_arg4); + setArg(call_fp_vector_imm_op_3341, 5, fp_vector_imm_op_3341_arg5); + setArg(call_fp_vector_imm_op_3341, 6, vm); + setArg(call_fp_vector_imm_op_3341, 7, vd); + setArg(call_fp_vector_imm_op_3341, 8, vs2); + setArg(call_fp_vector_imm_op_3341, 9, fp_vector_imm_op_3341_arg9); + setArg(call_fp_vector_imm_op_3341, 10, fp_vector_imm_op_3341_arg10); + setArg(call_fp_vector_imm_op_3341, 11, fp_vector_imm_op_3341_arg11); + InvokeNode* call_fget_flags_3343; + x86::Gp ret_val_fget_flags_3343 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3343, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3343; + setRet(call_fget_flags_3343, 0, ret_val_fget_flags_3343); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3344 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3344, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3344, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 718); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 719: VFNMACC__VV */ + continuation_e __vfnmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 719); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3345; + x86::Gp ret_val_get_sew_pow_3345 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3345, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3346 = get_reg(cc, 8, false); + mov(cc, tmp3346, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3346, (ret_val_get_sew_pow_3345))), 8, false), ~ 1); + setArg(call_get_sew_pow_3345, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3345, 0, ret_val_get_sew_pow_3345); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3347; + auto illegal_fp_normal_3347_arg2 = SEW; + auto illegal_fp_normal_3347_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3347 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3347, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3347; + setArg(call_illegal_fp_normal_3347, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3347, 1, vd); + setArg(call_illegal_fp_normal_3347, 2, vm); + setArg(call_illegal_fp_normal_3347, 3, illegal_fp_normal_3347_arg2); + setArg(call_illegal_fp_normal_3347, 4, illegal_fp_normal_3347_arg3); + setRet(call_illegal_fp_normal_3347, 0, ret_val_illegal_fp_normal_3347); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3349; + x86::Gp ret_val_sew_3349 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3349, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3348; + auto fp_vector_vector_op_3348_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3348_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3348_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3348_arg10 = rm; + auto fp_vector_vector_op_3348_arg11 = ret_val_sew_3349; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3348, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3349, 0, reinterpret_cast(this)); + setRet(call_sew_3349, 0, ret_val_sew_3349); + setArg(call_fp_vector_vector_op_3348, 0, V); + setArg(call_fp_vector_vector_op_3348, 1, 45); + setArg(call_fp_vector_vector_op_3348, 2, 1); + setArg(call_fp_vector_vector_op_3348, 3, fp_vector_vector_op_3348_arg3); + setArg(call_fp_vector_vector_op_3348, 4, fp_vector_vector_op_3348_arg4); + setArg(call_fp_vector_vector_op_3348, 5, fp_vector_vector_op_3348_arg5); + setArg(call_fp_vector_vector_op_3348, 6, vm); + setArg(call_fp_vector_vector_op_3348, 7, vd); + setArg(call_fp_vector_vector_op_3348, 8, vs2); + setArg(call_fp_vector_vector_op_3348, 9, vs1); + setArg(call_fp_vector_vector_op_3348, 10, fp_vector_vector_op_3348_arg10); + setArg(call_fp_vector_vector_op_3348, 11, fp_vector_vector_op_3348_arg11); + InvokeNode* call_fget_flags_3350; + x86::Gp ret_val_fget_flags_3350 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3350, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3350; + setRet(call_fget_flags_3350, 0, ret_val_fget_flags_3350); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3351 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3351, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3351, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 719); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 720: VFMSAC__VF */ + continuation_e __vfmsac__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMSAC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 720); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3352; + x86::Gp ret_val_get_sew_pow_3352 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3352, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3353 = get_reg(cc, 8, false); + mov(cc, tmp3353, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3353, (ret_val_get_sew_pow_3352))), 8, false), ~ 1); + setArg(call_get_sew_pow_3352, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3352, 0, ret_val_get_sew_pow_3352); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3354; + auto illegal_fp_normal_3354_arg2 = SEW; + auto illegal_fp_normal_3354_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3354 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3354, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3354; + setArg(call_illegal_fp_normal_3354, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3354, 1, vd); + setArg(call_illegal_fp_normal_3354, 2, vm); + setArg(call_illegal_fp_normal_3354, 3, illegal_fp_normal_3354_arg2); + setArg(call_illegal_fp_normal_3354, 4, illegal_fp_normal_3354_arg3); + setRet(call_illegal_fp_normal_3354, 0, ret_val_illegal_fp_normal_3354); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3356; + x86::Gp ret_val_sew_3356 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3356, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3355; + auto fp_vector_imm_op_3355_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3355_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3355_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3355_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3355_arg10 = rm; + auto fp_vector_imm_op_3355_arg11 = ret_val_sew_3356; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3355, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3356, 0, reinterpret_cast(this)); + setRet(call_sew_3356, 0, ret_val_sew_3356); + setArg(call_fp_vector_imm_op_3355, 0, V); + setArg(call_fp_vector_imm_op_3355, 1, 46); + setArg(call_fp_vector_imm_op_3355, 2, 5); + setArg(call_fp_vector_imm_op_3355, 3, fp_vector_imm_op_3355_arg3); + setArg(call_fp_vector_imm_op_3355, 4, fp_vector_imm_op_3355_arg4); + setArg(call_fp_vector_imm_op_3355, 5, fp_vector_imm_op_3355_arg5); + setArg(call_fp_vector_imm_op_3355, 6, vm); + setArg(call_fp_vector_imm_op_3355, 7, vd); + setArg(call_fp_vector_imm_op_3355, 8, vs2); + setArg(call_fp_vector_imm_op_3355, 9, fp_vector_imm_op_3355_arg9); + setArg(call_fp_vector_imm_op_3355, 10, fp_vector_imm_op_3355_arg10); + setArg(call_fp_vector_imm_op_3355, 11, fp_vector_imm_op_3355_arg11); + InvokeNode* call_fget_flags_3357; + x86::Gp ret_val_fget_flags_3357 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3357, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3357; + setRet(call_fget_flags_3357, 0, ret_val_fget_flags_3357); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3358 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3358, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3358, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 720); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 721: VFMSAC__VV */ + continuation_e __vfmsac__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMSAC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 721); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3359; + x86::Gp ret_val_get_sew_pow_3359 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3359, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3360 = get_reg(cc, 8, false); + mov(cc, tmp3360, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3360, (ret_val_get_sew_pow_3359))), 8, false), ~ 1); + setArg(call_get_sew_pow_3359, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3359, 0, ret_val_get_sew_pow_3359); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3361; + auto illegal_fp_normal_3361_arg2 = SEW; + auto illegal_fp_normal_3361_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3361 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3361, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3361; + setArg(call_illegal_fp_normal_3361, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3361, 1, vd); + setArg(call_illegal_fp_normal_3361, 2, vm); + setArg(call_illegal_fp_normal_3361, 3, illegal_fp_normal_3361_arg2); + setArg(call_illegal_fp_normal_3361, 4, illegal_fp_normal_3361_arg3); + setRet(call_illegal_fp_normal_3361, 0, ret_val_illegal_fp_normal_3361); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3363; + x86::Gp ret_val_sew_3363 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3363, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3362; + auto fp_vector_vector_op_3362_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3362_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3362_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3362_arg10 = rm; + auto fp_vector_vector_op_3362_arg11 = ret_val_sew_3363; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3362, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3363, 0, reinterpret_cast(this)); + setRet(call_sew_3363, 0, ret_val_sew_3363); + setArg(call_fp_vector_vector_op_3362, 0, V); + setArg(call_fp_vector_vector_op_3362, 1, 46); + setArg(call_fp_vector_vector_op_3362, 2, 1); + setArg(call_fp_vector_vector_op_3362, 3, fp_vector_vector_op_3362_arg3); + setArg(call_fp_vector_vector_op_3362, 4, fp_vector_vector_op_3362_arg4); + setArg(call_fp_vector_vector_op_3362, 5, fp_vector_vector_op_3362_arg5); + setArg(call_fp_vector_vector_op_3362, 6, vm); + setArg(call_fp_vector_vector_op_3362, 7, vd); + setArg(call_fp_vector_vector_op_3362, 8, vs2); + setArg(call_fp_vector_vector_op_3362, 9, vs1); + setArg(call_fp_vector_vector_op_3362, 10, fp_vector_vector_op_3362_arg10); + setArg(call_fp_vector_vector_op_3362, 11, fp_vector_vector_op_3362_arg11); + InvokeNode* call_fget_flags_3364; + x86::Gp ret_val_fget_flags_3364 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3364, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3364; + setRet(call_fget_flags_3364, 0, ret_val_fget_flags_3364); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3365 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3365, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3365, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 721); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 722: VFNMSAC__VF */ + continuation_e __vfnmsac__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMSAC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 722); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3366; + x86::Gp ret_val_get_sew_pow_3366 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3366, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3367 = get_reg(cc, 8, false); + mov(cc, tmp3367, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3367, (ret_val_get_sew_pow_3366))), 8, false), ~ 1); + setArg(call_get_sew_pow_3366, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3366, 0, ret_val_get_sew_pow_3366); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3368; + auto illegal_fp_normal_3368_arg2 = SEW; + auto illegal_fp_normal_3368_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3368 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3368, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3368; + setArg(call_illegal_fp_normal_3368, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3368, 1, vd); + setArg(call_illegal_fp_normal_3368, 2, vm); + setArg(call_illegal_fp_normal_3368, 3, illegal_fp_normal_3368_arg2); + setArg(call_illegal_fp_normal_3368, 4, illegal_fp_normal_3368_arg3); + setRet(call_illegal_fp_normal_3368, 0, ret_val_illegal_fp_normal_3368); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3370; + x86::Gp ret_val_sew_3370 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3370, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3369; + auto fp_vector_imm_op_3369_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3369_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3369_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3369_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3369_arg10 = rm; + auto fp_vector_imm_op_3369_arg11 = ret_val_sew_3370; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3369, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3370, 0, reinterpret_cast(this)); + setRet(call_sew_3370, 0, ret_val_sew_3370); + setArg(call_fp_vector_imm_op_3369, 0, V); + setArg(call_fp_vector_imm_op_3369, 1, 47); + setArg(call_fp_vector_imm_op_3369, 2, 5); + setArg(call_fp_vector_imm_op_3369, 3, fp_vector_imm_op_3369_arg3); + setArg(call_fp_vector_imm_op_3369, 4, fp_vector_imm_op_3369_arg4); + setArg(call_fp_vector_imm_op_3369, 5, fp_vector_imm_op_3369_arg5); + setArg(call_fp_vector_imm_op_3369, 6, vm); + setArg(call_fp_vector_imm_op_3369, 7, vd); + setArg(call_fp_vector_imm_op_3369, 8, vs2); + setArg(call_fp_vector_imm_op_3369, 9, fp_vector_imm_op_3369_arg9); + setArg(call_fp_vector_imm_op_3369, 10, fp_vector_imm_op_3369_arg10); + setArg(call_fp_vector_imm_op_3369, 11, fp_vector_imm_op_3369_arg11); + InvokeNode* call_fget_flags_3371; + x86::Gp ret_val_fget_flags_3371 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3371, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3371; + setRet(call_fget_flags_3371, 0, ret_val_fget_flags_3371); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3372 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3372, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3372, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 722); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 723: VFNMSAC__VV */ + continuation_e __vfnmsac__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMSAC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 723); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3373; + x86::Gp ret_val_get_sew_pow_3373 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3373, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3374 = get_reg(cc, 8, false); + mov(cc, tmp3374, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3374, (ret_val_get_sew_pow_3373))), 8, false), ~ 1); + setArg(call_get_sew_pow_3373, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3373, 0, ret_val_get_sew_pow_3373); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3375; + auto illegal_fp_normal_3375_arg2 = SEW; + auto illegal_fp_normal_3375_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3375 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3375, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3375; + setArg(call_illegal_fp_normal_3375, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3375, 1, vd); + setArg(call_illegal_fp_normal_3375, 2, vm); + setArg(call_illegal_fp_normal_3375, 3, illegal_fp_normal_3375_arg2); + setArg(call_illegal_fp_normal_3375, 4, illegal_fp_normal_3375_arg3); + setRet(call_illegal_fp_normal_3375, 0, ret_val_illegal_fp_normal_3375); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3377; + x86::Gp ret_val_sew_3377 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3377, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3376; + auto fp_vector_vector_op_3376_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3376_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3376_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3376_arg10 = rm; + auto fp_vector_vector_op_3376_arg11 = ret_val_sew_3377; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3376, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3377, 0, reinterpret_cast(this)); + setRet(call_sew_3377, 0, ret_val_sew_3377); + setArg(call_fp_vector_vector_op_3376, 0, V); + setArg(call_fp_vector_vector_op_3376, 1, 47); + setArg(call_fp_vector_vector_op_3376, 2, 1); + setArg(call_fp_vector_vector_op_3376, 3, fp_vector_vector_op_3376_arg3); + setArg(call_fp_vector_vector_op_3376, 4, fp_vector_vector_op_3376_arg4); + setArg(call_fp_vector_vector_op_3376, 5, fp_vector_vector_op_3376_arg5); + setArg(call_fp_vector_vector_op_3376, 6, vm); + setArg(call_fp_vector_vector_op_3376, 7, vd); + setArg(call_fp_vector_vector_op_3376, 8, vs2); + setArg(call_fp_vector_vector_op_3376, 9, vs1); + setArg(call_fp_vector_vector_op_3376, 10, fp_vector_vector_op_3376_arg10); + setArg(call_fp_vector_vector_op_3376, 11, fp_vector_vector_op_3376_arg11); + InvokeNode* call_fget_flags_3378; + x86::Gp ret_val_fget_flags_3378 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3378, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3378; + setRet(call_fget_flags_3378, 0, ret_val_fget_flags_3378); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3379 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3379, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3379, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 723); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 724: VFMADD__VF */ + continuation_e __vfmadd__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMADD__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 724); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3380; + x86::Gp ret_val_get_sew_pow_3380 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3380, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3381 = get_reg(cc, 8, false); + mov(cc, tmp3381, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3381, (ret_val_get_sew_pow_3380))), 8, false), ~ 1); + setArg(call_get_sew_pow_3380, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3380, 0, ret_val_get_sew_pow_3380); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3382; + auto illegal_fp_normal_3382_arg2 = SEW; + auto illegal_fp_normal_3382_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3382 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3382, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3382; + setArg(call_illegal_fp_normal_3382, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3382, 1, vd); + setArg(call_illegal_fp_normal_3382, 2, vm); + setArg(call_illegal_fp_normal_3382, 3, illegal_fp_normal_3382_arg2); + setArg(call_illegal_fp_normal_3382, 4, illegal_fp_normal_3382_arg3); + setRet(call_illegal_fp_normal_3382, 0, ret_val_illegal_fp_normal_3382); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3384; + x86::Gp ret_val_sew_3384 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3384, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3383; + auto fp_vector_imm_op_3383_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3383_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3383_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3383_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3383_arg10 = rm; + auto fp_vector_imm_op_3383_arg11 = ret_val_sew_3384; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3383, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3384, 0, reinterpret_cast(this)); + setRet(call_sew_3384, 0, ret_val_sew_3384); + setArg(call_fp_vector_imm_op_3383, 0, V); + setArg(call_fp_vector_imm_op_3383, 1, 40); + setArg(call_fp_vector_imm_op_3383, 2, 5); + setArg(call_fp_vector_imm_op_3383, 3, fp_vector_imm_op_3383_arg3); + setArg(call_fp_vector_imm_op_3383, 4, fp_vector_imm_op_3383_arg4); + setArg(call_fp_vector_imm_op_3383, 5, fp_vector_imm_op_3383_arg5); + setArg(call_fp_vector_imm_op_3383, 6, vm); + setArg(call_fp_vector_imm_op_3383, 7, vd); + setArg(call_fp_vector_imm_op_3383, 8, vs2); + setArg(call_fp_vector_imm_op_3383, 9, fp_vector_imm_op_3383_arg9); + setArg(call_fp_vector_imm_op_3383, 10, fp_vector_imm_op_3383_arg10); + setArg(call_fp_vector_imm_op_3383, 11, fp_vector_imm_op_3383_arg11); + InvokeNode* call_fget_flags_3385; + x86::Gp ret_val_fget_flags_3385 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3385, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3385; + setRet(call_fget_flags_3385, 0, ret_val_fget_flags_3385); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3386 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3386, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3386, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 724); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 725: VFMADD__VV */ + continuation_e __vfmadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 725); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3387; + x86::Gp ret_val_get_sew_pow_3387 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3387, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3388 = get_reg(cc, 8, false); + mov(cc, tmp3388, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3388, (ret_val_get_sew_pow_3387))), 8, false), ~ 1); + setArg(call_get_sew_pow_3387, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3387, 0, ret_val_get_sew_pow_3387); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3389; + auto illegal_fp_normal_3389_arg2 = SEW; + auto illegal_fp_normal_3389_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3389 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3389, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3389; + setArg(call_illegal_fp_normal_3389, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3389, 1, vd); + setArg(call_illegal_fp_normal_3389, 2, vm); + setArg(call_illegal_fp_normal_3389, 3, illegal_fp_normal_3389_arg2); + setArg(call_illegal_fp_normal_3389, 4, illegal_fp_normal_3389_arg3); + setRet(call_illegal_fp_normal_3389, 0, ret_val_illegal_fp_normal_3389); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3391; + x86::Gp ret_val_sew_3391 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3391, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3390; + auto fp_vector_vector_op_3390_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3390_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3390_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3390_arg10 = rm; + auto fp_vector_vector_op_3390_arg11 = ret_val_sew_3391; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3390, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3391, 0, reinterpret_cast(this)); + setRet(call_sew_3391, 0, ret_val_sew_3391); + setArg(call_fp_vector_vector_op_3390, 0, V); + setArg(call_fp_vector_vector_op_3390, 1, 40); + setArg(call_fp_vector_vector_op_3390, 2, 1); + setArg(call_fp_vector_vector_op_3390, 3, fp_vector_vector_op_3390_arg3); + setArg(call_fp_vector_vector_op_3390, 4, fp_vector_vector_op_3390_arg4); + setArg(call_fp_vector_vector_op_3390, 5, fp_vector_vector_op_3390_arg5); + setArg(call_fp_vector_vector_op_3390, 6, vm); + setArg(call_fp_vector_vector_op_3390, 7, vd); + setArg(call_fp_vector_vector_op_3390, 8, vs2); + setArg(call_fp_vector_vector_op_3390, 9, vs1); + setArg(call_fp_vector_vector_op_3390, 10, fp_vector_vector_op_3390_arg10); + setArg(call_fp_vector_vector_op_3390, 11, fp_vector_vector_op_3390_arg11); + InvokeNode* call_fget_flags_3392; + x86::Gp ret_val_fget_flags_3392 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3392, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3392; + setRet(call_fget_flags_3392, 0, ret_val_fget_flags_3392); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3393 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3393, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3393, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 725); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 726: VFNMADD__VF */ + continuation_e __vfnmadd__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMADD__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 726); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3394; + x86::Gp ret_val_get_sew_pow_3394 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3394, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3395 = get_reg(cc, 8, false); + mov(cc, tmp3395, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3395, (ret_val_get_sew_pow_3394))), 8, false), ~ 1); + setArg(call_get_sew_pow_3394, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3394, 0, ret_val_get_sew_pow_3394); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3396; + auto illegal_fp_normal_3396_arg2 = SEW; + auto illegal_fp_normal_3396_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3396 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3396, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3396; + setArg(call_illegal_fp_normal_3396, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3396, 1, vd); + setArg(call_illegal_fp_normal_3396, 2, vm); + setArg(call_illegal_fp_normal_3396, 3, illegal_fp_normal_3396_arg2); + setArg(call_illegal_fp_normal_3396, 4, illegal_fp_normal_3396_arg3); + setRet(call_illegal_fp_normal_3396, 0, ret_val_illegal_fp_normal_3396); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3398; + x86::Gp ret_val_sew_3398 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3398, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3397; + auto fp_vector_imm_op_3397_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3397_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3397_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3397_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3397_arg10 = rm; + auto fp_vector_imm_op_3397_arg11 = ret_val_sew_3398; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3397, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3398, 0, reinterpret_cast(this)); + setRet(call_sew_3398, 0, ret_val_sew_3398); + setArg(call_fp_vector_imm_op_3397, 0, V); + setArg(call_fp_vector_imm_op_3397, 1, 41); + setArg(call_fp_vector_imm_op_3397, 2, 5); + setArg(call_fp_vector_imm_op_3397, 3, fp_vector_imm_op_3397_arg3); + setArg(call_fp_vector_imm_op_3397, 4, fp_vector_imm_op_3397_arg4); + setArg(call_fp_vector_imm_op_3397, 5, fp_vector_imm_op_3397_arg5); + setArg(call_fp_vector_imm_op_3397, 6, vm); + setArg(call_fp_vector_imm_op_3397, 7, vd); + setArg(call_fp_vector_imm_op_3397, 8, vs2); + setArg(call_fp_vector_imm_op_3397, 9, fp_vector_imm_op_3397_arg9); + setArg(call_fp_vector_imm_op_3397, 10, fp_vector_imm_op_3397_arg10); + setArg(call_fp_vector_imm_op_3397, 11, fp_vector_imm_op_3397_arg11); + InvokeNode* call_fget_flags_3399; + x86::Gp ret_val_fget_flags_3399 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3399, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3399; + setRet(call_fget_flags_3399, 0, ret_val_fget_flags_3399); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3400 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3400, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3400, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 726); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 727: VFNMADD__VV */ + continuation_e __vfnmadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 727); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3401; + x86::Gp ret_val_get_sew_pow_3401 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3401, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3402 = get_reg(cc, 8, false); + mov(cc, tmp3402, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3402, (ret_val_get_sew_pow_3401))), 8, false), ~ 1); + setArg(call_get_sew_pow_3401, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3401, 0, ret_val_get_sew_pow_3401); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3403; + auto illegal_fp_normal_3403_arg2 = SEW; + auto illegal_fp_normal_3403_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3403 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3403, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3403; + setArg(call_illegal_fp_normal_3403, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3403, 1, vd); + setArg(call_illegal_fp_normal_3403, 2, vm); + setArg(call_illegal_fp_normal_3403, 3, illegal_fp_normal_3403_arg2); + setArg(call_illegal_fp_normal_3403, 4, illegal_fp_normal_3403_arg3); + setRet(call_illegal_fp_normal_3403, 0, ret_val_illegal_fp_normal_3403); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3405; + x86::Gp ret_val_sew_3405 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3405, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3404; + auto fp_vector_vector_op_3404_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3404_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3404_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3404_arg10 = rm; + auto fp_vector_vector_op_3404_arg11 = ret_val_sew_3405; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3404, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3405, 0, reinterpret_cast(this)); + setRet(call_sew_3405, 0, ret_val_sew_3405); + setArg(call_fp_vector_vector_op_3404, 0, V); + setArg(call_fp_vector_vector_op_3404, 1, 41); + setArg(call_fp_vector_vector_op_3404, 2, 1); + setArg(call_fp_vector_vector_op_3404, 3, fp_vector_vector_op_3404_arg3); + setArg(call_fp_vector_vector_op_3404, 4, fp_vector_vector_op_3404_arg4); + setArg(call_fp_vector_vector_op_3404, 5, fp_vector_vector_op_3404_arg5); + setArg(call_fp_vector_vector_op_3404, 6, vm); + setArg(call_fp_vector_vector_op_3404, 7, vd); + setArg(call_fp_vector_vector_op_3404, 8, vs2); + setArg(call_fp_vector_vector_op_3404, 9, vs1); + setArg(call_fp_vector_vector_op_3404, 10, fp_vector_vector_op_3404_arg10); + setArg(call_fp_vector_vector_op_3404, 11, fp_vector_vector_op_3404_arg11); + InvokeNode* call_fget_flags_3406; + x86::Gp ret_val_fget_flags_3406 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3406, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3406; + setRet(call_fget_flags_3406, 0, ret_val_fget_flags_3406); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3407 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3407, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3407, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 727); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 728: VFMSUB__VF */ + continuation_e __vfmsub__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMSUB__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 728); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3408; + x86::Gp ret_val_get_sew_pow_3408 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3408, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3409 = get_reg(cc, 8, false); + mov(cc, tmp3409, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3409, (ret_val_get_sew_pow_3408))), 8, false), ~ 1); + setArg(call_get_sew_pow_3408, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3408, 0, ret_val_get_sew_pow_3408); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3410; + auto illegal_fp_normal_3410_arg2 = SEW; + auto illegal_fp_normal_3410_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3410 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3410, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3410; + setArg(call_illegal_fp_normal_3410, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3410, 1, vd); + setArg(call_illegal_fp_normal_3410, 2, vm); + setArg(call_illegal_fp_normal_3410, 3, illegal_fp_normal_3410_arg2); + setArg(call_illegal_fp_normal_3410, 4, illegal_fp_normal_3410_arg3); + setRet(call_illegal_fp_normal_3410, 0, ret_val_illegal_fp_normal_3410); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3412; + x86::Gp ret_val_sew_3412 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3412, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3411; + auto fp_vector_imm_op_3411_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3411_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3411_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3411_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3411_arg10 = rm; + auto fp_vector_imm_op_3411_arg11 = ret_val_sew_3412; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3411, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3412, 0, reinterpret_cast(this)); + setRet(call_sew_3412, 0, ret_val_sew_3412); + setArg(call_fp_vector_imm_op_3411, 0, V); + setArg(call_fp_vector_imm_op_3411, 1, 42); + setArg(call_fp_vector_imm_op_3411, 2, 5); + setArg(call_fp_vector_imm_op_3411, 3, fp_vector_imm_op_3411_arg3); + setArg(call_fp_vector_imm_op_3411, 4, fp_vector_imm_op_3411_arg4); + setArg(call_fp_vector_imm_op_3411, 5, fp_vector_imm_op_3411_arg5); + setArg(call_fp_vector_imm_op_3411, 6, vm); + setArg(call_fp_vector_imm_op_3411, 7, vd); + setArg(call_fp_vector_imm_op_3411, 8, vs2); + setArg(call_fp_vector_imm_op_3411, 9, fp_vector_imm_op_3411_arg9); + setArg(call_fp_vector_imm_op_3411, 10, fp_vector_imm_op_3411_arg10); + setArg(call_fp_vector_imm_op_3411, 11, fp_vector_imm_op_3411_arg11); + InvokeNode* call_fget_flags_3413; + x86::Gp ret_val_fget_flags_3413 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3413, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3413; + setRet(call_fget_flags_3413, 0, ret_val_fget_flags_3413); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3414 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3414, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3414, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 728); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 729: VFMSUB__VV */ + continuation_e __vfmsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 729); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3415; + x86::Gp ret_val_get_sew_pow_3415 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3415, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3416 = get_reg(cc, 8, false); + mov(cc, tmp3416, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3416, (ret_val_get_sew_pow_3415))), 8, false), ~ 1); + setArg(call_get_sew_pow_3415, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3415, 0, ret_val_get_sew_pow_3415); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3417; + auto illegal_fp_normal_3417_arg2 = SEW; + auto illegal_fp_normal_3417_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3417 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3417, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3417; + setArg(call_illegal_fp_normal_3417, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3417, 1, vd); + setArg(call_illegal_fp_normal_3417, 2, vm); + setArg(call_illegal_fp_normal_3417, 3, illegal_fp_normal_3417_arg2); + setArg(call_illegal_fp_normal_3417, 4, illegal_fp_normal_3417_arg3); + setRet(call_illegal_fp_normal_3417, 0, ret_val_illegal_fp_normal_3417); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3419; + x86::Gp ret_val_sew_3419 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3419, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3418; + auto fp_vector_vector_op_3418_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3418_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3418_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3418_arg10 = rm; + auto fp_vector_vector_op_3418_arg11 = ret_val_sew_3419; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3418, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3419, 0, reinterpret_cast(this)); + setRet(call_sew_3419, 0, ret_val_sew_3419); + setArg(call_fp_vector_vector_op_3418, 0, V); + setArg(call_fp_vector_vector_op_3418, 1, 42); + setArg(call_fp_vector_vector_op_3418, 2, 1); + setArg(call_fp_vector_vector_op_3418, 3, fp_vector_vector_op_3418_arg3); + setArg(call_fp_vector_vector_op_3418, 4, fp_vector_vector_op_3418_arg4); + setArg(call_fp_vector_vector_op_3418, 5, fp_vector_vector_op_3418_arg5); + setArg(call_fp_vector_vector_op_3418, 6, vm); + setArg(call_fp_vector_vector_op_3418, 7, vd); + setArg(call_fp_vector_vector_op_3418, 8, vs2); + setArg(call_fp_vector_vector_op_3418, 9, vs1); + setArg(call_fp_vector_vector_op_3418, 10, fp_vector_vector_op_3418_arg10); + setArg(call_fp_vector_vector_op_3418, 11, fp_vector_vector_op_3418_arg11); + InvokeNode* call_fget_flags_3420; + x86::Gp ret_val_fget_flags_3420 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3420, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3420; + setRet(call_fget_flags_3420, 0, ret_val_fget_flags_3420); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3421 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3421, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3421, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 729); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 730: VFNMSUB__VF */ + continuation_e __vfnmsub__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMSUB__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 730); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3422; + x86::Gp ret_val_get_sew_pow_3422 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3422, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3423 = get_reg(cc, 8, false); + mov(cc, tmp3423, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3423, (ret_val_get_sew_pow_3422))), 8, false), ~ 1); + setArg(call_get_sew_pow_3422, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3422, 0, ret_val_get_sew_pow_3422); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3424; + auto illegal_fp_normal_3424_arg2 = SEW; + auto illegal_fp_normal_3424_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3424 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3424, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3424; + setArg(call_illegal_fp_normal_3424, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3424, 1, vd); + setArg(call_illegal_fp_normal_3424, 2, vm); + setArg(call_illegal_fp_normal_3424, 3, illegal_fp_normal_3424_arg2); + setArg(call_illegal_fp_normal_3424, 4, illegal_fp_normal_3424_arg3); + setRet(call_illegal_fp_normal_3424, 0, ret_val_illegal_fp_normal_3424); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3426; + x86::Gp ret_val_sew_3426 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3426, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3425; + auto fp_vector_imm_op_3425_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3425_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3425_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3425_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3425_arg10 = rm; + auto fp_vector_imm_op_3425_arg11 = ret_val_sew_3426; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3425, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3426, 0, reinterpret_cast(this)); + setRet(call_sew_3426, 0, ret_val_sew_3426); + setArg(call_fp_vector_imm_op_3425, 0, V); + setArg(call_fp_vector_imm_op_3425, 1, 43); + setArg(call_fp_vector_imm_op_3425, 2, 5); + setArg(call_fp_vector_imm_op_3425, 3, fp_vector_imm_op_3425_arg3); + setArg(call_fp_vector_imm_op_3425, 4, fp_vector_imm_op_3425_arg4); + setArg(call_fp_vector_imm_op_3425, 5, fp_vector_imm_op_3425_arg5); + setArg(call_fp_vector_imm_op_3425, 6, vm); + setArg(call_fp_vector_imm_op_3425, 7, vd); + setArg(call_fp_vector_imm_op_3425, 8, vs2); + setArg(call_fp_vector_imm_op_3425, 9, fp_vector_imm_op_3425_arg9); + setArg(call_fp_vector_imm_op_3425, 10, fp_vector_imm_op_3425_arg10); + setArg(call_fp_vector_imm_op_3425, 11, fp_vector_imm_op_3425_arg11); + InvokeNode* call_fget_flags_3427; + x86::Gp ret_val_fget_flags_3427 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3427, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3427; + setRet(call_fget_flags_3427, 0, ret_val_fget_flags_3427); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3428 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3428, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3428, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 730); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 731: VFNMSUB__VV */ + continuation_e __vfnmsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 731); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3429; + x86::Gp ret_val_get_sew_pow_3429 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3429, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3430 = get_reg(cc, 8, false); + mov(cc, tmp3430, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3430, (ret_val_get_sew_pow_3429))), 8, false), ~ 1); + setArg(call_get_sew_pow_3429, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3429, 0, ret_val_get_sew_pow_3429); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3431; + auto illegal_fp_normal_3431_arg2 = SEW; + auto illegal_fp_normal_3431_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3431 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3431, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3431; + setArg(call_illegal_fp_normal_3431, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3431, 1, vd); + setArg(call_illegal_fp_normal_3431, 2, vm); + setArg(call_illegal_fp_normal_3431, 3, illegal_fp_normal_3431_arg2); + setArg(call_illegal_fp_normal_3431, 4, illegal_fp_normal_3431_arg3); + setRet(call_illegal_fp_normal_3431, 0, ret_val_illegal_fp_normal_3431); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3433; + x86::Gp ret_val_sew_3433 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3433, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3432; + auto fp_vector_vector_op_3432_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3432_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3432_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3432_arg10 = rm; + auto fp_vector_vector_op_3432_arg11 = ret_val_sew_3433; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3432, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3433, 0, reinterpret_cast(this)); + setRet(call_sew_3433, 0, ret_val_sew_3433); + setArg(call_fp_vector_vector_op_3432, 0, V); + setArg(call_fp_vector_vector_op_3432, 1, 43); + setArg(call_fp_vector_vector_op_3432, 2, 1); + setArg(call_fp_vector_vector_op_3432, 3, fp_vector_vector_op_3432_arg3); + setArg(call_fp_vector_vector_op_3432, 4, fp_vector_vector_op_3432_arg4); + setArg(call_fp_vector_vector_op_3432, 5, fp_vector_vector_op_3432_arg5); + setArg(call_fp_vector_vector_op_3432, 6, vm); + setArg(call_fp_vector_vector_op_3432, 7, vd); + setArg(call_fp_vector_vector_op_3432, 8, vs2); + setArg(call_fp_vector_vector_op_3432, 9, vs1); + setArg(call_fp_vector_vector_op_3432, 10, fp_vector_vector_op_3432_arg10); + setArg(call_fp_vector_vector_op_3432, 11, fp_vector_vector_op_3432_arg11); + InvokeNode* call_fget_flags_3434; + x86::Gp ret_val_fget_flags_3434 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3434, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3434; + setRet(call_fget_flags_3434, 0, ret_val_fget_flags_3434); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3435 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3435, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3435, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 731); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 732: VFWMACC__VF */ + continuation_e __vfwmacc__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMACC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 732); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3436; + x86::Gp ret_val_get_sew_pow_3436 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3436, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3437 = get_reg(cc, 8, false); + mov(cc, tmp3437, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3437, (ret_val_get_sew_pow_3436))), 8, false), ~ 1); + setArg(call_get_sew_pow_3436, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3436, 0, ret_val_get_sew_pow_3436); + InvokeNode* call_get_lmul_pow_3438; + x86::Gp ret_val_get_lmul_pow_3438 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3438, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3438; + setArg(call_get_lmul_pow_3438, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3438, 0, ret_val_get_lmul_pow_3438); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3439; + auto illegal_fp_variable_width_3439_arg2 = SEW; + auto illegal_fp_variable_width_3439_arg3 = rm; + auto illegal_fp_variable_width_3439_arg4 = SEW_widen; + auto illegal_fp_variable_width_3439_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3439 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3439, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3440; + auto valid_reg_overlap_3440_arg2 = LMUL_pow; + auto valid_reg_overlap_3440_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3440 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3440, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3439, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3440)); + setArg(call_illegal_fp_variable_width_3439, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3439, 1, vd); + setArg(call_illegal_fp_variable_width_3439, 2, vm); + setArg(call_illegal_fp_variable_width_3439, 3, illegal_fp_variable_width_3439_arg2); + setArg(call_illegal_fp_variable_width_3439, 4, illegal_fp_variable_width_3439_arg3); + setArg(call_illegal_fp_variable_width_3439, 5, illegal_fp_variable_width_3439_arg4); + setArg(call_illegal_fp_variable_width_3439, 6, illegal_fp_variable_width_3439_arg5); + setRet(call_illegal_fp_variable_width_3439, 0, ret_val_illegal_fp_variable_width_3439); + setArg(call_valid_reg_overlap_3440, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3440, 1, vs2); + setArg(call_valid_reg_overlap_3440, 2, vd); + setArg(call_valid_reg_overlap_3440, 3, valid_reg_overlap_3440_arg2); + setArg(call_valid_reg_overlap_3440, 4, valid_reg_overlap_3440_arg3); + setRet(call_valid_reg_overlap_3440, 0, ret_val_valid_reg_overlap_3440); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3442; + x86::Gp ret_val_sew_3442 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3442, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3441; + auto fp_vector_imm_wv_3441_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3441_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3441_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3441_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_wv_3441_arg10 = rm; + auto fp_vector_imm_wv_3441_arg11 = ret_val_sew_3442; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3441, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3442, 0, reinterpret_cast(this)); + setRet(call_sew_3442, 0, ret_val_sew_3442); + setArg(call_fp_vector_imm_wv_3441, 0, V); + setArg(call_fp_vector_imm_wv_3441, 1, 60); + setArg(call_fp_vector_imm_wv_3441, 2, 5); + setArg(call_fp_vector_imm_wv_3441, 3, fp_vector_imm_wv_3441_arg3); + setArg(call_fp_vector_imm_wv_3441, 4, fp_vector_imm_wv_3441_arg4); + setArg(call_fp_vector_imm_wv_3441, 5, fp_vector_imm_wv_3441_arg5); + setArg(call_fp_vector_imm_wv_3441, 6, vm); + setArg(call_fp_vector_imm_wv_3441, 7, vd); + setArg(call_fp_vector_imm_wv_3441, 8, vs2); + setArg(call_fp_vector_imm_wv_3441, 9, fp_vector_imm_wv_3441_arg9); + setArg(call_fp_vector_imm_wv_3441, 10, fp_vector_imm_wv_3441_arg10); + setArg(call_fp_vector_imm_wv_3441, 11, fp_vector_imm_wv_3441_arg11); + InvokeNode* call_fget_flags_3443; + x86::Gp ret_val_fget_flags_3443 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3443, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3443; + setRet(call_fget_flags_3443, 0, ret_val_fget_flags_3443); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3444 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3444, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3444, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 732); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 733: VFWMACC__VV */ + continuation_e __vfwmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 733); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3445; + x86::Gp ret_val_get_sew_pow_3445 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3445, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3446 = get_reg(cc, 8, false); + mov(cc, tmp3446, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3446, (ret_val_get_sew_pow_3445))), 8, false), ~ 1); + setArg(call_get_sew_pow_3445, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3445, 0, ret_val_get_sew_pow_3445); + InvokeNode* call_get_lmul_pow_3447; + x86::Gp ret_val_get_lmul_pow_3447 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3447, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3447; + setArg(call_get_lmul_pow_3447, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3447, 0, ret_val_get_lmul_pow_3447); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3448; + auto illegal_fp_variable_width_3448_arg2 = SEW; + auto illegal_fp_variable_width_3448_arg3 = rm; + auto illegal_fp_variable_width_3448_arg4 = SEW_widen; + auto illegal_fp_variable_width_3448_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3448 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3448, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3449; + auto valid_reg_overlap_3449_arg2 = LMUL_pow; + auto valid_reg_overlap_3449_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3449 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3449, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3450; + auto valid_reg_overlap_3450_arg2 = LMUL_pow; + auto valid_reg_overlap_3450_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3450 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3450, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3448, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3449)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3450)); + setArg(call_illegal_fp_variable_width_3448, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3448, 1, vd); + setArg(call_illegal_fp_variable_width_3448, 2, vm); + setArg(call_illegal_fp_variable_width_3448, 3, illegal_fp_variable_width_3448_arg2); + setArg(call_illegal_fp_variable_width_3448, 4, illegal_fp_variable_width_3448_arg3); + setArg(call_illegal_fp_variable_width_3448, 5, illegal_fp_variable_width_3448_arg4); + setArg(call_illegal_fp_variable_width_3448, 6, illegal_fp_variable_width_3448_arg5); + setRet(call_illegal_fp_variable_width_3448, 0, ret_val_illegal_fp_variable_width_3448); + setArg(call_valid_reg_overlap_3449, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3449, 1, vs1); + setArg(call_valid_reg_overlap_3449, 2, vd); + setArg(call_valid_reg_overlap_3449, 3, valid_reg_overlap_3449_arg2); + setArg(call_valid_reg_overlap_3449, 4, valid_reg_overlap_3449_arg3); + setRet(call_valid_reg_overlap_3449, 0, ret_val_valid_reg_overlap_3449); + setArg(call_valid_reg_overlap_3450, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3450, 1, vs2); + setArg(call_valid_reg_overlap_3450, 2, vd); + setArg(call_valid_reg_overlap_3450, 3, valid_reg_overlap_3450_arg2); + setArg(call_valid_reg_overlap_3450, 4, valid_reg_overlap_3450_arg3); + setRet(call_valid_reg_overlap_3450, 0, ret_val_valid_reg_overlap_3450); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3452; + x86::Gp ret_val_sew_3452 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3452, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3451; + auto fp_vector_vector_wv_3451_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3451_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3451_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3451_arg10 = rm; + auto fp_vector_vector_wv_3451_arg11 = ret_val_sew_3452; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3451, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3452, 0, reinterpret_cast(this)); + setRet(call_sew_3452, 0, ret_val_sew_3452); + setArg(call_fp_vector_vector_wv_3451, 0, V); + setArg(call_fp_vector_vector_wv_3451, 1, 60); + setArg(call_fp_vector_vector_wv_3451, 2, 1); + setArg(call_fp_vector_vector_wv_3451, 3, fp_vector_vector_wv_3451_arg3); + setArg(call_fp_vector_vector_wv_3451, 4, fp_vector_vector_wv_3451_arg4); + setArg(call_fp_vector_vector_wv_3451, 5, fp_vector_vector_wv_3451_arg5); + setArg(call_fp_vector_vector_wv_3451, 6, vm); + setArg(call_fp_vector_vector_wv_3451, 7, vd); + setArg(call_fp_vector_vector_wv_3451, 8, vs2); + setArg(call_fp_vector_vector_wv_3451, 9, vs1); + setArg(call_fp_vector_vector_wv_3451, 10, fp_vector_vector_wv_3451_arg10); + setArg(call_fp_vector_vector_wv_3451, 11, fp_vector_vector_wv_3451_arg11); + InvokeNode* call_fget_flags_3453; + x86::Gp ret_val_fget_flags_3453 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3453, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3453; + setRet(call_fget_flags_3453, 0, ret_val_fget_flags_3453); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3454 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3454, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3454, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 733); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 734: VFWNMACC__VF */ + continuation_e __vfwnmacc__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwnmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWNMACC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 734); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3455; + x86::Gp ret_val_get_sew_pow_3455 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3455, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3456 = get_reg(cc, 8, false); + mov(cc, tmp3456, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3456, (ret_val_get_sew_pow_3455))), 8, false), ~ 1); + setArg(call_get_sew_pow_3455, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3455, 0, ret_val_get_sew_pow_3455); + InvokeNode* call_get_lmul_pow_3457; + x86::Gp ret_val_get_lmul_pow_3457 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3457, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3457; + setArg(call_get_lmul_pow_3457, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3457, 0, ret_val_get_lmul_pow_3457); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3458; + auto illegal_fp_variable_width_3458_arg2 = SEW; + auto illegal_fp_variable_width_3458_arg3 = rm; + auto illegal_fp_variable_width_3458_arg4 = SEW_widen; + auto illegal_fp_variable_width_3458_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3458 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3458, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3459; + auto valid_reg_overlap_3459_arg2 = LMUL_pow; + auto valid_reg_overlap_3459_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3459 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3459, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3458, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3459)); + setArg(call_illegal_fp_variable_width_3458, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3458, 1, vd); + setArg(call_illegal_fp_variable_width_3458, 2, vm); + setArg(call_illegal_fp_variable_width_3458, 3, illegal_fp_variable_width_3458_arg2); + setArg(call_illegal_fp_variable_width_3458, 4, illegal_fp_variable_width_3458_arg3); + setArg(call_illegal_fp_variable_width_3458, 5, illegal_fp_variable_width_3458_arg4); + setArg(call_illegal_fp_variable_width_3458, 6, illegal_fp_variable_width_3458_arg5); + setRet(call_illegal_fp_variable_width_3458, 0, ret_val_illegal_fp_variable_width_3458); + setArg(call_valid_reg_overlap_3459, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3459, 1, vs2); + setArg(call_valid_reg_overlap_3459, 2, vd); + setArg(call_valid_reg_overlap_3459, 3, valid_reg_overlap_3459_arg2); + setArg(call_valid_reg_overlap_3459, 4, valid_reg_overlap_3459_arg3); + setRet(call_valid_reg_overlap_3459, 0, ret_val_valid_reg_overlap_3459); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3461; + x86::Gp ret_val_sew_3461 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3461, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3460; + auto fp_vector_imm_wv_3460_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3460_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3460_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3460_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_wv_3460_arg10 = rm; + auto fp_vector_imm_wv_3460_arg11 = ret_val_sew_3461; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3460, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3461, 0, reinterpret_cast(this)); + setRet(call_sew_3461, 0, ret_val_sew_3461); + setArg(call_fp_vector_imm_wv_3460, 0, V); + setArg(call_fp_vector_imm_wv_3460, 1, 61); + setArg(call_fp_vector_imm_wv_3460, 2, 5); + setArg(call_fp_vector_imm_wv_3460, 3, fp_vector_imm_wv_3460_arg3); + setArg(call_fp_vector_imm_wv_3460, 4, fp_vector_imm_wv_3460_arg4); + setArg(call_fp_vector_imm_wv_3460, 5, fp_vector_imm_wv_3460_arg5); + setArg(call_fp_vector_imm_wv_3460, 6, vm); + setArg(call_fp_vector_imm_wv_3460, 7, vd); + setArg(call_fp_vector_imm_wv_3460, 8, vs2); + setArg(call_fp_vector_imm_wv_3460, 9, fp_vector_imm_wv_3460_arg9); + setArg(call_fp_vector_imm_wv_3460, 10, fp_vector_imm_wv_3460_arg10); + setArg(call_fp_vector_imm_wv_3460, 11, fp_vector_imm_wv_3460_arg11); + InvokeNode* call_fget_flags_3462; + x86::Gp ret_val_fget_flags_3462 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3462, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3462; + setRet(call_fget_flags_3462, 0, ret_val_fget_flags_3462); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3463 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3463, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3463, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 734); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 735: VFWNMACC__VV */ + continuation_e __vfwnmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwnmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWNMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 735); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3464; + x86::Gp ret_val_get_sew_pow_3464 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3464, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3465 = get_reg(cc, 8, false); + mov(cc, tmp3465, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3465, (ret_val_get_sew_pow_3464))), 8, false), ~ 1); + setArg(call_get_sew_pow_3464, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3464, 0, ret_val_get_sew_pow_3464); + InvokeNode* call_get_lmul_pow_3466; + x86::Gp ret_val_get_lmul_pow_3466 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3466, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3466; + setArg(call_get_lmul_pow_3466, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3466, 0, ret_val_get_lmul_pow_3466); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3467; + auto illegal_fp_variable_width_3467_arg2 = SEW; + auto illegal_fp_variable_width_3467_arg3 = rm; + auto illegal_fp_variable_width_3467_arg4 = SEW_widen; + auto illegal_fp_variable_width_3467_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3467 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3467, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3468; + auto valid_reg_overlap_3468_arg2 = LMUL_pow; + auto valid_reg_overlap_3468_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3468 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3468, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3469; + auto valid_reg_overlap_3469_arg2 = LMUL_pow; + auto valid_reg_overlap_3469_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3469 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3469, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3467, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3468)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3469)); + setArg(call_illegal_fp_variable_width_3467, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3467, 1, vd); + setArg(call_illegal_fp_variable_width_3467, 2, vm); + setArg(call_illegal_fp_variable_width_3467, 3, illegal_fp_variable_width_3467_arg2); + setArg(call_illegal_fp_variable_width_3467, 4, illegal_fp_variable_width_3467_arg3); + setArg(call_illegal_fp_variable_width_3467, 5, illegal_fp_variable_width_3467_arg4); + setArg(call_illegal_fp_variable_width_3467, 6, illegal_fp_variable_width_3467_arg5); + setRet(call_illegal_fp_variable_width_3467, 0, ret_val_illegal_fp_variable_width_3467); + setArg(call_valid_reg_overlap_3468, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3468, 1, vs1); + setArg(call_valid_reg_overlap_3468, 2, vd); + setArg(call_valid_reg_overlap_3468, 3, valid_reg_overlap_3468_arg2); + setArg(call_valid_reg_overlap_3468, 4, valid_reg_overlap_3468_arg3); + setRet(call_valid_reg_overlap_3468, 0, ret_val_valid_reg_overlap_3468); + setArg(call_valid_reg_overlap_3469, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3469, 1, vs2); + setArg(call_valid_reg_overlap_3469, 2, vd); + setArg(call_valid_reg_overlap_3469, 3, valid_reg_overlap_3469_arg2); + setArg(call_valid_reg_overlap_3469, 4, valid_reg_overlap_3469_arg3); + setRet(call_valid_reg_overlap_3469, 0, ret_val_valid_reg_overlap_3469); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3471; + x86::Gp ret_val_sew_3471 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3471, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3470; + auto fp_vector_vector_wv_3470_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3470_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3470_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3470_arg10 = rm; + auto fp_vector_vector_wv_3470_arg11 = ret_val_sew_3471; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3470, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3471, 0, reinterpret_cast(this)); + setRet(call_sew_3471, 0, ret_val_sew_3471); + setArg(call_fp_vector_vector_wv_3470, 0, V); + setArg(call_fp_vector_vector_wv_3470, 1, 61); + setArg(call_fp_vector_vector_wv_3470, 2, 1); + setArg(call_fp_vector_vector_wv_3470, 3, fp_vector_vector_wv_3470_arg3); + setArg(call_fp_vector_vector_wv_3470, 4, fp_vector_vector_wv_3470_arg4); + setArg(call_fp_vector_vector_wv_3470, 5, fp_vector_vector_wv_3470_arg5); + setArg(call_fp_vector_vector_wv_3470, 6, vm); + setArg(call_fp_vector_vector_wv_3470, 7, vd); + setArg(call_fp_vector_vector_wv_3470, 8, vs2); + setArg(call_fp_vector_vector_wv_3470, 9, vs1); + setArg(call_fp_vector_vector_wv_3470, 10, fp_vector_vector_wv_3470_arg10); + setArg(call_fp_vector_vector_wv_3470, 11, fp_vector_vector_wv_3470_arg11); + InvokeNode* call_fget_flags_3472; + x86::Gp ret_val_fget_flags_3472 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3472, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3472; + setRet(call_fget_flags_3472, 0, ret_val_fget_flags_3472); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3473 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3473, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3473, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 735); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 736: VFWMSAC__VF */ + continuation_e __vfwmsac__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMSAC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 736); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3474; + x86::Gp ret_val_get_sew_pow_3474 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3474, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3475 = get_reg(cc, 8, false); + mov(cc, tmp3475, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3475, (ret_val_get_sew_pow_3474))), 8, false), ~ 1); + setArg(call_get_sew_pow_3474, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3474, 0, ret_val_get_sew_pow_3474); + InvokeNode* call_get_lmul_pow_3476; + x86::Gp ret_val_get_lmul_pow_3476 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3476, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3476; + setArg(call_get_lmul_pow_3476, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3476, 0, ret_val_get_lmul_pow_3476); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3477; + auto illegal_fp_variable_width_3477_arg2 = SEW; + auto illegal_fp_variable_width_3477_arg3 = rm; + auto illegal_fp_variable_width_3477_arg4 = SEW_widen; + auto illegal_fp_variable_width_3477_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3477 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3477, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3478; + auto valid_reg_overlap_3478_arg2 = LMUL_pow; + auto valid_reg_overlap_3478_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3478 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3478, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3477, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3478)); + setArg(call_illegal_fp_variable_width_3477, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3477, 1, vd); + setArg(call_illegal_fp_variable_width_3477, 2, vm); + setArg(call_illegal_fp_variable_width_3477, 3, illegal_fp_variable_width_3477_arg2); + setArg(call_illegal_fp_variable_width_3477, 4, illegal_fp_variable_width_3477_arg3); + setArg(call_illegal_fp_variable_width_3477, 5, illegal_fp_variable_width_3477_arg4); + setArg(call_illegal_fp_variable_width_3477, 6, illegal_fp_variable_width_3477_arg5); + setRet(call_illegal_fp_variable_width_3477, 0, ret_val_illegal_fp_variable_width_3477); + setArg(call_valid_reg_overlap_3478, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3478, 1, vs2); + setArg(call_valid_reg_overlap_3478, 2, vd); + setArg(call_valid_reg_overlap_3478, 3, valid_reg_overlap_3478_arg2); + setArg(call_valid_reg_overlap_3478, 4, valid_reg_overlap_3478_arg3); + setRet(call_valid_reg_overlap_3478, 0, ret_val_valid_reg_overlap_3478); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3480; + x86::Gp ret_val_sew_3480 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3480, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3479; + auto fp_vector_imm_wv_3479_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3479_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3479_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3479_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_wv_3479_arg10 = rm; + auto fp_vector_imm_wv_3479_arg11 = ret_val_sew_3480; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3479, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3480, 0, reinterpret_cast(this)); + setRet(call_sew_3480, 0, ret_val_sew_3480); + setArg(call_fp_vector_imm_wv_3479, 0, V); + setArg(call_fp_vector_imm_wv_3479, 1, 62); + setArg(call_fp_vector_imm_wv_3479, 2, 5); + setArg(call_fp_vector_imm_wv_3479, 3, fp_vector_imm_wv_3479_arg3); + setArg(call_fp_vector_imm_wv_3479, 4, fp_vector_imm_wv_3479_arg4); + setArg(call_fp_vector_imm_wv_3479, 5, fp_vector_imm_wv_3479_arg5); + setArg(call_fp_vector_imm_wv_3479, 6, vm); + setArg(call_fp_vector_imm_wv_3479, 7, vd); + setArg(call_fp_vector_imm_wv_3479, 8, vs2); + setArg(call_fp_vector_imm_wv_3479, 9, fp_vector_imm_wv_3479_arg9); + setArg(call_fp_vector_imm_wv_3479, 10, fp_vector_imm_wv_3479_arg10); + setArg(call_fp_vector_imm_wv_3479, 11, fp_vector_imm_wv_3479_arg11); + InvokeNode* call_fget_flags_3481; + x86::Gp ret_val_fget_flags_3481 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3481, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3481; + setRet(call_fget_flags_3481, 0, ret_val_fget_flags_3481); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3482 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3482, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3482, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 736); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 737: VFWMSAC__VV */ + continuation_e __vfwmsac__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMSAC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 737); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3483; + x86::Gp ret_val_get_sew_pow_3483 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3483, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3484 = get_reg(cc, 8, false); + mov(cc, tmp3484, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3484, (ret_val_get_sew_pow_3483))), 8, false), ~ 1); + setArg(call_get_sew_pow_3483, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3483, 0, ret_val_get_sew_pow_3483); + InvokeNode* call_get_lmul_pow_3485; + x86::Gp ret_val_get_lmul_pow_3485 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3485, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3485; + setArg(call_get_lmul_pow_3485, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3485, 0, ret_val_get_lmul_pow_3485); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3486; + auto illegal_fp_variable_width_3486_arg2 = SEW; + auto illegal_fp_variable_width_3486_arg3 = rm; + auto illegal_fp_variable_width_3486_arg4 = SEW_widen; + auto illegal_fp_variable_width_3486_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3486 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3486, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3487; + auto valid_reg_overlap_3487_arg2 = LMUL_pow; + auto valid_reg_overlap_3487_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3487 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3487, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3488; + auto valid_reg_overlap_3488_arg2 = LMUL_pow; + auto valid_reg_overlap_3488_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3488 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3488, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3486, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3487)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3488)); + setArg(call_illegal_fp_variable_width_3486, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3486, 1, vd); + setArg(call_illegal_fp_variable_width_3486, 2, vm); + setArg(call_illegal_fp_variable_width_3486, 3, illegal_fp_variable_width_3486_arg2); + setArg(call_illegal_fp_variable_width_3486, 4, illegal_fp_variable_width_3486_arg3); + setArg(call_illegal_fp_variable_width_3486, 5, illegal_fp_variable_width_3486_arg4); + setArg(call_illegal_fp_variable_width_3486, 6, illegal_fp_variable_width_3486_arg5); + setRet(call_illegal_fp_variable_width_3486, 0, ret_val_illegal_fp_variable_width_3486); + setArg(call_valid_reg_overlap_3487, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3487, 1, vs1); + setArg(call_valid_reg_overlap_3487, 2, vd); + setArg(call_valid_reg_overlap_3487, 3, valid_reg_overlap_3487_arg2); + setArg(call_valid_reg_overlap_3487, 4, valid_reg_overlap_3487_arg3); + setRet(call_valid_reg_overlap_3487, 0, ret_val_valid_reg_overlap_3487); + setArg(call_valid_reg_overlap_3488, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3488, 1, vs2); + setArg(call_valid_reg_overlap_3488, 2, vd); + setArg(call_valid_reg_overlap_3488, 3, valid_reg_overlap_3488_arg2); + setArg(call_valid_reg_overlap_3488, 4, valid_reg_overlap_3488_arg3); + setRet(call_valid_reg_overlap_3488, 0, ret_val_valid_reg_overlap_3488); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3490; + x86::Gp ret_val_sew_3490 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3490, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3489; + auto fp_vector_vector_wv_3489_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3489_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3489_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3489_arg10 = rm; + auto fp_vector_vector_wv_3489_arg11 = ret_val_sew_3490; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3489, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3490, 0, reinterpret_cast(this)); + setRet(call_sew_3490, 0, ret_val_sew_3490); + setArg(call_fp_vector_vector_wv_3489, 0, V); + setArg(call_fp_vector_vector_wv_3489, 1, 62); + setArg(call_fp_vector_vector_wv_3489, 2, 1); + setArg(call_fp_vector_vector_wv_3489, 3, fp_vector_vector_wv_3489_arg3); + setArg(call_fp_vector_vector_wv_3489, 4, fp_vector_vector_wv_3489_arg4); + setArg(call_fp_vector_vector_wv_3489, 5, fp_vector_vector_wv_3489_arg5); + setArg(call_fp_vector_vector_wv_3489, 6, vm); + setArg(call_fp_vector_vector_wv_3489, 7, vd); + setArg(call_fp_vector_vector_wv_3489, 8, vs2); + setArg(call_fp_vector_vector_wv_3489, 9, vs1); + setArg(call_fp_vector_vector_wv_3489, 10, fp_vector_vector_wv_3489_arg10); + setArg(call_fp_vector_vector_wv_3489, 11, fp_vector_vector_wv_3489_arg11); + InvokeNode* call_fget_flags_3491; + x86::Gp ret_val_fget_flags_3491 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3491, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3491; + setRet(call_fget_flags_3491, 0, ret_val_fget_flags_3491); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3492 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3492, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3492, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 737); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 738: VFWNMSAC__VF */ + continuation_e __vfwnmsac__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwnmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWNMSAC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 738); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3493; + x86::Gp ret_val_get_sew_pow_3493 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3493, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3494 = get_reg(cc, 8, false); + mov(cc, tmp3494, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3494, (ret_val_get_sew_pow_3493))), 8, false), ~ 1); + setArg(call_get_sew_pow_3493, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3493, 0, ret_val_get_sew_pow_3493); + InvokeNode* call_get_lmul_pow_3495; + x86::Gp ret_val_get_lmul_pow_3495 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3495, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3495; + setArg(call_get_lmul_pow_3495, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3495, 0, ret_val_get_lmul_pow_3495); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3496; + auto illegal_fp_variable_width_3496_arg2 = SEW; + auto illegal_fp_variable_width_3496_arg3 = rm; + auto illegal_fp_variable_width_3496_arg4 = SEW_widen; + auto illegal_fp_variable_width_3496_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3496 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3496, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3497; + auto valid_reg_overlap_3497_arg2 = LMUL_pow; + auto valid_reg_overlap_3497_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3497 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3497, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3496, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3497)); + setArg(call_illegal_fp_variable_width_3496, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3496, 1, vd); + setArg(call_illegal_fp_variable_width_3496, 2, vm); + setArg(call_illegal_fp_variable_width_3496, 3, illegal_fp_variable_width_3496_arg2); + setArg(call_illegal_fp_variable_width_3496, 4, illegal_fp_variable_width_3496_arg3); + setArg(call_illegal_fp_variable_width_3496, 5, illegal_fp_variable_width_3496_arg4); + setArg(call_illegal_fp_variable_width_3496, 6, illegal_fp_variable_width_3496_arg5); + setRet(call_illegal_fp_variable_width_3496, 0, ret_val_illegal_fp_variable_width_3496); + setArg(call_valid_reg_overlap_3497, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3497, 1, vs2); + setArg(call_valid_reg_overlap_3497, 2, vd); + setArg(call_valid_reg_overlap_3497, 3, valid_reg_overlap_3497_arg2); + setArg(call_valid_reg_overlap_3497, 4, valid_reg_overlap_3497_arg3); + setRet(call_valid_reg_overlap_3497, 0, ret_val_valid_reg_overlap_3497); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3499; + x86::Gp ret_val_sew_3499 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3499, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3498; + auto fp_vector_imm_wv_3498_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3498_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3498_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3498_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_wv_3498_arg10 = rm; + auto fp_vector_imm_wv_3498_arg11 = ret_val_sew_3499; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3498, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3499, 0, reinterpret_cast(this)); + setRet(call_sew_3499, 0, ret_val_sew_3499); + setArg(call_fp_vector_imm_wv_3498, 0, V); + setArg(call_fp_vector_imm_wv_3498, 1, 63); + setArg(call_fp_vector_imm_wv_3498, 2, 5); + setArg(call_fp_vector_imm_wv_3498, 3, fp_vector_imm_wv_3498_arg3); + setArg(call_fp_vector_imm_wv_3498, 4, fp_vector_imm_wv_3498_arg4); + setArg(call_fp_vector_imm_wv_3498, 5, fp_vector_imm_wv_3498_arg5); + setArg(call_fp_vector_imm_wv_3498, 6, vm); + setArg(call_fp_vector_imm_wv_3498, 7, vd); + setArg(call_fp_vector_imm_wv_3498, 8, vs2); + setArg(call_fp_vector_imm_wv_3498, 9, fp_vector_imm_wv_3498_arg9); + setArg(call_fp_vector_imm_wv_3498, 10, fp_vector_imm_wv_3498_arg10); + setArg(call_fp_vector_imm_wv_3498, 11, fp_vector_imm_wv_3498_arg11); + InvokeNode* call_fget_flags_3500; + x86::Gp ret_val_fget_flags_3500 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3500, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3500; + setRet(call_fget_flags_3500, 0, ret_val_fget_flags_3500); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3501 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3501, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3501, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 738); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 739: VFWNMSAC__VV */ + continuation_e __vfwnmsac__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWNMSAC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 739); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3502; + x86::Gp ret_val_get_sew_pow_3502 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3502, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3503 = get_reg(cc, 8, false); + mov(cc, tmp3503, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3503, (ret_val_get_sew_pow_3502))), 8, false), ~ 1); + setArg(call_get_sew_pow_3502, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3502, 0, ret_val_get_sew_pow_3502); + InvokeNode* call_get_lmul_pow_3504; + x86::Gp ret_val_get_lmul_pow_3504 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3504, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3504; + setArg(call_get_lmul_pow_3504, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3504, 0, ret_val_get_lmul_pow_3504); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3505; + auto illegal_fp_variable_width_3505_arg2 = SEW; + auto illegal_fp_variable_width_3505_arg3 = rm; + auto illegal_fp_variable_width_3505_arg4 = SEW_widen; + auto illegal_fp_variable_width_3505_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3505 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3505, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3506; + auto valid_reg_overlap_3506_arg2 = LMUL_pow; + auto valid_reg_overlap_3506_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3506 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3506, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3507; + auto valid_reg_overlap_3507_arg2 = LMUL_pow; + auto valid_reg_overlap_3507_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3507 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3507, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3505, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3506)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3507)); + setArg(call_illegal_fp_variable_width_3505, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3505, 1, vd); + setArg(call_illegal_fp_variable_width_3505, 2, vm); + setArg(call_illegal_fp_variable_width_3505, 3, illegal_fp_variable_width_3505_arg2); + setArg(call_illegal_fp_variable_width_3505, 4, illegal_fp_variable_width_3505_arg3); + setArg(call_illegal_fp_variable_width_3505, 5, illegal_fp_variable_width_3505_arg4); + setArg(call_illegal_fp_variable_width_3505, 6, illegal_fp_variable_width_3505_arg5); + setRet(call_illegal_fp_variable_width_3505, 0, ret_val_illegal_fp_variable_width_3505); + setArg(call_valid_reg_overlap_3506, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3506, 1, vs1); + setArg(call_valid_reg_overlap_3506, 2, vd); + setArg(call_valid_reg_overlap_3506, 3, valid_reg_overlap_3506_arg2); + setArg(call_valid_reg_overlap_3506, 4, valid_reg_overlap_3506_arg3); + setRet(call_valid_reg_overlap_3506, 0, ret_val_valid_reg_overlap_3506); + setArg(call_valid_reg_overlap_3507, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3507, 1, vs2); + setArg(call_valid_reg_overlap_3507, 2, vd); + setArg(call_valid_reg_overlap_3507, 3, valid_reg_overlap_3507_arg2); + setArg(call_valid_reg_overlap_3507, 4, valid_reg_overlap_3507_arg3); + setRet(call_valid_reg_overlap_3507, 0, ret_val_valid_reg_overlap_3507); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3509; + x86::Gp ret_val_sew_3509 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3509, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3508; + auto fp_vector_vector_wv_3508_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3508_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3508_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3508_arg10 = rm; + auto fp_vector_vector_wv_3508_arg11 = ret_val_sew_3509; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3508, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3509, 0, reinterpret_cast(this)); + setRet(call_sew_3509, 0, ret_val_sew_3509); + setArg(call_fp_vector_vector_wv_3508, 0, V); + setArg(call_fp_vector_vector_wv_3508, 1, 63); + setArg(call_fp_vector_vector_wv_3508, 2, 1); + setArg(call_fp_vector_vector_wv_3508, 3, fp_vector_vector_wv_3508_arg3); + setArg(call_fp_vector_vector_wv_3508, 4, fp_vector_vector_wv_3508_arg4); + setArg(call_fp_vector_vector_wv_3508, 5, fp_vector_vector_wv_3508_arg5); + setArg(call_fp_vector_vector_wv_3508, 6, vm); + setArg(call_fp_vector_vector_wv_3508, 7, vd); + setArg(call_fp_vector_vector_wv_3508, 8, vs2); + setArg(call_fp_vector_vector_wv_3508, 9, vs1); + setArg(call_fp_vector_vector_wv_3508, 10, fp_vector_vector_wv_3508_arg10); + setArg(call_fp_vector_vector_wv_3508, 11, fp_vector_vector_wv_3508_arg11); + InvokeNode* call_fget_flags_3510; + x86::Gp ret_val_fget_flags_3510 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3510, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3510; + setRet(call_fget_flags_3510, 0, ret_val_fget_flags_3510); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3511 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3511, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3511, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 739); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 740: VFSQRT__V */ + continuation_e __vfsqrt__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfsqrt.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSQRT__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 740); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3512; + x86::Gp ret_val_get_sew_pow_3512 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3512, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3513 = get_reg(cc, 8, false); + mov(cc, tmp3513, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3513, (ret_val_get_sew_pow_3512))), 8, false), ~ 1); + setArg(call_get_sew_pow_3512, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3512, 0, ret_val_get_sew_pow_3512); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3514; + auto illegal_fp_normal_3514_arg2 = SEW; + auto illegal_fp_normal_3514_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3514 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3514, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3514; + setArg(call_illegal_fp_normal_3514, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3514, 1, vd); + setArg(call_illegal_fp_normal_3514, 2, vm); + setArg(call_illegal_fp_normal_3514, 3, illegal_fp_normal_3514_arg2); + setArg(call_illegal_fp_normal_3514, 4, illegal_fp_normal_3514_arg3); + setRet(call_illegal_fp_normal_3514, 0, ret_val_illegal_fp_normal_3514); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3516; + x86::Gp ret_val_sew_3516 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3516, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3515; + auto fp_vector_unary_op_3515_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3515_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3515_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3515_arg9 = rm; + auto fp_vector_unary_op_3515_arg10 = ret_val_sew_3516; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3515, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3516, 0, reinterpret_cast(this)); + setRet(call_sew_3516, 0, ret_val_sew_3516); + setArg(call_fp_vector_unary_op_3515, 0, V); + setArg(call_fp_vector_unary_op_3515, 1, 19); + setArg(call_fp_vector_unary_op_3515, 2, 0); + setArg(call_fp_vector_unary_op_3515, 3, fp_vector_unary_op_3515_arg3); + setArg(call_fp_vector_unary_op_3515, 4, fp_vector_unary_op_3515_arg4); + setArg(call_fp_vector_unary_op_3515, 5, fp_vector_unary_op_3515_arg5); + setArg(call_fp_vector_unary_op_3515, 6, vm); + setArg(call_fp_vector_unary_op_3515, 7, vd); + setArg(call_fp_vector_unary_op_3515, 8, vs2); + setArg(call_fp_vector_unary_op_3515, 9, fp_vector_unary_op_3515_arg9); + setArg(call_fp_vector_unary_op_3515, 10, fp_vector_unary_op_3515_arg10); + InvokeNode* call_fget_flags_3517; + x86::Gp ret_val_fget_flags_3517 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3517, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3517; + setRet(call_fget_flags_3517, 0, ret_val_fget_flags_3517); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3518 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3518, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3518, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 740); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 741: VFRSQRT7__V */ + continuation_e __vfrsqrt7__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfrsqrt7.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFRSQRT7__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 741); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3519; + x86::Gp ret_val_get_sew_pow_3519 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3519, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3520 = get_reg(cc, 8, false); + mov(cc, tmp3520, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3520, (ret_val_get_sew_pow_3519))), 8, false), ~ 1); + setArg(call_get_sew_pow_3519, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3519, 0, ret_val_get_sew_pow_3519); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3521; + auto illegal_fp_normal_3521_arg2 = SEW; + auto illegal_fp_normal_3521_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3521 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3521, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3521; + setArg(call_illegal_fp_normal_3521, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3521, 1, vd); + setArg(call_illegal_fp_normal_3521, 2, vm); + setArg(call_illegal_fp_normal_3521, 3, illegal_fp_normal_3521_arg2); + setArg(call_illegal_fp_normal_3521, 4, illegal_fp_normal_3521_arg3); + setRet(call_illegal_fp_normal_3521, 0, ret_val_illegal_fp_normal_3521); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3523; + x86::Gp ret_val_sew_3523 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3523, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3522; + auto fp_vector_unary_op_3522_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3522_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3522_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3522_arg9 = rm; + auto fp_vector_unary_op_3522_arg10 = ret_val_sew_3523; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3522, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3523, 0, reinterpret_cast(this)); + setRet(call_sew_3523, 0, ret_val_sew_3523); + setArg(call_fp_vector_unary_op_3522, 0, V); + setArg(call_fp_vector_unary_op_3522, 1, 19); + setArg(call_fp_vector_unary_op_3522, 2, 4); + setArg(call_fp_vector_unary_op_3522, 3, fp_vector_unary_op_3522_arg3); + setArg(call_fp_vector_unary_op_3522, 4, fp_vector_unary_op_3522_arg4); + setArg(call_fp_vector_unary_op_3522, 5, fp_vector_unary_op_3522_arg5); + setArg(call_fp_vector_unary_op_3522, 6, vm); + setArg(call_fp_vector_unary_op_3522, 7, vd); + setArg(call_fp_vector_unary_op_3522, 8, vs2); + setArg(call_fp_vector_unary_op_3522, 9, fp_vector_unary_op_3522_arg9); + setArg(call_fp_vector_unary_op_3522, 10, fp_vector_unary_op_3522_arg10); + InvokeNode* call_fget_flags_3524; + x86::Gp ret_val_fget_flags_3524 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3524, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3524; + setRet(call_fget_flags_3524, 0, ret_val_fget_flags_3524); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3525 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3525, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3525, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 741); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 742: VFREC7__V */ + continuation_e __vfrec7__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfrec7.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFREC7__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 742); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3526; + x86::Gp ret_val_get_sew_pow_3526 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3526, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3527 = get_reg(cc, 8, false); + mov(cc, tmp3527, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3527, (ret_val_get_sew_pow_3526))), 8, false), ~ 1); + setArg(call_get_sew_pow_3526, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3526, 0, ret_val_get_sew_pow_3526); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3528; + auto illegal_fp_normal_3528_arg2 = SEW; + auto illegal_fp_normal_3528_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3528 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3528, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3528; + setArg(call_illegal_fp_normal_3528, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3528, 1, vd); + setArg(call_illegal_fp_normal_3528, 2, vm); + setArg(call_illegal_fp_normal_3528, 3, illegal_fp_normal_3528_arg2); + setArg(call_illegal_fp_normal_3528, 4, illegal_fp_normal_3528_arg3); + setRet(call_illegal_fp_normal_3528, 0, ret_val_illegal_fp_normal_3528); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3530; + x86::Gp ret_val_sew_3530 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3530, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3529; + auto fp_vector_unary_op_3529_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3529_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3529_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3529_arg9 = rm; + auto fp_vector_unary_op_3529_arg10 = ret_val_sew_3530; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3529, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3530, 0, reinterpret_cast(this)); + setRet(call_sew_3530, 0, ret_val_sew_3530); + setArg(call_fp_vector_unary_op_3529, 0, V); + setArg(call_fp_vector_unary_op_3529, 1, 19); + setArg(call_fp_vector_unary_op_3529, 2, 5); + setArg(call_fp_vector_unary_op_3529, 3, fp_vector_unary_op_3529_arg3); + setArg(call_fp_vector_unary_op_3529, 4, fp_vector_unary_op_3529_arg4); + setArg(call_fp_vector_unary_op_3529, 5, fp_vector_unary_op_3529_arg5); + setArg(call_fp_vector_unary_op_3529, 6, vm); + setArg(call_fp_vector_unary_op_3529, 7, vd); + setArg(call_fp_vector_unary_op_3529, 8, vs2); + setArg(call_fp_vector_unary_op_3529, 9, fp_vector_unary_op_3529_arg9); + setArg(call_fp_vector_unary_op_3529, 10, fp_vector_unary_op_3529_arg10); + InvokeNode* call_fget_flags_3531; + x86::Gp ret_val_fget_flags_3531 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3531, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3531; + setRet(call_fget_flags_3531, 0, ret_val_fget_flags_3531); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3532 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3532, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3532, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 742); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 743: VFMIN__VF */ + continuation_e __vfmin__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmin.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMIN__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 743); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3533; + x86::Gp ret_val_get_sew_pow_3533 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3533, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3534 = get_reg(cc, 8, false); + mov(cc, tmp3534, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3534, (ret_val_get_sew_pow_3533))), 8, false), ~ 1); + setArg(call_get_sew_pow_3533, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3533, 0, ret_val_get_sew_pow_3533); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3535; + auto illegal_fp_normal_3535_arg2 = SEW; + auto illegal_fp_normal_3535_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3535 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3535, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3535; + setArg(call_illegal_fp_normal_3535, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3535, 1, vd); + setArg(call_illegal_fp_normal_3535, 2, vm); + setArg(call_illegal_fp_normal_3535, 3, illegal_fp_normal_3535_arg2); + setArg(call_illegal_fp_normal_3535, 4, illegal_fp_normal_3535_arg3); + setRet(call_illegal_fp_normal_3535, 0, ret_val_illegal_fp_normal_3535); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3537; + x86::Gp ret_val_sew_3537 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3537, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3536; + auto fp_vector_imm_op_3536_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3536_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3536_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3536_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3536_arg10 = rm; + auto fp_vector_imm_op_3536_arg11 = ret_val_sew_3537; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3536, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3537, 0, reinterpret_cast(this)); + setRet(call_sew_3537, 0, ret_val_sew_3537); + setArg(call_fp_vector_imm_op_3536, 0, V); + setArg(call_fp_vector_imm_op_3536, 1, 4); + setArg(call_fp_vector_imm_op_3536, 2, 5); + setArg(call_fp_vector_imm_op_3536, 3, fp_vector_imm_op_3536_arg3); + setArg(call_fp_vector_imm_op_3536, 4, fp_vector_imm_op_3536_arg4); + setArg(call_fp_vector_imm_op_3536, 5, fp_vector_imm_op_3536_arg5); + setArg(call_fp_vector_imm_op_3536, 6, vm); + setArg(call_fp_vector_imm_op_3536, 7, vd); + setArg(call_fp_vector_imm_op_3536, 8, vs2); + setArg(call_fp_vector_imm_op_3536, 9, fp_vector_imm_op_3536_arg9); + setArg(call_fp_vector_imm_op_3536, 10, fp_vector_imm_op_3536_arg10); + setArg(call_fp_vector_imm_op_3536, 11, fp_vector_imm_op_3536_arg11); + } + cc.bind(label_merge); + } + auto tmp3538 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3538, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3538, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 743); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 744: VFMIN__VV */ + continuation_e __vfmin__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmin.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMIN__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 744); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3539; + x86::Gp ret_val_get_sew_pow_3539 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3539, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3540 = get_reg(cc, 8, false); + mov(cc, tmp3540, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3540, (ret_val_get_sew_pow_3539))), 8, false), ~ 1); + setArg(call_get_sew_pow_3539, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3539, 0, ret_val_get_sew_pow_3539); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3541; + auto illegal_fp_normal_3541_arg2 = SEW; + auto illegal_fp_normal_3541_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3541 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3541, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3541; + setArg(call_illegal_fp_normal_3541, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3541, 1, vd); + setArg(call_illegal_fp_normal_3541, 2, vm); + setArg(call_illegal_fp_normal_3541, 3, illegal_fp_normal_3541_arg2); + setArg(call_illegal_fp_normal_3541, 4, illegal_fp_normal_3541_arg3); + setRet(call_illegal_fp_normal_3541, 0, ret_val_illegal_fp_normal_3541); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3543; + x86::Gp ret_val_sew_3543 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3543, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3542; + auto fp_vector_vector_op_3542_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3542_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3542_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3542_arg10 = rm; + auto fp_vector_vector_op_3542_arg11 = ret_val_sew_3543; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3542, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3543, 0, reinterpret_cast(this)); + setRet(call_sew_3543, 0, ret_val_sew_3543); + setArg(call_fp_vector_vector_op_3542, 0, V); + setArg(call_fp_vector_vector_op_3542, 1, 4); + setArg(call_fp_vector_vector_op_3542, 2, 1); + setArg(call_fp_vector_vector_op_3542, 3, fp_vector_vector_op_3542_arg3); + setArg(call_fp_vector_vector_op_3542, 4, fp_vector_vector_op_3542_arg4); + setArg(call_fp_vector_vector_op_3542, 5, fp_vector_vector_op_3542_arg5); + setArg(call_fp_vector_vector_op_3542, 6, vm); + setArg(call_fp_vector_vector_op_3542, 7, vd); + setArg(call_fp_vector_vector_op_3542, 8, vs2); + setArg(call_fp_vector_vector_op_3542, 9, vs1); + setArg(call_fp_vector_vector_op_3542, 10, fp_vector_vector_op_3542_arg10); + setArg(call_fp_vector_vector_op_3542, 11, fp_vector_vector_op_3542_arg11); + } + cc.bind(label_merge); + } + auto tmp3544 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3544, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3544, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 744); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 745: VFMAX__VF */ + continuation_e __vfmax__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmax.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMAX__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 745); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3545; + x86::Gp ret_val_get_sew_pow_3545 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3545, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3546 = get_reg(cc, 8, false); + mov(cc, tmp3546, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3546, (ret_val_get_sew_pow_3545))), 8, false), ~ 1); + setArg(call_get_sew_pow_3545, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3545, 0, ret_val_get_sew_pow_3545); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3547; + auto illegal_fp_normal_3547_arg2 = SEW; + auto illegal_fp_normal_3547_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3547 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3547, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3547; + setArg(call_illegal_fp_normal_3547, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3547, 1, vd); + setArg(call_illegal_fp_normal_3547, 2, vm); + setArg(call_illegal_fp_normal_3547, 3, illegal_fp_normal_3547_arg2); + setArg(call_illegal_fp_normal_3547, 4, illegal_fp_normal_3547_arg3); + setRet(call_illegal_fp_normal_3547, 0, ret_val_illegal_fp_normal_3547); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3549; + x86::Gp ret_val_sew_3549 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3549, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3548; + auto fp_vector_imm_op_3548_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3548_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3548_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3548_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3548_arg10 = rm; + auto fp_vector_imm_op_3548_arg11 = ret_val_sew_3549; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3548, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3549, 0, reinterpret_cast(this)); + setRet(call_sew_3549, 0, ret_val_sew_3549); + setArg(call_fp_vector_imm_op_3548, 0, V); + setArg(call_fp_vector_imm_op_3548, 1, 6); + setArg(call_fp_vector_imm_op_3548, 2, 5); + setArg(call_fp_vector_imm_op_3548, 3, fp_vector_imm_op_3548_arg3); + setArg(call_fp_vector_imm_op_3548, 4, fp_vector_imm_op_3548_arg4); + setArg(call_fp_vector_imm_op_3548, 5, fp_vector_imm_op_3548_arg5); + setArg(call_fp_vector_imm_op_3548, 6, vm); + setArg(call_fp_vector_imm_op_3548, 7, vd); + setArg(call_fp_vector_imm_op_3548, 8, vs2); + setArg(call_fp_vector_imm_op_3548, 9, fp_vector_imm_op_3548_arg9); + setArg(call_fp_vector_imm_op_3548, 10, fp_vector_imm_op_3548_arg10); + setArg(call_fp_vector_imm_op_3548, 11, fp_vector_imm_op_3548_arg11); + } + cc.bind(label_merge); + } + auto tmp3550 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3550, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3550, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 745); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 746: VFMAX__VV */ + continuation_e __vfmax__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmax.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMAX__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 746); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3551; + x86::Gp ret_val_get_sew_pow_3551 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3551, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3552 = get_reg(cc, 8, false); + mov(cc, tmp3552, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3552, (ret_val_get_sew_pow_3551))), 8, false), ~ 1); + setArg(call_get_sew_pow_3551, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3551, 0, ret_val_get_sew_pow_3551); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3553; + auto illegal_fp_normal_3553_arg2 = SEW; + auto illegal_fp_normal_3553_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3553 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3553, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3553; + setArg(call_illegal_fp_normal_3553, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3553, 1, vd); + setArg(call_illegal_fp_normal_3553, 2, vm); + setArg(call_illegal_fp_normal_3553, 3, illegal_fp_normal_3553_arg2); + setArg(call_illegal_fp_normal_3553, 4, illegal_fp_normal_3553_arg3); + setRet(call_illegal_fp_normal_3553, 0, ret_val_illegal_fp_normal_3553); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3555; + x86::Gp ret_val_sew_3555 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3555, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3554; + auto fp_vector_vector_op_3554_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3554_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3554_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3554_arg10 = rm; + auto fp_vector_vector_op_3554_arg11 = ret_val_sew_3555; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3554, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3555, 0, reinterpret_cast(this)); + setRet(call_sew_3555, 0, ret_val_sew_3555); + setArg(call_fp_vector_vector_op_3554, 0, V); + setArg(call_fp_vector_vector_op_3554, 1, 6); + setArg(call_fp_vector_vector_op_3554, 2, 1); + setArg(call_fp_vector_vector_op_3554, 3, fp_vector_vector_op_3554_arg3); + setArg(call_fp_vector_vector_op_3554, 4, fp_vector_vector_op_3554_arg4); + setArg(call_fp_vector_vector_op_3554, 5, fp_vector_vector_op_3554_arg5); + setArg(call_fp_vector_vector_op_3554, 6, vm); + setArg(call_fp_vector_vector_op_3554, 7, vd); + setArg(call_fp_vector_vector_op_3554, 8, vs2); + setArg(call_fp_vector_vector_op_3554, 9, vs1); + setArg(call_fp_vector_vector_op_3554, 10, fp_vector_vector_op_3554_arg10); + setArg(call_fp_vector_vector_op_3554, 11, fp_vector_vector_op_3554_arg11); + } + cc.bind(label_merge); + } + auto tmp3556 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3556, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3556, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 746); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 747: VFSGNJ__VF */ + continuation_e __vfsgnj__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnj.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJ__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 747); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3557; + x86::Gp ret_val_get_sew_pow_3557 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3557, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3558 = get_reg(cc, 8, false); + mov(cc, tmp3558, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3558, (ret_val_get_sew_pow_3557))), 8, false), ~ 1); + setArg(call_get_sew_pow_3557, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3557, 0, ret_val_get_sew_pow_3557); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3559; + auto illegal_fp_normal_3559_arg2 = SEW; + auto illegal_fp_normal_3559_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3559 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3559, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3559; + setArg(call_illegal_fp_normal_3559, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3559, 1, vd); + setArg(call_illegal_fp_normal_3559, 2, vm); + setArg(call_illegal_fp_normal_3559, 3, illegal_fp_normal_3559_arg2); + setArg(call_illegal_fp_normal_3559, 4, illegal_fp_normal_3559_arg3); + setRet(call_illegal_fp_normal_3559, 0, ret_val_illegal_fp_normal_3559); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3561; + x86::Gp ret_val_sew_3561 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3561, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3560; + auto fp_vector_imm_op_3560_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3560_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3560_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3560_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3560_arg10 = rm; + auto fp_vector_imm_op_3560_arg11 = ret_val_sew_3561; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3560, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3561, 0, reinterpret_cast(this)); + setRet(call_sew_3561, 0, ret_val_sew_3561); + setArg(call_fp_vector_imm_op_3560, 0, V); + setArg(call_fp_vector_imm_op_3560, 1, 8); + setArg(call_fp_vector_imm_op_3560, 2, 5); + setArg(call_fp_vector_imm_op_3560, 3, fp_vector_imm_op_3560_arg3); + setArg(call_fp_vector_imm_op_3560, 4, fp_vector_imm_op_3560_arg4); + setArg(call_fp_vector_imm_op_3560, 5, fp_vector_imm_op_3560_arg5); + setArg(call_fp_vector_imm_op_3560, 6, vm); + setArg(call_fp_vector_imm_op_3560, 7, vd); + setArg(call_fp_vector_imm_op_3560, 8, vs2); + setArg(call_fp_vector_imm_op_3560, 9, fp_vector_imm_op_3560_arg9); + setArg(call_fp_vector_imm_op_3560, 10, fp_vector_imm_op_3560_arg10); + setArg(call_fp_vector_imm_op_3560, 11, fp_vector_imm_op_3560_arg11); + } + cc.bind(label_merge); + } + auto tmp3562 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3562, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3562, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 747); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 748: VFSGNJ__VV */ + continuation_e __vfsgnj__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnj.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJ__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 748); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3563; + x86::Gp ret_val_get_sew_pow_3563 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3563, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3564 = get_reg(cc, 8, false); + mov(cc, tmp3564, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3564, (ret_val_get_sew_pow_3563))), 8, false), ~ 1); + setArg(call_get_sew_pow_3563, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3563, 0, ret_val_get_sew_pow_3563); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3565; + auto illegal_fp_normal_3565_arg2 = SEW; + auto illegal_fp_normal_3565_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3565 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3565, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3565; + setArg(call_illegal_fp_normal_3565, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3565, 1, vd); + setArg(call_illegal_fp_normal_3565, 2, vm); + setArg(call_illegal_fp_normal_3565, 3, illegal_fp_normal_3565_arg2); + setArg(call_illegal_fp_normal_3565, 4, illegal_fp_normal_3565_arg3); + setRet(call_illegal_fp_normal_3565, 0, ret_val_illegal_fp_normal_3565); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3567; + x86::Gp ret_val_sew_3567 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3567, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3566; + auto fp_vector_vector_op_3566_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3566_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3566_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3566_arg10 = rm; + auto fp_vector_vector_op_3566_arg11 = ret_val_sew_3567; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3566, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3567, 0, reinterpret_cast(this)); + setRet(call_sew_3567, 0, ret_val_sew_3567); + setArg(call_fp_vector_vector_op_3566, 0, V); + setArg(call_fp_vector_vector_op_3566, 1, 8); + setArg(call_fp_vector_vector_op_3566, 2, 1); + setArg(call_fp_vector_vector_op_3566, 3, fp_vector_vector_op_3566_arg3); + setArg(call_fp_vector_vector_op_3566, 4, fp_vector_vector_op_3566_arg4); + setArg(call_fp_vector_vector_op_3566, 5, fp_vector_vector_op_3566_arg5); + setArg(call_fp_vector_vector_op_3566, 6, vm); + setArg(call_fp_vector_vector_op_3566, 7, vd); + setArg(call_fp_vector_vector_op_3566, 8, vs2); + setArg(call_fp_vector_vector_op_3566, 9, vs1); + setArg(call_fp_vector_vector_op_3566, 10, fp_vector_vector_op_3566_arg10); + setArg(call_fp_vector_vector_op_3566, 11, fp_vector_vector_op_3566_arg11); + } + cc.bind(label_merge); + } + auto tmp3568 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3568, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3568, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 748); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 749: VFSGNJN__VF */ + continuation_e __vfsgnjn__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnjn.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJN__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 749); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3569; + x86::Gp ret_val_get_sew_pow_3569 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3569, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3570 = get_reg(cc, 8, false); + mov(cc, tmp3570, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3570, (ret_val_get_sew_pow_3569))), 8, false), ~ 1); + setArg(call_get_sew_pow_3569, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3569, 0, ret_val_get_sew_pow_3569); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3571; + auto illegal_fp_normal_3571_arg2 = SEW; + auto illegal_fp_normal_3571_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3571 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3571, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3571; + setArg(call_illegal_fp_normal_3571, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3571, 1, vd); + setArg(call_illegal_fp_normal_3571, 2, vm); + setArg(call_illegal_fp_normal_3571, 3, illegal_fp_normal_3571_arg2); + setArg(call_illegal_fp_normal_3571, 4, illegal_fp_normal_3571_arg3); + setRet(call_illegal_fp_normal_3571, 0, ret_val_illegal_fp_normal_3571); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3573; + x86::Gp ret_val_sew_3573 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3573, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3572; + auto fp_vector_imm_op_3572_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3572_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3572_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3572_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3572_arg10 = rm; + auto fp_vector_imm_op_3572_arg11 = ret_val_sew_3573; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3572, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3573, 0, reinterpret_cast(this)); + setRet(call_sew_3573, 0, ret_val_sew_3573); + setArg(call_fp_vector_imm_op_3572, 0, V); + setArg(call_fp_vector_imm_op_3572, 1, 9); + setArg(call_fp_vector_imm_op_3572, 2, 5); + setArg(call_fp_vector_imm_op_3572, 3, fp_vector_imm_op_3572_arg3); + setArg(call_fp_vector_imm_op_3572, 4, fp_vector_imm_op_3572_arg4); + setArg(call_fp_vector_imm_op_3572, 5, fp_vector_imm_op_3572_arg5); + setArg(call_fp_vector_imm_op_3572, 6, vm); + setArg(call_fp_vector_imm_op_3572, 7, vd); + setArg(call_fp_vector_imm_op_3572, 8, vs2); + setArg(call_fp_vector_imm_op_3572, 9, fp_vector_imm_op_3572_arg9); + setArg(call_fp_vector_imm_op_3572, 10, fp_vector_imm_op_3572_arg10); + setArg(call_fp_vector_imm_op_3572, 11, fp_vector_imm_op_3572_arg11); + } + cc.bind(label_merge); + } + auto tmp3574 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3574, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3574, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 749); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 750: VFSGNJN__VV */ + continuation_e __vfsgnjn__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnjn.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJN__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 750); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3575; + x86::Gp ret_val_get_sew_pow_3575 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3575, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3576 = get_reg(cc, 8, false); + mov(cc, tmp3576, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3576, (ret_val_get_sew_pow_3575))), 8, false), ~ 1); + setArg(call_get_sew_pow_3575, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3575, 0, ret_val_get_sew_pow_3575); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3577; + auto illegal_fp_normal_3577_arg2 = SEW; + auto illegal_fp_normal_3577_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3577 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3577, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3577; + setArg(call_illegal_fp_normal_3577, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3577, 1, vd); + setArg(call_illegal_fp_normal_3577, 2, vm); + setArg(call_illegal_fp_normal_3577, 3, illegal_fp_normal_3577_arg2); + setArg(call_illegal_fp_normal_3577, 4, illegal_fp_normal_3577_arg3); + setRet(call_illegal_fp_normal_3577, 0, ret_val_illegal_fp_normal_3577); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3579; + x86::Gp ret_val_sew_3579 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3579, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3578; + auto fp_vector_vector_op_3578_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3578_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3578_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3578_arg10 = rm; + auto fp_vector_vector_op_3578_arg11 = ret_val_sew_3579; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3578, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3579, 0, reinterpret_cast(this)); + setRet(call_sew_3579, 0, ret_val_sew_3579); + setArg(call_fp_vector_vector_op_3578, 0, V); + setArg(call_fp_vector_vector_op_3578, 1, 9); + setArg(call_fp_vector_vector_op_3578, 2, 1); + setArg(call_fp_vector_vector_op_3578, 3, fp_vector_vector_op_3578_arg3); + setArg(call_fp_vector_vector_op_3578, 4, fp_vector_vector_op_3578_arg4); + setArg(call_fp_vector_vector_op_3578, 5, fp_vector_vector_op_3578_arg5); + setArg(call_fp_vector_vector_op_3578, 6, vm); + setArg(call_fp_vector_vector_op_3578, 7, vd); + setArg(call_fp_vector_vector_op_3578, 8, vs2); + setArg(call_fp_vector_vector_op_3578, 9, vs1); + setArg(call_fp_vector_vector_op_3578, 10, fp_vector_vector_op_3578_arg10); + setArg(call_fp_vector_vector_op_3578, 11, fp_vector_vector_op_3578_arg11); + } + cc.bind(label_merge); + } + auto tmp3580 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3580, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3580, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 750); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 751: VFSGNJX__VF */ + continuation_e __vfsgnjx__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnjx.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJX__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 751); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3581; + x86::Gp ret_val_get_sew_pow_3581 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3581, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3582 = get_reg(cc, 8, false); + mov(cc, tmp3582, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3582, (ret_val_get_sew_pow_3581))), 8, false), ~ 1); + setArg(call_get_sew_pow_3581, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3581, 0, ret_val_get_sew_pow_3581); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3583; + auto illegal_fp_normal_3583_arg2 = SEW; + auto illegal_fp_normal_3583_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3583 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3583, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3583; + setArg(call_illegal_fp_normal_3583, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3583, 1, vd); + setArg(call_illegal_fp_normal_3583, 2, vm); + setArg(call_illegal_fp_normal_3583, 3, illegal_fp_normal_3583_arg2); + setArg(call_illegal_fp_normal_3583, 4, illegal_fp_normal_3583_arg3); + setRet(call_illegal_fp_normal_3583, 0, ret_val_illegal_fp_normal_3583); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3585; + x86::Gp ret_val_sew_3585 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3585, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3584; + auto fp_vector_imm_op_3584_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3584_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3584_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3584_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto fp_vector_imm_op_3584_arg10 = rm; + auto fp_vector_imm_op_3584_arg11 = ret_val_sew_3585; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3584, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3585, 0, reinterpret_cast(this)); + setRet(call_sew_3585, 0, ret_val_sew_3585); + setArg(call_fp_vector_imm_op_3584, 0, V); + setArg(call_fp_vector_imm_op_3584, 1, 10); + setArg(call_fp_vector_imm_op_3584, 2, 5); + setArg(call_fp_vector_imm_op_3584, 3, fp_vector_imm_op_3584_arg3); + setArg(call_fp_vector_imm_op_3584, 4, fp_vector_imm_op_3584_arg4); + setArg(call_fp_vector_imm_op_3584, 5, fp_vector_imm_op_3584_arg5); + setArg(call_fp_vector_imm_op_3584, 6, vm); + setArg(call_fp_vector_imm_op_3584, 7, vd); + setArg(call_fp_vector_imm_op_3584, 8, vs2); + setArg(call_fp_vector_imm_op_3584, 9, fp_vector_imm_op_3584_arg9); + setArg(call_fp_vector_imm_op_3584, 10, fp_vector_imm_op_3584_arg10); + setArg(call_fp_vector_imm_op_3584, 11, fp_vector_imm_op_3584_arg11); + } + cc.bind(label_merge); + } + auto tmp3586 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3586, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3586, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 751); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 752: VFSGNJX__VV */ + continuation_e __vfsgnjx__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnjx.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJX__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 752); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3587; + x86::Gp ret_val_get_sew_pow_3587 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3587, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3588 = get_reg(cc, 8, false); + mov(cc, tmp3588, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3588, (ret_val_get_sew_pow_3587))), 8, false), ~ 1); + setArg(call_get_sew_pow_3587, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3587, 0, ret_val_get_sew_pow_3587); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3589; + auto illegal_fp_normal_3589_arg2 = SEW; + auto illegal_fp_normal_3589_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3589 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3589, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3589; + setArg(call_illegal_fp_normal_3589, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3589, 1, vd); + setArg(call_illegal_fp_normal_3589, 2, vm); + setArg(call_illegal_fp_normal_3589, 3, illegal_fp_normal_3589_arg2); + setArg(call_illegal_fp_normal_3589, 4, illegal_fp_normal_3589_arg3); + setRet(call_illegal_fp_normal_3589, 0, ret_val_illegal_fp_normal_3589); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3591; + x86::Gp ret_val_sew_3591 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3591, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3590; + auto fp_vector_vector_op_3590_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3590_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3590_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3590_arg10 = rm; + auto fp_vector_vector_op_3590_arg11 = ret_val_sew_3591; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3590, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3591, 0, reinterpret_cast(this)); + setRet(call_sew_3591, 0, ret_val_sew_3591); + setArg(call_fp_vector_vector_op_3590, 0, V); + setArg(call_fp_vector_vector_op_3590, 1, 10); + setArg(call_fp_vector_vector_op_3590, 2, 1); + setArg(call_fp_vector_vector_op_3590, 3, fp_vector_vector_op_3590_arg3); + setArg(call_fp_vector_vector_op_3590, 4, fp_vector_vector_op_3590_arg4); + setArg(call_fp_vector_vector_op_3590, 5, fp_vector_vector_op_3590_arg5); + setArg(call_fp_vector_vector_op_3590, 6, vm); + setArg(call_fp_vector_vector_op_3590, 7, vd); + setArg(call_fp_vector_vector_op_3590, 8, vs2); + setArg(call_fp_vector_vector_op_3590, 9, vs1); + setArg(call_fp_vector_vector_op_3590, 10, fp_vector_vector_op_3590_arg10); + setArg(call_fp_vector_vector_op_3590, 11, fp_vector_vector_op_3590_arg11); + } + cc.bind(label_merge); + } + auto tmp3592 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3592, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3592, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 752); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 753: VMFEQ__VF */ + continuation_e __vmfeq__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfeq.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFEQ__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 753); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3593; + x86::Gp ret_val_get_sew_pow_3593 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3593, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3594 = get_reg(cc, 8, false); + mov(cc, tmp3594, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3594, (ret_val_get_sew_pow_3593))), 8, false), ~ 1); + setArg(call_get_sew_pow_3593, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3593, 0, ret_val_get_sew_pow_3593); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3595; + auto illegal_fp_vd_unmasked_3595_arg0 = SEW; + auto illegal_fp_vd_unmasked_3595_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3595 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3595, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3595; + setArg(call_illegal_fp_vd_unmasked_3595, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3595, 1, illegal_fp_vd_unmasked_3595_arg0); + setArg(call_illegal_fp_vd_unmasked_3595, 2, illegal_fp_vd_unmasked_3595_arg1); + setRet(call_illegal_fp_vd_unmasked_3595, 0, ret_val_illegal_fp_vd_unmasked_3595); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3597; + x86::Gp ret_val_sew_3597 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3597, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3596; + auto mask_fp_vector_imm_op_3596_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3596_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3596_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3596_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto mask_fp_vector_imm_op_3596_arg9 = rm; + auto mask_fp_vector_imm_op_3596_arg10 = ret_val_sew_3597; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3596, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3597, 0, reinterpret_cast(this)); + setRet(call_sew_3597, 0, ret_val_sew_3597); + setArg(call_mask_fp_vector_imm_op_3596, 0, V); + setArg(call_mask_fp_vector_imm_op_3596, 1, 24); + setArg(call_mask_fp_vector_imm_op_3596, 2, mask_fp_vector_imm_op_3596_arg2); + setArg(call_mask_fp_vector_imm_op_3596, 3, mask_fp_vector_imm_op_3596_arg3); + setArg(call_mask_fp_vector_imm_op_3596, 4, mask_fp_vector_imm_op_3596_arg4); + setArg(call_mask_fp_vector_imm_op_3596, 5, vm); + setArg(call_mask_fp_vector_imm_op_3596, 6, vd); + setArg(call_mask_fp_vector_imm_op_3596, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3596, 8, mask_fp_vector_imm_op_3596_arg8); + setArg(call_mask_fp_vector_imm_op_3596, 9, mask_fp_vector_imm_op_3596_arg9); + setArg(call_mask_fp_vector_imm_op_3596, 10, mask_fp_vector_imm_op_3596_arg10); + InvokeNode* call_fget_flags_3598; + x86::Gp ret_val_fget_flags_3598 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3598, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3598; + setRet(call_fget_flags_3598, 0, ret_val_fget_flags_3598); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3599 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3599, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3599, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 753); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 754: VMFEQ__VV */ + continuation_e __vmfeq__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfeq.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFEQ__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 754); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3600; + x86::Gp ret_val_get_sew_pow_3600 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3600, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3601 = get_reg(cc, 8, false); + mov(cc, tmp3601, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3601, (ret_val_get_sew_pow_3600))), 8, false), ~ 1); + setArg(call_get_sew_pow_3600, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3600, 0, ret_val_get_sew_pow_3600); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3602; + auto illegal_fp_vd_unmasked_3602_arg0 = SEW; + auto illegal_fp_vd_unmasked_3602_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3602 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3602, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3602; + setArg(call_illegal_fp_vd_unmasked_3602, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3602, 1, illegal_fp_vd_unmasked_3602_arg0); + setArg(call_illegal_fp_vd_unmasked_3602, 2, illegal_fp_vd_unmasked_3602_arg1); + setRet(call_illegal_fp_vd_unmasked_3602, 0, ret_val_illegal_fp_vd_unmasked_3602); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3604; + x86::Gp ret_val_sew_3604 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3604, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3603; + auto mask_fp_vector_vector_op_3603_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3603_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3603_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3603_arg9 = rm; + auto mask_fp_vector_vector_op_3603_arg10 = ret_val_sew_3604; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_vector_op_3603, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3604, 0, reinterpret_cast(this)); + setRet(call_sew_3604, 0, ret_val_sew_3604); + setArg(call_mask_fp_vector_vector_op_3603, 0, V); + setArg(call_mask_fp_vector_vector_op_3603, 1, 24); + setArg(call_mask_fp_vector_vector_op_3603, 2, mask_fp_vector_vector_op_3603_arg2); + setArg(call_mask_fp_vector_vector_op_3603, 3, mask_fp_vector_vector_op_3603_arg3); + setArg(call_mask_fp_vector_vector_op_3603, 4, mask_fp_vector_vector_op_3603_arg4); + setArg(call_mask_fp_vector_vector_op_3603, 5, vm); + setArg(call_mask_fp_vector_vector_op_3603, 6, vd); + setArg(call_mask_fp_vector_vector_op_3603, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3603, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3603, 9, mask_fp_vector_vector_op_3603_arg9); + setArg(call_mask_fp_vector_vector_op_3603, 10, mask_fp_vector_vector_op_3603_arg10); + InvokeNode* call_fget_flags_3605; + x86::Gp ret_val_fget_flags_3605 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3605, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3605; + setRet(call_fget_flags_3605, 0, ret_val_fget_flags_3605); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3606 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3606, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3606, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 754); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 755: VMFNE__VF */ + continuation_e __vmfne__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfne.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFNE__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 755); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3607; + x86::Gp ret_val_get_sew_pow_3607 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3607, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3608 = get_reg(cc, 8, false); + mov(cc, tmp3608, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3608, (ret_val_get_sew_pow_3607))), 8, false), ~ 1); + setArg(call_get_sew_pow_3607, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3607, 0, ret_val_get_sew_pow_3607); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3609; + auto illegal_fp_vd_unmasked_3609_arg0 = SEW; + auto illegal_fp_vd_unmasked_3609_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3609 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3609, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3609; + setArg(call_illegal_fp_vd_unmasked_3609, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3609, 1, illegal_fp_vd_unmasked_3609_arg0); + setArg(call_illegal_fp_vd_unmasked_3609, 2, illegal_fp_vd_unmasked_3609_arg1); + setRet(call_illegal_fp_vd_unmasked_3609, 0, ret_val_illegal_fp_vd_unmasked_3609); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3611; + x86::Gp ret_val_sew_3611 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3611, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3610; + auto mask_fp_vector_imm_op_3610_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3610_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3610_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3610_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto mask_fp_vector_imm_op_3610_arg9 = rm; + auto mask_fp_vector_imm_op_3610_arg10 = ret_val_sew_3611; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3610, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3611, 0, reinterpret_cast(this)); + setRet(call_sew_3611, 0, ret_val_sew_3611); + setArg(call_mask_fp_vector_imm_op_3610, 0, V); + setArg(call_mask_fp_vector_imm_op_3610, 1, 28); + setArg(call_mask_fp_vector_imm_op_3610, 2, mask_fp_vector_imm_op_3610_arg2); + setArg(call_mask_fp_vector_imm_op_3610, 3, mask_fp_vector_imm_op_3610_arg3); + setArg(call_mask_fp_vector_imm_op_3610, 4, mask_fp_vector_imm_op_3610_arg4); + setArg(call_mask_fp_vector_imm_op_3610, 5, vm); + setArg(call_mask_fp_vector_imm_op_3610, 6, vd); + setArg(call_mask_fp_vector_imm_op_3610, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3610, 8, mask_fp_vector_imm_op_3610_arg8); + setArg(call_mask_fp_vector_imm_op_3610, 9, mask_fp_vector_imm_op_3610_arg9); + setArg(call_mask_fp_vector_imm_op_3610, 10, mask_fp_vector_imm_op_3610_arg10); + InvokeNode* call_fget_flags_3612; + x86::Gp ret_val_fget_flags_3612 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3612, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3612; + setRet(call_fget_flags_3612, 0, ret_val_fget_flags_3612); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3613 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3613, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3613, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 755); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 756: VMFNE__VV */ + continuation_e __vmfne__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfne.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFNE__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 756); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3614; + x86::Gp ret_val_get_sew_pow_3614 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3614, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3615 = get_reg(cc, 8, false); + mov(cc, tmp3615, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3615, (ret_val_get_sew_pow_3614))), 8, false), ~ 1); + setArg(call_get_sew_pow_3614, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3614, 0, ret_val_get_sew_pow_3614); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3616; + auto illegal_fp_vd_unmasked_3616_arg0 = SEW; + auto illegal_fp_vd_unmasked_3616_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3616 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3616, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3616; + setArg(call_illegal_fp_vd_unmasked_3616, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3616, 1, illegal_fp_vd_unmasked_3616_arg0); + setArg(call_illegal_fp_vd_unmasked_3616, 2, illegal_fp_vd_unmasked_3616_arg1); + setRet(call_illegal_fp_vd_unmasked_3616, 0, ret_val_illegal_fp_vd_unmasked_3616); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3618; + x86::Gp ret_val_sew_3618 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3618, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3617; + auto mask_fp_vector_vector_op_3617_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3617_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3617_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3617_arg9 = rm; + auto mask_fp_vector_vector_op_3617_arg10 = ret_val_sew_3618; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_vector_op_3617, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3618, 0, reinterpret_cast(this)); + setRet(call_sew_3618, 0, ret_val_sew_3618); + setArg(call_mask_fp_vector_vector_op_3617, 0, V); + setArg(call_mask_fp_vector_vector_op_3617, 1, 28); + setArg(call_mask_fp_vector_vector_op_3617, 2, mask_fp_vector_vector_op_3617_arg2); + setArg(call_mask_fp_vector_vector_op_3617, 3, mask_fp_vector_vector_op_3617_arg3); + setArg(call_mask_fp_vector_vector_op_3617, 4, mask_fp_vector_vector_op_3617_arg4); + setArg(call_mask_fp_vector_vector_op_3617, 5, vm); + setArg(call_mask_fp_vector_vector_op_3617, 6, vd); + setArg(call_mask_fp_vector_vector_op_3617, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3617, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3617, 9, mask_fp_vector_vector_op_3617_arg9); + setArg(call_mask_fp_vector_vector_op_3617, 10, mask_fp_vector_vector_op_3617_arg10); + InvokeNode* call_fget_flags_3619; + x86::Gp ret_val_fget_flags_3619 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3619, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3619; + setRet(call_fget_flags_3619, 0, ret_val_fget_flags_3619); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3620 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3620, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3620, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 756); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 757: VMFLT__VF */ + continuation_e __vmflt__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmflt.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFLT__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 757); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3621; + x86::Gp ret_val_get_sew_pow_3621 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3621, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3622 = get_reg(cc, 8, false); + mov(cc, tmp3622, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3622, (ret_val_get_sew_pow_3621))), 8, false), ~ 1); + setArg(call_get_sew_pow_3621, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3621, 0, ret_val_get_sew_pow_3621); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3623; + auto illegal_fp_vd_unmasked_3623_arg0 = SEW; + auto illegal_fp_vd_unmasked_3623_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3623 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3623, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3623; + setArg(call_illegal_fp_vd_unmasked_3623, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3623, 1, illegal_fp_vd_unmasked_3623_arg0); + setArg(call_illegal_fp_vd_unmasked_3623, 2, illegal_fp_vd_unmasked_3623_arg1); + setRet(call_illegal_fp_vd_unmasked_3623, 0, ret_val_illegal_fp_vd_unmasked_3623); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3625; + x86::Gp ret_val_sew_3625 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3625, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3624; + auto mask_fp_vector_imm_op_3624_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3624_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3624_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3624_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto mask_fp_vector_imm_op_3624_arg9 = rm; + auto mask_fp_vector_imm_op_3624_arg10 = ret_val_sew_3625; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3624, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3625, 0, reinterpret_cast(this)); + setRet(call_sew_3625, 0, ret_val_sew_3625); + setArg(call_mask_fp_vector_imm_op_3624, 0, V); + setArg(call_mask_fp_vector_imm_op_3624, 1, 27); + setArg(call_mask_fp_vector_imm_op_3624, 2, mask_fp_vector_imm_op_3624_arg2); + setArg(call_mask_fp_vector_imm_op_3624, 3, mask_fp_vector_imm_op_3624_arg3); + setArg(call_mask_fp_vector_imm_op_3624, 4, mask_fp_vector_imm_op_3624_arg4); + setArg(call_mask_fp_vector_imm_op_3624, 5, vm); + setArg(call_mask_fp_vector_imm_op_3624, 6, vd); + setArg(call_mask_fp_vector_imm_op_3624, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3624, 8, mask_fp_vector_imm_op_3624_arg8); + setArg(call_mask_fp_vector_imm_op_3624, 9, mask_fp_vector_imm_op_3624_arg9); + setArg(call_mask_fp_vector_imm_op_3624, 10, mask_fp_vector_imm_op_3624_arg10); + InvokeNode* call_fget_flags_3626; + x86::Gp ret_val_fget_flags_3626 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3626, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3626; + setRet(call_fget_flags_3626, 0, ret_val_fget_flags_3626); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3627 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3627, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3627, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 757); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 758: VMFLT__VV */ + continuation_e __vmflt__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmflt.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFLT__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 758); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3628; + x86::Gp ret_val_get_sew_pow_3628 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3628, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3629 = get_reg(cc, 8, false); + mov(cc, tmp3629, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3629, (ret_val_get_sew_pow_3628))), 8, false), ~ 1); + setArg(call_get_sew_pow_3628, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3628, 0, ret_val_get_sew_pow_3628); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3630; + auto illegal_fp_vd_unmasked_3630_arg0 = SEW; + auto illegal_fp_vd_unmasked_3630_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3630 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3630, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3630; + setArg(call_illegal_fp_vd_unmasked_3630, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3630, 1, illegal_fp_vd_unmasked_3630_arg0); + setArg(call_illegal_fp_vd_unmasked_3630, 2, illegal_fp_vd_unmasked_3630_arg1); + setRet(call_illegal_fp_vd_unmasked_3630, 0, ret_val_illegal_fp_vd_unmasked_3630); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3632; + x86::Gp ret_val_sew_3632 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3632, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3631; + auto mask_fp_vector_vector_op_3631_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3631_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3631_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3631_arg9 = rm; + auto mask_fp_vector_vector_op_3631_arg10 = ret_val_sew_3632; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_vector_op_3631, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3632, 0, reinterpret_cast(this)); + setRet(call_sew_3632, 0, ret_val_sew_3632); + setArg(call_mask_fp_vector_vector_op_3631, 0, V); + setArg(call_mask_fp_vector_vector_op_3631, 1, 27); + setArg(call_mask_fp_vector_vector_op_3631, 2, mask_fp_vector_vector_op_3631_arg2); + setArg(call_mask_fp_vector_vector_op_3631, 3, mask_fp_vector_vector_op_3631_arg3); + setArg(call_mask_fp_vector_vector_op_3631, 4, mask_fp_vector_vector_op_3631_arg4); + setArg(call_mask_fp_vector_vector_op_3631, 5, vm); + setArg(call_mask_fp_vector_vector_op_3631, 6, vd); + setArg(call_mask_fp_vector_vector_op_3631, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3631, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3631, 9, mask_fp_vector_vector_op_3631_arg9); + setArg(call_mask_fp_vector_vector_op_3631, 10, mask_fp_vector_vector_op_3631_arg10); + InvokeNode* call_fget_flags_3633; + x86::Gp ret_val_fget_flags_3633 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3633, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3633; + setRet(call_fget_flags_3633, 0, ret_val_fget_flags_3633); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3634 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3634, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3634, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 758); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 759: VMFLE__VF */ + continuation_e __vmfle__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfle.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFLE__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 759); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3635; + x86::Gp ret_val_get_sew_pow_3635 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3635, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3636 = get_reg(cc, 8, false); + mov(cc, tmp3636, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3636, (ret_val_get_sew_pow_3635))), 8, false), ~ 1); + setArg(call_get_sew_pow_3635, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3635, 0, ret_val_get_sew_pow_3635); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3637; + auto illegal_fp_vd_unmasked_3637_arg0 = SEW; + auto illegal_fp_vd_unmasked_3637_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3637 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3637, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3637; + setArg(call_illegal_fp_vd_unmasked_3637, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3637, 1, illegal_fp_vd_unmasked_3637_arg0); + setArg(call_illegal_fp_vd_unmasked_3637, 2, illegal_fp_vd_unmasked_3637_arg1); + setRet(call_illegal_fp_vd_unmasked_3637, 0, ret_val_illegal_fp_vd_unmasked_3637); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3639; + x86::Gp ret_val_sew_3639 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3639, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3638; + auto mask_fp_vector_imm_op_3638_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3638_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3638_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3638_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto mask_fp_vector_imm_op_3638_arg9 = rm; + auto mask_fp_vector_imm_op_3638_arg10 = ret_val_sew_3639; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3638, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3639, 0, reinterpret_cast(this)); + setRet(call_sew_3639, 0, ret_val_sew_3639); + setArg(call_mask_fp_vector_imm_op_3638, 0, V); + setArg(call_mask_fp_vector_imm_op_3638, 1, 25); + setArg(call_mask_fp_vector_imm_op_3638, 2, mask_fp_vector_imm_op_3638_arg2); + setArg(call_mask_fp_vector_imm_op_3638, 3, mask_fp_vector_imm_op_3638_arg3); + setArg(call_mask_fp_vector_imm_op_3638, 4, mask_fp_vector_imm_op_3638_arg4); + setArg(call_mask_fp_vector_imm_op_3638, 5, vm); + setArg(call_mask_fp_vector_imm_op_3638, 6, vd); + setArg(call_mask_fp_vector_imm_op_3638, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3638, 8, mask_fp_vector_imm_op_3638_arg8); + setArg(call_mask_fp_vector_imm_op_3638, 9, mask_fp_vector_imm_op_3638_arg9); + setArg(call_mask_fp_vector_imm_op_3638, 10, mask_fp_vector_imm_op_3638_arg10); + InvokeNode* call_fget_flags_3640; + x86::Gp ret_val_fget_flags_3640 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3640, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3640; + setRet(call_fget_flags_3640, 0, ret_val_fget_flags_3640); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3641 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3641, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3641, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 759); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 760: VMFLE__VV */ + continuation_e __vmfle__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfle.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFLE__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 760); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3642; + x86::Gp ret_val_get_sew_pow_3642 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3642, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3643 = get_reg(cc, 8, false); + mov(cc, tmp3643, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3643, (ret_val_get_sew_pow_3642))), 8, false), ~ 1); + setArg(call_get_sew_pow_3642, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3642, 0, ret_val_get_sew_pow_3642); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3644; + auto illegal_fp_vd_unmasked_3644_arg0 = SEW; + auto illegal_fp_vd_unmasked_3644_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3644 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3644, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3644; + setArg(call_illegal_fp_vd_unmasked_3644, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3644, 1, illegal_fp_vd_unmasked_3644_arg0); + setArg(call_illegal_fp_vd_unmasked_3644, 2, illegal_fp_vd_unmasked_3644_arg1); + setRet(call_illegal_fp_vd_unmasked_3644, 0, ret_val_illegal_fp_vd_unmasked_3644); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3646; + x86::Gp ret_val_sew_3646 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3646, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3645; + auto mask_fp_vector_vector_op_3645_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3645_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3645_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3645_arg9 = rm; + auto mask_fp_vector_vector_op_3645_arg10 = ret_val_sew_3646; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_vector_op_3645, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3646, 0, reinterpret_cast(this)); + setRet(call_sew_3646, 0, ret_val_sew_3646); + setArg(call_mask_fp_vector_vector_op_3645, 0, V); + setArg(call_mask_fp_vector_vector_op_3645, 1, 25); + setArg(call_mask_fp_vector_vector_op_3645, 2, mask_fp_vector_vector_op_3645_arg2); + setArg(call_mask_fp_vector_vector_op_3645, 3, mask_fp_vector_vector_op_3645_arg3); + setArg(call_mask_fp_vector_vector_op_3645, 4, mask_fp_vector_vector_op_3645_arg4); + setArg(call_mask_fp_vector_vector_op_3645, 5, vm); + setArg(call_mask_fp_vector_vector_op_3645, 6, vd); + setArg(call_mask_fp_vector_vector_op_3645, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3645, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3645, 9, mask_fp_vector_vector_op_3645_arg9); + setArg(call_mask_fp_vector_vector_op_3645, 10, mask_fp_vector_vector_op_3645_arg10); + InvokeNode* call_fget_flags_3647; + x86::Gp ret_val_fget_flags_3647 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3647, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3647; + setRet(call_fget_flags_3647, 0, ret_val_fget_flags_3647); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3648 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3648, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3648, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 760); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 761: VMFGT__VF */ + continuation_e __vmfgt__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfgt.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFGT__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 761); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3649; + x86::Gp ret_val_get_sew_pow_3649 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3649, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3650 = get_reg(cc, 8, false); + mov(cc, tmp3650, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3650, (ret_val_get_sew_pow_3649))), 8, false), ~ 1); + setArg(call_get_sew_pow_3649, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3649, 0, ret_val_get_sew_pow_3649); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3651; + auto illegal_fp_vd_unmasked_3651_arg0 = SEW; + auto illegal_fp_vd_unmasked_3651_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3651 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3651, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3651; + setArg(call_illegal_fp_vd_unmasked_3651, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3651, 1, illegal_fp_vd_unmasked_3651_arg0); + setArg(call_illegal_fp_vd_unmasked_3651, 2, illegal_fp_vd_unmasked_3651_arg1); + setRet(call_illegal_fp_vd_unmasked_3651, 0, ret_val_illegal_fp_vd_unmasked_3651); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3653; + x86::Gp ret_val_sew_3653 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3653, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3652; + auto mask_fp_vector_imm_op_3652_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3652_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3652_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3652_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto mask_fp_vector_imm_op_3652_arg9 = rm; + auto mask_fp_vector_imm_op_3652_arg10 = ret_val_sew_3653; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3652, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3653, 0, reinterpret_cast(this)); + setRet(call_sew_3653, 0, ret_val_sew_3653); + setArg(call_mask_fp_vector_imm_op_3652, 0, V); + setArg(call_mask_fp_vector_imm_op_3652, 1, 29); + setArg(call_mask_fp_vector_imm_op_3652, 2, mask_fp_vector_imm_op_3652_arg2); + setArg(call_mask_fp_vector_imm_op_3652, 3, mask_fp_vector_imm_op_3652_arg3); + setArg(call_mask_fp_vector_imm_op_3652, 4, mask_fp_vector_imm_op_3652_arg4); + setArg(call_mask_fp_vector_imm_op_3652, 5, vm); + setArg(call_mask_fp_vector_imm_op_3652, 6, vd); + setArg(call_mask_fp_vector_imm_op_3652, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3652, 8, mask_fp_vector_imm_op_3652_arg8); + setArg(call_mask_fp_vector_imm_op_3652, 9, mask_fp_vector_imm_op_3652_arg9); + setArg(call_mask_fp_vector_imm_op_3652, 10, mask_fp_vector_imm_op_3652_arg10); + InvokeNode* call_fget_flags_3654; + x86::Gp ret_val_fget_flags_3654 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3654, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3654; + setRet(call_fget_flags_3654, 0, ret_val_fget_flags_3654); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3655 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3655, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3655, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 761); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 762: VMFGE__VF */ + continuation_e __vmfge__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfge.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFGE__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 762); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3656; + x86::Gp ret_val_get_sew_pow_3656 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3656, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3657 = get_reg(cc, 8, false); + mov(cc, tmp3657, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3657, (ret_val_get_sew_pow_3656))), 8, false), ~ 1); + setArg(call_get_sew_pow_3656, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3656, 0, ret_val_get_sew_pow_3656); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3658; + auto illegal_fp_vd_unmasked_3658_arg0 = SEW; + auto illegal_fp_vd_unmasked_3658_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3658 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3658, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3658; + setArg(call_illegal_fp_vd_unmasked_3658, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3658, 1, illegal_fp_vd_unmasked_3658_arg0); + setArg(call_illegal_fp_vd_unmasked_3658, 2, illegal_fp_vd_unmasked_3658_arg1); + setRet(call_illegal_fp_vd_unmasked_3658, 0, ret_val_illegal_fp_vd_unmasked_3658); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3660; + x86::Gp ret_val_sew_3660 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3660, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3659; + auto mask_fp_vector_imm_op_3659_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3659_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3659_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3659_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto mask_fp_vector_imm_op_3659_arg9 = rm; + auto mask_fp_vector_imm_op_3659_arg10 = ret_val_sew_3660; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3659, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3660, 0, reinterpret_cast(this)); + setRet(call_sew_3660, 0, ret_val_sew_3660); + setArg(call_mask_fp_vector_imm_op_3659, 0, V); + setArg(call_mask_fp_vector_imm_op_3659, 1, 31); + setArg(call_mask_fp_vector_imm_op_3659, 2, mask_fp_vector_imm_op_3659_arg2); + setArg(call_mask_fp_vector_imm_op_3659, 3, mask_fp_vector_imm_op_3659_arg3); + setArg(call_mask_fp_vector_imm_op_3659, 4, mask_fp_vector_imm_op_3659_arg4); + setArg(call_mask_fp_vector_imm_op_3659, 5, vm); + setArg(call_mask_fp_vector_imm_op_3659, 6, vd); + setArg(call_mask_fp_vector_imm_op_3659, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3659, 8, mask_fp_vector_imm_op_3659_arg8); + setArg(call_mask_fp_vector_imm_op_3659, 9, mask_fp_vector_imm_op_3659_arg9); + setArg(call_mask_fp_vector_imm_op_3659, 10, mask_fp_vector_imm_op_3659_arg10); + InvokeNode* call_fget_flags_3661; + x86::Gp ret_val_fget_flags_3661 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3661, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3661; + setRet(call_fget_flags_3661, 0, ret_val_fget_flags_3661); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3662 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3662, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3662, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 762); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 763: VFCLASS__V */ + continuation_e __vfclass__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfclass.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCLASS__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 763); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3663; + x86::Gp ret_val_get_sew_pow_3663 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3663, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3664 = get_reg(cc, 8, false); + mov(cc, tmp3664, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3664, (ret_val_get_sew_pow_3663))), 8, false), ~ 1); + setArg(call_get_sew_pow_3663, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3663, 0, ret_val_get_sew_pow_3663); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3665; + auto illegal_fp_normal_3665_arg2 = SEW; + auto illegal_fp_normal_3665_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3665 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3665, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3665; + setArg(call_illegal_fp_normal_3665, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3665, 1, vd); + setArg(call_illegal_fp_normal_3665, 2, vm); + setArg(call_illegal_fp_normal_3665, 3, illegal_fp_normal_3665_arg2); + setArg(call_illegal_fp_normal_3665, 4, illegal_fp_normal_3665_arg3); + setRet(call_illegal_fp_normal_3665, 0, ret_val_illegal_fp_normal_3665); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3667; + x86::Gp ret_val_sew_3667 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3667, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3666; + auto fp_vector_unary_op_3666_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3666_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3666_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3666_arg9 = rm; + auto fp_vector_unary_op_3666_arg10 = ret_val_sew_3667; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3666, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3667, 0, reinterpret_cast(this)); + setRet(call_sew_3667, 0, ret_val_sew_3667); + setArg(call_fp_vector_unary_op_3666, 0, V); + setArg(call_fp_vector_unary_op_3666, 1, 19); + setArg(call_fp_vector_unary_op_3666, 2, 16); + setArg(call_fp_vector_unary_op_3666, 3, fp_vector_unary_op_3666_arg3); + setArg(call_fp_vector_unary_op_3666, 4, fp_vector_unary_op_3666_arg4); + setArg(call_fp_vector_unary_op_3666, 5, fp_vector_unary_op_3666_arg5); + setArg(call_fp_vector_unary_op_3666, 6, vm); + setArg(call_fp_vector_unary_op_3666, 7, vd); + setArg(call_fp_vector_unary_op_3666, 8, vs2); + setArg(call_fp_vector_unary_op_3666, 9, fp_vector_unary_op_3666_arg9); + setArg(call_fp_vector_unary_op_3666, 10, fp_vector_unary_op_3666_arg10); + } + cc.bind(label_merge); + } + auto tmp3668 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3668, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3668, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 763); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 764: VFMERGE__VFM */ + continuation_e __vfmerge__vfm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vfmerge.vfm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMERGE__VFM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 764); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3669; + x86::Gp ret_val_get_sew_pow_3669 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3669, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3670 = get_reg(cc, 8, false); + mov(cc, tmp3670, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3670, (ret_val_get_sew_pow_3669))), 8, false), ~ 1); + setArg(call_get_sew_pow_3669, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3669, 0, ret_val_get_sew_pow_3669); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_masked_3671; + auto illegal_fp_vd_masked_3671_arg1 = SEW; + auto illegal_fp_vd_masked_3671_arg2 = rm; + x86::Gp ret_val_illegal_fp_vd_masked_3671 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_masked_3671, (uintptr_t)&vm_impl::_illegal_fp_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_masked_3671; + setArg(call_illegal_fp_vd_masked_3671, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_masked_3671, 1, vd); + setArg(call_illegal_fp_vd_masked_3671, 2, illegal_fp_vd_masked_3671_arg1); + setArg(call_illegal_fp_vd_masked_3671, 3, illegal_fp_vd_masked_3671_arg2); + setRet(call_illegal_fp_vd_masked_3671, 0, ret_val_illegal_fp_vd_masked_3671); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3673; + x86::Gp ret_val_sew_3673 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3673, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_3672; + auto vector_imm_merge_3672_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_3672_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_3672_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_3672_arg7 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto vector_imm_merge_3672_arg8 = ret_val_sew_3673; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_3672, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_3673, 0, reinterpret_cast(this)); + setRet(call_sew_3673, 0, ret_val_sew_3673); + setArg(call_vector_imm_merge_3672, 0, V); + setArg(call_vector_imm_merge_3672, 1, vector_imm_merge_3672_arg1); + setArg(call_vector_imm_merge_3672, 2, vector_imm_merge_3672_arg2); + setArg(call_vector_imm_merge_3672, 3, vector_imm_merge_3672_arg3); + setArg(call_vector_imm_merge_3672, 4, 0); + setArg(call_vector_imm_merge_3672, 5, vd); + setArg(call_vector_imm_merge_3672, 6, vs2); + setArg(call_vector_imm_merge_3672, 7, vector_imm_merge_3672_arg7); + setArg(call_vector_imm_merge_3672, 8, vector_imm_merge_3672_arg8); + } + cc.bind(label_merge); + } + auto tmp3674 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3674, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3674, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 764); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 765: VFMV__V__F */ + continuation_e __vfmv__v__f(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vfmv.v.f"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMV__V__F_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 765); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3675; + x86::Gp ret_val_get_sew_pow_3675 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3675, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3676 = get_reg(cc, 8, false); + mov(cc, tmp3676, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3676, (ret_val_get_sew_pow_3675))), 8, false), ~ 1); + setArg(call_get_sew_pow_3675, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3675, 0, ret_val_get_sew_pow_3675); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3677; + auto illegal_fp_vd_unmasked_3677_arg0 = SEW; + auto illegal_fp_vd_unmasked_3677_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3677 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3677, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3677; + setArg(call_illegal_fp_vd_unmasked_3677, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3677, 1, illegal_fp_vd_unmasked_3677_arg0); + setArg(call_illegal_fp_vd_unmasked_3677, 2, illegal_fp_vd_unmasked_3677_arg1); + setRet(call_illegal_fp_vd_unmasked_3677, 0, ret_val_illegal_fp_vd_unmasked_3677); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3679; + x86::Gp ret_val_sew_3679 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3679, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_3678; + auto vector_imm_merge_3678_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_3678_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_3678_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_3678_arg7 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); + auto vector_imm_merge_3678_arg8 = ret_val_sew_3679; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_3678, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_3679, 0, reinterpret_cast(this)); + setRet(call_sew_3679, 0, ret_val_sew_3679); + setArg(call_vector_imm_merge_3678, 0, V); + setArg(call_vector_imm_merge_3678, 1, vector_imm_merge_3678_arg1); + setArg(call_vector_imm_merge_3678, 2, vector_imm_merge_3678_arg2); + setArg(call_vector_imm_merge_3678, 3, vector_imm_merge_3678_arg3); + setArg(call_vector_imm_merge_3678, 4, 1); + setArg(call_vector_imm_merge_3678, 5, vd); + setArg(call_vector_imm_merge_3678, 6, 0); + setArg(call_vector_imm_merge_3678, 7, vector_imm_merge_3678_arg7); + setArg(call_vector_imm_merge_3678, 8, vector_imm_merge_3678_arg8); + } + cc.bind(label_merge); + } + auto tmp3680 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3680, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3680, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 765); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 766: VFCVT__XU__F__V */ + continuation_e __vfcvt__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__XU__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 766); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3681; + x86::Gp ret_val_get_sew_pow_3681 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3681, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3682 = get_reg(cc, 8, false); + mov(cc, tmp3682, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3682, (ret_val_get_sew_pow_3681))), 8, false), ~ 1); + setArg(call_get_sew_pow_3681, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3681, 0, ret_val_get_sew_pow_3681); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3683; + auto illegal_fp_normal_3683_arg2 = SEW; + auto illegal_fp_normal_3683_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3683 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3683, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3683; + setArg(call_illegal_fp_normal_3683, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3683, 1, vd); + setArg(call_illegal_fp_normal_3683, 2, vm); + setArg(call_illegal_fp_normal_3683, 3, illegal_fp_normal_3683_arg2); + setArg(call_illegal_fp_normal_3683, 4, illegal_fp_normal_3683_arg3); + setRet(call_illegal_fp_normal_3683, 0, ret_val_illegal_fp_normal_3683); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3685; + x86::Gp ret_val_sew_3685 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3685, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3684; + auto fp_vector_unary_op_3684_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3684_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3684_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3684_arg9 = rm; + auto fp_vector_unary_op_3684_arg10 = ret_val_sew_3685; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3684, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3685, 0, reinterpret_cast(this)); + setRet(call_sew_3685, 0, ret_val_sew_3685); + setArg(call_fp_vector_unary_op_3684, 0, V); + setArg(call_fp_vector_unary_op_3684, 1, 18); + setArg(call_fp_vector_unary_op_3684, 2, 0); + setArg(call_fp_vector_unary_op_3684, 3, fp_vector_unary_op_3684_arg3); + setArg(call_fp_vector_unary_op_3684, 4, fp_vector_unary_op_3684_arg4); + setArg(call_fp_vector_unary_op_3684, 5, fp_vector_unary_op_3684_arg5); + setArg(call_fp_vector_unary_op_3684, 6, vm); + setArg(call_fp_vector_unary_op_3684, 7, vd); + setArg(call_fp_vector_unary_op_3684, 8, vs2); + setArg(call_fp_vector_unary_op_3684, 9, fp_vector_unary_op_3684_arg9); + setArg(call_fp_vector_unary_op_3684, 10, fp_vector_unary_op_3684_arg10); + } + cc.bind(label_merge); + } + auto tmp3686 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3686, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3686, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 766); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 767: VFCVT__X__F__V */ + continuation_e __vfcvt__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 767); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3687; + x86::Gp ret_val_get_sew_pow_3687 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3687, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3688 = get_reg(cc, 8, false); + mov(cc, tmp3688, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3688, (ret_val_get_sew_pow_3687))), 8, false), ~ 1); + setArg(call_get_sew_pow_3687, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3687, 0, ret_val_get_sew_pow_3687); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3689; + auto illegal_fp_normal_3689_arg2 = SEW; + auto illegal_fp_normal_3689_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3689 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3689, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3689; + setArg(call_illegal_fp_normal_3689, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3689, 1, vd); + setArg(call_illegal_fp_normal_3689, 2, vm); + setArg(call_illegal_fp_normal_3689, 3, illegal_fp_normal_3689_arg2); + setArg(call_illegal_fp_normal_3689, 4, illegal_fp_normal_3689_arg3); + setRet(call_illegal_fp_normal_3689, 0, ret_val_illegal_fp_normal_3689); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3691; + x86::Gp ret_val_sew_3691 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3691, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3690; + auto fp_vector_unary_op_3690_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3690_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3690_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3690_arg9 = rm; + auto fp_vector_unary_op_3690_arg10 = ret_val_sew_3691; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3690, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3691, 0, reinterpret_cast(this)); + setRet(call_sew_3691, 0, ret_val_sew_3691); + setArg(call_fp_vector_unary_op_3690, 0, V); + setArg(call_fp_vector_unary_op_3690, 1, 18); + setArg(call_fp_vector_unary_op_3690, 2, 1); + setArg(call_fp_vector_unary_op_3690, 3, fp_vector_unary_op_3690_arg3); + setArg(call_fp_vector_unary_op_3690, 4, fp_vector_unary_op_3690_arg4); + setArg(call_fp_vector_unary_op_3690, 5, fp_vector_unary_op_3690_arg5); + setArg(call_fp_vector_unary_op_3690, 6, vm); + setArg(call_fp_vector_unary_op_3690, 7, vd); + setArg(call_fp_vector_unary_op_3690, 8, vs2); + setArg(call_fp_vector_unary_op_3690, 9, fp_vector_unary_op_3690_arg9); + setArg(call_fp_vector_unary_op_3690, 10, fp_vector_unary_op_3690_arg10); + } + cc.bind(label_merge); + } + auto tmp3692 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3692, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3692, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 767); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 768: VFCVT__RTZ__XU__F__V */ + continuation_e __vfcvt__rtz__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.rtz.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__RTZ__XU__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 768); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3693; + x86::Gp ret_val_get_sew_pow_3693 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3693, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3694 = get_reg(cc, 8, false); + mov(cc, tmp3694, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3694, (ret_val_get_sew_pow_3693))), 8, false), ~ 1); + setArg(call_get_sew_pow_3693, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3693, 0, ret_val_get_sew_pow_3693); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3695; + auto illegal_fp_normal_3695_arg2 = SEW; + x86::Gp ret_val_illegal_fp_normal_3695 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3695, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3695; + setArg(call_illegal_fp_normal_3695, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3695, 1, vd); + setArg(call_illegal_fp_normal_3695, 2, vm); + setArg(call_illegal_fp_normal_3695, 3, illegal_fp_normal_3695_arg2); + setArg(call_illegal_fp_normal_3695, 4, rm); + setRet(call_illegal_fp_normal_3695, 0, ret_val_illegal_fp_normal_3695); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3697; + x86::Gp ret_val_sew_3697 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3697, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3696; + auto fp_vector_unary_op_3696_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3696_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3696_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3696_arg10 = ret_val_sew_3697; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3696, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3697, 0, reinterpret_cast(this)); + setRet(call_sew_3697, 0, ret_val_sew_3697); + setArg(call_fp_vector_unary_op_3696, 0, V); + setArg(call_fp_vector_unary_op_3696, 1, 18); + setArg(call_fp_vector_unary_op_3696, 2, 6); + setArg(call_fp_vector_unary_op_3696, 3, fp_vector_unary_op_3696_arg3); + setArg(call_fp_vector_unary_op_3696, 4, fp_vector_unary_op_3696_arg4); + setArg(call_fp_vector_unary_op_3696, 5, fp_vector_unary_op_3696_arg5); + setArg(call_fp_vector_unary_op_3696, 6, vm); + setArg(call_fp_vector_unary_op_3696, 7, vd); + setArg(call_fp_vector_unary_op_3696, 8, vs2); + setArg(call_fp_vector_unary_op_3696, 9, rm); + setArg(call_fp_vector_unary_op_3696, 10, fp_vector_unary_op_3696_arg10); + } + cc.bind(label_merge); + } + auto tmp3698 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3698, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3698, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 768); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 769: VFCVT__RTZ__X__F__V */ + continuation_e __vfcvt__rtz__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.rtz.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__RTZ__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 769); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3699; + x86::Gp ret_val_get_sew_pow_3699 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3699, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3700 = get_reg(cc, 8, false); + mov(cc, tmp3700, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3700, (ret_val_get_sew_pow_3699))), 8, false), ~ 1); + setArg(call_get_sew_pow_3699, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3699, 0, ret_val_get_sew_pow_3699); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3701; + auto illegal_fp_normal_3701_arg2 = SEW; + x86::Gp ret_val_illegal_fp_normal_3701 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3701, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3701; + setArg(call_illegal_fp_normal_3701, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3701, 1, vd); + setArg(call_illegal_fp_normal_3701, 2, vm); + setArg(call_illegal_fp_normal_3701, 3, illegal_fp_normal_3701_arg2); + setArg(call_illegal_fp_normal_3701, 4, rm); + setRet(call_illegal_fp_normal_3701, 0, ret_val_illegal_fp_normal_3701); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3703; + x86::Gp ret_val_sew_3703 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3703, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3702; + auto fp_vector_unary_op_3702_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3702_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3702_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3702_arg10 = ret_val_sew_3703; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3702, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3703, 0, reinterpret_cast(this)); + setRet(call_sew_3703, 0, ret_val_sew_3703); + setArg(call_fp_vector_unary_op_3702, 0, V); + setArg(call_fp_vector_unary_op_3702, 1, 18); + setArg(call_fp_vector_unary_op_3702, 2, 7); + setArg(call_fp_vector_unary_op_3702, 3, fp_vector_unary_op_3702_arg3); + setArg(call_fp_vector_unary_op_3702, 4, fp_vector_unary_op_3702_arg4); + setArg(call_fp_vector_unary_op_3702, 5, fp_vector_unary_op_3702_arg5); + setArg(call_fp_vector_unary_op_3702, 6, vm); + setArg(call_fp_vector_unary_op_3702, 7, vd); + setArg(call_fp_vector_unary_op_3702, 8, vs2); + setArg(call_fp_vector_unary_op_3702, 9, rm); + setArg(call_fp_vector_unary_op_3702, 10, fp_vector_unary_op_3702_arg10); + } + cc.bind(label_merge); + } + auto tmp3704 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3704, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3704, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 769); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 770: VFCVT__F__XU__V */ + continuation_e __vfcvt__f__xu__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.f.xu.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__F__XU__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 770); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3705; + x86::Gp ret_val_get_sew_pow_3705 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3705, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3706 = get_reg(cc, 8, false); + mov(cc, tmp3706, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3706, (ret_val_get_sew_pow_3705))), 8, false), ~ 1); + setArg(call_get_sew_pow_3705, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3705, 0, ret_val_get_sew_pow_3705); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3707; + auto illegal_fp_normal_3707_arg2 = SEW; + auto illegal_fp_normal_3707_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3707 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3707, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3707; + setArg(call_illegal_fp_normal_3707, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3707, 1, vd); + setArg(call_illegal_fp_normal_3707, 2, vm); + setArg(call_illegal_fp_normal_3707, 3, illegal_fp_normal_3707_arg2); + setArg(call_illegal_fp_normal_3707, 4, illegal_fp_normal_3707_arg3); + setRet(call_illegal_fp_normal_3707, 0, ret_val_illegal_fp_normal_3707); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3709; + x86::Gp ret_val_sew_3709 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3709, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3708; + auto fp_vector_unary_op_3708_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3708_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3708_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3708_arg9 = rm; + auto fp_vector_unary_op_3708_arg10 = ret_val_sew_3709; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3708, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3709, 0, reinterpret_cast(this)); + setRet(call_sew_3709, 0, ret_val_sew_3709); + setArg(call_fp_vector_unary_op_3708, 0, V); + setArg(call_fp_vector_unary_op_3708, 1, 18); + setArg(call_fp_vector_unary_op_3708, 2, 2); + setArg(call_fp_vector_unary_op_3708, 3, fp_vector_unary_op_3708_arg3); + setArg(call_fp_vector_unary_op_3708, 4, fp_vector_unary_op_3708_arg4); + setArg(call_fp_vector_unary_op_3708, 5, fp_vector_unary_op_3708_arg5); + setArg(call_fp_vector_unary_op_3708, 6, vm); + setArg(call_fp_vector_unary_op_3708, 7, vd); + setArg(call_fp_vector_unary_op_3708, 8, vs2); + setArg(call_fp_vector_unary_op_3708, 9, fp_vector_unary_op_3708_arg9); + setArg(call_fp_vector_unary_op_3708, 10, fp_vector_unary_op_3708_arg10); + } + cc.bind(label_merge); + } + auto tmp3710 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3710, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3710, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 770); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 771: VFCVT__F__X__V */ + continuation_e __vfcvt__f__x__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.f.x.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__F__X__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 771); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3711; + x86::Gp ret_val_get_sew_pow_3711 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3711, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3712 = get_reg(cc, 8, false); + mov(cc, tmp3712, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3712, (ret_val_get_sew_pow_3711))), 8, false), ~ 1); + setArg(call_get_sew_pow_3711, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3711, 0, ret_val_get_sew_pow_3711); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3713; + auto illegal_fp_normal_3713_arg2 = SEW; + auto illegal_fp_normal_3713_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3713 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3713, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3713; + setArg(call_illegal_fp_normal_3713, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3713, 1, vd); + setArg(call_illegal_fp_normal_3713, 2, vm); + setArg(call_illegal_fp_normal_3713, 3, illegal_fp_normal_3713_arg2); + setArg(call_illegal_fp_normal_3713, 4, illegal_fp_normal_3713_arg3); + setRet(call_illegal_fp_normal_3713, 0, ret_val_illegal_fp_normal_3713); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3715; + x86::Gp ret_val_sew_3715 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3715, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3714; + auto fp_vector_unary_op_3714_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3714_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3714_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3714_arg9 = rm; + auto fp_vector_unary_op_3714_arg10 = ret_val_sew_3715; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3714, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3715, 0, reinterpret_cast(this)); + setRet(call_sew_3715, 0, ret_val_sew_3715); + setArg(call_fp_vector_unary_op_3714, 0, V); + setArg(call_fp_vector_unary_op_3714, 1, 18); + setArg(call_fp_vector_unary_op_3714, 2, 3); + setArg(call_fp_vector_unary_op_3714, 3, fp_vector_unary_op_3714_arg3); + setArg(call_fp_vector_unary_op_3714, 4, fp_vector_unary_op_3714_arg4); + setArg(call_fp_vector_unary_op_3714, 5, fp_vector_unary_op_3714_arg5); + setArg(call_fp_vector_unary_op_3714, 6, vm); + setArg(call_fp_vector_unary_op_3714, 7, vd); + setArg(call_fp_vector_unary_op_3714, 8, vs2); + setArg(call_fp_vector_unary_op_3714, 9, fp_vector_unary_op_3714_arg9); + setArg(call_fp_vector_unary_op_3714, 10, fp_vector_unary_op_3714_arg10); + } + cc.bind(label_merge); + } + auto tmp3716 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3716, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3716, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 771); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 772: VFWCVT__XU__F__V */ + continuation_e __vfwcvt__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__XU__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 772); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3717; + x86::Gp ret_val_get_sew_pow_3717 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3717, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3718 = get_reg(cc, 8, false); + mov(cc, tmp3718, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3718, (ret_val_get_sew_pow_3717))), 8, false), ~ 1); + setArg(call_get_sew_pow_3717, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3717, 0, ret_val_get_sew_pow_3717); + InvokeNode* call_get_lmul_pow_3719; + x86::Gp ret_val_get_lmul_pow_3719 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3719, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3719; + setArg(call_get_lmul_pow_3719, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3719, 0, ret_val_get_lmul_pow_3719); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3720; + auto illegal_fp_variable_width_3720_arg2 = SEW; + auto illegal_fp_variable_width_3720_arg3 = rm; + auto illegal_fp_variable_width_3720_arg4 = SEW_widen; + auto illegal_fp_variable_width_3720_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3720 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3720, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3721; + auto valid_reg_overlap_3721_arg2 = LMUL_pow; + auto valid_reg_overlap_3721_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3721 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3721, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3720, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3721)); + setArg(call_illegal_fp_variable_width_3720, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3720, 1, vd); + setArg(call_illegal_fp_variable_width_3720, 2, vm); + setArg(call_illegal_fp_variable_width_3720, 3, illegal_fp_variable_width_3720_arg2); + setArg(call_illegal_fp_variable_width_3720, 4, illegal_fp_variable_width_3720_arg3); + setArg(call_illegal_fp_variable_width_3720, 5, illegal_fp_variable_width_3720_arg4); + setArg(call_illegal_fp_variable_width_3720, 6, illegal_fp_variable_width_3720_arg5); + setRet(call_illegal_fp_variable_width_3720, 0, ret_val_illegal_fp_variable_width_3720); + setArg(call_valid_reg_overlap_3721, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3721, 1, vs2); + setArg(call_valid_reg_overlap_3721, 2, vd); + setArg(call_valid_reg_overlap_3721, 3, valid_reg_overlap_3721_arg2); + setArg(call_valid_reg_overlap_3721, 4, valid_reg_overlap_3721_arg3); + setRet(call_valid_reg_overlap_3721, 0, ret_val_valid_reg_overlap_3721); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3723; + x86::Gp ret_val_sew_3723 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3723, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3722; + auto fp_vector_unary_w_3722_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3722_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3722_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3722_arg8 = rm; + auto fp_vector_unary_w_3722_arg9 = ret_val_sew_3723; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3722, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3723, 0, reinterpret_cast(this)); + setRet(call_sew_3723, 0, ret_val_sew_3723); + setArg(call_fp_vector_unary_w_3722, 0, V); + setArg(call_fp_vector_unary_w_3722, 1, 8); + setArg(call_fp_vector_unary_w_3722, 2, fp_vector_unary_w_3722_arg2); + setArg(call_fp_vector_unary_w_3722, 3, fp_vector_unary_w_3722_arg3); + setArg(call_fp_vector_unary_w_3722, 4, fp_vector_unary_w_3722_arg4); + setArg(call_fp_vector_unary_w_3722, 5, vm); + setArg(call_fp_vector_unary_w_3722, 6, vd); + setArg(call_fp_vector_unary_w_3722, 7, vs2); + setArg(call_fp_vector_unary_w_3722, 8, fp_vector_unary_w_3722_arg8); + setArg(call_fp_vector_unary_w_3722, 9, fp_vector_unary_w_3722_arg9); + } + cc.bind(label_merge); + } + auto tmp3724 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3724, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3724, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 772); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 773: VFWCVT__X__F__V */ + continuation_e __vfwcvt__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 773); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3725; + x86::Gp ret_val_get_sew_pow_3725 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3725, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3726 = get_reg(cc, 8, false); + mov(cc, tmp3726, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3726, (ret_val_get_sew_pow_3725))), 8, false), ~ 1); + setArg(call_get_sew_pow_3725, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3725, 0, ret_val_get_sew_pow_3725); + InvokeNode* call_get_lmul_pow_3727; + x86::Gp ret_val_get_lmul_pow_3727 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3727, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3727; + setArg(call_get_lmul_pow_3727, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3727, 0, ret_val_get_lmul_pow_3727); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3728; + auto illegal_fp_variable_width_3728_arg2 = SEW; + auto illegal_fp_variable_width_3728_arg3 = rm; + auto illegal_fp_variable_width_3728_arg4 = SEW_widen; + auto illegal_fp_variable_width_3728_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3728 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3728, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3729; + auto valid_reg_overlap_3729_arg2 = LMUL_pow; + auto valid_reg_overlap_3729_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3729 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3729, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3728, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3729)); + setArg(call_illegal_fp_variable_width_3728, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3728, 1, vd); + setArg(call_illegal_fp_variable_width_3728, 2, vm); + setArg(call_illegal_fp_variable_width_3728, 3, illegal_fp_variable_width_3728_arg2); + setArg(call_illegal_fp_variable_width_3728, 4, illegal_fp_variable_width_3728_arg3); + setArg(call_illegal_fp_variable_width_3728, 5, illegal_fp_variable_width_3728_arg4); + setArg(call_illegal_fp_variable_width_3728, 6, illegal_fp_variable_width_3728_arg5); + setRet(call_illegal_fp_variable_width_3728, 0, ret_val_illegal_fp_variable_width_3728); + setArg(call_valid_reg_overlap_3729, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3729, 1, vs2); + setArg(call_valid_reg_overlap_3729, 2, vd); + setArg(call_valid_reg_overlap_3729, 3, valid_reg_overlap_3729_arg2); + setArg(call_valid_reg_overlap_3729, 4, valid_reg_overlap_3729_arg3); + setRet(call_valid_reg_overlap_3729, 0, ret_val_valid_reg_overlap_3729); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3731; + x86::Gp ret_val_sew_3731 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3731, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3730; + auto fp_vector_unary_w_3730_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3730_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3730_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3730_arg8 = rm; + auto fp_vector_unary_w_3730_arg9 = ret_val_sew_3731; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3730, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3731, 0, reinterpret_cast(this)); + setRet(call_sew_3731, 0, ret_val_sew_3731); + setArg(call_fp_vector_unary_w_3730, 0, V); + setArg(call_fp_vector_unary_w_3730, 1, 9); + setArg(call_fp_vector_unary_w_3730, 2, fp_vector_unary_w_3730_arg2); + setArg(call_fp_vector_unary_w_3730, 3, fp_vector_unary_w_3730_arg3); + setArg(call_fp_vector_unary_w_3730, 4, fp_vector_unary_w_3730_arg4); + setArg(call_fp_vector_unary_w_3730, 5, vm); + setArg(call_fp_vector_unary_w_3730, 6, vd); + setArg(call_fp_vector_unary_w_3730, 7, vs2); + setArg(call_fp_vector_unary_w_3730, 8, fp_vector_unary_w_3730_arg8); + setArg(call_fp_vector_unary_w_3730, 9, fp_vector_unary_w_3730_arg9); + } + cc.bind(label_merge); + } + auto tmp3732 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3732, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3732, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 773); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 774: VFWCVT__RTZ__XU__F__V */ + continuation_e __vfwcvt__rtz__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__RTZ__XU__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 774); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3733; + x86::Gp ret_val_get_sew_pow_3733 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3733, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3734 = get_reg(cc, 8, false); + mov(cc, tmp3734, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3734, (ret_val_get_sew_pow_3733))), 8, false), ~ 1); + setArg(call_get_sew_pow_3733, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3733, 0, ret_val_get_sew_pow_3733); + InvokeNode* call_get_lmul_pow_3735; + x86::Gp ret_val_get_lmul_pow_3735 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3735, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3735; + setArg(call_get_lmul_pow_3735, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3735, 0, ret_val_get_lmul_pow_3735); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3736; + auto illegal_fp_variable_width_3736_arg2 = SEW; + auto illegal_fp_variable_width_3736_arg4 = SEW_widen; + auto illegal_fp_variable_width_3736_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3736 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3736, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3737; + auto valid_reg_overlap_3737_arg2 = LMUL_pow; + auto valid_reg_overlap_3737_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3737 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3737, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3736, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3737)); + setArg(call_illegal_fp_variable_width_3736, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3736, 1, vd); + setArg(call_illegal_fp_variable_width_3736, 2, vm); + setArg(call_illegal_fp_variable_width_3736, 3, illegal_fp_variable_width_3736_arg2); + setArg(call_illegal_fp_variable_width_3736, 4, rm); + setArg(call_illegal_fp_variable_width_3736, 5, illegal_fp_variable_width_3736_arg4); + setArg(call_illegal_fp_variable_width_3736, 6, illegal_fp_variable_width_3736_arg5); + setRet(call_illegal_fp_variable_width_3736, 0, ret_val_illegal_fp_variable_width_3736); + setArg(call_valid_reg_overlap_3737, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3737, 1, vs2); + setArg(call_valid_reg_overlap_3737, 2, vd); + setArg(call_valid_reg_overlap_3737, 3, valid_reg_overlap_3737_arg2); + setArg(call_valid_reg_overlap_3737, 4, valid_reg_overlap_3737_arg3); + setRet(call_valid_reg_overlap_3737, 0, ret_val_valid_reg_overlap_3737); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3739; + x86::Gp ret_val_sew_3739 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3739, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3738; + auto fp_vector_unary_w_3738_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3738_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3738_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3738_arg9 = ret_val_sew_3739; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3738, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3739, 0, reinterpret_cast(this)); + setRet(call_sew_3739, 0, ret_val_sew_3739); + setArg(call_fp_vector_unary_w_3738, 0, V); + setArg(call_fp_vector_unary_w_3738, 1, 14); + setArg(call_fp_vector_unary_w_3738, 2, fp_vector_unary_w_3738_arg2); + setArg(call_fp_vector_unary_w_3738, 3, fp_vector_unary_w_3738_arg3); + setArg(call_fp_vector_unary_w_3738, 4, fp_vector_unary_w_3738_arg4); + setArg(call_fp_vector_unary_w_3738, 5, vm); + setArg(call_fp_vector_unary_w_3738, 6, vd); + setArg(call_fp_vector_unary_w_3738, 7, vs2); + setArg(call_fp_vector_unary_w_3738, 8, rm); + setArg(call_fp_vector_unary_w_3738, 9, fp_vector_unary_w_3738_arg9); + } + cc.bind(label_merge); + } + auto tmp3740 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3740, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3740, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 774); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 775: VFWCVT__RTZ__X__F__V */ + continuation_e __vfwcvt__rtz__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__RTZ__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 775); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3741; + x86::Gp ret_val_get_sew_pow_3741 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3741, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3742 = get_reg(cc, 8, false); + mov(cc, tmp3742, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3742, (ret_val_get_sew_pow_3741))), 8, false), ~ 1); + setArg(call_get_sew_pow_3741, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3741, 0, ret_val_get_sew_pow_3741); + InvokeNode* call_get_lmul_pow_3743; + x86::Gp ret_val_get_lmul_pow_3743 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3743, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3743; + setArg(call_get_lmul_pow_3743, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3743, 0, ret_val_get_lmul_pow_3743); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3744; + auto illegal_fp_variable_width_3744_arg2 = SEW; + auto illegal_fp_variable_width_3744_arg4 = SEW_widen; + auto illegal_fp_variable_width_3744_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3744 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3744, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3745; + auto valid_reg_overlap_3745_arg2 = LMUL_pow; + auto valid_reg_overlap_3745_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3745 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3745, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3744, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3745)); + setArg(call_illegal_fp_variable_width_3744, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3744, 1, vd); + setArg(call_illegal_fp_variable_width_3744, 2, vm); + setArg(call_illegal_fp_variable_width_3744, 3, illegal_fp_variable_width_3744_arg2); + setArg(call_illegal_fp_variable_width_3744, 4, rm); + setArg(call_illegal_fp_variable_width_3744, 5, illegal_fp_variable_width_3744_arg4); + setArg(call_illegal_fp_variable_width_3744, 6, illegal_fp_variable_width_3744_arg5); + setRet(call_illegal_fp_variable_width_3744, 0, ret_val_illegal_fp_variable_width_3744); + setArg(call_valid_reg_overlap_3745, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3745, 1, vs2); + setArg(call_valid_reg_overlap_3745, 2, vd); + setArg(call_valid_reg_overlap_3745, 3, valid_reg_overlap_3745_arg2); + setArg(call_valid_reg_overlap_3745, 4, valid_reg_overlap_3745_arg3); + setRet(call_valid_reg_overlap_3745, 0, ret_val_valid_reg_overlap_3745); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3747; + x86::Gp ret_val_sew_3747 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3747, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3746; + auto fp_vector_unary_w_3746_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3746_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3746_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3746_arg9 = ret_val_sew_3747; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3746, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3747, 0, reinterpret_cast(this)); + setRet(call_sew_3747, 0, ret_val_sew_3747); + setArg(call_fp_vector_unary_w_3746, 0, V); + setArg(call_fp_vector_unary_w_3746, 1, 15); + setArg(call_fp_vector_unary_w_3746, 2, fp_vector_unary_w_3746_arg2); + setArg(call_fp_vector_unary_w_3746, 3, fp_vector_unary_w_3746_arg3); + setArg(call_fp_vector_unary_w_3746, 4, fp_vector_unary_w_3746_arg4); + setArg(call_fp_vector_unary_w_3746, 5, vm); + setArg(call_fp_vector_unary_w_3746, 6, vd); + setArg(call_fp_vector_unary_w_3746, 7, vs2); + setArg(call_fp_vector_unary_w_3746, 8, rm); + setArg(call_fp_vector_unary_w_3746, 9, fp_vector_unary_w_3746_arg9); + } + cc.bind(label_merge); + } + auto tmp3748 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3748, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3748, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 775); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 776: VFWCVT__F__XU__V */ + continuation_e __vfwcvt__f__xu__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.xu.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__F__XU__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 776); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3749; + x86::Gp ret_val_get_sew_pow_3749 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3749, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3750 = get_reg(cc, 8, false); + mov(cc, tmp3750, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3750, (ret_val_get_sew_pow_3749))), 8, false), ~ 1); + setArg(call_get_sew_pow_3749, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3749, 0, ret_val_get_sew_pow_3749); + InvokeNode* call_get_lmul_pow_3751; + x86::Gp ret_val_get_lmul_pow_3751 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3751, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3751; + setArg(call_get_lmul_pow_3751, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3751, 0, ret_val_get_lmul_pow_3751); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3752; + auto illegal_fp_variable_width_3752_arg2 = SEW; + auto illegal_fp_variable_width_3752_arg3 = rm; + auto illegal_fp_variable_width_3752_arg4 = SEW_widen; + auto illegal_fp_variable_width_3752_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3752 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3752, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3753; + auto valid_reg_overlap_3753_arg2 = LMUL_pow; + auto valid_reg_overlap_3753_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3753 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3753, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3752, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3753)); + setArg(call_illegal_fp_variable_width_3752, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3752, 1, vd); + setArg(call_illegal_fp_variable_width_3752, 2, vm); + setArg(call_illegal_fp_variable_width_3752, 3, illegal_fp_variable_width_3752_arg2); + setArg(call_illegal_fp_variable_width_3752, 4, illegal_fp_variable_width_3752_arg3); + setArg(call_illegal_fp_variable_width_3752, 5, illegal_fp_variable_width_3752_arg4); + setArg(call_illegal_fp_variable_width_3752, 6, illegal_fp_variable_width_3752_arg5); + setRet(call_illegal_fp_variable_width_3752, 0, ret_val_illegal_fp_variable_width_3752); + setArg(call_valid_reg_overlap_3753, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3753, 1, vs2); + setArg(call_valid_reg_overlap_3753, 2, vd); + setArg(call_valid_reg_overlap_3753, 3, valid_reg_overlap_3753_arg2); + setArg(call_valid_reg_overlap_3753, 4, valid_reg_overlap_3753_arg3); + setRet(call_valid_reg_overlap_3753, 0, ret_val_valid_reg_overlap_3753); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3755; + x86::Gp ret_val_sew_3755 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3755, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3754; + auto fp_vector_unary_w_3754_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3754_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3754_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3754_arg8 = rm; + auto fp_vector_unary_w_3754_arg9 = ret_val_sew_3755; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3754, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3755, 0, reinterpret_cast(this)); + setRet(call_sew_3755, 0, ret_val_sew_3755); + setArg(call_fp_vector_unary_w_3754, 0, V); + setArg(call_fp_vector_unary_w_3754, 1, 10); + setArg(call_fp_vector_unary_w_3754, 2, fp_vector_unary_w_3754_arg2); + setArg(call_fp_vector_unary_w_3754, 3, fp_vector_unary_w_3754_arg3); + setArg(call_fp_vector_unary_w_3754, 4, fp_vector_unary_w_3754_arg4); + setArg(call_fp_vector_unary_w_3754, 5, vm); + setArg(call_fp_vector_unary_w_3754, 6, vd); + setArg(call_fp_vector_unary_w_3754, 7, vs2); + setArg(call_fp_vector_unary_w_3754, 8, fp_vector_unary_w_3754_arg8); + setArg(call_fp_vector_unary_w_3754, 9, fp_vector_unary_w_3754_arg9); + } + cc.bind(label_merge); + } + auto tmp3756 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3756, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3756, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 776); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 777: VFWCVT__F__X__V */ + continuation_e __vfwcvt__f__x__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.x.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__F__X__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 777); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3757; + x86::Gp ret_val_get_sew_pow_3757 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3757, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3758 = get_reg(cc, 8, false); + mov(cc, tmp3758, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3758, (ret_val_get_sew_pow_3757))), 8, false), ~ 1); + setArg(call_get_sew_pow_3757, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3757, 0, ret_val_get_sew_pow_3757); + InvokeNode* call_get_lmul_pow_3759; + x86::Gp ret_val_get_lmul_pow_3759 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3759, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3759; + setArg(call_get_lmul_pow_3759, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3759, 0, ret_val_get_lmul_pow_3759); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3760; + auto illegal_fp_variable_width_3760_arg2 = SEW; + auto illegal_fp_variable_width_3760_arg3 = rm; + auto illegal_fp_variable_width_3760_arg4 = SEW_widen; + auto illegal_fp_variable_width_3760_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3760 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3760, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3761; + auto valid_reg_overlap_3761_arg2 = LMUL_pow; + auto valid_reg_overlap_3761_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3761 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3761, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3760, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3761)); + setArg(call_illegal_fp_variable_width_3760, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3760, 1, vd); + setArg(call_illegal_fp_variable_width_3760, 2, vm); + setArg(call_illegal_fp_variable_width_3760, 3, illegal_fp_variable_width_3760_arg2); + setArg(call_illegal_fp_variable_width_3760, 4, illegal_fp_variable_width_3760_arg3); + setArg(call_illegal_fp_variable_width_3760, 5, illegal_fp_variable_width_3760_arg4); + setArg(call_illegal_fp_variable_width_3760, 6, illegal_fp_variable_width_3760_arg5); + setRet(call_illegal_fp_variable_width_3760, 0, ret_val_illegal_fp_variable_width_3760); + setArg(call_valid_reg_overlap_3761, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3761, 1, vs2); + setArg(call_valid_reg_overlap_3761, 2, vd); + setArg(call_valid_reg_overlap_3761, 3, valid_reg_overlap_3761_arg2); + setArg(call_valid_reg_overlap_3761, 4, valid_reg_overlap_3761_arg3); + setRet(call_valid_reg_overlap_3761, 0, ret_val_valid_reg_overlap_3761); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3763; + x86::Gp ret_val_sew_3763 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3763, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3762; + auto fp_vector_unary_w_3762_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3762_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3762_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3762_arg8 = rm; + auto fp_vector_unary_w_3762_arg9 = ret_val_sew_3763; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3762, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3763, 0, reinterpret_cast(this)); + setRet(call_sew_3763, 0, ret_val_sew_3763); + setArg(call_fp_vector_unary_w_3762, 0, V); + setArg(call_fp_vector_unary_w_3762, 1, 11); + setArg(call_fp_vector_unary_w_3762, 2, fp_vector_unary_w_3762_arg2); + setArg(call_fp_vector_unary_w_3762, 3, fp_vector_unary_w_3762_arg3); + setArg(call_fp_vector_unary_w_3762, 4, fp_vector_unary_w_3762_arg4); + setArg(call_fp_vector_unary_w_3762, 5, vm); + setArg(call_fp_vector_unary_w_3762, 6, vd); + setArg(call_fp_vector_unary_w_3762, 7, vs2); + setArg(call_fp_vector_unary_w_3762, 8, fp_vector_unary_w_3762_arg8); + setArg(call_fp_vector_unary_w_3762, 9, fp_vector_unary_w_3762_arg9); + } + cc.bind(label_merge); + } + auto tmp3764 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3764, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3764, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 777); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 778: VFWCVT__F__F__V */ + continuation_e __vfwcvt__f__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__F__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 778); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3765; + x86::Gp ret_val_get_sew_pow_3765 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3765, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3766 = get_reg(cc, 8, false); + mov(cc, tmp3766, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3766, (ret_val_get_sew_pow_3765))), 8, false), ~ 1); + setArg(call_get_sew_pow_3765, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3765, 0, ret_val_get_sew_pow_3765); + InvokeNode* call_get_lmul_pow_3767; + x86::Gp ret_val_get_lmul_pow_3767 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3767, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3767; + setArg(call_get_lmul_pow_3767, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3767, 0, ret_val_get_lmul_pow_3767); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3768; + auto illegal_fp_variable_width_3768_arg2 = SEW; + auto illegal_fp_variable_width_3768_arg3 = rm; + auto illegal_fp_variable_width_3768_arg4 = SEW_widen; + auto illegal_fp_variable_width_3768_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3768 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3768, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3769; + auto valid_reg_overlap_3769_arg2 = LMUL_pow; + auto valid_reg_overlap_3769_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3769 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3769, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3768, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3769)); + setArg(call_illegal_fp_variable_width_3768, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3768, 1, vd); + setArg(call_illegal_fp_variable_width_3768, 2, vm); + setArg(call_illegal_fp_variable_width_3768, 3, illegal_fp_variable_width_3768_arg2); + setArg(call_illegal_fp_variable_width_3768, 4, illegal_fp_variable_width_3768_arg3); + setArg(call_illegal_fp_variable_width_3768, 5, illegal_fp_variable_width_3768_arg4); + setArg(call_illegal_fp_variable_width_3768, 6, illegal_fp_variable_width_3768_arg5); + setRet(call_illegal_fp_variable_width_3768, 0, ret_val_illegal_fp_variable_width_3768); + setArg(call_valid_reg_overlap_3769, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3769, 1, vs2); + setArg(call_valid_reg_overlap_3769, 2, vd); + setArg(call_valid_reg_overlap_3769, 3, valid_reg_overlap_3769_arg2); + setArg(call_valid_reg_overlap_3769, 4, valid_reg_overlap_3769_arg3); + setRet(call_valid_reg_overlap_3769, 0, ret_val_valid_reg_overlap_3769); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3771; + x86::Gp ret_val_sew_3771 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3771, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3770; + auto fp_vector_unary_w_3770_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3770_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3770_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3770_arg8 = rm; + auto fp_vector_unary_w_3770_arg9 = ret_val_sew_3771; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3770, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3771, 0, reinterpret_cast(this)); + setRet(call_sew_3771, 0, ret_val_sew_3771); + setArg(call_fp_vector_unary_w_3770, 0, V); + setArg(call_fp_vector_unary_w_3770, 1, 12); + setArg(call_fp_vector_unary_w_3770, 2, fp_vector_unary_w_3770_arg2); + setArg(call_fp_vector_unary_w_3770, 3, fp_vector_unary_w_3770_arg3); + setArg(call_fp_vector_unary_w_3770, 4, fp_vector_unary_w_3770_arg4); + setArg(call_fp_vector_unary_w_3770, 5, vm); + setArg(call_fp_vector_unary_w_3770, 6, vd); + setArg(call_fp_vector_unary_w_3770, 7, vs2); + setArg(call_fp_vector_unary_w_3770, 8, fp_vector_unary_w_3770_arg8); + setArg(call_fp_vector_unary_w_3770, 9, fp_vector_unary_w_3770_arg9); + } + cc.bind(label_merge); + } + auto tmp3772 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3772, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3772, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 778); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 779: VFNCVT__X__F__W */ + continuation_e __vfncvt__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.x.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__X__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 779); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3773; + x86::Gp ret_val_get_sew_pow_3773 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3773, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3774 = get_reg(cc, 8, false); + mov(cc, tmp3774, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3774, (ret_val_get_sew_pow_3773))), 8, false), ~ 1); + setArg(call_get_sew_pow_3773, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3773, 0, ret_val_get_sew_pow_3773); + InvokeNode* call_get_lmul_pow_3775; + x86::Gp ret_val_get_lmul_pow_3775 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3775, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3775; + setArg(call_get_lmul_pow_3775, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3775, 0, ret_val_get_lmul_pow_3775); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3776; + auto illegal_fp_variable_width_3776_arg2 = SEW; + auto illegal_fp_variable_width_3776_arg3 = rm; + auto illegal_fp_variable_width_3776_arg4 = SEW_widen; + auto illegal_fp_variable_width_3776_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3776 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3776, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3777; + auto valid_reg_overlap_3777_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3777_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3777 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3777, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3776, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3777)); + setArg(call_illegal_fp_variable_width_3776, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3776, 1, vd); + setArg(call_illegal_fp_variable_width_3776, 2, vm); + setArg(call_illegal_fp_variable_width_3776, 3, illegal_fp_variable_width_3776_arg2); + setArg(call_illegal_fp_variable_width_3776, 4, illegal_fp_variable_width_3776_arg3); + setArg(call_illegal_fp_variable_width_3776, 5, illegal_fp_variable_width_3776_arg4); + setArg(call_illegal_fp_variable_width_3776, 6, illegal_fp_variable_width_3776_arg5); + setRet(call_illegal_fp_variable_width_3776, 0, ret_val_illegal_fp_variable_width_3776); + setArg(call_valid_reg_overlap_3777, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3777, 1, vs2); + setArg(call_valid_reg_overlap_3777, 2, vd); + setArg(call_valid_reg_overlap_3777, 3, valid_reg_overlap_3777_arg2); + setArg(call_valid_reg_overlap_3777, 4, valid_reg_overlap_3777_arg3); + setRet(call_valid_reg_overlap_3777, 0, ret_val_valid_reg_overlap_3777); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3779; + x86::Gp ret_val_sew_3779 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3779, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3778; + auto fp_vector_unary_n_3778_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3778_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3778_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3778_arg8 = rm; + auto fp_vector_unary_n_3778_arg9 = ret_val_sew_3779; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3778, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3779, 0, reinterpret_cast(this)); + setRet(call_sew_3779, 0, ret_val_sew_3779); + setArg(call_fp_vector_unary_n_3778, 0, V); + setArg(call_fp_vector_unary_n_3778, 1, 17); + setArg(call_fp_vector_unary_n_3778, 2, fp_vector_unary_n_3778_arg2); + setArg(call_fp_vector_unary_n_3778, 3, fp_vector_unary_n_3778_arg3); + setArg(call_fp_vector_unary_n_3778, 4, fp_vector_unary_n_3778_arg4); + setArg(call_fp_vector_unary_n_3778, 5, vm); + setArg(call_fp_vector_unary_n_3778, 6, vd); + setArg(call_fp_vector_unary_n_3778, 7, vs2); + setArg(call_fp_vector_unary_n_3778, 8, fp_vector_unary_n_3778_arg8); + setArg(call_fp_vector_unary_n_3778, 9, fp_vector_unary_n_3778_arg9); + } + cc.bind(label_merge); + } + auto tmp3780 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3780, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3780, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 779); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 780: VFNCVT__XU__F__W */ + continuation_e __vfncvt__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.xu.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__XU__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 780); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3781; + x86::Gp ret_val_get_sew_pow_3781 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3781, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3782 = get_reg(cc, 8, false); + mov(cc, tmp3782, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3782, (ret_val_get_sew_pow_3781))), 8, false), ~ 1); + setArg(call_get_sew_pow_3781, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3781, 0, ret_val_get_sew_pow_3781); + InvokeNode* call_get_lmul_pow_3783; + x86::Gp ret_val_get_lmul_pow_3783 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3783, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3783; + setArg(call_get_lmul_pow_3783, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3783, 0, ret_val_get_lmul_pow_3783); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3784; + auto illegal_fp_variable_width_3784_arg2 = SEW; + auto illegal_fp_variable_width_3784_arg3 = rm; + auto illegal_fp_variable_width_3784_arg4 = SEW_widen; + auto illegal_fp_variable_width_3784_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3784 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3784, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3785; + auto valid_reg_overlap_3785_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3785_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3785 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3785, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3784, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3785)); + setArg(call_illegal_fp_variable_width_3784, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3784, 1, vd); + setArg(call_illegal_fp_variable_width_3784, 2, vm); + setArg(call_illegal_fp_variable_width_3784, 3, illegal_fp_variable_width_3784_arg2); + setArg(call_illegal_fp_variable_width_3784, 4, illegal_fp_variable_width_3784_arg3); + setArg(call_illegal_fp_variable_width_3784, 5, illegal_fp_variable_width_3784_arg4); + setArg(call_illegal_fp_variable_width_3784, 6, illegal_fp_variable_width_3784_arg5); + setRet(call_illegal_fp_variable_width_3784, 0, ret_val_illegal_fp_variable_width_3784); + setArg(call_valid_reg_overlap_3785, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3785, 1, vs2); + setArg(call_valid_reg_overlap_3785, 2, vd); + setArg(call_valid_reg_overlap_3785, 3, valid_reg_overlap_3785_arg2); + setArg(call_valid_reg_overlap_3785, 4, valid_reg_overlap_3785_arg3); + setRet(call_valid_reg_overlap_3785, 0, ret_val_valid_reg_overlap_3785); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3787; + x86::Gp ret_val_sew_3787 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3787, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3786; + auto fp_vector_unary_n_3786_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3786_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3786_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3786_arg8 = rm; + auto fp_vector_unary_n_3786_arg9 = ret_val_sew_3787; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3786, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3787, 0, reinterpret_cast(this)); + setRet(call_sew_3787, 0, ret_val_sew_3787); + setArg(call_fp_vector_unary_n_3786, 0, V); + setArg(call_fp_vector_unary_n_3786, 1, 16); + setArg(call_fp_vector_unary_n_3786, 2, fp_vector_unary_n_3786_arg2); + setArg(call_fp_vector_unary_n_3786, 3, fp_vector_unary_n_3786_arg3); + setArg(call_fp_vector_unary_n_3786, 4, fp_vector_unary_n_3786_arg4); + setArg(call_fp_vector_unary_n_3786, 5, vm); + setArg(call_fp_vector_unary_n_3786, 6, vd); + setArg(call_fp_vector_unary_n_3786, 7, vs2); + setArg(call_fp_vector_unary_n_3786, 8, fp_vector_unary_n_3786_arg8); + setArg(call_fp_vector_unary_n_3786, 9, fp_vector_unary_n_3786_arg9); + } + cc.bind(label_merge); + } + auto tmp3788 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3788, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3788, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 780); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 781: VFNCVT__RTZ__XU__F__W */ + continuation_e __vfncvt__rtz__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.xu.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__RTZ__XU__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 781); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3789; + x86::Gp ret_val_get_sew_pow_3789 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3789, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3790 = get_reg(cc, 8, false); + mov(cc, tmp3790, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3790, (ret_val_get_sew_pow_3789))), 8, false), ~ 1); + setArg(call_get_sew_pow_3789, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3789, 0, ret_val_get_sew_pow_3789); + InvokeNode* call_get_lmul_pow_3791; + x86::Gp ret_val_get_lmul_pow_3791 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3791, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3791; + setArg(call_get_lmul_pow_3791, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3791, 0, ret_val_get_lmul_pow_3791); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3792; + auto illegal_fp_variable_width_3792_arg2 = SEW; + auto illegal_fp_variable_width_3792_arg4 = SEW_widen; + auto illegal_fp_variable_width_3792_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3792 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3792, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3793; + auto valid_reg_overlap_3793_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3793_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3793 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3793, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3792, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3793)); + setArg(call_illegal_fp_variable_width_3792, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3792, 1, vd); + setArg(call_illegal_fp_variable_width_3792, 2, vm); + setArg(call_illegal_fp_variable_width_3792, 3, illegal_fp_variable_width_3792_arg2); + setArg(call_illegal_fp_variable_width_3792, 4, rm); + setArg(call_illegal_fp_variable_width_3792, 5, illegal_fp_variable_width_3792_arg4); + setArg(call_illegal_fp_variable_width_3792, 6, illegal_fp_variable_width_3792_arg5); + setRet(call_illegal_fp_variable_width_3792, 0, ret_val_illegal_fp_variable_width_3792); + setArg(call_valid_reg_overlap_3793, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3793, 1, vs2); + setArg(call_valid_reg_overlap_3793, 2, vd); + setArg(call_valid_reg_overlap_3793, 3, valid_reg_overlap_3793_arg2); + setArg(call_valid_reg_overlap_3793, 4, valid_reg_overlap_3793_arg3); + setRet(call_valid_reg_overlap_3793, 0, ret_val_valid_reg_overlap_3793); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3795; + x86::Gp ret_val_sew_3795 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3795, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3794; + auto fp_vector_unary_n_3794_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3794_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3794_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3794_arg9 = ret_val_sew_3795; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3794, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3795, 0, reinterpret_cast(this)); + setRet(call_sew_3795, 0, ret_val_sew_3795); + setArg(call_fp_vector_unary_n_3794, 0, V); + setArg(call_fp_vector_unary_n_3794, 1, 22); + setArg(call_fp_vector_unary_n_3794, 2, fp_vector_unary_n_3794_arg2); + setArg(call_fp_vector_unary_n_3794, 3, fp_vector_unary_n_3794_arg3); + setArg(call_fp_vector_unary_n_3794, 4, fp_vector_unary_n_3794_arg4); + setArg(call_fp_vector_unary_n_3794, 5, vm); + setArg(call_fp_vector_unary_n_3794, 6, vd); + setArg(call_fp_vector_unary_n_3794, 7, vs2); + setArg(call_fp_vector_unary_n_3794, 8, rm); + setArg(call_fp_vector_unary_n_3794, 9, fp_vector_unary_n_3794_arg9); + } + cc.bind(label_merge); + } + auto tmp3796 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3796, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3796, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 781); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 782: VFNCVT__RTZ__X__F__W */ + continuation_e __vfncvt__rtz__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.x.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__RTZ__X__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 782); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3797; + x86::Gp ret_val_get_sew_pow_3797 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3797, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3798 = get_reg(cc, 8, false); + mov(cc, tmp3798, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3798, (ret_val_get_sew_pow_3797))), 8, false), ~ 1); + setArg(call_get_sew_pow_3797, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3797, 0, ret_val_get_sew_pow_3797); + InvokeNode* call_get_lmul_pow_3799; + x86::Gp ret_val_get_lmul_pow_3799 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3799, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3799; + setArg(call_get_lmul_pow_3799, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3799, 0, ret_val_get_lmul_pow_3799); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3800; + auto illegal_fp_variable_width_3800_arg2 = SEW; + auto illegal_fp_variable_width_3800_arg4 = SEW_widen; + auto illegal_fp_variable_width_3800_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3800 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3800, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3801; + auto valid_reg_overlap_3801_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3801_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3801 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3801, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3800, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3801)); + setArg(call_illegal_fp_variable_width_3800, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3800, 1, vd); + setArg(call_illegal_fp_variable_width_3800, 2, vm); + setArg(call_illegal_fp_variable_width_3800, 3, illegal_fp_variable_width_3800_arg2); + setArg(call_illegal_fp_variable_width_3800, 4, rm); + setArg(call_illegal_fp_variable_width_3800, 5, illegal_fp_variable_width_3800_arg4); + setArg(call_illegal_fp_variable_width_3800, 6, illegal_fp_variable_width_3800_arg5); + setRet(call_illegal_fp_variable_width_3800, 0, ret_val_illegal_fp_variable_width_3800); + setArg(call_valid_reg_overlap_3801, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3801, 1, vs2); + setArg(call_valid_reg_overlap_3801, 2, vd); + setArg(call_valid_reg_overlap_3801, 3, valid_reg_overlap_3801_arg2); + setArg(call_valid_reg_overlap_3801, 4, valid_reg_overlap_3801_arg3); + setRet(call_valid_reg_overlap_3801, 0, ret_val_valid_reg_overlap_3801); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3803; + x86::Gp ret_val_sew_3803 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3803, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3802; + auto fp_vector_unary_n_3802_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3802_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3802_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3802_arg9 = ret_val_sew_3803; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3802, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3803, 0, reinterpret_cast(this)); + setRet(call_sew_3803, 0, ret_val_sew_3803); + setArg(call_fp_vector_unary_n_3802, 0, V); + setArg(call_fp_vector_unary_n_3802, 1, 23); + setArg(call_fp_vector_unary_n_3802, 2, fp_vector_unary_n_3802_arg2); + setArg(call_fp_vector_unary_n_3802, 3, fp_vector_unary_n_3802_arg3); + setArg(call_fp_vector_unary_n_3802, 4, fp_vector_unary_n_3802_arg4); + setArg(call_fp_vector_unary_n_3802, 5, vm); + setArg(call_fp_vector_unary_n_3802, 6, vd); + setArg(call_fp_vector_unary_n_3802, 7, vs2); + setArg(call_fp_vector_unary_n_3802, 8, rm); + setArg(call_fp_vector_unary_n_3802, 9, fp_vector_unary_n_3802_arg9); + } + cc.bind(label_merge); + } + auto tmp3804 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3804, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3804, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 782); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 783: VFNCVT__F__XU__W */ + continuation_e __vfncvt__f__xu__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.xu.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__F__XU__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 783); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3805; + x86::Gp ret_val_get_sew_pow_3805 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3805, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3806 = get_reg(cc, 8, false); + mov(cc, tmp3806, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3806, (ret_val_get_sew_pow_3805))), 8, false), ~ 1); + setArg(call_get_sew_pow_3805, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3805, 0, ret_val_get_sew_pow_3805); + InvokeNode* call_get_lmul_pow_3807; + x86::Gp ret_val_get_lmul_pow_3807 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3807, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3807; + setArg(call_get_lmul_pow_3807, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3807, 0, ret_val_get_lmul_pow_3807); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3808; + auto illegal_fp_variable_width_3808_arg2 = SEW; + auto illegal_fp_variable_width_3808_arg3 = rm; + auto illegal_fp_variable_width_3808_arg4 = SEW_widen; + auto illegal_fp_variable_width_3808_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3808 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3808, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3809; + auto valid_reg_overlap_3809_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3809_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3809 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3809, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3808, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3809)); + setArg(call_illegal_fp_variable_width_3808, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3808, 1, vd); + setArg(call_illegal_fp_variable_width_3808, 2, vm); + setArg(call_illegal_fp_variable_width_3808, 3, illegal_fp_variable_width_3808_arg2); + setArg(call_illegal_fp_variable_width_3808, 4, illegal_fp_variable_width_3808_arg3); + setArg(call_illegal_fp_variable_width_3808, 5, illegal_fp_variable_width_3808_arg4); + setArg(call_illegal_fp_variable_width_3808, 6, illegal_fp_variable_width_3808_arg5); + setRet(call_illegal_fp_variable_width_3808, 0, ret_val_illegal_fp_variable_width_3808); + setArg(call_valid_reg_overlap_3809, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3809, 1, vs2); + setArg(call_valid_reg_overlap_3809, 2, vd); + setArg(call_valid_reg_overlap_3809, 3, valid_reg_overlap_3809_arg2); + setArg(call_valid_reg_overlap_3809, 4, valid_reg_overlap_3809_arg3); + setRet(call_valid_reg_overlap_3809, 0, ret_val_valid_reg_overlap_3809); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3811; + x86::Gp ret_val_sew_3811 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3811, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3810; + auto fp_vector_unary_n_3810_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3810_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3810_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3810_arg8 = rm; + auto fp_vector_unary_n_3810_arg9 = ret_val_sew_3811; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3810, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3811, 0, reinterpret_cast(this)); + setRet(call_sew_3811, 0, ret_val_sew_3811); + setArg(call_fp_vector_unary_n_3810, 0, V); + setArg(call_fp_vector_unary_n_3810, 1, 18); + setArg(call_fp_vector_unary_n_3810, 2, fp_vector_unary_n_3810_arg2); + setArg(call_fp_vector_unary_n_3810, 3, fp_vector_unary_n_3810_arg3); + setArg(call_fp_vector_unary_n_3810, 4, fp_vector_unary_n_3810_arg4); + setArg(call_fp_vector_unary_n_3810, 5, vm); + setArg(call_fp_vector_unary_n_3810, 6, vd); + setArg(call_fp_vector_unary_n_3810, 7, vs2); + setArg(call_fp_vector_unary_n_3810, 8, fp_vector_unary_n_3810_arg8); + setArg(call_fp_vector_unary_n_3810, 9, fp_vector_unary_n_3810_arg9); + } + cc.bind(label_merge); + } + auto tmp3812 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3812, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3812, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 783); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 784: VFNCVT__F__X__W */ + continuation_e __vfncvt__f__x__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.x.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__F__X__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 784); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3813; + x86::Gp ret_val_get_sew_pow_3813 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3813, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3814 = get_reg(cc, 8, false); + mov(cc, tmp3814, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3814, (ret_val_get_sew_pow_3813))), 8, false), ~ 1); + setArg(call_get_sew_pow_3813, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3813, 0, ret_val_get_sew_pow_3813); + InvokeNode* call_get_lmul_pow_3815; + x86::Gp ret_val_get_lmul_pow_3815 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3815, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3815; + setArg(call_get_lmul_pow_3815, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3815, 0, ret_val_get_lmul_pow_3815); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3816; + auto illegal_fp_variable_width_3816_arg2 = SEW; + auto illegal_fp_variable_width_3816_arg3 = rm; + auto illegal_fp_variable_width_3816_arg4 = SEW_widen; + auto illegal_fp_variable_width_3816_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3816 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3816, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3817; + auto valid_reg_overlap_3817_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3817_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3817 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3817, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3816, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3817)); + setArg(call_illegal_fp_variable_width_3816, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3816, 1, vd); + setArg(call_illegal_fp_variable_width_3816, 2, vm); + setArg(call_illegal_fp_variable_width_3816, 3, illegal_fp_variable_width_3816_arg2); + setArg(call_illegal_fp_variable_width_3816, 4, illegal_fp_variable_width_3816_arg3); + setArg(call_illegal_fp_variable_width_3816, 5, illegal_fp_variable_width_3816_arg4); + setArg(call_illegal_fp_variable_width_3816, 6, illegal_fp_variable_width_3816_arg5); + setRet(call_illegal_fp_variable_width_3816, 0, ret_val_illegal_fp_variable_width_3816); + setArg(call_valid_reg_overlap_3817, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3817, 1, vs2); + setArg(call_valid_reg_overlap_3817, 2, vd); + setArg(call_valid_reg_overlap_3817, 3, valid_reg_overlap_3817_arg2); + setArg(call_valid_reg_overlap_3817, 4, valid_reg_overlap_3817_arg3); + setRet(call_valid_reg_overlap_3817, 0, ret_val_valid_reg_overlap_3817); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3819; + x86::Gp ret_val_sew_3819 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3819, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3818; + auto fp_vector_unary_n_3818_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3818_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3818_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3818_arg8 = rm; + auto fp_vector_unary_n_3818_arg9 = ret_val_sew_3819; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3818, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3819, 0, reinterpret_cast(this)); + setRet(call_sew_3819, 0, ret_val_sew_3819); + setArg(call_fp_vector_unary_n_3818, 0, V); + setArg(call_fp_vector_unary_n_3818, 1, 19); + setArg(call_fp_vector_unary_n_3818, 2, fp_vector_unary_n_3818_arg2); + setArg(call_fp_vector_unary_n_3818, 3, fp_vector_unary_n_3818_arg3); + setArg(call_fp_vector_unary_n_3818, 4, fp_vector_unary_n_3818_arg4); + setArg(call_fp_vector_unary_n_3818, 5, vm); + setArg(call_fp_vector_unary_n_3818, 6, vd); + setArg(call_fp_vector_unary_n_3818, 7, vs2); + setArg(call_fp_vector_unary_n_3818, 8, fp_vector_unary_n_3818_arg8); + setArg(call_fp_vector_unary_n_3818, 9, fp_vector_unary_n_3818_arg9); + } + cc.bind(label_merge); + } + auto tmp3820 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3820, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3820, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 784); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 785: VFNCVT__F__F__W */ + continuation_e __vfncvt__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__F__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 785); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3821; + x86::Gp ret_val_get_sew_pow_3821 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3821, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3822 = get_reg(cc, 8, false); + mov(cc, tmp3822, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3822, (ret_val_get_sew_pow_3821))), 8, false), ~ 1); + setArg(call_get_sew_pow_3821, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3821, 0, ret_val_get_sew_pow_3821); + InvokeNode* call_get_lmul_pow_3823; + x86::Gp ret_val_get_lmul_pow_3823 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3823, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3823; + setArg(call_get_lmul_pow_3823, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3823, 0, ret_val_get_lmul_pow_3823); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3824; + auto illegal_fp_variable_width_3824_arg2 = SEW; + auto illegal_fp_variable_width_3824_arg3 = rm; + auto illegal_fp_variable_width_3824_arg4 = SEW_widen; + auto illegal_fp_variable_width_3824_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3824 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3824, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3825; + auto valid_reg_overlap_3825_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3825_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3825 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3825, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3824, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3825)); + setArg(call_illegal_fp_variable_width_3824, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3824, 1, vd); + setArg(call_illegal_fp_variable_width_3824, 2, vm); + setArg(call_illegal_fp_variable_width_3824, 3, illegal_fp_variable_width_3824_arg2); + setArg(call_illegal_fp_variable_width_3824, 4, illegal_fp_variable_width_3824_arg3); + setArg(call_illegal_fp_variable_width_3824, 5, illegal_fp_variable_width_3824_arg4); + setArg(call_illegal_fp_variable_width_3824, 6, illegal_fp_variable_width_3824_arg5); + setRet(call_illegal_fp_variable_width_3824, 0, ret_val_illegal_fp_variable_width_3824); + setArg(call_valid_reg_overlap_3825, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3825, 1, vs2); + setArg(call_valid_reg_overlap_3825, 2, vd); + setArg(call_valid_reg_overlap_3825, 3, valid_reg_overlap_3825_arg2); + setArg(call_valid_reg_overlap_3825, 4, valid_reg_overlap_3825_arg3); + setRet(call_valid_reg_overlap_3825, 0, ret_val_valid_reg_overlap_3825); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3827; + x86::Gp ret_val_sew_3827 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3827, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3826; + auto fp_vector_unary_n_3826_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3826_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3826_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3826_arg8 = rm; + auto fp_vector_unary_n_3826_arg9 = ret_val_sew_3827; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3826, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3827, 0, reinterpret_cast(this)); + setRet(call_sew_3827, 0, ret_val_sew_3827); + setArg(call_fp_vector_unary_n_3826, 0, V); + setArg(call_fp_vector_unary_n_3826, 1, 20); + setArg(call_fp_vector_unary_n_3826, 2, fp_vector_unary_n_3826_arg2); + setArg(call_fp_vector_unary_n_3826, 3, fp_vector_unary_n_3826_arg3); + setArg(call_fp_vector_unary_n_3826, 4, fp_vector_unary_n_3826_arg4); + setArg(call_fp_vector_unary_n_3826, 5, vm); + setArg(call_fp_vector_unary_n_3826, 6, vd); + setArg(call_fp_vector_unary_n_3826, 7, vs2); + setArg(call_fp_vector_unary_n_3826, 8, fp_vector_unary_n_3826_arg8); + setArg(call_fp_vector_unary_n_3826, 9, fp_vector_unary_n_3826_arg9); + } + cc.bind(label_merge); + } + auto tmp3828 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3828, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3828, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 785); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 786: VFNCVT__ROD__F__F__W */ + continuation_e __vfncvt__rod__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rod.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__ROD__F__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 786); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3829; + x86::Gp ret_val_get_sew_pow_3829 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3829, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3830 = get_reg(cc, 8, false); + mov(cc, tmp3830, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3830, (ret_val_get_sew_pow_3829))), 8, false), ~ 1); + setArg(call_get_sew_pow_3829, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3829, 0, ret_val_get_sew_pow_3829); + InvokeNode* call_get_lmul_pow_3831; + x86::Gp ret_val_get_lmul_pow_3831 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3831, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3831; + setArg(call_get_lmul_pow_3831, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3831, 0, ret_val_get_lmul_pow_3831); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3832; + auto illegal_fp_variable_width_3832_arg2 = SEW; + auto illegal_fp_variable_width_3832_arg3 = rm; + auto illegal_fp_variable_width_3832_arg4 = SEW_widen; + auto illegal_fp_variable_width_3832_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3832 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3832, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3833; + auto valid_reg_overlap_3833_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3833_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3833 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3833, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3832, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3833)); + setArg(call_illegal_fp_variable_width_3832, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3832, 1, vd); + setArg(call_illegal_fp_variable_width_3832, 2, vm); + setArg(call_illegal_fp_variable_width_3832, 3, illegal_fp_variable_width_3832_arg2); + setArg(call_illegal_fp_variable_width_3832, 4, illegal_fp_variable_width_3832_arg3); + setArg(call_illegal_fp_variable_width_3832, 5, illegal_fp_variable_width_3832_arg4); + setArg(call_illegal_fp_variable_width_3832, 6, illegal_fp_variable_width_3832_arg5); + setRet(call_illegal_fp_variable_width_3832, 0, ret_val_illegal_fp_variable_width_3832); + setArg(call_valid_reg_overlap_3833, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3833, 1, vs2); + setArg(call_valid_reg_overlap_3833, 2, vd); + setArg(call_valid_reg_overlap_3833, 3, valid_reg_overlap_3833_arg2); + setArg(call_valid_reg_overlap_3833, 4, valid_reg_overlap_3833_arg3); + setRet(call_valid_reg_overlap_3833, 0, ret_val_valid_reg_overlap_3833); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3835; + x86::Gp ret_val_sew_3835 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3835, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3834; + auto fp_vector_unary_n_3834_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3834_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3834_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3834_arg9 = ret_val_sew_3835; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3834, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3835, 0, reinterpret_cast(this)); + setRet(call_sew_3835, 0, ret_val_sew_3835); + setArg(call_fp_vector_unary_n_3834, 0, V); + setArg(call_fp_vector_unary_n_3834, 1, 21); + setArg(call_fp_vector_unary_n_3834, 2, fp_vector_unary_n_3834_arg2); + setArg(call_fp_vector_unary_n_3834, 3, fp_vector_unary_n_3834_arg3); + setArg(call_fp_vector_unary_n_3834, 4, fp_vector_unary_n_3834_arg4); + setArg(call_fp_vector_unary_n_3834, 5, vm); + setArg(call_fp_vector_unary_n_3834, 6, vd); + setArg(call_fp_vector_unary_n_3834, 7, vs2); + setArg(call_fp_vector_unary_n_3834, 8, 6); + setArg(call_fp_vector_unary_n_3834, 9, fp_vector_unary_n_3834_arg9); + } + cc.bind(label_merge); + } + auto tmp3836 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3836, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3836, 32, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 786); + gen_instr_epilogue(jh); + return returnValue; + } + + /**************************************************************************** + * end opcode definitions + ****************************************************************************/ + continuation_e illegal_instruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) { + x86::Compiler& cc = jh.cc; + if(this->disass_enabled){ + auto mnemonic = std::string("illegal_instruction"); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } + cc.comment(fmt::format("illegal_instruction{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, instr_descr.size()); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc + ((instr & 3) == 3 ? 4 : 2); + mov(cc, jh.next_pc, pc.val); + gen_instr_prologue(jh); + gen_raise(jh, 0, 2); + gen_sync(jh, POST_SYNC, instr_descr.size()); + gen_instr_epilogue(jh); + return ILLEGAL_INSTR; + } +}; + +template vm_impl::vm_impl() { this(new ARCH()); } + +template +vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) +: vm_base(core, core_id, cluster_id) +, instr_decoder([this]() { + std::vector g_instr_descr; + g_instr_descr.reserve(instr_descr.size()); + for (uint32_t i = 0; i < instr_descr.size(); ++i) { + generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i}; + g_instr_descr.push_back(new_instr_descr); + } + return std::move(g_instr_descr); + }()) {} + +template +continuation_e vm_impl::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) { + enum {TRAP_ID=1<<16}; + code_word_t instr = 0; + phys_addr_t paddr(pc); + auto *const data = (uint8_t *)&instr; + auto res = this->core.read(paddr, 4, data); + if (res != iss::Ok) + return ILLEGAL_FETCH; + if (instr == 0x0000006f || (instr&0xffff)==0xa001) + return JUMP_TO_SELF; + uint32_t inst_index = instr_decoder.decode_instr(instr); + compile_func f = nullptr; + if(inst_index < instr_descr.size()) + f = instr_descr[inst_index].op; + if (f == nullptr) + f = &this_class::illegal_instruction; + return (this->*f)(pc, instr, jh); +} +template +void vm_impl::gen_instr_prologue(jit_holder& jh) { + auto& cc = jh.cc; + + x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE); + mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state); + cc.comment("//Instruction prologue end"); + +} +template +void vm_impl::gen_instr_epilogue(jit_holder& jh) { + auto& cc = jh.cc; + + cc.comment("//Instruction epilogue begin"); + cc.inc(get_ptr_for(jh, traits::CYCLE)); + x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE); + mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + cmp(cc, current_trap_state, 0); + cc.jne(jh.trap_entry); + cc.inc(get_ptr_for(jh, traits::ICOUNT)); + cc.inc(get_ptr_for(jh, traits::INSTRET)); + cc.comment("//Instruction epilogue end"); + +} +template +void vm_impl::gen_block_prologue(jit_holder& jh){ + jh.pc = load_reg_from_mem_Gp(jh, traits::PC); + jh.next_pc = load_reg_from_mem_Gp(jh, traits::NEXT_PC); + jh.globals.resize(GLOBALS_SIZE); + jh.globals[TVAL] = get_reg_Gp(jh.cc, 64, false); +} +template +void vm_impl::gen_block_epilogue(jit_holder& jh){ + x86::Compiler& cc = jh.cc; + cc.comment("//gen_block_epilogue"); + cc.ret(jh.next_pc); + + cc.bind(jh.trap_entry); + this->write_back(jh); + + x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE); + mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + + x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC); + mov(cc, current_pc, get_ptr_for(jh, traits::PC)); + + InvokeNode* call_enter_trap; + cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build()); + call_enter_trap->setArg(0, jh.arch_if_ptr); + call_enter_trap->setArg(1, current_trap_state); + call_enter_trap->setArg(2, current_pc); + call_enter_trap->setArg(3, jh.globals[TVAL]); + + x86_reg_t current_next_pc = get_reg_for(cc, traits::NEXT_PC); + mov(cc, current_next_pc, get_ptr_for(jh, traits::NEXT_PC)); + mov(cc, jh.next_pc, current_next_pc); + + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(UNKNOWN_JUMP)); + cc.ret(jh.next_pc); +} +template +inline void vm_impl::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) { + auto& cc = jh.cc; + auto tmp1 = get_reg_for(cc, traits::TRAP_STATE); + mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id); + mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1); + cc.jmp(jh.trap_entry); +} +template +inline void vm_impl::gen_lower(jit_holder& jh) { + auto& cc = jh.cc; + auto tmp1 = get_reg_for(cc, traits::TRAP_STATE); + mov(cc, tmp1, 0); + mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1); + cc.jmp(jh.trap_entry); +} +template +template +void vm_impl::gen_set_tval(jit_holder& jh, T new_tval) { + mov(jh.cc, jh.globals[TVAL], new_tval); + } +template +void vm_impl::gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) { + if(nonstd::holds_alternative(_new_tval)) { + x86::Gp new_tval = nonstd::get(_new_tval); + if(new_tval.size() < 8) + new_tval = gen_ext_Gp(jh.cc, new_tval, 64, false); + mov(jh.cc, jh.globals[TVAL], new_tval); + } else { + throw std::runtime_error("Variant not supported in gen_set_tval"); + } +} + +} // namespace tgc5c + +template <> +std::unique_ptr create(arch::rv32gcv *core, unsigned short port, bool dump) { + auto ret = new rv32gcv::vm_impl(*core, dump); + if (port != 0) debugger::server::run_server(ret, port); + return std::unique_ptr(ret); +} +} // namespace asmjit +} // namespace iss + +#include +#include +#include +#include +namespace iss { +namespace { + +volatile std::array dummy = { + core_factory::instance().register_creator("rv32gcv_msu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_msu_vp(); + auto vm = new asmjit::rv32gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("rv32gcv_m:asmjit", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_m_p(); + auto vm = new asmjit::rv32gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("rv32gcv_mu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_mu_p(); + auto vm = new asmjit::rv32gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }) +}; +} +} +// clang-format on diff --git a/src/vm/asmjit/vm_rv64gcv.cpp b/src/vm/asmjit/vm_rv64gcv.cpp new file mode 100644 index 0000000..8f43ee1 --- /dev/null +++ b/src/vm/asmjit/vm_rv64gcv.cpp @@ -0,0 +1,88707 @@ +/******************************************************************************* + * Copyright (C) 2024 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +// clang-format off +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define CUR_VLEN 512 +#define CUR_XLEN 64 +#include +#include + +#ifndef FMT_HEADER_ONLY +#define FMT_HEADER_ONLY +#endif +#include + +#include +#include + +#ifndef _MSC_VER +using int128_t = __int128; +using uint128_t = unsigned __int128; +namespace std { +template <> struct make_unsigned<__int128> { typedef unsigned __int128 type; }; +template <> class __make_unsigned_selector<__int128 unsigned, false, false> { +public: + typedef unsigned __int128 __type; +}; +template <> struct is_signed { static constexpr bool value = true; }; +template <> struct is_signed { static constexpr bool value = false; }; +template <> struct is_unsigned { static constexpr bool value = false; }; +template <> struct is_unsigned { static constexpr bool value = true; }; +} // namespace std +#endif + +namespace iss { +namespace asmjit { + + +namespace rv64gcv { +using namespace ::asmjit; +using namespace iss::arch; +using namespace iss::debugger; + +template class vm_impl : public iss::asmjit::vm_base { +public: + using traits = arch::traits; + using super = typename iss::asmjit::vm_base; + using virt_addr_t = typename super::virt_addr_t; + using phys_addr_t = typename super::phys_addr_t; + using code_word_t = typename super::code_word_t; + using mem_type_e = typename super::mem_type_e; + using addr_t = typename super::addr_t; + + vm_impl(); + + vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); + + void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } + + target_adapter_if *accquire_target_adapter(server_if *srv) override { + debugger_if::dbg_enabled = true; + if (vm_base::tgt_adapter == nullptr) + vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); + return vm_base::tgt_adapter; + } + +protected: + using super::get_ptr_for; + using super::get_reg_for; + using super::get_reg_for_Gp; + using super::load_reg_from_mem; + using super::load_reg_from_mem_Gp; + using super::write_reg_to_mem; + using super::gen_read_mem; + using super::gen_write_mem; + using super::gen_leave; + using super::gen_sync; + + using this_class = vm_impl; + using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&); + + continuation_e gen_single_inst_behavior(virt_addr_t&, jit_holder&) override; + enum globals_e {TVAL = 0, GLOBALS_SIZE}; + void gen_block_prologue(jit_holder& jh) override; + void gen_block_epilogue(jit_holder& jh) override; + inline const char *name(size_t index){return traits::reg_aliases.at(index);} + + inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";} + + inline const char* vname(size_t index) { return index < 32 ? name(index + traits::V0) : "illegal"; } + inline const char* sew_name(size_t bits) { + switch(bits) { + case 0b000: + return "e8"; + case 0b001: + return "e16"; + case 0b010: + return "e32"; + case 0b011: + return "e64"; + default: + return "illegal"; + } + } + inline const char* lmul_name(size_t bits) { + switch(bits) { + case 0b101: + return "mf8"; + case 0b110: + return "mf4"; + case 0b111: + return "mf2"; + case 0b000: + return "m1"; + case 0b001: + return "m2"; + case 0b010: + return "m4"; + case 0b011: + return "m8"; + default: + return "illegal"; + } + } + inline const char* ma_name(bool ma) { return ma ? "ma" : "mu"; } + inline const char* ta_name(bool ta) { return ta ? "ta" : "tu"; } + + void gen_instr_prologue(jit_holder& jh); + void gen_instr_epilogue(jit_holder& jh); + inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause); + inline void gen_lower(jit_holder& jh); + template ::value>::type> void gen_set_tval(jit_holder& jh, T new_tval) ; + void gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) ; + + template::type> + inline S sext(U from) { + auto mask = (1ULL<core.reg.trap_state = trap_val; + } + + + static uint64_t _NaNBox32(void* vm_impl_ptr , uint32_t val){ + return reinterpret_cast(vm_impl_ptr)->NaNBox32(val); + } + uint64_t NaNBox32(uint32_t val){ + if(traits::FLEN == 32) { + return (uint64_t)val; + } + else { + uint64_t box = ~((uint64_t)0); + return (uint64_t)(((uint128_t)box<<32)|val); + } + } + static uint8_t _get_rm(void* vm_impl_ptr , uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->get_rm(rm); + } + uint8_t get_rm(uint8_t rm){ + auto* FCSR = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::FCSR]); + uint8_t rm_eff = rm == 7? bit_sub<5, 7-5+1>(*FCSR) : rm; + if(rm_eff > 4) { + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return rm_eff; + } + static uint64_t _NaNBox64(void* vm_impl_ptr , uint64_t val){ + return reinterpret_cast(vm_impl_ptr)->NaNBox64(val); + } + uint64_t NaNBox64(uint64_t val){ + if(traits::FLEN == 64) { + return (uint64_t)val; + } + else { + uint64_t box = ~((uint64_t)0); + return (uint64_t)(((uint128_t)box<<64)|val); + } + } + static uint8_t _get_pow(void* vm_impl_ptr , uint32_t val){ + return reinterpret_cast(vm_impl_ptr)->get_pow(val); + } + uint8_t get_pow(uint32_t val){ + switch(val){ + case 8: + return 3; + case 16: + return 4; + case 32: + return 5; + case 64: + return 6; + case 128: + return 7; + case 256: + return 8; + case 512: + return 9; + case 1024: + return 10; + case 2048: + return 11; + case 4096: + return 12; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + static uint8_t _lmul(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->lmul(); + } + uint8_t lmul(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub<0, 2-0+1>(*vtype); + } + static uint8_t _sew(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->sew(); + } + uint8_t sew(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub<3, 5-3+1>(*vtype); + } + static int8_t _get_lmul_pow(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->get_lmul_pow(); + } + int8_t get_lmul_pow(){ + switch(lmul()){ + case 5: + return - 3; + case 6: + return - 2; + case 7: + return - 1; + case 0: + return 0; + case 1: + return 1; + case 2: + return 2; + case 3: + return 3; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + static uint8_t _get_sew_pow(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->get_sew_pow(); + } + uint8_t get_sew_pow(){ + switch(sew()){ + case 0: + return 3; + case 1: + return 4; + case 2: + return 5; + case 3: + return 6; + default: + raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); + } + return 0; + } + static uint16_t _get_elem_count(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->get_elem_count(); + } + uint16_t get_elem_count(){ + uint8_t total_pow = (uint8_t)((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow())); + return (uint16_t)(1 << total_pow) & ~1; + } + static uint8_t _valid_vtype(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->valid_vtype(); + } + uint8_t valid_vtype(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + return bit_sub(*vtype, (uint64_t)(traits::XLEN) - (uint64_t)(1), 1) == 0; + } + static uint8_t _valid_rd_mask(void* vm_impl_ptr , uint8_t rd, uint8_t vm){ + return reinterpret_cast(vm_impl_ptr)->valid_rd_mask(rd,vm); + } + uint8_t valid_rd_mask(uint8_t rd, uint8_t vm){ + return rd != 0 || vm != 0; + } + static uint8_t _valid_eew_emul(void* vm_impl_ptr , uint8_t EEW, int8_t EMUL_pow){ + return reinterpret_cast(vm_impl_ptr)->valid_eew_emul(EEW,EMUL_pow); + } + uint8_t valid_eew_emul(uint8_t EEW, int8_t EMUL_pow){ + return EEW >= 8 && EEW <= traits::ELEN && EEW <= traits::EEW_MAX && EMUL_pow >= - 3 && EMUL_pow <= 3; + } + static uint8_t _valid_segment(void* vm_impl_ptr , uint8_t nf, int8_t EMUL_pow){ + return reinterpret_cast(vm_impl_ptr)->valid_segment(nf,EMUL_pow); + } + uint8_t valid_segment(uint8_t nf, int8_t EMUL_pow){ + if(EMUL_pow < 0) { + uint8_t neg_EMUL = (uint8_t)(1 << - EMUL_pow) & ~1; + return nf / neg_EMUL <= 8; + } + else { + uint8_t EMUL = (uint8_t)(1 << EMUL_pow) & ~1; + return (uint16_t)(nf) * (uint16_t)(EMUL) <= 8; + } + } + static uint8_t _illegal_vd_unmasked(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->illegal_vd_unmasked(); + } + uint8_t illegal_vd_unmasked(){ + return ! valid_vtype(); + } + static uint8_t _illegal_variable_width(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return reinterpret_cast(vm_impl_ptr)->illegal_variable_width(vd,vm,SEW_new,LMUL_pow_new); + } + uint8_t illegal_variable_width(uint8_t vd, uint8_t vm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_eew_emul(SEW_new, LMUL_pow_new)); + } + static uint8_t _valid_reg_overlap(void* vm_impl_ptr , uint8_t rs, uint8_t rd, int8_t EMUL_pow_rs, int8_t EMUL_pow_rd){ + return reinterpret_cast(vm_impl_ptr)->valid_reg_overlap(rs,rd,EMUL_pow_rs,EMUL_pow_rd); + } + uint8_t valid_reg_overlap(uint8_t rs, uint8_t rd, int8_t EMUL_pow_rs, int8_t EMUL_pow_rd){ + uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& (1ULL << 4) : 1; + uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& (1ULL << 4) : 1; + if(EMUL_pow_rs < EMUL_pow_rd) { + return (rs + rs_group <= rd) || (rs >= rd + rd_group) || ((rs + rs_group == rd + rd_group) & (EMUL_pow_rs >= 0)); + } + else { + if(EMUL_pow_rs > EMUL_pow_rd) { + return (rd <= rs) || (rd >= rs + rs_group); + } + else { + return true; + } + } + } + static uint8_t _illegal_vd_masked(void* vm_impl_ptr , uint8_t vd){ + return reinterpret_cast(vm_impl_ptr)->illegal_vd_masked(vd); + } + uint8_t illegal_vd_masked(uint8_t vd){ + return ! (valid_vtype()) || vd == 0; + } + static uint8_t _illegal_normal(void* vm_impl_ptr , uint8_t vd, uint8_t vm){ + return reinterpret_cast(vm_impl_ptr)->illegal_normal(vd,vm); + } + uint8_t illegal_normal(uint8_t vd, uint8_t vm){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)); + } + static uint8_t _valid_fp_op(void* vm_impl_ptr , uint8_t SEW, uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->valid_fp_op(SEW,rm); + } + uint8_t valid_fp_op(uint8_t SEW, uint8_t rm){ + int8_t valid_sew = (traits::FP_SEW_MIN >= 32 & SEW <= traits::FP_SEW_MAX); + int8_t valid_rm = ! (rm == 5 | rm == 6 | rm == 7); + return valid_sew && valid_rm; + } + static uint8_t _illegal_fp_vd_unmasked(void* vm_impl_ptr , uint8_t SEW, uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_vd_unmasked(SEW,rm); + } + uint8_t illegal_fp_vd_unmasked(uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || ! (valid_fp_op(SEW, rm)); + } + static uint8_t _illegal_fp_normal(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_normal(vd,vm,SEW,rm); + } + uint8_t illegal_fp_normal(uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_fp_op(SEW, rm)); + } + static uint8_t _valid_sew_lmul(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->valid_sew_lmul(); + } + uint8_t valid_sew_lmul(){ + return get_sew_pow() <= (uint16_t)(get_pow(traits::ELEN)) + (int16_t)(get_lmul_pow()); + } + static uint16_t _calculate_new_vl(void* vm_impl_ptr , uint64_t avl, uint16_t vlmax){ + return reinterpret_cast(vm_impl_ptr)->calculate_new_vl(avl,vlmax); + } + uint16_t calculate_new_vl(uint64_t avl, uint16_t vlmax){ + if(avl <= vlmax) { + return ((uint16_t)avl); + } + else { + if(avl < ((uint32_t)(2) * (uint32_t)(vlmax))) { + return vlmax; + } + else { + return vlmax; + } + } + } + static + void _handle_illegal_vtype(void* vm_impl_ptr ){ + reinterpret_cast(vm_impl_ptr)->handle_illegal_vtype(); + } + void handle_illegal_vtype(){ + auto* vtype = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vtype]); + auto* vl = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vl]); + *vtype = (uint64_t)1 << ((uint64_t)(traits::XLEN) - (uint64_t)(1)); + *vl = (uint64_t)0; + } + static uint8_t _convert_width(void* vm_impl_ptr , uint8_t width){ + return reinterpret_cast(vm_impl_ptr)->convert_width(width); + } + uint8_t convert_width(uint8_t width){ + switch(width){ + case (0): + return 1; + case (5): + return 2; + case (6): + return 4; + case (7): + return 8; + } + return 0; + } + static uint8_t _illegal_load(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return reinterpret_cast(vm_impl_ptr)->illegal_load(vd,vm,nf,EEW,EMUL_pow); + } + uint8_t illegal_load(uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return ! valid_vtype() || ! valid_rd_mask(vd, vm) || ! valid_eew_emul(EEW, EMUL_pow) || ! valid_segment(nf, EMUL_pow); + } + static uint8_t _illegal_store(void* vm_impl_ptr , uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return reinterpret_cast(vm_impl_ptr)->illegal_store(nf,EEW,EMUL_pow); + } + uint8_t illegal_store(uint8_t nf, uint8_t EEW, int8_t EMUL_pow){ + return ! valid_vtype() || ! valid_eew_emul(EEW, EMUL_pow) || ! valid_segment(nf, EMUL_pow); + } + static uint8_t _illegal_indexed_load(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return reinterpret_cast(vm_impl_ptr)->illegal_indexed_load(vd,vm,nf,EEW_index,EMUL_pow_index,EMUL_pow_data); + } + uint8_t illegal_indexed_load(uint8_t vd, uint8_t vm, uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return ! valid_vtype() || ! valid_rd_mask(vd, vm) || ! valid_eew_emul(EEW_index, EMUL_pow_index) || ! valid_segment(nf, EMUL_pow_data); + } + static uint8_t _illegal_indexed_store(void* vm_impl_ptr , uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return reinterpret_cast(vm_impl_ptr)->illegal_indexed_store(nf,EEW_index,EMUL_pow_index,EMUL_pow_data); + } + uint8_t illegal_indexed_store(uint8_t nf, uint8_t EEW_index, int8_t EMUL_pow_index, int8_t EMUL_pow_data){ + return ! valid_vtype() || ! valid_eew_emul(EEW_index, EMUL_pow_index) || ! valid_segment(nf, EMUL_pow_data); + } + static uint8_t _illegal_reduction(void* vm_impl_ptr ){ + return reinterpret_cast(vm_impl_ptr)->illegal_reduction(); + } + uint8_t illegal_reduction(){ + auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); + return ! valid_vtype() || *vstart != 0; + } + static uint8_t _illegal_reduction_widen(void* vm_impl_ptr , uint8_t EEW, int8_t EMUL_pow){ + return reinterpret_cast(vm_impl_ptr)->illegal_reduction_widen(EEW,EMUL_pow); + } + uint8_t illegal_reduction_widen(uint8_t EEW, int8_t EMUL_pow){ + return illegal_reduction() || ! valid_eew_emul(EEW, EMUL_pow); + } + static uint8_t _illegal_fp_reduction(void* vm_impl_ptr , uint8_t SEW, uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_reduction(SEW,rm); + } + uint8_t illegal_fp_reduction(uint8_t SEW, uint8_t rm){ + auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); + return ! valid_vtype() || *vstart != 0 || ! valid_fp_op(SEW, rm); + } + static uint8_t _illegal_fp_variable_width(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_variable_width(vd,vm,SEW,rm,SEW_new,LMUL_pow_new); + } + uint8_t illegal_fp_variable_width(uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm, uint8_t SEW_new, int8_t LMUL_pow_new){ + return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_fp_op(SEW, rm)) || ! (valid_eew_emul(SEW_new, LMUL_pow_new)); + } + static uint8_t _illegal_fp_vd_masked(void* vm_impl_ptr , uint8_t vd, uint8_t SEW, uint8_t rm){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_vd_masked(vd,SEW,rm); + } + uint8_t illegal_fp_vd_masked(uint8_t vd, uint8_t SEW, uint8_t rm){ + return ! (valid_vtype()) || vd == 0 || ! (valid_fp_op(SEW, rm)); + } +private: + /**************************************************************************** + * start opcode definitions + ****************************************************************************/ + struct instruction_descriptor { + uint32_t length; + uint32_t value; + uint32_t mask; + compile_func op; + }; + + const std::array instr_descr = {{ + /* entries are: size, valid value, valid mask, function ptr */ + /* instruction LUI, encoding '0b00000000000000000000000000110111' */ + {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, + /* instruction AUIPC, encoding '0b00000000000000000000000000010111' */ + {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, + /* instruction JAL, encoding '0b00000000000000000000000001101111' */ + {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, + /* instruction JALR, encoding '0b00000000000000000000000001100111' */ + {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, + /* instruction BEQ, encoding '0b00000000000000000000000001100011' */ + {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, + /* instruction BNE, encoding '0b00000000000000000001000001100011' */ + {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne}, + /* instruction BLT, encoding '0b00000000000000000100000001100011' */ + {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt}, + /* instruction BGE, encoding '0b00000000000000000101000001100011' */ + {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge}, + /* instruction BLTU, encoding '0b00000000000000000110000001100011' */ + {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu}, + /* instruction BGEU, encoding '0b00000000000000000111000001100011' */ + {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu}, + /* instruction LB, encoding '0b00000000000000000000000000000011' */ + {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb}, + /* instruction LH, encoding '0b00000000000000000001000000000011' */ + {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh}, + /* instruction LW, encoding '0b00000000000000000010000000000011' */ + {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw}, + /* instruction LBU, encoding '0b00000000000000000100000000000011' */ + {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu}, + /* instruction LHU, encoding '0b00000000000000000101000000000011' */ + {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu}, + /* instruction SB, encoding '0b00000000000000000000000000100011' */ + {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb}, + /* instruction SH, encoding '0b00000000000000000001000000100011' */ + {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh}, + /* instruction SW, encoding '0b00000000000000000010000000100011' */ + {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw}, + /* instruction ADDI, encoding '0b00000000000000000000000000010011' */ + {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi}, + /* instruction SLTI, encoding '0b00000000000000000010000000010011' */ + {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti}, + /* instruction SLTIU, encoding '0b00000000000000000011000000010011' */ + {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu}, + /* instruction XORI, encoding '0b00000000000000000100000000010011' */ + {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori}, + /* instruction ORI, encoding '0b00000000000000000110000000010011' */ + {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, + /* instruction ANDI, encoding '0b00000000000000000111000000010011' */ + {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, + /* instruction SLLI, encoding '0b00000000000000000001000000010011' */ + {32, 0b00000000000000000001000000010011, 0b11111100000000000111000001111111, &this_class::__slli}, + /* instruction SRLI, encoding '0b00000000000000000101000000010011' */ + {32, 0b00000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srli}, + /* instruction SRAI, encoding '0b01000000000000000101000000010011' */ + {32, 0b01000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srai}, + /* instruction ADD, encoding '0b00000000000000000000000000110011' */ + {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, + /* instruction SUB, encoding '0b01000000000000000000000000110011' */ + {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub}, + /* instruction SLL, encoding '0b00000000000000000001000000110011' */ + {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll}, + /* instruction SLT, encoding '0b00000000000000000010000000110011' */ + {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt}, + /* instruction SLTU, encoding '0b00000000000000000011000000110011' */ + {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu}, + /* instruction XOR, encoding '0b00000000000000000100000000110011' */ + {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor}, + /* instruction SRL, encoding '0b00000000000000000101000000110011' */ + {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl}, + /* instruction SRA, encoding '0b01000000000000000101000000110011' */ + {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra}, + /* instruction OR, encoding '0b00000000000000000110000000110011' */ + {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or}, + /* instruction AND, encoding '0b00000000000000000111000000110011' */ + {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and}, + /* instruction FENCE, encoding '0b00000000000000000000000000001111' */ + {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, &this_class::__fence}, + /* instruction ECALL, encoding '0b00000000000000000000000001110011' */ + {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall}, + /* instruction EBREAK, encoding '0b00000000000100000000000001110011' */ + {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak}, + /* instruction MRET, encoding '0b00110000001000000000000001110011' */ + {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret}, + /* instruction WFI, encoding '0b00010000010100000000000001110011' */ + {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi}, + /* instruction LWU, encoding '0b00000000000000000110000000000011' */ + {32, 0b00000000000000000110000000000011, 0b00000000000000000111000001111111, &this_class::__lwu}, + /* instruction LD, encoding '0b00000000000000000011000000000011' */ + {32, 0b00000000000000000011000000000011, 0b00000000000000000111000001111111, &this_class::__ld}, + /* instruction SD, encoding '0b00000000000000000011000000100011' */ + {32, 0b00000000000000000011000000100011, 0b00000000000000000111000001111111, &this_class::__sd}, + /* instruction ADDIW, encoding '0b00000000000000000000000000011011' */ + {32, 0b00000000000000000000000000011011, 0b00000000000000000111000001111111, &this_class::__addiw}, + /* instruction SLLIW, encoding '0b00000000000000000001000000011011' */ + {32, 0b00000000000000000001000000011011, 0b11111110000000000111000001111111, &this_class::__slliw}, + /* instruction SRLIW, encoding '0b00000000000000000101000000011011' */ + {32, 0b00000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__srliw}, + /* instruction SRAIW, encoding '0b01000000000000000101000000011011' */ + {32, 0b01000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__sraiw}, + /* instruction ADDW, encoding '0b00000000000000000000000000111011' */ + {32, 0b00000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__addw}, + /* instruction SUBW, encoding '0b01000000000000000000000000111011' */ + {32, 0b01000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__subw}, + /* instruction SLLW, encoding '0b00000000000000000001000000111011' */ + {32, 0b00000000000000000001000000111011, 0b11111110000000000111000001111111, &this_class::__sllw}, + /* instruction SRLW, encoding '0b00000000000000000101000000111011' */ + {32, 0b00000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__srlw}, + /* instruction SRAW, encoding '0b01000000000000000101000000111011' */ + {32, 0b01000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__sraw}, + /* instruction CSRRW, encoding '0b00000000000000000001000001110011' */ + {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw}, + /* instruction CSRRS, encoding '0b00000000000000000010000001110011' */ + {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs}, + /* instruction CSRRC, encoding '0b00000000000000000011000001110011' */ + {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc}, + /* instruction CSRRWI, encoding '0b00000000000000000101000001110011' */ + {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi}, + /* instruction CSRRSI, encoding '0b00000000000000000110000001110011' */ + {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi}, + /* instruction CSRRCI, encoding '0b00000000000000000111000001110011' */ + {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci}, + /* instruction FENCE_I, encoding '0b00000000000000000001000000001111' */ + {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i}, + /* instruction MUL, encoding '0b00000010000000000000000000110011' */ + {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul}, + /* instruction MULH, encoding '0b00000010000000000001000000110011' */ + {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh}, + /* instruction MULHSU, encoding '0b00000010000000000010000000110011' */ + {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu}, + /* instruction MULHU, encoding '0b00000010000000000011000000110011' */ + {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu}, + /* instruction DIV, encoding '0b00000010000000000100000000110011' */ + {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div}, + /* instruction DIVU, encoding '0b00000010000000000101000000110011' */ + {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu}, + /* instruction REM, encoding '0b00000010000000000110000000110011' */ + {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem}, + /* instruction REMU, encoding '0b00000010000000000111000000110011' */ + {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu}, + /* instruction MULW, encoding '0b00000010000000000000000000111011' */ + {32, 0b00000010000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__mulw}, + /* instruction DIVW, encoding '0b00000010000000000100000000111011' */ + {32, 0b00000010000000000100000000111011, 0b11111110000000000111000001111111, &this_class::__divw}, + /* instruction DIVUW, encoding '0b00000010000000000101000000111011' */ + {32, 0b00000010000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__divuw}, + /* instruction REMW, encoding '0b00000010000000000110000000111011' */ + {32, 0b00000010000000000110000000111011, 0b11111110000000000111000001111111, &this_class::__remw}, + /* instruction REMUW, encoding '0b00000010000000000111000000111011' */ + {32, 0b00000010000000000111000000111011, 0b11111110000000000111000001111111, &this_class::__remuw}, + /* instruction LRW, encoding '0b00010000000000000010000000101111' */ + {32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, &this_class::__lrw}, + /* instruction SCW, encoding '0b00011000000000000010000000101111' */ + {32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__scw}, + /* instruction AMOSWAPW, encoding '0b00001000000000000010000000101111' */ + {32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoswapw}, + /* instruction AMOADDW, encoding '0b00000000000000000010000000101111' */ + {32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoaddw}, + /* instruction AMOXORW, encoding '0b00100000000000000010000000101111' */ + {32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoxorw}, + /* instruction AMOANDW, encoding '0b01100000000000000010000000101111' */ + {32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoandw}, + /* instruction AMOORW, encoding '0b01000000000000000010000000101111' */ + {32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoorw}, + /* instruction AMOMINW, encoding '0b10000000000000000010000000101111' */ + {32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominw}, + /* instruction AMOMAXW, encoding '0b10100000000000000010000000101111' */ + {32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxw}, + /* instruction AMOMINUW, encoding '0b11000000000000000010000000101111' */ + {32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominuw}, + /* instruction AMOMAXUW, encoding '0b11100000000000000010000000101111' */ + {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxuw}, + /* instruction LRD, encoding '0b00010000000000000011000000101111' */ + {32, 0b00010000000000000011000000101111, 0b11111001111100000111000001111111, &this_class::__lrd}, + /* instruction SCD, encoding '0b00011000000000000011000000101111' */ + {32, 0b00011000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__scd}, + /* instruction AMOSWAPD, encoding '0b00001000000000000011000000101111' */ + {32, 0b00001000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoswapd}, + /* instruction AMOADDD, encoding '0b00000000000000000011000000101111' */ + {32, 0b00000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoaddd}, + /* instruction AMOXORD, encoding '0b00100000000000000011000000101111' */ + {32, 0b00100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoxord}, + /* instruction AMOANDD, encoding '0b01100000000000000011000000101111' */ + {32, 0b01100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoandd}, + /* instruction AMOORD, encoding '0b01000000000000000011000000101111' */ + {32, 0b01000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoord}, + /* instruction AMOMIND, encoding '0b10000000000000000011000000101111' */ + {32, 0b10000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amomind}, + /* instruction AMOMAXD, encoding '0b10100000000000000011000000101111' */ + {32, 0b10100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxd}, + /* instruction AMOMINUD, encoding '0b11000000000000000011000000101111' */ + {32, 0b11000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amominud}, + /* instruction AMOMAXUD, encoding '0b11100000000000000011000000101111' */ + {32, 0b11100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxud}, + /* instruction C__ADDI4SPN, encoding '0b0000000000000000' */ + {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c__addi4spn}, + /* instruction C__LW, encoding '0b0100000000000000' */ + {16, 0b0100000000000000, 0b1110000000000011, &this_class::__c__lw}, + /* instruction C__LD, encoding '0b0110000000000000' */ + {16, 0b0110000000000000, 0b1110000000000011, &this_class::__c__ld}, + /* instruction C__SW, encoding '0b1100000000000000' */ + {16, 0b1100000000000000, 0b1110000000000011, &this_class::__c__sw}, + /* instruction C__SD, encoding '0b1110000000000000' */ + {16, 0b1110000000000000, 0b1110000000000011, &this_class::__c__sd}, + /* instruction C__ADDI, encoding '0b0000000000000001' */ + {16, 0b0000000000000001, 0b1110000000000011, &this_class::__c__addi}, + /* instruction C__NOP, encoding '0b0000000000000001' */ + {16, 0b0000000000000001, 0b1110111110000011, &this_class::__c__nop}, + /* instruction C__ADDIW, encoding '0b0010000000000001' */ + {16, 0b0010000000000001, 0b1110000000000011, &this_class::__c__addiw}, + /* instruction C__LI, encoding '0b0100000000000001' */ + {16, 0b0100000000000001, 0b1110000000000011, &this_class::__c__li}, + /* instruction C__LUI, encoding '0b0110000000000001' */ + {16, 0b0110000000000001, 0b1110000000000011, &this_class::__c__lui}, + /* instruction C__ADDI16SP, encoding '0b0110000100000001' */ + {16, 0b0110000100000001, 0b1110111110000011, &this_class::__c__addi16sp}, + /* instruction __reserved_clui, encoding '0b0110000000000001' */ + {16, 0b0110000000000001, 0b1111000001111111, &this_class::____reserved_clui}, + /* instruction C__SRLI, encoding '0b1000000000000001' */ + {16, 0b1000000000000001, 0b1110110000000011, &this_class::__c__srli}, + /* instruction C__SRAI, encoding '0b1000010000000001' */ + {16, 0b1000010000000001, 0b1110110000000011, &this_class::__c__srai}, + /* instruction C__ANDI, encoding '0b1000100000000001' */ + {16, 0b1000100000000001, 0b1110110000000011, &this_class::__c__andi}, + /* instruction C__SUB, encoding '0b1000110000000001' */ + {16, 0b1000110000000001, 0b1111110001100011, &this_class::__c__sub}, + /* instruction C__XOR, encoding '0b1000110000100001' */ + {16, 0b1000110000100001, 0b1111110001100011, &this_class::__c__xor}, + /* instruction C__OR, encoding '0b1000110001000001' */ + {16, 0b1000110001000001, 0b1111110001100011, &this_class::__c__or}, + /* instruction C__AND, encoding '0b1000110001100001' */ + {16, 0b1000110001100001, 0b1111110001100011, &this_class::__c__and}, + /* instruction C__SUBW, encoding '0b1001110000000001' */ + {16, 0b1001110000000001, 0b1111110001100011, &this_class::__c__subw}, + /* instruction C__ADDW, encoding '0b1001110000100001' */ + {16, 0b1001110000100001, 0b1111110001100011, &this_class::__c__addw}, + /* instruction C__J, encoding '0b1010000000000001' */ + {16, 0b1010000000000001, 0b1110000000000011, &this_class::__c__j}, + /* instruction C__BEQZ, encoding '0b1100000000000001' */ + {16, 0b1100000000000001, 0b1110000000000011, &this_class::__c__beqz}, + /* instruction C__BNEZ, encoding '0b1110000000000001' */ + {16, 0b1110000000000001, 0b1110000000000011, &this_class::__c__bnez}, + /* instruction C__SLLI, encoding '0b0000000000000010' */ + {16, 0b0000000000000010, 0b1110000000000011, &this_class::__c__slli}, + /* instruction C__LWSP, encoding '0b0100000000000010' */ + {16, 0b0100000000000010, 0b1110000000000011, &this_class::__c__lwsp}, + /* instruction C__LDSP, encoding '0b0110000000000010' */ + {16, 0b0110000000000010, 0b1110000000000011, &this_class::__c__ldsp}, + /* instruction C__MV, encoding '0b1000000000000010' */ + {16, 0b1000000000000010, 0b1111000000000011, &this_class::__c__mv}, + /* instruction C__JR, encoding '0b1000000000000010' */ + {16, 0b1000000000000010, 0b1111000001111111, &this_class::__c__jr}, + /* instruction __reserved_cmv, encoding '0b1000000000000010' */ + {16, 0b1000000000000010, 0b1111111111111111, &this_class::____reserved_cmv}, + /* instruction C__ADD, encoding '0b1001000000000010' */ + {16, 0b1001000000000010, 0b1111000000000011, &this_class::__c__add}, + /* instruction C__JALR, encoding '0b1001000000000010' */ + {16, 0b1001000000000010, 0b1111000001111111, &this_class::__c__jalr}, + /* instruction C__EBREAK, encoding '0b1001000000000010' */ + {16, 0b1001000000000010, 0b1111111111111111, &this_class::__c__ebreak}, + /* instruction C__SWSP, encoding '0b1100000000000010' */ + {16, 0b1100000000000010, 0b1110000000000011, &this_class::__c__swsp}, + /* instruction C__SDSP, encoding '0b1110000000000010' */ + {16, 0b1110000000000010, 0b1110000000000011, &this_class::__c__sdsp}, + /* instruction DII, encoding '0b0000000000000000' */ + {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, + /* instruction FLW, encoding '0b00000000000000000010000000000111' */ + {32, 0b00000000000000000010000000000111, 0b00000000000000000111000001111111, &this_class::__flw}, + /* instruction FSW, encoding '0b00000000000000000010000000100111' */ + {32, 0b00000000000000000010000000100111, 0b00000000000000000111000001111111, &this_class::__fsw}, + /* instruction FADD__S, encoding '0b00000000000000000000000001010011' */ + {32, 0b00000000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fadd__s}, + /* instruction FSUB__S, encoding '0b00001000000000000000000001010011' */ + {32, 0b00001000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fsub__s}, + /* instruction FMUL__S, encoding '0b00010000000000000000000001010011' */ + {32, 0b00010000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fmul__s}, + /* instruction FDIV__S, encoding '0b00011000000000000000000001010011' */ + {32, 0b00011000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fdiv__s}, + /* instruction FMIN__S, encoding '0b00101000000000000000000001010011' */ + {32, 0b00101000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fmin__s}, + /* instruction FMAX__S, encoding '0b00101000000000000001000001010011' */ + {32, 0b00101000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fmax__s}, + /* instruction FSQRT__S, encoding '0b01011000000000000000000001010011' */ + {32, 0b01011000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fsqrt__s}, + /* instruction FMADD__S, encoding '0b00000000000000000000000001000011' */ + {32, 0b00000000000000000000000001000011, 0b00000110000000000000000001111111, &this_class::__fmadd__s}, + /* instruction FMSUB__S, encoding '0b00000000000000000000000001000111' */ + {32, 0b00000000000000000000000001000111, 0b00000110000000000000000001111111, &this_class::__fmsub__s}, + /* instruction FNMADD__S, encoding '0b00000000000000000000000001001111' */ + {32, 0b00000000000000000000000001001111, 0b00000110000000000000000001111111, &this_class::__fnmadd__s}, + /* instruction FNMSUB__S, encoding '0b00000000000000000000000001001011' */ + {32, 0b00000000000000000000000001001011, 0b00000110000000000000000001111111, &this_class::__fnmsub__s}, + /* instruction FCVT__W__S, encoding '0b11000000000000000000000001010011' */ + {32, 0b11000000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__w__s}, + /* instruction FCVT__WU__S, encoding '0b11000000000100000000000001010011' */ + {32, 0b11000000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__wu__s}, + /* instruction FCVT__L__S, encoding '0b11000000001000000000000001010011' */ + {32, 0b11000000001000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__l__s}, + /* instruction FCVT__LU__S, encoding '0b11000000001100000000000001010011' */ + {32, 0b11000000001100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__lu__s}, + /* instruction FCVT__S__W, encoding '0b11010000000000000000000001010011' */ + {32, 0b11010000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__s__w}, + /* instruction FCVT__S__WU, encoding '0b11010000000100000000000001010011' */ + {32, 0b11010000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__s__wu}, + /* instruction FCVT__S__L, encoding '0b11010000001000000000000001010011' */ + {32, 0b11010000001000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__s__l}, + /* instruction FCVT__S__LU, encoding '0b11010000001100000000000001010011' */ + {32, 0b11010000001100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__s__lu}, + /* instruction FSGNJ__S, encoding '0b00100000000000000000000001010011' */ + {32, 0b00100000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnj__s}, + /* instruction FSGNJN__S, encoding '0b00100000000000000001000001010011' */ + {32, 0b00100000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjn__s}, + /* instruction FSGNJX__S, encoding '0b00100000000000000010000001010011' */ + {32, 0b00100000000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjx__s}, + /* instruction FMV__X__W, encoding '0b11100000000000000000000001010011' */ + {32, 0b11100000000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv__x__w}, + /* instruction FMV__W__X, encoding '0b11110000000000000000000001010011' */ + {32, 0b11110000000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv__w__x}, + /* instruction FEQ__S, encoding '0b10100000000000000010000001010011' */ + {32, 0b10100000000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__feq__s}, + /* instruction FLT__S, encoding '0b10100000000000000001000001010011' */ + {32, 0b10100000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__flt__s}, + /* instruction FLE__S, encoding '0b10100000000000000000000001010011' */ + {32, 0b10100000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fle__s}, + /* instruction FCLASS__S, encoding '0b11100000000000000001000001010011' */ + {32, 0b11100000000000000001000001010011, 0b11111111111100000111000001111111, &this_class::__fclass__s}, + /* instruction FLD, encoding '0b00000000000000000011000000000111' */ + {32, 0b00000000000000000011000000000111, 0b00000000000000000111000001111111, &this_class::__fld}, + /* instruction FSD, encoding '0b00000000000000000011000000100111' */ + {32, 0b00000000000000000011000000100111, 0b00000000000000000111000001111111, &this_class::__fsd}, + /* instruction FADD__D, encoding '0b00000010000000000000000001010011' */ + {32, 0b00000010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fadd__d}, + /* instruction FSUB__D, encoding '0b00001010000000000000000001010011' */ + {32, 0b00001010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fsub__d}, + /* instruction FMUL__D, encoding '0b00010010000000000000000001010011' */ + {32, 0b00010010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fmul__d}, + /* instruction FDIV__D, encoding '0b00011010000000000000000001010011' */ + {32, 0b00011010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fdiv__d}, + /* instruction FMIN__D, encoding '0b00101010000000000000000001010011' */ + {32, 0b00101010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fmin__d}, + /* instruction FMAX__D, encoding '0b00101010000000000001000001010011' */ + {32, 0b00101010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fmax__d}, + /* instruction FSQRT__D, encoding '0b01011010000000000000000001010011' */ + {32, 0b01011010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fsqrt__d}, + /* instruction FMADD__D, encoding '0b00000010000000000000000001000011' */ + {32, 0b00000010000000000000000001000011, 0b00000110000000000000000001111111, &this_class::__fmadd__d}, + /* instruction FMSUB__D, encoding '0b00000010000000000000000001000111' */ + {32, 0b00000010000000000000000001000111, 0b00000110000000000000000001111111, &this_class::__fmsub__d}, + /* instruction FNMADD__D, encoding '0b00000010000000000000000001001111' */ + {32, 0b00000010000000000000000001001111, 0b00000110000000000000000001111111, &this_class::__fnmadd__d}, + /* instruction FNMSUB__D, encoding '0b00000010000000000000000001001011' */ + {32, 0b00000010000000000000000001001011, 0b00000110000000000000000001111111, &this_class::__fnmsub__d}, + /* instruction FCVT__W__D, encoding '0b11000010000000000000000001010011' */ + {32, 0b11000010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__w__d}, + /* instruction FCVT__WU__D, encoding '0b11000010000100000000000001010011' */ + {32, 0b11000010000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__wu__d}, + /* instruction FCVT__L__D, encoding '0b11000010001000000000000001010011' */ + {32, 0b11000010001000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__l__d}, + /* instruction FCVT__LU__D, encoding '0b11000010001100000000000001010011' */ + {32, 0b11000010001100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__lu__d}, + /* instruction FCVT__D__W, encoding '0b11010010000000000000000001010011' */ + {32, 0b11010010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__d__w}, + /* instruction FCVT__D__WU, encoding '0b11010010000100000000000001010011' */ + {32, 0b11010010000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__d__wu}, + /* instruction FCVT__D__L, encoding '0b11010010001000000000000001010011' */ + {32, 0b11010010001000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__d__l}, + /* instruction FCVT__D__LU, encoding '0b11010010001100000000000001010011' */ + {32, 0b11010010001100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__d__lu}, + /* instruction FCVT__S__D, encoding '0b01000000000100000000000001010011' */ + {32, 0b01000000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__s__d}, + /* instruction FCVT__D__S, encoding '0b01000010000000000000000001010011' */ + {32, 0b01000010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt__d__s}, + /* instruction FSGNJ__D, encoding '0b00100010000000000000000001010011' */ + {32, 0b00100010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnj__d}, + /* instruction FSGNJN__D, encoding '0b00100010000000000001000001010011' */ + {32, 0b00100010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjn__d}, + /* instruction FSGNJX__D, encoding '0b00100010000000000010000001010011' */ + {32, 0b00100010000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjx__d}, + /* instruction FMV__X__D, encoding '0b11100010000000000000000001010011' */ + {32, 0b11100010000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv__x__d}, + /* instruction FMV__D__X, encoding '0b11110010000000000000000001010011' */ + {32, 0b11110010000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv__d__x}, + /* instruction FEQ__D, encoding '0b10100010000000000010000001010011' */ + {32, 0b10100010000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__feq__d}, + /* instruction FLT__D, encoding '0b10100010000000000001000001010011' */ + {32, 0b10100010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__flt__d}, + /* instruction FLE__D, encoding '0b10100010000000000000000001010011' */ + {32, 0b10100010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fle__d}, + /* instruction FCLASS__D, encoding '0b11100010000000000001000001010011' */ + {32, 0b11100010000000000001000001010011, 0b11111111111100000111000001111111, &this_class::__fclass__d}, + /* instruction C__FLD, encoding '0b0010000000000000' */ + {16, 0b0010000000000000, 0b1110000000000011, &this_class::__c__fld}, + /* instruction C__FSD, encoding '0b1010000000000000' */ + {16, 0b1010000000000000, 0b1110000000000011, &this_class::__c__fsd}, + /* instruction C__FLDSP, encoding '0b0010000000000010' */ + {16, 0b0010000000000010, 0b1110000000000011, &this_class::__c__fldsp}, + /* instruction C__FSDSP, encoding '0b1010000000000010' */ + {16, 0b1010000000000010, 0b1110000000000011, &this_class::__c__fsdsp}, + /* instruction SFENCE__VMA, encoding '0b00010010000000000000000001110011' */ + {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence__vma}, + /* instruction SRET, encoding '0b00010000001000000000000001110011' */ + {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, + /* instruction VSETVLI, encoding '0b00000000000000000111000001010111' */ + {32, 0b00000000000000000111000001010111, 0b11110000000000000111000001111111, &this_class::__vsetvli}, + /* instruction VSETIVLI, encoding '0b11000000000000000111000001010111' */ + {32, 0b11000000000000000111000001010111, 0b11110000000000000111000001111111, &this_class::__vsetivli}, + /* instruction VSETVL, encoding '0b10000000000000000111000001010111' */ + {32, 0b10000000000000000111000001010111, 0b11111110000000000111000001111111, &this_class::__vsetvl}, + /* instruction VLE8__V, encoding '0b00000000000000000000000000000111' */ + {32, 0b00000000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vle8__v}, + /* instruction VLE16__V, encoding '0b00000000000000000101000000000111' */ + {32, 0b00000000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vle16__v}, + /* instruction VLE32__V, encoding '0b00000000000000000110000000000111' */ + {32, 0b00000000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vle32__v}, + /* instruction VLE64__V, encoding '0b00000000000000000111000000000111' */ + {32, 0b00000000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vle64__v}, + /* instruction VLSEG2E8__V, encoding '0b00100000000000000000000000000111' */ + {32, 0b00100000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e8__v}, + /* instruction VLSEG2E16__V, encoding '0b00100000000000000101000000000111' */ + {32, 0b00100000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e16__v}, + /* instruction VLSEG2E32__V, encoding '0b00100000000000000110000000000111' */ + {32, 0b00100000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e32__v}, + /* instruction VLSEG2E64__V, encoding '0b00100000000000000111000000000111' */ + {32, 0b00100000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e64__v}, + /* instruction VLSEG3E8__V, encoding '0b01000000000000000000000000000111' */ + {32, 0b01000000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e8__v}, + /* instruction VLSEG3E16__V, encoding '0b01000000000000000101000000000111' */ + {32, 0b01000000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e16__v}, + /* instruction VLSEG3E32__V, encoding '0b01000000000000000110000000000111' */ + {32, 0b01000000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e32__v}, + /* instruction VLSEG3E64__V, encoding '0b01000000000000000111000000000111' */ + {32, 0b01000000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e64__v}, + /* instruction VLSEG4E8__V, encoding '0b01100000000000000000000000000111' */ + {32, 0b01100000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e8__v}, + /* instruction VLSEG4E16__V, encoding '0b01100000000000000101000000000111' */ + {32, 0b01100000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e16__v}, + /* instruction VLSEG4E32__V, encoding '0b01100000000000000110000000000111' */ + {32, 0b01100000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e32__v}, + /* instruction VLSEG4E64__V, encoding '0b01100000000000000111000000000111' */ + {32, 0b01100000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e64__v}, + /* instruction VLSEG5E8__V, encoding '0b10000000000000000000000000000111' */ + {32, 0b10000000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e8__v}, + /* instruction VLSEG5E16__V, encoding '0b10000000000000000101000000000111' */ + {32, 0b10000000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e16__v}, + /* instruction VLSEG5E32__V, encoding '0b10000000000000000110000000000111' */ + {32, 0b10000000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e32__v}, + /* instruction VLSEG5E64__V, encoding '0b10000000000000000111000000000111' */ + {32, 0b10000000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e64__v}, + /* instruction VLSEG6E8__V, encoding '0b10100000000000000000000000000111' */ + {32, 0b10100000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e8__v}, + /* instruction VLSEG6E16__V, encoding '0b10100000000000000101000000000111' */ + {32, 0b10100000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e16__v}, + /* instruction VLSEG6E32__V, encoding '0b10100000000000000110000000000111' */ + {32, 0b10100000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e32__v}, + /* instruction VLSEG6E64__V, encoding '0b10100000000000000111000000000111' */ + {32, 0b10100000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e64__v}, + /* instruction VLSEG7E8__V, encoding '0b11000000000000000000000000000111' */ + {32, 0b11000000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e8__v}, + /* instruction VLSEG7E16__V, encoding '0b11000000000000000101000000000111' */ + {32, 0b11000000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e16__v}, + /* instruction VLSEG7E32__V, encoding '0b11000000000000000110000000000111' */ + {32, 0b11000000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e32__v}, + /* instruction VLSEG7E64__V, encoding '0b11000000000000000111000000000111' */ + {32, 0b11000000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e64__v}, + /* instruction VLSEG8E8__V, encoding '0b11100000000000000000000000000111' */ + {32, 0b11100000000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e8__v}, + /* instruction VLSEG8E16__V, encoding '0b11100000000000000101000000000111' */ + {32, 0b11100000000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e16__v}, + /* instruction VLSEG8E32__V, encoding '0b11100000000000000110000000000111' */ + {32, 0b11100000000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e32__v}, + /* instruction VLSEG8E64__V, encoding '0b11100000000000000111000000000111' */ + {32, 0b11100000000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e64__v}, + /* instruction VSE8__V, encoding '0b00000000000000000000000000100111' */ + {32, 0b00000000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vse8__v}, + /* instruction VSE16__V, encoding '0b00000000000000000101000000100111' */ + {32, 0b00000000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vse16__v}, + /* instruction VSE32__V, encoding '0b00000000000000000110000000100111' */ + {32, 0b00000000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vse32__v}, + /* instruction VSE64__V, encoding '0b00000000000000000111000000100111' */ + {32, 0b00000000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vse64__v}, + /* instruction VSSEG2E8__V, encoding '0b00100000000000000000000000100111' */ + {32, 0b00100000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg2e8__v}, + /* instruction VSSEG2E16__V, encoding '0b00100000000000000101000000100111' */ + {32, 0b00100000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg2e16__v}, + /* instruction VSSEG2E32__V, encoding '0b00100000000000000110000000100111' */ + {32, 0b00100000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg2e32__v}, + /* instruction VSSEG2E64__V, encoding '0b00100000000000000111000000100111' */ + {32, 0b00100000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg2e64__v}, + /* instruction VSSEG3E8__V, encoding '0b01000000000000000000000000100111' */ + {32, 0b01000000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg3e8__v}, + /* instruction VSSEG3E16__V, encoding '0b01000000000000000101000000100111' */ + {32, 0b01000000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg3e16__v}, + /* instruction VSSEG3E32__V, encoding '0b01000000000000000110000000100111' */ + {32, 0b01000000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg3e32__v}, + /* instruction VSSEG3E64__V, encoding '0b01000000000000000111000000100111' */ + {32, 0b01000000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg3e64__v}, + /* instruction VSSEG4E8__V, encoding '0b01100000000000000000000000100111' */ + {32, 0b01100000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg4e8__v}, + /* instruction VSSEG4E16__V, encoding '0b01100000000000000101000000100111' */ + {32, 0b01100000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg4e16__v}, + /* instruction VSSEG4E32__V, encoding '0b01100000000000000110000000100111' */ + {32, 0b01100000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg4e32__v}, + /* instruction VSSEG4E64__V, encoding '0b01100000000000000111000000100111' */ + {32, 0b01100000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg4e64__v}, + /* instruction VSSEG5E8__V, encoding '0b10000000000000000000000000100111' */ + {32, 0b10000000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg5e8__v}, + /* instruction VSSEG5E16__V, encoding '0b10000000000000000101000000100111' */ + {32, 0b10000000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg5e16__v}, + /* instruction VSSEG5E32__V, encoding '0b10000000000000000110000000100111' */ + {32, 0b10000000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg5e32__v}, + /* instruction VSSEG5E64__V, encoding '0b10000000000000000111000000100111' */ + {32, 0b10000000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg5e64__v}, + /* instruction VSSEG6E8__V, encoding '0b10100000000000000000000000100111' */ + {32, 0b10100000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg6e8__v}, + /* instruction VSSEG6E16__V, encoding '0b10100000000000000101000000100111' */ + {32, 0b10100000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg6e16__v}, + /* instruction VSSEG6E32__V, encoding '0b10100000000000000110000000100111' */ + {32, 0b10100000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg6e32__v}, + /* instruction VSSEG6E64__V, encoding '0b10100000000000000111000000100111' */ + {32, 0b10100000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg6e64__v}, + /* instruction VSSEG7E8__V, encoding '0b11000000000000000000000000100111' */ + {32, 0b11000000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg7e8__v}, + /* instruction VSSEG7E16__V, encoding '0b11000000000000000101000000100111' */ + {32, 0b11000000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg7e16__v}, + /* instruction VSSEG7E32__V, encoding '0b11000000000000000110000000100111' */ + {32, 0b11000000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg7e32__v}, + /* instruction VSSEG7E64__V, encoding '0b11000000000000000111000000100111' */ + {32, 0b11000000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg7e64__v}, + /* instruction VSSEG8E8__V, encoding '0b11100000000000000000000000100111' */ + {32, 0b11100000000000000000000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg8e8__v}, + /* instruction VSSEG8E16__V, encoding '0b11100000000000000101000000100111' */ + {32, 0b11100000000000000101000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg8e16__v}, + /* instruction VSSEG8E32__V, encoding '0b11100000000000000110000000100111' */ + {32, 0b11100000000000000110000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg8e32__v}, + /* instruction VSSEG8E64__V, encoding '0b11100000000000000111000000100111' */ + {32, 0b11100000000000000111000000100111, 0b11101101111100000111000001111111, &this_class::__vsseg8e64__v}, + /* instruction VLSE8__V, encoding '0b00001000000000000000000000000111' */ + {32, 0b00001000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlse8__v}, + /* instruction VLSE16__V, encoding '0b00001000000000000101000000000111' */ + {32, 0b00001000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlse16__v}, + /* instruction VLSE32__V, encoding '0b00001000000000000110000000000111' */ + {32, 0b00001000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlse32__v}, + /* instruction VLSE64__V, encoding '0b00001000000000000111000000000111' */ + {32, 0b00001000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlse64__v}, + /* instruction VLSSEG2E8__V, encoding '0b00101000000000000000000000000111' */ + {32, 0b00101000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg2e8__v}, + /* instruction VLSSEG2E16__V, encoding '0b00101000000000000101000000000111' */ + {32, 0b00101000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg2e16__v}, + /* instruction VLSSEG2E32__V, encoding '0b00101000000000000110000000000111' */ + {32, 0b00101000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg2e32__v}, + /* instruction VLSSEG2E64__V, encoding '0b00101000000000000111000000000111' */ + {32, 0b00101000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg2e64__v}, + /* instruction VLSSEG3E8__V, encoding '0b01001000000000000000000000000111' */ + {32, 0b01001000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg3e8__v}, + /* instruction VLSSEG3E16__V, encoding '0b01001000000000000101000000000111' */ + {32, 0b01001000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg3e16__v}, + /* instruction VLSSEG3E32__V, encoding '0b01001000000000000110000000000111' */ + {32, 0b01001000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg3e32__v}, + /* instruction VLSSEG3E64__V, encoding '0b01001000000000000111000000000111' */ + {32, 0b01001000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg3e64__v}, + /* instruction VLSSEG4E8__V, encoding '0b01101000000000000000000000000111' */ + {32, 0b01101000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg4e8__v}, + /* instruction VLSSEG4E16__V, encoding '0b01101000000000000101000000000111' */ + {32, 0b01101000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg4e16__v}, + /* instruction VLSSEG4E32__V, encoding '0b01101000000000000110000000000111' */ + {32, 0b01101000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg4e32__v}, + /* instruction VLSSEG4E64__V, encoding '0b01101000000000000111000000000111' */ + {32, 0b01101000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg4e64__v}, + /* instruction VLSSEG5E8__V, encoding '0b10001000000000000000000000000111' */ + {32, 0b10001000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg5e8__v}, + /* instruction VLSSEG5E16__V, encoding '0b10001000000000000101000000000111' */ + {32, 0b10001000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg5e16__v}, + /* instruction VLSSEG5E32__V, encoding '0b10001000000000000110000000000111' */ + {32, 0b10001000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg5e32__v}, + /* instruction VLSSEG5E64__V, encoding '0b10001000000000000111000000000111' */ + {32, 0b10001000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg5e64__v}, + /* instruction VLSSEG6E8__V, encoding '0b10101000000000000000000000000111' */ + {32, 0b10101000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg6e8__v}, + /* instruction VLSSEG6E16__V, encoding '0b10101000000000000101000000000111' */ + {32, 0b10101000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg6e16__v}, + /* instruction VLSSEG6E32__V, encoding '0b10101000000000000110000000000111' */ + {32, 0b10101000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg6e32__v}, + /* instruction VLSSEG6E64__V, encoding '0b10101000000000000111000000000111' */ + {32, 0b10101000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg6e64__v}, + /* instruction VLSSEG7E8__V, encoding '0b11001000000000000000000000000111' */ + {32, 0b11001000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg7e8__v}, + /* instruction VLSSEG7E16__V, encoding '0b11001000000000000101000000000111' */ + {32, 0b11001000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg7e16__v}, + /* instruction VLSSEG7E32__V, encoding '0b11001000000000000110000000000111' */ + {32, 0b11001000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg7e32__v}, + /* instruction VLSSEG7E64__V, encoding '0b11001000000000000111000000000111' */ + {32, 0b11001000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg7e64__v}, + /* instruction VLSSEG8E8__V, encoding '0b11101000000000000000000000000111' */ + {32, 0b11101000000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg8e8__v}, + /* instruction VLSSEG8E16__V, encoding '0b11101000000000000101000000000111' */ + {32, 0b11101000000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg8e16__v}, + /* instruction VLSSEG8E32__V, encoding '0b11101000000000000110000000000111' */ + {32, 0b11101000000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg8e32__v}, + /* instruction VLSSEG8E64__V, encoding '0b11101000000000000111000000000111' */ + {32, 0b11101000000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vlsseg8e64__v}, + /* instruction VSSE8__V, encoding '0b00001000000000000000000000100111' */ + {32, 0b00001000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsse8__v}, + /* instruction VSSE16__V, encoding '0b00001000000000000101000000100111' */ + {32, 0b00001000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsse16__v}, + /* instruction VSSE32__V, encoding '0b00001000000000000110000000100111' */ + {32, 0b00001000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsse32__v}, + /* instruction VSSE64__V, encoding '0b00001000000000000111000000100111' */ + {32, 0b00001000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsse64__v}, + /* instruction VSSSEG2E8__V, encoding '0b00101000000000000000000000100111' */ + {32, 0b00101000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg2e8__v}, + /* instruction VSSSEG2E16__V, encoding '0b00101000000000000101000000100111' */ + {32, 0b00101000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg2e16__v}, + /* instruction VSSSEG2E32__V, encoding '0b00101000000000000110000000100111' */ + {32, 0b00101000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg2e32__v}, + /* instruction VSSSEG2E64__V, encoding '0b00101000000000000111000000100111' */ + {32, 0b00101000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg2e64__v}, + /* instruction VSSSEG3E8__V, encoding '0b01001000000000000000000000100111' */ + {32, 0b01001000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg3e8__v}, + /* instruction VSSSEG3E16__V, encoding '0b01001000000000000101000000100111' */ + {32, 0b01001000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg3e16__v}, + /* instruction VSSSEG3E32__V, encoding '0b01001000000000000110000000100111' */ + {32, 0b01001000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg3e32__v}, + /* instruction VSSSEG3E64__V, encoding '0b01001000000000000111000000100111' */ + {32, 0b01001000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg3e64__v}, + /* instruction VSSSEG4E8__V, encoding '0b01101000000000000000000000100111' */ + {32, 0b01101000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg4e8__v}, + /* instruction VSSSEG4E16__V, encoding '0b01101000000000000101000000100111' */ + {32, 0b01101000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg4e16__v}, + /* instruction VSSSEG4E32__V, encoding '0b01101000000000000110000000100111' */ + {32, 0b01101000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg4e32__v}, + /* instruction VSSSEG4E64__V, encoding '0b01101000000000000111000000100111' */ + {32, 0b01101000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg4e64__v}, + /* instruction VSSSEG5E8__V, encoding '0b10001000000000000000000000100111' */ + {32, 0b10001000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg5e8__v}, + /* instruction VSSSEG5E16__V, encoding '0b10001000000000000101000000100111' */ + {32, 0b10001000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg5e16__v}, + /* instruction VSSSEG5E32__V, encoding '0b10001000000000000110000000100111' */ + {32, 0b10001000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg5e32__v}, + /* instruction VSSSEG5E64__V, encoding '0b10001000000000000111000000100111' */ + {32, 0b10001000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg5e64__v}, + /* instruction VSSSEG6E8__V, encoding '0b10101000000000000000000000100111' */ + {32, 0b10101000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg6e8__v}, + /* instruction VSSSEG6E16__V, encoding '0b10101000000000000101000000100111' */ + {32, 0b10101000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg6e16__v}, + /* instruction VSSSEG6E32__V, encoding '0b10101000000000000110000000100111' */ + {32, 0b10101000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg6e32__v}, + /* instruction VSSSEG6E64__V, encoding '0b10101000000000000111000000100111' */ + {32, 0b10101000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg6e64__v}, + /* instruction VSSSEG7E8__V, encoding '0b11001000000000000000000000100111' */ + {32, 0b11001000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg7e8__v}, + /* instruction VSSSEG7E16__V, encoding '0b11001000000000000101000000100111' */ + {32, 0b11001000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg7e16__v}, + /* instruction VSSSEG7E32__V, encoding '0b11001000000000000110000000100111' */ + {32, 0b11001000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg7e32__v}, + /* instruction VSSSEG7E64__V, encoding '0b11001000000000000111000000100111' */ + {32, 0b11001000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg7e64__v}, + /* instruction VSSSEG8E8__V, encoding '0b11101000000000000000000000100111' */ + {32, 0b11101000000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg8e8__v}, + /* instruction VSSSEG8E16__V, encoding '0b11101000000000000101000000100111' */ + {32, 0b11101000000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg8e16__v}, + /* instruction VSSSEG8E32__V, encoding '0b11101000000000000110000000100111' */ + {32, 0b11101000000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg8e32__v}, + /* instruction VSSSEG8E64__V, encoding '0b11101000000000000111000000100111' */ + {32, 0b11101000000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vssseg8e64__v}, + /* instruction VLE8FF__V, encoding '0b00000001000000000000000000000111' */ + {32, 0b00000001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vle8ff__v}, + /* instruction VLE16FF__V, encoding '0b00000001000000000101000000000111' */ + {32, 0b00000001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vle16ff__v}, + /* instruction VLE32FF__V, encoding '0b00000001000000000110000000000111' */ + {32, 0b00000001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vle32ff__v}, + /* instruction VLE64FF__V, encoding '0b00000001000000000111000000000111' */ + {32, 0b00000001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vle64ff__v}, + /* instruction VLSEG2E8FF__V, encoding '0b00100001000000000000000000000111' */ + {32, 0b00100001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e8ff__v}, + /* instruction VLSEG2E16FF__V, encoding '0b00100001000000000101000000000111' */ + {32, 0b00100001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e16ff__v}, + /* instruction VLSEG2E32FF__V, encoding '0b00100001000000000110000000000111' */ + {32, 0b00100001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e32ff__v}, + /* instruction VLSEG2E64FF__V, encoding '0b00100001000000000111000000000111' */ + {32, 0b00100001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg2e64ff__v}, + /* instruction VLSEG3E8FF__V, encoding '0b01000001000000000000000000000111' */ + {32, 0b01000001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e8ff__v}, + /* instruction VLSEG3E16FF__V, encoding '0b01000001000000000101000000000111' */ + {32, 0b01000001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e16ff__v}, + /* instruction VLSEG3E32FF__V, encoding '0b01000001000000000110000000000111' */ + {32, 0b01000001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e32ff__v}, + /* instruction VLSEG3E64FF__V, encoding '0b01000001000000000111000000000111' */ + {32, 0b01000001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg3e64ff__v}, + /* instruction VLSEG4E8FF__V, encoding '0b01100001000000000000000000000111' */ + {32, 0b01100001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e8ff__v}, + /* instruction VLSEG4E16FF__V, encoding '0b01100001000000000101000000000111' */ + {32, 0b01100001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e16ff__v}, + /* instruction VLSEG4E32FF__V, encoding '0b01100001000000000110000000000111' */ + {32, 0b01100001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e32ff__v}, + /* instruction VLSEG4E64FF__V, encoding '0b01100001000000000111000000000111' */ + {32, 0b01100001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg4e64ff__v}, + /* instruction VLSEG5E8FF__V, encoding '0b10000001000000000000000000000111' */ + {32, 0b10000001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e8ff__v}, + /* instruction VLSEG5E16FF__V, encoding '0b10000001000000000101000000000111' */ + {32, 0b10000001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e16ff__v}, + /* instruction VLSEG5E32FF__V, encoding '0b10000001000000000110000000000111' */ + {32, 0b10000001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e32ff__v}, + /* instruction VLSEG5E64FF__V, encoding '0b10000001000000000111000000000111' */ + {32, 0b10000001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg5e64ff__v}, + /* instruction VLSEG6E8FF__V, encoding '0b10100001000000000000000000000111' */ + {32, 0b10100001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e8ff__v}, + /* instruction VLSEG6E16FF__V, encoding '0b10100001000000000101000000000111' */ + {32, 0b10100001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e16ff__v}, + /* instruction VLSEG6E32FF__V, encoding '0b10100001000000000110000000000111' */ + {32, 0b10100001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e32ff__v}, + /* instruction VLSEG6E64FF__V, encoding '0b10100001000000000111000000000111' */ + {32, 0b10100001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg6e64ff__v}, + /* instruction VLSEG7E8FF__V, encoding '0b11000001000000000000000000000111' */ + {32, 0b11000001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e8ff__v}, + /* instruction VLSEG7E16FF__V, encoding '0b11000001000000000101000000000111' */ + {32, 0b11000001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e16ff__v}, + /* instruction VLSEG7E32FF__V, encoding '0b11000001000000000110000000000111' */ + {32, 0b11000001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e32ff__v}, + /* instruction VLSEG7E64FF__V, encoding '0b11000001000000000111000000000111' */ + {32, 0b11000001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg7e64ff__v}, + /* instruction VLSEG8E8FF__V, encoding '0b11100001000000000000000000000111' */ + {32, 0b11100001000000000000000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e8ff__v}, + /* instruction VLSEG8E16FF__V, encoding '0b11100001000000000101000000000111' */ + {32, 0b11100001000000000101000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e16ff__v}, + /* instruction VLSEG8E32FF__V, encoding '0b11100001000000000110000000000111' */ + {32, 0b11100001000000000110000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e32ff__v}, + /* instruction VLSEG8E64FF__V, encoding '0b11100001000000000111000000000111' */ + {32, 0b11100001000000000111000000000111, 0b11101101111100000111000001111111, &this_class::__vlseg8e64ff__v}, + /* instruction VSM__V, encoding '0b00000010101100000000000000100111' */ + {32, 0b00000010101100000000000000100111, 0b11111111111100000111000001111111, &this_class::__vsm__v}, + /* instruction VLM__V, encoding '0b00000010101100000000000000000111' */ + {32, 0b00000010101100000000000000000111, 0b11111111111100000111000001111111, &this_class::__vlm__v}, + /* instruction VL1RE8__V, encoding '0b00000010100000000000000000000111' */ + {32, 0b00000010100000000000000000000111, 0b11101111111100000111000001111111, &this_class::__vl1re8__v}, + /* instruction VL1RE16__V, encoding '0b00000010100000000101000000000111' */ + {32, 0b00000010100000000101000000000111, 0b11101111111100000111000001111111, &this_class::__vl1re16__v}, + /* instruction VL1RE32__V, encoding '0b00000010100000000110000000000111' */ + {32, 0b00000010100000000110000000000111, 0b11101111111100000111000001111111, &this_class::__vl1re32__v}, + /* instruction VL1RE64__V, encoding '0b00000010100000000111000000000111' */ + {32, 0b00000010100000000111000000000111, 0b11101111111100000111000001111111, &this_class::__vl1re64__v}, + /* instruction VL2RE8__V, encoding '0b00100010100000000000000000000111' */ + {32, 0b00100010100000000000000000000111, 0b11101111111100000111000001111111, &this_class::__vl2re8__v}, + /* instruction VL2RE16__V, encoding '0b00100010100000000101000000000111' */ + {32, 0b00100010100000000101000000000111, 0b11101111111100000111000001111111, &this_class::__vl2re16__v}, + /* instruction VL2RE32__V, encoding '0b00100010100000000110000000000111' */ + {32, 0b00100010100000000110000000000111, 0b11101111111100000111000001111111, &this_class::__vl2re32__v}, + /* instruction VL2RE64__V, encoding '0b00100010100000000111000000000111' */ + {32, 0b00100010100000000111000000000111, 0b11101111111100000111000001111111, &this_class::__vl2re64__v}, + /* instruction VL4RE8__V, encoding '0b01100010100000000000000000000111' */ + {32, 0b01100010100000000000000000000111, 0b11101111111100000111000001111111, &this_class::__vl4re8__v}, + /* instruction VL4RE16__V, encoding '0b01100010100000000101000000000111' */ + {32, 0b01100010100000000101000000000111, 0b11101111111100000111000001111111, &this_class::__vl4re16__v}, + /* instruction VL4RE32__V, encoding '0b01100010100000000110000000000111' */ + {32, 0b01100010100000000110000000000111, 0b11101111111100000111000001111111, &this_class::__vl4re32__v}, + /* instruction VL4RE64__V, encoding '0b01100010100000000111000000000111' */ + {32, 0b01100010100000000111000000000111, 0b11101111111100000111000001111111, &this_class::__vl4re64__v}, + /* instruction VL8RE8__V, encoding '0b11100010100000000000000000000111' */ + {32, 0b11100010100000000000000000000111, 0b11101111111100000111000001111111, &this_class::__vl8re8__v}, + /* instruction VL8RE16__V, encoding '0b11100010100000000101000000000111' */ + {32, 0b11100010100000000101000000000111, 0b11101111111100000111000001111111, &this_class::__vl8re16__v}, + /* instruction VL8RE32__V, encoding '0b11100010100000000110000000000111' */ + {32, 0b11100010100000000110000000000111, 0b11101111111100000111000001111111, &this_class::__vl8re32__v}, + /* instruction VL8RE64__V, encoding '0b11100010100000000111000000000111' */ + {32, 0b11100010100000000111000000000111, 0b11101111111100000111000001111111, &this_class::__vl8re64__v}, + /* instruction VS1RE64__V, encoding '0b00000010100000000000000000100111' */ + {32, 0b00000010100000000000000000100111, 0b11111111111100000111000001111111, &this_class::__vs1re64__v}, + /* instruction VS2RE64__V, encoding '0b00100010100000000000000000100111' */ + {32, 0b00100010100000000000000000100111, 0b11111111111100000111000001111111, &this_class::__vs2re64__v}, + /* instruction VS4RE64__V, encoding '0b01100010100000000000000000100111' */ + {32, 0b01100010100000000000000000100111, 0b11111111111100000111000001111111, &this_class::__vs4re64__v}, + /* instruction VS8RE64__V, encoding '0b11100010100000000000000000100111' */ + {32, 0b11100010100000000000000000100111, 0b11111111111100000111000001111111, &this_class::__vs8re64__v}, + /* instruction VLOXEI8__V, encoding '0b00001100000000000000000000000111' */ + {32, 0b00001100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxei8__v}, + /* instruction VLOXEI16__V, encoding '0b00001100000000000101000000000111' */ + {32, 0b00001100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxei16__v}, + /* instruction VLOXEI32__V, encoding '0b00001100000000000110000000000111' */ + {32, 0b00001100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxei32__v}, + /* instruction VLOXEI64__V, encoding '0b00001100000000000111000000000111' */ + {32, 0b00001100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxei64__v}, + /* instruction VLOXSEG2EI8__V, encoding '0b00101100000000000000000000000111' */ + {32, 0b00101100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg2ei8__v}, + /* instruction VLOXSEG2EI16__V, encoding '0b00101100000000000101000000000111' */ + {32, 0b00101100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg2ei16__v}, + /* instruction VLOXSEG2EI32__V, encoding '0b00101100000000000110000000000111' */ + {32, 0b00101100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg2ei32__v}, + /* instruction VLOXSEG2EI64__V, encoding '0b00101100000000000111000000000111' */ + {32, 0b00101100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg2ei64__v}, + /* instruction VLOXSEG3EI8__V, encoding '0b01001100000000000000000000000111' */ + {32, 0b01001100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg3ei8__v}, + /* instruction VLOXSEG3EI16__V, encoding '0b01001100000000000101000000000111' */ + {32, 0b01001100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg3ei16__v}, + /* instruction VLOXSEG3EI32__V, encoding '0b01001100000000000110000000000111' */ + {32, 0b01001100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg3ei32__v}, + /* instruction VLOXSEG3EI64__V, encoding '0b01001100000000000111000000000111' */ + {32, 0b01001100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg3ei64__v}, + /* instruction VLOXSEG4EI8__V, encoding '0b01101100000000000000000000000111' */ + {32, 0b01101100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg4ei8__v}, + /* instruction VLOXSEG4EI16__V, encoding '0b01101100000000000101000000000111' */ + {32, 0b01101100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg4ei16__v}, + /* instruction VLOXSEG4EI32__V, encoding '0b01101100000000000110000000000111' */ + {32, 0b01101100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg4ei32__v}, + /* instruction VLOXSEG4EI64__V, encoding '0b01101100000000000111000000000111' */ + {32, 0b01101100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg4ei64__v}, + /* instruction VLOXSEG5EI8__V, encoding '0b10001100000000000000000000000111' */ + {32, 0b10001100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg5ei8__v}, + /* instruction VLOXSEG5EI16__V, encoding '0b10001100000000000101000000000111' */ + {32, 0b10001100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg5ei16__v}, + /* instruction VLOXSEG5EI32__V, encoding '0b10001100000000000110000000000111' */ + {32, 0b10001100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg5ei32__v}, + /* instruction VLOXSEG5EI64__V, encoding '0b10001100000000000111000000000111' */ + {32, 0b10001100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg5ei64__v}, + /* instruction VLOXSEG6EI8__V, encoding '0b10101100000000000000000000000111' */ + {32, 0b10101100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg6ei8__v}, + /* instruction VLOXSEG6EI16__V, encoding '0b10101100000000000101000000000111' */ + {32, 0b10101100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg6ei16__v}, + /* instruction VLOXSEG6EI32__V, encoding '0b10101100000000000110000000000111' */ + {32, 0b10101100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg6ei32__v}, + /* instruction VLOXSEG6EI64__V, encoding '0b10101100000000000111000000000111' */ + {32, 0b10101100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg6ei64__v}, + /* instruction VLOXSEG7EI8__V, encoding '0b11001100000000000000000000000111' */ + {32, 0b11001100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg7ei8__v}, + /* instruction VLOXSEG7EI16__V, encoding '0b11001100000000000101000000000111' */ + {32, 0b11001100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg7ei16__v}, + /* instruction VLOXSEG7EI32__V, encoding '0b11001100000000000110000000000111' */ + {32, 0b11001100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg7ei32__v}, + /* instruction VLOXSEG7EI64__V, encoding '0b11001100000000000111000000000111' */ + {32, 0b11001100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg7ei64__v}, + /* instruction VLOXSEG8EI8__V, encoding '0b11101100000000000000000000000111' */ + {32, 0b11101100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg8ei8__v}, + /* instruction VLOXSEG8EI16__V, encoding '0b11101100000000000101000000000111' */ + {32, 0b11101100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg8ei16__v}, + /* instruction VLOXSEG8EI32__V, encoding '0b11101100000000000110000000000111' */ + {32, 0b11101100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg8ei32__v}, + /* instruction VLOXSEG8EI64__V, encoding '0b11101100000000000111000000000111' */ + {32, 0b11101100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vloxseg8ei64__v}, + /* instruction VSOXEI8__V, encoding '0b00001100000000000000000000100111' */ + {32, 0b00001100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxei8__v}, + /* instruction VSOXEI16__V, encoding '0b00001100000000000101000000100111' */ + {32, 0b00001100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxei16__v}, + /* instruction VSOXEI32__V, encoding '0b00001100000000000110000000100111' */ + {32, 0b00001100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxei32__v}, + /* instruction VSOXEI64__V, encoding '0b00001100000000000111000000100111' */ + {32, 0b00001100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxei64__v}, + /* instruction VSOXSEG2EI8__V, encoding '0b00101100000000000000000000100111' */ + {32, 0b00101100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg2ei8__v}, + /* instruction VSOXSEG2EI16__V, encoding '0b00101100000000000101000000100111' */ + {32, 0b00101100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg2ei16__v}, + /* instruction VSOXSEG2EI32__V, encoding '0b00101100000000000110000000100111' */ + {32, 0b00101100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg2ei32__v}, + /* instruction VSOXSEG2EI64__V, encoding '0b00101100000000000111000000100111' */ + {32, 0b00101100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg2ei64__v}, + /* instruction VSOXSEG3EI8__V, encoding '0b01001100000000000000000000100111' */ + {32, 0b01001100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg3ei8__v}, + /* instruction VSOXSEG3EI16__V, encoding '0b01001100000000000101000000100111' */ + {32, 0b01001100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg3ei16__v}, + /* instruction VSOXSEG3EI32__V, encoding '0b01001100000000000110000000100111' */ + {32, 0b01001100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg3ei32__v}, + /* instruction VSOXSEG3EI64__V, encoding '0b01001100000000000111000000100111' */ + {32, 0b01001100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg3ei64__v}, + /* instruction VSOXSEG4EI8__V, encoding '0b01101100000000000000000000100111' */ + {32, 0b01101100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg4ei8__v}, + /* instruction VSOXSEG4EI16__V, encoding '0b01101100000000000101000000100111' */ + {32, 0b01101100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg4ei16__v}, + /* instruction VSOXSEG4EI32__V, encoding '0b01101100000000000110000000100111' */ + {32, 0b01101100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg4ei32__v}, + /* instruction VSOXSEG4EI64__V, encoding '0b01101100000000000111000000100111' */ + {32, 0b01101100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg4ei64__v}, + /* instruction VSOXSEG5EI8__V, encoding '0b10001100000000000000000000100111' */ + {32, 0b10001100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg5ei8__v}, + /* instruction VSOXSEG5EI16__V, encoding '0b10001100000000000101000000100111' */ + {32, 0b10001100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg5ei16__v}, + /* instruction VSOXSEG5EI32__V, encoding '0b10001100000000000110000000100111' */ + {32, 0b10001100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg5ei32__v}, + /* instruction VSOXSEG5EI64__V, encoding '0b10001100000000000111000000100111' */ + {32, 0b10001100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg5ei64__v}, + /* instruction VSOXSEG6EI8__V, encoding '0b10101100000000000000000000100111' */ + {32, 0b10101100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg6ei8__v}, + /* instruction VSOXSEG6EI16__V, encoding '0b10101100000000000101000000100111' */ + {32, 0b10101100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg6ei16__v}, + /* instruction VSOXSEG6EI32__V, encoding '0b10101100000000000110000000100111' */ + {32, 0b10101100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg6ei32__v}, + /* instruction VSOXSEG6EI64__V, encoding '0b10101100000000000111000000100111' */ + {32, 0b10101100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg6ei64__v}, + /* instruction VSOXSEG7EI8__V, encoding '0b11001100000000000000000000100111' */ + {32, 0b11001100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg7ei8__v}, + /* instruction VSOXSEG7EI16__V, encoding '0b11001100000000000101000000100111' */ + {32, 0b11001100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg7ei16__v}, + /* instruction VSOXSEG7EI32__V, encoding '0b11001100000000000110000000100111' */ + {32, 0b11001100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg7ei32__v}, + /* instruction VSOXSEG7EI64__V, encoding '0b11001100000000000111000000100111' */ + {32, 0b11001100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg7ei64__v}, + /* instruction VSOXSEG8EI8__V, encoding '0b11101100000000000000000000100111' */ + {32, 0b11101100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg8ei8__v}, + /* instruction VSOXSEG8EI16__V, encoding '0b11101100000000000101000000100111' */ + {32, 0b11101100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg8ei16__v}, + /* instruction VSOXSEG8EI32__V, encoding '0b11101100000000000110000000100111' */ + {32, 0b11101100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg8ei32__v}, + /* instruction VSOXSEG8EI64__V, encoding '0b11101100000000000111000000100111' */ + {32, 0b11101100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsoxseg8ei64__v}, + /* instruction VLUXEI8__V, encoding '0b00000100000000000000000000000111' */ + {32, 0b00000100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxei8__v}, + /* instruction VLUXEI16__V, encoding '0b00000100000000000101000000000111' */ + {32, 0b00000100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxei16__v}, + /* instruction VLUXEI32__V, encoding '0b00000100000000000110000000000111' */ + {32, 0b00000100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxei32__v}, + /* instruction VLUXEI64__V, encoding '0b00000100000000000111000000000111' */ + {32, 0b00000100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxei64__v}, + /* instruction VLUXSEG2EI8__V, encoding '0b00100100000000000000000000000111' */ + {32, 0b00100100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg2ei8__v}, + /* instruction VLUXSEG2EI16__V, encoding '0b00100100000000000101000000000111' */ + {32, 0b00100100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg2ei16__v}, + /* instruction VLUXSEG2EI32__V, encoding '0b00100100000000000110000000000111' */ + {32, 0b00100100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg2ei32__v}, + /* instruction VLUXSEG2EI64__V, encoding '0b00100100000000000111000000000111' */ + {32, 0b00100100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg2ei64__v}, + /* instruction VLUXSEG3EI8__V, encoding '0b01000100000000000000000000000111' */ + {32, 0b01000100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg3ei8__v}, + /* instruction VLUXSEG3EI16__V, encoding '0b01000100000000000101000000000111' */ + {32, 0b01000100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg3ei16__v}, + /* instruction VLUXSEG3EI32__V, encoding '0b01000100000000000110000000000111' */ + {32, 0b01000100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg3ei32__v}, + /* instruction VLUXSEG3EI64__V, encoding '0b01000100000000000111000000000111' */ + {32, 0b01000100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg3ei64__v}, + /* instruction VLUXSEG4EI8__V, encoding '0b01100100000000000000000000000111' */ + {32, 0b01100100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg4ei8__v}, + /* instruction VLUXSEG4EI16__V, encoding '0b01100100000000000101000000000111' */ + {32, 0b01100100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg4ei16__v}, + /* instruction VLUXSEG4EI32__V, encoding '0b01100100000000000110000000000111' */ + {32, 0b01100100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg4ei32__v}, + /* instruction VLUXSEG4EI64__V, encoding '0b01100100000000000111000000000111' */ + {32, 0b01100100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg4ei64__v}, + /* instruction VLUXSEG5EI8__V, encoding '0b10000100000000000000000000000111' */ + {32, 0b10000100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg5ei8__v}, + /* instruction VLUXSEG5EI16__V, encoding '0b10000100000000000101000000000111' */ + {32, 0b10000100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg5ei16__v}, + /* instruction VLUXSEG5EI32__V, encoding '0b10000100000000000110000000000111' */ + {32, 0b10000100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg5ei32__v}, + /* instruction VLUXSEG5EI64__V, encoding '0b10000100000000000111000000000111' */ + {32, 0b10000100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg5ei64__v}, + /* instruction VLUXSEG6EI8__V, encoding '0b10100100000000000000000000000111' */ + {32, 0b10100100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg6ei8__v}, + /* instruction VLUXSEG6EI16__V, encoding '0b10100100000000000101000000000111' */ + {32, 0b10100100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg6ei16__v}, + /* instruction VLUXSEG6EI32__V, encoding '0b10100100000000000110000000000111' */ + {32, 0b10100100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg6ei32__v}, + /* instruction VLUXSEG6EI64__V, encoding '0b10100100000000000111000000000111' */ + {32, 0b10100100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg6ei64__v}, + /* instruction VLUXSEG7EI8__V, encoding '0b11000100000000000000000000000111' */ + {32, 0b11000100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg7ei8__v}, + /* instruction VLUXSEG7EI16__V, encoding '0b11000100000000000101000000000111' */ + {32, 0b11000100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg7ei16__v}, + /* instruction VLUXSEG7EI32__V, encoding '0b11000100000000000110000000000111' */ + {32, 0b11000100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg7ei32__v}, + /* instruction VLUXSEG7EI64__V, encoding '0b11000100000000000111000000000111' */ + {32, 0b11000100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg7ei64__v}, + /* instruction VLUXSEG8EI8__V, encoding '0b11100100000000000000000000000111' */ + {32, 0b11100100000000000000000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg8ei8__v}, + /* instruction VLUXSEG8EI16__V, encoding '0b11100100000000000101000000000111' */ + {32, 0b11100100000000000101000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg8ei16__v}, + /* instruction VLUXSEG8EI32__V, encoding '0b11100100000000000110000000000111' */ + {32, 0b11100100000000000110000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg8ei32__v}, + /* instruction VLUXSEG8EI64__V, encoding '0b11100100000000000111000000000111' */ + {32, 0b11100100000000000111000000000111, 0b11101100000000000111000001111111, &this_class::__vluxseg8ei64__v}, + /* instruction VSUXEI8__V, encoding '0b00000100000000000000000000100111' */ + {32, 0b00000100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxei8__v}, + /* instruction VSUXEI16__V, encoding '0b00000100000000000101000000100111' */ + {32, 0b00000100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxei16__v}, + /* instruction VSUXEI32__V, encoding '0b00000100000000000110000000100111' */ + {32, 0b00000100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxei32__v}, + /* instruction VSUXEI64__V, encoding '0b00000100000000000111000000100111' */ + {32, 0b00000100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxei64__v}, + /* instruction VSUXSEG2EI8__V, encoding '0b00100100000000000000000000100111' */ + {32, 0b00100100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg2ei8__v}, + /* instruction VSUXSEG2EI16__V, encoding '0b00100100000000000101000000100111' */ + {32, 0b00100100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg2ei16__v}, + /* instruction VSUXSEG2EI32__V, encoding '0b00100100000000000110000000100111' */ + {32, 0b00100100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg2ei32__v}, + /* instruction VSUXSEG2EI64__V, encoding '0b00100100000000000111000000100111' */ + {32, 0b00100100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg2ei64__v}, + /* instruction VSUXSEG3EI8__V, encoding '0b01000100000000000000000000100111' */ + {32, 0b01000100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg3ei8__v}, + /* instruction VSUXSEG3EI16__V, encoding '0b01000100000000000101000000100111' */ + {32, 0b01000100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg3ei16__v}, + /* instruction VSUXSEG3EI32__V, encoding '0b01000100000000000110000000100111' */ + {32, 0b01000100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg3ei32__v}, + /* instruction VSUXSEG3EI64__V, encoding '0b01000100000000000111000000100111' */ + {32, 0b01000100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg3ei64__v}, + /* instruction VSUXSEG4EI8__V, encoding '0b01100100000000000000000000100111' */ + {32, 0b01100100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg4ei8__v}, + /* instruction VSUXSEG4EI16__V, encoding '0b01100100000000000101000000100111' */ + {32, 0b01100100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg4ei16__v}, + /* instruction VSUXSEG4EI32__V, encoding '0b01100100000000000110000000100111' */ + {32, 0b01100100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg4ei32__v}, + /* instruction VSUXSEG4EI64__V, encoding '0b01100100000000000111000000100111' */ + {32, 0b01100100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg4ei64__v}, + /* instruction VSUXSEG5EI8__V, encoding '0b10000100000000000000000000100111' */ + {32, 0b10000100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg5ei8__v}, + /* instruction VSUXSEG5EI16__V, encoding '0b10000100000000000101000000100111' */ + {32, 0b10000100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg5ei16__v}, + /* instruction VSUXSEG5EI32__V, encoding '0b10000100000000000110000000100111' */ + {32, 0b10000100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg5ei32__v}, + /* instruction VSUXSEG5EI64__V, encoding '0b10000100000000000111000000100111' */ + {32, 0b10000100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg5ei64__v}, + /* instruction VSUXSEG6EI8__V, encoding '0b10100100000000000000000000100111' */ + {32, 0b10100100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg6ei8__v}, + /* instruction VSUXSEG6EI16__V, encoding '0b10100100000000000101000000100111' */ + {32, 0b10100100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg6ei16__v}, + /* instruction VSUXSEG6EI32__V, encoding '0b10100100000000000110000000100111' */ + {32, 0b10100100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg6ei32__v}, + /* instruction VSUXSEG6EI64__V, encoding '0b10100100000000000111000000100111' */ + {32, 0b10100100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg6ei64__v}, + /* instruction VSUXSEG7EI8__V, encoding '0b11000100000000000000000000100111' */ + {32, 0b11000100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg7ei8__v}, + /* instruction VSUXSEG7EI16__V, encoding '0b11000100000000000101000000100111' */ + {32, 0b11000100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg7ei16__v}, + /* instruction VSUXSEG7EI32__V, encoding '0b11000100000000000110000000100111' */ + {32, 0b11000100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg7ei32__v}, + /* instruction VSUXSEG7EI64__V, encoding '0b11000100000000000111000000100111' */ + {32, 0b11000100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg7ei64__v}, + /* instruction VSUXSEG8EI8__V, encoding '0b11100100000000000000000000100111' */ + {32, 0b11100100000000000000000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg8ei8__v}, + /* instruction VSUXSEG8EI16__V, encoding '0b11100100000000000101000000100111' */ + {32, 0b11100100000000000101000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg8ei16__v}, + /* instruction VSUXSEG8EI32__V, encoding '0b11100100000000000110000000100111' */ + {32, 0b11100100000000000110000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg8ei32__v}, + /* instruction VSUXSEG8EI64__V, encoding '0b11100100000000000111000000100111' */ + {32, 0b11100100000000000111000000100111, 0b11101100000000000111000001111111, &this_class::__vsuxseg8ei64__v}, + /* instruction VADD__VI, encoding '0b00000000000000000011000001010111' */ + {32, 0b00000000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vadd__vi}, + /* instruction VADD__VV, encoding '0b00000000000000000000000001010111' */ + {32, 0b00000000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vadd__vv}, + /* instruction VADD__VX, encoding '0b00000000000000000100000001010111' */ + {32, 0b00000000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vadd__vx}, + /* instruction VSUB__VV, encoding '0b00001000000000000000000001010111' */ + {32, 0b00001000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsub__vv}, + /* instruction VSUB__VX, encoding '0b00001000000000000100000001010111' */ + {32, 0b00001000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsub__vx}, + /* instruction VRSUB__VI, encoding '0b00001100000000000011000001010111' */ + {32, 0b00001100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vrsub__vi}, + /* instruction VRSUB__VX, encoding '0b00001100000000000100000001010111' */ + {32, 0b00001100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vrsub__vx}, + /* instruction VWADDU__VV, encoding '0b11000000000000000010000001010111' */ + {32, 0b11000000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwaddu__vv}, + /* instruction VWADDU__VX, encoding '0b11000000000000000110000001010111' */ + {32, 0b11000000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwaddu__vx}, + /* instruction VWSUBU__VV, encoding '0b11001000000000000010000001010111' */ + {32, 0b11001000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwsubu__vv}, + /* instruction VWSUBU__VX, encoding '0b11001000000000000110000001010111' */ + {32, 0b11001000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwsubu__vx}, + /* instruction VWADD__VV, encoding '0b11000100000000000010000001010111' */ + {32, 0b11000100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwadd__vv}, + /* instruction VWADD__VX, encoding '0b11000100000000000110000001010111' */ + {32, 0b11000100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwadd__vx}, + /* instruction VWSUB__VV, encoding '0b11001100000000000010000001010111' */ + {32, 0b11001100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwsub__vv}, + /* instruction VWSUB__VX, encoding '0b11001100000000000110000001010111' */ + {32, 0b11001100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwsub__vx}, + /* instruction VWADDU__WV, encoding '0b11010000000000000010000001010111' */ + {32, 0b11010000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwaddu__wv}, + /* instruction VWADDU__WX, encoding '0b11010000000000000110000001010111' */ + {32, 0b11010000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwaddu__wx}, + /* instruction VWSUBU__WV, encoding '0b11011000000000000010000001010111' */ + {32, 0b11011000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwsubu__wv}, + /* instruction VWSUBU__WX, encoding '0b11011000000000000110000001010111' */ + {32, 0b11011000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwsubu__wx}, + /* instruction VWADD__WV, encoding '0b11010100000000000010000001010111' */ + {32, 0b11010100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwadd__wv}, + /* instruction VWADD__WX, encoding '0b11010100000000000110000001010111' */ + {32, 0b11010100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwadd__wx}, + /* instruction VWSUB__WV, encoding '0b11011100000000000010000001010111' */ + {32, 0b11011100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwsub__wv}, + /* instruction VWSUB__WX, encoding '0b11011100000000000110000001010111' */ + {32, 0b11011100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwsub__wx}, + /* instruction VZEXT__VF2, encoding '0b01001000000000110010000001010111' */ + {32, 0b01001000000000110010000001010111, 0b11111100000011111111000001111111, &this_class::__vzext__vf2}, + /* instruction VSEXT__VF2, encoding '0b01001000000000111010000001010111' */ + {32, 0b01001000000000111010000001010111, 0b11111100000011111111000001111111, &this_class::__vsext__vf2}, + /* instruction VZEXT__VF4, encoding '0b01001000000000100010000001010111' */ + {32, 0b01001000000000100010000001010111, 0b11111100000011111111000001111111, &this_class::__vzext__vf4}, + /* instruction VSEXT__VF4, encoding '0b01001000000000101010000001010111' */ + {32, 0b01001000000000101010000001010111, 0b11111100000011111111000001111111, &this_class::__vsext__vf4}, + /* instruction VZEXT__VF8, encoding '0b01001000000000010010000001010111' */ + {32, 0b01001000000000010010000001010111, 0b11111100000011111111000001111111, &this_class::__vzext__vf8}, + /* instruction VSEXT__VF8, encoding '0b01001000000000011010000001010111' */ + {32, 0b01001000000000011010000001010111, 0b11111100000011111111000001111111, &this_class::__vsext__vf8}, + /* instruction VADC__VVM, encoding '0b01000000000000000000000001010111' */ + {32, 0b01000000000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vadc__vvm}, + /* instruction VADC__VXM, encoding '0b01000000000000000100000001010111' */ + {32, 0b01000000000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vadc__vxm}, + /* instruction VADC__VIM, encoding '0b01000000000000000011000001010111' */ + {32, 0b01000000000000000011000001010111, 0b11111110000000000111000001111111, &this_class::__vadc__vim}, + /* instruction VMADC__VVM, encoding '0b01000100000000000000000001010111' */ + {32, 0b01000100000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vvm}, + /* instruction VMADC__VXM, encoding '0b01000100000000000100000001010111' */ + {32, 0b01000100000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vxm}, + /* instruction VMADC__VIM, encoding '0b01000100000000000011000001010111' */ + {32, 0b01000100000000000011000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vim}, + /* instruction VMADC__VV, encoding '0b01000110000000000000000001010111' */ + {32, 0b01000110000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vv}, + /* instruction VMADC__VX, encoding '0b01000110000000000100000001010111' */ + {32, 0b01000110000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vx}, + /* instruction VMADC__VI, encoding '0b01000110000000000011000001010111' */ + {32, 0b01000110000000000011000001010111, 0b11111110000000000111000001111111, &this_class::__vmadc__vi}, + /* instruction VSBC__VVM, encoding '0b01001000000000000000000001010111' */ + {32, 0b01001000000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vsbc__vvm}, + /* instruction VSBC__VXM, encoding '0b01001000000000000100000001010111' */ + {32, 0b01001000000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vsbc__vxm}, + /* instruction VMSBC__VVM, encoding '0b01001100000000000000000001010111' */ + {32, 0b01001100000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vmsbc__vvm}, + /* instruction VMSBC__VXM, encoding '0b01001100000000000100000001010111' */ + {32, 0b01001100000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vmsbc__vxm}, + /* instruction VMSBC__VV, encoding '0b01001110000000000000000001010111' */ + {32, 0b01001110000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vmsbc__vv}, + /* instruction VMSBC__VX, encoding '0b01001110000000000100000001010111' */ + {32, 0b01001110000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vmsbc__vx}, + /* instruction VAND__VI, encoding '0b00100100000000000011000001010111' */ + {32, 0b00100100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vand__vi}, + /* instruction VAND__VV, encoding '0b00100100000000000000000001010111' */ + {32, 0b00100100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vand__vv}, + /* instruction VAND__VX, encoding '0b00100100000000000100000001010111' */ + {32, 0b00100100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vand__vx}, + /* instruction VOR__VI, encoding '0b00101000000000000011000001010111' */ + {32, 0b00101000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vor__vi}, + /* instruction VOR__VV, encoding '0b00101000000000000000000001010111' */ + {32, 0b00101000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vor__vv}, + /* instruction VOR__VX, encoding '0b00101000000000000100000001010111' */ + {32, 0b00101000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vor__vx}, + /* instruction VXOR__VI, encoding '0b00101100000000000011000001010111' */ + {32, 0b00101100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vxor__vi}, + /* instruction VXOR__VV, encoding '0b00101100000000000000000001010111' */ + {32, 0b00101100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vxor__vv}, + /* instruction VXOR__VX, encoding '0b00101100000000000100000001010111' */ + {32, 0b00101100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vxor__vx}, + /* instruction VSLL__VI, encoding '0b10010100000000000011000001010111' */ + {32, 0b10010100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vsll__vi}, + /* instruction VSLL__VV, encoding '0b10010100000000000000000001010111' */ + {32, 0b10010100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsll__vv}, + /* instruction VSLL__VX, encoding '0b10010100000000000100000001010111' */ + {32, 0b10010100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsll__vx}, + /* instruction VSRL__VI, encoding '0b10100000000000000011000001010111' */ + {32, 0b10100000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vsrl__vi}, + /* instruction VSRL__VV, encoding '0b10100000000000000000000001010111' */ + {32, 0b10100000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsrl__vv}, + /* instruction VSRL__VX, encoding '0b10100000000000000100000001010111' */ + {32, 0b10100000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsrl__vx}, + /* instruction VSRA__VI, encoding '0b10100100000000000011000001010111' */ + {32, 0b10100100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vsra__vi}, + /* instruction VSRA__VV, encoding '0b10100100000000000000000001010111' */ + {32, 0b10100100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsra__vv}, + /* instruction VSRA__VX, encoding '0b10100100000000000100000001010111' */ + {32, 0b10100100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsra__vx}, + /* instruction VNSRL__WI, encoding '0b10110000000000000011000001010111' */ + {32, 0b10110000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vnsrl__wi}, + /* instruction VNSRL__WV, encoding '0b10110000000000000000000001010111' */ + {32, 0b10110000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vnsrl__wv}, + /* instruction VNSRL__WX, encoding '0b10110000000000000100000001010111' */ + {32, 0b10110000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vnsrl__wx}, + /* instruction VNSRA__WI, encoding '0b10110100000000000011000001010111' */ + {32, 0b10110100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vnsra__wi}, + /* instruction VNSRA__WV, encoding '0b10110100000000000000000001010111' */ + {32, 0b10110100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vnsra__wv}, + /* instruction VNSRA__WX, encoding '0b10110100000000000100000001010111' */ + {32, 0b10110100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vnsra__wx}, + /* instruction VMSEQ__VI, encoding '0b01100000000000000011000001010111' */ + {32, 0b01100000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmseq__vi}, + /* instruction VMSEQ__VV, encoding '0b01100000000000000000000001010111' */ + {32, 0b01100000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmseq__vv}, + /* instruction VMSEQ__VX, encoding '0b01100000000000000100000001010111' */ + {32, 0b01100000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmseq__vx}, + /* instruction VMSNE__VI, encoding '0b01100100000000000011000001010111' */ + {32, 0b01100100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmsne__vi}, + /* instruction VMSNE__VV, encoding '0b01100100000000000000000001010111' */ + {32, 0b01100100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmsne__vv}, + /* instruction VMSNE__VX, encoding '0b01100100000000000100000001010111' */ + {32, 0b01100100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsne__vx}, + /* instruction VMSLTU__VV, encoding '0b01101000000000000000000001010111' */ + {32, 0b01101000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmsltu__vv}, + /* instruction VMSLTU__VX, encoding '0b01101000000000000100000001010111' */ + {32, 0b01101000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsltu__vx}, + /* instruction VMSLT__VV, encoding '0b01101100000000000000000001010111' */ + {32, 0b01101100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmslt__vv}, + /* instruction VMSLT__VX, encoding '0b01101100000000000100000001010111' */ + {32, 0b01101100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmslt__vx}, + /* instruction VMSLEU__VI, encoding '0b01110000000000000011000001010111' */ + {32, 0b01110000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmsleu__vi}, + /* instruction VMSLEU__VV, encoding '0b01110000000000000000000001010111' */ + {32, 0b01110000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmsleu__vv}, + /* instruction VMSLEU__VX, encoding '0b01110000000000000100000001010111' */ + {32, 0b01110000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsleu__vx}, + /* instruction VMSLE__VI, encoding '0b01110100000000000011000001010111' */ + {32, 0b01110100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmsle__vi}, + /* instruction VMSLE__VV, encoding '0b01110100000000000000000001010111' */ + {32, 0b01110100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmsle__vv}, + /* instruction VMSLE__VX, encoding '0b01110100000000000100000001010111' */ + {32, 0b01110100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsle__vx}, + /* instruction VMSGTU__VI, encoding '0b01111000000000000011000001010111' */ + {32, 0b01111000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmsgtu__vi}, + /* instruction VMSGTU__VX, encoding '0b01111000000000000100000001010111' */ + {32, 0b01111000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsgtu__vx}, + /* instruction VMSGT__VI, encoding '0b01111100000000000011000001010111' */ + {32, 0b01111100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vmsgt__vi}, + /* instruction VMSGT__VX, encoding '0b01111100000000000100000001010111' */ + {32, 0b01111100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmsgt__vx}, + /* instruction VMINU__VV, encoding '0b00010000000000000000000001010111' */ + {32, 0b00010000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vminu__vv}, + /* instruction VMINU__VX, encoding '0b00010000000000000100000001010111' */ + {32, 0b00010000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vminu__vx}, + /* instruction VMIN__VV, encoding '0b00010100000000000000000001010111' */ + {32, 0b00010100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmin__vv}, + /* instruction VMIN__VX, encoding '0b00010100000000000100000001010111' */ + {32, 0b00010100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmin__vx}, + /* instruction VMAXU__VV, encoding '0b00011000000000000000000001010111' */ + {32, 0b00011000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmaxu__vv}, + /* instruction VMAXU__VX, encoding '0b00011000000000000100000001010111' */ + {32, 0b00011000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmaxu__vx}, + /* instruction VMAX__VV, encoding '0b00011100000000000000000001010111' */ + {32, 0b00011100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vmax__vv}, + /* instruction VMAX__VX, encoding '0b00011100000000000100000001010111' */ + {32, 0b00011100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vmax__vx}, + /* instruction VMUL__VV, encoding '0b10010100000000000010000001010111' */ + {32, 0b10010100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmul__vv}, + /* instruction VMUL__VX, encoding '0b10010100000000000110000001010111' */ + {32, 0b10010100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmul__vx}, + /* instruction VMULH__VV, encoding '0b10011100000000000010000001010111' */ + {32, 0b10011100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmulh__vv}, + /* instruction VMULH__VX, encoding '0b10011100000000000110000001010111' */ + {32, 0b10011100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmulh__vx}, + /* instruction VMULHU__VV, encoding '0b10010000000000000010000001010111' */ + {32, 0b10010000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmulhu__vv}, + /* instruction VMULHU__VX, encoding '0b10010000000000000110000001010111' */ + {32, 0b10010000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmulhu__vx}, + /* instruction VMULHSU__VV, encoding '0b10011000000000000010000001010111' */ + {32, 0b10011000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmulhsu__vv}, + /* instruction VMULHSU__VX, encoding '0b10011000000000000110000001010111' */ + {32, 0b10011000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmulhsu__vx}, + /* instruction VDIVU__VV, encoding '0b10000000000000000010000001010111' */ + {32, 0b10000000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vdivu__vv}, + /* instruction VDIVU__VX, encoding '0b10000000000000000110000001010111' */ + {32, 0b10000000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vdivu__vx}, + /* instruction VDIV__VV, encoding '0b10000100000000000010000001010111' */ + {32, 0b10000100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vdiv__vv}, + /* instruction VDIV__VX, encoding '0b10000100000000000110000001010111' */ + {32, 0b10000100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vdiv__vx}, + /* instruction VREMU__VV, encoding '0b10001000000000000010000001010111' */ + {32, 0b10001000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vremu__vv}, + /* instruction VREMU__VX, encoding '0b10001000000000000110000001010111' */ + {32, 0b10001000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vremu__vx}, + /* instruction VREM__VV, encoding '0b10001100000000000010000001010111' */ + {32, 0b10001100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vrem__vv}, + /* instruction VREM__VX, encoding '0b10001100000000000110000001010111' */ + {32, 0b10001100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vrem__vx}, + /* instruction VWMUL__VV, encoding '0b11101100000000000010000001010111' */ + {32, 0b11101100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmul__vv}, + /* instruction VWMUL__VX, encoding '0b11101100000000000110000001010111' */ + {32, 0b11101100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmul__vx}, + /* instruction VWMULU__VV, encoding '0b11100000000000000010000001010111' */ + {32, 0b11100000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmulu__vv}, + /* instruction VWMULU__VX, encoding '0b11100000000000000110000001010111' */ + {32, 0b11100000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmulu__vx}, + /* instruction VWMULSU__VV, encoding '0b11101000000000000010000001010111' */ + {32, 0b11101000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmulsu__vv}, + /* instruction VWMULSU__VX, encoding '0b11101000000000000110000001010111' */ + {32, 0b11101000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmulsu__vx}, + /* instruction VMACC__VV, encoding '0b10110100000000000010000001010111' */ + {32, 0b10110100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmacc__vv}, + /* instruction VMACC__VX, encoding '0b10110100000000000110000001010111' */ + {32, 0b10110100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmacc__vx}, + /* instruction VNMSAC__VV, encoding '0b10111100000000000010000001010111' */ + {32, 0b10111100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vnmsac__vv}, + /* instruction VNMSAC__VX, encoding '0b10111100000000000110000001010111' */ + {32, 0b10111100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vnmsac__vx}, + /* instruction VMADD__VV, encoding '0b10100100000000000010000001010111' */ + {32, 0b10100100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vmadd__vv}, + /* instruction VMADD__VX, encoding '0b10100100000000000110000001010111' */ + {32, 0b10100100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vmadd__vx}, + /* instruction VNMSUB__VV, encoding '0b10101100000000000010000001010111' */ + {32, 0b10101100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vnmsub__vv}, + /* instruction VNMSUB__VX, encoding '0b10101100000000000110000001010111' */ + {32, 0b10101100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vnmsub__vx}, + /* instruction VWMACCU__VV, encoding '0b11110000000000000010000001010111' */ + {32, 0b11110000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmaccu__vv}, + /* instruction VWMACCU__VX, encoding '0b11110000000000000110000001010111' */ + {32, 0b11110000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmaccu__vx}, + /* instruction VWMACC__VV, encoding '0b11110100000000000010000001010111' */ + {32, 0b11110100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmacc__vv}, + /* instruction VWMACC__VX, encoding '0b11110100000000000110000001010111' */ + {32, 0b11110100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmacc__vx}, + /* instruction VWMACCSU__VV, encoding '0b11111100000000000010000001010111' */ + {32, 0b11111100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vwmaccsu__vv}, + /* instruction VWMACCSU__VX, encoding '0b11111100000000000110000001010111' */ + {32, 0b11111100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmaccsu__vx}, + /* instruction VWMACCUS__VX, encoding '0b11111000000000000110000001010111' */ + {32, 0b11111000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vwmaccus__vx}, + /* instruction VMERGE__VIM, encoding '0b01011100000000000011000001010111' */ + {32, 0b01011100000000000011000001010111, 0b11111110000000000111000001111111, &this_class::__vmerge__vim}, + /* instruction VMERGE__VVM, encoding '0b01011100000000000000000001010111' */ + {32, 0b01011100000000000000000001010111, 0b11111110000000000111000001111111, &this_class::__vmerge__vvm}, + /* instruction VMERGE__VXM, encoding '0b01011100000000000100000001010111' */ + {32, 0b01011100000000000100000001010111, 0b11111110000000000111000001111111, &this_class::__vmerge__vxm}, + /* instruction VMV__V__I, encoding '0b01011110000000000011000001010111' */ + {32, 0b01011110000000000011000001010111, 0b11111111111100000111000001111111, &this_class::__vmv__v__i}, + /* instruction VMV__V__V, encoding '0b01011110000000000000000001010111' */ + {32, 0b01011110000000000000000001010111, 0b11111111111100000111000001111111, &this_class::__vmv__v__v}, + /* instruction VMV__V__X, encoding '0b01011110000000000100000001010111' */ + {32, 0b01011110000000000100000001010111, 0b11111111111100000111000001111111, &this_class::__vmv__v__x}, + /* instruction VSADDU__VI, encoding '0b10000000000000000011000001010111' */ + {32, 0b10000000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vsaddu__vi}, + /* instruction VSADDU__VV, encoding '0b10000000000000000000000001010111' */ + {32, 0b10000000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsaddu__vv}, + /* instruction VSADDU__VX, encoding '0b10000000000000000100000001010111' */ + {32, 0b10000000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsaddu__vx}, + /* instruction VSADD__VI, encoding '0b10000100000000000011000001010111' */ + {32, 0b10000100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vsadd__vi}, + /* instruction VSADD__VV, encoding '0b10000100000000000000000001010111' */ + {32, 0b10000100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsadd__vv}, + /* instruction VSADD__VX, encoding '0b10000100000000000100000001010111' */ + {32, 0b10000100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsadd__vx}, + /* instruction VSSUBU__VV, encoding '0b10001000000000000000000001010111' */ + {32, 0b10001000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vssubu__vv}, + /* instruction VSSUBU__VX, encoding '0b10001000000000000100000001010111' */ + {32, 0b10001000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vssubu__vx}, + /* instruction VSSUB__VV, encoding '0b10001100000000000000000001010111' */ + {32, 0b10001100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vssub__vv}, + /* instruction VSSUB__VX, encoding '0b10001100000000000100000001010111' */ + {32, 0b10001100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vssub__vx}, + /* instruction VAADDU__VV, encoding '0b00100000000000000010000001010111' */ + {32, 0b00100000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vaaddu__vv}, + /* instruction VAADDU__VX, encoding '0b00100000000000000110000001010111' */ + {32, 0b00100000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vaaddu__vx}, + /* instruction VAADD__VV, encoding '0b00100100000000000010000001010111' */ + {32, 0b00100100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vaadd__vv}, + /* instruction VAADD__VX, encoding '0b00100100000000000110000001010111' */ + {32, 0b00100100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vaadd__vx}, + /* instruction VASUBU__VV, encoding '0b00101000000000000010000001010111' */ + {32, 0b00101000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vasubu__vv}, + /* instruction VASUBU__VX, encoding '0b00101000000000000110000001010111' */ + {32, 0b00101000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vasubu__vx}, + /* instruction VASUB__VV, encoding '0b00101100000000000010000001010111' */ + {32, 0b00101100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vasub__vv}, + /* instruction VASUB__VX, encoding '0b00101100000000000110000001010111' */ + {32, 0b00101100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vasub__vx}, + /* instruction VSMUL__VV, encoding '0b10011100000000000000000001010111' */ + {32, 0b10011100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vsmul__vv}, + /* instruction VSMUL__VX, encoding '0b10011100000000000100000001010111' */ + {32, 0b10011100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vsmul__vx}, + /* instruction VSSRL__VI, encoding '0b10101000000000000011000001010111' */ + {32, 0b10101000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vssrl__vi}, + /* instruction VSSRL__VV, encoding '0b10101000000000000000000001010111' */ + {32, 0b10101000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vssrl__vv}, + /* instruction VSSRL__VX, encoding '0b10101000000000000100000001010111' */ + {32, 0b10101000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vssrl__vx}, + /* instruction VSSRA__VI, encoding '0b10101100000000000011000001010111' */ + {32, 0b10101100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vssra__vi}, + /* instruction VSSRA__VV, encoding '0b10101100000000000000000001010111' */ + {32, 0b10101100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vssra__vv}, + /* instruction VSSRA__VX, encoding '0b10101100000000000100000001010111' */ + {32, 0b10101100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vssra__vx}, + /* instruction VNCLIPU__WI, encoding '0b10111000000000000011000001010111' */ + {32, 0b10111000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vnclipu__wi}, + /* instruction VNCLIPU__WV, encoding '0b10111000000000000000000001010111' */ + {32, 0b10111000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vnclipu__wv}, + /* instruction VNCLIPU__WX, encoding '0b10111000000000000100000001010111' */ + {32, 0b10111000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vnclipu__wx}, + /* instruction VNCLIP__WI, encoding '0b10111100000000000011000001010111' */ + {32, 0b10111100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vnclip__wi}, + /* instruction VNCLIP__WV, encoding '0b10111100000000000000000001010111' */ + {32, 0b10111100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vnclip__wv}, + /* instruction VNCLIP__WX, encoding '0b10111100000000000100000001010111' */ + {32, 0b10111100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vnclip__wx}, + /* instruction VREDSUM__VS, encoding '0b00000000000000000010000001010111' */ + {32, 0b00000000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredsum__vs}, + /* instruction VREDMAXU__VS, encoding '0b00011000000000000010000001010111' */ + {32, 0b00011000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredmaxu__vs}, + /* instruction VREDMAX__VS, encoding '0b00011100000000000010000001010111' */ + {32, 0b00011100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredmax__vs}, + /* instruction VREDMINU__VS, encoding '0b00010000000000000010000001010111' */ + {32, 0b00010000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredminu__vs}, + /* instruction VREDMIN__VS, encoding '0b00010100000000000010000001010111' */ + {32, 0b00010100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredmin__vs}, + /* instruction VREDAND__VS, encoding '0b00000100000000000010000001010111' */ + {32, 0b00000100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredand__vs}, + /* instruction VREDOR__VS, encoding '0b00001000000000000010000001010111' */ + {32, 0b00001000000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredor__vs}, + /* instruction VREDXOR__VS, encoding '0b00001100000000000010000001010111' */ + {32, 0b00001100000000000010000001010111, 0b11111100000000000111000001111111, &this_class::__vredxor__vs}, + /* instruction VWREDSUMU__VS, encoding '0b11000000000000000000000001010111' */ + {32, 0b11000000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vwredsumu__vs}, + /* instruction VWREDSUM__VS, encoding '0b11000100000000000000000001010111' */ + {32, 0b11000100000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vwredsum__vs}, + /* instruction VFREDOSUM__VS, encoding '0b00001100000000000001000001010111' */ + {32, 0b00001100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfredosum__vs}, + /* instruction VFREDUSUM__VS, encoding '0b00000100000000000001000001010111' */ + {32, 0b00000100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfredusum__vs}, + /* instruction VFREDMAX__VS, encoding '0b00011100000000000001000001010111' */ + {32, 0b00011100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfredmax__vs}, + /* instruction VFREDMIN__VS, encoding '0b00010100000000000001000001010111' */ + {32, 0b00010100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfredmin__vs}, + /* instruction VFWREDOSUM__VS, encoding '0b11001100000000000001000001010111' */ + {32, 0b11001100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwredosum__vs}, + /* instruction VFWREDUSUM__VS, encoding '0b11000100000000000001000001010111' */ + {32, 0b11000100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwredusum__vs}, + /* instruction VMAND__MM, encoding '0b01100110000000000010000001010111' */ + {32, 0b01100110000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmand__mm}, + /* instruction VMNAND__MM, encoding '0b01110110000000000010000001010111' */ + {32, 0b01110110000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmnand__mm}, + /* instruction VMANDN__MM, encoding '0b01100010000000000010000001010111' */ + {32, 0b01100010000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmandn__mm}, + /* instruction VMXOR__MM, encoding '0b01101110000000000010000001010111' */ + {32, 0b01101110000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmxor__mm}, + /* instruction VMOR__MM, encoding '0b01101010000000000010000001010111' */ + {32, 0b01101010000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmor__mm}, + /* instruction VMNOR__MM, encoding '0b01111010000000000010000001010111' */ + {32, 0b01111010000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmnor__mm}, + /* instruction VMORN__MM, encoding '0b01110010000000000010000001010111' */ + {32, 0b01110010000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmorn__mm}, + /* instruction VMXNOR__MM, encoding '0b01111110000000000010000001010111' */ + {32, 0b01111110000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vmxnor__mm}, + /* instruction VCPOP__M, encoding '0b01000000000010000010000001010111' */ + {32, 0b01000000000010000010000001010111, 0b11111100000011111111000001111111, &this_class::__vcpop__m}, + /* instruction VFIRST__M, encoding '0b01000000000010001010000001010111' */ + {32, 0b01000000000010001010000001010111, 0b11111100000011111111000001111111, &this_class::__vfirst__m}, + /* instruction VMSBF__M, encoding '0b01010000000000001010000001010111' */ + {32, 0b01010000000000001010000001010111, 0b11111100000011111111000001111111, &this_class::__vmsbf__m}, + /* instruction VMSIF__M, encoding '0b01010000000000011010000001010111' */ + {32, 0b01010000000000011010000001010111, 0b11111100000011111111000001111111, &this_class::__vmsif__m}, + /* instruction VMSOF__M, encoding '0b01010000000000010010000001010111' */ + {32, 0b01010000000000010010000001010111, 0b11111100000011111111000001111111, &this_class::__vmsof__m}, + /* instruction VIOTA__M, encoding '0b01010000000010000010000001010111' */ + {32, 0b01010000000010000010000001010111, 0b11111100000011111111000001111111, &this_class::__viota__m}, + /* instruction VID__V, encoding '0b01010000000010001010000001010111' */ + {32, 0b01010000000010001010000001010111, 0b11111101111111111111000001111111, &this_class::__vid__v}, + /* instruction VMV__S__X, encoding '0b01000010000000000110000001010111' */ + {32, 0b01000010000000000110000001010111, 0b11111111111100000111000001111111, &this_class::__vmv__s__x}, + /* instruction VMV__X__S, encoding '0b01000010000000000010000001010111' */ + {32, 0b01000010000000000010000001010111, 0b11111110000011111111000001111111, &this_class::__vmv__x__s}, + /* instruction VSLIDEUP__VI, encoding '0b00111000000000000011000001010111' */ + {32, 0b00111000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vslideup__vi}, + /* instruction VSLIDEUP__VX, encoding '0b00111000000000000100000001010111' */ + {32, 0b00111000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vslideup__vx}, + /* instruction VSLIDEDOWN__VI, encoding '0b00111100000000000011000001010111' */ + {32, 0b00111100000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vslidedown__vi}, + /* instruction VSLIDEDOWN__VX, encoding '0b00111100000000000100000001010111' */ + {32, 0b00111100000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vslidedown__vx}, + /* instruction VSLIDE1UP__VX, encoding '0b00111000000000000110000001010111' */ + {32, 0b00111000000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vslide1up__vx}, + /* instruction VSLIDE1DOWN__VX, encoding '0b00111100000000000110000001010111' */ + {32, 0b00111100000000000110000001010111, 0b11111100000000000111000001111111, &this_class::__vslide1down__vx}, + /* instruction VRGATHER__VI, encoding '0b00110000000000000011000001010111' */ + {32, 0b00110000000000000011000001010111, 0b11111100000000000111000001111111, &this_class::__vrgather__vi}, + /* instruction VRGATHER__VV, encoding '0b00110000000000000000000001010111' */ + {32, 0b00110000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vrgather__vv}, + /* instruction VRGATHER__VX, encoding '0b00110000000000000100000001010111' */ + {32, 0b00110000000000000100000001010111, 0b11111100000000000111000001111111, &this_class::__vrgather__vx}, + /* instruction VRGATHEREI16__VV, encoding '0b00111000000000000000000001010111' */ + {32, 0b00111000000000000000000001010111, 0b11111100000000000111000001111111, &this_class::__vrgatherei16__vv}, + /* instruction VCOMPRESS__VM, encoding '0b01011110000000000010000001010111' */ + {32, 0b01011110000000000010000001010111, 0b11111110000000000111000001111111, &this_class::__vcompress__vm}, + /* instruction VMV1R__V, encoding '0b10011110000000000011000001010111' */ + {32, 0b10011110000000000011000001010111, 0b11111110000011111111000001111111, &this_class::__vmv1r__v}, + /* instruction VMV2R__V, encoding '0b10011110000000001011000001010111' */ + {32, 0b10011110000000001011000001010111, 0b11111110000011111111000001111111, &this_class::__vmv2r__v}, + /* instruction VMV4R__V, encoding '0b10011110000000011011000001010111' */ + {32, 0b10011110000000011011000001010111, 0b11111110000011111111000001111111, &this_class::__vmv4r__v}, + /* instruction VMV8R__V, encoding '0b10011110000000111011000001010111' */ + {32, 0b10011110000000111011000001010111, 0b11111110000011111111000001111111, &this_class::__vmv8r__v}, + /* instruction VFMV__S__F, encoding '0b01000010000000000101000001010111' */ + {32, 0b01000010000000000101000001010111, 0b11111111111100000111000001111111, &this_class::__vfmv__s__f}, + /* instruction VFMV__F__S, encoding '0b01000010000000000001000001010111' */ + {32, 0b01000010000000000001000001010111, 0b11111110000011111111000001111111, &this_class::__vfmv__f__s}, + /* instruction VFSLIDE1UP__VF, encoding '0b00111000000000000101000001010111' */ + {32, 0b00111000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfslide1up__vf}, + /* instruction VFSLIDE1DOWN__VF, encoding '0b00111100000000000101000001010111' */ + {32, 0b00111100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfslide1down__vf}, + /* instruction VFADD__VF, encoding '0b00000000000000000101000001010111' */ + {32, 0b00000000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfadd__vf}, + /* instruction VFADD__VV, encoding '0b00000000000000000001000001010111' */ + {32, 0b00000000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfadd__vv}, + /* instruction VFSUB__VF, encoding '0b00001000000000000101000001010111' */ + {32, 0b00001000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfsub__vf}, + /* instruction VFSUB__VV, encoding '0b00001000000000000001000001010111' */ + {32, 0b00001000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfsub__vv}, + /* instruction VFRSUB__VF, encoding '0b10011100000000000101000001010111' */ + {32, 0b10011100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfrsub__vf}, + /* instruction VFWADD__VF, encoding '0b11000000000000000101000001010111' */ + {32, 0b11000000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwadd__vf}, + /* instruction VFWADD__VV, encoding '0b11000000000000000001000001010111' */ + {32, 0b11000000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwadd__vv}, + /* instruction VFWSUB__VF, encoding '0b11001000000000000101000001010111' */ + {32, 0b11001000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwsub__vf}, + /* instruction VFWSUB__VV, encoding '0b11001000000000000001000001010111' */ + {32, 0b11001000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwsub__vv}, + /* instruction VFWADD__WF, encoding '0b11010000000000000101000001010111' */ + {32, 0b11010000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwadd__wf}, + /* instruction VFWADD__WV, encoding '0b11010000000000000001000001010111' */ + {32, 0b11010000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwadd__wv}, + /* instruction VFWSUB__WF, encoding '0b11011000000000000101000001010111' */ + {32, 0b11011000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwsub__wf}, + /* instruction VFWSUB__WV, encoding '0b11011000000000000001000001010111' */ + {32, 0b11011000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwsub__wv}, + /* instruction VFMUL__VF, encoding '0b10010000000000000101000001010111' */ + {32, 0b10010000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmul__vf}, + /* instruction VFMUL__VV, encoding '0b10010000000000000001000001010111' */ + {32, 0b10010000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmul__vv}, + /* instruction VFDIV__VF, encoding '0b10000000000000000101000001010111' */ + {32, 0b10000000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfdiv__vf}, + /* instruction VFDIV__VV, encoding '0b10000000000000000001000001010111' */ + {32, 0b10000000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfdiv__vv}, + /* instruction VFRDIV__VF, encoding '0b10000100000000000101000001010111' */ + {32, 0b10000100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfrdiv__vf}, + /* instruction VFWMUL__VF, encoding '0b11100000000000000101000001010111' */ + {32, 0b11100000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmul__vf}, + /* instruction VFWMUL__VV, encoding '0b11100000000000000001000001010111' */ + {32, 0b11100000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmul__vv}, + /* instruction VFMACC__VF, encoding '0b10110000000000000101000001010111' */ + {32, 0b10110000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmacc__vf}, + /* instruction VFMACC__VV, encoding '0b10110000000000000001000001010111' */ + {32, 0b10110000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmacc__vv}, + /* instruction VFNMACC__VF, encoding '0b10110100000000000101000001010111' */ + {32, 0b10110100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmacc__vf}, + /* instruction VFNMACC__VV, encoding '0b10110100000000000001000001010111' */ + {32, 0b10110100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmacc__vv}, + /* instruction VFMSAC__VF, encoding '0b10111000000000000101000001010111' */ + {32, 0b10111000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmsac__vf}, + /* instruction VFMSAC__VV, encoding '0b10111000000000000001000001010111' */ + {32, 0b10111000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmsac__vv}, + /* instruction VFNMSAC__VF, encoding '0b10111100000000000101000001010111' */ + {32, 0b10111100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmsac__vf}, + /* instruction VFNMSAC__VV, encoding '0b10111100000000000001000001010111' */ + {32, 0b10111100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmsac__vv}, + /* instruction VFMADD__VF, encoding '0b10100000000000000101000001010111' */ + {32, 0b10100000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmadd__vf}, + /* instruction VFMADD__VV, encoding '0b10100000000000000001000001010111' */ + {32, 0b10100000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmadd__vv}, + /* instruction VFNMADD__VF, encoding '0b10100100000000000101000001010111' */ + {32, 0b10100100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmadd__vf}, + /* instruction VFNMADD__VV, encoding '0b10100100000000000001000001010111' */ + {32, 0b10100100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmadd__vv}, + /* instruction VFMSUB__VF, encoding '0b10101000000000000101000001010111' */ + {32, 0b10101000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmsub__vf}, + /* instruction VFMSUB__VV, encoding '0b10101000000000000001000001010111' */ + {32, 0b10101000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmsub__vv}, + /* instruction VFNMSUB__VF, encoding '0b10101100000000000101000001010111' */ + {32, 0b10101100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmsub__vf}, + /* instruction VFNMSUB__VV, encoding '0b10101100000000000001000001010111' */ + {32, 0b10101100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfnmsub__vv}, + /* instruction VFWMACC__VF, encoding '0b11110000000000000101000001010111' */ + {32, 0b11110000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmacc__vf}, + /* instruction VFWMACC__VV, encoding '0b11110000000000000001000001010111' */ + {32, 0b11110000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmacc__vv}, + /* instruction VFWNMACC__VF, encoding '0b11110100000000000101000001010111' */ + {32, 0b11110100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwnmacc__vf}, + /* instruction VFWNMACC__VV, encoding '0b11110100000000000001000001010111' */ + {32, 0b11110100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwnmacc__vv}, + /* instruction VFWMSAC__VF, encoding '0b11111000000000000101000001010111' */ + {32, 0b11111000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmsac__vf}, + /* instruction VFWMSAC__VV, encoding '0b11111000000000000001000001010111' */ + {32, 0b11111000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwmsac__vv}, + /* instruction VFWNMSAC__VF, encoding '0b11111100000000000101000001010111' */ + {32, 0b11111100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfwnmsac__vf}, + /* instruction VFWNMSAC__VV, encoding '0b11111100000000000001000001010111' */ + {32, 0b11111100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfwnmsac__vv}, + /* instruction VFSQRT__V, encoding '0b01001100000000000001000001010111' */ + {32, 0b01001100000000000001000001010111, 0b11111100000011111111000001111111, &this_class::__vfsqrt__v}, + /* instruction VFRSQRT7__V, encoding '0b01001100000000100001000001010111' */ + {32, 0b01001100000000100001000001010111, 0b11111100000011111111000001111111, &this_class::__vfrsqrt7__v}, + /* instruction VFREC7__V, encoding '0b01001100000000101001000001010111' */ + {32, 0b01001100000000101001000001010111, 0b11111100000011111111000001111111, &this_class::__vfrec7__v}, + /* instruction VFMIN__VF, encoding '0b00010000000000000101000001010111' */ + {32, 0b00010000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmin__vf}, + /* instruction VFMIN__VV, encoding '0b00010000000000000001000001010111' */ + {32, 0b00010000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmin__vv}, + /* instruction VFMAX__VF, encoding '0b00011000000000000101000001010111' */ + {32, 0b00011000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfmax__vf}, + /* instruction VFMAX__VV, encoding '0b00011000000000000001000001010111' */ + {32, 0b00011000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfmax__vv}, + /* instruction VFSGNJ__VF, encoding '0b00100000000000000101000001010111' */ + {32, 0b00100000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnj__vf}, + /* instruction VFSGNJ__VV, encoding '0b00100000000000000001000001010111' */ + {32, 0b00100000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnj__vv}, + /* instruction VFSGNJN__VF, encoding '0b00100100000000000101000001010111' */ + {32, 0b00100100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnjn__vf}, + /* instruction VFSGNJN__VV, encoding '0b00100100000000000001000001010111' */ + {32, 0b00100100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnjn__vv}, + /* instruction VFSGNJX__VF, encoding '0b00101000000000000101000001010111' */ + {32, 0b00101000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnjx__vf}, + /* instruction VFSGNJX__VV, encoding '0b00101000000000000001000001010111' */ + {32, 0b00101000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vfsgnjx__vv}, + /* instruction VMFEQ__VF, encoding '0b01100000000000000101000001010111' */ + {32, 0b01100000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmfeq__vf}, + /* instruction VMFEQ__VV, encoding '0b01100000000000000001000001010111' */ + {32, 0b01100000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vmfeq__vv}, + /* instruction VMFNE__VF, encoding '0b01110000000000000101000001010111' */ + {32, 0b01110000000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmfne__vf}, + /* instruction VMFNE__VV, encoding '0b01110000000000000001000001010111' */ + {32, 0b01110000000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vmfne__vv}, + /* instruction VMFLT__VF, encoding '0b01101100000000000101000001010111' */ + {32, 0b01101100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmflt__vf}, + /* instruction VMFLT__VV, encoding '0b01101100000000000001000001010111' */ + {32, 0b01101100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vmflt__vv}, + /* instruction VMFLE__VF, encoding '0b01100100000000000101000001010111' */ + {32, 0b01100100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmfle__vf}, + /* instruction VMFLE__VV, encoding '0b01100100000000000001000001010111' */ + {32, 0b01100100000000000001000001010111, 0b11111100000000000111000001111111, &this_class::__vmfle__vv}, + /* instruction VMFGT__VF, encoding '0b01110100000000000101000001010111' */ + {32, 0b01110100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmfgt__vf}, + /* instruction VMFGE__VF, encoding '0b01111100000000000101000001010111' */ + {32, 0b01111100000000000101000001010111, 0b11111100000000000111000001111111, &this_class::__vmfge__vf}, + /* instruction VFCLASS__V, encoding '0b01001100000010000001000001010111' */ + {32, 0b01001100000010000001000001010111, 0b11111100000011111111000001111111, &this_class::__vfclass__v}, + /* instruction VFMERGE__VFM, encoding '0b01011100000000000101000001010111' */ + {32, 0b01011100000000000101000001010111, 0b11111110000000000111000001111111, &this_class::__vfmerge__vfm}, + /* instruction VFMV__V__F, encoding '0b01011110000000000101000001010111' */ + {32, 0b01011110000000000101000001010111, 0b11111111111100000111000001111111, &this_class::__vfmv__v__f}, + /* instruction VFCVT__XU__F__V, encoding '0b01001000000000000001000001010111' */ + {32, 0b01001000000000000001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__xu__f__v}, + /* instruction VFCVT__X__F__V, encoding '0b01001000000000001001000001010111' */ + {32, 0b01001000000000001001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__x__f__v}, + /* instruction VFCVT__RTZ__XU__F__V, encoding '0b01001000000000110001000001010111' */ + {32, 0b01001000000000110001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__rtz__xu__f__v}, + /* instruction VFCVT__RTZ__X__F__V, encoding '0b01001000000000111001000001010111' */ + {32, 0b01001000000000111001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__rtz__x__f__v}, + /* instruction VFCVT__F__XU__V, encoding '0b01001000000000010001000001010111' */ + {32, 0b01001000000000010001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__f__xu__v}, + /* instruction VFCVT__F__X__V, encoding '0b01001000000000011001000001010111' */ + {32, 0b01001000000000011001000001010111, 0b11111100000011111111000001111111, &this_class::__vfcvt__f__x__v}, + /* instruction VFWCVT__XU__F__V, encoding '0b01001000000001000001000001010111' */ + {32, 0b01001000000001000001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__xu__f__v}, + /* instruction VFWCVT__X__F__V, encoding '0b01001000000001001001000001010111' */ + {32, 0b01001000000001001001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__x__f__v}, + /* instruction VFWCVT__RTZ__XU__F__V, encoding '0b01001000000001110001000001010111' */ + {32, 0b01001000000001110001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__rtz__xu__f__v}, + /* instruction VFWCVT__RTZ__X__F__V, encoding '0b01001000000001111001000001010111' */ + {32, 0b01001000000001111001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__rtz__x__f__v}, + /* instruction VFWCVT__F__XU__V, encoding '0b01001000000001010001000001010111' */ + {32, 0b01001000000001010001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__f__xu__v}, + /* instruction VFWCVT__F__X__V, encoding '0b01001000000001011001000001010111' */ + {32, 0b01001000000001011001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__f__x__v}, + /* instruction VFWCVT__F__F__V, encoding '0b01001000000001100001000001010111' */ + {32, 0b01001000000001100001000001010111, 0b11111100000011111111000001111111, &this_class::__vfwcvt__f__f__v}, + /* instruction VFNCVT__X__F__W, encoding '0b01001000000010001001000001010111' */ + {32, 0b01001000000010001001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__x__f__w}, + /* instruction VFNCVT__XU__F__W, encoding '0b01001000000010000001000001010111' */ + {32, 0b01001000000010000001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__xu__f__w}, + /* instruction VFNCVT__RTZ__XU__F__W, encoding '0b01001000000010110001000001010111' */ + {32, 0b01001000000010110001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__rtz__xu__f__w}, + /* instruction VFNCVT__RTZ__X__F__W, encoding '0b01001000000010111001000001010111' */ + {32, 0b01001000000010111001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__rtz__x__f__w}, + /* instruction VFNCVT__F__XU__W, encoding '0b01001000000010010001000001010111' */ + {32, 0b01001000000010010001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__f__xu__w}, + /* instruction VFNCVT__F__X__W, encoding '0b01001000000010011001000001010111' */ + {32, 0b01001000000010011001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__f__x__w}, + /* instruction VFNCVT__F__F__W, encoding '0b01001000000010100001000001010111' */ + {32, 0b01001000000010100001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__f__f__w}, + /* instruction VFNCVT__ROD__F__F__W, encoding '0b01001000000010101001000001010111' */ + {32, 0b01001000000010101001000001010111, 0b11111100000011111111000001111111, &this_class::__vfncvt__rod__f__f__w}, + }}; + + //needs to be declared after instr_descr + decoder instr_decoder; + + /* instruction definitions */ + /* instruction 0: LUI */ + continuation_e __lui(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LUI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 0); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)((int32_t)imm)); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 0); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 1: AUIPC */ + continuation_e __auipc(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AUIPC_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 1); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)(PC+(int32_t)imm)); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 1); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 2: JAL */ + continuation_e __jal(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("JAL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 2); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto new_pc = (uint64_t)(PC+(int32_t)sext<21>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)(PC+4)); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 2); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 3: JALR */ + continuation_e __jalr(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("JALR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 3); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto addr_mask = (uint64_t)- 2; + auto new_pc = gen_ext(cc, + (gen_operation(cc, band, (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), addr_mask)), 64, true); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, urem, new_pc, static_cast(traits::INSTR_ALIGNMENT)); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)(PC+4)); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(UNKNOWN_JUMP)); + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 3); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 4: BEQ */ + continuation_e __beq(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BEQ_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 4); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, eq, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint64_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 4); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 5: BNE */ + continuation_e __bne(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BNE_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 5); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint64_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 5); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 6: BLT */ + continuation_e __blt(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BLT_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 6); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, lt, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, false)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint64_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 6); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 7: BGE */ + continuation_e __bge(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BGE_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 7); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gte, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, false)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint64_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 7); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 8: BLTU */ + continuation_e __bltu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BLTU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 8); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ltu, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint64_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 8); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 9: BGEU */ + continuation_e __bgeu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("BGEU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 9); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gteu, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto new_pc = (uint64_t)(PC+(int16_t)sext<13>(imm)); + if(new_pc%static_cast(traits::INSTR_ALIGNMENT)){ + gen_set_tval(jh, new_pc); + gen_raise(jh, 0, 0); + } + else { + auto PC_val_v = new_pc; + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 9); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 10: LB */ + continuation_e __lb(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LB_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 10); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto load_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, load_address, 1), 8, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 10); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 11: LH */ + continuation_e __lh(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LH_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 11); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto load_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, load_address, 2), 16, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 11); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 12: LW */ + continuation_e __lw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 12); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto load_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, load_address, 4), 32, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 12); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 13: LBU */ + continuation_e __lbu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LBU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 13); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto load_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + auto res = gen_read_mem(jh, traits::MEM, load_address, 1); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 13); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 14: LHU */ + continuation_e __lhu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LHU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 14); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto load_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + auto res = gen_read_mem(jh, traits::MEM, load_address, 2); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 14); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 15: SB */ + continuation_e __sb(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SB_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 15); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto store_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + gen_write_mem(jh, traits::MEM, store_address, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 8, false), 1); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 15); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 16: SH */ + continuation_e __sh(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SH_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 16); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto store_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + gen_write_mem(jh, traits::MEM, store_address, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 16, false), 2); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 16); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 17: SW */ + continuation_e __sw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 17); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto store_address = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + gen_write_mem(jh, traits::MEM, store_address, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 17); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 18: ADDI */ + continuation_e __addi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ADDI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 18); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 18); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 19: SLTI */ + continuation_e __slti(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLTI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 19); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto label_then1 = cc.newLabel(); + auto label_merge1 = cc.newLabel(); + auto tmp_reg1 = get_reg_Gp(cc, 8, false); + cmp(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, true), (int16_t)sext<12>(imm)); + cc.jl(label_then1); + mov(cc, tmp_reg1,0); + cc.jmp(label_merge1); + cc.bind(label_then1); + mov(cc, tmp_reg1, 1); + cc.bind(label_merge1); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg1 + , 64, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 19); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 20: SLTIU */ + continuation_e __sltiu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLTIU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 20); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto label_then2 = cc.newLabel(); + auto label_merge2 = cc.newLabel(); + auto tmp_reg2 = get_reg_Gp(cc, 8, false); + cmp(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (uint64_t)((int16_t)sext<12>(imm))); + cc.jb(label_then2); + mov(cc, tmp_reg2,0); + cc.jmp(label_merge2); + cc.bind(label_then2); + mov(cc, tmp_reg2, 1); + cc.bind(label_merge2); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg2 + , 64, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 20); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 21: XORI */ + continuation_e __xori(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("XORI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 21); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, bxor, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (uint64_t)((int16_t)sext<12>(imm)))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 21); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 22: ORI */ + continuation_e __ori(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ORI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 22); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, bor, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (uint64_t)((int16_t)sext<12>(imm)))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 22); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 23: ANDI */ + continuation_e __andi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ANDI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 23); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (uint64_t)((int16_t)sext<12>(imm)))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 23); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 24: SLLI */ + continuation_e __slli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 24); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, shl, load_reg_from_mem_Gp(jh, traits::X0 + rs1), shamt)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 24); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 25: SRLI */ + continuation_e __srli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 25); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, shr, load_reg_from_mem_Gp(jh, traits::X0 + rs1), shamt)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 25); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 26: SRAI */ + continuation_e __srai(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRAI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 26); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sar, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false)), shamt)), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 26); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 27: ADD */ + continuation_e __add(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ADD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 27); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))), 64, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 27); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 28: SUB */ + continuation_e __sub(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SUB_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 28); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sub, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 28); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 29: SLL */ + continuation_e __sll(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 29); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, shl, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1))))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 29); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 30: SLT */ + continuation_e __slt(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLT_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 30); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto label_then3 = cc.newLabel(); + auto label_merge3 = cc.newLabel(); + auto tmp_reg3 = get_reg_Gp(cc, 8, false); + cmp(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, true), gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true)); + cc.jl(label_then3); + mov(cc, tmp_reg3,0); + cc.jmp(label_merge3); + cc.bind(label_then3); + mov(cc, tmp_reg3, 1); + cc.bind(label_merge3); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg3 + , 64, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 30); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 31: SLTU */ + continuation_e __sltu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLTU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 31); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto label_then4 = cc.newLabel(); + auto label_merge4 = cc.newLabel(); + auto tmp_reg4 = get_reg_Gp(cc, 8, false); + cmp(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cc.jb(label_then4); + mov(cc, tmp_reg4,0); + cc.jmp(label_merge4); + cc.bind(label_then4); + mov(cc, tmp_reg4, 1); + cc.bind(label_merge4); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg4 + , 64, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 31); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 32: XOR */ + continuation_e __xor(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("XOR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 32); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, bxor, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 32); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 33: SRL */ + continuation_e __srl(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 33); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, shr, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1))))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 33); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 34: SRA */ + continuation_e __sra(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRA_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 34); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sar, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, true), (gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1))))), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 34); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 35: OR */ + continuation_e __or(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("OR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 35); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, bor, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 35); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 36: AND */ + continuation_e __and(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AND_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 36); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 36); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 37: FENCE */ + continuation_e __fence(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + uint8_t fm = ((bit_sub<28,4>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FENCE_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 37); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_write_mem(jh, traits::FENCE, static_cast(traits::fence), (uint8_t)pred<<4|succ, 8); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 37); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 38: ECALL */ + continuation_e __ecall(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "ecall"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ECALL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 38); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + gen_raise(jh, 0, 11); + auto returnValue = TRAP; + + gen_sync(jh, POST_SYNC, 38); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 39: EBREAK */ + continuation_e __ebreak(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "ebreak"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("EBREAK_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 39); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + gen_raise(jh, 0, 3); + auto returnValue = TRAP; + + gen_sync(jh, POST_SYNC, 39); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 40: MRET */ + continuation_e __mret(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "mret"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MRET_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 40); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + gen_leave(jh, 3); + auto returnValue = TRAP; + + gen_sync(jh, POST_SYNC, 40); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 41: WFI */ + continuation_e __wfi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "wfi"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("WFI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 41); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_wait_5; + cc.invoke(&call_wait_5, &wait, FuncSignature::build()); + setArg(call_wait_5, 0, 1); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 41); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 42: LWU */ + continuation_e __lwu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lwu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LWU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 42); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 42); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 43: LD */ + continuation_e __ld(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "ld"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 43); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 43); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 44: SD */ + continuation_e __sd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sd"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 44); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, false), 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 44); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 45: ADDIW */ + continuation_e __addiw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addiw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ADDIW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 45); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto res = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 45); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 46: SLLIW */ + continuation_e __slliw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slliw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLLIW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 46); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto sh_val = gen_operation(cc, shl, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false)), shamt); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + gen_ext(cc, sh_val, 32, true), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 46); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 47: SRLIW */ + continuation_e __srliw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srliw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRLIW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 47); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto sh_val = gen_operation(cc, shr, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false)), shamt); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + gen_ext(cc, sh_val, 32, true), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 47); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 48: SRAIW */ + continuation_e __sraiw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "sraiw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRAIW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 48); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto sh_val = gen_operation(cc, sar, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false)), shamt); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + sh_val, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 48); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 49: ADDW */ + continuation_e __addw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "addw"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("ADDW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 49); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto res = gen_ext(cc, + (gen_operation(cc, add, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false))), 32, true); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 49); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 50: SUBW */ + continuation_e __subw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "subw"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SUBW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 50); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto res = gen_ext(cc, + (gen_operation(cc, sub, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false))), 32, true); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 50); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 51: SLLW */ + continuation_e __sllw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sllw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SLLW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 51); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto count = gen_operation(cc, band, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), 31); + auto sh_val = gen_operation(cc, shl, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false)), count); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + gen_ext(cc, sh_val, 32, true), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 51); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 52: SRLW */ + continuation_e __srlw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srlw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRLW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 52); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto count = gen_operation(cc, band, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), 31); + auto sh_val = gen_operation(cc, shr, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false)), count); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + gen_ext(cc, sh_val, 32, true), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 52); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 53: SRAW */ + continuation_e __sraw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sraw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRAW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 53); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto count = gen_operation(cc, band, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), 31); + auto sh_val = gen_operation(cc, sar, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false)), count); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + sh_val, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 53); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 54: CSRRW */ + continuation_e __csrrw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 54); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrs1 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + if(rd!=0){ + auto xrd = gen_read_mem(jh, traits::CSR, csr, 8); + gen_write_mem(jh, traits::CSR, csr, xrs1, 8); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + else { + gen_write_mem(jh, traits::CSR, csr, xrs1, 8); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 54); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 55: CSRRS */ + continuation_e __csrrs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 55); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrd = gen_read_mem(jh, traits::CSR, csr, 8); + auto xrs1 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + if(rs1!=0){ + gen_write_mem(jh, traits::CSR, csr, gen_operation(cc, bor, xrd, xrs1), 8); + } + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 55); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 56: CSRRC */ + continuation_e __csrrc(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRC_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 56); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrd = gen_read_mem(jh, traits::CSR, csr, 8); + auto xrs1 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + if(rs1!=0){ + gen_write_mem(jh, traits::CSR, csr, gen_operation(cc, band, xrd, gen_operation(cc, bnot, xrs1)), 8); + } + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 56); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 57: CSRRWI */ + continuation_e __csrrwi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRWI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 57); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrd = gen_read_mem(jh, traits::CSR, csr, 8); + gen_write_mem(jh, traits::CSR, csr, (uint64_t)zimm, 8); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 57); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 58: CSRRSI */ + continuation_e __csrrsi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRSI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 58); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrd = gen_read_mem(jh, traits::CSR, csr, 8); + if(zimm!=0){ + gen_write_mem(jh, traits::CSR, csr, gen_operation(cc, bor, xrd, (uint64_t)zimm), 8); + } + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 58); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 59: CSRRCI */ + continuation_e __csrrci(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("CSRRCI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 59); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto xrd = gen_read_mem(jh, traits::CSR, csr, 8); + if(zimm!=0){ + gen_write_mem(jh, traits::CSR, csr, gen_operation(cc, band, xrd, ~ ((uint64_t)zimm)), 8); + } + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + xrd); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 59); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 60: FENCE_I */ + continuation_e __fence_i(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FENCE_I_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 60); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_write_mem(jh, traits::FENCE, static_cast(traits::fencei), imm, 8); + auto returnValue = FLUSH; + + gen_sync(jh, POST_SYNC, 60); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 61: MUL */ + continuation_e __mul(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MUL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 61); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto res = gen_operation(cc, smul, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, true), gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 61); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 62: MULH */ + continuation_e __mulh(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MULH_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 62); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto res = gen_operation(cc, smul, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, true), gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sar, res, static_cast(traits::XLEN))), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 62); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 63: MULHSU */ + continuation_e __mulhsu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MULHSU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 63); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto res = gen_operation(cc, sumul, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, true), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sar, res, static_cast(traits::XLEN))), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 63); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 64: MULHU */ + continuation_e __mulhu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MULHU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 64); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto res = gen_operation(cc, umul, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, shr, res, static_cast(traits::XLEN))), 64, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 64); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 65: DIV */ + continuation_e __div(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("DIV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 65); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto dividend = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, true); + auto divisor = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + if(rd!=0){ + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, divisor, 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + auto MMIN = ((uint64_t)1)<<(static_cast(traits::XLEN)-1); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, land, gen_operation(cc, eq, load_reg_from_mem_Gp(jh, traits::X0 + rs1), MMIN), gen_operation(cc, eq, divisor, - 1)); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, MMIN); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sdiv, dividend, divisor)), 64, true)); + } + cc.bind(label_merge); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)- 1); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 65); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 66: DIVU */ + continuation_e __divu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("DIVU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 66); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, udiv, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)- 1); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 66); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 67: REM */ + continuation_e __rem(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("REM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 67); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + auto MMIN = (uint64_t)1<<(static_cast(traits::XLEN)-1); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, land, gen_operation(cc, eq, load_reg_from_mem_Gp(jh, traits::X0 + rs1), MMIN), gen_operation(cc, eq, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, false), - 1)); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, 0); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, (gen_operation(cc, srem, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, true), gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true))), 64, false)); + } + } + cc.bind(label_merge); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem_Gp(jh, traits::X0 + rs1)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 67); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 68: REMU */ + continuation_e __remu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("REMU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 68); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_operation(cc, urem, load_reg_from_mem_Gp(jh, traits::X0 + rs1), load_reg_from_mem_Gp(jh, traits::X0 + rs2))); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem_Gp(jh, traits::X0 + rs1)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 68); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 69: MULW */ + continuation_e __mulw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("MULW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 69); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto resw = gen_ext(cc, + (gen_operation(cc, smul, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false))), 32, true); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + resw, 64, true), 64, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 69); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 70: DIVW */ + continuation_e __divw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("DIVW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 70); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto dividend = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto divisor = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, divisor, 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + auto MMIN = (int32_t)1<<31; + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, land, gen_operation(cc, eq, dividend, MMIN), gen_operation(cc, eq, divisor, - 1)); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)- 1<<31); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, sdiv, dividend, divisor)), 64, true)); + } + } + cc.bind(label_merge); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)- 1); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 70); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 71: DIVUW */ + continuation_e __divuw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("DIVUW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 71); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto divisor = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, divisor, 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + auto res = gen_ext(cc, + (gen_operation(cc, udiv, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), divisor)), 32, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + res, 64, true), 64, false)); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)- 1); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 71); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 72: REMW */ + continuation_e __remw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("REMW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 72); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)), 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + auto SMIN = (int32_t)1<<31; + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, land, gen_operation(cc, eq, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), SMIN), gen_operation(cc, eq, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), - 1)); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, 0); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, srem, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false))), 64, true)); + } + } + cc.bind(label_merge); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false)), 64, true)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 72); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 73: REMUW */ + continuation_e __remuw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("REMUW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 73); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto divisor = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, divisor, 0); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + auto res = gen_ext(cc, + (gen_operation(cc, urem, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), divisor)), 32, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + res, 64, true), 64, false)); + } + } + cc.jmp(label_merge); + cc.bind(label_else); + { + auto res = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + res, 64, true), 64, false)); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 73); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 74: LRW */ + continuation_e __lrw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {aq}, {rl}", fmt::arg("mnemonic", "lrw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("aq", name(aq)), fmt::arg("rl", name(rl))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LRW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 74); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false)), 64, true)); + gen_write_mem(jh, traits::RES, offs, (uint8_t)- 1, 1); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 74); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 75: SCW */ + continuation_e __scw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {aq}, {rl}", fmt::arg("mnemonic", "scw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", name(aq)), fmt::arg("rl", name(rl))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SCW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 75); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::RES, offs, 1); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, res1, 0); + cmp(cc, cond, 0); + cc.je(label_merge); + { + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), 4); + } + cc.bind(label_merge); + } + if(rd!=0){ + auto label_then6 = cc.newLabel(); + auto label_merge6 = cc.newLabel(); + auto tmp_reg6 = get_reg_Gp(cc, 8, false); + cmp(cc, res1, 0); + cc.jne(label_then6); + mov(cc, tmp_reg6,1); + cc.jmp(label_merge6); + cc.bind(label_then6); + mov(cc, tmp_reg6, 0); + cc.bind(label_merge6); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg6 + , 64, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 75); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 76: AMOSWAPW */ + continuation_e __amoswapw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoswapw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOSWAPW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 76); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res = load_reg_from_mem_Gp(jh, traits::X0 + rs2); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false)), 64, true)); + } + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + res, 32, false), 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 76); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 77: AMOADDW */ + continuation_e __amoaddw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoaddw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOADDW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 77); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false); + auto res2 = gen_operation(cc, add, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 64, true)); + } + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + res2, 32, true), 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 77); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 78: AMOXORW */ + continuation_e __amoxorw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoxorw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOXORW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 78); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 4); + auto res2 = gen_operation(cc, bxor, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + gen_ext(cc, res1, 32, true), 64, true), 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 78); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 79: AMOANDW */ + continuation_e __amoandw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoandw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOANDW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 79); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 4); + auto res2 = gen_operation(cc, band, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + gen_ext(cc, res1, 32, true), 64, true), 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 79); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 80: AMOORW */ + continuation_e __amoorw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoorw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOORW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 80); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 4); + auto res2 = gen_operation(cc, bor, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + gen_ext(cc, res1, 32, true), 64, true), 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 80); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 81: AMOMINW */ + continuation_e __amominw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amominw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMINW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 81); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false); + auto label_then7 = cc.newLabel(); + auto label_merge7 = cc.newLabel(); + auto tmp_reg7 = get_reg_Gp(cc, 32, false); + cmp(cc, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.jg(label_then7); + mov(cc, tmp_reg7,gen_ext(cc, res1, 32, false)); + cc.jmp(label_merge7); + cc.bind(label_then7); + mov(cc, tmp_reg7, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.bind(label_merge7); + auto res2 = tmp_reg7 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 64, true)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 81); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 82: AMOMAXW */ + continuation_e __amomaxw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMAXW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 82); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false); + auto label_then8 = cc.newLabel(); + auto label_merge8 = cc.newLabel(); + auto tmp_reg8 = get_reg_Gp(cc, 32, false); + cmp(cc, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.jl(label_then8); + mov(cc, tmp_reg8,gen_ext(cc, res1, 32, false)); + cc.jmp(label_merge8); + cc.bind(label_then8); + mov(cc, tmp_reg8, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.bind(label_merge8); + auto res2 = tmp_reg8 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 64, true)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 82); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 83: AMOMINUW */ + continuation_e __amominuw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amominuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMINUW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 83); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 4); + auto label_then9 = cc.newLabel(); + auto label_merge9 = cc.newLabel(); + auto tmp_reg9 = get_reg_Gp(cc, 32, false); + cmp(cc, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.ja(label_then9); + mov(cc, tmp_reg9,res1); + cc.jmp(label_merge9); + cc.bind(label_then9); + mov(cc, tmp_reg9, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.bind(label_merge9); + auto res2 = tmp_reg9 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + gen_ext(cc, res1, 32, true), 64, true), 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 83); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 84: AMOMAXUW */ + continuation_e __amomaxuw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxuw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMAXUW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 84); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 4); + auto label_then10 = cc.newLabel(); + auto label_merge10 = cc.newLabel(); + auto tmp_reg10 = get_reg_Gp(cc, 32, false); + cmp(cc, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.jb(label_then10); + mov(cc, tmp_reg10,res1); + cc.jmp(label_merge10); + cc.bind(label_then10); + mov(cc, tmp_reg10, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false)); + cc.bind(label_merge10); + auto res2 = tmp_reg10 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + gen_ext(cc, res1, 32, true), 64, true), 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 84); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 85: LRD */ + continuation_e __lrd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "lrd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("LRD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 85); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false)), 64, true)); + gen_write_mem(jh, traits::RES, offs, (uint8_t)- 1, 1); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 85); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 86: SCD */ + continuation_e __scd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "scd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SCD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 86); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res = gen_read_mem(jh, traits::RES, offs, 1); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, res, 0); + cmp(cc, cond, 0); + cc.je(label_merge); + { + gen_write_mem(jh, traits::MEM, offs, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 8); + } + cc.bind(label_merge); + } + if(rd!=0){ + auto label_then11 = cc.newLabel(); + auto label_merge11 = cc.newLabel(); + auto tmp_reg11 = get_reg_Gp(cc, 8, false); + cmp(cc, res, 0); + cc.jne(label_then11); + mov(cc, tmp_reg11,1); + cc.jmp(label_merge11); + cc.bind(label_then11); + mov(cc, tmp_reg11, 0); + cc.bind(label_merge11); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, tmp_reg11 + , 64, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 86); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 87: AMOSWAPD */ + continuation_e __amoswapd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoswapd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOSWAPD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 87); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res = load_reg_from_mem_Gp(jh, traits::X0 + rs2); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false)), 64, true)); + } + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + res, 64, false), 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 87); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 88: AMOADDD */ + continuation_e __amoaddd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoaddd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOADDD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 88); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 8); + auto res2 = gen_ext(cc, + (gen_operation(cc, add, res1, load_reg_from_mem_Gp(jh, traits::X0 + rs2))), 64, false); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 88); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 89: AMOXORD */ + continuation_e __amoxord(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoxord"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOXORD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 89); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 8); + auto res2 = gen_operation(cc, bxor, res1, load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, gen_ext(cc, + res1, 64, false), 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 89); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 90: AMOANDD */ + continuation_e __amoandd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoandd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOANDD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 90); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 8); + auto res2 = gen_operation(cc, band, res1, load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 90); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 91: AMOORD */ + continuation_e __amoord(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amoord"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOORD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 91); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 8); + auto res2 = gen_operation(cc, bor, res1, load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 91); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 92: AMOMIND */ + continuation_e __amomind(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomind"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMIND_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 92); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false); + auto label_then12 = cc.newLabel(); + auto label_merge12 = cc.newLabel(); + auto tmp_reg12 = get_reg_Gp(cc, 64, false); + cmp(cc, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, false)); + cc.jg(label_then12); + mov(cc, tmp_reg12,gen_ext(cc, res1, 64, false)); + cc.jmp(label_merge12); + cc.bind(label_then12); + mov(cc, tmp_reg12, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, false)); + cc.bind(label_merge12); + auto res2 = tmp_reg12 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 64, true)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 92); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 93: AMOMAXD */ + continuation_e __amomaxd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxd"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMAXD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 93); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false); + auto label_then13 = cc.newLabel(); + auto label_merge13 = cc.newLabel(); + auto tmp_reg13 = get_reg_Gp(cc, 64, false); + cmp(cc, res1, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, false)); + cc.jl(label_then13); + mov(cc, tmp_reg13,gen_ext(cc, res1, 64, false)); + cc.jmp(label_merge13); + cc.bind(label_then13); + mov(cc, tmp_reg13, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, false)); + cc.bind(label_merge13); + auto res2 = tmp_reg13 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 64, true)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 93); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 94: AMOMINUD */ + continuation_e __amominud(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amominud"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMINUD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 94); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 8); + auto label_then14 = cc.newLabel(); + auto label_merge14 = cc.newLabel(); + auto tmp_reg14 = get_reg_Gp(cc, 64, false); + cmp(cc, res1, load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cc.ja(label_then14); + mov(cc, tmp_reg14,res1); + cc.jmp(label_merge14); + cc.bind(label_then14); + mov(cc, tmp_reg14, load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cc.bind(label_merge14); + auto res2 = tmp_reg14 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 94); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 95: AMOMAXUD */ + continuation_e __amomaxud(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu = {aq},rel = {rl})", fmt::arg("mnemonic", "amomaxud"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("AMOMAXUD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 95); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto res1 = gen_read_mem(jh, traits::MEM, offs, 8); + auto label_then15 = cc.newLabel(); + auto label_merge15 = cc.newLabel(); + auto tmp_reg15 = get_reg_Gp(cc, 64, false); + cmp(cc, res1, load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + cc.jb(label_then15); + mov(cc, tmp_reg15,res1); + cc.jmp(label_merge15); + cc.bind(label_then15); + mov(cc, tmp_reg15, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, false)); + cc.bind(label_merge15); + auto res2 = tmp_reg15 + ; + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res1, 64, false)); + } + gen_write_mem(jh, traits::MEM, offs, res2, 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 95); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 96: C__ADDI4SPN */ + continuation_e __c__addi4spn(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"), + fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ADDI4SPN_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 96); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(imm){ + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), imm)), 64, false)); + } + else { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 96); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 97: C__LW */ + continuation_e __c__lw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__LW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 97); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 64, false); + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_ext(cc, + gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 64, true)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 97); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 98: C__LD */ + continuation_e __c__ld(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm},({rs1})", fmt::arg("mnemonic", "c.ld"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__LD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 98); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 64, false); + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 98); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 99: C__SW */ + continuation_e __c__sw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 99); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 64, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2+8), 32, false), 4); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 99); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 100: C__SD */ + continuation_e __c__sd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm},({rs1})", fmt::arg("mnemonic", "c.sd"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 100); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 64, false); + gen_write_mem(jh, traits::MEM, offs, load_reg_from_mem_Gp(jh, traits::X0 + rs2+8), 8); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 100); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 101: C__ADDI */ + continuation_e __c__addi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ADDI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 101); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rs1!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rs1), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int8_t)sext<6>(imm))), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 101); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 102: C__NOP */ + continuation_e __c__nop(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "c.nop"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__NOP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 102); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 102); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 103: C__ADDIW */ + continuation_e __c__addiw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addiw"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ADDIW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 103); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs1==0){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rs1!=0){ + auto res = gen_ext(cc, + (gen_operation(cc, add, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), (int8_t)sext<6>(imm))), 32, true); + mov(cc, get_ptr_for(jh, traits::X0+ rs1), + gen_ext(cc, + res, 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 103); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 104: C__LI */ + continuation_e __c__li(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__LI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 104); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)((int8_t)sext<6>(imm))); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 104); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 105: C__LUI */ + continuation_e __c__lui(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__LUI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 105); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(imm==0||rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + if(rd!=0){ + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)((int32_t)sext<18>(imm))); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + value_reg); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 105); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 106: C__ADDI16SP */ + continuation_e __c__addi16sp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"), + fmt::arg("nzimm", nzimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ADDI16SP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 106); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(nzimm){ + mov(cc, get_ptr_for(jh, traits::X0+ 2), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), (int16_t)sext<10>(nzimm))), 64, true)); + } + else { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 106); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 107: __reserved_clui */ + continuation_e ____reserved_clui(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = ".reserved_clui"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("__reserved_clui_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 107); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 107); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 108: C__SRLI */ + continuation_e __c__srli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t nzuimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("nzuimm", nzuimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SRLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 108); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rs1+8), + gen_operation(cc, shr, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), nzuimm)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 108); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 109: C__SRAI */ + continuation_e __c__srai(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SRAI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 109); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rs1+8), + gen_ext(cc, + (gen_operation(cc, sar, (gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), 64, false)), shamt)), 64, true)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 109); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 110: C__ANDI */ + continuation_e __c__andi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ANDI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 110); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rs1+8), + gen_ext(cc, + (gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), (int8_t)sext<6>(imm))), 64, true)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 110); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 111: C__SUB */ + continuation_e __c__sub(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SUB_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 111); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_ext(cc, + (gen_operation(cc, sub, load_reg_from_mem_Gp(jh, traits::X0 + rd+8), load_reg_from_mem_Gp(jh, traits::X0 + rs2+8))), 64, true)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 111); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 112: C__XOR */ + continuation_e __c__xor(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__XOR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 112); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_operation(cc, bxor, load_reg_from_mem_Gp(jh, traits::X0 + rd+8), load_reg_from_mem_Gp(jh, traits::X0 + rs2+8))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 112); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 113: C__OR */ + continuation_e __c__or(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__OR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 113); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_operation(cc, bor, load_reg_from_mem_Gp(jh, traits::X0 + rd+8), load_reg_from_mem_Gp(jh, traits::X0 + rs2+8))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 113); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 114: C__AND */ + continuation_e __c__and(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__AND_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 114); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rd+8), load_reg_from_mem_Gp(jh, traits::X0 + rs2+8))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 114); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 115: C__SUBW */ + continuation_e __c__subw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rd}, {rs2}", fmt::arg("mnemonic", "c.subw"), + fmt::arg("rd", name(8+rd)), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SUBW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 115); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto res = gen_ext(cc, + (gen_operation(cc, sub, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rd+8), 32, false), gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2+8), 32, false))), 32, true); + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_ext(cc, + res, 64, true)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 115); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 116: C__ADDW */ + continuation_e __c__addw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rd}, {rs2}", fmt::arg("mnemonic", "c.addw"), + fmt::arg("rd", name(8+rd)), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ADDW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 116); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto res = gen_ext(cc, + (gen_operation(cc, add, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rd+8), 32, false), gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2+8), 32, false))), 32, true); + mov(cc, get_ptr_for(jh, traits::X0+ rd+8), + gen_ext(cc, + res, 64, true)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 116); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 117: C__J */ + continuation_e __c__j(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"), + fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__J_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 117); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + auto PC_val_v = (uint64_t)(PC+(int16_t)sext<12>(imm)); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 117); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 118: C__BEQZ */ + continuation_e __c__beqz(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__BEQZ_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 118); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, eq, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), 0); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto PC_val_v = (uint64_t)(PC+(int16_t)sext<9>(imm)); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + cc.bind(label_merge); + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 118); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 119: C__BNEZ */ + continuation_e __c__bnez(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__BNEZ_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 119); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), 0); + cmp(cc, cond, 0); + cc.je(label_merge); + { + auto PC_val_v = (uint64_t)(PC+(int16_t)sext<9>(imm)); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(KNOWN_JUMP)); + } + cc.bind(label_merge); + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 119); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 120: C__SLLI */ + continuation_e __c__slli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SLLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 120); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rs1!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rs1), + gen_operation(cc, shl, load_reg_from_mem_Gp(jh, traits::X0 + rs1), shamt)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 120); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 121: C__LWSP */ + continuation_e __c__lwsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__LWSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 121); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rd==0){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 64, false); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 64, true)); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 121); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 122: C__LDSP */ + continuation_e __c__ldsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t uimm = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm}(sp)", fmt::arg("mnemonic", "c.ldsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__LDSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 122); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rd==0){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 64, false); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + res); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 122); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 123: C__MV */ + continuation_e __c__mv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__MV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 123); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem_Gp(jh, traits::X0 + rs2)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 123); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 124: C__JR */ + continuation_e __c__jr(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"), + fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__JR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 124); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs1&&rs1(traits::RFS)){ + auto addr_mask = (uint64_t)- 2; + auto PC_val_v = gen_operation(cc, band, load_reg_from_mem_Gp(jh, traits::X0 + rs1%static_cast(traits::RFS)), addr_mask); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(UNKNOWN_JUMP)); + } + else { + gen_raise(jh, 0, 2); + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 124); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 125: __reserved_cmv */ + continuation_e ____reserved_cmv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = ".reserved_cmv"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("__reserved_cmv_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 125); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_raise(jh, 0, 2); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 125); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 126: C__ADD */ + continuation_e __c__add(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__ADD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 126); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rd), load_reg_from_mem_Gp(jh, traits::X0 + rs2))), 64, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 126); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 127: C__JALR */ + continuation_e __c__jalr(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"), + fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__JALR_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 127); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto addr_mask = (uint64_t)- 2; + auto new_pc = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto value_reg = get_reg_Gp(cc, 64, false); + cc.movabs(value_reg, (uint64_t)(PC+2)); + mov(cc, get_ptr_for(jh, traits::X0+ 1), + value_reg); + auto PC_val_v = gen_operation(cc, band, new_pc, addr_mask); + mov(cc, jh.next_pc, PC_val_v); + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(UNKNOWN_JUMP)); + } + auto returnValue = BRANCH; + + gen_sync(jh, POST_SYNC, 127); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 128: C__EBREAK */ + continuation_e __c__ebreak(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "c.ebreak"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__EBREAK_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 128); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_raise(jh, 0, 3); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 128); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 129: C__SWSP */ + continuation_e __c__swsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SWSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 129); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 64, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, false), 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 129); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 130: C__SDSP */ + continuation_e __c__sdsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint16_t uimm = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm}(sp)", fmt::arg("mnemonic", "c.sdsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__SDSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 130); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 64, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, false), 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 130); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 131: DII */ + continuation_e __dii(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "dii"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("DII_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 131); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 131); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 132: FLW */ + continuation_e __flw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "flw"), + fmt::arg("rd", fname(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 132); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + InvokeNode* call_NaNBox32_16; + auto NaNBox32_16_arg0 = gen_read_mem(jh, traits::MEM, offs, 4); + x86::Gp ret_val_NaNBox32_16 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_16, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_16); + setArg(call_NaNBox32_16, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_16, 1, NaNBox32_16_arg0); + setRet(call_NaNBox32_16, 0, ret_val_NaNBox32_16); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 132); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 133: FSW */ + continuation_e __fsw(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "fsw"), + fmt::arg("rs2", fname(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSW_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 133); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 32, true); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs2), 32, false), 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 133); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 134: FADD__S */ + continuation_e __fadd__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FADD__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 134); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_19; + auto unbox_s_19_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_19 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_19, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_20; + auto unbox_s_20_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_20 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_20, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_21; + x86::Gp ret_val_get_rm_21 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_21, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fadd_s_18; + auto fadd_s_18_arg0 = ret_val_unbox_s_19; + auto fadd_s_18_arg1 = ret_val_unbox_s_20; + auto fadd_s_18_arg2 = ret_val_get_rm_21; + x86::Gp ret_val_fadd_s_18 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fadd_s_18, &fadd_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_17; + auto NaNBox32_17_arg0 = ret_val_fadd_s_18; + x86::Gp ret_val_NaNBox32_17 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_17, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_17); + setArg(call_unbox_s_19, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_19, 1, unbox_s_19_arg1); + setRet(call_unbox_s_19, 0, ret_val_unbox_s_19); + setArg(call_unbox_s_20, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_20, 1, unbox_s_20_arg1); + setRet(call_unbox_s_20, 0, ret_val_unbox_s_20); + setArg(call_get_rm_21, 0, reinterpret_cast(this)); + setArg(call_get_rm_21, 1, rm); + setRet(call_get_rm_21, 0, ret_val_get_rm_21); + setArg(call_fadd_s_18, 0, fadd_s_18_arg0); + setArg(call_fadd_s_18, 1, fadd_s_18_arg1); + setArg(call_fadd_s_18, 2, fadd_s_18_arg2); + setRet(call_fadd_s_18, 0, ret_val_fadd_s_18); + setArg(call_NaNBox32_17, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_17, 1, NaNBox32_17_arg0); + setRet(call_NaNBox32_17, 0, ret_val_NaNBox32_17); + InvokeNode* call_fget_flags_22; + x86::Gp ret_val_fget_flags_22 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_22, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_22; + setRet(call_fget_flags_22, 0, ret_val_fget_flags_22); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 134); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 135: FSUB__S */ + continuation_e __fsub__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSUB__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 135); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_25; + auto unbox_s_25_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_25 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_25, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_26; + auto unbox_s_26_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_26 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_26, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_27; + x86::Gp ret_val_get_rm_27 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_27, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fsub_s_24; + auto fsub_s_24_arg0 = ret_val_unbox_s_25; + auto fsub_s_24_arg1 = ret_val_unbox_s_26; + auto fsub_s_24_arg2 = ret_val_get_rm_27; + x86::Gp ret_val_fsub_s_24 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fsub_s_24, &fsub_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_23; + auto NaNBox32_23_arg0 = ret_val_fsub_s_24; + x86::Gp ret_val_NaNBox32_23 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_23, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_23); + setArg(call_unbox_s_25, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_25, 1, unbox_s_25_arg1); + setRet(call_unbox_s_25, 0, ret_val_unbox_s_25); + setArg(call_unbox_s_26, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_26, 1, unbox_s_26_arg1); + setRet(call_unbox_s_26, 0, ret_val_unbox_s_26); + setArg(call_get_rm_27, 0, reinterpret_cast(this)); + setArg(call_get_rm_27, 1, rm); + setRet(call_get_rm_27, 0, ret_val_get_rm_27); + setArg(call_fsub_s_24, 0, fsub_s_24_arg0); + setArg(call_fsub_s_24, 1, fsub_s_24_arg1); + setArg(call_fsub_s_24, 2, fsub_s_24_arg2); + setRet(call_fsub_s_24, 0, ret_val_fsub_s_24); + setArg(call_NaNBox32_23, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_23, 1, NaNBox32_23_arg0); + setRet(call_NaNBox32_23, 0, ret_val_NaNBox32_23); + InvokeNode* call_fget_flags_28; + x86::Gp ret_val_fget_flags_28 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_28, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_28; + setRet(call_fget_flags_28, 0, ret_val_fget_flags_28); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 135); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 136: FMUL__S */ + continuation_e __fmul__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fmul.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMUL__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 136); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_31; + auto unbox_s_31_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_31 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_31, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_32; + auto unbox_s_32_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_32 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_32, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_33; + x86::Gp ret_val_get_rm_33 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_33, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmul_s_30; + auto fmul_s_30_arg0 = ret_val_unbox_s_31; + auto fmul_s_30_arg1 = ret_val_unbox_s_32; + auto fmul_s_30_arg2 = ret_val_get_rm_33; + x86::Gp ret_val_fmul_s_30 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fmul_s_30, &fmul_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_29; + auto NaNBox32_29_arg0 = ret_val_fmul_s_30; + x86::Gp ret_val_NaNBox32_29 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_29, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_29); + setArg(call_unbox_s_31, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_31, 1, unbox_s_31_arg1); + setRet(call_unbox_s_31, 0, ret_val_unbox_s_31); + setArg(call_unbox_s_32, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_32, 1, unbox_s_32_arg1); + setRet(call_unbox_s_32, 0, ret_val_unbox_s_32); + setArg(call_get_rm_33, 0, reinterpret_cast(this)); + setArg(call_get_rm_33, 1, rm); + setRet(call_get_rm_33, 0, ret_val_get_rm_33); + setArg(call_fmul_s_30, 0, fmul_s_30_arg0); + setArg(call_fmul_s_30, 1, fmul_s_30_arg1); + setArg(call_fmul_s_30, 2, fmul_s_30_arg2); + setRet(call_fmul_s_30, 0, ret_val_fmul_s_30); + setArg(call_NaNBox32_29, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_29, 1, NaNBox32_29_arg0); + setRet(call_NaNBox32_29, 0, ret_val_NaNBox32_29); + InvokeNode* call_fget_flags_34; + x86::Gp ret_val_fget_flags_34 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_34, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_34; + setRet(call_fget_flags_34, 0, ret_val_fget_flags_34); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 136); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 137: FDIV__S */ + continuation_e __fdiv__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fdiv.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FDIV__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 137); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_37; + auto unbox_s_37_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_37 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_37, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_38; + auto unbox_s_38_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_38 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_38, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_39; + x86::Gp ret_val_get_rm_39 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_39, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fdiv_s_36; + auto fdiv_s_36_arg0 = ret_val_unbox_s_37; + auto fdiv_s_36_arg1 = ret_val_unbox_s_38; + auto fdiv_s_36_arg2 = ret_val_get_rm_39; + x86::Gp ret_val_fdiv_s_36 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fdiv_s_36, &fdiv_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_35; + auto NaNBox32_35_arg0 = ret_val_fdiv_s_36; + x86::Gp ret_val_NaNBox32_35 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_35, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_35); + setArg(call_unbox_s_37, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_37, 1, unbox_s_37_arg1); + setRet(call_unbox_s_37, 0, ret_val_unbox_s_37); + setArg(call_unbox_s_38, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_38, 1, unbox_s_38_arg1); + setRet(call_unbox_s_38, 0, ret_val_unbox_s_38); + setArg(call_get_rm_39, 0, reinterpret_cast(this)); + setArg(call_get_rm_39, 1, rm); + setRet(call_get_rm_39, 0, ret_val_get_rm_39); + setArg(call_fdiv_s_36, 0, fdiv_s_36_arg0); + setArg(call_fdiv_s_36, 1, fdiv_s_36_arg1); + setArg(call_fdiv_s_36, 2, fdiv_s_36_arg2); + setRet(call_fdiv_s_36, 0, ret_val_fdiv_s_36); + setArg(call_NaNBox32_35, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_35, 1, NaNBox32_35_arg0); + setRet(call_NaNBox32_35, 0, ret_val_NaNBox32_35); + InvokeNode* call_fget_flags_40; + x86::Gp ret_val_fget_flags_40 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_40, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_40; + setRet(call_fget_flags_40, 0, ret_val_fget_flags_40); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 137); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 138: FMIN__S */ + continuation_e __fmin__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmin.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMIN__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 138); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_43; + auto unbox_s_43_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_43 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_43, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_44; + auto unbox_s_44_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_44 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_44, &unbox_s, FuncSignature::build()); + InvokeNode* call_fsel_s_42; + auto fsel_s_42_arg0 = ret_val_unbox_s_43; + auto fsel_s_42_arg1 = ret_val_unbox_s_44; + x86::Gp ret_val_fsel_s_42 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fsel_s_42, &fsel_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_41; + auto NaNBox32_41_arg0 = ret_val_fsel_s_42; + x86::Gp ret_val_NaNBox32_41 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_41, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_41); + setArg(call_unbox_s_43, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_43, 1, unbox_s_43_arg1); + setRet(call_unbox_s_43, 0, ret_val_unbox_s_43); + setArg(call_unbox_s_44, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_44, 1, unbox_s_44_arg1); + setRet(call_unbox_s_44, 0, ret_val_unbox_s_44); + setArg(call_fsel_s_42, 0, fsel_s_42_arg0); + setArg(call_fsel_s_42, 1, fsel_s_42_arg1); + setArg(call_fsel_s_42, 2, 0); + setRet(call_fsel_s_42, 0, ret_val_fsel_s_42); + setArg(call_NaNBox32_41, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_41, 1, NaNBox32_41_arg0); + setRet(call_NaNBox32_41, 0, ret_val_NaNBox32_41); + InvokeNode* call_fget_flags_45; + x86::Gp ret_val_fget_flags_45 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_45, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_45; + setRet(call_fget_flags_45, 0, ret_val_fget_flags_45); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 138); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 139: FMAX__S */ + continuation_e __fmax__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmax.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMAX__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 139); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_48; + auto unbox_s_48_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_48 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_48, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_49; + auto unbox_s_49_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_49 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_49, &unbox_s, FuncSignature::build()); + InvokeNode* call_fsel_s_47; + auto fsel_s_47_arg0 = ret_val_unbox_s_48; + auto fsel_s_47_arg1 = ret_val_unbox_s_49; + x86::Gp ret_val_fsel_s_47 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fsel_s_47, &fsel_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_46; + auto NaNBox32_46_arg0 = ret_val_fsel_s_47; + x86::Gp ret_val_NaNBox32_46 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_46, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_46); + setArg(call_unbox_s_48, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_48, 1, unbox_s_48_arg1); + setRet(call_unbox_s_48, 0, ret_val_unbox_s_48); + setArg(call_unbox_s_49, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_49, 1, unbox_s_49_arg1); + setRet(call_unbox_s_49, 0, ret_val_unbox_s_49); + setArg(call_fsel_s_47, 0, fsel_s_47_arg0); + setArg(call_fsel_s_47, 1, fsel_s_47_arg1); + setArg(call_fsel_s_47, 2, 1); + setRet(call_fsel_s_47, 0, ret_val_fsel_s_47); + setArg(call_NaNBox32_46, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_46, 1, NaNBox32_46_arg0); + setRet(call_NaNBox32_46, 0, ret_val_NaNBox32_46); + InvokeNode* call_fget_flags_50; + x86::Gp ret_val_fget_flags_50 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_50, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_50; + setRet(call_fget_flags_50, 0, ret_val_fget_flags_50); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 139); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 140: FSQRT__S */ + continuation_e __fsqrt__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fsqrt.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSQRT__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 140); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_53; + auto unbox_s_53_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_53 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_53, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_54; + x86::Gp ret_val_get_rm_54 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_54, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fsqrt_s_52; + auto fsqrt_s_52_arg0 = ret_val_unbox_s_53; + auto fsqrt_s_52_arg1 = ret_val_get_rm_54; + x86::Gp ret_val_fsqrt_s_52 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fsqrt_s_52, &fsqrt_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_51; + auto NaNBox32_51_arg0 = ret_val_fsqrt_s_52; + x86::Gp ret_val_NaNBox32_51 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_51, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_51); + setArg(call_unbox_s_53, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_53, 1, unbox_s_53_arg1); + setRet(call_unbox_s_53, 0, ret_val_unbox_s_53); + setArg(call_get_rm_54, 0, reinterpret_cast(this)); + setArg(call_get_rm_54, 1, rm); + setRet(call_get_rm_54, 0, ret_val_get_rm_54); + setArg(call_fsqrt_s_52, 0, fsqrt_s_52_arg0); + setArg(call_fsqrt_s_52, 1, fsqrt_s_52_arg1); + setRet(call_fsqrt_s_52, 0, ret_val_fsqrt_s_52); + setArg(call_NaNBox32_51, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_51, 1, NaNBox32_51_arg0); + setRet(call_NaNBox32_51, 0, ret_val_NaNBox32_51); + InvokeNode* call_fget_flags_55; + x86::Gp ret_val_fget_flags_55 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_55, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_55; + setRet(call_fget_flags_55, 0, ret_val_fget_flags_55); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 140); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 141: FMADD__S */ + continuation_e __fmadd__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMADD__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 141); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_58; + auto unbox_s_58_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_58 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_58, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_59; + auto unbox_s_59_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_59 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_59, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_60; + auto unbox_s_60_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_s_60 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_60, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_61; + x86::Gp ret_val_get_rm_61 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_61, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_s_57; + auto fmadd_s_57_arg0 = ret_val_unbox_s_58; + auto fmadd_s_57_arg1 = ret_val_unbox_s_59; + auto fmadd_s_57_arg2 = ret_val_unbox_s_60; + auto fmadd_s_57_arg4 = ret_val_get_rm_61; + x86::Gp ret_val_fmadd_s_57 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fmadd_s_57, &fmadd_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_56; + auto NaNBox32_56_arg0 = ret_val_fmadd_s_57; + x86::Gp ret_val_NaNBox32_56 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_56, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_56); + setArg(call_unbox_s_58, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_58, 1, unbox_s_58_arg1); + setRet(call_unbox_s_58, 0, ret_val_unbox_s_58); + setArg(call_unbox_s_59, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_59, 1, unbox_s_59_arg1); + setRet(call_unbox_s_59, 0, ret_val_unbox_s_59); + setArg(call_unbox_s_60, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_60, 1, unbox_s_60_arg1); + setRet(call_unbox_s_60, 0, ret_val_unbox_s_60); + setArg(call_get_rm_61, 0, reinterpret_cast(this)); + setArg(call_get_rm_61, 1, rm); + setRet(call_get_rm_61, 0, ret_val_get_rm_61); + setArg(call_fmadd_s_57, 0, fmadd_s_57_arg0); + setArg(call_fmadd_s_57, 1, fmadd_s_57_arg1); + setArg(call_fmadd_s_57, 2, fmadd_s_57_arg2); + setArg(call_fmadd_s_57, 3, 0); + setArg(call_fmadd_s_57, 4, fmadd_s_57_arg4); + setRet(call_fmadd_s_57, 0, ret_val_fmadd_s_57); + setArg(call_NaNBox32_56, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_56, 1, NaNBox32_56_arg0); + setRet(call_NaNBox32_56, 0, ret_val_NaNBox32_56); + InvokeNode* call_fget_flags_62; + x86::Gp ret_val_fget_flags_62 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_62, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_62; + setRet(call_fget_flags_62, 0, ret_val_fget_flags_62); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 141); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 142: FMSUB__S */ + continuation_e __fmsub__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMSUB__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 142); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_65; + auto unbox_s_65_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_65 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_65, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_66; + auto unbox_s_66_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_66 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_66, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_67; + auto unbox_s_67_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_s_67 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_67, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_68; + x86::Gp ret_val_get_rm_68 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_68, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_s_64; + auto fmadd_s_64_arg0 = ret_val_unbox_s_65; + auto fmadd_s_64_arg1 = ret_val_unbox_s_66; + auto fmadd_s_64_arg2 = ret_val_unbox_s_67; + auto fmadd_s_64_arg4 = ret_val_get_rm_68; + x86::Gp ret_val_fmadd_s_64 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fmadd_s_64, &fmadd_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_63; + auto NaNBox32_63_arg0 = ret_val_fmadd_s_64; + x86::Gp ret_val_NaNBox32_63 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_63, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_63); + setArg(call_unbox_s_65, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_65, 1, unbox_s_65_arg1); + setRet(call_unbox_s_65, 0, ret_val_unbox_s_65); + setArg(call_unbox_s_66, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_66, 1, unbox_s_66_arg1); + setRet(call_unbox_s_66, 0, ret_val_unbox_s_66); + setArg(call_unbox_s_67, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_67, 1, unbox_s_67_arg1); + setRet(call_unbox_s_67, 0, ret_val_unbox_s_67); + setArg(call_get_rm_68, 0, reinterpret_cast(this)); + setArg(call_get_rm_68, 1, rm); + setRet(call_get_rm_68, 0, ret_val_get_rm_68); + setArg(call_fmadd_s_64, 0, fmadd_s_64_arg0); + setArg(call_fmadd_s_64, 1, fmadd_s_64_arg1); + setArg(call_fmadd_s_64, 2, fmadd_s_64_arg2); + setArg(call_fmadd_s_64, 3, 1); + setArg(call_fmadd_s_64, 4, fmadd_s_64_arg4); + setRet(call_fmadd_s_64, 0, ret_val_fmadd_s_64); + setArg(call_NaNBox32_63, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_63, 1, NaNBox32_63_arg0); + setRet(call_NaNBox32_63, 0, ret_val_NaNBox32_63); + InvokeNode* call_fget_flags_69; + x86::Gp ret_val_fget_flags_69 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_69, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_69; + setRet(call_fget_flags_69, 0, ret_val_fget_flags_69); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 142); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 143: FNMADD__S */ + continuation_e __fnmadd__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmadd.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FNMADD__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 143); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_72; + auto unbox_s_72_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_72 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_72, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_73; + auto unbox_s_73_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_73 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_73, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_74; + auto unbox_s_74_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_s_74 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_74, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_75; + x86::Gp ret_val_get_rm_75 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_75, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_s_71; + auto fmadd_s_71_arg0 = ret_val_unbox_s_72; + auto fmadd_s_71_arg1 = ret_val_unbox_s_73; + auto fmadd_s_71_arg2 = ret_val_unbox_s_74; + auto fmadd_s_71_arg4 = ret_val_get_rm_75; + x86::Gp ret_val_fmadd_s_71 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fmadd_s_71, &fmadd_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_70; + auto NaNBox32_70_arg0 = ret_val_fmadd_s_71; + x86::Gp ret_val_NaNBox32_70 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_70, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_70); + setArg(call_unbox_s_72, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_72, 1, unbox_s_72_arg1); + setRet(call_unbox_s_72, 0, ret_val_unbox_s_72); + setArg(call_unbox_s_73, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_73, 1, unbox_s_73_arg1); + setRet(call_unbox_s_73, 0, ret_val_unbox_s_73); + setArg(call_unbox_s_74, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_74, 1, unbox_s_74_arg1); + setRet(call_unbox_s_74, 0, ret_val_unbox_s_74); + setArg(call_get_rm_75, 0, reinterpret_cast(this)); + setArg(call_get_rm_75, 1, rm); + setRet(call_get_rm_75, 0, ret_val_get_rm_75); + setArg(call_fmadd_s_71, 0, fmadd_s_71_arg0); + setArg(call_fmadd_s_71, 1, fmadd_s_71_arg1); + setArg(call_fmadd_s_71, 2, fmadd_s_71_arg2); + setArg(call_fmadd_s_71, 3, 2); + setArg(call_fmadd_s_71, 4, fmadd_s_71_arg4); + setRet(call_fmadd_s_71, 0, ret_val_fmadd_s_71); + setArg(call_NaNBox32_70, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_70, 1, NaNBox32_70_arg0); + setRet(call_NaNBox32_70, 0, ret_val_NaNBox32_70); + InvokeNode* call_fget_flags_76; + x86::Gp ret_val_fget_flags_76 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_76, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_76; + setRet(call_fget_flags_76, 0, ret_val_fget_flags_76); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 143); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 144: FNMSUB__S */ + continuation_e __fnmsub__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmsub.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FNMSUB__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 144); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_79; + auto unbox_s_79_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_79 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_79, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_80; + auto unbox_s_80_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_80 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_80, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_81; + auto unbox_s_81_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_s_81 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_81, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_82; + x86::Gp ret_val_get_rm_82 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_82, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_s_78; + auto fmadd_s_78_arg0 = ret_val_unbox_s_79; + auto fmadd_s_78_arg1 = ret_val_unbox_s_80; + auto fmadd_s_78_arg2 = ret_val_unbox_s_81; + auto fmadd_s_78_arg4 = ret_val_get_rm_82; + x86::Gp ret_val_fmadd_s_78 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fmadd_s_78, &fmadd_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_77; + auto NaNBox32_77_arg0 = ret_val_fmadd_s_78; + x86::Gp ret_val_NaNBox32_77 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_77, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_77); + setArg(call_unbox_s_79, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_79, 1, unbox_s_79_arg1); + setRet(call_unbox_s_79, 0, ret_val_unbox_s_79); + setArg(call_unbox_s_80, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_80, 1, unbox_s_80_arg1); + setRet(call_unbox_s_80, 0, ret_val_unbox_s_80); + setArg(call_unbox_s_81, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_81, 1, unbox_s_81_arg1); + setRet(call_unbox_s_81, 0, ret_val_unbox_s_81); + setArg(call_get_rm_82, 0, reinterpret_cast(this)); + setArg(call_get_rm_82, 1, rm); + setRet(call_get_rm_82, 0, ret_val_get_rm_82); + setArg(call_fmadd_s_78, 0, fmadd_s_78_arg0); + setArg(call_fmadd_s_78, 1, fmadd_s_78_arg1); + setArg(call_fmadd_s_78, 2, fmadd_s_78_arg2); + setArg(call_fmadd_s_78, 3, 3); + setArg(call_fmadd_s_78, 4, fmadd_s_78_arg4); + setRet(call_fmadd_s_78, 0, ret_val_fmadd_s_78); + setArg(call_NaNBox32_77, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_77, 1, NaNBox32_77_arg0); + setRet(call_NaNBox32_77, 0, ret_val_NaNBox32_77); + InvokeNode* call_fget_flags_83; + x86::Gp ret_val_fget_flags_83 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_83, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_83; + setRet(call_fget_flags_83, 0, ret_val_fget_flags_83); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 144); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 145: FCVT__W__S */ + continuation_e __fcvt__w__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.w.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__W__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 145); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_85; + auto unbox_s_85_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_85 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_85, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_86; + x86::Gp ret_val_get_rm_86 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_86, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f32toi32_84; + auto f32toi32_84_arg0 = ret_val_unbox_s_85; + auto f32toi32_84_arg1 = ret_val_get_rm_86; + x86::Gp ret_val_f32toi32_84 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_f32toi32_84, &f32toi32, FuncSignature::build()); + auto res = gen_ext(cc, + gen_ext(cc, + ret_val_f32toi32_84, 32, false), 64, true); + setArg(call_unbox_s_85, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_85, 1, unbox_s_85_arg1); + setRet(call_unbox_s_85, 0, ret_val_unbox_s_85); + setArg(call_get_rm_86, 0, reinterpret_cast(this)); + setArg(call_get_rm_86, 1, rm); + setRet(call_get_rm_86, 0, ret_val_get_rm_86); + setArg(call_f32toi32_84, 0, f32toi32_84_arg0); + setArg(call_f32toi32_84, 1, f32toi32_84_arg1); + setRet(call_f32toi32_84, 0, ret_val_f32toi32_84); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + InvokeNode* call_fget_flags_87; + x86::Gp ret_val_fget_flags_87 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_87, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_87; + setRet(call_fget_flags_87, 0, ret_val_fget_flags_87); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 145); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 146: FCVT__WU__S */ + continuation_e __fcvt__wu__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.wu.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__WU__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 146); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_89; + auto unbox_s_89_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_89 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_89, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_90; + x86::Gp ret_val_get_rm_90 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_90, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f32toui32_88; + auto f32toui32_88_arg0 = ret_val_unbox_s_89; + auto f32toui32_88_arg1 = ret_val_get_rm_90; + x86::Gp ret_val_f32toui32_88 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_f32toui32_88, &f32toui32, FuncSignature::build()); + auto res = gen_ext(cc, + gen_ext(cc, + ret_val_f32toui32_88, 32, false), 64, true); + setArg(call_unbox_s_89, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_89, 1, unbox_s_89_arg1); + setRet(call_unbox_s_89, 0, ret_val_unbox_s_89); + setArg(call_get_rm_90, 0, reinterpret_cast(this)); + setArg(call_get_rm_90, 1, rm); + setRet(call_get_rm_90, 0, ret_val_get_rm_90); + setArg(call_f32toui32_88, 0, f32toui32_88_arg0); + setArg(call_f32toui32_88, 1, f32toui32_88_arg1); + setRet(call_f32toui32_88, 0, ret_val_f32toui32_88); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + InvokeNode* call_fget_flags_91; + x86::Gp ret_val_fget_flags_91 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_91, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_91; + setRet(call_fget_flags_91, 0, ret_val_fget_flags_91); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 146); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 147: FCVT__L__S */ + continuation_e __fcvt__l__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.l.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__L__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 147); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_93; + auto unbox_s_93_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_93 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_93, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_94; + x86::Gp ret_val_get_rm_94 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_94, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f32toi64_92; + auto f32toi64_92_arg0 = ret_val_unbox_s_93; + auto f32toi64_92_arg1 = ret_val_get_rm_94; + x86::Gp ret_val_f32toi64_92 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_f32toi64_92, &f32toi64, FuncSignature::build()); + auto res = gen_ext(cc, + gen_ext(cc, + ret_val_f32toi64_92, 64, false), 64, true); + setArg(call_unbox_s_93, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_93, 1, unbox_s_93_arg1); + setRet(call_unbox_s_93, 0, ret_val_unbox_s_93); + setArg(call_get_rm_94, 0, reinterpret_cast(this)); + setArg(call_get_rm_94, 1, rm); + setRet(call_get_rm_94, 0, ret_val_get_rm_94); + setArg(call_f32toi64_92, 0, f32toi64_92_arg0); + setArg(call_f32toi64_92, 1, f32toi64_92_arg1); + setRet(call_f32toi64_92, 0, ret_val_f32toi64_92); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + InvokeNode* call_fget_flags_95; + x86::Gp ret_val_fget_flags_95 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_95, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_95; + setRet(call_fget_flags_95, 0, ret_val_fget_flags_95); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 147); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 148: FCVT__LU__S */ + continuation_e __fcvt__lu__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.lu.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__LU__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 148); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_97; + auto unbox_s_97_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_97 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_97, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_98; + x86::Gp ret_val_get_rm_98 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_98, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f32toui64_96; + auto f32toui64_96_arg0 = ret_val_unbox_s_97; + auto f32toui64_96_arg1 = ret_val_get_rm_98; + x86::Gp ret_val_f32toui64_96 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_f32toui64_96, &f32toui64, FuncSignature::build()); + auto res = ret_val_f32toui64_96; + setArg(call_unbox_s_97, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_97, 1, unbox_s_97_arg1); + setRet(call_unbox_s_97, 0, ret_val_unbox_s_97); + setArg(call_get_rm_98, 0, reinterpret_cast(this)); + setArg(call_get_rm_98, 1, rm); + setRet(call_get_rm_98, 0, ret_val_get_rm_98); + setArg(call_f32toui64_96, 0, f32toui64_96_arg0); + setArg(call_f32toui64_96, 1, f32toui64_96_arg1); + setRet(call_f32toui64_96, 0, ret_val_f32toui64_96); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + res); + } + InvokeNode* call_fget_flags_99; + x86::Gp ret_val_fget_flags_99 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_99, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_99; + setRet(call_fget_flags_99, 0, ret_val_fget_flags_99); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 148); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 149: FCVT__S__W */ + continuation_e __fcvt__s__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.w"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__S__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 149); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_102; + x86::Gp ret_val_get_rm_102 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_102, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_i32tof32_101; + auto i32tof32_101_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto i32tof32_101_arg1 = ret_val_get_rm_102; + x86::Gp ret_val_i32tof32_101 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_i32tof32_101, &i32tof32, FuncSignature::build()); + InvokeNode* call_NaNBox32_100; + auto NaNBox32_100_arg0 = ret_val_i32tof32_101; + x86::Gp ret_val_NaNBox32_100 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_100, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_100); + setArg(call_get_rm_102, 0, reinterpret_cast(this)); + setArg(call_get_rm_102, 1, rm); + setRet(call_get_rm_102, 0, ret_val_get_rm_102); + setArg(call_i32tof32_101, 0, i32tof32_101_arg0); + setArg(call_i32tof32_101, 1, i32tof32_101_arg1); + setRet(call_i32tof32_101, 0, ret_val_i32tof32_101); + setArg(call_NaNBox32_100, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_100, 1, NaNBox32_100_arg0); + setRet(call_NaNBox32_100, 0, ret_val_NaNBox32_100); + InvokeNode* call_fget_flags_103; + x86::Gp ret_val_fget_flags_103 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_103, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_103; + setRet(call_fget_flags_103, 0, ret_val_fget_flags_103); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 149); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 150: FCVT__S__WU */ + continuation_e __fcvt__s__wu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.wu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__S__WU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 150); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_106; + x86::Gp ret_val_get_rm_106 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_106, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_ui32tof32_105; + auto ui32tof32_105_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto ui32tof32_105_arg1 = ret_val_get_rm_106; + x86::Gp ret_val_ui32tof32_105 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_ui32tof32_105, &ui32tof32, FuncSignature::build()); + InvokeNode* call_NaNBox32_104; + auto NaNBox32_104_arg0 = ret_val_ui32tof32_105; + x86::Gp ret_val_NaNBox32_104 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_104, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_104); + setArg(call_get_rm_106, 0, reinterpret_cast(this)); + setArg(call_get_rm_106, 1, rm); + setRet(call_get_rm_106, 0, ret_val_get_rm_106); + setArg(call_ui32tof32_105, 0, ui32tof32_105_arg0); + setArg(call_ui32tof32_105, 1, ui32tof32_105_arg1); + setRet(call_ui32tof32_105, 0, ret_val_ui32tof32_105); + setArg(call_NaNBox32_104, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_104, 1, NaNBox32_104_arg0); + setRet(call_NaNBox32_104, 0, ret_val_NaNBox32_104); + InvokeNode* call_fget_flags_107; + x86::Gp ret_val_fget_flags_107 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_107, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_107; + setRet(call_fget_flags_107, 0, ret_val_fget_flags_107); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 150); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 151: FCVT__S__L */ + continuation_e __fcvt__s__l(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.l"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__S__L_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 151); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_110; + x86::Gp ret_val_get_rm_110 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_110, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_i64tof32_109; + auto i64tof32_109_arg0 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto i64tof32_109_arg1 = ret_val_get_rm_110; + x86::Gp ret_val_i64tof32_109 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_i64tof32_109, &i64tof32, FuncSignature::build()); + InvokeNode* call_NaNBox32_108; + auto NaNBox32_108_arg0 = ret_val_i64tof32_109; + x86::Gp ret_val_NaNBox32_108 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_108, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_108); + setArg(call_get_rm_110, 0, reinterpret_cast(this)); + setArg(call_get_rm_110, 1, rm); + setRet(call_get_rm_110, 0, ret_val_get_rm_110); + setArg(call_i64tof32_109, 0, i64tof32_109_arg0); + setArg(call_i64tof32_109, 1, i64tof32_109_arg1); + setRet(call_i64tof32_109, 0, ret_val_i64tof32_109); + setArg(call_NaNBox32_108, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_108, 1, NaNBox32_108_arg0); + setRet(call_NaNBox32_108, 0, ret_val_NaNBox32_108); + InvokeNode* call_fget_flags_111; + x86::Gp ret_val_fget_flags_111 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_111, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_111; + setRet(call_fget_flags_111, 0, ret_val_fget_flags_111); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 151); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 152: FCVT__S__LU */ + continuation_e __fcvt__s__lu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.lu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__S__LU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 152); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_114; + x86::Gp ret_val_get_rm_114 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_114, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_ui64tof32_113; + auto ui64tof32_113_arg0 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto ui64tof32_113_arg1 = ret_val_get_rm_114; + x86::Gp ret_val_ui64tof32_113 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_ui64tof32_113, &ui64tof32, FuncSignature::build()); + InvokeNode* call_NaNBox32_112; + auto NaNBox32_112_arg0 = ret_val_ui64tof32_113; + x86::Gp ret_val_NaNBox32_112 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_112, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_112); + setArg(call_get_rm_114, 0, reinterpret_cast(this)); + setArg(call_get_rm_114, 1, rm); + setRet(call_get_rm_114, 0, ret_val_get_rm_114); + setArg(call_ui64tof32_113, 0, ui64tof32_113_arg0); + setArg(call_ui64tof32_113, 1, ui64tof32_113_arg1); + setRet(call_ui64tof32_113, 0, ret_val_ui64tof32_113); + setArg(call_NaNBox32_112, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_112, 1, NaNBox32_112_arg0); + setRet(call_NaNBox32_112, 0, ret_val_NaNBox32_112); + InvokeNode* call_fget_flags_115; + x86::Gp ret_val_fget_flags_115 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_115, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_115; + setRet(call_fget_flags_115, 0, ret_val_fget_flags_115); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 152); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 153: FSGNJ__S */ + continuation_e __fsgnj__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnj.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJ__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 153); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_117; + auto unbox_s_117_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_117 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_117, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_118; + auto unbox_s_118_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_118 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_118, &unbox_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_116; + auto NaNBox32_116_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_s_117, 31, 31-31+1), 32, false), 31), gen_ext(cc, gen_slice(cc, ret_val_unbox_s_118, 0, 30-0+1), 32, false)); + x86::Gp ret_val_NaNBox32_116 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_116, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_116); + setArg(call_unbox_s_117, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_117, 1, unbox_s_117_arg1); + setRet(call_unbox_s_117, 0, ret_val_unbox_s_117); + setArg(call_unbox_s_118, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_118, 1, unbox_s_118_arg1); + setRet(call_unbox_s_118, 0, ret_val_unbox_s_118); + setArg(call_NaNBox32_116, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_116, 1, NaNBox32_116_arg0); + setRet(call_NaNBox32_116, 0, ret_val_NaNBox32_116); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 153); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 154: FSGNJN__S */ + continuation_e __fsgnjn__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjn.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJN__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 154); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_120; + auto unbox_s_120_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_120 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_120, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_121; + auto unbox_s_121_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_121 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_121, &unbox_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_119; + auto NaNBox32_119_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_s_120, 31, 31-31+1)), 32, false), 31), gen_ext(cc, gen_slice(cc, ret_val_unbox_s_121, 0, 30-0+1), 32, false)); + x86::Gp ret_val_NaNBox32_119 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_119, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_119); + setArg(call_unbox_s_120, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_120, 1, unbox_s_120_arg1); + setRet(call_unbox_s_120, 0, ret_val_unbox_s_120); + setArg(call_unbox_s_121, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_121, 1, unbox_s_121_arg1); + setRet(call_unbox_s_121, 0, ret_val_unbox_s_121); + setArg(call_NaNBox32_119, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_119, 1, NaNBox32_119_arg0); + setRet(call_NaNBox32_119, 0, ret_val_NaNBox32_119); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 154); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 155: FSGNJX__S */ + continuation_e __fsgnjx__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjx.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJX__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 155); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_123; + auto unbox_s_123_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_123 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_123, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_124; + auto unbox_s_124_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_124 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_124, &unbox_s, FuncSignature::build()); + InvokeNode* call_NaNBox32_122; + auto NaNBox32_122_arg0 = gen_operation(cc, bxor, (gen_operation(cc, band, ret_val_unbox_s_123, ((uint32_t)1<<31))), ret_val_unbox_s_124); + x86::Gp ret_val_NaNBox32_122 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_122, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_122); + setArg(call_unbox_s_123, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_123, 1, unbox_s_123_arg1); + setRet(call_unbox_s_123, 0, ret_val_unbox_s_123); + setArg(call_unbox_s_124, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_124, 1, unbox_s_124_arg1); + setRet(call_unbox_s_124, 0, ret_val_unbox_s_124); + setArg(call_NaNBox32_122, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_122, 1, NaNBox32_122_arg0); + setRet(call_NaNBox32_122, 0, ret_val_NaNBox32_122); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 155); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 156: FMV__X__W */ + continuation_e __fmv__x__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.x.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMV__X__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 156); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false), 64, true), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 156); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 157: FMV__W__X */ + continuation_e __fmv__w__x(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.w.x"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMV__W__X_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 157); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_NaNBox32_125; + auto NaNBox32_125_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + x86::Gp ret_val_NaNBox32_125 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_125, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_125); + setArg(call_NaNBox32_125, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_125, 1, NaNBox32_125_arg0); + setRet(call_NaNBox32_125, 0, ret_val_NaNBox32_125); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 157); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 158: FEQ__S */ + continuation_e __feq__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "feq.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FEQ__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 158); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_127; + auto unbox_s_127_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_127 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_127, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_128; + auto unbox_s_128_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_128 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_128, &unbox_s, FuncSignature::build()); + InvokeNode* call_fcmp_s_126; + auto fcmp_s_126_arg0 = ret_val_unbox_s_127; + auto fcmp_s_126_arg1 = ret_val_unbox_s_128; + x86::Gp ret_val_fcmp_s_126 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fcmp_s_126, &fcmp_s, FuncSignature::build()); + auto res = ret_val_fcmp_s_126; + setArg(call_unbox_s_127, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_127, 1, unbox_s_127_arg1); + setRet(call_unbox_s_127, 0, ret_val_unbox_s_127); + setArg(call_unbox_s_128, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_128, 1, unbox_s_128_arg1); + setRet(call_unbox_s_128, 0, ret_val_unbox_s_128); + setArg(call_fcmp_s_126, 0, fcmp_s_126_arg0); + setArg(call_fcmp_s_126, 1, fcmp_s_126_arg1); + setArg(call_fcmp_s_126, 2, 0); + setRet(call_fcmp_s_126, 0, ret_val_fcmp_s_126); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, res, 64, false) + ); + } + InvokeNode* call_fget_flags_129; + x86::Gp ret_val_fget_flags_129 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_129, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_129; + setRet(call_fget_flags_129, 0, ret_val_fget_flags_129); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 158); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 159: FLT__S */ + continuation_e __flt__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "flt.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLT__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 159); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_131; + auto unbox_s_131_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_131 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_131, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_132; + auto unbox_s_132_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_132 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_132, &unbox_s, FuncSignature::build()); + InvokeNode* call_fcmp_s_130; + auto fcmp_s_130_arg0 = ret_val_unbox_s_131; + auto fcmp_s_130_arg1 = ret_val_unbox_s_132; + x86::Gp ret_val_fcmp_s_130 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fcmp_s_130, &fcmp_s, FuncSignature::build()); + auto res = ret_val_fcmp_s_130; + setArg(call_unbox_s_131, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_131, 1, unbox_s_131_arg1); + setRet(call_unbox_s_131, 0, ret_val_unbox_s_131); + setArg(call_unbox_s_132, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_132, 1, unbox_s_132_arg1); + setRet(call_unbox_s_132, 0, ret_val_unbox_s_132); + setArg(call_fcmp_s_130, 0, fcmp_s_130_arg0); + setArg(call_fcmp_s_130, 1, fcmp_s_130_arg1); + setArg(call_fcmp_s_130, 2, 2); + setRet(call_fcmp_s_130, 0, ret_val_fcmp_s_130); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, res, 64, false) + ); + } + InvokeNode* call_fget_flags_133; + x86::Gp ret_val_fget_flags_133 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_133, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_133; + setRet(call_fget_flags_133, 0, ret_val_fget_flags_133); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 159); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 160: FLE__S */ + continuation_e __fle__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fle.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLE__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 160); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_135; + auto unbox_s_135_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_135 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_135, &unbox_s, FuncSignature::build()); + InvokeNode* call_unbox_s_136; + auto unbox_s_136_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_s_136 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_136, &unbox_s, FuncSignature::build()); + InvokeNode* call_fcmp_s_134; + auto fcmp_s_134_arg0 = ret_val_unbox_s_135; + auto fcmp_s_134_arg1 = ret_val_unbox_s_136; + x86::Gp ret_val_fcmp_s_134 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fcmp_s_134, &fcmp_s, FuncSignature::build()); + auto res = ret_val_fcmp_s_134; + setArg(call_unbox_s_135, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_135, 1, unbox_s_135_arg1); + setRet(call_unbox_s_135, 0, ret_val_unbox_s_135); + setArg(call_unbox_s_136, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_136, 1, unbox_s_136_arg1); + setRet(call_unbox_s_136, 0, ret_val_unbox_s_136); + setArg(call_fcmp_s_134, 0, fcmp_s_134_arg0); + setArg(call_fcmp_s_134, 1, fcmp_s_134_arg1); + setArg(call_fcmp_s_134, 2, 1); + setRet(call_fcmp_s_134, 0, ret_val_fcmp_s_134); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, res, 64, false) + ); + } + InvokeNode* call_fget_flags_137; + x86::Gp ret_val_fget_flags_137 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_137, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_137; + setRet(call_fget_flags_137, 0, ret_val_fget_flags_137); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 160); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 161: FCLASS__S */ + continuation_e __fclass__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fclass.s"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCLASS__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 161); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_s_139; + auto unbox_s_139_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_139 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_139, &unbox_s, FuncSignature::build()); + InvokeNode* call_fclass_s_138; + auto fclass_s_138_arg0 = ret_val_unbox_s_139; + x86::Gp ret_val_fclass_s_138 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fclass_s_138, &fclass_s, FuncSignature::build()); + auto res = ret_val_fclass_s_138; + setArg(call_unbox_s_139, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_139, 1, unbox_s_139_arg1); + setRet(call_unbox_s_139, 0, ret_val_unbox_s_139); + setArg(call_fclass_s_138, 0, fclass_s_138_arg0); + setRet(call_fclass_s_138, 0, ret_val_fclass_s_138); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, res, 64, false) + ); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 161); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 162: FLD */ + continuation_e __fld(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "fld"), + fmt::arg("rd", fname(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 162); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + InvokeNode* call_NaNBox64_140; + auto NaNBox64_140_arg0 = gen_read_mem(jh, traits::MEM, offs, 8); + x86::Gp ret_val_NaNBox64_140 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_140, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_140); + setArg(call_NaNBox64_140, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_140, 1, NaNBox64_140_arg0); + setRet(call_NaNBox64_140, 0, ret_val_NaNBox64_140); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 162); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 163: FSD */ + continuation_e __fsd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "fsd"), + fmt::arg("rs2", fname(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 163); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))), 64, true); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs2), 64, false), 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 163); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 164: FADD__D */ + continuation_e __fadd__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FADD__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 164); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_143; + auto unbox_d_143_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_143 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_143, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_144; + auto unbox_d_144_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_144 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_144, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_145; + x86::Gp ret_val_get_rm_145 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_145, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fadd_d_142; + auto fadd_d_142_arg0 = ret_val_unbox_d_143; + auto fadd_d_142_arg1 = ret_val_unbox_d_144; + auto fadd_d_142_arg2 = ret_val_get_rm_145; + x86::Gp ret_val_fadd_d_142 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fadd_d_142, &fadd_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_141; + auto NaNBox64_141_arg0 = ret_val_fadd_d_142; + x86::Gp ret_val_NaNBox64_141 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_141, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_141); + setArg(call_unbox_d_143, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_143, 1, unbox_d_143_arg1); + setRet(call_unbox_d_143, 0, ret_val_unbox_d_143); + setArg(call_unbox_d_144, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_144, 1, unbox_d_144_arg1); + setRet(call_unbox_d_144, 0, ret_val_unbox_d_144); + setArg(call_get_rm_145, 0, reinterpret_cast(this)); + setArg(call_get_rm_145, 1, rm); + setRet(call_get_rm_145, 0, ret_val_get_rm_145); + setArg(call_fadd_d_142, 0, fadd_d_142_arg0); + setArg(call_fadd_d_142, 1, fadd_d_142_arg1); + setArg(call_fadd_d_142, 2, fadd_d_142_arg2); + setRet(call_fadd_d_142, 0, ret_val_fadd_d_142); + setArg(call_NaNBox64_141, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_141, 1, NaNBox64_141_arg0); + setRet(call_NaNBox64_141, 0, ret_val_NaNBox64_141); + InvokeNode* call_fget_flags_146; + x86::Gp ret_val_fget_flags_146 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_146, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_146; + setRet(call_fget_flags_146, 0, ret_val_fget_flags_146); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 164); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 165: FSUB__D */ + continuation_e __fsub__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSUB__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 165); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_149; + auto unbox_d_149_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_149 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_149, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_150; + auto unbox_d_150_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_150 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_150, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_151; + x86::Gp ret_val_get_rm_151 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_151, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fsub_d_148; + auto fsub_d_148_arg0 = ret_val_unbox_d_149; + auto fsub_d_148_arg1 = ret_val_unbox_d_150; + auto fsub_d_148_arg2 = ret_val_get_rm_151; + x86::Gp ret_val_fsub_d_148 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fsub_d_148, &fsub_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_147; + auto NaNBox64_147_arg0 = ret_val_fsub_d_148; + x86::Gp ret_val_NaNBox64_147 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_147, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_147); + setArg(call_unbox_d_149, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_149, 1, unbox_d_149_arg1); + setRet(call_unbox_d_149, 0, ret_val_unbox_d_149); + setArg(call_unbox_d_150, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_150, 1, unbox_d_150_arg1); + setRet(call_unbox_d_150, 0, ret_val_unbox_d_150); + setArg(call_get_rm_151, 0, reinterpret_cast(this)); + setArg(call_get_rm_151, 1, rm); + setRet(call_get_rm_151, 0, ret_val_get_rm_151); + setArg(call_fsub_d_148, 0, fsub_d_148_arg0); + setArg(call_fsub_d_148, 1, fsub_d_148_arg1); + setArg(call_fsub_d_148, 2, fsub_d_148_arg2); + setRet(call_fsub_d_148, 0, ret_val_fsub_d_148); + setArg(call_NaNBox64_147, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_147, 1, NaNBox64_147_arg0); + setRet(call_NaNBox64_147, 0, ret_val_NaNBox64_147); + InvokeNode* call_fget_flags_152; + x86::Gp ret_val_fget_flags_152 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_152, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_152; + setRet(call_fget_flags_152, 0, ret_val_fget_flags_152); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 165); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 166: FMUL__D */ + continuation_e __fmul__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fmul.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMUL__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 166); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_155; + auto unbox_d_155_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_155 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_155, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_156; + auto unbox_d_156_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_156 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_156, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_157; + x86::Gp ret_val_get_rm_157 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_157, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmul_d_154; + auto fmul_d_154_arg0 = ret_val_unbox_d_155; + auto fmul_d_154_arg1 = ret_val_unbox_d_156; + auto fmul_d_154_arg2 = ret_val_get_rm_157; + x86::Gp ret_val_fmul_d_154 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fmul_d_154, &fmul_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_153; + auto NaNBox64_153_arg0 = ret_val_fmul_d_154; + x86::Gp ret_val_NaNBox64_153 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_153, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_153); + setArg(call_unbox_d_155, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_155, 1, unbox_d_155_arg1); + setRet(call_unbox_d_155, 0, ret_val_unbox_d_155); + setArg(call_unbox_d_156, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_156, 1, unbox_d_156_arg1); + setRet(call_unbox_d_156, 0, ret_val_unbox_d_156); + setArg(call_get_rm_157, 0, reinterpret_cast(this)); + setArg(call_get_rm_157, 1, rm); + setRet(call_get_rm_157, 0, ret_val_get_rm_157); + setArg(call_fmul_d_154, 0, fmul_d_154_arg0); + setArg(call_fmul_d_154, 1, fmul_d_154_arg1); + setArg(call_fmul_d_154, 2, fmul_d_154_arg2); + setRet(call_fmul_d_154, 0, ret_val_fmul_d_154); + setArg(call_NaNBox64_153, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_153, 1, NaNBox64_153_arg0); + setRet(call_NaNBox64_153, 0, ret_val_NaNBox64_153); + InvokeNode* call_fget_flags_158; + x86::Gp ret_val_fget_flags_158 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_158, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_158; + setRet(call_fget_flags_158, 0, ret_val_fget_flags_158); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 166); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 167: FDIV__D */ + continuation_e __fdiv__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rm}", fmt::arg("mnemonic", "fdiv.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FDIV__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 167); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_161; + auto unbox_d_161_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_161 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_161, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_162; + auto unbox_d_162_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_162 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_162, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_163; + x86::Gp ret_val_get_rm_163 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_163, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fdiv_d_160; + auto fdiv_d_160_arg0 = ret_val_unbox_d_161; + auto fdiv_d_160_arg1 = ret_val_unbox_d_162; + auto fdiv_d_160_arg2 = ret_val_get_rm_163; + x86::Gp ret_val_fdiv_d_160 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fdiv_d_160, &fdiv_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_159; + auto NaNBox64_159_arg0 = ret_val_fdiv_d_160; + x86::Gp ret_val_NaNBox64_159 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_159, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_159); + setArg(call_unbox_d_161, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_161, 1, unbox_d_161_arg1); + setRet(call_unbox_d_161, 0, ret_val_unbox_d_161); + setArg(call_unbox_d_162, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_162, 1, unbox_d_162_arg1); + setRet(call_unbox_d_162, 0, ret_val_unbox_d_162); + setArg(call_get_rm_163, 0, reinterpret_cast(this)); + setArg(call_get_rm_163, 1, rm); + setRet(call_get_rm_163, 0, ret_val_get_rm_163); + setArg(call_fdiv_d_160, 0, fdiv_d_160_arg0); + setArg(call_fdiv_d_160, 1, fdiv_d_160_arg1); + setArg(call_fdiv_d_160, 2, fdiv_d_160_arg2); + setRet(call_fdiv_d_160, 0, ret_val_fdiv_d_160); + setArg(call_NaNBox64_159, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_159, 1, NaNBox64_159_arg0); + setRet(call_NaNBox64_159, 0, ret_val_NaNBox64_159); + InvokeNode* call_fget_flags_164; + x86::Gp ret_val_fget_flags_164 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_164, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_164; + setRet(call_fget_flags_164, 0, ret_val_fget_flags_164); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 167); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 168: FMIN__D */ + continuation_e __fmin__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmin.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMIN__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 168); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_167; + auto unbox_d_167_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_167 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_167, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_168; + auto unbox_d_168_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_168 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_168, &unbox_d, FuncSignature::build()); + InvokeNode* call_fsel_d_166; + auto fsel_d_166_arg0 = ret_val_unbox_d_167; + auto fsel_d_166_arg1 = ret_val_unbox_d_168; + x86::Gp ret_val_fsel_d_166 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fsel_d_166, &fsel_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_165; + auto NaNBox64_165_arg0 = ret_val_fsel_d_166; + x86::Gp ret_val_NaNBox64_165 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_165, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_165); + setArg(call_unbox_d_167, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_167, 1, unbox_d_167_arg1); + setRet(call_unbox_d_167, 0, ret_val_unbox_d_167); + setArg(call_unbox_d_168, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_168, 1, unbox_d_168_arg1); + setRet(call_unbox_d_168, 0, ret_val_unbox_d_168); + setArg(call_fsel_d_166, 0, fsel_d_166_arg0); + setArg(call_fsel_d_166, 1, fsel_d_166_arg1); + setArg(call_fsel_d_166, 2, 0); + setRet(call_fsel_d_166, 0, ret_val_fsel_d_166); + setArg(call_NaNBox64_165, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_165, 1, NaNBox64_165_arg0); + setRet(call_NaNBox64_165, 0, ret_val_NaNBox64_165); + InvokeNode* call_fget_flags_169; + x86::Gp ret_val_fget_flags_169 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_169, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_169; + setRet(call_fget_flags_169, 0, ret_val_fget_flags_169); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 168); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 169: FMAX__D */ + continuation_e __fmax__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fmax.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMAX__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 169); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_172; + auto unbox_d_172_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_172 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_172, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_173; + auto unbox_d_173_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_173 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_173, &unbox_d, FuncSignature::build()); + InvokeNode* call_fsel_d_171; + auto fsel_d_171_arg0 = ret_val_unbox_d_172; + auto fsel_d_171_arg1 = ret_val_unbox_d_173; + x86::Gp ret_val_fsel_d_171 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fsel_d_171, &fsel_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_170; + auto NaNBox64_170_arg0 = ret_val_fsel_d_171; + x86::Gp ret_val_NaNBox64_170 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_170, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_170); + setArg(call_unbox_d_172, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_172, 1, unbox_d_172_arg1); + setRet(call_unbox_d_172, 0, ret_val_unbox_d_172); + setArg(call_unbox_d_173, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_173, 1, unbox_d_173_arg1); + setRet(call_unbox_d_173, 0, ret_val_unbox_d_173); + setArg(call_fsel_d_171, 0, fsel_d_171_arg0); + setArg(call_fsel_d_171, 1, fsel_d_171_arg1); + setArg(call_fsel_d_171, 2, 1); + setRet(call_fsel_d_171, 0, ret_val_fsel_d_171); + setArg(call_NaNBox64_170, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_170, 1, NaNBox64_170_arg0); + setRet(call_NaNBox64_170, 0, ret_val_NaNBox64_170); + InvokeNode* call_fget_flags_174; + x86::Gp ret_val_fget_flags_174 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_174, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_174; + setRet(call_fget_flags_174, 0, ret_val_fget_flags_174); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 169); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 170: FSQRT__D */ + continuation_e __fsqrt__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fsqrt.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSQRT__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 170); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_177; + auto unbox_d_177_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_177 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_177, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_178; + x86::Gp ret_val_get_rm_178 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_178, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fsqrt_d_176; + auto fsqrt_d_176_arg0 = ret_val_unbox_d_177; + auto fsqrt_d_176_arg1 = ret_val_get_rm_178; + x86::Gp ret_val_fsqrt_d_176 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fsqrt_d_176, &fsqrt_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_175; + auto NaNBox64_175_arg0 = ret_val_fsqrt_d_176; + x86::Gp ret_val_NaNBox64_175 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_175, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_175); + setArg(call_unbox_d_177, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_177, 1, unbox_d_177_arg1); + setRet(call_unbox_d_177, 0, ret_val_unbox_d_177); + setArg(call_get_rm_178, 0, reinterpret_cast(this)); + setArg(call_get_rm_178, 1, rm); + setRet(call_get_rm_178, 0, ret_val_get_rm_178); + setArg(call_fsqrt_d_176, 0, fsqrt_d_176_arg0); + setArg(call_fsqrt_d_176, 1, fsqrt_d_176_arg1); + setRet(call_fsqrt_d_176, 0, ret_val_fsqrt_d_176); + setArg(call_NaNBox64_175, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_175, 1, NaNBox64_175_arg0); + setRet(call_NaNBox64_175, 0, ret_val_NaNBox64_175); + InvokeNode* call_fget_flags_179; + x86::Gp ret_val_fget_flags_179 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_179, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_179; + setRet(call_fget_flags_179, 0, ret_val_fget_flags_179); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 170); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 171: FMADD__D */ + continuation_e __fmadd__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMADD__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 171); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_182; + auto unbox_d_182_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_182 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_182, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_183; + auto unbox_d_183_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_183 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_183, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_184; + auto unbox_d_184_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_d_184 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_184, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_185; + x86::Gp ret_val_get_rm_185 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_185, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_d_181; + auto fmadd_d_181_arg0 = ret_val_unbox_d_182; + auto fmadd_d_181_arg1 = ret_val_unbox_d_183; + auto fmadd_d_181_arg2 = ret_val_unbox_d_184; + auto fmadd_d_181_arg4 = ret_val_get_rm_185; + x86::Gp ret_val_fmadd_d_181 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fmadd_d_181, &fmadd_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_180; + auto NaNBox64_180_arg0 = ret_val_fmadd_d_181; + x86::Gp ret_val_NaNBox64_180 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_180, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_180); + setArg(call_unbox_d_182, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_182, 1, unbox_d_182_arg1); + setRet(call_unbox_d_182, 0, ret_val_unbox_d_182); + setArg(call_unbox_d_183, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_183, 1, unbox_d_183_arg1); + setRet(call_unbox_d_183, 0, ret_val_unbox_d_183); + setArg(call_unbox_d_184, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_184, 1, unbox_d_184_arg1); + setRet(call_unbox_d_184, 0, ret_val_unbox_d_184); + setArg(call_get_rm_185, 0, reinterpret_cast(this)); + setArg(call_get_rm_185, 1, rm); + setRet(call_get_rm_185, 0, ret_val_get_rm_185); + setArg(call_fmadd_d_181, 0, fmadd_d_181_arg0); + setArg(call_fmadd_d_181, 1, fmadd_d_181_arg1); + setArg(call_fmadd_d_181, 2, fmadd_d_181_arg2); + setArg(call_fmadd_d_181, 3, 0); + setArg(call_fmadd_d_181, 4, fmadd_d_181_arg4); + setRet(call_fmadd_d_181, 0, ret_val_fmadd_d_181); + setArg(call_NaNBox64_180, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_180, 1, NaNBox64_180_arg0); + setRet(call_NaNBox64_180, 0, ret_val_NaNBox64_180); + InvokeNode* call_fget_flags_186; + x86::Gp ret_val_fget_flags_186 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_186, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_186; + setRet(call_fget_flags_186, 0, ret_val_fget_flags_186); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 171); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 172: FMSUB__D */ + continuation_e __fmsub__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fmsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMSUB__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 172); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_189; + auto unbox_d_189_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_189 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_189, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_190; + auto unbox_d_190_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_190 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_190, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_191; + auto unbox_d_191_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_d_191 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_191, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_192; + x86::Gp ret_val_get_rm_192 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_192, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_d_188; + auto fmadd_d_188_arg0 = ret_val_unbox_d_189; + auto fmadd_d_188_arg1 = ret_val_unbox_d_190; + auto fmadd_d_188_arg2 = ret_val_unbox_d_191; + auto fmadd_d_188_arg4 = ret_val_get_rm_192; + x86::Gp ret_val_fmadd_d_188 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fmadd_d_188, &fmadd_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_187; + auto NaNBox64_187_arg0 = ret_val_fmadd_d_188; + x86::Gp ret_val_NaNBox64_187 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_187, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + auto res = ret_val_NaNBox64_187; + setArg(call_unbox_d_189, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_189, 1, unbox_d_189_arg1); + setRet(call_unbox_d_189, 0, ret_val_unbox_d_189); + setArg(call_unbox_d_190, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_190, 1, unbox_d_190_arg1); + setRet(call_unbox_d_190, 0, ret_val_unbox_d_190); + setArg(call_unbox_d_191, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_191, 1, unbox_d_191_arg1); + setRet(call_unbox_d_191, 0, ret_val_unbox_d_191); + setArg(call_get_rm_192, 0, reinterpret_cast(this)); + setArg(call_get_rm_192, 1, rm); + setRet(call_get_rm_192, 0, ret_val_get_rm_192); + setArg(call_fmadd_d_188, 0, fmadd_d_188_arg0); + setArg(call_fmadd_d_188, 1, fmadd_d_188_arg1); + setArg(call_fmadd_d_188, 2, fmadd_d_188_arg2); + setArg(call_fmadd_d_188, 3, 1); + setArg(call_fmadd_d_188, 4, fmadd_d_188_arg4); + setRet(call_fmadd_d_188, 0, ret_val_fmadd_d_188); + setArg(call_NaNBox64_187, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_187, 1, NaNBox64_187_arg0); + setRet(call_NaNBox64_187, 0, ret_val_NaNBox64_187); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + res); + InvokeNode* call_fget_flags_193; + x86::Gp ret_val_fget_flags_193 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_193, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_193; + setRet(call_fget_flags_193, 0, ret_val_fget_flags_193); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 172); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 173: FNMADD__D */ + continuation_e __fnmadd__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmadd.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FNMADD__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 173); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_196; + auto unbox_d_196_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_196 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_196, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_197; + auto unbox_d_197_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_197 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_197, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_198; + auto unbox_d_198_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_d_198 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_198, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_199; + x86::Gp ret_val_get_rm_199 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_199, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_d_195; + auto fmadd_d_195_arg0 = ret_val_unbox_d_196; + auto fmadd_d_195_arg1 = ret_val_unbox_d_197; + auto fmadd_d_195_arg2 = ret_val_unbox_d_198; + auto fmadd_d_195_arg4 = ret_val_get_rm_199; + x86::Gp ret_val_fmadd_d_195 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fmadd_d_195, &fmadd_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_194; + auto NaNBox64_194_arg0 = ret_val_fmadd_d_195; + x86::Gp ret_val_NaNBox64_194 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_194, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_194); + setArg(call_unbox_d_196, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_196, 1, unbox_d_196_arg1); + setRet(call_unbox_d_196, 0, ret_val_unbox_d_196); + setArg(call_unbox_d_197, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_197, 1, unbox_d_197_arg1); + setRet(call_unbox_d_197, 0, ret_val_unbox_d_197); + setArg(call_unbox_d_198, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_198, 1, unbox_d_198_arg1); + setRet(call_unbox_d_198, 0, ret_val_unbox_d_198); + setArg(call_get_rm_199, 0, reinterpret_cast(this)); + setArg(call_get_rm_199, 1, rm); + setRet(call_get_rm_199, 0, ret_val_get_rm_199); + setArg(call_fmadd_d_195, 0, fmadd_d_195_arg0); + setArg(call_fmadd_d_195, 1, fmadd_d_195_arg1); + setArg(call_fmadd_d_195, 2, fmadd_d_195_arg2); + setArg(call_fmadd_d_195, 3, 2); + setArg(call_fmadd_d_195, 4, fmadd_d_195_arg4); + setRet(call_fmadd_d_195, 0, ret_val_fmadd_d_195); + setArg(call_NaNBox64_194, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_194, 1, NaNBox64_194_arg0); + setRet(call_NaNBox64_194, 0, ret_val_NaNBox64_194); + InvokeNode* call_fget_flags_200; + x86::Gp ret_val_fget_flags_200 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_200, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_200; + setRet(call_fget_flags_200, 0, ret_val_fget_flags_200); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 173); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 174: FNMSUB__D */ + continuation_e __fnmsub__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}, {rs3}, {rm}", fmt::arg("mnemonic", "fnmsub.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2)), fmt::arg("rs3", fname(rs3)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FNMSUB__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 174); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_203; + auto unbox_d_203_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_203 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_203, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_204; + auto unbox_d_204_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_204 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_204, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_205; + auto unbox_d_205_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs3); + x86::Gp ret_val_unbox_d_205 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_205, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_206; + x86::Gp ret_val_get_rm_206 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_206, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_fmadd_d_202; + auto fmadd_d_202_arg0 = ret_val_unbox_d_203; + auto fmadd_d_202_arg1 = ret_val_unbox_d_204; + auto fmadd_d_202_arg2 = ret_val_unbox_d_205; + auto fmadd_d_202_arg4 = ret_val_get_rm_206; + x86::Gp ret_val_fmadd_d_202 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fmadd_d_202, &fmadd_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_201; + auto NaNBox64_201_arg0 = ret_val_fmadd_d_202; + x86::Gp ret_val_NaNBox64_201 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_201, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_201); + setArg(call_unbox_d_203, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_203, 1, unbox_d_203_arg1); + setRet(call_unbox_d_203, 0, ret_val_unbox_d_203); + setArg(call_unbox_d_204, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_204, 1, unbox_d_204_arg1); + setRet(call_unbox_d_204, 0, ret_val_unbox_d_204); + setArg(call_unbox_d_205, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_205, 1, unbox_d_205_arg1); + setRet(call_unbox_d_205, 0, ret_val_unbox_d_205); + setArg(call_get_rm_206, 0, reinterpret_cast(this)); + setArg(call_get_rm_206, 1, rm); + setRet(call_get_rm_206, 0, ret_val_get_rm_206); + setArg(call_fmadd_d_202, 0, fmadd_d_202_arg0); + setArg(call_fmadd_d_202, 1, fmadd_d_202_arg1); + setArg(call_fmadd_d_202, 2, fmadd_d_202_arg2); + setArg(call_fmadd_d_202, 3, 3); + setArg(call_fmadd_d_202, 4, fmadd_d_202_arg4); + setRet(call_fmadd_d_202, 0, ret_val_fmadd_d_202); + setArg(call_NaNBox64_201, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_201, 1, NaNBox64_201_arg0); + setRet(call_NaNBox64_201, 0, ret_val_NaNBox64_201); + InvokeNode* call_fget_flags_207; + x86::Gp ret_val_fget_flags_207 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_207, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_207; + setRet(call_fget_flags_207, 0, ret_val_fget_flags_207); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 174); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 175: FCVT__W__D */ + continuation_e __fcvt__w__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.w.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__W__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 175); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_209; + auto unbox_d_209_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_209 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_209, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_210; + x86::Gp ret_val_get_rm_210 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_210, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f64toi32_208; + auto f64toi32_208_arg0 = ret_val_unbox_d_209; + auto f64toi32_208_arg1 = ret_val_get_rm_210; + x86::Gp ret_val_f64toi32_208 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_f64toi32_208, &f64toi32, FuncSignature::build()); + auto res = gen_ext(cc, + gen_ext(cc, + ret_val_f64toi32_208, 32, false), 64, true); + setArg(call_unbox_d_209, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_209, 1, unbox_d_209_arg1); + setRet(call_unbox_d_209, 0, ret_val_unbox_d_209); + setArg(call_get_rm_210, 0, reinterpret_cast(this)); + setArg(call_get_rm_210, 1, rm); + setRet(call_get_rm_210, 0, ret_val_get_rm_210); + setArg(call_f64toi32_208, 0, f64toi32_208_arg0); + setArg(call_f64toi32_208, 1, f64toi32_208_arg1); + setRet(call_f64toi32_208, 0, ret_val_f64toi32_208); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + InvokeNode* call_fget_flags_211; + x86::Gp ret_val_fget_flags_211 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_211, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_211; + setRet(call_fget_flags_211, 0, ret_val_fget_flags_211); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 175); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 176: FCVT__WU__D */ + continuation_e __fcvt__wu__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.wu.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__WU__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 176); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_213; + auto unbox_d_213_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_213 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_213, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_214; + x86::Gp ret_val_get_rm_214 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_214, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f64toui32_212; + auto f64toui32_212_arg0 = ret_val_unbox_d_213; + auto f64toui32_212_arg1 = ret_val_get_rm_214; + x86::Gp ret_val_f64toui32_212 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_f64toui32_212, &f64toui32, FuncSignature::build()); + auto res = gen_ext(cc, + gen_ext(cc, + ret_val_f64toui32_212, 32, false), 64, true); + setArg(call_unbox_d_213, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_213, 1, unbox_d_213_arg1); + setRet(call_unbox_d_213, 0, ret_val_unbox_d_213); + setArg(call_get_rm_214, 0, reinterpret_cast(this)); + setArg(call_get_rm_214, 1, rm); + setRet(call_get_rm_214, 0, ret_val_get_rm_214); + setArg(call_f64toui32_212, 0, f64toui32_212_arg0); + setArg(call_f64toui32_212, 1, f64toui32_212_arg1); + setRet(call_f64toui32_212, 0, ret_val_f64toui32_212); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + InvokeNode* call_fget_flags_215; + x86::Gp ret_val_fget_flags_215 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_215, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_215; + setRet(call_fget_flags_215, 0, ret_val_fget_flags_215); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 176); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 177: FCVT__L__D */ + continuation_e __fcvt__l__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.l.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__L__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 177); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_217; + auto unbox_d_217_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_217 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_217, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_218; + x86::Gp ret_val_get_rm_218 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_218, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f64toi64_216; + auto f64toi64_216_arg0 = ret_val_unbox_d_217; + auto f64toi64_216_arg1 = ret_val_get_rm_218; + x86::Gp ret_val_f64toi64_216 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_f64toi64_216, &f64toi64, FuncSignature::build()); + auto res = gen_ext(cc, + gen_ext(cc, + ret_val_f64toi64_216, 64, false), 64, true); + setArg(call_unbox_d_217, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_217, 1, unbox_d_217_arg1); + setRet(call_unbox_d_217, 0, ret_val_unbox_d_217); + setArg(call_get_rm_218, 0, reinterpret_cast(this)); + setArg(call_get_rm_218, 1, rm); + setRet(call_get_rm_218, 0, ret_val_get_rm_218); + setArg(call_f64toi64_216, 0, f64toi64_216_arg0); + setArg(call_f64toi64_216, 1, f64toi64_216_arg1); + setRet(call_f64toi64_216, 0, ret_val_f64toi64_216); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, true)); + } + InvokeNode* call_fget_flags_219; + x86::Gp ret_val_fget_flags_219 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_219, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_219; + setRet(call_fget_flags_219, 0, ret_val_fget_flags_219); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 177); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 178: FCVT__LU__D */ + continuation_e __fcvt__lu__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.lu.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__LU__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 178); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_221; + auto unbox_d_221_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_221 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_221, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_222; + x86::Gp ret_val_get_rm_222 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_222, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f64toui64_220; + auto f64toui64_220_arg0 = ret_val_unbox_d_221; + auto f64toui64_220_arg1 = ret_val_get_rm_222; + x86::Gp ret_val_f64toui64_220 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_f64toui64_220, &f64toui64, FuncSignature::build()); + auto res = ret_val_f64toui64_220; + setArg(call_unbox_d_221, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_221, 1, unbox_d_221_arg1); + setRet(call_unbox_d_221, 0, ret_val_unbox_d_221); + setArg(call_get_rm_222, 0, reinterpret_cast(this)); + setArg(call_get_rm_222, 1, rm); + setRet(call_get_rm_222, 0, ret_val_get_rm_222); + setArg(call_f64toui64_220, 0, f64toui64_220_arg0); + setArg(call_f64toui64_220, 1, f64toui64_220_arg1); + setRet(call_f64toui64_220, 0, ret_val_f64toui64_220); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + res); + } + InvokeNode* call_fget_flags_223; + x86::Gp ret_val_fget_flags_223 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_223, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_223; + setRet(call_fget_flags_223, 0, ret_val_fget_flags_223); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 178); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 179: FCVT__D__W */ + continuation_e __fcvt__d__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.w"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__D__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 179); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_226; + x86::Gp ret_val_get_rm_226 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_226, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_i32tof64_225; + auto i32tof64_225_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto i32tof64_225_arg1 = ret_val_get_rm_226; + x86::Gp ret_val_i32tof64_225 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_i32tof64_225, &i32tof64, FuncSignature::build()); + InvokeNode* call_NaNBox64_224; + auto NaNBox64_224_arg0 = ret_val_i32tof64_225; + x86::Gp ret_val_NaNBox64_224 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_224, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_224); + setArg(call_get_rm_226, 0, reinterpret_cast(this)); + setArg(call_get_rm_226, 1, rm); + setRet(call_get_rm_226, 0, ret_val_get_rm_226); + setArg(call_i32tof64_225, 0, i32tof64_225_arg0); + setArg(call_i32tof64_225, 1, i32tof64_225_arg1); + setRet(call_i32tof64_225, 0, ret_val_i32tof64_225); + setArg(call_NaNBox64_224, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_224, 1, NaNBox64_224_arg0); + setRet(call_NaNBox64_224, 0, ret_val_NaNBox64_224); + InvokeNode* call_fget_flags_227; + x86::Gp ret_val_fget_flags_227 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_227, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_227; + setRet(call_fget_flags_227, 0, ret_val_fget_flags_227); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 179); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 180: FCVT__D__WU */ + continuation_e __fcvt__d__wu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.wu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__D__WU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 180); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_230; + x86::Gp ret_val_get_rm_230 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_230, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_ui32tof64_229; + auto ui32tof64_229_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); + auto ui32tof64_229_arg1 = ret_val_get_rm_230; + x86::Gp ret_val_ui32tof64_229 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_ui32tof64_229, &ui32tof64, FuncSignature::build()); + InvokeNode* call_NaNBox64_228; + auto NaNBox64_228_arg0 = ret_val_ui32tof64_229; + x86::Gp ret_val_NaNBox64_228 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_228, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_228); + setArg(call_get_rm_230, 0, reinterpret_cast(this)); + setArg(call_get_rm_230, 1, rm); + setRet(call_get_rm_230, 0, ret_val_get_rm_230); + setArg(call_ui32tof64_229, 0, ui32tof64_229_arg0); + setArg(call_ui32tof64_229, 1, ui32tof64_229_arg1); + setRet(call_ui32tof64_229, 0, ret_val_ui32tof64_229); + setArg(call_NaNBox64_228, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_228, 1, NaNBox64_228_arg0); + setRet(call_NaNBox64_228, 0, ret_val_NaNBox64_228); + InvokeNode* call_fget_flags_231; + x86::Gp ret_val_fget_flags_231 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_231, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_231; + setRet(call_fget_flags_231, 0, ret_val_fget_flags_231); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 180); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 181: FCVT__D__L */ + continuation_e __fcvt__d__l(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.l"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__D__L_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 181); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_234; + x86::Gp ret_val_get_rm_234 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_234, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_i64tof64_233; + auto i64tof64_233_arg0 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto i64tof64_233_arg1 = ret_val_get_rm_234; + x86::Gp ret_val_i64tof64_233 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_i64tof64_233, &i64tof64, FuncSignature::build()); + InvokeNode* call_NaNBox64_232; + auto NaNBox64_232_arg0 = ret_val_i64tof64_233; + x86::Gp ret_val_NaNBox64_232 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_232, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_232); + setArg(call_get_rm_234, 0, reinterpret_cast(this)); + setArg(call_get_rm_234, 1, rm); + setRet(call_get_rm_234, 0, ret_val_get_rm_234); + setArg(call_i64tof64_233, 0, i64tof64_233_arg0); + setArg(call_i64tof64_233, 1, i64tof64_233_arg1); + setRet(call_i64tof64_233, 0, ret_val_i64tof64_233); + setArg(call_NaNBox64_232, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_232, 1, NaNBox64_232_arg0); + setRet(call_NaNBox64_232, 0, ret_val_NaNBox64_232); + InvokeNode* call_fget_flags_235; + x86::Gp ret_val_fget_flags_235 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_235, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_235; + setRet(call_fget_flags_235, 0, ret_val_fget_flags_235); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 181); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 182: FCVT__D__LU */ + continuation_e __fcvt__d__lu(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.lu"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__D__LU_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 182); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_rm_238; + x86::Gp ret_val_get_rm_238 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_238, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_ui64tof64_237; + auto ui64tof64_237_arg0 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto ui64tof64_237_arg1 = ret_val_get_rm_238; + x86::Gp ret_val_ui64tof64_237 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_ui64tof64_237, &ui64tof64, FuncSignature::build()); + InvokeNode* call_NaNBox64_236; + auto NaNBox64_236_arg0 = ret_val_ui64tof64_237; + x86::Gp ret_val_NaNBox64_236 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_236, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_236); + setArg(call_get_rm_238, 0, reinterpret_cast(this)); + setArg(call_get_rm_238, 1, rm); + setRet(call_get_rm_238, 0, ret_val_get_rm_238); + setArg(call_ui64tof64_237, 0, ui64tof64_237_arg0); + setArg(call_ui64tof64_237, 1, ui64tof64_237_arg1); + setRet(call_ui64tof64_237, 0, ret_val_ui64tof64_237); + setArg(call_NaNBox64_236, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_236, 1, NaNBox64_236_arg0); + setRet(call_NaNBox64_236, 0, ret_val_NaNBox64_236); + InvokeNode* call_fget_flags_239; + x86::Gp ret_val_fget_flags_239 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_239, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_239; + setRet(call_fget_flags_239, 0, ret_val_fget_flags_239); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 182); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 183: FCVT__S__D */ + continuation_e __fcvt__s__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.s.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__S__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 183); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_242; + auto unbox_d_242_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_242 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_242, &unbox_d, FuncSignature::build()); + InvokeNode* call_get_rm_243; + x86::Gp ret_val_get_rm_243 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_243, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f64tof32_241; + auto f64tof32_241_arg0 = ret_val_unbox_d_242; + auto f64tof32_241_arg1 = ret_val_get_rm_243; + x86::Gp ret_val_f64tof32_241 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_f64tof32_241, &f64tof32, FuncSignature::build()); + InvokeNode* call_NaNBox32_240; + auto NaNBox32_240_arg0 = ret_val_f64tof32_241; + x86::Gp ret_val_NaNBox32_240 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox32_240, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox32_240); + setArg(call_unbox_d_242, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_242, 1, unbox_d_242_arg1); + setRet(call_unbox_d_242, 0, ret_val_unbox_d_242); + setArg(call_get_rm_243, 0, reinterpret_cast(this)); + setArg(call_get_rm_243, 1, rm); + setRet(call_get_rm_243, 0, ret_val_get_rm_243); + setArg(call_f64tof32_241, 0, f64tof32_241_arg0); + setArg(call_f64tof32_241, 1, f64tof32_241_arg1); + setRet(call_f64tof32_241, 0, ret_val_f64tof32_241); + setArg(call_NaNBox32_240, 0, reinterpret_cast(this)); + setArg(call_NaNBox32_240, 1, NaNBox32_240_arg0); + setRet(call_NaNBox32_240, 0, ret_val_NaNBox32_240); + InvokeNode* call_fget_flags_244; + x86::Gp ret_val_fget_flags_244 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_244, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_244; + setRet(call_fget_flags_244, 0, ret_val_fget_flags_244); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 183); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 184: FCVT__D__S */ + continuation_e __fcvt__d__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rm}", fmt::arg("mnemonic", "fcvt.d.s"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rm", rm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCVT__D__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 184); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_s_247; + auto unbox_s_247_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_s_247 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_unbox_s_247, &unbox_s, FuncSignature::build()); + InvokeNode* call_get_rm_248; + x86::Gp ret_val_get_rm_248 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_rm_248, (uintptr_t)&vm_impl::_get_rm, FuncSignature::build()); + InvokeNode* call_f32tof64_246; + auto f32tof64_246_arg0 = ret_val_unbox_s_247; + auto f32tof64_246_arg1 = ret_val_get_rm_248; + x86::Gp ret_val_f32tof64_246 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_f32tof64_246, &f32tof64, FuncSignature::build()); + InvokeNode* call_NaNBox64_245; + auto NaNBox64_245_arg0 = ret_val_f32tof64_246; + x86::Gp ret_val_NaNBox64_245 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_245, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_245); + setArg(call_unbox_s_247, 0, static_cast(traits::FLEN)); + setArg(call_unbox_s_247, 1, unbox_s_247_arg1); + setRet(call_unbox_s_247, 0, ret_val_unbox_s_247); + setArg(call_get_rm_248, 0, reinterpret_cast(this)); + setArg(call_get_rm_248, 1, rm); + setRet(call_get_rm_248, 0, ret_val_get_rm_248); + setArg(call_f32tof64_246, 0, f32tof64_246_arg0); + setArg(call_f32tof64_246, 1, f32tof64_246_arg1); + setRet(call_f32tof64_246, 0, ret_val_f32tof64_246); + setArg(call_NaNBox64_245, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_245, 1, NaNBox64_245_arg0); + setRet(call_NaNBox64_245, 0, ret_val_NaNBox64_245); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 184); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 185: FSGNJ__D */ + continuation_e __fsgnj__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnj.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJ__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 185); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_250; + auto unbox_d_250_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_250 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_250, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_251; + auto unbox_d_251_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_251 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_251, &unbox_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_249; + auto NaNBox64_249_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_d_250, 63, 63-63+1), 64, false), 63), gen_ext(cc, gen_slice(cc, ret_val_unbox_d_251, 0, 62-0+1), 64, false)); + x86::Gp ret_val_NaNBox64_249 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_249, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_249); + setArg(call_unbox_d_250, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_250, 1, unbox_d_250_arg1); + setRet(call_unbox_d_250, 0, ret_val_unbox_d_250); + setArg(call_unbox_d_251, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_251, 1, unbox_d_251_arg1); + setRet(call_unbox_d_251, 0, ret_val_unbox_d_251); + setArg(call_NaNBox64_249, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_249, 1, NaNBox64_249_arg0); + setRet(call_NaNBox64_249, 0, ret_val_NaNBox64_249); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 185); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 186: FSGNJN__D */ + continuation_e __fsgnjn__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjn.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJN__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 186); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_253; + auto unbox_d_253_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_253 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_253, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_254; + auto unbox_d_254_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_254 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_254, &unbox_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_252; + auto NaNBox64_252_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_d_253, 63, 63-63+1)), 64, false), 63), gen_ext(cc, gen_slice(cc, ret_val_unbox_d_254, 0, 62-0+1), 64, false)); + x86::Gp ret_val_NaNBox64_252 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_252, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_252); + setArg(call_unbox_d_253, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_253, 1, unbox_d_253_arg1); + setRet(call_unbox_d_253, 0, ret_val_unbox_d_253); + setArg(call_unbox_d_254, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_254, 1, unbox_d_254_arg1); + setRet(call_unbox_d_254, 0, ret_val_unbox_d_254); + setArg(call_NaNBox64_252, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_252, 1, NaNBox64_252_arg0); + setRet(call_NaNBox64_252, 0, ret_val_NaNBox64_252); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 186); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 187: FSGNJX__D */ + continuation_e __fsgnjx__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fsgnjx.d"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FSGNJX__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 187); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_unbox_d_256; + auto unbox_d_256_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_256 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_256, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_257; + auto unbox_d_257_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_257 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_257, &unbox_d, FuncSignature::build()); + InvokeNode* call_NaNBox64_255; + auto NaNBox64_255_arg0 = gen_operation(cc, bxor, (gen_operation(cc, band, ret_val_unbox_d_256, ((uint64_t)1<<63))), ret_val_unbox_d_257); + x86::Gp ret_val_NaNBox64_255 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_255, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_255); + setArg(call_unbox_d_256, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_256, 1, unbox_d_256_arg1); + setRet(call_unbox_d_256, 0, ret_val_unbox_d_256); + setArg(call_unbox_d_257, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_257, 1, unbox_d_257_arg1); + setRet(call_unbox_d_257, 0, ret_val_unbox_d_257); + setArg(call_NaNBox64_255, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_255, 1, NaNBox64_255_arg0); + setRet(call_NaNBox64_255, 0, ret_val_NaNBox64_255); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 187); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 188: FMV__X__D */ + continuation_e __fmv__x__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.x.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMV__X__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 188); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false), 64, true), 64, true)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 188); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 189: FMV__D__X */ + continuation_e __fmv__d__x(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fmv.d.x"), + fmt::arg("rd", fname(rd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FMV__D__X_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 189); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_NaNBox64_258; + auto NaNBox64_258_arg0 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false); + x86::Gp ret_val_NaNBox64_258 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_258, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_258); + setArg(call_NaNBox64_258, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_258, 1, NaNBox64_258_arg0); + setRet(call_NaNBox64_258, 0, ret_val_NaNBox64_258); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 189); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 190: FEQ__D */ + continuation_e __feq__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "feq.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FEQ__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 190); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_260; + auto unbox_d_260_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_260 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_260, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_261; + auto unbox_d_261_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_261 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_261, &unbox_d, FuncSignature::build()); + InvokeNode* call_fcmp_d_259; + auto fcmp_d_259_arg0 = ret_val_unbox_d_260; + auto fcmp_d_259_arg1 = ret_val_unbox_d_261; + x86::Gp ret_val_fcmp_d_259 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fcmp_d_259, &fcmp_d, FuncSignature::build()); + auto res = ret_val_fcmp_d_259; + setArg(call_unbox_d_260, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_260, 1, unbox_d_260_arg1); + setRet(call_unbox_d_260, 0, ret_val_unbox_d_260); + setArg(call_unbox_d_261, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_261, 1, unbox_d_261_arg1); + setRet(call_unbox_d_261, 0, ret_val_unbox_d_261); + setArg(call_fcmp_d_259, 0, fcmp_d_259_arg0); + setArg(call_fcmp_d_259, 1, fcmp_d_259_arg1); + setArg(call_fcmp_d_259, 2, 0); + setRet(call_fcmp_d_259, 0, ret_val_fcmp_d_259); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, false)); + } + InvokeNode* call_fget_flags_262; + x86::Gp ret_val_fget_flags_262 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_262, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_262; + setRet(call_fget_flags_262, 0, ret_val_fget_flags_262); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 190); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 191: FLT__D */ + continuation_e __flt__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "flt.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLT__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 191); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_264; + auto unbox_d_264_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_264 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_264, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_265; + auto unbox_d_265_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_265 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_265, &unbox_d, FuncSignature::build()); + InvokeNode* call_fcmp_d_263; + auto fcmp_d_263_arg0 = ret_val_unbox_d_264; + auto fcmp_d_263_arg1 = ret_val_unbox_d_265; + x86::Gp ret_val_fcmp_d_263 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fcmp_d_263, &fcmp_d, FuncSignature::build()); + auto res = ret_val_fcmp_d_263; + setArg(call_unbox_d_264, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_264, 1, unbox_d_264_arg1); + setRet(call_unbox_d_264, 0, ret_val_unbox_d_264); + setArg(call_unbox_d_265, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_265, 1, unbox_d_265_arg1); + setRet(call_unbox_d_265, 0, ret_val_unbox_d_265); + setArg(call_fcmp_d_263, 0, fcmp_d_263_arg0); + setArg(call_fcmp_d_263, 1, fcmp_d_263_arg1); + setArg(call_fcmp_d_263, 2, 2); + setRet(call_fcmp_d_263, 0, ret_val_fcmp_d_263); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, false)); + } + InvokeNode* call_fget_flags_266; + x86::Gp ret_val_fget_flags_266 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_266, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_266; + setRet(call_fget_flags_266, 0, ret_val_fget_flags_266); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 191); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 192: FLE__D */ + continuation_e __fle__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "fle.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1)), fmt::arg("rs2", fname(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FLE__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 192); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_268; + auto unbox_d_268_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_268 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_268, &unbox_d, FuncSignature::build()); + InvokeNode* call_unbox_d_269; + auto unbox_d_269_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs2); + x86::Gp ret_val_unbox_d_269 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_269, &unbox_d, FuncSignature::build()); + InvokeNode* call_fcmp_d_267; + auto fcmp_d_267_arg0 = ret_val_unbox_d_268; + auto fcmp_d_267_arg1 = ret_val_unbox_d_269; + x86::Gp ret_val_fcmp_d_267 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fcmp_d_267, &fcmp_d, FuncSignature::build()); + auto res = ret_val_fcmp_d_267; + setArg(call_unbox_d_268, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_268, 1, unbox_d_268_arg1); + setRet(call_unbox_d_268, 0, ret_val_unbox_d_268); + setArg(call_unbox_d_269, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_269, 1, unbox_d_269_arg1); + setRet(call_unbox_d_269, 0, ret_val_unbox_d_269); + setArg(call_fcmp_d_267, 0, fcmp_d_267_arg0); + setArg(call_fcmp_d_267, 1, fcmp_d_267_arg1); + setArg(call_fcmp_d_267, 2, 1); + setRet(call_fcmp_d_267, 0, ret_val_fcmp_d_267); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, false)); + } + InvokeNode* call_fget_flags_270; + x86::Gp ret_val_fget_flags_270 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_270, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_270; + setRet(call_fget_flags_270, 0, ret_val_fget_flags_270); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 192); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 193: FCLASS__D */ + continuation_e __fclass__d(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "fclass.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("FCLASS__D_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 193); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_unbox_d_272; + auto unbox_d_272_arg1 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + x86::Gp ret_val_unbox_d_272 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_unbox_d_272, &unbox_d, FuncSignature::build()); + InvokeNode* call_fclass_d_271; + auto fclass_d_271_arg0 = ret_val_unbox_d_272; + x86::Gp ret_val_fclass_d_271 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fclass_d_271, &fclass_d, FuncSignature::build()); + auto res = ret_val_fclass_d_271; + setArg(call_unbox_d_272, 0, static_cast(traits::FLEN)); + setArg(call_unbox_d_272, 1, unbox_d_272_arg1); + setRet(call_unbox_d_272, 0, ret_val_unbox_d_272); + setArg(call_fclass_d_271, 0, fclass_d_271_arg0); + setRet(call_fclass_d_271, 0, ret_val_fclass_d_271); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + res, 64, false)); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 193); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 194: C__FLD */ + continuation_e __c__fld(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rd}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fld"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FLD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 194); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 64, false); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false); + InvokeNode* call_NaNBox64_273; + auto NaNBox64_273_arg0 = res; + x86::Gp ret_val_NaNBox64_273 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_273, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd+8), + ret_val_NaNBox64_273); + setArg(call_NaNBox64_273, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_273, 1, NaNBox64_273_arg0); + setRet(call_NaNBox64_273, 0, ret_val_NaNBox64_273); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 194); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 195: C__FSD */ + continuation_e __c__fsd(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rs2}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fsd"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FSD_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 195); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + rs1+8), uimm)), 64, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs2+8), 64, false), 8); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 195); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 196: C__FLDSP */ + continuation_e __c__fldsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint16_t uimm = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f {rd}, {uimm}(x2)", fmt::arg("mnemonic", "c.fldsp"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FLDSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 196); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 64, false); + auto res = gen_ext(cc, + gen_read_mem(jh, traits::MEM, offs, 8), 64, false); + InvokeNode* call_NaNBox64_274; + auto NaNBox64_274_arg0 = res; + x86::Gp ret_val_NaNBox64_274 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_NaNBox64_274, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_NaNBox64_274); + setArg(call_NaNBox64_274, 0, reinterpret_cast(this)); + setArg(call_NaNBox64_274, 1, NaNBox64_274_arg0); + setRet(call_NaNBox64_274, 0, ret_val_NaNBox64_274); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 196); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 197: C__FSDSP */ + continuation_e __c__fsdsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint16_t uimm = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} f {rs2}, {uimm}(x2), ", fmt::arg("mnemonic", "c.fsdsp"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("C__FSDSP_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 197); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+2; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + auto offs = gen_ext(cc, + (gen_operation(cc, add, load_reg_from_mem_Gp(jh, traits::X0 + 2), uimm)), 64, false); + gen_write_mem(jh, traits::MEM, offs, gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs2), 64, false), 8); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 197); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 198: SFENCE__VMA */ + continuation_e __sfence__vma(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t asid = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {asid}", fmt::arg("mnemonic", "sfence.vma"), + fmt::arg("rs1", name(rs1)), fmt::arg("asid", name(asid))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SFENCE__VMA_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 198); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + gen_write_mem(jh, traits::FENCE, static_cast(traits::fencevma), ((uint8_t)rs1<<8)|(uint8_t)asid, 8); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 198); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 199: SRET */ + continuation_e __sret(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate disass */ + + //No disass specified, using instruction name + std::string mnemonic = "sret"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("SRET_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 199); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(NO_JUMP)); + gen_leave(jh, 1); + auto returnValue = TRAP; + + gen_sync(jh, POST_SYNC, 199); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 200: VSETVLI */ + continuation_e __vsetvli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t lmul = ((bit_sub<20,3>(instr))); + uint8_t sew = ((bit_sub<23,3>(instr))); + uint8_t ta = ((bit_sub<26,1>(instr))); + uint8_t ma = ((bit_sub<27,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {sew}, {lmul}, {ta}, {ma}", fmt::arg("mnemonic", "vsetvli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("sew", sew_name(sew)), fmt::arg("lmul", lmul_name(lmul)), fmt::arg("ta", ta_name(ta)), fmt::arg("ma", ma_name(ma))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSETVLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 200); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_275; + x86::Gp ret_val_get_sew_pow_275 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_275, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_276; + x86::Gp ret_val_get_lmul_pow_276 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_276, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto orig_ratio = gen_ext(cc, + (gen_operation(cc, sub, ret_val_get_sew_pow_275, ret_val_get_lmul_pow_276)), 5, true); + setArg(call_get_sew_pow_275, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_275, 0, ret_val_get_sew_pow_275); + setArg(call_get_lmul_pow_276, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_276, 0, ret_val_get_lmul_pow_276); + auto orig_vstart = load_reg_from_mem(jh, traits::vstart); + auto tmp277 = get_reg_Gp(cc, 8, false); + mov(cc, tmp277, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp277, 64, false) + , traits::vstart); + auto tmp278 = get_reg_Gp(cc, 64, false); + mov(cc, tmp278, (uint64_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul)); + write_reg_to_mem(jh, tmp278, traits::vtype); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_valid_sew_lmul_279; + x86::Gp ret_val_valid_sew_lmul_279 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_sew_lmul_279, (uintptr_t)&vm_impl::_valid_sew_lmul, FuncSignature::build()); + auto cond = gen_operation(cc, lnot, ret_val_valid_sew_lmul_279); + setArg(call_valid_sew_lmul_279, 0, reinterpret_cast(this)); + setRet(call_valid_sew_lmul_279, 0, ret_val_valid_sew_lmul_279); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + InvokeNode* call_handle_illegal_vtype_280; + cc.invoke(&call_handle_illegal_vtype_280, (uintptr_t)&vm_impl::_handle_illegal_vtype, FuncSignature::build()); + setArg(call_handle_illegal_vtype_280, 0, reinterpret_cast(this)); + write_reg_to_mem(jh, orig_vstart, traits::vstart); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_get_pow_281; + x86::Gp ret_val_get_pow_281 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_281, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_282; + x86::Gp ret_val_get_lmul_pow_282 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_282, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_283; + x86::Gp ret_val_get_sew_pow_283 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_283, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp284 = get_reg(cc, 16, false); + mov(cc, tmp284, 1); + auto VLMAX = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp284, (gen_operation(cc, sub, gen_operation(cc, add, ret_val_get_pow_281, ret_val_get_lmul_pow_282), ret_val_get_sew_pow_283)))), 16, false), ~ 1); + setArg(call_get_pow_281, 0, reinterpret_cast(this)); + setArg(call_get_pow_281, 1, static_cast(traits::VLEN)); + setRet(call_get_pow_281, 0, ret_val_get_pow_281); + setArg(call_get_lmul_pow_282, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_282, 0, ret_val_get_lmul_pow_282); + setArg(call_get_sew_pow_283, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_283, 0, ret_val_get_sew_pow_283); + if(rs1!=0){ + auto AVL = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + InvokeNode* call_calculate_new_vl_285; + auto calculate_new_vl_285_arg0 = AVL; + auto calculate_new_vl_285_arg1 = VLMAX; + x86::Gp ret_val_calculate_new_vl_285 = get_reg_Gp(cc, 16, false); + cc.invoke(&call_calculate_new_vl_285, (uintptr_t)&vm_impl::_calculate_new_vl, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_calculate_new_vl_285, 64, false), traits::vl); + setArg(call_calculate_new_vl_285, 0, reinterpret_cast(this)); + setArg(call_calculate_new_vl_285, 1, calculate_new_vl_285_arg0); + setArg(call_calculate_new_vl_285, 2, calculate_new_vl_285_arg1); + setRet(call_calculate_new_vl_285, 0, ret_val_calculate_new_vl_285); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem(jh, traits::vl)); + } + } + else { + if(rd!=0){ + write_reg_to_mem(jh, + gen_ext(cc, VLMAX, 64, false) + , traits::vl); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + VLMAX, 64, false)); + } + else { + InvokeNode* call_get_sew_pow_286; + x86::Gp ret_val_get_sew_pow_286 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_286, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_287; + x86::Gp ret_val_get_lmul_pow_287 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_287, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto new_ratio = gen_ext(cc, + (gen_operation(cc, sub, ret_val_get_sew_pow_286, ret_val_get_lmul_pow_287)), 5, true); + setArg(call_get_sew_pow_286, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_286, 0, ret_val_get_sew_pow_286); + setArg(call_get_lmul_pow_287, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_287, 0, ret_val_get_lmul_pow_287); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, orig_ratio, new_ratio); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_handle_illegal_vtype_288; + cc.invoke(&call_handle_illegal_vtype_288, (uintptr_t)&vm_impl::_handle_illegal_vtype, FuncSignature::build()); + setArg(call_handle_illegal_vtype_288, 0, reinterpret_cast(this)); + write_reg_to_mem(jh, orig_vstart, traits::vstart); + } + cc.bind(label_merge); + } + } + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 200); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 201: VSETIVLI */ + continuation_e __vsetivli(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t uimm = ((bit_sub<15,5>(instr))); + uint8_t lmul = ((bit_sub<20,3>(instr))); + uint8_t sew = ((bit_sub<23,3>(instr))); + uint8_t ta = ((bit_sub<26,1>(instr))); + uint8_t ma = ((bit_sub<27,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm}, {sew}, {lmul}, {ta}, {ma}", fmt::arg("mnemonic", "vsetivli"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm), fmt::arg("sew", sew_name(sew)), fmt::arg("lmul", lmul_name(lmul)), fmt::arg("ta", ta_name(ta)), fmt::arg("ma", ma_name(ma))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSETIVLI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 201); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto tmp289 = get_reg_Gp(cc, 64, false); + mov(cc, tmp289, (uint64_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul)); + write_reg_to_mem(jh, tmp289, traits::vtype); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_valid_sew_lmul_290; + x86::Gp ret_val_valid_sew_lmul_290 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_sew_lmul_290, (uintptr_t)&vm_impl::_valid_sew_lmul, FuncSignature::build()); + auto cond = gen_operation(cc, lnot, ret_val_valid_sew_lmul_290); + setArg(call_valid_sew_lmul_290, 0, reinterpret_cast(this)); + setRet(call_valid_sew_lmul_290, 0, ret_val_valid_sew_lmul_290); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + InvokeNode* call_handle_illegal_vtype_291; + cc.invoke(&call_handle_illegal_vtype_291, (uintptr_t)&vm_impl::_handle_illegal_vtype, FuncSignature::build()); + setArg(call_handle_illegal_vtype_291, 0, reinterpret_cast(this)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_get_pow_292; + x86::Gp ret_val_get_pow_292 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_292, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_293; + x86::Gp ret_val_get_lmul_pow_293 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_293, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_294; + x86::Gp ret_val_get_sew_pow_294 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_294, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp295 = get_reg(cc, 16, false); + mov(cc, tmp295, 1); + auto VLMAX = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp295, (gen_operation(cc, sub, gen_operation(cc, add, ret_val_get_pow_292, ret_val_get_lmul_pow_293), ret_val_get_sew_pow_294)))), 16, false), ~ 1); + setArg(call_get_pow_292, 0, reinterpret_cast(this)); + setArg(call_get_pow_292, 1, static_cast(traits::VLEN)); + setRet(call_get_pow_292, 0, ret_val_get_pow_292); + setArg(call_get_lmul_pow_293, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_293, 0, ret_val_get_lmul_pow_293); + setArg(call_get_sew_pow_294, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_294, 0, ret_val_get_sew_pow_294); + InvokeNode* call_calculate_new_vl_296; + auto calculate_new_vl_296_arg1 = VLMAX; + x86::Gp ret_val_calculate_new_vl_296 = get_reg_Gp(cc, 16, false); + cc.invoke(&call_calculate_new_vl_296, (uintptr_t)&vm_impl::_calculate_new_vl, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_calculate_new_vl_296, 64, false) + , traits::vl); + setArg(call_calculate_new_vl_296, 0, reinterpret_cast(this)); + setArg(call_calculate_new_vl_296, 1, uimm); + setArg(call_calculate_new_vl_296, 2, calculate_new_vl_296_arg1); + setRet(call_calculate_new_vl_296, 0, ret_val_calculate_new_vl_296); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem(jh, traits::vl)); + auto tmp297 = get_reg_Gp(cc, 8, false); + mov(cc, tmp297, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp297, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 201); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 202: VSETVL */ + continuation_e __vsetvl(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "vsetvl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSETVL_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 202); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_298; + x86::Gp ret_val_get_sew_pow_298 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_298, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_299; + x86::Gp ret_val_get_lmul_pow_299 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_299, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto orig_ratio = gen_ext(cc, + (gen_operation(cc, sub, ret_val_get_sew_pow_298, ret_val_get_lmul_pow_299)), 5, true); + setArg(call_get_sew_pow_298, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_298, 0, ret_val_get_sew_pow_298); + setArg(call_get_lmul_pow_299, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_299, 0, ret_val_get_lmul_pow_299); + auto orig_vstart = load_reg_from_mem(jh, traits::vstart); + auto tmp300 = get_reg_Gp(cc, 8, false); + mov(cc, tmp300, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp300, 64, false) + , traits::vstart); + { + auto label_merge = cc.newLabel(); + auto cond = gen_slice(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 8, (static_cast(traits::XLEN)-2)-8+1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.bind(label_merge); + } + write_reg_to_mem(jh, load_reg_from_mem_Gp(jh, traits::X0 + rs2), traits::vtype); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_valid_sew_lmul_301; + x86::Gp ret_val_valid_sew_lmul_301 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_sew_lmul_301, (uintptr_t)&vm_impl::_valid_sew_lmul, FuncSignature::build()); + auto cond = gen_operation(cc, lnot, ret_val_valid_sew_lmul_301); + setArg(call_valid_sew_lmul_301, 0, reinterpret_cast(this)); + setRet(call_valid_sew_lmul_301, 0, ret_val_valid_sew_lmul_301); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + InvokeNode* call_handle_illegal_vtype_302; + cc.invoke(&call_handle_illegal_vtype_302, (uintptr_t)&vm_impl::_handle_illegal_vtype, FuncSignature::build()); + setArg(call_handle_illegal_vtype_302, 0, reinterpret_cast(this)); + write_reg_to_mem(jh, orig_vstart, traits::vstart); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_get_pow_303; + x86::Gp ret_val_get_pow_303 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_303, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_304; + x86::Gp ret_val_get_lmul_pow_304 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_304, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_305; + x86::Gp ret_val_get_sew_pow_305 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_305, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp306 = get_reg(cc, 16, false); + mov(cc, tmp306, 1); + auto VLMAX = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp306, (gen_operation(cc, sub, gen_operation(cc, add, ret_val_get_pow_303, ret_val_get_lmul_pow_304), ret_val_get_sew_pow_305)))), 16, false), ~ 1); + setArg(call_get_pow_303, 0, reinterpret_cast(this)); + setArg(call_get_pow_303, 1, static_cast(traits::VLEN)); + setRet(call_get_pow_303, 0, ret_val_get_pow_303); + setArg(call_get_lmul_pow_304, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_304, 0, ret_val_get_lmul_pow_304); + setArg(call_get_sew_pow_305, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_305, 0, ret_val_get_sew_pow_305); + if(rs1!=0){ + auto AVL = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + InvokeNode* call_calculate_new_vl_307; + auto calculate_new_vl_307_arg0 = AVL; + auto calculate_new_vl_307_arg1 = VLMAX; + x86::Gp ret_val_calculate_new_vl_307 = get_reg_Gp(cc, 16, false); + cc.invoke(&call_calculate_new_vl_307, (uintptr_t)&vm_impl::_calculate_new_vl, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_calculate_new_vl_307, 64, false), traits::vl); + setArg(call_calculate_new_vl_307, 0, reinterpret_cast(this)); + setArg(call_calculate_new_vl_307, 1, calculate_new_vl_307_arg0); + setArg(call_calculate_new_vl_307, 2, calculate_new_vl_307_arg1); + setRet(call_calculate_new_vl_307, 0, ret_val_calculate_new_vl_307); + if(rd!=0){ + mov(cc, get_ptr_for(jh, traits::X0+ rd), + load_reg_from_mem(jh, traits::vl)); + } + } + else { + if(rd!=0){ + write_reg_to_mem(jh, + gen_ext(cc, VLMAX, 64, false) + , traits::vl); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + gen_ext(cc, + VLMAX, 64, false)); + } + else { + InvokeNode* call_get_sew_pow_308; + x86::Gp ret_val_get_sew_pow_308 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_308, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_309; + x86::Gp ret_val_get_lmul_pow_309 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_309, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto new_ratio = gen_ext(cc, + (gen_operation(cc, sub, ret_val_get_sew_pow_308, ret_val_get_lmul_pow_309)), 5, true); + setArg(call_get_sew_pow_308, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_308, 0, ret_val_get_sew_pow_308); + setArg(call_get_lmul_pow_309, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_309, 0, ret_val_get_lmul_pow_309); + auto vill = gen_slice(cc, load_reg_from_mem(jh, traits::vtype), static_cast(traits::XLEN)-1, 1); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, lor, vill, (gen_operation(cc, ne, orig_ratio, new_ratio))); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_handle_illegal_vtype_310; + cc.invoke(&call_handle_illegal_vtype_310, (uintptr_t)&vm_impl::_handle_illegal_vtype, FuncSignature::build()); + setArg(call_handle_illegal_vtype_310, 0, reinterpret_cast(this)); + write_reg_to_mem(jh, orig_vstart, traits::vstart); + } + cc.bind(label_merge); + } + } + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 202); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 203: VLE8__V */ + continuation_e __vle8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 203); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_311; + x86::Gp ret_val_get_pow_311 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_311, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_312; + x86::Gp ret_val_get_sew_pow_312 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_312, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_313; + x86::Gp ret_val_get_lmul_pow_313 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_313, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_311, ret_val_get_sew_pow_312), ret_val_get_lmul_pow_313)), 3, true); + setArg(call_get_pow_311, 0, reinterpret_cast(this)); + setArg(call_get_pow_311, 1, EEW); + setRet(call_get_pow_311, 0, ret_val_get_pow_311); + setArg(call_get_sew_pow_312, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_312, 0, ret_val_get_sew_pow_312); + setArg(call_get_lmul_pow_313, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_313, 0, ret_val_get_lmul_pow_313); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_314; + auto illegal_load_314_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_314 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_314, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_314; + setArg(call_illegal_load_314, 0, reinterpret_cast(this)); + setArg(call_illegal_load_314, 1, vd); + setArg(call_illegal_load_314, 2, vm); + setArg(call_illegal_load_314, 3, 1); + setArg(call_illegal_load_314, 4, EEW); + setArg(call_illegal_load_314, 5, illegal_load_314_arg4); + setRet(call_illegal_load_314, 0, ret_val_illegal_load_314); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_315; + auto vlseg_315_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_315_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_315_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_315_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_315 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_315, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_315, 64, false), traits::vstart); + setArg(call_vlseg_315, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_315, 1, V); + setArg(call_vlseg_315, 2, vlseg_315_arg1); + setArg(call_vlseg_315, 3, vlseg_315_arg2); + setArg(call_vlseg_315, 4, vlseg_315_arg3); + setArg(call_vlseg_315, 5, vm); + setArg(call_vlseg_315, 6, vd); + setArg(call_vlseg_315, 7, vlseg_315_arg6); + setArg(call_vlseg_315, 8, 0); + setArg(call_vlseg_315, 9, 1); + setRet(call_vlseg_315, 0, ret_val_vlseg_315); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 203); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 204: VLE16__V */ + continuation_e __vle16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 204); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_316; + x86::Gp ret_val_get_pow_316 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_316, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_317; + x86::Gp ret_val_get_sew_pow_317 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_317, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_318; + x86::Gp ret_val_get_lmul_pow_318 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_318, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_316, ret_val_get_sew_pow_317), ret_val_get_lmul_pow_318)), 3, true); + setArg(call_get_pow_316, 0, reinterpret_cast(this)); + setArg(call_get_pow_316, 1, EEW); + setRet(call_get_pow_316, 0, ret_val_get_pow_316); + setArg(call_get_sew_pow_317, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_317, 0, ret_val_get_sew_pow_317); + setArg(call_get_lmul_pow_318, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_318, 0, ret_val_get_lmul_pow_318); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_319; + auto illegal_load_319_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_319 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_319, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_319; + setArg(call_illegal_load_319, 0, reinterpret_cast(this)); + setArg(call_illegal_load_319, 1, vd); + setArg(call_illegal_load_319, 2, vm); + setArg(call_illegal_load_319, 3, 1); + setArg(call_illegal_load_319, 4, EEW); + setArg(call_illegal_load_319, 5, illegal_load_319_arg4); + setRet(call_illegal_load_319, 0, ret_val_illegal_load_319); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_320; + auto vlseg_320_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_320_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_320_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_320_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_320 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_320, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_320, 64, false), traits::vstart); + setArg(call_vlseg_320, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_320, 1, V); + setArg(call_vlseg_320, 2, vlseg_320_arg1); + setArg(call_vlseg_320, 3, vlseg_320_arg2); + setArg(call_vlseg_320, 4, vlseg_320_arg3); + setArg(call_vlseg_320, 5, vm); + setArg(call_vlseg_320, 6, vd); + setArg(call_vlseg_320, 7, vlseg_320_arg6); + setArg(call_vlseg_320, 8, 5); + setArg(call_vlseg_320, 9, 1); + setRet(call_vlseg_320, 0, ret_val_vlseg_320); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 204); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 205: VLE32__V */ + continuation_e __vle32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 205); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_321; + x86::Gp ret_val_get_pow_321 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_321, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_322; + x86::Gp ret_val_get_sew_pow_322 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_322, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_323; + x86::Gp ret_val_get_lmul_pow_323 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_323, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_321, ret_val_get_sew_pow_322), ret_val_get_lmul_pow_323)), 3, true); + setArg(call_get_pow_321, 0, reinterpret_cast(this)); + setArg(call_get_pow_321, 1, EEW); + setRet(call_get_pow_321, 0, ret_val_get_pow_321); + setArg(call_get_sew_pow_322, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_322, 0, ret_val_get_sew_pow_322); + setArg(call_get_lmul_pow_323, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_323, 0, ret_val_get_lmul_pow_323); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_324; + auto illegal_load_324_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_324 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_324, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_324; + setArg(call_illegal_load_324, 0, reinterpret_cast(this)); + setArg(call_illegal_load_324, 1, vd); + setArg(call_illegal_load_324, 2, vm); + setArg(call_illegal_load_324, 3, 1); + setArg(call_illegal_load_324, 4, EEW); + setArg(call_illegal_load_324, 5, illegal_load_324_arg4); + setRet(call_illegal_load_324, 0, ret_val_illegal_load_324); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_325; + auto vlseg_325_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_325_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_325_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_325_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_325 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_325, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_325, 64, false), traits::vstart); + setArg(call_vlseg_325, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_325, 1, V); + setArg(call_vlseg_325, 2, vlseg_325_arg1); + setArg(call_vlseg_325, 3, vlseg_325_arg2); + setArg(call_vlseg_325, 4, vlseg_325_arg3); + setArg(call_vlseg_325, 5, vm); + setArg(call_vlseg_325, 6, vd); + setArg(call_vlseg_325, 7, vlseg_325_arg6); + setArg(call_vlseg_325, 8, 6); + setArg(call_vlseg_325, 9, 1); + setRet(call_vlseg_325, 0, ret_val_vlseg_325); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 205); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 206: VLE64__V */ + continuation_e __vle64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vle64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 206); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_326; + x86::Gp ret_val_get_pow_326 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_326, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_327; + x86::Gp ret_val_get_sew_pow_327 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_327, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_328; + x86::Gp ret_val_get_lmul_pow_328 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_328, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_326, ret_val_get_sew_pow_327), ret_val_get_lmul_pow_328)), 3, true); + setArg(call_get_pow_326, 0, reinterpret_cast(this)); + setArg(call_get_pow_326, 1, EEW); + setRet(call_get_pow_326, 0, ret_val_get_pow_326); + setArg(call_get_sew_pow_327, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_327, 0, ret_val_get_sew_pow_327); + setArg(call_get_lmul_pow_328, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_328, 0, ret_val_get_lmul_pow_328); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_329; + auto illegal_load_329_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_329 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_329, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_329; + setArg(call_illegal_load_329, 0, reinterpret_cast(this)); + setArg(call_illegal_load_329, 1, vd); + setArg(call_illegal_load_329, 2, vm); + setArg(call_illegal_load_329, 3, 1); + setArg(call_illegal_load_329, 4, EEW); + setArg(call_illegal_load_329, 5, illegal_load_329_arg4); + setRet(call_illegal_load_329, 0, ret_val_illegal_load_329); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_330; + auto vlseg_330_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_330_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_330_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_330_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_330 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_330, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_330, 64, false), traits::vstart); + setArg(call_vlseg_330, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_330, 1, V); + setArg(call_vlseg_330, 2, vlseg_330_arg1); + setArg(call_vlseg_330, 3, vlseg_330_arg2); + setArg(call_vlseg_330, 4, vlseg_330_arg3); + setArg(call_vlseg_330, 5, vm); + setArg(call_vlseg_330, 6, vd); + setArg(call_vlseg_330, 7, vlseg_330_arg6); + setArg(call_vlseg_330, 8, 7); + setArg(call_vlseg_330, 9, 1); + setRet(call_vlseg_330, 0, ret_val_vlseg_330); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 206); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 207: VLSEG2E8__V */ + continuation_e __vlseg2e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 207); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_331; + x86::Gp ret_val_get_pow_331 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_331, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_332; + x86::Gp ret_val_get_sew_pow_332 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_332, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_333; + x86::Gp ret_val_get_lmul_pow_333 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_333, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_331, ret_val_get_sew_pow_332), ret_val_get_lmul_pow_333)), 3, true); + setArg(call_get_pow_331, 0, reinterpret_cast(this)); + setArg(call_get_pow_331, 1, EEW); + setRet(call_get_pow_331, 0, ret_val_get_pow_331); + setArg(call_get_sew_pow_332, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_332, 0, ret_val_get_sew_pow_332); + setArg(call_get_lmul_pow_333, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_333, 0, ret_val_get_lmul_pow_333); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_334; + auto illegal_load_334_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_334 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_334, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_334; + setArg(call_illegal_load_334, 0, reinterpret_cast(this)); + setArg(call_illegal_load_334, 1, vd); + setArg(call_illegal_load_334, 2, vm); + setArg(call_illegal_load_334, 3, 2); + setArg(call_illegal_load_334, 4, EEW); + setArg(call_illegal_load_334, 5, illegal_load_334_arg4); + setRet(call_illegal_load_334, 0, ret_val_illegal_load_334); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_335; + auto vlseg_335_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_335_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_335_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_335_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_335 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_335, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_335, 64, false), traits::vstart); + setArg(call_vlseg_335, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_335, 1, V); + setArg(call_vlseg_335, 2, vlseg_335_arg1); + setArg(call_vlseg_335, 3, vlseg_335_arg2); + setArg(call_vlseg_335, 4, vlseg_335_arg3); + setArg(call_vlseg_335, 5, vm); + setArg(call_vlseg_335, 6, vd); + setArg(call_vlseg_335, 7, vlseg_335_arg6); + setArg(call_vlseg_335, 8, 0); + setArg(call_vlseg_335, 9, 2); + setRet(call_vlseg_335, 0, ret_val_vlseg_335); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 207); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 208: VLSEG2E16__V */ + continuation_e __vlseg2e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 208); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_336; + x86::Gp ret_val_get_pow_336 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_336, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_337; + x86::Gp ret_val_get_sew_pow_337 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_337, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_338; + x86::Gp ret_val_get_lmul_pow_338 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_338, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_336, ret_val_get_sew_pow_337), ret_val_get_lmul_pow_338)), 3, true); + setArg(call_get_pow_336, 0, reinterpret_cast(this)); + setArg(call_get_pow_336, 1, EEW); + setRet(call_get_pow_336, 0, ret_val_get_pow_336); + setArg(call_get_sew_pow_337, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_337, 0, ret_val_get_sew_pow_337); + setArg(call_get_lmul_pow_338, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_338, 0, ret_val_get_lmul_pow_338); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_339; + auto illegal_load_339_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_339 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_339, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_339; + setArg(call_illegal_load_339, 0, reinterpret_cast(this)); + setArg(call_illegal_load_339, 1, vd); + setArg(call_illegal_load_339, 2, vm); + setArg(call_illegal_load_339, 3, 2); + setArg(call_illegal_load_339, 4, EEW); + setArg(call_illegal_load_339, 5, illegal_load_339_arg4); + setRet(call_illegal_load_339, 0, ret_val_illegal_load_339); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_340; + auto vlseg_340_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_340_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_340_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_340_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_340 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_340, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_340, 64, false), traits::vstart); + setArg(call_vlseg_340, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_340, 1, V); + setArg(call_vlseg_340, 2, vlseg_340_arg1); + setArg(call_vlseg_340, 3, vlseg_340_arg2); + setArg(call_vlseg_340, 4, vlseg_340_arg3); + setArg(call_vlseg_340, 5, vm); + setArg(call_vlseg_340, 6, vd); + setArg(call_vlseg_340, 7, vlseg_340_arg6); + setArg(call_vlseg_340, 8, 5); + setArg(call_vlseg_340, 9, 2); + setRet(call_vlseg_340, 0, ret_val_vlseg_340); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 208); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 209: VLSEG2E32__V */ + continuation_e __vlseg2e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 209); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_341; + x86::Gp ret_val_get_pow_341 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_341, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_342; + x86::Gp ret_val_get_sew_pow_342 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_342, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_343; + x86::Gp ret_val_get_lmul_pow_343 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_343, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_341, ret_val_get_sew_pow_342), ret_val_get_lmul_pow_343)), 3, true); + setArg(call_get_pow_341, 0, reinterpret_cast(this)); + setArg(call_get_pow_341, 1, EEW); + setRet(call_get_pow_341, 0, ret_val_get_pow_341); + setArg(call_get_sew_pow_342, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_342, 0, ret_val_get_sew_pow_342); + setArg(call_get_lmul_pow_343, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_343, 0, ret_val_get_lmul_pow_343); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_344; + auto illegal_load_344_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_344 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_344, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_344; + setArg(call_illegal_load_344, 0, reinterpret_cast(this)); + setArg(call_illegal_load_344, 1, vd); + setArg(call_illegal_load_344, 2, vm); + setArg(call_illegal_load_344, 3, 2); + setArg(call_illegal_load_344, 4, EEW); + setArg(call_illegal_load_344, 5, illegal_load_344_arg4); + setRet(call_illegal_load_344, 0, ret_val_illegal_load_344); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_345; + auto vlseg_345_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_345_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_345_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_345_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_345 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_345, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_345, 64, false), traits::vstart); + setArg(call_vlseg_345, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_345, 1, V); + setArg(call_vlseg_345, 2, vlseg_345_arg1); + setArg(call_vlseg_345, 3, vlseg_345_arg2); + setArg(call_vlseg_345, 4, vlseg_345_arg3); + setArg(call_vlseg_345, 5, vm); + setArg(call_vlseg_345, 6, vd); + setArg(call_vlseg_345, 7, vlseg_345_arg6); + setArg(call_vlseg_345, 8, 6); + setArg(call_vlseg_345, 9, 2); + setRet(call_vlseg_345, 0, ret_val_vlseg_345); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 209); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 210: VLSEG2E64__V */ + continuation_e __vlseg2e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg2e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 210); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_346; + x86::Gp ret_val_get_pow_346 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_346, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_347; + x86::Gp ret_val_get_sew_pow_347 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_347, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_348; + x86::Gp ret_val_get_lmul_pow_348 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_348, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_346, ret_val_get_sew_pow_347), ret_val_get_lmul_pow_348)), 3, true); + setArg(call_get_pow_346, 0, reinterpret_cast(this)); + setArg(call_get_pow_346, 1, EEW); + setRet(call_get_pow_346, 0, ret_val_get_pow_346); + setArg(call_get_sew_pow_347, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_347, 0, ret_val_get_sew_pow_347); + setArg(call_get_lmul_pow_348, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_348, 0, ret_val_get_lmul_pow_348); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_349; + auto illegal_load_349_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_349 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_349, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_349; + setArg(call_illegal_load_349, 0, reinterpret_cast(this)); + setArg(call_illegal_load_349, 1, vd); + setArg(call_illegal_load_349, 2, vm); + setArg(call_illegal_load_349, 3, 2); + setArg(call_illegal_load_349, 4, EEW); + setArg(call_illegal_load_349, 5, illegal_load_349_arg4); + setRet(call_illegal_load_349, 0, ret_val_illegal_load_349); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_350; + auto vlseg_350_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_350_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_350_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_350_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_350 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_350, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_350, 64, false), traits::vstart); + setArg(call_vlseg_350, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_350, 1, V); + setArg(call_vlseg_350, 2, vlseg_350_arg1); + setArg(call_vlseg_350, 3, vlseg_350_arg2); + setArg(call_vlseg_350, 4, vlseg_350_arg3); + setArg(call_vlseg_350, 5, vm); + setArg(call_vlseg_350, 6, vd); + setArg(call_vlseg_350, 7, vlseg_350_arg6); + setArg(call_vlseg_350, 8, 7); + setArg(call_vlseg_350, 9, 2); + setRet(call_vlseg_350, 0, ret_val_vlseg_350); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 210); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 211: VLSEG3E8__V */ + continuation_e __vlseg3e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 211); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_351; + x86::Gp ret_val_get_pow_351 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_351, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_352; + x86::Gp ret_val_get_sew_pow_352 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_352, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_353; + x86::Gp ret_val_get_lmul_pow_353 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_353, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_351, ret_val_get_sew_pow_352), ret_val_get_lmul_pow_353)), 3, true); + setArg(call_get_pow_351, 0, reinterpret_cast(this)); + setArg(call_get_pow_351, 1, EEW); + setRet(call_get_pow_351, 0, ret_val_get_pow_351); + setArg(call_get_sew_pow_352, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_352, 0, ret_val_get_sew_pow_352); + setArg(call_get_lmul_pow_353, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_353, 0, ret_val_get_lmul_pow_353); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_354; + auto illegal_load_354_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_354 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_354, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_354; + setArg(call_illegal_load_354, 0, reinterpret_cast(this)); + setArg(call_illegal_load_354, 1, vd); + setArg(call_illegal_load_354, 2, vm); + setArg(call_illegal_load_354, 3, 3); + setArg(call_illegal_load_354, 4, EEW); + setArg(call_illegal_load_354, 5, illegal_load_354_arg4); + setRet(call_illegal_load_354, 0, ret_val_illegal_load_354); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_355; + auto vlseg_355_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_355_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_355_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_355_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_355 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_355, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_355, 64, false), traits::vstart); + setArg(call_vlseg_355, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_355, 1, V); + setArg(call_vlseg_355, 2, vlseg_355_arg1); + setArg(call_vlseg_355, 3, vlseg_355_arg2); + setArg(call_vlseg_355, 4, vlseg_355_arg3); + setArg(call_vlseg_355, 5, vm); + setArg(call_vlseg_355, 6, vd); + setArg(call_vlseg_355, 7, vlseg_355_arg6); + setArg(call_vlseg_355, 8, 0); + setArg(call_vlseg_355, 9, 3); + setRet(call_vlseg_355, 0, ret_val_vlseg_355); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 211); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 212: VLSEG3E16__V */ + continuation_e __vlseg3e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 212); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_356; + x86::Gp ret_val_get_pow_356 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_356, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_357; + x86::Gp ret_val_get_sew_pow_357 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_357, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_358; + x86::Gp ret_val_get_lmul_pow_358 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_358, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_356, ret_val_get_sew_pow_357), ret_val_get_lmul_pow_358)), 3, true); + setArg(call_get_pow_356, 0, reinterpret_cast(this)); + setArg(call_get_pow_356, 1, EEW); + setRet(call_get_pow_356, 0, ret_val_get_pow_356); + setArg(call_get_sew_pow_357, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_357, 0, ret_val_get_sew_pow_357); + setArg(call_get_lmul_pow_358, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_358, 0, ret_val_get_lmul_pow_358); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_359; + auto illegal_load_359_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_359 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_359, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_359; + setArg(call_illegal_load_359, 0, reinterpret_cast(this)); + setArg(call_illegal_load_359, 1, vd); + setArg(call_illegal_load_359, 2, vm); + setArg(call_illegal_load_359, 3, 3); + setArg(call_illegal_load_359, 4, EEW); + setArg(call_illegal_load_359, 5, illegal_load_359_arg4); + setRet(call_illegal_load_359, 0, ret_val_illegal_load_359); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_360; + auto vlseg_360_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_360_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_360_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_360_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_360 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_360, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_360, 64, false), traits::vstart); + setArg(call_vlseg_360, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_360, 1, V); + setArg(call_vlseg_360, 2, vlseg_360_arg1); + setArg(call_vlseg_360, 3, vlseg_360_arg2); + setArg(call_vlseg_360, 4, vlseg_360_arg3); + setArg(call_vlseg_360, 5, vm); + setArg(call_vlseg_360, 6, vd); + setArg(call_vlseg_360, 7, vlseg_360_arg6); + setArg(call_vlseg_360, 8, 5); + setArg(call_vlseg_360, 9, 3); + setRet(call_vlseg_360, 0, ret_val_vlseg_360); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 212); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 213: VLSEG3E32__V */ + continuation_e __vlseg3e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 213); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_361; + x86::Gp ret_val_get_pow_361 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_361, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_362; + x86::Gp ret_val_get_sew_pow_362 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_362, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_363; + x86::Gp ret_val_get_lmul_pow_363 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_363, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_361, ret_val_get_sew_pow_362), ret_val_get_lmul_pow_363)), 3, true); + setArg(call_get_pow_361, 0, reinterpret_cast(this)); + setArg(call_get_pow_361, 1, EEW); + setRet(call_get_pow_361, 0, ret_val_get_pow_361); + setArg(call_get_sew_pow_362, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_362, 0, ret_val_get_sew_pow_362); + setArg(call_get_lmul_pow_363, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_363, 0, ret_val_get_lmul_pow_363); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_364; + auto illegal_load_364_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_364 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_364, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_364; + setArg(call_illegal_load_364, 0, reinterpret_cast(this)); + setArg(call_illegal_load_364, 1, vd); + setArg(call_illegal_load_364, 2, vm); + setArg(call_illegal_load_364, 3, 3); + setArg(call_illegal_load_364, 4, EEW); + setArg(call_illegal_load_364, 5, illegal_load_364_arg4); + setRet(call_illegal_load_364, 0, ret_val_illegal_load_364); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_365; + auto vlseg_365_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_365_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_365_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_365_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_365 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_365, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_365, 64, false), traits::vstart); + setArg(call_vlseg_365, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_365, 1, V); + setArg(call_vlseg_365, 2, vlseg_365_arg1); + setArg(call_vlseg_365, 3, vlseg_365_arg2); + setArg(call_vlseg_365, 4, vlseg_365_arg3); + setArg(call_vlseg_365, 5, vm); + setArg(call_vlseg_365, 6, vd); + setArg(call_vlseg_365, 7, vlseg_365_arg6); + setArg(call_vlseg_365, 8, 6); + setArg(call_vlseg_365, 9, 3); + setRet(call_vlseg_365, 0, ret_val_vlseg_365); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 213); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 214: VLSEG3E64__V */ + continuation_e __vlseg3e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg3e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 214); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_366; + x86::Gp ret_val_get_pow_366 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_366, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_367; + x86::Gp ret_val_get_sew_pow_367 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_367, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_368; + x86::Gp ret_val_get_lmul_pow_368 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_368, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_366, ret_val_get_sew_pow_367), ret_val_get_lmul_pow_368)), 3, true); + setArg(call_get_pow_366, 0, reinterpret_cast(this)); + setArg(call_get_pow_366, 1, EEW); + setRet(call_get_pow_366, 0, ret_val_get_pow_366); + setArg(call_get_sew_pow_367, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_367, 0, ret_val_get_sew_pow_367); + setArg(call_get_lmul_pow_368, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_368, 0, ret_val_get_lmul_pow_368); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_369; + auto illegal_load_369_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_369 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_369, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_369; + setArg(call_illegal_load_369, 0, reinterpret_cast(this)); + setArg(call_illegal_load_369, 1, vd); + setArg(call_illegal_load_369, 2, vm); + setArg(call_illegal_load_369, 3, 3); + setArg(call_illegal_load_369, 4, EEW); + setArg(call_illegal_load_369, 5, illegal_load_369_arg4); + setRet(call_illegal_load_369, 0, ret_val_illegal_load_369); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_370; + auto vlseg_370_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_370_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_370_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_370_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_370 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_370, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_370, 64, false), traits::vstart); + setArg(call_vlseg_370, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_370, 1, V); + setArg(call_vlseg_370, 2, vlseg_370_arg1); + setArg(call_vlseg_370, 3, vlseg_370_arg2); + setArg(call_vlseg_370, 4, vlseg_370_arg3); + setArg(call_vlseg_370, 5, vm); + setArg(call_vlseg_370, 6, vd); + setArg(call_vlseg_370, 7, vlseg_370_arg6); + setArg(call_vlseg_370, 8, 7); + setArg(call_vlseg_370, 9, 3); + setRet(call_vlseg_370, 0, ret_val_vlseg_370); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 214); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 215: VLSEG4E8__V */ + continuation_e __vlseg4e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 215); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_371; + x86::Gp ret_val_get_pow_371 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_371, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_372; + x86::Gp ret_val_get_sew_pow_372 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_372, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_373; + x86::Gp ret_val_get_lmul_pow_373 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_373, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_371, ret_val_get_sew_pow_372), ret_val_get_lmul_pow_373)), 3, true); + setArg(call_get_pow_371, 0, reinterpret_cast(this)); + setArg(call_get_pow_371, 1, EEW); + setRet(call_get_pow_371, 0, ret_val_get_pow_371); + setArg(call_get_sew_pow_372, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_372, 0, ret_val_get_sew_pow_372); + setArg(call_get_lmul_pow_373, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_373, 0, ret_val_get_lmul_pow_373); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_374; + auto illegal_load_374_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_374 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_374, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_374; + setArg(call_illegal_load_374, 0, reinterpret_cast(this)); + setArg(call_illegal_load_374, 1, vd); + setArg(call_illegal_load_374, 2, vm); + setArg(call_illegal_load_374, 3, 4); + setArg(call_illegal_load_374, 4, EEW); + setArg(call_illegal_load_374, 5, illegal_load_374_arg4); + setRet(call_illegal_load_374, 0, ret_val_illegal_load_374); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_375; + auto vlseg_375_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_375_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_375_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_375_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_375 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_375, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_375, 64, false), traits::vstart); + setArg(call_vlseg_375, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_375, 1, V); + setArg(call_vlseg_375, 2, vlseg_375_arg1); + setArg(call_vlseg_375, 3, vlseg_375_arg2); + setArg(call_vlseg_375, 4, vlseg_375_arg3); + setArg(call_vlseg_375, 5, vm); + setArg(call_vlseg_375, 6, vd); + setArg(call_vlseg_375, 7, vlseg_375_arg6); + setArg(call_vlseg_375, 8, 0); + setArg(call_vlseg_375, 9, 4); + setRet(call_vlseg_375, 0, ret_val_vlseg_375); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 215); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 216: VLSEG4E16__V */ + continuation_e __vlseg4e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 216); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_376; + x86::Gp ret_val_get_pow_376 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_376, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_377; + x86::Gp ret_val_get_sew_pow_377 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_377, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_378; + x86::Gp ret_val_get_lmul_pow_378 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_378, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_376, ret_val_get_sew_pow_377), ret_val_get_lmul_pow_378)), 3, true); + setArg(call_get_pow_376, 0, reinterpret_cast(this)); + setArg(call_get_pow_376, 1, EEW); + setRet(call_get_pow_376, 0, ret_val_get_pow_376); + setArg(call_get_sew_pow_377, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_377, 0, ret_val_get_sew_pow_377); + setArg(call_get_lmul_pow_378, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_378, 0, ret_val_get_lmul_pow_378); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_379; + auto illegal_load_379_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_379 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_379, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_379; + setArg(call_illegal_load_379, 0, reinterpret_cast(this)); + setArg(call_illegal_load_379, 1, vd); + setArg(call_illegal_load_379, 2, vm); + setArg(call_illegal_load_379, 3, 4); + setArg(call_illegal_load_379, 4, EEW); + setArg(call_illegal_load_379, 5, illegal_load_379_arg4); + setRet(call_illegal_load_379, 0, ret_val_illegal_load_379); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_380; + auto vlseg_380_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_380_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_380_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_380_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_380 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_380, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_380, 64, false), traits::vstart); + setArg(call_vlseg_380, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_380, 1, V); + setArg(call_vlseg_380, 2, vlseg_380_arg1); + setArg(call_vlseg_380, 3, vlseg_380_arg2); + setArg(call_vlseg_380, 4, vlseg_380_arg3); + setArg(call_vlseg_380, 5, vm); + setArg(call_vlseg_380, 6, vd); + setArg(call_vlseg_380, 7, vlseg_380_arg6); + setArg(call_vlseg_380, 8, 5); + setArg(call_vlseg_380, 9, 4); + setRet(call_vlseg_380, 0, ret_val_vlseg_380); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 216); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 217: VLSEG4E32__V */ + continuation_e __vlseg4e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 217); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_381; + x86::Gp ret_val_get_pow_381 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_381, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_382; + x86::Gp ret_val_get_sew_pow_382 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_382, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_383; + x86::Gp ret_val_get_lmul_pow_383 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_383, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_381, ret_val_get_sew_pow_382), ret_val_get_lmul_pow_383)), 3, true); + setArg(call_get_pow_381, 0, reinterpret_cast(this)); + setArg(call_get_pow_381, 1, EEW); + setRet(call_get_pow_381, 0, ret_val_get_pow_381); + setArg(call_get_sew_pow_382, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_382, 0, ret_val_get_sew_pow_382); + setArg(call_get_lmul_pow_383, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_383, 0, ret_val_get_lmul_pow_383); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_384; + auto illegal_load_384_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_384 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_384, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_384; + setArg(call_illegal_load_384, 0, reinterpret_cast(this)); + setArg(call_illegal_load_384, 1, vd); + setArg(call_illegal_load_384, 2, vm); + setArg(call_illegal_load_384, 3, 4); + setArg(call_illegal_load_384, 4, EEW); + setArg(call_illegal_load_384, 5, illegal_load_384_arg4); + setRet(call_illegal_load_384, 0, ret_val_illegal_load_384); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_385; + auto vlseg_385_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_385_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_385_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_385_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_385 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_385, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_385, 64, false), traits::vstart); + setArg(call_vlseg_385, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_385, 1, V); + setArg(call_vlseg_385, 2, vlseg_385_arg1); + setArg(call_vlseg_385, 3, vlseg_385_arg2); + setArg(call_vlseg_385, 4, vlseg_385_arg3); + setArg(call_vlseg_385, 5, vm); + setArg(call_vlseg_385, 6, vd); + setArg(call_vlseg_385, 7, vlseg_385_arg6); + setArg(call_vlseg_385, 8, 6); + setArg(call_vlseg_385, 9, 4); + setRet(call_vlseg_385, 0, ret_val_vlseg_385); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 217); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 218: VLSEG4E64__V */ + continuation_e __vlseg4e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg4e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 218); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_386; + x86::Gp ret_val_get_pow_386 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_386, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_387; + x86::Gp ret_val_get_sew_pow_387 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_387, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_388; + x86::Gp ret_val_get_lmul_pow_388 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_388, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_386, ret_val_get_sew_pow_387), ret_val_get_lmul_pow_388)), 3, true); + setArg(call_get_pow_386, 0, reinterpret_cast(this)); + setArg(call_get_pow_386, 1, EEW); + setRet(call_get_pow_386, 0, ret_val_get_pow_386); + setArg(call_get_sew_pow_387, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_387, 0, ret_val_get_sew_pow_387); + setArg(call_get_lmul_pow_388, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_388, 0, ret_val_get_lmul_pow_388); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_389; + auto illegal_load_389_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_389 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_389, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_389; + setArg(call_illegal_load_389, 0, reinterpret_cast(this)); + setArg(call_illegal_load_389, 1, vd); + setArg(call_illegal_load_389, 2, vm); + setArg(call_illegal_load_389, 3, 4); + setArg(call_illegal_load_389, 4, EEW); + setArg(call_illegal_load_389, 5, illegal_load_389_arg4); + setRet(call_illegal_load_389, 0, ret_val_illegal_load_389); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_390; + auto vlseg_390_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_390_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_390_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_390_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_390 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_390, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_390, 64, false), traits::vstart); + setArg(call_vlseg_390, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_390, 1, V); + setArg(call_vlseg_390, 2, vlseg_390_arg1); + setArg(call_vlseg_390, 3, vlseg_390_arg2); + setArg(call_vlseg_390, 4, vlseg_390_arg3); + setArg(call_vlseg_390, 5, vm); + setArg(call_vlseg_390, 6, vd); + setArg(call_vlseg_390, 7, vlseg_390_arg6); + setArg(call_vlseg_390, 8, 7); + setArg(call_vlseg_390, 9, 4); + setRet(call_vlseg_390, 0, ret_val_vlseg_390); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 218); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 219: VLSEG5E8__V */ + continuation_e __vlseg5e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 219); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_391; + x86::Gp ret_val_get_pow_391 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_391, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_392; + x86::Gp ret_val_get_sew_pow_392 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_392, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_393; + x86::Gp ret_val_get_lmul_pow_393 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_393, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_391, ret_val_get_sew_pow_392), ret_val_get_lmul_pow_393)), 3, true); + setArg(call_get_pow_391, 0, reinterpret_cast(this)); + setArg(call_get_pow_391, 1, EEW); + setRet(call_get_pow_391, 0, ret_val_get_pow_391); + setArg(call_get_sew_pow_392, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_392, 0, ret_val_get_sew_pow_392); + setArg(call_get_lmul_pow_393, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_393, 0, ret_val_get_lmul_pow_393); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_394; + auto illegal_load_394_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_394 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_394, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_394; + setArg(call_illegal_load_394, 0, reinterpret_cast(this)); + setArg(call_illegal_load_394, 1, vd); + setArg(call_illegal_load_394, 2, vm); + setArg(call_illegal_load_394, 3, 5); + setArg(call_illegal_load_394, 4, EEW); + setArg(call_illegal_load_394, 5, illegal_load_394_arg4); + setRet(call_illegal_load_394, 0, ret_val_illegal_load_394); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_395; + auto vlseg_395_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_395_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_395_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_395_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_395 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_395, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_395, 64, false), traits::vstart); + setArg(call_vlseg_395, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_395, 1, V); + setArg(call_vlseg_395, 2, vlseg_395_arg1); + setArg(call_vlseg_395, 3, vlseg_395_arg2); + setArg(call_vlseg_395, 4, vlseg_395_arg3); + setArg(call_vlseg_395, 5, vm); + setArg(call_vlseg_395, 6, vd); + setArg(call_vlseg_395, 7, vlseg_395_arg6); + setArg(call_vlseg_395, 8, 0); + setArg(call_vlseg_395, 9, 5); + setRet(call_vlseg_395, 0, ret_val_vlseg_395); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 219); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 220: VLSEG5E16__V */ + continuation_e __vlseg5e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 220); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_396; + x86::Gp ret_val_get_pow_396 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_396, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_397; + x86::Gp ret_val_get_sew_pow_397 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_397, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_398; + x86::Gp ret_val_get_lmul_pow_398 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_398, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_396, ret_val_get_sew_pow_397), ret_val_get_lmul_pow_398)), 3, true); + setArg(call_get_pow_396, 0, reinterpret_cast(this)); + setArg(call_get_pow_396, 1, EEW); + setRet(call_get_pow_396, 0, ret_val_get_pow_396); + setArg(call_get_sew_pow_397, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_397, 0, ret_val_get_sew_pow_397); + setArg(call_get_lmul_pow_398, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_398, 0, ret_val_get_lmul_pow_398); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_399; + auto illegal_load_399_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_399 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_399, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_399; + setArg(call_illegal_load_399, 0, reinterpret_cast(this)); + setArg(call_illegal_load_399, 1, vd); + setArg(call_illegal_load_399, 2, vm); + setArg(call_illegal_load_399, 3, 5); + setArg(call_illegal_load_399, 4, EEW); + setArg(call_illegal_load_399, 5, illegal_load_399_arg4); + setRet(call_illegal_load_399, 0, ret_val_illegal_load_399); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_400; + auto vlseg_400_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_400_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_400_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_400_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_400 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_400, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_400, 64, false), traits::vstart); + setArg(call_vlseg_400, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_400, 1, V); + setArg(call_vlseg_400, 2, vlseg_400_arg1); + setArg(call_vlseg_400, 3, vlseg_400_arg2); + setArg(call_vlseg_400, 4, vlseg_400_arg3); + setArg(call_vlseg_400, 5, vm); + setArg(call_vlseg_400, 6, vd); + setArg(call_vlseg_400, 7, vlseg_400_arg6); + setArg(call_vlseg_400, 8, 5); + setArg(call_vlseg_400, 9, 5); + setRet(call_vlseg_400, 0, ret_val_vlseg_400); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 220); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 221: VLSEG5E32__V */ + continuation_e __vlseg5e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 221); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_401; + x86::Gp ret_val_get_pow_401 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_401, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_402; + x86::Gp ret_val_get_sew_pow_402 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_402, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_403; + x86::Gp ret_val_get_lmul_pow_403 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_403, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_401, ret_val_get_sew_pow_402), ret_val_get_lmul_pow_403)), 3, true); + setArg(call_get_pow_401, 0, reinterpret_cast(this)); + setArg(call_get_pow_401, 1, EEW); + setRet(call_get_pow_401, 0, ret_val_get_pow_401); + setArg(call_get_sew_pow_402, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_402, 0, ret_val_get_sew_pow_402); + setArg(call_get_lmul_pow_403, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_403, 0, ret_val_get_lmul_pow_403); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_404; + auto illegal_load_404_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_404 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_404, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_404; + setArg(call_illegal_load_404, 0, reinterpret_cast(this)); + setArg(call_illegal_load_404, 1, vd); + setArg(call_illegal_load_404, 2, vm); + setArg(call_illegal_load_404, 3, 5); + setArg(call_illegal_load_404, 4, EEW); + setArg(call_illegal_load_404, 5, illegal_load_404_arg4); + setRet(call_illegal_load_404, 0, ret_val_illegal_load_404); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_405; + auto vlseg_405_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_405_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_405_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_405_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_405 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_405, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_405, 64, false), traits::vstart); + setArg(call_vlseg_405, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_405, 1, V); + setArg(call_vlseg_405, 2, vlseg_405_arg1); + setArg(call_vlseg_405, 3, vlseg_405_arg2); + setArg(call_vlseg_405, 4, vlseg_405_arg3); + setArg(call_vlseg_405, 5, vm); + setArg(call_vlseg_405, 6, vd); + setArg(call_vlseg_405, 7, vlseg_405_arg6); + setArg(call_vlseg_405, 8, 6); + setArg(call_vlseg_405, 9, 5); + setRet(call_vlseg_405, 0, ret_val_vlseg_405); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 221); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 222: VLSEG5E64__V */ + continuation_e __vlseg5e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg5e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 222); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_406; + x86::Gp ret_val_get_pow_406 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_406, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_407; + x86::Gp ret_val_get_sew_pow_407 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_407, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_408; + x86::Gp ret_val_get_lmul_pow_408 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_408, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_406, ret_val_get_sew_pow_407), ret_val_get_lmul_pow_408)), 3, true); + setArg(call_get_pow_406, 0, reinterpret_cast(this)); + setArg(call_get_pow_406, 1, EEW); + setRet(call_get_pow_406, 0, ret_val_get_pow_406); + setArg(call_get_sew_pow_407, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_407, 0, ret_val_get_sew_pow_407); + setArg(call_get_lmul_pow_408, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_408, 0, ret_val_get_lmul_pow_408); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_409; + auto illegal_load_409_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_409 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_409, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_409; + setArg(call_illegal_load_409, 0, reinterpret_cast(this)); + setArg(call_illegal_load_409, 1, vd); + setArg(call_illegal_load_409, 2, vm); + setArg(call_illegal_load_409, 3, 5); + setArg(call_illegal_load_409, 4, EEW); + setArg(call_illegal_load_409, 5, illegal_load_409_arg4); + setRet(call_illegal_load_409, 0, ret_val_illegal_load_409); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_410; + auto vlseg_410_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_410_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_410_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_410_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_410 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_410, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_410, 64, false), traits::vstart); + setArg(call_vlseg_410, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_410, 1, V); + setArg(call_vlseg_410, 2, vlseg_410_arg1); + setArg(call_vlseg_410, 3, vlseg_410_arg2); + setArg(call_vlseg_410, 4, vlseg_410_arg3); + setArg(call_vlseg_410, 5, vm); + setArg(call_vlseg_410, 6, vd); + setArg(call_vlseg_410, 7, vlseg_410_arg6); + setArg(call_vlseg_410, 8, 7); + setArg(call_vlseg_410, 9, 5); + setRet(call_vlseg_410, 0, ret_val_vlseg_410); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 222); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 223: VLSEG6E8__V */ + continuation_e __vlseg6e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 223); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_411; + x86::Gp ret_val_get_pow_411 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_411, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_412; + x86::Gp ret_val_get_sew_pow_412 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_412, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_413; + x86::Gp ret_val_get_lmul_pow_413 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_413, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_411, ret_val_get_sew_pow_412), ret_val_get_lmul_pow_413)), 3, true); + setArg(call_get_pow_411, 0, reinterpret_cast(this)); + setArg(call_get_pow_411, 1, EEW); + setRet(call_get_pow_411, 0, ret_val_get_pow_411); + setArg(call_get_sew_pow_412, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_412, 0, ret_val_get_sew_pow_412); + setArg(call_get_lmul_pow_413, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_413, 0, ret_val_get_lmul_pow_413); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_414; + auto illegal_load_414_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_414 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_414, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_414; + setArg(call_illegal_load_414, 0, reinterpret_cast(this)); + setArg(call_illegal_load_414, 1, vd); + setArg(call_illegal_load_414, 2, vm); + setArg(call_illegal_load_414, 3, 6); + setArg(call_illegal_load_414, 4, EEW); + setArg(call_illegal_load_414, 5, illegal_load_414_arg4); + setRet(call_illegal_load_414, 0, ret_val_illegal_load_414); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_415; + auto vlseg_415_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_415_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_415_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_415_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_415 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_415, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_415, 64, false), traits::vstart); + setArg(call_vlseg_415, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_415, 1, V); + setArg(call_vlseg_415, 2, vlseg_415_arg1); + setArg(call_vlseg_415, 3, vlseg_415_arg2); + setArg(call_vlseg_415, 4, vlseg_415_arg3); + setArg(call_vlseg_415, 5, vm); + setArg(call_vlseg_415, 6, vd); + setArg(call_vlseg_415, 7, vlseg_415_arg6); + setArg(call_vlseg_415, 8, 0); + setArg(call_vlseg_415, 9, 6); + setRet(call_vlseg_415, 0, ret_val_vlseg_415); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 223); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 224: VLSEG6E16__V */ + continuation_e __vlseg6e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 224); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_416; + x86::Gp ret_val_get_pow_416 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_416, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_417; + x86::Gp ret_val_get_sew_pow_417 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_417, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_418; + x86::Gp ret_val_get_lmul_pow_418 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_418, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_416, ret_val_get_sew_pow_417), ret_val_get_lmul_pow_418)), 3, true); + setArg(call_get_pow_416, 0, reinterpret_cast(this)); + setArg(call_get_pow_416, 1, EEW); + setRet(call_get_pow_416, 0, ret_val_get_pow_416); + setArg(call_get_sew_pow_417, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_417, 0, ret_val_get_sew_pow_417); + setArg(call_get_lmul_pow_418, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_418, 0, ret_val_get_lmul_pow_418); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_419; + auto illegal_load_419_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_419 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_419, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_419; + setArg(call_illegal_load_419, 0, reinterpret_cast(this)); + setArg(call_illegal_load_419, 1, vd); + setArg(call_illegal_load_419, 2, vm); + setArg(call_illegal_load_419, 3, 6); + setArg(call_illegal_load_419, 4, EEW); + setArg(call_illegal_load_419, 5, illegal_load_419_arg4); + setRet(call_illegal_load_419, 0, ret_val_illegal_load_419); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_420; + auto vlseg_420_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_420_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_420_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_420_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_420 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_420, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_420, 64, false), traits::vstart); + setArg(call_vlseg_420, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_420, 1, V); + setArg(call_vlseg_420, 2, vlseg_420_arg1); + setArg(call_vlseg_420, 3, vlseg_420_arg2); + setArg(call_vlseg_420, 4, vlseg_420_arg3); + setArg(call_vlseg_420, 5, vm); + setArg(call_vlseg_420, 6, vd); + setArg(call_vlseg_420, 7, vlseg_420_arg6); + setArg(call_vlseg_420, 8, 5); + setArg(call_vlseg_420, 9, 6); + setRet(call_vlseg_420, 0, ret_val_vlseg_420); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 224); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 225: VLSEG6E32__V */ + continuation_e __vlseg6e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 225); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_421; + x86::Gp ret_val_get_pow_421 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_421, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_422; + x86::Gp ret_val_get_sew_pow_422 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_422, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_423; + x86::Gp ret_val_get_lmul_pow_423 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_423, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_421, ret_val_get_sew_pow_422), ret_val_get_lmul_pow_423)), 3, true); + setArg(call_get_pow_421, 0, reinterpret_cast(this)); + setArg(call_get_pow_421, 1, EEW); + setRet(call_get_pow_421, 0, ret_val_get_pow_421); + setArg(call_get_sew_pow_422, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_422, 0, ret_val_get_sew_pow_422); + setArg(call_get_lmul_pow_423, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_423, 0, ret_val_get_lmul_pow_423); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_424; + auto illegal_load_424_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_424 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_424, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_424; + setArg(call_illegal_load_424, 0, reinterpret_cast(this)); + setArg(call_illegal_load_424, 1, vd); + setArg(call_illegal_load_424, 2, vm); + setArg(call_illegal_load_424, 3, 6); + setArg(call_illegal_load_424, 4, EEW); + setArg(call_illegal_load_424, 5, illegal_load_424_arg4); + setRet(call_illegal_load_424, 0, ret_val_illegal_load_424); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_425; + auto vlseg_425_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_425_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_425_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_425_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_425 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_425, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_425, 64, false), traits::vstart); + setArg(call_vlseg_425, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_425, 1, V); + setArg(call_vlseg_425, 2, vlseg_425_arg1); + setArg(call_vlseg_425, 3, vlseg_425_arg2); + setArg(call_vlseg_425, 4, vlseg_425_arg3); + setArg(call_vlseg_425, 5, vm); + setArg(call_vlseg_425, 6, vd); + setArg(call_vlseg_425, 7, vlseg_425_arg6); + setArg(call_vlseg_425, 8, 6); + setArg(call_vlseg_425, 9, 6); + setRet(call_vlseg_425, 0, ret_val_vlseg_425); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 225); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 226: VLSEG6E64__V */ + continuation_e __vlseg6e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg6e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 226); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_426; + x86::Gp ret_val_get_pow_426 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_426, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_427; + x86::Gp ret_val_get_sew_pow_427 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_427, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_428; + x86::Gp ret_val_get_lmul_pow_428 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_428, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_426, ret_val_get_sew_pow_427), ret_val_get_lmul_pow_428)), 3, true); + setArg(call_get_pow_426, 0, reinterpret_cast(this)); + setArg(call_get_pow_426, 1, EEW); + setRet(call_get_pow_426, 0, ret_val_get_pow_426); + setArg(call_get_sew_pow_427, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_427, 0, ret_val_get_sew_pow_427); + setArg(call_get_lmul_pow_428, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_428, 0, ret_val_get_lmul_pow_428); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_429; + auto illegal_load_429_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_429 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_429, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_429; + setArg(call_illegal_load_429, 0, reinterpret_cast(this)); + setArg(call_illegal_load_429, 1, vd); + setArg(call_illegal_load_429, 2, vm); + setArg(call_illegal_load_429, 3, 6); + setArg(call_illegal_load_429, 4, EEW); + setArg(call_illegal_load_429, 5, illegal_load_429_arg4); + setRet(call_illegal_load_429, 0, ret_val_illegal_load_429); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_430; + auto vlseg_430_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_430_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_430_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_430_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_430 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_430, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_430, 64, false), traits::vstart); + setArg(call_vlseg_430, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_430, 1, V); + setArg(call_vlseg_430, 2, vlseg_430_arg1); + setArg(call_vlseg_430, 3, vlseg_430_arg2); + setArg(call_vlseg_430, 4, vlseg_430_arg3); + setArg(call_vlseg_430, 5, vm); + setArg(call_vlseg_430, 6, vd); + setArg(call_vlseg_430, 7, vlseg_430_arg6); + setArg(call_vlseg_430, 8, 7); + setArg(call_vlseg_430, 9, 6); + setRet(call_vlseg_430, 0, ret_val_vlseg_430); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 226); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 227: VLSEG7E8__V */ + continuation_e __vlseg7e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 227); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_431; + x86::Gp ret_val_get_pow_431 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_431, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_432; + x86::Gp ret_val_get_sew_pow_432 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_432, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_433; + x86::Gp ret_val_get_lmul_pow_433 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_433, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_431, ret_val_get_sew_pow_432), ret_val_get_lmul_pow_433)), 3, true); + setArg(call_get_pow_431, 0, reinterpret_cast(this)); + setArg(call_get_pow_431, 1, EEW); + setRet(call_get_pow_431, 0, ret_val_get_pow_431); + setArg(call_get_sew_pow_432, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_432, 0, ret_val_get_sew_pow_432); + setArg(call_get_lmul_pow_433, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_433, 0, ret_val_get_lmul_pow_433); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_434; + auto illegal_load_434_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_434 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_434, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_434; + setArg(call_illegal_load_434, 0, reinterpret_cast(this)); + setArg(call_illegal_load_434, 1, vd); + setArg(call_illegal_load_434, 2, vm); + setArg(call_illegal_load_434, 3, 7); + setArg(call_illegal_load_434, 4, EEW); + setArg(call_illegal_load_434, 5, illegal_load_434_arg4); + setRet(call_illegal_load_434, 0, ret_val_illegal_load_434); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_435; + auto vlseg_435_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_435_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_435_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_435_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_435 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_435, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_435, 64, false), traits::vstart); + setArg(call_vlseg_435, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_435, 1, V); + setArg(call_vlseg_435, 2, vlseg_435_arg1); + setArg(call_vlseg_435, 3, vlseg_435_arg2); + setArg(call_vlseg_435, 4, vlseg_435_arg3); + setArg(call_vlseg_435, 5, vm); + setArg(call_vlseg_435, 6, vd); + setArg(call_vlseg_435, 7, vlseg_435_arg6); + setArg(call_vlseg_435, 8, 0); + setArg(call_vlseg_435, 9, 7); + setRet(call_vlseg_435, 0, ret_val_vlseg_435); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 227); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 228: VLSEG7E16__V */ + continuation_e __vlseg7e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 228); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_436; + x86::Gp ret_val_get_pow_436 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_436, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_437; + x86::Gp ret_val_get_sew_pow_437 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_437, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_438; + x86::Gp ret_val_get_lmul_pow_438 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_438, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_436, ret_val_get_sew_pow_437), ret_val_get_lmul_pow_438)), 3, true); + setArg(call_get_pow_436, 0, reinterpret_cast(this)); + setArg(call_get_pow_436, 1, EEW); + setRet(call_get_pow_436, 0, ret_val_get_pow_436); + setArg(call_get_sew_pow_437, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_437, 0, ret_val_get_sew_pow_437); + setArg(call_get_lmul_pow_438, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_438, 0, ret_val_get_lmul_pow_438); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_439; + auto illegal_load_439_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_439 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_439, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_439; + setArg(call_illegal_load_439, 0, reinterpret_cast(this)); + setArg(call_illegal_load_439, 1, vd); + setArg(call_illegal_load_439, 2, vm); + setArg(call_illegal_load_439, 3, 7); + setArg(call_illegal_load_439, 4, EEW); + setArg(call_illegal_load_439, 5, illegal_load_439_arg4); + setRet(call_illegal_load_439, 0, ret_val_illegal_load_439); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_440; + auto vlseg_440_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_440_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_440_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_440_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_440 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_440, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_440, 64, false), traits::vstart); + setArg(call_vlseg_440, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_440, 1, V); + setArg(call_vlseg_440, 2, vlseg_440_arg1); + setArg(call_vlseg_440, 3, vlseg_440_arg2); + setArg(call_vlseg_440, 4, vlseg_440_arg3); + setArg(call_vlseg_440, 5, vm); + setArg(call_vlseg_440, 6, vd); + setArg(call_vlseg_440, 7, vlseg_440_arg6); + setArg(call_vlseg_440, 8, 5); + setArg(call_vlseg_440, 9, 7); + setRet(call_vlseg_440, 0, ret_val_vlseg_440); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 228); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 229: VLSEG7E32__V */ + continuation_e __vlseg7e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 229); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_441; + x86::Gp ret_val_get_pow_441 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_441, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_442; + x86::Gp ret_val_get_sew_pow_442 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_442, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_443; + x86::Gp ret_val_get_lmul_pow_443 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_443, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_441, ret_val_get_sew_pow_442), ret_val_get_lmul_pow_443)), 3, true); + setArg(call_get_pow_441, 0, reinterpret_cast(this)); + setArg(call_get_pow_441, 1, EEW); + setRet(call_get_pow_441, 0, ret_val_get_pow_441); + setArg(call_get_sew_pow_442, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_442, 0, ret_val_get_sew_pow_442); + setArg(call_get_lmul_pow_443, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_443, 0, ret_val_get_lmul_pow_443); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_444; + auto illegal_load_444_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_444 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_444, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_444; + setArg(call_illegal_load_444, 0, reinterpret_cast(this)); + setArg(call_illegal_load_444, 1, vd); + setArg(call_illegal_load_444, 2, vm); + setArg(call_illegal_load_444, 3, 7); + setArg(call_illegal_load_444, 4, EEW); + setArg(call_illegal_load_444, 5, illegal_load_444_arg4); + setRet(call_illegal_load_444, 0, ret_val_illegal_load_444); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_445; + auto vlseg_445_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_445_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_445_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_445_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_445 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_445, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_445, 64, false), traits::vstart); + setArg(call_vlseg_445, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_445, 1, V); + setArg(call_vlseg_445, 2, vlseg_445_arg1); + setArg(call_vlseg_445, 3, vlseg_445_arg2); + setArg(call_vlseg_445, 4, vlseg_445_arg3); + setArg(call_vlseg_445, 5, vm); + setArg(call_vlseg_445, 6, vd); + setArg(call_vlseg_445, 7, vlseg_445_arg6); + setArg(call_vlseg_445, 8, 6); + setArg(call_vlseg_445, 9, 7); + setRet(call_vlseg_445, 0, ret_val_vlseg_445); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 229); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 230: VLSEG7E64__V */ + continuation_e __vlseg7e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg7e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 230); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_446; + x86::Gp ret_val_get_pow_446 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_446, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_447; + x86::Gp ret_val_get_sew_pow_447 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_447, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_448; + x86::Gp ret_val_get_lmul_pow_448 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_448, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_446, ret_val_get_sew_pow_447), ret_val_get_lmul_pow_448)), 3, true); + setArg(call_get_pow_446, 0, reinterpret_cast(this)); + setArg(call_get_pow_446, 1, EEW); + setRet(call_get_pow_446, 0, ret_val_get_pow_446); + setArg(call_get_sew_pow_447, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_447, 0, ret_val_get_sew_pow_447); + setArg(call_get_lmul_pow_448, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_448, 0, ret_val_get_lmul_pow_448); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_449; + auto illegal_load_449_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_449 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_449, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_449; + setArg(call_illegal_load_449, 0, reinterpret_cast(this)); + setArg(call_illegal_load_449, 1, vd); + setArg(call_illegal_load_449, 2, vm); + setArg(call_illegal_load_449, 3, 7); + setArg(call_illegal_load_449, 4, EEW); + setArg(call_illegal_load_449, 5, illegal_load_449_arg4); + setRet(call_illegal_load_449, 0, ret_val_illegal_load_449); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_450; + auto vlseg_450_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_450_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_450_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_450_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_450 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_450, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_450, 64, false), traits::vstart); + setArg(call_vlseg_450, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_450, 1, V); + setArg(call_vlseg_450, 2, vlseg_450_arg1); + setArg(call_vlseg_450, 3, vlseg_450_arg2); + setArg(call_vlseg_450, 4, vlseg_450_arg3); + setArg(call_vlseg_450, 5, vm); + setArg(call_vlseg_450, 6, vd); + setArg(call_vlseg_450, 7, vlseg_450_arg6); + setArg(call_vlseg_450, 8, 7); + setArg(call_vlseg_450, 9, 7); + setRet(call_vlseg_450, 0, ret_val_vlseg_450); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 230); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 231: VLSEG8E8__V */ + continuation_e __vlseg8e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 231); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_451; + x86::Gp ret_val_get_pow_451 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_451, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_452; + x86::Gp ret_val_get_sew_pow_452 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_452, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_453; + x86::Gp ret_val_get_lmul_pow_453 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_453, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_451, ret_val_get_sew_pow_452), ret_val_get_lmul_pow_453)), 3, true); + setArg(call_get_pow_451, 0, reinterpret_cast(this)); + setArg(call_get_pow_451, 1, EEW); + setRet(call_get_pow_451, 0, ret_val_get_pow_451); + setArg(call_get_sew_pow_452, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_452, 0, ret_val_get_sew_pow_452); + setArg(call_get_lmul_pow_453, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_453, 0, ret_val_get_lmul_pow_453); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_454; + auto illegal_load_454_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_454 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_454, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_454; + setArg(call_illegal_load_454, 0, reinterpret_cast(this)); + setArg(call_illegal_load_454, 1, vd); + setArg(call_illegal_load_454, 2, vm); + setArg(call_illegal_load_454, 3, 8); + setArg(call_illegal_load_454, 4, EEW); + setArg(call_illegal_load_454, 5, illegal_load_454_arg4); + setRet(call_illegal_load_454, 0, ret_val_illegal_load_454); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_455; + auto vlseg_455_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_455_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_455_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_455_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_455 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_455, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_455, 64, false), traits::vstart); + setArg(call_vlseg_455, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_455, 1, V); + setArg(call_vlseg_455, 2, vlseg_455_arg1); + setArg(call_vlseg_455, 3, vlseg_455_arg2); + setArg(call_vlseg_455, 4, vlseg_455_arg3); + setArg(call_vlseg_455, 5, vm); + setArg(call_vlseg_455, 6, vd); + setArg(call_vlseg_455, 7, vlseg_455_arg6); + setArg(call_vlseg_455, 8, 0); + setArg(call_vlseg_455, 9, 8); + setRet(call_vlseg_455, 0, ret_val_vlseg_455); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 231); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 232: VLSEG8E16__V */ + continuation_e __vlseg8e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 232); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_456; + x86::Gp ret_val_get_pow_456 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_456, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_457; + x86::Gp ret_val_get_sew_pow_457 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_457, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_458; + x86::Gp ret_val_get_lmul_pow_458 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_458, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_456, ret_val_get_sew_pow_457), ret_val_get_lmul_pow_458)), 3, true); + setArg(call_get_pow_456, 0, reinterpret_cast(this)); + setArg(call_get_pow_456, 1, EEW); + setRet(call_get_pow_456, 0, ret_val_get_pow_456); + setArg(call_get_sew_pow_457, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_457, 0, ret_val_get_sew_pow_457); + setArg(call_get_lmul_pow_458, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_458, 0, ret_val_get_lmul_pow_458); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_459; + auto illegal_load_459_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_459 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_459, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_459; + setArg(call_illegal_load_459, 0, reinterpret_cast(this)); + setArg(call_illegal_load_459, 1, vd); + setArg(call_illegal_load_459, 2, vm); + setArg(call_illegal_load_459, 3, 8); + setArg(call_illegal_load_459, 4, EEW); + setArg(call_illegal_load_459, 5, illegal_load_459_arg4); + setRet(call_illegal_load_459, 0, ret_val_illegal_load_459); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_460; + auto vlseg_460_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_460_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_460_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_460_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_460 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_460, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_460, 64, false), traits::vstart); + setArg(call_vlseg_460, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_460, 1, V); + setArg(call_vlseg_460, 2, vlseg_460_arg1); + setArg(call_vlseg_460, 3, vlseg_460_arg2); + setArg(call_vlseg_460, 4, vlseg_460_arg3); + setArg(call_vlseg_460, 5, vm); + setArg(call_vlseg_460, 6, vd); + setArg(call_vlseg_460, 7, vlseg_460_arg6); + setArg(call_vlseg_460, 8, 5); + setArg(call_vlseg_460, 9, 8); + setRet(call_vlseg_460, 0, ret_val_vlseg_460); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 232); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 233: VLSEG8E32__V */ + continuation_e __vlseg8e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 233); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_461; + x86::Gp ret_val_get_pow_461 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_461, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_462; + x86::Gp ret_val_get_sew_pow_462 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_462, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_463; + x86::Gp ret_val_get_lmul_pow_463 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_463, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_461, ret_val_get_sew_pow_462), ret_val_get_lmul_pow_463)), 3, true); + setArg(call_get_pow_461, 0, reinterpret_cast(this)); + setArg(call_get_pow_461, 1, EEW); + setRet(call_get_pow_461, 0, ret_val_get_pow_461); + setArg(call_get_sew_pow_462, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_462, 0, ret_val_get_sew_pow_462); + setArg(call_get_lmul_pow_463, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_463, 0, ret_val_get_lmul_pow_463); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_464; + auto illegal_load_464_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_464 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_464, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_464; + setArg(call_illegal_load_464, 0, reinterpret_cast(this)); + setArg(call_illegal_load_464, 1, vd); + setArg(call_illegal_load_464, 2, vm); + setArg(call_illegal_load_464, 3, 8); + setArg(call_illegal_load_464, 4, EEW); + setArg(call_illegal_load_464, 5, illegal_load_464_arg4); + setRet(call_illegal_load_464, 0, ret_val_illegal_load_464); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_465; + auto vlseg_465_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_465_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_465_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_465_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_465 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_465, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_465, 64, false), traits::vstart); + setArg(call_vlseg_465, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_465, 1, V); + setArg(call_vlseg_465, 2, vlseg_465_arg1); + setArg(call_vlseg_465, 3, vlseg_465_arg2); + setArg(call_vlseg_465, 4, vlseg_465_arg3); + setArg(call_vlseg_465, 5, vm); + setArg(call_vlseg_465, 6, vd); + setArg(call_vlseg_465, 7, vlseg_465_arg6); + setArg(call_vlseg_465, 8, 6); + setArg(call_vlseg_465, 9, 8); + setRet(call_vlseg_465, 0, ret_val_vlseg_465); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 233); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 234: VLSEG8E64__V */ + continuation_e __vlseg8e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlseg8e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 234); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_466; + x86::Gp ret_val_get_pow_466 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_466, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_467; + x86::Gp ret_val_get_sew_pow_467 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_467, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_468; + x86::Gp ret_val_get_lmul_pow_468 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_468, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_466, ret_val_get_sew_pow_467), ret_val_get_lmul_pow_468)), 3, true); + setArg(call_get_pow_466, 0, reinterpret_cast(this)); + setArg(call_get_pow_466, 1, EEW); + setRet(call_get_pow_466, 0, ret_val_get_pow_466); + setArg(call_get_sew_pow_467, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_467, 0, ret_val_get_sew_pow_467); + setArg(call_get_lmul_pow_468, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_468, 0, ret_val_get_lmul_pow_468); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_469; + auto illegal_load_469_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_469 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_469, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_469; + setArg(call_illegal_load_469, 0, reinterpret_cast(this)); + setArg(call_illegal_load_469, 1, vd); + setArg(call_illegal_load_469, 2, vm); + setArg(call_illegal_load_469, 3, 8); + setArg(call_illegal_load_469, 4, EEW); + setArg(call_illegal_load_469, 5, illegal_load_469_arg4); + setRet(call_illegal_load_469, 0, ret_val_illegal_load_469); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_470; + auto vlseg_470_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_470_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_470_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_470_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_470 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_470, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_470, 64, false), traits::vstart); + setArg(call_vlseg_470, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_470, 1, V); + setArg(call_vlseg_470, 2, vlseg_470_arg1); + setArg(call_vlseg_470, 3, vlseg_470_arg2); + setArg(call_vlseg_470, 4, vlseg_470_arg3); + setArg(call_vlseg_470, 5, vm); + setArg(call_vlseg_470, 6, vd); + setArg(call_vlseg_470, 7, vlseg_470_arg6); + setArg(call_vlseg_470, 8, 7); + setArg(call_vlseg_470, 9, 8); + setRet(call_vlseg_470, 0, ret_val_vlseg_470); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 234); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 235: VSE8__V */ + continuation_e __vse8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 235); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_471; + x86::Gp ret_val_get_pow_471 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_471, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_472; + x86::Gp ret_val_get_sew_pow_472 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_472, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_473; + x86::Gp ret_val_get_lmul_pow_473 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_473, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_471, ret_val_get_sew_pow_472), ret_val_get_lmul_pow_473)), 3, true); + setArg(call_get_pow_471, 0, reinterpret_cast(this)); + setArg(call_get_pow_471, 1, EEW); + setRet(call_get_pow_471, 0, ret_val_get_pow_471); + setArg(call_get_sew_pow_472, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_472, 0, ret_val_get_sew_pow_472); + setArg(call_get_lmul_pow_473, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_473, 0, ret_val_get_lmul_pow_473); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_474; + auto illegal_store_474_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_474 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_474, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_474; + setArg(call_illegal_store_474, 0, reinterpret_cast(this)); + setArg(call_illegal_store_474, 1, 1); + setArg(call_illegal_store_474, 2, EEW); + setArg(call_illegal_store_474, 3, illegal_store_474_arg2); + setRet(call_illegal_store_474, 0, ret_val_illegal_store_474); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_475; + auto vsseg_475_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_475_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_475_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_475_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_475 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_475, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_475, 64, false), traits::vstart); + setArg(call_vsseg_475, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_475, 1, V); + setArg(call_vsseg_475, 2, vsseg_475_arg1); + setArg(call_vsseg_475, 3, vsseg_475_arg2); + setArg(call_vsseg_475, 4, vsseg_475_arg3); + setArg(call_vsseg_475, 5, vm); + setArg(call_vsseg_475, 6, vs3); + setArg(call_vsseg_475, 7, vsseg_475_arg6); + setArg(call_vsseg_475, 8, 0); + setArg(call_vsseg_475, 9, 1); + setRet(call_vsseg_475, 0, ret_val_vsseg_475); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 235); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 236: VSE16__V */ + continuation_e __vse16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 236); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_476; + x86::Gp ret_val_get_pow_476 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_476, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_477; + x86::Gp ret_val_get_sew_pow_477 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_477, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_478; + x86::Gp ret_val_get_lmul_pow_478 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_478, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_476, ret_val_get_sew_pow_477), ret_val_get_lmul_pow_478)), 3, true); + setArg(call_get_pow_476, 0, reinterpret_cast(this)); + setArg(call_get_pow_476, 1, EEW); + setRet(call_get_pow_476, 0, ret_val_get_pow_476); + setArg(call_get_sew_pow_477, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_477, 0, ret_val_get_sew_pow_477); + setArg(call_get_lmul_pow_478, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_478, 0, ret_val_get_lmul_pow_478); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_479; + auto illegal_store_479_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_479 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_479, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_479; + setArg(call_illegal_store_479, 0, reinterpret_cast(this)); + setArg(call_illegal_store_479, 1, 1); + setArg(call_illegal_store_479, 2, EEW); + setArg(call_illegal_store_479, 3, illegal_store_479_arg2); + setRet(call_illegal_store_479, 0, ret_val_illegal_store_479); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_480; + auto vsseg_480_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_480_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_480_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_480_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_480 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_480, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_480, 64, false), traits::vstart); + setArg(call_vsseg_480, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_480, 1, V); + setArg(call_vsseg_480, 2, vsseg_480_arg1); + setArg(call_vsseg_480, 3, vsseg_480_arg2); + setArg(call_vsseg_480, 4, vsseg_480_arg3); + setArg(call_vsseg_480, 5, vm); + setArg(call_vsseg_480, 6, vs3); + setArg(call_vsseg_480, 7, vsseg_480_arg6); + setArg(call_vsseg_480, 8, 5); + setArg(call_vsseg_480, 9, 1); + setRet(call_vsseg_480, 0, ret_val_vsseg_480); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 236); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 237: VSE32__V */ + continuation_e __vse32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 237); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_481; + x86::Gp ret_val_get_pow_481 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_481, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_482; + x86::Gp ret_val_get_sew_pow_482 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_482, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_483; + x86::Gp ret_val_get_lmul_pow_483 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_483, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_481, ret_val_get_sew_pow_482), ret_val_get_lmul_pow_483)), 3, true); + setArg(call_get_pow_481, 0, reinterpret_cast(this)); + setArg(call_get_pow_481, 1, EEW); + setRet(call_get_pow_481, 0, ret_val_get_pow_481); + setArg(call_get_sew_pow_482, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_482, 0, ret_val_get_sew_pow_482); + setArg(call_get_lmul_pow_483, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_483, 0, ret_val_get_lmul_pow_483); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_484; + auto illegal_store_484_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_484 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_484, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_484; + setArg(call_illegal_store_484, 0, reinterpret_cast(this)); + setArg(call_illegal_store_484, 1, 1); + setArg(call_illegal_store_484, 2, EEW); + setArg(call_illegal_store_484, 3, illegal_store_484_arg2); + setRet(call_illegal_store_484, 0, ret_val_illegal_store_484); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_485; + auto vsseg_485_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_485_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_485_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_485_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_485 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_485, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_485, 64, false), traits::vstart); + setArg(call_vsseg_485, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_485, 1, V); + setArg(call_vsseg_485, 2, vsseg_485_arg1); + setArg(call_vsseg_485, 3, vsseg_485_arg2); + setArg(call_vsseg_485, 4, vsseg_485_arg3); + setArg(call_vsseg_485, 5, vm); + setArg(call_vsseg_485, 6, vs3); + setArg(call_vsseg_485, 7, vsseg_485_arg6); + setArg(call_vsseg_485, 8, 6); + setArg(call_vsseg_485, 9, 1); + setRet(call_vsseg_485, 0, ret_val_vsseg_485); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 237); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 238: VSE64__V */ + continuation_e __vse64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vse64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 238); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_486; + x86::Gp ret_val_get_pow_486 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_486, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_487; + x86::Gp ret_val_get_sew_pow_487 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_487, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_488; + x86::Gp ret_val_get_lmul_pow_488 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_488, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_486, ret_val_get_sew_pow_487), ret_val_get_lmul_pow_488)), 3, true); + setArg(call_get_pow_486, 0, reinterpret_cast(this)); + setArg(call_get_pow_486, 1, EEW); + setRet(call_get_pow_486, 0, ret_val_get_pow_486); + setArg(call_get_sew_pow_487, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_487, 0, ret_val_get_sew_pow_487); + setArg(call_get_lmul_pow_488, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_488, 0, ret_val_get_lmul_pow_488); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_489; + auto illegal_store_489_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_489 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_489, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_489; + setArg(call_illegal_store_489, 0, reinterpret_cast(this)); + setArg(call_illegal_store_489, 1, 1); + setArg(call_illegal_store_489, 2, EEW); + setArg(call_illegal_store_489, 3, illegal_store_489_arg2); + setRet(call_illegal_store_489, 0, ret_val_illegal_store_489); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_490; + auto vsseg_490_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_490_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_490_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_490_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_490 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_490, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_490, 64, false), traits::vstart); + setArg(call_vsseg_490, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_490, 1, V); + setArg(call_vsseg_490, 2, vsseg_490_arg1); + setArg(call_vsseg_490, 3, vsseg_490_arg2); + setArg(call_vsseg_490, 4, vsseg_490_arg3); + setArg(call_vsseg_490, 5, vm); + setArg(call_vsseg_490, 6, vs3); + setArg(call_vsseg_490, 7, vsseg_490_arg6); + setArg(call_vsseg_490, 8, 7); + setArg(call_vsseg_490, 9, 1); + setRet(call_vsseg_490, 0, ret_val_vsseg_490); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 238); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 239: VSSEG2E8__V */ + continuation_e __vsseg2e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG2E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 239); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_491; + x86::Gp ret_val_get_pow_491 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_491, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_492; + x86::Gp ret_val_get_sew_pow_492 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_492, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_493; + x86::Gp ret_val_get_lmul_pow_493 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_493, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_491, ret_val_get_sew_pow_492), ret_val_get_lmul_pow_493)), 3, true); + setArg(call_get_pow_491, 0, reinterpret_cast(this)); + setArg(call_get_pow_491, 1, EEW); + setRet(call_get_pow_491, 0, ret_val_get_pow_491); + setArg(call_get_sew_pow_492, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_492, 0, ret_val_get_sew_pow_492); + setArg(call_get_lmul_pow_493, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_493, 0, ret_val_get_lmul_pow_493); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_494; + auto illegal_store_494_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_494 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_494, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_494; + setArg(call_illegal_store_494, 0, reinterpret_cast(this)); + setArg(call_illegal_store_494, 1, 2); + setArg(call_illegal_store_494, 2, EEW); + setArg(call_illegal_store_494, 3, illegal_store_494_arg2); + setRet(call_illegal_store_494, 0, ret_val_illegal_store_494); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_495; + auto vsseg_495_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_495_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_495_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_495_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_495 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_495, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_495, 64, false), traits::vstart); + setArg(call_vsseg_495, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_495, 1, V); + setArg(call_vsseg_495, 2, vsseg_495_arg1); + setArg(call_vsseg_495, 3, vsseg_495_arg2); + setArg(call_vsseg_495, 4, vsseg_495_arg3); + setArg(call_vsseg_495, 5, vm); + setArg(call_vsseg_495, 6, vs3); + setArg(call_vsseg_495, 7, vsseg_495_arg6); + setArg(call_vsseg_495, 8, 0); + setArg(call_vsseg_495, 9, 2); + setRet(call_vsseg_495, 0, ret_val_vsseg_495); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 239); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 240: VSSEG2E16__V */ + continuation_e __vsseg2e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG2E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 240); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_496; + x86::Gp ret_val_get_pow_496 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_496, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_497; + x86::Gp ret_val_get_sew_pow_497 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_497, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_498; + x86::Gp ret_val_get_lmul_pow_498 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_498, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_496, ret_val_get_sew_pow_497), ret_val_get_lmul_pow_498)), 3, true); + setArg(call_get_pow_496, 0, reinterpret_cast(this)); + setArg(call_get_pow_496, 1, EEW); + setRet(call_get_pow_496, 0, ret_val_get_pow_496); + setArg(call_get_sew_pow_497, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_497, 0, ret_val_get_sew_pow_497); + setArg(call_get_lmul_pow_498, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_498, 0, ret_val_get_lmul_pow_498); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_499; + auto illegal_store_499_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_499 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_499, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_499; + setArg(call_illegal_store_499, 0, reinterpret_cast(this)); + setArg(call_illegal_store_499, 1, 2); + setArg(call_illegal_store_499, 2, EEW); + setArg(call_illegal_store_499, 3, illegal_store_499_arg2); + setRet(call_illegal_store_499, 0, ret_val_illegal_store_499); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_500; + auto vsseg_500_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_500_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_500_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_500_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_500 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_500, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_500, 64, false), traits::vstart); + setArg(call_vsseg_500, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_500, 1, V); + setArg(call_vsseg_500, 2, vsseg_500_arg1); + setArg(call_vsseg_500, 3, vsseg_500_arg2); + setArg(call_vsseg_500, 4, vsseg_500_arg3); + setArg(call_vsseg_500, 5, vm); + setArg(call_vsseg_500, 6, vs3); + setArg(call_vsseg_500, 7, vsseg_500_arg6); + setArg(call_vsseg_500, 8, 5); + setArg(call_vsseg_500, 9, 2); + setRet(call_vsseg_500, 0, ret_val_vsseg_500); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 240); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 241: VSSEG2E32__V */ + continuation_e __vsseg2e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG2E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 241); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_501; + x86::Gp ret_val_get_pow_501 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_501, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_502; + x86::Gp ret_val_get_sew_pow_502 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_502, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_503; + x86::Gp ret_val_get_lmul_pow_503 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_503, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_501, ret_val_get_sew_pow_502), ret_val_get_lmul_pow_503)), 3, true); + setArg(call_get_pow_501, 0, reinterpret_cast(this)); + setArg(call_get_pow_501, 1, EEW); + setRet(call_get_pow_501, 0, ret_val_get_pow_501); + setArg(call_get_sew_pow_502, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_502, 0, ret_val_get_sew_pow_502); + setArg(call_get_lmul_pow_503, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_503, 0, ret_val_get_lmul_pow_503); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_504; + auto illegal_store_504_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_504 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_504, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_504; + setArg(call_illegal_store_504, 0, reinterpret_cast(this)); + setArg(call_illegal_store_504, 1, 2); + setArg(call_illegal_store_504, 2, EEW); + setArg(call_illegal_store_504, 3, illegal_store_504_arg2); + setRet(call_illegal_store_504, 0, ret_val_illegal_store_504); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_505; + auto vsseg_505_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_505_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_505_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_505_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_505 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_505, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_505, 64, false), traits::vstart); + setArg(call_vsseg_505, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_505, 1, V); + setArg(call_vsseg_505, 2, vsseg_505_arg1); + setArg(call_vsseg_505, 3, vsseg_505_arg2); + setArg(call_vsseg_505, 4, vsseg_505_arg3); + setArg(call_vsseg_505, 5, vm); + setArg(call_vsseg_505, 6, vs3); + setArg(call_vsseg_505, 7, vsseg_505_arg6); + setArg(call_vsseg_505, 8, 6); + setArg(call_vsseg_505, 9, 2); + setRet(call_vsseg_505, 0, ret_val_vsseg_505); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 241); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 242: VSSEG2E64__V */ + continuation_e __vsseg2e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg2e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG2E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 242); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_506; + x86::Gp ret_val_get_pow_506 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_506, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_507; + x86::Gp ret_val_get_sew_pow_507 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_507, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_508; + x86::Gp ret_val_get_lmul_pow_508 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_508, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_506, ret_val_get_sew_pow_507), ret_val_get_lmul_pow_508)), 3, true); + setArg(call_get_pow_506, 0, reinterpret_cast(this)); + setArg(call_get_pow_506, 1, EEW); + setRet(call_get_pow_506, 0, ret_val_get_pow_506); + setArg(call_get_sew_pow_507, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_507, 0, ret_val_get_sew_pow_507); + setArg(call_get_lmul_pow_508, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_508, 0, ret_val_get_lmul_pow_508); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_509; + auto illegal_store_509_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_509 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_509, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_509; + setArg(call_illegal_store_509, 0, reinterpret_cast(this)); + setArg(call_illegal_store_509, 1, 2); + setArg(call_illegal_store_509, 2, EEW); + setArg(call_illegal_store_509, 3, illegal_store_509_arg2); + setRet(call_illegal_store_509, 0, ret_val_illegal_store_509); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_510; + auto vsseg_510_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_510_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_510_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_510_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_510 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_510, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_510, 64, false), traits::vstart); + setArg(call_vsseg_510, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_510, 1, V); + setArg(call_vsseg_510, 2, vsseg_510_arg1); + setArg(call_vsseg_510, 3, vsseg_510_arg2); + setArg(call_vsseg_510, 4, vsseg_510_arg3); + setArg(call_vsseg_510, 5, vm); + setArg(call_vsseg_510, 6, vs3); + setArg(call_vsseg_510, 7, vsseg_510_arg6); + setArg(call_vsseg_510, 8, 7); + setArg(call_vsseg_510, 9, 2); + setRet(call_vsseg_510, 0, ret_val_vsseg_510); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 242); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 243: VSSEG3E8__V */ + continuation_e __vsseg3e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG3E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 243); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_511; + x86::Gp ret_val_get_pow_511 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_511, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_512; + x86::Gp ret_val_get_sew_pow_512 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_512, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_513; + x86::Gp ret_val_get_lmul_pow_513 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_513, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_511, ret_val_get_sew_pow_512), ret_val_get_lmul_pow_513)), 3, true); + setArg(call_get_pow_511, 0, reinterpret_cast(this)); + setArg(call_get_pow_511, 1, EEW); + setRet(call_get_pow_511, 0, ret_val_get_pow_511); + setArg(call_get_sew_pow_512, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_512, 0, ret_val_get_sew_pow_512); + setArg(call_get_lmul_pow_513, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_513, 0, ret_val_get_lmul_pow_513); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_514; + auto illegal_store_514_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_514 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_514, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_514; + setArg(call_illegal_store_514, 0, reinterpret_cast(this)); + setArg(call_illegal_store_514, 1, 3); + setArg(call_illegal_store_514, 2, EEW); + setArg(call_illegal_store_514, 3, illegal_store_514_arg2); + setRet(call_illegal_store_514, 0, ret_val_illegal_store_514); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_515; + auto vsseg_515_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_515_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_515_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_515_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_515 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_515, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_515, 64, false), traits::vstart); + setArg(call_vsseg_515, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_515, 1, V); + setArg(call_vsseg_515, 2, vsseg_515_arg1); + setArg(call_vsseg_515, 3, vsseg_515_arg2); + setArg(call_vsseg_515, 4, vsseg_515_arg3); + setArg(call_vsseg_515, 5, vm); + setArg(call_vsseg_515, 6, vs3); + setArg(call_vsseg_515, 7, vsseg_515_arg6); + setArg(call_vsseg_515, 8, 0); + setArg(call_vsseg_515, 9, 3); + setRet(call_vsseg_515, 0, ret_val_vsseg_515); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 243); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 244: VSSEG3E16__V */ + continuation_e __vsseg3e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG3E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 244); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_516; + x86::Gp ret_val_get_pow_516 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_516, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_517; + x86::Gp ret_val_get_sew_pow_517 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_517, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_518; + x86::Gp ret_val_get_lmul_pow_518 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_518, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_516, ret_val_get_sew_pow_517), ret_val_get_lmul_pow_518)), 3, true); + setArg(call_get_pow_516, 0, reinterpret_cast(this)); + setArg(call_get_pow_516, 1, EEW); + setRet(call_get_pow_516, 0, ret_val_get_pow_516); + setArg(call_get_sew_pow_517, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_517, 0, ret_val_get_sew_pow_517); + setArg(call_get_lmul_pow_518, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_518, 0, ret_val_get_lmul_pow_518); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_519; + auto illegal_store_519_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_519 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_519, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_519; + setArg(call_illegal_store_519, 0, reinterpret_cast(this)); + setArg(call_illegal_store_519, 1, 3); + setArg(call_illegal_store_519, 2, EEW); + setArg(call_illegal_store_519, 3, illegal_store_519_arg2); + setRet(call_illegal_store_519, 0, ret_val_illegal_store_519); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_520; + auto vsseg_520_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_520_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_520_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_520_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_520 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_520, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_520, 64, false), traits::vstart); + setArg(call_vsseg_520, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_520, 1, V); + setArg(call_vsseg_520, 2, vsseg_520_arg1); + setArg(call_vsseg_520, 3, vsseg_520_arg2); + setArg(call_vsseg_520, 4, vsseg_520_arg3); + setArg(call_vsseg_520, 5, vm); + setArg(call_vsseg_520, 6, vs3); + setArg(call_vsseg_520, 7, vsseg_520_arg6); + setArg(call_vsseg_520, 8, 5); + setArg(call_vsseg_520, 9, 3); + setRet(call_vsseg_520, 0, ret_val_vsseg_520); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 244); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 245: VSSEG3E32__V */ + continuation_e __vsseg3e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG3E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 245); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_521; + x86::Gp ret_val_get_pow_521 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_521, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_522; + x86::Gp ret_val_get_sew_pow_522 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_522, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_523; + x86::Gp ret_val_get_lmul_pow_523 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_523, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_521, ret_val_get_sew_pow_522), ret_val_get_lmul_pow_523)), 3, true); + setArg(call_get_pow_521, 0, reinterpret_cast(this)); + setArg(call_get_pow_521, 1, EEW); + setRet(call_get_pow_521, 0, ret_val_get_pow_521); + setArg(call_get_sew_pow_522, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_522, 0, ret_val_get_sew_pow_522); + setArg(call_get_lmul_pow_523, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_523, 0, ret_val_get_lmul_pow_523); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_524; + auto illegal_store_524_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_524 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_524, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_524; + setArg(call_illegal_store_524, 0, reinterpret_cast(this)); + setArg(call_illegal_store_524, 1, 3); + setArg(call_illegal_store_524, 2, EEW); + setArg(call_illegal_store_524, 3, illegal_store_524_arg2); + setRet(call_illegal_store_524, 0, ret_val_illegal_store_524); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_525; + auto vsseg_525_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_525_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_525_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_525_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_525 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_525, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_525, 64, false), traits::vstart); + setArg(call_vsseg_525, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_525, 1, V); + setArg(call_vsseg_525, 2, vsseg_525_arg1); + setArg(call_vsseg_525, 3, vsseg_525_arg2); + setArg(call_vsseg_525, 4, vsseg_525_arg3); + setArg(call_vsseg_525, 5, vm); + setArg(call_vsseg_525, 6, vs3); + setArg(call_vsseg_525, 7, vsseg_525_arg6); + setArg(call_vsseg_525, 8, 6); + setArg(call_vsseg_525, 9, 3); + setRet(call_vsseg_525, 0, ret_val_vsseg_525); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 245); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 246: VSSEG3E64__V */ + continuation_e __vsseg3e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg3e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG3E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 246); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_526; + x86::Gp ret_val_get_pow_526 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_526, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_527; + x86::Gp ret_val_get_sew_pow_527 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_527, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_528; + x86::Gp ret_val_get_lmul_pow_528 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_528, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_526, ret_val_get_sew_pow_527), ret_val_get_lmul_pow_528)), 3, true); + setArg(call_get_pow_526, 0, reinterpret_cast(this)); + setArg(call_get_pow_526, 1, EEW); + setRet(call_get_pow_526, 0, ret_val_get_pow_526); + setArg(call_get_sew_pow_527, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_527, 0, ret_val_get_sew_pow_527); + setArg(call_get_lmul_pow_528, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_528, 0, ret_val_get_lmul_pow_528); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_529; + auto illegal_store_529_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_529 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_529, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_529; + setArg(call_illegal_store_529, 0, reinterpret_cast(this)); + setArg(call_illegal_store_529, 1, 3); + setArg(call_illegal_store_529, 2, EEW); + setArg(call_illegal_store_529, 3, illegal_store_529_arg2); + setRet(call_illegal_store_529, 0, ret_val_illegal_store_529); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_530; + auto vsseg_530_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_530_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_530_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_530_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_530 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_530, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_530, 64, false), traits::vstart); + setArg(call_vsseg_530, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_530, 1, V); + setArg(call_vsseg_530, 2, vsseg_530_arg1); + setArg(call_vsseg_530, 3, vsseg_530_arg2); + setArg(call_vsseg_530, 4, vsseg_530_arg3); + setArg(call_vsseg_530, 5, vm); + setArg(call_vsseg_530, 6, vs3); + setArg(call_vsseg_530, 7, vsseg_530_arg6); + setArg(call_vsseg_530, 8, 7); + setArg(call_vsseg_530, 9, 3); + setRet(call_vsseg_530, 0, ret_val_vsseg_530); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 246); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 247: VSSEG4E8__V */ + continuation_e __vsseg4e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG4E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 247); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_531; + x86::Gp ret_val_get_pow_531 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_531, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_532; + x86::Gp ret_val_get_sew_pow_532 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_532, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_533; + x86::Gp ret_val_get_lmul_pow_533 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_533, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_531, ret_val_get_sew_pow_532), ret_val_get_lmul_pow_533)), 3, true); + setArg(call_get_pow_531, 0, reinterpret_cast(this)); + setArg(call_get_pow_531, 1, EEW); + setRet(call_get_pow_531, 0, ret_val_get_pow_531); + setArg(call_get_sew_pow_532, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_532, 0, ret_val_get_sew_pow_532); + setArg(call_get_lmul_pow_533, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_533, 0, ret_val_get_lmul_pow_533); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_534; + auto illegal_store_534_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_534 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_534, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_534; + setArg(call_illegal_store_534, 0, reinterpret_cast(this)); + setArg(call_illegal_store_534, 1, 4); + setArg(call_illegal_store_534, 2, EEW); + setArg(call_illegal_store_534, 3, illegal_store_534_arg2); + setRet(call_illegal_store_534, 0, ret_val_illegal_store_534); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_535; + auto vsseg_535_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_535_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_535_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_535_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_535 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_535, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_535, 64, false), traits::vstart); + setArg(call_vsseg_535, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_535, 1, V); + setArg(call_vsseg_535, 2, vsseg_535_arg1); + setArg(call_vsseg_535, 3, vsseg_535_arg2); + setArg(call_vsseg_535, 4, vsseg_535_arg3); + setArg(call_vsseg_535, 5, vm); + setArg(call_vsseg_535, 6, vs3); + setArg(call_vsseg_535, 7, vsseg_535_arg6); + setArg(call_vsseg_535, 8, 0); + setArg(call_vsseg_535, 9, 4); + setRet(call_vsseg_535, 0, ret_val_vsseg_535); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 247); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 248: VSSEG4E16__V */ + continuation_e __vsseg4e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG4E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 248); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_536; + x86::Gp ret_val_get_pow_536 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_536, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_537; + x86::Gp ret_val_get_sew_pow_537 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_537, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_538; + x86::Gp ret_val_get_lmul_pow_538 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_538, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_536, ret_val_get_sew_pow_537), ret_val_get_lmul_pow_538)), 3, true); + setArg(call_get_pow_536, 0, reinterpret_cast(this)); + setArg(call_get_pow_536, 1, EEW); + setRet(call_get_pow_536, 0, ret_val_get_pow_536); + setArg(call_get_sew_pow_537, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_537, 0, ret_val_get_sew_pow_537); + setArg(call_get_lmul_pow_538, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_538, 0, ret_val_get_lmul_pow_538); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_539; + auto illegal_store_539_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_539 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_539, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_539; + setArg(call_illegal_store_539, 0, reinterpret_cast(this)); + setArg(call_illegal_store_539, 1, 4); + setArg(call_illegal_store_539, 2, EEW); + setArg(call_illegal_store_539, 3, illegal_store_539_arg2); + setRet(call_illegal_store_539, 0, ret_val_illegal_store_539); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_540; + auto vsseg_540_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_540_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_540_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_540_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_540 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_540, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_540, 64, false), traits::vstart); + setArg(call_vsseg_540, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_540, 1, V); + setArg(call_vsseg_540, 2, vsseg_540_arg1); + setArg(call_vsseg_540, 3, vsseg_540_arg2); + setArg(call_vsseg_540, 4, vsseg_540_arg3); + setArg(call_vsseg_540, 5, vm); + setArg(call_vsseg_540, 6, vs3); + setArg(call_vsseg_540, 7, vsseg_540_arg6); + setArg(call_vsseg_540, 8, 5); + setArg(call_vsseg_540, 9, 4); + setRet(call_vsseg_540, 0, ret_val_vsseg_540); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 248); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 249: VSSEG4E32__V */ + continuation_e __vsseg4e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG4E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 249); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_541; + x86::Gp ret_val_get_pow_541 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_541, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_542; + x86::Gp ret_val_get_sew_pow_542 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_542, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_543; + x86::Gp ret_val_get_lmul_pow_543 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_543, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_541, ret_val_get_sew_pow_542), ret_val_get_lmul_pow_543)), 3, true); + setArg(call_get_pow_541, 0, reinterpret_cast(this)); + setArg(call_get_pow_541, 1, EEW); + setRet(call_get_pow_541, 0, ret_val_get_pow_541); + setArg(call_get_sew_pow_542, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_542, 0, ret_val_get_sew_pow_542); + setArg(call_get_lmul_pow_543, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_543, 0, ret_val_get_lmul_pow_543); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_544; + auto illegal_store_544_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_544 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_544, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_544; + setArg(call_illegal_store_544, 0, reinterpret_cast(this)); + setArg(call_illegal_store_544, 1, 4); + setArg(call_illegal_store_544, 2, EEW); + setArg(call_illegal_store_544, 3, illegal_store_544_arg2); + setRet(call_illegal_store_544, 0, ret_val_illegal_store_544); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_545; + auto vsseg_545_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_545_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_545_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_545_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_545 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_545, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_545, 64, false), traits::vstart); + setArg(call_vsseg_545, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_545, 1, V); + setArg(call_vsseg_545, 2, vsseg_545_arg1); + setArg(call_vsseg_545, 3, vsseg_545_arg2); + setArg(call_vsseg_545, 4, vsseg_545_arg3); + setArg(call_vsseg_545, 5, vm); + setArg(call_vsseg_545, 6, vs3); + setArg(call_vsseg_545, 7, vsseg_545_arg6); + setArg(call_vsseg_545, 8, 6); + setArg(call_vsseg_545, 9, 4); + setRet(call_vsseg_545, 0, ret_val_vsseg_545); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 249); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 250: VSSEG4E64__V */ + continuation_e __vsseg4e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg4e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG4E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 250); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_546; + x86::Gp ret_val_get_pow_546 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_546, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_547; + x86::Gp ret_val_get_sew_pow_547 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_547, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_548; + x86::Gp ret_val_get_lmul_pow_548 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_548, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_546, ret_val_get_sew_pow_547), ret_val_get_lmul_pow_548)), 3, true); + setArg(call_get_pow_546, 0, reinterpret_cast(this)); + setArg(call_get_pow_546, 1, EEW); + setRet(call_get_pow_546, 0, ret_val_get_pow_546); + setArg(call_get_sew_pow_547, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_547, 0, ret_val_get_sew_pow_547); + setArg(call_get_lmul_pow_548, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_548, 0, ret_val_get_lmul_pow_548); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_549; + auto illegal_store_549_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_549 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_549, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_549; + setArg(call_illegal_store_549, 0, reinterpret_cast(this)); + setArg(call_illegal_store_549, 1, 4); + setArg(call_illegal_store_549, 2, EEW); + setArg(call_illegal_store_549, 3, illegal_store_549_arg2); + setRet(call_illegal_store_549, 0, ret_val_illegal_store_549); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_550; + auto vsseg_550_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_550_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_550_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_550_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_550 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_550, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_550, 64, false), traits::vstart); + setArg(call_vsseg_550, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_550, 1, V); + setArg(call_vsseg_550, 2, vsseg_550_arg1); + setArg(call_vsseg_550, 3, vsseg_550_arg2); + setArg(call_vsseg_550, 4, vsseg_550_arg3); + setArg(call_vsseg_550, 5, vm); + setArg(call_vsseg_550, 6, vs3); + setArg(call_vsseg_550, 7, vsseg_550_arg6); + setArg(call_vsseg_550, 8, 7); + setArg(call_vsseg_550, 9, 4); + setRet(call_vsseg_550, 0, ret_val_vsseg_550); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 250); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 251: VSSEG5E8__V */ + continuation_e __vsseg5e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG5E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 251); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_551; + x86::Gp ret_val_get_pow_551 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_551, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_552; + x86::Gp ret_val_get_sew_pow_552 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_552, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_553; + x86::Gp ret_val_get_lmul_pow_553 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_553, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_551, ret_val_get_sew_pow_552), ret_val_get_lmul_pow_553)), 3, true); + setArg(call_get_pow_551, 0, reinterpret_cast(this)); + setArg(call_get_pow_551, 1, EEW); + setRet(call_get_pow_551, 0, ret_val_get_pow_551); + setArg(call_get_sew_pow_552, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_552, 0, ret_val_get_sew_pow_552); + setArg(call_get_lmul_pow_553, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_553, 0, ret_val_get_lmul_pow_553); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_554; + auto illegal_store_554_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_554 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_554, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_554; + setArg(call_illegal_store_554, 0, reinterpret_cast(this)); + setArg(call_illegal_store_554, 1, 5); + setArg(call_illegal_store_554, 2, EEW); + setArg(call_illegal_store_554, 3, illegal_store_554_arg2); + setRet(call_illegal_store_554, 0, ret_val_illegal_store_554); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_555; + auto vsseg_555_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_555_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_555_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_555_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_555 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_555, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_555, 64, false), traits::vstart); + setArg(call_vsseg_555, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_555, 1, V); + setArg(call_vsseg_555, 2, vsseg_555_arg1); + setArg(call_vsseg_555, 3, vsseg_555_arg2); + setArg(call_vsseg_555, 4, vsseg_555_arg3); + setArg(call_vsseg_555, 5, vm); + setArg(call_vsseg_555, 6, vs3); + setArg(call_vsseg_555, 7, vsseg_555_arg6); + setArg(call_vsseg_555, 8, 0); + setArg(call_vsseg_555, 9, 5); + setRet(call_vsseg_555, 0, ret_val_vsseg_555); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 251); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 252: VSSEG5E16__V */ + continuation_e __vsseg5e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG5E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 252); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_556; + x86::Gp ret_val_get_pow_556 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_556, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_557; + x86::Gp ret_val_get_sew_pow_557 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_557, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_558; + x86::Gp ret_val_get_lmul_pow_558 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_558, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_556, ret_val_get_sew_pow_557), ret_val_get_lmul_pow_558)), 3, true); + setArg(call_get_pow_556, 0, reinterpret_cast(this)); + setArg(call_get_pow_556, 1, EEW); + setRet(call_get_pow_556, 0, ret_val_get_pow_556); + setArg(call_get_sew_pow_557, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_557, 0, ret_val_get_sew_pow_557); + setArg(call_get_lmul_pow_558, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_558, 0, ret_val_get_lmul_pow_558); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_559; + auto illegal_store_559_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_559 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_559, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_559; + setArg(call_illegal_store_559, 0, reinterpret_cast(this)); + setArg(call_illegal_store_559, 1, 5); + setArg(call_illegal_store_559, 2, EEW); + setArg(call_illegal_store_559, 3, illegal_store_559_arg2); + setRet(call_illegal_store_559, 0, ret_val_illegal_store_559); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_560; + auto vsseg_560_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_560_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_560_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_560_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_560 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_560, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_560, 64, false), traits::vstart); + setArg(call_vsseg_560, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_560, 1, V); + setArg(call_vsseg_560, 2, vsseg_560_arg1); + setArg(call_vsseg_560, 3, vsseg_560_arg2); + setArg(call_vsseg_560, 4, vsseg_560_arg3); + setArg(call_vsseg_560, 5, vm); + setArg(call_vsseg_560, 6, vs3); + setArg(call_vsseg_560, 7, vsseg_560_arg6); + setArg(call_vsseg_560, 8, 5); + setArg(call_vsseg_560, 9, 5); + setRet(call_vsseg_560, 0, ret_val_vsseg_560); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 252); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 253: VSSEG5E32__V */ + continuation_e __vsseg5e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG5E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 253); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_561; + x86::Gp ret_val_get_pow_561 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_561, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_562; + x86::Gp ret_val_get_sew_pow_562 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_562, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_563; + x86::Gp ret_val_get_lmul_pow_563 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_563, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_561, ret_val_get_sew_pow_562), ret_val_get_lmul_pow_563)), 3, true); + setArg(call_get_pow_561, 0, reinterpret_cast(this)); + setArg(call_get_pow_561, 1, EEW); + setRet(call_get_pow_561, 0, ret_val_get_pow_561); + setArg(call_get_sew_pow_562, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_562, 0, ret_val_get_sew_pow_562); + setArg(call_get_lmul_pow_563, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_563, 0, ret_val_get_lmul_pow_563); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_564; + auto illegal_store_564_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_564 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_564, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_564; + setArg(call_illegal_store_564, 0, reinterpret_cast(this)); + setArg(call_illegal_store_564, 1, 5); + setArg(call_illegal_store_564, 2, EEW); + setArg(call_illegal_store_564, 3, illegal_store_564_arg2); + setRet(call_illegal_store_564, 0, ret_val_illegal_store_564); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_565; + auto vsseg_565_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_565_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_565_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_565_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_565 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_565, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_565, 64, false), traits::vstart); + setArg(call_vsseg_565, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_565, 1, V); + setArg(call_vsseg_565, 2, vsseg_565_arg1); + setArg(call_vsseg_565, 3, vsseg_565_arg2); + setArg(call_vsseg_565, 4, vsseg_565_arg3); + setArg(call_vsseg_565, 5, vm); + setArg(call_vsseg_565, 6, vs3); + setArg(call_vsseg_565, 7, vsseg_565_arg6); + setArg(call_vsseg_565, 8, 6); + setArg(call_vsseg_565, 9, 5); + setRet(call_vsseg_565, 0, ret_val_vsseg_565); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 253); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 254: VSSEG5E64__V */ + continuation_e __vsseg5e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg5e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG5E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 254); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_566; + x86::Gp ret_val_get_pow_566 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_566, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_567; + x86::Gp ret_val_get_sew_pow_567 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_567, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_568; + x86::Gp ret_val_get_lmul_pow_568 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_568, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_566, ret_val_get_sew_pow_567), ret_val_get_lmul_pow_568)), 3, true); + setArg(call_get_pow_566, 0, reinterpret_cast(this)); + setArg(call_get_pow_566, 1, EEW); + setRet(call_get_pow_566, 0, ret_val_get_pow_566); + setArg(call_get_sew_pow_567, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_567, 0, ret_val_get_sew_pow_567); + setArg(call_get_lmul_pow_568, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_568, 0, ret_val_get_lmul_pow_568); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_569; + auto illegal_store_569_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_569 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_569, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_569; + setArg(call_illegal_store_569, 0, reinterpret_cast(this)); + setArg(call_illegal_store_569, 1, 5); + setArg(call_illegal_store_569, 2, EEW); + setArg(call_illegal_store_569, 3, illegal_store_569_arg2); + setRet(call_illegal_store_569, 0, ret_val_illegal_store_569); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_570; + auto vsseg_570_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_570_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_570_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_570_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_570 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_570, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_570, 64, false), traits::vstart); + setArg(call_vsseg_570, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_570, 1, V); + setArg(call_vsseg_570, 2, vsseg_570_arg1); + setArg(call_vsseg_570, 3, vsseg_570_arg2); + setArg(call_vsseg_570, 4, vsseg_570_arg3); + setArg(call_vsseg_570, 5, vm); + setArg(call_vsseg_570, 6, vs3); + setArg(call_vsseg_570, 7, vsseg_570_arg6); + setArg(call_vsseg_570, 8, 7); + setArg(call_vsseg_570, 9, 5); + setRet(call_vsseg_570, 0, ret_val_vsseg_570); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 254); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 255: VSSEG6E8__V */ + continuation_e __vsseg6e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG6E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 255); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_571; + x86::Gp ret_val_get_pow_571 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_571, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_572; + x86::Gp ret_val_get_sew_pow_572 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_572, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_573; + x86::Gp ret_val_get_lmul_pow_573 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_573, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_571, ret_val_get_sew_pow_572), ret_val_get_lmul_pow_573)), 3, true); + setArg(call_get_pow_571, 0, reinterpret_cast(this)); + setArg(call_get_pow_571, 1, EEW); + setRet(call_get_pow_571, 0, ret_val_get_pow_571); + setArg(call_get_sew_pow_572, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_572, 0, ret_val_get_sew_pow_572); + setArg(call_get_lmul_pow_573, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_573, 0, ret_val_get_lmul_pow_573); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_574; + auto illegal_store_574_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_574 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_574, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_574; + setArg(call_illegal_store_574, 0, reinterpret_cast(this)); + setArg(call_illegal_store_574, 1, 6); + setArg(call_illegal_store_574, 2, EEW); + setArg(call_illegal_store_574, 3, illegal_store_574_arg2); + setRet(call_illegal_store_574, 0, ret_val_illegal_store_574); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_575; + auto vsseg_575_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_575_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_575_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_575_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_575 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_575, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_575, 64, false), traits::vstart); + setArg(call_vsseg_575, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_575, 1, V); + setArg(call_vsseg_575, 2, vsseg_575_arg1); + setArg(call_vsseg_575, 3, vsseg_575_arg2); + setArg(call_vsseg_575, 4, vsseg_575_arg3); + setArg(call_vsseg_575, 5, vm); + setArg(call_vsseg_575, 6, vs3); + setArg(call_vsseg_575, 7, vsseg_575_arg6); + setArg(call_vsseg_575, 8, 0); + setArg(call_vsseg_575, 9, 6); + setRet(call_vsseg_575, 0, ret_val_vsseg_575); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 255); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 256: VSSEG6E16__V */ + continuation_e __vsseg6e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG6E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 256); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_576; + x86::Gp ret_val_get_pow_576 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_576, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_577; + x86::Gp ret_val_get_sew_pow_577 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_577, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_578; + x86::Gp ret_val_get_lmul_pow_578 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_578, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_576, ret_val_get_sew_pow_577), ret_val_get_lmul_pow_578)), 3, true); + setArg(call_get_pow_576, 0, reinterpret_cast(this)); + setArg(call_get_pow_576, 1, EEW); + setRet(call_get_pow_576, 0, ret_val_get_pow_576); + setArg(call_get_sew_pow_577, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_577, 0, ret_val_get_sew_pow_577); + setArg(call_get_lmul_pow_578, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_578, 0, ret_val_get_lmul_pow_578); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_579; + auto illegal_store_579_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_579 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_579, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_579; + setArg(call_illegal_store_579, 0, reinterpret_cast(this)); + setArg(call_illegal_store_579, 1, 6); + setArg(call_illegal_store_579, 2, EEW); + setArg(call_illegal_store_579, 3, illegal_store_579_arg2); + setRet(call_illegal_store_579, 0, ret_val_illegal_store_579); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_580; + auto vsseg_580_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_580_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_580_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_580_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_580 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_580, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_580, 64, false), traits::vstart); + setArg(call_vsseg_580, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_580, 1, V); + setArg(call_vsseg_580, 2, vsseg_580_arg1); + setArg(call_vsseg_580, 3, vsseg_580_arg2); + setArg(call_vsseg_580, 4, vsseg_580_arg3); + setArg(call_vsseg_580, 5, vm); + setArg(call_vsseg_580, 6, vs3); + setArg(call_vsseg_580, 7, vsseg_580_arg6); + setArg(call_vsseg_580, 8, 5); + setArg(call_vsseg_580, 9, 6); + setRet(call_vsseg_580, 0, ret_val_vsseg_580); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 256); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 257: VSSEG6E32__V */ + continuation_e __vsseg6e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG6E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 257); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_581; + x86::Gp ret_val_get_pow_581 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_581, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_582; + x86::Gp ret_val_get_sew_pow_582 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_582, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_583; + x86::Gp ret_val_get_lmul_pow_583 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_583, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_581, ret_val_get_sew_pow_582), ret_val_get_lmul_pow_583)), 3, true); + setArg(call_get_pow_581, 0, reinterpret_cast(this)); + setArg(call_get_pow_581, 1, EEW); + setRet(call_get_pow_581, 0, ret_val_get_pow_581); + setArg(call_get_sew_pow_582, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_582, 0, ret_val_get_sew_pow_582); + setArg(call_get_lmul_pow_583, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_583, 0, ret_val_get_lmul_pow_583); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_584; + auto illegal_store_584_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_584 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_584, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_584; + setArg(call_illegal_store_584, 0, reinterpret_cast(this)); + setArg(call_illegal_store_584, 1, 6); + setArg(call_illegal_store_584, 2, EEW); + setArg(call_illegal_store_584, 3, illegal_store_584_arg2); + setRet(call_illegal_store_584, 0, ret_val_illegal_store_584); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_585; + auto vsseg_585_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_585_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_585_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_585_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_585 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_585, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_585, 64, false), traits::vstart); + setArg(call_vsseg_585, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_585, 1, V); + setArg(call_vsseg_585, 2, vsseg_585_arg1); + setArg(call_vsseg_585, 3, vsseg_585_arg2); + setArg(call_vsseg_585, 4, vsseg_585_arg3); + setArg(call_vsseg_585, 5, vm); + setArg(call_vsseg_585, 6, vs3); + setArg(call_vsseg_585, 7, vsseg_585_arg6); + setArg(call_vsseg_585, 8, 6); + setArg(call_vsseg_585, 9, 6); + setRet(call_vsseg_585, 0, ret_val_vsseg_585); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 257); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 258: VSSEG6E64__V */ + continuation_e __vsseg6e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg6e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG6E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 258); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_586; + x86::Gp ret_val_get_pow_586 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_586, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_587; + x86::Gp ret_val_get_sew_pow_587 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_587, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_588; + x86::Gp ret_val_get_lmul_pow_588 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_588, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_586, ret_val_get_sew_pow_587), ret_val_get_lmul_pow_588)), 3, true); + setArg(call_get_pow_586, 0, reinterpret_cast(this)); + setArg(call_get_pow_586, 1, EEW); + setRet(call_get_pow_586, 0, ret_val_get_pow_586); + setArg(call_get_sew_pow_587, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_587, 0, ret_val_get_sew_pow_587); + setArg(call_get_lmul_pow_588, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_588, 0, ret_val_get_lmul_pow_588); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_589; + auto illegal_store_589_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_589 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_589, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_589; + setArg(call_illegal_store_589, 0, reinterpret_cast(this)); + setArg(call_illegal_store_589, 1, 6); + setArg(call_illegal_store_589, 2, EEW); + setArg(call_illegal_store_589, 3, illegal_store_589_arg2); + setRet(call_illegal_store_589, 0, ret_val_illegal_store_589); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_590; + auto vsseg_590_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_590_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_590_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_590_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_590 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_590, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_590, 64, false), traits::vstart); + setArg(call_vsseg_590, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_590, 1, V); + setArg(call_vsseg_590, 2, vsseg_590_arg1); + setArg(call_vsseg_590, 3, vsseg_590_arg2); + setArg(call_vsseg_590, 4, vsseg_590_arg3); + setArg(call_vsseg_590, 5, vm); + setArg(call_vsseg_590, 6, vs3); + setArg(call_vsseg_590, 7, vsseg_590_arg6); + setArg(call_vsseg_590, 8, 7); + setArg(call_vsseg_590, 9, 6); + setRet(call_vsseg_590, 0, ret_val_vsseg_590); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 258); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 259: VSSEG7E8__V */ + continuation_e __vsseg7e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG7E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 259); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_591; + x86::Gp ret_val_get_pow_591 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_591, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_592; + x86::Gp ret_val_get_sew_pow_592 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_592, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_593; + x86::Gp ret_val_get_lmul_pow_593 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_593, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_591, ret_val_get_sew_pow_592), ret_val_get_lmul_pow_593)), 3, true); + setArg(call_get_pow_591, 0, reinterpret_cast(this)); + setArg(call_get_pow_591, 1, EEW); + setRet(call_get_pow_591, 0, ret_val_get_pow_591); + setArg(call_get_sew_pow_592, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_592, 0, ret_val_get_sew_pow_592); + setArg(call_get_lmul_pow_593, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_593, 0, ret_val_get_lmul_pow_593); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_594; + auto illegal_store_594_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_594 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_594, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_594; + setArg(call_illegal_store_594, 0, reinterpret_cast(this)); + setArg(call_illegal_store_594, 1, 7); + setArg(call_illegal_store_594, 2, EEW); + setArg(call_illegal_store_594, 3, illegal_store_594_arg2); + setRet(call_illegal_store_594, 0, ret_val_illegal_store_594); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_595; + auto vsseg_595_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_595_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_595_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_595_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_595 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_595, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_595, 64, false), traits::vstart); + setArg(call_vsseg_595, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_595, 1, V); + setArg(call_vsseg_595, 2, vsseg_595_arg1); + setArg(call_vsseg_595, 3, vsseg_595_arg2); + setArg(call_vsseg_595, 4, vsseg_595_arg3); + setArg(call_vsseg_595, 5, vm); + setArg(call_vsseg_595, 6, vs3); + setArg(call_vsseg_595, 7, vsseg_595_arg6); + setArg(call_vsseg_595, 8, 0); + setArg(call_vsseg_595, 9, 7); + setRet(call_vsseg_595, 0, ret_val_vsseg_595); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 259); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 260: VSSEG7E16__V */ + continuation_e __vsseg7e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG7E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 260); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_596; + x86::Gp ret_val_get_pow_596 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_596, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_597; + x86::Gp ret_val_get_sew_pow_597 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_597, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_598; + x86::Gp ret_val_get_lmul_pow_598 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_598, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_596, ret_val_get_sew_pow_597), ret_val_get_lmul_pow_598)), 3, true); + setArg(call_get_pow_596, 0, reinterpret_cast(this)); + setArg(call_get_pow_596, 1, EEW); + setRet(call_get_pow_596, 0, ret_val_get_pow_596); + setArg(call_get_sew_pow_597, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_597, 0, ret_val_get_sew_pow_597); + setArg(call_get_lmul_pow_598, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_598, 0, ret_val_get_lmul_pow_598); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_599; + auto illegal_store_599_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_599 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_599, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_599; + setArg(call_illegal_store_599, 0, reinterpret_cast(this)); + setArg(call_illegal_store_599, 1, 7); + setArg(call_illegal_store_599, 2, EEW); + setArg(call_illegal_store_599, 3, illegal_store_599_arg2); + setRet(call_illegal_store_599, 0, ret_val_illegal_store_599); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_600; + auto vsseg_600_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_600_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_600_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_600_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_600 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_600, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_600, 64, false), traits::vstart); + setArg(call_vsseg_600, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_600, 1, V); + setArg(call_vsseg_600, 2, vsseg_600_arg1); + setArg(call_vsseg_600, 3, vsseg_600_arg2); + setArg(call_vsseg_600, 4, vsseg_600_arg3); + setArg(call_vsseg_600, 5, vm); + setArg(call_vsseg_600, 6, vs3); + setArg(call_vsseg_600, 7, vsseg_600_arg6); + setArg(call_vsseg_600, 8, 5); + setArg(call_vsseg_600, 9, 7); + setRet(call_vsseg_600, 0, ret_val_vsseg_600); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 260); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 261: VSSEG7E32__V */ + continuation_e __vsseg7e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG7E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 261); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_601; + x86::Gp ret_val_get_pow_601 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_601, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_602; + x86::Gp ret_val_get_sew_pow_602 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_602, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_603; + x86::Gp ret_val_get_lmul_pow_603 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_603, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_601, ret_val_get_sew_pow_602), ret_val_get_lmul_pow_603)), 3, true); + setArg(call_get_pow_601, 0, reinterpret_cast(this)); + setArg(call_get_pow_601, 1, EEW); + setRet(call_get_pow_601, 0, ret_val_get_pow_601); + setArg(call_get_sew_pow_602, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_602, 0, ret_val_get_sew_pow_602); + setArg(call_get_lmul_pow_603, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_603, 0, ret_val_get_lmul_pow_603); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_604; + auto illegal_store_604_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_604 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_604, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_604; + setArg(call_illegal_store_604, 0, reinterpret_cast(this)); + setArg(call_illegal_store_604, 1, 7); + setArg(call_illegal_store_604, 2, EEW); + setArg(call_illegal_store_604, 3, illegal_store_604_arg2); + setRet(call_illegal_store_604, 0, ret_val_illegal_store_604); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_605; + auto vsseg_605_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_605_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_605_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_605_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_605 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_605, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_605, 64, false), traits::vstart); + setArg(call_vsseg_605, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_605, 1, V); + setArg(call_vsseg_605, 2, vsseg_605_arg1); + setArg(call_vsseg_605, 3, vsseg_605_arg2); + setArg(call_vsseg_605, 4, vsseg_605_arg3); + setArg(call_vsseg_605, 5, vm); + setArg(call_vsseg_605, 6, vs3); + setArg(call_vsseg_605, 7, vsseg_605_arg6); + setArg(call_vsseg_605, 8, 6); + setArg(call_vsseg_605, 9, 7); + setRet(call_vsseg_605, 0, ret_val_vsseg_605); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 261); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 262: VSSEG7E64__V */ + continuation_e __vsseg7e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg7e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG7E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 262); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_606; + x86::Gp ret_val_get_pow_606 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_606, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_607; + x86::Gp ret_val_get_sew_pow_607 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_607, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_608; + x86::Gp ret_val_get_lmul_pow_608 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_608, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_606, ret_val_get_sew_pow_607), ret_val_get_lmul_pow_608)), 3, true); + setArg(call_get_pow_606, 0, reinterpret_cast(this)); + setArg(call_get_pow_606, 1, EEW); + setRet(call_get_pow_606, 0, ret_val_get_pow_606); + setArg(call_get_sew_pow_607, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_607, 0, ret_val_get_sew_pow_607); + setArg(call_get_lmul_pow_608, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_608, 0, ret_val_get_lmul_pow_608); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_609; + auto illegal_store_609_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_609 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_609, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_609; + setArg(call_illegal_store_609, 0, reinterpret_cast(this)); + setArg(call_illegal_store_609, 1, 7); + setArg(call_illegal_store_609, 2, EEW); + setArg(call_illegal_store_609, 3, illegal_store_609_arg2); + setRet(call_illegal_store_609, 0, ret_val_illegal_store_609); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_610; + auto vsseg_610_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_610_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_610_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_610_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_610 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_610, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_610, 64, false), traits::vstart); + setArg(call_vsseg_610, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_610, 1, V); + setArg(call_vsseg_610, 2, vsseg_610_arg1); + setArg(call_vsseg_610, 3, vsseg_610_arg2); + setArg(call_vsseg_610, 4, vsseg_610_arg3); + setArg(call_vsseg_610, 5, vm); + setArg(call_vsseg_610, 6, vs3); + setArg(call_vsseg_610, 7, vsseg_610_arg6); + setArg(call_vsseg_610, 8, 7); + setArg(call_vsseg_610, 9, 7); + setRet(call_vsseg_610, 0, ret_val_vsseg_610); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 262); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 263: VSSEG8E8__V */ + continuation_e __vsseg8e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG8E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 263); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_611; + x86::Gp ret_val_get_pow_611 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_611, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_612; + x86::Gp ret_val_get_sew_pow_612 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_612, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_613; + x86::Gp ret_val_get_lmul_pow_613 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_613, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_611, ret_val_get_sew_pow_612), ret_val_get_lmul_pow_613)), 3, true); + setArg(call_get_pow_611, 0, reinterpret_cast(this)); + setArg(call_get_pow_611, 1, EEW); + setRet(call_get_pow_611, 0, ret_val_get_pow_611); + setArg(call_get_sew_pow_612, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_612, 0, ret_val_get_sew_pow_612); + setArg(call_get_lmul_pow_613, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_613, 0, ret_val_get_lmul_pow_613); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_614; + auto illegal_store_614_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_614 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_614, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_614; + setArg(call_illegal_store_614, 0, reinterpret_cast(this)); + setArg(call_illegal_store_614, 1, 8); + setArg(call_illegal_store_614, 2, EEW); + setArg(call_illegal_store_614, 3, illegal_store_614_arg2); + setRet(call_illegal_store_614, 0, ret_val_illegal_store_614); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_615; + auto vsseg_615_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_615_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_615_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_615_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_615 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_615, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_615, 64, false), traits::vstart); + setArg(call_vsseg_615, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_615, 1, V); + setArg(call_vsseg_615, 2, vsseg_615_arg1); + setArg(call_vsseg_615, 3, vsseg_615_arg2); + setArg(call_vsseg_615, 4, vsseg_615_arg3); + setArg(call_vsseg_615, 5, vm); + setArg(call_vsseg_615, 6, vs3); + setArg(call_vsseg_615, 7, vsseg_615_arg6); + setArg(call_vsseg_615, 8, 0); + setArg(call_vsseg_615, 9, 8); + setRet(call_vsseg_615, 0, ret_val_vsseg_615); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 263); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 264: VSSEG8E16__V */ + continuation_e __vsseg8e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG8E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 264); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_616; + x86::Gp ret_val_get_pow_616 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_616, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_617; + x86::Gp ret_val_get_sew_pow_617 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_617, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_618; + x86::Gp ret_val_get_lmul_pow_618 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_618, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_616, ret_val_get_sew_pow_617), ret_val_get_lmul_pow_618)), 3, true); + setArg(call_get_pow_616, 0, reinterpret_cast(this)); + setArg(call_get_pow_616, 1, EEW); + setRet(call_get_pow_616, 0, ret_val_get_pow_616); + setArg(call_get_sew_pow_617, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_617, 0, ret_val_get_sew_pow_617); + setArg(call_get_lmul_pow_618, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_618, 0, ret_val_get_lmul_pow_618); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_619; + auto illegal_store_619_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_619 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_619, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_619; + setArg(call_illegal_store_619, 0, reinterpret_cast(this)); + setArg(call_illegal_store_619, 1, 8); + setArg(call_illegal_store_619, 2, EEW); + setArg(call_illegal_store_619, 3, illegal_store_619_arg2); + setRet(call_illegal_store_619, 0, ret_val_illegal_store_619); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_620; + auto vsseg_620_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_620_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_620_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_620_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_620 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_620, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_620, 64, false), traits::vstart); + setArg(call_vsseg_620, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_620, 1, V); + setArg(call_vsseg_620, 2, vsseg_620_arg1); + setArg(call_vsseg_620, 3, vsseg_620_arg2); + setArg(call_vsseg_620, 4, vsseg_620_arg3); + setArg(call_vsseg_620, 5, vm); + setArg(call_vsseg_620, 6, vs3); + setArg(call_vsseg_620, 7, vsseg_620_arg6); + setArg(call_vsseg_620, 8, 5); + setArg(call_vsseg_620, 9, 8); + setRet(call_vsseg_620, 0, ret_val_vsseg_620); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 264); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 265: VSSEG8E32__V */ + continuation_e __vsseg8e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG8E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 265); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_621; + x86::Gp ret_val_get_pow_621 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_621, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_622; + x86::Gp ret_val_get_sew_pow_622 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_622, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_623; + x86::Gp ret_val_get_lmul_pow_623 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_623, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_621, ret_val_get_sew_pow_622), ret_val_get_lmul_pow_623)), 3, true); + setArg(call_get_pow_621, 0, reinterpret_cast(this)); + setArg(call_get_pow_621, 1, EEW); + setRet(call_get_pow_621, 0, ret_val_get_pow_621); + setArg(call_get_sew_pow_622, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_622, 0, ret_val_get_sew_pow_622); + setArg(call_get_lmul_pow_623, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_623, 0, ret_val_get_lmul_pow_623); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_624; + auto illegal_store_624_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_624 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_624, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_624; + setArg(call_illegal_store_624, 0, reinterpret_cast(this)); + setArg(call_illegal_store_624, 1, 8); + setArg(call_illegal_store_624, 2, EEW); + setArg(call_illegal_store_624, 3, illegal_store_624_arg2); + setRet(call_illegal_store_624, 0, ret_val_illegal_store_624); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_625; + auto vsseg_625_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_625_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_625_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_625_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_625 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_625, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_625, 64, false), traits::vstart); + setArg(call_vsseg_625, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_625, 1, V); + setArg(call_vsseg_625, 2, vsseg_625_arg1); + setArg(call_vsseg_625, 3, vsseg_625_arg2); + setArg(call_vsseg_625, 4, vsseg_625_arg3); + setArg(call_vsseg_625, 5, vm); + setArg(call_vsseg_625, 6, vs3); + setArg(call_vsseg_625, 7, vsseg_625_arg6); + setArg(call_vsseg_625, 8, 6); + setArg(call_vsseg_625, 9, 8); + setRet(call_vsseg_625, 0, ret_val_vsseg_625); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 265); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 266: VSSEG8E64__V */ + continuation_e __vsseg8e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsseg8e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSEG8E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 266); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_626; + x86::Gp ret_val_get_pow_626 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_626, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_627; + x86::Gp ret_val_get_sew_pow_627 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_627, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_628; + x86::Gp ret_val_get_lmul_pow_628 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_628, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_626, ret_val_get_sew_pow_627), ret_val_get_lmul_pow_628)), 3, true); + setArg(call_get_pow_626, 0, reinterpret_cast(this)); + setArg(call_get_pow_626, 1, EEW); + setRet(call_get_pow_626, 0, ret_val_get_pow_626); + setArg(call_get_sew_pow_627, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_627, 0, ret_val_get_sew_pow_627); + setArg(call_get_lmul_pow_628, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_628, 0, ret_val_get_lmul_pow_628); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_629; + auto illegal_store_629_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_629 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_629, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_629; + setArg(call_illegal_store_629, 0, reinterpret_cast(this)); + setArg(call_illegal_store_629, 1, 8); + setArg(call_illegal_store_629, 2, EEW); + setArg(call_illegal_store_629, 3, illegal_store_629_arg2); + setRet(call_illegal_store_629, 0, ret_val_illegal_store_629); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_630; + auto vsseg_630_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsseg_630_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_630_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_630_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_630 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_630, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_630, 64, false), traits::vstart); + setArg(call_vsseg_630, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_630, 1, V); + setArg(call_vsseg_630, 2, vsseg_630_arg1); + setArg(call_vsseg_630, 3, vsseg_630_arg2); + setArg(call_vsseg_630, 4, vsseg_630_arg3); + setArg(call_vsseg_630, 5, vm); + setArg(call_vsseg_630, 6, vs3); + setArg(call_vsseg_630, 7, vsseg_630_arg6); + setArg(call_vsseg_630, 8, 7); + setArg(call_vsseg_630, 9, 8); + setRet(call_vsseg_630, 0, ret_val_vsseg_630); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 266); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 267: VLSE8__V */ + continuation_e __vlse8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 267); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_631; + x86::Gp ret_val_get_pow_631 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_631, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_632; + x86::Gp ret_val_get_sew_pow_632 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_632, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_633; + x86::Gp ret_val_get_lmul_pow_633 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_633, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_631, ret_val_get_sew_pow_632), ret_val_get_lmul_pow_633)), 3, true); + setArg(call_get_pow_631, 0, reinterpret_cast(this)); + setArg(call_get_pow_631, 1, EEW); + setRet(call_get_pow_631, 0, ret_val_get_pow_631); + setArg(call_get_sew_pow_632, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_632, 0, ret_val_get_sew_pow_632); + setArg(call_get_lmul_pow_633, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_633, 0, ret_val_get_lmul_pow_633); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_634; + auto illegal_load_634_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_634 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_634, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_634; + setArg(call_illegal_load_634, 0, reinterpret_cast(this)); + setArg(call_illegal_load_634, 1, vd); + setArg(call_illegal_load_634, 2, vm); + setArg(call_illegal_load_634, 3, 1); + setArg(call_illegal_load_634, 4, EEW); + setArg(call_illegal_load_634, 5, illegal_load_634_arg4); + setRet(call_illegal_load_634, 0, ret_val_illegal_load_634); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_635; + auto vlsseg_635_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_635_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_635_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_635_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_635_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_635 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_635, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_635, 64, false), traits::vstart); + setArg(call_vlsseg_635, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_635, 1, V); + setArg(call_vlsseg_635, 2, vlsseg_635_arg1); + setArg(call_vlsseg_635, 3, vlsseg_635_arg2); + setArg(call_vlsseg_635, 4, vlsseg_635_arg3); + setArg(call_vlsseg_635, 5, vm); + setArg(call_vlsseg_635, 6, vd); + setArg(call_vlsseg_635, 7, vlsseg_635_arg6); + setArg(call_vlsseg_635, 8, 0); + setArg(call_vlsseg_635, 9, 1); + setArg(call_vlsseg_635, 10, vlsseg_635_arg9); + setRet(call_vlsseg_635, 0, ret_val_vlsseg_635); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 267); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 268: VLSE16__V */ + continuation_e __vlse16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 268); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_636; + x86::Gp ret_val_get_pow_636 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_636, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_637; + x86::Gp ret_val_get_sew_pow_637 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_637, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_638; + x86::Gp ret_val_get_lmul_pow_638 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_638, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_636, ret_val_get_sew_pow_637), ret_val_get_lmul_pow_638)), 3, true); + setArg(call_get_pow_636, 0, reinterpret_cast(this)); + setArg(call_get_pow_636, 1, EEW); + setRet(call_get_pow_636, 0, ret_val_get_pow_636); + setArg(call_get_sew_pow_637, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_637, 0, ret_val_get_sew_pow_637); + setArg(call_get_lmul_pow_638, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_638, 0, ret_val_get_lmul_pow_638); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_639; + auto illegal_load_639_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_639 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_639, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_639; + setArg(call_illegal_load_639, 0, reinterpret_cast(this)); + setArg(call_illegal_load_639, 1, vd); + setArg(call_illegal_load_639, 2, vm); + setArg(call_illegal_load_639, 3, 1); + setArg(call_illegal_load_639, 4, EEW); + setArg(call_illegal_load_639, 5, illegal_load_639_arg4); + setRet(call_illegal_load_639, 0, ret_val_illegal_load_639); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_640; + auto vlsseg_640_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_640_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_640_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_640_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_640_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_640 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_640, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_640, 64, false), traits::vstart); + setArg(call_vlsseg_640, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_640, 1, V); + setArg(call_vlsseg_640, 2, vlsseg_640_arg1); + setArg(call_vlsseg_640, 3, vlsseg_640_arg2); + setArg(call_vlsseg_640, 4, vlsseg_640_arg3); + setArg(call_vlsseg_640, 5, vm); + setArg(call_vlsseg_640, 6, vd); + setArg(call_vlsseg_640, 7, vlsseg_640_arg6); + setArg(call_vlsseg_640, 8, 5); + setArg(call_vlsseg_640, 9, 1); + setArg(call_vlsseg_640, 10, vlsseg_640_arg9); + setRet(call_vlsseg_640, 0, ret_val_vlsseg_640); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 268); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 269: VLSE32__V */ + continuation_e __vlse32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 269); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_641; + x86::Gp ret_val_get_pow_641 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_641, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_642; + x86::Gp ret_val_get_sew_pow_642 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_642, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_643; + x86::Gp ret_val_get_lmul_pow_643 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_643, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_641, ret_val_get_sew_pow_642), ret_val_get_lmul_pow_643)), 3, true); + setArg(call_get_pow_641, 0, reinterpret_cast(this)); + setArg(call_get_pow_641, 1, EEW); + setRet(call_get_pow_641, 0, ret_val_get_pow_641); + setArg(call_get_sew_pow_642, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_642, 0, ret_val_get_sew_pow_642); + setArg(call_get_lmul_pow_643, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_643, 0, ret_val_get_lmul_pow_643); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_644; + auto illegal_load_644_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_644 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_644, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_644; + setArg(call_illegal_load_644, 0, reinterpret_cast(this)); + setArg(call_illegal_load_644, 1, vd); + setArg(call_illegal_load_644, 2, vm); + setArg(call_illegal_load_644, 3, 1); + setArg(call_illegal_load_644, 4, EEW); + setArg(call_illegal_load_644, 5, illegal_load_644_arg4); + setRet(call_illegal_load_644, 0, ret_val_illegal_load_644); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_645; + auto vlsseg_645_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_645_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_645_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_645_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_645_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_645 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_645, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_645, 64, false), traits::vstart); + setArg(call_vlsseg_645, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_645, 1, V); + setArg(call_vlsseg_645, 2, vlsseg_645_arg1); + setArg(call_vlsseg_645, 3, vlsseg_645_arg2); + setArg(call_vlsseg_645, 4, vlsseg_645_arg3); + setArg(call_vlsseg_645, 5, vm); + setArg(call_vlsseg_645, 6, vd); + setArg(call_vlsseg_645, 7, vlsseg_645_arg6); + setArg(call_vlsseg_645, 8, 6); + setArg(call_vlsseg_645, 9, 1); + setArg(call_vlsseg_645, 10, vlsseg_645_arg9); + setRet(call_vlsseg_645, 0, ret_val_vlsseg_645); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 269); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 270: VLSE64__V */ + continuation_e __vlse64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlse64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 270); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_646; + x86::Gp ret_val_get_pow_646 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_646, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_647; + x86::Gp ret_val_get_sew_pow_647 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_647, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_648; + x86::Gp ret_val_get_lmul_pow_648 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_648, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_646, ret_val_get_sew_pow_647), ret_val_get_lmul_pow_648)), 3, true); + setArg(call_get_pow_646, 0, reinterpret_cast(this)); + setArg(call_get_pow_646, 1, EEW); + setRet(call_get_pow_646, 0, ret_val_get_pow_646); + setArg(call_get_sew_pow_647, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_647, 0, ret_val_get_sew_pow_647); + setArg(call_get_lmul_pow_648, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_648, 0, ret_val_get_lmul_pow_648); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_649; + auto illegal_load_649_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_649 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_649, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_649; + setArg(call_illegal_load_649, 0, reinterpret_cast(this)); + setArg(call_illegal_load_649, 1, vd); + setArg(call_illegal_load_649, 2, vm); + setArg(call_illegal_load_649, 3, 1); + setArg(call_illegal_load_649, 4, EEW); + setArg(call_illegal_load_649, 5, illegal_load_649_arg4); + setRet(call_illegal_load_649, 0, ret_val_illegal_load_649); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_650; + auto vlsseg_650_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_650_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_650_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_650_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_650_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_650 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_650, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_650, 64, false), traits::vstart); + setArg(call_vlsseg_650, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_650, 1, V); + setArg(call_vlsseg_650, 2, vlsseg_650_arg1); + setArg(call_vlsseg_650, 3, vlsseg_650_arg2); + setArg(call_vlsseg_650, 4, vlsseg_650_arg3); + setArg(call_vlsseg_650, 5, vm); + setArg(call_vlsseg_650, 6, vd); + setArg(call_vlsseg_650, 7, vlsseg_650_arg6); + setArg(call_vlsseg_650, 8, 7); + setArg(call_vlsseg_650, 9, 1); + setArg(call_vlsseg_650, 10, vlsseg_650_arg9); + setRet(call_vlsseg_650, 0, ret_val_vlsseg_650); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 270); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 271: VLSSEG2E8__V */ + continuation_e __vlsseg2e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG2E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 271); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_651; + x86::Gp ret_val_get_pow_651 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_651, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_652; + x86::Gp ret_val_get_sew_pow_652 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_652, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_653; + x86::Gp ret_val_get_lmul_pow_653 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_653, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_651, ret_val_get_sew_pow_652), ret_val_get_lmul_pow_653)), 3, true); + setArg(call_get_pow_651, 0, reinterpret_cast(this)); + setArg(call_get_pow_651, 1, EEW); + setRet(call_get_pow_651, 0, ret_val_get_pow_651); + setArg(call_get_sew_pow_652, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_652, 0, ret_val_get_sew_pow_652); + setArg(call_get_lmul_pow_653, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_653, 0, ret_val_get_lmul_pow_653); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_654; + auto illegal_load_654_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_654 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_654, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_654; + setArg(call_illegal_load_654, 0, reinterpret_cast(this)); + setArg(call_illegal_load_654, 1, vd); + setArg(call_illegal_load_654, 2, vm); + setArg(call_illegal_load_654, 3, 2); + setArg(call_illegal_load_654, 4, EEW); + setArg(call_illegal_load_654, 5, illegal_load_654_arg4); + setRet(call_illegal_load_654, 0, ret_val_illegal_load_654); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_655; + auto vlsseg_655_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_655_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_655_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_655_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_655_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_655 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_655, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_655, 64, false), traits::vstart); + setArg(call_vlsseg_655, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_655, 1, V); + setArg(call_vlsseg_655, 2, vlsseg_655_arg1); + setArg(call_vlsseg_655, 3, vlsseg_655_arg2); + setArg(call_vlsseg_655, 4, vlsseg_655_arg3); + setArg(call_vlsseg_655, 5, vm); + setArg(call_vlsseg_655, 6, vd); + setArg(call_vlsseg_655, 7, vlsseg_655_arg6); + setArg(call_vlsseg_655, 8, 0); + setArg(call_vlsseg_655, 9, 2); + setArg(call_vlsseg_655, 10, vlsseg_655_arg9); + setRet(call_vlsseg_655, 0, ret_val_vlsseg_655); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 271); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 272: VLSSEG2E16__V */ + continuation_e __vlsseg2e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG2E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 272); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_656; + x86::Gp ret_val_get_pow_656 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_656, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_657; + x86::Gp ret_val_get_sew_pow_657 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_657, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_658; + x86::Gp ret_val_get_lmul_pow_658 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_658, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_656, ret_val_get_sew_pow_657), ret_val_get_lmul_pow_658)), 3, true); + setArg(call_get_pow_656, 0, reinterpret_cast(this)); + setArg(call_get_pow_656, 1, EEW); + setRet(call_get_pow_656, 0, ret_val_get_pow_656); + setArg(call_get_sew_pow_657, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_657, 0, ret_val_get_sew_pow_657); + setArg(call_get_lmul_pow_658, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_658, 0, ret_val_get_lmul_pow_658); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_659; + auto illegal_load_659_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_659 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_659, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_659; + setArg(call_illegal_load_659, 0, reinterpret_cast(this)); + setArg(call_illegal_load_659, 1, vd); + setArg(call_illegal_load_659, 2, vm); + setArg(call_illegal_load_659, 3, 2); + setArg(call_illegal_load_659, 4, EEW); + setArg(call_illegal_load_659, 5, illegal_load_659_arg4); + setRet(call_illegal_load_659, 0, ret_val_illegal_load_659); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_660; + auto vlsseg_660_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_660_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_660_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_660_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_660_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_660 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_660, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_660, 64, false), traits::vstart); + setArg(call_vlsseg_660, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_660, 1, V); + setArg(call_vlsseg_660, 2, vlsseg_660_arg1); + setArg(call_vlsseg_660, 3, vlsseg_660_arg2); + setArg(call_vlsseg_660, 4, vlsseg_660_arg3); + setArg(call_vlsseg_660, 5, vm); + setArg(call_vlsseg_660, 6, vd); + setArg(call_vlsseg_660, 7, vlsseg_660_arg6); + setArg(call_vlsseg_660, 8, 5); + setArg(call_vlsseg_660, 9, 2); + setArg(call_vlsseg_660, 10, vlsseg_660_arg9); + setRet(call_vlsseg_660, 0, ret_val_vlsseg_660); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 272); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 273: VLSSEG2E32__V */ + continuation_e __vlsseg2e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG2E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 273); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_661; + x86::Gp ret_val_get_pow_661 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_661, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_662; + x86::Gp ret_val_get_sew_pow_662 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_662, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_663; + x86::Gp ret_val_get_lmul_pow_663 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_663, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_661, ret_val_get_sew_pow_662), ret_val_get_lmul_pow_663)), 3, true); + setArg(call_get_pow_661, 0, reinterpret_cast(this)); + setArg(call_get_pow_661, 1, EEW); + setRet(call_get_pow_661, 0, ret_val_get_pow_661); + setArg(call_get_sew_pow_662, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_662, 0, ret_val_get_sew_pow_662); + setArg(call_get_lmul_pow_663, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_663, 0, ret_val_get_lmul_pow_663); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_664; + auto illegal_load_664_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_664 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_664, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_664; + setArg(call_illegal_load_664, 0, reinterpret_cast(this)); + setArg(call_illegal_load_664, 1, vd); + setArg(call_illegal_load_664, 2, vm); + setArg(call_illegal_load_664, 3, 2); + setArg(call_illegal_load_664, 4, EEW); + setArg(call_illegal_load_664, 5, illegal_load_664_arg4); + setRet(call_illegal_load_664, 0, ret_val_illegal_load_664); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_665; + auto vlsseg_665_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_665_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_665_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_665_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_665_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_665 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_665, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_665, 64, false), traits::vstart); + setArg(call_vlsseg_665, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_665, 1, V); + setArg(call_vlsseg_665, 2, vlsseg_665_arg1); + setArg(call_vlsseg_665, 3, vlsseg_665_arg2); + setArg(call_vlsseg_665, 4, vlsseg_665_arg3); + setArg(call_vlsseg_665, 5, vm); + setArg(call_vlsseg_665, 6, vd); + setArg(call_vlsseg_665, 7, vlsseg_665_arg6); + setArg(call_vlsseg_665, 8, 6); + setArg(call_vlsseg_665, 9, 2); + setArg(call_vlsseg_665, 10, vlsseg_665_arg9); + setRet(call_vlsseg_665, 0, ret_val_vlsseg_665); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 273); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 274: VLSSEG2E64__V */ + continuation_e __vlsseg2e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg2e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG2E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 274); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_666; + x86::Gp ret_val_get_pow_666 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_666, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_667; + x86::Gp ret_val_get_sew_pow_667 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_667, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_668; + x86::Gp ret_val_get_lmul_pow_668 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_668, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_666, ret_val_get_sew_pow_667), ret_val_get_lmul_pow_668)), 3, true); + setArg(call_get_pow_666, 0, reinterpret_cast(this)); + setArg(call_get_pow_666, 1, EEW); + setRet(call_get_pow_666, 0, ret_val_get_pow_666); + setArg(call_get_sew_pow_667, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_667, 0, ret_val_get_sew_pow_667); + setArg(call_get_lmul_pow_668, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_668, 0, ret_val_get_lmul_pow_668); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_669; + auto illegal_load_669_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_669 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_669, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_669; + setArg(call_illegal_load_669, 0, reinterpret_cast(this)); + setArg(call_illegal_load_669, 1, vd); + setArg(call_illegal_load_669, 2, vm); + setArg(call_illegal_load_669, 3, 2); + setArg(call_illegal_load_669, 4, EEW); + setArg(call_illegal_load_669, 5, illegal_load_669_arg4); + setRet(call_illegal_load_669, 0, ret_val_illegal_load_669); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_670; + auto vlsseg_670_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_670_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_670_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_670_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_670_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_670 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_670, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_670, 64, false), traits::vstart); + setArg(call_vlsseg_670, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_670, 1, V); + setArg(call_vlsseg_670, 2, vlsseg_670_arg1); + setArg(call_vlsseg_670, 3, vlsseg_670_arg2); + setArg(call_vlsseg_670, 4, vlsseg_670_arg3); + setArg(call_vlsseg_670, 5, vm); + setArg(call_vlsseg_670, 6, vd); + setArg(call_vlsseg_670, 7, vlsseg_670_arg6); + setArg(call_vlsseg_670, 8, 7); + setArg(call_vlsseg_670, 9, 2); + setArg(call_vlsseg_670, 10, vlsseg_670_arg9); + setRet(call_vlsseg_670, 0, ret_val_vlsseg_670); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 274); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 275: VLSSEG3E8__V */ + continuation_e __vlsseg3e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG3E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 275); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_671; + x86::Gp ret_val_get_pow_671 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_671, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_672; + x86::Gp ret_val_get_sew_pow_672 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_672, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_673; + x86::Gp ret_val_get_lmul_pow_673 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_673, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_671, ret_val_get_sew_pow_672), ret_val_get_lmul_pow_673)), 3, true); + setArg(call_get_pow_671, 0, reinterpret_cast(this)); + setArg(call_get_pow_671, 1, EEW); + setRet(call_get_pow_671, 0, ret_val_get_pow_671); + setArg(call_get_sew_pow_672, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_672, 0, ret_val_get_sew_pow_672); + setArg(call_get_lmul_pow_673, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_673, 0, ret_val_get_lmul_pow_673); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_674; + auto illegal_load_674_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_674 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_674, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_674; + setArg(call_illegal_load_674, 0, reinterpret_cast(this)); + setArg(call_illegal_load_674, 1, vd); + setArg(call_illegal_load_674, 2, vm); + setArg(call_illegal_load_674, 3, 3); + setArg(call_illegal_load_674, 4, EEW); + setArg(call_illegal_load_674, 5, illegal_load_674_arg4); + setRet(call_illegal_load_674, 0, ret_val_illegal_load_674); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_675; + auto vlsseg_675_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_675_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_675_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_675_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_675_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_675 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_675, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_675, 64, false), traits::vstart); + setArg(call_vlsseg_675, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_675, 1, V); + setArg(call_vlsseg_675, 2, vlsseg_675_arg1); + setArg(call_vlsseg_675, 3, vlsseg_675_arg2); + setArg(call_vlsseg_675, 4, vlsseg_675_arg3); + setArg(call_vlsseg_675, 5, vm); + setArg(call_vlsseg_675, 6, vd); + setArg(call_vlsseg_675, 7, vlsseg_675_arg6); + setArg(call_vlsseg_675, 8, 0); + setArg(call_vlsseg_675, 9, 3); + setArg(call_vlsseg_675, 10, vlsseg_675_arg9); + setRet(call_vlsseg_675, 0, ret_val_vlsseg_675); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 275); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 276: VLSSEG3E16__V */ + continuation_e __vlsseg3e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG3E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 276); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_676; + x86::Gp ret_val_get_pow_676 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_676, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_677; + x86::Gp ret_val_get_sew_pow_677 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_677, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_678; + x86::Gp ret_val_get_lmul_pow_678 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_678, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_676, ret_val_get_sew_pow_677), ret_val_get_lmul_pow_678)), 3, true); + setArg(call_get_pow_676, 0, reinterpret_cast(this)); + setArg(call_get_pow_676, 1, EEW); + setRet(call_get_pow_676, 0, ret_val_get_pow_676); + setArg(call_get_sew_pow_677, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_677, 0, ret_val_get_sew_pow_677); + setArg(call_get_lmul_pow_678, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_678, 0, ret_val_get_lmul_pow_678); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_679; + auto illegal_load_679_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_679 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_679, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_679; + setArg(call_illegal_load_679, 0, reinterpret_cast(this)); + setArg(call_illegal_load_679, 1, vd); + setArg(call_illegal_load_679, 2, vm); + setArg(call_illegal_load_679, 3, 3); + setArg(call_illegal_load_679, 4, EEW); + setArg(call_illegal_load_679, 5, illegal_load_679_arg4); + setRet(call_illegal_load_679, 0, ret_val_illegal_load_679); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_680; + auto vlsseg_680_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_680_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_680_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_680_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_680_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_680 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_680, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_680, 64, false), traits::vstart); + setArg(call_vlsseg_680, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_680, 1, V); + setArg(call_vlsseg_680, 2, vlsseg_680_arg1); + setArg(call_vlsseg_680, 3, vlsseg_680_arg2); + setArg(call_vlsseg_680, 4, vlsseg_680_arg3); + setArg(call_vlsseg_680, 5, vm); + setArg(call_vlsseg_680, 6, vd); + setArg(call_vlsseg_680, 7, vlsseg_680_arg6); + setArg(call_vlsseg_680, 8, 5); + setArg(call_vlsseg_680, 9, 3); + setArg(call_vlsseg_680, 10, vlsseg_680_arg9); + setRet(call_vlsseg_680, 0, ret_val_vlsseg_680); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 276); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 277: VLSSEG3E32__V */ + continuation_e __vlsseg3e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG3E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 277); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_681; + x86::Gp ret_val_get_pow_681 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_681, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_682; + x86::Gp ret_val_get_sew_pow_682 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_682, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_683; + x86::Gp ret_val_get_lmul_pow_683 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_683, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_681, ret_val_get_sew_pow_682), ret_val_get_lmul_pow_683)), 3, true); + setArg(call_get_pow_681, 0, reinterpret_cast(this)); + setArg(call_get_pow_681, 1, EEW); + setRet(call_get_pow_681, 0, ret_val_get_pow_681); + setArg(call_get_sew_pow_682, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_682, 0, ret_val_get_sew_pow_682); + setArg(call_get_lmul_pow_683, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_683, 0, ret_val_get_lmul_pow_683); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_684; + auto illegal_load_684_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_684 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_684, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_684; + setArg(call_illegal_load_684, 0, reinterpret_cast(this)); + setArg(call_illegal_load_684, 1, vd); + setArg(call_illegal_load_684, 2, vm); + setArg(call_illegal_load_684, 3, 3); + setArg(call_illegal_load_684, 4, EEW); + setArg(call_illegal_load_684, 5, illegal_load_684_arg4); + setRet(call_illegal_load_684, 0, ret_val_illegal_load_684); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_685; + auto vlsseg_685_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_685_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_685_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_685_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_685_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_685 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_685, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_685, 64, false), traits::vstart); + setArg(call_vlsseg_685, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_685, 1, V); + setArg(call_vlsseg_685, 2, vlsseg_685_arg1); + setArg(call_vlsseg_685, 3, vlsseg_685_arg2); + setArg(call_vlsseg_685, 4, vlsseg_685_arg3); + setArg(call_vlsseg_685, 5, vm); + setArg(call_vlsseg_685, 6, vd); + setArg(call_vlsseg_685, 7, vlsseg_685_arg6); + setArg(call_vlsseg_685, 8, 6); + setArg(call_vlsseg_685, 9, 3); + setArg(call_vlsseg_685, 10, vlsseg_685_arg9); + setRet(call_vlsseg_685, 0, ret_val_vlsseg_685); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 277); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 278: VLSSEG3E64__V */ + continuation_e __vlsseg3e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg3e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG3E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 278); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_686; + x86::Gp ret_val_get_pow_686 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_686, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_687; + x86::Gp ret_val_get_sew_pow_687 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_687, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_688; + x86::Gp ret_val_get_lmul_pow_688 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_688, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_686, ret_val_get_sew_pow_687), ret_val_get_lmul_pow_688)), 3, true); + setArg(call_get_pow_686, 0, reinterpret_cast(this)); + setArg(call_get_pow_686, 1, EEW); + setRet(call_get_pow_686, 0, ret_val_get_pow_686); + setArg(call_get_sew_pow_687, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_687, 0, ret_val_get_sew_pow_687); + setArg(call_get_lmul_pow_688, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_688, 0, ret_val_get_lmul_pow_688); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_689; + auto illegal_load_689_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_689 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_689, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_689; + setArg(call_illegal_load_689, 0, reinterpret_cast(this)); + setArg(call_illegal_load_689, 1, vd); + setArg(call_illegal_load_689, 2, vm); + setArg(call_illegal_load_689, 3, 3); + setArg(call_illegal_load_689, 4, EEW); + setArg(call_illegal_load_689, 5, illegal_load_689_arg4); + setRet(call_illegal_load_689, 0, ret_val_illegal_load_689); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_690; + auto vlsseg_690_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_690_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_690_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_690_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_690_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_690 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_690, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_690, 64, false), traits::vstart); + setArg(call_vlsseg_690, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_690, 1, V); + setArg(call_vlsseg_690, 2, vlsseg_690_arg1); + setArg(call_vlsseg_690, 3, vlsseg_690_arg2); + setArg(call_vlsseg_690, 4, vlsseg_690_arg3); + setArg(call_vlsseg_690, 5, vm); + setArg(call_vlsseg_690, 6, vd); + setArg(call_vlsseg_690, 7, vlsseg_690_arg6); + setArg(call_vlsseg_690, 8, 7); + setArg(call_vlsseg_690, 9, 3); + setArg(call_vlsseg_690, 10, vlsseg_690_arg9); + setRet(call_vlsseg_690, 0, ret_val_vlsseg_690); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 278); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 279: VLSSEG4E8__V */ + continuation_e __vlsseg4e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG4E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 279); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_691; + x86::Gp ret_val_get_pow_691 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_691, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_692; + x86::Gp ret_val_get_sew_pow_692 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_692, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_693; + x86::Gp ret_val_get_lmul_pow_693 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_693, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_691, ret_val_get_sew_pow_692), ret_val_get_lmul_pow_693)), 3, true); + setArg(call_get_pow_691, 0, reinterpret_cast(this)); + setArg(call_get_pow_691, 1, EEW); + setRet(call_get_pow_691, 0, ret_val_get_pow_691); + setArg(call_get_sew_pow_692, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_692, 0, ret_val_get_sew_pow_692); + setArg(call_get_lmul_pow_693, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_693, 0, ret_val_get_lmul_pow_693); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_694; + auto illegal_load_694_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_694 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_694, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_694; + setArg(call_illegal_load_694, 0, reinterpret_cast(this)); + setArg(call_illegal_load_694, 1, vd); + setArg(call_illegal_load_694, 2, vm); + setArg(call_illegal_load_694, 3, 4); + setArg(call_illegal_load_694, 4, EEW); + setArg(call_illegal_load_694, 5, illegal_load_694_arg4); + setRet(call_illegal_load_694, 0, ret_val_illegal_load_694); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_695; + auto vlsseg_695_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_695_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_695_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_695_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_695_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_695 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_695, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_695, 64, false), traits::vstart); + setArg(call_vlsseg_695, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_695, 1, V); + setArg(call_vlsseg_695, 2, vlsseg_695_arg1); + setArg(call_vlsseg_695, 3, vlsseg_695_arg2); + setArg(call_vlsseg_695, 4, vlsseg_695_arg3); + setArg(call_vlsseg_695, 5, vm); + setArg(call_vlsseg_695, 6, vd); + setArg(call_vlsseg_695, 7, vlsseg_695_arg6); + setArg(call_vlsseg_695, 8, 0); + setArg(call_vlsseg_695, 9, 4); + setArg(call_vlsseg_695, 10, vlsseg_695_arg9); + setRet(call_vlsseg_695, 0, ret_val_vlsseg_695); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 279); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 280: VLSSEG4E16__V */ + continuation_e __vlsseg4e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG4E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 280); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_696; + x86::Gp ret_val_get_pow_696 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_696, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_697; + x86::Gp ret_val_get_sew_pow_697 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_697, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_698; + x86::Gp ret_val_get_lmul_pow_698 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_698, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_696, ret_val_get_sew_pow_697), ret_val_get_lmul_pow_698)), 3, true); + setArg(call_get_pow_696, 0, reinterpret_cast(this)); + setArg(call_get_pow_696, 1, EEW); + setRet(call_get_pow_696, 0, ret_val_get_pow_696); + setArg(call_get_sew_pow_697, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_697, 0, ret_val_get_sew_pow_697); + setArg(call_get_lmul_pow_698, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_698, 0, ret_val_get_lmul_pow_698); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_699; + auto illegal_load_699_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_699 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_699, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_699; + setArg(call_illegal_load_699, 0, reinterpret_cast(this)); + setArg(call_illegal_load_699, 1, vd); + setArg(call_illegal_load_699, 2, vm); + setArg(call_illegal_load_699, 3, 4); + setArg(call_illegal_load_699, 4, EEW); + setArg(call_illegal_load_699, 5, illegal_load_699_arg4); + setRet(call_illegal_load_699, 0, ret_val_illegal_load_699); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_700; + auto vlsseg_700_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_700_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_700_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_700_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_700_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_700 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_700, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_700, 64, false), traits::vstart); + setArg(call_vlsseg_700, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_700, 1, V); + setArg(call_vlsseg_700, 2, vlsseg_700_arg1); + setArg(call_vlsseg_700, 3, vlsseg_700_arg2); + setArg(call_vlsseg_700, 4, vlsseg_700_arg3); + setArg(call_vlsseg_700, 5, vm); + setArg(call_vlsseg_700, 6, vd); + setArg(call_vlsseg_700, 7, vlsseg_700_arg6); + setArg(call_vlsseg_700, 8, 5); + setArg(call_vlsseg_700, 9, 4); + setArg(call_vlsseg_700, 10, vlsseg_700_arg9); + setRet(call_vlsseg_700, 0, ret_val_vlsseg_700); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 280); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 281: VLSSEG4E32__V */ + continuation_e __vlsseg4e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG4E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 281); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_701; + x86::Gp ret_val_get_pow_701 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_701, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_702; + x86::Gp ret_val_get_sew_pow_702 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_702, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_703; + x86::Gp ret_val_get_lmul_pow_703 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_703, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_701, ret_val_get_sew_pow_702), ret_val_get_lmul_pow_703)), 3, true); + setArg(call_get_pow_701, 0, reinterpret_cast(this)); + setArg(call_get_pow_701, 1, EEW); + setRet(call_get_pow_701, 0, ret_val_get_pow_701); + setArg(call_get_sew_pow_702, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_702, 0, ret_val_get_sew_pow_702); + setArg(call_get_lmul_pow_703, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_703, 0, ret_val_get_lmul_pow_703); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_704; + auto illegal_load_704_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_704 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_704, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_704; + setArg(call_illegal_load_704, 0, reinterpret_cast(this)); + setArg(call_illegal_load_704, 1, vd); + setArg(call_illegal_load_704, 2, vm); + setArg(call_illegal_load_704, 3, 4); + setArg(call_illegal_load_704, 4, EEW); + setArg(call_illegal_load_704, 5, illegal_load_704_arg4); + setRet(call_illegal_load_704, 0, ret_val_illegal_load_704); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_705; + auto vlsseg_705_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_705_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_705_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_705_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_705_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_705 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_705, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_705, 64, false), traits::vstart); + setArg(call_vlsseg_705, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_705, 1, V); + setArg(call_vlsseg_705, 2, vlsseg_705_arg1); + setArg(call_vlsseg_705, 3, vlsseg_705_arg2); + setArg(call_vlsseg_705, 4, vlsseg_705_arg3); + setArg(call_vlsseg_705, 5, vm); + setArg(call_vlsseg_705, 6, vd); + setArg(call_vlsseg_705, 7, vlsseg_705_arg6); + setArg(call_vlsseg_705, 8, 6); + setArg(call_vlsseg_705, 9, 4); + setArg(call_vlsseg_705, 10, vlsseg_705_arg9); + setRet(call_vlsseg_705, 0, ret_val_vlsseg_705); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 281); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 282: VLSSEG4E64__V */ + continuation_e __vlsseg4e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg4e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG4E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 282); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_706; + x86::Gp ret_val_get_pow_706 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_706, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_707; + x86::Gp ret_val_get_sew_pow_707 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_707, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_708; + x86::Gp ret_val_get_lmul_pow_708 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_708, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_706, ret_val_get_sew_pow_707), ret_val_get_lmul_pow_708)), 3, true); + setArg(call_get_pow_706, 0, reinterpret_cast(this)); + setArg(call_get_pow_706, 1, EEW); + setRet(call_get_pow_706, 0, ret_val_get_pow_706); + setArg(call_get_sew_pow_707, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_707, 0, ret_val_get_sew_pow_707); + setArg(call_get_lmul_pow_708, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_708, 0, ret_val_get_lmul_pow_708); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_709; + auto illegal_load_709_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_709 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_709, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_709; + setArg(call_illegal_load_709, 0, reinterpret_cast(this)); + setArg(call_illegal_load_709, 1, vd); + setArg(call_illegal_load_709, 2, vm); + setArg(call_illegal_load_709, 3, 4); + setArg(call_illegal_load_709, 4, EEW); + setArg(call_illegal_load_709, 5, illegal_load_709_arg4); + setRet(call_illegal_load_709, 0, ret_val_illegal_load_709); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_710; + auto vlsseg_710_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_710_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_710_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_710_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_710_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_710 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_710, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_710, 64, false), traits::vstart); + setArg(call_vlsseg_710, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_710, 1, V); + setArg(call_vlsseg_710, 2, vlsseg_710_arg1); + setArg(call_vlsseg_710, 3, vlsseg_710_arg2); + setArg(call_vlsseg_710, 4, vlsseg_710_arg3); + setArg(call_vlsseg_710, 5, vm); + setArg(call_vlsseg_710, 6, vd); + setArg(call_vlsseg_710, 7, vlsseg_710_arg6); + setArg(call_vlsseg_710, 8, 7); + setArg(call_vlsseg_710, 9, 4); + setArg(call_vlsseg_710, 10, vlsseg_710_arg9); + setRet(call_vlsseg_710, 0, ret_val_vlsseg_710); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 282); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 283: VLSSEG5E8__V */ + continuation_e __vlsseg5e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG5E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 283); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_711; + x86::Gp ret_val_get_pow_711 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_711, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_712; + x86::Gp ret_val_get_sew_pow_712 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_712, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_713; + x86::Gp ret_val_get_lmul_pow_713 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_713, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_711, ret_val_get_sew_pow_712), ret_val_get_lmul_pow_713)), 3, true); + setArg(call_get_pow_711, 0, reinterpret_cast(this)); + setArg(call_get_pow_711, 1, EEW); + setRet(call_get_pow_711, 0, ret_val_get_pow_711); + setArg(call_get_sew_pow_712, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_712, 0, ret_val_get_sew_pow_712); + setArg(call_get_lmul_pow_713, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_713, 0, ret_val_get_lmul_pow_713); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_714; + auto illegal_load_714_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_714 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_714, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_714; + setArg(call_illegal_load_714, 0, reinterpret_cast(this)); + setArg(call_illegal_load_714, 1, vd); + setArg(call_illegal_load_714, 2, vm); + setArg(call_illegal_load_714, 3, 5); + setArg(call_illegal_load_714, 4, EEW); + setArg(call_illegal_load_714, 5, illegal_load_714_arg4); + setRet(call_illegal_load_714, 0, ret_val_illegal_load_714); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_715; + auto vlsseg_715_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_715_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_715_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_715_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_715_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_715 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_715, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_715, 64, false), traits::vstart); + setArg(call_vlsseg_715, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_715, 1, V); + setArg(call_vlsseg_715, 2, vlsseg_715_arg1); + setArg(call_vlsseg_715, 3, vlsseg_715_arg2); + setArg(call_vlsseg_715, 4, vlsseg_715_arg3); + setArg(call_vlsseg_715, 5, vm); + setArg(call_vlsseg_715, 6, vd); + setArg(call_vlsseg_715, 7, vlsseg_715_arg6); + setArg(call_vlsseg_715, 8, 0); + setArg(call_vlsseg_715, 9, 5); + setArg(call_vlsseg_715, 10, vlsseg_715_arg9); + setRet(call_vlsseg_715, 0, ret_val_vlsseg_715); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 283); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 284: VLSSEG5E16__V */ + continuation_e __vlsseg5e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG5E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 284); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_716; + x86::Gp ret_val_get_pow_716 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_716, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_717; + x86::Gp ret_val_get_sew_pow_717 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_717, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_718; + x86::Gp ret_val_get_lmul_pow_718 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_718, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_716, ret_val_get_sew_pow_717), ret_val_get_lmul_pow_718)), 3, true); + setArg(call_get_pow_716, 0, reinterpret_cast(this)); + setArg(call_get_pow_716, 1, EEW); + setRet(call_get_pow_716, 0, ret_val_get_pow_716); + setArg(call_get_sew_pow_717, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_717, 0, ret_val_get_sew_pow_717); + setArg(call_get_lmul_pow_718, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_718, 0, ret_val_get_lmul_pow_718); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_719; + auto illegal_load_719_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_719 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_719, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_719; + setArg(call_illegal_load_719, 0, reinterpret_cast(this)); + setArg(call_illegal_load_719, 1, vd); + setArg(call_illegal_load_719, 2, vm); + setArg(call_illegal_load_719, 3, 5); + setArg(call_illegal_load_719, 4, EEW); + setArg(call_illegal_load_719, 5, illegal_load_719_arg4); + setRet(call_illegal_load_719, 0, ret_val_illegal_load_719); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_720; + auto vlsseg_720_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_720_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_720_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_720_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_720_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_720 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_720, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_720, 64, false), traits::vstart); + setArg(call_vlsseg_720, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_720, 1, V); + setArg(call_vlsseg_720, 2, vlsseg_720_arg1); + setArg(call_vlsseg_720, 3, vlsseg_720_arg2); + setArg(call_vlsseg_720, 4, vlsseg_720_arg3); + setArg(call_vlsseg_720, 5, vm); + setArg(call_vlsseg_720, 6, vd); + setArg(call_vlsseg_720, 7, vlsseg_720_arg6); + setArg(call_vlsseg_720, 8, 5); + setArg(call_vlsseg_720, 9, 5); + setArg(call_vlsseg_720, 10, vlsseg_720_arg9); + setRet(call_vlsseg_720, 0, ret_val_vlsseg_720); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 284); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 285: VLSSEG5E32__V */ + continuation_e __vlsseg5e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG5E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 285); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_721; + x86::Gp ret_val_get_pow_721 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_721, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_722; + x86::Gp ret_val_get_sew_pow_722 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_722, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_723; + x86::Gp ret_val_get_lmul_pow_723 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_723, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_721, ret_val_get_sew_pow_722), ret_val_get_lmul_pow_723)), 3, true); + setArg(call_get_pow_721, 0, reinterpret_cast(this)); + setArg(call_get_pow_721, 1, EEW); + setRet(call_get_pow_721, 0, ret_val_get_pow_721); + setArg(call_get_sew_pow_722, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_722, 0, ret_val_get_sew_pow_722); + setArg(call_get_lmul_pow_723, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_723, 0, ret_val_get_lmul_pow_723); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_724; + auto illegal_load_724_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_724 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_724, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_724; + setArg(call_illegal_load_724, 0, reinterpret_cast(this)); + setArg(call_illegal_load_724, 1, vd); + setArg(call_illegal_load_724, 2, vm); + setArg(call_illegal_load_724, 3, 5); + setArg(call_illegal_load_724, 4, EEW); + setArg(call_illegal_load_724, 5, illegal_load_724_arg4); + setRet(call_illegal_load_724, 0, ret_val_illegal_load_724); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_725; + auto vlsseg_725_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_725_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_725_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_725_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_725_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_725 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_725, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_725, 64, false), traits::vstart); + setArg(call_vlsseg_725, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_725, 1, V); + setArg(call_vlsseg_725, 2, vlsseg_725_arg1); + setArg(call_vlsseg_725, 3, vlsseg_725_arg2); + setArg(call_vlsseg_725, 4, vlsseg_725_arg3); + setArg(call_vlsseg_725, 5, vm); + setArg(call_vlsseg_725, 6, vd); + setArg(call_vlsseg_725, 7, vlsseg_725_arg6); + setArg(call_vlsseg_725, 8, 6); + setArg(call_vlsseg_725, 9, 5); + setArg(call_vlsseg_725, 10, vlsseg_725_arg9); + setRet(call_vlsseg_725, 0, ret_val_vlsseg_725); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 285); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 286: VLSSEG5E64__V */ + continuation_e __vlsseg5e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg5e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG5E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 286); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_726; + x86::Gp ret_val_get_pow_726 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_726, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_727; + x86::Gp ret_val_get_sew_pow_727 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_727, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_728; + x86::Gp ret_val_get_lmul_pow_728 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_728, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_726, ret_val_get_sew_pow_727), ret_val_get_lmul_pow_728)), 3, true); + setArg(call_get_pow_726, 0, reinterpret_cast(this)); + setArg(call_get_pow_726, 1, EEW); + setRet(call_get_pow_726, 0, ret_val_get_pow_726); + setArg(call_get_sew_pow_727, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_727, 0, ret_val_get_sew_pow_727); + setArg(call_get_lmul_pow_728, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_728, 0, ret_val_get_lmul_pow_728); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_729; + auto illegal_load_729_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_729 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_729, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_729; + setArg(call_illegal_load_729, 0, reinterpret_cast(this)); + setArg(call_illegal_load_729, 1, vd); + setArg(call_illegal_load_729, 2, vm); + setArg(call_illegal_load_729, 3, 5); + setArg(call_illegal_load_729, 4, EEW); + setArg(call_illegal_load_729, 5, illegal_load_729_arg4); + setRet(call_illegal_load_729, 0, ret_val_illegal_load_729); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_730; + auto vlsseg_730_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_730_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_730_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_730_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_730_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_730 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_730, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_730, 64, false), traits::vstart); + setArg(call_vlsseg_730, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_730, 1, V); + setArg(call_vlsseg_730, 2, vlsseg_730_arg1); + setArg(call_vlsseg_730, 3, vlsseg_730_arg2); + setArg(call_vlsseg_730, 4, vlsseg_730_arg3); + setArg(call_vlsseg_730, 5, vm); + setArg(call_vlsseg_730, 6, vd); + setArg(call_vlsseg_730, 7, vlsseg_730_arg6); + setArg(call_vlsseg_730, 8, 7); + setArg(call_vlsseg_730, 9, 5); + setArg(call_vlsseg_730, 10, vlsseg_730_arg9); + setRet(call_vlsseg_730, 0, ret_val_vlsseg_730); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 286); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 287: VLSSEG6E8__V */ + continuation_e __vlsseg6e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG6E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 287); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_731; + x86::Gp ret_val_get_pow_731 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_731, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_732; + x86::Gp ret_val_get_sew_pow_732 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_732, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_733; + x86::Gp ret_val_get_lmul_pow_733 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_733, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_731, ret_val_get_sew_pow_732), ret_val_get_lmul_pow_733)), 3, true); + setArg(call_get_pow_731, 0, reinterpret_cast(this)); + setArg(call_get_pow_731, 1, EEW); + setRet(call_get_pow_731, 0, ret_val_get_pow_731); + setArg(call_get_sew_pow_732, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_732, 0, ret_val_get_sew_pow_732); + setArg(call_get_lmul_pow_733, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_733, 0, ret_val_get_lmul_pow_733); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_734; + auto illegal_load_734_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_734 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_734, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_734; + setArg(call_illegal_load_734, 0, reinterpret_cast(this)); + setArg(call_illegal_load_734, 1, vd); + setArg(call_illegal_load_734, 2, vm); + setArg(call_illegal_load_734, 3, 6); + setArg(call_illegal_load_734, 4, EEW); + setArg(call_illegal_load_734, 5, illegal_load_734_arg4); + setRet(call_illegal_load_734, 0, ret_val_illegal_load_734); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_735; + auto vlsseg_735_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_735_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_735_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_735_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_735_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_735 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_735, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_735, 64, false), traits::vstart); + setArg(call_vlsseg_735, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_735, 1, V); + setArg(call_vlsseg_735, 2, vlsseg_735_arg1); + setArg(call_vlsseg_735, 3, vlsseg_735_arg2); + setArg(call_vlsseg_735, 4, vlsseg_735_arg3); + setArg(call_vlsseg_735, 5, vm); + setArg(call_vlsseg_735, 6, vd); + setArg(call_vlsseg_735, 7, vlsseg_735_arg6); + setArg(call_vlsseg_735, 8, 0); + setArg(call_vlsseg_735, 9, 6); + setArg(call_vlsseg_735, 10, vlsseg_735_arg9); + setRet(call_vlsseg_735, 0, ret_val_vlsseg_735); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 287); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 288: VLSSEG6E16__V */ + continuation_e __vlsseg6e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG6E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 288); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_736; + x86::Gp ret_val_get_pow_736 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_736, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_737; + x86::Gp ret_val_get_sew_pow_737 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_737, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_738; + x86::Gp ret_val_get_lmul_pow_738 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_738, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_736, ret_val_get_sew_pow_737), ret_val_get_lmul_pow_738)), 3, true); + setArg(call_get_pow_736, 0, reinterpret_cast(this)); + setArg(call_get_pow_736, 1, EEW); + setRet(call_get_pow_736, 0, ret_val_get_pow_736); + setArg(call_get_sew_pow_737, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_737, 0, ret_val_get_sew_pow_737); + setArg(call_get_lmul_pow_738, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_738, 0, ret_val_get_lmul_pow_738); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_739; + auto illegal_load_739_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_739 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_739, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_739; + setArg(call_illegal_load_739, 0, reinterpret_cast(this)); + setArg(call_illegal_load_739, 1, vd); + setArg(call_illegal_load_739, 2, vm); + setArg(call_illegal_load_739, 3, 6); + setArg(call_illegal_load_739, 4, EEW); + setArg(call_illegal_load_739, 5, illegal_load_739_arg4); + setRet(call_illegal_load_739, 0, ret_val_illegal_load_739); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_740; + auto vlsseg_740_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_740_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_740_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_740_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_740_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_740 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_740, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_740, 64, false), traits::vstart); + setArg(call_vlsseg_740, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_740, 1, V); + setArg(call_vlsseg_740, 2, vlsseg_740_arg1); + setArg(call_vlsseg_740, 3, vlsseg_740_arg2); + setArg(call_vlsseg_740, 4, vlsseg_740_arg3); + setArg(call_vlsseg_740, 5, vm); + setArg(call_vlsseg_740, 6, vd); + setArg(call_vlsseg_740, 7, vlsseg_740_arg6); + setArg(call_vlsseg_740, 8, 5); + setArg(call_vlsseg_740, 9, 6); + setArg(call_vlsseg_740, 10, vlsseg_740_arg9); + setRet(call_vlsseg_740, 0, ret_val_vlsseg_740); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 288); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 289: VLSSEG6E32__V */ + continuation_e __vlsseg6e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG6E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 289); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_741; + x86::Gp ret_val_get_pow_741 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_741, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_742; + x86::Gp ret_val_get_sew_pow_742 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_742, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_743; + x86::Gp ret_val_get_lmul_pow_743 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_743, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_741, ret_val_get_sew_pow_742), ret_val_get_lmul_pow_743)), 3, true); + setArg(call_get_pow_741, 0, reinterpret_cast(this)); + setArg(call_get_pow_741, 1, EEW); + setRet(call_get_pow_741, 0, ret_val_get_pow_741); + setArg(call_get_sew_pow_742, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_742, 0, ret_val_get_sew_pow_742); + setArg(call_get_lmul_pow_743, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_743, 0, ret_val_get_lmul_pow_743); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_744; + auto illegal_load_744_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_744 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_744, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_744; + setArg(call_illegal_load_744, 0, reinterpret_cast(this)); + setArg(call_illegal_load_744, 1, vd); + setArg(call_illegal_load_744, 2, vm); + setArg(call_illegal_load_744, 3, 6); + setArg(call_illegal_load_744, 4, EEW); + setArg(call_illegal_load_744, 5, illegal_load_744_arg4); + setRet(call_illegal_load_744, 0, ret_val_illegal_load_744); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_745; + auto vlsseg_745_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_745_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_745_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_745_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_745_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_745 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_745, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_745, 64, false), traits::vstart); + setArg(call_vlsseg_745, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_745, 1, V); + setArg(call_vlsseg_745, 2, vlsseg_745_arg1); + setArg(call_vlsseg_745, 3, vlsseg_745_arg2); + setArg(call_vlsseg_745, 4, vlsseg_745_arg3); + setArg(call_vlsseg_745, 5, vm); + setArg(call_vlsseg_745, 6, vd); + setArg(call_vlsseg_745, 7, vlsseg_745_arg6); + setArg(call_vlsseg_745, 8, 6); + setArg(call_vlsseg_745, 9, 6); + setArg(call_vlsseg_745, 10, vlsseg_745_arg9); + setRet(call_vlsseg_745, 0, ret_val_vlsseg_745); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 289); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 290: VLSSEG6E64__V */ + continuation_e __vlsseg6e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg6e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG6E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 290); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_746; + x86::Gp ret_val_get_pow_746 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_746, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_747; + x86::Gp ret_val_get_sew_pow_747 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_747, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_748; + x86::Gp ret_val_get_lmul_pow_748 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_748, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_746, ret_val_get_sew_pow_747), ret_val_get_lmul_pow_748)), 3, true); + setArg(call_get_pow_746, 0, reinterpret_cast(this)); + setArg(call_get_pow_746, 1, EEW); + setRet(call_get_pow_746, 0, ret_val_get_pow_746); + setArg(call_get_sew_pow_747, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_747, 0, ret_val_get_sew_pow_747); + setArg(call_get_lmul_pow_748, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_748, 0, ret_val_get_lmul_pow_748); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_749; + auto illegal_load_749_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_749 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_749, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_749; + setArg(call_illegal_load_749, 0, reinterpret_cast(this)); + setArg(call_illegal_load_749, 1, vd); + setArg(call_illegal_load_749, 2, vm); + setArg(call_illegal_load_749, 3, 6); + setArg(call_illegal_load_749, 4, EEW); + setArg(call_illegal_load_749, 5, illegal_load_749_arg4); + setRet(call_illegal_load_749, 0, ret_val_illegal_load_749); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_750; + auto vlsseg_750_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_750_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_750_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_750_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_750_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_750 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_750, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_750, 64, false), traits::vstart); + setArg(call_vlsseg_750, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_750, 1, V); + setArg(call_vlsseg_750, 2, vlsseg_750_arg1); + setArg(call_vlsseg_750, 3, vlsseg_750_arg2); + setArg(call_vlsseg_750, 4, vlsseg_750_arg3); + setArg(call_vlsseg_750, 5, vm); + setArg(call_vlsseg_750, 6, vd); + setArg(call_vlsseg_750, 7, vlsseg_750_arg6); + setArg(call_vlsseg_750, 8, 7); + setArg(call_vlsseg_750, 9, 6); + setArg(call_vlsseg_750, 10, vlsseg_750_arg9); + setRet(call_vlsseg_750, 0, ret_val_vlsseg_750); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 290); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 291: VLSSEG7E8__V */ + continuation_e __vlsseg7e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG7E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 291); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_751; + x86::Gp ret_val_get_pow_751 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_751, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_752; + x86::Gp ret_val_get_sew_pow_752 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_752, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_753; + x86::Gp ret_val_get_lmul_pow_753 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_753, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_751, ret_val_get_sew_pow_752), ret_val_get_lmul_pow_753)), 3, true); + setArg(call_get_pow_751, 0, reinterpret_cast(this)); + setArg(call_get_pow_751, 1, EEW); + setRet(call_get_pow_751, 0, ret_val_get_pow_751); + setArg(call_get_sew_pow_752, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_752, 0, ret_val_get_sew_pow_752); + setArg(call_get_lmul_pow_753, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_753, 0, ret_val_get_lmul_pow_753); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_754; + auto illegal_load_754_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_754 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_754, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_754; + setArg(call_illegal_load_754, 0, reinterpret_cast(this)); + setArg(call_illegal_load_754, 1, vd); + setArg(call_illegal_load_754, 2, vm); + setArg(call_illegal_load_754, 3, 7); + setArg(call_illegal_load_754, 4, EEW); + setArg(call_illegal_load_754, 5, illegal_load_754_arg4); + setRet(call_illegal_load_754, 0, ret_val_illegal_load_754); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_755; + auto vlsseg_755_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_755_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_755_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_755_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_755_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_755 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_755, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_755, 64, false), traits::vstart); + setArg(call_vlsseg_755, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_755, 1, V); + setArg(call_vlsseg_755, 2, vlsseg_755_arg1); + setArg(call_vlsseg_755, 3, vlsseg_755_arg2); + setArg(call_vlsseg_755, 4, vlsseg_755_arg3); + setArg(call_vlsseg_755, 5, vm); + setArg(call_vlsseg_755, 6, vd); + setArg(call_vlsseg_755, 7, vlsseg_755_arg6); + setArg(call_vlsseg_755, 8, 0); + setArg(call_vlsseg_755, 9, 7); + setArg(call_vlsseg_755, 10, vlsseg_755_arg9); + setRet(call_vlsseg_755, 0, ret_val_vlsseg_755); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 291); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 292: VLSSEG7E16__V */ + continuation_e __vlsseg7e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG7E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 292); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_756; + x86::Gp ret_val_get_pow_756 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_756, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_757; + x86::Gp ret_val_get_sew_pow_757 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_757, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_758; + x86::Gp ret_val_get_lmul_pow_758 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_758, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_756, ret_val_get_sew_pow_757), ret_val_get_lmul_pow_758)), 3, true); + setArg(call_get_pow_756, 0, reinterpret_cast(this)); + setArg(call_get_pow_756, 1, EEW); + setRet(call_get_pow_756, 0, ret_val_get_pow_756); + setArg(call_get_sew_pow_757, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_757, 0, ret_val_get_sew_pow_757); + setArg(call_get_lmul_pow_758, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_758, 0, ret_val_get_lmul_pow_758); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_759; + auto illegal_load_759_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_759 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_759, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_759; + setArg(call_illegal_load_759, 0, reinterpret_cast(this)); + setArg(call_illegal_load_759, 1, vd); + setArg(call_illegal_load_759, 2, vm); + setArg(call_illegal_load_759, 3, 7); + setArg(call_illegal_load_759, 4, EEW); + setArg(call_illegal_load_759, 5, illegal_load_759_arg4); + setRet(call_illegal_load_759, 0, ret_val_illegal_load_759); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_760; + auto vlsseg_760_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_760_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_760_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_760_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_760_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_760 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_760, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_760, 64, false), traits::vstart); + setArg(call_vlsseg_760, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_760, 1, V); + setArg(call_vlsseg_760, 2, vlsseg_760_arg1); + setArg(call_vlsseg_760, 3, vlsseg_760_arg2); + setArg(call_vlsseg_760, 4, vlsseg_760_arg3); + setArg(call_vlsseg_760, 5, vm); + setArg(call_vlsseg_760, 6, vd); + setArg(call_vlsseg_760, 7, vlsseg_760_arg6); + setArg(call_vlsseg_760, 8, 5); + setArg(call_vlsseg_760, 9, 7); + setArg(call_vlsseg_760, 10, vlsseg_760_arg9); + setRet(call_vlsseg_760, 0, ret_val_vlsseg_760); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 292); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 293: VLSSEG7E32__V */ + continuation_e __vlsseg7e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG7E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 293); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_761; + x86::Gp ret_val_get_pow_761 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_761, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_762; + x86::Gp ret_val_get_sew_pow_762 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_762, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_763; + x86::Gp ret_val_get_lmul_pow_763 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_763, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_761, ret_val_get_sew_pow_762), ret_val_get_lmul_pow_763)), 3, true); + setArg(call_get_pow_761, 0, reinterpret_cast(this)); + setArg(call_get_pow_761, 1, EEW); + setRet(call_get_pow_761, 0, ret_val_get_pow_761); + setArg(call_get_sew_pow_762, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_762, 0, ret_val_get_sew_pow_762); + setArg(call_get_lmul_pow_763, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_763, 0, ret_val_get_lmul_pow_763); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_764; + auto illegal_load_764_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_764 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_764, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_764; + setArg(call_illegal_load_764, 0, reinterpret_cast(this)); + setArg(call_illegal_load_764, 1, vd); + setArg(call_illegal_load_764, 2, vm); + setArg(call_illegal_load_764, 3, 7); + setArg(call_illegal_load_764, 4, EEW); + setArg(call_illegal_load_764, 5, illegal_load_764_arg4); + setRet(call_illegal_load_764, 0, ret_val_illegal_load_764); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_765; + auto vlsseg_765_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_765_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_765_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_765_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_765_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_765 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_765, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_765, 64, false), traits::vstart); + setArg(call_vlsseg_765, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_765, 1, V); + setArg(call_vlsseg_765, 2, vlsseg_765_arg1); + setArg(call_vlsseg_765, 3, vlsseg_765_arg2); + setArg(call_vlsseg_765, 4, vlsseg_765_arg3); + setArg(call_vlsseg_765, 5, vm); + setArg(call_vlsseg_765, 6, vd); + setArg(call_vlsseg_765, 7, vlsseg_765_arg6); + setArg(call_vlsseg_765, 8, 6); + setArg(call_vlsseg_765, 9, 7); + setArg(call_vlsseg_765, 10, vlsseg_765_arg9); + setRet(call_vlsseg_765, 0, ret_val_vlsseg_765); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 293); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 294: VLSSEG7E64__V */ + continuation_e __vlsseg7e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg7e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG7E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 294); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_766; + x86::Gp ret_val_get_pow_766 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_766, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_767; + x86::Gp ret_val_get_sew_pow_767 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_767, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_768; + x86::Gp ret_val_get_lmul_pow_768 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_768, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_766, ret_val_get_sew_pow_767), ret_val_get_lmul_pow_768)), 3, true); + setArg(call_get_pow_766, 0, reinterpret_cast(this)); + setArg(call_get_pow_766, 1, EEW); + setRet(call_get_pow_766, 0, ret_val_get_pow_766); + setArg(call_get_sew_pow_767, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_767, 0, ret_val_get_sew_pow_767); + setArg(call_get_lmul_pow_768, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_768, 0, ret_val_get_lmul_pow_768); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_769; + auto illegal_load_769_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_769 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_769, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_769; + setArg(call_illegal_load_769, 0, reinterpret_cast(this)); + setArg(call_illegal_load_769, 1, vd); + setArg(call_illegal_load_769, 2, vm); + setArg(call_illegal_load_769, 3, 7); + setArg(call_illegal_load_769, 4, EEW); + setArg(call_illegal_load_769, 5, illegal_load_769_arg4); + setRet(call_illegal_load_769, 0, ret_val_illegal_load_769); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_770; + auto vlsseg_770_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_770_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_770_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_770_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_770_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_770 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_770, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_770, 64, false), traits::vstart); + setArg(call_vlsseg_770, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_770, 1, V); + setArg(call_vlsseg_770, 2, vlsseg_770_arg1); + setArg(call_vlsseg_770, 3, vlsseg_770_arg2); + setArg(call_vlsseg_770, 4, vlsseg_770_arg3); + setArg(call_vlsseg_770, 5, vm); + setArg(call_vlsseg_770, 6, vd); + setArg(call_vlsseg_770, 7, vlsseg_770_arg6); + setArg(call_vlsseg_770, 8, 7); + setArg(call_vlsseg_770, 9, 7); + setArg(call_vlsseg_770, 10, vlsseg_770_arg9); + setRet(call_vlsseg_770, 0, ret_val_vlsseg_770); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 294); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 295: VLSSEG8E8__V */ + continuation_e __vlsseg8e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG8E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 295); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_771; + x86::Gp ret_val_get_pow_771 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_771, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_772; + x86::Gp ret_val_get_sew_pow_772 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_772, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_773; + x86::Gp ret_val_get_lmul_pow_773 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_773, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_771, ret_val_get_sew_pow_772), ret_val_get_lmul_pow_773)), 3, true); + setArg(call_get_pow_771, 0, reinterpret_cast(this)); + setArg(call_get_pow_771, 1, EEW); + setRet(call_get_pow_771, 0, ret_val_get_pow_771); + setArg(call_get_sew_pow_772, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_772, 0, ret_val_get_sew_pow_772); + setArg(call_get_lmul_pow_773, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_773, 0, ret_val_get_lmul_pow_773); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_774; + auto illegal_load_774_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_774 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_774, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_774; + setArg(call_illegal_load_774, 0, reinterpret_cast(this)); + setArg(call_illegal_load_774, 1, vd); + setArg(call_illegal_load_774, 2, vm); + setArg(call_illegal_load_774, 3, 8); + setArg(call_illegal_load_774, 4, EEW); + setArg(call_illegal_load_774, 5, illegal_load_774_arg4); + setRet(call_illegal_load_774, 0, ret_val_illegal_load_774); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_775; + auto vlsseg_775_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_775_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_775_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_775_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_775_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_775 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_775, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_775, 64, false), traits::vstart); + setArg(call_vlsseg_775, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_775, 1, V); + setArg(call_vlsseg_775, 2, vlsseg_775_arg1); + setArg(call_vlsseg_775, 3, vlsseg_775_arg2); + setArg(call_vlsseg_775, 4, vlsseg_775_arg3); + setArg(call_vlsseg_775, 5, vm); + setArg(call_vlsseg_775, 6, vd); + setArg(call_vlsseg_775, 7, vlsseg_775_arg6); + setArg(call_vlsseg_775, 8, 0); + setArg(call_vlsseg_775, 9, 8); + setArg(call_vlsseg_775, 10, vlsseg_775_arg9); + setRet(call_vlsseg_775, 0, ret_val_vlsseg_775); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 295); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 296: VLSSEG8E16__V */ + continuation_e __vlsseg8e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG8E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 296); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_776; + x86::Gp ret_val_get_pow_776 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_776, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_777; + x86::Gp ret_val_get_sew_pow_777 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_777, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_778; + x86::Gp ret_val_get_lmul_pow_778 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_778, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_776, ret_val_get_sew_pow_777), ret_val_get_lmul_pow_778)), 3, true); + setArg(call_get_pow_776, 0, reinterpret_cast(this)); + setArg(call_get_pow_776, 1, EEW); + setRet(call_get_pow_776, 0, ret_val_get_pow_776); + setArg(call_get_sew_pow_777, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_777, 0, ret_val_get_sew_pow_777); + setArg(call_get_lmul_pow_778, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_778, 0, ret_val_get_lmul_pow_778); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_779; + auto illegal_load_779_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_779 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_779, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_779; + setArg(call_illegal_load_779, 0, reinterpret_cast(this)); + setArg(call_illegal_load_779, 1, vd); + setArg(call_illegal_load_779, 2, vm); + setArg(call_illegal_load_779, 3, 8); + setArg(call_illegal_load_779, 4, EEW); + setArg(call_illegal_load_779, 5, illegal_load_779_arg4); + setRet(call_illegal_load_779, 0, ret_val_illegal_load_779); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_780; + auto vlsseg_780_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_780_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_780_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_780_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_780_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_780 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_780, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_780, 64, false), traits::vstart); + setArg(call_vlsseg_780, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_780, 1, V); + setArg(call_vlsseg_780, 2, vlsseg_780_arg1); + setArg(call_vlsseg_780, 3, vlsseg_780_arg2); + setArg(call_vlsseg_780, 4, vlsseg_780_arg3); + setArg(call_vlsseg_780, 5, vm); + setArg(call_vlsseg_780, 6, vd); + setArg(call_vlsseg_780, 7, vlsseg_780_arg6); + setArg(call_vlsseg_780, 8, 5); + setArg(call_vlsseg_780, 9, 8); + setArg(call_vlsseg_780, 10, vlsseg_780_arg9); + setRet(call_vlsseg_780, 0, ret_val_vlsseg_780); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 296); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 297: VLSSEG8E32__V */ + continuation_e __vlsseg8e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG8E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 297); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_781; + x86::Gp ret_val_get_pow_781 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_781, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_782; + x86::Gp ret_val_get_sew_pow_782 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_782, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_783; + x86::Gp ret_val_get_lmul_pow_783 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_783, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_781, ret_val_get_sew_pow_782), ret_val_get_lmul_pow_783)), 3, true); + setArg(call_get_pow_781, 0, reinterpret_cast(this)); + setArg(call_get_pow_781, 1, EEW); + setRet(call_get_pow_781, 0, ret_val_get_pow_781); + setArg(call_get_sew_pow_782, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_782, 0, ret_val_get_sew_pow_782); + setArg(call_get_lmul_pow_783, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_783, 0, ret_val_get_lmul_pow_783); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_784; + auto illegal_load_784_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_784 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_784, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_784; + setArg(call_illegal_load_784, 0, reinterpret_cast(this)); + setArg(call_illegal_load_784, 1, vd); + setArg(call_illegal_load_784, 2, vm); + setArg(call_illegal_load_784, 3, 8); + setArg(call_illegal_load_784, 4, EEW); + setArg(call_illegal_load_784, 5, illegal_load_784_arg4); + setRet(call_illegal_load_784, 0, ret_val_illegal_load_784); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_785; + auto vlsseg_785_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_785_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_785_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_785_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_785_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_785 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_785, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_785, 64, false), traits::vstart); + setArg(call_vlsseg_785, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_785, 1, V); + setArg(call_vlsseg_785, 2, vlsseg_785_arg1); + setArg(call_vlsseg_785, 3, vlsseg_785_arg2); + setArg(call_vlsseg_785, 4, vlsseg_785_arg3); + setArg(call_vlsseg_785, 5, vm); + setArg(call_vlsseg_785, 6, vd); + setArg(call_vlsseg_785, 7, vlsseg_785_arg6); + setArg(call_vlsseg_785, 8, 6); + setArg(call_vlsseg_785, 9, 8); + setArg(call_vlsseg_785, 10, vlsseg_785_arg9); + setRet(call_vlsseg_785, 0, ret_val_vlsseg_785); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 297); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 298: VLSSEG8E64__V */ + continuation_e __vlsseg8e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vm}", fmt::arg("mnemonic", "vlsseg8e64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSSEG8E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 298); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_786; + x86::Gp ret_val_get_pow_786 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_786, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_787; + x86::Gp ret_val_get_sew_pow_787 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_787, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_788; + x86::Gp ret_val_get_lmul_pow_788 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_788, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_786, ret_val_get_sew_pow_787), ret_val_get_lmul_pow_788)), 3, true); + setArg(call_get_pow_786, 0, reinterpret_cast(this)); + setArg(call_get_pow_786, 1, EEW); + setRet(call_get_pow_786, 0, ret_val_get_pow_786); + setArg(call_get_sew_pow_787, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_787, 0, ret_val_get_sew_pow_787); + setArg(call_get_lmul_pow_788, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_788, 0, ret_val_get_lmul_pow_788); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_789; + auto illegal_load_789_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_789 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_789, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_789; + setArg(call_illegal_load_789, 0, reinterpret_cast(this)); + setArg(call_illegal_load_789, 1, vd); + setArg(call_illegal_load_789, 2, vm); + setArg(call_illegal_load_789, 3, 8); + setArg(call_illegal_load_789, 4, EEW); + setArg(call_illegal_load_789, 5, illegal_load_789_arg4); + setRet(call_illegal_load_789, 0, ret_val_illegal_load_789); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlsseg_790; + auto vlsseg_790_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlsseg_790_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlsseg_790_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlsseg_790_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlsseg_790_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlsseg_790 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlsseg_790, &vlsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlsseg_790, 64, false), traits::vstart); + setArg(call_vlsseg_790, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlsseg_790, 1, V); + setArg(call_vlsseg_790, 2, vlsseg_790_arg1); + setArg(call_vlsseg_790, 3, vlsseg_790_arg2); + setArg(call_vlsseg_790, 4, vlsseg_790_arg3); + setArg(call_vlsseg_790, 5, vm); + setArg(call_vlsseg_790, 6, vd); + setArg(call_vlsseg_790, 7, vlsseg_790_arg6); + setArg(call_vlsseg_790, 8, 7); + setArg(call_vlsseg_790, 9, 8); + setArg(call_vlsseg_790, 10, vlsseg_790_arg9); + setRet(call_vlsseg_790, 0, ret_val_vlsseg_790); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 298); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 299: VSSE8__V */ + continuation_e __vsse8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 299); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_791; + x86::Gp ret_val_get_pow_791 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_791, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_792; + x86::Gp ret_val_get_sew_pow_792 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_792, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_793; + x86::Gp ret_val_get_lmul_pow_793 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_793, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_791, ret_val_get_sew_pow_792), ret_val_get_lmul_pow_793)), 3, true); + setArg(call_get_pow_791, 0, reinterpret_cast(this)); + setArg(call_get_pow_791, 1, EEW); + setRet(call_get_pow_791, 0, ret_val_get_pow_791); + setArg(call_get_sew_pow_792, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_792, 0, ret_val_get_sew_pow_792); + setArg(call_get_lmul_pow_793, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_793, 0, ret_val_get_lmul_pow_793); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_794; + auto illegal_store_794_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_794 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_794, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_794; + setArg(call_illegal_store_794, 0, reinterpret_cast(this)); + setArg(call_illegal_store_794, 1, 1); + setArg(call_illegal_store_794, 2, EEW); + setArg(call_illegal_store_794, 3, illegal_store_794_arg2); + setRet(call_illegal_store_794, 0, ret_val_illegal_store_794); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_795; + auto vssseg_795_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_795_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_795_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_795_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_795_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_795 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_795, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_795, 64, false), traits::vstart); + setArg(call_vssseg_795, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_795, 1, V); + setArg(call_vssseg_795, 2, vssseg_795_arg1); + setArg(call_vssseg_795, 3, vssseg_795_arg2); + setArg(call_vssseg_795, 4, vssseg_795_arg3); + setArg(call_vssseg_795, 5, vm); + setArg(call_vssseg_795, 6, vs3); + setArg(call_vssseg_795, 7, vssseg_795_arg6); + setArg(call_vssseg_795, 8, 0); + setArg(call_vssseg_795, 9, 1); + setArg(call_vssseg_795, 10, vssseg_795_arg9); + setRet(call_vssseg_795, 0, ret_val_vssseg_795); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 299); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 300: VSSE16__V */ + continuation_e __vsse16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 300); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_796; + x86::Gp ret_val_get_pow_796 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_796, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_797; + x86::Gp ret_val_get_sew_pow_797 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_797, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_798; + x86::Gp ret_val_get_lmul_pow_798 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_798, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_796, ret_val_get_sew_pow_797), ret_val_get_lmul_pow_798)), 3, true); + setArg(call_get_pow_796, 0, reinterpret_cast(this)); + setArg(call_get_pow_796, 1, EEW); + setRet(call_get_pow_796, 0, ret_val_get_pow_796); + setArg(call_get_sew_pow_797, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_797, 0, ret_val_get_sew_pow_797); + setArg(call_get_lmul_pow_798, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_798, 0, ret_val_get_lmul_pow_798); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_799; + auto illegal_store_799_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_799 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_799, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_799; + setArg(call_illegal_store_799, 0, reinterpret_cast(this)); + setArg(call_illegal_store_799, 1, 1); + setArg(call_illegal_store_799, 2, EEW); + setArg(call_illegal_store_799, 3, illegal_store_799_arg2); + setRet(call_illegal_store_799, 0, ret_val_illegal_store_799); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_800; + auto vssseg_800_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_800_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_800_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_800_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_800_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_800 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_800, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_800, 64, false), traits::vstart); + setArg(call_vssseg_800, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_800, 1, V); + setArg(call_vssseg_800, 2, vssseg_800_arg1); + setArg(call_vssseg_800, 3, vssseg_800_arg2); + setArg(call_vssseg_800, 4, vssseg_800_arg3); + setArg(call_vssseg_800, 5, vm); + setArg(call_vssseg_800, 6, vs3); + setArg(call_vssseg_800, 7, vssseg_800_arg6); + setArg(call_vssseg_800, 8, 5); + setArg(call_vssseg_800, 9, 1); + setArg(call_vssseg_800, 10, vssseg_800_arg9); + setRet(call_vssseg_800, 0, ret_val_vssseg_800); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 300); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 301: VSSE32__V */ + continuation_e __vsse32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 301); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_801; + x86::Gp ret_val_get_pow_801 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_801, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_802; + x86::Gp ret_val_get_sew_pow_802 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_802, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_803; + x86::Gp ret_val_get_lmul_pow_803 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_803, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_801, ret_val_get_sew_pow_802), ret_val_get_lmul_pow_803)), 3, true); + setArg(call_get_pow_801, 0, reinterpret_cast(this)); + setArg(call_get_pow_801, 1, EEW); + setRet(call_get_pow_801, 0, ret_val_get_pow_801); + setArg(call_get_sew_pow_802, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_802, 0, ret_val_get_sew_pow_802); + setArg(call_get_lmul_pow_803, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_803, 0, ret_val_get_lmul_pow_803); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_804; + auto illegal_store_804_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_804 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_804, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_804; + setArg(call_illegal_store_804, 0, reinterpret_cast(this)); + setArg(call_illegal_store_804, 1, 1); + setArg(call_illegal_store_804, 2, EEW); + setArg(call_illegal_store_804, 3, illegal_store_804_arg2); + setRet(call_illegal_store_804, 0, ret_val_illegal_store_804); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_805; + auto vssseg_805_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_805_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_805_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_805_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_805_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_805 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_805, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_805, 64, false), traits::vstart); + setArg(call_vssseg_805, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_805, 1, V); + setArg(call_vssseg_805, 2, vssseg_805_arg1); + setArg(call_vssseg_805, 3, vssseg_805_arg2); + setArg(call_vssseg_805, 4, vssseg_805_arg3); + setArg(call_vssseg_805, 5, vm); + setArg(call_vssseg_805, 6, vs3); + setArg(call_vssseg_805, 7, vssseg_805_arg6); + setArg(call_vssseg_805, 8, 6); + setArg(call_vssseg_805, 9, 1); + setArg(call_vssseg_805, 10, vssseg_805_arg9); + setRet(call_vssseg_805, 0, ret_val_vssseg_805); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 301); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 302: VSSE64__V */ + continuation_e __vsse64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vsse64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 302); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_806; + x86::Gp ret_val_get_pow_806 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_806, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_807; + x86::Gp ret_val_get_sew_pow_807 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_807, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_808; + x86::Gp ret_val_get_lmul_pow_808 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_808, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_806, ret_val_get_sew_pow_807), ret_val_get_lmul_pow_808)), 3, true); + setArg(call_get_pow_806, 0, reinterpret_cast(this)); + setArg(call_get_pow_806, 1, EEW); + setRet(call_get_pow_806, 0, ret_val_get_pow_806); + setArg(call_get_sew_pow_807, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_807, 0, ret_val_get_sew_pow_807); + setArg(call_get_lmul_pow_808, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_808, 0, ret_val_get_lmul_pow_808); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_809; + auto illegal_store_809_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_809 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_809, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_809; + setArg(call_illegal_store_809, 0, reinterpret_cast(this)); + setArg(call_illegal_store_809, 1, 1); + setArg(call_illegal_store_809, 2, EEW); + setArg(call_illegal_store_809, 3, illegal_store_809_arg2); + setRet(call_illegal_store_809, 0, ret_val_illegal_store_809); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_810; + auto vssseg_810_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_810_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_810_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_810_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_810_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_810 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_810, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_810, 64, false), traits::vstart); + setArg(call_vssseg_810, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_810, 1, V); + setArg(call_vssseg_810, 2, vssseg_810_arg1); + setArg(call_vssseg_810, 3, vssseg_810_arg2); + setArg(call_vssseg_810, 4, vssseg_810_arg3); + setArg(call_vssseg_810, 5, vm); + setArg(call_vssseg_810, 6, vs3); + setArg(call_vssseg_810, 7, vssseg_810_arg6); + setArg(call_vssseg_810, 8, 7); + setArg(call_vssseg_810, 9, 1); + setArg(call_vssseg_810, 10, vssseg_810_arg9); + setRet(call_vssseg_810, 0, ret_val_vssseg_810); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 302); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 303: VSSSEG2E8__V */ + continuation_e __vssseg2e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG2E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 303); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_811; + x86::Gp ret_val_get_pow_811 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_811, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_812; + x86::Gp ret_val_get_sew_pow_812 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_812, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_813; + x86::Gp ret_val_get_lmul_pow_813 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_813, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_811, ret_val_get_sew_pow_812), ret_val_get_lmul_pow_813)), 3, true); + setArg(call_get_pow_811, 0, reinterpret_cast(this)); + setArg(call_get_pow_811, 1, EEW); + setRet(call_get_pow_811, 0, ret_val_get_pow_811); + setArg(call_get_sew_pow_812, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_812, 0, ret_val_get_sew_pow_812); + setArg(call_get_lmul_pow_813, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_813, 0, ret_val_get_lmul_pow_813); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_814; + auto illegal_store_814_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_814 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_814, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_814; + setArg(call_illegal_store_814, 0, reinterpret_cast(this)); + setArg(call_illegal_store_814, 1, 2); + setArg(call_illegal_store_814, 2, EEW); + setArg(call_illegal_store_814, 3, illegal_store_814_arg2); + setRet(call_illegal_store_814, 0, ret_val_illegal_store_814); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_815; + auto vssseg_815_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_815_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_815_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_815_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_815_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_815 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_815, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_815, 64, false), traits::vstart); + setArg(call_vssseg_815, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_815, 1, V); + setArg(call_vssseg_815, 2, vssseg_815_arg1); + setArg(call_vssseg_815, 3, vssseg_815_arg2); + setArg(call_vssseg_815, 4, vssseg_815_arg3); + setArg(call_vssseg_815, 5, vm); + setArg(call_vssseg_815, 6, vs3); + setArg(call_vssseg_815, 7, vssseg_815_arg6); + setArg(call_vssseg_815, 8, 0); + setArg(call_vssseg_815, 9, 2); + setArg(call_vssseg_815, 10, vssseg_815_arg9); + setRet(call_vssseg_815, 0, ret_val_vssseg_815); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 303); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 304: VSSSEG2E16__V */ + continuation_e __vssseg2e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG2E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 304); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_816; + x86::Gp ret_val_get_pow_816 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_816, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_817; + x86::Gp ret_val_get_sew_pow_817 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_817, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_818; + x86::Gp ret_val_get_lmul_pow_818 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_818, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_816, ret_val_get_sew_pow_817), ret_val_get_lmul_pow_818)), 3, true); + setArg(call_get_pow_816, 0, reinterpret_cast(this)); + setArg(call_get_pow_816, 1, EEW); + setRet(call_get_pow_816, 0, ret_val_get_pow_816); + setArg(call_get_sew_pow_817, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_817, 0, ret_val_get_sew_pow_817); + setArg(call_get_lmul_pow_818, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_818, 0, ret_val_get_lmul_pow_818); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_819; + auto illegal_store_819_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_819 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_819, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_819; + setArg(call_illegal_store_819, 0, reinterpret_cast(this)); + setArg(call_illegal_store_819, 1, 2); + setArg(call_illegal_store_819, 2, EEW); + setArg(call_illegal_store_819, 3, illegal_store_819_arg2); + setRet(call_illegal_store_819, 0, ret_val_illegal_store_819); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_820; + auto vssseg_820_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_820_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_820_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_820_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_820_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_820 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_820, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_820, 64, false), traits::vstart); + setArg(call_vssseg_820, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_820, 1, V); + setArg(call_vssseg_820, 2, vssseg_820_arg1); + setArg(call_vssseg_820, 3, vssseg_820_arg2); + setArg(call_vssseg_820, 4, vssseg_820_arg3); + setArg(call_vssseg_820, 5, vm); + setArg(call_vssseg_820, 6, vs3); + setArg(call_vssseg_820, 7, vssseg_820_arg6); + setArg(call_vssseg_820, 8, 5); + setArg(call_vssseg_820, 9, 2); + setArg(call_vssseg_820, 10, vssseg_820_arg9); + setRet(call_vssseg_820, 0, ret_val_vssseg_820); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 304); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 305: VSSSEG2E32__V */ + continuation_e __vssseg2e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG2E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 305); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_821; + x86::Gp ret_val_get_pow_821 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_821, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_822; + x86::Gp ret_val_get_sew_pow_822 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_822, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_823; + x86::Gp ret_val_get_lmul_pow_823 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_823, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_821, ret_val_get_sew_pow_822), ret_val_get_lmul_pow_823)), 3, true); + setArg(call_get_pow_821, 0, reinterpret_cast(this)); + setArg(call_get_pow_821, 1, EEW); + setRet(call_get_pow_821, 0, ret_val_get_pow_821); + setArg(call_get_sew_pow_822, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_822, 0, ret_val_get_sew_pow_822); + setArg(call_get_lmul_pow_823, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_823, 0, ret_val_get_lmul_pow_823); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_824; + auto illegal_store_824_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_824 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_824, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_824; + setArg(call_illegal_store_824, 0, reinterpret_cast(this)); + setArg(call_illegal_store_824, 1, 2); + setArg(call_illegal_store_824, 2, EEW); + setArg(call_illegal_store_824, 3, illegal_store_824_arg2); + setRet(call_illegal_store_824, 0, ret_val_illegal_store_824); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_825; + auto vssseg_825_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_825_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_825_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_825_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_825_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_825 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_825, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_825, 64, false), traits::vstart); + setArg(call_vssseg_825, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_825, 1, V); + setArg(call_vssseg_825, 2, vssseg_825_arg1); + setArg(call_vssseg_825, 3, vssseg_825_arg2); + setArg(call_vssseg_825, 4, vssseg_825_arg3); + setArg(call_vssseg_825, 5, vm); + setArg(call_vssseg_825, 6, vs3); + setArg(call_vssseg_825, 7, vssseg_825_arg6); + setArg(call_vssseg_825, 8, 6); + setArg(call_vssseg_825, 9, 2); + setArg(call_vssseg_825, 10, vssseg_825_arg9); + setRet(call_vssseg_825, 0, ret_val_vssseg_825); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 305); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 306: VSSSEG2E64__V */ + continuation_e __vssseg2e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg2e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG2E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 306); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_826; + x86::Gp ret_val_get_pow_826 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_826, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_827; + x86::Gp ret_val_get_sew_pow_827 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_827, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_828; + x86::Gp ret_val_get_lmul_pow_828 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_828, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_826, ret_val_get_sew_pow_827), ret_val_get_lmul_pow_828)), 3, true); + setArg(call_get_pow_826, 0, reinterpret_cast(this)); + setArg(call_get_pow_826, 1, EEW); + setRet(call_get_pow_826, 0, ret_val_get_pow_826); + setArg(call_get_sew_pow_827, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_827, 0, ret_val_get_sew_pow_827); + setArg(call_get_lmul_pow_828, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_828, 0, ret_val_get_lmul_pow_828); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_829; + auto illegal_store_829_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_829 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_829, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_829; + setArg(call_illegal_store_829, 0, reinterpret_cast(this)); + setArg(call_illegal_store_829, 1, 2); + setArg(call_illegal_store_829, 2, EEW); + setArg(call_illegal_store_829, 3, illegal_store_829_arg2); + setRet(call_illegal_store_829, 0, ret_val_illegal_store_829); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_830; + auto vssseg_830_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_830_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_830_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_830_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_830_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_830 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_830, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_830, 64, false), traits::vstart); + setArg(call_vssseg_830, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_830, 1, V); + setArg(call_vssseg_830, 2, vssseg_830_arg1); + setArg(call_vssseg_830, 3, vssseg_830_arg2); + setArg(call_vssseg_830, 4, vssseg_830_arg3); + setArg(call_vssseg_830, 5, vm); + setArg(call_vssseg_830, 6, vs3); + setArg(call_vssseg_830, 7, vssseg_830_arg6); + setArg(call_vssseg_830, 8, 7); + setArg(call_vssseg_830, 9, 2); + setArg(call_vssseg_830, 10, vssseg_830_arg9); + setRet(call_vssseg_830, 0, ret_val_vssseg_830); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 306); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 307: VSSSEG3E8__V */ + continuation_e __vssseg3e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG3E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 307); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_831; + x86::Gp ret_val_get_pow_831 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_831, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_832; + x86::Gp ret_val_get_sew_pow_832 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_832, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_833; + x86::Gp ret_val_get_lmul_pow_833 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_833, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_831, ret_val_get_sew_pow_832), ret_val_get_lmul_pow_833)), 3, true); + setArg(call_get_pow_831, 0, reinterpret_cast(this)); + setArg(call_get_pow_831, 1, EEW); + setRet(call_get_pow_831, 0, ret_val_get_pow_831); + setArg(call_get_sew_pow_832, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_832, 0, ret_val_get_sew_pow_832); + setArg(call_get_lmul_pow_833, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_833, 0, ret_val_get_lmul_pow_833); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_834; + auto illegal_store_834_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_834 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_834, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_834; + setArg(call_illegal_store_834, 0, reinterpret_cast(this)); + setArg(call_illegal_store_834, 1, 3); + setArg(call_illegal_store_834, 2, EEW); + setArg(call_illegal_store_834, 3, illegal_store_834_arg2); + setRet(call_illegal_store_834, 0, ret_val_illegal_store_834); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_835; + auto vssseg_835_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_835_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_835_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_835_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_835_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_835 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_835, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_835, 64, false), traits::vstart); + setArg(call_vssseg_835, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_835, 1, V); + setArg(call_vssseg_835, 2, vssseg_835_arg1); + setArg(call_vssseg_835, 3, vssseg_835_arg2); + setArg(call_vssseg_835, 4, vssseg_835_arg3); + setArg(call_vssseg_835, 5, vm); + setArg(call_vssseg_835, 6, vs3); + setArg(call_vssseg_835, 7, vssseg_835_arg6); + setArg(call_vssseg_835, 8, 0); + setArg(call_vssseg_835, 9, 3); + setArg(call_vssseg_835, 10, vssseg_835_arg9); + setRet(call_vssseg_835, 0, ret_val_vssseg_835); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 307); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 308: VSSSEG3E16__V */ + continuation_e __vssseg3e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG3E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 308); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_836; + x86::Gp ret_val_get_pow_836 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_836, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_837; + x86::Gp ret_val_get_sew_pow_837 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_837, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_838; + x86::Gp ret_val_get_lmul_pow_838 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_838, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_836, ret_val_get_sew_pow_837), ret_val_get_lmul_pow_838)), 3, true); + setArg(call_get_pow_836, 0, reinterpret_cast(this)); + setArg(call_get_pow_836, 1, EEW); + setRet(call_get_pow_836, 0, ret_val_get_pow_836); + setArg(call_get_sew_pow_837, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_837, 0, ret_val_get_sew_pow_837); + setArg(call_get_lmul_pow_838, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_838, 0, ret_val_get_lmul_pow_838); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_839; + auto illegal_store_839_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_839 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_839, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_839; + setArg(call_illegal_store_839, 0, reinterpret_cast(this)); + setArg(call_illegal_store_839, 1, 3); + setArg(call_illegal_store_839, 2, EEW); + setArg(call_illegal_store_839, 3, illegal_store_839_arg2); + setRet(call_illegal_store_839, 0, ret_val_illegal_store_839); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_840; + auto vssseg_840_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_840_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_840_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_840_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_840_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_840 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_840, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_840, 64, false), traits::vstart); + setArg(call_vssseg_840, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_840, 1, V); + setArg(call_vssseg_840, 2, vssseg_840_arg1); + setArg(call_vssseg_840, 3, vssseg_840_arg2); + setArg(call_vssseg_840, 4, vssseg_840_arg3); + setArg(call_vssseg_840, 5, vm); + setArg(call_vssseg_840, 6, vs3); + setArg(call_vssseg_840, 7, vssseg_840_arg6); + setArg(call_vssseg_840, 8, 5); + setArg(call_vssseg_840, 9, 3); + setArg(call_vssseg_840, 10, vssseg_840_arg9); + setRet(call_vssseg_840, 0, ret_val_vssseg_840); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 308); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 309: VSSSEG3E32__V */ + continuation_e __vssseg3e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG3E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 309); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_841; + x86::Gp ret_val_get_pow_841 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_841, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_842; + x86::Gp ret_val_get_sew_pow_842 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_842, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_843; + x86::Gp ret_val_get_lmul_pow_843 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_843, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_841, ret_val_get_sew_pow_842), ret_val_get_lmul_pow_843)), 3, true); + setArg(call_get_pow_841, 0, reinterpret_cast(this)); + setArg(call_get_pow_841, 1, EEW); + setRet(call_get_pow_841, 0, ret_val_get_pow_841); + setArg(call_get_sew_pow_842, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_842, 0, ret_val_get_sew_pow_842); + setArg(call_get_lmul_pow_843, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_843, 0, ret_val_get_lmul_pow_843); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_844; + auto illegal_store_844_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_844 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_844, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_844; + setArg(call_illegal_store_844, 0, reinterpret_cast(this)); + setArg(call_illegal_store_844, 1, 3); + setArg(call_illegal_store_844, 2, EEW); + setArg(call_illegal_store_844, 3, illegal_store_844_arg2); + setRet(call_illegal_store_844, 0, ret_val_illegal_store_844); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_845; + auto vssseg_845_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_845_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_845_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_845_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_845_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_845 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_845, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_845, 64, false), traits::vstart); + setArg(call_vssseg_845, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_845, 1, V); + setArg(call_vssseg_845, 2, vssseg_845_arg1); + setArg(call_vssseg_845, 3, vssseg_845_arg2); + setArg(call_vssseg_845, 4, vssseg_845_arg3); + setArg(call_vssseg_845, 5, vm); + setArg(call_vssseg_845, 6, vs3); + setArg(call_vssseg_845, 7, vssseg_845_arg6); + setArg(call_vssseg_845, 8, 6); + setArg(call_vssseg_845, 9, 3); + setArg(call_vssseg_845, 10, vssseg_845_arg9); + setRet(call_vssseg_845, 0, ret_val_vssseg_845); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 309); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 310: VSSSEG3E64__V */ + continuation_e __vssseg3e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg3e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG3E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 310); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_846; + x86::Gp ret_val_get_pow_846 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_846, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_847; + x86::Gp ret_val_get_sew_pow_847 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_847, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_848; + x86::Gp ret_val_get_lmul_pow_848 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_848, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_846, ret_val_get_sew_pow_847), ret_val_get_lmul_pow_848)), 3, true); + setArg(call_get_pow_846, 0, reinterpret_cast(this)); + setArg(call_get_pow_846, 1, EEW); + setRet(call_get_pow_846, 0, ret_val_get_pow_846); + setArg(call_get_sew_pow_847, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_847, 0, ret_val_get_sew_pow_847); + setArg(call_get_lmul_pow_848, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_848, 0, ret_val_get_lmul_pow_848); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_849; + auto illegal_store_849_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_849 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_849, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_849; + setArg(call_illegal_store_849, 0, reinterpret_cast(this)); + setArg(call_illegal_store_849, 1, 3); + setArg(call_illegal_store_849, 2, EEW); + setArg(call_illegal_store_849, 3, illegal_store_849_arg2); + setRet(call_illegal_store_849, 0, ret_val_illegal_store_849); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_850; + auto vssseg_850_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_850_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_850_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_850_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_850_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_850 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_850, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_850, 64, false), traits::vstart); + setArg(call_vssseg_850, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_850, 1, V); + setArg(call_vssseg_850, 2, vssseg_850_arg1); + setArg(call_vssseg_850, 3, vssseg_850_arg2); + setArg(call_vssseg_850, 4, vssseg_850_arg3); + setArg(call_vssseg_850, 5, vm); + setArg(call_vssseg_850, 6, vs3); + setArg(call_vssseg_850, 7, vssseg_850_arg6); + setArg(call_vssseg_850, 8, 7); + setArg(call_vssseg_850, 9, 3); + setArg(call_vssseg_850, 10, vssseg_850_arg9); + setRet(call_vssseg_850, 0, ret_val_vssseg_850); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 310); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 311: VSSSEG4E8__V */ + continuation_e __vssseg4e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG4E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 311); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_851; + x86::Gp ret_val_get_pow_851 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_851, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_852; + x86::Gp ret_val_get_sew_pow_852 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_852, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_853; + x86::Gp ret_val_get_lmul_pow_853 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_853, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_851, ret_val_get_sew_pow_852), ret_val_get_lmul_pow_853)), 3, true); + setArg(call_get_pow_851, 0, reinterpret_cast(this)); + setArg(call_get_pow_851, 1, EEW); + setRet(call_get_pow_851, 0, ret_val_get_pow_851); + setArg(call_get_sew_pow_852, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_852, 0, ret_val_get_sew_pow_852); + setArg(call_get_lmul_pow_853, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_853, 0, ret_val_get_lmul_pow_853); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_854; + auto illegal_store_854_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_854 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_854, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_854; + setArg(call_illegal_store_854, 0, reinterpret_cast(this)); + setArg(call_illegal_store_854, 1, 4); + setArg(call_illegal_store_854, 2, EEW); + setArg(call_illegal_store_854, 3, illegal_store_854_arg2); + setRet(call_illegal_store_854, 0, ret_val_illegal_store_854); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_855; + auto vssseg_855_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_855_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_855_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_855_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_855_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_855 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_855, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_855, 64, false), traits::vstart); + setArg(call_vssseg_855, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_855, 1, V); + setArg(call_vssseg_855, 2, vssseg_855_arg1); + setArg(call_vssseg_855, 3, vssseg_855_arg2); + setArg(call_vssseg_855, 4, vssseg_855_arg3); + setArg(call_vssseg_855, 5, vm); + setArg(call_vssseg_855, 6, vs3); + setArg(call_vssseg_855, 7, vssseg_855_arg6); + setArg(call_vssseg_855, 8, 0); + setArg(call_vssseg_855, 9, 4); + setArg(call_vssseg_855, 10, vssseg_855_arg9); + setRet(call_vssseg_855, 0, ret_val_vssseg_855); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 311); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 312: VSSSEG4E16__V */ + continuation_e __vssseg4e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG4E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 312); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_856; + x86::Gp ret_val_get_pow_856 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_856, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_857; + x86::Gp ret_val_get_sew_pow_857 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_857, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_858; + x86::Gp ret_val_get_lmul_pow_858 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_858, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_856, ret_val_get_sew_pow_857), ret_val_get_lmul_pow_858)), 3, true); + setArg(call_get_pow_856, 0, reinterpret_cast(this)); + setArg(call_get_pow_856, 1, EEW); + setRet(call_get_pow_856, 0, ret_val_get_pow_856); + setArg(call_get_sew_pow_857, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_857, 0, ret_val_get_sew_pow_857); + setArg(call_get_lmul_pow_858, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_858, 0, ret_val_get_lmul_pow_858); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_859; + auto illegal_store_859_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_859 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_859, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_859; + setArg(call_illegal_store_859, 0, reinterpret_cast(this)); + setArg(call_illegal_store_859, 1, 4); + setArg(call_illegal_store_859, 2, EEW); + setArg(call_illegal_store_859, 3, illegal_store_859_arg2); + setRet(call_illegal_store_859, 0, ret_val_illegal_store_859); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_860; + auto vssseg_860_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_860_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_860_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_860_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_860_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_860 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_860, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_860, 64, false), traits::vstart); + setArg(call_vssseg_860, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_860, 1, V); + setArg(call_vssseg_860, 2, vssseg_860_arg1); + setArg(call_vssseg_860, 3, vssseg_860_arg2); + setArg(call_vssseg_860, 4, vssseg_860_arg3); + setArg(call_vssseg_860, 5, vm); + setArg(call_vssseg_860, 6, vs3); + setArg(call_vssseg_860, 7, vssseg_860_arg6); + setArg(call_vssseg_860, 8, 5); + setArg(call_vssseg_860, 9, 4); + setArg(call_vssseg_860, 10, vssseg_860_arg9); + setRet(call_vssseg_860, 0, ret_val_vssseg_860); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 312); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 313: VSSSEG4E32__V */ + continuation_e __vssseg4e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG4E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 313); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_861; + x86::Gp ret_val_get_pow_861 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_861, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_862; + x86::Gp ret_val_get_sew_pow_862 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_862, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_863; + x86::Gp ret_val_get_lmul_pow_863 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_863, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_861, ret_val_get_sew_pow_862), ret_val_get_lmul_pow_863)), 3, true); + setArg(call_get_pow_861, 0, reinterpret_cast(this)); + setArg(call_get_pow_861, 1, EEW); + setRet(call_get_pow_861, 0, ret_val_get_pow_861); + setArg(call_get_sew_pow_862, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_862, 0, ret_val_get_sew_pow_862); + setArg(call_get_lmul_pow_863, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_863, 0, ret_val_get_lmul_pow_863); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_864; + auto illegal_store_864_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_864 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_864, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_864; + setArg(call_illegal_store_864, 0, reinterpret_cast(this)); + setArg(call_illegal_store_864, 1, 4); + setArg(call_illegal_store_864, 2, EEW); + setArg(call_illegal_store_864, 3, illegal_store_864_arg2); + setRet(call_illegal_store_864, 0, ret_val_illegal_store_864); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_865; + auto vssseg_865_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_865_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_865_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_865_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_865_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_865 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_865, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_865, 64, false), traits::vstart); + setArg(call_vssseg_865, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_865, 1, V); + setArg(call_vssseg_865, 2, vssseg_865_arg1); + setArg(call_vssseg_865, 3, vssseg_865_arg2); + setArg(call_vssseg_865, 4, vssseg_865_arg3); + setArg(call_vssseg_865, 5, vm); + setArg(call_vssseg_865, 6, vs3); + setArg(call_vssseg_865, 7, vssseg_865_arg6); + setArg(call_vssseg_865, 8, 6); + setArg(call_vssseg_865, 9, 4); + setArg(call_vssseg_865, 10, vssseg_865_arg9); + setRet(call_vssseg_865, 0, ret_val_vssseg_865); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 313); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 314: VSSSEG4E64__V */ + continuation_e __vssseg4e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg4e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG4E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 314); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_866; + x86::Gp ret_val_get_pow_866 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_866, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_867; + x86::Gp ret_val_get_sew_pow_867 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_867, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_868; + x86::Gp ret_val_get_lmul_pow_868 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_868, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_866, ret_val_get_sew_pow_867), ret_val_get_lmul_pow_868)), 3, true); + setArg(call_get_pow_866, 0, reinterpret_cast(this)); + setArg(call_get_pow_866, 1, EEW); + setRet(call_get_pow_866, 0, ret_val_get_pow_866); + setArg(call_get_sew_pow_867, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_867, 0, ret_val_get_sew_pow_867); + setArg(call_get_lmul_pow_868, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_868, 0, ret_val_get_lmul_pow_868); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_869; + auto illegal_store_869_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_869 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_869, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_869; + setArg(call_illegal_store_869, 0, reinterpret_cast(this)); + setArg(call_illegal_store_869, 1, 4); + setArg(call_illegal_store_869, 2, EEW); + setArg(call_illegal_store_869, 3, illegal_store_869_arg2); + setRet(call_illegal_store_869, 0, ret_val_illegal_store_869); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_870; + auto vssseg_870_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_870_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_870_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_870_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_870_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_870 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_870, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_870, 64, false), traits::vstart); + setArg(call_vssseg_870, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_870, 1, V); + setArg(call_vssseg_870, 2, vssseg_870_arg1); + setArg(call_vssseg_870, 3, vssseg_870_arg2); + setArg(call_vssseg_870, 4, vssseg_870_arg3); + setArg(call_vssseg_870, 5, vm); + setArg(call_vssseg_870, 6, vs3); + setArg(call_vssseg_870, 7, vssseg_870_arg6); + setArg(call_vssseg_870, 8, 7); + setArg(call_vssseg_870, 9, 4); + setArg(call_vssseg_870, 10, vssseg_870_arg9); + setRet(call_vssseg_870, 0, ret_val_vssseg_870); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 314); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 315: VSSSEG5E8__V */ + continuation_e __vssseg5e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG5E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 315); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_871; + x86::Gp ret_val_get_pow_871 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_871, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_872; + x86::Gp ret_val_get_sew_pow_872 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_872, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_873; + x86::Gp ret_val_get_lmul_pow_873 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_873, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_871, ret_val_get_sew_pow_872), ret_val_get_lmul_pow_873)), 3, true); + setArg(call_get_pow_871, 0, reinterpret_cast(this)); + setArg(call_get_pow_871, 1, EEW); + setRet(call_get_pow_871, 0, ret_val_get_pow_871); + setArg(call_get_sew_pow_872, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_872, 0, ret_val_get_sew_pow_872); + setArg(call_get_lmul_pow_873, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_873, 0, ret_val_get_lmul_pow_873); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_874; + auto illegal_store_874_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_874 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_874, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_874; + setArg(call_illegal_store_874, 0, reinterpret_cast(this)); + setArg(call_illegal_store_874, 1, 5); + setArg(call_illegal_store_874, 2, EEW); + setArg(call_illegal_store_874, 3, illegal_store_874_arg2); + setRet(call_illegal_store_874, 0, ret_val_illegal_store_874); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_875; + auto vssseg_875_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_875_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_875_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_875_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_875_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_875 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_875, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_875, 64, false), traits::vstart); + setArg(call_vssseg_875, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_875, 1, V); + setArg(call_vssseg_875, 2, vssseg_875_arg1); + setArg(call_vssseg_875, 3, vssseg_875_arg2); + setArg(call_vssseg_875, 4, vssseg_875_arg3); + setArg(call_vssseg_875, 5, vm); + setArg(call_vssseg_875, 6, vs3); + setArg(call_vssseg_875, 7, vssseg_875_arg6); + setArg(call_vssseg_875, 8, 0); + setArg(call_vssseg_875, 9, 5); + setArg(call_vssseg_875, 10, vssseg_875_arg9); + setRet(call_vssseg_875, 0, ret_val_vssseg_875); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 315); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 316: VSSSEG5E16__V */ + continuation_e __vssseg5e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG5E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 316); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_876; + x86::Gp ret_val_get_pow_876 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_876, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_877; + x86::Gp ret_val_get_sew_pow_877 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_877, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_878; + x86::Gp ret_val_get_lmul_pow_878 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_878, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_876, ret_val_get_sew_pow_877), ret_val_get_lmul_pow_878)), 3, true); + setArg(call_get_pow_876, 0, reinterpret_cast(this)); + setArg(call_get_pow_876, 1, EEW); + setRet(call_get_pow_876, 0, ret_val_get_pow_876); + setArg(call_get_sew_pow_877, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_877, 0, ret_val_get_sew_pow_877); + setArg(call_get_lmul_pow_878, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_878, 0, ret_val_get_lmul_pow_878); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_879; + auto illegal_store_879_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_879 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_879, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_879; + setArg(call_illegal_store_879, 0, reinterpret_cast(this)); + setArg(call_illegal_store_879, 1, 5); + setArg(call_illegal_store_879, 2, EEW); + setArg(call_illegal_store_879, 3, illegal_store_879_arg2); + setRet(call_illegal_store_879, 0, ret_val_illegal_store_879); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_880; + auto vssseg_880_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_880_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_880_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_880_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_880_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_880 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_880, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_880, 64, false), traits::vstart); + setArg(call_vssseg_880, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_880, 1, V); + setArg(call_vssseg_880, 2, vssseg_880_arg1); + setArg(call_vssseg_880, 3, vssseg_880_arg2); + setArg(call_vssseg_880, 4, vssseg_880_arg3); + setArg(call_vssseg_880, 5, vm); + setArg(call_vssseg_880, 6, vs3); + setArg(call_vssseg_880, 7, vssseg_880_arg6); + setArg(call_vssseg_880, 8, 5); + setArg(call_vssseg_880, 9, 5); + setArg(call_vssseg_880, 10, vssseg_880_arg9); + setRet(call_vssseg_880, 0, ret_val_vssseg_880); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 316); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 317: VSSSEG5E32__V */ + continuation_e __vssseg5e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG5E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 317); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_881; + x86::Gp ret_val_get_pow_881 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_881, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_882; + x86::Gp ret_val_get_sew_pow_882 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_882, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_883; + x86::Gp ret_val_get_lmul_pow_883 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_883, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_881, ret_val_get_sew_pow_882), ret_val_get_lmul_pow_883)), 3, true); + setArg(call_get_pow_881, 0, reinterpret_cast(this)); + setArg(call_get_pow_881, 1, EEW); + setRet(call_get_pow_881, 0, ret_val_get_pow_881); + setArg(call_get_sew_pow_882, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_882, 0, ret_val_get_sew_pow_882); + setArg(call_get_lmul_pow_883, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_883, 0, ret_val_get_lmul_pow_883); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_884; + auto illegal_store_884_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_884 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_884, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_884; + setArg(call_illegal_store_884, 0, reinterpret_cast(this)); + setArg(call_illegal_store_884, 1, 5); + setArg(call_illegal_store_884, 2, EEW); + setArg(call_illegal_store_884, 3, illegal_store_884_arg2); + setRet(call_illegal_store_884, 0, ret_val_illegal_store_884); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_885; + auto vssseg_885_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_885_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_885_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_885_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_885_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_885 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_885, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_885, 64, false), traits::vstart); + setArg(call_vssseg_885, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_885, 1, V); + setArg(call_vssseg_885, 2, vssseg_885_arg1); + setArg(call_vssseg_885, 3, vssseg_885_arg2); + setArg(call_vssseg_885, 4, vssseg_885_arg3); + setArg(call_vssseg_885, 5, vm); + setArg(call_vssseg_885, 6, vs3); + setArg(call_vssseg_885, 7, vssseg_885_arg6); + setArg(call_vssseg_885, 8, 6); + setArg(call_vssseg_885, 9, 5); + setArg(call_vssseg_885, 10, vssseg_885_arg9); + setRet(call_vssseg_885, 0, ret_val_vssseg_885); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 317); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 318: VSSSEG5E64__V */ + continuation_e __vssseg5e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg5e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG5E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 318); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_886; + x86::Gp ret_val_get_pow_886 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_886, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_887; + x86::Gp ret_val_get_sew_pow_887 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_887, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_888; + x86::Gp ret_val_get_lmul_pow_888 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_888, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_886, ret_val_get_sew_pow_887), ret_val_get_lmul_pow_888)), 3, true); + setArg(call_get_pow_886, 0, reinterpret_cast(this)); + setArg(call_get_pow_886, 1, EEW); + setRet(call_get_pow_886, 0, ret_val_get_pow_886); + setArg(call_get_sew_pow_887, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_887, 0, ret_val_get_sew_pow_887); + setArg(call_get_lmul_pow_888, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_888, 0, ret_val_get_lmul_pow_888); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_889; + auto illegal_store_889_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_889 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_889, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_889; + setArg(call_illegal_store_889, 0, reinterpret_cast(this)); + setArg(call_illegal_store_889, 1, 5); + setArg(call_illegal_store_889, 2, EEW); + setArg(call_illegal_store_889, 3, illegal_store_889_arg2); + setRet(call_illegal_store_889, 0, ret_val_illegal_store_889); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_890; + auto vssseg_890_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_890_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_890_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_890_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_890_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_890 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_890, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_890, 64, false), traits::vstart); + setArg(call_vssseg_890, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_890, 1, V); + setArg(call_vssseg_890, 2, vssseg_890_arg1); + setArg(call_vssseg_890, 3, vssseg_890_arg2); + setArg(call_vssseg_890, 4, vssseg_890_arg3); + setArg(call_vssseg_890, 5, vm); + setArg(call_vssseg_890, 6, vs3); + setArg(call_vssseg_890, 7, vssseg_890_arg6); + setArg(call_vssseg_890, 8, 7); + setArg(call_vssseg_890, 9, 5); + setArg(call_vssseg_890, 10, vssseg_890_arg9); + setRet(call_vssseg_890, 0, ret_val_vssseg_890); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 318); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 319: VSSSEG6E8__V */ + continuation_e __vssseg6e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG6E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 319); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_891; + x86::Gp ret_val_get_pow_891 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_891, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_892; + x86::Gp ret_val_get_sew_pow_892 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_892, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_893; + x86::Gp ret_val_get_lmul_pow_893 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_893, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_891, ret_val_get_sew_pow_892), ret_val_get_lmul_pow_893)), 3, true); + setArg(call_get_pow_891, 0, reinterpret_cast(this)); + setArg(call_get_pow_891, 1, EEW); + setRet(call_get_pow_891, 0, ret_val_get_pow_891); + setArg(call_get_sew_pow_892, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_892, 0, ret_val_get_sew_pow_892); + setArg(call_get_lmul_pow_893, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_893, 0, ret_val_get_lmul_pow_893); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_894; + auto illegal_store_894_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_894 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_894, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_894; + setArg(call_illegal_store_894, 0, reinterpret_cast(this)); + setArg(call_illegal_store_894, 1, 6); + setArg(call_illegal_store_894, 2, EEW); + setArg(call_illegal_store_894, 3, illegal_store_894_arg2); + setRet(call_illegal_store_894, 0, ret_val_illegal_store_894); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_895; + auto vssseg_895_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_895_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_895_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_895_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_895_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_895 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_895, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_895, 64, false), traits::vstart); + setArg(call_vssseg_895, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_895, 1, V); + setArg(call_vssseg_895, 2, vssseg_895_arg1); + setArg(call_vssseg_895, 3, vssseg_895_arg2); + setArg(call_vssseg_895, 4, vssseg_895_arg3); + setArg(call_vssseg_895, 5, vm); + setArg(call_vssseg_895, 6, vs3); + setArg(call_vssseg_895, 7, vssseg_895_arg6); + setArg(call_vssseg_895, 8, 0); + setArg(call_vssseg_895, 9, 6); + setArg(call_vssseg_895, 10, vssseg_895_arg9); + setRet(call_vssseg_895, 0, ret_val_vssseg_895); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 319); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 320: VSSSEG6E16__V */ + continuation_e __vssseg6e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG6E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 320); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_896; + x86::Gp ret_val_get_pow_896 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_896, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_897; + x86::Gp ret_val_get_sew_pow_897 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_897, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_898; + x86::Gp ret_val_get_lmul_pow_898 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_898, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_896, ret_val_get_sew_pow_897), ret_val_get_lmul_pow_898)), 3, true); + setArg(call_get_pow_896, 0, reinterpret_cast(this)); + setArg(call_get_pow_896, 1, EEW); + setRet(call_get_pow_896, 0, ret_val_get_pow_896); + setArg(call_get_sew_pow_897, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_897, 0, ret_val_get_sew_pow_897); + setArg(call_get_lmul_pow_898, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_898, 0, ret_val_get_lmul_pow_898); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_899; + auto illegal_store_899_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_899 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_899, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_899; + setArg(call_illegal_store_899, 0, reinterpret_cast(this)); + setArg(call_illegal_store_899, 1, 6); + setArg(call_illegal_store_899, 2, EEW); + setArg(call_illegal_store_899, 3, illegal_store_899_arg2); + setRet(call_illegal_store_899, 0, ret_val_illegal_store_899); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_900; + auto vssseg_900_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_900_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_900_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_900_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_900_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_900 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_900, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_900, 64, false), traits::vstart); + setArg(call_vssseg_900, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_900, 1, V); + setArg(call_vssseg_900, 2, vssseg_900_arg1); + setArg(call_vssseg_900, 3, vssseg_900_arg2); + setArg(call_vssseg_900, 4, vssseg_900_arg3); + setArg(call_vssseg_900, 5, vm); + setArg(call_vssseg_900, 6, vs3); + setArg(call_vssseg_900, 7, vssseg_900_arg6); + setArg(call_vssseg_900, 8, 5); + setArg(call_vssseg_900, 9, 6); + setArg(call_vssseg_900, 10, vssseg_900_arg9); + setRet(call_vssseg_900, 0, ret_val_vssseg_900); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 320); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 321: VSSSEG6E32__V */ + continuation_e __vssseg6e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG6E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 321); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_901; + x86::Gp ret_val_get_pow_901 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_901, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_902; + x86::Gp ret_val_get_sew_pow_902 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_902, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_903; + x86::Gp ret_val_get_lmul_pow_903 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_903, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_901, ret_val_get_sew_pow_902), ret_val_get_lmul_pow_903)), 3, true); + setArg(call_get_pow_901, 0, reinterpret_cast(this)); + setArg(call_get_pow_901, 1, EEW); + setRet(call_get_pow_901, 0, ret_val_get_pow_901); + setArg(call_get_sew_pow_902, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_902, 0, ret_val_get_sew_pow_902); + setArg(call_get_lmul_pow_903, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_903, 0, ret_val_get_lmul_pow_903); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_904; + auto illegal_store_904_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_904 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_904, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_904; + setArg(call_illegal_store_904, 0, reinterpret_cast(this)); + setArg(call_illegal_store_904, 1, 6); + setArg(call_illegal_store_904, 2, EEW); + setArg(call_illegal_store_904, 3, illegal_store_904_arg2); + setRet(call_illegal_store_904, 0, ret_val_illegal_store_904); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_905; + auto vssseg_905_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_905_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_905_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_905_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_905_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_905 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_905, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_905, 64, false), traits::vstart); + setArg(call_vssseg_905, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_905, 1, V); + setArg(call_vssseg_905, 2, vssseg_905_arg1); + setArg(call_vssseg_905, 3, vssseg_905_arg2); + setArg(call_vssseg_905, 4, vssseg_905_arg3); + setArg(call_vssseg_905, 5, vm); + setArg(call_vssseg_905, 6, vs3); + setArg(call_vssseg_905, 7, vssseg_905_arg6); + setArg(call_vssseg_905, 8, 6); + setArg(call_vssseg_905, 9, 6); + setArg(call_vssseg_905, 10, vssseg_905_arg9); + setRet(call_vssseg_905, 0, ret_val_vssseg_905); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 321); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 322: VSSSEG6E64__V */ + continuation_e __vssseg6e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg6e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG6E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 322); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_906; + x86::Gp ret_val_get_pow_906 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_906, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_907; + x86::Gp ret_val_get_sew_pow_907 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_907, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_908; + x86::Gp ret_val_get_lmul_pow_908 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_908, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_906, ret_val_get_sew_pow_907), ret_val_get_lmul_pow_908)), 3, true); + setArg(call_get_pow_906, 0, reinterpret_cast(this)); + setArg(call_get_pow_906, 1, EEW); + setRet(call_get_pow_906, 0, ret_val_get_pow_906); + setArg(call_get_sew_pow_907, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_907, 0, ret_val_get_sew_pow_907); + setArg(call_get_lmul_pow_908, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_908, 0, ret_val_get_lmul_pow_908); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_909; + auto illegal_store_909_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_909 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_909, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_909; + setArg(call_illegal_store_909, 0, reinterpret_cast(this)); + setArg(call_illegal_store_909, 1, 6); + setArg(call_illegal_store_909, 2, EEW); + setArg(call_illegal_store_909, 3, illegal_store_909_arg2); + setRet(call_illegal_store_909, 0, ret_val_illegal_store_909); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_910; + auto vssseg_910_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_910_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_910_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_910_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_910_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_910 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_910, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_910, 64, false), traits::vstart); + setArg(call_vssseg_910, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_910, 1, V); + setArg(call_vssseg_910, 2, vssseg_910_arg1); + setArg(call_vssseg_910, 3, vssseg_910_arg2); + setArg(call_vssseg_910, 4, vssseg_910_arg3); + setArg(call_vssseg_910, 5, vm); + setArg(call_vssseg_910, 6, vs3); + setArg(call_vssseg_910, 7, vssseg_910_arg6); + setArg(call_vssseg_910, 8, 7); + setArg(call_vssseg_910, 9, 6); + setArg(call_vssseg_910, 10, vssseg_910_arg9); + setRet(call_vssseg_910, 0, ret_val_vssseg_910); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 322); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 323: VSSSEG7E8__V */ + continuation_e __vssseg7e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG7E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 323); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_911; + x86::Gp ret_val_get_pow_911 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_911, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_912; + x86::Gp ret_val_get_sew_pow_912 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_912, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_913; + x86::Gp ret_val_get_lmul_pow_913 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_913, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_911, ret_val_get_sew_pow_912), ret_val_get_lmul_pow_913)), 3, true); + setArg(call_get_pow_911, 0, reinterpret_cast(this)); + setArg(call_get_pow_911, 1, EEW); + setRet(call_get_pow_911, 0, ret_val_get_pow_911); + setArg(call_get_sew_pow_912, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_912, 0, ret_val_get_sew_pow_912); + setArg(call_get_lmul_pow_913, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_913, 0, ret_val_get_lmul_pow_913); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_914; + auto illegal_store_914_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_914 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_914, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_914; + setArg(call_illegal_store_914, 0, reinterpret_cast(this)); + setArg(call_illegal_store_914, 1, 7); + setArg(call_illegal_store_914, 2, EEW); + setArg(call_illegal_store_914, 3, illegal_store_914_arg2); + setRet(call_illegal_store_914, 0, ret_val_illegal_store_914); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_915; + auto vssseg_915_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_915_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_915_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_915_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_915_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_915 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_915, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_915, 64, false), traits::vstart); + setArg(call_vssseg_915, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_915, 1, V); + setArg(call_vssseg_915, 2, vssseg_915_arg1); + setArg(call_vssseg_915, 3, vssseg_915_arg2); + setArg(call_vssseg_915, 4, vssseg_915_arg3); + setArg(call_vssseg_915, 5, vm); + setArg(call_vssseg_915, 6, vs3); + setArg(call_vssseg_915, 7, vssseg_915_arg6); + setArg(call_vssseg_915, 8, 0); + setArg(call_vssseg_915, 9, 7); + setArg(call_vssseg_915, 10, vssseg_915_arg9); + setRet(call_vssseg_915, 0, ret_val_vssseg_915); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 323); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 324: VSSSEG7E16__V */ + continuation_e __vssseg7e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG7E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 324); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_916; + x86::Gp ret_val_get_pow_916 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_916, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_917; + x86::Gp ret_val_get_sew_pow_917 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_917, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_918; + x86::Gp ret_val_get_lmul_pow_918 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_918, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_916, ret_val_get_sew_pow_917), ret_val_get_lmul_pow_918)), 3, true); + setArg(call_get_pow_916, 0, reinterpret_cast(this)); + setArg(call_get_pow_916, 1, EEW); + setRet(call_get_pow_916, 0, ret_val_get_pow_916); + setArg(call_get_sew_pow_917, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_917, 0, ret_val_get_sew_pow_917); + setArg(call_get_lmul_pow_918, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_918, 0, ret_val_get_lmul_pow_918); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_919; + auto illegal_store_919_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_919 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_919, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_919; + setArg(call_illegal_store_919, 0, reinterpret_cast(this)); + setArg(call_illegal_store_919, 1, 7); + setArg(call_illegal_store_919, 2, EEW); + setArg(call_illegal_store_919, 3, illegal_store_919_arg2); + setRet(call_illegal_store_919, 0, ret_val_illegal_store_919); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_920; + auto vssseg_920_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_920_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_920_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_920_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_920_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_920 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_920, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_920, 64, false), traits::vstart); + setArg(call_vssseg_920, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_920, 1, V); + setArg(call_vssseg_920, 2, vssseg_920_arg1); + setArg(call_vssseg_920, 3, vssseg_920_arg2); + setArg(call_vssseg_920, 4, vssseg_920_arg3); + setArg(call_vssseg_920, 5, vm); + setArg(call_vssseg_920, 6, vs3); + setArg(call_vssseg_920, 7, vssseg_920_arg6); + setArg(call_vssseg_920, 8, 5); + setArg(call_vssseg_920, 9, 7); + setArg(call_vssseg_920, 10, vssseg_920_arg9); + setRet(call_vssseg_920, 0, ret_val_vssseg_920); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 324); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 325: VSSSEG7E32__V */ + continuation_e __vssseg7e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG7E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 325); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_921; + x86::Gp ret_val_get_pow_921 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_921, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_922; + x86::Gp ret_val_get_sew_pow_922 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_922, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_923; + x86::Gp ret_val_get_lmul_pow_923 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_923, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_921, ret_val_get_sew_pow_922), ret_val_get_lmul_pow_923)), 3, true); + setArg(call_get_pow_921, 0, reinterpret_cast(this)); + setArg(call_get_pow_921, 1, EEW); + setRet(call_get_pow_921, 0, ret_val_get_pow_921); + setArg(call_get_sew_pow_922, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_922, 0, ret_val_get_sew_pow_922); + setArg(call_get_lmul_pow_923, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_923, 0, ret_val_get_lmul_pow_923); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_924; + auto illegal_store_924_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_924 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_924, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_924; + setArg(call_illegal_store_924, 0, reinterpret_cast(this)); + setArg(call_illegal_store_924, 1, 7); + setArg(call_illegal_store_924, 2, EEW); + setArg(call_illegal_store_924, 3, illegal_store_924_arg2); + setRet(call_illegal_store_924, 0, ret_val_illegal_store_924); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_925; + auto vssseg_925_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_925_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_925_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_925_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_925_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_925 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_925, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_925, 64, false), traits::vstart); + setArg(call_vssseg_925, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_925, 1, V); + setArg(call_vssseg_925, 2, vssseg_925_arg1); + setArg(call_vssseg_925, 3, vssseg_925_arg2); + setArg(call_vssseg_925, 4, vssseg_925_arg3); + setArg(call_vssseg_925, 5, vm); + setArg(call_vssseg_925, 6, vs3); + setArg(call_vssseg_925, 7, vssseg_925_arg6); + setArg(call_vssseg_925, 8, 6); + setArg(call_vssseg_925, 9, 7); + setArg(call_vssseg_925, 10, vssseg_925_arg9); + setRet(call_vssseg_925, 0, ret_val_vssseg_925); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 325); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 326: VSSSEG7E64__V */ + continuation_e __vssseg7e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg7e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG7E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 326); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_926; + x86::Gp ret_val_get_pow_926 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_926, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_927; + x86::Gp ret_val_get_sew_pow_927 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_927, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_928; + x86::Gp ret_val_get_lmul_pow_928 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_928, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_926, ret_val_get_sew_pow_927), ret_val_get_lmul_pow_928)), 3, true); + setArg(call_get_pow_926, 0, reinterpret_cast(this)); + setArg(call_get_pow_926, 1, EEW); + setRet(call_get_pow_926, 0, ret_val_get_pow_926); + setArg(call_get_sew_pow_927, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_927, 0, ret_val_get_sew_pow_927); + setArg(call_get_lmul_pow_928, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_928, 0, ret_val_get_lmul_pow_928); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_929; + auto illegal_store_929_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_929 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_929, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_929; + setArg(call_illegal_store_929, 0, reinterpret_cast(this)); + setArg(call_illegal_store_929, 1, 7); + setArg(call_illegal_store_929, 2, EEW); + setArg(call_illegal_store_929, 3, illegal_store_929_arg2); + setRet(call_illegal_store_929, 0, ret_val_illegal_store_929); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_930; + auto vssseg_930_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_930_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_930_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_930_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_930_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_930 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_930, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_930, 64, false), traits::vstart); + setArg(call_vssseg_930, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_930, 1, V); + setArg(call_vssseg_930, 2, vssseg_930_arg1); + setArg(call_vssseg_930, 3, vssseg_930_arg2); + setArg(call_vssseg_930, 4, vssseg_930_arg3); + setArg(call_vssseg_930, 5, vm); + setArg(call_vssseg_930, 6, vs3); + setArg(call_vssseg_930, 7, vssseg_930_arg6); + setArg(call_vssseg_930, 8, 7); + setArg(call_vssseg_930, 9, 7); + setArg(call_vssseg_930, 10, vssseg_930_arg9); + setRet(call_vssseg_930, 0, ret_val_vssseg_930); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 326); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 327: VSSSEG8E8__V */ + continuation_e __vssseg8e8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG8E8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 327); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_931; + x86::Gp ret_val_get_pow_931 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_931, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_932; + x86::Gp ret_val_get_sew_pow_932 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_932, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_933; + x86::Gp ret_val_get_lmul_pow_933 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_933, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_931, ret_val_get_sew_pow_932), ret_val_get_lmul_pow_933)), 3, true); + setArg(call_get_pow_931, 0, reinterpret_cast(this)); + setArg(call_get_pow_931, 1, EEW); + setRet(call_get_pow_931, 0, ret_val_get_pow_931); + setArg(call_get_sew_pow_932, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_932, 0, ret_val_get_sew_pow_932); + setArg(call_get_lmul_pow_933, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_933, 0, ret_val_get_lmul_pow_933); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_934; + auto illegal_store_934_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_934 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_934, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_934; + setArg(call_illegal_store_934, 0, reinterpret_cast(this)); + setArg(call_illegal_store_934, 1, 8); + setArg(call_illegal_store_934, 2, EEW); + setArg(call_illegal_store_934, 3, illegal_store_934_arg2); + setRet(call_illegal_store_934, 0, ret_val_illegal_store_934); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_935; + auto vssseg_935_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_935_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_935_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_935_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_935_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_935 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_935, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_935, 64, false), traits::vstart); + setArg(call_vssseg_935, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_935, 1, V); + setArg(call_vssseg_935, 2, vssseg_935_arg1); + setArg(call_vssseg_935, 3, vssseg_935_arg2); + setArg(call_vssseg_935, 4, vssseg_935_arg3); + setArg(call_vssseg_935, 5, vm); + setArg(call_vssseg_935, 6, vs3); + setArg(call_vssseg_935, 7, vssseg_935_arg6); + setArg(call_vssseg_935, 8, 0); + setArg(call_vssseg_935, 9, 8); + setArg(call_vssseg_935, 10, vssseg_935_arg9); + setRet(call_vssseg_935, 0, ret_val_vssseg_935); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 327); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 328: VSSSEG8E16__V */ + continuation_e __vssseg8e16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG8E16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 328); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_936; + x86::Gp ret_val_get_pow_936 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_936, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_937; + x86::Gp ret_val_get_sew_pow_937 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_937, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_938; + x86::Gp ret_val_get_lmul_pow_938 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_938, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_936, ret_val_get_sew_pow_937), ret_val_get_lmul_pow_938)), 3, true); + setArg(call_get_pow_936, 0, reinterpret_cast(this)); + setArg(call_get_pow_936, 1, EEW); + setRet(call_get_pow_936, 0, ret_val_get_pow_936); + setArg(call_get_sew_pow_937, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_937, 0, ret_val_get_sew_pow_937); + setArg(call_get_lmul_pow_938, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_938, 0, ret_val_get_lmul_pow_938); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_939; + auto illegal_store_939_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_939 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_939, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_939; + setArg(call_illegal_store_939, 0, reinterpret_cast(this)); + setArg(call_illegal_store_939, 1, 8); + setArg(call_illegal_store_939, 2, EEW); + setArg(call_illegal_store_939, 3, illegal_store_939_arg2); + setRet(call_illegal_store_939, 0, ret_val_illegal_store_939); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_940; + auto vssseg_940_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_940_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_940_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_940_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_940_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_940 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_940, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_940, 64, false), traits::vstart); + setArg(call_vssseg_940, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_940, 1, V); + setArg(call_vssseg_940, 2, vssseg_940_arg1); + setArg(call_vssseg_940, 3, vssseg_940_arg2); + setArg(call_vssseg_940, 4, vssseg_940_arg3); + setArg(call_vssseg_940, 5, vm); + setArg(call_vssseg_940, 6, vs3); + setArg(call_vssseg_940, 7, vssseg_940_arg6); + setArg(call_vssseg_940, 8, 5); + setArg(call_vssseg_940, 9, 8); + setArg(call_vssseg_940, 10, vssseg_940_arg9); + setRet(call_vssseg_940, 0, ret_val_vssseg_940); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 328); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 329: VSSSEG8E32__V */ + continuation_e __vssseg8e32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG8E32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 329); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_941; + x86::Gp ret_val_get_pow_941 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_941, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_942; + x86::Gp ret_val_get_sew_pow_942 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_942, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_943; + x86::Gp ret_val_get_lmul_pow_943 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_943, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_941, ret_val_get_sew_pow_942), ret_val_get_lmul_pow_943)), 3, true); + setArg(call_get_pow_941, 0, reinterpret_cast(this)); + setArg(call_get_pow_941, 1, EEW); + setRet(call_get_pow_941, 0, ret_val_get_pow_941); + setArg(call_get_sew_pow_942, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_942, 0, ret_val_get_sew_pow_942); + setArg(call_get_lmul_pow_943, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_943, 0, ret_val_get_lmul_pow_943); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_944; + auto illegal_store_944_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_944 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_944, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_944; + setArg(call_illegal_store_944, 0, reinterpret_cast(this)); + setArg(call_illegal_store_944, 1, 8); + setArg(call_illegal_store_944, 2, EEW); + setArg(call_illegal_store_944, 3, illegal_store_944_arg2); + setRet(call_illegal_store_944, 0, ret_val_illegal_store_944); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_945; + auto vssseg_945_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_945_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_945_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_945_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_945_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_945 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_945, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_945, 64, false), traits::vstart); + setArg(call_vssseg_945, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_945, 1, V); + setArg(call_vssseg_945, 2, vssseg_945_arg1); + setArg(call_vssseg_945, 3, vssseg_945_arg2); + setArg(call_vssseg_945, 4, vssseg_945_arg3); + setArg(call_vssseg_945, 5, vm); + setArg(call_vssseg_945, 6, vs3); + setArg(call_vssseg_945, 7, vssseg_945_arg6); + setArg(call_vssseg_945, 8, 6); + setArg(call_vssseg_945, 9, 8); + setArg(call_vssseg_945, 10, vssseg_945_arg9); + setRet(call_vssseg_945, 0, ret_val_vssseg_945); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 329); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 330: VSSSEG8E64__V */ + continuation_e __vssseg8e64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vm}", fmt::arg("mnemonic", "vssseg8e64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSSEG8E64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 330); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_946; + x86::Gp ret_val_get_pow_946 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_946, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_947; + x86::Gp ret_val_get_sew_pow_947 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_947, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_948; + x86::Gp ret_val_get_lmul_pow_948 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_948, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_946, ret_val_get_sew_pow_947), ret_val_get_lmul_pow_948)), 3, true); + setArg(call_get_pow_946, 0, reinterpret_cast(this)); + setArg(call_get_pow_946, 1, EEW); + setRet(call_get_pow_946, 0, ret_val_get_pow_946); + setArg(call_get_sew_pow_947, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_947, 0, ret_val_get_sew_pow_947); + setArg(call_get_lmul_pow_948, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_948, 0, ret_val_get_lmul_pow_948); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_store_949; + auto illegal_store_949_arg2 = EMUL_pow; + x86::Gp ret_val_illegal_store_949 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_store_949, (uintptr_t)&vm_impl::_illegal_store, FuncSignature::build()); + auto cond = ret_val_illegal_store_949; + setArg(call_illegal_store_949, 0, reinterpret_cast(this)); + setArg(call_illegal_store_949, 1, 8); + setArg(call_illegal_store_949, 2, EEW); + setArg(call_illegal_store_949, 3, illegal_store_949_arg2); + setRet(call_illegal_store_949, 0, ret_val_illegal_store_949); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vssseg_950; + auto vssseg_950_arg1 = load_reg_from_mem(jh, traits::vl); + auto vssseg_950_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vssseg_950_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vssseg_950_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vssseg_950_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 64, true); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vssseg_950 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vssseg_950, &vssseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vssseg_950, 64, false), traits::vstart); + setArg(call_vssseg_950, 0, reinterpret_cast(this->get_arch())); + setArg(call_vssseg_950, 1, V); + setArg(call_vssseg_950, 2, vssseg_950_arg1); + setArg(call_vssseg_950, 3, vssseg_950_arg2); + setArg(call_vssseg_950, 4, vssseg_950_arg3); + setArg(call_vssseg_950, 5, vm); + setArg(call_vssseg_950, 6, vs3); + setArg(call_vssseg_950, 7, vssseg_950_arg6); + setArg(call_vssseg_950, 8, 7); + setArg(call_vssseg_950, 9, 8); + setArg(call_vssseg_950, 10, vssseg_950_arg9); + setRet(call_vssseg_950, 0, ret_val_vssseg_950); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 330); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 331: VLE8FF__V */ + continuation_e __vle8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 331); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_951; + x86::Gp ret_val_get_pow_951 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_951, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_952; + x86::Gp ret_val_get_sew_pow_952 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_952, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_953; + x86::Gp ret_val_get_lmul_pow_953 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_953, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_951, ret_val_get_sew_pow_952), ret_val_get_lmul_pow_953)), 3, true); + setArg(call_get_pow_951, 0, reinterpret_cast(this)); + setArg(call_get_pow_951, 1, EEW); + setRet(call_get_pow_951, 0, ret_val_get_pow_951); + setArg(call_get_sew_pow_952, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_952, 0, ret_val_get_sew_pow_952); + setArg(call_get_lmul_pow_953, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_953, 0, ret_val_get_lmul_pow_953); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_954; + auto illegal_load_954_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_954 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_954, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_954; + setArg(call_illegal_load_954, 0, reinterpret_cast(this)); + setArg(call_illegal_load_954, 1, vd); + setArg(call_illegal_load_954, 2, vm); + setArg(call_illegal_load_954, 3, 1); + setArg(call_illegal_load_954, 4, EEW); + setArg(call_illegal_load_954, 5, illegal_load_954_arg4); + setRet(call_illegal_load_954, 0, ret_val_illegal_load_954); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_955; + auto vlseg_955_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_955_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_955_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_955_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_955 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_955, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_955, 64, false); + setArg(call_vlseg_955, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_955, 1, V); + setArg(call_vlseg_955, 2, vlseg_955_arg1); + setArg(call_vlseg_955, 3, vlseg_955_arg2); + setArg(call_vlseg_955, 4, vlseg_955_arg3); + setArg(call_vlseg_955, 5, vm); + setArg(call_vlseg_955, 6, vd); + setArg(call_vlseg_955, 7, vlseg_955_arg6); + setArg(call_vlseg_955, 8, 0); + setArg(call_vlseg_955, 9, 1); + setRet(call_vlseg_955, 0, ret_val_vlseg_955); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 331); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 332: VLE16FF__V */ + continuation_e __vle16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 332); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_956; + x86::Gp ret_val_get_pow_956 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_956, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_957; + x86::Gp ret_val_get_sew_pow_957 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_957, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_958; + x86::Gp ret_val_get_lmul_pow_958 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_958, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_956, ret_val_get_sew_pow_957), ret_val_get_lmul_pow_958)), 3, true); + setArg(call_get_pow_956, 0, reinterpret_cast(this)); + setArg(call_get_pow_956, 1, EEW); + setRet(call_get_pow_956, 0, ret_val_get_pow_956); + setArg(call_get_sew_pow_957, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_957, 0, ret_val_get_sew_pow_957); + setArg(call_get_lmul_pow_958, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_958, 0, ret_val_get_lmul_pow_958); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_959; + auto illegal_load_959_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_959 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_959, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_959; + setArg(call_illegal_load_959, 0, reinterpret_cast(this)); + setArg(call_illegal_load_959, 1, vd); + setArg(call_illegal_load_959, 2, vm); + setArg(call_illegal_load_959, 3, 1); + setArg(call_illegal_load_959, 4, EEW); + setArg(call_illegal_load_959, 5, illegal_load_959_arg4); + setRet(call_illegal_load_959, 0, ret_val_illegal_load_959); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_960; + auto vlseg_960_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_960_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_960_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_960_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_960 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_960, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_960, 64, false); + setArg(call_vlseg_960, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_960, 1, V); + setArg(call_vlseg_960, 2, vlseg_960_arg1); + setArg(call_vlseg_960, 3, vlseg_960_arg2); + setArg(call_vlseg_960, 4, vlseg_960_arg3); + setArg(call_vlseg_960, 5, vm); + setArg(call_vlseg_960, 6, vd); + setArg(call_vlseg_960, 7, vlseg_960_arg6); + setArg(call_vlseg_960, 8, 5); + setArg(call_vlseg_960, 9, 1); + setRet(call_vlseg_960, 0, ret_val_vlseg_960); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 332); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 333: VLE32FF__V */ + continuation_e __vle32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 333); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_961; + x86::Gp ret_val_get_pow_961 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_961, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_962; + x86::Gp ret_val_get_sew_pow_962 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_962, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_963; + x86::Gp ret_val_get_lmul_pow_963 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_963, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_961, ret_val_get_sew_pow_962), ret_val_get_lmul_pow_963)), 3, true); + setArg(call_get_pow_961, 0, reinterpret_cast(this)); + setArg(call_get_pow_961, 1, EEW); + setRet(call_get_pow_961, 0, ret_val_get_pow_961); + setArg(call_get_sew_pow_962, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_962, 0, ret_val_get_sew_pow_962); + setArg(call_get_lmul_pow_963, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_963, 0, ret_val_get_lmul_pow_963); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_964; + auto illegal_load_964_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_964 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_964, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_964; + setArg(call_illegal_load_964, 0, reinterpret_cast(this)); + setArg(call_illegal_load_964, 1, vd); + setArg(call_illegal_load_964, 2, vm); + setArg(call_illegal_load_964, 3, 1); + setArg(call_illegal_load_964, 4, EEW); + setArg(call_illegal_load_964, 5, illegal_load_964_arg4); + setRet(call_illegal_load_964, 0, ret_val_illegal_load_964); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_965; + auto vlseg_965_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_965_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_965_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_965_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_965 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_965, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_965, 64, false); + setArg(call_vlseg_965, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_965, 1, V); + setArg(call_vlseg_965, 2, vlseg_965_arg1); + setArg(call_vlseg_965, 3, vlseg_965_arg2); + setArg(call_vlseg_965, 4, vlseg_965_arg3); + setArg(call_vlseg_965, 5, vm); + setArg(call_vlseg_965, 6, vd); + setArg(call_vlseg_965, 7, vlseg_965_arg6); + setArg(call_vlseg_965, 8, 6); + setArg(call_vlseg_965, 9, 1); + setRet(call_vlseg_965, 0, ret_val_vlseg_965); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 333); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 334: VLE64FF__V */ + continuation_e __vle64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vle64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLE64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 334); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_966; + x86::Gp ret_val_get_pow_966 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_966, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_967; + x86::Gp ret_val_get_sew_pow_967 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_967, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_968; + x86::Gp ret_val_get_lmul_pow_968 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_968, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_966, ret_val_get_sew_pow_967), ret_val_get_lmul_pow_968)), 3, true); + setArg(call_get_pow_966, 0, reinterpret_cast(this)); + setArg(call_get_pow_966, 1, EEW); + setRet(call_get_pow_966, 0, ret_val_get_pow_966); + setArg(call_get_sew_pow_967, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_967, 0, ret_val_get_sew_pow_967); + setArg(call_get_lmul_pow_968, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_968, 0, ret_val_get_lmul_pow_968); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_969; + auto illegal_load_969_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_969 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_969, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_969; + setArg(call_illegal_load_969, 0, reinterpret_cast(this)); + setArg(call_illegal_load_969, 1, vd); + setArg(call_illegal_load_969, 2, vm); + setArg(call_illegal_load_969, 3, 1); + setArg(call_illegal_load_969, 4, EEW); + setArg(call_illegal_load_969, 5, illegal_load_969_arg4); + setRet(call_illegal_load_969, 0, ret_val_illegal_load_969); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_970; + auto vlseg_970_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_970_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_970_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_970_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_970 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_970, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_970, 64, false); + setArg(call_vlseg_970, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_970, 1, V); + setArg(call_vlseg_970, 2, vlseg_970_arg1); + setArg(call_vlseg_970, 3, vlseg_970_arg2); + setArg(call_vlseg_970, 4, vlseg_970_arg3); + setArg(call_vlseg_970, 5, vm); + setArg(call_vlseg_970, 6, vd); + setArg(call_vlseg_970, 7, vlseg_970_arg6); + setArg(call_vlseg_970, 8, 7); + setArg(call_vlseg_970, 9, 1); + setRet(call_vlseg_970, 0, ret_val_vlseg_970); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 334); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 335: VLSEG2E8FF__V */ + continuation_e __vlseg2e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 335); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_971; + x86::Gp ret_val_get_pow_971 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_971, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_972; + x86::Gp ret_val_get_sew_pow_972 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_972, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_973; + x86::Gp ret_val_get_lmul_pow_973 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_973, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_971, ret_val_get_sew_pow_972), ret_val_get_lmul_pow_973)), 3, true); + setArg(call_get_pow_971, 0, reinterpret_cast(this)); + setArg(call_get_pow_971, 1, EEW); + setRet(call_get_pow_971, 0, ret_val_get_pow_971); + setArg(call_get_sew_pow_972, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_972, 0, ret_val_get_sew_pow_972); + setArg(call_get_lmul_pow_973, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_973, 0, ret_val_get_lmul_pow_973); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_974; + auto illegal_load_974_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_974 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_974, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_974; + setArg(call_illegal_load_974, 0, reinterpret_cast(this)); + setArg(call_illegal_load_974, 1, vd); + setArg(call_illegal_load_974, 2, vm); + setArg(call_illegal_load_974, 3, 2); + setArg(call_illegal_load_974, 4, EEW); + setArg(call_illegal_load_974, 5, illegal_load_974_arg4); + setRet(call_illegal_load_974, 0, ret_val_illegal_load_974); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_975; + auto vlseg_975_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_975_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_975_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_975_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_975 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_975, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_975, 64, false); + setArg(call_vlseg_975, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_975, 1, V); + setArg(call_vlseg_975, 2, vlseg_975_arg1); + setArg(call_vlseg_975, 3, vlseg_975_arg2); + setArg(call_vlseg_975, 4, vlseg_975_arg3); + setArg(call_vlseg_975, 5, vm); + setArg(call_vlseg_975, 6, vd); + setArg(call_vlseg_975, 7, vlseg_975_arg6); + setArg(call_vlseg_975, 8, 0); + setArg(call_vlseg_975, 9, 2); + setRet(call_vlseg_975, 0, ret_val_vlseg_975); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 335); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 336: VLSEG2E16FF__V */ + continuation_e __vlseg2e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 336); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_976; + x86::Gp ret_val_get_pow_976 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_976, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_977; + x86::Gp ret_val_get_sew_pow_977 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_977, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_978; + x86::Gp ret_val_get_lmul_pow_978 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_978, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_976, ret_val_get_sew_pow_977), ret_val_get_lmul_pow_978)), 3, true); + setArg(call_get_pow_976, 0, reinterpret_cast(this)); + setArg(call_get_pow_976, 1, EEW); + setRet(call_get_pow_976, 0, ret_val_get_pow_976); + setArg(call_get_sew_pow_977, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_977, 0, ret_val_get_sew_pow_977); + setArg(call_get_lmul_pow_978, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_978, 0, ret_val_get_lmul_pow_978); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_979; + auto illegal_load_979_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_979 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_979, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_979; + setArg(call_illegal_load_979, 0, reinterpret_cast(this)); + setArg(call_illegal_load_979, 1, vd); + setArg(call_illegal_load_979, 2, vm); + setArg(call_illegal_load_979, 3, 2); + setArg(call_illegal_load_979, 4, EEW); + setArg(call_illegal_load_979, 5, illegal_load_979_arg4); + setRet(call_illegal_load_979, 0, ret_val_illegal_load_979); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_980; + auto vlseg_980_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_980_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_980_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_980_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_980 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_980, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_980, 64, false); + setArg(call_vlseg_980, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_980, 1, V); + setArg(call_vlseg_980, 2, vlseg_980_arg1); + setArg(call_vlseg_980, 3, vlseg_980_arg2); + setArg(call_vlseg_980, 4, vlseg_980_arg3); + setArg(call_vlseg_980, 5, vm); + setArg(call_vlseg_980, 6, vd); + setArg(call_vlseg_980, 7, vlseg_980_arg6); + setArg(call_vlseg_980, 8, 5); + setArg(call_vlseg_980, 9, 2); + setRet(call_vlseg_980, 0, ret_val_vlseg_980); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 336); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 337: VLSEG2E32FF__V */ + continuation_e __vlseg2e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 337); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_981; + x86::Gp ret_val_get_pow_981 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_981, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_982; + x86::Gp ret_val_get_sew_pow_982 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_982, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_983; + x86::Gp ret_val_get_lmul_pow_983 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_983, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_981, ret_val_get_sew_pow_982), ret_val_get_lmul_pow_983)), 3, true); + setArg(call_get_pow_981, 0, reinterpret_cast(this)); + setArg(call_get_pow_981, 1, EEW); + setRet(call_get_pow_981, 0, ret_val_get_pow_981); + setArg(call_get_sew_pow_982, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_982, 0, ret_val_get_sew_pow_982); + setArg(call_get_lmul_pow_983, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_983, 0, ret_val_get_lmul_pow_983); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_984; + auto illegal_load_984_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_984 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_984, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_984; + setArg(call_illegal_load_984, 0, reinterpret_cast(this)); + setArg(call_illegal_load_984, 1, vd); + setArg(call_illegal_load_984, 2, vm); + setArg(call_illegal_load_984, 3, 2); + setArg(call_illegal_load_984, 4, EEW); + setArg(call_illegal_load_984, 5, illegal_load_984_arg4); + setRet(call_illegal_load_984, 0, ret_val_illegal_load_984); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_985; + auto vlseg_985_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_985_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_985_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_985_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_985 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_985, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_985, 64, false); + setArg(call_vlseg_985, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_985, 1, V); + setArg(call_vlseg_985, 2, vlseg_985_arg1); + setArg(call_vlseg_985, 3, vlseg_985_arg2); + setArg(call_vlseg_985, 4, vlseg_985_arg3); + setArg(call_vlseg_985, 5, vm); + setArg(call_vlseg_985, 6, vd); + setArg(call_vlseg_985, 7, vlseg_985_arg6); + setArg(call_vlseg_985, 8, 6); + setArg(call_vlseg_985, 9, 2); + setRet(call_vlseg_985, 0, ret_val_vlseg_985); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 337); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 338: VLSEG2E64FF__V */ + continuation_e __vlseg2e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg2e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG2E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 338); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_986; + x86::Gp ret_val_get_pow_986 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_986, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_987; + x86::Gp ret_val_get_sew_pow_987 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_987, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_988; + x86::Gp ret_val_get_lmul_pow_988 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_988, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_986, ret_val_get_sew_pow_987), ret_val_get_lmul_pow_988)), 3, true); + setArg(call_get_pow_986, 0, reinterpret_cast(this)); + setArg(call_get_pow_986, 1, EEW); + setRet(call_get_pow_986, 0, ret_val_get_pow_986); + setArg(call_get_sew_pow_987, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_987, 0, ret_val_get_sew_pow_987); + setArg(call_get_lmul_pow_988, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_988, 0, ret_val_get_lmul_pow_988); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_989; + auto illegal_load_989_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_989 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_989, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_989; + setArg(call_illegal_load_989, 0, reinterpret_cast(this)); + setArg(call_illegal_load_989, 1, vd); + setArg(call_illegal_load_989, 2, vm); + setArg(call_illegal_load_989, 3, 2); + setArg(call_illegal_load_989, 4, EEW); + setArg(call_illegal_load_989, 5, illegal_load_989_arg4); + setRet(call_illegal_load_989, 0, ret_val_illegal_load_989); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_990; + auto vlseg_990_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_990_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_990_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_990_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_990 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_990, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_990, 64, false); + setArg(call_vlseg_990, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_990, 1, V); + setArg(call_vlseg_990, 2, vlseg_990_arg1); + setArg(call_vlseg_990, 3, vlseg_990_arg2); + setArg(call_vlseg_990, 4, vlseg_990_arg3); + setArg(call_vlseg_990, 5, vm); + setArg(call_vlseg_990, 6, vd); + setArg(call_vlseg_990, 7, vlseg_990_arg6); + setArg(call_vlseg_990, 8, 7); + setArg(call_vlseg_990, 9, 2); + setRet(call_vlseg_990, 0, ret_val_vlseg_990); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 338); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 339: VLSEG3E8FF__V */ + continuation_e __vlseg3e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 339); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_991; + x86::Gp ret_val_get_pow_991 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_991, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_992; + x86::Gp ret_val_get_sew_pow_992 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_992, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_993; + x86::Gp ret_val_get_lmul_pow_993 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_993, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_991, ret_val_get_sew_pow_992), ret_val_get_lmul_pow_993)), 3, true); + setArg(call_get_pow_991, 0, reinterpret_cast(this)); + setArg(call_get_pow_991, 1, EEW); + setRet(call_get_pow_991, 0, ret_val_get_pow_991); + setArg(call_get_sew_pow_992, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_992, 0, ret_val_get_sew_pow_992); + setArg(call_get_lmul_pow_993, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_993, 0, ret_val_get_lmul_pow_993); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_994; + auto illegal_load_994_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_994 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_994, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_994; + setArg(call_illegal_load_994, 0, reinterpret_cast(this)); + setArg(call_illegal_load_994, 1, vd); + setArg(call_illegal_load_994, 2, vm); + setArg(call_illegal_load_994, 3, 3); + setArg(call_illegal_load_994, 4, EEW); + setArg(call_illegal_load_994, 5, illegal_load_994_arg4); + setRet(call_illegal_load_994, 0, ret_val_illegal_load_994); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_995; + auto vlseg_995_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_995_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_995_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_995_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_995 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_995, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_995, 64, false); + setArg(call_vlseg_995, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_995, 1, V); + setArg(call_vlseg_995, 2, vlseg_995_arg1); + setArg(call_vlseg_995, 3, vlseg_995_arg2); + setArg(call_vlseg_995, 4, vlseg_995_arg3); + setArg(call_vlseg_995, 5, vm); + setArg(call_vlseg_995, 6, vd); + setArg(call_vlseg_995, 7, vlseg_995_arg6); + setArg(call_vlseg_995, 8, 0); + setArg(call_vlseg_995, 9, 3); + setRet(call_vlseg_995, 0, ret_val_vlseg_995); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 339); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 340: VLSEG3E16FF__V */ + continuation_e __vlseg3e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 340); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_996; + x86::Gp ret_val_get_pow_996 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_996, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_997; + x86::Gp ret_val_get_sew_pow_997 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_997, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_998; + x86::Gp ret_val_get_lmul_pow_998 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_998, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_996, ret_val_get_sew_pow_997), ret_val_get_lmul_pow_998)), 3, true); + setArg(call_get_pow_996, 0, reinterpret_cast(this)); + setArg(call_get_pow_996, 1, EEW); + setRet(call_get_pow_996, 0, ret_val_get_pow_996); + setArg(call_get_sew_pow_997, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_997, 0, ret_val_get_sew_pow_997); + setArg(call_get_lmul_pow_998, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_998, 0, ret_val_get_lmul_pow_998); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_999; + auto illegal_load_999_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_999 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_999, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_999; + setArg(call_illegal_load_999, 0, reinterpret_cast(this)); + setArg(call_illegal_load_999, 1, vd); + setArg(call_illegal_load_999, 2, vm); + setArg(call_illegal_load_999, 3, 3); + setArg(call_illegal_load_999, 4, EEW); + setArg(call_illegal_load_999, 5, illegal_load_999_arg4); + setRet(call_illegal_load_999, 0, ret_val_illegal_load_999); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1000; + auto vlseg_1000_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1000_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1000_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1000_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1000 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1000, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1000, 64, false); + setArg(call_vlseg_1000, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1000, 1, V); + setArg(call_vlseg_1000, 2, vlseg_1000_arg1); + setArg(call_vlseg_1000, 3, vlseg_1000_arg2); + setArg(call_vlseg_1000, 4, vlseg_1000_arg3); + setArg(call_vlseg_1000, 5, vm); + setArg(call_vlseg_1000, 6, vd); + setArg(call_vlseg_1000, 7, vlseg_1000_arg6); + setArg(call_vlseg_1000, 8, 5); + setArg(call_vlseg_1000, 9, 3); + setRet(call_vlseg_1000, 0, ret_val_vlseg_1000); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 340); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 341: VLSEG3E32FF__V */ + continuation_e __vlseg3e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 341); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1001; + x86::Gp ret_val_get_pow_1001 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1001, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1002; + x86::Gp ret_val_get_sew_pow_1002 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1002, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1003; + x86::Gp ret_val_get_lmul_pow_1003 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1003, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1001, ret_val_get_sew_pow_1002), ret_val_get_lmul_pow_1003)), 3, true); + setArg(call_get_pow_1001, 0, reinterpret_cast(this)); + setArg(call_get_pow_1001, 1, EEW); + setRet(call_get_pow_1001, 0, ret_val_get_pow_1001); + setArg(call_get_sew_pow_1002, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1002, 0, ret_val_get_sew_pow_1002); + setArg(call_get_lmul_pow_1003, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1003, 0, ret_val_get_lmul_pow_1003); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1004; + auto illegal_load_1004_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1004 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1004, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1004; + setArg(call_illegal_load_1004, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1004, 1, vd); + setArg(call_illegal_load_1004, 2, vm); + setArg(call_illegal_load_1004, 3, 3); + setArg(call_illegal_load_1004, 4, EEW); + setArg(call_illegal_load_1004, 5, illegal_load_1004_arg4); + setRet(call_illegal_load_1004, 0, ret_val_illegal_load_1004); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1005; + auto vlseg_1005_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1005_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1005_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1005_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1005 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1005, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1005, 64, false); + setArg(call_vlseg_1005, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1005, 1, V); + setArg(call_vlseg_1005, 2, vlseg_1005_arg1); + setArg(call_vlseg_1005, 3, vlseg_1005_arg2); + setArg(call_vlseg_1005, 4, vlseg_1005_arg3); + setArg(call_vlseg_1005, 5, vm); + setArg(call_vlseg_1005, 6, vd); + setArg(call_vlseg_1005, 7, vlseg_1005_arg6); + setArg(call_vlseg_1005, 8, 6); + setArg(call_vlseg_1005, 9, 3); + setRet(call_vlseg_1005, 0, ret_val_vlseg_1005); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 341); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 342: VLSEG3E64FF__V */ + continuation_e __vlseg3e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg3e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG3E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 342); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1006; + x86::Gp ret_val_get_pow_1006 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1006, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1007; + x86::Gp ret_val_get_sew_pow_1007 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1007, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1008; + x86::Gp ret_val_get_lmul_pow_1008 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1008, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1006, ret_val_get_sew_pow_1007), ret_val_get_lmul_pow_1008)), 3, true); + setArg(call_get_pow_1006, 0, reinterpret_cast(this)); + setArg(call_get_pow_1006, 1, EEW); + setRet(call_get_pow_1006, 0, ret_val_get_pow_1006); + setArg(call_get_sew_pow_1007, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1007, 0, ret_val_get_sew_pow_1007); + setArg(call_get_lmul_pow_1008, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1008, 0, ret_val_get_lmul_pow_1008); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1009; + auto illegal_load_1009_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1009 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1009, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1009; + setArg(call_illegal_load_1009, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1009, 1, vd); + setArg(call_illegal_load_1009, 2, vm); + setArg(call_illegal_load_1009, 3, 3); + setArg(call_illegal_load_1009, 4, EEW); + setArg(call_illegal_load_1009, 5, illegal_load_1009_arg4); + setRet(call_illegal_load_1009, 0, ret_val_illegal_load_1009); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1010; + auto vlseg_1010_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1010_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1010_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1010_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1010 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1010, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1010, 64, false); + setArg(call_vlseg_1010, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1010, 1, V); + setArg(call_vlseg_1010, 2, vlseg_1010_arg1); + setArg(call_vlseg_1010, 3, vlseg_1010_arg2); + setArg(call_vlseg_1010, 4, vlseg_1010_arg3); + setArg(call_vlseg_1010, 5, vm); + setArg(call_vlseg_1010, 6, vd); + setArg(call_vlseg_1010, 7, vlseg_1010_arg6); + setArg(call_vlseg_1010, 8, 7); + setArg(call_vlseg_1010, 9, 3); + setRet(call_vlseg_1010, 0, ret_val_vlseg_1010); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 342); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 343: VLSEG4E8FF__V */ + continuation_e __vlseg4e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 343); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1011; + x86::Gp ret_val_get_pow_1011 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1011, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1012; + x86::Gp ret_val_get_sew_pow_1012 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1012, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1013; + x86::Gp ret_val_get_lmul_pow_1013 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1013, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1011, ret_val_get_sew_pow_1012), ret_val_get_lmul_pow_1013)), 3, true); + setArg(call_get_pow_1011, 0, reinterpret_cast(this)); + setArg(call_get_pow_1011, 1, EEW); + setRet(call_get_pow_1011, 0, ret_val_get_pow_1011); + setArg(call_get_sew_pow_1012, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1012, 0, ret_val_get_sew_pow_1012); + setArg(call_get_lmul_pow_1013, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1013, 0, ret_val_get_lmul_pow_1013); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1014; + auto illegal_load_1014_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1014 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1014, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1014; + setArg(call_illegal_load_1014, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1014, 1, vd); + setArg(call_illegal_load_1014, 2, vm); + setArg(call_illegal_load_1014, 3, 4); + setArg(call_illegal_load_1014, 4, EEW); + setArg(call_illegal_load_1014, 5, illegal_load_1014_arg4); + setRet(call_illegal_load_1014, 0, ret_val_illegal_load_1014); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1015; + auto vlseg_1015_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1015_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1015_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1015_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1015 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1015, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1015, 64, false); + setArg(call_vlseg_1015, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1015, 1, V); + setArg(call_vlseg_1015, 2, vlseg_1015_arg1); + setArg(call_vlseg_1015, 3, vlseg_1015_arg2); + setArg(call_vlseg_1015, 4, vlseg_1015_arg3); + setArg(call_vlseg_1015, 5, vm); + setArg(call_vlseg_1015, 6, vd); + setArg(call_vlseg_1015, 7, vlseg_1015_arg6); + setArg(call_vlseg_1015, 8, 0); + setArg(call_vlseg_1015, 9, 4); + setRet(call_vlseg_1015, 0, ret_val_vlseg_1015); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 343); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 344: VLSEG4E16FF__V */ + continuation_e __vlseg4e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 344); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1016; + x86::Gp ret_val_get_pow_1016 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1016, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1017; + x86::Gp ret_val_get_sew_pow_1017 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1017, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1018; + x86::Gp ret_val_get_lmul_pow_1018 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1018, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1016, ret_val_get_sew_pow_1017), ret_val_get_lmul_pow_1018)), 3, true); + setArg(call_get_pow_1016, 0, reinterpret_cast(this)); + setArg(call_get_pow_1016, 1, EEW); + setRet(call_get_pow_1016, 0, ret_val_get_pow_1016); + setArg(call_get_sew_pow_1017, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1017, 0, ret_val_get_sew_pow_1017); + setArg(call_get_lmul_pow_1018, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1018, 0, ret_val_get_lmul_pow_1018); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1019; + auto illegal_load_1019_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1019 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1019, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1019; + setArg(call_illegal_load_1019, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1019, 1, vd); + setArg(call_illegal_load_1019, 2, vm); + setArg(call_illegal_load_1019, 3, 4); + setArg(call_illegal_load_1019, 4, EEW); + setArg(call_illegal_load_1019, 5, illegal_load_1019_arg4); + setRet(call_illegal_load_1019, 0, ret_val_illegal_load_1019); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1020; + auto vlseg_1020_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1020_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1020_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1020_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1020 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1020, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1020, 64, false); + setArg(call_vlseg_1020, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1020, 1, V); + setArg(call_vlseg_1020, 2, vlseg_1020_arg1); + setArg(call_vlseg_1020, 3, vlseg_1020_arg2); + setArg(call_vlseg_1020, 4, vlseg_1020_arg3); + setArg(call_vlseg_1020, 5, vm); + setArg(call_vlseg_1020, 6, vd); + setArg(call_vlseg_1020, 7, vlseg_1020_arg6); + setArg(call_vlseg_1020, 8, 5); + setArg(call_vlseg_1020, 9, 4); + setRet(call_vlseg_1020, 0, ret_val_vlseg_1020); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 344); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 345: VLSEG4E32FF__V */ + continuation_e __vlseg4e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 345); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1021; + x86::Gp ret_val_get_pow_1021 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1021, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1022; + x86::Gp ret_val_get_sew_pow_1022 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1022, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1023; + x86::Gp ret_val_get_lmul_pow_1023 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1023, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1021, ret_val_get_sew_pow_1022), ret_val_get_lmul_pow_1023)), 3, true); + setArg(call_get_pow_1021, 0, reinterpret_cast(this)); + setArg(call_get_pow_1021, 1, EEW); + setRet(call_get_pow_1021, 0, ret_val_get_pow_1021); + setArg(call_get_sew_pow_1022, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1022, 0, ret_val_get_sew_pow_1022); + setArg(call_get_lmul_pow_1023, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1023, 0, ret_val_get_lmul_pow_1023); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1024; + auto illegal_load_1024_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1024 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1024, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1024; + setArg(call_illegal_load_1024, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1024, 1, vd); + setArg(call_illegal_load_1024, 2, vm); + setArg(call_illegal_load_1024, 3, 4); + setArg(call_illegal_load_1024, 4, EEW); + setArg(call_illegal_load_1024, 5, illegal_load_1024_arg4); + setRet(call_illegal_load_1024, 0, ret_val_illegal_load_1024); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1025; + auto vlseg_1025_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1025_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1025_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1025_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1025 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1025, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1025, 64, false); + setArg(call_vlseg_1025, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1025, 1, V); + setArg(call_vlseg_1025, 2, vlseg_1025_arg1); + setArg(call_vlseg_1025, 3, vlseg_1025_arg2); + setArg(call_vlseg_1025, 4, vlseg_1025_arg3); + setArg(call_vlseg_1025, 5, vm); + setArg(call_vlseg_1025, 6, vd); + setArg(call_vlseg_1025, 7, vlseg_1025_arg6); + setArg(call_vlseg_1025, 8, 6); + setArg(call_vlseg_1025, 9, 4); + setRet(call_vlseg_1025, 0, ret_val_vlseg_1025); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 345); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 346: VLSEG4E64FF__V */ + continuation_e __vlseg4e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg4e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG4E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 346); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1026; + x86::Gp ret_val_get_pow_1026 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1026, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1027; + x86::Gp ret_val_get_sew_pow_1027 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1027, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1028; + x86::Gp ret_val_get_lmul_pow_1028 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1028, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1026, ret_val_get_sew_pow_1027), ret_val_get_lmul_pow_1028)), 3, true); + setArg(call_get_pow_1026, 0, reinterpret_cast(this)); + setArg(call_get_pow_1026, 1, EEW); + setRet(call_get_pow_1026, 0, ret_val_get_pow_1026); + setArg(call_get_sew_pow_1027, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1027, 0, ret_val_get_sew_pow_1027); + setArg(call_get_lmul_pow_1028, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1028, 0, ret_val_get_lmul_pow_1028); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1029; + auto illegal_load_1029_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1029 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1029, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1029; + setArg(call_illegal_load_1029, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1029, 1, vd); + setArg(call_illegal_load_1029, 2, vm); + setArg(call_illegal_load_1029, 3, 4); + setArg(call_illegal_load_1029, 4, EEW); + setArg(call_illegal_load_1029, 5, illegal_load_1029_arg4); + setRet(call_illegal_load_1029, 0, ret_val_illegal_load_1029); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1030; + auto vlseg_1030_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1030_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1030_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1030_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1030 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1030, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1030, 64, false); + setArg(call_vlseg_1030, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1030, 1, V); + setArg(call_vlseg_1030, 2, vlseg_1030_arg1); + setArg(call_vlseg_1030, 3, vlseg_1030_arg2); + setArg(call_vlseg_1030, 4, vlseg_1030_arg3); + setArg(call_vlseg_1030, 5, vm); + setArg(call_vlseg_1030, 6, vd); + setArg(call_vlseg_1030, 7, vlseg_1030_arg6); + setArg(call_vlseg_1030, 8, 7); + setArg(call_vlseg_1030, 9, 4); + setRet(call_vlseg_1030, 0, ret_val_vlseg_1030); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 346); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 347: VLSEG5E8FF__V */ + continuation_e __vlseg5e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 347); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1031; + x86::Gp ret_val_get_pow_1031 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1031, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1032; + x86::Gp ret_val_get_sew_pow_1032 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1032, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1033; + x86::Gp ret_val_get_lmul_pow_1033 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1033, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1031, ret_val_get_sew_pow_1032), ret_val_get_lmul_pow_1033)), 3, true); + setArg(call_get_pow_1031, 0, reinterpret_cast(this)); + setArg(call_get_pow_1031, 1, EEW); + setRet(call_get_pow_1031, 0, ret_val_get_pow_1031); + setArg(call_get_sew_pow_1032, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1032, 0, ret_val_get_sew_pow_1032); + setArg(call_get_lmul_pow_1033, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1033, 0, ret_val_get_lmul_pow_1033); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1034; + auto illegal_load_1034_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1034 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1034, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1034; + setArg(call_illegal_load_1034, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1034, 1, vd); + setArg(call_illegal_load_1034, 2, vm); + setArg(call_illegal_load_1034, 3, 5); + setArg(call_illegal_load_1034, 4, EEW); + setArg(call_illegal_load_1034, 5, illegal_load_1034_arg4); + setRet(call_illegal_load_1034, 0, ret_val_illegal_load_1034); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1035; + auto vlseg_1035_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1035_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1035_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1035_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1035 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1035, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1035, 64, false); + setArg(call_vlseg_1035, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1035, 1, V); + setArg(call_vlseg_1035, 2, vlseg_1035_arg1); + setArg(call_vlseg_1035, 3, vlseg_1035_arg2); + setArg(call_vlseg_1035, 4, vlseg_1035_arg3); + setArg(call_vlseg_1035, 5, vm); + setArg(call_vlseg_1035, 6, vd); + setArg(call_vlseg_1035, 7, vlseg_1035_arg6); + setArg(call_vlseg_1035, 8, 0); + setArg(call_vlseg_1035, 9, 5); + setRet(call_vlseg_1035, 0, ret_val_vlseg_1035); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 347); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 348: VLSEG5E16FF__V */ + continuation_e __vlseg5e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 348); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1036; + x86::Gp ret_val_get_pow_1036 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1036, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1037; + x86::Gp ret_val_get_sew_pow_1037 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1037, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1038; + x86::Gp ret_val_get_lmul_pow_1038 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1038, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1036, ret_val_get_sew_pow_1037), ret_val_get_lmul_pow_1038)), 3, true); + setArg(call_get_pow_1036, 0, reinterpret_cast(this)); + setArg(call_get_pow_1036, 1, EEW); + setRet(call_get_pow_1036, 0, ret_val_get_pow_1036); + setArg(call_get_sew_pow_1037, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1037, 0, ret_val_get_sew_pow_1037); + setArg(call_get_lmul_pow_1038, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1038, 0, ret_val_get_lmul_pow_1038); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1039; + auto illegal_load_1039_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1039 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1039, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1039; + setArg(call_illegal_load_1039, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1039, 1, vd); + setArg(call_illegal_load_1039, 2, vm); + setArg(call_illegal_load_1039, 3, 5); + setArg(call_illegal_load_1039, 4, EEW); + setArg(call_illegal_load_1039, 5, illegal_load_1039_arg4); + setRet(call_illegal_load_1039, 0, ret_val_illegal_load_1039); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1040; + auto vlseg_1040_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1040_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1040_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1040_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1040 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1040, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1040, 64, false); + setArg(call_vlseg_1040, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1040, 1, V); + setArg(call_vlseg_1040, 2, vlseg_1040_arg1); + setArg(call_vlseg_1040, 3, vlseg_1040_arg2); + setArg(call_vlseg_1040, 4, vlseg_1040_arg3); + setArg(call_vlseg_1040, 5, vm); + setArg(call_vlseg_1040, 6, vd); + setArg(call_vlseg_1040, 7, vlseg_1040_arg6); + setArg(call_vlseg_1040, 8, 5); + setArg(call_vlseg_1040, 9, 5); + setRet(call_vlseg_1040, 0, ret_val_vlseg_1040); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 348); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 349: VLSEG5E32FF__V */ + continuation_e __vlseg5e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 349); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1041; + x86::Gp ret_val_get_pow_1041 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1041, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1042; + x86::Gp ret_val_get_sew_pow_1042 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1042, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1043; + x86::Gp ret_val_get_lmul_pow_1043 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1043, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1041, ret_val_get_sew_pow_1042), ret_val_get_lmul_pow_1043)), 3, true); + setArg(call_get_pow_1041, 0, reinterpret_cast(this)); + setArg(call_get_pow_1041, 1, EEW); + setRet(call_get_pow_1041, 0, ret_val_get_pow_1041); + setArg(call_get_sew_pow_1042, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1042, 0, ret_val_get_sew_pow_1042); + setArg(call_get_lmul_pow_1043, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1043, 0, ret_val_get_lmul_pow_1043); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1044; + auto illegal_load_1044_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1044 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1044, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1044; + setArg(call_illegal_load_1044, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1044, 1, vd); + setArg(call_illegal_load_1044, 2, vm); + setArg(call_illegal_load_1044, 3, 5); + setArg(call_illegal_load_1044, 4, EEW); + setArg(call_illegal_load_1044, 5, illegal_load_1044_arg4); + setRet(call_illegal_load_1044, 0, ret_val_illegal_load_1044); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1045; + auto vlseg_1045_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1045_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1045_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1045_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1045 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1045, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1045, 64, false); + setArg(call_vlseg_1045, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1045, 1, V); + setArg(call_vlseg_1045, 2, vlseg_1045_arg1); + setArg(call_vlseg_1045, 3, vlseg_1045_arg2); + setArg(call_vlseg_1045, 4, vlseg_1045_arg3); + setArg(call_vlseg_1045, 5, vm); + setArg(call_vlseg_1045, 6, vd); + setArg(call_vlseg_1045, 7, vlseg_1045_arg6); + setArg(call_vlseg_1045, 8, 6); + setArg(call_vlseg_1045, 9, 5); + setRet(call_vlseg_1045, 0, ret_val_vlseg_1045); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 349); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 350: VLSEG5E64FF__V */ + continuation_e __vlseg5e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg5e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG5E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 350); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1046; + x86::Gp ret_val_get_pow_1046 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1046, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1047; + x86::Gp ret_val_get_sew_pow_1047 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1047, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1048; + x86::Gp ret_val_get_lmul_pow_1048 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1048, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1046, ret_val_get_sew_pow_1047), ret_val_get_lmul_pow_1048)), 3, true); + setArg(call_get_pow_1046, 0, reinterpret_cast(this)); + setArg(call_get_pow_1046, 1, EEW); + setRet(call_get_pow_1046, 0, ret_val_get_pow_1046); + setArg(call_get_sew_pow_1047, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1047, 0, ret_val_get_sew_pow_1047); + setArg(call_get_lmul_pow_1048, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1048, 0, ret_val_get_lmul_pow_1048); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1049; + auto illegal_load_1049_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1049 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1049, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1049; + setArg(call_illegal_load_1049, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1049, 1, vd); + setArg(call_illegal_load_1049, 2, vm); + setArg(call_illegal_load_1049, 3, 5); + setArg(call_illegal_load_1049, 4, EEW); + setArg(call_illegal_load_1049, 5, illegal_load_1049_arg4); + setRet(call_illegal_load_1049, 0, ret_val_illegal_load_1049); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1050; + auto vlseg_1050_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1050_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1050_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1050_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1050 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1050, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1050, 64, false); + setArg(call_vlseg_1050, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1050, 1, V); + setArg(call_vlseg_1050, 2, vlseg_1050_arg1); + setArg(call_vlseg_1050, 3, vlseg_1050_arg2); + setArg(call_vlseg_1050, 4, vlseg_1050_arg3); + setArg(call_vlseg_1050, 5, vm); + setArg(call_vlseg_1050, 6, vd); + setArg(call_vlseg_1050, 7, vlseg_1050_arg6); + setArg(call_vlseg_1050, 8, 7); + setArg(call_vlseg_1050, 9, 5); + setRet(call_vlseg_1050, 0, ret_val_vlseg_1050); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 350); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 351: VLSEG6E8FF__V */ + continuation_e __vlseg6e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 351); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1051; + x86::Gp ret_val_get_pow_1051 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1051, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1052; + x86::Gp ret_val_get_sew_pow_1052 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1052, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1053; + x86::Gp ret_val_get_lmul_pow_1053 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1053, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1051, ret_val_get_sew_pow_1052), ret_val_get_lmul_pow_1053)), 3, true); + setArg(call_get_pow_1051, 0, reinterpret_cast(this)); + setArg(call_get_pow_1051, 1, EEW); + setRet(call_get_pow_1051, 0, ret_val_get_pow_1051); + setArg(call_get_sew_pow_1052, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1052, 0, ret_val_get_sew_pow_1052); + setArg(call_get_lmul_pow_1053, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1053, 0, ret_val_get_lmul_pow_1053); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1054; + auto illegal_load_1054_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1054 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1054, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1054; + setArg(call_illegal_load_1054, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1054, 1, vd); + setArg(call_illegal_load_1054, 2, vm); + setArg(call_illegal_load_1054, 3, 6); + setArg(call_illegal_load_1054, 4, EEW); + setArg(call_illegal_load_1054, 5, illegal_load_1054_arg4); + setRet(call_illegal_load_1054, 0, ret_val_illegal_load_1054); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1055; + auto vlseg_1055_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1055_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1055_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1055_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1055 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1055, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1055, 64, false); + setArg(call_vlseg_1055, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1055, 1, V); + setArg(call_vlseg_1055, 2, vlseg_1055_arg1); + setArg(call_vlseg_1055, 3, vlseg_1055_arg2); + setArg(call_vlseg_1055, 4, vlseg_1055_arg3); + setArg(call_vlseg_1055, 5, vm); + setArg(call_vlseg_1055, 6, vd); + setArg(call_vlseg_1055, 7, vlseg_1055_arg6); + setArg(call_vlseg_1055, 8, 0); + setArg(call_vlseg_1055, 9, 6); + setRet(call_vlseg_1055, 0, ret_val_vlseg_1055); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 351); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 352: VLSEG6E16FF__V */ + continuation_e __vlseg6e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 352); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1056; + x86::Gp ret_val_get_pow_1056 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1056, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1057; + x86::Gp ret_val_get_sew_pow_1057 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1057, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1058; + x86::Gp ret_val_get_lmul_pow_1058 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1058, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1056, ret_val_get_sew_pow_1057), ret_val_get_lmul_pow_1058)), 3, true); + setArg(call_get_pow_1056, 0, reinterpret_cast(this)); + setArg(call_get_pow_1056, 1, EEW); + setRet(call_get_pow_1056, 0, ret_val_get_pow_1056); + setArg(call_get_sew_pow_1057, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1057, 0, ret_val_get_sew_pow_1057); + setArg(call_get_lmul_pow_1058, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1058, 0, ret_val_get_lmul_pow_1058); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1059; + auto illegal_load_1059_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1059 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1059, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1059; + setArg(call_illegal_load_1059, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1059, 1, vd); + setArg(call_illegal_load_1059, 2, vm); + setArg(call_illegal_load_1059, 3, 6); + setArg(call_illegal_load_1059, 4, EEW); + setArg(call_illegal_load_1059, 5, illegal_load_1059_arg4); + setRet(call_illegal_load_1059, 0, ret_val_illegal_load_1059); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1060; + auto vlseg_1060_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1060_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1060_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1060_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1060 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1060, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1060, 64, false); + setArg(call_vlseg_1060, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1060, 1, V); + setArg(call_vlseg_1060, 2, vlseg_1060_arg1); + setArg(call_vlseg_1060, 3, vlseg_1060_arg2); + setArg(call_vlseg_1060, 4, vlseg_1060_arg3); + setArg(call_vlseg_1060, 5, vm); + setArg(call_vlseg_1060, 6, vd); + setArg(call_vlseg_1060, 7, vlseg_1060_arg6); + setArg(call_vlseg_1060, 8, 5); + setArg(call_vlseg_1060, 9, 6); + setRet(call_vlseg_1060, 0, ret_val_vlseg_1060); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 352); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 353: VLSEG6E32FF__V */ + continuation_e __vlseg6e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 353); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1061; + x86::Gp ret_val_get_pow_1061 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1061, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1062; + x86::Gp ret_val_get_sew_pow_1062 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1062, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1063; + x86::Gp ret_val_get_lmul_pow_1063 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1063, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1061, ret_val_get_sew_pow_1062), ret_val_get_lmul_pow_1063)), 3, true); + setArg(call_get_pow_1061, 0, reinterpret_cast(this)); + setArg(call_get_pow_1061, 1, EEW); + setRet(call_get_pow_1061, 0, ret_val_get_pow_1061); + setArg(call_get_sew_pow_1062, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1062, 0, ret_val_get_sew_pow_1062); + setArg(call_get_lmul_pow_1063, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1063, 0, ret_val_get_lmul_pow_1063); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1064; + auto illegal_load_1064_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1064 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1064, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1064; + setArg(call_illegal_load_1064, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1064, 1, vd); + setArg(call_illegal_load_1064, 2, vm); + setArg(call_illegal_load_1064, 3, 6); + setArg(call_illegal_load_1064, 4, EEW); + setArg(call_illegal_load_1064, 5, illegal_load_1064_arg4); + setRet(call_illegal_load_1064, 0, ret_val_illegal_load_1064); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1065; + auto vlseg_1065_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1065_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1065_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1065_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1065 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1065, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1065, 64, false); + setArg(call_vlseg_1065, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1065, 1, V); + setArg(call_vlseg_1065, 2, vlseg_1065_arg1); + setArg(call_vlseg_1065, 3, vlseg_1065_arg2); + setArg(call_vlseg_1065, 4, vlseg_1065_arg3); + setArg(call_vlseg_1065, 5, vm); + setArg(call_vlseg_1065, 6, vd); + setArg(call_vlseg_1065, 7, vlseg_1065_arg6); + setArg(call_vlseg_1065, 8, 6); + setArg(call_vlseg_1065, 9, 6); + setRet(call_vlseg_1065, 0, ret_val_vlseg_1065); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 353); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 354: VLSEG6E64FF__V */ + continuation_e __vlseg6e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg6e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG6E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 354); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1066; + x86::Gp ret_val_get_pow_1066 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1066, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1067; + x86::Gp ret_val_get_sew_pow_1067 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1067, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1068; + x86::Gp ret_val_get_lmul_pow_1068 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1068, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1066, ret_val_get_sew_pow_1067), ret_val_get_lmul_pow_1068)), 3, true); + setArg(call_get_pow_1066, 0, reinterpret_cast(this)); + setArg(call_get_pow_1066, 1, EEW); + setRet(call_get_pow_1066, 0, ret_val_get_pow_1066); + setArg(call_get_sew_pow_1067, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1067, 0, ret_val_get_sew_pow_1067); + setArg(call_get_lmul_pow_1068, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1068, 0, ret_val_get_lmul_pow_1068); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1069; + auto illegal_load_1069_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1069 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1069, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1069; + setArg(call_illegal_load_1069, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1069, 1, vd); + setArg(call_illegal_load_1069, 2, vm); + setArg(call_illegal_load_1069, 3, 6); + setArg(call_illegal_load_1069, 4, EEW); + setArg(call_illegal_load_1069, 5, illegal_load_1069_arg4); + setRet(call_illegal_load_1069, 0, ret_val_illegal_load_1069); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1070; + auto vlseg_1070_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1070_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1070_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1070_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1070 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1070, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1070, 64, false); + setArg(call_vlseg_1070, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1070, 1, V); + setArg(call_vlseg_1070, 2, vlseg_1070_arg1); + setArg(call_vlseg_1070, 3, vlseg_1070_arg2); + setArg(call_vlseg_1070, 4, vlseg_1070_arg3); + setArg(call_vlseg_1070, 5, vm); + setArg(call_vlseg_1070, 6, vd); + setArg(call_vlseg_1070, 7, vlseg_1070_arg6); + setArg(call_vlseg_1070, 8, 7); + setArg(call_vlseg_1070, 9, 6); + setRet(call_vlseg_1070, 0, ret_val_vlseg_1070); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 354); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 355: VLSEG7E8FF__V */ + continuation_e __vlseg7e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 355); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1071; + x86::Gp ret_val_get_pow_1071 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1071, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1072; + x86::Gp ret_val_get_sew_pow_1072 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1072, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1073; + x86::Gp ret_val_get_lmul_pow_1073 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1073, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1071, ret_val_get_sew_pow_1072), ret_val_get_lmul_pow_1073)), 3, true); + setArg(call_get_pow_1071, 0, reinterpret_cast(this)); + setArg(call_get_pow_1071, 1, EEW); + setRet(call_get_pow_1071, 0, ret_val_get_pow_1071); + setArg(call_get_sew_pow_1072, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1072, 0, ret_val_get_sew_pow_1072); + setArg(call_get_lmul_pow_1073, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1073, 0, ret_val_get_lmul_pow_1073); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1074; + auto illegal_load_1074_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1074 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1074, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1074; + setArg(call_illegal_load_1074, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1074, 1, vd); + setArg(call_illegal_load_1074, 2, vm); + setArg(call_illegal_load_1074, 3, 7); + setArg(call_illegal_load_1074, 4, EEW); + setArg(call_illegal_load_1074, 5, illegal_load_1074_arg4); + setRet(call_illegal_load_1074, 0, ret_val_illegal_load_1074); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1075; + auto vlseg_1075_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1075_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1075_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1075_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1075 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1075, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1075, 64, false); + setArg(call_vlseg_1075, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1075, 1, V); + setArg(call_vlseg_1075, 2, vlseg_1075_arg1); + setArg(call_vlseg_1075, 3, vlseg_1075_arg2); + setArg(call_vlseg_1075, 4, vlseg_1075_arg3); + setArg(call_vlseg_1075, 5, vm); + setArg(call_vlseg_1075, 6, vd); + setArg(call_vlseg_1075, 7, vlseg_1075_arg6); + setArg(call_vlseg_1075, 8, 0); + setArg(call_vlseg_1075, 9, 7); + setRet(call_vlseg_1075, 0, ret_val_vlseg_1075); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 355); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 356: VLSEG7E16FF__V */ + continuation_e __vlseg7e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 356); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1076; + x86::Gp ret_val_get_pow_1076 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1076, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1077; + x86::Gp ret_val_get_sew_pow_1077 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1077, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1078; + x86::Gp ret_val_get_lmul_pow_1078 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1078, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1076, ret_val_get_sew_pow_1077), ret_val_get_lmul_pow_1078)), 3, true); + setArg(call_get_pow_1076, 0, reinterpret_cast(this)); + setArg(call_get_pow_1076, 1, EEW); + setRet(call_get_pow_1076, 0, ret_val_get_pow_1076); + setArg(call_get_sew_pow_1077, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1077, 0, ret_val_get_sew_pow_1077); + setArg(call_get_lmul_pow_1078, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1078, 0, ret_val_get_lmul_pow_1078); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1079; + auto illegal_load_1079_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1079 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1079, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1079; + setArg(call_illegal_load_1079, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1079, 1, vd); + setArg(call_illegal_load_1079, 2, vm); + setArg(call_illegal_load_1079, 3, 7); + setArg(call_illegal_load_1079, 4, EEW); + setArg(call_illegal_load_1079, 5, illegal_load_1079_arg4); + setRet(call_illegal_load_1079, 0, ret_val_illegal_load_1079); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1080; + auto vlseg_1080_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1080_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1080_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1080_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1080 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1080, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1080, 64, false); + setArg(call_vlseg_1080, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1080, 1, V); + setArg(call_vlseg_1080, 2, vlseg_1080_arg1); + setArg(call_vlseg_1080, 3, vlseg_1080_arg2); + setArg(call_vlseg_1080, 4, vlseg_1080_arg3); + setArg(call_vlseg_1080, 5, vm); + setArg(call_vlseg_1080, 6, vd); + setArg(call_vlseg_1080, 7, vlseg_1080_arg6); + setArg(call_vlseg_1080, 8, 5); + setArg(call_vlseg_1080, 9, 7); + setRet(call_vlseg_1080, 0, ret_val_vlseg_1080); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 356); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 357: VLSEG7E32FF__V */ + continuation_e __vlseg7e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 357); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1081; + x86::Gp ret_val_get_pow_1081 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1081, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1082; + x86::Gp ret_val_get_sew_pow_1082 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1082, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1083; + x86::Gp ret_val_get_lmul_pow_1083 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1083, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1081, ret_val_get_sew_pow_1082), ret_val_get_lmul_pow_1083)), 3, true); + setArg(call_get_pow_1081, 0, reinterpret_cast(this)); + setArg(call_get_pow_1081, 1, EEW); + setRet(call_get_pow_1081, 0, ret_val_get_pow_1081); + setArg(call_get_sew_pow_1082, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1082, 0, ret_val_get_sew_pow_1082); + setArg(call_get_lmul_pow_1083, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1083, 0, ret_val_get_lmul_pow_1083); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1084; + auto illegal_load_1084_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1084 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1084, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1084; + setArg(call_illegal_load_1084, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1084, 1, vd); + setArg(call_illegal_load_1084, 2, vm); + setArg(call_illegal_load_1084, 3, 7); + setArg(call_illegal_load_1084, 4, EEW); + setArg(call_illegal_load_1084, 5, illegal_load_1084_arg4); + setRet(call_illegal_load_1084, 0, ret_val_illegal_load_1084); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1085; + auto vlseg_1085_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1085_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1085_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1085_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1085 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1085, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1085, 64, false); + setArg(call_vlseg_1085, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1085, 1, V); + setArg(call_vlseg_1085, 2, vlseg_1085_arg1); + setArg(call_vlseg_1085, 3, vlseg_1085_arg2); + setArg(call_vlseg_1085, 4, vlseg_1085_arg3); + setArg(call_vlseg_1085, 5, vm); + setArg(call_vlseg_1085, 6, vd); + setArg(call_vlseg_1085, 7, vlseg_1085_arg6); + setArg(call_vlseg_1085, 8, 6); + setArg(call_vlseg_1085, 9, 7); + setRet(call_vlseg_1085, 0, ret_val_vlseg_1085); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 357); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 358: VLSEG7E64FF__V */ + continuation_e __vlseg7e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg7e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG7E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 358); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1086; + x86::Gp ret_val_get_pow_1086 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1086, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1087; + x86::Gp ret_val_get_sew_pow_1087 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1087, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1088; + x86::Gp ret_val_get_lmul_pow_1088 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1088, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1086, ret_val_get_sew_pow_1087), ret_val_get_lmul_pow_1088)), 3, true); + setArg(call_get_pow_1086, 0, reinterpret_cast(this)); + setArg(call_get_pow_1086, 1, EEW); + setRet(call_get_pow_1086, 0, ret_val_get_pow_1086); + setArg(call_get_sew_pow_1087, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1087, 0, ret_val_get_sew_pow_1087); + setArg(call_get_lmul_pow_1088, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1088, 0, ret_val_get_lmul_pow_1088); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1089; + auto illegal_load_1089_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1089 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1089, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1089; + setArg(call_illegal_load_1089, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1089, 1, vd); + setArg(call_illegal_load_1089, 2, vm); + setArg(call_illegal_load_1089, 3, 7); + setArg(call_illegal_load_1089, 4, EEW); + setArg(call_illegal_load_1089, 5, illegal_load_1089_arg4); + setRet(call_illegal_load_1089, 0, ret_val_illegal_load_1089); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1090; + auto vlseg_1090_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1090_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1090_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1090_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1090 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1090, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1090, 64, false); + setArg(call_vlseg_1090, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1090, 1, V); + setArg(call_vlseg_1090, 2, vlseg_1090_arg1); + setArg(call_vlseg_1090, 3, vlseg_1090_arg2); + setArg(call_vlseg_1090, 4, vlseg_1090_arg3); + setArg(call_vlseg_1090, 5, vm); + setArg(call_vlseg_1090, 6, vd); + setArg(call_vlseg_1090, 7, vlseg_1090_arg6); + setArg(call_vlseg_1090, 8, 7); + setArg(call_vlseg_1090, 9, 7); + setRet(call_vlseg_1090, 0, ret_val_vlseg_1090); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 358); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 359: VLSEG8E8FF__V */ + continuation_e __vlseg8e8ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e8ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E8FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 359); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1091; + x86::Gp ret_val_get_pow_1091 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1091, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1092; + x86::Gp ret_val_get_sew_pow_1092 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1092, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1093; + x86::Gp ret_val_get_lmul_pow_1093 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1093, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1091, ret_val_get_sew_pow_1092), ret_val_get_lmul_pow_1093)), 3, true); + setArg(call_get_pow_1091, 0, reinterpret_cast(this)); + setArg(call_get_pow_1091, 1, EEW); + setRet(call_get_pow_1091, 0, ret_val_get_pow_1091); + setArg(call_get_sew_pow_1092, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1092, 0, ret_val_get_sew_pow_1092); + setArg(call_get_lmul_pow_1093, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1093, 0, ret_val_get_lmul_pow_1093); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1094; + auto illegal_load_1094_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1094 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1094, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1094; + setArg(call_illegal_load_1094, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1094, 1, vd); + setArg(call_illegal_load_1094, 2, vm); + setArg(call_illegal_load_1094, 3, 8); + setArg(call_illegal_load_1094, 4, EEW); + setArg(call_illegal_load_1094, 5, illegal_load_1094_arg4); + setRet(call_illegal_load_1094, 0, ret_val_illegal_load_1094); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1095; + auto vlseg_1095_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1095_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1095_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1095_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1095 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1095, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1095, 64, false); + setArg(call_vlseg_1095, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1095, 1, V); + setArg(call_vlseg_1095, 2, vlseg_1095_arg1); + setArg(call_vlseg_1095, 3, vlseg_1095_arg2); + setArg(call_vlseg_1095, 4, vlseg_1095_arg3); + setArg(call_vlseg_1095, 5, vm); + setArg(call_vlseg_1095, 6, vd); + setArg(call_vlseg_1095, 7, vlseg_1095_arg6); + setArg(call_vlseg_1095, 8, 0); + setArg(call_vlseg_1095, 9, 8); + setRet(call_vlseg_1095, 0, ret_val_vlseg_1095); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 359); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 360: VLSEG8E16FF__V */ + continuation_e __vlseg8e16ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e16ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E16FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 360); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1096; + x86::Gp ret_val_get_pow_1096 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1096, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1097; + x86::Gp ret_val_get_sew_pow_1097 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1097, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1098; + x86::Gp ret_val_get_lmul_pow_1098 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1098, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1096, ret_val_get_sew_pow_1097), ret_val_get_lmul_pow_1098)), 3, true); + setArg(call_get_pow_1096, 0, reinterpret_cast(this)); + setArg(call_get_pow_1096, 1, EEW); + setRet(call_get_pow_1096, 0, ret_val_get_pow_1096); + setArg(call_get_sew_pow_1097, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1097, 0, ret_val_get_sew_pow_1097); + setArg(call_get_lmul_pow_1098, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1098, 0, ret_val_get_lmul_pow_1098); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1099; + auto illegal_load_1099_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1099 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1099, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1099; + setArg(call_illegal_load_1099, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1099, 1, vd); + setArg(call_illegal_load_1099, 2, vm); + setArg(call_illegal_load_1099, 3, 8); + setArg(call_illegal_load_1099, 4, EEW); + setArg(call_illegal_load_1099, 5, illegal_load_1099_arg4); + setRet(call_illegal_load_1099, 0, ret_val_illegal_load_1099); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1100; + auto vlseg_1100_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1100_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1100_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1100_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1100 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1100, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1100, 64, false); + setArg(call_vlseg_1100, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1100, 1, V); + setArg(call_vlseg_1100, 2, vlseg_1100_arg1); + setArg(call_vlseg_1100, 3, vlseg_1100_arg2); + setArg(call_vlseg_1100, 4, vlseg_1100_arg3); + setArg(call_vlseg_1100, 5, vm); + setArg(call_vlseg_1100, 6, vd); + setArg(call_vlseg_1100, 7, vlseg_1100_arg6); + setArg(call_vlseg_1100, 8, 5); + setArg(call_vlseg_1100, 9, 8); + setRet(call_vlseg_1100, 0, ret_val_vlseg_1100); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 360); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 361: VLSEG8E32FF__V */ + continuation_e __vlseg8e32ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e32ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E32FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 361); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1101; + x86::Gp ret_val_get_pow_1101 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1101, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1102; + x86::Gp ret_val_get_sew_pow_1102 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1102, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1103; + x86::Gp ret_val_get_lmul_pow_1103 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1103, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1101, ret_val_get_sew_pow_1102), ret_val_get_lmul_pow_1103)), 3, true); + setArg(call_get_pow_1101, 0, reinterpret_cast(this)); + setArg(call_get_pow_1101, 1, EEW); + setRet(call_get_pow_1101, 0, ret_val_get_pow_1101); + setArg(call_get_sew_pow_1102, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1102, 0, ret_val_get_sew_pow_1102); + setArg(call_get_lmul_pow_1103, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1103, 0, ret_val_get_lmul_pow_1103); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1104; + auto illegal_load_1104_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1104 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1104, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1104; + setArg(call_illegal_load_1104, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1104, 1, vd); + setArg(call_illegal_load_1104, 2, vm); + setArg(call_illegal_load_1104, 3, 8); + setArg(call_illegal_load_1104, 4, EEW); + setArg(call_illegal_load_1104, 5, illegal_load_1104_arg4); + setRet(call_illegal_load_1104, 0, ret_val_illegal_load_1104); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1105; + auto vlseg_1105_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1105_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1105_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1105_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1105 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1105, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1105, 64, false); + setArg(call_vlseg_1105, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1105, 1, V); + setArg(call_vlseg_1105, 2, vlseg_1105_arg1); + setArg(call_vlseg_1105, 3, vlseg_1105_arg2); + setArg(call_vlseg_1105, 4, vlseg_1105_arg3); + setArg(call_vlseg_1105, 5, vm); + setArg(call_vlseg_1105, 6, vd); + setArg(call_vlseg_1105, 7, vlseg_1105_arg6); + setArg(call_vlseg_1105, 8, 6); + setArg(call_vlseg_1105, 9, 8); + setRet(call_vlseg_1105, 0, ret_val_vlseg_1105); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 361); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 362: VLSEG8E64FF__V */ + continuation_e __vlseg8e64ff__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vlseg8e64ff.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLSEG8E64FF__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 362); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1106; + x86::Gp ret_val_get_pow_1106 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1106, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1107; + x86::Gp ret_val_get_sew_pow_1107 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1107, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1108; + x86::Gp ret_val_get_lmul_pow_1108 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1108, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1106, ret_val_get_sew_pow_1107), ret_val_get_lmul_pow_1108)), 3, true); + setArg(call_get_pow_1106, 0, reinterpret_cast(this)); + setArg(call_get_pow_1106, 1, EEW); + setRet(call_get_pow_1106, 0, ret_val_get_pow_1106); + setArg(call_get_sew_pow_1107, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1107, 0, ret_val_get_sew_pow_1107); + setArg(call_get_lmul_pow_1108, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1108, 0, ret_val_get_lmul_pow_1108); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_load_1109; + auto illegal_load_1109_arg4 = EMUL_pow; + x86::Gp ret_val_illegal_load_1109 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_load_1109, (uintptr_t)&vm_impl::_illegal_load, FuncSignature::build()); + auto cond = ret_val_illegal_load_1109; + setArg(call_illegal_load_1109, 0, reinterpret_cast(this)); + setArg(call_illegal_load_1109, 1, vd); + setArg(call_illegal_load_1109, 2, vm); + setArg(call_illegal_load_1109, 3, 8); + setArg(call_illegal_load_1109, 4, EEW); + setArg(call_illegal_load_1109, 5, illegal_load_1109_arg4); + setRet(call_illegal_load_1109, 0, ret_val_illegal_load_1109); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_vlseg_1110; + auto vlseg_1110_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlseg_1110_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1110_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1110_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1110 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1110, &vlseg, FuncSignature::build()); + auto trapped_idx = gen_ext(cc, + ret_val_vlseg_1110, 64, false); + setArg(call_vlseg_1110, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1110, 1, V); + setArg(call_vlseg_1110, 2, vlseg_1110_arg1); + setArg(call_vlseg_1110, 3, vlseg_1110_arg2); + setArg(call_vlseg_1110, 4, vlseg_1110_arg3); + setArg(call_vlseg_1110, 5, vm); + setArg(call_vlseg_1110, 6, vd); + setArg(call_vlseg_1110, 7, vlseg_1110_arg6); + setArg(call_vlseg_1110, 8, 7); + setArg(call_vlseg_1110, 9, 8); + setRet(call_vlseg_1110, 0, ret_val_vlseg_1110); + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, ne, trapped_idx, 1); + cmp(cc, cond, 0); + cc.je(label_merge); + { + write_reg_to_mem(jh, gen_ext(cc, + trapped_idx, 64, false), traits::vl); + gen_lower(jh); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 362); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 363: VSM__V */ + continuation_e __vsm__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {vs3}", fmt::arg("mnemonic", "vsm.v"), + fmt::arg("rs1", name(rs1)), fmt::arg("vs3", vname(vs3))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSM__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 363); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto label_then1111 = cc.newLabel(); + auto label_merge1111 = cc.newLabel(); + auto tmp_reg1111 = get_reg_Gp(cc, 64, false); + cmp(cc, gen_operation(cc, urem, load_reg_from_mem(jh, traits::vl), 8), 0); + cc.je(label_then1111); + mov(cc, tmp_reg1111,gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, udiv, load_reg_from_mem(jh, traits::vl), 8), 1)), 64, false)); + cc.jmp(label_merge1111); + cc.bind(label_then1111); + mov(cc, tmp_reg1111, gen_operation(cc, udiv, load_reg_from_mem(jh, traits::vl), 8)); + cc.bind(label_merge1111); + auto evl = tmp_reg1111 + ; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_1112; + x86::Gp ret_val_illegal_vd_unmasked_1112 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_1112, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_1112; + setArg(call_illegal_vd_unmasked_1112, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_1112, 0, ret_val_illegal_vd_unmasked_1112); + cmp(cc, cond, 0); + cc.je(label_merge); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.bind(label_merge); + } + auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 7, static_cast(traits::XLEN)-1-7+1), 64, false), 7), gen_operation(cc, shl, gen_ext(cc, 1, 64, false), 6)), gen_operation(cc, shl, gen_ext(cc, 0, 64, false), 3)), gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 0, 2-0+1), 64, false)); + InvokeNode* call_vsseg_1113; + auto vsseg_1113_arg1 = evl; + auto vsseg_1113_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_1113_arg3 = _vtype; + auto vsseg_1113_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_1113 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_1113, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_1113, 64, false), traits::vstart); + setArg(call_vsseg_1113, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_1113, 1, V); + setArg(call_vsseg_1113, 2, vsseg_1113_arg1); + setArg(call_vsseg_1113, 3, vsseg_1113_arg2); + setArg(call_vsseg_1113, 4, vsseg_1113_arg3); + setArg(call_vsseg_1113, 5, 1); + setArg(call_vsseg_1113, 6, vs3); + setArg(call_vsseg_1113, 7, vsseg_1113_arg6); + setArg(call_vsseg_1113, 8, 0); + setArg(call_vsseg_1113, 9, 1); + setRet(call_vsseg_1113, 0, ret_val_vsseg_1113); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 363); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 364: VLM__V */ + continuation_e __vlm__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {vd}", fmt::arg("mnemonic", "vlm.v"), + fmt::arg("rs1", name(rs1)), fmt::arg("vd", vname(vd))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLM__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 364); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto label_then1114 = cc.newLabel(); + auto label_merge1114 = cc.newLabel(); + auto tmp_reg1114 = get_reg_Gp(cc, 64, false); + cmp(cc, gen_operation(cc, urem, load_reg_from_mem(jh, traits::vl), 8), 0); + cc.je(label_then1114); + mov(cc, tmp_reg1114,gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, udiv, load_reg_from_mem(jh, traits::vl), 8), 1)), 64, false)); + cc.jmp(label_merge1114); + cc.bind(label_then1114); + mov(cc, tmp_reg1114, gen_operation(cc, udiv, load_reg_from_mem(jh, traits::vl), 8)); + cc.bind(label_merge1114); + auto evl = tmp_reg1114 + ; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_1115; + x86::Gp ret_val_illegal_vd_unmasked_1115 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_1115, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_1115; + setArg(call_illegal_vd_unmasked_1115, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_1115, 0, ret_val_illegal_vd_unmasked_1115); + cmp(cc, cond, 0); + cc.je(label_merge); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.bind(label_merge); + } + auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 7, static_cast(traits::XLEN)-1-7+1), 64, false), 7), gen_operation(cc, shl, gen_ext(cc, 1, 64, false), 6)), gen_operation(cc, shl, gen_ext(cc, 0, 64, false), 3)), gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 0, 2-0+1), 64, false)); + InvokeNode* call_vlseg_1116; + auto vlseg_1116_arg1 = evl; + auto vlseg_1116_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1116_arg3 = _vtype; + auto vlseg_1116_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1116 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1116, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1116, 64, false), traits::vstart); + setArg(call_vlseg_1116, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1116, 1, V); + setArg(call_vlseg_1116, 2, vlseg_1116_arg1); + setArg(call_vlseg_1116, 3, vlseg_1116_arg2); + setArg(call_vlseg_1116, 4, vlseg_1116_arg3); + setArg(call_vlseg_1116, 5, 1); + setArg(call_vlseg_1116, 6, vd); + setArg(call_vlseg_1116, 7, vlseg_1116_arg6); + setArg(call_vlseg_1116, 8, 0); + setArg(call_vlseg_1116, 9, 1); + setRet(call_vlseg_1116, 0, ret_val_vlseg_1116); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 364); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 365: VL1RE8__V */ + continuation_e __vl1re8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL1RE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 365); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(1*static_cast(traits::VLEN)/8); + { + auto label_merge = cc.newLabel(); + auto tmp1117 = get_reg(cc, 64, false); + mov(cc, tmp1117, evl); + auto cond = gen_operation(cc, gtu, tmp1117, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1118; + auto vlseg_1118_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1118_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1118_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1118 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1118, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1118, 64, false), traits::vstart); + setArg(call_vlseg_1118, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1118, 1, V); + setArg(call_vlseg_1118, 2, evl); + setArg(call_vlseg_1118, 3, vlseg_1118_arg2); + setArg(call_vlseg_1118, 4, vlseg_1118_arg3); + setArg(call_vlseg_1118, 5, 1); + setArg(call_vlseg_1118, 6, vd); + setArg(call_vlseg_1118, 7, vlseg_1118_arg6); + setArg(call_vlseg_1118, 8, 0); + setArg(call_vlseg_1118, 9, 1); + setRet(call_vlseg_1118, 0, ret_val_vlseg_1118); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 365); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 366: VL1RE16__V */ + continuation_e __vl1re16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL1RE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 366); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(1*static_cast(traits::VLEN)/16); + { + auto label_merge = cc.newLabel(); + auto tmp1119 = get_reg(cc, 64, false); + mov(cc, tmp1119, evl); + auto cond = gen_operation(cc, gtu, tmp1119, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1120; + auto vlseg_1120_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1120_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1120_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1120 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1120, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1120, 64, false), traits::vstart); + setArg(call_vlseg_1120, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1120, 1, V); + setArg(call_vlseg_1120, 2, evl); + setArg(call_vlseg_1120, 3, vlseg_1120_arg2); + setArg(call_vlseg_1120, 4, vlseg_1120_arg3); + setArg(call_vlseg_1120, 5, 1); + setArg(call_vlseg_1120, 6, vd); + setArg(call_vlseg_1120, 7, vlseg_1120_arg6); + setArg(call_vlseg_1120, 8, 5); + setArg(call_vlseg_1120, 9, 1); + setRet(call_vlseg_1120, 0, ret_val_vlseg_1120); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 366); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 367: VL1RE32__V */ + continuation_e __vl1re32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL1RE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 367); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(1*static_cast(traits::VLEN)/32); + { + auto label_merge = cc.newLabel(); + auto tmp1121 = get_reg(cc, 64, false); + mov(cc, tmp1121, evl); + auto cond = gen_operation(cc, gtu, tmp1121, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1122; + auto vlseg_1122_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1122_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1122_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1122 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1122, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1122, 64, false), traits::vstart); + setArg(call_vlseg_1122, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1122, 1, V); + setArg(call_vlseg_1122, 2, evl); + setArg(call_vlseg_1122, 3, vlseg_1122_arg2); + setArg(call_vlseg_1122, 4, vlseg_1122_arg3); + setArg(call_vlseg_1122, 5, 1); + setArg(call_vlseg_1122, 6, vd); + setArg(call_vlseg_1122, 7, vlseg_1122_arg6); + setArg(call_vlseg_1122, 8, 6); + setArg(call_vlseg_1122, 9, 1); + setRet(call_vlseg_1122, 0, ret_val_vlseg_1122); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 367); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 368: VL1RE64__V */ + continuation_e __vl1re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl1re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL1RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 368); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(1*static_cast(traits::VLEN)/64); + { + auto label_merge = cc.newLabel(); + auto tmp1123 = get_reg(cc, 64, false); + mov(cc, tmp1123, evl); + auto cond = gen_operation(cc, gtu, tmp1123, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1124; + auto vlseg_1124_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1124_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1124_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1124 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1124, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1124, 64, false), traits::vstart); + setArg(call_vlseg_1124, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1124, 1, V); + setArg(call_vlseg_1124, 2, evl); + setArg(call_vlseg_1124, 3, vlseg_1124_arg2); + setArg(call_vlseg_1124, 4, vlseg_1124_arg3); + setArg(call_vlseg_1124, 5, 1); + setArg(call_vlseg_1124, 6, vd); + setArg(call_vlseg_1124, 7, vlseg_1124_arg6); + setArg(call_vlseg_1124, 8, 7); + setArg(call_vlseg_1124, 9, 1); + setRet(call_vlseg_1124, 0, ret_val_vlseg_1124); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 368); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 369: VL2RE8__V */ + continuation_e __vl2re8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL2RE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 369); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(2*static_cast(traits::VLEN)/8); + if(vd%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1125 = get_reg(cc, 64, false); + mov(cc, tmp1125, evl); + auto cond = gen_operation(cc, gtu, tmp1125, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1126; + auto vlseg_1126_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1126_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1126_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1126 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1126, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1126, 64, false), traits::vstart); + setArg(call_vlseg_1126, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1126, 1, V); + setArg(call_vlseg_1126, 2, evl); + setArg(call_vlseg_1126, 3, vlseg_1126_arg2); + setArg(call_vlseg_1126, 4, vlseg_1126_arg3); + setArg(call_vlseg_1126, 5, 1); + setArg(call_vlseg_1126, 6, vd); + setArg(call_vlseg_1126, 7, vlseg_1126_arg6); + setArg(call_vlseg_1126, 8, 0); + setArg(call_vlseg_1126, 9, 1); + setRet(call_vlseg_1126, 0, ret_val_vlseg_1126); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 369); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 370: VL2RE16__V */ + continuation_e __vl2re16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL2RE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 370); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(2*static_cast(traits::VLEN)/16); + if(vd%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1127 = get_reg(cc, 64, false); + mov(cc, tmp1127, evl); + auto cond = gen_operation(cc, gtu, tmp1127, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1128; + auto vlseg_1128_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1128_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1128_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1128 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1128, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1128, 64, false), traits::vstart); + setArg(call_vlseg_1128, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1128, 1, V); + setArg(call_vlseg_1128, 2, evl); + setArg(call_vlseg_1128, 3, vlseg_1128_arg2); + setArg(call_vlseg_1128, 4, vlseg_1128_arg3); + setArg(call_vlseg_1128, 5, 1); + setArg(call_vlseg_1128, 6, vd); + setArg(call_vlseg_1128, 7, vlseg_1128_arg6); + setArg(call_vlseg_1128, 8, 5); + setArg(call_vlseg_1128, 9, 1); + setRet(call_vlseg_1128, 0, ret_val_vlseg_1128); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 370); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 371: VL2RE32__V */ + continuation_e __vl2re32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL2RE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 371); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(2*static_cast(traits::VLEN)/32); + if(vd%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1129 = get_reg(cc, 64, false); + mov(cc, tmp1129, evl); + auto cond = gen_operation(cc, gtu, tmp1129, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1130; + auto vlseg_1130_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1130_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1130_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1130 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1130, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1130, 64, false), traits::vstart); + setArg(call_vlseg_1130, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1130, 1, V); + setArg(call_vlseg_1130, 2, evl); + setArg(call_vlseg_1130, 3, vlseg_1130_arg2); + setArg(call_vlseg_1130, 4, vlseg_1130_arg3); + setArg(call_vlseg_1130, 5, 1); + setArg(call_vlseg_1130, 6, vd); + setArg(call_vlseg_1130, 7, vlseg_1130_arg6); + setArg(call_vlseg_1130, 8, 6); + setArg(call_vlseg_1130, 9, 1); + setRet(call_vlseg_1130, 0, ret_val_vlseg_1130); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 371); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 372: VL2RE64__V */ + continuation_e __vl2re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl2re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL2RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 372); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(2*static_cast(traits::VLEN)/64); + if(vd%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1131 = get_reg(cc, 64, false); + mov(cc, tmp1131, evl); + auto cond = gen_operation(cc, gtu, tmp1131, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1132; + auto vlseg_1132_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1132_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1132_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1132 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1132, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1132, 64, false), traits::vstart); + setArg(call_vlseg_1132, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1132, 1, V); + setArg(call_vlseg_1132, 2, evl); + setArg(call_vlseg_1132, 3, vlseg_1132_arg2); + setArg(call_vlseg_1132, 4, vlseg_1132_arg3); + setArg(call_vlseg_1132, 5, 1); + setArg(call_vlseg_1132, 6, vd); + setArg(call_vlseg_1132, 7, vlseg_1132_arg6); + setArg(call_vlseg_1132, 8, 7); + setArg(call_vlseg_1132, 9, 1); + setRet(call_vlseg_1132, 0, ret_val_vlseg_1132); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 372); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 373: VL4RE8__V */ + continuation_e __vl4re8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL4RE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 373); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(4*static_cast(traits::VLEN)/8); + if(vd%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1133 = get_reg(cc, 64, false); + mov(cc, tmp1133, evl); + auto cond = gen_operation(cc, gtu, tmp1133, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1134; + auto vlseg_1134_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1134_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1134_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1134 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1134, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1134, 64, false), traits::vstart); + setArg(call_vlseg_1134, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1134, 1, V); + setArg(call_vlseg_1134, 2, evl); + setArg(call_vlseg_1134, 3, vlseg_1134_arg2); + setArg(call_vlseg_1134, 4, vlseg_1134_arg3); + setArg(call_vlseg_1134, 5, 1); + setArg(call_vlseg_1134, 6, vd); + setArg(call_vlseg_1134, 7, vlseg_1134_arg6); + setArg(call_vlseg_1134, 8, 0); + setArg(call_vlseg_1134, 9, 1); + setRet(call_vlseg_1134, 0, ret_val_vlseg_1134); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 373); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 374: VL4RE16__V */ + continuation_e __vl4re16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL4RE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 374); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(4*static_cast(traits::VLEN)/16); + if(vd%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1135 = get_reg(cc, 64, false); + mov(cc, tmp1135, evl); + auto cond = gen_operation(cc, gtu, tmp1135, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1136; + auto vlseg_1136_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1136_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1136_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1136 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1136, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1136, 64, false), traits::vstart); + setArg(call_vlseg_1136, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1136, 1, V); + setArg(call_vlseg_1136, 2, evl); + setArg(call_vlseg_1136, 3, vlseg_1136_arg2); + setArg(call_vlseg_1136, 4, vlseg_1136_arg3); + setArg(call_vlseg_1136, 5, 1); + setArg(call_vlseg_1136, 6, vd); + setArg(call_vlseg_1136, 7, vlseg_1136_arg6); + setArg(call_vlseg_1136, 8, 5); + setArg(call_vlseg_1136, 9, 1); + setRet(call_vlseg_1136, 0, ret_val_vlseg_1136); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 374); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 375: VL4RE32__V */ + continuation_e __vl4re32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL4RE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 375); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(4*static_cast(traits::VLEN)/32); + if(vd%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1137 = get_reg(cc, 64, false); + mov(cc, tmp1137, evl); + auto cond = gen_operation(cc, gtu, tmp1137, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1138; + auto vlseg_1138_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1138_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1138_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1138 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1138, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1138, 64, false), traits::vstart); + setArg(call_vlseg_1138, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1138, 1, V); + setArg(call_vlseg_1138, 2, evl); + setArg(call_vlseg_1138, 3, vlseg_1138_arg2); + setArg(call_vlseg_1138, 4, vlseg_1138_arg3); + setArg(call_vlseg_1138, 5, 1); + setArg(call_vlseg_1138, 6, vd); + setArg(call_vlseg_1138, 7, vlseg_1138_arg6); + setArg(call_vlseg_1138, 8, 6); + setArg(call_vlseg_1138, 9, 1); + setRet(call_vlseg_1138, 0, ret_val_vlseg_1138); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 375); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 376: VL4RE64__V */ + continuation_e __vl4re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl4re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL4RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 376); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(4*static_cast(traits::VLEN)/64); + if(vd%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1139 = get_reg(cc, 64, false); + mov(cc, tmp1139, evl); + auto cond = gen_operation(cc, gtu, tmp1139, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1140; + auto vlseg_1140_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1140_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1140_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1140 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1140, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1140, 64, false), traits::vstart); + setArg(call_vlseg_1140, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1140, 1, V); + setArg(call_vlseg_1140, 2, evl); + setArg(call_vlseg_1140, 3, vlseg_1140_arg2); + setArg(call_vlseg_1140, 4, vlseg_1140_arg3); + setArg(call_vlseg_1140, 5, 1); + setArg(call_vlseg_1140, 6, vd); + setArg(call_vlseg_1140, 7, vlseg_1140_arg6); + setArg(call_vlseg_1140, 8, 7); + setArg(call_vlseg_1140, 9, 1); + setRet(call_vlseg_1140, 0, ret_val_vlseg_1140); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 376); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 377: VL8RE8__V */ + continuation_e __vl8re8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL8RE8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 377); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(8*static_cast(traits::VLEN)/8); + if(vd%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1141 = get_reg(cc, 64, false); + mov(cc, tmp1141, evl); + auto cond = gen_operation(cc, gtu, tmp1141, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1142; + auto vlseg_1142_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1142_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1142_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1142 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1142, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1142, 64, false), traits::vstart); + setArg(call_vlseg_1142, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1142, 1, V); + setArg(call_vlseg_1142, 2, evl); + setArg(call_vlseg_1142, 3, vlseg_1142_arg2); + setArg(call_vlseg_1142, 4, vlseg_1142_arg3); + setArg(call_vlseg_1142, 5, 1); + setArg(call_vlseg_1142, 6, vd); + setArg(call_vlseg_1142, 7, vlseg_1142_arg6); + setArg(call_vlseg_1142, 8, 0); + setArg(call_vlseg_1142, 9, 1); + setRet(call_vlseg_1142, 0, ret_val_vlseg_1142); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 377); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 378: VL8RE16__V */ + continuation_e __vl8re16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL8RE16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 378); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(8*static_cast(traits::VLEN)/16); + if(vd%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1143 = get_reg(cc, 64, false); + mov(cc, tmp1143, evl); + auto cond = gen_operation(cc, gtu, tmp1143, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1144; + auto vlseg_1144_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1144_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1144_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1144 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1144, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1144, 64, false), traits::vstart); + setArg(call_vlseg_1144, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1144, 1, V); + setArg(call_vlseg_1144, 2, evl); + setArg(call_vlseg_1144, 3, vlseg_1144_arg2); + setArg(call_vlseg_1144, 4, vlseg_1144_arg3); + setArg(call_vlseg_1144, 5, 1); + setArg(call_vlseg_1144, 6, vd); + setArg(call_vlseg_1144, 7, vlseg_1144_arg6); + setArg(call_vlseg_1144, 8, 5); + setArg(call_vlseg_1144, 9, 1); + setRet(call_vlseg_1144, 0, ret_val_vlseg_1144); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 378); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 379: VL8RE32__V */ + continuation_e __vl8re32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL8RE32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 379); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(8*static_cast(traits::VLEN)/32); + if(vd%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1145 = get_reg(cc, 64, false); + mov(cc, tmp1145, evl); + auto cond = gen_operation(cc, gtu, tmp1145, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1146; + auto vlseg_1146_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1146_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1146_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1146 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1146, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1146, 64, false), traits::vstart); + setArg(call_vlseg_1146, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1146, 1, V); + setArg(call_vlseg_1146, 2, evl); + setArg(call_vlseg_1146, 3, vlseg_1146_arg2); + setArg(call_vlseg_1146, 4, vlseg_1146_arg3); + setArg(call_vlseg_1146, 5, 1); + setArg(call_vlseg_1146, 6, vd); + setArg(call_vlseg_1146, 7, vlseg_1146_arg6); + setArg(call_vlseg_1146, 8, 6); + setArg(call_vlseg_1146, 9, 1); + setRet(call_vlseg_1146, 0, ret_val_vlseg_1146); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 379); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 380: VL8RE64__V */ + continuation_e __vl8re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1})", fmt::arg("mnemonic", "vl8re64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VL8RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 380); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(8*static_cast(traits::VLEN)/64); + if(vd%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1147 = get_reg(cc, 64, false); + mov(cc, tmp1147, evl); + auto cond = gen_operation(cc, gtu, tmp1147, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vlseg_1148; + auto vlseg_1148_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlseg_1148_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlseg_1148_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlseg_1148 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlseg_1148, &vlseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlseg_1148, 64, false), traits::vstart); + setArg(call_vlseg_1148, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlseg_1148, 1, V); + setArg(call_vlseg_1148, 2, evl); + setArg(call_vlseg_1148, 3, vlseg_1148_arg2); + setArg(call_vlseg_1148, 4, vlseg_1148_arg3); + setArg(call_vlseg_1148, 5, 1); + setArg(call_vlseg_1148, 6, vd); + setArg(call_vlseg_1148, 7, vlseg_1148_arg6); + setArg(call_vlseg_1148, 8, 7); + setArg(call_vlseg_1148, 9, 1); + setRet(call_vlseg_1148, 0, ret_val_vlseg_1148); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 380); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 381: VS1RE64__V */ + continuation_e __vs1re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs1re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VS1RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 381); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(1*static_cast(traits::VLEN)/8); + { + auto label_merge = cc.newLabel(); + auto tmp1149 = get_reg(cc, 64, false); + mov(cc, tmp1149, evl); + auto cond = gen_operation(cc, gtu, tmp1149, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_1150; + auto vsseg_1150_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_1150_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_1150_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_1150 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_1150, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_1150, 64, false), traits::vstart); + setArg(call_vsseg_1150, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_1150, 1, V); + setArg(call_vsseg_1150, 2, evl); + setArg(call_vsseg_1150, 3, vsseg_1150_arg2); + setArg(call_vsseg_1150, 4, vsseg_1150_arg3); + setArg(call_vsseg_1150, 5, 1); + setArg(call_vsseg_1150, 6, vs3); + setArg(call_vsseg_1150, 7, vsseg_1150_arg6); + setArg(call_vsseg_1150, 8, 0); + setArg(call_vsseg_1150, 9, 1); + setRet(call_vsseg_1150, 0, ret_val_vsseg_1150); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 381); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 382: VS2RE64__V */ + continuation_e __vs2re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs2re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VS2RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 382); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(2*static_cast(traits::VLEN)/8); + if(vs3%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1151 = get_reg(cc, 64, false); + mov(cc, tmp1151, evl); + auto cond = gen_operation(cc, gtu, tmp1151, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_1152; + auto vsseg_1152_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_1152_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_1152_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_1152 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_1152, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_1152, 64, false), traits::vstart); + setArg(call_vsseg_1152, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_1152, 1, V); + setArg(call_vsseg_1152, 2, evl); + setArg(call_vsseg_1152, 3, vsseg_1152_arg2); + setArg(call_vsseg_1152, 4, vsseg_1152_arg3); + setArg(call_vsseg_1152, 5, 1); + setArg(call_vsseg_1152, 6, vs3); + setArg(call_vsseg_1152, 7, vsseg_1152_arg6); + setArg(call_vsseg_1152, 8, 0); + setArg(call_vsseg_1152, 9, 1); + setRet(call_vsseg_1152, 0, ret_val_vsseg_1152); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 382); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 383: VS4RE64__V */ + continuation_e __vs4re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs4re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VS4RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 383); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(4*static_cast(traits::VLEN)/8); + if(vs3%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1153 = get_reg(cc, 64, false); + mov(cc, tmp1153, evl); + auto cond = gen_operation(cc, gtu, tmp1153, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_1154; + auto vsseg_1154_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_1154_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_1154_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_1154 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_1154, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_1154, 64, false), traits::vstart); + setArg(call_vsseg_1154, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_1154, 1, V); + setArg(call_vsseg_1154, 2, evl); + setArg(call_vsseg_1154, 3, vsseg_1154_arg2); + setArg(call_vsseg_1154, 4, vsseg_1154_arg3); + setArg(call_vsseg_1154, 5, 1); + setArg(call_vsseg_1154, 6, vs3); + setArg(call_vsseg_1154, 7, vsseg_1154_arg6); + setArg(call_vsseg_1154, 8, 0); + setArg(call_vsseg_1154, 9, 1); + setRet(call_vsseg_1154, 0, ret_val_vsseg_1154); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 383); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 384: VS8RE64__V */ + continuation_e __vs8re64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1})", fmt::arg("mnemonic", "vs8re64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VS8RE64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 384); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto evl = (uint64_t)(8*static_cast(traits::VLEN)/8); + if(vs3%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + { + auto label_merge = cc.newLabel(); + auto tmp1155 = get_reg(cc, 64, false); + mov(cc, tmp1155, evl); + auto cond = gen_operation(cc, gtu, tmp1155, load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vsseg_1156; + auto vsseg_1156_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsseg_1156_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsseg_1156_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsseg_1156 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsseg_1156, &vsseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsseg_1156, 64, false), traits::vstart); + setArg(call_vsseg_1156, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsseg_1156, 1, V); + setArg(call_vsseg_1156, 2, evl); + setArg(call_vsseg_1156, 3, vsseg_1156_arg2); + setArg(call_vsseg_1156, 4, vsseg_1156_arg3); + setArg(call_vsseg_1156, 5, 1); + setArg(call_vsseg_1156, 6, vs3); + setArg(call_vsseg_1156, 7, vsseg_1156_arg6); + setArg(call_vsseg_1156, 8, 0); + setArg(call_vsseg_1156, 9, 1); + setRet(call_vsseg_1156, 0, ret_val_vsseg_1156); + } + cc.bind(label_merge); + } + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 384); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 385: VLOXEI8__V */ + continuation_e __vloxei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXEI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 385); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1157; + x86::Gp ret_val_get_pow_1157 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1157, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1158; + x86::Gp ret_val_get_sew_pow_1158 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1158, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1159; + x86::Gp ret_val_get_lmul_pow_1159 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1159, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1157, ret_val_get_sew_pow_1158), ret_val_get_lmul_pow_1159)), 3, true); + setArg(call_get_pow_1157, 0, reinterpret_cast(this)); + setArg(call_get_pow_1157, 1, EEW); + setRet(call_get_pow_1157, 0, ret_val_get_pow_1157); + setArg(call_get_sew_pow_1158, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1158, 0, ret_val_get_sew_pow_1158); + setArg(call_get_lmul_pow_1159, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1159, 0, ret_val_get_lmul_pow_1159); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1161; + x86::Gp ret_val_get_lmul_pow_1161 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1161, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1160; + auto illegal_indexed_load_1160_arg4 = EMUL_pow; + auto illegal_indexed_load_1160_arg5 = ret_val_get_lmul_pow_1161; + x86::Gp ret_val_illegal_indexed_load_1160 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1160, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1160; + setArg(call_get_lmul_pow_1161, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1161, 0, ret_val_get_lmul_pow_1161); + setArg(call_illegal_indexed_load_1160, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1160, 1, vd); + setArg(call_illegal_indexed_load_1160, 2, vm); + setArg(call_illegal_indexed_load_1160, 3, 1); + setArg(call_illegal_indexed_load_1160, 4, EEW); + setArg(call_illegal_indexed_load_1160, 5, illegal_indexed_load_1160_arg4); + setArg(call_illegal_indexed_load_1160, 6, illegal_indexed_load_1160_arg5); + setRet(call_illegal_indexed_load_1160, 0, ret_val_illegal_indexed_load_1160); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1163; + x86::Gp ret_val_sew_1163 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1163, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1162; + auto vlxseg_1162_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1162_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1162_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1162_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1162_arg10 = ret_val_sew_1163; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1162 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1162, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1162, 64, false), traits::vstart); + setArg(call_sew_1163, 0, reinterpret_cast(this)); + setRet(call_sew_1163, 0, ret_val_sew_1163); + setArg(call_vlxseg_1162, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1162, 1, V); + setArg(call_vlxseg_1162, 2, vlxseg_1162_arg1); + setArg(call_vlxseg_1162, 3, vlxseg_1162_arg2); + setArg(call_vlxseg_1162, 4, vlxseg_1162_arg3); + setArg(call_vlxseg_1162, 5, vm); + setArg(call_vlxseg_1162, 6, vd); + setArg(call_vlxseg_1162, 7, vlxseg_1162_arg6); + setArg(call_vlxseg_1162, 8, vs2); + setArg(call_vlxseg_1162, 9, 1); + setArg(call_vlxseg_1162, 10, 1); + setArg(call_vlxseg_1162, 11, vlxseg_1162_arg10); + setArg(call_vlxseg_1162, 12, 1); + setRet(call_vlxseg_1162, 0, ret_val_vlxseg_1162); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 385); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 386: VLOXEI16__V */ + continuation_e __vloxei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXEI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 386); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1164; + x86::Gp ret_val_get_pow_1164 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1164, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1165; + x86::Gp ret_val_get_sew_pow_1165 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1165, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1166; + x86::Gp ret_val_get_lmul_pow_1166 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1166, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1164, ret_val_get_sew_pow_1165), ret_val_get_lmul_pow_1166)), 3, true); + setArg(call_get_pow_1164, 0, reinterpret_cast(this)); + setArg(call_get_pow_1164, 1, EEW); + setRet(call_get_pow_1164, 0, ret_val_get_pow_1164); + setArg(call_get_sew_pow_1165, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1165, 0, ret_val_get_sew_pow_1165); + setArg(call_get_lmul_pow_1166, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1166, 0, ret_val_get_lmul_pow_1166); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1168; + x86::Gp ret_val_get_lmul_pow_1168 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1168, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1167; + auto illegal_indexed_load_1167_arg4 = EMUL_pow; + auto illegal_indexed_load_1167_arg5 = ret_val_get_lmul_pow_1168; + x86::Gp ret_val_illegal_indexed_load_1167 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1167, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1167; + setArg(call_get_lmul_pow_1168, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1168, 0, ret_val_get_lmul_pow_1168); + setArg(call_illegal_indexed_load_1167, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1167, 1, vd); + setArg(call_illegal_indexed_load_1167, 2, vm); + setArg(call_illegal_indexed_load_1167, 3, 1); + setArg(call_illegal_indexed_load_1167, 4, EEW); + setArg(call_illegal_indexed_load_1167, 5, illegal_indexed_load_1167_arg4); + setArg(call_illegal_indexed_load_1167, 6, illegal_indexed_load_1167_arg5); + setRet(call_illegal_indexed_load_1167, 0, ret_val_illegal_indexed_load_1167); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1170; + x86::Gp ret_val_sew_1170 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1170, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1169; + auto vlxseg_1169_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1169_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1169_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1169_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1169_arg10 = ret_val_sew_1170; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1169 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1169, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1169, 64, false), traits::vstart); + setArg(call_sew_1170, 0, reinterpret_cast(this)); + setRet(call_sew_1170, 0, ret_val_sew_1170); + setArg(call_vlxseg_1169, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1169, 1, V); + setArg(call_vlxseg_1169, 2, vlxseg_1169_arg1); + setArg(call_vlxseg_1169, 3, vlxseg_1169_arg2); + setArg(call_vlxseg_1169, 4, vlxseg_1169_arg3); + setArg(call_vlxseg_1169, 5, vm); + setArg(call_vlxseg_1169, 6, vd); + setArg(call_vlxseg_1169, 7, vlxseg_1169_arg6); + setArg(call_vlxseg_1169, 8, vs2); + setArg(call_vlxseg_1169, 9, 1); + setArg(call_vlxseg_1169, 10, 2); + setArg(call_vlxseg_1169, 11, vlxseg_1169_arg10); + setArg(call_vlxseg_1169, 12, 1); + setRet(call_vlxseg_1169, 0, ret_val_vlxseg_1169); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 386); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 387: VLOXEI32__V */ + continuation_e __vloxei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXEI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 387); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1171; + x86::Gp ret_val_get_pow_1171 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1171, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1172; + x86::Gp ret_val_get_sew_pow_1172 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1172, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1173; + x86::Gp ret_val_get_lmul_pow_1173 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1173, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1171, ret_val_get_sew_pow_1172), ret_val_get_lmul_pow_1173)), 3, true); + setArg(call_get_pow_1171, 0, reinterpret_cast(this)); + setArg(call_get_pow_1171, 1, EEW); + setRet(call_get_pow_1171, 0, ret_val_get_pow_1171); + setArg(call_get_sew_pow_1172, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1172, 0, ret_val_get_sew_pow_1172); + setArg(call_get_lmul_pow_1173, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1173, 0, ret_val_get_lmul_pow_1173); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1175; + x86::Gp ret_val_get_lmul_pow_1175 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1175, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1174; + auto illegal_indexed_load_1174_arg4 = EMUL_pow; + auto illegal_indexed_load_1174_arg5 = ret_val_get_lmul_pow_1175; + x86::Gp ret_val_illegal_indexed_load_1174 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1174, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1174; + setArg(call_get_lmul_pow_1175, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1175, 0, ret_val_get_lmul_pow_1175); + setArg(call_illegal_indexed_load_1174, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1174, 1, vd); + setArg(call_illegal_indexed_load_1174, 2, vm); + setArg(call_illegal_indexed_load_1174, 3, 1); + setArg(call_illegal_indexed_load_1174, 4, EEW); + setArg(call_illegal_indexed_load_1174, 5, illegal_indexed_load_1174_arg4); + setArg(call_illegal_indexed_load_1174, 6, illegal_indexed_load_1174_arg5); + setRet(call_illegal_indexed_load_1174, 0, ret_val_illegal_indexed_load_1174); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1177; + x86::Gp ret_val_sew_1177 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1177, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1176; + auto vlxseg_1176_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1176_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1176_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1176_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1176_arg10 = ret_val_sew_1177; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1176 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1176, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1176, 64, false), traits::vstart); + setArg(call_sew_1177, 0, reinterpret_cast(this)); + setRet(call_sew_1177, 0, ret_val_sew_1177); + setArg(call_vlxseg_1176, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1176, 1, V); + setArg(call_vlxseg_1176, 2, vlxseg_1176_arg1); + setArg(call_vlxseg_1176, 3, vlxseg_1176_arg2); + setArg(call_vlxseg_1176, 4, vlxseg_1176_arg3); + setArg(call_vlxseg_1176, 5, vm); + setArg(call_vlxseg_1176, 6, vd); + setArg(call_vlxseg_1176, 7, vlxseg_1176_arg6); + setArg(call_vlxseg_1176, 8, vs2); + setArg(call_vlxseg_1176, 9, 1); + setArg(call_vlxseg_1176, 10, 4); + setArg(call_vlxseg_1176, 11, vlxseg_1176_arg10); + setArg(call_vlxseg_1176, 12, 1); + setRet(call_vlxseg_1176, 0, ret_val_vlxseg_1176); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 387); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 388: VLOXEI64__V */ + continuation_e __vloxei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXEI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 388); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1178; + x86::Gp ret_val_get_pow_1178 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1178, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1179; + x86::Gp ret_val_get_sew_pow_1179 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1179, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1180; + x86::Gp ret_val_get_lmul_pow_1180 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1180, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1178, ret_val_get_sew_pow_1179), ret_val_get_lmul_pow_1180)), 3, true); + setArg(call_get_pow_1178, 0, reinterpret_cast(this)); + setArg(call_get_pow_1178, 1, EEW); + setRet(call_get_pow_1178, 0, ret_val_get_pow_1178); + setArg(call_get_sew_pow_1179, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1179, 0, ret_val_get_sew_pow_1179); + setArg(call_get_lmul_pow_1180, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1180, 0, ret_val_get_lmul_pow_1180); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1182; + x86::Gp ret_val_get_lmul_pow_1182 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1182, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1181; + auto illegal_indexed_load_1181_arg4 = EMUL_pow; + auto illegal_indexed_load_1181_arg5 = ret_val_get_lmul_pow_1182; + x86::Gp ret_val_illegal_indexed_load_1181 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1181, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1181; + setArg(call_get_lmul_pow_1182, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1182, 0, ret_val_get_lmul_pow_1182); + setArg(call_illegal_indexed_load_1181, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1181, 1, vd); + setArg(call_illegal_indexed_load_1181, 2, vm); + setArg(call_illegal_indexed_load_1181, 3, 1); + setArg(call_illegal_indexed_load_1181, 4, EEW); + setArg(call_illegal_indexed_load_1181, 5, illegal_indexed_load_1181_arg4); + setArg(call_illegal_indexed_load_1181, 6, illegal_indexed_load_1181_arg5); + setRet(call_illegal_indexed_load_1181, 0, ret_val_illegal_indexed_load_1181); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1184; + x86::Gp ret_val_sew_1184 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1184, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1183; + auto vlxseg_1183_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1183_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1183_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1183_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1183_arg10 = ret_val_sew_1184; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1183 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1183, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1183, 64, false), traits::vstart); + setArg(call_sew_1184, 0, reinterpret_cast(this)); + setRet(call_sew_1184, 0, ret_val_sew_1184); + setArg(call_vlxseg_1183, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1183, 1, V); + setArg(call_vlxseg_1183, 2, vlxseg_1183_arg1); + setArg(call_vlxseg_1183, 3, vlxseg_1183_arg2); + setArg(call_vlxseg_1183, 4, vlxseg_1183_arg3); + setArg(call_vlxseg_1183, 5, vm); + setArg(call_vlxseg_1183, 6, vd); + setArg(call_vlxseg_1183, 7, vlxseg_1183_arg6); + setArg(call_vlxseg_1183, 8, vs2); + setArg(call_vlxseg_1183, 9, 1); + setArg(call_vlxseg_1183, 10, 8); + setArg(call_vlxseg_1183, 11, vlxseg_1183_arg10); + setArg(call_vlxseg_1183, 12, 1); + setRet(call_vlxseg_1183, 0, ret_val_vlxseg_1183); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 388); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 389: VLOXSEG2EI8__V */ + continuation_e __vloxseg2ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG2EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 389); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1185; + x86::Gp ret_val_get_pow_1185 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1185, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1186; + x86::Gp ret_val_get_sew_pow_1186 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1186, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1187; + x86::Gp ret_val_get_lmul_pow_1187 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1187, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1185, ret_val_get_sew_pow_1186), ret_val_get_lmul_pow_1187)), 3, true); + setArg(call_get_pow_1185, 0, reinterpret_cast(this)); + setArg(call_get_pow_1185, 1, EEW); + setRet(call_get_pow_1185, 0, ret_val_get_pow_1185); + setArg(call_get_sew_pow_1186, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1186, 0, ret_val_get_sew_pow_1186); + setArg(call_get_lmul_pow_1187, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1187, 0, ret_val_get_lmul_pow_1187); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1189; + x86::Gp ret_val_get_lmul_pow_1189 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1189, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1188; + auto illegal_indexed_load_1188_arg4 = EMUL_pow; + auto illegal_indexed_load_1188_arg5 = ret_val_get_lmul_pow_1189; + x86::Gp ret_val_illegal_indexed_load_1188 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1188, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1188; + setArg(call_get_lmul_pow_1189, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1189, 0, ret_val_get_lmul_pow_1189); + setArg(call_illegal_indexed_load_1188, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1188, 1, vd); + setArg(call_illegal_indexed_load_1188, 2, vm); + setArg(call_illegal_indexed_load_1188, 3, 2); + setArg(call_illegal_indexed_load_1188, 4, EEW); + setArg(call_illegal_indexed_load_1188, 5, illegal_indexed_load_1188_arg4); + setArg(call_illegal_indexed_load_1188, 6, illegal_indexed_load_1188_arg5); + setRet(call_illegal_indexed_load_1188, 0, ret_val_illegal_indexed_load_1188); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1191; + x86::Gp ret_val_sew_1191 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1191, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1190; + auto vlxseg_1190_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1190_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1190_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1190_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1190_arg10 = ret_val_sew_1191; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1190 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1190, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1190, 64, false), traits::vstart); + setArg(call_sew_1191, 0, reinterpret_cast(this)); + setRet(call_sew_1191, 0, ret_val_sew_1191); + setArg(call_vlxseg_1190, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1190, 1, V); + setArg(call_vlxseg_1190, 2, vlxseg_1190_arg1); + setArg(call_vlxseg_1190, 3, vlxseg_1190_arg2); + setArg(call_vlxseg_1190, 4, vlxseg_1190_arg3); + setArg(call_vlxseg_1190, 5, vm); + setArg(call_vlxseg_1190, 6, vd); + setArg(call_vlxseg_1190, 7, vlxseg_1190_arg6); + setArg(call_vlxseg_1190, 8, vs2); + setArg(call_vlxseg_1190, 9, 2); + setArg(call_vlxseg_1190, 10, 1); + setArg(call_vlxseg_1190, 11, vlxseg_1190_arg10); + setArg(call_vlxseg_1190, 12, 1); + setRet(call_vlxseg_1190, 0, ret_val_vlxseg_1190); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 389); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 390: VLOXSEG2EI16__V */ + continuation_e __vloxseg2ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG2EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 390); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1192; + x86::Gp ret_val_get_pow_1192 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1192, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1193; + x86::Gp ret_val_get_sew_pow_1193 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1193, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1194; + x86::Gp ret_val_get_lmul_pow_1194 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1194, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1192, ret_val_get_sew_pow_1193), ret_val_get_lmul_pow_1194)), 3, true); + setArg(call_get_pow_1192, 0, reinterpret_cast(this)); + setArg(call_get_pow_1192, 1, EEW); + setRet(call_get_pow_1192, 0, ret_val_get_pow_1192); + setArg(call_get_sew_pow_1193, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1193, 0, ret_val_get_sew_pow_1193); + setArg(call_get_lmul_pow_1194, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1194, 0, ret_val_get_lmul_pow_1194); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1196; + x86::Gp ret_val_get_lmul_pow_1196 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1196, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1195; + auto illegal_indexed_load_1195_arg4 = EMUL_pow; + auto illegal_indexed_load_1195_arg5 = ret_val_get_lmul_pow_1196; + x86::Gp ret_val_illegal_indexed_load_1195 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1195, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1195; + setArg(call_get_lmul_pow_1196, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1196, 0, ret_val_get_lmul_pow_1196); + setArg(call_illegal_indexed_load_1195, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1195, 1, vd); + setArg(call_illegal_indexed_load_1195, 2, vm); + setArg(call_illegal_indexed_load_1195, 3, 2); + setArg(call_illegal_indexed_load_1195, 4, EEW); + setArg(call_illegal_indexed_load_1195, 5, illegal_indexed_load_1195_arg4); + setArg(call_illegal_indexed_load_1195, 6, illegal_indexed_load_1195_arg5); + setRet(call_illegal_indexed_load_1195, 0, ret_val_illegal_indexed_load_1195); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1198; + x86::Gp ret_val_sew_1198 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1198, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1197; + auto vlxseg_1197_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1197_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1197_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1197_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1197_arg10 = ret_val_sew_1198; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1197 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1197, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1197, 64, false), traits::vstart); + setArg(call_sew_1198, 0, reinterpret_cast(this)); + setRet(call_sew_1198, 0, ret_val_sew_1198); + setArg(call_vlxseg_1197, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1197, 1, V); + setArg(call_vlxseg_1197, 2, vlxseg_1197_arg1); + setArg(call_vlxseg_1197, 3, vlxseg_1197_arg2); + setArg(call_vlxseg_1197, 4, vlxseg_1197_arg3); + setArg(call_vlxseg_1197, 5, vm); + setArg(call_vlxseg_1197, 6, vd); + setArg(call_vlxseg_1197, 7, vlxseg_1197_arg6); + setArg(call_vlxseg_1197, 8, vs2); + setArg(call_vlxseg_1197, 9, 2); + setArg(call_vlxseg_1197, 10, 2); + setArg(call_vlxseg_1197, 11, vlxseg_1197_arg10); + setArg(call_vlxseg_1197, 12, 1); + setRet(call_vlxseg_1197, 0, ret_val_vlxseg_1197); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 390); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 391: VLOXSEG2EI32__V */ + continuation_e __vloxseg2ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG2EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 391); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1199; + x86::Gp ret_val_get_pow_1199 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1199, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1200; + x86::Gp ret_val_get_sew_pow_1200 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1200, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1201; + x86::Gp ret_val_get_lmul_pow_1201 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1201, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1199, ret_val_get_sew_pow_1200), ret_val_get_lmul_pow_1201)), 3, true); + setArg(call_get_pow_1199, 0, reinterpret_cast(this)); + setArg(call_get_pow_1199, 1, EEW); + setRet(call_get_pow_1199, 0, ret_val_get_pow_1199); + setArg(call_get_sew_pow_1200, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1200, 0, ret_val_get_sew_pow_1200); + setArg(call_get_lmul_pow_1201, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1201, 0, ret_val_get_lmul_pow_1201); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1203; + x86::Gp ret_val_get_lmul_pow_1203 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1203, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1202; + auto illegal_indexed_load_1202_arg4 = EMUL_pow; + auto illegal_indexed_load_1202_arg5 = ret_val_get_lmul_pow_1203; + x86::Gp ret_val_illegal_indexed_load_1202 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1202, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1202; + setArg(call_get_lmul_pow_1203, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1203, 0, ret_val_get_lmul_pow_1203); + setArg(call_illegal_indexed_load_1202, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1202, 1, vd); + setArg(call_illegal_indexed_load_1202, 2, vm); + setArg(call_illegal_indexed_load_1202, 3, 2); + setArg(call_illegal_indexed_load_1202, 4, EEW); + setArg(call_illegal_indexed_load_1202, 5, illegal_indexed_load_1202_arg4); + setArg(call_illegal_indexed_load_1202, 6, illegal_indexed_load_1202_arg5); + setRet(call_illegal_indexed_load_1202, 0, ret_val_illegal_indexed_load_1202); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1205; + x86::Gp ret_val_sew_1205 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1205, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1204; + auto vlxseg_1204_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1204_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1204_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1204_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1204_arg10 = ret_val_sew_1205; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1204 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1204, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1204, 64, false), traits::vstart); + setArg(call_sew_1205, 0, reinterpret_cast(this)); + setRet(call_sew_1205, 0, ret_val_sew_1205); + setArg(call_vlxseg_1204, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1204, 1, V); + setArg(call_vlxseg_1204, 2, vlxseg_1204_arg1); + setArg(call_vlxseg_1204, 3, vlxseg_1204_arg2); + setArg(call_vlxseg_1204, 4, vlxseg_1204_arg3); + setArg(call_vlxseg_1204, 5, vm); + setArg(call_vlxseg_1204, 6, vd); + setArg(call_vlxseg_1204, 7, vlxseg_1204_arg6); + setArg(call_vlxseg_1204, 8, vs2); + setArg(call_vlxseg_1204, 9, 2); + setArg(call_vlxseg_1204, 10, 4); + setArg(call_vlxseg_1204, 11, vlxseg_1204_arg10); + setArg(call_vlxseg_1204, 12, 1); + setRet(call_vlxseg_1204, 0, ret_val_vlxseg_1204); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 391); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 392: VLOXSEG2EI64__V */ + continuation_e __vloxseg2ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg2ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG2EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 392); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1206; + x86::Gp ret_val_get_pow_1206 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1206, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1207; + x86::Gp ret_val_get_sew_pow_1207 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1207, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1208; + x86::Gp ret_val_get_lmul_pow_1208 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1208, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1206, ret_val_get_sew_pow_1207), ret_val_get_lmul_pow_1208)), 3, true); + setArg(call_get_pow_1206, 0, reinterpret_cast(this)); + setArg(call_get_pow_1206, 1, EEW); + setRet(call_get_pow_1206, 0, ret_val_get_pow_1206); + setArg(call_get_sew_pow_1207, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1207, 0, ret_val_get_sew_pow_1207); + setArg(call_get_lmul_pow_1208, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1208, 0, ret_val_get_lmul_pow_1208); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1210; + x86::Gp ret_val_get_lmul_pow_1210 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1210, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1209; + auto illegal_indexed_load_1209_arg4 = EMUL_pow; + auto illegal_indexed_load_1209_arg5 = ret_val_get_lmul_pow_1210; + x86::Gp ret_val_illegal_indexed_load_1209 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1209, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1209; + setArg(call_get_lmul_pow_1210, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1210, 0, ret_val_get_lmul_pow_1210); + setArg(call_illegal_indexed_load_1209, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1209, 1, vd); + setArg(call_illegal_indexed_load_1209, 2, vm); + setArg(call_illegal_indexed_load_1209, 3, 2); + setArg(call_illegal_indexed_load_1209, 4, EEW); + setArg(call_illegal_indexed_load_1209, 5, illegal_indexed_load_1209_arg4); + setArg(call_illegal_indexed_load_1209, 6, illegal_indexed_load_1209_arg5); + setRet(call_illegal_indexed_load_1209, 0, ret_val_illegal_indexed_load_1209); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1212; + x86::Gp ret_val_sew_1212 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1212, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1211; + auto vlxseg_1211_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1211_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1211_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1211_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1211_arg10 = ret_val_sew_1212; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1211 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1211, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1211, 64, false), traits::vstart); + setArg(call_sew_1212, 0, reinterpret_cast(this)); + setRet(call_sew_1212, 0, ret_val_sew_1212); + setArg(call_vlxseg_1211, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1211, 1, V); + setArg(call_vlxseg_1211, 2, vlxseg_1211_arg1); + setArg(call_vlxseg_1211, 3, vlxseg_1211_arg2); + setArg(call_vlxseg_1211, 4, vlxseg_1211_arg3); + setArg(call_vlxseg_1211, 5, vm); + setArg(call_vlxseg_1211, 6, vd); + setArg(call_vlxseg_1211, 7, vlxseg_1211_arg6); + setArg(call_vlxseg_1211, 8, vs2); + setArg(call_vlxseg_1211, 9, 2); + setArg(call_vlxseg_1211, 10, 8); + setArg(call_vlxseg_1211, 11, vlxseg_1211_arg10); + setArg(call_vlxseg_1211, 12, 1); + setRet(call_vlxseg_1211, 0, ret_val_vlxseg_1211); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 392); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 393: VLOXSEG3EI8__V */ + continuation_e __vloxseg3ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG3EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 393); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1213; + x86::Gp ret_val_get_pow_1213 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1213, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1214; + x86::Gp ret_val_get_sew_pow_1214 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1214, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1215; + x86::Gp ret_val_get_lmul_pow_1215 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1215, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1213, ret_val_get_sew_pow_1214), ret_val_get_lmul_pow_1215)), 3, true); + setArg(call_get_pow_1213, 0, reinterpret_cast(this)); + setArg(call_get_pow_1213, 1, EEW); + setRet(call_get_pow_1213, 0, ret_val_get_pow_1213); + setArg(call_get_sew_pow_1214, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1214, 0, ret_val_get_sew_pow_1214); + setArg(call_get_lmul_pow_1215, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1215, 0, ret_val_get_lmul_pow_1215); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1217; + x86::Gp ret_val_get_lmul_pow_1217 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1217, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1216; + auto illegal_indexed_load_1216_arg4 = EMUL_pow; + auto illegal_indexed_load_1216_arg5 = ret_val_get_lmul_pow_1217; + x86::Gp ret_val_illegal_indexed_load_1216 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1216, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1216; + setArg(call_get_lmul_pow_1217, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1217, 0, ret_val_get_lmul_pow_1217); + setArg(call_illegal_indexed_load_1216, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1216, 1, vd); + setArg(call_illegal_indexed_load_1216, 2, vm); + setArg(call_illegal_indexed_load_1216, 3, 3); + setArg(call_illegal_indexed_load_1216, 4, EEW); + setArg(call_illegal_indexed_load_1216, 5, illegal_indexed_load_1216_arg4); + setArg(call_illegal_indexed_load_1216, 6, illegal_indexed_load_1216_arg5); + setRet(call_illegal_indexed_load_1216, 0, ret_val_illegal_indexed_load_1216); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1219; + x86::Gp ret_val_sew_1219 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1219, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1218; + auto vlxseg_1218_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1218_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1218_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1218_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1218_arg10 = ret_val_sew_1219; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1218 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1218, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1218, 64, false), traits::vstart); + setArg(call_sew_1219, 0, reinterpret_cast(this)); + setRet(call_sew_1219, 0, ret_val_sew_1219); + setArg(call_vlxseg_1218, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1218, 1, V); + setArg(call_vlxseg_1218, 2, vlxseg_1218_arg1); + setArg(call_vlxseg_1218, 3, vlxseg_1218_arg2); + setArg(call_vlxseg_1218, 4, vlxseg_1218_arg3); + setArg(call_vlxseg_1218, 5, vm); + setArg(call_vlxseg_1218, 6, vd); + setArg(call_vlxseg_1218, 7, vlxseg_1218_arg6); + setArg(call_vlxseg_1218, 8, vs2); + setArg(call_vlxseg_1218, 9, 3); + setArg(call_vlxseg_1218, 10, 1); + setArg(call_vlxseg_1218, 11, vlxseg_1218_arg10); + setArg(call_vlxseg_1218, 12, 1); + setRet(call_vlxseg_1218, 0, ret_val_vlxseg_1218); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 393); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 394: VLOXSEG3EI16__V */ + continuation_e __vloxseg3ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG3EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 394); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1220; + x86::Gp ret_val_get_pow_1220 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1220, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1221; + x86::Gp ret_val_get_sew_pow_1221 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1221, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1222; + x86::Gp ret_val_get_lmul_pow_1222 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1222, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1220, ret_val_get_sew_pow_1221), ret_val_get_lmul_pow_1222)), 3, true); + setArg(call_get_pow_1220, 0, reinterpret_cast(this)); + setArg(call_get_pow_1220, 1, EEW); + setRet(call_get_pow_1220, 0, ret_val_get_pow_1220); + setArg(call_get_sew_pow_1221, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1221, 0, ret_val_get_sew_pow_1221); + setArg(call_get_lmul_pow_1222, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1222, 0, ret_val_get_lmul_pow_1222); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1224; + x86::Gp ret_val_get_lmul_pow_1224 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1224, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1223; + auto illegal_indexed_load_1223_arg4 = EMUL_pow; + auto illegal_indexed_load_1223_arg5 = ret_val_get_lmul_pow_1224; + x86::Gp ret_val_illegal_indexed_load_1223 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1223, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1223; + setArg(call_get_lmul_pow_1224, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1224, 0, ret_val_get_lmul_pow_1224); + setArg(call_illegal_indexed_load_1223, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1223, 1, vd); + setArg(call_illegal_indexed_load_1223, 2, vm); + setArg(call_illegal_indexed_load_1223, 3, 3); + setArg(call_illegal_indexed_load_1223, 4, EEW); + setArg(call_illegal_indexed_load_1223, 5, illegal_indexed_load_1223_arg4); + setArg(call_illegal_indexed_load_1223, 6, illegal_indexed_load_1223_arg5); + setRet(call_illegal_indexed_load_1223, 0, ret_val_illegal_indexed_load_1223); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1226; + x86::Gp ret_val_sew_1226 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1226, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1225; + auto vlxseg_1225_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1225_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1225_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1225_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1225_arg10 = ret_val_sew_1226; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1225 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1225, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1225, 64, false), traits::vstart); + setArg(call_sew_1226, 0, reinterpret_cast(this)); + setRet(call_sew_1226, 0, ret_val_sew_1226); + setArg(call_vlxseg_1225, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1225, 1, V); + setArg(call_vlxseg_1225, 2, vlxseg_1225_arg1); + setArg(call_vlxseg_1225, 3, vlxseg_1225_arg2); + setArg(call_vlxseg_1225, 4, vlxseg_1225_arg3); + setArg(call_vlxseg_1225, 5, vm); + setArg(call_vlxseg_1225, 6, vd); + setArg(call_vlxseg_1225, 7, vlxseg_1225_arg6); + setArg(call_vlxseg_1225, 8, vs2); + setArg(call_vlxseg_1225, 9, 3); + setArg(call_vlxseg_1225, 10, 2); + setArg(call_vlxseg_1225, 11, vlxseg_1225_arg10); + setArg(call_vlxseg_1225, 12, 1); + setRet(call_vlxseg_1225, 0, ret_val_vlxseg_1225); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 394); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 395: VLOXSEG3EI32__V */ + continuation_e __vloxseg3ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG3EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 395); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1227; + x86::Gp ret_val_get_pow_1227 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1227, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1228; + x86::Gp ret_val_get_sew_pow_1228 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1228, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1229; + x86::Gp ret_val_get_lmul_pow_1229 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1229, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1227, ret_val_get_sew_pow_1228), ret_val_get_lmul_pow_1229)), 3, true); + setArg(call_get_pow_1227, 0, reinterpret_cast(this)); + setArg(call_get_pow_1227, 1, EEW); + setRet(call_get_pow_1227, 0, ret_val_get_pow_1227); + setArg(call_get_sew_pow_1228, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1228, 0, ret_val_get_sew_pow_1228); + setArg(call_get_lmul_pow_1229, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1229, 0, ret_val_get_lmul_pow_1229); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1231; + x86::Gp ret_val_get_lmul_pow_1231 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1231, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1230; + auto illegal_indexed_load_1230_arg4 = EMUL_pow; + auto illegal_indexed_load_1230_arg5 = ret_val_get_lmul_pow_1231; + x86::Gp ret_val_illegal_indexed_load_1230 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1230, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1230; + setArg(call_get_lmul_pow_1231, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1231, 0, ret_val_get_lmul_pow_1231); + setArg(call_illegal_indexed_load_1230, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1230, 1, vd); + setArg(call_illegal_indexed_load_1230, 2, vm); + setArg(call_illegal_indexed_load_1230, 3, 3); + setArg(call_illegal_indexed_load_1230, 4, EEW); + setArg(call_illegal_indexed_load_1230, 5, illegal_indexed_load_1230_arg4); + setArg(call_illegal_indexed_load_1230, 6, illegal_indexed_load_1230_arg5); + setRet(call_illegal_indexed_load_1230, 0, ret_val_illegal_indexed_load_1230); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1233; + x86::Gp ret_val_sew_1233 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1233, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1232; + auto vlxseg_1232_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1232_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1232_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1232_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1232_arg10 = ret_val_sew_1233; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1232 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1232, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1232, 64, false), traits::vstart); + setArg(call_sew_1233, 0, reinterpret_cast(this)); + setRet(call_sew_1233, 0, ret_val_sew_1233); + setArg(call_vlxseg_1232, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1232, 1, V); + setArg(call_vlxseg_1232, 2, vlxseg_1232_arg1); + setArg(call_vlxseg_1232, 3, vlxseg_1232_arg2); + setArg(call_vlxseg_1232, 4, vlxseg_1232_arg3); + setArg(call_vlxseg_1232, 5, vm); + setArg(call_vlxseg_1232, 6, vd); + setArg(call_vlxseg_1232, 7, vlxseg_1232_arg6); + setArg(call_vlxseg_1232, 8, vs2); + setArg(call_vlxseg_1232, 9, 3); + setArg(call_vlxseg_1232, 10, 4); + setArg(call_vlxseg_1232, 11, vlxseg_1232_arg10); + setArg(call_vlxseg_1232, 12, 1); + setRet(call_vlxseg_1232, 0, ret_val_vlxseg_1232); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 395); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 396: VLOXSEG3EI64__V */ + continuation_e __vloxseg3ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg3ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG3EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 396); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1234; + x86::Gp ret_val_get_pow_1234 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1234, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1235; + x86::Gp ret_val_get_sew_pow_1235 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1235, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1236; + x86::Gp ret_val_get_lmul_pow_1236 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1236, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1234, ret_val_get_sew_pow_1235), ret_val_get_lmul_pow_1236)), 3, true); + setArg(call_get_pow_1234, 0, reinterpret_cast(this)); + setArg(call_get_pow_1234, 1, EEW); + setRet(call_get_pow_1234, 0, ret_val_get_pow_1234); + setArg(call_get_sew_pow_1235, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1235, 0, ret_val_get_sew_pow_1235); + setArg(call_get_lmul_pow_1236, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1236, 0, ret_val_get_lmul_pow_1236); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1238; + x86::Gp ret_val_get_lmul_pow_1238 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1238, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1237; + auto illegal_indexed_load_1237_arg4 = EMUL_pow; + auto illegal_indexed_load_1237_arg5 = ret_val_get_lmul_pow_1238; + x86::Gp ret_val_illegal_indexed_load_1237 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1237, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1237; + setArg(call_get_lmul_pow_1238, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1238, 0, ret_val_get_lmul_pow_1238); + setArg(call_illegal_indexed_load_1237, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1237, 1, vd); + setArg(call_illegal_indexed_load_1237, 2, vm); + setArg(call_illegal_indexed_load_1237, 3, 3); + setArg(call_illegal_indexed_load_1237, 4, EEW); + setArg(call_illegal_indexed_load_1237, 5, illegal_indexed_load_1237_arg4); + setArg(call_illegal_indexed_load_1237, 6, illegal_indexed_load_1237_arg5); + setRet(call_illegal_indexed_load_1237, 0, ret_val_illegal_indexed_load_1237); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1240; + x86::Gp ret_val_sew_1240 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1240, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1239; + auto vlxseg_1239_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1239_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1239_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1239_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1239_arg10 = ret_val_sew_1240; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1239 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1239, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1239, 64, false), traits::vstart); + setArg(call_sew_1240, 0, reinterpret_cast(this)); + setRet(call_sew_1240, 0, ret_val_sew_1240); + setArg(call_vlxseg_1239, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1239, 1, V); + setArg(call_vlxseg_1239, 2, vlxseg_1239_arg1); + setArg(call_vlxseg_1239, 3, vlxseg_1239_arg2); + setArg(call_vlxseg_1239, 4, vlxseg_1239_arg3); + setArg(call_vlxseg_1239, 5, vm); + setArg(call_vlxseg_1239, 6, vd); + setArg(call_vlxseg_1239, 7, vlxseg_1239_arg6); + setArg(call_vlxseg_1239, 8, vs2); + setArg(call_vlxseg_1239, 9, 3); + setArg(call_vlxseg_1239, 10, 8); + setArg(call_vlxseg_1239, 11, vlxseg_1239_arg10); + setArg(call_vlxseg_1239, 12, 1); + setRet(call_vlxseg_1239, 0, ret_val_vlxseg_1239); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 396); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 397: VLOXSEG4EI8__V */ + continuation_e __vloxseg4ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG4EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 397); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1241; + x86::Gp ret_val_get_pow_1241 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1241, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1242; + x86::Gp ret_val_get_sew_pow_1242 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1242, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1243; + x86::Gp ret_val_get_lmul_pow_1243 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1243, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1241, ret_val_get_sew_pow_1242), ret_val_get_lmul_pow_1243)), 3, true); + setArg(call_get_pow_1241, 0, reinterpret_cast(this)); + setArg(call_get_pow_1241, 1, EEW); + setRet(call_get_pow_1241, 0, ret_val_get_pow_1241); + setArg(call_get_sew_pow_1242, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1242, 0, ret_val_get_sew_pow_1242); + setArg(call_get_lmul_pow_1243, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1243, 0, ret_val_get_lmul_pow_1243); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1245; + x86::Gp ret_val_get_lmul_pow_1245 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1245, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1244; + auto illegal_indexed_load_1244_arg4 = EMUL_pow; + auto illegal_indexed_load_1244_arg5 = ret_val_get_lmul_pow_1245; + x86::Gp ret_val_illegal_indexed_load_1244 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1244, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1244; + setArg(call_get_lmul_pow_1245, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1245, 0, ret_val_get_lmul_pow_1245); + setArg(call_illegal_indexed_load_1244, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1244, 1, vd); + setArg(call_illegal_indexed_load_1244, 2, vm); + setArg(call_illegal_indexed_load_1244, 3, 4); + setArg(call_illegal_indexed_load_1244, 4, EEW); + setArg(call_illegal_indexed_load_1244, 5, illegal_indexed_load_1244_arg4); + setArg(call_illegal_indexed_load_1244, 6, illegal_indexed_load_1244_arg5); + setRet(call_illegal_indexed_load_1244, 0, ret_val_illegal_indexed_load_1244); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1247; + x86::Gp ret_val_sew_1247 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1247, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1246; + auto vlxseg_1246_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1246_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1246_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1246_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1246_arg10 = ret_val_sew_1247; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1246 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1246, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1246, 64, false), traits::vstart); + setArg(call_sew_1247, 0, reinterpret_cast(this)); + setRet(call_sew_1247, 0, ret_val_sew_1247); + setArg(call_vlxseg_1246, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1246, 1, V); + setArg(call_vlxseg_1246, 2, vlxseg_1246_arg1); + setArg(call_vlxseg_1246, 3, vlxseg_1246_arg2); + setArg(call_vlxseg_1246, 4, vlxseg_1246_arg3); + setArg(call_vlxseg_1246, 5, vm); + setArg(call_vlxseg_1246, 6, vd); + setArg(call_vlxseg_1246, 7, vlxseg_1246_arg6); + setArg(call_vlxseg_1246, 8, vs2); + setArg(call_vlxseg_1246, 9, 4); + setArg(call_vlxseg_1246, 10, 1); + setArg(call_vlxseg_1246, 11, vlxseg_1246_arg10); + setArg(call_vlxseg_1246, 12, 1); + setRet(call_vlxseg_1246, 0, ret_val_vlxseg_1246); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 397); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 398: VLOXSEG4EI16__V */ + continuation_e __vloxseg4ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG4EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 398); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1248; + x86::Gp ret_val_get_pow_1248 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1248, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1249; + x86::Gp ret_val_get_sew_pow_1249 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1249, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1250; + x86::Gp ret_val_get_lmul_pow_1250 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1250, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1248, ret_val_get_sew_pow_1249), ret_val_get_lmul_pow_1250)), 3, true); + setArg(call_get_pow_1248, 0, reinterpret_cast(this)); + setArg(call_get_pow_1248, 1, EEW); + setRet(call_get_pow_1248, 0, ret_val_get_pow_1248); + setArg(call_get_sew_pow_1249, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1249, 0, ret_val_get_sew_pow_1249); + setArg(call_get_lmul_pow_1250, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1250, 0, ret_val_get_lmul_pow_1250); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1252; + x86::Gp ret_val_get_lmul_pow_1252 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1252, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1251; + auto illegal_indexed_load_1251_arg4 = EMUL_pow; + auto illegal_indexed_load_1251_arg5 = ret_val_get_lmul_pow_1252; + x86::Gp ret_val_illegal_indexed_load_1251 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1251, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1251; + setArg(call_get_lmul_pow_1252, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1252, 0, ret_val_get_lmul_pow_1252); + setArg(call_illegal_indexed_load_1251, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1251, 1, vd); + setArg(call_illegal_indexed_load_1251, 2, vm); + setArg(call_illegal_indexed_load_1251, 3, 4); + setArg(call_illegal_indexed_load_1251, 4, EEW); + setArg(call_illegal_indexed_load_1251, 5, illegal_indexed_load_1251_arg4); + setArg(call_illegal_indexed_load_1251, 6, illegal_indexed_load_1251_arg5); + setRet(call_illegal_indexed_load_1251, 0, ret_val_illegal_indexed_load_1251); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1254; + x86::Gp ret_val_sew_1254 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1254, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1253; + auto vlxseg_1253_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1253_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1253_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1253_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1253_arg10 = ret_val_sew_1254; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1253 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1253, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1253, 64, false), traits::vstart); + setArg(call_sew_1254, 0, reinterpret_cast(this)); + setRet(call_sew_1254, 0, ret_val_sew_1254); + setArg(call_vlxseg_1253, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1253, 1, V); + setArg(call_vlxseg_1253, 2, vlxseg_1253_arg1); + setArg(call_vlxseg_1253, 3, vlxseg_1253_arg2); + setArg(call_vlxseg_1253, 4, vlxseg_1253_arg3); + setArg(call_vlxseg_1253, 5, vm); + setArg(call_vlxseg_1253, 6, vd); + setArg(call_vlxseg_1253, 7, vlxseg_1253_arg6); + setArg(call_vlxseg_1253, 8, vs2); + setArg(call_vlxseg_1253, 9, 4); + setArg(call_vlxseg_1253, 10, 2); + setArg(call_vlxseg_1253, 11, vlxseg_1253_arg10); + setArg(call_vlxseg_1253, 12, 1); + setRet(call_vlxseg_1253, 0, ret_val_vlxseg_1253); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 398); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 399: VLOXSEG4EI32__V */ + continuation_e __vloxseg4ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG4EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 399); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1255; + x86::Gp ret_val_get_pow_1255 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1255, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1256; + x86::Gp ret_val_get_sew_pow_1256 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1256, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1257; + x86::Gp ret_val_get_lmul_pow_1257 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1257, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1255, ret_val_get_sew_pow_1256), ret_val_get_lmul_pow_1257)), 3, true); + setArg(call_get_pow_1255, 0, reinterpret_cast(this)); + setArg(call_get_pow_1255, 1, EEW); + setRet(call_get_pow_1255, 0, ret_val_get_pow_1255); + setArg(call_get_sew_pow_1256, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1256, 0, ret_val_get_sew_pow_1256); + setArg(call_get_lmul_pow_1257, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1257, 0, ret_val_get_lmul_pow_1257); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1259; + x86::Gp ret_val_get_lmul_pow_1259 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1259, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1258; + auto illegal_indexed_load_1258_arg4 = EMUL_pow; + auto illegal_indexed_load_1258_arg5 = ret_val_get_lmul_pow_1259; + x86::Gp ret_val_illegal_indexed_load_1258 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1258, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1258; + setArg(call_get_lmul_pow_1259, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1259, 0, ret_val_get_lmul_pow_1259); + setArg(call_illegal_indexed_load_1258, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1258, 1, vd); + setArg(call_illegal_indexed_load_1258, 2, vm); + setArg(call_illegal_indexed_load_1258, 3, 4); + setArg(call_illegal_indexed_load_1258, 4, EEW); + setArg(call_illegal_indexed_load_1258, 5, illegal_indexed_load_1258_arg4); + setArg(call_illegal_indexed_load_1258, 6, illegal_indexed_load_1258_arg5); + setRet(call_illegal_indexed_load_1258, 0, ret_val_illegal_indexed_load_1258); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1261; + x86::Gp ret_val_sew_1261 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1261, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1260; + auto vlxseg_1260_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1260_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1260_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1260_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1260_arg10 = ret_val_sew_1261; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1260 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1260, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1260, 64, false), traits::vstart); + setArg(call_sew_1261, 0, reinterpret_cast(this)); + setRet(call_sew_1261, 0, ret_val_sew_1261); + setArg(call_vlxseg_1260, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1260, 1, V); + setArg(call_vlxseg_1260, 2, vlxseg_1260_arg1); + setArg(call_vlxseg_1260, 3, vlxseg_1260_arg2); + setArg(call_vlxseg_1260, 4, vlxseg_1260_arg3); + setArg(call_vlxseg_1260, 5, vm); + setArg(call_vlxseg_1260, 6, vd); + setArg(call_vlxseg_1260, 7, vlxseg_1260_arg6); + setArg(call_vlxseg_1260, 8, vs2); + setArg(call_vlxseg_1260, 9, 4); + setArg(call_vlxseg_1260, 10, 4); + setArg(call_vlxseg_1260, 11, vlxseg_1260_arg10); + setArg(call_vlxseg_1260, 12, 1); + setRet(call_vlxseg_1260, 0, ret_val_vlxseg_1260); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 399); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 400: VLOXSEG4EI64__V */ + continuation_e __vloxseg4ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg4ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG4EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 400); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1262; + x86::Gp ret_val_get_pow_1262 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1262, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1263; + x86::Gp ret_val_get_sew_pow_1263 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1263, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1264; + x86::Gp ret_val_get_lmul_pow_1264 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1264, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1262, ret_val_get_sew_pow_1263), ret_val_get_lmul_pow_1264)), 3, true); + setArg(call_get_pow_1262, 0, reinterpret_cast(this)); + setArg(call_get_pow_1262, 1, EEW); + setRet(call_get_pow_1262, 0, ret_val_get_pow_1262); + setArg(call_get_sew_pow_1263, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1263, 0, ret_val_get_sew_pow_1263); + setArg(call_get_lmul_pow_1264, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1264, 0, ret_val_get_lmul_pow_1264); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1266; + x86::Gp ret_val_get_lmul_pow_1266 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1266, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1265; + auto illegal_indexed_load_1265_arg4 = EMUL_pow; + auto illegal_indexed_load_1265_arg5 = ret_val_get_lmul_pow_1266; + x86::Gp ret_val_illegal_indexed_load_1265 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1265, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1265; + setArg(call_get_lmul_pow_1266, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1266, 0, ret_val_get_lmul_pow_1266); + setArg(call_illegal_indexed_load_1265, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1265, 1, vd); + setArg(call_illegal_indexed_load_1265, 2, vm); + setArg(call_illegal_indexed_load_1265, 3, 4); + setArg(call_illegal_indexed_load_1265, 4, EEW); + setArg(call_illegal_indexed_load_1265, 5, illegal_indexed_load_1265_arg4); + setArg(call_illegal_indexed_load_1265, 6, illegal_indexed_load_1265_arg5); + setRet(call_illegal_indexed_load_1265, 0, ret_val_illegal_indexed_load_1265); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1268; + x86::Gp ret_val_sew_1268 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1268, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1267; + auto vlxseg_1267_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1267_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1267_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1267_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1267_arg10 = ret_val_sew_1268; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1267 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1267, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1267, 64, false), traits::vstart); + setArg(call_sew_1268, 0, reinterpret_cast(this)); + setRet(call_sew_1268, 0, ret_val_sew_1268); + setArg(call_vlxseg_1267, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1267, 1, V); + setArg(call_vlxseg_1267, 2, vlxseg_1267_arg1); + setArg(call_vlxseg_1267, 3, vlxseg_1267_arg2); + setArg(call_vlxseg_1267, 4, vlxseg_1267_arg3); + setArg(call_vlxseg_1267, 5, vm); + setArg(call_vlxseg_1267, 6, vd); + setArg(call_vlxseg_1267, 7, vlxseg_1267_arg6); + setArg(call_vlxseg_1267, 8, vs2); + setArg(call_vlxseg_1267, 9, 4); + setArg(call_vlxseg_1267, 10, 8); + setArg(call_vlxseg_1267, 11, vlxseg_1267_arg10); + setArg(call_vlxseg_1267, 12, 1); + setRet(call_vlxseg_1267, 0, ret_val_vlxseg_1267); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 400); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 401: VLOXSEG5EI8__V */ + continuation_e __vloxseg5ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG5EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 401); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1269; + x86::Gp ret_val_get_pow_1269 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1269, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1270; + x86::Gp ret_val_get_sew_pow_1270 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1270, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1271; + x86::Gp ret_val_get_lmul_pow_1271 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1271, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1269, ret_val_get_sew_pow_1270), ret_val_get_lmul_pow_1271)), 3, true); + setArg(call_get_pow_1269, 0, reinterpret_cast(this)); + setArg(call_get_pow_1269, 1, EEW); + setRet(call_get_pow_1269, 0, ret_val_get_pow_1269); + setArg(call_get_sew_pow_1270, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1270, 0, ret_val_get_sew_pow_1270); + setArg(call_get_lmul_pow_1271, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1271, 0, ret_val_get_lmul_pow_1271); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1273; + x86::Gp ret_val_get_lmul_pow_1273 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1273, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1272; + auto illegal_indexed_load_1272_arg4 = EMUL_pow; + auto illegal_indexed_load_1272_arg5 = ret_val_get_lmul_pow_1273; + x86::Gp ret_val_illegal_indexed_load_1272 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1272, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1272; + setArg(call_get_lmul_pow_1273, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1273, 0, ret_val_get_lmul_pow_1273); + setArg(call_illegal_indexed_load_1272, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1272, 1, vd); + setArg(call_illegal_indexed_load_1272, 2, vm); + setArg(call_illegal_indexed_load_1272, 3, 5); + setArg(call_illegal_indexed_load_1272, 4, EEW); + setArg(call_illegal_indexed_load_1272, 5, illegal_indexed_load_1272_arg4); + setArg(call_illegal_indexed_load_1272, 6, illegal_indexed_load_1272_arg5); + setRet(call_illegal_indexed_load_1272, 0, ret_val_illegal_indexed_load_1272); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1275; + x86::Gp ret_val_sew_1275 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1275, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1274; + auto vlxseg_1274_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1274_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1274_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1274_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1274_arg10 = ret_val_sew_1275; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1274 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1274, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1274, 64, false), traits::vstart); + setArg(call_sew_1275, 0, reinterpret_cast(this)); + setRet(call_sew_1275, 0, ret_val_sew_1275); + setArg(call_vlxseg_1274, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1274, 1, V); + setArg(call_vlxseg_1274, 2, vlxseg_1274_arg1); + setArg(call_vlxseg_1274, 3, vlxseg_1274_arg2); + setArg(call_vlxseg_1274, 4, vlxseg_1274_arg3); + setArg(call_vlxseg_1274, 5, vm); + setArg(call_vlxseg_1274, 6, vd); + setArg(call_vlxseg_1274, 7, vlxseg_1274_arg6); + setArg(call_vlxseg_1274, 8, vs2); + setArg(call_vlxseg_1274, 9, 5); + setArg(call_vlxseg_1274, 10, 1); + setArg(call_vlxseg_1274, 11, vlxseg_1274_arg10); + setArg(call_vlxseg_1274, 12, 1); + setRet(call_vlxseg_1274, 0, ret_val_vlxseg_1274); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 401); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 402: VLOXSEG5EI16__V */ + continuation_e __vloxseg5ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG5EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 402); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1276; + x86::Gp ret_val_get_pow_1276 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1276, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1277; + x86::Gp ret_val_get_sew_pow_1277 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1277, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1278; + x86::Gp ret_val_get_lmul_pow_1278 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1278, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1276, ret_val_get_sew_pow_1277), ret_val_get_lmul_pow_1278)), 3, true); + setArg(call_get_pow_1276, 0, reinterpret_cast(this)); + setArg(call_get_pow_1276, 1, EEW); + setRet(call_get_pow_1276, 0, ret_val_get_pow_1276); + setArg(call_get_sew_pow_1277, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1277, 0, ret_val_get_sew_pow_1277); + setArg(call_get_lmul_pow_1278, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1278, 0, ret_val_get_lmul_pow_1278); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1280; + x86::Gp ret_val_get_lmul_pow_1280 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1280, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1279; + auto illegal_indexed_load_1279_arg4 = EMUL_pow; + auto illegal_indexed_load_1279_arg5 = ret_val_get_lmul_pow_1280; + x86::Gp ret_val_illegal_indexed_load_1279 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1279, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1279; + setArg(call_get_lmul_pow_1280, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1280, 0, ret_val_get_lmul_pow_1280); + setArg(call_illegal_indexed_load_1279, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1279, 1, vd); + setArg(call_illegal_indexed_load_1279, 2, vm); + setArg(call_illegal_indexed_load_1279, 3, 5); + setArg(call_illegal_indexed_load_1279, 4, EEW); + setArg(call_illegal_indexed_load_1279, 5, illegal_indexed_load_1279_arg4); + setArg(call_illegal_indexed_load_1279, 6, illegal_indexed_load_1279_arg5); + setRet(call_illegal_indexed_load_1279, 0, ret_val_illegal_indexed_load_1279); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1282; + x86::Gp ret_val_sew_1282 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1282, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1281; + auto vlxseg_1281_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1281_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1281_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1281_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1281_arg10 = ret_val_sew_1282; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1281 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1281, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1281, 64, false), traits::vstart); + setArg(call_sew_1282, 0, reinterpret_cast(this)); + setRet(call_sew_1282, 0, ret_val_sew_1282); + setArg(call_vlxseg_1281, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1281, 1, V); + setArg(call_vlxseg_1281, 2, vlxseg_1281_arg1); + setArg(call_vlxseg_1281, 3, vlxseg_1281_arg2); + setArg(call_vlxseg_1281, 4, vlxseg_1281_arg3); + setArg(call_vlxseg_1281, 5, vm); + setArg(call_vlxseg_1281, 6, vd); + setArg(call_vlxseg_1281, 7, vlxseg_1281_arg6); + setArg(call_vlxseg_1281, 8, vs2); + setArg(call_vlxseg_1281, 9, 5); + setArg(call_vlxseg_1281, 10, 2); + setArg(call_vlxseg_1281, 11, vlxseg_1281_arg10); + setArg(call_vlxseg_1281, 12, 1); + setRet(call_vlxseg_1281, 0, ret_val_vlxseg_1281); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 402); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 403: VLOXSEG5EI32__V */ + continuation_e __vloxseg5ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG5EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 403); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1283; + x86::Gp ret_val_get_pow_1283 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1283, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1284; + x86::Gp ret_val_get_sew_pow_1284 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1284, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1285; + x86::Gp ret_val_get_lmul_pow_1285 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1285, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1283, ret_val_get_sew_pow_1284), ret_val_get_lmul_pow_1285)), 3, true); + setArg(call_get_pow_1283, 0, reinterpret_cast(this)); + setArg(call_get_pow_1283, 1, EEW); + setRet(call_get_pow_1283, 0, ret_val_get_pow_1283); + setArg(call_get_sew_pow_1284, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1284, 0, ret_val_get_sew_pow_1284); + setArg(call_get_lmul_pow_1285, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1285, 0, ret_val_get_lmul_pow_1285); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1287; + x86::Gp ret_val_get_lmul_pow_1287 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1287, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1286; + auto illegal_indexed_load_1286_arg4 = EMUL_pow; + auto illegal_indexed_load_1286_arg5 = ret_val_get_lmul_pow_1287; + x86::Gp ret_val_illegal_indexed_load_1286 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1286, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1286; + setArg(call_get_lmul_pow_1287, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1287, 0, ret_val_get_lmul_pow_1287); + setArg(call_illegal_indexed_load_1286, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1286, 1, vd); + setArg(call_illegal_indexed_load_1286, 2, vm); + setArg(call_illegal_indexed_load_1286, 3, 5); + setArg(call_illegal_indexed_load_1286, 4, EEW); + setArg(call_illegal_indexed_load_1286, 5, illegal_indexed_load_1286_arg4); + setArg(call_illegal_indexed_load_1286, 6, illegal_indexed_load_1286_arg5); + setRet(call_illegal_indexed_load_1286, 0, ret_val_illegal_indexed_load_1286); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1289; + x86::Gp ret_val_sew_1289 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1289, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1288; + auto vlxseg_1288_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1288_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1288_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1288_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1288_arg10 = ret_val_sew_1289; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1288 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1288, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1288, 64, false), traits::vstart); + setArg(call_sew_1289, 0, reinterpret_cast(this)); + setRet(call_sew_1289, 0, ret_val_sew_1289); + setArg(call_vlxseg_1288, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1288, 1, V); + setArg(call_vlxseg_1288, 2, vlxseg_1288_arg1); + setArg(call_vlxseg_1288, 3, vlxseg_1288_arg2); + setArg(call_vlxseg_1288, 4, vlxseg_1288_arg3); + setArg(call_vlxseg_1288, 5, vm); + setArg(call_vlxseg_1288, 6, vd); + setArg(call_vlxseg_1288, 7, vlxseg_1288_arg6); + setArg(call_vlxseg_1288, 8, vs2); + setArg(call_vlxseg_1288, 9, 5); + setArg(call_vlxseg_1288, 10, 4); + setArg(call_vlxseg_1288, 11, vlxseg_1288_arg10); + setArg(call_vlxseg_1288, 12, 1); + setRet(call_vlxseg_1288, 0, ret_val_vlxseg_1288); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 403); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 404: VLOXSEG5EI64__V */ + continuation_e __vloxseg5ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg5ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG5EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 404); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1290; + x86::Gp ret_val_get_pow_1290 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1290, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1291; + x86::Gp ret_val_get_sew_pow_1291 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1291, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1292; + x86::Gp ret_val_get_lmul_pow_1292 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1292, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1290, ret_val_get_sew_pow_1291), ret_val_get_lmul_pow_1292)), 3, true); + setArg(call_get_pow_1290, 0, reinterpret_cast(this)); + setArg(call_get_pow_1290, 1, EEW); + setRet(call_get_pow_1290, 0, ret_val_get_pow_1290); + setArg(call_get_sew_pow_1291, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1291, 0, ret_val_get_sew_pow_1291); + setArg(call_get_lmul_pow_1292, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1292, 0, ret_val_get_lmul_pow_1292); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1294; + x86::Gp ret_val_get_lmul_pow_1294 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1294, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1293; + auto illegal_indexed_load_1293_arg4 = EMUL_pow; + auto illegal_indexed_load_1293_arg5 = ret_val_get_lmul_pow_1294; + x86::Gp ret_val_illegal_indexed_load_1293 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1293, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1293; + setArg(call_get_lmul_pow_1294, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1294, 0, ret_val_get_lmul_pow_1294); + setArg(call_illegal_indexed_load_1293, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1293, 1, vd); + setArg(call_illegal_indexed_load_1293, 2, vm); + setArg(call_illegal_indexed_load_1293, 3, 5); + setArg(call_illegal_indexed_load_1293, 4, EEW); + setArg(call_illegal_indexed_load_1293, 5, illegal_indexed_load_1293_arg4); + setArg(call_illegal_indexed_load_1293, 6, illegal_indexed_load_1293_arg5); + setRet(call_illegal_indexed_load_1293, 0, ret_val_illegal_indexed_load_1293); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1296; + x86::Gp ret_val_sew_1296 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1296, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1295; + auto vlxseg_1295_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1295_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1295_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1295_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1295_arg10 = ret_val_sew_1296; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1295 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1295, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1295, 64, false), traits::vstart); + setArg(call_sew_1296, 0, reinterpret_cast(this)); + setRet(call_sew_1296, 0, ret_val_sew_1296); + setArg(call_vlxseg_1295, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1295, 1, V); + setArg(call_vlxseg_1295, 2, vlxseg_1295_arg1); + setArg(call_vlxseg_1295, 3, vlxseg_1295_arg2); + setArg(call_vlxseg_1295, 4, vlxseg_1295_arg3); + setArg(call_vlxseg_1295, 5, vm); + setArg(call_vlxseg_1295, 6, vd); + setArg(call_vlxseg_1295, 7, vlxseg_1295_arg6); + setArg(call_vlxseg_1295, 8, vs2); + setArg(call_vlxseg_1295, 9, 5); + setArg(call_vlxseg_1295, 10, 8); + setArg(call_vlxseg_1295, 11, vlxseg_1295_arg10); + setArg(call_vlxseg_1295, 12, 1); + setRet(call_vlxseg_1295, 0, ret_val_vlxseg_1295); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 404); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 405: VLOXSEG6EI8__V */ + continuation_e __vloxseg6ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG6EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 405); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1297; + x86::Gp ret_val_get_pow_1297 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1297, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1298; + x86::Gp ret_val_get_sew_pow_1298 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1298, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1299; + x86::Gp ret_val_get_lmul_pow_1299 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1299, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1297, ret_val_get_sew_pow_1298), ret_val_get_lmul_pow_1299)), 3, true); + setArg(call_get_pow_1297, 0, reinterpret_cast(this)); + setArg(call_get_pow_1297, 1, EEW); + setRet(call_get_pow_1297, 0, ret_val_get_pow_1297); + setArg(call_get_sew_pow_1298, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1298, 0, ret_val_get_sew_pow_1298); + setArg(call_get_lmul_pow_1299, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1299, 0, ret_val_get_lmul_pow_1299); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1301; + x86::Gp ret_val_get_lmul_pow_1301 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1301, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1300; + auto illegal_indexed_load_1300_arg4 = EMUL_pow; + auto illegal_indexed_load_1300_arg5 = ret_val_get_lmul_pow_1301; + x86::Gp ret_val_illegal_indexed_load_1300 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1300, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1300; + setArg(call_get_lmul_pow_1301, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1301, 0, ret_val_get_lmul_pow_1301); + setArg(call_illegal_indexed_load_1300, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1300, 1, vd); + setArg(call_illegal_indexed_load_1300, 2, vm); + setArg(call_illegal_indexed_load_1300, 3, 6); + setArg(call_illegal_indexed_load_1300, 4, EEW); + setArg(call_illegal_indexed_load_1300, 5, illegal_indexed_load_1300_arg4); + setArg(call_illegal_indexed_load_1300, 6, illegal_indexed_load_1300_arg5); + setRet(call_illegal_indexed_load_1300, 0, ret_val_illegal_indexed_load_1300); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1303; + x86::Gp ret_val_sew_1303 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1303, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1302; + auto vlxseg_1302_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1302_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1302_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1302_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1302_arg10 = ret_val_sew_1303; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1302 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1302, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1302, 64, false), traits::vstart); + setArg(call_sew_1303, 0, reinterpret_cast(this)); + setRet(call_sew_1303, 0, ret_val_sew_1303); + setArg(call_vlxseg_1302, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1302, 1, V); + setArg(call_vlxseg_1302, 2, vlxseg_1302_arg1); + setArg(call_vlxseg_1302, 3, vlxseg_1302_arg2); + setArg(call_vlxseg_1302, 4, vlxseg_1302_arg3); + setArg(call_vlxseg_1302, 5, vm); + setArg(call_vlxseg_1302, 6, vd); + setArg(call_vlxseg_1302, 7, vlxseg_1302_arg6); + setArg(call_vlxseg_1302, 8, vs2); + setArg(call_vlxseg_1302, 9, 6); + setArg(call_vlxseg_1302, 10, 1); + setArg(call_vlxseg_1302, 11, vlxseg_1302_arg10); + setArg(call_vlxseg_1302, 12, 1); + setRet(call_vlxseg_1302, 0, ret_val_vlxseg_1302); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 405); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 406: VLOXSEG6EI16__V */ + continuation_e __vloxseg6ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG6EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 406); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1304; + x86::Gp ret_val_get_pow_1304 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1304, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1305; + x86::Gp ret_val_get_sew_pow_1305 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1305, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1306; + x86::Gp ret_val_get_lmul_pow_1306 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1306, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1304, ret_val_get_sew_pow_1305), ret_val_get_lmul_pow_1306)), 3, true); + setArg(call_get_pow_1304, 0, reinterpret_cast(this)); + setArg(call_get_pow_1304, 1, EEW); + setRet(call_get_pow_1304, 0, ret_val_get_pow_1304); + setArg(call_get_sew_pow_1305, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1305, 0, ret_val_get_sew_pow_1305); + setArg(call_get_lmul_pow_1306, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1306, 0, ret_val_get_lmul_pow_1306); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1308; + x86::Gp ret_val_get_lmul_pow_1308 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1308, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1307; + auto illegal_indexed_load_1307_arg4 = EMUL_pow; + auto illegal_indexed_load_1307_arg5 = ret_val_get_lmul_pow_1308; + x86::Gp ret_val_illegal_indexed_load_1307 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1307, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1307; + setArg(call_get_lmul_pow_1308, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1308, 0, ret_val_get_lmul_pow_1308); + setArg(call_illegal_indexed_load_1307, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1307, 1, vd); + setArg(call_illegal_indexed_load_1307, 2, vm); + setArg(call_illegal_indexed_load_1307, 3, 6); + setArg(call_illegal_indexed_load_1307, 4, EEW); + setArg(call_illegal_indexed_load_1307, 5, illegal_indexed_load_1307_arg4); + setArg(call_illegal_indexed_load_1307, 6, illegal_indexed_load_1307_arg5); + setRet(call_illegal_indexed_load_1307, 0, ret_val_illegal_indexed_load_1307); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1310; + x86::Gp ret_val_sew_1310 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1310, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1309; + auto vlxseg_1309_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1309_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1309_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1309_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1309_arg10 = ret_val_sew_1310; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1309 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1309, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1309, 64, false), traits::vstart); + setArg(call_sew_1310, 0, reinterpret_cast(this)); + setRet(call_sew_1310, 0, ret_val_sew_1310); + setArg(call_vlxseg_1309, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1309, 1, V); + setArg(call_vlxseg_1309, 2, vlxseg_1309_arg1); + setArg(call_vlxseg_1309, 3, vlxseg_1309_arg2); + setArg(call_vlxseg_1309, 4, vlxseg_1309_arg3); + setArg(call_vlxseg_1309, 5, vm); + setArg(call_vlxseg_1309, 6, vd); + setArg(call_vlxseg_1309, 7, vlxseg_1309_arg6); + setArg(call_vlxseg_1309, 8, vs2); + setArg(call_vlxseg_1309, 9, 6); + setArg(call_vlxseg_1309, 10, 2); + setArg(call_vlxseg_1309, 11, vlxseg_1309_arg10); + setArg(call_vlxseg_1309, 12, 1); + setRet(call_vlxseg_1309, 0, ret_val_vlxseg_1309); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 406); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 407: VLOXSEG6EI32__V */ + continuation_e __vloxseg6ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG6EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 407); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1311; + x86::Gp ret_val_get_pow_1311 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1311, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1312; + x86::Gp ret_val_get_sew_pow_1312 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1312, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1313; + x86::Gp ret_val_get_lmul_pow_1313 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1313, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1311, ret_val_get_sew_pow_1312), ret_val_get_lmul_pow_1313)), 3, true); + setArg(call_get_pow_1311, 0, reinterpret_cast(this)); + setArg(call_get_pow_1311, 1, EEW); + setRet(call_get_pow_1311, 0, ret_val_get_pow_1311); + setArg(call_get_sew_pow_1312, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1312, 0, ret_val_get_sew_pow_1312); + setArg(call_get_lmul_pow_1313, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1313, 0, ret_val_get_lmul_pow_1313); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1315; + x86::Gp ret_val_get_lmul_pow_1315 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1315, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1314; + auto illegal_indexed_load_1314_arg4 = EMUL_pow; + auto illegal_indexed_load_1314_arg5 = ret_val_get_lmul_pow_1315; + x86::Gp ret_val_illegal_indexed_load_1314 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1314, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1314; + setArg(call_get_lmul_pow_1315, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1315, 0, ret_val_get_lmul_pow_1315); + setArg(call_illegal_indexed_load_1314, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1314, 1, vd); + setArg(call_illegal_indexed_load_1314, 2, vm); + setArg(call_illegal_indexed_load_1314, 3, 6); + setArg(call_illegal_indexed_load_1314, 4, EEW); + setArg(call_illegal_indexed_load_1314, 5, illegal_indexed_load_1314_arg4); + setArg(call_illegal_indexed_load_1314, 6, illegal_indexed_load_1314_arg5); + setRet(call_illegal_indexed_load_1314, 0, ret_val_illegal_indexed_load_1314); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1317; + x86::Gp ret_val_sew_1317 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1317, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1316; + auto vlxseg_1316_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1316_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1316_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1316_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1316_arg10 = ret_val_sew_1317; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1316 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1316, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1316, 64, false), traits::vstart); + setArg(call_sew_1317, 0, reinterpret_cast(this)); + setRet(call_sew_1317, 0, ret_val_sew_1317); + setArg(call_vlxseg_1316, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1316, 1, V); + setArg(call_vlxseg_1316, 2, vlxseg_1316_arg1); + setArg(call_vlxseg_1316, 3, vlxseg_1316_arg2); + setArg(call_vlxseg_1316, 4, vlxseg_1316_arg3); + setArg(call_vlxseg_1316, 5, vm); + setArg(call_vlxseg_1316, 6, vd); + setArg(call_vlxseg_1316, 7, vlxseg_1316_arg6); + setArg(call_vlxseg_1316, 8, vs2); + setArg(call_vlxseg_1316, 9, 6); + setArg(call_vlxseg_1316, 10, 4); + setArg(call_vlxseg_1316, 11, vlxseg_1316_arg10); + setArg(call_vlxseg_1316, 12, 1); + setRet(call_vlxseg_1316, 0, ret_val_vlxseg_1316); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 407); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 408: VLOXSEG6EI64__V */ + continuation_e __vloxseg6ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg6ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG6EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 408); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1318; + x86::Gp ret_val_get_pow_1318 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1318, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1319; + x86::Gp ret_val_get_sew_pow_1319 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1319, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1320; + x86::Gp ret_val_get_lmul_pow_1320 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1320, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1318, ret_val_get_sew_pow_1319), ret_val_get_lmul_pow_1320)), 3, true); + setArg(call_get_pow_1318, 0, reinterpret_cast(this)); + setArg(call_get_pow_1318, 1, EEW); + setRet(call_get_pow_1318, 0, ret_val_get_pow_1318); + setArg(call_get_sew_pow_1319, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1319, 0, ret_val_get_sew_pow_1319); + setArg(call_get_lmul_pow_1320, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1320, 0, ret_val_get_lmul_pow_1320); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1322; + x86::Gp ret_val_get_lmul_pow_1322 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1322, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1321; + auto illegal_indexed_load_1321_arg4 = EMUL_pow; + auto illegal_indexed_load_1321_arg5 = ret_val_get_lmul_pow_1322; + x86::Gp ret_val_illegal_indexed_load_1321 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1321, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1321; + setArg(call_get_lmul_pow_1322, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1322, 0, ret_val_get_lmul_pow_1322); + setArg(call_illegal_indexed_load_1321, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1321, 1, vd); + setArg(call_illegal_indexed_load_1321, 2, vm); + setArg(call_illegal_indexed_load_1321, 3, 6); + setArg(call_illegal_indexed_load_1321, 4, EEW); + setArg(call_illegal_indexed_load_1321, 5, illegal_indexed_load_1321_arg4); + setArg(call_illegal_indexed_load_1321, 6, illegal_indexed_load_1321_arg5); + setRet(call_illegal_indexed_load_1321, 0, ret_val_illegal_indexed_load_1321); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1324; + x86::Gp ret_val_sew_1324 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1324, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1323; + auto vlxseg_1323_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1323_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1323_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1323_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1323_arg10 = ret_val_sew_1324; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1323 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1323, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1323, 64, false), traits::vstart); + setArg(call_sew_1324, 0, reinterpret_cast(this)); + setRet(call_sew_1324, 0, ret_val_sew_1324); + setArg(call_vlxseg_1323, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1323, 1, V); + setArg(call_vlxseg_1323, 2, vlxseg_1323_arg1); + setArg(call_vlxseg_1323, 3, vlxseg_1323_arg2); + setArg(call_vlxseg_1323, 4, vlxseg_1323_arg3); + setArg(call_vlxseg_1323, 5, vm); + setArg(call_vlxseg_1323, 6, vd); + setArg(call_vlxseg_1323, 7, vlxseg_1323_arg6); + setArg(call_vlxseg_1323, 8, vs2); + setArg(call_vlxseg_1323, 9, 6); + setArg(call_vlxseg_1323, 10, 8); + setArg(call_vlxseg_1323, 11, vlxseg_1323_arg10); + setArg(call_vlxseg_1323, 12, 1); + setRet(call_vlxseg_1323, 0, ret_val_vlxseg_1323); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 408); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 409: VLOXSEG7EI8__V */ + continuation_e __vloxseg7ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG7EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 409); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1325; + x86::Gp ret_val_get_pow_1325 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1325, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1326; + x86::Gp ret_val_get_sew_pow_1326 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1326, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1327; + x86::Gp ret_val_get_lmul_pow_1327 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1327, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1325, ret_val_get_sew_pow_1326), ret_val_get_lmul_pow_1327)), 3, true); + setArg(call_get_pow_1325, 0, reinterpret_cast(this)); + setArg(call_get_pow_1325, 1, EEW); + setRet(call_get_pow_1325, 0, ret_val_get_pow_1325); + setArg(call_get_sew_pow_1326, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1326, 0, ret_val_get_sew_pow_1326); + setArg(call_get_lmul_pow_1327, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1327, 0, ret_val_get_lmul_pow_1327); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1329; + x86::Gp ret_val_get_lmul_pow_1329 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1329, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1328; + auto illegal_indexed_load_1328_arg4 = EMUL_pow; + auto illegal_indexed_load_1328_arg5 = ret_val_get_lmul_pow_1329; + x86::Gp ret_val_illegal_indexed_load_1328 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1328, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1328; + setArg(call_get_lmul_pow_1329, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1329, 0, ret_val_get_lmul_pow_1329); + setArg(call_illegal_indexed_load_1328, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1328, 1, vd); + setArg(call_illegal_indexed_load_1328, 2, vm); + setArg(call_illegal_indexed_load_1328, 3, 7); + setArg(call_illegal_indexed_load_1328, 4, EEW); + setArg(call_illegal_indexed_load_1328, 5, illegal_indexed_load_1328_arg4); + setArg(call_illegal_indexed_load_1328, 6, illegal_indexed_load_1328_arg5); + setRet(call_illegal_indexed_load_1328, 0, ret_val_illegal_indexed_load_1328); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1331; + x86::Gp ret_val_sew_1331 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1331, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1330; + auto vlxseg_1330_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1330_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1330_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1330_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1330_arg10 = ret_val_sew_1331; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1330 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1330, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1330, 64, false), traits::vstart); + setArg(call_sew_1331, 0, reinterpret_cast(this)); + setRet(call_sew_1331, 0, ret_val_sew_1331); + setArg(call_vlxseg_1330, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1330, 1, V); + setArg(call_vlxseg_1330, 2, vlxseg_1330_arg1); + setArg(call_vlxseg_1330, 3, vlxseg_1330_arg2); + setArg(call_vlxseg_1330, 4, vlxseg_1330_arg3); + setArg(call_vlxseg_1330, 5, vm); + setArg(call_vlxseg_1330, 6, vd); + setArg(call_vlxseg_1330, 7, vlxseg_1330_arg6); + setArg(call_vlxseg_1330, 8, vs2); + setArg(call_vlxseg_1330, 9, 7); + setArg(call_vlxseg_1330, 10, 1); + setArg(call_vlxseg_1330, 11, vlxseg_1330_arg10); + setArg(call_vlxseg_1330, 12, 1); + setRet(call_vlxseg_1330, 0, ret_val_vlxseg_1330); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 409); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 410: VLOXSEG7EI16__V */ + continuation_e __vloxseg7ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG7EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 410); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1332; + x86::Gp ret_val_get_pow_1332 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1332, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1333; + x86::Gp ret_val_get_sew_pow_1333 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1333, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1334; + x86::Gp ret_val_get_lmul_pow_1334 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1334, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1332, ret_val_get_sew_pow_1333), ret_val_get_lmul_pow_1334)), 3, true); + setArg(call_get_pow_1332, 0, reinterpret_cast(this)); + setArg(call_get_pow_1332, 1, EEW); + setRet(call_get_pow_1332, 0, ret_val_get_pow_1332); + setArg(call_get_sew_pow_1333, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1333, 0, ret_val_get_sew_pow_1333); + setArg(call_get_lmul_pow_1334, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1334, 0, ret_val_get_lmul_pow_1334); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1336; + x86::Gp ret_val_get_lmul_pow_1336 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1336, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1335; + auto illegal_indexed_load_1335_arg4 = EMUL_pow; + auto illegal_indexed_load_1335_arg5 = ret_val_get_lmul_pow_1336; + x86::Gp ret_val_illegal_indexed_load_1335 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1335, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1335; + setArg(call_get_lmul_pow_1336, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1336, 0, ret_val_get_lmul_pow_1336); + setArg(call_illegal_indexed_load_1335, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1335, 1, vd); + setArg(call_illegal_indexed_load_1335, 2, vm); + setArg(call_illegal_indexed_load_1335, 3, 7); + setArg(call_illegal_indexed_load_1335, 4, EEW); + setArg(call_illegal_indexed_load_1335, 5, illegal_indexed_load_1335_arg4); + setArg(call_illegal_indexed_load_1335, 6, illegal_indexed_load_1335_arg5); + setRet(call_illegal_indexed_load_1335, 0, ret_val_illegal_indexed_load_1335); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1338; + x86::Gp ret_val_sew_1338 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1338, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1337; + auto vlxseg_1337_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1337_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1337_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1337_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1337_arg10 = ret_val_sew_1338; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1337 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1337, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1337, 64, false), traits::vstart); + setArg(call_sew_1338, 0, reinterpret_cast(this)); + setRet(call_sew_1338, 0, ret_val_sew_1338); + setArg(call_vlxseg_1337, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1337, 1, V); + setArg(call_vlxseg_1337, 2, vlxseg_1337_arg1); + setArg(call_vlxseg_1337, 3, vlxseg_1337_arg2); + setArg(call_vlxseg_1337, 4, vlxseg_1337_arg3); + setArg(call_vlxseg_1337, 5, vm); + setArg(call_vlxseg_1337, 6, vd); + setArg(call_vlxseg_1337, 7, vlxseg_1337_arg6); + setArg(call_vlxseg_1337, 8, vs2); + setArg(call_vlxseg_1337, 9, 7); + setArg(call_vlxseg_1337, 10, 2); + setArg(call_vlxseg_1337, 11, vlxseg_1337_arg10); + setArg(call_vlxseg_1337, 12, 1); + setRet(call_vlxseg_1337, 0, ret_val_vlxseg_1337); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 410); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 411: VLOXSEG7EI32__V */ + continuation_e __vloxseg7ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG7EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 411); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1339; + x86::Gp ret_val_get_pow_1339 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1339, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1340; + x86::Gp ret_val_get_sew_pow_1340 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1340, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1341; + x86::Gp ret_val_get_lmul_pow_1341 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1341, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1339, ret_val_get_sew_pow_1340), ret_val_get_lmul_pow_1341)), 3, true); + setArg(call_get_pow_1339, 0, reinterpret_cast(this)); + setArg(call_get_pow_1339, 1, EEW); + setRet(call_get_pow_1339, 0, ret_val_get_pow_1339); + setArg(call_get_sew_pow_1340, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1340, 0, ret_val_get_sew_pow_1340); + setArg(call_get_lmul_pow_1341, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1341, 0, ret_val_get_lmul_pow_1341); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1343; + x86::Gp ret_val_get_lmul_pow_1343 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1343, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1342; + auto illegal_indexed_load_1342_arg4 = EMUL_pow; + auto illegal_indexed_load_1342_arg5 = ret_val_get_lmul_pow_1343; + x86::Gp ret_val_illegal_indexed_load_1342 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1342, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1342; + setArg(call_get_lmul_pow_1343, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1343, 0, ret_val_get_lmul_pow_1343); + setArg(call_illegal_indexed_load_1342, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1342, 1, vd); + setArg(call_illegal_indexed_load_1342, 2, vm); + setArg(call_illegal_indexed_load_1342, 3, 7); + setArg(call_illegal_indexed_load_1342, 4, EEW); + setArg(call_illegal_indexed_load_1342, 5, illegal_indexed_load_1342_arg4); + setArg(call_illegal_indexed_load_1342, 6, illegal_indexed_load_1342_arg5); + setRet(call_illegal_indexed_load_1342, 0, ret_val_illegal_indexed_load_1342); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1345; + x86::Gp ret_val_sew_1345 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1345, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1344; + auto vlxseg_1344_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1344_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1344_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1344_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1344_arg10 = ret_val_sew_1345; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1344 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1344, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1344, 64, false), traits::vstart); + setArg(call_sew_1345, 0, reinterpret_cast(this)); + setRet(call_sew_1345, 0, ret_val_sew_1345); + setArg(call_vlxseg_1344, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1344, 1, V); + setArg(call_vlxseg_1344, 2, vlxseg_1344_arg1); + setArg(call_vlxseg_1344, 3, vlxseg_1344_arg2); + setArg(call_vlxseg_1344, 4, vlxseg_1344_arg3); + setArg(call_vlxseg_1344, 5, vm); + setArg(call_vlxseg_1344, 6, vd); + setArg(call_vlxseg_1344, 7, vlxseg_1344_arg6); + setArg(call_vlxseg_1344, 8, vs2); + setArg(call_vlxseg_1344, 9, 7); + setArg(call_vlxseg_1344, 10, 4); + setArg(call_vlxseg_1344, 11, vlxseg_1344_arg10); + setArg(call_vlxseg_1344, 12, 1); + setRet(call_vlxseg_1344, 0, ret_val_vlxseg_1344); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 411); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 412: VLOXSEG7EI64__V */ + continuation_e __vloxseg7ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg7ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG7EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 412); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1346; + x86::Gp ret_val_get_pow_1346 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1346, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1347; + x86::Gp ret_val_get_sew_pow_1347 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1347, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1348; + x86::Gp ret_val_get_lmul_pow_1348 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1348, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1346, ret_val_get_sew_pow_1347), ret_val_get_lmul_pow_1348)), 3, true); + setArg(call_get_pow_1346, 0, reinterpret_cast(this)); + setArg(call_get_pow_1346, 1, EEW); + setRet(call_get_pow_1346, 0, ret_val_get_pow_1346); + setArg(call_get_sew_pow_1347, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1347, 0, ret_val_get_sew_pow_1347); + setArg(call_get_lmul_pow_1348, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1348, 0, ret_val_get_lmul_pow_1348); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1350; + x86::Gp ret_val_get_lmul_pow_1350 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1350, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1349; + auto illegal_indexed_load_1349_arg4 = EMUL_pow; + auto illegal_indexed_load_1349_arg5 = ret_val_get_lmul_pow_1350; + x86::Gp ret_val_illegal_indexed_load_1349 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1349, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1349; + setArg(call_get_lmul_pow_1350, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1350, 0, ret_val_get_lmul_pow_1350); + setArg(call_illegal_indexed_load_1349, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1349, 1, vd); + setArg(call_illegal_indexed_load_1349, 2, vm); + setArg(call_illegal_indexed_load_1349, 3, 7); + setArg(call_illegal_indexed_load_1349, 4, EEW); + setArg(call_illegal_indexed_load_1349, 5, illegal_indexed_load_1349_arg4); + setArg(call_illegal_indexed_load_1349, 6, illegal_indexed_load_1349_arg5); + setRet(call_illegal_indexed_load_1349, 0, ret_val_illegal_indexed_load_1349); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1352; + x86::Gp ret_val_sew_1352 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1352, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1351; + auto vlxseg_1351_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1351_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1351_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1351_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1351_arg10 = ret_val_sew_1352; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1351 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1351, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1351, 64, false), traits::vstart); + setArg(call_sew_1352, 0, reinterpret_cast(this)); + setRet(call_sew_1352, 0, ret_val_sew_1352); + setArg(call_vlxseg_1351, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1351, 1, V); + setArg(call_vlxseg_1351, 2, vlxseg_1351_arg1); + setArg(call_vlxseg_1351, 3, vlxseg_1351_arg2); + setArg(call_vlxseg_1351, 4, vlxseg_1351_arg3); + setArg(call_vlxseg_1351, 5, vm); + setArg(call_vlxseg_1351, 6, vd); + setArg(call_vlxseg_1351, 7, vlxseg_1351_arg6); + setArg(call_vlxseg_1351, 8, vs2); + setArg(call_vlxseg_1351, 9, 7); + setArg(call_vlxseg_1351, 10, 8); + setArg(call_vlxseg_1351, 11, vlxseg_1351_arg10); + setArg(call_vlxseg_1351, 12, 1); + setRet(call_vlxseg_1351, 0, ret_val_vlxseg_1351); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 412); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 413: VLOXSEG8EI8__V */ + continuation_e __vloxseg8ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG8EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 413); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1353; + x86::Gp ret_val_get_pow_1353 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1353, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1354; + x86::Gp ret_val_get_sew_pow_1354 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1354, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1355; + x86::Gp ret_val_get_lmul_pow_1355 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1355, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1353, ret_val_get_sew_pow_1354), ret_val_get_lmul_pow_1355)), 3, true); + setArg(call_get_pow_1353, 0, reinterpret_cast(this)); + setArg(call_get_pow_1353, 1, EEW); + setRet(call_get_pow_1353, 0, ret_val_get_pow_1353); + setArg(call_get_sew_pow_1354, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1354, 0, ret_val_get_sew_pow_1354); + setArg(call_get_lmul_pow_1355, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1355, 0, ret_val_get_lmul_pow_1355); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1357; + x86::Gp ret_val_get_lmul_pow_1357 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1357, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1356; + auto illegal_indexed_load_1356_arg4 = EMUL_pow; + auto illegal_indexed_load_1356_arg5 = ret_val_get_lmul_pow_1357; + x86::Gp ret_val_illegal_indexed_load_1356 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1356, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1356; + setArg(call_get_lmul_pow_1357, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1357, 0, ret_val_get_lmul_pow_1357); + setArg(call_illegal_indexed_load_1356, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1356, 1, vd); + setArg(call_illegal_indexed_load_1356, 2, vm); + setArg(call_illegal_indexed_load_1356, 3, 8); + setArg(call_illegal_indexed_load_1356, 4, EEW); + setArg(call_illegal_indexed_load_1356, 5, illegal_indexed_load_1356_arg4); + setArg(call_illegal_indexed_load_1356, 6, illegal_indexed_load_1356_arg5); + setRet(call_illegal_indexed_load_1356, 0, ret_val_illegal_indexed_load_1356); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1359; + x86::Gp ret_val_sew_1359 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1359, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1358; + auto vlxseg_1358_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1358_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1358_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1358_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1358_arg10 = ret_val_sew_1359; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1358 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1358, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1358, 64, false), traits::vstart); + setArg(call_sew_1359, 0, reinterpret_cast(this)); + setRet(call_sew_1359, 0, ret_val_sew_1359); + setArg(call_vlxseg_1358, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1358, 1, V); + setArg(call_vlxseg_1358, 2, vlxseg_1358_arg1); + setArg(call_vlxseg_1358, 3, vlxseg_1358_arg2); + setArg(call_vlxseg_1358, 4, vlxseg_1358_arg3); + setArg(call_vlxseg_1358, 5, vm); + setArg(call_vlxseg_1358, 6, vd); + setArg(call_vlxseg_1358, 7, vlxseg_1358_arg6); + setArg(call_vlxseg_1358, 8, vs2); + setArg(call_vlxseg_1358, 9, 8); + setArg(call_vlxseg_1358, 10, 1); + setArg(call_vlxseg_1358, 11, vlxseg_1358_arg10); + setArg(call_vlxseg_1358, 12, 1); + setRet(call_vlxseg_1358, 0, ret_val_vlxseg_1358); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 413); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 414: VLOXSEG8EI16__V */ + continuation_e __vloxseg8ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG8EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 414); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1360; + x86::Gp ret_val_get_pow_1360 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1360, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1361; + x86::Gp ret_val_get_sew_pow_1361 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1361, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1362; + x86::Gp ret_val_get_lmul_pow_1362 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1362, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1360, ret_val_get_sew_pow_1361), ret_val_get_lmul_pow_1362)), 3, true); + setArg(call_get_pow_1360, 0, reinterpret_cast(this)); + setArg(call_get_pow_1360, 1, EEW); + setRet(call_get_pow_1360, 0, ret_val_get_pow_1360); + setArg(call_get_sew_pow_1361, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1361, 0, ret_val_get_sew_pow_1361); + setArg(call_get_lmul_pow_1362, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1362, 0, ret_val_get_lmul_pow_1362); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1364; + x86::Gp ret_val_get_lmul_pow_1364 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1364, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1363; + auto illegal_indexed_load_1363_arg4 = EMUL_pow; + auto illegal_indexed_load_1363_arg5 = ret_val_get_lmul_pow_1364; + x86::Gp ret_val_illegal_indexed_load_1363 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1363, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1363; + setArg(call_get_lmul_pow_1364, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1364, 0, ret_val_get_lmul_pow_1364); + setArg(call_illegal_indexed_load_1363, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1363, 1, vd); + setArg(call_illegal_indexed_load_1363, 2, vm); + setArg(call_illegal_indexed_load_1363, 3, 8); + setArg(call_illegal_indexed_load_1363, 4, EEW); + setArg(call_illegal_indexed_load_1363, 5, illegal_indexed_load_1363_arg4); + setArg(call_illegal_indexed_load_1363, 6, illegal_indexed_load_1363_arg5); + setRet(call_illegal_indexed_load_1363, 0, ret_val_illegal_indexed_load_1363); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1366; + x86::Gp ret_val_sew_1366 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1366, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1365; + auto vlxseg_1365_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1365_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1365_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1365_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1365_arg10 = ret_val_sew_1366; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1365 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1365, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1365, 64, false), traits::vstart); + setArg(call_sew_1366, 0, reinterpret_cast(this)); + setRet(call_sew_1366, 0, ret_val_sew_1366); + setArg(call_vlxseg_1365, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1365, 1, V); + setArg(call_vlxseg_1365, 2, vlxseg_1365_arg1); + setArg(call_vlxseg_1365, 3, vlxseg_1365_arg2); + setArg(call_vlxseg_1365, 4, vlxseg_1365_arg3); + setArg(call_vlxseg_1365, 5, vm); + setArg(call_vlxseg_1365, 6, vd); + setArg(call_vlxseg_1365, 7, vlxseg_1365_arg6); + setArg(call_vlxseg_1365, 8, vs2); + setArg(call_vlxseg_1365, 9, 8); + setArg(call_vlxseg_1365, 10, 2); + setArg(call_vlxseg_1365, 11, vlxseg_1365_arg10); + setArg(call_vlxseg_1365, 12, 1); + setRet(call_vlxseg_1365, 0, ret_val_vlxseg_1365); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 414); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 415: VLOXSEG8EI32__V */ + continuation_e __vloxseg8ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG8EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 415); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1367; + x86::Gp ret_val_get_pow_1367 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1367, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1368; + x86::Gp ret_val_get_sew_pow_1368 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1368, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1369; + x86::Gp ret_val_get_lmul_pow_1369 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1369, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1367, ret_val_get_sew_pow_1368), ret_val_get_lmul_pow_1369)), 3, true); + setArg(call_get_pow_1367, 0, reinterpret_cast(this)); + setArg(call_get_pow_1367, 1, EEW); + setRet(call_get_pow_1367, 0, ret_val_get_pow_1367); + setArg(call_get_sew_pow_1368, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1368, 0, ret_val_get_sew_pow_1368); + setArg(call_get_lmul_pow_1369, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1369, 0, ret_val_get_lmul_pow_1369); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1371; + x86::Gp ret_val_get_lmul_pow_1371 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1371, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1370; + auto illegal_indexed_load_1370_arg4 = EMUL_pow; + auto illegal_indexed_load_1370_arg5 = ret_val_get_lmul_pow_1371; + x86::Gp ret_val_illegal_indexed_load_1370 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1370, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1370; + setArg(call_get_lmul_pow_1371, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1371, 0, ret_val_get_lmul_pow_1371); + setArg(call_illegal_indexed_load_1370, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1370, 1, vd); + setArg(call_illegal_indexed_load_1370, 2, vm); + setArg(call_illegal_indexed_load_1370, 3, 8); + setArg(call_illegal_indexed_load_1370, 4, EEW); + setArg(call_illegal_indexed_load_1370, 5, illegal_indexed_load_1370_arg4); + setArg(call_illegal_indexed_load_1370, 6, illegal_indexed_load_1370_arg5); + setRet(call_illegal_indexed_load_1370, 0, ret_val_illegal_indexed_load_1370); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1373; + x86::Gp ret_val_sew_1373 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1373, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1372; + auto vlxseg_1372_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1372_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1372_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1372_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1372_arg10 = ret_val_sew_1373; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1372 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1372, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1372, 64, false), traits::vstart); + setArg(call_sew_1373, 0, reinterpret_cast(this)); + setRet(call_sew_1373, 0, ret_val_sew_1373); + setArg(call_vlxseg_1372, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1372, 1, V); + setArg(call_vlxseg_1372, 2, vlxseg_1372_arg1); + setArg(call_vlxseg_1372, 3, vlxseg_1372_arg2); + setArg(call_vlxseg_1372, 4, vlxseg_1372_arg3); + setArg(call_vlxseg_1372, 5, vm); + setArg(call_vlxseg_1372, 6, vd); + setArg(call_vlxseg_1372, 7, vlxseg_1372_arg6); + setArg(call_vlxseg_1372, 8, vs2); + setArg(call_vlxseg_1372, 9, 8); + setArg(call_vlxseg_1372, 10, 4); + setArg(call_vlxseg_1372, 11, vlxseg_1372_arg10); + setArg(call_vlxseg_1372, 12, 1); + setRet(call_vlxseg_1372, 0, ret_val_vlxseg_1372); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 415); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 416: VLOXSEG8EI64__V */ + continuation_e __vloxseg8ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vloxseg8ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLOXSEG8EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 416); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1374; + x86::Gp ret_val_get_pow_1374 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1374, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1375; + x86::Gp ret_val_get_sew_pow_1375 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1375, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1376; + x86::Gp ret_val_get_lmul_pow_1376 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1376, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1374, ret_val_get_sew_pow_1375), ret_val_get_lmul_pow_1376)), 3, true); + setArg(call_get_pow_1374, 0, reinterpret_cast(this)); + setArg(call_get_pow_1374, 1, EEW); + setRet(call_get_pow_1374, 0, ret_val_get_pow_1374); + setArg(call_get_sew_pow_1375, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1375, 0, ret_val_get_sew_pow_1375); + setArg(call_get_lmul_pow_1376, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1376, 0, ret_val_get_lmul_pow_1376); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1378; + x86::Gp ret_val_get_lmul_pow_1378 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1378, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1377; + auto illegal_indexed_load_1377_arg4 = EMUL_pow; + auto illegal_indexed_load_1377_arg5 = ret_val_get_lmul_pow_1378; + x86::Gp ret_val_illegal_indexed_load_1377 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1377, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1377; + setArg(call_get_lmul_pow_1378, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1378, 0, ret_val_get_lmul_pow_1378); + setArg(call_illegal_indexed_load_1377, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1377, 1, vd); + setArg(call_illegal_indexed_load_1377, 2, vm); + setArg(call_illegal_indexed_load_1377, 3, 8); + setArg(call_illegal_indexed_load_1377, 4, EEW); + setArg(call_illegal_indexed_load_1377, 5, illegal_indexed_load_1377_arg4); + setArg(call_illegal_indexed_load_1377, 6, illegal_indexed_load_1377_arg5); + setRet(call_illegal_indexed_load_1377, 0, ret_val_illegal_indexed_load_1377); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1380; + x86::Gp ret_val_sew_1380 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1380, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1379; + auto vlxseg_1379_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1379_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1379_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1379_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1379_arg10 = ret_val_sew_1380; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1379 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1379, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1379, 64, false), traits::vstart); + setArg(call_sew_1380, 0, reinterpret_cast(this)); + setRet(call_sew_1380, 0, ret_val_sew_1380); + setArg(call_vlxseg_1379, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1379, 1, V); + setArg(call_vlxseg_1379, 2, vlxseg_1379_arg1); + setArg(call_vlxseg_1379, 3, vlxseg_1379_arg2); + setArg(call_vlxseg_1379, 4, vlxseg_1379_arg3); + setArg(call_vlxseg_1379, 5, vm); + setArg(call_vlxseg_1379, 6, vd); + setArg(call_vlxseg_1379, 7, vlxseg_1379_arg6); + setArg(call_vlxseg_1379, 8, vs2); + setArg(call_vlxseg_1379, 9, 8); + setArg(call_vlxseg_1379, 10, 8); + setArg(call_vlxseg_1379, 11, vlxseg_1379_arg10); + setArg(call_vlxseg_1379, 12, 1); + setRet(call_vlxseg_1379, 0, ret_val_vlxseg_1379); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 416); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 417: VSOXEI8__V */ + continuation_e __vsoxei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXEI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 417); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1381; + x86::Gp ret_val_get_pow_1381 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1381, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1382; + x86::Gp ret_val_get_sew_pow_1382 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1382, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1383; + x86::Gp ret_val_get_lmul_pow_1383 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1383, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1381, ret_val_get_sew_pow_1382), ret_val_get_lmul_pow_1383)), 3, true); + setArg(call_get_pow_1381, 0, reinterpret_cast(this)); + setArg(call_get_pow_1381, 1, EEW); + setRet(call_get_pow_1381, 0, ret_val_get_pow_1381); + setArg(call_get_sew_pow_1382, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1382, 0, ret_val_get_sew_pow_1382); + setArg(call_get_lmul_pow_1383, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1383, 0, ret_val_get_lmul_pow_1383); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1385; + x86::Gp ret_val_get_lmul_pow_1385 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1385, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1384; + auto illegal_indexed_store_1384_arg2 = EMUL_pow; + auto illegal_indexed_store_1384_arg3 = ret_val_get_lmul_pow_1385; + x86::Gp ret_val_illegal_indexed_store_1384 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1384, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1384; + setArg(call_get_lmul_pow_1385, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1385, 0, ret_val_get_lmul_pow_1385); + setArg(call_illegal_indexed_store_1384, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1384, 1, 1); + setArg(call_illegal_indexed_store_1384, 2, EEW); + setArg(call_illegal_indexed_store_1384, 3, illegal_indexed_store_1384_arg2); + setArg(call_illegal_indexed_store_1384, 4, illegal_indexed_store_1384_arg3); + setRet(call_illegal_indexed_store_1384, 0, ret_val_illegal_indexed_store_1384); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1387; + x86::Gp ret_val_sew_1387 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1387, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1386; + auto vsxseg_1386_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1386_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1386_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1386_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1386_arg10 = ret_val_sew_1387; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1386 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1386, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1386, 64, false), traits::vstart); + setArg(call_sew_1387, 0, reinterpret_cast(this)); + setRet(call_sew_1387, 0, ret_val_sew_1387); + setArg(call_vsxseg_1386, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1386, 1, V); + setArg(call_vsxseg_1386, 2, vsxseg_1386_arg1); + setArg(call_vsxseg_1386, 3, vsxseg_1386_arg2); + setArg(call_vsxseg_1386, 4, vsxseg_1386_arg3); + setArg(call_vsxseg_1386, 5, vm); + setArg(call_vsxseg_1386, 6, vs3); + setArg(call_vsxseg_1386, 7, vsxseg_1386_arg6); + setArg(call_vsxseg_1386, 8, vs2); + setArg(call_vsxseg_1386, 9, 1); + setArg(call_vsxseg_1386, 10, 1); + setArg(call_vsxseg_1386, 11, vsxseg_1386_arg10); + setArg(call_vsxseg_1386, 12, 1); + setRet(call_vsxseg_1386, 0, ret_val_vsxseg_1386); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 417); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 418: VSOXEI16__V */ + continuation_e __vsoxei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXEI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 418); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1388; + x86::Gp ret_val_get_pow_1388 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1388, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1389; + x86::Gp ret_val_get_sew_pow_1389 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1389, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1390; + x86::Gp ret_val_get_lmul_pow_1390 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1390, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1388, ret_val_get_sew_pow_1389), ret_val_get_lmul_pow_1390)), 3, true); + setArg(call_get_pow_1388, 0, reinterpret_cast(this)); + setArg(call_get_pow_1388, 1, EEW); + setRet(call_get_pow_1388, 0, ret_val_get_pow_1388); + setArg(call_get_sew_pow_1389, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1389, 0, ret_val_get_sew_pow_1389); + setArg(call_get_lmul_pow_1390, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1390, 0, ret_val_get_lmul_pow_1390); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1392; + x86::Gp ret_val_get_lmul_pow_1392 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1392, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1391; + auto illegal_indexed_store_1391_arg2 = EMUL_pow; + auto illegal_indexed_store_1391_arg3 = ret_val_get_lmul_pow_1392; + x86::Gp ret_val_illegal_indexed_store_1391 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1391, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1391; + setArg(call_get_lmul_pow_1392, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1392, 0, ret_val_get_lmul_pow_1392); + setArg(call_illegal_indexed_store_1391, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1391, 1, 1); + setArg(call_illegal_indexed_store_1391, 2, EEW); + setArg(call_illegal_indexed_store_1391, 3, illegal_indexed_store_1391_arg2); + setArg(call_illegal_indexed_store_1391, 4, illegal_indexed_store_1391_arg3); + setRet(call_illegal_indexed_store_1391, 0, ret_val_illegal_indexed_store_1391); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1394; + x86::Gp ret_val_sew_1394 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1394, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1393; + auto vsxseg_1393_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1393_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1393_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1393_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1393_arg10 = ret_val_sew_1394; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1393 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1393, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1393, 64, false), traits::vstart); + setArg(call_sew_1394, 0, reinterpret_cast(this)); + setRet(call_sew_1394, 0, ret_val_sew_1394); + setArg(call_vsxseg_1393, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1393, 1, V); + setArg(call_vsxseg_1393, 2, vsxseg_1393_arg1); + setArg(call_vsxseg_1393, 3, vsxseg_1393_arg2); + setArg(call_vsxseg_1393, 4, vsxseg_1393_arg3); + setArg(call_vsxseg_1393, 5, vm); + setArg(call_vsxseg_1393, 6, vs3); + setArg(call_vsxseg_1393, 7, vsxseg_1393_arg6); + setArg(call_vsxseg_1393, 8, vs2); + setArg(call_vsxseg_1393, 9, 1); + setArg(call_vsxseg_1393, 10, 2); + setArg(call_vsxseg_1393, 11, vsxseg_1393_arg10); + setArg(call_vsxseg_1393, 12, 1); + setRet(call_vsxseg_1393, 0, ret_val_vsxseg_1393); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 418); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 419: VSOXEI32__V */ + continuation_e __vsoxei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXEI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 419); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1395; + x86::Gp ret_val_get_pow_1395 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1395, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1396; + x86::Gp ret_val_get_sew_pow_1396 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1396, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1397; + x86::Gp ret_val_get_lmul_pow_1397 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1397, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1395, ret_val_get_sew_pow_1396), ret_val_get_lmul_pow_1397)), 3, true); + setArg(call_get_pow_1395, 0, reinterpret_cast(this)); + setArg(call_get_pow_1395, 1, EEW); + setRet(call_get_pow_1395, 0, ret_val_get_pow_1395); + setArg(call_get_sew_pow_1396, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1396, 0, ret_val_get_sew_pow_1396); + setArg(call_get_lmul_pow_1397, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1397, 0, ret_val_get_lmul_pow_1397); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1399; + x86::Gp ret_val_get_lmul_pow_1399 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1399, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1398; + auto illegal_indexed_store_1398_arg2 = EMUL_pow; + auto illegal_indexed_store_1398_arg3 = ret_val_get_lmul_pow_1399; + x86::Gp ret_val_illegal_indexed_store_1398 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1398, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1398; + setArg(call_get_lmul_pow_1399, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1399, 0, ret_val_get_lmul_pow_1399); + setArg(call_illegal_indexed_store_1398, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1398, 1, 1); + setArg(call_illegal_indexed_store_1398, 2, EEW); + setArg(call_illegal_indexed_store_1398, 3, illegal_indexed_store_1398_arg2); + setArg(call_illegal_indexed_store_1398, 4, illegal_indexed_store_1398_arg3); + setRet(call_illegal_indexed_store_1398, 0, ret_val_illegal_indexed_store_1398); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1401; + x86::Gp ret_val_sew_1401 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1401, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1400; + auto vsxseg_1400_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1400_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1400_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1400_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1400_arg10 = ret_val_sew_1401; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1400 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1400, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1400, 64, false), traits::vstart); + setArg(call_sew_1401, 0, reinterpret_cast(this)); + setRet(call_sew_1401, 0, ret_val_sew_1401); + setArg(call_vsxseg_1400, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1400, 1, V); + setArg(call_vsxseg_1400, 2, vsxseg_1400_arg1); + setArg(call_vsxseg_1400, 3, vsxseg_1400_arg2); + setArg(call_vsxseg_1400, 4, vsxseg_1400_arg3); + setArg(call_vsxseg_1400, 5, vm); + setArg(call_vsxseg_1400, 6, vs3); + setArg(call_vsxseg_1400, 7, vsxseg_1400_arg6); + setArg(call_vsxseg_1400, 8, vs2); + setArg(call_vsxseg_1400, 9, 1); + setArg(call_vsxseg_1400, 10, 4); + setArg(call_vsxseg_1400, 11, vsxseg_1400_arg10); + setArg(call_vsxseg_1400, 12, 1); + setRet(call_vsxseg_1400, 0, ret_val_vsxseg_1400); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 419); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 420: VSOXEI64__V */ + continuation_e __vsoxei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXEI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 420); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1402; + x86::Gp ret_val_get_pow_1402 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1402, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1403; + x86::Gp ret_val_get_sew_pow_1403 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1403, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1404; + x86::Gp ret_val_get_lmul_pow_1404 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1404, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1402, ret_val_get_sew_pow_1403), ret_val_get_lmul_pow_1404)), 3, true); + setArg(call_get_pow_1402, 0, reinterpret_cast(this)); + setArg(call_get_pow_1402, 1, EEW); + setRet(call_get_pow_1402, 0, ret_val_get_pow_1402); + setArg(call_get_sew_pow_1403, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1403, 0, ret_val_get_sew_pow_1403); + setArg(call_get_lmul_pow_1404, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1404, 0, ret_val_get_lmul_pow_1404); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1406; + x86::Gp ret_val_get_lmul_pow_1406 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1406, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1405; + auto illegal_indexed_store_1405_arg2 = EMUL_pow; + auto illegal_indexed_store_1405_arg3 = ret_val_get_lmul_pow_1406; + x86::Gp ret_val_illegal_indexed_store_1405 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1405, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1405; + setArg(call_get_lmul_pow_1406, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1406, 0, ret_val_get_lmul_pow_1406); + setArg(call_illegal_indexed_store_1405, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1405, 1, 1); + setArg(call_illegal_indexed_store_1405, 2, EEW); + setArg(call_illegal_indexed_store_1405, 3, illegal_indexed_store_1405_arg2); + setArg(call_illegal_indexed_store_1405, 4, illegal_indexed_store_1405_arg3); + setRet(call_illegal_indexed_store_1405, 0, ret_val_illegal_indexed_store_1405); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1408; + x86::Gp ret_val_sew_1408 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1408, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1407; + auto vsxseg_1407_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1407_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1407_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1407_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1407_arg10 = ret_val_sew_1408; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1407 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1407, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1407, 64, false), traits::vstart); + setArg(call_sew_1408, 0, reinterpret_cast(this)); + setRet(call_sew_1408, 0, ret_val_sew_1408); + setArg(call_vsxseg_1407, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1407, 1, V); + setArg(call_vsxseg_1407, 2, vsxseg_1407_arg1); + setArg(call_vsxseg_1407, 3, vsxseg_1407_arg2); + setArg(call_vsxseg_1407, 4, vsxseg_1407_arg3); + setArg(call_vsxseg_1407, 5, vm); + setArg(call_vsxseg_1407, 6, vs3); + setArg(call_vsxseg_1407, 7, vsxseg_1407_arg6); + setArg(call_vsxseg_1407, 8, vs2); + setArg(call_vsxseg_1407, 9, 1); + setArg(call_vsxseg_1407, 10, 8); + setArg(call_vsxseg_1407, 11, vsxseg_1407_arg10); + setArg(call_vsxseg_1407, 12, 1); + setRet(call_vsxseg_1407, 0, ret_val_vsxseg_1407); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 420); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 421: VSOXSEG2EI8__V */ + continuation_e __vsoxseg2ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG2EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 421); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1409; + x86::Gp ret_val_get_pow_1409 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1409, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1410; + x86::Gp ret_val_get_sew_pow_1410 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1410, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1411; + x86::Gp ret_val_get_lmul_pow_1411 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1411, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1409, ret_val_get_sew_pow_1410), ret_val_get_lmul_pow_1411)), 3, true); + setArg(call_get_pow_1409, 0, reinterpret_cast(this)); + setArg(call_get_pow_1409, 1, EEW); + setRet(call_get_pow_1409, 0, ret_val_get_pow_1409); + setArg(call_get_sew_pow_1410, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1410, 0, ret_val_get_sew_pow_1410); + setArg(call_get_lmul_pow_1411, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1411, 0, ret_val_get_lmul_pow_1411); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1413; + x86::Gp ret_val_get_lmul_pow_1413 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1413, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1412; + auto illegal_indexed_store_1412_arg2 = EMUL_pow; + auto illegal_indexed_store_1412_arg3 = ret_val_get_lmul_pow_1413; + x86::Gp ret_val_illegal_indexed_store_1412 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1412, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1412; + setArg(call_get_lmul_pow_1413, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1413, 0, ret_val_get_lmul_pow_1413); + setArg(call_illegal_indexed_store_1412, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1412, 1, 2); + setArg(call_illegal_indexed_store_1412, 2, EEW); + setArg(call_illegal_indexed_store_1412, 3, illegal_indexed_store_1412_arg2); + setArg(call_illegal_indexed_store_1412, 4, illegal_indexed_store_1412_arg3); + setRet(call_illegal_indexed_store_1412, 0, ret_val_illegal_indexed_store_1412); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1415; + x86::Gp ret_val_sew_1415 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1415, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1414; + auto vsxseg_1414_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1414_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1414_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1414_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1414_arg10 = ret_val_sew_1415; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1414 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1414, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1414, 64, false), traits::vstart); + setArg(call_sew_1415, 0, reinterpret_cast(this)); + setRet(call_sew_1415, 0, ret_val_sew_1415); + setArg(call_vsxseg_1414, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1414, 1, V); + setArg(call_vsxseg_1414, 2, vsxseg_1414_arg1); + setArg(call_vsxseg_1414, 3, vsxseg_1414_arg2); + setArg(call_vsxseg_1414, 4, vsxseg_1414_arg3); + setArg(call_vsxseg_1414, 5, vm); + setArg(call_vsxseg_1414, 6, vs3); + setArg(call_vsxseg_1414, 7, vsxseg_1414_arg6); + setArg(call_vsxseg_1414, 8, vs2); + setArg(call_vsxseg_1414, 9, 2); + setArg(call_vsxseg_1414, 10, 1); + setArg(call_vsxseg_1414, 11, vsxseg_1414_arg10); + setArg(call_vsxseg_1414, 12, 1); + setRet(call_vsxseg_1414, 0, ret_val_vsxseg_1414); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 421); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 422: VSOXSEG2EI16__V */ + continuation_e __vsoxseg2ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG2EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 422); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1416; + x86::Gp ret_val_get_pow_1416 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1416, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1417; + x86::Gp ret_val_get_sew_pow_1417 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1417, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1418; + x86::Gp ret_val_get_lmul_pow_1418 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1418, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1416, ret_val_get_sew_pow_1417), ret_val_get_lmul_pow_1418)), 3, true); + setArg(call_get_pow_1416, 0, reinterpret_cast(this)); + setArg(call_get_pow_1416, 1, EEW); + setRet(call_get_pow_1416, 0, ret_val_get_pow_1416); + setArg(call_get_sew_pow_1417, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1417, 0, ret_val_get_sew_pow_1417); + setArg(call_get_lmul_pow_1418, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1418, 0, ret_val_get_lmul_pow_1418); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1420; + x86::Gp ret_val_get_lmul_pow_1420 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1420, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1419; + auto illegal_indexed_store_1419_arg2 = EMUL_pow; + auto illegal_indexed_store_1419_arg3 = ret_val_get_lmul_pow_1420; + x86::Gp ret_val_illegal_indexed_store_1419 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1419, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1419; + setArg(call_get_lmul_pow_1420, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1420, 0, ret_val_get_lmul_pow_1420); + setArg(call_illegal_indexed_store_1419, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1419, 1, 2); + setArg(call_illegal_indexed_store_1419, 2, EEW); + setArg(call_illegal_indexed_store_1419, 3, illegal_indexed_store_1419_arg2); + setArg(call_illegal_indexed_store_1419, 4, illegal_indexed_store_1419_arg3); + setRet(call_illegal_indexed_store_1419, 0, ret_val_illegal_indexed_store_1419); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1422; + x86::Gp ret_val_sew_1422 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1422, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1421; + auto vsxseg_1421_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1421_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1421_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1421_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1421_arg10 = ret_val_sew_1422; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1421 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1421, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1421, 64, false), traits::vstart); + setArg(call_sew_1422, 0, reinterpret_cast(this)); + setRet(call_sew_1422, 0, ret_val_sew_1422); + setArg(call_vsxseg_1421, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1421, 1, V); + setArg(call_vsxseg_1421, 2, vsxseg_1421_arg1); + setArg(call_vsxseg_1421, 3, vsxseg_1421_arg2); + setArg(call_vsxseg_1421, 4, vsxseg_1421_arg3); + setArg(call_vsxseg_1421, 5, vm); + setArg(call_vsxseg_1421, 6, vs3); + setArg(call_vsxseg_1421, 7, vsxseg_1421_arg6); + setArg(call_vsxseg_1421, 8, vs2); + setArg(call_vsxseg_1421, 9, 2); + setArg(call_vsxseg_1421, 10, 2); + setArg(call_vsxseg_1421, 11, vsxseg_1421_arg10); + setArg(call_vsxseg_1421, 12, 1); + setRet(call_vsxseg_1421, 0, ret_val_vsxseg_1421); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 422); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 423: VSOXSEG2EI32__V */ + continuation_e __vsoxseg2ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG2EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 423); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1423; + x86::Gp ret_val_get_pow_1423 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1423, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1424; + x86::Gp ret_val_get_sew_pow_1424 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1424, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1425; + x86::Gp ret_val_get_lmul_pow_1425 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1425, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1423, ret_val_get_sew_pow_1424), ret_val_get_lmul_pow_1425)), 3, true); + setArg(call_get_pow_1423, 0, reinterpret_cast(this)); + setArg(call_get_pow_1423, 1, EEW); + setRet(call_get_pow_1423, 0, ret_val_get_pow_1423); + setArg(call_get_sew_pow_1424, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1424, 0, ret_val_get_sew_pow_1424); + setArg(call_get_lmul_pow_1425, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1425, 0, ret_val_get_lmul_pow_1425); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1427; + x86::Gp ret_val_get_lmul_pow_1427 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1427, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1426; + auto illegal_indexed_store_1426_arg2 = EMUL_pow; + auto illegal_indexed_store_1426_arg3 = ret_val_get_lmul_pow_1427; + x86::Gp ret_val_illegal_indexed_store_1426 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1426, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1426; + setArg(call_get_lmul_pow_1427, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1427, 0, ret_val_get_lmul_pow_1427); + setArg(call_illegal_indexed_store_1426, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1426, 1, 2); + setArg(call_illegal_indexed_store_1426, 2, EEW); + setArg(call_illegal_indexed_store_1426, 3, illegal_indexed_store_1426_arg2); + setArg(call_illegal_indexed_store_1426, 4, illegal_indexed_store_1426_arg3); + setRet(call_illegal_indexed_store_1426, 0, ret_val_illegal_indexed_store_1426); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1429; + x86::Gp ret_val_sew_1429 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1429, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1428; + auto vsxseg_1428_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1428_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1428_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1428_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1428_arg10 = ret_val_sew_1429; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1428 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1428, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1428, 64, false), traits::vstart); + setArg(call_sew_1429, 0, reinterpret_cast(this)); + setRet(call_sew_1429, 0, ret_val_sew_1429); + setArg(call_vsxseg_1428, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1428, 1, V); + setArg(call_vsxseg_1428, 2, vsxseg_1428_arg1); + setArg(call_vsxseg_1428, 3, vsxseg_1428_arg2); + setArg(call_vsxseg_1428, 4, vsxseg_1428_arg3); + setArg(call_vsxseg_1428, 5, vm); + setArg(call_vsxseg_1428, 6, vs3); + setArg(call_vsxseg_1428, 7, vsxseg_1428_arg6); + setArg(call_vsxseg_1428, 8, vs2); + setArg(call_vsxseg_1428, 9, 2); + setArg(call_vsxseg_1428, 10, 4); + setArg(call_vsxseg_1428, 11, vsxseg_1428_arg10); + setArg(call_vsxseg_1428, 12, 1); + setRet(call_vsxseg_1428, 0, ret_val_vsxseg_1428); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 423); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 424: VSOXSEG2EI64__V */ + continuation_e __vsoxseg2ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg2ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG2EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 424); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1430; + x86::Gp ret_val_get_pow_1430 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1430, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1431; + x86::Gp ret_val_get_sew_pow_1431 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1431, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1432; + x86::Gp ret_val_get_lmul_pow_1432 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1432, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1430, ret_val_get_sew_pow_1431), ret_val_get_lmul_pow_1432)), 3, true); + setArg(call_get_pow_1430, 0, reinterpret_cast(this)); + setArg(call_get_pow_1430, 1, EEW); + setRet(call_get_pow_1430, 0, ret_val_get_pow_1430); + setArg(call_get_sew_pow_1431, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1431, 0, ret_val_get_sew_pow_1431); + setArg(call_get_lmul_pow_1432, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1432, 0, ret_val_get_lmul_pow_1432); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1434; + x86::Gp ret_val_get_lmul_pow_1434 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1434, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1433; + auto illegal_indexed_store_1433_arg2 = EMUL_pow; + auto illegal_indexed_store_1433_arg3 = ret_val_get_lmul_pow_1434; + x86::Gp ret_val_illegal_indexed_store_1433 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1433, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1433; + setArg(call_get_lmul_pow_1434, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1434, 0, ret_val_get_lmul_pow_1434); + setArg(call_illegal_indexed_store_1433, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1433, 1, 2); + setArg(call_illegal_indexed_store_1433, 2, EEW); + setArg(call_illegal_indexed_store_1433, 3, illegal_indexed_store_1433_arg2); + setArg(call_illegal_indexed_store_1433, 4, illegal_indexed_store_1433_arg3); + setRet(call_illegal_indexed_store_1433, 0, ret_val_illegal_indexed_store_1433); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1436; + x86::Gp ret_val_sew_1436 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1436, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1435; + auto vsxseg_1435_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1435_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1435_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1435_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1435_arg10 = ret_val_sew_1436; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1435 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1435, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1435, 64, false), traits::vstart); + setArg(call_sew_1436, 0, reinterpret_cast(this)); + setRet(call_sew_1436, 0, ret_val_sew_1436); + setArg(call_vsxseg_1435, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1435, 1, V); + setArg(call_vsxseg_1435, 2, vsxseg_1435_arg1); + setArg(call_vsxseg_1435, 3, vsxseg_1435_arg2); + setArg(call_vsxseg_1435, 4, vsxseg_1435_arg3); + setArg(call_vsxseg_1435, 5, vm); + setArg(call_vsxseg_1435, 6, vs3); + setArg(call_vsxseg_1435, 7, vsxseg_1435_arg6); + setArg(call_vsxseg_1435, 8, vs2); + setArg(call_vsxseg_1435, 9, 2); + setArg(call_vsxseg_1435, 10, 8); + setArg(call_vsxseg_1435, 11, vsxseg_1435_arg10); + setArg(call_vsxseg_1435, 12, 1); + setRet(call_vsxseg_1435, 0, ret_val_vsxseg_1435); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 424); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 425: VSOXSEG3EI8__V */ + continuation_e __vsoxseg3ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG3EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 425); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1437; + x86::Gp ret_val_get_pow_1437 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1437, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1438; + x86::Gp ret_val_get_sew_pow_1438 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1438, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1439; + x86::Gp ret_val_get_lmul_pow_1439 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1439, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1437, ret_val_get_sew_pow_1438), ret_val_get_lmul_pow_1439)), 3, true); + setArg(call_get_pow_1437, 0, reinterpret_cast(this)); + setArg(call_get_pow_1437, 1, EEW); + setRet(call_get_pow_1437, 0, ret_val_get_pow_1437); + setArg(call_get_sew_pow_1438, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1438, 0, ret_val_get_sew_pow_1438); + setArg(call_get_lmul_pow_1439, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1439, 0, ret_val_get_lmul_pow_1439); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1441; + x86::Gp ret_val_get_lmul_pow_1441 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1441, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1440; + auto illegal_indexed_store_1440_arg2 = EMUL_pow; + auto illegal_indexed_store_1440_arg3 = ret_val_get_lmul_pow_1441; + x86::Gp ret_val_illegal_indexed_store_1440 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1440, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1440; + setArg(call_get_lmul_pow_1441, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1441, 0, ret_val_get_lmul_pow_1441); + setArg(call_illegal_indexed_store_1440, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1440, 1, 3); + setArg(call_illegal_indexed_store_1440, 2, EEW); + setArg(call_illegal_indexed_store_1440, 3, illegal_indexed_store_1440_arg2); + setArg(call_illegal_indexed_store_1440, 4, illegal_indexed_store_1440_arg3); + setRet(call_illegal_indexed_store_1440, 0, ret_val_illegal_indexed_store_1440); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1443; + x86::Gp ret_val_sew_1443 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1443, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1442; + auto vsxseg_1442_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1442_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1442_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1442_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1442_arg10 = ret_val_sew_1443; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1442 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1442, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1442, 64, false), traits::vstart); + setArg(call_sew_1443, 0, reinterpret_cast(this)); + setRet(call_sew_1443, 0, ret_val_sew_1443); + setArg(call_vsxseg_1442, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1442, 1, V); + setArg(call_vsxseg_1442, 2, vsxseg_1442_arg1); + setArg(call_vsxseg_1442, 3, vsxseg_1442_arg2); + setArg(call_vsxseg_1442, 4, vsxseg_1442_arg3); + setArg(call_vsxseg_1442, 5, vm); + setArg(call_vsxseg_1442, 6, vs3); + setArg(call_vsxseg_1442, 7, vsxseg_1442_arg6); + setArg(call_vsxseg_1442, 8, vs2); + setArg(call_vsxseg_1442, 9, 3); + setArg(call_vsxseg_1442, 10, 1); + setArg(call_vsxseg_1442, 11, vsxseg_1442_arg10); + setArg(call_vsxseg_1442, 12, 1); + setRet(call_vsxseg_1442, 0, ret_val_vsxseg_1442); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 425); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 426: VSOXSEG3EI16__V */ + continuation_e __vsoxseg3ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG3EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 426); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1444; + x86::Gp ret_val_get_pow_1444 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1444, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1445; + x86::Gp ret_val_get_sew_pow_1445 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1445, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1446; + x86::Gp ret_val_get_lmul_pow_1446 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1446, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1444, ret_val_get_sew_pow_1445), ret_val_get_lmul_pow_1446)), 3, true); + setArg(call_get_pow_1444, 0, reinterpret_cast(this)); + setArg(call_get_pow_1444, 1, EEW); + setRet(call_get_pow_1444, 0, ret_val_get_pow_1444); + setArg(call_get_sew_pow_1445, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1445, 0, ret_val_get_sew_pow_1445); + setArg(call_get_lmul_pow_1446, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1446, 0, ret_val_get_lmul_pow_1446); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1448; + x86::Gp ret_val_get_lmul_pow_1448 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1448, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1447; + auto illegal_indexed_store_1447_arg2 = EMUL_pow; + auto illegal_indexed_store_1447_arg3 = ret_val_get_lmul_pow_1448; + x86::Gp ret_val_illegal_indexed_store_1447 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1447, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1447; + setArg(call_get_lmul_pow_1448, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1448, 0, ret_val_get_lmul_pow_1448); + setArg(call_illegal_indexed_store_1447, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1447, 1, 3); + setArg(call_illegal_indexed_store_1447, 2, EEW); + setArg(call_illegal_indexed_store_1447, 3, illegal_indexed_store_1447_arg2); + setArg(call_illegal_indexed_store_1447, 4, illegal_indexed_store_1447_arg3); + setRet(call_illegal_indexed_store_1447, 0, ret_val_illegal_indexed_store_1447); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1450; + x86::Gp ret_val_sew_1450 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1450, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1449; + auto vsxseg_1449_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1449_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1449_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1449_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1449_arg10 = ret_val_sew_1450; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1449 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1449, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1449, 64, false), traits::vstart); + setArg(call_sew_1450, 0, reinterpret_cast(this)); + setRet(call_sew_1450, 0, ret_val_sew_1450); + setArg(call_vsxseg_1449, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1449, 1, V); + setArg(call_vsxseg_1449, 2, vsxseg_1449_arg1); + setArg(call_vsxseg_1449, 3, vsxseg_1449_arg2); + setArg(call_vsxseg_1449, 4, vsxseg_1449_arg3); + setArg(call_vsxseg_1449, 5, vm); + setArg(call_vsxseg_1449, 6, vs3); + setArg(call_vsxseg_1449, 7, vsxseg_1449_arg6); + setArg(call_vsxseg_1449, 8, vs2); + setArg(call_vsxseg_1449, 9, 3); + setArg(call_vsxseg_1449, 10, 2); + setArg(call_vsxseg_1449, 11, vsxseg_1449_arg10); + setArg(call_vsxseg_1449, 12, 1); + setRet(call_vsxseg_1449, 0, ret_val_vsxseg_1449); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 426); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 427: VSOXSEG3EI32__V */ + continuation_e __vsoxseg3ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG3EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 427); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1451; + x86::Gp ret_val_get_pow_1451 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1451, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1452; + x86::Gp ret_val_get_sew_pow_1452 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1452, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1453; + x86::Gp ret_val_get_lmul_pow_1453 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1453, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1451, ret_val_get_sew_pow_1452), ret_val_get_lmul_pow_1453)), 3, true); + setArg(call_get_pow_1451, 0, reinterpret_cast(this)); + setArg(call_get_pow_1451, 1, EEW); + setRet(call_get_pow_1451, 0, ret_val_get_pow_1451); + setArg(call_get_sew_pow_1452, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1452, 0, ret_val_get_sew_pow_1452); + setArg(call_get_lmul_pow_1453, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1453, 0, ret_val_get_lmul_pow_1453); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1455; + x86::Gp ret_val_get_lmul_pow_1455 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1455, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1454; + auto illegal_indexed_store_1454_arg2 = EMUL_pow; + auto illegal_indexed_store_1454_arg3 = ret_val_get_lmul_pow_1455; + x86::Gp ret_val_illegal_indexed_store_1454 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1454, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1454; + setArg(call_get_lmul_pow_1455, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1455, 0, ret_val_get_lmul_pow_1455); + setArg(call_illegal_indexed_store_1454, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1454, 1, 3); + setArg(call_illegal_indexed_store_1454, 2, EEW); + setArg(call_illegal_indexed_store_1454, 3, illegal_indexed_store_1454_arg2); + setArg(call_illegal_indexed_store_1454, 4, illegal_indexed_store_1454_arg3); + setRet(call_illegal_indexed_store_1454, 0, ret_val_illegal_indexed_store_1454); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1457; + x86::Gp ret_val_sew_1457 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1457, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1456; + auto vsxseg_1456_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1456_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1456_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1456_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1456_arg10 = ret_val_sew_1457; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1456 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1456, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1456, 64, false), traits::vstart); + setArg(call_sew_1457, 0, reinterpret_cast(this)); + setRet(call_sew_1457, 0, ret_val_sew_1457); + setArg(call_vsxseg_1456, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1456, 1, V); + setArg(call_vsxseg_1456, 2, vsxseg_1456_arg1); + setArg(call_vsxseg_1456, 3, vsxseg_1456_arg2); + setArg(call_vsxseg_1456, 4, vsxseg_1456_arg3); + setArg(call_vsxseg_1456, 5, vm); + setArg(call_vsxseg_1456, 6, vs3); + setArg(call_vsxseg_1456, 7, vsxseg_1456_arg6); + setArg(call_vsxseg_1456, 8, vs2); + setArg(call_vsxseg_1456, 9, 3); + setArg(call_vsxseg_1456, 10, 4); + setArg(call_vsxseg_1456, 11, vsxseg_1456_arg10); + setArg(call_vsxseg_1456, 12, 1); + setRet(call_vsxseg_1456, 0, ret_val_vsxseg_1456); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 427); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 428: VSOXSEG3EI64__V */ + continuation_e __vsoxseg3ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg3ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG3EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 428); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1458; + x86::Gp ret_val_get_pow_1458 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1458, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1459; + x86::Gp ret_val_get_sew_pow_1459 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1459, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1460; + x86::Gp ret_val_get_lmul_pow_1460 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1460, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1458, ret_val_get_sew_pow_1459), ret_val_get_lmul_pow_1460)), 3, true); + setArg(call_get_pow_1458, 0, reinterpret_cast(this)); + setArg(call_get_pow_1458, 1, EEW); + setRet(call_get_pow_1458, 0, ret_val_get_pow_1458); + setArg(call_get_sew_pow_1459, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1459, 0, ret_val_get_sew_pow_1459); + setArg(call_get_lmul_pow_1460, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1460, 0, ret_val_get_lmul_pow_1460); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1462; + x86::Gp ret_val_get_lmul_pow_1462 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1462, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1461; + auto illegal_indexed_store_1461_arg2 = EMUL_pow; + auto illegal_indexed_store_1461_arg3 = ret_val_get_lmul_pow_1462; + x86::Gp ret_val_illegal_indexed_store_1461 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1461, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1461; + setArg(call_get_lmul_pow_1462, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1462, 0, ret_val_get_lmul_pow_1462); + setArg(call_illegal_indexed_store_1461, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1461, 1, 3); + setArg(call_illegal_indexed_store_1461, 2, EEW); + setArg(call_illegal_indexed_store_1461, 3, illegal_indexed_store_1461_arg2); + setArg(call_illegal_indexed_store_1461, 4, illegal_indexed_store_1461_arg3); + setRet(call_illegal_indexed_store_1461, 0, ret_val_illegal_indexed_store_1461); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1464; + x86::Gp ret_val_sew_1464 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1464, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1463; + auto vsxseg_1463_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1463_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1463_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1463_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1463_arg10 = ret_val_sew_1464; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1463 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1463, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1463, 64, false), traits::vstart); + setArg(call_sew_1464, 0, reinterpret_cast(this)); + setRet(call_sew_1464, 0, ret_val_sew_1464); + setArg(call_vsxseg_1463, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1463, 1, V); + setArg(call_vsxseg_1463, 2, vsxseg_1463_arg1); + setArg(call_vsxseg_1463, 3, vsxseg_1463_arg2); + setArg(call_vsxseg_1463, 4, vsxseg_1463_arg3); + setArg(call_vsxseg_1463, 5, vm); + setArg(call_vsxseg_1463, 6, vs3); + setArg(call_vsxseg_1463, 7, vsxseg_1463_arg6); + setArg(call_vsxseg_1463, 8, vs2); + setArg(call_vsxseg_1463, 9, 3); + setArg(call_vsxseg_1463, 10, 8); + setArg(call_vsxseg_1463, 11, vsxseg_1463_arg10); + setArg(call_vsxseg_1463, 12, 1); + setRet(call_vsxseg_1463, 0, ret_val_vsxseg_1463); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 428); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 429: VSOXSEG4EI8__V */ + continuation_e __vsoxseg4ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG4EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 429); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1465; + x86::Gp ret_val_get_pow_1465 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1465, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1466; + x86::Gp ret_val_get_sew_pow_1466 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1466, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1467; + x86::Gp ret_val_get_lmul_pow_1467 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1467, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1465, ret_val_get_sew_pow_1466), ret_val_get_lmul_pow_1467)), 3, true); + setArg(call_get_pow_1465, 0, reinterpret_cast(this)); + setArg(call_get_pow_1465, 1, EEW); + setRet(call_get_pow_1465, 0, ret_val_get_pow_1465); + setArg(call_get_sew_pow_1466, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1466, 0, ret_val_get_sew_pow_1466); + setArg(call_get_lmul_pow_1467, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1467, 0, ret_val_get_lmul_pow_1467); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1469; + x86::Gp ret_val_get_lmul_pow_1469 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1469, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1468; + auto illegal_indexed_store_1468_arg2 = EMUL_pow; + auto illegal_indexed_store_1468_arg3 = ret_val_get_lmul_pow_1469; + x86::Gp ret_val_illegal_indexed_store_1468 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1468, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1468; + setArg(call_get_lmul_pow_1469, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1469, 0, ret_val_get_lmul_pow_1469); + setArg(call_illegal_indexed_store_1468, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1468, 1, 4); + setArg(call_illegal_indexed_store_1468, 2, EEW); + setArg(call_illegal_indexed_store_1468, 3, illegal_indexed_store_1468_arg2); + setArg(call_illegal_indexed_store_1468, 4, illegal_indexed_store_1468_arg3); + setRet(call_illegal_indexed_store_1468, 0, ret_val_illegal_indexed_store_1468); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1471; + x86::Gp ret_val_sew_1471 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1471, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1470; + auto vsxseg_1470_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1470_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1470_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1470_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1470_arg10 = ret_val_sew_1471; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1470 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1470, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1470, 64, false), traits::vstart); + setArg(call_sew_1471, 0, reinterpret_cast(this)); + setRet(call_sew_1471, 0, ret_val_sew_1471); + setArg(call_vsxseg_1470, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1470, 1, V); + setArg(call_vsxseg_1470, 2, vsxseg_1470_arg1); + setArg(call_vsxseg_1470, 3, vsxseg_1470_arg2); + setArg(call_vsxseg_1470, 4, vsxseg_1470_arg3); + setArg(call_vsxseg_1470, 5, vm); + setArg(call_vsxseg_1470, 6, vs3); + setArg(call_vsxseg_1470, 7, vsxseg_1470_arg6); + setArg(call_vsxseg_1470, 8, vs2); + setArg(call_vsxseg_1470, 9, 4); + setArg(call_vsxseg_1470, 10, 1); + setArg(call_vsxseg_1470, 11, vsxseg_1470_arg10); + setArg(call_vsxseg_1470, 12, 1); + setRet(call_vsxseg_1470, 0, ret_val_vsxseg_1470); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 429); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 430: VSOXSEG4EI16__V */ + continuation_e __vsoxseg4ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG4EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 430); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1472; + x86::Gp ret_val_get_pow_1472 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1472, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1473; + x86::Gp ret_val_get_sew_pow_1473 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1473, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1474; + x86::Gp ret_val_get_lmul_pow_1474 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1474, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1472, ret_val_get_sew_pow_1473), ret_val_get_lmul_pow_1474)), 3, true); + setArg(call_get_pow_1472, 0, reinterpret_cast(this)); + setArg(call_get_pow_1472, 1, EEW); + setRet(call_get_pow_1472, 0, ret_val_get_pow_1472); + setArg(call_get_sew_pow_1473, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1473, 0, ret_val_get_sew_pow_1473); + setArg(call_get_lmul_pow_1474, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1474, 0, ret_val_get_lmul_pow_1474); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1476; + x86::Gp ret_val_get_lmul_pow_1476 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1476, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1475; + auto illegal_indexed_store_1475_arg2 = EMUL_pow; + auto illegal_indexed_store_1475_arg3 = ret_val_get_lmul_pow_1476; + x86::Gp ret_val_illegal_indexed_store_1475 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1475, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1475; + setArg(call_get_lmul_pow_1476, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1476, 0, ret_val_get_lmul_pow_1476); + setArg(call_illegal_indexed_store_1475, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1475, 1, 4); + setArg(call_illegal_indexed_store_1475, 2, EEW); + setArg(call_illegal_indexed_store_1475, 3, illegal_indexed_store_1475_arg2); + setArg(call_illegal_indexed_store_1475, 4, illegal_indexed_store_1475_arg3); + setRet(call_illegal_indexed_store_1475, 0, ret_val_illegal_indexed_store_1475); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1478; + x86::Gp ret_val_sew_1478 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1478, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1477; + auto vsxseg_1477_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1477_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1477_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1477_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1477_arg10 = ret_val_sew_1478; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1477 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1477, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1477, 64, false), traits::vstart); + setArg(call_sew_1478, 0, reinterpret_cast(this)); + setRet(call_sew_1478, 0, ret_val_sew_1478); + setArg(call_vsxseg_1477, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1477, 1, V); + setArg(call_vsxseg_1477, 2, vsxseg_1477_arg1); + setArg(call_vsxseg_1477, 3, vsxseg_1477_arg2); + setArg(call_vsxseg_1477, 4, vsxseg_1477_arg3); + setArg(call_vsxseg_1477, 5, vm); + setArg(call_vsxseg_1477, 6, vs3); + setArg(call_vsxseg_1477, 7, vsxseg_1477_arg6); + setArg(call_vsxseg_1477, 8, vs2); + setArg(call_vsxseg_1477, 9, 4); + setArg(call_vsxseg_1477, 10, 2); + setArg(call_vsxseg_1477, 11, vsxseg_1477_arg10); + setArg(call_vsxseg_1477, 12, 1); + setRet(call_vsxseg_1477, 0, ret_val_vsxseg_1477); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 430); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 431: VSOXSEG4EI32__V */ + continuation_e __vsoxseg4ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG4EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 431); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1479; + x86::Gp ret_val_get_pow_1479 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1479, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1480; + x86::Gp ret_val_get_sew_pow_1480 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1480, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1481; + x86::Gp ret_val_get_lmul_pow_1481 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1481, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1479, ret_val_get_sew_pow_1480), ret_val_get_lmul_pow_1481)), 3, true); + setArg(call_get_pow_1479, 0, reinterpret_cast(this)); + setArg(call_get_pow_1479, 1, EEW); + setRet(call_get_pow_1479, 0, ret_val_get_pow_1479); + setArg(call_get_sew_pow_1480, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1480, 0, ret_val_get_sew_pow_1480); + setArg(call_get_lmul_pow_1481, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1481, 0, ret_val_get_lmul_pow_1481); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1483; + x86::Gp ret_val_get_lmul_pow_1483 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1483, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1482; + auto illegal_indexed_store_1482_arg2 = EMUL_pow; + auto illegal_indexed_store_1482_arg3 = ret_val_get_lmul_pow_1483; + x86::Gp ret_val_illegal_indexed_store_1482 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1482, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1482; + setArg(call_get_lmul_pow_1483, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1483, 0, ret_val_get_lmul_pow_1483); + setArg(call_illegal_indexed_store_1482, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1482, 1, 4); + setArg(call_illegal_indexed_store_1482, 2, EEW); + setArg(call_illegal_indexed_store_1482, 3, illegal_indexed_store_1482_arg2); + setArg(call_illegal_indexed_store_1482, 4, illegal_indexed_store_1482_arg3); + setRet(call_illegal_indexed_store_1482, 0, ret_val_illegal_indexed_store_1482); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1485; + x86::Gp ret_val_sew_1485 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1485, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1484; + auto vsxseg_1484_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1484_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1484_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1484_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1484_arg10 = ret_val_sew_1485; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1484 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1484, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1484, 64, false), traits::vstart); + setArg(call_sew_1485, 0, reinterpret_cast(this)); + setRet(call_sew_1485, 0, ret_val_sew_1485); + setArg(call_vsxseg_1484, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1484, 1, V); + setArg(call_vsxseg_1484, 2, vsxseg_1484_arg1); + setArg(call_vsxseg_1484, 3, vsxseg_1484_arg2); + setArg(call_vsxseg_1484, 4, vsxseg_1484_arg3); + setArg(call_vsxseg_1484, 5, vm); + setArg(call_vsxseg_1484, 6, vs3); + setArg(call_vsxseg_1484, 7, vsxseg_1484_arg6); + setArg(call_vsxseg_1484, 8, vs2); + setArg(call_vsxseg_1484, 9, 4); + setArg(call_vsxseg_1484, 10, 4); + setArg(call_vsxseg_1484, 11, vsxseg_1484_arg10); + setArg(call_vsxseg_1484, 12, 1); + setRet(call_vsxseg_1484, 0, ret_val_vsxseg_1484); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 431); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 432: VSOXSEG4EI64__V */ + continuation_e __vsoxseg4ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg4ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG4EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 432); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1486; + x86::Gp ret_val_get_pow_1486 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1486, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1487; + x86::Gp ret_val_get_sew_pow_1487 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1487, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1488; + x86::Gp ret_val_get_lmul_pow_1488 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1488, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1486, ret_val_get_sew_pow_1487), ret_val_get_lmul_pow_1488)), 3, true); + setArg(call_get_pow_1486, 0, reinterpret_cast(this)); + setArg(call_get_pow_1486, 1, EEW); + setRet(call_get_pow_1486, 0, ret_val_get_pow_1486); + setArg(call_get_sew_pow_1487, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1487, 0, ret_val_get_sew_pow_1487); + setArg(call_get_lmul_pow_1488, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1488, 0, ret_val_get_lmul_pow_1488); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1490; + x86::Gp ret_val_get_lmul_pow_1490 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1490, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1489; + auto illegal_indexed_store_1489_arg2 = EMUL_pow; + auto illegal_indexed_store_1489_arg3 = ret_val_get_lmul_pow_1490; + x86::Gp ret_val_illegal_indexed_store_1489 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1489, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1489; + setArg(call_get_lmul_pow_1490, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1490, 0, ret_val_get_lmul_pow_1490); + setArg(call_illegal_indexed_store_1489, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1489, 1, 4); + setArg(call_illegal_indexed_store_1489, 2, EEW); + setArg(call_illegal_indexed_store_1489, 3, illegal_indexed_store_1489_arg2); + setArg(call_illegal_indexed_store_1489, 4, illegal_indexed_store_1489_arg3); + setRet(call_illegal_indexed_store_1489, 0, ret_val_illegal_indexed_store_1489); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1492; + x86::Gp ret_val_sew_1492 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1492, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1491; + auto vsxseg_1491_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1491_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1491_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1491_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1491_arg10 = ret_val_sew_1492; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1491 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1491, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1491, 64, false), traits::vstart); + setArg(call_sew_1492, 0, reinterpret_cast(this)); + setRet(call_sew_1492, 0, ret_val_sew_1492); + setArg(call_vsxseg_1491, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1491, 1, V); + setArg(call_vsxseg_1491, 2, vsxseg_1491_arg1); + setArg(call_vsxseg_1491, 3, vsxseg_1491_arg2); + setArg(call_vsxseg_1491, 4, vsxseg_1491_arg3); + setArg(call_vsxseg_1491, 5, vm); + setArg(call_vsxseg_1491, 6, vs3); + setArg(call_vsxseg_1491, 7, vsxseg_1491_arg6); + setArg(call_vsxseg_1491, 8, vs2); + setArg(call_vsxseg_1491, 9, 4); + setArg(call_vsxseg_1491, 10, 8); + setArg(call_vsxseg_1491, 11, vsxseg_1491_arg10); + setArg(call_vsxseg_1491, 12, 1); + setRet(call_vsxseg_1491, 0, ret_val_vsxseg_1491); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 432); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 433: VSOXSEG5EI8__V */ + continuation_e __vsoxseg5ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG5EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 433); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1493; + x86::Gp ret_val_get_pow_1493 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1493, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1494; + x86::Gp ret_val_get_sew_pow_1494 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1494, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1495; + x86::Gp ret_val_get_lmul_pow_1495 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1495, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1493, ret_val_get_sew_pow_1494), ret_val_get_lmul_pow_1495)), 3, true); + setArg(call_get_pow_1493, 0, reinterpret_cast(this)); + setArg(call_get_pow_1493, 1, EEW); + setRet(call_get_pow_1493, 0, ret_val_get_pow_1493); + setArg(call_get_sew_pow_1494, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1494, 0, ret_val_get_sew_pow_1494); + setArg(call_get_lmul_pow_1495, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1495, 0, ret_val_get_lmul_pow_1495); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1497; + x86::Gp ret_val_get_lmul_pow_1497 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1497, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1496; + auto illegal_indexed_store_1496_arg2 = EMUL_pow; + auto illegal_indexed_store_1496_arg3 = ret_val_get_lmul_pow_1497; + x86::Gp ret_val_illegal_indexed_store_1496 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1496, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1496; + setArg(call_get_lmul_pow_1497, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1497, 0, ret_val_get_lmul_pow_1497); + setArg(call_illegal_indexed_store_1496, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1496, 1, 5); + setArg(call_illegal_indexed_store_1496, 2, EEW); + setArg(call_illegal_indexed_store_1496, 3, illegal_indexed_store_1496_arg2); + setArg(call_illegal_indexed_store_1496, 4, illegal_indexed_store_1496_arg3); + setRet(call_illegal_indexed_store_1496, 0, ret_val_illegal_indexed_store_1496); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1499; + x86::Gp ret_val_sew_1499 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1499, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1498; + auto vsxseg_1498_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1498_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1498_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1498_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1498_arg10 = ret_val_sew_1499; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1498 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1498, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1498, 64, false), traits::vstart); + setArg(call_sew_1499, 0, reinterpret_cast(this)); + setRet(call_sew_1499, 0, ret_val_sew_1499); + setArg(call_vsxseg_1498, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1498, 1, V); + setArg(call_vsxseg_1498, 2, vsxseg_1498_arg1); + setArg(call_vsxseg_1498, 3, vsxseg_1498_arg2); + setArg(call_vsxseg_1498, 4, vsxseg_1498_arg3); + setArg(call_vsxseg_1498, 5, vm); + setArg(call_vsxseg_1498, 6, vs3); + setArg(call_vsxseg_1498, 7, vsxseg_1498_arg6); + setArg(call_vsxseg_1498, 8, vs2); + setArg(call_vsxseg_1498, 9, 5); + setArg(call_vsxseg_1498, 10, 1); + setArg(call_vsxseg_1498, 11, vsxseg_1498_arg10); + setArg(call_vsxseg_1498, 12, 1); + setRet(call_vsxseg_1498, 0, ret_val_vsxseg_1498); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 433); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 434: VSOXSEG5EI16__V */ + continuation_e __vsoxseg5ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG5EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 434); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1500; + x86::Gp ret_val_get_pow_1500 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1500, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1501; + x86::Gp ret_val_get_sew_pow_1501 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1501, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1502; + x86::Gp ret_val_get_lmul_pow_1502 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1502, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1500, ret_val_get_sew_pow_1501), ret_val_get_lmul_pow_1502)), 3, true); + setArg(call_get_pow_1500, 0, reinterpret_cast(this)); + setArg(call_get_pow_1500, 1, EEW); + setRet(call_get_pow_1500, 0, ret_val_get_pow_1500); + setArg(call_get_sew_pow_1501, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1501, 0, ret_val_get_sew_pow_1501); + setArg(call_get_lmul_pow_1502, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1502, 0, ret_val_get_lmul_pow_1502); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1504; + x86::Gp ret_val_get_lmul_pow_1504 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1504, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1503; + auto illegal_indexed_store_1503_arg2 = EMUL_pow; + auto illegal_indexed_store_1503_arg3 = ret_val_get_lmul_pow_1504; + x86::Gp ret_val_illegal_indexed_store_1503 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1503, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1503; + setArg(call_get_lmul_pow_1504, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1504, 0, ret_val_get_lmul_pow_1504); + setArg(call_illegal_indexed_store_1503, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1503, 1, 5); + setArg(call_illegal_indexed_store_1503, 2, EEW); + setArg(call_illegal_indexed_store_1503, 3, illegal_indexed_store_1503_arg2); + setArg(call_illegal_indexed_store_1503, 4, illegal_indexed_store_1503_arg3); + setRet(call_illegal_indexed_store_1503, 0, ret_val_illegal_indexed_store_1503); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1506; + x86::Gp ret_val_sew_1506 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1506, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1505; + auto vsxseg_1505_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1505_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1505_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1505_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1505_arg10 = ret_val_sew_1506; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1505 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1505, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1505, 64, false), traits::vstart); + setArg(call_sew_1506, 0, reinterpret_cast(this)); + setRet(call_sew_1506, 0, ret_val_sew_1506); + setArg(call_vsxseg_1505, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1505, 1, V); + setArg(call_vsxseg_1505, 2, vsxseg_1505_arg1); + setArg(call_vsxseg_1505, 3, vsxseg_1505_arg2); + setArg(call_vsxseg_1505, 4, vsxseg_1505_arg3); + setArg(call_vsxseg_1505, 5, vm); + setArg(call_vsxseg_1505, 6, vs3); + setArg(call_vsxseg_1505, 7, vsxseg_1505_arg6); + setArg(call_vsxseg_1505, 8, vs2); + setArg(call_vsxseg_1505, 9, 5); + setArg(call_vsxseg_1505, 10, 2); + setArg(call_vsxseg_1505, 11, vsxseg_1505_arg10); + setArg(call_vsxseg_1505, 12, 1); + setRet(call_vsxseg_1505, 0, ret_val_vsxseg_1505); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 434); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 435: VSOXSEG5EI32__V */ + continuation_e __vsoxseg5ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG5EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 435); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1507; + x86::Gp ret_val_get_pow_1507 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1507, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1508; + x86::Gp ret_val_get_sew_pow_1508 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1508, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1509; + x86::Gp ret_val_get_lmul_pow_1509 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1509, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1507, ret_val_get_sew_pow_1508), ret_val_get_lmul_pow_1509)), 3, true); + setArg(call_get_pow_1507, 0, reinterpret_cast(this)); + setArg(call_get_pow_1507, 1, EEW); + setRet(call_get_pow_1507, 0, ret_val_get_pow_1507); + setArg(call_get_sew_pow_1508, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1508, 0, ret_val_get_sew_pow_1508); + setArg(call_get_lmul_pow_1509, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1509, 0, ret_val_get_lmul_pow_1509); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1511; + x86::Gp ret_val_get_lmul_pow_1511 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1511, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1510; + auto illegal_indexed_store_1510_arg2 = EMUL_pow; + auto illegal_indexed_store_1510_arg3 = ret_val_get_lmul_pow_1511; + x86::Gp ret_val_illegal_indexed_store_1510 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1510, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1510; + setArg(call_get_lmul_pow_1511, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1511, 0, ret_val_get_lmul_pow_1511); + setArg(call_illegal_indexed_store_1510, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1510, 1, 5); + setArg(call_illegal_indexed_store_1510, 2, EEW); + setArg(call_illegal_indexed_store_1510, 3, illegal_indexed_store_1510_arg2); + setArg(call_illegal_indexed_store_1510, 4, illegal_indexed_store_1510_arg3); + setRet(call_illegal_indexed_store_1510, 0, ret_val_illegal_indexed_store_1510); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1513; + x86::Gp ret_val_sew_1513 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1513, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1512; + auto vsxseg_1512_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1512_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1512_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1512_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1512_arg10 = ret_val_sew_1513; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1512 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1512, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1512, 64, false), traits::vstart); + setArg(call_sew_1513, 0, reinterpret_cast(this)); + setRet(call_sew_1513, 0, ret_val_sew_1513); + setArg(call_vsxseg_1512, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1512, 1, V); + setArg(call_vsxseg_1512, 2, vsxseg_1512_arg1); + setArg(call_vsxseg_1512, 3, vsxseg_1512_arg2); + setArg(call_vsxseg_1512, 4, vsxseg_1512_arg3); + setArg(call_vsxseg_1512, 5, vm); + setArg(call_vsxseg_1512, 6, vs3); + setArg(call_vsxseg_1512, 7, vsxseg_1512_arg6); + setArg(call_vsxseg_1512, 8, vs2); + setArg(call_vsxseg_1512, 9, 5); + setArg(call_vsxseg_1512, 10, 4); + setArg(call_vsxseg_1512, 11, vsxseg_1512_arg10); + setArg(call_vsxseg_1512, 12, 1); + setRet(call_vsxseg_1512, 0, ret_val_vsxseg_1512); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 435); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 436: VSOXSEG5EI64__V */ + continuation_e __vsoxseg5ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg5ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG5EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 436); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1514; + x86::Gp ret_val_get_pow_1514 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1514, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1515; + x86::Gp ret_val_get_sew_pow_1515 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1515, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1516; + x86::Gp ret_val_get_lmul_pow_1516 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1516, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1514, ret_val_get_sew_pow_1515), ret_val_get_lmul_pow_1516)), 3, true); + setArg(call_get_pow_1514, 0, reinterpret_cast(this)); + setArg(call_get_pow_1514, 1, EEW); + setRet(call_get_pow_1514, 0, ret_val_get_pow_1514); + setArg(call_get_sew_pow_1515, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1515, 0, ret_val_get_sew_pow_1515); + setArg(call_get_lmul_pow_1516, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1516, 0, ret_val_get_lmul_pow_1516); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1518; + x86::Gp ret_val_get_lmul_pow_1518 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1518, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1517; + auto illegal_indexed_store_1517_arg2 = EMUL_pow; + auto illegal_indexed_store_1517_arg3 = ret_val_get_lmul_pow_1518; + x86::Gp ret_val_illegal_indexed_store_1517 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1517, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1517; + setArg(call_get_lmul_pow_1518, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1518, 0, ret_val_get_lmul_pow_1518); + setArg(call_illegal_indexed_store_1517, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1517, 1, 5); + setArg(call_illegal_indexed_store_1517, 2, EEW); + setArg(call_illegal_indexed_store_1517, 3, illegal_indexed_store_1517_arg2); + setArg(call_illegal_indexed_store_1517, 4, illegal_indexed_store_1517_arg3); + setRet(call_illegal_indexed_store_1517, 0, ret_val_illegal_indexed_store_1517); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1520; + x86::Gp ret_val_sew_1520 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1520, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1519; + auto vsxseg_1519_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1519_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1519_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1519_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1519_arg10 = ret_val_sew_1520; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1519 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1519, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1519, 64, false), traits::vstart); + setArg(call_sew_1520, 0, reinterpret_cast(this)); + setRet(call_sew_1520, 0, ret_val_sew_1520); + setArg(call_vsxseg_1519, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1519, 1, V); + setArg(call_vsxseg_1519, 2, vsxseg_1519_arg1); + setArg(call_vsxseg_1519, 3, vsxseg_1519_arg2); + setArg(call_vsxseg_1519, 4, vsxseg_1519_arg3); + setArg(call_vsxseg_1519, 5, vm); + setArg(call_vsxseg_1519, 6, vs3); + setArg(call_vsxseg_1519, 7, vsxseg_1519_arg6); + setArg(call_vsxseg_1519, 8, vs2); + setArg(call_vsxseg_1519, 9, 5); + setArg(call_vsxseg_1519, 10, 8); + setArg(call_vsxseg_1519, 11, vsxseg_1519_arg10); + setArg(call_vsxseg_1519, 12, 1); + setRet(call_vsxseg_1519, 0, ret_val_vsxseg_1519); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 436); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 437: VSOXSEG6EI8__V */ + continuation_e __vsoxseg6ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG6EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 437); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1521; + x86::Gp ret_val_get_pow_1521 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1521, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1522; + x86::Gp ret_val_get_sew_pow_1522 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1522, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1523; + x86::Gp ret_val_get_lmul_pow_1523 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1523, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1521, ret_val_get_sew_pow_1522), ret_val_get_lmul_pow_1523)), 3, true); + setArg(call_get_pow_1521, 0, reinterpret_cast(this)); + setArg(call_get_pow_1521, 1, EEW); + setRet(call_get_pow_1521, 0, ret_val_get_pow_1521); + setArg(call_get_sew_pow_1522, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1522, 0, ret_val_get_sew_pow_1522); + setArg(call_get_lmul_pow_1523, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1523, 0, ret_val_get_lmul_pow_1523); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1525; + x86::Gp ret_val_get_lmul_pow_1525 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1525, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1524; + auto illegal_indexed_store_1524_arg2 = EMUL_pow; + auto illegal_indexed_store_1524_arg3 = ret_val_get_lmul_pow_1525; + x86::Gp ret_val_illegal_indexed_store_1524 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1524, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1524; + setArg(call_get_lmul_pow_1525, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1525, 0, ret_val_get_lmul_pow_1525); + setArg(call_illegal_indexed_store_1524, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1524, 1, 6); + setArg(call_illegal_indexed_store_1524, 2, EEW); + setArg(call_illegal_indexed_store_1524, 3, illegal_indexed_store_1524_arg2); + setArg(call_illegal_indexed_store_1524, 4, illegal_indexed_store_1524_arg3); + setRet(call_illegal_indexed_store_1524, 0, ret_val_illegal_indexed_store_1524); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1527; + x86::Gp ret_val_sew_1527 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1527, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1526; + auto vsxseg_1526_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1526_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1526_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1526_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1526_arg10 = ret_val_sew_1527; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1526 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1526, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1526, 64, false), traits::vstart); + setArg(call_sew_1527, 0, reinterpret_cast(this)); + setRet(call_sew_1527, 0, ret_val_sew_1527); + setArg(call_vsxseg_1526, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1526, 1, V); + setArg(call_vsxseg_1526, 2, vsxseg_1526_arg1); + setArg(call_vsxseg_1526, 3, vsxseg_1526_arg2); + setArg(call_vsxseg_1526, 4, vsxseg_1526_arg3); + setArg(call_vsxseg_1526, 5, vm); + setArg(call_vsxseg_1526, 6, vs3); + setArg(call_vsxseg_1526, 7, vsxseg_1526_arg6); + setArg(call_vsxseg_1526, 8, vs2); + setArg(call_vsxseg_1526, 9, 6); + setArg(call_vsxseg_1526, 10, 1); + setArg(call_vsxseg_1526, 11, vsxseg_1526_arg10); + setArg(call_vsxseg_1526, 12, 1); + setRet(call_vsxseg_1526, 0, ret_val_vsxseg_1526); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 437); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 438: VSOXSEG6EI16__V */ + continuation_e __vsoxseg6ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG6EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 438); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1528; + x86::Gp ret_val_get_pow_1528 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1528, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1529; + x86::Gp ret_val_get_sew_pow_1529 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1529, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1530; + x86::Gp ret_val_get_lmul_pow_1530 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1530, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1528, ret_val_get_sew_pow_1529), ret_val_get_lmul_pow_1530)), 3, true); + setArg(call_get_pow_1528, 0, reinterpret_cast(this)); + setArg(call_get_pow_1528, 1, EEW); + setRet(call_get_pow_1528, 0, ret_val_get_pow_1528); + setArg(call_get_sew_pow_1529, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1529, 0, ret_val_get_sew_pow_1529); + setArg(call_get_lmul_pow_1530, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1530, 0, ret_val_get_lmul_pow_1530); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1532; + x86::Gp ret_val_get_lmul_pow_1532 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1532, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1531; + auto illegal_indexed_store_1531_arg2 = EMUL_pow; + auto illegal_indexed_store_1531_arg3 = ret_val_get_lmul_pow_1532; + x86::Gp ret_val_illegal_indexed_store_1531 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1531, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1531; + setArg(call_get_lmul_pow_1532, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1532, 0, ret_val_get_lmul_pow_1532); + setArg(call_illegal_indexed_store_1531, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1531, 1, 6); + setArg(call_illegal_indexed_store_1531, 2, EEW); + setArg(call_illegal_indexed_store_1531, 3, illegal_indexed_store_1531_arg2); + setArg(call_illegal_indexed_store_1531, 4, illegal_indexed_store_1531_arg3); + setRet(call_illegal_indexed_store_1531, 0, ret_val_illegal_indexed_store_1531); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1534; + x86::Gp ret_val_sew_1534 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1534, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1533; + auto vsxseg_1533_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1533_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1533_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1533_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1533_arg10 = ret_val_sew_1534; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1533 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1533, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1533, 64, false), traits::vstart); + setArg(call_sew_1534, 0, reinterpret_cast(this)); + setRet(call_sew_1534, 0, ret_val_sew_1534); + setArg(call_vsxseg_1533, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1533, 1, V); + setArg(call_vsxseg_1533, 2, vsxseg_1533_arg1); + setArg(call_vsxseg_1533, 3, vsxseg_1533_arg2); + setArg(call_vsxseg_1533, 4, vsxseg_1533_arg3); + setArg(call_vsxseg_1533, 5, vm); + setArg(call_vsxseg_1533, 6, vs3); + setArg(call_vsxseg_1533, 7, vsxseg_1533_arg6); + setArg(call_vsxseg_1533, 8, vs2); + setArg(call_vsxseg_1533, 9, 6); + setArg(call_vsxseg_1533, 10, 2); + setArg(call_vsxseg_1533, 11, vsxseg_1533_arg10); + setArg(call_vsxseg_1533, 12, 1); + setRet(call_vsxseg_1533, 0, ret_val_vsxseg_1533); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 438); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 439: VSOXSEG6EI32__V */ + continuation_e __vsoxseg6ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG6EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 439); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1535; + x86::Gp ret_val_get_pow_1535 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1535, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1536; + x86::Gp ret_val_get_sew_pow_1536 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1536, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1537; + x86::Gp ret_val_get_lmul_pow_1537 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1537, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1535, ret_val_get_sew_pow_1536), ret_val_get_lmul_pow_1537)), 3, true); + setArg(call_get_pow_1535, 0, reinterpret_cast(this)); + setArg(call_get_pow_1535, 1, EEW); + setRet(call_get_pow_1535, 0, ret_val_get_pow_1535); + setArg(call_get_sew_pow_1536, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1536, 0, ret_val_get_sew_pow_1536); + setArg(call_get_lmul_pow_1537, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1537, 0, ret_val_get_lmul_pow_1537); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1539; + x86::Gp ret_val_get_lmul_pow_1539 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1539, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1538; + auto illegal_indexed_store_1538_arg2 = EMUL_pow; + auto illegal_indexed_store_1538_arg3 = ret_val_get_lmul_pow_1539; + x86::Gp ret_val_illegal_indexed_store_1538 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1538, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1538; + setArg(call_get_lmul_pow_1539, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1539, 0, ret_val_get_lmul_pow_1539); + setArg(call_illegal_indexed_store_1538, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1538, 1, 6); + setArg(call_illegal_indexed_store_1538, 2, EEW); + setArg(call_illegal_indexed_store_1538, 3, illegal_indexed_store_1538_arg2); + setArg(call_illegal_indexed_store_1538, 4, illegal_indexed_store_1538_arg3); + setRet(call_illegal_indexed_store_1538, 0, ret_val_illegal_indexed_store_1538); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1541; + x86::Gp ret_val_sew_1541 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1541, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1540; + auto vsxseg_1540_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1540_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1540_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1540_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1540_arg10 = ret_val_sew_1541; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1540 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1540, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1540, 64, false), traits::vstart); + setArg(call_sew_1541, 0, reinterpret_cast(this)); + setRet(call_sew_1541, 0, ret_val_sew_1541); + setArg(call_vsxseg_1540, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1540, 1, V); + setArg(call_vsxseg_1540, 2, vsxseg_1540_arg1); + setArg(call_vsxseg_1540, 3, vsxseg_1540_arg2); + setArg(call_vsxseg_1540, 4, vsxseg_1540_arg3); + setArg(call_vsxseg_1540, 5, vm); + setArg(call_vsxseg_1540, 6, vs3); + setArg(call_vsxseg_1540, 7, vsxseg_1540_arg6); + setArg(call_vsxseg_1540, 8, vs2); + setArg(call_vsxseg_1540, 9, 6); + setArg(call_vsxseg_1540, 10, 4); + setArg(call_vsxseg_1540, 11, vsxseg_1540_arg10); + setArg(call_vsxseg_1540, 12, 1); + setRet(call_vsxseg_1540, 0, ret_val_vsxseg_1540); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 439); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 440: VSOXSEG6EI64__V */ + continuation_e __vsoxseg6ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg6ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG6EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 440); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1542; + x86::Gp ret_val_get_pow_1542 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1542, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1543; + x86::Gp ret_val_get_sew_pow_1543 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1543, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1544; + x86::Gp ret_val_get_lmul_pow_1544 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1544, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1542, ret_val_get_sew_pow_1543), ret_val_get_lmul_pow_1544)), 3, true); + setArg(call_get_pow_1542, 0, reinterpret_cast(this)); + setArg(call_get_pow_1542, 1, EEW); + setRet(call_get_pow_1542, 0, ret_val_get_pow_1542); + setArg(call_get_sew_pow_1543, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1543, 0, ret_val_get_sew_pow_1543); + setArg(call_get_lmul_pow_1544, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1544, 0, ret_val_get_lmul_pow_1544); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1546; + x86::Gp ret_val_get_lmul_pow_1546 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1546, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1545; + auto illegal_indexed_store_1545_arg2 = EMUL_pow; + auto illegal_indexed_store_1545_arg3 = ret_val_get_lmul_pow_1546; + x86::Gp ret_val_illegal_indexed_store_1545 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1545, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1545; + setArg(call_get_lmul_pow_1546, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1546, 0, ret_val_get_lmul_pow_1546); + setArg(call_illegal_indexed_store_1545, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1545, 1, 6); + setArg(call_illegal_indexed_store_1545, 2, EEW); + setArg(call_illegal_indexed_store_1545, 3, illegal_indexed_store_1545_arg2); + setArg(call_illegal_indexed_store_1545, 4, illegal_indexed_store_1545_arg3); + setRet(call_illegal_indexed_store_1545, 0, ret_val_illegal_indexed_store_1545); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1548; + x86::Gp ret_val_sew_1548 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1548, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1547; + auto vsxseg_1547_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1547_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1547_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1547_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1547_arg10 = ret_val_sew_1548; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1547 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1547, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1547, 64, false), traits::vstart); + setArg(call_sew_1548, 0, reinterpret_cast(this)); + setRet(call_sew_1548, 0, ret_val_sew_1548); + setArg(call_vsxseg_1547, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1547, 1, V); + setArg(call_vsxseg_1547, 2, vsxseg_1547_arg1); + setArg(call_vsxseg_1547, 3, vsxseg_1547_arg2); + setArg(call_vsxseg_1547, 4, vsxseg_1547_arg3); + setArg(call_vsxseg_1547, 5, vm); + setArg(call_vsxseg_1547, 6, vs3); + setArg(call_vsxseg_1547, 7, vsxseg_1547_arg6); + setArg(call_vsxseg_1547, 8, vs2); + setArg(call_vsxseg_1547, 9, 6); + setArg(call_vsxseg_1547, 10, 8); + setArg(call_vsxseg_1547, 11, vsxseg_1547_arg10); + setArg(call_vsxseg_1547, 12, 1); + setRet(call_vsxseg_1547, 0, ret_val_vsxseg_1547); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 440); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 441: VSOXSEG7EI8__V */ + continuation_e __vsoxseg7ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG7EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 441); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1549; + x86::Gp ret_val_get_pow_1549 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1549, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1550; + x86::Gp ret_val_get_sew_pow_1550 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1550, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1551; + x86::Gp ret_val_get_lmul_pow_1551 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1551, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1549, ret_val_get_sew_pow_1550), ret_val_get_lmul_pow_1551)), 3, true); + setArg(call_get_pow_1549, 0, reinterpret_cast(this)); + setArg(call_get_pow_1549, 1, EEW); + setRet(call_get_pow_1549, 0, ret_val_get_pow_1549); + setArg(call_get_sew_pow_1550, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1550, 0, ret_val_get_sew_pow_1550); + setArg(call_get_lmul_pow_1551, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1551, 0, ret_val_get_lmul_pow_1551); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1553; + x86::Gp ret_val_get_lmul_pow_1553 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1553, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1552; + auto illegal_indexed_store_1552_arg2 = EMUL_pow; + auto illegal_indexed_store_1552_arg3 = ret_val_get_lmul_pow_1553; + x86::Gp ret_val_illegal_indexed_store_1552 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1552, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1552; + setArg(call_get_lmul_pow_1553, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1553, 0, ret_val_get_lmul_pow_1553); + setArg(call_illegal_indexed_store_1552, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1552, 1, 7); + setArg(call_illegal_indexed_store_1552, 2, EEW); + setArg(call_illegal_indexed_store_1552, 3, illegal_indexed_store_1552_arg2); + setArg(call_illegal_indexed_store_1552, 4, illegal_indexed_store_1552_arg3); + setRet(call_illegal_indexed_store_1552, 0, ret_val_illegal_indexed_store_1552); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1555; + x86::Gp ret_val_sew_1555 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1555, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1554; + auto vsxseg_1554_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1554_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1554_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1554_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1554_arg10 = ret_val_sew_1555; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1554 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1554, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1554, 64, false), traits::vstart); + setArg(call_sew_1555, 0, reinterpret_cast(this)); + setRet(call_sew_1555, 0, ret_val_sew_1555); + setArg(call_vsxseg_1554, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1554, 1, V); + setArg(call_vsxseg_1554, 2, vsxseg_1554_arg1); + setArg(call_vsxseg_1554, 3, vsxseg_1554_arg2); + setArg(call_vsxseg_1554, 4, vsxseg_1554_arg3); + setArg(call_vsxseg_1554, 5, vm); + setArg(call_vsxseg_1554, 6, vs3); + setArg(call_vsxseg_1554, 7, vsxseg_1554_arg6); + setArg(call_vsxseg_1554, 8, vs2); + setArg(call_vsxseg_1554, 9, 7); + setArg(call_vsxseg_1554, 10, 1); + setArg(call_vsxseg_1554, 11, vsxseg_1554_arg10); + setArg(call_vsxseg_1554, 12, 1); + setRet(call_vsxseg_1554, 0, ret_val_vsxseg_1554); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 441); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 442: VSOXSEG7EI16__V */ + continuation_e __vsoxseg7ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG7EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 442); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1556; + x86::Gp ret_val_get_pow_1556 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1556, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1557; + x86::Gp ret_val_get_sew_pow_1557 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1557, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1558; + x86::Gp ret_val_get_lmul_pow_1558 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1558, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1556, ret_val_get_sew_pow_1557), ret_val_get_lmul_pow_1558)), 3, true); + setArg(call_get_pow_1556, 0, reinterpret_cast(this)); + setArg(call_get_pow_1556, 1, EEW); + setRet(call_get_pow_1556, 0, ret_val_get_pow_1556); + setArg(call_get_sew_pow_1557, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1557, 0, ret_val_get_sew_pow_1557); + setArg(call_get_lmul_pow_1558, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1558, 0, ret_val_get_lmul_pow_1558); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1560; + x86::Gp ret_val_get_lmul_pow_1560 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1560, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1559; + auto illegal_indexed_store_1559_arg2 = EMUL_pow; + auto illegal_indexed_store_1559_arg3 = ret_val_get_lmul_pow_1560; + x86::Gp ret_val_illegal_indexed_store_1559 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1559, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1559; + setArg(call_get_lmul_pow_1560, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1560, 0, ret_val_get_lmul_pow_1560); + setArg(call_illegal_indexed_store_1559, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1559, 1, 7); + setArg(call_illegal_indexed_store_1559, 2, EEW); + setArg(call_illegal_indexed_store_1559, 3, illegal_indexed_store_1559_arg2); + setArg(call_illegal_indexed_store_1559, 4, illegal_indexed_store_1559_arg3); + setRet(call_illegal_indexed_store_1559, 0, ret_val_illegal_indexed_store_1559); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1562; + x86::Gp ret_val_sew_1562 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1562, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1561; + auto vsxseg_1561_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1561_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1561_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1561_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1561_arg10 = ret_val_sew_1562; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1561 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1561, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1561, 64, false), traits::vstart); + setArg(call_sew_1562, 0, reinterpret_cast(this)); + setRet(call_sew_1562, 0, ret_val_sew_1562); + setArg(call_vsxseg_1561, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1561, 1, V); + setArg(call_vsxseg_1561, 2, vsxseg_1561_arg1); + setArg(call_vsxseg_1561, 3, vsxseg_1561_arg2); + setArg(call_vsxseg_1561, 4, vsxseg_1561_arg3); + setArg(call_vsxseg_1561, 5, vm); + setArg(call_vsxseg_1561, 6, vs3); + setArg(call_vsxseg_1561, 7, vsxseg_1561_arg6); + setArg(call_vsxseg_1561, 8, vs2); + setArg(call_vsxseg_1561, 9, 7); + setArg(call_vsxseg_1561, 10, 2); + setArg(call_vsxseg_1561, 11, vsxseg_1561_arg10); + setArg(call_vsxseg_1561, 12, 1); + setRet(call_vsxseg_1561, 0, ret_val_vsxseg_1561); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 442); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 443: VSOXSEG7EI32__V */ + continuation_e __vsoxseg7ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG7EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 443); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1563; + x86::Gp ret_val_get_pow_1563 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1563, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1564; + x86::Gp ret_val_get_sew_pow_1564 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1564, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1565; + x86::Gp ret_val_get_lmul_pow_1565 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1565, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1563, ret_val_get_sew_pow_1564), ret_val_get_lmul_pow_1565)), 3, true); + setArg(call_get_pow_1563, 0, reinterpret_cast(this)); + setArg(call_get_pow_1563, 1, EEW); + setRet(call_get_pow_1563, 0, ret_val_get_pow_1563); + setArg(call_get_sew_pow_1564, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1564, 0, ret_val_get_sew_pow_1564); + setArg(call_get_lmul_pow_1565, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1565, 0, ret_val_get_lmul_pow_1565); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1567; + x86::Gp ret_val_get_lmul_pow_1567 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1567, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1566; + auto illegal_indexed_store_1566_arg2 = EMUL_pow; + auto illegal_indexed_store_1566_arg3 = ret_val_get_lmul_pow_1567; + x86::Gp ret_val_illegal_indexed_store_1566 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1566, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1566; + setArg(call_get_lmul_pow_1567, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1567, 0, ret_val_get_lmul_pow_1567); + setArg(call_illegal_indexed_store_1566, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1566, 1, 7); + setArg(call_illegal_indexed_store_1566, 2, EEW); + setArg(call_illegal_indexed_store_1566, 3, illegal_indexed_store_1566_arg2); + setArg(call_illegal_indexed_store_1566, 4, illegal_indexed_store_1566_arg3); + setRet(call_illegal_indexed_store_1566, 0, ret_val_illegal_indexed_store_1566); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1569; + x86::Gp ret_val_sew_1569 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1569, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1568; + auto vsxseg_1568_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1568_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1568_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1568_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1568_arg10 = ret_val_sew_1569; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1568 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1568, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1568, 64, false), traits::vstart); + setArg(call_sew_1569, 0, reinterpret_cast(this)); + setRet(call_sew_1569, 0, ret_val_sew_1569); + setArg(call_vsxseg_1568, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1568, 1, V); + setArg(call_vsxseg_1568, 2, vsxseg_1568_arg1); + setArg(call_vsxseg_1568, 3, vsxseg_1568_arg2); + setArg(call_vsxseg_1568, 4, vsxseg_1568_arg3); + setArg(call_vsxseg_1568, 5, vm); + setArg(call_vsxseg_1568, 6, vs3); + setArg(call_vsxseg_1568, 7, vsxseg_1568_arg6); + setArg(call_vsxseg_1568, 8, vs2); + setArg(call_vsxseg_1568, 9, 7); + setArg(call_vsxseg_1568, 10, 4); + setArg(call_vsxseg_1568, 11, vsxseg_1568_arg10); + setArg(call_vsxseg_1568, 12, 1); + setRet(call_vsxseg_1568, 0, ret_val_vsxseg_1568); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 443); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 444: VSOXSEG7EI64__V */ + continuation_e __vsoxseg7ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg7ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG7EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 444); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1570; + x86::Gp ret_val_get_pow_1570 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1570, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1571; + x86::Gp ret_val_get_sew_pow_1571 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1571, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1572; + x86::Gp ret_val_get_lmul_pow_1572 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1572, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1570, ret_val_get_sew_pow_1571), ret_val_get_lmul_pow_1572)), 3, true); + setArg(call_get_pow_1570, 0, reinterpret_cast(this)); + setArg(call_get_pow_1570, 1, EEW); + setRet(call_get_pow_1570, 0, ret_val_get_pow_1570); + setArg(call_get_sew_pow_1571, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1571, 0, ret_val_get_sew_pow_1571); + setArg(call_get_lmul_pow_1572, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1572, 0, ret_val_get_lmul_pow_1572); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1574; + x86::Gp ret_val_get_lmul_pow_1574 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1574, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1573; + auto illegal_indexed_store_1573_arg2 = EMUL_pow; + auto illegal_indexed_store_1573_arg3 = ret_val_get_lmul_pow_1574; + x86::Gp ret_val_illegal_indexed_store_1573 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1573, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1573; + setArg(call_get_lmul_pow_1574, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1574, 0, ret_val_get_lmul_pow_1574); + setArg(call_illegal_indexed_store_1573, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1573, 1, 7); + setArg(call_illegal_indexed_store_1573, 2, EEW); + setArg(call_illegal_indexed_store_1573, 3, illegal_indexed_store_1573_arg2); + setArg(call_illegal_indexed_store_1573, 4, illegal_indexed_store_1573_arg3); + setRet(call_illegal_indexed_store_1573, 0, ret_val_illegal_indexed_store_1573); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1576; + x86::Gp ret_val_sew_1576 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1576, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1575; + auto vsxseg_1575_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1575_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1575_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1575_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1575_arg10 = ret_val_sew_1576; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1575 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1575, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1575, 64, false), traits::vstart); + setArg(call_sew_1576, 0, reinterpret_cast(this)); + setRet(call_sew_1576, 0, ret_val_sew_1576); + setArg(call_vsxseg_1575, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1575, 1, V); + setArg(call_vsxseg_1575, 2, vsxseg_1575_arg1); + setArg(call_vsxseg_1575, 3, vsxseg_1575_arg2); + setArg(call_vsxseg_1575, 4, vsxseg_1575_arg3); + setArg(call_vsxseg_1575, 5, vm); + setArg(call_vsxseg_1575, 6, vs3); + setArg(call_vsxseg_1575, 7, vsxseg_1575_arg6); + setArg(call_vsxseg_1575, 8, vs2); + setArg(call_vsxseg_1575, 9, 7); + setArg(call_vsxseg_1575, 10, 8); + setArg(call_vsxseg_1575, 11, vsxseg_1575_arg10); + setArg(call_vsxseg_1575, 12, 1); + setRet(call_vsxseg_1575, 0, ret_val_vsxseg_1575); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 444); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 445: VSOXSEG8EI8__V */ + continuation_e __vsoxseg8ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG8EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 445); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1577; + x86::Gp ret_val_get_pow_1577 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1577, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1578; + x86::Gp ret_val_get_sew_pow_1578 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1578, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1579; + x86::Gp ret_val_get_lmul_pow_1579 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1579, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1577, ret_val_get_sew_pow_1578), ret_val_get_lmul_pow_1579)), 3, true); + setArg(call_get_pow_1577, 0, reinterpret_cast(this)); + setArg(call_get_pow_1577, 1, EEW); + setRet(call_get_pow_1577, 0, ret_val_get_pow_1577); + setArg(call_get_sew_pow_1578, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1578, 0, ret_val_get_sew_pow_1578); + setArg(call_get_lmul_pow_1579, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1579, 0, ret_val_get_lmul_pow_1579); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1581; + x86::Gp ret_val_get_lmul_pow_1581 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1581, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1580; + auto illegal_indexed_store_1580_arg2 = EMUL_pow; + auto illegal_indexed_store_1580_arg3 = ret_val_get_lmul_pow_1581; + x86::Gp ret_val_illegal_indexed_store_1580 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1580, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1580; + setArg(call_get_lmul_pow_1581, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1581, 0, ret_val_get_lmul_pow_1581); + setArg(call_illegal_indexed_store_1580, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1580, 1, 8); + setArg(call_illegal_indexed_store_1580, 2, EEW); + setArg(call_illegal_indexed_store_1580, 3, illegal_indexed_store_1580_arg2); + setArg(call_illegal_indexed_store_1580, 4, illegal_indexed_store_1580_arg3); + setRet(call_illegal_indexed_store_1580, 0, ret_val_illegal_indexed_store_1580); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1583; + x86::Gp ret_val_sew_1583 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1583, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1582; + auto vsxseg_1582_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1582_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1582_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1582_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1582_arg10 = ret_val_sew_1583; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1582 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1582, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1582, 64, false), traits::vstart); + setArg(call_sew_1583, 0, reinterpret_cast(this)); + setRet(call_sew_1583, 0, ret_val_sew_1583); + setArg(call_vsxseg_1582, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1582, 1, V); + setArg(call_vsxseg_1582, 2, vsxseg_1582_arg1); + setArg(call_vsxseg_1582, 3, vsxseg_1582_arg2); + setArg(call_vsxseg_1582, 4, vsxseg_1582_arg3); + setArg(call_vsxseg_1582, 5, vm); + setArg(call_vsxseg_1582, 6, vs3); + setArg(call_vsxseg_1582, 7, vsxseg_1582_arg6); + setArg(call_vsxseg_1582, 8, vs2); + setArg(call_vsxseg_1582, 9, 8); + setArg(call_vsxseg_1582, 10, 1); + setArg(call_vsxseg_1582, 11, vsxseg_1582_arg10); + setArg(call_vsxseg_1582, 12, 1); + setRet(call_vsxseg_1582, 0, ret_val_vsxseg_1582); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 445); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 446: VSOXSEG8EI16__V */ + continuation_e __vsoxseg8ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG8EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 446); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1584; + x86::Gp ret_val_get_pow_1584 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1584, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1585; + x86::Gp ret_val_get_sew_pow_1585 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1585, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1586; + x86::Gp ret_val_get_lmul_pow_1586 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1586, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1584, ret_val_get_sew_pow_1585), ret_val_get_lmul_pow_1586)), 3, true); + setArg(call_get_pow_1584, 0, reinterpret_cast(this)); + setArg(call_get_pow_1584, 1, EEW); + setRet(call_get_pow_1584, 0, ret_val_get_pow_1584); + setArg(call_get_sew_pow_1585, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1585, 0, ret_val_get_sew_pow_1585); + setArg(call_get_lmul_pow_1586, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1586, 0, ret_val_get_lmul_pow_1586); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1588; + x86::Gp ret_val_get_lmul_pow_1588 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1588, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1587; + auto illegal_indexed_store_1587_arg2 = EMUL_pow; + auto illegal_indexed_store_1587_arg3 = ret_val_get_lmul_pow_1588; + x86::Gp ret_val_illegal_indexed_store_1587 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1587, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1587; + setArg(call_get_lmul_pow_1588, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1588, 0, ret_val_get_lmul_pow_1588); + setArg(call_illegal_indexed_store_1587, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1587, 1, 8); + setArg(call_illegal_indexed_store_1587, 2, EEW); + setArg(call_illegal_indexed_store_1587, 3, illegal_indexed_store_1587_arg2); + setArg(call_illegal_indexed_store_1587, 4, illegal_indexed_store_1587_arg3); + setRet(call_illegal_indexed_store_1587, 0, ret_val_illegal_indexed_store_1587); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1590; + x86::Gp ret_val_sew_1590 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1590, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1589; + auto vsxseg_1589_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1589_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1589_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1589_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1589_arg10 = ret_val_sew_1590; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1589 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1589, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1589, 64, false), traits::vstart); + setArg(call_sew_1590, 0, reinterpret_cast(this)); + setRet(call_sew_1590, 0, ret_val_sew_1590); + setArg(call_vsxseg_1589, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1589, 1, V); + setArg(call_vsxseg_1589, 2, vsxseg_1589_arg1); + setArg(call_vsxseg_1589, 3, vsxseg_1589_arg2); + setArg(call_vsxseg_1589, 4, vsxseg_1589_arg3); + setArg(call_vsxseg_1589, 5, vm); + setArg(call_vsxseg_1589, 6, vs3); + setArg(call_vsxseg_1589, 7, vsxseg_1589_arg6); + setArg(call_vsxseg_1589, 8, vs2); + setArg(call_vsxseg_1589, 9, 8); + setArg(call_vsxseg_1589, 10, 2); + setArg(call_vsxseg_1589, 11, vsxseg_1589_arg10); + setArg(call_vsxseg_1589, 12, 1); + setRet(call_vsxseg_1589, 0, ret_val_vsxseg_1589); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 446); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 447: VSOXSEG8EI32__V */ + continuation_e __vsoxseg8ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG8EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 447); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1591; + x86::Gp ret_val_get_pow_1591 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1591, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1592; + x86::Gp ret_val_get_sew_pow_1592 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1592, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1593; + x86::Gp ret_val_get_lmul_pow_1593 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1593, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1591, ret_val_get_sew_pow_1592), ret_val_get_lmul_pow_1593)), 3, true); + setArg(call_get_pow_1591, 0, reinterpret_cast(this)); + setArg(call_get_pow_1591, 1, EEW); + setRet(call_get_pow_1591, 0, ret_val_get_pow_1591); + setArg(call_get_sew_pow_1592, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1592, 0, ret_val_get_sew_pow_1592); + setArg(call_get_lmul_pow_1593, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1593, 0, ret_val_get_lmul_pow_1593); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1595; + x86::Gp ret_val_get_lmul_pow_1595 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1595, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1594; + auto illegal_indexed_store_1594_arg2 = EMUL_pow; + auto illegal_indexed_store_1594_arg3 = ret_val_get_lmul_pow_1595; + x86::Gp ret_val_illegal_indexed_store_1594 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1594, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1594; + setArg(call_get_lmul_pow_1595, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1595, 0, ret_val_get_lmul_pow_1595); + setArg(call_illegal_indexed_store_1594, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1594, 1, 8); + setArg(call_illegal_indexed_store_1594, 2, EEW); + setArg(call_illegal_indexed_store_1594, 3, illegal_indexed_store_1594_arg2); + setArg(call_illegal_indexed_store_1594, 4, illegal_indexed_store_1594_arg3); + setRet(call_illegal_indexed_store_1594, 0, ret_val_illegal_indexed_store_1594); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1597; + x86::Gp ret_val_sew_1597 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1597, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1596; + auto vsxseg_1596_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1596_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1596_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1596_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1596_arg10 = ret_val_sew_1597; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1596 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1596, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1596, 64, false), traits::vstart); + setArg(call_sew_1597, 0, reinterpret_cast(this)); + setRet(call_sew_1597, 0, ret_val_sew_1597); + setArg(call_vsxseg_1596, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1596, 1, V); + setArg(call_vsxseg_1596, 2, vsxseg_1596_arg1); + setArg(call_vsxseg_1596, 3, vsxseg_1596_arg2); + setArg(call_vsxseg_1596, 4, vsxseg_1596_arg3); + setArg(call_vsxseg_1596, 5, vm); + setArg(call_vsxseg_1596, 6, vs3); + setArg(call_vsxseg_1596, 7, vsxseg_1596_arg6); + setArg(call_vsxseg_1596, 8, vs2); + setArg(call_vsxseg_1596, 9, 8); + setArg(call_vsxseg_1596, 10, 4); + setArg(call_vsxseg_1596, 11, vsxseg_1596_arg10); + setArg(call_vsxseg_1596, 12, 1); + setRet(call_vsxseg_1596, 0, ret_val_vsxseg_1596); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 447); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 448: VSOXSEG8EI64__V */ + continuation_e __vsoxseg8ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsoxseg8ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSOXSEG8EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 448); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1598; + x86::Gp ret_val_get_pow_1598 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1598, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1599; + x86::Gp ret_val_get_sew_pow_1599 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1599, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1600; + x86::Gp ret_val_get_lmul_pow_1600 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1600, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1598, ret_val_get_sew_pow_1599), ret_val_get_lmul_pow_1600)), 3, true); + setArg(call_get_pow_1598, 0, reinterpret_cast(this)); + setArg(call_get_pow_1598, 1, EEW); + setRet(call_get_pow_1598, 0, ret_val_get_pow_1598); + setArg(call_get_sew_pow_1599, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1599, 0, ret_val_get_sew_pow_1599); + setArg(call_get_lmul_pow_1600, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1600, 0, ret_val_get_lmul_pow_1600); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1602; + x86::Gp ret_val_get_lmul_pow_1602 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1602, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1601; + auto illegal_indexed_store_1601_arg2 = EMUL_pow; + auto illegal_indexed_store_1601_arg3 = ret_val_get_lmul_pow_1602; + x86::Gp ret_val_illegal_indexed_store_1601 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1601, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1601; + setArg(call_get_lmul_pow_1602, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1602, 0, ret_val_get_lmul_pow_1602); + setArg(call_illegal_indexed_store_1601, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1601, 1, 8); + setArg(call_illegal_indexed_store_1601, 2, EEW); + setArg(call_illegal_indexed_store_1601, 3, illegal_indexed_store_1601_arg2); + setArg(call_illegal_indexed_store_1601, 4, illegal_indexed_store_1601_arg3); + setRet(call_illegal_indexed_store_1601, 0, ret_val_illegal_indexed_store_1601); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1604; + x86::Gp ret_val_sew_1604 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1604, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1603; + auto vsxseg_1603_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1603_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1603_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1603_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1603_arg10 = ret_val_sew_1604; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1603 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1603, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1603, 64, false), traits::vstart); + setArg(call_sew_1604, 0, reinterpret_cast(this)); + setRet(call_sew_1604, 0, ret_val_sew_1604); + setArg(call_vsxseg_1603, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1603, 1, V); + setArg(call_vsxseg_1603, 2, vsxseg_1603_arg1); + setArg(call_vsxseg_1603, 3, vsxseg_1603_arg2); + setArg(call_vsxseg_1603, 4, vsxseg_1603_arg3); + setArg(call_vsxseg_1603, 5, vm); + setArg(call_vsxseg_1603, 6, vs3); + setArg(call_vsxseg_1603, 7, vsxseg_1603_arg6); + setArg(call_vsxseg_1603, 8, vs2); + setArg(call_vsxseg_1603, 9, 8); + setArg(call_vsxseg_1603, 10, 8); + setArg(call_vsxseg_1603, 11, vsxseg_1603_arg10); + setArg(call_vsxseg_1603, 12, 1); + setRet(call_vsxseg_1603, 0, ret_val_vsxseg_1603); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 448); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 449: VLUXEI8__V */ + continuation_e __vluxei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXEI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 449); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1605; + x86::Gp ret_val_get_pow_1605 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1605, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1606; + x86::Gp ret_val_get_sew_pow_1606 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1606, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1607; + x86::Gp ret_val_get_lmul_pow_1607 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1607, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1605, ret_val_get_sew_pow_1606), ret_val_get_lmul_pow_1607)), 3, true); + setArg(call_get_pow_1605, 0, reinterpret_cast(this)); + setArg(call_get_pow_1605, 1, EEW); + setRet(call_get_pow_1605, 0, ret_val_get_pow_1605); + setArg(call_get_sew_pow_1606, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1606, 0, ret_val_get_sew_pow_1606); + setArg(call_get_lmul_pow_1607, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1607, 0, ret_val_get_lmul_pow_1607); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1609; + x86::Gp ret_val_get_lmul_pow_1609 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1609, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1608; + auto illegal_indexed_load_1608_arg4 = EMUL_pow; + auto illegal_indexed_load_1608_arg5 = ret_val_get_lmul_pow_1609; + x86::Gp ret_val_illegal_indexed_load_1608 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1608, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1608; + setArg(call_get_lmul_pow_1609, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1609, 0, ret_val_get_lmul_pow_1609); + setArg(call_illegal_indexed_load_1608, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1608, 1, vd); + setArg(call_illegal_indexed_load_1608, 2, vm); + setArg(call_illegal_indexed_load_1608, 3, 1); + setArg(call_illegal_indexed_load_1608, 4, EEW); + setArg(call_illegal_indexed_load_1608, 5, illegal_indexed_load_1608_arg4); + setArg(call_illegal_indexed_load_1608, 6, illegal_indexed_load_1608_arg5); + setRet(call_illegal_indexed_load_1608, 0, ret_val_illegal_indexed_load_1608); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1611; + x86::Gp ret_val_sew_1611 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1611, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1610; + auto vlxseg_1610_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1610_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1610_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1610_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1610_arg10 = ret_val_sew_1611; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1610 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1610, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1610, 64, false), traits::vstart); + setArg(call_sew_1611, 0, reinterpret_cast(this)); + setRet(call_sew_1611, 0, ret_val_sew_1611); + setArg(call_vlxseg_1610, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1610, 1, V); + setArg(call_vlxseg_1610, 2, vlxseg_1610_arg1); + setArg(call_vlxseg_1610, 3, vlxseg_1610_arg2); + setArg(call_vlxseg_1610, 4, vlxseg_1610_arg3); + setArg(call_vlxseg_1610, 5, vm); + setArg(call_vlxseg_1610, 6, vd); + setArg(call_vlxseg_1610, 7, vlxseg_1610_arg6); + setArg(call_vlxseg_1610, 8, vs2); + setArg(call_vlxseg_1610, 9, 1); + setArg(call_vlxseg_1610, 10, 1); + setArg(call_vlxseg_1610, 11, vlxseg_1610_arg10); + setArg(call_vlxseg_1610, 12, 0); + setRet(call_vlxseg_1610, 0, ret_val_vlxseg_1610); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 449); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 450: VLUXEI16__V */ + continuation_e __vluxei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXEI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 450); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1612; + x86::Gp ret_val_get_pow_1612 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1612, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1613; + x86::Gp ret_val_get_sew_pow_1613 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1613, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1614; + x86::Gp ret_val_get_lmul_pow_1614 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1614, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1612, ret_val_get_sew_pow_1613), ret_val_get_lmul_pow_1614)), 3, true); + setArg(call_get_pow_1612, 0, reinterpret_cast(this)); + setArg(call_get_pow_1612, 1, EEW); + setRet(call_get_pow_1612, 0, ret_val_get_pow_1612); + setArg(call_get_sew_pow_1613, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1613, 0, ret_val_get_sew_pow_1613); + setArg(call_get_lmul_pow_1614, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1614, 0, ret_val_get_lmul_pow_1614); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1616; + x86::Gp ret_val_get_lmul_pow_1616 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1616, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1615; + auto illegal_indexed_load_1615_arg4 = EMUL_pow; + auto illegal_indexed_load_1615_arg5 = ret_val_get_lmul_pow_1616; + x86::Gp ret_val_illegal_indexed_load_1615 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1615, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1615; + setArg(call_get_lmul_pow_1616, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1616, 0, ret_val_get_lmul_pow_1616); + setArg(call_illegal_indexed_load_1615, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1615, 1, vd); + setArg(call_illegal_indexed_load_1615, 2, vm); + setArg(call_illegal_indexed_load_1615, 3, 1); + setArg(call_illegal_indexed_load_1615, 4, EEW); + setArg(call_illegal_indexed_load_1615, 5, illegal_indexed_load_1615_arg4); + setArg(call_illegal_indexed_load_1615, 6, illegal_indexed_load_1615_arg5); + setRet(call_illegal_indexed_load_1615, 0, ret_val_illegal_indexed_load_1615); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1618; + x86::Gp ret_val_sew_1618 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1618, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1617; + auto vlxseg_1617_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1617_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1617_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1617_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1617_arg10 = ret_val_sew_1618; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1617 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1617, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1617, 64, false), traits::vstart); + setArg(call_sew_1618, 0, reinterpret_cast(this)); + setRet(call_sew_1618, 0, ret_val_sew_1618); + setArg(call_vlxseg_1617, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1617, 1, V); + setArg(call_vlxseg_1617, 2, vlxseg_1617_arg1); + setArg(call_vlxseg_1617, 3, vlxseg_1617_arg2); + setArg(call_vlxseg_1617, 4, vlxseg_1617_arg3); + setArg(call_vlxseg_1617, 5, vm); + setArg(call_vlxseg_1617, 6, vd); + setArg(call_vlxseg_1617, 7, vlxseg_1617_arg6); + setArg(call_vlxseg_1617, 8, vs2); + setArg(call_vlxseg_1617, 9, 1); + setArg(call_vlxseg_1617, 10, 2); + setArg(call_vlxseg_1617, 11, vlxseg_1617_arg10); + setArg(call_vlxseg_1617, 12, 0); + setRet(call_vlxseg_1617, 0, ret_val_vlxseg_1617); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 450); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 451: VLUXEI32__V */ + continuation_e __vluxei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXEI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 451); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1619; + x86::Gp ret_val_get_pow_1619 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1619, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1620; + x86::Gp ret_val_get_sew_pow_1620 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1620, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1621; + x86::Gp ret_val_get_lmul_pow_1621 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1621, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1619, ret_val_get_sew_pow_1620), ret_val_get_lmul_pow_1621)), 3, true); + setArg(call_get_pow_1619, 0, reinterpret_cast(this)); + setArg(call_get_pow_1619, 1, EEW); + setRet(call_get_pow_1619, 0, ret_val_get_pow_1619); + setArg(call_get_sew_pow_1620, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1620, 0, ret_val_get_sew_pow_1620); + setArg(call_get_lmul_pow_1621, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1621, 0, ret_val_get_lmul_pow_1621); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1623; + x86::Gp ret_val_get_lmul_pow_1623 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1623, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1622; + auto illegal_indexed_load_1622_arg4 = EMUL_pow; + auto illegal_indexed_load_1622_arg5 = ret_val_get_lmul_pow_1623; + x86::Gp ret_val_illegal_indexed_load_1622 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1622, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1622; + setArg(call_get_lmul_pow_1623, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1623, 0, ret_val_get_lmul_pow_1623); + setArg(call_illegal_indexed_load_1622, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1622, 1, vd); + setArg(call_illegal_indexed_load_1622, 2, vm); + setArg(call_illegal_indexed_load_1622, 3, 1); + setArg(call_illegal_indexed_load_1622, 4, EEW); + setArg(call_illegal_indexed_load_1622, 5, illegal_indexed_load_1622_arg4); + setArg(call_illegal_indexed_load_1622, 6, illegal_indexed_load_1622_arg5); + setRet(call_illegal_indexed_load_1622, 0, ret_val_illegal_indexed_load_1622); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1625; + x86::Gp ret_val_sew_1625 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1625, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1624; + auto vlxseg_1624_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1624_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1624_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1624_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1624_arg10 = ret_val_sew_1625; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1624 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1624, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1624, 64, false), traits::vstart); + setArg(call_sew_1625, 0, reinterpret_cast(this)); + setRet(call_sew_1625, 0, ret_val_sew_1625); + setArg(call_vlxseg_1624, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1624, 1, V); + setArg(call_vlxseg_1624, 2, vlxseg_1624_arg1); + setArg(call_vlxseg_1624, 3, vlxseg_1624_arg2); + setArg(call_vlxseg_1624, 4, vlxseg_1624_arg3); + setArg(call_vlxseg_1624, 5, vm); + setArg(call_vlxseg_1624, 6, vd); + setArg(call_vlxseg_1624, 7, vlxseg_1624_arg6); + setArg(call_vlxseg_1624, 8, vs2); + setArg(call_vlxseg_1624, 9, 1); + setArg(call_vlxseg_1624, 10, 4); + setArg(call_vlxseg_1624, 11, vlxseg_1624_arg10); + setArg(call_vlxseg_1624, 12, 0); + setRet(call_vlxseg_1624, 0, ret_val_vlxseg_1624); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 451); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 452: VLUXEI64__V */ + continuation_e __vluxei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXEI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 452); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1626; + x86::Gp ret_val_get_pow_1626 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1626, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1627; + x86::Gp ret_val_get_sew_pow_1627 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1627, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1628; + x86::Gp ret_val_get_lmul_pow_1628 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1628, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1626, ret_val_get_sew_pow_1627), ret_val_get_lmul_pow_1628)), 3, true); + setArg(call_get_pow_1626, 0, reinterpret_cast(this)); + setArg(call_get_pow_1626, 1, EEW); + setRet(call_get_pow_1626, 0, ret_val_get_pow_1626); + setArg(call_get_sew_pow_1627, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1627, 0, ret_val_get_sew_pow_1627); + setArg(call_get_lmul_pow_1628, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1628, 0, ret_val_get_lmul_pow_1628); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1630; + x86::Gp ret_val_get_lmul_pow_1630 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1630, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1629; + auto illegal_indexed_load_1629_arg4 = EMUL_pow; + auto illegal_indexed_load_1629_arg5 = ret_val_get_lmul_pow_1630; + x86::Gp ret_val_illegal_indexed_load_1629 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1629, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1629; + setArg(call_get_lmul_pow_1630, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1630, 0, ret_val_get_lmul_pow_1630); + setArg(call_illegal_indexed_load_1629, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1629, 1, vd); + setArg(call_illegal_indexed_load_1629, 2, vm); + setArg(call_illegal_indexed_load_1629, 3, 1); + setArg(call_illegal_indexed_load_1629, 4, EEW); + setArg(call_illegal_indexed_load_1629, 5, illegal_indexed_load_1629_arg4); + setArg(call_illegal_indexed_load_1629, 6, illegal_indexed_load_1629_arg5); + setRet(call_illegal_indexed_load_1629, 0, ret_val_illegal_indexed_load_1629); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1632; + x86::Gp ret_val_sew_1632 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1632, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1631; + auto vlxseg_1631_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1631_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1631_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1631_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1631_arg10 = ret_val_sew_1632; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1631 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1631, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1631, 64, false), traits::vstart); + setArg(call_sew_1632, 0, reinterpret_cast(this)); + setRet(call_sew_1632, 0, ret_val_sew_1632); + setArg(call_vlxseg_1631, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1631, 1, V); + setArg(call_vlxseg_1631, 2, vlxseg_1631_arg1); + setArg(call_vlxseg_1631, 3, vlxseg_1631_arg2); + setArg(call_vlxseg_1631, 4, vlxseg_1631_arg3); + setArg(call_vlxseg_1631, 5, vm); + setArg(call_vlxseg_1631, 6, vd); + setArg(call_vlxseg_1631, 7, vlxseg_1631_arg6); + setArg(call_vlxseg_1631, 8, vs2); + setArg(call_vlxseg_1631, 9, 1); + setArg(call_vlxseg_1631, 10, 8); + setArg(call_vlxseg_1631, 11, vlxseg_1631_arg10); + setArg(call_vlxseg_1631, 12, 0); + setRet(call_vlxseg_1631, 0, ret_val_vlxseg_1631); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 452); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 453: VLUXSEG2EI8__V */ + continuation_e __vluxseg2ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG2EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 453); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1633; + x86::Gp ret_val_get_pow_1633 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1633, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1634; + x86::Gp ret_val_get_sew_pow_1634 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1634, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1635; + x86::Gp ret_val_get_lmul_pow_1635 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1635, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1633, ret_val_get_sew_pow_1634), ret_val_get_lmul_pow_1635)), 3, true); + setArg(call_get_pow_1633, 0, reinterpret_cast(this)); + setArg(call_get_pow_1633, 1, EEW); + setRet(call_get_pow_1633, 0, ret_val_get_pow_1633); + setArg(call_get_sew_pow_1634, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1634, 0, ret_val_get_sew_pow_1634); + setArg(call_get_lmul_pow_1635, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1635, 0, ret_val_get_lmul_pow_1635); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1637; + x86::Gp ret_val_get_lmul_pow_1637 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1637, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1636; + auto illegal_indexed_load_1636_arg4 = EMUL_pow; + auto illegal_indexed_load_1636_arg5 = ret_val_get_lmul_pow_1637; + x86::Gp ret_val_illegal_indexed_load_1636 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1636, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1636; + setArg(call_get_lmul_pow_1637, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1637, 0, ret_val_get_lmul_pow_1637); + setArg(call_illegal_indexed_load_1636, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1636, 1, vd); + setArg(call_illegal_indexed_load_1636, 2, vm); + setArg(call_illegal_indexed_load_1636, 3, 2); + setArg(call_illegal_indexed_load_1636, 4, EEW); + setArg(call_illegal_indexed_load_1636, 5, illegal_indexed_load_1636_arg4); + setArg(call_illegal_indexed_load_1636, 6, illegal_indexed_load_1636_arg5); + setRet(call_illegal_indexed_load_1636, 0, ret_val_illegal_indexed_load_1636); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1639; + x86::Gp ret_val_sew_1639 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1639, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1638; + auto vlxseg_1638_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1638_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1638_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1638_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1638_arg10 = ret_val_sew_1639; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1638 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1638, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1638, 64, false), traits::vstart); + setArg(call_sew_1639, 0, reinterpret_cast(this)); + setRet(call_sew_1639, 0, ret_val_sew_1639); + setArg(call_vlxseg_1638, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1638, 1, V); + setArg(call_vlxseg_1638, 2, vlxseg_1638_arg1); + setArg(call_vlxseg_1638, 3, vlxseg_1638_arg2); + setArg(call_vlxseg_1638, 4, vlxseg_1638_arg3); + setArg(call_vlxseg_1638, 5, vm); + setArg(call_vlxseg_1638, 6, vd); + setArg(call_vlxseg_1638, 7, vlxseg_1638_arg6); + setArg(call_vlxseg_1638, 8, vs2); + setArg(call_vlxseg_1638, 9, 2); + setArg(call_vlxseg_1638, 10, 1); + setArg(call_vlxseg_1638, 11, vlxseg_1638_arg10); + setArg(call_vlxseg_1638, 12, 0); + setRet(call_vlxseg_1638, 0, ret_val_vlxseg_1638); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 453); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 454: VLUXSEG2EI16__V */ + continuation_e __vluxseg2ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG2EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 454); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1640; + x86::Gp ret_val_get_pow_1640 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1640, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1641; + x86::Gp ret_val_get_sew_pow_1641 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1641, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1642; + x86::Gp ret_val_get_lmul_pow_1642 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1642, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1640, ret_val_get_sew_pow_1641), ret_val_get_lmul_pow_1642)), 3, true); + setArg(call_get_pow_1640, 0, reinterpret_cast(this)); + setArg(call_get_pow_1640, 1, EEW); + setRet(call_get_pow_1640, 0, ret_val_get_pow_1640); + setArg(call_get_sew_pow_1641, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1641, 0, ret_val_get_sew_pow_1641); + setArg(call_get_lmul_pow_1642, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1642, 0, ret_val_get_lmul_pow_1642); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1644; + x86::Gp ret_val_get_lmul_pow_1644 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1644, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1643; + auto illegal_indexed_load_1643_arg4 = EMUL_pow; + auto illegal_indexed_load_1643_arg5 = ret_val_get_lmul_pow_1644; + x86::Gp ret_val_illegal_indexed_load_1643 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1643, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1643; + setArg(call_get_lmul_pow_1644, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1644, 0, ret_val_get_lmul_pow_1644); + setArg(call_illegal_indexed_load_1643, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1643, 1, vd); + setArg(call_illegal_indexed_load_1643, 2, vm); + setArg(call_illegal_indexed_load_1643, 3, 2); + setArg(call_illegal_indexed_load_1643, 4, EEW); + setArg(call_illegal_indexed_load_1643, 5, illegal_indexed_load_1643_arg4); + setArg(call_illegal_indexed_load_1643, 6, illegal_indexed_load_1643_arg5); + setRet(call_illegal_indexed_load_1643, 0, ret_val_illegal_indexed_load_1643); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1646; + x86::Gp ret_val_sew_1646 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1646, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1645; + auto vlxseg_1645_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1645_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1645_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1645_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1645_arg10 = ret_val_sew_1646; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1645 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1645, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1645, 64, false), traits::vstart); + setArg(call_sew_1646, 0, reinterpret_cast(this)); + setRet(call_sew_1646, 0, ret_val_sew_1646); + setArg(call_vlxseg_1645, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1645, 1, V); + setArg(call_vlxseg_1645, 2, vlxseg_1645_arg1); + setArg(call_vlxseg_1645, 3, vlxseg_1645_arg2); + setArg(call_vlxseg_1645, 4, vlxseg_1645_arg3); + setArg(call_vlxseg_1645, 5, vm); + setArg(call_vlxseg_1645, 6, vd); + setArg(call_vlxseg_1645, 7, vlxseg_1645_arg6); + setArg(call_vlxseg_1645, 8, vs2); + setArg(call_vlxseg_1645, 9, 2); + setArg(call_vlxseg_1645, 10, 2); + setArg(call_vlxseg_1645, 11, vlxseg_1645_arg10); + setArg(call_vlxseg_1645, 12, 0); + setRet(call_vlxseg_1645, 0, ret_val_vlxseg_1645); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 454); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 455: VLUXSEG2EI32__V */ + continuation_e __vluxseg2ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG2EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 455); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1647; + x86::Gp ret_val_get_pow_1647 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1647, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1648; + x86::Gp ret_val_get_sew_pow_1648 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1648, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1649; + x86::Gp ret_val_get_lmul_pow_1649 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1649, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1647, ret_val_get_sew_pow_1648), ret_val_get_lmul_pow_1649)), 3, true); + setArg(call_get_pow_1647, 0, reinterpret_cast(this)); + setArg(call_get_pow_1647, 1, EEW); + setRet(call_get_pow_1647, 0, ret_val_get_pow_1647); + setArg(call_get_sew_pow_1648, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1648, 0, ret_val_get_sew_pow_1648); + setArg(call_get_lmul_pow_1649, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1649, 0, ret_val_get_lmul_pow_1649); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1651; + x86::Gp ret_val_get_lmul_pow_1651 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1651, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1650; + auto illegal_indexed_load_1650_arg4 = EMUL_pow; + auto illegal_indexed_load_1650_arg5 = ret_val_get_lmul_pow_1651; + x86::Gp ret_val_illegal_indexed_load_1650 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1650, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1650; + setArg(call_get_lmul_pow_1651, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1651, 0, ret_val_get_lmul_pow_1651); + setArg(call_illegal_indexed_load_1650, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1650, 1, vd); + setArg(call_illegal_indexed_load_1650, 2, vm); + setArg(call_illegal_indexed_load_1650, 3, 2); + setArg(call_illegal_indexed_load_1650, 4, EEW); + setArg(call_illegal_indexed_load_1650, 5, illegal_indexed_load_1650_arg4); + setArg(call_illegal_indexed_load_1650, 6, illegal_indexed_load_1650_arg5); + setRet(call_illegal_indexed_load_1650, 0, ret_val_illegal_indexed_load_1650); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1653; + x86::Gp ret_val_sew_1653 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1653, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1652; + auto vlxseg_1652_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1652_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1652_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1652_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1652_arg10 = ret_val_sew_1653; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1652 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1652, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1652, 64, false), traits::vstart); + setArg(call_sew_1653, 0, reinterpret_cast(this)); + setRet(call_sew_1653, 0, ret_val_sew_1653); + setArg(call_vlxseg_1652, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1652, 1, V); + setArg(call_vlxseg_1652, 2, vlxseg_1652_arg1); + setArg(call_vlxseg_1652, 3, vlxseg_1652_arg2); + setArg(call_vlxseg_1652, 4, vlxseg_1652_arg3); + setArg(call_vlxseg_1652, 5, vm); + setArg(call_vlxseg_1652, 6, vd); + setArg(call_vlxseg_1652, 7, vlxseg_1652_arg6); + setArg(call_vlxseg_1652, 8, vs2); + setArg(call_vlxseg_1652, 9, 2); + setArg(call_vlxseg_1652, 10, 4); + setArg(call_vlxseg_1652, 11, vlxseg_1652_arg10); + setArg(call_vlxseg_1652, 12, 0); + setRet(call_vlxseg_1652, 0, ret_val_vlxseg_1652); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 455); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 456: VLUXSEG2EI64__V */ + continuation_e __vluxseg2ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg2ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG2EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 456); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1654; + x86::Gp ret_val_get_pow_1654 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1654, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1655; + x86::Gp ret_val_get_sew_pow_1655 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1655, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1656; + x86::Gp ret_val_get_lmul_pow_1656 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1656, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1654, ret_val_get_sew_pow_1655), ret_val_get_lmul_pow_1656)), 3, true); + setArg(call_get_pow_1654, 0, reinterpret_cast(this)); + setArg(call_get_pow_1654, 1, EEW); + setRet(call_get_pow_1654, 0, ret_val_get_pow_1654); + setArg(call_get_sew_pow_1655, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1655, 0, ret_val_get_sew_pow_1655); + setArg(call_get_lmul_pow_1656, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1656, 0, ret_val_get_lmul_pow_1656); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1658; + x86::Gp ret_val_get_lmul_pow_1658 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1658, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1657; + auto illegal_indexed_load_1657_arg4 = EMUL_pow; + auto illegal_indexed_load_1657_arg5 = ret_val_get_lmul_pow_1658; + x86::Gp ret_val_illegal_indexed_load_1657 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1657, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1657; + setArg(call_get_lmul_pow_1658, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1658, 0, ret_val_get_lmul_pow_1658); + setArg(call_illegal_indexed_load_1657, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1657, 1, vd); + setArg(call_illegal_indexed_load_1657, 2, vm); + setArg(call_illegal_indexed_load_1657, 3, 2); + setArg(call_illegal_indexed_load_1657, 4, EEW); + setArg(call_illegal_indexed_load_1657, 5, illegal_indexed_load_1657_arg4); + setArg(call_illegal_indexed_load_1657, 6, illegal_indexed_load_1657_arg5); + setRet(call_illegal_indexed_load_1657, 0, ret_val_illegal_indexed_load_1657); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1660; + x86::Gp ret_val_sew_1660 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1660, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1659; + auto vlxseg_1659_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1659_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1659_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1659_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1659_arg10 = ret_val_sew_1660; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1659 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1659, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1659, 64, false), traits::vstart); + setArg(call_sew_1660, 0, reinterpret_cast(this)); + setRet(call_sew_1660, 0, ret_val_sew_1660); + setArg(call_vlxseg_1659, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1659, 1, V); + setArg(call_vlxseg_1659, 2, vlxseg_1659_arg1); + setArg(call_vlxseg_1659, 3, vlxseg_1659_arg2); + setArg(call_vlxseg_1659, 4, vlxseg_1659_arg3); + setArg(call_vlxseg_1659, 5, vm); + setArg(call_vlxseg_1659, 6, vd); + setArg(call_vlxseg_1659, 7, vlxseg_1659_arg6); + setArg(call_vlxseg_1659, 8, vs2); + setArg(call_vlxseg_1659, 9, 2); + setArg(call_vlxseg_1659, 10, 8); + setArg(call_vlxseg_1659, 11, vlxseg_1659_arg10); + setArg(call_vlxseg_1659, 12, 0); + setRet(call_vlxseg_1659, 0, ret_val_vlxseg_1659); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 456); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 457: VLUXSEG3EI8__V */ + continuation_e __vluxseg3ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG3EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 457); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1661; + x86::Gp ret_val_get_pow_1661 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1661, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1662; + x86::Gp ret_val_get_sew_pow_1662 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1662, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1663; + x86::Gp ret_val_get_lmul_pow_1663 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1663, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1661, ret_val_get_sew_pow_1662), ret_val_get_lmul_pow_1663)), 3, true); + setArg(call_get_pow_1661, 0, reinterpret_cast(this)); + setArg(call_get_pow_1661, 1, EEW); + setRet(call_get_pow_1661, 0, ret_val_get_pow_1661); + setArg(call_get_sew_pow_1662, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1662, 0, ret_val_get_sew_pow_1662); + setArg(call_get_lmul_pow_1663, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1663, 0, ret_val_get_lmul_pow_1663); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1665; + x86::Gp ret_val_get_lmul_pow_1665 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1665, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1664; + auto illegal_indexed_load_1664_arg4 = EMUL_pow; + auto illegal_indexed_load_1664_arg5 = ret_val_get_lmul_pow_1665; + x86::Gp ret_val_illegal_indexed_load_1664 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1664, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1664; + setArg(call_get_lmul_pow_1665, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1665, 0, ret_val_get_lmul_pow_1665); + setArg(call_illegal_indexed_load_1664, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1664, 1, vd); + setArg(call_illegal_indexed_load_1664, 2, vm); + setArg(call_illegal_indexed_load_1664, 3, 3); + setArg(call_illegal_indexed_load_1664, 4, EEW); + setArg(call_illegal_indexed_load_1664, 5, illegal_indexed_load_1664_arg4); + setArg(call_illegal_indexed_load_1664, 6, illegal_indexed_load_1664_arg5); + setRet(call_illegal_indexed_load_1664, 0, ret_val_illegal_indexed_load_1664); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1667; + x86::Gp ret_val_sew_1667 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1667, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1666; + auto vlxseg_1666_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1666_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1666_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1666_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1666_arg10 = ret_val_sew_1667; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1666 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1666, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1666, 64, false), traits::vstart); + setArg(call_sew_1667, 0, reinterpret_cast(this)); + setRet(call_sew_1667, 0, ret_val_sew_1667); + setArg(call_vlxseg_1666, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1666, 1, V); + setArg(call_vlxseg_1666, 2, vlxseg_1666_arg1); + setArg(call_vlxseg_1666, 3, vlxseg_1666_arg2); + setArg(call_vlxseg_1666, 4, vlxseg_1666_arg3); + setArg(call_vlxseg_1666, 5, vm); + setArg(call_vlxseg_1666, 6, vd); + setArg(call_vlxseg_1666, 7, vlxseg_1666_arg6); + setArg(call_vlxseg_1666, 8, vs2); + setArg(call_vlxseg_1666, 9, 3); + setArg(call_vlxseg_1666, 10, 1); + setArg(call_vlxseg_1666, 11, vlxseg_1666_arg10); + setArg(call_vlxseg_1666, 12, 0); + setRet(call_vlxseg_1666, 0, ret_val_vlxseg_1666); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 457); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 458: VLUXSEG3EI16__V */ + continuation_e __vluxseg3ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG3EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 458); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1668; + x86::Gp ret_val_get_pow_1668 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1668, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1669; + x86::Gp ret_val_get_sew_pow_1669 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1669, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1670; + x86::Gp ret_val_get_lmul_pow_1670 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1670, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1668, ret_val_get_sew_pow_1669), ret_val_get_lmul_pow_1670)), 3, true); + setArg(call_get_pow_1668, 0, reinterpret_cast(this)); + setArg(call_get_pow_1668, 1, EEW); + setRet(call_get_pow_1668, 0, ret_val_get_pow_1668); + setArg(call_get_sew_pow_1669, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1669, 0, ret_val_get_sew_pow_1669); + setArg(call_get_lmul_pow_1670, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1670, 0, ret_val_get_lmul_pow_1670); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1672; + x86::Gp ret_val_get_lmul_pow_1672 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1672, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1671; + auto illegal_indexed_load_1671_arg4 = EMUL_pow; + auto illegal_indexed_load_1671_arg5 = ret_val_get_lmul_pow_1672; + x86::Gp ret_val_illegal_indexed_load_1671 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1671, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1671; + setArg(call_get_lmul_pow_1672, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1672, 0, ret_val_get_lmul_pow_1672); + setArg(call_illegal_indexed_load_1671, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1671, 1, vd); + setArg(call_illegal_indexed_load_1671, 2, vm); + setArg(call_illegal_indexed_load_1671, 3, 3); + setArg(call_illegal_indexed_load_1671, 4, EEW); + setArg(call_illegal_indexed_load_1671, 5, illegal_indexed_load_1671_arg4); + setArg(call_illegal_indexed_load_1671, 6, illegal_indexed_load_1671_arg5); + setRet(call_illegal_indexed_load_1671, 0, ret_val_illegal_indexed_load_1671); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1674; + x86::Gp ret_val_sew_1674 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1674, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1673; + auto vlxseg_1673_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1673_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1673_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1673_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1673_arg10 = ret_val_sew_1674; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1673 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1673, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1673, 64, false), traits::vstart); + setArg(call_sew_1674, 0, reinterpret_cast(this)); + setRet(call_sew_1674, 0, ret_val_sew_1674); + setArg(call_vlxseg_1673, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1673, 1, V); + setArg(call_vlxseg_1673, 2, vlxseg_1673_arg1); + setArg(call_vlxseg_1673, 3, vlxseg_1673_arg2); + setArg(call_vlxseg_1673, 4, vlxseg_1673_arg3); + setArg(call_vlxseg_1673, 5, vm); + setArg(call_vlxseg_1673, 6, vd); + setArg(call_vlxseg_1673, 7, vlxseg_1673_arg6); + setArg(call_vlxseg_1673, 8, vs2); + setArg(call_vlxseg_1673, 9, 3); + setArg(call_vlxseg_1673, 10, 2); + setArg(call_vlxseg_1673, 11, vlxseg_1673_arg10); + setArg(call_vlxseg_1673, 12, 0); + setRet(call_vlxseg_1673, 0, ret_val_vlxseg_1673); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 458); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 459: VLUXSEG3EI32__V */ + continuation_e __vluxseg3ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG3EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 459); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1675; + x86::Gp ret_val_get_pow_1675 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1675, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1676; + x86::Gp ret_val_get_sew_pow_1676 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1676, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1677; + x86::Gp ret_val_get_lmul_pow_1677 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1677, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1675, ret_val_get_sew_pow_1676), ret_val_get_lmul_pow_1677)), 3, true); + setArg(call_get_pow_1675, 0, reinterpret_cast(this)); + setArg(call_get_pow_1675, 1, EEW); + setRet(call_get_pow_1675, 0, ret_val_get_pow_1675); + setArg(call_get_sew_pow_1676, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1676, 0, ret_val_get_sew_pow_1676); + setArg(call_get_lmul_pow_1677, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1677, 0, ret_val_get_lmul_pow_1677); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1679; + x86::Gp ret_val_get_lmul_pow_1679 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1679, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1678; + auto illegal_indexed_load_1678_arg4 = EMUL_pow; + auto illegal_indexed_load_1678_arg5 = ret_val_get_lmul_pow_1679; + x86::Gp ret_val_illegal_indexed_load_1678 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1678, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1678; + setArg(call_get_lmul_pow_1679, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1679, 0, ret_val_get_lmul_pow_1679); + setArg(call_illegal_indexed_load_1678, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1678, 1, vd); + setArg(call_illegal_indexed_load_1678, 2, vm); + setArg(call_illegal_indexed_load_1678, 3, 3); + setArg(call_illegal_indexed_load_1678, 4, EEW); + setArg(call_illegal_indexed_load_1678, 5, illegal_indexed_load_1678_arg4); + setArg(call_illegal_indexed_load_1678, 6, illegal_indexed_load_1678_arg5); + setRet(call_illegal_indexed_load_1678, 0, ret_val_illegal_indexed_load_1678); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1681; + x86::Gp ret_val_sew_1681 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1681, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1680; + auto vlxseg_1680_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1680_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1680_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1680_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1680_arg10 = ret_val_sew_1681; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1680 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1680, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1680, 64, false), traits::vstart); + setArg(call_sew_1681, 0, reinterpret_cast(this)); + setRet(call_sew_1681, 0, ret_val_sew_1681); + setArg(call_vlxseg_1680, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1680, 1, V); + setArg(call_vlxseg_1680, 2, vlxseg_1680_arg1); + setArg(call_vlxseg_1680, 3, vlxseg_1680_arg2); + setArg(call_vlxseg_1680, 4, vlxseg_1680_arg3); + setArg(call_vlxseg_1680, 5, vm); + setArg(call_vlxseg_1680, 6, vd); + setArg(call_vlxseg_1680, 7, vlxseg_1680_arg6); + setArg(call_vlxseg_1680, 8, vs2); + setArg(call_vlxseg_1680, 9, 3); + setArg(call_vlxseg_1680, 10, 4); + setArg(call_vlxseg_1680, 11, vlxseg_1680_arg10); + setArg(call_vlxseg_1680, 12, 0); + setRet(call_vlxseg_1680, 0, ret_val_vlxseg_1680); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 459); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 460: VLUXSEG3EI64__V */ + continuation_e __vluxseg3ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg3ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG3EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 460); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1682; + x86::Gp ret_val_get_pow_1682 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1682, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1683; + x86::Gp ret_val_get_sew_pow_1683 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1683, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1684; + x86::Gp ret_val_get_lmul_pow_1684 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1684, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1682, ret_val_get_sew_pow_1683), ret_val_get_lmul_pow_1684)), 3, true); + setArg(call_get_pow_1682, 0, reinterpret_cast(this)); + setArg(call_get_pow_1682, 1, EEW); + setRet(call_get_pow_1682, 0, ret_val_get_pow_1682); + setArg(call_get_sew_pow_1683, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1683, 0, ret_val_get_sew_pow_1683); + setArg(call_get_lmul_pow_1684, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1684, 0, ret_val_get_lmul_pow_1684); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1686; + x86::Gp ret_val_get_lmul_pow_1686 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1686, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1685; + auto illegal_indexed_load_1685_arg4 = EMUL_pow; + auto illegal_indexed_load_1685_arg5 = ret_val_get_lmul_pow_1686; + x86::Gp ret_val_illegal_indexed_load_1685 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1685, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1685; + setArg(call_get_lmul_pow_1686, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1686, 0, ret_val_get_lmul_pow_1686); + setArg(call_illegal_indexed_load_1685, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1685, 1, vd); + setArg(call_illegal_indexed_load_1685, 2, vm); + setArg(call_illegal_indexed_load_1685, 3, 3); + setArg(call_illegal_indexed_load_1685, 4, EEW); + setArg(call_illegal_indexed_load_1685, 5, illegal_indexed_load_1685_arg4); + setArg(call_illegal_indexed_load_1685, 6, illegal_indexed_load_1685_arg5); + setRet(call_illegal_indexed_load_1685, 0, ret_val_illegal_indexed_load_1685); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1688; + x86::Gp ret_val_sew_1688 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1688, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1687; + auto vlxseg_1687_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1687_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1687_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1687_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1687_arg10 = ret_val_sew_1688; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1687 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1687, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1687, 64, false), traits::vstart); + setArg(call_sew_1688, 0, reinterpret_cast(this)); + setRet(call_sew_1688, 0, ret_val_sew_1688); + setArg(call_vlxseg_1687, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1687, 1, V); + setArg(call_vlxseg_1687, 2, vlxseg_1687_arg1); + setArg(call_vlxseg_1687, 3, vlxseg_1687_arg2); + setArg(call_vlxseg_1687, 4, vlxseg_1687_arg3); + setArg(call_vlxseg_1687, 5, vm); + setArg(call_vlxseg_1687, 6, vd); + setArg(call_vlxseg_1687, 7, vlxseg_1687_arg6); + setArg(call_vlxseg_1687, 8, vs2); + setArg(call_vlxseg_1687, 9, 3); + setArg(call_vlxseg_1687, 10, 8); + setArg(call_vlxseg_1687, 11, vlxseg_1687_arg10); + setArg(call_vlxseg_1687, 12, 0); + setRet(call_vlxseg_1687, 0, ret_val_vlxseg_1687); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 460); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 461: VLUXSEG4EI8__V */ + continuation_e __vluxseg4ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG4EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 461); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1689; + x86::Gp ret_val_get_pow_1689 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1689, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1690; + x86::Gp ret_val_get_sew_pow_1690 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1690, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1691; + x86::Gp ret_val_get_lmul_pow_1691 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1691, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1689, ret_val_get_sew_pow_1690), ret_val_get_lmul_pow_1691)), 3, true); + setArg(call_get_pow_1689, 0, reinterpret_cast(this)); + setArg(call_get_pow_1689, 1, EEW); + setRet(call_get_pow_1689, 0, ret_val_get_pow_1689); + setArg(call_get_sew_pow_1690, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1690, 0, ret_val_get_sew_pow_1690); + setArg(call_get_lmul_pow_1691, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1691, 0, ret_val_get_lmul_pow_1691); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1693; + x86::Gp ret_val_get_lmul_pow_1693 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1693, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1692; + auto illegal_indexed_load_1692_arg4 = EMUL_pow; + auto illegal_indexed_load_1692_arg5 = ret_val_get_lmul_pow_1693; + x86::Gp ret_val_illegal_indexed_load_1692 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1692, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1692; + setArg(call_get_lmul_pow_1693, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1693, 0, ret_val_get_lmul_pow_1693); + setArg(call_illegal_indexed_load_1692, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1692, 1, vd); + setArg(call_illegal_indexed_load_1692, 2, vm); + setArg(call_illegal_indexed_load_1692, 3, 4); + setArg(call_illegal_indexed_load_1692, 4, EEW); + setArg(call_illegal_indexed_load_1692, 5, illegal_indexed_load_1692_arg4); + setArg(call_illegal_indexed_load_1692, 6, illegal_indexed_load_1692_arg5); + setRet(call_illegal_indexed_load_1692, 0, ret_val_illegal_indexed_load_1692); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1695; + x86::Gp ret_val_sew_1695 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1695, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1694; + auto vlxseg_1694_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1694_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1694_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1694_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1694_arg10 = ret_val_sew_1695; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1694 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1694, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1694, 64, false), traits::vstart); + setArg(call_sew_1695, 0, reinterpret_cast(this)); + setRet(call_sew_1695, 0, ret_val_sew_1695); + setArg(call_vlxseg_1694, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1694, 1, V); + setArg(call_vlxseg_1694, 2, vlxseg_1694_arg1); + setArg(call_vlxseg_1694, 3, vlxseg_1694_arg2); + setArg(call_vlxseg_1694, 4, vlxseg_1694_arg3); + setArg(call_vlxseg_1694, 5, vm); + setArg(call_vlxseg_1694, 6, vd); + setArg(call_vlxseg_1694, 7, vlxseg_1694_arg6); + setArg(call_vlxseg_1694, 8, vs2); + setArg(call_vlxseg_1694, 9, 4); + setArg(call_vlxseg_1694, 10, 1); + setArg(call_vlxseg_1694, 11, vlxseg_1694_arg10); + setArg(call_vlxseg_1694, 12, 0); + setRet(call_vlxseg_1694, 0, ret_val_vlxseg_1694); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 461); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 462: VLUXSEG4EI16__V */ + continuation_e __vluxseg4ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG4EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 462); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1696; + x86::Gp ret_val_get_pow_1696 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1696, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1697; + x86::Gp ret_val_get_sew_pow_1697 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1697, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1698; + x86::Gp ret_val_get_lmul_pow_1698 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1698, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1696, ret_val_get_sew_pow_1697), ret_val_get_lmul_pow_1698)), 3, true); + setArg(call_get_pow_1696, 0, reinterpret_cast(this)); + setArg(call_get_pow_1696, 1, EEW); + setRet(call_get_pow_1696, 0, ret_val_get_pow_1696); + setArg(call_get_sew_pow_1697, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1697, 0, ret_val_get_sew_pow_1697); + setArg(call_get_lmul_pow_1698, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1698, 0, ret_val_get_lmul_pow_1698); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1700; + x86::Gp ret_val_get_lmul_pow_1700 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1700, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1699; + auto illegal_indexed_load_1699_arg4 = EMUL_pow; + auto illegal_indexed_load_1699_arg5 = ret_val_get_lmul_pow_1700; + x86::Gp ret_val_illegal_indexed_load_1699 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1699, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1699; + setArg(call_get_lmul_pow_1700, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1700, 0, ret_val_get_lmul_pow_1700); + setArg(call_illegal_indexed_load_1699, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1699, 1, vd); + setArg(call_illegal_indexed_load_1699, 2, vm); + setArg(call_illegal_indexed_load_1699, 3, 4); + setArg(call_illegal_indexed_load_1699, 4, EEW); + setArg(call_illegal_indexed_load_1699, 5, illegal_indexed_load_1699_arg4); + setArg(call_illegal_indexed_load_1699, 6, illegal_indexed_load_1699_arg5); + setRet(call_illegal_indexed_load_1699, 0, ret_val_illegal_indexed_load_1699); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1702; + x86::Gp ret_val_sew_1702 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1702, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1701; + auto vlxseg_1701_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1701_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1701_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1701_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1701_arg10 = ret_val_sew_1702; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1701 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1701, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1701, 64, false), traits::vstart); + setArg(call_sew_1702, 0, reinterpret_cast(this)); + setRet(call_sew_1702, 0, ret_val_sew_1702); + setArg(call_vlxseg_1701, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1701, 1, V); + setArg(call_vlxseg_1701, 2, vlxseg_1701_arg1); + setArg(call_vlxseg_1701, 3, vlxseg_1701_arg2); + setArg(call_vlxseg_1701, 4, vlxseg_1701_arg3); + setArg(call_vlxseg_1701, 5, vm); + setArg(call_vlxseg_1701, 6, vd); + setArg(call_vlxseg_1701, 7, vlxseg_1701_arg6); + setArg(call_vlxseg_1701, 8, vs2); + setArg(call_vlxseg_1701, 9, 4); + setArg(call_vlxseg_1701, 10, 2); + setArg(call_vlxseg_1701, 11, vlxseg_1701_arg10); + setArg(call_vlxseg_1701, 12, 0); + setRet(call_vlxseg_1701, 0, ret_val_vlxseg_1701); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 462); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 463: VLUXSEG4EI32__V */ + continuation_e __vluxseg4ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG4EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 463); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1703; + x86::Gp ret_val_get_pow_1703 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1703, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1704; + x86::Gp ret_val_get_sew_pow_1704 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1704, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1705; + x86::Gp ret_val_get_lmul_pow_1705 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1705, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1703, ret_val_get_sew_pow_1704), ret_val_get_lmul_pow_1705)), 3, true); + setArg(call_get_pow_1703, 0, reinterpret_cast(this)); + setArg(call_get_pow_1703, 1, EEW); + setRet(call_get_pow_1703, 0, ret_val_get_pow_1703); + setArg(call_get_sew_pow_1704, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1704, 0, ret_val_get_sew_pow_1704); + setArg(call_get_lmul_pow_1705, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1705, 0, ret_val_get_lmul_pow_1705); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1707; + x86::Gp ret_val_get_lmul_pow_1707 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1707, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1706; + auto illegal_indexed_load_1706_arg4 = EMUL_pow; + auto illegal_indexed_load_1706_arg5 = ret_val_get_lmul_pow_1707; + x86::Gp ret_val_illegal_indexed_load_1706 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1706, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1706; + setArg(call_get_lmul_pow_1707, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1707, 0, ret_val_get_lmul_pow_1707); + setArg(call_illegal_indexed_load_1706, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1706, 1, vd); + setArg(call_illegal_indexed_load_1706, 2, vm); + setArg(call_illegal_indexed_load_1706, 3, 4); + setArg(call_illegal_indexed_load_1706, 4, EEW); + setArg(call_illegal_indexed_load_1706, 5, illegal_indexed_load_1706_arg4); + setArg(call_illegal_indexed_load_1706, 6, illegal_indexed_load_1706_arg5); + setRet(call_illegal_indexed_load_1706, 0, ret_val_illegal_indexed_load_1706); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1709; + x86::Gp ret_val_sew_1709 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1709, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1708; + auto vlxseg_1708_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1708_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1708_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1708_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1708_arg10 = ret_val_sew_1709; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1708 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1708, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1708, 64, false), traits::vstart); + setArg(call_sew_1709, 0, reinterpret_cast(this)); + setRet(call_sew_1709, 0, ret_val_sew_1709); + setArg(call_vlxseg_1708, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1708, 1, V); + setArg(call_vlxseg_1708, 2, vlxseg_1708_arg1); + setArg(call_vlxseg_1708, 3, vlxseg_1708_arg2); + setArg(call_vlxseg_1708, 4, vlxseg_1708_arg3); + setArg(call_vlxseg_1708, 5, vm); + setArg(call_vlxseg_1708, 6, vd); + setArg(call_vlxseg_1708, 7, vlxseg_1708_arg6); + setArg(call_vlxseg_1708, 8, vs2); + setArg(call_vlxseg_1708, 9, 4); + setArg(call_vlxseg_1708, 10, 4); + setArg(call_vlxseg_1708, 11, vlxseg_1708_arg10); + setArg(call_vlxseg_1708, 12, 0); + setRet(call_vlxseg_1708, 0, ret_val_vlxseg_1708); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 463); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 464: VLUXSEG4EI64__V */ + continuation_e __vluxseg4ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg4ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG4EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 464); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1710; + x86::Gp ret_val_get_pow_1710 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1710, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1711; + x86::Gp ret_val_get_sew_pow_1711 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1711, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1712; + x86::Gp ret_val_get_lmul_pow_1712 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1712, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1710, ret_val_get_sew_pow_1711), ret_val_get_lmul_pow_1712)), 3, true); + setArg(call_get_pow_1710, 0, reinterpret_cast(this)); + setArg(call_get_pow_1710, 1, EEW); + setRet(call_get_pow_1710, 0, ret_val_get_pow_1710); + setArg(call_get_sew_pow_1711, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1711, 0, ret_val_get_sew_pow_1711); + setArg(call_get_lmul_pow_1712, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1712, 0, ret_val_get_lmul_pow_1712); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1714; + x86::Gp ret_val_get_lmul_pow_1714 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1714, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1713; + auto illegal_indexed_load_1713_arg4 = EMUL_pow; + auto illegal_indexed_load_1713_arg5 = ret_val_get_lmul_pow_1714; + x86::Gp ret_val_illegal_indexed_load_1713 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1713, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1713; + setArg(call_get_lmul_pow_1714, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1714, 0, ret_val_get_lmul_pow_1714); + setArg(call_illegal_indexed_load_1713, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1713, 1, vd); + setArg(call_illegal_indexed_load_1713, 2, vm); + setArg(call_illegal_indexed_load_1713, 3, 4); + setArg(call_illegal_indexed_load_1713, 4, EEW); + setArg(call_illegal_indexed_load_1713, 5, illegal_indexed_load_1713_arg4); + setArg(call_illegal_indexed_load_1713, 6, illegal_indexed_load_1713_arg5); + setRet(call_illegal_indexed_load_1713, 0, ret_val_illegal_indexed_load_1713); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1716; + x86::Gp ret_val_sew_1716 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1716, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1715; + auto vlxseg_1715_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1715_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1715_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1715_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1715_arg10 = ret_val_sew_1716; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1715 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1715, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1715, 64, false), traits::vstart); + setArg(call_sew_1716, 0, reinterpret_cast(this)); + setRet(call_sew_1716, 0, ret_val_sew_1716); + setArg(call_vlxseg_1715, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1715, 1, V); + setArg(call_vlxseg_1715, 2, vlxseg_1715_arg1); + setArg(call_vlxseg_1715, 3, vlxseg_1715_arg2); + setArg(call_vlxseg_1715, 4, vlxseg_1715_arg3); + setArg(call_vlxseg_1715, 5, vm); + setArg(call_vlxseg_1715, 6, vd); + setArg(call_vlxseg_1715, 7, vlxseg_1715_arg6); + setArg(call_vlxseg_1715, 8, vs2); + setArg(call_vlxseg_1715, 9, 4); + setArg(call_vlxseg_1715, 10, 8); + setArg(call_vlxseg_1715, 11, vlxseg_1715_arg10); + setArg(call_vlxseg_1715, 12, 0); + setRet(call_vlxseg_1715, 0, ret_val_vlxseg_1715); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 464); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 465: VLUXSEG5EI8__V */ + continuation_e __vluxseg5ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG5EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 465); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1717; + x86::Gp ret_val_get_pow_1717 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1717, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1718; + x86::Gp ret_val_get_sew_pow_1718 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1718, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1719; + x86::Gp ret_val_get_lmul_pow_1719 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1719, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1717, ret_val_get_sew_pow_1718), ret_val_get_lmul_pow_1719)), 3, true); + setArg(call_get_pow_1717, 0, reinterpret_cast(this)); + setArg(call_get_pow_1717, 1, EEW); + setRet(call_get_pow_1717, 0, ret_val_get_pow_1717); + setArg(call_get_sew_pow_1718, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1718, 0, ret_val_get_sew_pow_1718); + setArg(call_get_lmul_pow_1719, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1719, 0, ret_val_get_lmul_pow_1719); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1721; + x86::Gp ret_val_get_lmul_pow_1721 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1721, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1720; + auto illegal_indexed_load_1720_arg4 = EMUL_pow; + auto illegal_indexed_load_1720_arg5 = ret_val_get_lmul_pow_1721; + x86::Gp ret_val_illegal_indexed_load_1720 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1720, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1720; + setArg(call_get_lmul_pow_1721, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1721, 0, ret_val_get_lmul_pow_1721); + setArg(call_illegal_indexed_load_1720, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1720, 1, vd); + setArg(call_illegal_indexed_load_1720, 2, vm); + setArg(call_illegal_indexed_load_1720, 3, 5); + setArg(call_illegal_indexed_load_1720, 4, EEW); + setArg(call_illegal_indexed_load_1720, 5, illegal_indexed_load_1720_arg4); + setArg(call_illegal_indexed_load_1720, 6, illegal_indexed_load_1720_arg5); + setRet(call_illegal_indexed_load_1720, 0, ret_val_illegal_indexed_load_1720); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1723; + x86::Gp ret_val_sew_1723 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1723, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1722; + auto vlxseg_1722_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1722_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1722_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1722_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1722_arg10 = ret_val_sew_1723; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1722 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1722, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1722, 64, false), traits::vstart); + setArg(call_sew_1723, 0, reinterpret_cast(this)); + setRet(call_sew_1723, 0, ret_val_sew_1723); + setArg(call_vlxseg_1722, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1722, 1, V); + setArg(call_vlxseg_1722, 2, vlxseg_1722_arg1); + setArg(call_vlxseg_1722, 3, vlxseg_1722_arg2); + setArg(call_vlxseg_1722, 4, vlxseg_1722_arg3); + setArg(call_vlxseg_1722, 5, vm); + setArg(call_vlxseg_1722, 6, vd); + setArg(call_vlxseg_1722, 7, vlxseg_1722_arg6); + setArg(call_vlxseg_1722, 8, vs2); + setArg(call_vlxseg_1722, 9, 5); + setArg(call_vlxseg_1722, 10, 1); + setArg(call_vlxseg_1722, 11, vlxseg_1722_arg10); + setArg(call_vlxseg_1722, 12, 0); + setRet(call_vlxseg_1722, 0, ret_val_vlxseg_1722); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 465); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 466: VLUXSEG5EI16__V */ + continuation_e __vluxseg5ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG5EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 466); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1724; + x86::Gp ret_val_get_pow_1724 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1724, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1725; + x86::Gp ret_val_get_sew_pow_1725 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1725, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1726; + x86::Gp ret_val_get_lmul_pow_1726 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1726, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1724, ret_val_get_sew_pow_1725), ret_val_get_lmul_pow_1726)), 3, true); + setArg(call_get_pow_1724, 0, reinterpret_cast(this)); + setArg(call_get_pow_1724, 1, EEW); + setRet(call_get_pow_1724, 0, ret_val_get_pow_1724); + setArg(call_get_sew_pow_1725, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1725, 0, ret_val_get_sew_pow_1725); + setArg(call_get_lmul_pow_1726, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1726, 0, ret_val_get_lmul_pow_1726); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1728; + x86::Gp ret_val_get_lmul_pow_1728 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1728, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1727; + auto illegal_indexed_load_1727_arg4 = EMUL_pow; + auto illegal_indexed_load_1727_arg5 = ret_val_get_lmul_pow_1728; + x86::Gp ret_val_illegal_indexed_load_1727 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1727, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1727; + setArg(call_get_lmul_pow_1728, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1728, 0, ret_val_get_lmul_pow_1728); + setArg(call_illegal_indexed_load_1727, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1727, 1, vd); + setArg(call_illegal_indexed_load_1727, 2, vm); + setArg(call_illegal_indexed_load_1727, 3, 5); + setArg(call_illegal_indexed_load_1727, 4, EEW); + setArg(call_illegal_indexed_load_1727, 5, illegal_indexed_load_1727_arg4); + setArg(call_illegal_indexed_load_1727, 6, illegal_indexed_load_1727_arg5); + setRet(call_illegal_indexed_load_1727, 0, ret_val_illegal_indexed_load_1727); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1730; + x86::Gp ret_val_sew_1730 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1730, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1729; + auto vlxseg_1729_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1729_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1729_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1729_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1729_arg10 = ret_val_sew_1730; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1729 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1729, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1729, 64, false), traits::vstart); + setArg(call_sew_1730, 0, reinterpret_cast(this)); + setRet(call_sew_1730, 0, ret_val_sew_1730); + setArg(call_vlxseg_1729, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1729, 1, V); + setArg(call_vlxseg_1729, 2, vlxseg_1729_arg1); + setArg(call_vlxseg_1729, 3, vlxseg_1729_arg2); + setArg(call_vlxseg_1729, 4, vlxseg_1729_arg3); + setArg(call_vlxseg_1729, 5, vm); + setArg(call_vlxseg_1729, 6, vd); + setArg(call_vlxseg_1729, 7, vlxseg_1729_arg6); + setArg(call_vlxseg_1729, 8, vs2); + setArg(call_vlxseg_1729, 9, 5); + setArg(call_vlxseg_1729, 10, 2); + setArg(call_vlxseg_1729, 11, vlxseg_1729_arg10); + setArg(call_vlxseg_1729, 12, 0); + setRet(call_vlxseg_1729, 0, ret_val_vlxseg_1729); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 466); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 467: VLUXSEG5EI32__V */ + continuation_e __vluxseg5ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG5EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 467); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1731; + x86::Gp ret_val_get_pow_1731 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1731, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1732; + x86::Gp ret_val_get_sew_pow_1732 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1732, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1733; + x86::Gp ret_val_get_lmul_pow_1733 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1733, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1731, ret_val_get_sew_pow_1732), ret_val_get_lmul_pow_1733)), 3, true); + setArg(call_get_pow_1731, 0, reinterpret_cast(this)); + setArg(call_get_pow_1731, 1, EEW); + setRet(call_get_pow_1731, 0, ret_val_get_pow_1731); + setArg(call_get_sew_pow_1732, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1732, 0, ret_val_get_sew_pow_1732); + setArg(call_get_lmul_pow_1733, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1733, 0, ret_val_get_lmul_pow_1733); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1735; + x86::Gp ret_val_get_lmul_pow_1735 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1735, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1734; + auto illegal_indexed_load_1734_arg4 = EMUL_pow; + auto illegal_indexed_load_1734_arg5 = ret_val_get_lmul_pow_1735; + x86::Gp ret_val_illegal_indexed_load_1734 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1734, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1734; + setArg(call_get_lmul_pow_1735, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1735, 0, ret_val_get_lmul_pow_1735); + setArg(call_illegal_indexed_load_1734, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1734, 1, vd); + setArg(call_illegal_indexed_load_1734, 2, vm); + setArg(call_illegal_indexed_load_1734, 3, 5); + setArg(call_illegal_indexed_load_1734, 4, EEW); + setArg(call_illegal_indexed_load_1734, 5, illegal_indexed_load_1734_arg4); + setArg(call_illegal_indexed_load_1734, 6, illegal_indexed_load_1734_arg5); + setRet(call_illegal_indexed_load_1734, 0, ret_val_illegal_indexed_load_1734); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1737; + x86::Gp ret_val_sew_1737 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1737, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1736; + auto vlxseg_1736_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1736_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1736_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1736_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1736_arg10 = ret_val_sew_1737; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1736 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1736, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1736, 64, false), traits::vstart); + setArg(call_sew_1737, 0, reinterpret_cast(this)); + setRet(call_sew_1737, 0, ret_val_sew_1737); + setArg(call_vlxseg_1736, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1736, 1, V); + setArg(call_vlxseg_1736, 2, vlxseg_1736_arg1); + setArg(call_vlxseg_1736, 3, vlxseg_1736_arg2); + setArg(call_vlxseg_1736, 4, vlxseg_1736_arg3); + setArg(call_vlxseg_1736, 5, vm); + setArg(call_vlxseg_1736, 6, vd); + setArg(call_vlxseg_1736, 7, vlxseg_1736_arg6); + setArg(call_vlxseg_1736, 8, vs2); + setArg(call_vlxseg_1736, 9, 5); + setArg(call_vlxseg_1736, 10, 4); + setArg(call_vlxseg_1736, 11, vlxseg_1736_arg10); + setArg(call_vlxseg_1736, 12, 0); + setRet(call_vlxseg_1736, 0, ret_val_vlxseg_1736); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 467); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 468: VLUXSEG5EI64__V */ + continuation_e __vluxseg5ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg5ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG5EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 468); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1738; + x86::Gp ret_val_get_pow_1738 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1738, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1739; + x86::Gp ret_val_get_sew_pow_1739 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1739, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1740; + x86::Gp ret_val_get_lmul_pow_1740 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1740, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1738, ret_val_get_sew_pow_1739), ret_val_get_lmul_pow_1740)), 3, true); + setArg(call_get_pow_1738, 0, reinterpret_cast(this)); + setArg(call_get_pow_1738, 1, EEW); + setRet(call_get_pow_1738, 0, ret_val_get_pow_1738); + setArg(call_get_sew_pow_1739, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1739, 0, ret_val_get_sew_pow_1739); + setArg(call_get_lmul_pow_1740, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1740, 0, ret_val_get_lmul_pow_1740); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1742; + x86::Gp ret_val_get_lmul_pow_1742 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1742, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1741; + auto illegal_indexed_load_1741_arg4 = EMUL_pow; + auto illegal_indexed_load_1741_arg5 = ret_val_get_lmul_pow_1742; + x86::Gp ret_val_illegal_indexed_load_1741 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1741, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1741; + setArg(call_get_lmul_pow_1742, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1742, 0, ret_val_get_lmul_pow_1742); + setArg(call_illegal_indexed_load_1741, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1741, 1, vd); + setArg(call_illegal_indexed_load_1741, 2, vm); + setArg(call_illegal_indexed_load_1741, 3, 5); + setArg(call_illegal_indexed_load_1741, 4, EEW); + setArg(call_illegal_indexed_load_1741, 5, illegal_indexed_load_1741_arg4); + setArg(call_illegal_indexed_load_1741, 6, illegal_indexed_load_1741_arg5); + setRet(call_illegal_indexed_load_1741, 0, ret_val_illegal_indexed_load_1741); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1744; + x86::Gp ret_val_sew_1744 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1744, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1743; + auto vlxseg_1743_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1743_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1743_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1743_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1743_arg10 = ret_val_sew_1744; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1743 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1743, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1743, 64, false), traits::vstart); + setArg(call_sew_1744, 0, reinterpret_cast(this)); + setRet(call_sew_1744, 0, ret_val_sew_1744); + setArg(call_vlxseg_1743, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1743, 1, V); + setArg(call_vlxseg_1743, 2, vlxseg_1743_arg1); + setArg(call_vlxseg_1743, 3, vlxseg_1743_arg2); + setArg(call_vlxseg_1743, 4, vlxseg_1743_arg3); + setArg(call_vlxseg_1743, 5, vm); + setArg(call_vlxseg_1743, 6, vd); + setArg(call_vlxseg_1743, 7, vlxseg_1743_arg6); + setArg(call_vlxseg_1743, 8, vs2); + setArg(call_vlxseg_1743, 9, 5); + setArg(call_vlxseg_1743, 10, 8); + setArg(call_vlxseg_1743, 11, vlxseg_1743_arg10); + setArg(call_vlxseg_1743, 12, 0); + setRet(call_vlxseg_1743, 0, ret_val_vlxseg_1743); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 468); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 469: VLUXSEG6EI8__V */ + continuation_e __vluxseg6ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG6EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 469); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1745; + x86::Gp ret_val_get_pow_1745 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1745, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1746; + x86::Gp ret_val_get_sew_pow_1746 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1746, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1747; + x86::Gp ret_val_get_lmul_pow_1747 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1747, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1745, ret_val_get_sew_pow_1746), ret_val_get_lmul_pow_1747)), 3, true); + setArg(call_get_pow_1745, 0, reinterpret_cast(this)); + setArg(call_get_pow_1745, 1, EEW); + setRet(call_get_pow_1745, 0, ret_val_get_pow_1745); + setArg(call_get_sew_pow_1746, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1746, 0, ret_val_get_sew_pow_1746); + setArg(call_get_lmul_pow_1747, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1747, 0, ret_val_get_lmul_pow_1747); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1749; + x86::Gp ret_val_get_lmul_pow_1749 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1749, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1748; + auto illegal_indexed_load_1748_arg4 = EMUL_pow; + auto illegal_indexed_load_1748_arg5 = ret_val_get_lmul_pow_1749; + x86::Gp ret_val_illegal_indexed_load_1748 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1748, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1748; + setArg(call_get_lmul_pow_1749, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1749, 0, ret_val_get_lmul_pow_1749); + setArg(call_illegal_indexed_load_1748, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1748, 1, vd); + setArg(call_illegal_indexed_load_1748, 2, vm); + setArg(call_illegal_indexed_load_1748, 3, 6); + setArg(call_illegal_indexed_load_1748, 4, EEW); + setArg(call_illegal_indexed_load_1748, 5, illegal_indexed_load_1748_arg4); + setArg(call_illegal_indexed_load_1748, 6, illegal_indexed_load_1748_arg5); + setRet(call_illegal_indexed_load_1748, 0, ret_val_illegal_indexed_load_1748); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1751; + x86::Gp ret_val_sew_1751 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1751, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1750; + auto vlxseg_1750_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1750_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1750_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1750_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1750_arg10 = ret_val_sew_1751; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1750 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1750, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1750, 64, false), traits::vstart); + setArg(call_sew_1751, 0, reinterpret_cast(this)); + setRet(call_sew_1751, 0, ret_val_sew_1751); + setArg(call_vlxseg_1750, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1750, 1, V); + setArg(call_vlxseg_1750, 2, vlxseg_1750_arg1); + setArg(call_vlxseg_1750, 3, vlxseg_1750_arg2); + setArg(call_vlxseg_1750, 4, vlxseg_1750_arg3); + setArg(call_vlxseg_1750, 5, vm); + setArg(call_vlxseg_1750, 6, vd); + setArg(call_vlxseg_1750, 7, vlxseg_1750_arg6); + setArg(call_vlxseg_1750, 8, vs2); + setArg(call_vlxseg_1750, 9, 6); + setArg(call_vlxseg_1750, 10, 1); + setArg(call_vlxseg_1750, 11, vlxseg_1750_arg10); + setArg(call_vlxseg_1750, 12, 0); + setRet(call_vlxseg_1750, 0, ret_val_vlxseg_1750); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 469); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 470: VLUXSEG6EI16__V */ + continuation_e __vluxseg6ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG6EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 470); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1752; + x86::Gp ret_val_get_pow_1752 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1752, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1753; + x86::Gp ret_val_get_sew_pow_1753 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1753, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1754; + x86::Gp ret_val_get_lmul_pow_1754 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1754, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1752, ret_val_get_sew_pow_1753), ret_val_get_lmul_pow_1754)), 3, true); + setArg(call_get_pow_1752, 0, reinterpret_cast(this)); + setArg(call_get_pow_1752, 1, EEW); + setRet(call_get_pow_1752, 0, ret_val_get_pow_1752); + setArg(call_get_sew_pow_1753, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1753, 0, ret_val_get_sew_pow_1753); + setArg(call_get_lmul_pow_1754, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1754, 0, ret_val_get_lmul_pow_1754); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1756; + x86::Gp ret_val_get_lmul_pow_1756 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1756, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1755; + auto illegal_indexed_load_1755_arg4 = EMUL_pow; + auto illegal_indexed_load_1755_arg5 = ret_val_get_lmul_pow_1756; + x86::Gp ret_val_illegal_indexed_load_1755 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1755, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1755; + setArg(call_get_lmul_pow_1756, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1756, 0, ret_val_get_lmul_pow_1756); + setArg(call_illegal_indexed_load_1755, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1755, 1, vd); + setArg(call_illegal_indexed_load_1755, 2, vm); + setArg(call_illegal_indexed_load_1755, 3, 6); + setArg(call_illegal_indexed_load_1755, 4, EEW); + setArg(call_illegal_indexed_load_1755, 5, illegal_indexed_load_1755_arg4); + setArg(call_illegal_indexed_load_1755, 6, illegal_indexed_load_1755_arg5); + setRet(call_illegal_indexed_load_1755, 0, ret_val_illegal_indexed_load_1755); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1758; + x86::Gp ret_val_sew_1758 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1758, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1757; + auto vlxseg_1757_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1757_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1757_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1757_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1757_arg10 = ret_val_sew_1758; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1757 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1757, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1757, 64, false), traits::vstart); + setArg(call_sew_1758, 0, reinterpret_cast(this)); + setRet(call_sew_1758, 0, ret_val_sew_1758); + setArg(call_vlxseg_1757, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1757, 1, V); + setArg(call_vlxseg_1757, 2, vlxseg_1757_arg1); + setArg(call_vlxseg_1757, 3, vlxseg_1757_arg2); + setArg(call_vlxseg_1757, 4, vlxseg_1757_arg3); + setArg(call_vlxseg_1757, 5, vm); + setArg(call_vlxseg_1757, 6, vd); + setArg(call_vlxseg_1757, 7, vlxseg_1757_arg6); + setArg(call_vlxseg_1757, 8, vs2); + setArg(call_vlxseg_1757, 9, 6); + setArg(call_vlxseg_1757, 10, 2); + setArg(call_vlxseg_1757, 11, vlxseg_1757_arg10); + setArg(call_vlxseg_1757, 12, 0); + setRet(call_vlxseg_1757, 0, ret_val_vlxseg_1757); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 470); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 471: VLUXSEG6EI32__V */ + continuation_e __vluxseg6ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG6EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 471); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1759; + x86::Gp ret_val_get_pow_1759 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1759, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1760; + x86::Gp ret_val_get_sew_pow_1760 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1760, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1761; + x86::Gp ret_val_get_lmul_pow_1761 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1761, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1759, ret_val_get_sew_pow_1760), ret_val_get_lmul_pow_1761)), 3, true); + setArg(call_get_pow_1759, 0, reinterpret_cast(this)); + setArg(call_get_pow_1759, 1, EEW); + setRet(call_get_pow_1759, 0, ret_val_get_pow_1759); + setArg(call_get_sew_pow_1760, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1760, 0, ret_val_get_sew_pow_1760); + setArg(call_get_lmul_pow_1761, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1761, 0, ret_val_get_lmul_pow_1761); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1763; + x86::Gp ret_val_get_lmul_pow_1763 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1763, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1762; + auto illegal_indexed_load_1762_arg4 = EMUL_pow; + auto illegal_indexed_load_1762_arg5 = ret_val_get_lmul_pow_1763; + x86::Gp ret_val_illegal_indexed_load_1762 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1762, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1762; + setArg(call_get_lmul_pow_1763, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1763, 0, ret_val_get_lmul_pow_1763); + setArg(call_illegal_indexed_load_1762, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1762, 1, vd); + setArg(call_illegal_indexed_load_1762, 2, vm); + setArg(call_illegal_indexed_load_1762, 3, 6); + setArg(call_illegal_indexed_load_1762, 4, EEW); + setArg(call_illegal_indexed_load_1762, 5, illegal_indexed_load_1762_arg4); + setArg(call_illegal_indexed_load_1762, 6, illegal_indexed_load_1762_arg5); + setRet(call_illegal_indexed_load_1762, 0, ret_val_illegal_indexed_load_1762); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1765; + x86::Gp ret_val_sew_1765 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1765, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1764; + auto vlxseg_1764_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1764_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1764_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1764_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1764_arg10 = ret_val_sew_1765; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1764 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1764, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1764, 64, false), traits::vstart); + setArg(call_sew_1765, 0, reinterpret_cast(this)); + setRet(call_sew_1765, 0, ret_val_sew_1765); + setArg(call_vlxseg_1764, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1764, 1, V); + setArg(call_vlxseg_1764, 2, vlxseg_1764_arg1); + setArg(call_vlxseg_1764, 3, vlxseg_1764_arg2); + setArg(call_vlxseg_1764, 4, vlxseg_1764_arg3); + setArg(call_vlxseg_1764, 5, vm); + setArg(call_vlxseg_1764, 6, vd); + setArg(call_vlxseg_1764, 7, vlxseg_1764_arg6); + setArg(call_vlxseg_1764, 8, vs2); + setArg(call_vlxseg_1764, 9, 6); + setArg(call_vlxseg_1764, 10, 4); + setArg(call_vlxseg_1764, 11, vlxseg_1764_arg10); + setArg(call_vlxseg_1764, 12, 0); + setRet(call_vlxseg_1764, 0, ret_val_vlxseg_1764); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 471); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 472: VLUXSEG6EI64__V */ + continuation_e __vluxseg6ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg6ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG6EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 472); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1766; + x86::Gp ret_val_get_pow_1766 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1766, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1767; + x86::Gp ret_val_get_sew_pow_1767 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1767, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1768; + x86::Gp ret_val_get_lmul_pow_1768 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1768, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1766, ret_val_get_sew_pow_1767), ret_val_get_lmul_pow_1768)), 3, true); + setArg(call_get_pow_1766, 0, reinterpret_cast(this)); + setArg(call_get_pow_1766, 1, EEW); + setRet(call_get_pow_1766, 0, ret_val_get_pow_1766); + setArg(call_get_sew_pow_1767, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1767, 0, ret_val_get_sew_pow_1767); + setArg(call_get_lmul_pow_1768, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1768, 0, ret_val_get_lmul_pow_1768); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1770; + x86::Gp ret_val_get_lmul_pow_1770 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1770, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1769; + auto illegal_indexed_load_1769_arg4 = EMUL_pow; + auto illegal_indexed_load_1769_arg5 = ret_val_get_lmul_pow_1770; + x86::Gp ret_val_illegal_indexed_load_1769 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1769, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1769; + setArg(call_get_lmul_pow_1770, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1770, 0, ret_val_get_lmul_pow_1770); + setArg(call_illegal_indexed_load_1769, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1769, 1, vd); + setArg(call_illegal_indexed_load_1769, 2, vm); + setArg(call_illegal_indexed_load_1769, 3, 6); + setArg(call_illegal_indexed_load_1769, 4, EEW); + setArg(call_illegal_indexed_load_1769, 5, illegal_indexed_load_1769_arg4); + setArg(call_illegal_indexed_load_1769, 6, illegal_indexed_load_1769_arg5); + setRet(call_illegal_indexed_load_1769, 0, ret_val_illegal_indexed_load_1769); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1772; + x86::Gp ret_val_sew_1772 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1772, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1771; + auto vlxseg_1771_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1771_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1771_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1771_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1771_arg10 = ret_val_sew_1772; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1771 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1771, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1771, 64, false), traits::vstart); + setArg(call_sew_1772, 0, reinterpret_cast(this)); + setRet(call_sew_1772, 0, ret_val_sew_1772); + setArg(call_vlxseg_1771, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1771, 1, V); + setArg(call_vlxseg_1771, 2, vlxseg_1771_arg1); + setArg(call_vlxseg_1771, 3, vlxseg_1771_arg2); + setArg(call_vlxseg_1771, 4, vlxseg_1771_arg3); + setArg(call_vlxseg_1771, 5, vm); + setArg(call_vlxseg_1771, 6, vd); + setArg(call_vlxseg_1771, 7, vlxseg_1771_arg6); + setArg(call_vlxseg_1771, 8, vs2); + setArg(call_vlxseg_1771, 9, 6); + setArg(call_vlxseg_1771, 10, 8); + setArg(call_vlxseg_1771, 11, vlxseg_1771_arg10); + setArg(call_vlxseg_1771, 12, 0); + setRet(call_vlxseg_1771, 0, ret_val_vlxseg_1771); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 472); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 473: VLUXSEG7EI8__V */ + continuation_e __vluxseg7ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG7EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 473); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1773; + x86::Gp ret_val_get_pow_1773 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1773, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1774; + x86::Gp ret_val_get_sew_pow_1774 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1774, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1775; + x86::Gp ret_val_get_lmul_pow_1775 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1775, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1773, ret_val_get_sew_pow_1774), ret_val_get_lmul_pow_1775)), 3, true); + setArg(call_get_pow_1773, 0, reinterpret_cast(this)); + setArg(call_get_pow_1773, 1, EEW); + setRet(call_get_pow_1773, 0, ret_val_get_pow_1773); + setArg(call_get_sew_pow_1774, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1774, 0, ret_val_get_sew_pow_1774); + setArg(call_get_lmul_pow_1775, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1775, 0, ret_val_get_lmul_pow_1775); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1777; + x86::Gp ret_val_get_lmul_pow_1777 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1777, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1776; + auto illegal_indexed_load_1776_arg4 = EMUL_pow; + auto illegal_indexed_load_1776_arg5 = ret_val_get_lmul_pow_1777; + x86::Gp ret_val_illegal_indexed_load_1776 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1776, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1776; + setArg(call_get_lmul_pow_1777, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1777, 0, ret_val_get_lmul_pow_1777); + setArg(call_illegal_indexed_load_1776, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1776, 1, vd); + setArg(call_illegal_indexed_load_1776, 2, vm); + setArg(call_illegal_indexed_load_1776, 3, 7); + setArg(call_illegal_indexed_load_1776, 4, EEW); + setArg(call_illegal_indexed_load_1776, 5, illegal_indexed_load_1776_arg4); + setArg(call_illegal_indexed_load_1776, 6, illegal_indexed_load_1776_arg5); + setRet(call_illegal_indexed_load_1776, 0, ret_val_illegal_indexed_load_1776); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1779; + x86::Gp ret_val_sew_1779 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1779, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1778; + auto vlxseg_1778_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1778_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1778_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1778_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1778_arg10 = ret_val_sew_1779; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1778 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1778, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1778, 64, false), traits::vstart); + setArg(call_sew_1779, 0, reinterpret_cast(this)); + setRet(call_sew_1779, 0, ret_val_sew_1779); + setArg(call_vlxseg_1778, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1778, 1, V); + setArg(call_vlxseg_1778, 2, vlxseg_1778_arg1); + setArg(call_vlxseg_1778, 3, vlxseg_1778_arg2); + setArg(call_vlxseg_1778, 4, vlxseg_1778_arg3); + setArg(call_vlxseg_1778, 5, vm); + setArg(call_vlxseg_1778, 6, vd); + setArg(call_vlxseg_1778, 7, vlxseg_1778_arg6); + setArg(call_vlxseg_1778, 8, vs2); + setArg(call_vlxseg_1778, 9, 7); + setArg(call_vlxseg_1778, 10, 1); + setArg(call_vlxseg_1778, 11, vlxseg_1778_arg10); + setArg(call_vlxseg_1778, 12, 0); + setRet(call_vlxseg_1778, 0, ret_val_vlxseg_1778); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 473); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 474: VLUXSEG7EI16__V */ + continuation_e __vluxseg7ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG7EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 474); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1780; + x86::Gp ret_val_get_pow_1780 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1780, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1781; + x86::Gp ret_val_get_sew_pow_1781 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1781, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1782; + x86::Gp ret_val_get_lmul_pow_1782 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1782, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1780, ret_val_get_sew_pow_1781), ret_val_get_lmul_pow_1782)), 3, true); + setArg(call_get_pow_1780, 0, reinterpret_cast(this)); + setArg(call_get_pow_1780, 1, EEW); + setRet(call_get_pow_1780, 0, ret_val_get_pow_1780); + setArg(call_get_sew_pow_1781, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1781, 0, ret_val_get_sew_pow_1781); + setArg(call_get_lmul_pow_1782, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1782, 0, ret_val_get_lmul_pow_1782); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1784; + x86::Gp ret_val_get_lmul_pow_1784 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1784, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1783; + auto illegal_indexed_load_1783_arg4 = EMUL_pow; + auto illegal_indexed_load_1783_arg5 = ret_val_get_lmul_pow_1784; + x86::Gp ret_val_illegal_indexed_load_1783 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1783, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1783; + setArg(call_get_lmul_pow_1784, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1784, 0, ret_val_get_lmul_pow_1784); + setArg(call_illegal_indexed_load_1783, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1783, 1, vd); + setArg(call_illegal_indexed_load_1783, 2, vm); + setArg(call_illegal_indexed_load_1783, 3, 7); + setArg(call_illegal_indexed_load_1783, 4, EEW); + setArg(call_illegal_indexed_load_1783, 5, illegal_indexed_load_1783_arg4); + setArg(call_illegal_indexed_load_1783, 6, illegal_indexed_load_1783_arg5); + setRet(call_illegal_indexed_load_1783, 0, ret_val_illegal_indexed_load_1783); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1786; + x86::Gp ret_val_sew_1786 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1786, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1785; + auto vlxseg_1785_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1785_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1785_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1785_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1785_arg10 = ret_val_sew_1786; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1785 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1785, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1785, 64, false), traits::vstart); + setArg(call_sew_1786, 0, reinterpret_cast(this)); + setRet(call_sew_1786, 0, ret_val_sew_1786); + setArg(call_vlxseg_1785, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1785, 1, V); + setArg(call_vlxseg_1785, 2, vlxseg_1785_arg1); + setArg(call_vlxseg_1785, 3, vlxseg_1785_arg2); + setArg(call_vlxseg_1785, 4, vlxseg_1785_arg3); + setArg(call_vlxseg_1785, 5, vm); + setArg(call_vlxseg_1785, 6, vd); + setArg(call_vlxseg_1785, 7, vlxseg_1785_arg6); + setArg(call_vlxseg_1785, 8, vs2); + setArg(call_vlxseg_1785, 9, 7); + setArg(call_vlxseg_1785, 10, 2); + setArg(call_vlxseg_1785, 11, vlxseg_1785_arg10); + setArg(call_vlxseg_1785, 12, 0); + setRet(call_vlxseg_1785, 0, ret_val_vlxseg_1785); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 474); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 475: VLUXSEG7EI32__V */ + continuation_e __vluxseg7ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG7EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 475); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1787; + x86::Gp ret_val_get_pow_1787 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1787, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1788; + x86::Gp ret_val_get_sew_pow_1788 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1788, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1789; + x86::Gp ret_val_get_lmul_pow_1789 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1789, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1787, ret_val_get_sew_pow_1788), ret_val_get_lmul_pow_1789)), 3, true); + setArg(call_get_pow_1787, 0, reinterpret_cast(this)); + setArg(call_get_pow_1787, 1, EEW); + setRet(call_get_pow_1787, 0, ret_val_get_pow_1787); + setArg(call_get_sew_pow_1788, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1788, 0, ret_val_get_sew_pow_1788); + setArg(call_get_lmul_pow_1789, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1789, 0, ret_val_get_lmul_pow_1789); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1791; + x86::Gp ret_val_get_lmul_pow_1791 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1791, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1790; + auto illegal_indexed_load_1790_arg4 = EMUL_pow; + auto illegal_indexed_load_1790_arg5 = ret_val_get_lmul_pow_1791; + x86::Gp ret_val_illegal_indexed_load_1790 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1790, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1790; + setArg(call_get_lmul_pow_1791, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1791, 0, ret_val_get_lmul_pow_1791); + setArg(call_illegal_indexed_load_1790, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1790, 1, vd); + setArg(call_illegal_indexed_load_1790, 2, vm); + setArg(call_illegal_indexed_load_1790, 3, 7); + setArg(call_illegal_indexed_load_1790, 4, EEW); + setArg(call_illegal_indexed_load_1790, 5, illegal_indexed_load_1790_arg4); + setArg(call_illegal_indexed_load_1790, 6, illegal_indexed_load_1790_arg5); + setRet(call_illegal_indexed_load_1790, 0, ret_val_illegal_indexed_load_1790); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1793; + x86::Gp ret_val_sew_1793 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1793, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1792; + auto vlxseg_1792_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1792_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1792_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1792_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1792_arg10 = ret_val_sew_1793; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1792 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1792, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1792, 64, false), traits::vstart); + setArg(call_sew_1793, 0, reinterpret_cast(this)); + setRet(call_sew_1793, 0, ret_val_sew_1793); + setArg(call_vlxseg_1792, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1792, 1, V); + setArg(call_vlxseg_1792, 2, vlxseg_1792_arg1); + setArg(call_vlxseg_1792, 3, vlxseg_1792_arg2); + setArg(call_vlxseg_1792, 4, vlxseg_1792_arg3); + setArg(call_vlxseg_1792, 5, vm); + setArg(call_vlxseg_1792, 6, vd); + setArg(call_vlxseg_1792, 7, vlxseg_1792_arg6); + setArg(call_vlxseg_1792, 8, vs2); + setArg(call_vlxseg_1792, 9, 7); + setArg(call_vlxseg_1792, 10, 4); + setArg(call_vlxseg_1792, 11, vlxseg_1792_arg10); + setArg(call_vlxseg_1792, 12, 0); + setRet(call_vlxseg_1792, 0, ret_val_vlxseg_1792); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 475); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 476: VLUXSEG7EI64__V */ + continuation_e __vluxseg7ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg7ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG7EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 476); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1794; + x86::Gp ret_val_get_pow_1794 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1794, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1795; + x86::Gp ret_val_get_sew_pow_1795 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1795, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1796; + x86::Gp ret_val_get_lmul_pow_1796 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1796, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1794, ret_val_get_sew_pow_1795), ret_val_get_lmul_pow_1796)), 3, true); + setArg(call_get_pow_1794, 0, reinterpret_cast(this)); + setArg(call_get_pow_1794, 1, EEW); + setRet(call_get_pow_1794, 0, ret_val_get_pow_1794); + setArg(call_get_sew_pow_1795, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1795, 0, ret_val_get_sew_pow_1795); + setArg(call_get_lmul_pow_1796, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1796, 0, ret_val_get_lmul_pow_1796); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1798; + x86::Gp ret_val_get_lmul_pow_1798 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1798, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1797; + auto illegal_indexed_load_1797_arg4 = EMUL_pow; + auto illegal_indexed_load_1797_arg5 = ret_val_get_lmul_pow_1798; + x86::Gp ret_val_illegal_indexed_load_1797 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1797, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1797; + setArg(call_get_lmul_pow_1798, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1798, 0, ret_val_get_lmul_pow_1798); + setArg(call_illegal_indexed_load_1797, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1797, 1, vd); + setArg(call_illegal_indexed_load_1797, 2, vm); + setArg(call_illegal_indexed_load_1797, 3, 7); + setArg(call_illegal_indexed_load_1797, 4, EEW); + setArg(call_illegal_indexed_load_1797, 5, illegal_indexed_load_1797_arg4); + setArg(call_illegal_indexed_load_1797, 6, illegal_indexed_load_1797_arg5); + setRet(call_illegal_indexed_load_1797, 0, ret_val_illegal_indexed_load_1797); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1800; + x86::Gp ret_val_sew_1800 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1800, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1799; + auto vlxseg_1799_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1799_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1799_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1799_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1799_arg10 = ret_val_sew_1800; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1799 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1799, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1799, 64, false), traits::vstart); + setArg(call_sew_1800, 0, reinterpret_cast(this)); + setRet(call_sew_1800, 0, ret_val_sew_1800); + setArg(call_vlxseg_1799, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1799, 1, V); + setArg(call_vlxseg_1799, 2, vlxseg_1799_arg1); + setArg(call_vlxseg_1799, 3, vlxseg_1799_arg2); + setArg(call_vlxseg_1799, 4, vlxseg_1799_arg3); + setArg(call_vlxseg_1799, 5, vm); + setArg(call_vlxseg_1799, 6, vd); + setArg(call_vlxseg_1799, 7, vlxseg_1799_arg6); + setArg(call_vlxseg_1799, 8, vs2); + setArg(call_vlxseg_1799, 9, 7); + setArg(call_vlxseg_1799, 10, 8); + setArg(call_vlxseg_1799, 11, vlxseg_1799_arg10); + setArg(call_vlxseg_1799, 12, 0); + setRet(call_vlxseg_1799, 0, ret_val_vlxseg_1799); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 476); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 477: VLUXSEG8EI8__V */ + continuation_e __vluxseg8ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei8.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG8EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 477); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1801; + x86::Gp ret_val_get_pow_1801 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1801, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1802; + x86::Gp ret_val_get_sew_pow_1802 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1802, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1803; + x86::Gp ret_val_get_lmul_pow_1803 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1803, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1801, ret_val_get_sew_pow_1802), ret_val_get_lmul_pow_1803)), 3, true); + setArg(call_get_pow_1801, 0, reinterpret_cast(this)); + setArg(call_get_pow_1801, 1, EEW); + setRet(call_get_pow_1801, 0, ret_val_get_pow_1801); + setArg(call_get_sew_pow_1802, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1802, 0, ret_val_get_sew_pow_1802); + setArg(call_get_lmul_pow_1803, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1803, 0, ret_val_get_lmul_pow_1803); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1805; + x86::Gp ret_val_get_lmul_pow_1805 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1805, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1804; + auto illegal_indexed_load_1804_arg4 = EMUL_pow; + auto illegal_indexed_load_1804_arg5 = ret_val_get_lmul_pow_1805; + x86::Gp ret_val_illegal_indexed_load_1804 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1804, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1804; + setArg(call_get_lmul_pow_1805, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1805, 0, ret_val_get_lmul_pow_1805); + setArg(call_illegal_indexed_load_1804, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1804, 1, vd); + setArg(call_illegal_indexed_load_1804, 2, vm); + setArg(call_illegal_indexed_load_1804, 3, 8); + setArg(call_illegal_indexed_load_1804, 4, EEW); + setArg(call_illegal_indexed_load_1804, 5, illegal_indexed_load_1804_arg4); + setArg(call_illegal_indexed_load_1804, 6, illegal_indexed_load_1804_arg5); + setRet(call_illegal_indexed_load_1804, 0, ret_val_illegal_indexed_load_1804); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1807; + x86::Gp ret_val_sew_1807 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1807, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1806; + auto vlxseg_1806_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1806_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1806_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1806_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1806_arg10 = ret_val_sew_1807; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1806 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1806, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1806, 64, false), traits::vstart); + setArg(call_sew_1807, 0, reinterpret_cast(this)); + setRet(call_sew_1807, 0, ret_val_sew_1807); + setArg(call_vlxseg_1806, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1806, 1, V); + setArg(call_vlxseg_1806, 2, vlxseg_1806_arg1); + setArg(call_vlxseg_1806, 3, vlxseg_1806_arg2); + setArg(call_vlxseg_1806, 4, vlxseg_1806_arg3); + setArg(call_vlxseg_1806, 5, vm); + setArg(call_vlxseg_1806, 6, vd); + setArg(call_vlxseg_1806, 7, vlxseg_1806_arg6); + setArg(call_vlxseg_1806, 8, vs2); + setArg(call_vlxseg_1806, 9, 8); + setArg(call_vlxseg_1806, 10, 1); + setArg(call_vlxseg_1806, 11, vlxseg_1806_arg10); + setArg(call_vlxseg_1806, 12, 0); + setRet(call_vlxseg_1806, 0, ret_val_vlxseg_1806); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 477); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 478: VLUXSEG8EI16__V */ + continuation_e __vluxseg8ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei16.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG8EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 478); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1808; + x86::Gp ret_val_get_pow_1808 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1808, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1809; + x86::Gp ret_val_get_sew_pow_1809 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1809, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1810; + x86::Gp ret_val_get_lmul_pow_1810 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1810, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1808, ret_val_get_sew_pow_1809), ret_val_get_lmul_pow_1810)), 3, true); + setArg(call_get_pow_1808, 0, reinterpret_cast(this)); + setArg(call_get_pow_1808, 1, EEW); + setRet(call_get_pow_1808, 0, ret_val_get_pow_1808); + setArg(call_get_sew_pow_1809, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1809, 0, ret_val_get_sew_pow_1809); + setArg(call_get_lmul_pow_1810, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1810, 0, ret_val_get_lmul_pow_1810); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1812; + x86::Gp ret_val_get_lmul_pow_1812 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1812, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1811; + auto illegal_indexed_load_1811_arg4 = EMUL_pow; + auto illegal_indexed_load_1811_arg5 = ret_val_get_lmul_pow_1812; + x86::Gp ret_val_illegal_indexed_load_1811 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1811, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1811; + setArg(call_get_lmul_pow_1812, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1812, 0, ret_val_get_lmul_pow_1812); + setArg(call_illegal_indexed_load_1811, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1811, 1, vd); + setArg(call_illegal_indexed_load_1811, 2, vm); + setArg(call_illegal_indexed_load_1811, 3, 8); + setArg(call_illegal_indexed_load_1811, 4, EEW); + setArg(call_illegal_indexed_load_1811, 5, illegal_indexed_load_1811_arg4); + setArg(call_illegal_indexed_load_1811, 6, illegal_indexed_load_1811_arg5); + setRet(call_illegal_indexed_load_1811, 0, ret_val_illegal_indexed_load_1811); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1814; + x86::Gp ret_val_sew_1814 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1814, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1813; + auto vlxseg_1813_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1813_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1813_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1813_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1813_arg10 = ret_val_sew_1814; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1813 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1813, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1813, 64, false), traits::vstart); + setArg(call_sew_1814, 0, reinterpret_cast(this)); + setRet(call_sew_1814, 0, ret_val_sew_1814); + setArg(call_vlxseg_1813, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1813, 1, V); + setArg(call_vlxseg_1813, 2, vlxseg_1813_arg1); + setArg(call_vlxseg_1813, 3, vlxseg_1813_arg2); + setArg(call_vlxseg_1813, 4, vlxseg_1813_arg3); + setArg(call_vlxseg_1813, 5, vm); + setArg(call_vlxseg_1813, 6, vd); + setArg(call_vlxseg_1813, 7, vlxseg_1813_arg6); + setArg(call_vlxseg_1813, 8, vs2); + setArg(call_vlxseg_1813, 9, 8); + setArg(call_vlxseg_1813, 10, 2); + setArg(call_vlxseg_1813, 11, vlxseg_1813_arg10); + setArg(call_vlxseg_1813, 12, 0); + setRet(call_vlxseg_1813, 0, ret_val_vlxseg_1813); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 478); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 479: VLUXSEG8EI32__V */ + continuation_e __vluxseg8ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei32.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG8EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 479); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1815; + x86::Gp ret_val_get_pow_1815 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1815, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1816; + x86::Gp ret_val_get_sew_pow_1816 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1816, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1817; + x86::Gp ret_val_get_lmul_pow_1817 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1817, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1815, ret_val_get_sew_pow_1816), ret_val_get_lmul_pow_1817)), 3, true); + setArg(call_get_pow_1815, 0, reinterpret_cast(this)); + setArg(call_get_pow_1815, 1, EEW); + setRet(call_get_pow_1815, 0, ret_val_get_pow_1815); + setArg(call_get_sew_pow_1816, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1816, 0, ret_val_get_sew_pow_1816); + setArg(call_get_lmul_pow_1817, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1817, 0, ret_val_get_lmul_pow_1817); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1819; + x86::Gp ret_val_get_lmul_pow_1819 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1819, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1818; + auto illegal_indexed_load_1818_arg4 = EMUL_pow; + auto illegal_indexed_load_1818_arg5 = ret_val_get_lmul_pow_1819; + x86::Gp ret_val_illegal_indexed_load_1818 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1818, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1818; + setArg(call_get_lmul_pow_1819, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1819, 0, ret_val_get_lmul_pow_1819); + setArg(call_illegal_indexed_load_1818, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1818, 1, vd); + setArg(call_illegal_indexed_load_1818, 2, vm); + setArg(call_illegal_indexed_load_1818, 3, 8); + setArg(call_illegal_indexed_load_1818, 4, EEW); + setArg(call_illegal_indexed_load_1818, 5, illegal_indexed_load_1818_arg4); + setArg(call_illegal_indexed_load_1818, 6, illegal_indexed_load_1818_arg5); + setRet(call_illegal_indexed_load_1818, 0, ret_val_illegal_indexed_load_1818); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1821; + x86::Gp ret_val_sew_1821 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1821, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1820; + auto vlxseg_1820_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1820_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1820_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1820_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1820_arg10 = ret_val_sew_1821; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1820 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1820, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1820, 64, false), traits::vstart); + setArg(call_sew_1821, 0, reinterpret_cast(this)); + setRet(call_sew_1821, 0, ret_val_sew_1821); + setArg(call_vlxseg_1820, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1820, 1, V); + setArg(call_vlxseg_1820, 2, vlxseg_1820_arg1); + setArg(call_vlxseg_1820, 3, vlxseg_1820_arg2); + setArg(call_vlxseg_1820, 4, vlxseg_1820_arg3); + setArg(call_vlxseg_1820, 5, vm); + setArg(call_vlxseg_1820, 6, vd); + setArg(call_vlxseg_1820, 7, vlxseg_1820_arg6); + setArg(call_vlxseg_1820, 8, vs2); + setArg(call_vlxseg_1820, 9, 8); + setArg(call_vlxseg_1820, 10, 4); + setArg(call_vlxseg_1820, 11, vlxseg_1820_arg10); + setArg(call_vlxseg_1820, 12, 0); + setRet(call_vlxseg_1820, 0, ret_val_vlxseg_1820); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 479); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 480: VLUXSEG8EI64__V */ + continuation_e __vluxseg8ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vluxseg8ei64.v"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VLUXSEG8EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 480); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1822; + x86::Gp ret_val_get_pow_1822 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1822, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1823; + x86::Gp ret_val_get_sew_pow_1823 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1823, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1824; + x86::Gp ret_val_get_lmul_pow_1824 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1824, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1822, ret_val_get_sew_pow_1823), ret_val_get_lmul_pow_1824)), 3, true); + setArg(call_get_pow_1822, 0, reinterpret_cast(this)); + setArg(call_get_pow_1822, 1, EEW); + setRet(call_get_pow_1822, 0, ret_val_get_pow_1822); + setArg(call_get_sew_pow_1823, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1823, 0, ret_val_get_sew_pow_1823); + setArg(call_get_lmul_pow_1824, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1824, 0, ret_val_get_lmul_pow_1824); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1826; + x86::Gp ret_val_get_lmul_pow_1826 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1826, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_load_1825; + auto illegal_indexed_load_1825_arg4 = EMUL_pow; + auto illegal_indexed_load_1825_arg5 = ret_val_get_lmul_pow_1826; + x86::Gp ret_val_illegal_indexed_load_1825 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_load_1825, (uintptr_t)&vm_impl::_illegal_indexed_load, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_load_1825; + setArg(call_get_lmul_pow_1826, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1826, 0, ret_val_get_lmul_pow_1826); + setArg(call_illegal_indexed_load_1825, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_load_1825, 1, vd); + setArg(call_illegal_indexed_load_1825, 2, vm); + setArg(call_illegal_indexed_load_1825, 3, 8); + setArg(call_illegal_indexed_load_1825, 4, EEW); + setArg(call_illegal_indexed_load_1825, 5, illegal_indexed_load_1825_arg4); + setArg(call_illegal_indexed_load_1825, 6, illegal_indexed_load_1825_arg5); + setRet(call_illegal_indexed_load_1825, 0, ret_val_illegal_indexed_load_1825); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1828; + x86::Gp ret_val_sew_1828 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1828, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vlxseg_1827; + auto vlxseg_1827_arg1 = load_reg_from_mem(jh, traits::vl); + auto vlxseg_1827_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vlxseg_1827_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vlxseg_1827_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vlxseg_1827_arg10 = ret_val_sew_1828; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vlxseg_1827 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vlxseg_1827, &vlxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vlxseg_1827, 64, false), traits::vstart); + setArg(call_sew_1828, 0, reinterpret_cast(this)); + setRet(call_sew_1828, 0, ret_val_sew_1828); + setArg(call_vlxseg_1827, 0, reinterpret_cast(this->get_arch())); + setArg(call_vlxseg_1827, 1, V); + setArg(call_vlxseg_1827, 2, vlxseg_1827_arg1); + setArg(call_vlxseg_1827, 3, vlxseg_1827_arg2); + setArg(call_vlxseg_1827, 4, vlxseg_1827_arg3); + setArg(call_vlxseg_1827, 5, vm); + setArg(call_vlxseg_1827, 6, vd); + setArg(call_vlxseg_1827, 7, vlxseg_1827_arg6); + setArg(call_vlxseg_1827, 8, vs2); + setArg(call_vlxseg_1827, 9, 8); + setArg(call_vlxseg_1827, 10, 8); + setArg(call_vlxseg_1827, 11, vlxseg_1827_arg10); + setArg(call_vlxseg_1827, 12, 0); + setRet(call_vlxseg_1827, 0, ret_val_vlxseg_1827); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 480); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 481: VSUXEI8__V */ + continuation_e __vsuxei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXEI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 481); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1829; + x86::Gp ret_val_get_pow_1829 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1829, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1830; + x86::Gp ret_val_get_sew_pow_1830 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1830, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1831; + x86::Gp ret_val_get_lmul_pow_1831 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1831, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1829, ret_val_get_sew_pow_1830), ret_val_get_lmul_pow_1831)), 3, true); + setArg(call_get_pow_1829, 0, reinterpret_cast(this)); + setArg(call_get_pow_1829, 1, EEW); + setRet(call_get_pow_1829, 0, ret_val_get_pow_1829); + setArg(call_get_sew_pow_1830, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1830, 0, ret_val_get_sew_pow_1830); + setArg(call_get_lmul_pow_1831, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1831, 0, ret_val_get_lmul_pow_1831); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1833; + x86::Gp ret_val_get_lmul_pow_1833 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1833, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1832; + auto illegal_indexed_store_1832_arg2 = EMUL_pow; + auto illegal_indexed_store_1832_arg3 = ret_val_get_lmul_pow_1833; + x86::Gp ret_val_illegal_indexed_store_1832 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1832, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1832; + setArg(call_get_lmul_pow_1833, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1833, 0, ret_val_get_lmul_pow_1833); + setArg(call_illegal_indexed_store_1832, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1832, 1, 1); + setArg(call_illegal_indexed_store_1832, 2, EEW); + setArg(call_illegal_indexed_store_1832, 3, illegal_indexed_store_1832_arg2); + setArg(call_illegal_indexed_store_1832, 4, illegal_indexed_store_1832_arg3); + setRet(call_illegal_indexed_store_1832, 0, ret_val_illegal_indexed_store_1832); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1835; + x86::Gp ret_val_sew_1835 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1835, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1834; + auto vsxseg_1834_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1834_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1834_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1834_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1834_arg10 = ret_val_sew_1835; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1834 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1834, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1834, 64, false), traits::vstart); + setArg(call_sew_1835, 0, reinterpret_cast(this)); + setRet(call_sew_1835, 0, ret_val_sew_1835); + setArg(call_vsxseg_1834, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1834, 1, V); + setArg(call_vsxseg_1834, 2, vsxseg_1834_arg1); + setArg(call_vsxseg_1834, 3, vsxseg_1834_arg2); + setArg(call_vsxseg_1834, 4, vsxseg_1834_arg3); + setArg(call_vsxseg_1834, 5, vm); + setArg(call_vsxseg_1834, 6, vs3); + setArg(call_vsxseg_1834, 7, vsxseg_1834_arg6); + setArg(call_vsxseg_1834, 8, vs2); + setArg(call_vsxseg_1834, 9, 1); + setArg(call_vsxseg_1834, 10, 1); + setArg(call_vsxseg_1834, 11, vsxseg_1834_arg10); + setArg(call_vsxseg_1834, 12, 0); + setRet(call_vsxseg_1834, 0, ret_val_vsxseg_1834); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 481); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 482: VSUXEI16__V */ + continuation_e __vsuxei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXEI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 482); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1836; + x86::Gp ret_val_get_pow_1836 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1836, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1837; + x86::Gp ret_val_get_sew_pow_1837 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1837, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1838; + x86::Gp ret_val_get_lmul_pow_1838 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1838, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1836, ret_val_get_sew_pow_1837), ret_val_get_lmul_pow_1838)), 3, true); + setArg(call_get_pow_1836, 0, reinterpret_cast(this)); + setArg(call_get_pow_1836, 1, EEW); + setRet(call_get_pow_1836, 0, ret_val_get_pow_1836); + setArg(call_get_sew_pow_1837, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1837, 0, ret_val_get_sew_pow_1837); + setArg(call_get_lmul_pow_1838, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1838, 0, ret_val_get_lmul_pow_1838); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1840; + x86::Gp ret_val_get_lmul_pow_1840 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1840, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1839; + auto illegal_indexed_store_1839_arg2 = EMUL_pow; + auto illegal_indexed_store_1839_arg3 = ret_val_get_lmul_pow_1840; + x86::Gp ret_val_illegal_indexed_store_1839 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1839, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1839; + setArg(call_get_lmul_pow_1840, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1840, 0, ret_val_get_lmul_pow_1840); + setArg(call_illegal_indexed_store_1839, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1839, 1, 1); + setArg(call_illegal_indexed_store_1839, 2, EEW); + setArg(call_illegal_indexed_store_1839, 3, illegal_indexed_store_1839_arg2); + setArg(call_illegal_indexed_store_1839, 4, illegal_indexed_store_1839_arg3); + setRet(call_illegal_indexed_store_1839, 0, ret_val_illegal_indexed_store_1839); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1842; + x86::Gp ret_val_sew_1842 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1842, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1841; + auto vsxseg_1841_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1841_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1841_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1841_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1841_arg10 = ret_val_sew_1842; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1841 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1841, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1841, 64, false), traits::vstart); + setArg(call_sew_1842, 0, reinterpret_cast(this)); + setRet(call_sew_1842, 0, ret_val_sew_1842); + setArg(call_vsxseg_1841, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1841, 1, V); + setArg(call_vsxseg_1841, 2, vsxseg_1841_arg1); + setArg(call_vsxseg_1841, 3, vsxseg_1841_arg2); + setArg(call_vsxseg_1841, 4, vsxseg_1841_arg3); + setArg(call_vsxseg_1841, 5, vm); + setArg(call_vsxseg_1841, 6, vs3); + setArg(call_vsxseg_1841, 7, vsxseg_1841_arg6); + setArg(call_vsxseg_1841, 8, vs2); + setArg(call_vsxseg_1841, 9, 1); + setArg(call_vsxseg_1841, 10, 2); + setArg(call_vsxseg_1841, 11, vsxseg_1841_arg10); + setArg(call_vsxseg_1841, 12, 0); + setRet(call_vsxseg_1841, 0, ret_val_vsxseg_1841); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 482); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 483: VSUXEI32__V */ + continuation_e __vsuxei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXEI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 483); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1843; + x86::Gp ret_val_get_pow_1843 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1843, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1844; + x86::Gp ret_val_get_sew_pow_1844 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1844, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1845; + x86::Gp ret_val_get_lmul_pow_1845 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1845, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1843, ret_val_get_sew_pow_1844), ret_val_get_lmul_pow_1845)), 3, true); + setArg(call_get_pow_1843, 0, reinterpret_cast(this)); + setArg(call_get_pow_1843, 1, EEW); + setRet(call_get_pow_1843, 0, ret_val_get_pow_1843); + setArg(call_get_sew_pow_1844, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1844, 0, ret_val_get_sew_pow_1844); + setArg(call_get_lmul_pow_1845, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1845, 0, ret_val_get_lmul_pow_1845); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1847; + x86::Gp ret_val_get_lmul_pow_1847 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1847, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1846; + auto illegal_indexed_store_1846_arg2 = EMUL_pow; + auto illegal_indexed_store_1846_arg3 = ret_val_get_lmul_pow_1847; + x86::Gp ret_val_illegal_indexed_store_1846 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1846, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1846; + setArg(call_get_lmul_pow_1847, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1847, 0, ret_val_get_lmul_pow_1847); + setArg(call_illegal_indexed_store_1846, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1846, 1, 1); + setArg(call_illegal_indexed_store_1846, 2, EEW); + setArg(call_illegal_indexed_store_1846, 3, illegal_indexed_store_1846_arg2); + setArg(call_illegal_indexed_store_1846, 4, illegal_indexed_store_1846_arg3); + setRet(call_illegal_indexed_store_1846, 0, ret_val_illegal_indexed_store_1846); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1849; + x86::Gp ret_val_sew_1849 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1849, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1848; + auto vsxseg_1848_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1848_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1848_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1848_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1848_arg10 = ret_val_sew_1849; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1848 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1848, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1848, 64, false), traits::vstart); + setArg(call_sew_1849, 0, reinterpret_cast(this)); + setRet(call_sew_1849, 0, ret_val_sew_1849); + setArg(call_vsxseg_1848, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1848, 1, V); + setArg(call_vsxseg_1848, 2, vsxseg_1848_arg1); + setArg(call_vsxseg_1848, 3, vsxseg_1848_arg2); + setArg(call_vsxseg_1848, 4, vsxseg_1848_arg3); + setArg(call_vsxseg_1848, 5, vm); + setArg(call_vsxseg_1848, 6, vs3); + setArg(call_vsxseg_1848, 7, vsxseg_1848_arg6); + setArg(call_vsxseg_1848, 8, vs2); + setArg(call_vsxseg_1848, 9, 1); + setArg(call_vsxseg_1848, 10, 4); + setArg(call_vsxseg_1848, 11, vsxseg_1848_arg10); + setArg(call_vsxseg_1848, 12, 0); + setRet(call_vsxseg_1848, 0, ret_val_vsxseg_1848); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 483); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 484: VSUXEI64__V */ + continuation_e __vsuxei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXEI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 484); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1850; + x86::Gp ret_val_get_pow_1850 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1850, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1851; + x86::Gp ret_val_get_sew_pow_1851 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1851, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1852; + x86::Gp ret_val_get_lmul_pow_1852 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1852, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1850, ret_val_get_sew_pow_1851), ret_val_get_lmul_pow_1852)), 3, true); + setArg(call_get_pow_1850, 0, reinterpret_cast(this)); + setArg(call_get_pow_1850, 1, EEW); + setRet(call_get_pow_1850, 0, ret_val_get_pow_1850); + setArg(call_get_sew_pow_1851, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1851, 0, ret_val_get_sew_pow_1851); + setArg(call_get_lmul_pow_1852, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1852, 0, ret_val_get_lmul_pow_1852); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1854; + x86::Gp ret_val_get_lmul_pow_1854 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1854, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1853; + auto illegal_indexed_store_1853_arg2 = EMUL_pow; + auto illegal_indexed_store_1853_arg3 = ret_val_get_lmul_pow_1854; + x86::Gp ret_val_illegal_indexed_store_1853 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1853, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1853; + setArg(call_get_lmul_pow_1854, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1854, 0, ret_val_get_lmul_pow_1854); + setArg(call_illegal_indexed_store_1853, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1853, 1, 1); + setArg(call_illegal_indexed_store_1853, 2, EEW); + setArg(call_illegal_indexed_store_1853, 3, illegal_indexed_store_1853_arg2); + setArg(call_illegal_indexed_store_1853, 4, illegal_indexed_store_1853_arg3); + setRet(call_illegal_indexed_store_1853, 0, ret_val_illegal_indexed_store_1853); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1856; + x86::Gp ret_val_sew_1856 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1856, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1855; + auto vsxseg_1855_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1855_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1855_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1855_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1855_arg10 = ret_val_sew_1856; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1855 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1855, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1855, 64, false), traits::vstart); + setArg(call_sew_1856, 0, reinterpret_cast(this)); + setRet(call_sew_1856, 0, ret_val_sew_1856); + setArg(call_vsxseg_1855, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1855, 1, V); + setArg(call_vsxseg_1855, 2, vsxseg_1855_arg1); + setArg(call_vsxseg_1855, 3, vsxseg_1855_arg2); + setArg(call_vsxseg_1855, 4, vsxseg_1855_arg3); + setArg(call_vsxseg_1855, 5, vm); + setArg(call_vsxseg_1855, 6, vs3); + setArg(call_vsxseg_1855, 7, vsxseg_1855_arg6); + setArg(call_vsxseg_1855, 8, vs2); + setArg(call_vsxseg_1855, 9, 1); + setArg(call_vsxseg_1855, 10, 8); + setArg(call_vsxseg_1855, 11, vsxseg_1855_arg10); + setArg(call_vsxseg_1855, 12, 0); + setRet(call_vsxseg_1855, 0, ret_val_vsxseg_1855); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 484); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 485: VSUXSEG2EI8__V */ + continuation_e __vsuxseg2ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG2EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 485); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1857; + x86::Gp ret_val_get_pow_1857 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1857, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1858; + x86::Gp ret_val_get_sew_pow_1858 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1858, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1859; + x86::Gp ret_val_get_lmul_pow_1859 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1859, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1857, ret_val_get_sew_pow_1858), ret_val_get_lmul_pow_1859)), 3, true); + setArg(call_get_pow_1857, 0, reinterpret_cast(this)); + setArg(call_get_pow_1857, 1, EEW); + setRet(call_get_pow_1857, 0, ret_val_get_pow_1857); + setArg(call_get_sew_pow_1858, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1858, 0, ret_val_get_sew_pow_1858); + setArg(call_get_lmul_pow_1859, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1859, 0, ret_val_get_lmul_pow_1859); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1861; + x86::Gp ret_val_get_lmul_pow_1861 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1861, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1860; + auto illegal_indexed_store_1860_arg2 = EMUL_pow; + auto illegal_indexed_store_1860_arg3 = ret_val_get_lmul_pow_1861; + x86::Gp ret_val_illegal_indexed_store_1860 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1860, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1860; + setArg(call_get_lmul_pow_1861, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1861, 0, ret_val_get_lmul_pow_1861); + setArg(call_illegal_indexed_store_1860, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1860, 1, 2); + setArg(call_illegal_indexed_store_1860, 2, EEW); + setArg(call_illegal_indexed_store_1860, 3, illegal_indexed_store_1860_arg2); + setArg(call_illegal_indexed_store_1860, 4, illegal_indexed_store_1860_arg3); + setRet(call_illegal_indexed_store_1860, 0, ret_val_illegal_indexed_store_1860); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1863; + x86::Gp ret_val_sew_1863 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1863, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1862; + auto vsxseg_1862_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1862_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1862_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1862_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1862_arg10 = ret_val_sew_1863; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1862 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1862, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1862, 64, false), traits::vstart); + setArg(call_sew_1863, 0, reinterpret_cast(this)); + setRet(call_sew_1863, 0, ret_val_sew_1863); + setArg(call_vsxseg_1862, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1862, 1, V); + setArg(call_vsxseg_1862, 2, vsxseg_1862_arg1); + setArg(call_vsxseg_1862, 3, vsxseg_1862_arg2); + setArg(call_vsxseg_1862, 4, vsxseg_1862_arg3); + setArg(call_vsxseg_1862, 5, vm); + setArg(call_vsxseg_1862, 6, vs3); + setArg(call_vsxseg_1862, 7, vsxseg_1862_arg6); + setArg(call_vsxseg_1862, 8, vs2); + setArg(call_vsxseg_1862, 9, 2); + setArg(call_vsxseg_1862, 10, 1); + setArg(call_vsxseg_1862, 11, vsxseg_1862_arg10); + setArg(call_vsxseg_1862, 12, 0); + setRet(call_vsxseg_1862, 0, ret_val_vsxseg_1862); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 485); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 486: VSUXSEG2EI16__V */ + continuation_e __vsuxseg2ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG2EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 486); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1864; + x86::Gp ret_val_get_pow_1864 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1864, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1865; + x86::Gp ret_val_get_sew_pow_1865 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1865, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1866; + x86::Gp ret_val_get_lmul_pow_1866 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1866, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1864, ret_val_get_sew_pow_1865), ret_val_get_lmul_pow_1866)), 3, true); + setArg(call_get_pow_1864, 0, reinterpret_cast(this)); + setArg(call_get_pow_1864, 1, EEW); + setRet(call_get_pow_1864, 0, ret_val_get_pow_1864); + setArg(call_get_sew_pow_1865, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1865, 0, ret_val_get_sew_pow_1865); + setArg(call_get_lmul_pow_1866, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1866, 0, ret_val_get_lmul_pow_1866); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1868; + x86::Gp ret_val_get_lmul_pow_1868 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1868, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1867; + auto illegal_indexed_store_1867_arg2 = EMUL_pow; + auto illegal_indexed_store_1867_arg3 = ret_val_get_lmul_pow_1868; + x86::Gp ret_val_illegal_indexed_store_1867 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1867, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1867; + setArg(call_get_lmul_pow_1868, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1868, 0, ret_val_get_lmul_pow_1868); + setArg(call_illegal_indexed_store_1867, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1867, 1, 2); + setArg(call_illegal_indexed_store_1867, 2, EEW); + setArg(call_illegal_indexed_store_1867, 3, illegal_indexed_store_1867_arg2); + setArg(call_illegal_indexed_store_1867, 4, illegal_indexed_store_1867_arg3); + setRet(call_illegal_indexed_store_1867, 0, ret_val_illegal_indexed_store_1867); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1870; + x86::Gp ret_val_sew_1870 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1870, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1869; + auto vsxseg_1869_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1869_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1869_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1869_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1869_arg10 = ret_val_sew_1870; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1869 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1869, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1869, 64, false), traits::vstart); + setArg(call_sew_1870, 0, reinterpret_cast(this)); + setRet(call_sew_1870, 0, ret_val_sew_1870); + setArg(call_vsxseg_1869, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1869, 1, V); + setArg(call_vsxseg_1869, 2, vsxseg_1869_arg1); + setArg(call_vsxseg_1869, 3, vsxseg_1869_arg2); + setArg(call_vsxseg_1869, 4, vsxseg_1869_arg3); + setArg(call_vsxseg_1869, 5, vm); + setArg(call_vsxseg_1869, 6, vs3); + setArg(call_vsxseg_1869, 7, vsxseg_1869_arg6); + setArg(call_vsxseg_1869, 8, vs2); + setArg(call_vsxseg_1869, 9, 2); + setArg(call_vsxseg_1869, 10, 2); + setArg(call_vsxseg_1869, 11, vsxseg_1869_arg10); + setArg(call_vsxseg_1869, 12, 0); + setRet(call_vsxseg_1869, 0, ret_val_vsxseg_1869); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 486); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 487: VSUXSEG2EI32__V */ + continuation_e __vsuxseg2ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG2EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 487); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1871; + x86::Gp ret_val_get_pow_1871 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1871, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1872; + x86::Gp ret_val_get_sew_pow_1872 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1872, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1873; + x86::Gp ret_val_get_lmul_pow_1873 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1873, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1871, ret_val_get_sew_pow_1872), ret_val_get_lmul_pow_1873)), 3, true); + setArg(call_get_pow_1871, 0, reinterpret_cast(this)); + setArg(call_get_pow_1871, 1, EEW); + setRet(call_get_pow_1871, 0, ret_val_get_pow_1871); + setArg(call_get_sew_pow_1872, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1872, 0, ret_val_get_sew_pow_1872); + setArg(call_get_lmul_pow_1873, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1873, 0, ret_val_get_lmul_pow_1873); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1875; + x86::Gp ret_val_get_lmul_pow_1875 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1875, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1874; + auto illegal_indexed_store_1874_arg2 = EMUL_pow; + auto illegal_indexed_store_1874_arg3 = ret_val_get_lmul_pow_1875; + x86::Gp ret_val_illegal_indexed_store_1874 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1874, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1874; + setArg(call_get_lmul_pow_1875, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1875, 0, ret_val_get_lmul_pow_1875); + setArg(call_illegal_indexed_store_1874, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1874, 1, 2); + setArg(call_illegal_indexed_store_1874, 2, EEW); + setArg(call_illegal_indexed_store_1874, 3, illegal_indexed_store_1874_arg2); + setArg(call_illegal_indexed_store_1874, 4, illegal_indexed_store_1874_arg3); + setRet(call_illegal_indexed_store_1874, 0, ret_val_illegal_indexed_store_1874); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1877; + x86::Gp ret_val_sew_1877 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1877, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1876; + auto vsxseg_1876_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1876_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1876_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1876_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1876_arg10 = ret_val_sew_1877; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1876 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1876, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1876, 64, false), traits::vstart); + setArg(call_sew_1877, 0, reinterpret_cast(this)); + setRet(call_sew_1877, 0, ret_val_sew_1877); + setArg(call_vsxseg_1876, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1876, 1, V); + setArg(call_vsxseg_1876, 2, vsxseg_1876_arg1); + setArg(call_vsxseg_1876, 3, vsxseg_1876_arg2); + setArg(call_vsxseg_1876, 4, vsxseg_1876_arg3); + setArg(call_vsxseg_1876, 5, vm); + setArg(call_vsxseg_1876, 6, vs3); + setArg(call_vsxseg_1876, 7, vsxseg_1876_arg6); + setArg(call_vsxseg_1876, 8, vs2); + setArg(call_vsxseg_1876, 9, 2); + setArg(call_vsxseg_1876, 10, 4); + setArg(call_vsxseg_1876, 11, vsxseg_1876_arg10); + setArg(call_vsxseg_1876, 12, 0); + setRet(call_vsxseg_1876, 0, ret_val_vsxseg_1876); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 487); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 488: VSUXSEG2EI64__V */ + continuation_e __vsuxseg2ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg2ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG2EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 488); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1878; + x86::Gp ret_val_get_pow_1878 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1878, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1879; + x86::Gp ret_val_get_sew_pow_1879 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1879, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1880; + x86::Gp ret_val_get_lmul_pow_1880 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1880, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1878, ret_val_get_sew_pow_1879), ret_val_get_lmul_pow_1880)), 3, true); + setArg(call_get_pow_1878, 0, reinterpret_cast(this)); + setArg(call_get_pow_1878, 1, EEW); + setRet(call_get_pow_1878, 0, ret_val_get_pow_1878); + setArg(call_get_sew_pow_1879, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1879, 0, ret_val_get_sew_pow_1879); + setArg(call_get_lmul_pow_1880, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1880, 0, ret_val_get_lmul_pow_1880); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1882; + x86::Gp ret_val_get_lmul_pow_1882 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1882, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1881; + auto illegal_indexed_store_1881_arg2 = EMUL_pow; + auto illegal_indexed_store_1881_arg3 = ret_val_get_lmul_pow_1882; + x86::Gp ret_val_illegal_indexed_store_1881 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1881, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1881; + setArg(call_get_lmul_pow_1882, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1882, 0, ret_val_get_lmul_pow_1882); + setArg(call_illegal_indexed_store_1881, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1881, 1, 2); + setArg(call_illegal_indexed_store_1881, 2, EEW); + setArg(call_illegal_indexed_store_1881, 3, illegal_indexed_store_1881_arg2); + setArg(call_illegal_indexed_store_1881, 4, illegal_indexed_store_1881_arg3); + setRet(call_illegal_indexed_store_1881, 0, ret_val_illegal_indexed_store_1881); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1884; + x86::Gp ret_val_sew_1884 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1884, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1883; + auto vsxseg_1883_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1883_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1883_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1883_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1883_arg10 = ret_val_sew_1884; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1883 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1883, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1883, 64, false), traits::vstart); + setArg(call_sew_1884, 0, reinterpret_cast(this)); + setRet(call_sew_1884, 0, ret_val_sew_1884); + setArg(call_vsxseg_1883, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1883, 1, V); + setArg(call_vsxseg_1883, 2, vsxseg_1883_arg1); + setArg(call_vsxseg_1883, 3, vsxseg_1883_arg2); + setArg(call_vsxseg_1883, 4, vsxseg_1883_arg3); + setArg(call_vsxseg_1883, 5, vm); + setArg(call_vsxseg_1883, 6, vs3); + setArg(call_vsxseg_1883, 7, vsxseg_1883_arg6); + setArg(call_vsxseg_1883, 8, vs2); + setArg(call_vsxseg_1883, 9, 2); + setArg(call_vsxseg_1883, 10, 8); + setArg(call_vsxseg_1883, 11, vsxseg_1883_arg10); + setArg(call_vsxseg_1883, 12, 0); + setRet(call_vsxseg_1883, 0, ret_val_vsxseg_1883); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 488); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 489: VSUXSEG3EI8__V */ + continuation_e __vsuxseg3ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG3EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 489); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1885; + x86::Gp ret_val_get_pow_1885 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1885, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1886; + x86::Gp ret_val_get_sew_pow_1886 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1886, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1887; + x86::Gp ret_val_get_lmul_pow_1887 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1887, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1885, ret_val_get_sew_pow_1886), ret_val_get_lmul_pow_1887)), 3, true); + setArg(call_get_pow_1885, 0, reinterpret_cast(this)); + setArg(call_get_pow_1885, 1, EEW); + setRet(call_get_pow_1885, 0, ret_val_get_pow_1885); + setArg(call_get_sew_pow_1886, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1886, 0, ret_val_get_sew_pow_1886); + setArg(call_get_lmul_pow_1887, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1887, 0, ret_val_get_lmul_pow_1887); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1889; + x86::Gp ret_val_get_lmul_pow_1889 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1889, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1888; + auto illegal_indexed_store_1888_arg2 = EMUL_pow; + auto illegal_indexed_store_1888_arg3 = ret_val_get_lmul_pow_1889; + x86::Gp ret_val_illegal_indexed_store_1888 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1888, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1888; + setArg(call_get_lmul_pow_1889, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1889, 0, ret_val_get_lmul_pow_1889); + setArg(call_illegal_indexed_store_1888, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1888, 1, 3); + setArg(call_illegal_indexed_store_1888, 2, EEW); + setArg(call_illegal_indexed_store_1888, 3, illegal_indexed_store_1888_arg2); + setArg(call_illegal_indexed_store_1888, 4, illegal_indexed_store_1888_arg3); + setRet(call_illegal_indexed_store_1888, 0, ret_val_illegal_indexed_store_1888); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1891; + x86::Gp ret_val_sew_1891 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1891, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1890; + auto vsxseg_1890_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1890_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1890_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1890_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1890_arg10 = ret_val_sew_1891; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1890 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1890, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1890, 64, false), traits::vstart); + setArg(call_sew_1891, 0, reinterpret_cast(this)); + setRet(call_sew_1891, 0, ret_val_sew_1891); + setArg(call_vsxseg_1890, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1890, 1, V); + setArg(call_vsxseg_1890, 2, vsxseg_1890_arg1); + setArg(call_vsxseg_1890, 3, vsxseg_1890_arg2); + setArg(call_vsxseg_1890, 4, vsxseg_1890_arg3); + setArg(call_vsxseg_1890, 5, vm); + setArg(call_vsxseg_1890, 6, vs3); + setArg(call_vsxseg_1890, 7, vsxseg_1890_arg6); + setArg(call_vsxseg_1890, 8, vs2); + setArg(call_vsxseg_1890, 9, 3); + setArg(call_vsxseg_1890, 10, 1); + setArg(call_vsxseg_1890, 11, vsxseg_1890_arg10); + setArg(call_vsxseg_1890, 12, 0); + setRet(call_vsxseg_1890, 0, ret_val_vsxseg_1890); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 489); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 490: VSUXSEG3EI16__V */ + continuation_e __vsuxseg3ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG3EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 490); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1892; + x86::Gp ret_val_get_pow_1892 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1892, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1893; + x86::Gp ret_val_get_sew_pow_1893 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1893, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1894; + x86::Gp ret_val_get_lmul_pow_1894 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1894, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1892, ret_val_get_sew_pow_1893), ret_val_get_lmul_pow_1894)), 3, true); + setArg(call_get_pow_1892, 0, reinterpret_cast(this)); + setArg(call_get_pow_1892, 1, EEW); + setRet(call_get_pow_1892, 0, ret_val_get_pow_1892); + setArg(call_get_sew_pow_1893, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1893, 0, ret_val_get_sew_pow_1893); + setArg(call_get_lmul_pow_1894, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1894, 0, ret_val_get_lmul_pow_1894); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1896; + x86::Gp ret_val_get_lmul_pow_1896 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1896, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1895; + auto illegal_indexed_store_1895_arg2 = EMUL_pow; + auto illegal_indexed_store_1895_arg3 = ret_val_get_lmul_pow_1896; + x86::Gp ret_val_illegal_indexed_store_1895 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1895, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1895; + setArg(call_get_lmul_pow_1896, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1896, 0, ret_val_get_lmul_pow_1896); + setArg(call_illegal_indexed_store_1895, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1895, 1, 3); + setArg(call_illegal_indexed_store_1895, 2, EEW); + setArg(call_illegal_indexed_store_1895, 3, illegal_indexed_store_1895_arg2); + setArg(call_illegal_indexed_store_1895, 4, illegal_indexed_store_1895_arg3); + setRet(call_illegal_indexed_store_1895, 0, ret_val_illegal_indexed_store_1895); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1898; + x86::Gp ret_val_sew_1898 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1898, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1897; + auto vsxseg_1897_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1897_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1897_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1897_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1897_arg10 = ret_val_sew_1898; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1897 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1897, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1897, 64, false), traits::vstart); + setArg(call_sew_1898, 0, reinterpret_cast(this)); + setRet(call_sew_1898, 0, ret_val_sew_1898); + setArg(call_vsxseg_1897, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1897, 1, V); + setArg(call_vsxseg_1897, 2, vsxseg_1897_arg1); + setArg(call_vsxseg_1897, 3, vsxseg_1897_arg2); + setArg(call_vsxseg_1897, 4, vsxseg_1897_arg3); + setArg(call_vsxseg_1897, 5, vm); + setArg(call_vsxseg_1897, 6, vs3); + setArg(call_vsxseg_1897, 7, vsxseg_1897_arg6); + setArg(call_vsxseg_1897, 8, vs2); + setArg(call_vsxseg_1897, 9, 3); + setArg(call_vsxseg_1897, 10, 2); + setArg(call_vsxseg_1897, 11, vsxseg_1897_arg10); + setArg(call_vsxseg_1897, 12, 0); + setRet(call_vsxseg_1897, 0, ret_val_vsxseg_1897); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 490); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 491: VSUXSEG3EI32__V */ + continuation_e __vsuxseg3ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG3EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 491); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1899; + x86::Gp ret_val_get_pow_1899 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1899, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1900; + x86::Gp ret_val_get_sew_pow_1900 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1900, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1901; + x86::Gp ret_val_get_lmul_pow_1901 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1901, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1899, ret_val_get_sew_pow_1900), ret_val_get_lmul_pow_1901)), 3, true); + setArg(call_get_pow_1899, 0, reinterpret_cast(this)); + setArg(call_get_pow_1899, 1, EEW); + setRet(call_get_pow_1899, 0, ret_val_get_pow_1899); + setArg(call_get_sew_pow_1900, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1900, 0, ret_val_get_sew_pow_1900); + setArg(call_get_lmul_pow_1901, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1901, 0, ret_val_get_lmul_pow_1901); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1903; + x86::Gp ret_val_get_lmul_pow_1903 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1903, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1902; + auto illegal_indexed_store_1902_arg2 = EMUL_pow; + auto illegal_indexed_store_1902_arg3 = ret_val_get_lmul_pow_1903; + x86::Gp ret_val_illegal_indexed_store_1902 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1902, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1902; + setArg(call_get_lmul_pow_1903, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1903, 0, ret_val_get_lmul_pow_1903); + setArg(call_illegal_indexed_store_1902, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1902, 1, 3); + setArg(call_illegal_indexed_store_1902, 2, EEW); + setArg(call_illegal_indexed_store_1902, 3, illegal_indexed_store_1902_arg2); + setArg(call_illegal_indexed_store_1902, 4, illegal_indexed_store_1902_arg3); + setRet(call_illegal_indexed_store_1902, 0, ret_val_illegal_indexed_store_1902); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1905; + x86::Gp ret_val_sew_1905 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1905, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1904; + auto vsxseg_1904_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1904_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1904_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1904_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1904_arg10 = ret_val_sew_1905; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1904 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1904, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1904, 64, false), traits::vstart); + setArg(call_sew_1905, 0, reinterpret_cast(this)); + setRet(call_sew_1905, 0, ret_val_sew_1905); + setArg(call_vsxseg_1904, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1904, 1, V); + setArg(call_vsxseg_1904, 2, vsxseg_1904_arg1); + setArg(call_vsxseg_1904, 3, vsxseg_1904_arg2); + setArg(call_vsxseg_1904, 4, vsxseg_1904_arg3); + setArg(call_vsxseg_1904, 5, vm); + setArg(call_vsxseg_1904, 6, vs3); + setArg(call_vsxseg_1904, 7, vsxseg_1904_arg6); + setArg(call_vsxseg_1904, 8, vs2); + setArg(call_vsxseg_1904, 9, 3); + setArg(call_vsxseg_1904, 10, 4); + setArg(call_vsxseg_1904, 11, vsxseg_1904_arg10); + setArg(call_vsxseg_1904, 12, 0); + setRet(call_vsxseg_1904, 0, ret_val_vsxseg_1904); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 491); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 492: VSUXSEG3EI64__V */ + continuation_e __vsuxseg3ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg3ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG3EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 492); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1906; + x86::Gp ret_val_get_pow_1906 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1906, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1907; + x86::Gp ret_val_get_sew_pow_1907 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1907, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1908; + x86::Gp ret_val_get_lmul_pow_1908 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1908, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1906, ret_val_get_sew_pow_1907), ret_val_get_lmul_pow_1908)), 3, true); + setArg(call_get_pow_1906, 0, reinterpret_cast(this)); + setArg(call_get_pow_1906, 1, EEW); + setRet(call_get_pow_1906, 0, ret_val_get_pow_1906); + setArg(call_get_sew_pow_1907, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1907, 0, ret_val_get_sew_pow_1907); + setArg(call_get_lmul_pow_1908, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1908, 0, ret_val_get_lmul_pow_1908); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1910; + x86::Gp ret_val_get_lmul_pow_1910 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1910, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1909; + auto illegal_indexed_store_1909_arg2 = EMUL_pow; + auto illegal_indexed_store_1909_arg3 = ret_val_get_lmul_pow_1910; + x86::Gp ret_val_illegal_indexed_store_1909 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1909, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1909; + setArg(call_get_lmul_pow_1910, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1910, 0, ret_val_get_lmul_pow_1910); + setArg(call_illegal_indexed_store_1909, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1909, 1, 3); + setArg(call_illegal_indexed_store_1909, 2, EEW); + setArg(call_illegal_indexed_store_1909, 3, illegal_indexed_store_1909_arg2); + setArg(call_illegal_indexed_store_1909, 4, illegal_indexed_store_1909_arg3); + setRet(call_illegal_indexed_store_1909, 0, ret_val_illegal_indexed_store_1909); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1912; + x86::Gp ret_val_sew_1912 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1912, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1911; + auto vsxseg_1911_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1911_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1911_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1911_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1911_arg10 = ret_val_sew_1912; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1911 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1911, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1911, 64, false), traits::vstart); + setArg(call_sew_1912, 0, reinterpret_cast(this)); + setRet(call_sew_1912, 0, ret_val_sew_1912); + setArg(call_vsxseg_1911, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1911, 1, V); + setArg(call_vsxseg_1911, 2, vsxseg_1911_arg1); + setArg(call_vsxseg_1911, 3, vsxseg_1911_arg2); + setArg(call_vsxseg_1911, 4, vsxseg_1911_arg3); + setArg(call_vsxseg_1911, 5, vm); + setArg(call_vsxseg_1911, 6, vs3); + setArg(call_vsxseg_1911, 7, vsxseg_1911_arg6); + setArg(call_vsxseg_1911, 8, vs2); + setArg(call_vsxseg_1911, 9, 3); + setArg(call_vsxseg_1911, 10, 8); + setArg(call_vsxseg_1911, 11, vsxseg_1911_arg10); + setArg(call_vsxseg_1911, 12, 0); + setRet(call_vsxseg_1911, 0, ret_val_vsxseg_1911); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 492); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 493: VSUXSEG4EI8__V */ + continuation_e __vsuxseg4ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG4EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 493); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1913; + x86::Gp ret_val_get_pow_1913 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1913, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1914; + x86::Gp ret_val_get_sew_pow_1914 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1914, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1915; + x86::Gp ret_val_get_lmul_pow_1915 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1915, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1913, ret_val_get_sew_pow_1914), ret_val_get_lmul_pow_1915)), 3, true); + setArg(call_get_pow_1913, 0, reinterpret_cast(this)); + setArg(call_get_pow_1913, 1, EEW); + setRet(call_get_pow_1913, 0, ret_val_get_pow_1913); + setArg(call_get_sew_pow_1914, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1914, 0, ret_val_get_sew_pow_1914); + setArg(call_get_lmul_pow_1915, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1915, 0, ret_val_get_lmul_pow_1915); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1917; + x86::Gp ret_val_get_lmul_pow_1917 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1917, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1916; + auto illegal_indexed_store_1916_arg2 = EMUL_pow; + auto illegal_indexed_store_1916_arg3 = ret_val_get_lmul_pow_1917; + x86::Gp ret_val_illegal_indexed_store_1916 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1916, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1916; + setArg(call_get_lmul_pow_1917, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1917, 0, ret_val_get_lmul_pow_1917); + setArg(call_illegal_indexed_store_1916, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1916, 1, 4); + setArg(call_illegal_indexed_store_1916, 2, EEW); + setArg(call_illegal_indexed_store_1916, 3, illegal_indexed_store_1916_arg2); + setArg(call_illegal_indexed_store_1916, 4, illegal_indexed_store_1916_arg3); + setRet(call_illegal_indexed_store_1916, 0, ret_val_illegal_indexed_store_1916); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1919; + x86::Gp ret_val_sew_1919 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1919, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1918; + auto vsxseg_1918_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1918_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1918_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1918_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1918_arg10 = ret_val_sew_1919; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1918 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1918, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1918, 64, false), traits::vstart); + setArg(call_sew_1919, 0, reinterpret_cast(this)); + setRet(call_sew_1919, 0, ret_val_sew_1919); + setArg(call_vsxseg_1918, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1918, 1, V); + setArg(call_vsxseg_1918, 2, vsxseg_1918_arg1); + setArg(call_vsxseg_1918, 3, vsxseg_1918_arg2); + setArg(call_vsxseg_1918, 4, vsxseg_1918_arg3); + setArg(call_vsxseg_1918, 5, vm); + setArg(call_vsxseg_1918, 6, vs3); + setArg(call_vsxseg_1918, 7, vsxseg_1918_arg6); + setArg(call_vsxseg_1918, 8, vs2); + setArg(call_vsxseg_1918, 9, 4); + setArg(call_vsxseg_1918, 10, 1); + setArg(call_vsxseg_1918, 11, vsxseg_1918_arg10); + setArg(call_vsxseg_1918, 12, 0); + setRet(call_vsxseg_1918, 0, ret_val_vsxseg_1918); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 493); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 494: VSUXSEG4EI16__V */ + continuation_e __vsuxseg4ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG4EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 494); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1920; + x86::Gp ret_val_get_pow_1920 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1920, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1921; + x86::Gp ret_val_get_sew_pow_1921 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1921, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1922; + x86::Gp ret_val_get_lmul_pow_1922 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1922, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1920, ret_val_get_sew_pow_1921), ret_val_get_lmul_pow_1922)), 3, true); + setArg(call_get_pow_1920, 0, reinterpret_cast(this)); + setArg(call_get_pow_1920, 1, EEW); + setRet(call_get_pow_1920, 0, ret_val_get_pow_1920); + setArg(call_get_sew_pow_1921, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1921, 0, ret_val_get_sew_pow_1921); + setArg(call_get_lmul_pow_1922, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1922, 0, ret_val_get_lmul_pow_1922); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1924; + x86::Gp ret_val_get_lmul_pow_1924 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1924, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1923; + auto illegal_indexed_store_1923_arg2 = EMUL_pow; + auto illegal_indexed_store_1923_arg3 = ret_val_get_lmul_pow_1924; + x86::Gp ret_val_illegal_indexed_store_1923 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1923, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1923; + setArg(call_get_lmul_pow_1924, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1924, 0, ret_val_get_lmul_pow_1924); + setArg(call_illegal_indexed_store_1923, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1923, 1, 4); + setArg(call_illegal_indexed_store_1923, 2, EEW); + setArg(call_illegal_indexed_store_1923, 3, illegal_indexed_store_1923_arg2); + setArg(call_illegal_indexed_store_1923, 4, illegal_indexed_store_1923_arg3); + setRet(call_illegal_indexed_store_1923, 0, ret_val_illegal_indexed_store_1923); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1926; + x86::Gp ret_val_sew_1926 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1926, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1925; + auto vsxseg_1925_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1925_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1925_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1925_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1925_arg10 = ret_val_sew_1926; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1925 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1925, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1925, 64, false), traits::vstart); + setArg(call_sew_1926, 0, reinterpret_cast(this)); + setRet(call_sew_1926, 0, ret_val_sew_1926); + setArg(call_vsxseg_1925, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1925, 1, V); + setArg(call_vsxseg_1925, 2, vsxseg_1925_arg1); + setArg(call_vsxseg_1925, 3, vsxseg_1925_arg2); + setArg(call_vsxseg_1925, 4, vsxseg_1925_arg3); + setArg(call_vsxseg_1925, 5, vm); + setArg(call_vsxseg_1925, 6, vs3); + setArg(call_vsxseg_1925, 7, vsxseg_1925_arg6); + setArg(call_vsxseg_1925, 8, vs2); + setArg(call_vsxseg_1925, 9, 4); + setArg(call_vsxseg_1925, 10, 2); + setArg(call_vsxseg_1925, 11, vsxseg_1925_arg10); + setArg(call_vsxseg_1925, 12, 0); + setRet(call_vsxseg_1925, 0, ret_val_vsxseg_1925); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 494); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 495: VSUXSEG4EI32__V */ + continuation_e __vsuxseg4ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG4EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 495); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1927; + x86::Gp ret_val_get_pow_1927 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1927, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1928; + x86::Gp ret_val_get_sew_pow_1928 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1928, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1929; + x86::Gp ret_val_get_lmul_pow_1929 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1929, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1927, ret_val_get_sew_pow_1928), ret_val_get_lmul_pow_1929)), 3, true); + setArg(call_get_pow_1927, 0, reinterpret_cast(this)); + setArg(call_get_pow_1927, 1, EEW); + setRet(call_get_pow_1927, 0, ret_val_get_pow_1927); + setArg(call_get_sew_pow_1928, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1928, 0, ret_val_get_sew_pow_1928); + setArg(call_get_lmul_pow_1929, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1929, 0, ret_val_get_lmul_pow_1929); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1931; + x86::Gp ret_val_get_lmul_pow_1931 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1931, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1930; + auto illegal_indexed_store_1930_arg2 = EMUL_pow; + auto illegal_indexed_store_1930_arg3 = ret_val_get_lmul_pow_1931; + x86::Gp ret_val_illegal_indexed_store_1930 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1930, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1930; + setArg(call_get_lmul_pow_1931, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1931, 0, ret_val_get_lmul_pow_1931); + setArg(call_illegal_indexed_store_1930, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1930, 1, 4); + setArg(call_illegal_indexed_store_1930, 2, EEW); + setArg(call_illegal_indexed_store_1930, 3, illegal_indexed_store_1930_arg2); + setArg(call_illegal_indexed_store_1930, 4, illegal_indexed_store_1930_arg3); + setRet(call_illegal_indexed_store_1930, 0, ret_val_illegal_indexed_store_1930); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1933; + x86::Gp ret_val_sew_1933 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1933, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1932; + auto vsxseg_1932_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1932_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1932_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1932_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1932_arg10 = ret_val_sew_1933; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1932 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1932, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1932, 64, false), traits::vstart); + setArg(call_sew_1933, 0, reinterpret_cast(this)); + setRet(call_sew_1933, 0, ret_val_sew_1933); + setArg(call_vsxseg_1932, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1932, 1, V); + setArg(call_vsxseg_1932, 2, vsxseg_1932_arg1); + setArg(call_vsxseg_1932, 3, vsxseg_1932_arg2); + setArg(call_vsxseg_1932, 4, vsxseg_1932_arg3); + setArg(call_vsxseg_1932, 5, vm); + setArg(call_vsxseg_1932, 6, vs3); + setArg(call_vsxseg_1932, 7, vsxseg_1932_arg6); + setArg(call_vsxseg_1932, 8, vs2); + setArg(call_vsxseg_1932, 9, 4); + setArg(call_vsxseg_1932, 10, 4); + setArg(call_vsxseg_1932, 11, vsxseg_1932_arg10); + setArg(call_vsxseg_1932, 12, 0); + setRet(call_vsxseg_1932, 0, ret_val_vsxseg_1932); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 495); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 496: VSUXSEG4EI64__V */ + continuation_e __vsuxseg4ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg4ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG4EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 496); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1934; + x86::Gp ret_val_get_pow_1934 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1934, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1935; + x86::Gp ret_val_get_sew_pow_1935 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1935, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1936; + x86::Gp ret_val_get_lmul_pow_1936 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1936, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1934, ret_val_get_sew_pow_1935), ret_val_get_lmul_pow_1936)), 3, true); + setArg(call_get_pow_1934, 0, reinterpret_cast(this)); + setArg(call_get_pow_1934, 1, EEW); + setRet(call_get_pow_1934, 0, ret_val_get_pow_1934); + setArg(call_get_sew_pow_1935, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1935, 0, ret_val_get_sew_pow_1935); + setArg(call_get_lmul_pow_1936, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1936, 0, ret_val_get_lmul_pow_1936); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1938; + x86::Gp ret_val_get_lmul_pow_1938 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1938, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1937; + auto illegal_indexed_store_1937_arg2 = EMUL_pow; + auto illegal_indexed_store_1937_arg3 = ret_val_get_lmul_pow_1938; + x86::Gp ret_val_illegal_indexed_store_1937 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1937, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1937; + setArg(call_get_lmul_pow_1938, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1938, 0, ret_val_get_lmul_pow_1938); + setArg(call_illegal_indexed_store_1937, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1937, 1, 4); + setArg(call_illegal_indexed_store_1937, 2, EEW); + setArg(call_illegal_indexed_store_1937, 3, illegal_indexed_store_1937_arg2); + setArg(call_illegal_indexed_store_1937, 4, illegal_indexed_store_1937_arg3); + setRet(call_illegal_indexed_store_1937, 0, ret_val_illegal_indexed_store_1937); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1940; + x86::Gp ret_val_sew_1940 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1940, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1939; + auto vsxseg_1939_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1939_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1939_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1939_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1939_arg10 = ret_val_sew_1940; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1939 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1939, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1939, 64, false), traits::vstart); + setArg(call_sew_1940, 0, reinterpret_cast(this)); + setRet(call_sew_1940, 0, ret_val_sew_1940); + setArg(call_vsxseg_1939, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1939, 1, V); + setArg(call_vsxseg_1939, 2, vsxseg_1939_arg1); + setArg(call_vsxseg_1939, 3, vsxseg_1939_arg2); + setArg(call_vsxseg_1939, 4, vsxseg_1939_arg3); + setArg(call_vsxseg_1939, 5, vm); + setArg(call_vsxseg_1939, 6, vs3); + setArg(call_vsxseg_1939, 7, vsxseg_1939_arg6); + setArg(call_vsxseg_1939, 8, vs2); + setArg(call_vsxseg_1939, 9, 4); + setArg(call_vsxseg_1939, 10, 8); + setArg(call_vsxseg_1939, 11, vsxseg_1939_arg10); + setArg(call_vsxseg_1939, 12, 0); + setRet(call_vsxseg_1939, 0, ret_val_vsxseg_1939); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 496); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 497: VSUXSEG5EI8__V */ + continuation_e __vsuxseg5ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG5EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 497); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1941; + x86::Gp ret_val_get_pow_1941 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1941, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1942; + x86::Gp ret_val_get_sew_pow_1942 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1942, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1943; + x86::Gp ret_val_get_lmul_pow_1943 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1943, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1941, ret_val_get_sew_pow_1942), ret_val_get_lmul_pow_1943)), 3, true); + setArg(call_get_pow_1941, 0, reinterpret_cast(this)); + setArg(call_get_pow_1941, 1, EEW); + setRet(call_get_pow_1941, 0, ret_val_get_pow_1941); + setArg(call_get_sew_pow_1942, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1942, 0, ret_val_get_sew_pow_1942); + setArg(call_get_lmul_pow_1943, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1943, 0, ret_val_get_lmul_pow_1943); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1945; + x86::Gp ret_val_get_lmul_pow_1945 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1945, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1944; + auto illegal_indexed_store_1944_arg2 = EMUL_pow; + auto illegal_indexed_store_1944_arg3 = ret_val_get_lmul_pow_1945; + x86::Gp ret_val_illegal_indexed_store_1944 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1944, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1944; + setArg(call_get_lmul_pow_1945, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1945, 0, ret_val_get_lmul_pow_1945); + setArg(call_illegal_indexed_store_1944, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1944, 1, 5); + setArg(call_illegal_indexed_store_1944, 2, EEW); + setArg(call_illegal_indexed_store_1944, 3, illegal_indexed_store_1944_arg2); + setArg(call_illegal_indexed_store_1944, 4, illegal_indexed_store_1944_arg3); + setRet(call_illegal_indexed_store_1944, 0, ret_val_illegal_indexed_store_1944); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1947; + x86::Gp ret_val_sew_1947 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1947, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1946; + auto vsxseg_1946_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1946_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1946_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1946_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1946_arg10 = ret_val_sew_1947; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1946 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1946, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1946, 64, false), traits::vstart); + setArg(call_sew_1947, 0, reinterpret_cast(this)); + setRet(call_sew_1947, 0, ret_val_sew_1947); + setArg(call_vsxseg_1946, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1946, 1, V); + setArg(call_vsxseg_1946, 2, vsxseg_1946_arg1); + setArg(call_vsxseg_1946, 3, vsxseg_1946_arg2); + setArg(call_vsxseg_1946, 4, vsxseg_1946_arg3); + setArg(call_vsxseg_1946, 5, vm); + setArg(call_vsxseg_1946, 6, vs3); + setArg(call_vsxseg_1946, 7, vsxseg_1946_arg6); + setArg(call_vsxseg_1946, 8, vs2); + setArg(call_vsxseg_1946, 9, 5); + setArg(call_vsxseg_1946, 10, 1); + setArg(call_vsxseg_1946, 11, vsxseg_1946_arg10); + setArg(call_vsxseg_1946, 12, 0); + setRet(call_vsxseg_1946, 0, ret_val_vsxseg_1946); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 497); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 498: VSUXSEG5EI16__V */ + continuation_e __vsuxseg5ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG5EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 498); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1948; + x86::Gp ret_val_get_pow_1948 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1948, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1949; + x86::Gp ret_val_get_sew_pow_1949 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1949, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1950; + x86::Gp ret_val_get_lmul_pow_1950 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1950, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1948, ret_val_get_sew_pow_1949), ret_val_get_lmul_pow_1950)), 3, true); + setArg(call_get_pow_1948, 0, reinterpret_cast(this)); + setArg(call_get_pow_1948, 1, EEW); + setRet(call_get_pow_1948, 0, ret_val_get_pow_1948); + setArg(call_get_sew_pow_1949, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1949, 0, ret_val_get_sew_pow_1949); + setArg(call_get_lmul_pow_1950, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1950, 0, ret_val_get_lmul_pow_1950); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1952; + x86::Gp ret_val_get_lmul_pow_1952 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1952, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1951; + auto illegal_indexed_store_1951_arg2 = EMUL_pow; + auto illegal_indexed_store_1951_arg3 = ret_val_get_lmul_pow_1952; + x86::Gp ret_val_illegal_indexed_store_1951 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1951, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1951; + setArg(call_get_lmul_pow_1952, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1952, 0, ret_val_get_lmul_pow_1952); + setArg(call_illegal_indexed_store_1951, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1951, 1, 5); + setArg(call_illegal_indexed_store_1951, 2, EEW); + setArg(call_illegal_indexed_store_1951, 3, illegal_indexed_store_1951_arg2); + setArg(call_illegal_indexed_store_1951, 4, illegal_indexed_store_1951_arg3); + setRet(call_illegal_indexed_store_1951, 0, ret_val_illegal_indexed_store_1951); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1954; + x86::Gp ret_val_sew_1954 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1954, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1953; + auto vsxseg_1953_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1953_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1953_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1953_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1953_arg10 = ret_val_sew_1954; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1953 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1953, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1953, 64, false), traits::vstart); + setArg(call_sew_1954, 0, reinterpret_cast(this)); + setRet(call_sew_1954, 0, ret_val_sew_1954); + setArg(call_vsxseg_1953, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1953, 1, V); + setArg(call_vsxseg_1953, 2, vsxseg_1953_arg1); + setArg(call_vsxseg_1953, 3, vsxseg_1953_arg2); + setArg(call_vsxseg_1953, 4, vsxseg_1953_arg3); + setArg(call_vsxseg_1953, 5, vm); + setArg(call_vsxseg_1953, 6, vs3); + setArg(call_vsxseg_1953, 7, vsxseg_1953_arg6); + setArg(call_vsxseg_1953, 8, vs2); + setArg(call_vsxseg_1953, 9, 5); + setArg(call_vsxseg_1953, 10, 2); + setArg(call_vsxseg_1953, 11, vsxseg_1953_arg10); + setArg(call_vsxseg_1953, 12, 0); + setRet(call_vsxseg_1953, 0, ret_val_vsxseg_1953); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 498); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 499: VSUXSEG5EI32__V */ + continuation_e __vsuxseg5ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG5EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 499); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1955; + x86::Gp ret_val_get_pow_1955 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1955, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1956; + x86::Gp ret_val_get_sew_pow_1956 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1956, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1957; + x86::Gp ret_val_get_lmul_pow_1957 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1957, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1955, ret_val_get_sew_pow_1956), ret_val_get_lmul_pow_1957)), 3, true); + setArg(call_get_pow_1955, 0, reinterpret_cast(this)); + setArg(call_get_pow_1955, 1, EEW); + setRet(call_get_pow_1955, 0, ret_val_get_pow_1955); + setArg(call_get_sew_pow_1956, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1956, 0, ret_val_get_sew_pow_1956); + setArg(call_get_lmul_pow_1957, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1957, 0, ret_val_get_lmul_pow_1957); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1959; + x86::Gp ret_val_get_lmul_pow_1959 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1959, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1958; + auto illegal_indexed_store_1958_arg2 = EMUL_pow; + auto illegal_indexed_store_1958_arg3 = ret_val_get_lmul_pow_1959; + x86::Gp ret_val_illegal_indexed_store_1958 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1958, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1958; + setArg(call_get_lmul_pow_1959, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1959, 0, ret_val_get_lmul_pow_1959); + setArg(call_illegal_indexed_store_1958, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1958, 1, 5); + setArg(call_illegal_indexed_store_1958, 2, EEW); + setArg(call_illegal_indexed_store_1958, 3, illegal_indexed_store_1958_arg2); + setArg(call_illegal_indexed_store_1958, 4, illegal_indexed_store_1958_arg3); + setRet(call_illegal_indexed_store_1958, 0, ret_val_illegal_indexed_store_1958); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1961; + x86::Gp ret_val_sew_1961 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1961, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1960; + auto vsxseg_1960_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1960_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1960_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1960_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1960_arg10 = ret_val_sew_1961; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1960 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1960, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1960, 64, false), traits::vstart); + setArg(call_sew_1961, 0, reinterpret_cast(this)); + setRet(call_sew_1961, 0, ret_val_sew_1961); + setArg(call_vsxseg_1960, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1960, 1, V); + setArg(call_vsxseg_1960, 2, vsxseg_1960_arg1); + setArg(call_vsxseg_1960, 3, vsxseg_1960_arg2); + setArg(call_vsxseg_1960, 4, vsxseg_1960_arg3); + setArg(call_vsxseg_1960, 5, vm); + setArg(call_vsxseg_1960, 6, vs3); + setArg(call_vsxseg_1960, 7, vsxseg_1960_arg6); + setArg(call_vsxseg_1960, 8, vs2); + setArg(call_vsxseg_1960, 9, 5); + setArg(call_vsxseg_1960, 10, 4); + setArg(call_vsxseg_1960, 11, vsxseg_1960_arg10); + setArg(call_vsxseg_1960, 12, 0); + setRet(call_vsxseg_1960, 0, ret_val_vsxseg_1960); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 499); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 500: VSUXSEG5EI64__V */ + continuation_e __vsuxseg5ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg5ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG5EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 500); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1962; + x86::Gp ret_val_get_pow_1962 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1962, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1963; + x86::Gp ret_val_get_sew_pow_1963 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1963, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1964; + x86::Gp ret_val_get_lmul_pow_1964 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1964, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1962, ret_val_get_sew_pow_1963), ret_val_get_lmul_pow_1964)), 3, true); + setArg(call_get_pow_1962, 0, reinterpret_cast(this)); + setArg(call_get_pow_1962, 1, EEW); + setRet(call_get_pow_1962, 0, ret_val_get_pow_1962); + setArg(call_get_sew_pow_1963, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1963, 0, ret_val_get_sew_pow_1963); + setArg(call_get_lmul_pow_1964, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1964, 0, ret_val_get_lmul_pow_1964); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1966; + x86::Gp ret_val_get_lmul_pow_1966 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1966, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1965; + auto illegal_indexed_store_1965_arg2 = EMUL_pow; + auto illegal_indexed_store_1965_arg3 = ret_val_get_lmul_pow_1966; + x86::Gp ret_val_illegal_indexed_store_1965 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1965, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1965; + setArg(call_get_lmul_pow_1966, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1966, 0, ret_val_get_lmul_pow_1966); + setArg(call_illegal_indexed_store_1965, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1965, 1, 5); + setArg(call_illegal_indexed_store_1965, 2, EEW); + setArg(call_illegal_indexed_store_1965, 3, illegal_indexed_store_1965_arg2); + setArg(call_illegal_indexed_store_1965, 4, illegal_indexed_store_1965_arg3); + setRet(call_illegal_indexed_store_1965, 0, ret_val_illegal_indexed_store_1965); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1968; + x86::Gp ret_val_sew_1968 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1968, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1967; + auto vsxseg_1967_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1967_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1967_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1967_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1967_arg10 = ret_val_sew_1968; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1967 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1967, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1967, 64, false), traits::vstart); + setArg(call_sew_1968, 0, reinterpret_cast(this)); + setRet(call_sew_1968, 0, ret_val_sew_1968); + setArg(call_vsxseg_1967, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1967, 1, V); + setArg(call_vsxseg_1967, 2, vsxseg_1967_arg1); + setArg(call_vsxseg_1967, 3, vsxseg_1967_arg2); + setArg(call_vsxseg_1967, 4, vsxseg_1967_arg3); + setArg(call_vsxseg_1967, 5, vm); + setArg(call_vsxseg_1967, 6, vs3); + setArg(call_vsxseg_1967, 7, vsxseg_1967_arg6); + setArg(call_vsxseg_1967, 8, vs2); + setArg(call_vsxseg_1967, 9, 5); + setArg(call_vsxseg_1967, 10, 8); + setArg(call_vsxseg_1967, 11, vsxseg_1967_arg10); + setArg(call_vsxseg_1967, 12, 0); + setRet(call_vsxseg_1967, 0, ret_val_vsxseg_1967); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 500); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 501: VSUXSEG6EI8__V */ + continuation_e __vsuxseg6ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG6EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 501); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1969; + x86::Gp ret_val_get_pow_1969 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1969, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1970; + x86::Gp ret_val_get_sew_pow_1970 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1970, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1971; + x86::Gp ret_val_get_lmul_pow_1971 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1971, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1969, ret_val_get_sew_pow_1970), ret_val_get_lmul_pow_1971)), 3, true); + setArg(call_get_pow_1969, 0, reinterpret_cast(this)); + setArg(call_get_pow_1969, 1, EEW); + setRet(call_get_pow_1969, 0, ret_val_get_pow_1969); + setArg(call_get_sew_pow_1970, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1970, 0, ret_val_get_sew_pow_1970); + setArg(call_get_lmul_pow_1971, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1971, 0, ret_val_get_lmul_pow_1971); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1973; + x86::Gp ret_val_get_lmul_pow_1973 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1973, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1972; + auto illegal_indexed_store_1972_arg2 = EMUL_pow; + auto illegal_indexed_store_1972_arg3 = ret_val_get_lmul_pow_1973; + x86::Gp ret_val_illegal_indexed_store_1972 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1972, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1972; + setArg(call_get_lmul_pow_1973, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1973, 0, ret_val_get_lmul_pow_1973); + setArg(call_illegal_indexed_store_1972, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1972, 1, 6); + setArg(call_illegal_indexed_store_1972, 2, EEW); + setArg(call_illegal_indexed_store_1972, 3, illegal_indexed_store_1972_arg2); + setArg(call_illegal_indexed_store_1972, 4, illegal_indexed_store_1972_arg3); + setRet(call_illegal_indexed_store_1972, 0, ret_val_illegal_indexed_store_1972); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1975; + x86::Gp ret_val_sew_1975 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1975, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1974; + auto vsxseg_1974_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1974_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1974_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1974_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1974_arg10 = ret_val_sew_1975; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1974 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1974, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1974, 64, false), traits::vstart); + setArg(call_sew_1975, 0, reinterpret_cast(this)); + setRet(call_sew_1975, 0, ret_val_sew_1975); + setArg(call_vsxseg_1974, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1974, 1, V); + setArg(call_vsxseg_1974, 2, vsxseg_1974_arg1); + setArg(call_vsxseg_1974, 3, vsxseg_1974_arg2); + setArg(call_vsxseg_1974, 4, vsxseg_1974_arg3); + setArg(call_vsxseg_1974, 5, vm); + setArg(call_vsxseg_1974, 6, vs3); + setArg(call_vsxseg_1974, 7, vsxseg_1974_arg6); + setArg(call_vsxseg_1974, 8, vs2); + setArg(call_vsxseg_1974, 9, 6); + setArg(call_vsxseg_1974, 10, 1); + setArg(call_vsxseg_1974, 11, vsxseg_1974_arg10); + setArg(call_vsxseg_1974, 12, 0); + setRet(call_vsxseg_1974, 0, ret_val_vsxseg_1974); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 501); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 502: VSUXSEG6EI16__V */ + continuation_e __vsuxseg6ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG6EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 502); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_1976; + x86::Gp ret_val_get_pow_1976 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1976, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1977; + x86::Gp ret_val_get_sew_pow_1977 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1977, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1978; + x86::Gp ret_val_get_lmul_pow_1978 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1978, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1976, ret_val_get_sew_pow_1977), ret_val_get_lmul_pow_1978)), 3, true); + setArg(call_get_pow_1976, 0, reinterpret_cast(this)); + setArg(call_get_pow_1976, 1, EEW); + setRet(call_get_pow_1976, 0, ret_val_get_pow_1976); + setArg(call_get_sew_pow_1977, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1977, 0, ret_val_get_sew_pow_1977); + setArg(call_get_lmul_pow_1978, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1978, 0, ret_val_get_lmul_pow_1978); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1980; + x86::Gp ret_val_get_lmul_pow_1980 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1980, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1979; + auto illegal_indexed_store_1979_arg2 = EMUL_pow; + auto illegal_indexed_store_1979_arg3 = ret_val_get_lmul_pow_1980; + x86::Gp ret_val_illegal_indexed_store_1979 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1979, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1979; + setArg(call_get_lmul_pow_1980, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1980, 0, ret_val_get_lmul_pow_1980); + setArg(call_illegal_indexed_store_1979, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1979, 1, 6); + setArg(call_illegal_indexed_store_1979, 2, EEW); + setArg(call_illegal_indexed_store_1979, 3, illegal_indexed_store_1979_arg2); + setArg(call_illegal_indexed_store_1979, 4, illegal_indexed_store_1979_arg3); + setRet(call_illegal_indexed_store_1979, 0, ret_val_illegal_indexed_store_1979); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1982; + x86::Gp ret_val_sew_1982 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1982, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1981; + auto vsxseg_1981_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1981_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1981_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1981_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1981_arg10 = ret_val_sew_1982; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1981 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1981, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1981, 64, false), traits::vstart); + setArg(call_sew_1982, 0, reinterpret_cast(this)); + setRet(call_sew_1982, 0, ret_val_sew_1982); + setArg(call_vsxseg_1981, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1981, 1, V); + setArg(call_vsxseg_1981, 2, vsxseg_1981_arg1); + setArg(call_vsxseg_1981, 3, vsxseg_1981_arg2); + setArg(call_vsxseg_1981, 4, vsxseg_1981_arg3); + setArg(call_vsxseg_1981, 5, vm); + setArg(call_vsxseg_1981, 6, vs3); + setArg(call_vsxseg_1981, 7, vsxseg_1981_arg6); + setArg(call_vsxseg_1981, 8, vs2); + setArg(call_vsxseg_1981, 9, 6); + setArg(call_vsxseg_1981, 10, 2); + setArg(call_vsxseg_1981, 11, vsxseg_1981_arg10); + setArg(call_vsxseg_1981, 12, 0); + setRet(call_vsxseg_1981, 0, ret_val_vsxseg_1981); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 502); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 503: VSUXSEG6EI32__V */ + continuation_e __vsuxseg6ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG6EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 503); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_1983; + x86::Gp ret_val_get_pow_1983 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1983, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1984; + x86::Gp ret_val_get_sew_pow_1984 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1984, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1985; + x86::Gp ret_val_get_lmul_pow_1985 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1985, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1983, ret_val_get_sew_pow_1984), ret_val_get_lmul_pow_1985)), 3, true); + setArg(call_get_pow_1983, 0, reinterpret_cast(this)); + setArg(call_get_pow_1983, 1, EEW); + setRet(call_get_pow_1983, 0, ret_val_get_pow_1983); + setArg(call_get_sew_pow_1984, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1984, 0, ret_val_get_sew_pow_1984); + setArg(call_get_lmul_pow_1985, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1985, 0, ret_val_get_lmul_pow_1985); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1987; + x86::Gp ret_val_get_lmul_pow_1987 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1987, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1986; + auto illegal_indexed_store_1986_arg2 = EMUL_pow; + auto illegal_indexed_store_1986_arg3 = ret_val_get_lmul_pow_1987; + x86::Gp ret_val_illegal_indexed_store_1986 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1986, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1986; + setArg(call_get_lmul_pow_1987, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1987, 0, ret_val_get_lmul_pow_1987); + setArg(call_illegal_indexed_store_1986, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1986, 1, 6); + setArg(call_illegal_indexed_store_1986, 2, EEW); + setArg(call_illegal_indexed_store_1986, 3, illegal_indexed_store_1986_arg2); + setArg(call_illegal_indexed_store_1986, 4, illegal_indexed_store_1986_arg3); + setRet(call_illegal_indexed_store_1986, 0, ret_val_illegal_indexed_store_1986); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1989; + x86::Gp ret_val_sew_1989 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1989, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1988; + auto vsxseg_1988_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1988_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1988_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1988_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1988_arg10 = ret_val_sew_1989; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1988 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1988, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1988, 64, false), traits::vstart); + setArg(call_sew_1989, 0, reinterpret_cast(this)); + setRet(call_sew_1989, 0, ret_val_sew_1989); + setArg(call_vsxseg_1988, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1988, 1, V); + setArg(call_vsxseg_1988, 2, vsxseg_1988_arg1); + setArg(call_vsxseg_1988, 3, vsxseg_1988_arg2); + setArg(call_vsxseg_1988, 4, vsxseg_1988_arg3); + setArg(call_vsxseg_1988, 5, vm); + setArg(call_vsxseg_1988, 6, vs3); + setArg(call_vsxseg_1988, 7, vsxseg_1988_arg6); + setArg(call_vsxseg_1988, 8, vs2); + setArg(call_vsxseg_1988, 9, 6); + setArg(call_vsxseg_1988, 10, 4); + setArg(call_vsxseg_1988, 11, vsxseg_1988_arg10); + setArg(call_vsxseg_1988, 12, 0); + setRet(call_vsxseg_1988, 0, ret_val_vsxseg_1988); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 503); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 504: VSUXSEG6EI64__V */ + continuation_e __vsuxseg6ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg6ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG6EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 504); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_1990; + x86::Gp ret_val_get_pow_1990 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1990, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1991; + x86::Gp ret_val_get_sew_pow_1991 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1991, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1992; + x86::Gp ret_val_get_lmul_pow_1992 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1992, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1990, ret_val_get_sew_pow_1991), ret_val_get_lmul_pow_1992)), 3, true); + setArg(call_get_pow_1990, 0, reinterpret_cast(this)); + setArg(call_get_pow_1990, 1, EEW); + setRet(call_get_pow_1990, 0, ret_val_get_pow_1990); + setArg(call_get_sew_pow_1991, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1991, 0, ret_val_get_sew_pow_1991); + setArg(call_get_lmul_pow_1992, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1992, 0, ret_val_get_lmul_pow_1992); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_1994; + x86::Gp ret_val_get_lmul_pow_1994 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1994, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_1993; + auto illegal_indexed_store_1993_arg2 = EMUL_pow; + auto illegal_indexed_store_1993_arg3 = ret_val_get_lmul_pow_1994; + x86::Gp ret_val_illegal_indexed_store_1993 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_1993, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_1993; + setArg(call_get_lmul_pow_1994, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1994, 0, ret_val_get_lmul_pow_1994); + setArg(call_illegal_indexed_store_1993, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_1993, 1, 6); + setArg(call_illegal_indexed_store_1993, 2, EEW); + setArg(call_illegal_indexed_store_1993, 3, illegal_indexed_store_1993_arg2); + setArg(call_illegal_indexed_store_1993, 4, illegal_indexed_store_1993_arg3); + setRet(call_illegal_indexed_store_1993, 0, ret_val_illegal_indexed_store_1993); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_1996; + x86::Gp ret_val_sew_1996 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_1996, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_1995; + auto vsxseg_1995_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_1995_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_1995_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_1995_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_1995_arg10 = ret_val_sew_1996; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_1995 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_1995, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_1995, 64, false), traits::vstart); + setArg(call_sew_1996, 0, reinterpret_cast(this)); + setRet(call_sew_1996, 0, ret_val_sew_1996); + setArg(call_vsxseg_1995, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_1995, 1, V); + setArg(call_vsxseg_1995, 2, vsxseg_1995_arg1); + setArg(call_vsxseg_1995, 3, vsxseg_1995_arg2); + setArg(call_vsxseg_1995, 4, vsxseg_1995_arg3); + setArg(call_vsxseg_1995, 5, vm); + setArg(call_vsxseg_1995, 6, vs3); + setArg(call_vsxseg_1995, 7, vsxseg_1995_arg6); + setArg(call_vsxseg_1995, 8, vs2); + setArg(call_vsxseg_1995, 9, 6); + setArg(call_vsxseg_1995, 10, 8); + setArg(call_vsxseg_1995, 11, vsxseg_1995_arg10); + setArg(call_vsxseg_1995, 12, 0); + setRet(call_vsxseg_1995, 0, ret_val_vsxseg_1995); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 504); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 505: VSUXSEG7EI8__V */ + continuation_e __vsuxseg7ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG7EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 505); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_1997; + x86::Gp ret_val_get_pow_1997 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_1997, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_1998; + x86::Gp ret_val_get_sew_pow_1998 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_1998, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_1999; + x86::Gp ret_val_get_lmul_pow_1999 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_1999, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1997, ret_val_get_sew_pow_1998), ret_val_get_lmul_pow_1999)), 3, true); + setArg(call_get_pow_1997, 0, reinterpret_cast(this)); + setArg(call_get_pow_1997, 1, EEW); + setRet(call_get_pow_1997, 0, ret_val_get_pow_1997); + setArg(call_get_sew_pow_1998, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_1998, 0, ret_val_get_sew_pow_1998); + setArg(call_get_lmul_pow_1999, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_1999, 0, ret_val_get_lmul_pow_1999); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2001; + x86::Gp ret_val_get_lmul_pow_2001 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2001, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_2000; + auto illegal_indexed_store_2000_arg2 = EMUL_pow; + auto illegal_indexed_store_2000_arg3 = ret_val_get_lmul_pow_2001; + x86::Gp ret_val_illegal_indexed_store_2000 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_2000, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_2000; + setArg(call_get_lmul_pow_2001, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2001, 0, ret_val_get_lmul_pow_2001); + setArg(call_illegal_indexed_store_2000, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_2000, 1, 7); + setArg(call_illegal_indexed_store_2000, 2, EEW); + setArg(call_illegal_indexed_store_2000, 3, illegal_indexed_store_2000_arg2); + setArg(call_illegal_indexed_store_2000, 4, illegal_indexed_store_2000_arg3); + setRet(call_illegal_indexed_store_2000, 0, ret_val_illegal_indexed_store_2000); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2003; + x86::Gp ret_val_sew_2003 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2003, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2002; + auto vsxseg_2002_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2002_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2002_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2002_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2002_arg10 = ret_val_sew_2003; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2002 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2002, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2002, 64, false), traits::vstart); + setArg(call_sew_2003, 0, reinterpret_cast(this)); + setRet(call_sew_2003, 0, ret_val_sew_2003); + setArg(call_vsxseg_2002, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2002, 1, V); + setArg(call_vsxseg_2002, 2, vsxseg_2002_arg1); + setArg(call_vsxseg_2002, 3, vsxseg_2002_arg2); + setArg(call_vsxseg_2002, 4, vsxseg_2002_arg3); + setArg(call_vsxseg_2002, 5, vm); + setArg(call_vsxseg_2002, 6, vs3); + setArg(call_vsxseg_2002, 7, vsxseg_2002_arg6); + setArg(call_vsxseg_2002, 8, vs2); + setArg(call_vsxseg_2002, 9, 7); + setArg(call_vsxseg_2002, 10, 1); + setArg(call_vsxseg_2002, 11, vsxseg_2002_arg10); + setArg(call_vsxseg_2002, 12, 0); + setRet(call_vsxseg_2002, 0, ret_val_vsxseg_2002); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 505); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 506: VSUXSEG7EI16__V */ + continuation_e __vsuxseg7ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG7EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 506); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_2004; + x86::Gp ret_val_get_pow_2004 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_2004, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_2005; + x86::Gp ret_val_get_sew_pow_2005 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2005, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_2006; + x86::Gp ret_val_get_lmul_pow_2006 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2006, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2004, ret_val_get_sew_pow_2005), ret_val_get_lmul_pow_2006)), 3, true); + setArg(call_get_pow_2004, 0, reinterpret_cast(this)); + setArg(call_get_pow_2004, 1, EEW); + setRet(call_get_pow_2004, 0, ret_val_get_pow_2004); + setArg(call_get_sew_pow_2005, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2005, 0, ret_val_get_sew_pow_2005); + setArg(call_get_lmul_pow_2006, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2006, 0, ret_val_get_lmul_pow_2006); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2008; + x86::Gp ret_val_get_lmul_pow_2008 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2008, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_2007; + auto illegal_indexed_store_2007_arg2 = EMUL_pow; + auto illegal_indexed_store_2007_arg3 = ret_val_get_lmul_pow_2008; + x86::Gp ret_val_illegal_indexed_store_2007 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_2007, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_2007; + setArg(call_get_lmul_pow_2008, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2008, 0, ret_val_get_lmul_pow_2008); + setArg(call_illegal_indexed_store_2007, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_2007, 1, 7); + setArg(call_illegal_indexed_store_2007, 2, EEW); + setArg(call_illegal_indexed_store_2007, 3, illegal_indexed_store_2007_arg2); + setArg(call_illegal_indexed_store_2007, 4, illegal_indexed_store_2007_arg3); + setRet(call_illegal_indexed_store_2007, 0, ret_val_illegal_indexed_store_2007); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2010; + x86::Gp ret_val_sew_2010 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2010, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2009; + auto vsxseg_2009_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2009_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2009_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2009_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2009_arg10 = ret_val_sew_2010; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2009 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2009, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2009, 64, false), traits::vstart); + setArg(call_sew_2010, 0, reinterpret_cast(this)); + setRet(call_sew_2010, 0, ret_val_sew_2010); + setArg(call_vsxseg_2009, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2009, 1, V); + setArg(call_vsxseg_2009, 2, vsxseg_2009_arg1); + setArg(call_vsxseg_2009, 3, vsxseg_2009_arg2); + setArg(call_vsxseg_2009, 4, vsxseg_2009_arg3); + setArg(call_vsxseg_2009, 5, vm); + setArg(call_vsxseg_2009, 6, vs3); + setArg(call_vsxseg_2009, 7, vsxseg_2009_arg6); + setArg(call_vsxseg_2009, 8, vs2); + setArg(call_vsxseg_2009, 9, 7); + setArg(call_vsxseg_2009, 10, 2); + setArg(call_vsxseg_2009, 11, vsxseg_2009_arg10); + setArg(call_vsxseg_2009, 12, 0); + setRet(call_vsxseg_2009, 0, ret_val_vsxseg_2009); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 506); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 507: VSUXSEG7EI32__V */ + continuation_e __vsuxseg7ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG7EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 507); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_2011; + x86::Gp ret_val_get_pow_2011 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_2011, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_2012; + x86::Gp ret_val_get_sew_pow_2012 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2012, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_2013; + x86::Gp ret_val_get_lmul_pow_2013 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2013, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2011, ret_val_get_sew_pow_2012), ret_val_get_lmul_pow_2013)), 3, true); + setArg(call_get_pow_2011, 0, reinterpret_cast(this)); + setArg(call_get_pow_2011, 1, EEW); + setRet(call_get_pow_2011, 0, ret_val_get_pow_2011); + setArg(call_get_sew_pow_2012, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2012, 0, ret_val_get_sew_pow_2012); + setArg(call_get_lmul_pow_2013, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2013, 0, ret_val_get_lmul_pow_2013); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2015; + x86::Gp ret_val_get_lmul_pow_2015 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2015, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_2014; + auto illegal_indexed_store_2014_arg2 = EMUL_pow; + auto illegal_indexed_store_2014_arg3 = ret_val_get_lmul_pow_2015; + x86::Gp ret_val_illegal_indexed_store_2014 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_2014, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_2014; + setArg(call_get_lmul_pow_2015, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2015, 0, ret_val_get_lmul_pow_2015); + setArg(call_illegal_indexed_store_2014, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_2014, 1, 7); + setArg(call_illegal_indexed_store_2014, 2, EEW); + setArg(call_illegal_indexed_store_2014, 3, illegal_indexed_store_2014_arg2); + setArg(call_illegal_indexed_store_2014, 4, illegal_indexed_store_2014_arg3); + setRet(call_illegal_indexed_store_2014, 0, ret_val_illegal_indexed_store_2014); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2017; + x86::Gp ret_val_sew_2017 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2017, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2016; + auto vsxseg_2016_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2016_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2016_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2016_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2016_arg10 = ret_val_sew_2017; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2016 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2016, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2016, 64, false), traits::vstart); + setArg(call_sew_2017, 0, reinterpret_cast(this)); + setRet(call_sew_2017, 0, ret_val_sew_2017); + setArg(call_vsxseg_2016, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2016, 1, V); + setArg(call_vsxseg_2016, 2, vsxseg_2016_arg1); + setArg(call_vsxseg_2016, 3, vsxseg_2016_arg2); + setArg(call_vsxseg_2016, 4, vsxseg_2016_arg3); + setArg(call_vsxseg_2016, 5, vm); + setArg(call_vsxseg_2016, 6, vs3); + setArg(call_vsxseg_2016, 7, vsxseg_2016_arg6); + setArg(call_vsxseg_2016, 8, vs2); + setArg(call_vsxseg_2016, 9, 7); + setArg(call_vsxseg_2016, 10, 4); + setArg(call_vsxseg_2016, 11, vsxseg_2016_arg10); + setArg(call_vsxseg_2016, 12, 0); + setRet(call_vsxseg_2016, 0, ret_val_vsxseg_2016); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 507); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 508: VSUXSEG7EI64__V */ + continuation_e __vsuxseg7ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg7ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG7EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 508); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_2018; + x86::Gp ret_val_get_pow_2018 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_2018, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_2019; + x86::Gp ret_val_get_sew_pow_2019 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2019, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_2020; + x86::Gp ret_val_get_lmul_pow_2020 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2020, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2018, ret_val_get_sew_pow_2019), ret_val_get_lmul_pow_2020)), 3, true); + setArg(call_get_pow_2018, 0, reinterpret_cast(this)); + setArg(call_get_pow_2018, 1, EEW); + setRet(call_get_pow_2018, 0, ret_val_get_pow_2018); + setArg(call_get_sew_pow_2019, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2019, 0, ret_val_get_sew_pow_2019); + setArg(call_get_lmul_pow_2020, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2020, 0, ret_val_get_lmul_pow_2020); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2022; + x86::Gp ret_val_get_lmul_pow_2022 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2022, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_2021; + auto illegal_indexed_store_2021_arg2 = EMUL_pow; + auto illegal_indexed_store_2021_arg3 = ret_val_get_lmul_pow_2022; + x86::Gp ret_val_illegal_indexed_store_2021 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_2021, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_2021; + setArg(call_get_lmul_pow_2022, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2022, 0, ret_val_get_lmul_pow_2022); + setArg(call_illegal_indexed_store_2021, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_2021, 1, 7); + setArg(call_illegal_indexed_store_2021, 2, EEW); + setArg(call_illegal_indexed_store_2021, 3, illegal_indexed_store_2021_arg2); + setArg(call_illegal_indexed_store_2021, 4, illegal_indexed_store_2021_arg3); + setRet(call_illegal_indexed_store_2021, 0, ret_val_illegal_indexed_store_2021); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2024; + x86::Gp ret_val_sew_2024 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2024, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2023; + auto vsxseg_2023_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2023_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2023_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2023_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2023_arg10 = ret_val_sew_2024; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2023 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2023, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2023, 64, false), traits::vstart); + setArg(call_sew_2024, 0, reinterpret_cast(this)); + setRet(call_sew_2024, 0, ret_val_sew_2024); + setArg(call_vsxseg_2023, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2023, 1, V); + setArg(call_vsxseg_2023, 2, vsxseg_2023_arg1); + setArg(call_vsxseg_2023, 3, vsxseg_2023_arg2); + setArg(call_vsxseg_2023, 4, vsxseg_2023_arg3); + setArg(call_vsxseg_2023, 5, vm); + setArg(call_vsxseg_2023, 6, vs3); + setArg(call_vsxseg_2023, 7, vsxseg_2023_arg6); + setArg(call_vsxseg_2023, 8, vs2); + setArg(call_vsxseg_2023, 9, 7); + setArg(call_vsxseg_2023, 10, 8); + setArg(call_vsxseg_2023, 11, vsxseg_2023_arg10); + setArg(call_vsxseg_2023, 12, 0); + setRet(call_vsxseg_2023, 0, ret_val_vsxseg_2023); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 508); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 509: VSUXSEG8EI8__V */ + continuation_e __vsuxseg8ei8__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei8.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG8EI8__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 509); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 8; + InvokeNode* call_get_pow_2025; + x86::Gp ret_val_get_pow_2025 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_2025, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_2026; + x86::Gp ret_val_get_sew_pow_2026 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2026, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_2027; + x86::Gp ret_val_get_lmul_pow_2027 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2027, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2025, ret_val_get_sew_pow_2026), ret_val_get_lmul_pow_2027)), 3, true); + setArg(call_get_pow_2025, 0, reinterpret_cast(this)); + setArg(call_get_pow_2025, 1, EEW); + setRet(call_get_pow_2025, 0, ret_val_get_pow_2025); + setArg(call_get_sew_pow_2026, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2026, 0, ret_val_get_sew_pow_2026); + setArg(call_get_lmul_pow_2027, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2027, 0, ret_val_get_lmul_pow_2027); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2029; + x86::Gp ret_val_get_lmul_pow_2029 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2029, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_2028; + auto illegal_indexed_store_2028_arg2 = EMUL_pow; + auto illegal_indexed_store_2028_arg3 = ret_val_get_lmul_pow_2029; + x86::Gp ret_val_illegal_indexed_store_2028 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_2028, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_2028; + setArg(call_get_lmul_pow_2029, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2029, 0, ret_val_get_lmul_pow_2029); + setArg(call_illegal_indexed_store_2028, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_2028, 1, 8); + setArg(call_illegal_indexed_store_2028, 2, EEW); + setArg(call_illegal_indexed_store_2028, 3, illegal_indexed_store_2028_arg2); + setArg(call_illegal_indexed_store_2028, 4, illegal_indexed_store_2028_arg3); + setRet(call_illegal_indexed_store_2028, 0, ret_val_illegal_indexed_store_2028); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2031; + x86::Gp ret_val_sew_2031 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2031, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2030; + auto vsxseg_2030_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2030_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2030_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2030_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2030_arg10 = ret_val_sew_2031; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2030 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2030, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2030, 64, false), traits::vstart); + setArg(call_sew_2031, 0, reinterpret_cast(this)); + setRet(call_sew_2031, 0, ret_val_sew_2031); + setArg(call_vsxseg_2030, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2030, 1, V); + setArg(call_vsxseg_2030, 2, vsxseg_2030_arg1); + setArg(call_vsxseg_2030, 3, vsxseg_2030_arg2); + setArg(call_vsxseg_2030, 4, vsxseg_2030_arg3); + setArg(call_vsxseg_2030, 5, vm); + setArg(call_vsxseg_2030, 6, vs3); + setArg(call_vsxseg_2030, 7, vsxseg_2030_arg6); + setArg(call_vsxseg_2030, 8, vs2); + setArg(call_vsxseg_2030, 9, 8); + setArg(call_vsxseg_2030, 10, 1); + setArg(call_vsxseg_2030, 11, vsxseg_2030_arg10); + setArg(call_vsxseg_2030, 12, 0); + setRet(call_vsxseg_2030, 0, ret_val_vsxseg_2030); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 509); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 510: VSUXSEG8EI16__V */ + continuation_e __vsuxseg8ei16__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei16.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG8EI16__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 510); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 16; + InvokeNode* call_get_pow_2032; + x86::Gp ret_val_get_pow_2032 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_2032, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_2033; + x86::Gp ret_val_get_sew_pow_2033 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2033, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_2034; + x86::Gp ret_val_get_lmul_pow_2034 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2034, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2032, ret_val_get_sew_pow_2033), ret_val_get_lmul_pow_2034)), 3, true); + setArg(call_get_pow_2032, 0, reinterpret_cast(this)); + setArg(call_get_pow_2032, 1, EEW); + setRet(call_get_pow_2032, 0, ret_val_get_pow_2032); + setArg(call_get_sew_pow_2033, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2033, 0, ret_val_get_sew_pow_2033); + setArg(call_get_lmul_pow_2034, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2034, 0, ret_val_get_lmul_pow_2034); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2036; + x86::Gp ret_val_get_lmul_pow_2036 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2036, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_2035; + auto illegal_indexed_store_2035_arg2 = EMUL_pow; + auto illegal_indexed_store_2035_arg3 = ret_val_get_lmul_pow_2036; + x86::Gp ret_val_illegal_indexed_store_2035 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_2035, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_2035; + setArg(call_get_lmul_pow_2036, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2036, 0, ret_val_get_lmul_pow_2036); + setArg(call_illegal_indexed_store_2035, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_2035, 1, 8); + setArg(call_illegal_indexed_store_2035, 2, EEW); + setArg(call_illegal_indexed_store_2035, 3, illegal_indexed_store_2035_arg2); + setArg(call_illegal_indexed_store_2035, 4, illegal_indexed_store_2035_arg3); + setRet(call_illegal_indexed_store_2035, 0, ret_val_illegal_indexed_store_2035); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2038; + x86::Gp ret_val_sew_2038 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2038, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2037; + auto vsxseg_2037_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2037_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2037_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2037_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2037_arg10 = ret_val_sew_2038; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2037 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2037, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2037, 64, false), traits::vstart); + setArg(call_sew_2038, 0, reinterpret_cast(this)); + setRet(call_sew_2038, 0, ret_val_sew_2038); + setArg(call_vsxseg_2037, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2037, 1, V); + setArg(call_vsxseg_2037, 2, vsxseg_2037_arg1); + setArg(call_vsxseg_2037, 3, vsxseg_2037_arg2); + setArg(call_vsxseg_2037, 4, vsxseg_2037_arg3); + setArg(call_vsxseg_2037, 5, vm); + setArg(call_vsxseg_2037, 6, vs3); + setArg(call_vsxseg_2037, 7, vsxseg_2037_arg6); + setArg(call_vsxseg_2037, 8, vs2); + setArg(call_vsxseg_2037, 9, 8); + setArg(call_vsxseg_2037, 10, 2); + setArg(call_vsxseg_2037, 11, vsxseg_2037_arg10); + setArg(call_vsxseg_2037, 12, 0); + setRet(call_vsxseg_2037, 0, ret_val_vsxseg_2037); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 510); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 511: VSUXSEG8EI32__V */ + continuation_e __vsuxseg8ei32__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei32.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG8EI32__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 511); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 32; + InvokeNode* call_get_pow_2039; + x86::Gp ret_val_get_pow_2039 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_2039, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_2040; + x86::Gp ret_val_get_sew_pow_2040 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2040, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_2041; + x86::Gp ret_val_get_lmul_pow_2041 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2041, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2039, ret_val_get_sew_pow_2040), ret_val_get_lmul_pow_2041)), 3, true); + setArg(call_get_pow_2039, 0, reinterpret_cast(this)); + setArg(call_get_pow_2039, 1, EEW); + setRet(call_get_pow_2039, 0, ret_val_get_pow_2039); + setArg(call_get_sew_pow_2040, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2040, 0, ret_val_get_sew_pow_2040); + setArg(call_get_lmul_pow_2041, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2041, 0, ret_val_get_lmul_pow_2041); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2043; + x86::Gp ret_val_get_lmul_pow_2043 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2043, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_2042; + auto illegal_indexed_store_2042_arg2 = EMUL_pow; + auto illegal_indexed_store_2042_arg3 = ret_val_get_lmul_pow_2043; + x86::Gp ret_val_illegal_indexed_store_2042 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_2042, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_2042; + setArg(call_get_lmul_pow_2043, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2043, 0, ret_val_get_lmul_pow_2043); + setArg(call_illegal_indexed_store_2042, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_2042, 1, 8); + setArg(call_illegal_indexed_store_2042, 2, EEW); + setArg(call_illegal_indexed_store_2042, 3, illegal_indexed_store_2042_arg2); + setArg(call_illegal_indexed_store_2042, 4, illegal_indexed_store_2042_arg3); + setRet(call_illegal_indexed_store_2042, 0, ret_val_illegal_indexed_store_2042); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2045; + x86::Gp ret_val_sew_2045 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2045, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2044; + auto vsxseg_2044_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2044_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2044_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2044_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2044_arg10 = ret_val_sew_2045; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2044 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2044, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2044, 64, false), traits::vstart); + setArg(call_sew_2045, 0, reinterpret_cast(this)); + setRet(call_sew_2045, 0, ret_val_sew_2045); + setArg(call_vsxseg_2044, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2044, 1, V); + setArg(call_vsxseg_2044, 2, vsxseg_2044_arg1); + setArg(call_vsxseg_2044, 3, vsxseg_2044_arg2); + setArg(call_vsxseg_2044, 4, vsxseg_2044_arg3); + setArg(call_vsxseg_2044, 5, vm); + setArg(call_vsxseg_2044, 6, vs3); + setArg(call_vsxseg_2044, 7, vsxseg_2044_arg6); + setArg(call_vsxseg_2044, 8, vs2); + setArg(call_vsxseg_2044, 9, 8); + setArg(call_vsxseg_2044, 10, 4); + setArg(call_vsxseg_2044, 11, vsxseg_2044_arg10); + setArg(call_vsxseg_2044, 12, 0); + setRet(call_vsxseg_2044, 0, ret_val_vsxseg_2044); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 511); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 512: VSUXSEG8EI64__V */ + continuation_e __vsuxseg8ei64__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vs3 = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + uint8_t mew = ((bit_sub<28,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vs3}, ({rs1}), {vs2}, {vm}", fmt::arg("mnemonic", "vsuxseg8ei64.v"), + fmt::arg("vs3", vname(vs3)), fmt::arg("rs1", name(rs1)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUXSEG8EI64__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 512); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + auto EEW = 64; + InvokeNode* call_get_pow_2046; + x86::Gp ret_val_get_pow_2046 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_pow_2046, (uintptr_t)&vm_impl::_get_pow, FuncSignature::build()); + InvokeNode* call_get_sew_pow_2047; + x86::Gp ret_val_get_sew_pow_2047 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2047, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + InvokeNode* call_get_lmul_pow_2048; + x86::Gp ret_val_get_lmul_pow_2048 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2048, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto EMUL_pow = gen_ext(cc, + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2046, ret_val_get_sew_pow_2047), ret_val_get_lmul_pow_2048)), 3, true); + setArg(call_get_pow_2046, 0, reinterpret_cast(this)); + setArg(call_get_pow_2046, 1, EEW); + setRet(call_get_pow_2046, 0, ret_val_get_pow_2046); + setArg(call_get_sew_pow_2047, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2047, 0, ret_val_get_sew_pow_2047); + setArg(call_get_lmul_pow_2048, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2048, 0, ret_val_get_lmul_pow_2048); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_get_lmul_pow_2050; + x86::Gp ret_val_get_lmul_pow_2050 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2050, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + InvokeNode* call_illegal_indexed_store_2049; + auto illegal_indexed_store_2049_arg2 = EMUL_pow; + auto illegal_indexed_store_2049_arg3 = ret_val_get_lmul_pow_2050; + x86::Gp ret_val_illegal_indexed_store_2049 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_indexed_store_2049, (uintptr_t)&vm_impl::_illegal_indexed_store, FuncSignature::build()); + auto cond = ret_val_illegal_indexed_store_2049; + setArg(call_get_lmul_pow_2050, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2050, 0, ret_val_get_lmul_pow_2050); + setArg(call_illegal_indexed_store_2049, 0, reinterpret_cast(this)); + setArg(call_illegal_indexed_store_2049, 1, 8); + setArg(call_illegal_indexed_store_2049, 2, EEW); + setArg(call_illegal_indexed_store_2049, 3, illegal_indexed_store_2049_arg2); + setArg(call_illegal_indexed_store_2049, 4, illegal_indexed_store_2049_arg3); + setRet(call_illegal_indexed_store_2049, 0, ret_val_illegal_indexed_store_2049); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2052; + x86::Gp ret_val_sew_2052 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2052, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vsxseg_2051; + auto vsxseg_2051_arg1 = load_reg_from_mem(jh, traits::vl); + auto vsxseg_2051_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vsxseg_2051_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vsxseg_2051_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vsxseg_2051_arg10 = ret_val_sew_2052; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vsxseg_2051 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vsxseg_2051, &vsxseg, FuncSignature::build()); + write_reg_to_mem(jh, gen_ext(cc, + ret_val_vsxseg_2051, 64, false), traits::vstart); + setArg(call_sew_2052, 0, reinterpret_cast(this)); + setRet(call_sew_2052, 0, ret_val_sew_2052); + setArg(call_vsxseg_2051, 0, reinterpret_cast(this->get_arch())); + setArg(call_vsxseg_2051, 1, V); + setArg(call_vsxseg_2051, 2, vsxseg_2051_arg1); + setArg(call_vsxseg_2051, 3, vsxseg_2051_arg2); + setArg(call_vsxseg_2051, 4, vsxseg_2051_arg3); + setArg(call_vsxseg_2051, 5, vm); + setArg(call_vsxseg_2051, 6, vs3); + setArg(call_vsxseg_2051, 7, vsxseg_2051_arg6); + setArg(call_vsxseg_2051, 8, vs2); + setArg(call_vsxseg_2051, 9, 8); + setArg(call_vsxseg_2051, 10, 8); + setArg(call_vsxseg_2051, 11, vsxseg_2051_arg10); + setArg(call_vsxseg_2051, 12, 0); + setRet(call_vsxseg_2051, 0, ret_val_vsxseg_2051); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 512); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 513: VADD__VI */ + continuation_e __vadd__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vadd.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADD__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 513); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2053; + x86::Gp ret_val_illegal_normal_2053 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2053, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2053; + setArg(call_illegal_normal_2053, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2053, 1, vd); + setArg(call_illegal_normal_2053, 2, vm); + setRet(call_illegal_normal_2053, 0, ret_val_illegal_normal_2053); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2055; + x86::Gp ret_val_sew_2055 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2055, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2054; + auto vector_imm_op_2054_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2054_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2054_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2054_arg10 = ret_val_sew_2055; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2054, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2055, 0, reinterpret_cast(this)); + setRet(call_sew_2055, 0, ret_val_sew_2055); + setArg(call_vector_imm_op_2054, 0, V); + setArg(call_vector_imm_op_2054, 1, 0); + setArg(call_vector_imm_op_2054, 2, 3); + setArg(call_vector_imm_op_2054, 3, vector_imm_op_2054_arg3); + setArg(call_vector_imm_op_2054, 4, vector_imm_op_2054_arg4); + setArg(call_vector_imm_op_2054, 5, vector_imm_op_2054_arg5); + setArg(call_vector_imm_op_2054, 6, vm); + setArg(call_vector_imm_op_2054, 7, vd); + setArg(call_vector_imm_op_2054, 8, vs2); + setArg(call_vector_imm_op_2054, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_op_2054, 10, vector_imm_op_2054_arg10); + } + cc.bind(label_merge); + } + auto tmp2056 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2056, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2056, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 513); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 514: VADD__VV */ + continuation_e __vadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 514); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2057; + x86::Gp ret_val_illegal_normal_2057 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2057, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2057; + setArg(call_illegal_normal_2057, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2057, 1, vd); + setArg(call_illegal_normal_2057, 2, vm); + setRet(call_illegal_normal_2057, 0, ret_val_illegal_normal_2057); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2059; + x86::Gp ret_val_sew_2059 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2059, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2058; + auto vector_vector_op_2058_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2058_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2058_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2058_arg10 = ret_val_sew_2059; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2058, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2059, 0, reinterpret_cast(this)); + setRet(call_sew_2059, 0, ret_val_sew_2059); + setArg(call_vector_vector_op_2058, 0, V); + setArg(call_vector_vector_op_2058, 1, 0); + setArg(call_vector_vector_op_2058, 2, 0); + setArg(call_vector_vector_op_2058, 3, vector_vector_op_2058_arg3); + setArg(call_vector_vector_op_2058, 4, vector_vector_op_2058_arg4); + setArg(call_vector_vector_op_2058, 5, vector_vector_op_2058_arg5); + setArg(call_vector_vector_op_2058, 6, vm); + setArg(call_vector_vector_op_2058, 7, vd); + setArg(call_vector_vector_op_2058, 8, vs2); + setArg(call_vector_vector_op_2058, 9, vs1); + setArg(call_vector_vector_op_2058, 10, vector_vector_op_2058_arg10); + } + cc.bind(label_merge); + } + auto tmp2060 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2060, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2060, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 514); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 515: VADD__VX */ + continuation_e __vadd__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADD__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 515); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2061; + x86::Gp ret_val_illegal_normal_2061 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2061, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2062 = get_reg(cc, 8, false); + mov(cc, tmp2062, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2062, ret_val_illegal_normal_2061); + setArg(call_illegal_normal_2061, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2061, 1, vd); + setArg(call_illegal_normal_2061, 2, vm); + setRet(call_illegal_normal_2061, 0, ret_val_illegal_normal_2061); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2064; + x86::Gp ret_val_sew_2064 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2064, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2063; + auto vector_imm_op_2063_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2063_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2063_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2063_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2063_arg10 = ret_val_sew_2064; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2063, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2064, 0, reinterpret_cast(this)); + setRet(call_sew_2064, 0, ret_val_sew_2064); + setArg(call_vector_imm_op_2063, 0, V); + setArg(call_vector_imm_op_2063, 1, 0); + setArg(call_vector_imm_op_2063, 2, 4); + setArg(call_vector_imm_op_2063, 3, vector_imm_op_2063_arg3); + setArg(call_vector_imm_op_2063, 4, vector_imm_op_2063_arg4); + setArg(call_vector_imm_op_2063, 5, vector_imm_op_2063_arg5); + setArg(call_vector_imm_op_2063, 6, vm); + setArg(call_vector_imm_op_2063, 7, vd); + setArg(call_vector_imm_op_2063, 8, vs2); + setArg(call_vector_imm_op_2063, 9, vector_imm_op_2063_arg9); + setArg(call_vector_imm_op_2063, 10, vector_imm_op_2063_arg10); + } + cc.bind(label_merge); + } + auto tmp2065 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2065, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2065, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 515); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 516: VSUB__VV */ + continuation_e __vsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 516); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2066; + x86::Gp ret_val_illegal_normal_2066 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2066, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2066; + setArg(call_illegal_normal_2066, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2066, 1, vd); + setArg(call_illegal_normal_2066, 2, vm); + setRet(call_illegal_normal_2066, 0, ret_val_illegal_normal_2066); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2068; + x86::Gp ret_val_sew_2068 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2068, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2067; + auto vector_vector_op_2067_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2067_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2067_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2067_arg10 = ret_val_sew_2068; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2067, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2068, 0, reinterpret_cast(this)); + setRet(call_sew_2068, 0, ret_val_sew_2068); + setArg(call_vector_vector_op_2067, 0, V); + setArg(call_vector_vector_op_2067, 1, 2); + setArg(call_vector_vector_op_2067, 2, 0); + setArg(call_vector_vector_op_2067, 3, vector_vector_op_2067_arg3); + setArg(call_vector_vector_op_2067, 4, vector_vector_op_2067_arg4); + setArg(call_vector_vector_op_2067, 5, vector_vector_op_2067_arg5); + setArg(call_vector_vector_op_2067, 6, vm); + setArg(call_vector_vector_op_2067, 7, vd); + setArg(call_vector_vector_op_2067, 8, vs2); + setArg(call_vector_vector_op_2067, 9, vs1); + setArg(call_vector_vector_op_2067, 10, vector_vector_op_2067_arg10); + } + cc.bind(label_merge); + } + auto tmp2069 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2069, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2069, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 516); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 517: VSUB__VX */ + continuation_e __vsub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 517); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2070; + x86::Gp ret_val_illegal_normal_2070 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2070, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2071 = get_reg(cc, 8, false); + mov(cc, tmp2071, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2071, ret_val_illegal_normal_2070); + setArg(call_illegal_normal_2070, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2070, 1, vd); + setArg(call_illegal_normal_2070, 2, vm); + setRet(call_illegal_normal_2070, 0, ret_val_illegal_normal_2070); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2073; + x86::Gp ret_val_sew_2073 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2073, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2072; + auto vector_imm_op_2072_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2072_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2072_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2072_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2072_arg10 = ret_val_sew_2073; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2072, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2073, 0, reinterpret_cast(this)); + setRet(call_sew_2073, 0, ret_val_sew_2073); + setArg(call_vector_imm_op_2072, 0, V); + setArg(call_vector_imm_op_2072, 1, 2); + setArg(call_vector_imm_op_2072, 2, 4); + setArg(call_vector_imm_op_2072, 3, vector_imm_op_2072_arg3); + setArg(call_vector_imm_op_2072, 4, vector_imm_op_2072_arg4); + setArg(call_vector_imm_op_2072, 5, vector_imm_op_2072_arg5); + setArg(call_vector_imm_op_2072, 6, vm); + setArg(call_vector_imm_op_2072, 7, vd); + setArg(call_vector_imm_op_2072, 8, vs2); + setArg(call_vector_imm_op_2072, 9, vector_imm_op_2072_arg9); + setArg(call_vector_imm_op_2072, 10, vector_imm_op_2072_arg10); + } + cc.bind(label_merge); + } + auto tmp2074 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2074, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2074, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 517); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 518: VRSUB__VI */ + continuation_e __vrsub__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vrsub.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRSUB__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 518); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2075; + x86::Gp ret_val_illegal_normal_2075 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2075, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2075; + setArg(call_illegal_normal_2075, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2075, 1, vd); + setArg(call_illegal_normal_2075, 2, vm); + setRet(call_illegal_normal_2075, 0, ret_val_illegal_normal_2075); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2077; + x86::Gp ret_val_sew_2077 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2077, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2076; + auto vector_imm_op_2076_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2076_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2076_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2076_arg10 = ret_val_sew_2077; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2076, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2077, 0, reinterpret_cast(this)); + setRet(call_sew_2077, 0, ret_val_sew_2077); + setArg(call_vector_imm_op_2076, 0, V); + setArg(call_vector_imm_op_2076, 1, 3); + setArg(call_vector_imm_op_2076, 2, 3); + setArg(call_vector_imm_op_2076, 3, vector_imm_op_2076_arg3); + setArg(call_vector_imm_op_2076, 4, vector_imm_op_2076_arg4); + setArg(call_vector_imm_op_2076, 5, vector_imm_op_2076_arg5); + setArg(call_vector_imm_op_2076, 6, vm); + setArg(call_vector_imm_op_2076, 7, vd); + setArg(call_vector_imm_op_2076, 8, vs2); + setArg(call_vector_imm_op_2076, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_op_2076, 10, vector_imm_op_2076_arg10); + } + cc.bind(label_merge); + } + auto tmp2078 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2078, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2078, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 518); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 519: VRSUB__VX */ + continuation_e __vrsub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRSUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 519); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2079; + x86::Gp ret_val_illegal_normal_2079 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2079, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2080 = get_reg(cc, 8, false); + mov(cc, tmp2080, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2080, ret_val_illegal_normal_2079); + setArg(call_illegal_normal_2079, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2079, 1, vd); + setArg(call_illegal_normal_2079, 2, vm); + setRet(call_illegal_normal_2079, 0, ret_val_illegal_normal_2079); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2082; + x86::Gp ret_val_sew_2082 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2082, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2081; + auto vector_imm_op_2081_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2081_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2081_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2081_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2081_arg10 = ret_val_sew_2082; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2081, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2082, 0, reinterpret_cast(this)); + setRet(call_sew_2082, 0, ret_val_sew_2082); + setArg(call_vector_imm_op_2081, 0, V); + setArg(call_vector_imm_op_2081, 1, 3); + setArg(call_vector_imm_op_2081, 2, 4); + setArg(call_vector_imm_op_2081, 3, vector_imm_op_2081_arg3); + setArg(call_vector_imm_op_2081, 4, vector_imm_op_2081_arg4); + setArg(call_vector_imm_op_2081, 5, vector_imm_op_2081_arg5); + setArg(call_vector_imm_op_2081, 6, vm); + setArg(call_vector_imm_op_2081, 7, vd); + setArg(call_vector_imm_op_2081, 8, vs2); + setArg(call_vector_imm_op_2081, 9, vector_imm_op_2081_arg9); + setArg(call_vector_imm_op_2081, 10, vector_imm_op_2081_arg10); + } + cc.bind(label_merge); + } + auto tmp2083 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2083, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2083, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 519); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 520: VWADDU__VV */ + continuation_e __vwaddu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADDU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 520); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2084; + x86::Gp ret_val_get_sew_pow_2084 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2084, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2085 = get_reg(cc, 8, false); + mov(cc, tmp2085, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2085, ret_val_get_sew_pow_2084)), 8, false), ~ 1); + setArg(call_get_sew_pow_2084, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2084, 0, ret_val_get_sew_pow_2084); + InvokeNode* call_get_lmul_pow_2086; + x86::Gp ret_val_get_lmul_pow_2086 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2086, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2086; + setArg(call_get_lmul_pow_2086, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2086, 0, ret_val_get_lmul_pow_2086); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2087; + auto illegal_variable_width_2087_arg2 = SEW_widen; + auto illegal_variable_width_2087_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2087 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2087, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2088; + auto valid_reg_overlap_2088_arg2 = LMUL_pow; + auto valid_reg_overlap_2088_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2088 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2088, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2089; + auto valid_reg_overlap_2089_arg2 = LMUL_pow; + auto valid_reg_overlap_2089_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2089 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2089, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2087, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2088)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2089)); + setArg(call_illegal_variable_width_2087, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2087, 1, vd); + setArg(call_illegal_variable_width_2087, 2, vm); + setArg(call_illegal_variable_width_2087, 3, illegal_variable_width_2087_arg2); + setArg(call_illegal_variable_width_2087, 4, illegal_variable_width_2087_arg3); + setRet(call_illegal_variable_width_2087, 0, ret_val_illegal_variable_width_2087); + setArg(call_valid_reg_overlap_2088, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2088, 1, vs1); + setArg(call_valid_reg_overlap_2088, 2, vd); + setArg(call_valid_reg_overlap_2088, 3, valid_reg_overlap_2088_arg2); + setArg(call_valid_reg_overlap_2088, 4, valid_reg_overlap_2088_arg3); + setRet(call_valid_reg_overlap_2088, 0, ret_val_valid_reg_overlap_2088); + setArg(call_valid_reg_overlap_2089, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2089, 1, vs2); + setArg(call_valid_reg_overlap_2089, 2, vd); + setArg(call_valid_reg_overlap_2089, 3, valid_reg_overlap_2089_arg2); + setArg(call_valid_reg_overlap_2089, 4, valid_reg_overlap_2089_arg3); + setRet(call_valid_reg_overlap_2089, 0, ret_val_valid_reg_overlap_2089); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2091; + x86::Gp ret_val_sew_2091 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2091, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2090; + auto vector_vector_wv_2090_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2090_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2090_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2090_arg10 = ret_val_sew_2091; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2090, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2091, 0, reinterpret_cast(this)); + setRet(call_sew_2091, 0, ret_val_sew_2091); + setArg(call_vector_vector_wv_2090, 0, V); + setArg(call_vector_vector_wv_2090, 1, 48); + setArg(call_vector_vector_wv_2090, 2, 2); + setArg(call_vector_vector_wv_2090, 3, vector_vector_wv_2090_arg3); + setArg(call_vector_vector_wv_2090, 4, vector_vector_wv_2090_arg4); + setArg(call_vector_vector_wv_2090, 5, vector_vector_wv_2090_arg5); + setArg(call_vector_vector_wv_2090, 6, vm); + setArg(call_vector_vector_wv_2090, 7, vd); + setArg(call_vector_vector_wv_2090, 8, vs2); + setArg(call_vector_vector_wv_2090, 9, vs1); + setArg(call_vector_vector_wv_2090, 10, vector_vector_wv_2090_arg10); + } + cc.bind(label_merge); + } + auto tmp2092 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2092, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2092, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 520); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 521: VWADDU__VX */ + continuation_e __vwaddu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADDU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 521); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2093; + x86::Gp ret_val_get_sew_pow_2093 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2093, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2094 = get_reg(cc, 8, false); + mov(cc, tmp2094, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2094, ret_val_get_sew_pow_2093)), 8, false), ~ 1); + setArg(call_get_sew_pow_2093, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2093, 0, ret_val_get_sew_pow_2093); + InvokeNode* call_get_lmul_pow_2095; + x86::Gp ret_val_get_lmul_pow_2095 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2095, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2095; + setArg(call_get_lmul_pow_2095, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2095, 0, ret_val_get_lmul_pow_2095); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2096; + auto illegal_variable_width_2096_arg2 = SEW_widen; + auto illegal_variable_width_2096_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2096 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2096, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2097; + auto valid_reg_overlap_2097_arg2 = LMUL_pow; + auto valid_reg_overlap_2097_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2097 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2097, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2096, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2097)); + setArg(call_illegal_variable_width_2096, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2096, 1, vd); + setArg(call_illegal_variable_width_2096, 2, vm); + setArg(call_illegal_variable_width_2096, 3, illegal_variable_width_2096_arg2); + setArg(call_illegal_variable_width_2096, 4, illegal_variable_width_2096_arg3); + setRet(call_illegal_variable_width_2096, 0, ret_val_illegal_variable_width_2096); + setArg(call_valid_reg_overlap_2097, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2097, 1, vs2); + setArg(call_valid_reg_overlap_2097, 2, vd); + setArg(call_valid_reg_overlap_2097, 3, valid_reg_overlap_2097_arg2); + setArg(call_valid_reg_overlap_2097, 4, valid_reg_overlap_2097_arg3); + setRet(call_valid_reg_overlap_2097, 0, ret_val_valid_reg_overlap_2097); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2099; + x86::Gp ret_val_sew_2099 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2099, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2098; + auto vector_imm_wv_2098_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2098_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2098_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2098_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2098_arg10 = ret_val_sew_2099; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2098, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2099, 0, reinterpret_cast(this)); + setRet(call_sew_2099, 0, ret_val_sew_2099); + setArg(call_vector_imm_wv_2098, 0, V); + setArg(call_vector_imm_wv_2098, 1, 48); + setArg(call_vector_imm_wv_2098, 2, 6); + setArg(call_vector_imm_wv_2098, 3, vector_imm_wv_2098_arg3); + setArg(call_vector_imm_wv_2098, 4, vector_imm_wv_2098_arg4); + setArg(call_vector_imm_wv_2098, 5, vector_imm_wv_2098_arg5); + setArg(call_vector_imm_wv_2098, 6, vm); + setArg(call_vector_imm_wv_2098, 7, vd); + setArg(call_vector_imm_wv_2098, 8, vs2); + setArg(call_vector_imm_wv_2098, 9, vector_imm_wv_2098_arg9); + setArg(call_vector_imm_wv_2098, 10, vector_imm_wv_2098_arg10); + } + cc.bind(label_merge); + } + auto tmp2100 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2100, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2100, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 521); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 522: VWSUBU__VV */ + continuation_e __vwsubu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUBU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 522); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2101; + x86::Gp ret_val_get_sew_pow_2101 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2101, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2102 = get_reg(cc, 8, false); + mov(cc, tmp2102, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2102, ret_val_get_sew_pow_2101)), 8, false), ~ 1); + setArg(call_get_sew_pow_2101, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2101, 0, ret_val_get_sew_pow_2101); + InvokeNode* call_get_lmul_pow_2103; + x86::Gp ret_val_get_lmul_pow_2103 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2103, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2103; + setArg(call_get_lmul_pow_2103, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2103, 0, ret_val_get_lmul_pow_2103); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2104; + auto illegal_variable_width_2104_arg2 = SEW_widen; + auto illegal_variable_width_2104_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2104 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2104, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2105; + auto valid_reg_overlap_2105_arg2 = LMUL_pow; + auto valid_reg_overlap_2105_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2105 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2105, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2106; + auto valid_reg_overlap_2106_arg2 = LMUL_pow; + auto valid_reg_overlap_2106_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2106 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2106, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2104, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2105)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2106)); + setArg(call_illegal_variable_width_2104, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2104, 1, vd); + setArg(call_illegal_variable_width_2104, 2, vm); + setArg(call_illegal_variable_width_2104, 3, illegal_variable_width_2104_arg2); + setArg(call_illegal_variable_width_2104, 4, illegal_variable_width_2104_arg3); + setRet(call_illegal_variable_width_2104, 0, ret_val_illegal_variable_width_2104); + setArg(call_valid_reg_overlap_2105, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2105, 1, vs1); + setArg(call_valid_reg_overlap_2105, 2, vd); + setArg(call_valid_reg_overlap_2105, 3, valid_reg_overlap_2105_arg2); + setArg(call_valid_reg_overlap_2105, 4, valid_reg_overlap_2105_arg3); + setRet(call_valid_reg_overlap_2105, 0, ret_val_valid_reg_overlap_2105); + setArg(call_valid_reg_overlap_2106, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2106, 1, vs2); + setArg(call_valid_reg_overlap_2106, 2, vd); + setArg(call_valid_reg_overlap_2106, 3, valid_reg_overlap_2106_arg2); + setArg(call_valid_reg_overlap_2106, 4, valid_reg_overlap_2106_arg3); + setRet(call_valid_reg_overlap_2106, 0, ret_val_valid_reg_overlap_2106); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2108; + x86::Gp ret_val_sew_2108 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2108, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2107; + auto vector_vector_wv_2107_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2107_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2107_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2107_arg10 = ret_val_sew_2108; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2107, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2108, 0, reinterpret_cast(this)); + setRet(call_sew_2108, 0, ret_val_sew_2108); + setArg(call_vector_vector_wv_2107, 0, V); + setArg(call_vector_vector_wv_2107, 1, 50); + setArg(call_vector_vector_wv_2107, 2, 2); + setArg(call_vector_vector_wv_2107, 3, vector_vector_wv_2107_arg3); + setArg(call_vector_vector_wv_2107, 4, vector_vector_wv_2107_arg4); + setArg(call_vector_vector_wv_2107, 5, vector_vector_wv_2107_arg5); + setArg(call_vector_vector_wv_2107, 6, vm); + setArg(call_vector_vector_wv_2107, 7, vd); + setArg(call_vector_vector_wv_2107, 8, vs2); + setArg(call_vector_vector_wv_2107, 9, vs1); + setArg(call_vector_vector_wv_2107, 10, vector_vector_wv_2107_arg10); + } + cc.bind(label_merge); + } + auto tmp2109 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2109, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2109, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 522); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 523: VWSUBU__VX */ + continuation_e __vwsubu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUBU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 523); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2110; + x86::Gp ret_val_get_sew_pow_2110 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2110, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2111 = get_reg(cc, 8, false); + mov(cc, tmp2111, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2111, ret_val_get_sew_pow_2110)), 8, false), ~ 1); + setArg(call_get_sew_pow_2110, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2110, 0, ret_val_get_sew_pow_2110); + InvokeNode* call_get_lmul_pow_2112; + x86::Gp ret_val_get_lmul_pow_2112 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2112, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2112; + setArg(call_get_lmul_pow_2112, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2112, 0, ret_val_get_lmul_pow_2112); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2113; + auto illegal_variable_width_2113_arg2 = SEW_widen; + auto illegal_variable_width_2113_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2113 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2113, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2114; + auto valid_reg_overlap_2114_arg2 = LMUL_pow; + auto valid_reg_overlap_2114_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2114 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2114, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2113, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2114)); + setArg(call_illegal_variable_width_2113, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2113, 1, vd); + setArg(call_illegal_variable_width_2113, 2, vm); + setArg(call_illegal_variable_width_2113, 3, illegal_variable_width_2113_arg2); + setArg(call_illegal_variable_width_2113, 4, illegal_variable_width_2113_arg3); + setRet(call_illegal_variable_width_2113, 0, ret_val_illegal_variable_width_2113); + setArg(call_valid_reg_overlap_2114, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2114, 1, vs2); + setArg(call_valid_reg_overlap_2114, 2, vd); + setArg(call_valid_reg_overlap_2114, 3, valid_reg_overlap_2114_arg2); + setArg(call_valid_reg_overlap_2114, 4, valid_reg_overlap_2114_arg3); + setRet(call_valid_reg_overlap_2114, 0, ret_val_valid_reg_overlap_2114); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2116; + x86::Gp ret_val_sew_2116 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2116, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2115; + auto vector_imm_wv_2115_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2115_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2115_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2115_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2115_arg10 = ret_val_sew_2116; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2115, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2116, 0, reinterpret_cast(this)); + setRet(call_sew_2116, 0, ret_val_sew_2116); + setArg(call_vector_imm_wv_2115, 0, V); + setArg(call_vector_imm_wv_2115, 1, 50); + setArg(call_vector_imm_wv_2115, 2, 6); + setArg(call_vector_imm_wv_2115, 3, vector_imm_wv_2115_arg3); + setArg(call_vector_imm_wv_2115, 4, vector_imm_wv_2115_arg4); + setArg(call_vector_imm_wv_2115, 5, vector_imm_wv_2115_arg5); + setArg(call_vector_imm_wv_2115, 6, vm); + setArg(call_vector_imm_wv_2115, 7, vd); + setArg(call_vector_imm_wv_2115, 8, vs2); + setArg(call_vector_imm_wv_2115, 9, vector_imm_wv_2115_arg9); + setArg(call_vector_imm_wv_2115, 10, vector_imm_wv_2115_arg10); + } + cc.bind(label_merge); + } + auto tmp2117 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2117, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2117, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 523); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 524: VWADD__VV */ + continuation_e __vwadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 524); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2118; + x86::Gp ret_val_get_sew_pow_2118 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2118, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2119 = get_reg(cc, 8, false); + mov(cc, tmp2119, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2119, ret_val_get_sew_pow_2118)), 8, false), ~ 1); + setArg(call_get_sew_pow_2118, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2118, 0, ret_val_get_sew_pow_2118); + InvokeNode* call_get_lmul_pow_2120; + x86::Gp ret_val_get_lmul_pow_2120 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2120, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2120; + setArg(call_get_lmul_pow_2120, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2120, 0, ret_val_get_lmul_pow_2120); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2121; + auto illegal_variable_width_2121_arg2 = SEW_widen; + auto illegal_variable_width_2121_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2121 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2121, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2122; + auto valid_reg_overlap_2122_arg2 = LMUL_pow; + auto valid_reg_overlap_2122_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2122 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2122, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2123; + auto valid_reg_overlap_2123_arg2 = LMUL_pow; + auto valid_reg_overlap_2123_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2123 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2123, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2121, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2122)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2123)); + setArg(call_illegal_variable_width_2121, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2121, 1, vd); + setArg(call_illegal_variable_width_2121, 2, vm); + setArg(call_illegal_variable_width_2121, 3, illegal_variable_width_2121_arg2); + setArg(call_illegal_variable_width_2121, 4, illegal_variable_width_2121_arg3); + setRet(call_illegal_variable_width_2121, 0, ret_val_illegal_variable_width_2121); + setArg(call_valid_reg_overlap_2122, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2122, 1, vs1); + setArg(call_valid_reg_overlap_2122, 2, vd); + setArg(call_valid_reg_overlap_2122, 3, valid_reg_overlap_2122_arg2); + setArg(call_valid_reg_overlap_2122, 4, valid_reg_overlap_2122_arg3); + setRet(call_valid_reg_overlap_2122, 0, ret_val_valid_reg_overlap_2122); + setArg(call_valid_reg_overlap_2123, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2123, 1, vs2); + setArg(call_valid_reg_overlap_2123, 2, vd); + setArg(call_valid_reg_overlap_2123, 3, valid_reg_overlap_2123_arg2); + setArg(call_valid_reg_overlap_2123, 4, valid_reg_overlap_2123_arg3); + setRet(call_valid_reg_overlap_2123, 0, ret_val_valid_reg_overlap_2123); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2125; + x86::Gp ret_val_sew_2125 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2125, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2124; + auto vector_vector_wv_2124_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2124_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2124_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2124_arg10 = ret_val_sew_2125; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2124, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2125, 0, reinterpret_cast(this)); + setRet(call_sew_2125, 0, ret_val_sew_2125); + setArg(call_vector_vector_wv_2124, 0, V); + setArg(call_vector_vector_wv_2124, 1, 49); + setArg(call_vector_vector_wv_2124, 2, 2); + setArg(call_vector_vector_wv_2124, 3, vector_vector_wv_2124_arg3); + setArg(call_vector_vector_wv_2124, 4, vector_vector_wv_2124_arg4); + setArg(call_vector_vector_wv_2124, 5, vector_vector_wv_2124_arg5); + setArg(call_vector_vector_wv_2124, 6, vm); + setArg(call_vector_vector_wv_2124, 7, vd); + setArg(call_vector_vector_wv_2124, 8, vs2); + setArg(call_vector_vector_wv_2124, 9, vs1); + setArg(call_vector_vector_wv_2124, 10, vector_vector_wv_2124_arg10); + } + cc.bind(label_merge); + } + auto tmp2126 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2126, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2126, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 524); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 525: VWADD__VX */ + continuation_e __vwadd__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADD__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 525); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2127; + x86::Gp ret_val_get_sew_pow_2127 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2127, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2128 = get_reg(cc, 8, false); + mov(cc, tmp2128, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2128, ret_val_get_sew_pow_2127)), 8, false), ~ 1); + setArg(call_get_sew_pow_2127, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2127, 0, ret_val_get_sew_pow_2127); + InvokeNode* call_get_lmul_pow_2129; + x86::Gp ret_val_get_lmul_pow_2129 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2129, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2129; + setArg(call_get_lmul_pow_2129, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2129, 0, ret_val_get_lmul_pow_2129); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2130; + auto illegal_variable_width_2130_arg2 = SEW_widen; + auto illegal_variable_width_2130_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2130 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2130, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2131; + auto valid_reg_overlap_2131_arg2 = LMUL_pow; + auto valid_reg_overlap_2131_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2131 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2131, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2130, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2131)); + setArg(call_illegal_variable_width_2130, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2130, 1, vd); + setArg(call_illegal_variable_width_2130, 2, vm); + setArg(call_illegal_variable_width_2130, 3, illegal_variable_width_2130_arg2); + setArg(call_illegal_variable_width_2130, 4, illegal_variable_width_2130_arg3); + setRet(call_illegal_variable_width_2130, 0, ret_val_illegal_variable_width_2130); + setArg(call_valid_reg_overlap_2131, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2131, 1, vs2); + setArg(call_valid_reg_overlap_2131, 2, vd); + setArg(call_valid_reg_overlap_2131, 3, valid_reg_overlap_2131_arg2); + setArg(call_valid_reg_overlap_2131, 4, valid_reg_overlap_2131_arg3); + setRet(call_valid_reg_overlap_2131, 0, ret_val_valid_reg_overlap_2131); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2133; + x86::Gp ret_val_sew_2133 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2133, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2132; + auto vector_imm_wv_2132_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2132_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2132_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2132_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2132_arg10 = ret_val_sew_2133; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2132, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2133, 0, reinterpret_cast(this)); + setRet(call_sew_2133, 0, ret_val_sew_2133); + setArg(call_vector_imm_wv_2132, 0, V); + setArg(call_vector_imm_wv_2132, 1, 49); + setArg(call_vector_imm_wv_2132, 2, 6); + setArg(call_vector_imm_wv_2132, 3, vector_imm_wv_2132_arg3); + setArg(call_vector_imm_wv_2132, 4, vector_imm_wv_2132_arg4); + setArg(call_vector_imm_wv_2132, 5, vector_imm_wv_2132_arg5); + setArg(call_vector_imm_wv_2132, 6, vm); + setArg(call_vector_imm_wv_2132, 7, vd); + setArg(call_vector_imm_wv_2132, 8, vs2); + setArg(call_vector_imm_wv_2132, 9, vector_imm_wv_2132_arg9); + setArg(call_vector_imm_wv_2132, 10, vector_imm_wv_2132_arg10); + } + cc.bind(label_merge); + } + auto tmp2134 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2134, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2134, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 525); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 526: VWSUB__VV */ + continuation_e __vwsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 526); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2135; + x86::Gp ret_val_get_sew_pow_2135 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2135, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2136 = get_reg(cc, 8, false); + mov(cc, tmp2136, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2136, ret_val_get_sew_pow_2135)), 8, false), ~ 1); + setArg(call_get_sew_pow_2135, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2135, 0, ret_val_get_sew_pow_2135); + InvokeNode* call_get_lmul_pow_2137; + x86::Gp ret_val_get_lmul_pow_2137 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2137, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2137; + setArg(call_get_lmul_pow_2137, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2137, 0, ret_val_get_lmul_pow_2137); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2138; + auto illegal_variable_width_2138_arg2 = SEW_widen; + auto illegal_variable_width_2138_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2138 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2138, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2139; + auto valid_reg_overlap_2139_arg2 = LMUL_pow; + auto valid_reg_overlap_2139_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2139 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2139, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2140; + auto valid_reg_overlap_2140_arg2 = LMUL_pow; + auto valid_reg_overlap_2140_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2140 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2140, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2138, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2139)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2140)); + setArg(call_illegal_variable_width_2138, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2138, 1, vd); + setArg(call_illegal_variable_width_2138, 2, vm); + setArg(call_illegal_variable_width_2138, 3, illegal_variable_width_2138_arg2); + setArg(call_illegal_variable_width_2138, 4, illegal_variable_width_2138_arg3); + setRet(call_illegal_variable_width_2138, 0, ret_val_illegal_variable_width_2138); + setArg(call_valid_reg_overlap_2139, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2139, 1, vs1); + setArg(call_valid_reg_overlap_2139, 2, vd); + setArg(call_valid_reg_overlap_2139, 3, valid_reg_overlap_2139_arg2); + setArg(call_valid_reg_overlap_2139, 4, valid_reg_overlap_2139_arg3); + setRet(call_valid_reg_overlap_2139, 0, ret_val_valid_reg_overlap_2139); + setArg(call_valid_reg_overlap_2140, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2140, 1, vs2); + setArg(call_valid_reg_overlap_2140, 2, vd); + setArg(call_valid_reg_overlap_2140, 3, valid_reg_overlap_2140_arg2); + setArg(call_valid_reg_overlap_2140, 4, valid_reg_overlap_2140_arg3); + setRet(call_valid_reg_overlap_2140, 0, ret_val_valid_reg_overlap_2140); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2142; + x86::Gp ret_val_sew_2142 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2142, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2141; + auto vector_vector_wv_2141_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2141_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2141_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2141_arg10 = ret_val_sew_2142; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2141, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2142, 0, reinterpret_cast(this)); + setRet(call_sew_2142, 0, ret_val_sew_2142); + setArg(call_vector_vector_wv_2141, 0, V); + setArg(call_vector_vector_wv_2141, 1, 51); + setArg(call_vector_vector_wv_2141, 2, 2); + setArg(call_vector_vector_wv_2141, 3, vector_vector_wv_2141_arg3); + setArg(call_vector_vector_wv_2141, 4, vector_vector_wv_2141_arg4); + setArg(call_vector_vector_wv_2141, 5, vector_vector_wv_2141_arg5); + setArg(call_vector_vector_wv_2141, 6, vm); + setArg(call_vector_vector_wv_2141, 7, vd); + setArg(call_vector_vector_wv_2141, 8, vs2); + setArg(call_vector_vector_wv_2141, 9, vs1); + setArg(call_vector_vector_wv_2141, 10, vector_vector_wv_2141_arg10); + } + cc.bind(label_merge); + } + auto tmp2143 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2143, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2143, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 526); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 527: VWSUB__VX */ + continuation_e __vwsub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 527); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2144; + x86::Gp ret_val_get_sew_pow_2144 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2144, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2145 = get_reg(cc, 8, false); + mov(cc, tmp2145, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2145, ret_val_get_sew_pow_2144)), 8, false), ~ 1); + setArg(call_get_sew_pow_2144, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2144, 0, ret_val_get_sew_pow_2144); + InvokeNode* call_get_lmul_pow_2146; + x86::Gp ret_val_get_lmul_pow_2146 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2146, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2146; + setArg(call_get_lmul_pow_2146, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2146, 0, ret_val_get_lmul_pow_2146); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2147; + auto illegal_variable_width_2147_arg2 = SEW_widen; + auto illegal_variable_width_2147_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2147 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2147, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2148; + auto valid_reg_overlap_2148_arg2 = LMUL_pow; + auto valid_reg_overlap_2148_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2148 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2148, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2147, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2148)); + setArg(call_illegal_variable_width_2147, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2147, 1, vd); + setArg(call_illegal_variable_width_2147, 2, vm); + setArg(call_illegal_variable_width_2147, 3, illegal_variable_width_2147_arg2); + setArg(call_illegal_variable_width_2147, 4, illegal_variable_width_2147_arg3); + setRet(call_illegal_variable_width_2147, 0, ret_val_illegal_variable_width_2147); + setArg(call_valid_reg_overlap_2148, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2148, 1, vs2); + setArg(call_valid_reg_overlap_2148, 2, vd); + setArg(call_valid_reg_overlap_2148, 3, valid_reg_overlap_2148_arg2); + setArg(call_valid_reg_overlap_2148, 4, valid_reg_overlap_2148_arg3); + setRet(call_valid_reg_overlap_2148, 0, ret_val_valid_reg_overlap_2148); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2150; + x86::Gp ret_val_sew_2150 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2150, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2149; + auto vector_imm_wv_2149_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2149_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2149_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2149_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2149_arg10 = ret_val_sew_2150; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2149, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2150, 0, reinterpret_cast(this)); + setRet(call_sew_2150, 0, ret_val_sew_2150); + setArg(call_vector_imm_wv_2149, 0, V); + setArg(call_vector_imm_wv_2149, 1, 51); + setArg(call_vector_imm_wv_2149, 2, 6); + setArg(call_vector_imm_wv_2149, 3, vector_imm_wv_2149_arg3); + setArg(call_vector_imm_wv_2149, 4, vector_imm_wv_2149_arg4); + setArg(call_vector_imm_wv_2149, 5, vector_imm_wv_2149_arg5); + setArg(call_vector_imm_wv_2149, 6, vm); + setArg(call_vector_imm_wv_2149, 7, vd); + setArg(call_vector_imm_wv_2149, 8, vs2); + setArg(call_vector_imm_wv_2149, 9, vector_imm_wv_2149_arg9); + setArg(call_vector_imm_wv_2149, 10, vector_imm_wv_2149_arg10); + } + cc.bind(label_merge); + } + auto tmp2151 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2151, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2151, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 527); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 528: VWADDU__WV */ + continuation_e __vwaddu__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwaddu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADDU__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 528); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2152; + x86::Gp ret_val_get_sew_pow_2152 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2152, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2153 = get_reg(cc, 8, false); + mov(cc, tmp2153, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2153, ret_val_get_sew_pow_2152)), 8, false), ~ 1); + setArg(call_get_sew_pow_2152, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2152, 0, ret_val_get_sew_pow_2152); + InvokeNode* call_get_lmul_pow_2154; + x86::Gp ret_val_get_lmul_pow_2154 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2154, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2154; + setArg(call_get_lmul_pow_2154, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2154, 0, ret_val_get_lmul_pow_2154); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2155; + auto illegal_variable_width_2155_arg2 = SEW_widen; + auto illegal_variable_width_2155_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2155 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2155, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2156; + auto valid_reg_overlap_2156_arg2 = LMUL_pow; + auto valid_reg_overlap_2156_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2156 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2156, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, bor, ret_val_illegal_variable_width_2155, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2156)); + setArg(call_illegal_variable_width_2155, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2155, 1, vd); + setArg(call_illegal_variable_width_2155, 2, vm); + setArg(call_illegal_variable_width_2155, 3, illegal_variable_width_2155_arg2); + setArg(call_illegal_variable_width_2155, 4, illegal_variable_width_2155_arg3); + setRet(call_illegal_variable_width_2155, 0, ret_val_illegal_variable_width_2155); + setArg(call_valid_reg_overlap_2156, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2156, 1, vs1); + setArg(call_valid_reg_overlap_2156, 2, vd); + setArg(call_valid_reg_overlap_2156, 3, valid_reg_overlap_2156_arg2); + setArg(call_valid_reg_overlap_2156, 4, valid_reg_overlap_2156_arg3); + setRet(call_valid_reg_overlap_2156, 0, ret_val_valid_reg_overlap_2156); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2158; + x86::Gp ret_val_sew_2158 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2158, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_ww_2157; + auto vector_vector_ww_2157_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_ww_2157_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_ww_2157_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_ww_2157_arg10 = ret_val_sew_2158; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_ww_2157, &vector_vector_ww, FuncSignature::build()); + setArg(call_sew_2158, 0, reinterpret_cast(this)); + setRet(call_sew_2158, 0, ret_val_sew_2158); + setArg(call_vector_vector_ww_2157, 0, V); + setArg(call_vector_vector_ww_2157, 1, 52); + setArg(call_vector_vector_ww_2157, 2, 2); + setArg(call_vector_vector_ww_2157, 3, vector_vector_ww_2157_arg3); + setArg(call_vector_vector_ww_2157, 4, vector_vector_ww_2157_arg4); + setArg(call_vector_vector_ww_2157, 5, vector_vector_ww_2157_arg5); + setArg(call_vector_vector_ww_2157, 6, vm); + setArg(call_vector_vector_ww_2157, 7, vd); + setArg(call_vector_vector_ww_2157, 8, vs2); + setArg(call_vector_vector_ww_2157, 9, vs1); + setArg(call_vector_vector_ww_2157, 10, vector_vector_ww_2157_arg10); + } + cc.bind(label_merge); + } + auto tmp2159 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2159, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2159, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 528); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 529: VWADDU__WX */ + continuation_e __vwaddu__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwaddu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADDU__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 529); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2160; + x86::Gp ret_val_get_sew_pow_2160 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2160, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2161 = get_reg(cc, 8, false); + mov(cc, tmp2161, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2161, ret_val_get_sew_pow_2160)), 8, false), ~ 1); + setArg(call_get_sew_pow_2160, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2160, 0, ret_val_get_sew_pow_2160); + InvokeNode* call_get_lmul_pow_2162; + x86::Gp ret_val_get_lmul_pow_2162 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2162, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2162; + setArg(call_get_lmul_pow_2162, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2162, 0, ret_val_get_lmul_pow_2162); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2163; + auto illegal_variable_width_2163_arg2 = SEW_widen; + auto illegal_variable_width_2163_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2163 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2163, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_variable_width_2163; + setArg(call_illegal_variable_width_2163, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2163, 1, vd); + setArg(call_illegal_variable_width_2163, 2, vm); + setArg(call_illegal_variable_width_2163, 3, illegal_variable_width_2163_arg2); + setArg(call_illegal_variable_width_2163, 4, illegal_variable_width_2163_arg3); + setRet(call_illegal_variable_width_2163, 0, ret_val_illegal_variable_width_2163); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2165; + x86::Gp ret_val_sew_2165 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2165, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_ww_2164; + auto vector_imm_ww_2164_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_ww_2164_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_ww_2164_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_ww_2164_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_ww_2164_arg10 = ret_val_sew_2165; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_ww_2164, &vector_imm_ww, FuncSignature::build()); + setArg(call_sew_2165, 0, reinterpret_cast(this)); + setRet(call_sew_2165, 0, ret_val_sew_2165); + setArg(call_vector_imm_ww_2164, 0, V); + setArg(call_vector_imm_ww_2164, 1, 52); + setArg(call_vector_imm_ww_2164, 2, 6); + setArg(call_vector_imm_ww_2164, 3, vector_imm_ww_2164_arg3); + setArg(call_vector_imm_ww_2164, 4, vector_imm_ww_2164_arg4); + setArg(call_vector_imm_ww_2164, 5, vector_imm_ww_2164_arg5); + setArg(call_vector_imm_ww_2164, 6, vm); + setArg(call_vector_imm_ww_2164, 7, vd); + setArg(call_vector_imm_ww_2164, 8, vs2); + setArg(call_vector_imm_ww_2164, 9, vector_imm_ww_2164_arg9); + setArg(call_vector_imm_ww_2164, 10, vector_imm_ww_2164_arg10); + } + cc.bind(label_merge); + } + auto tmp2166 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2166, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2166, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 529); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 530: VWSUBU__WV */ + continuation_e __vwsubu__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsubu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUBU__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 530); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2167; + x86::Gp ret_val_get_sew_pow_2167 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2167, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2168 = get_reg(cc, 8, false); + mov(cc, tmp2168, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2168, ret_val_get_sew_pow_2167)), 8, false), ~ 1); + setArg(call_get_sew_pow_2167, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2167, 0, ret_val_get_sew_pow_2167); + InvokeNode* call_get_lmul_pow_2169; + x86::Gp ret_val_get_lmul_pow_2169 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2169, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2169; + setArg(call_get_lmul_pow_2169, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2169, 0, ret_val_get_lmul_pow_2169); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2170; + auto illegal_variable_width_2170_arg2 = SEW_widen; + auto illegal_variable_width_2170_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2170 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2170, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2171; + auto valid_reg_overlap_2171_arg2 = LMUL_pow; + auto valid_reg_overlap_2171_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2171 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2171, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, bor, ret_val_illegal_variable_width_2170, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2171)); + setArg(call_illegal_variable_width_2170, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2170, 1, vd); + setArg(call_illegal_variable_width_2170, 2, vm); + setArg(call_illegal_variable_width_2170, 3, illegal_variable_width_2170_arg2); + setArg(call_illegal_variable_width_2170, 4, illegal_variable_width_2170_arg3); + setRet(call_illegal_variable_width_2170, 0, ret_val_illegal_variable_width_2170); + setArg(call_valid_reg_overlap_2171, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2171, 1, vs1); + setArg(call_valid_reg_overlap_2171, 2, vd); + setArg(call_valid_reg_overlap_2171, 3, valid_reg_overlap_2171_arg2); + setArg(call_valid_reg_overlap_2171, 4, valid_reg_overlap_2171_arg3); + setRet(call_valid_reg_overlap_2171, 0, ret_val_valid_reg_overlap_2171); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2173; + x86::Gp ret_val_sew_2173 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2173, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_ww_2172; + auto vector_vector_ww_2172_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_ww_2172_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_ww_2172_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_ww_2172_arg10 = ret_val_sew_2173; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_ww_2172, &vector_vector_ww, FuncSignature::build()); + setArg(call_sew_2173, 0, reinterpret_cast(this)); + setRet(call_sew_2173, 0, ret_val_sew_2173); + setArg(call_vector_vector_ww_2172, 0, V); + setArg(call_vector_vector_ww_2172, 1, 54); + setArg(call_vector_vector_ww_2172, 2, 2); + setArg(call_vector_vector_ww_2172, 3, vector_vector_ww_2172_arg3); + setArg(call_vector_vector_ww_2172, 4, vector_vector_ww_2172_arg4); + setArg(call_vector_vector_ww_2172, 5, vector_vector_ww_2172_arg5); + setArg(call_vector_vector_ww_2172, 6, vm); + setArg(call_vector_vector_ww_2172, 7, vd); + setArg(call_vector_vector_ww_2172, 8, vs2); + setArg(call_vector_vector_ww_2172, 9, vs1); + setArg(call_vector_vector_ww_2172, 10, vector_vector_ww_2172_arg10); + } + cc.bind(label_merge); + } + auto tmp2174 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2174, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2174, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 530); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 531: VWSUBU__WX */ + continuation_e __vwsubu__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsubu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUBU__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 531); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2175; + x86::Gp ret_val_get_sew_pow_2175 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2175, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2176 = get_reg(cc, 8, false); + mov(cc, tmp2176, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2176, ret_val_get_sew_pow_2175)), 8, false), ~ 1); + setArg(call_get_sew_pow_2175, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2175, 0, ret_val_get_sew_pow_2175); + InvokeNode* call_get_lmul_pow_2177; + x86::Gp ret_val_get_lmul_pow_2177 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2177, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2177; + setArg(call_get_lmul_pow_2177, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2177, 0, ret_val_get_lmul_pow_2177); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2178; + auto illegal_variable_width_2178_arg2 = SEW_widen; + auto illegal_variable_width_2178_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2178 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2178, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_variable_width_2178; + setArg(call_illegal_variable_width_2178, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2178, 1, vd); + setArg(call_illegal_variable_width_2178, 2, vm); + setArg(call_illegal_variable_width_2178, 3, illegal_variable_width_2178_arg2); + setArg(call_illegal_variable_width_2178, 4, illegal_variable_width_2178_arg3); + setRet(call_illegal_variable_width_2178, 0, ret_val_illegal_variable_width_2178); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2180; + x86::Gp ret_val_sew_2180 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2180, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_ww_2179; + auto vector_imm_ww_2179_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_ww_2179_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_ww_2179_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_ww_2179_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_ww_2179_arg10 = ret_val_sew_2180; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_ww_2179, &vector_imm_ww, FuncSignature::build()); + setArg(call_sew_2180, 0, reinterpret_cast(this)); + setRet(call_sew_2180, 0, ret_val_sew_2180); + setArg(call_vector_imm_ww_2179, 0, V); + setArg(call_vector_imm_ww_2179, 1, 54); + setArg(call_vector_imm_ww_2179, 2, 6); + setArg(call_vector_imm_ww_2179, 3, vector_imm_ww_2179_arg3); + setArg(call_vector_imm_ww_2179, 4, vector_imm_ww_2179_arg4); + setArg(call_vector_imm_ww_2179, 5, vector_imm_ww_2179_arg5); + setArg(call_vector_imm_ww_2179, 6, vm); + setArg(call_vector_imm_ww_2179, 7, vd); + setArg(call_vector_imm_ww_2179, 8, vs2); + setArg(call_vector_imm_ww_2179, 9, vector_imm_ww_2179_arg9); + setArg(call_vector_imm_ww_2179, 10, vector_imm_ww_2179_arg10); + } + cc.bind(label_merge); + } + auto tmp2181 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2181, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2181, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 531); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 532: VWADD__WV */ + continuation_e __vwadd__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwadd.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADD__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 532); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2182; + x86::Gp ret_val_get_sew_pow_2182 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2182, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2183 = get_reg(cc, 8, false); + mov(cc, tmp2183, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2183, ret_val_get_sew_pow_2182)), 8, false), ~ 1); + setArg(call_get_sew_pow_2182, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2182, 0, ret_val_get_sew_pow_2182); + InvokeNode* call_get_lmul_pow_2184; + x86::Gp ret_val_get_lmul_pow_2184 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2184, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2184; + setArg(call_get_lmul_pow_2184, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2184, 0, ret_val_get_lmul_pow_2184); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2185; + auto illegal_variable_width_2185_arg2 = SEW_widen; + auto illegal_variable_width_2185_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2185 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2185, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2186; + auto valid_reg_overlap_2186_arg2 = LMUL_pow; + auto valid_reg_overlap_2186_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2186 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2186, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, bor, ret_val_illegal_variable_width_2185, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2186)); + setArg(call_illegal_variable_width_2185, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2185, 1, vd); + setArg(call_illegal_variable_width_2185, 2, vm); + setArg(call_illegal_variable_width_2185, 3, illegal_variable_width_2185_arg2); + setArg(call_illegal_variable_width_2185, 4, illegal_variable_width_2185_arg3); + setRet(call_illegal_variable_width_2185, 0, ret_val_illegal_variable_width_2185); + setArg(call_valid_reg_overlap_2186, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2186, 1, vs1); + setArg(call_valid_reg_overlap_2186, 2, vd); + setArg(call_valid_reg_overlap_2186, 3, valid_reg_overlap_2186_arg2); + setArg(call_valid_reg_overlap_2186, 4, valid_reg_overlap_2186_arg3); + setRet(call_valid_reg_overlap_2186, 0, ret_val_valid_reg_overlap_2186); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2188; + x86::Gp ret_val_sew_2188 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2188, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_ww_2187; + auto vector_vector_ww_2187_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_ww_2187_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_ww_2187_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_ww_2187_arg10 = ret_val_sew_2188; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_ww_2187, &vector_vector_ww, FuncSignature::build()); + setArg(call_sew_2188, 0, reinterpret_cast(this)); + setRet(call_sew_2188, 0, ret_val_sew_2188); + setArg(call_vector_vector_ww_2187, 0, V); + setArg(call_vector_vector_ww_2187, 1, 53); + setArg(call_vector_vector_ww_2187, 2, 2); + setArg(call_vector_vector_ww_2187, 3, vector_vector_ww_2187_arg3); + setArg(call_vector_vector_ww_2187, 4, vector_vector_ww_2187_arg4); + setArg(call_vector_vector_ww_2187, 5, vector_vector_ww_2187_arg5); + setArg(call_vector_vector_ww_2187, 6, vm); + setArg(call_vector_vector_ww_2187, 7, vd); + setArg(call_vector_vector_ww_2187, 8, vs2); + setArg(call_vector_vector_ww_2187, 9, vs1); + setArg(call_vector_vector_ww_2187, 10, vector_vector_ww_2187_arg10); + } + cc.bind(label_merge); + } + auto tmp2189 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2189, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2189, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 532); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 533: VWADD__WX */ + continuation_e __vwadd__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwadd.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWADD__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 533); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2190; + x86::Gp ret_val_get_sew_pow_2190 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2190, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2191 = get_reg(cc, 8, false); + mov(cc, tmp2191, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2191, ret_val_get_sew_pow_2190)), 8, false), ~ 1); + setArg(call_get_sew_pow_2190, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2190, 0, ret_val_get_sew_pow_2190); + InvokeNode* call_get_lmul_pow_2192; + x86::Gp ret_val_get_lmul_pow_2192 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2192, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2192; + setArg(call_get_lmul_pow_2192, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2192, 0, ret_val_get_lmul_pow_2192); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2193; + auto illegal_variable_width_2193_arg2 = SEW_widen; + auto illegal_variable_width_2193_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2193 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2193, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_variable_width_2193; + setArg(call_illegal_variable_width_2193, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2193, 1, vd); + setArg(call_illegal_variable_width_2193, 2, vm); + setArg(call_illegal_variable_width_2193, 3, illegal_variable_width_2193_arg2); + setArg(call_illegal_variable_width_2193, 4, illegal_variable_width_2193_arg3); + setRet(call_illegal_variable_width_2193, 0, ret_val_illegal_variable_width_2193); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2195; + x86::Gp ret_val_sew_2195 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2195, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_ww_2194; + auto vector_imm_ww_2194_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_ww_2194_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_ww_2194_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_ww_2194_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_ww_2194_arg10 = ret_val_sew_2195; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_ww_2194, &vector_imm_ww, FuncSignature::build()); + setArg(call_sew_2195, 0, reinterpret_cast(this)); + setRet(call_sew_2195, 0, ret_val_sew_2195); + setArg(call_vector_imm_ww_2194, 0, V); + setArg(call_vector_imm_ww_2194, 1, 53); + setArg(call_vector_imm_ww_2194, 2, 6); + setArg(call_vector_imm_ww_2194, 3, vector_imm_ww_2194_arg3); + setArg(call_vector_imm_ww_2194, 4, vector_imm_ww_2194_arg4); + setArg(call_vector_imm_ww_2194, 5, vector_imm_ww_2194_arg5); + setArg(call_vector_imm_ww_2194, 6, vm); + setArg(call_vector_imm_ww_2194, 7, vd); + setArg(call_vector_imm_ww_2194, 8, vs2); + setArg(call_vector_imm_ww_2194, 9, vector_imm_ww_2194_arg9); + setArg(call_vector_imm_ww_2194, 10, vector_imm_ww_2194_arg10); + } + cc.bind(label_merge); + } + auto tmp2196 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2196, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2196, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 533); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 534: VWSUB__WV */ + continuation_e __vwsub__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwsub.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUB__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 534); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2197; + x86::Gp ret_val_get_sew_pow_2197 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2197, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2198 = get_reg(cc, 8, false); + mov(cc, tmp2198, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2198, ret_val_get_sew_pow_2197)), 8, false), ~ 1); + setArg(call_get_sew_pow_2197, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2197, 0, ret_val_get_sew_pow_2197); + InvokeNode* call_get_lmul_pow_2199; + x86::Gp ret_val_get_lmul_pow_2199 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2199, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2199; + setArg(call_get_lmul_pow_2199, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2199, 0, ret_val_get_lmul_pow_2199); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2200; + auto illegal_variable_width_2200_arg2 = SEW_widen; + auto illegal_variable_width_2200_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2200 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2200, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2201; + auto valid_reg_overlap_2201_arg2 = LMUL_pow; + auto valid_reg_overlap_2201_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2201 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2201, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, bor, ret_val_illegal_variable_width_2200, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2201)); + setArg(call_illegal_variable_width_2200, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2200, 1, vd); + setArg(call_illegal_variable_width_2200, 2, vm); + setArg(call_illegal_variable_width_2200, 3, illegal_variable_width_2200_arg2); + setArg(call_illegal_variable_width_2200, 4, illegal_variable_width_2200_arg3); + setRet(call_illegal_variable_width_2200, 0, ret_val_illegal_variable_width_2200); + setArg(call_valid_reg_overlap_2201, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2201, 1, vs1); + setArg(call_valid_reg_overlap_2201, 2, vd); + setArg(call_valid_reg_overlap_2201, 3, valid_reg_overlap_2201_arg2); + setArg(call_valid_reg_overlap_2201, 4, valid_reg_overlap_2201_arg3); + setRet(call_valid_reg_overlap_2201, 0, ret_val_valid_reg_overlap_2201); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2203; + x86::Gp ret_val_sew_2203 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2203, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_ww_2202; + auto vector_vector_ww_2202_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_ww_2202_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_ww_2202_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_ww_2202_arg10 = ret_val_sew_2203; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_ww_2202, &vector_vector_ww, FuncSignature::build()); + setArg(call_sew_2203, 0, reinterpret_cast(this)); + setRet(call_sew_2203, 0, ret_val_sew_2203); + setArg(call_vector_vector_ww_2202, 0, V); + setArg(call_vector_vector_ww_2202, 1, 55); + setArg(call_vector_vector_ww_2202, 2, 2); + setArg(call_vector_vector_ww_2202, 3, vector_vector_ww_2202_arg3); + setArg(call_vector_vector_ww_2202, 4, vector_vector_ww_2202_arg4); + setArg(call_vector_vector_ww_2202, 5, vector_vector_ww_2202_arg5); + setArg(call_vector_vector_ww_2202, 6, vm); + setArg(call_vector_vector_ww_2202, 7, vd); + setArg(call_vector_vector_ww_2202, 8, vs2); + setArg(call_vector_vector_ww_2202, 9, vs1); + setArg(call_vector_vector_ww_2202, 10, vector_vector_ww_2202_arg10); + } + cc.bind(label_merge); + } + auto tmp2204 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2204, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2204, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 534); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 535: VWSUB__WX */ + continuation_e __vwsub__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwsub.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWSUB__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 535); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2205; + x86::Gp ret_val_get_sew_pow_2205 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2205, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2206 = get_reg(cc, 8, false); + mov(cc, tmp2206, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2206, ret_val_get_sew_pow_2205)), 8, false), ~ 1); + setArg(call_get_sew_pow_2205, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2205, 0, ret_val_get_sew_pow_2205); + InvokeNode* call_get_lmul_pow_2207; + x86::Gp ret_val_get_lmul_pow_2207 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2207, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2207; + setArg(call_get_lmul_pow_2207, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2207, 0, ret_val_get_lmul_pow_2207); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2208; + auto illegal_variable_width_2208_arg2 = SEW_widen; + auto illegal_variable_width_2208_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2208 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2208, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_variable_width_2208; + setArg(call_illegal_variable_width_2208, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2208, 1, vd); + setArg(call_illegal_variable_width_2208, 2, vm); + setArg(call_illegal_variable_width_2208, 3, illegal_variable_width_2208_arg2); + setArg(call_illegal_variable_width_2208, 4, illegal_variable_width_2208_arg3); + setRet(call_illegal_variable_width_2208, 0, ret_val_illegal_variable_width_2208); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2210; + x86::Gp ret_val_sew_2210 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2210, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_ww_2209; + auto vector_imm_ww_2209_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_ww_2209_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_ww_2209_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_ww_2209_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_ww_2209_arg10 = ret_val_sew_2210; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_ww_2209, &vector_imm_ww, FuncSignature::build()); + setArg(call_sew_2210, 0, reinterpret_cast(this)); + setRet(call_sew_2210, 0, ret_val_sew_2210); + setArg(call_vector_imm_ww_2209, 0, V); + setArg(call_vector_imm_ww_2209, 1, 55); + setArg(call_vector_imm_ww_2209, 2, 6); + setArg(call_vector_imm_ww_2209, 3, vector_imm_ww_2209_arg3); + setArg(call_vector_imm_ww_2209, 4, vector_imm_ww_2209_arg4); + setArg(call_vector_imm_ww_2209, 5, vector_imm_ww_2209_arg5); + setArg(call_vector_imm_ww_2209, 6, vm); + setArg(call_vector_imm_ww_2209, 7, vd); + setArg(call_vector_imm_ww_2209, 8, vs2); + setArg(call_vector_imm_ww_2209, 9, vector_imm_ww_2209_arg9); + setArg(call_vector_imm_ww_2209, 10, vector_imm_ww_2209_arg10); + } + cc.bind(label_merge); + } + auto tmp2211 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2211, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2211, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 535); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 536: VZEXT__VF2 */ + continuation_e __vzext__vf2(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf2"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VZEXT__VF2_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 536); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2212; + x86::Gp ret_val_get_sew_pow_2212 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2212, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2212; + setArg(call_get_sew_pow_2212, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2212, 0, ret_val_get_sew_pow_2212); + auto tmp2213 = get_reg(cc, 8, false); + mov(cc, tmp2213, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2213, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2214; + x86::Gp ret_val_get_lmul_pow_2214 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2214, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2214; + setArg(call_get_lmul_pow_2214, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2214, 0, ret_val_get_lmul_pow_2214); + auto SEW_target = gen_operation(cc, udiv, SEW, 2); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2215; + auto illegal_variable_width_2215_arg2 = SEW_target; + auto illegal_variable_width_2215_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2215 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2215, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2216; + auto valid_reg_overlap_2216_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2216_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2216 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2216, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2215, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2216)); + setArg(call_illegal_variable_width_2215, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2215, 1, vd); + setArg(call_illegal_variable_width_2215, 2, vm); + setArg(call_illegal_variable_width_2215, 3, illegal_variable_width_2215_arg2); + setArg(call_illegal_variable_width_2215, 4, illegal_variable_width_2215_arg3); + setRet(call_illegal_variable_width_2215, 0, ret_val_illegal_variable_width_2215); + setArg(call_valid_reg_overlap_2216, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2216, 1, vs2); + setArg(call_valid_reg_overlap_2216, 2, vd); + setArg(call_valid_reg_overlap_2216, 3, valid_reg_overlap_2216_arg2); + setArg(call_valid_reg_overlap_2216, 4, valid_reg_overlap_2216_arg3); + setRet(call_valid_reg_overlap_2216, 0, ret_val_valid_reg_overlap_2216); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2217; + auto vector_extend_2217_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2217_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2217_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2217_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2217, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2217, 0, V); + setArg(call_vector_extend_2217, 1, 6); + setArg(call_vector_extend_2217, 2, vector_extend_2217_arg2); + setArg(call_vector_extend_2217, 3, vector_extend_2217_arg3); + setArg(call_vector_extend_2217, 4, vector_extend_2217_arg4); + setArg(call_vector_extend_2217, 5, vm); + setArg(call_vector_extend_2217, 6, vd); + setArg(call_vector_extend_2217, 7, vs2); + setArg(call_vector_extend_2217, 8, vector_extend_2217_arg8); + setArg(call_vector_extend_2217, 9, 1); + } + cc.bind(label_merge); + } + auto tmp2218 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2218, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2218, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 536); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 537: VSEXT__VF2 */ + continuation_e __vsext__vf2(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf2"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSEXT__VF2_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 537); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2219; + x86::Gp ret_val_get_sew_pow_2219 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2219, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2219; + setArg(call_get_sew_pow_2219, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2219, 0, ret_val_get_sew_pow_2219); + auto tmp2220 = get_reg(cc, 8, false); + mov(cc, tmp2220, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2220, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2221; + x86::Gp ret_val_get_lmul_pow_2221 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2221, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2221; + setArg(call_get_lmul_pow_2221, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2221, 0, ret_val_get_lmul_pow_2221); + auto SEW_target = gen_operation(cc, udiv, SEW, 2); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2222; + auto illegal_variable_width_2222_arg2 = SEW_target; + auto illegal_variable_width_2222_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2222 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2222, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2223; + auto valid_reg_overlap_2223_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2223_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2223 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2223, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2222, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2223)); + setArg(call_illegal_variable_width_2222, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2222, 1, vd); + setArg(call_illegal_variable_width_2222, 2, vm); + setArg(call_illegal_variable_width_2222, 3, illegal_variable_width_2222_arg2); + setArg(call_illegal_variable_width_2222, 4, illegal_variable_width_2222_arg3); + setRet(call_illegal_variable_width_2222, 0, ret_val_illegal_variable_width_2222); + setArg(call_valid_reg_overlap_2223, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2223, 1, vs2); + setArg(call_valid_reg_overlap_2223, 2, vd); + setArg(call_valid_reg_overlap_2223, 3, valid_reg_overlap_2223_arg2); + setArg(call_valid_reg_overlap_2223, 4, valid_reg_overlap_2223_arg3); + setRet(call_valid_reg_overlap_2223, 0, ret_val_valid_reg_overlap_2223); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2224; + auto vector_extend_2224_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2224_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2224_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2224_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2224, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2224, 0, V); + setArg(call_vector_extend_2224, 1, 7); + setArg(call_vector_extend_2224, 2, vector_extend_2224_arg2); + setArg(call_vector_extend_2224, 3, vector_extend_2224_arg3); + setArg(call_vector_extend_2224, 4, vector_extend_2224_arg4); + setArg(call_vector_extend_2224, 5, vm); + setArg(call_vector_extend_2224, 6, vd); + setArg(call_vector_extend_2224, 7, vs2); + setArg(call_vector_extend_2224, 8, vector_extend_2224_arg8); + setArg(call_vector_extend_2224, 9, 1); + } + cc.bind(label_merge); + } + auto tmp2225 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2225, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2225, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 537); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 538: VZEXT__VF4 */ + continuation_e __vzext__vf4(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf4"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VZEXT__VF4_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 538); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2226; + x86::Gp ret_val_get_sew_pow_2226 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2226, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2226; + setArg(call_get_sew_pow_2226, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2226, 0, ret_val_get_sew_pow_2226); + auto tmp2227 = get_reg(cc, 8, false); + mov(cc, tmp2227, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2227, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2228; + x86::Gp ret_val_get_lmul_pow_2228 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2228, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2228; + setArg(call_get_lmul_pow_2228, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2228, 0, ret_val_get_lmul_pow_2228); + auto SEW_target = gen_operation(cc, udiv, SEW, 4); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 2); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2229; + auto illegal_variable_width_2229_arg2 = SEW_target; + auto illegal_variable_width_2229_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2229 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2229, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2230; + auto valid_reg_overlap_2230_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2230_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2230 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2230, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2229, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2230)); + setArg(call_illegal_variable_width_2229, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2229, 1, vd); + setArg(call_illegal_variable_width_2229, 2, vm); + setArg(call_illegal_variable_width_2229, 3, illegal_variable_width_2229_arg2); + setArg(call_illegal_variable_width_2229, 4, illegal_variable_width_2229_arg3); + setRet(call_illegal_variable_width_2229, 0, ret_val_illegal_variable_width_2229); + setArg(call_valid_reg_overlap_2230, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2230, 1, vs2); + setArg(call_valid_reg_overlap_2230, 2, vd); + setArg(call_valid_reg_overlap_2230, 3, valid_reg_overlap_2230_arg2); + setArg(call_valid_reg_overlap_2230, 4, valid_reg_overlap_2230_arg3); + setRet(call_valid_reg_overlap_2230, 0, ret_val_valid_reg_overlap_2230); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2231; + auto vector_extend_2231_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2231_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2231_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2231_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2231, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2231, 0, V); + setArg(call_vector_extend_2231, 1, 4); + setArg(call_vector_extend_2231, 2, vector_extend_2231_arg2); + setArg(call_vector_extend_2231, 3, vector_extend_2231_arg3); + setArg(call_vector_extend_2231, 4, vector_extend_2231_arg4); + setArg(call_vector_extend_2231, 5, vm); + setArg(call_vector_extend_2231, 6, vd); + setArg(call_vector_extend_2231, 7, vs2); + setArg(call_vector_extend_2231, 8, vector_extend_2231_arg8); + setArg(call_vector_extend_2231, 9, 2); + } + cc.bind(label_merge); + } + auto tmp2232 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2232, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2232, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 538); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 539: VSEXT__VF4 */ + continuation_e __vsext__vf4(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf4"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSEXT__VF4_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 539); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2233; + x86::Gp ret_val_get_sew_pow_2233 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2233, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2233; + setArg(call_get_sew_pow_2233, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2233, 0, ret_val_get_sew_pow_2233); + auto tmp2234 = get_reg(cc, 8, false); + mov(cc, tmp2234, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2234, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2235; + x86::Gp ret_val_get_lmul_pow_2235 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2235, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2235; + setArg(call_get_lmul_pow_2235, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2235, 0, ret_val_get_lmul_pow_2235); + auto SEW_target = gen_operation(cc, udiv, SEW, 4); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 2); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2236; + auto illegal_variable_width_2236_arg2 = SEW_target; + auto illegal_variable_width_2236_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2236 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2236, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2237; + auto valid_reg_overlap_2237_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2237_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2237 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2237, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2236, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2237)); + setArg(call_illegal_variable_width_2236, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2236, 1, vd); + setArg(call_illegal_variable_width_2236, 2, vm); + setArg(call_illegal_variable_width_2236, 3, illegal_variable_width_2236_arg2); + setArg(call_illegal_variable_width_2236, 4, illegal_variable_width_2236_arg3); + setRet(call_illegal_variable_width_2236, 0, ret_val_illegal_variable_width_2236); + setArg(call_valid_reg_overlap_2237, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2237, 1, vs2); + setArg(call_valid_reg_overlap_2237, 2, vd); + setArg(call_valid_reg_overlap_2237, 3, valid_reg_overlap_2237_arg2); + setArg(call_valid_reg_overlap_2237, 4, valid_reg_overlap_2237_arg3); + setRet(call_valid_reg_overlap_2237, 0, ret_val_valid_reg_overlap_2237); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2238; + auto vector_extend_2238_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2238_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2238_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2238_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2238, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2238, 0, V); + setArg(call_vector_extend_2238, 1, 5); + setArg(call_vector_extend_2238, 2, vector_extend_2238_arg2); + setArg(call_vector_extend_2238, 3, vector_extend_2238_arg3); + setArg(call_vector_extend_2238, 4, vector_extend_2238_arg4); + setArg(call_vector_extend_2238, 5, vm); + setArg(call_vector_extend_2238, 6, vd); + setArg(call_vector_extend_2238, 7, vs2); + setArg(call_vector_extend_2238, 8, vector_extend_2238_arg8); + setArg(call_vector_extend_2238, 9, 2); + } + cc.bind(label_merge); + } + auto tmp2239 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2239, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2239, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 539); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 540: VZEXT__VF8 */ + continuation_e __vzext__vf8(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vzext.vf8"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VZEXT__VF8_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 540); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2240; + x86::Gp ret_val_get_sew_pow_2240 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2240, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2240; + setArg(call_get_sew_pow_2240, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2240, 0, ret_val_get_sew_pow_2240); + auto tmp2241 = get_reg(cc, 8, false); + mov(cc, tmp2241, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2241, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2242; + x86::Gp ret_val_get_lmul_pow_2242 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2242, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2242; + setArg(call_get_lmul_pow_2242, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2242, 0, ret_val_get_lmul_pow_2242); + auto SEW_target = gen_operation(cc, udiv, SEW, 8); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 3); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2243; + auto illegal_variable_width_2243_arg2 = SEW_target; + auto illegal_variable_width_2243_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2243 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2243, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2244; + auto valid_reg_overlap_2244_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2244_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2244 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2244, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2243, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2244)); + setArg(call_illegal_variable_width_2243, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2243, 1, vd); + setArg(call_illegal_variable_width_2243, 2, vm); + setArg(call_illegal_variable_width_2243, 3, illegal_variable_width_2243_arg2); + setArg(call_illegal_variable_width_2243, 4, illegal_variable_width_2243_arg3); + setRet(call_illegal_variable_width_2243, 0, ret_val_illegal_variable_width_2243); + setArg(call_valid_reg_overlap_2244, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2244, 1, vs2); + setArg(call_valid_reg_overlap_2244, 2, vd); + setArg(call_valid_reg_overlap_2244, 3, valid_reg_overlap_2244_arg2); + setArg(call_valid_reg_overlap_2244, 4, valid_reg_overlap_2244_arg3); + setRet(call_valid_reg_overlap_2244, 0, ret_val_valid_reg_overlap_2244); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2245; + auto vector_extend_2245_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2245_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2245_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2245_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2245, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2245, 0, V); + setArg(call_vector_extend_2245, 1, 2); + setArg(call_vector_extend_2245, 2, vector_extend_2245_arg2); + setArg(call_vector_extend_2245, 3, vector_extend_2245_arg3); + setArg(call_vector_extend_2245, 4, vector_extend_2245_arg4); + setArg(call_vector_extend_2245, 5, vm); + setArg(call_vector_extend_2245, 6, vd); + setArg(call_vector_extend_2245, 7, vs2); + setArg(call_vector_extend_2245, 8, vector_extend_2245_arg8); + setArg(call_vector_extend_2245, 9, 3); + } + cc.bind(label_merge); + } + auto tmp2246 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2246, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2246, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 540); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 541: VSEXT__VF8 */ + continuation_e __vsext__vf8(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vsext.vf8"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSEXT__VF8_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 541); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2247; + x86::Gp ret_val_get_sew_pow_2247 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2247, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto SEW_pow = ret_val_get_sew_pow_2247; + setArg(call_get_sew_pow_2247, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2247, 0, ret_val_get_sew_pow_2247); + auto tmp2248 = get_reg(cc, 8, false); + mov(cc, tmp2248, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2248, SEW_pow)), 5, false), ~ 1); + InvokeNode* call_get_lmul_pow_2249; + x86::Gp ret_val_get_lmul_pow_2249 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2249, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2249; + setArg(call_get_lmul_pow_2249, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2249, 0, ret_val_get_lmul_pow_2249); + auto SEW_target = gen_operation(cc, udiv, SEW, 8); + auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 3); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2250; + auto illegal_variable_width_2250_arg2 = SEW_target; + auto illegal_variable_width_2250_arg3 = LMUL_pow_target; + x86::Gp ret_val_illegal_variable_width_2250 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2250, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2251; + auto valid_reg_overlap_2251_arg2 = LMUL_pow_target; + auto valid_reg_overlap_2251_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2251 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2251, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2250, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2251)); + setArg(call_illegal_variable_width_2250, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2250, 1, vd); + setArg(call_illegal_variable_width_2250, 2, vm); + setArg(call_illegal_variable_width_2250, 3, illegal_variable_width_2250_arg2); + setArg(call_illegal_variable_width_2250, 4, illegal_variable_width_2250_arg3); + setRet(call_illegal_variable_width_2250, 0, ret_val_illegal_variable_width_2250); + setArg(call_valid_reg_overlap_2251, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2251, 1, vs2); + setArg(call_valid_reg_overlap_2251, 2, vd); + setArg(call_valid_reg_overlap_2251, 3, valid_reg_overlap_2251_arg2); + setArg(call_valid_reg_overlap_2251, 4, valid_reg_overlap_2251_arg3); + setRet(call_valid_reg_overlap_2251, 0, ret_val_valid_reg_overlap_2251); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_vector_extend_2252; + auto vector_extend_2252_arg2 = load_reg_from_mem(jh, traits::vl); + auto vector_extend_2252_arg3 = load_reg_from_mem(jh, traits::vstart); + auto vector_extend_2252_arg4 = load_reg_from_mem(jh, traits::vtype); + auto vector_extend_2252_arg8 = SEW_pow; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_extend_2252, &vector_extend, FuncSignature::build()); + setArg(call_vector_extend_2252, 0, V); + setArg(call_vector_extend_2252, 1, 3); + setArg(call_vector_extend_2252, 2, vector_extend_2252_arg2); + setArg(call_vector_extend_2252, 3, vector_extend_2252_arg3); + setArg(call_vector_extend_2252, 4, vector_extend_2252_arg4); + setArg(call_vector_extend_2252, 5, vm); + setArg(call_vector_extend_2252, 6, vd); + setArg(call_vector_extend_2252, 7, vs2); + setArg(call_vector_extend_2252, 8, vector_extend_2252_arg8); + setArg(call_vector_extend_2252, 9, 3); + } + cc.bind(label_merge); + } + auto tmp2253 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2253, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2253, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 541); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 542: VADC__VVM */ + continuation_e __vadc__vvm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vadc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADC__VVM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 542); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2254; + x86::Gp ret_val_illegal_vd_masked_2254 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2254, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_masked_2254; + setArg(call_illegal_vd_masked_2254, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2254, 1, vd); + setRet(call_illegal_vd_masked_2254, 0, ret_val_illegal_vd_masked_2254); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2256; + x86::Gp ret_val_sew_2256 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2256, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_carry_2255; + auto vector_vector_carry_2255_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_carry_2255_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_carry_2255_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_carry_2255_arg9 = ret_val_sew_2256; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_carry_2255, &vector_vector_carry, FuncSignature::build()); + setArg(call_sew_2256, 0, reinterpret_cast(this)); + setRet(call_sew_2256, 0, ret_val_sew_2256); + setArg(call_vector_vector_carry_2255, 0, V); + setArg(call_vector_vector_carry_2255, 1, 16); + setArg(call_vector_vector_carry_2255, 2, 0); + setArg(call_vector_vector_carry_2255, 3, vector_vector_carry_2255_arg3); + setArg(call_vector_vector_carry_2255, 4, vector_vector_carry_2255_arg4); + setArg(call_vector_vector_carry_2255, 5, vector_vector_carry_2255_arg5); + setArg(call_vector_vector_carry_2255, 6, vd); + setArg(call_vector_vector_carry_2255, 7, vs2); + setArg(call_vector_vector_carry_2255, 8, vs1); + setArg(call_vector_vector_carry_2255, 9, vector_vector_carry_2255_arg9); + setArg(call_vector_vector_carry_2255, 10, 1); + } + cc.bind(label_merge); + } + auto tmp2257 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2257, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2257, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 542); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 543: VADC__VXM */ + continuation_e __vadc__vxm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vadc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADC__VXM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 543); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2258; + x86::Gp ret_val_illegal_vd_masked_2258 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2258, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto tmp2259 = get_reg(cc, 8, false); + mov(cc, tmp2259, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2259, ret_val_illegal_vd_masked_2258); + setArg(call_illegal_vd_masked_2258, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2258, 1, vd); + setRet(call_illegal_vd_masked_2258, 0, ret_val_illegal_vd_masked_2258); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2261; + x86::Gp ret_val_sew_2261 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2261, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_carry_2260; + auto vector_imm_carry_2260_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_carry_2260_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_carry_2260_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_carry_2260_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_carry_2260_arg9 = ret_val_sew_2261; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_carry_2260, &vector_imm_carry, FuncSignature::build()); + setArg(call_sew_2261, 0, reinterpret_cast(this)); + setRet(call_sew_2261, 0, ret_val_sew_2261); + setArg(call_vector_imm_carry_2260, 0, V); + setArg(call_vector_imm_carry_2260, 1, 16); + setArg(call_vector_imm_carry_2260, 2, 4); + setArg(call_vector_imm_carry_2260, 3, vector_imm_carry_2260_arg3); + setArg(call_vector_imm_carry_2260, 4, vector_imm_carry_2260_arg4); + setArg(call_vector_imm_carry_2260, 5, vector_imm_carry_2260_arg5); + setArg(call_vector_imm_carry_2260, 6, vd); + setArg(call_vector_imm_carry_2260, 7, vs2); + setArg(call_vector_imm_carry_2260, 8, vector_imm_carry_2260_arg8); + setArg(call_vector_imm_carry_2260, 9, vector_imm_carry_2260_arg9); + setArg(call_vector_imm_carry_2260, 10, 1); + } + cc.bind(label_merge); + } + auto tmp2262 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2262, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2262, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 543); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 544: VADC__VIM */ + continuation_e __vadc__vim(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, v0", fmt::arg("mnemonic", "vadc.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VADC__VIM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 544); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2263; + x86::Gp ret_val_illegal_vd_unmasked_2263 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2263, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2263; + setArg(call_illegal_vd_unmasked_2263, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2263, 0, ret_val_illegal_vd_unmasked_2263); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2265; + x86::Gp ret_val_sew_2265 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2265, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_carry_2264; + auto vector_imm_carry_2264_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_carry_2264_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_carry_2264_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_carry_2264_arg9 = ret_val_sew_2265; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_carry_2264, &vector_imm_carry, FuncSignature::build()); + setArg(call_sew_2265, 0, reinterpret_cast(this)); + setRet(call_sew_2265, 0, ret_val_sew_2265); + setArg(call_vector_imm_carry_2264, 0, V); + setArg(call_vector_imm_carry_2264, 1, 16); + setArg(call_vector_imm_carry_2264, 2, 3); + setArg(call_vector_imm_carry_2264, 3, vector_imm_carry_2264_arg3); + setArg(call_vector_imm_carry_2264, 4, vector_imm_carry_2264_arg4); + setArg(call_vector_imm_carry_2264, 5, vector_imm_carry_2264_arg5); + setArg(call_vector_imm_carry_2264, 6, vd); + setArg(call_vector_imm_carry_2264, 7, vs2); + setArg(call_vector_imm_carry_2264, 8, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_carry_2264, 9, vector_imm_carry_2264_arg9); + setArg(call_vector_imm_carry_2264, 10, 1); + } + cc.bind(label_merge); + } + auto tmp2266 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2266, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2266, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 544); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 545: VMADC__VVM */ + continuation_e __vmadc__vvm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vmadc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VVM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 545); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2267; + x86::Gp ret_val_illegal_vd_unmasked_2267 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2267, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2267; + setArg(call_illegal_vd_unmasked_2267, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2267, 0, ret_val_illegal_vd_unmasked_2267); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2269; + x86::Gp ret_val_sew_2269 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2269, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_vector_op_2268; + auto carry_vector_vector_op_2268_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_vector_op_2268_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_vector_op_2268_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_vector_op_2268_arg9 = ret_val_sew_2269; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_vector_op_2268, &carry_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2269, 0, reinterpret_cast(this)); + setRet(call_sew_2269, 0, ret_val_sew_2269); + setArg(call_carry_vector_vector_op_2268, 0, V); + setArg(call_carry_vector_vector_op_2268, 1, 17); + setArg(call_carry_vector_vector_op_2268, 2, carry_vector_vector_op_2268_arg2); + setArg(call_carry_vector_vector_op_2268, 3, carry_vector_vector_op_2268_arg3); + setArg(call_carry_vector_vector_op_2268, 4, carry_vector_vector_op_2268_arg4); + setArg(call_carry_vector_vector_op_2268, 5, 0); + setArg(call_carry_vector_vector_op_2268, 6, vd); + setArg(call_carry_vector_vector_op_2268, 7, vs2); + setArg(call_carry_vector_vector_op_2268, 8, vs1); + setArg(call_carry_vector_vector_op_2268, 9, carry_vector_vector_op_2268_arg9); + } + cc.bind(label_merge); + } + auto tmp2270 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2270, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2270, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 545); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 546: VMADC__VXM */ + continuation_e __vmadc__vxm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vmadc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VXM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 546); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2271; + x86::Gp ret_val_illegal_vd_unmasked_2271 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2271, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2272 = get_reg(cc, 8, false); + mov(cc, tmp2272, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2272, ret_val_illegal_vd_unmasked_2271); + setArg(call_illegal_vd_unmasked_2271, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2271, 0, ret_val_illegal_vd_unmasked_2271); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2274; + x86::Gp ret_val_sew_2274 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2274, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2273; + auto carry_vector_imm_op_2273_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2273_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2273_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2273_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto carry_vector_imm_op_2273_arg9 = ret_val_sew_2274; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2273, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2274, 0, reinterpret_cast(this)); + setRet(call_sew_2274, 0, ret_val_sew_2274); + setArg(call_carry_vector_imm_op_2273, 0, V); + setArg(call_carry_vector_imm_op_2273, 1, 17); + setArg(call_carry_vector_imm_op_2273, 2, carry_vector_imm_op_2273_arg2); + setArg(call_carry_vector_imm_op_2273, 3, carry_vector_imm_op_2273_arg3); + setArg(call_carry_vector_imm_op_2273, 4, carry_vector_imm_op_2273_arg4); + setArg(call_carry_vector_imm_op_2273, 5, 0); + setArg(call_carry_vector_imm_op_2273, 6, vd); + setArg(call_carry_vector_imm_op_2273, 7, vs2); + setArg(call_carry_vector_imm_op_2273, 8, carry_vector_imm_op_2273_arg8); + setArg(call_carry_vector_imm_op_2273, 9, carry_vector_imm_op_2273_arg9); + } + cc.bind(label_merge); + } + auto tmp2275 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2275, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2275, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 546); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 547: VMADC__VIM */ + continuation_e __vmadc__vim(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, v0", fmt::arg("mnemonic", "vmadc.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VIM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 547); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2276; + x86::Gp ret_val_illegal_vd_unmasked_2276 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2276, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2276; + setArg(call_illegal_vd_unmasked_2276, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2276, 0, ret_val_illegal_vd_unmasked_2276); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2278; + x86::Gp ret_val_sew_2278 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2278, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2277; + auto carry_vector_imm_op_2277_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2277_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2277_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2277_arg9 = ret_val_sew_2278; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2277, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2278, 0, reinterpret_cast(this)); + setRet(call_sew_2278, 0, ret_val_sew_2278); + setArg(call_carry_vector_imm_op_2277, 0, V); + setArg(call_carry_vector_imm_op_2277, 1, 17); + setArg(call_carry_vector_imm_op_2277, 2, carry_vector_imm_op_2277_arg2); + setArg(call_carry_vector_imm_op_2277, 3, carry_vector_imm_op_2277_arg3); + setArg(call_carry_vector_imm_op_2277, 4, carry_vector_imm_op_2277_arg4); + setArg(call_carry_vector_imm_op_2277, 5, 0); + setArg(call_carry_vector_imm_op_2277, 6, vd); + setArg(call_carry_vector_imm_op_2277, 7, vs2); + setArg(call_carry_vector_imm_op_2277, 8, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_carry_vector_imm_op_2277, 9, carry_vector_imm_op_2277_arg9); + } + cc.bind(label_merge); + } + auto tmp2279 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2279, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2279, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 547); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 548: VMADC__VV */ + continuation_e __vmadc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmadc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 548); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2280; + x86::Gp ret_val_illegal_vd_unmasked_2280 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2280, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2280; + setArg(call_illegal_vd_unmasked_2280, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2280, 0, ret_val_illegal_vd_unmasked_2280); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2282; + x86::Gp ret_val_sew_2282 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2282, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_vector_op_2281; + auto carry_vector_vector_op_2281_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_vector_op_2281_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_vector_op_2281_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_vector_op_2281_arg9 = ret_val_sew_2282; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_vector_op_2281, &carry_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2282, 0, reinterpret_cast(this)); + setRet(call_sew_2282, 0, ret_val_sew_2282); + setArg(call_carry_vector_vector_op_2281, 0, V); + setArg(call_carry_vector_vector_op_2281, 1, 17); + setArg(call_carry_vector_vector_op_2281, 2, carry_vector_vector_op_2281_arg2); + setArg(call_carry_vector_vector_op_2281, 3, carry_vector_vector_op_2281_arg3); + setArg(call_carry_vector_vector_op_2281, 4, carry_vector_vector_op_2281_arg4); + setArg(call_carry_vector_vector_op_2281, 5, 1); + setArg(call_carry_vector_vector_op_2281, 6, vd); + setArg(call_carry_vector_vector_op_2281, 7, vs2); + setArg(call_carry_vector_vector_op_2281, 8, vs1); + setArg(call_carry_vector_vector_op_2281, 9, carry_vector_vector_op_2281_arg9); + } + cc.bind(label_merge); + } + auto tmp2283 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2283, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2283, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 548); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 549: VMADC__VX */ + continuation_e __vmadc__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmadc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 549); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2284; + x86::Gp ret_val_illegal_vd_unmasked_2284 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2284, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2285 = get_reg(cc, 8, false); + mov(cc, tmp2285, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2285, ret_val_illegal_vd_unmasked_2284); + setArg(call_illegal_vd_unmasked_2284, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2284, 0, ret_val_illegal_vd_unmasked_2284); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2287; + x86::Gp ret_val_sew_2287 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2287, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2286; + auto carry_vector_imm_op_2286_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2286_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2286_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2286_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto carry_vector_imm_op_2286_arg9 = ret_val_sew_2287; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2286, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2287, 0, reinterpret_cast(this)); + setRet(call_sew_2287, 0, ret_val_sew_2287); + setArg(call_carry_vector_imm_op_2286, 0, V); + setArg(call_carry_vector_imm_op_2286, 1, 17); + setArg(call_carry_vector_imm_op_2286, 2, carry_vector_imm_op_2286_arg2); + setArg(call_carry_vector_imm_op_2286, 3, carry_vector_imm_op_2286_arg3); + setArg(call_carry_vector_imm_op_2286, 4, carry_vector_imm_op_2286_arg4); + setArg(call_carry_vector_imm_op_2286, 5, 1); + setArg(call_carry_vector_imm_op_2286, 6, vd); + setArg(call_carry_vector_imm_op_2286, 7, vs2); + setArg(call_carry_vector_imm_op_2286, 8, carry_vector_imm_op_2286_arg8); + setArg(call_carry_vector_imm_op_2286, 9, carry_vector_imm_op_2286_arg9); + } + cc.bind(label_merge); + } + auto tmp2288 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2288, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2288, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 549); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 550: VMADC__VI */ + continuation_e __vmadc__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}", fmt::arg("mnemonic", "vmadc.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADC__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 550); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2289; + x86::Gp ret_val_illegal_vd_unmasked_2289 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2289, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2289; + setArg(call_illegal_vd_unmasked_2289, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2289, 0, ret_val_illegal_vd_unmasked_2289); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2291; + x86::Gp ret_val_sew_2291 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2291, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2290; + auto carry_vector_imm_op_2290_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2290_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2290_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2290_arg9 = ret_val_sew_2291; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2290, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2291, 0, reinterpret_cast(this)); + setRet(call_sew_2291, 0, ret_val_sew_2291); + setArg(call_carry_vector_imm_op_2290, 0, V); + setArg(call_carry_vector_imm_op_2290, 1, 17); + setArg(call_carry_vector_imm_op_2290, 2, carry_vector_imm_op_2290_arg2); + setArg(call_carry_vector_imm_op_2290, 3, carry_vector_imm_op_2290_arg3); + setArg(call_carry_vector_imm_op_2290, 4, carry_vector_imm_op_2290_arg4); + setArg(call_carry_vector_imm_op_2290, 5, 1); + setArg(call_carry_vector_imm_op_2290, 6, vd); + setArg(call_carry_vector_imm_op_2290, 7, vs2); + setArg(call_carry_vector_imm_op_2290, 8, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_carry_vector_imm_op_2290, 9, carry_vector_imm_op_2290_arg9); + } + cc.bind(label_merge); + } + auto tmp2292 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2292, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2292, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 550); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 551: VSBC__VVM */ + continuation_e __vsbc__vvm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vsbc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSBC__VVM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 551); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2293; + x86::Gp ret_val_illegal_vd_masked_2293 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2293, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_masked_2293; + setArg(call_illegal_vd_masked_2293, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2293, 1, vd); + setRet(call_illegal_vd_masked_2293, 0, ret_val_illegal_vd_masked_2293); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2295; + x86::Gp ret_val_sew_2295 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2295, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_carry_2294; + auto vector_vector_carry_2294_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_carry_2294_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_carry_2294_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_carry_2294_arg9 = ret_val_sew_2295; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_carry_2294, &vector_vector_carry, FuncSignature::build()); + setArg(call_sew_2295, 0, reinterpret_cast(this)); + setRet(call_sew_2295, 0, ret_val_sew_2295); + setArg(call_vector_vector_carry_2294, 0, V); + setArg(call_vector_vector_carry_2294, 1, 18); + setArg(call_vector_vector_carry_2294, 2, 0); + setArg(call_vector_vector_carry_2294, 3, vector_vector_carry_2294_arg3); + setArg(call_vector_vector_carry_2294, 4, vector_vector_carry_2294_arg4); + setArg(call_vector_vector_carry_2294, 5, vector_vector_carry_2294_arg5); + setArg(call_vector_vector_carry_2294, 6, vd); + setArg(call_vector_vector_carry_2294, 7, vs2); + setArg(call_vector_vector_carry_2294, 8, vs1); + setArg(call_vector_vector_carry_2294, 9, vector_vector_carry_2294_arg9); + setArg(call_vector_vector_carry_2294, 10, - 1); + } + cc.bind(label_merge); + } + auto tmp2296 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2296, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2296, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 551); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 552: VSBC__VXM */ + continuation_e __vsbc__vxm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vsbc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSBC__VXM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 552); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2297; + x86::Gp ret_val_illegal_vd_masked_2297 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2297, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto tmp2298 = get_reg(cc, 8, false); + mov(cc, tmp2298, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2298, ret_val_illegal_vd_masked_2297); + setArg(call_illegal_vd_masked_2297, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2297, 1, vd); + setRet(call_illegal_vd_masked_2297, 0, ret_val_illegal_vd_masked_2297); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2300; + x86::Gp ret_val_sew_2300 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2300, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_carry_2299; + auto vector_imm_carry_2299_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_carry_2299_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_carry_2299_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_carry_2299_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_carry_2299_arg9 = ret_val_sew_2300; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_carry_2299, &vector_imm_carry, FuncSignature::build()); + setArg(call_sew_2300, 0, reinterpret_cast(this)); + setRet(call_sew_2300, 0, ret_val_sew_2300); + setArg(call_vector_imm_carry_2299, 0, V); + setArg(call_vector_imm_carry_2299, 1, 18); + setArg(call_vector_imm_carry_2299, 2, 4); + setArg(call_vector_imm_carry_2299, 3, vector_imm_carry_2299_arg3); + setArg(call_vector_imm_carry_2299, 4, vector_imm_carry_2299_arg4); + setArg(call_vector_imm_carry_2299, 5, vector_imm_carry_2299_arg5); + setArg(call_vector_imm_carry_2299, 6, vd); + setArg(call_vector_imm_carry_2299, 7, vs2); + setArg(call_vector_imm_carry_2299, 8, vector_imm_carry_2299_arg8); + setArg(call_vector_imm_carry_2299, 9, vector_imm_carry_2299_arg9); + setArg(call_vector_imm_carry_2299, 10, - 1); + } + cc.bind(label_merge); + } + auto tmp2301 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2301, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2301, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 552); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 553: VMSBC__VVM */ + continuation_e __vmsbc__vvm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, v0", fmt::arg("mnemonic", "vmsbc.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSBC__VVM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 553); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2302; + x86::Gp ret_val_illegal_vd_unmasked_2302 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2302, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2302; + setArg(call_illegal_vd_unmasked_2302, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2302, 0, ret_val_illegal_vd_unmasked_2302); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2304; + x86::Gp ret_val_sew_2304 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2304, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_vector_op_2303; + auto carry_vector_vector_op_2303_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_vector_op_2303_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_vector_op_2303_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_vector_op_2303_arg9 = ret_val_sew_2304; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_vector_op_2303, &carry_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2304, 0, reinterpret_cast(this)); + setRet(call_sew_2304, 0, ret_val_sew_2304); + setArg(call_carry_vector_vector_op_2303, 0, V); + setArg(call_carry_vector_vector_op_2303, 1, 19); + setArg(call_carry_vector_vector_op_2303, 2, carry_vector_vector_op_2303_arg2); + setArg(call_carry_vector_vector_op_2303, 3, carry_vector_vector_op_2303_arg3); + setArg(call_carry_vector_vector_op_2303, 4, carry_vector_vector_op_2303_arg4); + setArg(call_carry_vector_vector_op_2303, 5, 0); + setArg(call_carry_vector_vector_op_2303, 6, vd); + setArg(call_carry_vector_vector_op_2303, 7, vs2); + setArg(call_carry_vector_vector_op_2303, 8, vs1); + setArg(call_carry_vector_vector_op_2303, 9, carry_vector_vector_op_2303_arg9); + } + cc.bind(label_merge); + } + auto tmp2305 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2305, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2305, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 553); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 554: VMSBC__VXM */ + continuation_e __vmsbc__vxm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, v0", fmt::arg("mnemonic", "vmsbc.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSBC__VXM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 554); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2306; + x86::Gp ret_val_illegal_vd_unmasked_2306 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2306, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2307 = get_reg(cc, 8, false); + mov(cc, tmp2307, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2307, ret_val_illegal_vd_unmasked_2306); + setArg(call_illegal_vd_unmasked_2306, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2306, 0, ret_val_illegal_vd_unmasked_2306); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2309; + x86::Gp ret_val_sew_2309 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2309, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2308; + auto carry_vector_imm_op_2308_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2308_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2308_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2308_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto carry_vector_imm_op_2308_arg9 = ret_val_sew_2309; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2308, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2309, 0, reinterpret_cast(this)); + setRet(call_sew_2309, 0, ret_val_sew_2309); + setArg(call_carry_vector_imm_op_2308, 0, V); + setArg(call_carry_vector_imm_op_2308, 1, 19); + setArg(call_carry_vector_imm_op_2308, 2, carry_vector_imm_op_2308_arg2); + setArg(call_carry_vector_imm_op_2308, 3, carry_vector_imm_op_2308_arg3); + setArg(call_carry_vector_imm_op_2308, 4, carry_vector_imm_op_2308_arg4); + setArg(call_carry_vector_imm_op_2308, 5, 0); + setArg(call_carry_vector_imm_op_2308, 6, vd); + setArg(call_carry_vector_imm_op_2308, 7, vs2); + setArg(call_carry_vector_imm_op_2308, 8, carry_vector_imm_op_2308_arg8); + setArg(call_carry_vector_imm_op_2308, 9, carry_vector_imm_op_2308_arg9); + } + cc.bind(label_merge); + } + auto tmp2310 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2310, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2310, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 554); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 555: VMSBC__VV */ + continuation_e __vmsbc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmsbc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSBC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 555); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2311; + x86::Gp ret_val_illegal_vd_unmasked_2311 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2311, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2311; + setArg(call_illegal_vd_unmasked_2311, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2311, 0, ret_val_illegal_vd_unmasked_2311); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2313; + x86::Gp ret_val_sew_2313 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2313, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_vector_op_2312; + auto carry_vector_vector_op_2312_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_vector_op_2312_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_vector_op_2312_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_vector_op_2312_arg9 = ret_val_sew_2313; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_vector_op_2312, &carry_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2313, 0, reinterpret_cast(this)); + setRet(call_sew_2313, 0, ret_val_sew_2313); + setArg(call_carry_vector_vector_op_2312, 0, V); + setArg(call_carry_vector_vector_op_2312, 1, 19); + setArg(call_carry_vector_vector_op_2312, 2, carry_vector_vector_op_2312_arg2); + setArg(call_carry_vector_vector_op_2312, 3, carry_vector_vector_op_2312_arg3); + setArg(call_carry_vector_vector_op_2312, 4, carry_vector_vector_op_2312_arg4); + setArg(call_carry_vector_vector_op_2312, 5, 1); + setArg(call_carry_vector_vector_op_2312, 6, vd); + setArg(call_carry_vector_vector_op_2312, 7, vs2); + setArg(call_carry_vector_vector_op_2312, 8, vs1); + setArg(call_carry_vector_vector_op_2312, 9, carry_vector_vector_op_2312_arg9); + } + cc.bind(label_merge); + } + auto tmp2314 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2314, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2314, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 555); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 556: VMSBC__VX */ + continuation_e __vmsbc__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmsbc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSBC__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 556); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2315; + x86::Gp ret_val_illegal_vd_unmasked_2315 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2315, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2316 = get_reg(cc, 8, false); + mov(cc, tmp2316, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2316, ret_val_illegal_vd_unmasked_2315); + setArg(call_illegal_vd_unmasked_2315, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2315, 0, ret_val_illegal_vd_unmasked_2315); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2318; + x86::Gp ret_val_sew_2318 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2318, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_carry_vector_imm_op_2317; + auto carry_vector_imm_op_2317_arg2 = load_reg_from_mem(jh, traits::vl); + auto carry_vector_imm_op_2317_arg3 = load_reg_from_mem(jh, traits::vstart); + auto carry_vector_imm_op_2317_arg4 = load_reg_from_mem(jh, traits::vtype); + auto carry_vector_imm_op_2317_arg8 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto carry_vector_imm_op_2317_arg9 = ret_val_sew_2318; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_carry_vector_imm_op_2317, &carry_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2318, 0, reinterpret_cast(this)); + setRet(call_sew_2318, 0, ret_val_sew_2318); + setArg(call_carry_vector_imm_op_2317, 0, V); + setArg(call_carry_vector_imm_op_2317, 1, 19); + setArg(call_carry_vector_imm_op_2317, 2, carry_vector_imm_op_2317_arg2); + setArg(call_carry_vector_imm_op_2317, 3, carry_vector_imm_op_2317_arg3); + setArg(call_carry_vector_imm_op_2317, 4, carry_vector_imm_op_2317_arg4); + setArg(call_carry_vector_imm_op_2317, 5, 1); + setArg(call_carry_vector_imm_op_2317, 6, vd); + setArg(call_carry_vector_imm_op_2317, 7, vs2); + setArg(call_carry_vector_imm_op_2317, 8, carry_vector_imm_op_2317_arg8); + setArg(call_carry_vector_imm_op_2317, 9, carry_vector_imm_op_2317_arg9); + } + cc.bind(label_merge); + } + auto tmp2319 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2319, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2319, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 556); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 557: VAND__VI */ + continuation_e __vand__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vand.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAND__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 557); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2320; + x86::Gp ret_val_illegal_normal_2320 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2320, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2320; + setArg(call_illegal_normal_2320, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2320, 1, vd); + setArg(call_illegal_normal_2320, 2, vm); + setRet(call_illegal_normal_2320, 0, ret_val_illegal_normal_2320); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2322; + x86::Gp ret_val_sew_2322 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2322, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2321; + auto vector_imm_op_2321_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2321_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2321_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2321_arg10 = ret_val_sew_2322; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2321, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2322, 0, reinterpret_cast(this)); + setRet(call_sew_2322, 0, ret_val_sew_2322); + setArg(call_vector_imm_op_2321, 0, V); + setArg(call_vector_imm_op_2321, 1, 9); + setArg(call_vector_imm_op_2321, 2, 3); + setArg(call_vector_imm_op_2321, 3, vector_imm_op_2321_arg3); + setArg(call_vector_imm_op_2321, 4, vector_imm_op_2321_arg4); + setArg(call_vector_imm_op_2321, 5, vector_imm_op_2321_arg5); + setArg(call_vector_imm_op_2321, 6, vm); + setArg(call_vector_imm_op_2321, 7, vd); + setArg(call_vector_imm_op_2321, 8, vs2); + setArg(call_vector_imm_op_2321, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_op_2321, 10, vector_imm_op_2321_arg10); + } + cc.bind(label_merge); + } + auto tmp2323 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2323, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2323, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 557); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 558: VAND__VV */ + continuation_e __vand__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vand.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAND__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 558); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2324; + x86::Gp ret_val_illegal_normal_2324 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2324, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2324; + setArg(call_illegal_normal_2324, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2324, 1, vd); + setArg(call_illegal_normal_2324, 2, vm); + setRet(call_illegal_normal_2324, 0, ret_val_illegal_normal_2324); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2326; + x86::Gp ret_val_sew_2326 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2326, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2325; + auto vector_vector_op_2325_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2325_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2325_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2325_arg10 = ret_val_sew_2326; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2325, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2326, 0, reinterpret_cast(this)); + setRet(call_sew_2326, 0, ret_val_sew_2326); + setArg(call_vector_vector_op_2325, 0, V); + setArg(call_vector_vector_op_2325, 1, 9); + setArg(call_vector_vector_op_2325, 2, 0); + setArg(call_vector_vector_op_2325, 3, vector_vector_op_2325_arg3); + setArg(call_vector_vector_op_2325, 4, vector_vector_op_2325_arg4); + setArg(call_vector_vector_op_2325, 5, vector_vector_op_2325_arg5); + setArg(call_vector_vector_op_2325, 6, vm); + setArg(call_vector_vector_op_2325, 7, vd); + setArg(call_vector_vector_op_2325, 8, vs2); + setArg(call_vector_vector_op_2325, 9, vs1); + setArg(call_vector_vector_op_2325, 10, vector_vector_op_2325_arg10); + } + cc.bind(label_merge); + } + auto tmp2327 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2327, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2327, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 558); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 559: VAND__VX */ + continuation_e __vand__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vand.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAND__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 559); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2328; + x86::Gp ret_val_illegal_normal_2328 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2328, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2329 = get_reg(cc, 8, false); + mov(cc, tmp2329, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2329, ret_val_illegal_normal_2328); + setArg(call_illegal_normal_2328, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2328, 1, vd); + setArg(call_illegal_normal_2328, 2, vm); + setRet(call_illegal_normal_2328, 0, ret_val_illegal_normal_2328); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2331; + x86::Gp ret_val_sew_2331 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2331, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2330; + auto vector_imm_op_2330_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2330_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2330_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2330_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2330_arg10 = ret_val_sew_2331; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2330, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2331, 0, reinterpret_cast(this)); + setRet(call_sew_2331, 0, ret_val_sew_2331); + setArg(call_vector_imm_op_2330, 0, V); + setArg(call_vector_imm_op_2330, 1, 9); + setArg(call_vector_imm_op_2330, 2, 4); + setArg(call_vector_imm_op_2330, 3, vector_imm_op_2330_arg3); + setArg(call_vector_imm_op_2330, 4, vector_imm_op_2330_arg4); + setArg(call_vector_imm_op_2330, 5, vector_imm_op_2330_arg5); + setArg(call_vector_imm_op_2330, 6, vm); + setArg(call_vector_imm_op_2330, 7, vd); + setArg(call_vector_imm_op_2330, 8, vs2); + setArg(call_vector_imm_op_2330, 9, vector_imm_op_2330_arg9); + setArg(call_vector_imm_op_2330, 10, vector_imm_op_2330_arg10); + } + cc.bind(label_merge); + } + auto tmp2332 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2332, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2332, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 559); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 560: VOR__VI */ + continuation_e __vor__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vor.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VOR__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 560); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2333; + x86::Gp ret_val_illegal_normal_2333 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2333, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2333; + setArg(call_illegal_normal_2333, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2333, 1, vd); + setArg(call_illegal_normal_2333, 2, vm); + setRet(call_illegal_normal_2333, 0, ret_val_illegal_normal_2333); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2335; + x86::Gp ret_val_sew_2335 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2335, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2334; + auto vector_imm_op_2334_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2334_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2334_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2334_arg10 = ret_val_sew_2335; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2334, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2335, 0, reinterpret_cast(this)); + setRet(call_sew_2335, 0, ret_val_sew_2335); + setArg(call_vector_imm_op_2334, 0, V); + setArg(call_vector_imm_op_2334, 1, 10); + setArg(call_vector_imm_op_2334, 2, 3); + setArg(call_vector_imm_op_2334, 3, vector_imm_op_2334_arg3); + setArg(call_vector_imm_op_2334, 4, vector_imm_op_2334_arg4); + setArg(call_vector_imm_op_2334, 5, vector_imm_op_2334_arg5); + setArg(call_vector_imm_op_2334, 6, vm); + setArg(call_vector_imm_op_2334, 7, vd); + setArg(call_vector_imm_op_2334, 8, vs2); + setArg(call_vector_imm_op_2334, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_op_2334, 10, vector_imm_op_2334_arg10); + } + cc.bind(label_merge); + } + auto tmp2336 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2336, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2336, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 560); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 561: VOR__VV */ + continuation_e __vor__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vor.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VOR__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 561); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2337; + x86::Gp ret_val_illegal_normal_2337 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2337, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2337; + setArg(call_illegal_normal_2337, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2337, 1, vd); + setArg(call_illegal_normal_2337, 2, vm); + setRet(call_illegal_normal_2337, 0, ret_val_illegal_normal_2337); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2339; + x86::Gp ret_val_sew_2339 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2339, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2338; + auto vector_vector_op_2338_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2338_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2338_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2338_arg10 = ret_val_sew_2339; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2338, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2339, 0, reinterpret_cast(this)); + setRet(call_sew_2339, 0, ret_val_sew_2339); + setArg(call_vector_vector_op_2338, 0, V); + setArg(call_vector_vector_op_2338, 1, 10); + setArg(call_vector_vector_op_2338, 2, 0); + setArg(call_vector_vector_op_2338, 3, vector_vector_op_2338_arg3); + setArg(call_vector_vector_op_2338, 4, vector_vector_op_2338_arg4); + setArg(call_vector_vector_op_2338, 5, vector_vector_op_2338_arg5); + setArg(call_vector_vector_op_2338, 6, vm); + setArg(call_vector_vector_op_2338, 7, vd); + setArg(call_vector_vector_op_2338, 8, vs2); + setArg(call_vector_vector_op_2338, 9, vs1); + setArg(call_vector_vector_op_2338, 10, vector_vector_op_2338_arg10); + } + cc.bind(label_merge); + } + auto tmp2340 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2340, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2340, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 561); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 562: VOR__VX */ + continuation_e __vor__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vor.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VOR__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 562); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2341; + x86::Gp ret_val_illegal_normal_2341 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2341, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2342 = get_reg(cc, 8, false); + mov(cc, tmp2342, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2342, ret_val_illegal_normal_2341); + setArg(call_illegal_normal_2341, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2341, 1, vd); + setArg(call_illegal_normal_2341, 2, vm); + setRet(call_illegal_normal_2341, 0, ret_val_illegal_normal_2341); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2344; + x86::Gp ret_val_sew_2344 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2344, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2343; + auto vector_imm_op_2343_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2343_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2343_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2343_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2343_arg10 = ret_val_sew_2344; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2343, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2344, 0, reinterpret_cast(this)); + setRet(call_sew_2344, 0, ret_val_sew_2344); + setArg(call_vector_imm_op_2343, 0, V); + setArg(call_vector_imm_op_2343, 1, 10); + setArg(call_vector_imm_op_2343, 2, 4); + setArg(call_vector_imm_op_2343, 3, vector_imm_op_2343_arg3); + setArg(call_vector_imm_op_2343, 4, vector_imm_op_2343_arg4); + setArg(call_vector_imm_op_2343, 5, vector_imm_op_2343_arg5); + setArg(call_vector_imm_op_2343, 6, vm); + setArg(call_vector_imm_op_2343, 7, vd); + setArg(call_vector_imm_op_2343, 8, vs2); + setArg(call_vector_imm_op_2343, 9, vector_imm_op_2343_arg9); + setArg(call_vector_imm_op_2343, 10, vector_imm_op_2343_arg10); + } + cc.bind(label_merge); + } + auto tmp2345 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2345, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2345, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 562); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 563: VXOR__VI */ + continuation_e __vxor__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vxor.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VXOR__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 563); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2346; + x86::Gp ret_val_illegal_normal_2346 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2346, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2346; + setArg(call_illegal_normal_2346, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2346, 1, vd); + setArg(call_illegal_normal_2346, 2, vm); + setRet(call_illegal_normal_2346, 0, ret_val_illegal_normal_2346); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2348; + x86::Gp ret_val_sew_2348 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2348, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2347; + auto vector_imm_op_2347_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2347_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2347_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2347_arg10 = ret_val_sew_2348; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2347, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2348, 0, reinterpret_cast(this)); + setRet(call_sew_2348, 0, ret_val_sew_2348); + setArg(call_vector_imm_op_2347, 0, V); + setArg(call_vector_imm_op_2347, 1, 11); + setArg(call_vector_imm_op_2347, 2, 3); + setArg(call_vector_imm_op_2347, 3, vector_imm_op_2347_arg3); + setArg(call_vector_imm_op_2347, 4, vector_imm_op_2347_arg4); + setArg(call_vector_imm_op_2347, 5, vector_imm_op_2347_arg5); + setArg(call_vector_imm_op_2347, 6, vm); + setArg(call_vector_imm_op_2347, 7, vd); + setArg(call_vector_imm_op_2347, 8, vs2); + setArg(call_vector_imm_op_2347, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_op_2347, 10, vector_imm_op_2347_arg10); + } + cc.bind(label_merge); + } + auto tmp2349 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2349, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2349, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 563); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 564: VXOR__VV */ + continuation_e __vxor__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vxor.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VXOR__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 564); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2350; + x86::Gp ret_val_illegal_normal_2350 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2350, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2350; + setArg(call_illegal_normal_2350, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2350, 1, vd); + setArg(call_illegal_normal_2350, 2, vm); + setRet(call_illegal_normal_2350, 0, ret_val_illegal_normal_2350); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2352; + x86::Gp ret_val_sew_2352 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2352, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2351; + auto vector_vector_op_2351_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2351_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2351_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2351_arg10 = ret_val_sew_2352; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2351, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2352, 0, reinterpret_cast(this)); + setRet(call_sew_2352, 0, ret_val_sew_2352); + setArg(call_vector_vector_op_2351, 0, V); + setArg(call_vector_vector_op_2351, 1, 11); + setArg(call_vector_vector_op_2351, 2, 0); + setArg(call_vector_vector_op_2351, 3, vector_vector_op_2351_arg3); + setArg(call_vector_vector_op_2351, 4, vector_vector_op_2351_arg4); + setArg(call_vector_vector_op_2351, 5, vector_vector_op_2351_arg5); + setArg(call_vector_vector_op_2351, 6, vm); + setArg(call_vector_vector_op_2351, 7, vd); + setArg(call_vector_vector_op_2351, 8, vs2); + setArg(call_vector_vector_op_2351, 9, vs1); + setArg(call_vector_vector_op_2351, 10, vector_vector_op_2351_arg10); + } + cc.bind(label_merge); + } + auto tmp2353 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2353, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2353, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 564); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 565: VXOR__VX */ + continuation_e __vxor__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vxor.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VXOR__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 565); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2354; + x86::Gp ret_val_illegal_normal_2354 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2354, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2355 = get_reg(cc, 8, false); + mov(cc, tmp2355, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2355, ret_val_illegal_normal_2354); + setArg(call_illegal_normal_2354, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2354, 1, vd); + setArg(call_illegal_normal_2354, 2, vm); + setRet(call_illegal_normal_2354, 0, ret_val_illegal_normal_2354); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2357; + x86::Gp ret_val_sew_2357 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2357, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2356; + auto vector_imm_op_2356_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2356_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2356_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2356_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2356_arg10 = ret_val_sew_2357; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2356, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2357, 0, reinterpret_cast(this)); + setRet(call_sew_2357, 0, ret_val_sew_2357); + setArg(call_vector_imm_op_2356, 0, V); + setArg(call_vector_imm_op_2356, 1, 11); + setArg(call_vector_imm_op_2356, 2, 4); + setArg(call_vector_imm_op_2356, 3, vector_imm_op_2356_arg3); + setArg(call_vector_imm_op_2356, 4, vector_imm_op_2356_arg4); + setArg(call_vector_imm_op_2356, 5, vector_imm_op_2356_arg5); + setArg(call_vector_imm_op_2356, 6, vm); + setArg(call_vector_imm_op_2356, 7, vd); + setArg(call_vector_imm_op_2356, 8, vs2); + setArg(call_vector_imm_op_2356, 9, vector_imm_op_2356_arg9); + setArg(call_vector_imm_op_2356, 10, vector_imm_op_2356_arg10); + } + cc.bind(label_merge); + } + auto tmp2358 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2358, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2358, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 565); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 566: VSLL__VI */ + continuation_e __vsll__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsll.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLL__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 566); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2359; + x86::Gp ret_val_illegal_normal_2359 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2359, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2359; + setArg(call_illegal_normal_2359, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2359, 1, vd); + setArg(call_illegal_normal_2359, 2, vm); + setRet(call_illegal_normal_2359, 0, ret_val_illegal_normal_2359); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2361; + x86::Gp ret_val_sew_2361 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2361, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2360; + auto vector_imm_op_2360_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2360_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2360_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2360_arg10 = ret_val_sew_2361; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2360, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2361, 0, reinterpret_cast(this)); + setRet(call_sew_2361, 0, ret_val_sew_2361); + setArg(call_vector_imm_op_2360, 0, V); + setArg(call_vector_imm_op_2360, 1, 37); + setArg(call_vector_imm_op_2360, 2, 3); + setArg(call_vector_imm_op_2360, 3, vector_imm_op_2360_arg3); + setArg(call_vector_imm_op_2360, 4, vector_imm_op_2360_arg4); + setArg(call_vector_imm_op_2360, 5, vector_imm_op_2360_arg5); + setArg(call_vector_imm_op_2360, 6, vm); + setArg(call_vector_imm_op_2360, 7, vd); + setArg(call_vector_imm_op_2360, 8, vs2); + setArg(call_vector_imm_op_2360, 9, (int64_t)(uint64_t)imm); + setArg(call_vector_imm_op_2360, 10, vector_imm_op_2360_arg10); + } + cc.bind(label_merge); + } + auto tmp2362 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2362, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2362, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 566); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 567: VSLL__VV */ + continuation_e __vsll__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsll.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 567); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2363; + x86::Gp ret_val_illegal_normal_2363 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2363, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2363; + setArg(call_illegal_normal_2363, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2363, 1, vd); + setArg(call_illegal_normal_2363, 2, vm); + setRet(call_illegal_normal_2363, 0, ret_val_illegal_normal_2363); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2365; + x86::Gp ret_val_sew_2365 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2365, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2364; + auto vector_vector_op_2364_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2364_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2364_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2364_arg10 = ret_val_sew_2365; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2364, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2365, 0, reinterpret_cast(this)); + setRet(call_sew_2365, 0, ret_val_sew_2365); + setArg(call_vector_vector_op_2364, 0, V); + setArg(call_vector_vector_op_2364, 1, 37); + setArg(call_vector_vector_op_2364, 2, 0); + setArg(call_vector_vector_op_2364, 3, vector_vector_op_2364_arg3); + setArg(call_vector_vector_op_2364, 4, vector_vector_op_2364_arg4); + setArg(call_vector_vector_op_2364, 5, vector_vector_op_2364_arg5); + setArg(call_vector_vector_op_2364, 6, vm); + setArg(call_vector_vector_op_2364, 7, vd); + setArg(call_vector_vector_op_2364, 8, vs2); + setArg(call_vector_vector_op_2364, 9, vs1); + setArg(call_vector_vector_op_2364, 10, vector_vector_op_2364_arg10); + } + cc.bind(label_merge); + } + auto tmp2366 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2366, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2366, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 567); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 568: VSLL__VX */ + continuation_e __vsll__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsll.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 568); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2367; + x86::Gp ret_val_illegal_normal_2367 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2367, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2368 = get_reg(cc, 8, false); + mov(cc, tmp2368, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2368, ret_val_illegal_normal_2367); + setArg(call_illegal_normal_2367, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2367, 1, vd); + setArg(call_illegal_normal_2367, 2, vm); + setRet(call_illegal_normal_2367, 0, ret_val_illegal_normal_2367); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2370; + x86::Gp ret_val_sew_2370 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2370, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2369; + auto vector_imm_op_2369_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2369_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2369_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2369_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); + auto vector_imm_op_2369_arg10 = ret_val_sew_2370; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2369, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2370, 0, reinterpret_cast(this)); + setRet(call_sew_2370, 0, ret_val_sew_2370); + setArg(call_vector_imm_op_2369, 0, V); + setArg(call_vector_imm_op_2369, 1, 37); + setArg(call_vector_imm_op_2369, 2, 4); + setArg(call_vector_imm_op_2369, 3, vector_imm_op_2369_arg3); + setArg(call_vector_imm_op_2369, 4, vector_imm_op_2369_arg4); + setArg(call_vector_imm_op_2369, 5, vector_imm_op_2369_arg5); + setArg(call_vector_imm_op_2369, 6, vm); + setArg(call_vector_imm_op_2369, 7, vd); + setArg(call_vector_imm_op_2369, 8, vs2); + setArg(call_vector_imm_op_2369, 9, vector_imm_op_2369_arg9); + setArg(call_vector_imm_op_2369, 10, vector_imm_op_2369_arg10); + } + cc.bind(label_merge); + } + auto tmp2371 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2371, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2371, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 568); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 569: VSRL__VI */ + continuation_e __vsrl__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsrl.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRL__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 569); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2372; + x86::Gp ret_val_illegal_normal_2372 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2372, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2372; + setArg(call_illegal_normal_2372, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2372, 1, vd); + setArg(call_illegal_normal_2372, 2, vm); + setRet(call_illegal_normal_2372, 0, ret_val_illegal_normal_2372); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2374; + x86::Gp ret_val_sew_2374 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2374, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2373; + auto vector_imm_op_2373_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2373_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2373_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2373_arg10 = ret_val_sew_2374; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2373, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2374, 0, reinterpret_cast(this)); + setRet(call_sew_2374, 0, ret_val_sew_2374); + setArg(call_vector_imm_op_2373, 0, V); + setArg(call_vector_imm_op_2373, 1, 40); + setArg(call_vector_imm_op_2373, 2, 3); + setArg(call_vector_imm_op_2373, 3, vector_imm_op_2373_arg3); + setArg(call_vector_imm_op_2373, 4, vector_imm_op_2373_arg4); + setArg(call_vector_imm_op_2373, 5, vector_imm_op_2373_arg5); + setArg(call_vector_imm_op_2373, 6, vm); + setArg(call_vector_imm_op_2373, 7, vd); + setArg(call_vector_imm_op_2373, 8, vs2); + setArg(call_vector_imm_op_2373, 9, (int64_t)(uint64_t)imm); + setArg(call_vector_imm_op_2373, 10, vector_imm_op_2373_arg10); + } + cc.bind(label_merge); + } + auto tmp2375 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2375, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2375, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 569); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 570: VSRL__VV */ + continuation_e __vsrl__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsrl.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 570); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2376; + x86::Gp ret_val_illegal_normal_2376 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2376, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2376; + setArg(call_illegal_normal_2376, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2376, 1, vd); + setArg(call_illegal_normal_2376, 2, vm); + setRet(call_illegal_normal_2376, 0, ret_val_illegal_normal_2376); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2378; + x86::Gp ret_val_sew_2378 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2378, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2377; + auto vector_vector_op_2377_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2377_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2377_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2377_arg10 = ret_val_sew_2378; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2377, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2378, 0, reinterpret_cast(this)); + setRet(call_sew_2378, 0, ret_val_sew_2378); + setArg(call_vector_vector_op_2377, 0, V); + setArg(call_vector_vector_op_2377, 1, 40); + setArg(call_vector_vector_op_2377, 2, 0); + setArg(call_vector_vector_op_2377, 3, vector_vector_op_2377_arg3); + setArg(call_vector_vector_op_2377, 4, vector_vector_op_2377_arg4); + setArg(call_vector_vector_op_2377, 5, vector_vector_op_2377_arg5); + setArg(call_vector_vector_op_2377, 6, vm); + setArg(call_vector_vector_op_2377, 7, vd); + setArg(call_vector_vector_op_2377, 8, vs2); + setArg(call_vector_vector_op_2377, 9, vs1); + setArg(call_vector_vector_op_2377, 10, vector_vector_op_2377_arg10); + } + cc.bind(label_merge); + } + auto tmp2379 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2379, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2379, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 570); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 571: VSRL__VX */ + continuation_e __vsrl__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsrl.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 571); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2380; + x86::Gp ret_val_illegal_normal_2380 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2380, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2381 = get_reg(cc, 8, false); + mov(cc, tmp2381, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2381, ret_val_illegal_normal_2380); + setArg(call_illegal_normal_2380, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2380, 1, vd); + setArg(call_illegal_normal_2380, 2, vm); + setRet(call_illegal_normal_2380, 0, ret_val_illegal_normal_2380); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2383; + x86::Gp ret_val_sew_2383 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2383, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2382; + auto vector_imm_op_2382_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2382_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2382_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2382_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); + auto vector_imm_op_2382_arg10 = ret_val_sew_2383; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2382, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2383, 0, reinterpret_cast(this)); + setRet(call_sew_2383, 0, ret_val_sew_2383); + setArg(call_vector_imm_op_2382, 0, V); + setArg(call_vector_imm_op_2382, 1, 40); + setArg(call_vector_imm_op_2382, 2, 4); + setArg(call_vector_imm_op_2382, 3, vector_imm_op_2382_arg3); + setArg(call_vector_imm_op_2382, 4, vector_imm_op_2382_arg4); + setArg(call_vector_imm_op_2382, 5, vector_imm_op_2382_arg5); + setArg(call_vector_imm_op_2382, 6, vm); + setArg(call_vector_imm_op_2382, 7, vd); + setArg(call_vector_imm_op_2382, 8, vs2); + setArg(call_vector_imm_op_2382, 9, vector_imm_op_2382_arg9); + setArg(call_vector_imm_op_2382, 10, vector_imm_op_2382_arg10); + } + cc.bind(label_merge); + } + auto tmp2384 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2384, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2384, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 571); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 572: VSRA__VI */ + continuation_e __vsra__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t imm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {imm}, {vm}", fmt::arg("mnemonic", "vsra.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("imm", imm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRA__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 572); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2385; + x86::Gp ret_val_illegal_normal_2385 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2385, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2385; + setArg(call_illegal_normal_2385, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2385, 1, vd); + setArg(call_illegal_normal_2385, 2, vm); + setRet(call_illegal_normal_2385, 0, ret_val_illegal_normal_2385); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2387; + x86::Gp ret_val_sew_2387 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2387, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2386; + auto vector_imm_op_2386_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2386_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2386_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2386_arg10 = ret_val_sew_2387; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2386, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2387, 0, reinterpret_cast(this)); + setRet(call_sew_2387, 0, ret_val_sew_2387); + setArg(call_vector_imm_op_2386, 0, V); + setArg(call_vector_imm_op_2386, 1, 41); + setArg(call_vector_imm_op_2386, 2, 3); + setArg(call_vector_imm_op_2386, 3, vector_imm_op_2386_arg3); + setArg(call_vector_imm_op_2386, 4, vector_imm_op_2386_arg4); + setArg(call_vector_imm_op_2386, 5, vector_imm_op_2386_arg5); + setArg(call_vector_imm_op_2386, 6, vm); + setArg(call_vector_imm_op_2386, 7, vd); + setArg(call_vector_imm_op_2386, 8, vs2); + setArg(call_vector_imm_op_2386, 9, (int64_t)(uint64_t)imm); + setArg(call_vector_imm_op_2386, 10, vector_imm_op_2386_arg10); + } + cc.bind(label_merge); + } + auto tmp2388 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2388, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2388, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 572); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 573: VSRA__VV */ + continuation_e __vsra__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsra.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRA__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 573); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2389; + x86::Gp ret_val_illegal_normal_2389 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2389, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2389; + setArg(call_illegal_normal_2389, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2389, 1, vd); + setArg(call_illegal_normal_2389, 2, vm); + setRet(call_illegal_normal_2389, 0, ret_val_illegal_normal_2389); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2391; + x86::Gp ret_val_sew_2391 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2391, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2390; + auto vector_vector_op_2390_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2390_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2390_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2390_arg10 = ret_val_sew_2391; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2390, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2391, 0, reinterpret_cast(this)); + setRet(call_sew_2391, 0, ret_val_sew_2391); + setArg(call_vector_vector_op_2390, 0, V); + setArg(call_vector_vector_op_2390, 1, 41); + setArg(call_vector_vector_op_2390, 2, 0); + setArg(call_vector_vector_op_2390, 3, vector_vector_op_2390_arg3); + setArg(call_vector_vector_op_2390, 4, vector_vector_op_2390_arg4); + setArg(call_vector_vector_op_2390, 5, vector_vector_op_2390_arg5); + setArg(call_vector_vector_op_2390, 6, vm); + setArg(call_vector_vector_op_2390, 7, vd); + setArg(call_vector_vector_op_2390, 8, vs2); + setArg(call_vector_vector_op_2390, 9, vs1); + setArg(call_vector_vector_op_2390, 10, vector_vector_op_2390_arg10); + } + cc.bind(label_merge); + } + auto tmp2392 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2392, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2392, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 573); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 574: VSRA__VX */ + continuation_e __vsra__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsra.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSRA__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 574); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2393; + x86::Gp ret_val_illegal_normal_2393 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2393, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2394 = get_reg(cc, 8, false); + mov(cc, tmp2394, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2394, ret_val_illegal_normal_2393); + setArg(call_illegal_normal_2393, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2393, 1, vd); + setArg(call_illegal_normal_2393, 2, vm); + setRet(call_illegal_normal_2393, 0, ret_val_illegal_normal_2393); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2396; + x86::Gp ret_val_sew_2396 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2396, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2395; + auto vector_imm_op_2395_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2395_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2395_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2395_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); + auto vector_imm_op_2395_arg10 = ret_val_sew_2396; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2395, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2396, 0, reinterpret_cast(this)); + setRet(call_sew_2396, 0, ret_val_sew_2396); + setArg(call_vector_imm_op_2395, 0, V); + setArg(call_vector_imm_op_2395, 1, 41); + setArg(call_vector_imm_op_2395, 2, 4); + setArg(call_vector_imm_op_2395, 3, vector_imm_op_2395_arg3); + setArg(call_vector_imm_op_2395, 4, vector_imm_op_2395_arg4); + setArg(call_vector_imm_op_2395, 5, vector_imm_op_2395_arg5); + setArg(call_vector_imm_op_2395, 6, vm); + setArg(call_vector_imm_op_2395, 7, vd); + setArg(call_vector_imm_op_2395, 8, vs2); + setArg(call_vector_imm_op_2395, 9, vector_imm_op_2395_arg9); + setArg(call_vector_imm_op_2395, 10, vector_imm_op_2395_arg10); + } + cc.bind(label_merge); + } + auto tmp2397 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2397, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2397, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 574); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 575: VNSRL__WI */ + continuation_e __vnsrl__wi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnsrl.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRL__WI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 575); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2398; + x86::Gp ret_val_get_sew_pow_2398 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2398, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2399 = get_reg(cc, 8, false); + mov(cc, tmp2399, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2399, ret_val_get_sew_pow_2398)), 8, false), ~ 1); + setArg(call_get_sew_pow_2398, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2398, 0, ret_val_get_sew_pow_2398); + InvokeNode* call_get_lmul_pow_2400; + x86::Gp ret_val_get_lmul_pow_2400 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2400, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2400; + setArg(call_get_lmul_pow_2400, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2400, 0, ret_val_get_lmul_pow_2400); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2401; + auto illegal_variable_width_2401_arg2 = SEW_widen; + auto illegal_variable_width_2401_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2401 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2401, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2402; + auto valid_reg_overlap_2402_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2402_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2402 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2402, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2401, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2402))); + setArg(call_illegal_variable_width_2401, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2401, 1, vd); + setArg(call_illegal_variable_width_2401, 2, vm); + setArg(call_illegal_variable_width_2401, 3, illegal_variable_width_2401_arg2); + setArg(call_illegal_variable_width_2401, 4, illegal_variable_width_2401_arg3); + setRet(call_illegal_variable_width_2401, 0, ret_val_illegal_variable_width_2401); + setArg(call_valid_reg_overlap_2402, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2402, 1, vs2); + setArg(call_valid_reg_overlap_2402, 2, vd); + setArg(call_valid_reg_overlap_2402, 3, valid_reg_overlap_2402_arg2); + setArg(call_valid_reg_overlap_2402, 4, valid_reg_overlap_2402_arg3); + setRet(call_valid_reg_overlap_2402, 0, ret_val_valid_reg_overlap_2402); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2404; + x86::Gp ret_val_sew_2404 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2404, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_vw_2403; + auto vector_imm_vw_2403_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_vw_2403_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_vw_2403_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_vw_2403_arg10 = ret_val_sew_2404; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_vw_2403, &vector_imm_vw, FuncSignature::build()); + setArg(call_sew_2404, 0, reinterpret_cast(this)); + setRet(call_sew_2404, 0, ret_val_sew_2404); + setArg(call_vector_imm_vw_2403, 0, V); + setArg(call_vector_imm_vw_2403, 1, 44); + setArg(call_vector_imm_vw_2403, 2, 3); + setArg(call_vector_imm_vw_2403, 3, vector_imm_vw_2403_arg3); + setArg(call_vector_imm_vw_2403, 4, vector_imm_vw_2403_arg4); + setArg(call_vector_imm_vw_2403, 5, vector_imm_vw_2403_arg5); + setArg(call_vector_imm_vw_2403, 6, vm); + setArg(call_vector_imm_vw_2403, 7, vd); + setArg(call_vector_imm_vw_2403, 8, vs2); + setArg(call_vector_imm_vw_2403, 9, (int64_t)(uint64_t)simm); + setArg(call_vector_imm_vw_2403, 10, vector_imm_vw_2403_arg10); + } + cc.bind(label_merge); + } + auto tmp2405 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2405, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2405, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 575); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 576: VNSRL__WV */ + continuation_e __vnsrl__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnsrl.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRL__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 576); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2406; + x86::Gp ret_val_get_sew_pow_2406 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2406, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2407 = get_reg(cc, 8, false); + mov(cc, tmp2407, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2407, ret_val_get_sew_pow_2406)), 8, false), ~ 1); + setArg(call_get_sew_pow_2406, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2406, 0, ret_val_get_sew_pow_2406); + InvokeNode* call_get_lmul_pow_2408; + x86::Gp ret_val_get_lmul_pow_2408 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2408, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2408; + setArg(call_get_lmul_pow_2408, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2408, 0, ret_val_get_lmul_pow_2408); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2409; + auto illegal_variable_width_2409_arg2 = SEW_widen; + auto illegal_variable_width_2409_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2409 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2409, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2410; + auto valid_reg_overlap_2410_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2410_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2410 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2410, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2409, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2410))); + setArg(call_illegal_variable_width_2409, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2409, 1, vd); + setArg(call_illegal_variable_width_2409, 2, vm); + setArg(call_illegal_variable_width_2409, 3, illegal_variable_width_2409_arg2); + setArg(call_illegal_variable_width_2409, 4, illegal_variable_width_2409_arg3); + setRet(call_illegal_variable_width_2409, 0, ret_val_illegal_variable_width_2409); + setArg(call_valid_reg_overlap_2410, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2410, 1, vs2); + setArg(call_valid_reg_overlap_2410, 2, vd); + setArg(call_valid_reg_overlap_2410, 3, valid_reg_overlap_2410_arg2); + setArg(call_valid_reg_overlap_2410, 4, valid_reg_overlap_2410_arg3); + setRet(call_valid_reg_overlap_2410, 0, ret_val_valid_reg_overlap_2410); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2412; + x86::Gp ret_val_sew_2412 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2412, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_vw_2411; + auto vector_vector_vw_2411_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_vw_2411_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_vw_2411_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_vw_2411_arg10 = ret_val_sew_2412; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_vw_2411, &vector_vector_vw, FuncSignature::build()); + setArg(call_sew_2412, 0, reinterpret_cast(this)); + setRet(call_sew_2412, 0, ret_val_sew_2412); + setArg(call_vector_vector_vw_2411, 0, V); + setArg(call_vector_vector_vw_2411, 1, 44); + setArg(call_vector_vector_vw_2411, 2, 0); + setArg(call_vector_vector_vw_2411, 3, vector_vector_vw_2411_arg3); + setArg(call_vector_vector_vw_2411, 4, vector_vector_vw_2411_arg4); + setArg(call_vector_vector_vw_2411, 5, vector_vector_vw_2411_arg5); + setArg(call_vector_vector_vw_2411, 6, vm); + setArg(call_vector_vector_vw_2411, 7, vd); + setArg(call_vector_vector_vw_2411, 8, vs2); + setArg(call_vector_vector_vw_2411, 9, vs1); + setArg(call_vector_vector_vw_2411, 10, vector_vector_vw_2411_arg10); + } + cc.bind(label_merge); + } + auto tmp2413 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2413, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2413, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 576); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 577: VNSRL__WX */ + continuation_e __vnsrl__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnsrl.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRL__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 577); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2414; + x86::Gp ret_val_get_sew_pow_2414 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2414, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2415 = get_reg(cc, 8, false); + mov(cc, tmp2415, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2415, ret_val_get_sew_pow_2414)), 8, false), ~ 1); + setArg(call_get_sew_pow_2414, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2414, 0, ret_val_get_sew_pow_2414); + InvokeNode* call_get_lmul_pow_2416; + x86::Gp ret_val_get_lmul_pow_2416 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2416, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2416; + setArg(call_get_lmul_pow_2416, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2416, 0, ret_val_get_lmul_pow_2416); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2417; + auto illegal_variable_width_2417_arg2 = SEW_widen; + auto illegal_variable_width_2417_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2417 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2417, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2418; + auto valid_reg_overlap_2418_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2418_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2418 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2418, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2417, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2418))); + setArg(call_illegal_variable_width_2417, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2417, 1, vd); + setArg(call_illegal_variable_width_2417, 2, vm); + setArg(call_illegal_variable_width_2417, 3, illegal_variable_width_2417_arg2); + setArg(call_illegal_variable_width_2417, 4, illegal_variable_width_2417_arg3); + setRet(call_illegal_variable_width_2417, 0, ret_val_illegal_variable_width_2417); + setArg(call_valid_reg_overlap_2418, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2418, 1, vs2); + setArg(call_valid_reg_overlap_2418, 2, vd); + setArg(call_valid_reg_overlap_2418, 3, valid_reg_overlap_2418_arg2); + setArg(call_valid_reg_overlap_2418, 4, valid_reg_overlap_2418_arg3); + setRet(call_valid_reg_overlap_2418, 0, ret_val_valid_reg_overlap_2418); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2420; + x86::Gp ret_val_sew_2420 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2420, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_vw_2419; + auto vector_imm_vw_2419_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_vw_2419_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_vw_2419_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_vw_2419_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); + auto vector_imm_vw_2419_arg10 = ret_val_sew_2420; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_vw_2419, &vector_imm_vw, FuncSignature::build()); + setArg(call_sew_2420, 0, reinterpret_cast(this)); + setRet(call_sew_2420, 0, ret_val_sew_2420); + setArg(call_vector_imm_vw_2419, 0, V); + setArg(call_vector_imm_vw_2419, 1, 44); + setArg(call_vector_imm_vw_2419, 2, 4); + setArg(call_vector_imm_vw_2419, 3, vector_imm_vw_2419_arg3); + setArg(call_vector_imm_vw_2419, 4, vector_imm_vw_2419_arg4); + setArg(call_vector_imm_vw_2419, 5, vector_imm_vw_2419_arg5); + setArg(call_vector_imm_vw_2419, 6, vm); + setArg(call_vector_imm_vw_2419, 7, vd); + setArg(call_vector_imm_vw_2419, 8, vs2); + setArg(call_vector_imm_vw_2419, 9, vector_imm_vw_2419_arg9); + setArg(call_vector_imm_vw_2419, 10, vector_imm_vw_2419_arg10); + } + cc.bind(label_merge); + } + auto tmp2421 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2421, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2421, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 577); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 578: VNSRA__WI */ + continuation_e __vnsra__wi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnsra.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRA__WI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 578); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2422; + x86::Gp ret_val_get_sew_pow_2422 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2422, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2423 = get_reg(cc, 8, false); + mov(cc, tmp2423, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2423, ret_val_get_sew_pow_2422)), 8, false), ~ 1); + setArg(call_get_sew_pow_2422, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2422, 0, ret_val_get_sew_pow_2422); + InvokeNode* call_get_lmul_pow_2424; + x86::Gp ret_val_get_lmul_pow_2424 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2424, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2424; + setArg(call_get_lmul_pow_2424, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2424, 0, ret_val_get_lmul_pow_2424); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2425; + auto illegal_variable_width_2425_arg2 = SEW_widen; + auto illegal_variable_width_2425_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2425 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2425, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2426; + auto valid_reg_overlap_2426_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2426_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2426 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2426, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2425, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2426))); + setArg(call_illegal_variable_width_2425, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2425, 1, vd); + setArg(call_illegal_variable_width_2425, 2, vm); + setArg(call_illegal_variable_width_2425, 3, illegal_variable_width_2425_arg2); + setArg(call_illegal_variable_width_2425, 4, illegal_variable_width_2425_arg3); + setRet(call_illegal_variable_width_2425, 0, ret_val_illegal_variable_width_2425); + setArg(call_valid_reg_overlap_2426, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2426, 1, vs2); + setArg(call_valid_reg_overlap_2426, 2, vd); + setArg(call_valid_reg_overlap_2426, 3, valid_reg_overlap_2426_arg2); + setArg(call_valid_reg_overlap_2426, 4, valid_reg_overlap_2426_arg3); + setRet(call_valid_reg_overlap_2426, 0, ret_val_valid_reg_overlap_2426); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2428; + x86::Gp ret_val_sew_2428 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2428, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_vw_2427; + auto vector_imm_vw_2427_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_vw_2427_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_vw_2427_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_vw_2427_arg10 = ret_val_sew_2428; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_vw_2427, &vector_imm_vw, FuncSignature::build()); + setArg(call_sew_2428, 0, reinterpret_cast(this)); + setRet(call_sew_2428, 0, ret_val_sew_2428); + setArg(call_vector_imm_vw_2427, 0, V); + setArg(call_vector_imm_vw_2427, 1, 45); + setArg(call_vector_imm_vw_2427, 2, 3); + setArg(call_vector_imm_vw_2427, 3, vector_imm_vw_2427_arg3); + setArg(call_vector_imm_vw_2427, 4, vector_imm_vw_2427_arg4); + setArg(call_vector_imm_vw_2427, 5, vector_imm_vw_2427_arg5); + setArg(call_vector_imm_vw_2427, 6, vm); + setArg(call_vector_imm_vw_2427, 7, vd); + setArg(call_vector_imm_vw_2427, 8, vs2); + setArg(call_vector_imm_vw_2427, 9, (int64_t)(uint64_t)simm); + setArg(call_vector_imm_vw_2427, 10, vector_imm_vw_2427_arg10); + } + cc.bind(label_merge); + } + auto tmp2429 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2429, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2429, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 578); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 579: VNSRA__WV */ + continuation_e __vnsra__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnsra.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRA__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 579); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2430; + x86::Gp ret_val_get_sew_pow_2430 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2430, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2431 = get_reg(cc, 8, false); + mov(cc, tmp2431, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2431, ret_val_get_sew_pow_2430)), 8, false), ~ 1); + setArg(call_get_sew_pow_2430, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2430, 0, ret_val_get_sew_pow_2430); + InvokeNode* call_get_lmul_pow_2432; + x86::Gp ret_val_get_lmul_pow_2432 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2432, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2432; + setArg(call_get_lmul_pow_2432, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2432, 0, ret_val_get_lmul_pow_2432); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2433; + auto illegal_variable_width_2433_arg2 = SEW_widen; + auto illegal_variable_width_2433_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2433 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2433, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2434; + auto valid_reg_overlap_2434_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2434_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2434 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2434, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2433, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2434))); + setArg(call_illegal_variable_width_2433, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2433, 1, vd); + setArg(call_illegal_variable_width_2433, 2, vm); + setArg(call_illegal_variable_width_2433, 3, illegal_variable_width_2433_arg2); + setArg(call_illegal_variable_width_2433, 4, illegal_variable_width_2433_arg3); + setRet(call_illegal_variable_width_2433, 0, ret_val_illegal_variable_width_2433); + setArg(call_valid_reg_overlap_2434, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2434, 1, vs2); + setArg(call_valid_reg_overlap_2434, 2, vd); + setArg(call_valid_reg_overlap_2434, 3, valid_reg_overlap_2434_arg2); + setArg(call_valid_reg_overlap_2434, 4, valid_reg_overlap_2434_arg3); + setRet(call_valid_reg_overlap_2434, 0, ret_val_valid_reg_overlap_2434); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2436; + x86::Gp ret_val_sew_2436 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2436, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_vw_2435; + auto vector_vector_vw_2435_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_vw_2435_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_vw_2435_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_vw_2435_arg10 = ret_val_sew_2436; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_vw_2435, &vector_vector_vw, FuncSignature::build()); + setArg(call_sew_2436, 0, reinterpret_cast(this)); + setRet(call_sew_2436, 0, ret_val_sew_2436); + setArg(call_vector_vector_vw_2435, 0, V); + setArg(call_vector_vector_vw_2435, 1, 45); + setArg(call_vector_vector_vw_2435, 2, 0); + setArg(call_vector_vector_vw_2435, 3, vector_vector_vw_2435_arg3); + setArg(call_vector_vector_vw_2435, 4, vector_vector_vw_2435_arg4); + setArg(call_vector_vector_vw_2435, 5, vector_vector_vw_2435_arg5); + setArg(call_vector_vector_vw_2435, 6, vm); + setArg(call_vector_vector_vw_2435, 7, vd); + setArg(call_vector_vector_vw_2435, 8, vs2); + setArg(call_vector_vector_vw_2435, 9, vs1); + setArg(call_vector_vector_vw_2435, 10, vector_vector_vw_2435_arg10); + } + cc.bind(label_merge); + } + auto tmp2437 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2437, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2437, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 579); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 580: VNSRA__WX */ + continuation_e __vnsra__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnsra.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNSRA__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 580); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2438; + x86::Gp ret_val_get_sew_pow_2438 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2438, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2439 = get_reg(cc, 8, false); + mov(cc, tmp2439, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2439, ret_val_get_sew_pow_2438)), 8, false), ~ 1); + setArg(call_get_sew_pow_2438, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2438, 0, ret_val_get_sew_pow_2438); + InvokeNode* call_get_lmul_pow_2440; + x86::Gp ret_val_get_lmul_pow_2440 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2440, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2440; + setArg(call_get_lmul_pow_2440, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2440, 0, ret_val_get_lmul_pow_2440); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2441; + auto illegal_variable_width_2441_arg2 = SEW_widen; + auto illegal_variable_width_2441_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2441 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2441, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2442; + auto valid_reg_overlap_2442_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2442_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2442 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2442, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2441, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2442))); + setArg(call_illegal_variable_width_2441, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2441, 1, vd); + setArg(call_illegal_variable_width_2441, 2, vm); + setArg(call_illegal_variable_width_2441, 3, illegal_variable_width_2441_arg2); + setArg(call_illegal_variable_width_2441, 4, illegal_variable_width_2441_arg3); + setRet(call_illegal_variable_width_2441, 0, ret_val_illegal_variable_width_2441); + setArg(call_valid_reg_overlap_2442, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2442, 1, vs2); + setArg(call_valid_reg_overlap_2442, 2, vd); + setArg(call_valid_reg_overlap_2442, 3, valid_reg_overlap_2442_arg2); + setArg(call_valid_reg_overlap_2442, 4, valid_reg_overlap_2442_arg3); + setRet(call_valid_reg_overlap_2442, 0, ret_val_valid_reg_overlap_2442); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2444; + x86::Gp ret_val_sew_2444 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2444, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_vw_2443; + auto vector_imm_vw_2443_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_vw_2443_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_vw_2443_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_vw_2443_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); + auto vector_imm_vw_2443_arg10 = ret_val_sew_2444; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_vw_2443, &vector_imm_vw, FuncSignature::build()); + setArg(call_sew_2444, 0, reinterpret_cast(this)); + setRet(call_sew_2444, 0, ret_val_sew_2444); + setArg(call_vector_imm_vw_2443, 0, V); + setArg(call_vector_imm_vw_2443, 1, 45); + setArg(call_vector_imm_vw_2443, 2, 4); + setArg(call_vector_imm_vw_2443, 3, vector_imm_vw_2443_arg3); + setArg(call_vector_imm_vw_2443, 4, vector_imm_vw_2443_arg4); + setArg(call_vector_imm_vw_2443, 5, vector_imm_vw_2443_arg5); + setArg(call_vector_imm_vw_2443, 6, vm); + setArg(call_vector_imm_vw_2443, 7, vd); + setArg(call_vector_imm_vw_2443, 8, vs2); + setArg(call_vector_imm_vw_2443, 9, vector_imm_vw_2443_arg9); + setArg(call_vector_imm_vw_2443, 10, vector_imm_vw_2443_arg10); + } + cc.bind(label_merge); + } + auto tmp2445 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2445, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2445, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 580); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 581: VMSEQ__VI */ + continuation_e __vmseq__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmseq.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSEQ__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 581); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2446; + x86::Gp ret_val_illegal_vd_unmasked_2446 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2446, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2446; + setArg(call_illegal_vd_unmasked_2446, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2446, 0, ret_val_illegal_vd_unmasked_2446); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2448; + x86::Gp ret_val_sew_2448 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2448, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2447; + auto mask_vector_imm_op_2447_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2447_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2447_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2447_arg10 = ret_val_sew_2448; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2447, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2448, 0, reinterpret_cast(this)); + setRet(call_sew_2448, 0, ret_val_sew_2448); + setArg(call_mask_vector_imm_op_2447, 0, V); + setArg(call_mask_vector_imm_op_2447, 1, 24); + setArg(call_mask_vector_imm_op_2447, 2, 3); + setArg(call_mask_vector_imm_op_2447, 3, mask_vector_imm_op_2447_arg3); + setArg(call_mask_vector_imm_op_2447, 4, mask_vector_imm_op_2447_arg4); + setArg(call_mask_vector_imm_op_2447, 5, mask_vector_imm_op_2447_arg5); + setArg(call_mask_vector_imm_op_2447, 6, vm); + setArg(call_mask_vector_imm_op_2447, 7, vd); + setArg(call_mask_vector_imm_op_2447, 8, vs2); + setArg(call_mask_vector_imm_op_2447, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2447, 10, mask_vector_imm_op_2447_arg10); + } + cc.bind(label_merge); + } + auto tmp2449 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2449, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2449, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 581); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 582: VMSEQ__VV */ + continuation_e __vmseq__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmseq.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSEQ__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 582); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2450; + x86::Gp ret_val_illegal_vd_unmasked_2450 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2450, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2450; + setArg(call_illegal_vd_unmasked_2450, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2450, 0, ret_val_illegal_vd_unmasked_2450); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2452; + x86::Gp ret_val_sew_2452 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2452, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2451; + auto mask_vector_vector_op_2451_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2451_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2451_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2451_arg10 = ret_val_sew_2452; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2451, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2452, 0, reinterpret_cast(this)); + setRet(call_sew_2452, 0, ret_val_sew_2452); + setArg(call_mask_vector_vector_op_2451, 0, V); + setArg(call_mask_vector_vector_op_2451, 1, 24); + setArg(call_mask_vector_vector_op_2451, 2, 0); + setArg(call_mask_vector_vector_op_2451, 3, mask_vector_vector_op_2451_arg3); + setArg(call_mask_vector_vector_op_2451, 4, mask_vector_vector_op_2451_arg4); + setArg(call_mask_vector_vector_op_2451, 5, mask_vector_vector_op_2451_arg5); + setArg(call_mask_vector_vector_op_2451, 6, vm); + setArg(call_mask_vector_vector_op_2451, 7, vd); + setArg(call_mask_vector_vector_op_2451, 8, vs2); + setArg(call_mask_vector_vector_op_2451, 9, vs1); + setArg(call_mask_vector_vector_op_2451, 10, mask_vector_vector_op_2451_arg10); + } + cc.bind(label_merge); + } + auto tmp2453 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2453, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2453, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 582); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 583: VMSEQ__VX */ + continuation_e __vmseq__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmseq.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSEQ__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 583); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2454; + x86::Gp ret_val_illegal_vd_unmasked_2454 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2454, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2455 = get_reg(cc, 8, false); + mov(cc, tmp2455, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2455, ret_val_illegal_vd_unmasked_2454); + setArg(call_illegal_vd_unmasked_2454, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2454, 0, ret_val_illegal_vd_unmasked_2454); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2457; + x86::Gp ret_val_sew_2457 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2457, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2456; + auto mask_vector_imm_op_2456_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2456_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2456_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2456_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto mask_vector_imm_op_2456_arg10 = ret_val_sew_2457; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2456, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2457, 0, reinterpret_cast(this)); + setRet(call_sew_2457, 0, ret_val_sew_2457); + setArg(call_mask_vector_imm_op_2456, 0, V); + setArg(call_mask_vector_imm_op_2456, 1, 24); + setArg(call_mask_vector_imm_op_2456, 2, 4); + setArg(call_mask_vector_imm_op_2456, 3, mask_vector_imm_op_2456_arg3); + setArg(call_mask_vector_imm_op_2456, 4, mask_vector_imm_op_2456_arg4); + setArg(call_mask_vector_imm_op_2456, 5, mask_vector_imm_op_2456_arg5); + setArg(call_mask_vector_imm_op_2456, 6, vm); + setArg(call_mask_vector_imm_op_2456, 7, vd); + setArg(call_mask_vector_imm_op_2456, 8, vs2); + setArg(call_mask_vector_imm_op_2456, 9, mask_vector_imm_op_2456_arg9); + setArg(call_mask_vector_imm_op_2456, 10, mask_vector_imm_op_2456_arg10); + } + cc.bind(label_merge); + } + auto tmp2458 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2458, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2458, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 583); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 584: VMSNE__VI */ + continuation_e __vmsne__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsne.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSNE__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 584); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2459; + x86::Gp ret_val_illegal_vd_unmasked_2459 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2459, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2459; + setArg(call_illegal_vd_unmasked_2459, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2459, 0, ret_val_illegal_vd_unmasked_2459); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2461; + x86::Gp ret_val_sew_2461 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2461, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2460; + auto mask_vector_imm_op_2460_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2460_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2460_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2460_arg10 = ret_val_sew_2461; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2460, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2461, 0, reinterpret_cast(this)); + setRet(call_sew_2461, 0, ret_val_sew_2461); + setArg(call_mask_vector_imm_op_2460, 0, V); + setArg(call_mask_vector_imm_op_2460, 1, 25); + setArg(call_mask_vector_imm_op_2460, 2, 3); + setArg(call_mask_vector_imm_op_2460, 3, mask_vector_imm_op_2460_arg3); + setArg(call_mask_vector_imm_op_2460, 4, mask_vector_imm_op_2460_arg4); + setArg(call_mask_vector_imm_op_2460, 5, mask_vector_imm_op_2460_arg5); + setArg(call_mask_vector_imm_op_2460, 6, vm); + setArg(call_mask_vector_imm_op_2460, 7, vd); + setArg(call_mask_vector_imm_op_2460, 8, vs2); + setArg(call_mask_vector_imm_op_2460, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2460, 10, mask_vector_imm_op_2460_arg10); + } + cc.bind(label_merge); + } + auto tmp2462 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2462, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2462, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 584); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 585: VMSNE__VV */ + continuation_e __vmsne__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsne.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSNE__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 585); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2463; + x86::Gp ret_val_illegal_vd_unmasked_2463 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2463, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2463; + setArg(call_illegal_vd_unmasked_2463, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2463, 0, ret_val_illegal_vd_unmasked_2463); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2465; + x86::Gp ret_val_sew_2465 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2465, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2464; + auto mask_vector_vector_op_2464_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2464_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2464_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2464_arg10 = ret_val_sew_2465; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2464, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2465, 0, reinterpret_cast(this)); + setRet(call_sew_2465, 0, ret_val_sew_2465); + setArg(call_mask_vector_vector_op_2464, 0, V); + setArg(call_mask_vector_vector_op_2464, 1, 25); + setArg(call_mask_vector_vector_op_2464, 2, 0); + setArg(call_mask_vector_vector_op_2464, 3, mask_vector_vector_op_2464_arg3); + setArg(call_mask_vector_vector_op_2464, 4, mask_vector_vector_op_2464_arg4); + setArg(call_mask_vector_vector_op_2464, 5, mask_vector_vector_op_2464_arg5); + setArg(call_mask_vector_vector_op_2464, 6, vm); + setArg(call_mask_vector_vector_op_2464, 7, vd); + setArg(call_mask_vector_vector_op_2464, 8, vs2); + setArg(call_mask_vector_vector_op_2464, 9, vs1); + setArg(call_mask_vector_vector_op_2464, 10, mask_vector_vector_op_2464_arg10); + } + cc.bind(label_merge); + } + auto tmp2466 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2466, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2466, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 585); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 586: VMSNE__VX */ + continuation_e __vmsne__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsne.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSNE__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 586); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2467; + x86::Gp ret_val_illegal_vd_unmasked_2467 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2467, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2468 = get_reg(cc, 8, false); + mov(cc, tmp2468, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2468, ret_val_illegal_vd_unmasked_2467); + setArg(call_illegal_vd_unmasked_2467, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2467, 0, ret_val_illegal_vd_unmasked_2467); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2470; + x86::Gp ret_val_sew_2470 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2470, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2469; + auto mask_vector_imm_op_2469_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2469_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2469_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2469_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto mask_vector_imm_op_2469_arg10 = ret_val_sew_2470; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2469, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2470, 0, reinterpret_cast(this)); + setRet(call_sew_2470, 0, ret_val_sew_2470); + setArg(call_mask_vector_imm_op_2469, 0, V); + setArg(call_mask_vector_imm_op_2469, 1, 25); + setArg(call_mask_vector_imm_op_2469, 2, 4); + setArg(call_mask_vector_imm_op_2469, 3, mask_vector_imm_op_2469_arg3); + setArg(call_mask_vector_imm_op_2469, 4, mask_vector_imm_op_2469_arg4); + setArg(call_mask_vector_imm_op_2469, 5, mask_vector_imm_op_2469_arg5); + setArg(call_mask_vector_imm_op_2469, 6, vm); + setArg(call_mask_vector_imm_op_2469, 7, vd); + setArg(call_mask_vector_imm_op_2469, 8, vs2); + setArg(call_mask_vector_imm_op_2469, 9, mask_vector_imm_op_2469_arg9); + setArg(call_mask_vector_imm_op_2469, 10, mask_vector_imm_op_2469_arg10); + } + cc.bind(label_merge); + } + auto tmp2471 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2471, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2471, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 586); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 587: VMSLTU__VV */ + continuation_e __vmsltu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsltu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLTU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 587); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2472; + x86::Gp ret_val_illegal_vd_unmasked_2472 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2472, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2472; + setArg(call_illegal_vd_unmasked_2472, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2472, 0, ret_val_illegal_vd_unmasked_2472); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2474; + x86::Gp ret_val_sew_2474 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2474, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2473; + auto mask_vector_vector_op_2473_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2473_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2473_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2473_arg10 = ret_val_sew_2474; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2473, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2474, 0, reinterpret_cast(this)); + setRet(call_sew_2474, 0, ret_val_sew_2474); + setArg(call_mask_vector_vector_op_2473, 0, V); + setArg(call_mask_vector_vector_op_2473, 1, 26); + setArg(call_mask_vector_vector_op_2473, 2, 0); + setArg(call_mask_vector_vector_op_2473, 3, mask_vector_vector_op_2473_arg3); + setArg(call_mask_vector_vector_op_2473, 4, mask_vector_vector_op_2473_arg4); + setArg(call_mask_vector_vector_op_2473, 5, mask_vector_vector_op_2473_arg5); + setArg(call_mask_vector_vector_op_2473, 6, vm); + setArg(call_mask_vector_vector_op_2473, 7, vd); + setArg(call_mask_vector_vector_op_2473, 8, vs2); + setArg(call_mask_vector_vector_op_2473, 9, vs1); + setArg(call_mask_vector_vector_op_2473, 10, mask_vector_vector_op_2473_arg10); + } + cc.bind(label_merge); + } + auto tmp2475 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2475, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2475, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 587); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 588: VMSLTU__VX */ + continuation_e __vmsltu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsltu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLTU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 588); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2476; + x86::Gp ret_val_illegal_vd_unmasked_2476 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2476, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2477 = get_reg(cc, 8, false); + mov(cc, tmp2477, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2477, ret_val_illegal_vd_unmasked_2476); + setArg(call_illegal_vd_unmasked_2476, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2476, 0, ret_val_illegal_vd_unmasked_2476); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2479; + x86::Gp ret_val_sew_2479 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2479, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2478; + auto mask_vector_imm_op_2478_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2478_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2478_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2478_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto mask_vector_imm_op_2478_arg10 = ret_val_sew_2479; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2478, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2479, 0, reinterpret_cast(this)); + setRet(call_sew_2479, 0, ret_val_sew_2479); + setArg(call_mask_vector_imm_op_2478, 0, V); + setArg(call_mask_vector_imm_op_2478, 1, 26); + setArg(call_mask_vector_imm_op_2478, 2, 4); + setArg(call_mask_vector_imm_op_2478, 3, mask_vector_imm_op_2478_arg3); + setArg(call_mask_vector_imm_op_2478, 4, mask_vector_imm_op_2478_arg4); + setArg(call_mask_vector_imm_op_2478, 5, mask_vector_imm_op_2478_arg5); + setArg(call_mask_vector_imm_op_2478, 6, vm); + setArg(call_mask_vector_imm_op_2478, 7, vd); + setArg(call_mask_vector_imm_op_2478, 8, vs2); + setArg(call_mask_vector_imm_op_2478, 9, mask_vector_imm_op_2478_arg9); + setArg(call_mask_vector_imm_op_2478, 10, mask_vector_imm_op_2478_arg10); + } + cc.bind(label_merge); + } + auto tmp2480 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2480, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2480, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 588); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 589: VMSLT__VV */ + continuation_e __vmslt__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmslt.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLT__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 589); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2481; + x86::Gp ret_val_illegal_vd_unmasked_2481 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2481, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2481; + setArg(call_illegal_vd_unmasked_2481, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2481, 0, ret_val_illegal_vd_unmasked_2481); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2483; + x86::Gp ret_val_sew_2483 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2483, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2482; + auto mask_vector_vector_op_2482_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2482_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2482_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2482_arg10 = ret_val_sew_2483; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2482, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2483, 0, reinterpret_cast(this)); + setRet(call_sew_2483, 0, ret_val_sew_2483); + setArg(call_mask_vector_vector_op_2482, 0, V); + setArg(call_mask_vector_vector_op_2482, 1, 27); + setArg(call_mask_vector_vector_op_2482, 2, 0); + setArg(call_mask_vector_vector_op_2482, 3, mask_vector_vector_op_2482_arg3); + setArg(call_mask_vector_vector_op_2482, 4, mask_vector_vector_op_2482_arg4); + setArg(call_mask_vector_vector_op_2482, 5, mask_vector_vector_op_2482_arg5); + setArg(call_mask_vector_vector_op_2482, 6, vm); + setArg(call_mask_vector_vector_op_2482, 7, vd); + setArg(call_mask_vector_vector_op_2482, 8, vs2); + setArg(call_mask_vector_vector_op_2482, 9, vs1); + setArg(call_mask_vector_vector_op_2482, 10, mask_vector_vector_op_2482_arg10); + } + cc.bind(label_merge); + } + auto tmp2484 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2484, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2484, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 589); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 590: VMSLT__VX */ + continuation_e __vmslt__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmslt.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLT__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 590); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2485; + x86::Gp ret_val_illegal_vd_unmasked_2485 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2485, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2486 = get_reg(cc, 8, false); + mov(cc, tmp2486, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2486, ret_val_illegal_vd_unmasked_2485); + setArg(call_illegal_vd_unmasked_2485, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2485, 0, ret_val_illegal_vd_unmasked_2485); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2488; + x86::Gp ret_val_sew_2488 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2488, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2487; + auto mask_vector_imm_op_2487_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2487_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2487_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2487_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto mask_vector_imm_op_2487_arg10 = ret_val_sew_2488; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2487, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2488, 0, reinterpret_cast(this)); + setRet(call_sew_2488, 0, ret_val_sew_2488); + setArg(call_mask_vector_imm_op_2487, 0, V); + setArg(call_mask_vector_imm_op_2487, 1, 27); + setArg(call_mask_vector_imm_op_2487, 2, 4); + setArg(call_mask_vector_imm_op_2487, 3, mask_vector_imm_op_2487_arg3); + setArg(call_mask_vector_imm_op_2487, 4, mask_vector_imm_op_2487_arg4); + setArg(call_mask_vector_imm_op_2487, 5, mask_vector_imm_op_2487_arg5); + setArg(call_mask_vector_imm_op_2487, 6, vm); + setArg(call_mask_vector_imm_op_2487, 7, vd); + setArg(call_mask_vector_imm_op_2487, 8, vs2); + setArg(call_mask_vector_imm_op_2487, 9, mask_vector_imm_op_2487_arg9); + setArg(call_mask_vector_imm_op_2487, 10, mask_vector_imm_op_2487_arg10); + } + cc.bind(label_merge); + } + auto tmp2489 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2489, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2489, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 590); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 591: VMSLEU__VI */ + continuation_e __vmsleu__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsleu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLEU__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 591); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2490; + x86::Gp ret_val_illegal_vd_unmasked_2490 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2490, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2490; + setArg(call_illegal_vd_unmasked_2490, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2490, 0, ret_val_illegal_vd_unmasked_2490); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2492; + x86::Gp ret_val_sew_2492 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2492, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2491; + auto mask_vector_imm_op_2491_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2491_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2491_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2491_arg10 = ret_val_sew_2492; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2491, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2492, 0, reinterpret_cast(this)); + setRet(call_sew_2492, 0, ret_val_sew_2492); + setArg(call_mask_vector_imm_op_2491, 0, V); + setArg(call_mask_vector_imm_op_2491, 1, 28); + setArg(call_mask_vector_imm_op_2491, 2, 3); + setArg(call_mask_vector_imm_op_2491, 3, mask_vector_imm_op_2491_arg3); + setArg(call_mask_vector_imm_op_2491, 4, mask_vector_imm_op_2491_arg4); + setArg(call_mask_vector_imm_op_2491, 5, mask_vector_imm_op_2491_arg5); + setArg(call_mask_vector_imm_op_2491, 6, vm); + setArg(call_mask_vector_imm_op_2491, 7, vd); + setArg(call_mask_vector_imm_op_2491, 8, vs2); + setArg(call_mask_vector_imm_op_2491, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2491, 10, mask_vector_imm_op_2491_arg10); + } + cc.bind(label_merge); + } + auto tmp2493 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2493, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2493, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 591); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 592: VMSLEU__VV */ + continuation_e __vmsleu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsleu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLEU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 592); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2494; + x86::Gp ret_val_illegal_vd_unmasked_2494 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2494, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2494; + setArg(call_illegal_vd_unmasked_2494, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2494, 0, ret_val_illegal_vd_unmasked_2494); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2496; + x86::Gp ret_val_sew_2496 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2496, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2495; + auto mask_vector_vector_op_2495_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2495_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2495_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2495_arg10 = ret_val_sew_2496; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2495, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2496, 0, reinterpret_cast(this)); + setRet(call_sew_2496, 0, ret_val_sew_2496); + setArg(call_mask_vector_vector_op_2495, 0, V); + setArg(call_mask_vector_vector_op_2495, 1, 28); + setArg(call_mask_vector_vector_op_2495, 2, 0); + setArg(call_mask_vector_vector_op_2495, 3, mask_vector_vector_op_2495_arg3); + setArg(call_mask_vector_vector_op_2495, 4, mask_vector_vector_op_2495_arg4); + setArg(call_mask_vector_vector_op_2495, 5, mask_vector_vector_op_2495_arg5); + setArg(call_mask_vector_vector_op_2495, 6, vm); + setArg(call_mask_vector_vector_op_2495, 7, vd); + setArg(call_mask_vector_vector_op_2495, 8, vs2); + setArg(call_mask_vector_vector_op_2495, 9, vs1); + setArg(call_mask_vector_vector_op_2495, 10, mask_vector_vector_op_2495_arg10); + } + cc.bind(label_merge); + } + auto tmp2497 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2497, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2497, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 592); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 593: VMSLEU__VX */ + continuation_e __vmsleu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsleu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLEU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 593); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2498; + x86::Gp ret_val_illegal_vd_unmasked_2498 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2498, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2499 = get_reg(cc, 8, false); + mov(cc, tmp2499, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2499, ret_val_illegal_vd_unmasked_2498); + setArg(call_illegal_vd_unmasked_2498, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2498, 0, ret_val_illegal_vd_unmasked_2498); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2501; + x86::Gp ret_val_sew_2501 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2501, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2500; + auto mask_vector_imm_op_2500_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2500_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2500_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2500_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto mask_vector_imm_op_2500_arg10 = ret_val_sew_2501; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2500, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2501, 0, reinterpret_cast(this)); + setRet(call_sew_2501, 0, ret_val_sew_2501); + setArg(call_mask_vector_imm_op_2500, 0, V); + setArg(call_mask_vector_imm_op_2500, 1, 28); + setArg(call_mask_vector_imm_op_2500, 2, 4); + setArg(call_mask_vector_imm_op_2500, 3, mask_vector_imm_op_2500_arg3); + setArg(call_mask_vector_imm_op_2500, 4, mask_vector_imm_op_2500_arg4); + setArg(call_mask_vector_imm_op_2500, 5, mask_vector_imm_op_2500_arg5); + setArg(call_mask_vector_imm_op_2500, 6, vm); + setArg(call_mask_vector_imm_op_2500, 7, vd); + setArg(call_mask_vector_imm_op_2500, 8, vs2); + setArg(call_mask_vector_imm_op_2500, 9, mask_vector_imm_op_2500_arg9); + setArg(call_mask_vector_imm_op_2500, 10, mask_vector_imm_op_2500_arg10); + } + cc.bind(label_merge); + } + auto tmp2502 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2502, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2502, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 593); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 594: VMSLE__VI */ + continuation_e __vmsle__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsle.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLE__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 594); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2503; + x86::Gp ret_val_illegal_vd_unmasked_2503 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2503, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2503; + setArg(call_illegal_vd_unmasked_2503, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2503, 0, ret_val_illegal_vd_unmasked_2503); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2505; + x86::Gp ret_val_sew_2505 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2505, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2504; + auto mask_vector_imm_op_2504_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2504_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2504_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2504_arg10 = ret_val_sew_2505; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2504, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2505, 0, reinterpret_cast(this)); + setRet(call_sew_2505, 0, ret_val_sew_2505); + setArg(call_mask_vector_imm_op_2504, 0, V); + setArg(call_mask_vector_imm_op_2504, 1, 29); + setArg(call_mask_vector_imm_op_2504, 2, 3); + setArg(call_mask_vector_imm_op_2504, 3, mask_vector_imm_op_2504_arg3); + setArg(call_mask_vector_imm_op_2504, 4, mask_vector_imm_op_2504_arg4); + setArg(call_mask_vector_imm_op_2504, 5, mask_vector_imm_op_2504_arg5); + setArg(call_mask_vector_imm_op_2504, 6, vm); + setArg(call_mask_vector_imm_op_2504, 7, vd); + setArg(call_mask_vector_imm_op_2504, 8, vs2); + setArg(call_mask_vector_imm_op_2504, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2504, 10, mask_vector_imm_op_2504_arg10); + } + cc.bind(label_merge); + } + auto tmp2506 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2506, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2506, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 594); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 595: VMSLE__VV */ + continuation_e __vmsle__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmsle.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLE__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 595); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2507; + x86::Gp ret_val_illegal_vd_unmasked_2507 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2507, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2507; + setArg(call_illegal_vd_unmasked_2507, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2507, 0, ret_val_illegal_vd_unmasked_2507); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2509; + x86::Gp ret_val_sew_2509 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2509, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_vector_op_2508; + auto mask_vector_vector_op_2508_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_vector_op_2508_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_vector_op_2508_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_vector_op_2508_arg10 = ret_val_sew_2509; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_vector_op_2508, &mask_vector_vector_op, FuncSignature::build()); + setArg(call_sew_2509, 0, reinterpret_cast(this)); + setRet(call_sew_2509, 0, ret_val_sew_2509); + setArg(call_mask_vector_vector_op_2508, 0, V); + setArg(call_mask_vector_vector_op_2508, 1, 29); + setArg(call_mask_vector_vector_op_2508, 2, 0); + setArg(call_mask_vector_vector_op_2508, 3, mask_vector_vector_op_2508_arg3); + setArg(call_mask_vector_vector_op_2508, 4, mask_vector_vector_op_2508_arg4); + setArg(call_mask_vector_vector_op_2508, 5, mask_vector_vector_op_2508_arg5); + setArg(call_mask_vector_vector_op_2508, 6, vm); + setArg(call_mask_vector_vector_op_2508, 7, vd); + setArg(call_mask_vector_vector_op_2508, 8, vs2); + setArg(call_mask_vector_vector_op_2508, 9, vs1); + setArg(call_mask_vector_vector_op_2508, 10, mask_vector_vector_op_2508_arg10); + } + cc.bind(label_merge); + } + auto tmp2510 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2510, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2510, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 595); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 596: VMSLE__VX */ + continuation_e __vmsle__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsle.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSLE__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 596); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2511; + x86::Gp ret_val_illegal_vd_unmasked_2511 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2511, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2512 = get_reg(cc, 8, false); + mov(cc, tmp2512, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2512, ret_val_illegal_vd_unmasked_2511); + setArg(call_illegal_vd_unmasked_2511, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2511, 0, ret_val_illegal_vd_unmasked_2511); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2514; + x86::Gp ret_val_sew_2514 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2514, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2513; + auto mask_vector_imm_op_2513_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2513_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2513_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2513_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto mask_vector_imm_op_2513_arg10 = ret_val_sew_2514; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2513, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2514, 0, reinterpret_cast(this)); + setRet(call_sew_2514, 0, ret_val_sew_2514); + setArg(call_mask_vector_imm_op_2513, 0, V); + setArg(call_mask_vector_imm_op_2513, 1, 29); + setArg(call_mask_vector_imm_op_2513, 2, 4); + setArg(call_mask_vector_imm_op_2513, 3, mask_vector_imm_op_2513_arg3); + setArg(call_mask_vector_imm_op_2513, 4, mask_vector_imm_op_2513_arg4); + setArg(call_mask_vector_imm_op_2513, 5, mask_vector_imm_op_2513_arg5); + setArg(call_mask_vector_imm_op_2513, 6, vm); + setArg(call_mask_vector_imm_op_2513, 7, vd); + setArg(call_mask_vector_imm_op_2513, 8, vs2); + setArg(call_mask_vector_imm_op_2513, 9, mask_vector_imm_op_2513_arg9); + setArg(call_mask_vector_imm_op_2513, 10, mask_vector_imm_op_2513_arg10); + } + cc.bind(label_merge); + } + auto tmp2515 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2515, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2515, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 596); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 597: VMSGTU__VI */ + continuation_e __vmsgtu__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsgtu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSGTU__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 597); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2516; + x86::Gp ret_val_illegal_vd_unmasked_2516 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2516, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2516; + setArg(call_illegal_vd_unmasked_2516, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2516, 0, ret_val_illegal_vd_unmasked_2516); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2518; + x86::Gp ret_val_sew_2518 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2518, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2517; + auto mask_vector_imm_op_2517_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2517_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2517_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2517_arg10 = ret_val_sew_2518; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2517, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2518, 0, reinterpret_cast(this)); + setRet(call_sew_2518, 0, ret_val_sew_2518); + setArg(call_mask_vector_imm_op_2517, 0, V); + setArg(call_mask_vector_imm_op_2517, 1, 30); + setArg(call_mask_vector_imm_op_2517, 2, 3); + setArg(call_mask_vector_imm_op_2517, 3, mask_vector_imm_op_2517_arg3); + setArg(call_mask_vector_imm_op_2517, 4, mask_vector_imm_op_2517_arg4); + setArg(call_mask_vector_imm_op_2517, 5, mask_vector_imm_op_2517_arg5); + setArg(call_mask_vector_imm_op_2517, 6, vm); + setArg(call_mask_vector_imm_op_2517, 7, vd); + setArg(call_mask_vector_imm_op_2517, 8, vs2); + setArg(call_mask_vector_imm_op_2517, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2517, 10, mask_vector_imm_op_2517_arg10); + } + cc.bind(label_merge); + } + auto tmp2519 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2519, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2519, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 597); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 598: VMSGTU__VX */ + continuation_e __vmsgtu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsgtu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSGTU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 598); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2520; + x86::Gp ret_val_illegal_vd_unmasked_2520 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2520, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2521 = get_reg(cc, 8, false); + mov(cc, tmp2521, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2521, ret_val_illegal_vd_unmasked_2520); + setArg(call_illegal_vd_unmasked_2520, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2520, 0, ret_val_illegal_vd_unmasked_2520); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2523; + x86::Gp ret_val_sew_2523 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2523, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2522; + auto mask_vector_imm_op_2522_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2522_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2522_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2522_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto mask_vector_imm_op_2522_arg10 = ret_val_sew_2523; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2522, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2523, 0, reinterpret_cast(this)); + setRet(call_sew_2523, 0, ret_val_sew_2523); + setArg(call_mask_vector_imm_op_2522, 0, V); + setArg(call_mask_vector_imm_op_2522, 1, 30); + setArg(call_mask_vector_imm_op_2522, 2, 4); + setArg(call_mask_vector_imm_op_2522, 3, mask_vector_imm_op_2522_arg3); + setArg(call_mask_vector_imm_op_2522, 4, mask_vector_imm_op_2522_arg4); + setArg(call_mask_vector_imm_op_2522, 5, mask_vector_imm_op_2522_arg5); + setArg(call_mask_vector_imm_op_2522, 6, vm); + setArg(call_mask_vector_imm_op_2522, 7, vd); + setArg(call_mask_vector_imm_op_2522, 8, vs2); + setArg(call_mask_vector_imm_op_2522, 9, mask_vector_imm_op_2522_arg9); + setArg(call_mask_vector_imm_op_2522, 10, mask_vector_imm_op_2522_arg10); + } + cc.bind(label_merge); + } + auto tmp2524 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2524, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2524, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 598); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 599: VMSGT__VI */ + continuation_e __vmsgt__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vmsgt.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSGT__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 599); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2525; + x86::Gp ret_val_illegal_vd_unmasked_2525 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2525, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2525; + setArg(call_illegal_vd_unmasked_2525, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2525, 0, ret_val_illegal_vd_unmasked_2525); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2527; + x86::Gp ret_val_sew_2527 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2527, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2526; + auto mask_vector_imm_op_2526_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2526_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2526_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2526_arg10 = ret_val_sew_2527; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2526, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2527, 0, reinterpret_cast(this)); + setRet(call_sew_2527, 0, ret_val_sew_2527); + setArg(call_mask_vector_imm_op_2526, 0, V); + setArg(call_mask_vector_imm_op_2526, 1, 31); + setArg(call_mask_vector_imm_op_2526, 2, 3); + setArg(call_mask_vector_imm_op_2526, 3, mask_vector_imm_op_2526_arg3); + setArg(call_mask_vector_imm_op_2526, 4, mask_vector_imm_op_2526_arg4); + setArg(call_mask_vector_imm_op_2526, 5, mask_vector_imm_op_2526_arg5); + setArg(call_mask_vector_imm_op_2526, 6, vm); + setArg(call_mask_vector_imm_op_2526, 7, vd); + setArg(call_mask_vector_imm_op_2526, 8, vs2); + setArg(call_mask_vector_imm_op_2526, 9, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_mask_vector_imm_op_2526, 10, mask_vector_imm_op_2526_arg10); + } + cc.bind(label_merge); + } + auto tmp2528 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2528, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2528, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 599); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 600: VMSGT__VX */ + continuation_e __vmsgt__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmsgt.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSGT__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 600); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2529; + x86::Gp ret_val_illegal_vd_unmasked_2529 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2529, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2530 = get_reg(cc, 8, false); + mov(cc, tmp2530, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2530, ret_val_illegal_vd_unmasked_2529); + setArg(call_illegal_vd_unmasked_2529, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2529, 0, ret_val_illegal_vd_unmasked_2529); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2532; + x86::Gp ret_val_sew_2532 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2532, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_vector_imm_op_2531; + auto mask_vector_imm_op_2531_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_vector_imm_op_2531_arg4 = load_reg_from_mem(jh, traits::vstart); + auto mask_vector_imm_op_2531_arg5 = load_reg_from_mem(jh, traits::vtype); + auto mask_vector_imm_op_2531_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto mask_vector_imm_op_2531_arg10 = ret_val_sew_2532; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_vector_imm_op_2531, &mask_vector_imm_op, FuncSignature::build()); + setArg(call_sew_2532, 0, reinterpret_cast(this)); + setRet(call_sew_2532, 0, ret_val_sew_2532); + setArg(call_mask_vector_imm_op_2531, 0, V); + setArg(call_mask_vector_imm_op_2531, 1, 31); + setArg(call_mask_vector_imm_op_2531, 2, 4); + setArg(call_mask_vector_imm_op_2531, 3, mask_vector_imm_op_2531_arg3); + setArg(call_mask_vector_imm_op_2531, 4, mask_vector_imm_op_2531_arg4); + setArg(call_mask_vector_imm_op_2531, 5, mask_vector_imm_op_2531_arg5); + setArg(call_mask_vector_imm_op_2531, 6, vm); + setArg(call_mask_vector_imm_op_2531, 7, vd); + setArg(call_mask_vector_imm_op_2531, 8, vs2); + setArg(call_mask_vector_imm_op_2531, 9, mask_vector_imm_op_2531_arg9); + setArg(call_mask_vector_imm_op_2531, 10, mask_vector_imm_op_2531_arg10); + } + cc.bind(label_merge); + } + auto tmp2533 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2533, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2533, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 600); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 601: VMINU__VV */ + continuation_e __vminu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vminu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMINU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 601); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2534; + x86::Gp ret_val_illegal_normal_2534 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2534, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2534; + setArg(call_illegal_normal_2534, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2534, 1, vd); + setArg(call_illegal_normal_2534, 2, vm); + setRet(call_illegal_normal_2534, 0, ret_val_illegal_normal_2534); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2536; + x86::Gp ret_val_sew_2536 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2536, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2535; + auto vector_vector_op_2535_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2535_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2535_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2535_arg10 = ret_val_sew_2536; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2535, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2536, 0, reinterpret_cast(this)); + setRet(call_sew_2536, 0, ret_val_sew_2536); + setArg(call_vector_vector_op_2535, 0, V); + setArg(call_vector_vector_op_2535, 1, 4); + setArg(call_vector_vector_op_2535, 2, 0); + setArg(call_vector_vector_op_2535, 3, vector_vector_op_2535_arg3); + setArg(call_vector_vector_op_2535, 4, vector_vector_op_2535_arg4); + setArg(call_vector_vector_op_2535, 5, vector_vector_op_2535_arg5); + setArg(call_vector_vector_op_2535, 6, vm); + setArg(call_vector_vector_op_2535, 7, vd); + setArg(call_vector_vector_op_2535, 8, vs2); + setArg(call_vector_vector_op_2535, 9, vs1); + setArg(call_vector_vector_op_2535, 10, vector_vector_op_2535_arg10); + } + cc.bind(label_merge); + } + auto tmp2537 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2537, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2537, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 601); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 602: VMINU__VX */ + continuation_e __vminu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vminu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMINU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 602); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2538; + x86::Gp ret_val_illegal_normal_2538 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2538, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2539 = get_reg(cc, 8, false); + mov(cc, tmp2539, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2539, ret_val_illegal_normal_2538); + setArg(call_illegal_normal_2538, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2538, 1, vd); + setArg(call_illegal_normal_2538, 2, vm); + setRet(call_illegal_normal_2538, 0, ret_val_illegal_normal_2538); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2541; + x86::Gp ret_val_sew_2541 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2541, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2540; + auto vector_imm_op_2540_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2540_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2540_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2540_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2540_arg10 = ret_val_sew_2541; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2540, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2541, 0, reinterpret_cast(this)); + setRet(call_sew_2541, 0, ret_val_sew_2541); + setArg(call_vector_imm_op_2540, 0, V); + setArg(call_vector_imm_op_2540, 1, 4); + setArg(call_vector_imm_op_2540, 2, 4); + setArg(call_vector_imm_op_2540, 3, vector_imm_op_2540_arg3); + setArg(call_vector_imm_op_2540, 4, vector_imm_op_2540_arg4); + setArg(call_vector_imm_op_2540, 5, vector_imm_op_2540_arg5); + setArg(call_vector_imm_op_2540, 6, vm); + setArg(call_vector_imm_op_2540, 7, vd); + setArg(call_vector_imm_op_2540, 8, vs2); + setArg(call_vector_imm_op_2540, 9, vector_imm_op_2540_arg9); + setArg(call_vector_imm_op_2540, 10, vector_imm_op_2540_arg10); + } + cc.bind(label_merge); + } + auto tmp2542 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2542, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2542, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 602); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 603: VMIN__VV */ + continuation_e __vmin__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmin.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMIN__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 603); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2543; + x86::Gp ret_val_illegal_normal_2543 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2543, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2543; + setArg(call_illegal_normal_2543, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2543, 1, vd); + setArg(call_illegal_normal_2543, 2, vm); + setRet(call_illegal_normal_2543, 0, ret_val_illegal_normal_2543); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2545; + x86::Gp ret_val_sew_2545 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2545, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2544; + auto vector_vector_op_2544_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2544_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2544_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2544_arg10 = ret_val_sew_2545; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2544, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2545, 0, reinterpret_cast(this)); + setRet(call_sew_2545, 0, ret_val_sew_2545); + setArg(call_vector_vector_op_2544, 0, V); + setArg(call_vector_vector_op_2544, 1, 5); + setArg(call_vector_vector_op_2544, 2, 0); + setArg(call_vector_vector_op_2544, 3, vector_vector_op_2544_arg3); + setArg(call_vector_vector_op_2544, 4, vector_vector_op_2544_arg4); + setArg(call_vector_vector_op_2544, 5, vector_vector_op_2544_arg5); + setArg(call_vector_vector_op_2544, 6, vm); + setArg(call_vector_vector_op_2544, 7, vd); + setArg(call_vector_vector_op_2544, 8, vs2); + setArg(call_vector_vector_op_2544, 9, vs1); + setArg(call_vector_vector_op_2544, 10, vector_vector_op_2544_arg10); + } + cc.bind(label_merge); + } + auto tmp2546 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2546, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2546, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 603); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 604: VMIN__VX */ + continuation_e __vmin__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmin.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMIN__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 604); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2547; + x86::Gp ret_val_illegal_normal_2547 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2547, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2548 = get_reg(cc, 8, false); + mov(cc, tmp2548, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2548, ret_val_illegal_normal_2547); + setArg(call_illegal_normal_2547, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2547, 1, vd); + setArg(call_illegal_normal_2547, 2, vm); + setRet(call_illegal_normal_2547, 0, ret_val_illegal_normal_2547); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2550; + x86::Gp ret_val_sew_2550 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2550, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2549; + auto vector_imm_op_2549_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2549_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2549_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2549_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2549_arg10 = ret_val_sew_2550; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2549, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2550, 0, reinterpret_cast(this)); + setRet(call_sew_2550, 0, ret_val_sew_2550); + setArg(call_vector_imm_op_2549, 0, V); + setArg(call_vector_imm_op_2549, 1, 5); + setArg(call_vector_imm_op_2549, 2, 4); + setArg(call_vector_imm_op_2549, 3, vector_imm_op_2549_arg3); + setArg(call_vector_imm_op_2549, 4, vector_imm_op_2549_arg4); + setArg(call_vector_imm_op_2549, 5, vector_imm_op_2549_arg5); + setArg(call_vector_imm_op_2549, 6, vm); + setArg(call_vector_imm_op_2549, 7, vd); + setArg(call_vector_imm_op_2549, 8, vs2); + setArg(call_vector_imm_op_2549, 9, vector_imm_op_2549_arg9); + setArg(call_vector_imm_op_2549, 10, vector_imm_op_2549_arg10); + } + cc.bind(label_merge); + } + auto tmp2551 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2551, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2551, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 604); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 605: VMAXU__VV */ + continuation_e __vmaxu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmaxu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMAXU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 605); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2552; + x86::Gp ret_val_illegal_normal_2552 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2552, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2552; + setArg(call_illegal_normal_2552, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2552, 1, vd); + setArg(call_illegal_normal_2552, 2, vm); + setRet(call_illegal_normal_2552, 0, ret_val_illegal_normal_2552); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2554; + x86::Gp ret_val_sew_2554 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2554, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2553; + auto vector_vector_op_2553_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2553_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2553_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2553_arg10 = ret_val_sew_2554; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2553, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2554, 0, reinterpret_cast(this)); + setRet(call_sew_2554, 0, ret_val_sew_2554); + setArg(call_vector_vector_op_2553, 0, V); + setArg(call_vector_vector_op_2553, 1, 6); + setArg(call_vector_vector_op_2553, 2, 0); + setArg(call_vector_vector_op_2553, 3, vector_vector_op_2553_arg3); + setArg(call_vector_vector_op_2553, 4, vector_vector_op_2553_arg4); + setArg(call_vector_vector_op_2553, 5, vector_vector_op_2553_arg5); + setArg(call_vector_vector_op_2553, 6, vm); + setArg(call_vector_vector_op_2553, 7, vd); + setArg(call_vector_vector_op_2553, 8, vs2); + setArg(call_vector_vector_op_2553, 9, vs1); + setArg(call_vector_vector_op_2553, 10, vector_vector_op_2553_arg10); + } + cc.bind(label_merge); + } + auto tmp2555 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2555, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2555, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 605); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 606: VMAXU__VX */ + continuation_e __vmaxu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmaxu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMAXU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 606); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2556; + x86::Gp ret_val_illegal_normal_2556 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2556, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2557 = get_reg(cc, 8, false); + mov(cc, tmp2557, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2557, ret_val_illegal_normal_2556); + setArg(call_illegal_normal_2556, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2556, 1, vd); + setArg(call_illegal_normal_2556, 2, vm); + setRet(call_illegal_normal_2556, 0, ret_val_illegal_normal_2556); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2559; + x86::Gp ret_val_sew_2559 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2559, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2558; + auto vector_imm_op_2558_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2558_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2558_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2558_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2558_arg10 = ret_val_sew_2559; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2558, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2559, 0, reinterpret_cast(this)); + setRet(call_sew_2559, 0, ret_val_sew_2559); + setArg(call_vector_imm_op_2558, 0, V); + setArg(call_vector_imm_op_2558, 1, 6); + setArg(call_vector_imm_op_2558, 2, 4); + setArg(call_vector_imm_op_2558, 3, vector_imm_op_2558_arg3); + setArg(call_vector_imm_op_2558, 4, vector_imm_op_2558_arg4); + setArg(call_vector_imm_op_2558, 5, vector_imm_op_2558_arg5); + setArg(call_vector_imm_op_2558, 6, vm); + setArg(call_vector_imm_op_2558, 7, vd); + setArg(call_vector_imm_op_2558, 8, vs2); + setArg(call_vector_imm_op_2558, 9, vector_imm_op_2558_arg9); + setArg(call_vector_imm_op_2558, 10, vector_imm_op_2558_arg10); + } + cc.bind(label_merge); + } + auto tmp2560 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2560, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2560, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 606); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 607: VMAX__VV */ + continuation_e __vmax__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vmax.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMAX__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 607); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2561; + x86::Gp ret_val_illegal_normal_2561 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2561, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2561; + setArg(call_illegal_normal_2561, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2561, 1, vd); + setArg(call_illegal_normal_2561, 2, vm); + setRet(call_illegal_normal_2561, 0, ret_val_illegal_normal_2561); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2563; + x86::Gp ret_val_sew_2563 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2563, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2562; + auto vector_vector_op_2562_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2562_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2562_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2562_arg10 = ret_val_sew_2563; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2562, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2563, 0, reinterpret_cast(this)); + setRet(call_sew_2563, 0, ret_val_sew_2563); + setArg(call_vector_vector_op_2562, 0, V); + setArg(call_vector_vector_op_2562, 1, 7); + setArg(call_vector_vector_op_2562, 2, 0); + setArg(call_vector_vector_op_2562, 3, vector_vector_op_2562_arg3); + setArg(call_vector_vector_op_2562, 4, vector_vector_op_2562_arg4); + setArg(call_vector_vector_op_2562, 5, vector_vector_op_2562_arg5); + setArg(call_vector_vector_op_2562, 6, vm); + setArg(call_vector_vector_op_2562, 7, vd); + setArg(call_vector_vector_op_2562, 8, vs2); + setArg(call_vector_vector_op_2562, 9, vs1); + setArg(call_vector_vector_op_2562, 10, vector_vector_op_2562_arg10); + } + cc.bind(label_merge); + } + auto tmp2564 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2564, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2564, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 607); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 608: VMAX__VX */ + continuation_e __vmax__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm},", fmt::arg("mnemonic", "vmax.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMAX__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 608); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2565; + x86::Gp ret_val_illegal_normal_2565 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2565, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2566 = get_reg(cc, 8, false); + mov(cc, tmp2566, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2566, ret_val_illegal_normal_2565); + setArg(call_illegal_normal_2565, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2565, 1, vd); + setArg(call_illegal_normal_2565, 2, vm); + setRet(call_illegal_normal_2565, 0, ret_val_illegal_normal_2565); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2568; + x86::Gp ret_val_sew_2568 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2568, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2567; + auto vector_imm_op_2567_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2567_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2567_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2567_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2567_arg10 = ret_val_sew_2568; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2567, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2568, 0, reinterpret_cast(this)); + setRet(call_sew_2568, 0, ret_val_sew_2568); + setArg(call_vector_imm_op_2567, 0, V); + setArg(call_vector_imm_op_2567, 1, 7); + setArg(call_vector_imm_op_2567, 2, 4); + setArg(call_vector_imm_op_2567, 3, vector_imm_op_2567_arg3); + setArg(call_vector_imm_op_2567, 4, vector_imm_op_2567_arg4); + setArg(call_vector_imm_op_2567, 5, vector_imm_op_2567_arg5); + setArg(call_vector_imm_op_2567, 6, vm); + setArg(call_vector_imm_op_2567, 7, vd); + setArg(call_vector_imm_op_2567, 8, vs2); + setArg(call_vector_imm_op_2567, 9, vector_imm_op_2567_arg9); + setArg(call_vector_imm_op_2567, 10, vector_imm_op_2567_arg10); + } + cc.bind(label_merge); + } + auto tmp2569 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2569, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2569, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 608); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 609: VMUL__VV */ + continuation_e __vmul__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMUL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 609); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2570; + x86::Gp ret_val_illegal_normal_2570 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2570, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2570; + setArg(call_illegal_normal_2570, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2570, 1, vd); + setArg(call_illegal_normal_2570, 2, vm); + setRet(call_illegal_normal_2570, 0, ret_val_illegal_normal_2570); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2572; + x86::Gp ret_val_sew_2572 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2572, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2571; + auto vector_vector_op_2571_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2571_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2571_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2571_arg10 = ret_val_sew_2572; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2571, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2572, 0, reinterpret_cast(this)); + setRet(call_sew_2572, 0, ret_val_sew_2572); + setArg(call_vector_vector_op_2571, 0, V); + setArg(call_vector_vector_op_2571, 1, 37); + setArg(call_vector_vector_op_2571, 2, 2); + setArg(call_vector_vector_op_2571, 3, vector_vector_op_2571_arg3); + setArg(call_vector_vector_op_2571, 4, vector_vector_op_2571_arg4); + setArg(call_vector_vector_op_2571, 5, vector_vector_op_2571_arg5); + setArg(call_vector_vector_op_2571, 6, vm); + setArg(call_vector_vector_op_2571, 7, vd); + setArg(call_vector_vector_op_2571, 8, vs2); + setArg(call_vector_vector_op_2571, 9, vs1); + setArg(call_vector_vector_op_2571, 10, vector_vector_op_2571_arg10); + } + cc.bind(label_merge); + } + auto tmp2573 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2573, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2573, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 609); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 610: VMUL__VX */ + continuation_e __vmul__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMUL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 610); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2574; + x86::Gp ret_val_illegal_normal_2574 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2574, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2575 = get_reg(cc, 8, false); + mov(cc, tmp2575, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2575, ret_val_illegal_normal_2574); + setArg(call_illegal_normal_2574, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2574, 1, vd); + setArg(call_illegal_normal_2574, 2, vm); + setRet(call_illegal_normal_2574, 0, ret_val_illegal_normal_2574); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2577; + x86::Gp ret_val_sew_2577 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2577, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2576; + auto vector_imm_op_2576_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2576_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2576_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2576_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2576_arg10 = ret_val_sew_2577; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2576, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2577, 0, reinterpret_cast(this)); + setRet(call_sew_2577, 0, ret_val_sew_2577); + setArg(call_vector_imm_op_2576, 0, V); + setArg(call_vector_imm_op_2576, 1, 37); + setArg(call_vector_imm_op_2576, 2, 6); + setArg(call_vector_imm_op_2576, 3, vector_imm_op_2576_arg3); + setArg(call_vector_imm_op_2576, 4, vector_imm_op_2576_arg4); + setArg(call_vector_imm_op_2576, 5, vector_imm_op_2576_arg5); + setArg(call_vector_imm_op_2576, 6, vm); + setArg(call_vector_imm_op_2576, 7, vd); + setArg(call_vector_imm_op_2576, 8, vs2); + setArg(call_vector_imm_op_2576, 9, vector_imm_op_2576_arg9); + setArg(call_vector_imm_op_2576, 10, vector_imm_op_2576_arg10); + } + cc.bind(label_merge); + } + auto tmp2578 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2578, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2578, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 610); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 611: VMULH__VV */ + continuation_e __vmulh__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulh.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULH__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 611); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2579; + x86::Gp ret_val_illegal_normal_2579 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2579, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2579; + setArg(call_illegal_normal_2579, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2579, 1, vd); + setArg(call_illegal_normal_2579, 2, vm); + setRet(call_illegal_normal_2579, 0, ret_val_illegal_normal_2579); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2581; + x86::Gp ret_val_sew_2581 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2581, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2580; + auto vector_vector_op_2580_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2580_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2580_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2580_arg10 = ret_val_sew_2581; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2580, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2581, 0, reinterpret_cast(this)); + setRet(call_sew_2581, 0, ret_val_sew_2581); + setArg(call_vector_vector_op_2580, 0, V); + setArg(call_vector_vector_op_2580, 1, 39); + setArg(call_vector_vector_op_2580, 2, 2); + setArg(call_vector_vector_op_2580, 3, vector_vector_op_2580_arg3); + setArg(call_vector_vector_op_2580, 4, vector_vector_op_2580_arg4); + setArg(call_vector_vector_op_2580, 5, vector_vector_op_2580_arg5); + setArg(call_vector_vector_op_2580, 6, vm); + setArg(call_vector_vector_op_2580, 7, vd); + setArg(call_vector_vector_op_2580, 8, vs2); + setArg(call_vector_vector_op_2580, 9, vs1); + setArg(call_vector_vector_op_2580, 10, vector_vector_op_2580_arg10); + } + cc.bind(label_merge); + } + auto tmp2582 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2582, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2582, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 611); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 612: VMULH__VX */ + continuation_e __vmulh__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulh.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULH__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 612); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2583; + x86::Gp ret_val_illegal_normal_2583 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2583, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2584 = get_reg(cc, 8, false); + mov(cc, tmp2584, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2584, ret_val_illegal_normal_2583); + setArg(call_illegal_normal_2583, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2583, 1, vd); + setArg(call_illegal_normal_2583, 2, vm); + setRet(call_illegal_normal_2583, 0, ret_val_illegal_normal_2583); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2586; + x86::Gp ret_val_sew_2586 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2586, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2585; + auto vector_imm_op_2585_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2585_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2585_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2585_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2585_arg10 = ret_val_sew_2586; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2585, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2586, 0, reinterpret_cast(this)); + setRet(call_sew_2586, 0, ret_val_sew_2586); + setArg(call_vector_imm_op_2585, 0, V); + setArg(call_vector_imm_op_2585, 1, 39); + setArg(call_vector_imm_op_2585, 2, 6); + setArg(call_vector_imm_op_2585, 3, vector_imm_op_2585_arg3); + setArg(call_vector_imm_op_2585, 4, vector_imm_op_2585_arg4); + setArg(call_vector_imm_op_2585, 5, vector_imm_op_2585_arg5); + setArg(call_vector_imm_op_2585, 6, vm); + setArg(call_vector_imm_op_2585, 7, vd); + setArg(call_vector_imm_op_2585, 8, vs2); + setArg(call_vector_imm_op_2585, 9, vector_imm_op_2585_arg9); + setArg(call_vector_imm_op_2585, 10, vector_imm_op_2585_arg10); + } + cc.bind(label_merge); + } + auto tmp2587 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2587, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2587, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 612); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 613: VMULHU__VV */ + continuation_e __vmulhu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulhu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULHU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 613); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2588; + x86::Gp ret_val_illegal_normal_2588 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2588, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2588; + setArg(call_illegal_normal_2588, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2588, 1, vd); + setArg(call_illegal_normal_2588, 2, vm); + setRet(call_illegal_normal_2588, 0, ret_val_illegal_normal_2588); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2590; + x86::Gp ret_val_sew_2590 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2590, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2589; + auto vector_vector_op_2589_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2589_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2589_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2589_arg10 = ret_val_sew_2590; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2589, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2590, 0, reinterpret_cast(this)); + setRet(call_sew_2590, 0, ret_val_sew_2590); + setArg(call_vector_vector_op_2589, 0, V); + setArg(call_vector_vector_op_2589, 1, 36); + setArg(call_vector_vector_op_2589, 2, 2); + setArg(call_vector_vector_op_2589, 3, vector_vector_op_2589_arg3); + setArg(call_vector_vector_op_2589, 4, vector_vector_op_2589_arg4); + setArg(call_vector_vector_op_2589, 5, vector_vector_op_2589_arg5); + setArg(call_vector_vector_op_2589, 6, vm); + setArg(call_vector_vector_op_2589, 7, vd); + setArg(call_vector_vector_op_2589, 8, vs2); + setArg(call_vector_vector_op_2589, 9, vs1); + setArg(call_vector_vector_op_2589, 10, vector_vector_op_2589_arg10); + } + cc.bind(label_merge); + } + auto tmp2591 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2591, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2591, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 613); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 614: VMULHU__VX */ + continuation_e __vmulhu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulhu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULHU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 614); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2592; + x86::Gp ret_val_illegal_normal_2592 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2592, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2593 = get_reg(cc, 8, false); + mov(cc, tmp2593, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2593, ret_val_illegal_normal_2592); + setArg(call_illegal_normal_2592, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2592, 1, vd); + setArg(call_illegal_normal_2592, 2, vm); + setRet(call_illegal_normal_2592, 0, ret_val_illegal_normal_2592); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2595; + x86::Gp ret_val_sew_2595 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2595, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2594; + auto vector_imm_op_2594_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2594_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2594_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2594_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2594_arg10 = ret_val_sew_2595; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2594, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2595, 0, reinterpret_cast(this)); + setRet(call_sew_2595, 0, ret_val_sew_2595); + setArg(call_vector_imm_op_2594, 0, V); + setArg(call_vector_imm_op_2594, 1, 36); + setArg(call_vector_imm_op_2594, 2, 6); + setArg(call_vector_imm_op_2594, 3, vector_imm_op_2594_arg3); + setArg(call_vector_imm_op_2594, 4, vector_imm_op_2594_arg4); + setArg(call_vector_imm_op_2594, 5, vector_imm_op_2594_arg5); + setArg(call_vector_imm_op_2594, 6, vm); + setArg(call_vector_imm_op_2594, 7, vd); + setArg(call_vector_imm_op_2594, 8, vs2); + setArg(call_vector_imm_op_2594, 9, vector_imm_op_2594_arg9); + setArg(call_vector_imm_op_2594, 10, vector_imm_op_2594_arg10); + } + cc.bind(label_merge); + } + auto tmp2596 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2596, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2596, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 614); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 615: VMULHSU__VV */ + continuation_e __vmulhsu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmulhsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULHSU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 615); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2597; + x86::Gp ret_val_illegal_normal_2597 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2597, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2597; + setArg(call_illegal_normal_2597, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2597, 1, vd); + setArg(call_illegal_normal_2597, 2, vm); + setRet(call_illegal_normal_2597, 0, ret_val_illegal_normal_2597); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2599; + x86::Gp ret_val_sew_2599 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2599, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2598; + auto vector_vector_op_2598_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2598_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2598_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2598_arg10 = ret_val_sew_2599; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2598, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2599, 0, reinterpret_cast(this)); + setRet(call_sew_2599, 0, ret_val_sew_2599); + setArg(call_vector_vector_op_2598, 0, V); + setArg(call_vector_vector_op_2598, 1, 38); + setArg(call_vector_vector_op_2598, 2, 2); + setArg(call_vector_vector_op_2598, 3, vector_vector_op_2598_arg3); + setArg(call_vector_vector_op_2598, 4, vector_vector_op_2598_arg4); + setArg(call_vector_vector_op_2598, 5, vector_vector_op_2598_arg5); + setArg(call_vector_vector_op_2598, 6, vm); + setArg(call_vector_vector_op_2598, 7, vd); + setArg(call_vector_vector_op_2598, 8, vs2); + setArg(call_vector_vector_op_2598, 9, vs1); + setArg(call_vector_vector_op_2598, 10, vector_vector_op_2598_arg10); + } + cc.bind(label_merge); + } + auto tmp2600 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2600, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2600, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 615); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 616: VMULHSU__VX */ + continuation_e __vmulhsu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmulhsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMULHSU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 616); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2601; + x86::Gp ret_val_illegal_normal_2601 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2601, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2602 = get_reg(cc, 8, false); + mov(cc, tmp2602, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2602, ret_val_illegal_normal_2601); + setArg(call_illegal_normal_2601, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2601, 1, vd); + setArg(call_illegal_normal_2601, 2, vm); + setRet(call_illegal_normal_2601, 0, ret_val_illegal_normal_2601); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2604; + x86::Gp ret_val_sew_2604 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2604, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2603; + auto vector_imm_op_2603_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2603_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2603_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2603_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2603_arg10 = ret_val_sew_2604; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2603, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2604, 0, reinterpret_cast(this)); + setRet(call_sew_2604, 0, ret_val_sew_2604); + setArg(call_vector_imm_op_2603, 0, V); + setArg(call_vector_imm_op_2603, 1, 38); + setArg(call_vector_imm_op_2603, 2, 6); + setArg(call_vector_imm_op_2603, 3, vector_imm_op_2603_arg3); + setArg(call_vector_imm_op_2603, 4, vector_imm_op_2603_arg4); + setArg(call_vector_imm_op_2603, 5, vector_imm_op_2603_arg5); + setArg(call_vector_imm_op_2603, 6, vm); + setArg(call_vector_imm_op_2603, 7, vd); + setArg(call_vector_imm_op_2603, 8, vs2); + setArg(call_vector_imm_op_2603, 9, vector_imm_op_2603_arg9); + setArg(call_vector_imm_op_2603, 10, vector_imm_op_2603_arg10); + } + cc.bind(label_merge); + } + auto tmp2605 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2605, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2605, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 616); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 617: VDIVU__VV */ + continuation_e __vdivu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vdivu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VDIVU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 617); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2606; + x86::Gp ret_val_illegal_normal_2606 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2606, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2606; + setArg(call_illegal_normal_2606, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2606, 1, vd); + setArg(call_illegal_normal_2606, 2, vm); + setRet(call_illegal_normal_2606, 0, ret_val_illegal_normal_2606); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2608; + x86::Gp ret_val_sew_2608 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2608, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2607; + auto vector_vector_op_2607_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2607_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2607_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2607_arg10 = ret_val_sew_2608; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2607, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2608, 0, reinterpret_cast(this)); + setRet(call_sew_2608, 0, ret_val_sew_2608); + setArg(call_vector_vector_op_2607, 0, V); + setArg(call_vector_vector_op_2607, 1, 32); + setArg(call_vector_vector_op_2607, 2, 2); + setArg(call_vector_vector_op_2607, 3, vector_vector_op_2607_arg3); + setArg(call_vector_vector_op_2607, 4, vector_vector_op_2607_arg4); + setArg(call_vector_vector_op_2607, 5, vector_vector_op_2607_arg5); + setArg(call_vector_vector_op_2607, 6, vm); + setArg(call_vector_vector_op_2607, 7, vd); + setArg(call_vector_vector_op_2607, 8, vs2); + setArg(call_vector_vector_op_2607, 9, vs1); + setArg(call_vector_vector_op_2607, 10, vector_vector_op_2607_arg10); + } + cc.bind(label_merge); + } + auto tmp2609 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2609, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2609, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 617); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 618: VDIVU__VX */ + continuation_e __vdivu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vdivu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VDIVU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 618); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2610; + x86::Gp ret_val_illegal_normal_2610 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2610, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2611 = get_reg(cc, 8, false); + mov(cc, tmp2611, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2611, ret_val_illegal_normal_2610); + setArg(call_illegal_normal_2610, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2610, 1, vd); + setArg(call_illegal_normal_2610, 2, vm); + setRet(call_illegal_normal_2610, 0, ret_val_illegal_normal_2610); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2613; + x86::Gp ret_val_sew_2613 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2613, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2612; + auto vector_imm_op_2612_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2612_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2612_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2612_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2612_arg10 = ret_val_sew_2613; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2612, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2613, 0, reinterpret_cast(this)); + setRet(call_sew_2613, 0, ret_val_sew_2613); + setArg(call_vector_imm_op_2612, 0, V); + setArg(call_vector_imm_op_2612, 1, 32); + setArg(call_vector_imm_op_2612, 2, 6); + setArg(call_vector_imm_op_2612, 3, vector_imm_op_2612_arg3); + setArg(call_vector_imm_op_2612, 4, vector_imm_op_2612_arg4); + setArg(call_vector_imm_op_2612, 5, vector_imm_op_2612_arg5); + setArg(call_vector_imm_op_2612, 6, vm); + setArg(call_vector_imm_op_2612, 7, vd); + setArg(call_vector_imm_op_2612, 8, vs2); + setArg(call_vector_imm_op_2612, 9, vector_imm_op_2612_arg9); + setArg(call_vector_imm_op_2612, 10, vector_imm_op_2612_arg10); + } + cc.bind(label_merge); + } + auto tmp2614 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2614, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2614, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 618); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 619: VDIV__VV */ + continuation_e __vdiv__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vdiv.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VDIV__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 619); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2615; + x86::Gp ret_val_illegal_normal_2615 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2615, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2615; + setArg(call_illegal_normal_2615, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2615, 1, vd); + setArg(call_illegal_normal_2615, 2, vm); + setRet(call_illegal_normal_2615, 0, ret_val_illegal_normal_2615); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2617; + x86::Gp ret_val_sew_2617 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2617, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2616; + auto vector_vector_op_2616_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2616_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2616_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2616_arg10 = ret_val_sew_2617; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2616, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2617, 0, reinterpret_cast(this)); + setRet(call_sew_2617, 0, ret_val_sew_2617); + setArg(call_vector_vector_op_2616, 0, V); + setArg(call_vector_vector_op_2616, 1, 33); + setArg(call_vector_vector_op_2616, 2, 2); + setArg(call_vector_vector_op_2616, 3, vector_vector_op_2616_arg3); + setArg(call_vector_vector_op_2616, 4, vector_vector_op_2616_arg4); + setArg(call_vector_vector_op_2616, 5, vector_vector_op_2616_arg5); + setArg(call_vector_vector_op_2616, 6, vm); + setArg(call_vector_vector_op_2616, 7, vd); + setArg(call_vector_vector_op_2616, 8, vs2); + setArg(call_vector_vector_op_2616, 9, vs1); + setArg(call_vector_vector_op_2616, 10, vector_vector_op_2616_arg10); + } + cc.bind(label_merge); + } + auto tmp2618 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2618, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2618, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 619); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 620: VDIV__VX */ + continuation_e __vdiv__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vdiv.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VDIV__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 620); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2619; + x86::Gp ret_val_illegal_normal_2619 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2619, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2620 = get_reg(cc, 8, false); + mov(cc, tmp2620, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2620, ret_val_illegal_normal_2619); + setArg(call_illegal_normal_2619, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2619, 1, vd); + setArg(call_illegal_normal_2619, 2, vm); + setRet(call_illegal_normal_2619, 0, ret_val_illegal_normal_2619); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2622; + x86::Gp ret_val_sew_2622 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2622, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2621; + auto vector_imm_op_2621_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2621_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2621_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2621_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2621_arg10 = ret_val_sew_2622; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2621, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2622, 0, reinterpret_cast(this)); + setRet(call_sew_2622, 0, ret_val_sew_2622); + setArg(call_vector_imm_op_2621, 0, V); + setArg(call_vector_imm_op_2621, 1, 33); + setArg(call_vector_imm_op_2621, 2, 6); + setArg(call_vector_imm_op_2621, 3, vector_imm_op_2621_arg3); + setArg(call_vector_imm_op_2621, 4, vector_imm_op_2621_arg4); + setArg(call_vector_imm_op_2621, 5, vector_imm_op_2621_arg5); + setArg(call_vector_imm_op_2621, 6, vm); + setArg(call_vector_imm_op_2621, 7, vd); + setArg(call_vector_imm_op_2621, 8, vs2); + setArg(call_vector_imm_op_2621, 9, vector_imm_op_2621_arg9); + setArg(call_vector_imm_op_2621, 10, vector_imm_op_2621_arg10); + } + cc.bind(label_merge); + } + auto tmp2623 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2623, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2623, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 620); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 621: VREMU__VV */ + continuation_e __vremu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vremu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREMU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 621); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2624; + x86::Gp ret_val_illegal_normal_2624 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2624, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2624; + setArg(call_illegal_normal_2624, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2624, 1, vd); + setArg(call_illegal_normal_2624, 2, vm); + setRet(call_illegal_normal_2624, 0, ret_val_illegal_normal_2624); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2626; + x86::Gp ret_val_sew_2626 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2626, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2625; + auto vector_vector_op_2625_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2625_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2625_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2625_arg10 = ret_val_sew_2626; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2625, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2626, 0, reinterpret_cast(this)); + setRet(call_sew_2626, 0, ret_val_sew_2626); + setArg(call_vector_vector_op_2625, 0, V); + setArg(call_vector_vector_op_2625, 1, 34); + setArg(call_vector_vector_op_2625, 2, 2); + setArg(call_vector_vector_op_2625, 3, vector_vector_op_2625_arg3); + setArg(call_vector_vector_op_2625, 4, vector_vector_op_2625_arg4); + setArg(call_vector_vector_op_2625, 5, vector_vector_op_2625_arg5); + setArg(call_vector_vector_op_2625, 6, vm); + setArg(call_vector_vector_op_2625, 7, vd); + setArg(call_vector_vector_op_2625, 8, vs2); + setArg(call_vector_vector_op_2625, 9, vs1); + setArg(call_vector_vector_op_2625, 10, vector_vector_op_2625_arg10); + } + cc.bind(label_merge); + } + auto tmp2627 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2627, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2627, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 621); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 622: VREMU__VX */ + continuation_e __vremu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vremu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREMU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 622); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2628; + x86::Gp ret_val_illegal_normal_2628 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2628, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2629 = get_reg(cc, 8, false); + mov(cc, tmp2629, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2629, ret_val_illegal_normal_2628); + setArg(call_illegal_normal_2628, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2628, 1, vd); + setArg(call_illegal_normal_2628, 2, vm); + setRet(call_illegal_normal_2628, 0, ret_val_illegal_normal_2628); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2631; + x86::Gp ret_val_sew_2631 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2631, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2630; + auto vector_imm_op_2630_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2630_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2630_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2630_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2630_arg10 = ret_val_sew_2631; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2630, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2631, 0, reinterpret_cast(this)); + setRet(call_sew_2631, 0, ret_val_sew_2631); + setArg(call_vector_imm_op_2630, 0, V); + setArg(call_vector_imm_op_2630, 1, 34); + setArg(call_vector_imm_op_2630, 2, 6); + setArg(call_vector_imm_op_2630, 3, vector_imm_op_2630_arg3); + setArg(call_vector_imm_op_2630, 4, vector_imm_op_2630_arg4); + setArg(call_vector_imm_op_2630, 5, vector_imm_op_2630_arg5); + setArg(call_vector_imm_op_2630, 6, vm); + setArg(call_vector_imm_op_2630, 7, vd); + setArg(call_vector_imm_op_2630, 8, vs2); + setArg(call_vector_imm_op_2630, 9, vector_imm_op_2630_arg9); + setArg(call_vector_imm_op_2630, 10, vector_imm_op_2630_arg10); + } + cc.bind(label_merge); + } + auto tmp2632 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2632, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2632, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 622); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 623: VREM__VV */ + continuation_e __vrem__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrem.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREM__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 623); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2633; + x86::Gp ret_val_illegal_normal_2633 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2633, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2633; + setArg(call_illegal_normal_2633, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2633, 1, vd); + setArg(call_illegal_normal_2633, 2, vm); + setRet(call_illegal_normal_2633, 0, ret_val_illegal_normal_2633); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2635; + x86::Gp ret_val_sew_2635 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2635, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2634; + auto vector_vector_op_2634_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2634_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2634_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2634_arg10 = ret_val_sew_2635; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2634, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2635, 0, reinterpret_cast(this)); + setRet(call_sew_2635, 0, ret_val_sew_2635); + setArg(call_vector_vector_op_2634, 0, V); + setArg(call_vector_vector_op_2634, 1, 35); + setArg(call_vector_vector_op_2634, 2, 2); + setArg(call_vector_vector_op_2634, 3, vector_vector_op_2634_arg3); + setArg(call_vector_vector_op_2634, 4, vector_vector_op_2634_arg4); + setArg(call_vector_vector_op_2634, 5, vector_vector_op_2634_arg5); + setArg(call_vector_vector_op_2634, 6, vm); + setArg(call_vector_vector_op_2634, 7, vd); + setArg(call_vector_vector_op_2634, 8, vs2); + setArg(call_vector_vector_op_2634, 9, vs1); + setArg(call_vector_vector_op_2634, 10, vector_vector_op_2634_arg10); + } + cc.bind(label_merge); + } + auto tmp2636 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2636, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2636, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 623); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 624: VREM__VX */ + continuation_e __vrem__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrem.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREM__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 624); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2637; + x86::Gp ret_val_illegal_normal_2637 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2637, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2638 = get_reg(cc, 8, false); + mov(cc, tmp2638, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2638, ret_val_illegal_normal_2637); + setArg(call_illegal_normal_2637, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2637, 1, vd); + setArg(call_illegal_normal_2637, 2, vm); + setRet(call_illegal_normal_2637, 0, ret_val_illegal_normal_2637); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2640; + x86::Gp ret_val_sew_2640 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2640, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2639; + auto vector_imm_op_2639_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2639_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2639_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2639_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2639_arg10 = ret_val_sew_2640; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2639, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2640, 0, reinterpret_cast(this)); + setRet(call_sew_2640, 0, ret_val_sew_2640); + setArg(call_vector_imm_op_2639, 0, V); + setArg(call_vector_imm_op_2639, 1, 35); + setArg(call_vector_imm_op_2639, 2, 6); + setArg(call_vector_imm_op_2639, 3, vector_imm_op_2639_arg3); + setArg(call_vector_imm_op_2639, 4, vector_imm_op_2639_arg4); + setArg(call_vector_imm_op_2639, 5, vector_imm_op_2639_arg5); + setArg(call_vector_imm_op_2639, 6, vm); + setArg(call_vector_imm_op_2639, 7, vd); + setArg(call_vector_imm_op_2639, 8, vs2); + setArg(call_vector_imm_op_2639, 9, vector_imm_op_2639_arg9); + setArg(call_vector_imm_op_2639, 10, vector_imm_op_2639_arg10); + } + cc.bind(label_merge); + } + auto tmp2641 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2641, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2641, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 624); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 625: VWMUL__VV */ + continuation_e __vwmul__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMUL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 625); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2642; + x86::Gp ret_val_get_sew_pow_2642 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2642, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2643 = get_reg(cc, 8, false); + mov(cc, tmp2643, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2643, ret_val_get_sew_pow_2642)), 8, false), ~ 1); + setArg(call_get_sew_pow_2642, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2642, 0, ret_val_get_sew_pow_2642); + InvokeNode* call_get_lmul_pow_2644; + x86::Gp ret_val_get_lmul_pow_2644 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2644, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2644; + setArg(call_get_lmul_pow_2644, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2644, 0, ret_val_get_lmul_pow_2644); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2645; + auto illegal_variable_width_2645_arg2 = SEW_widen; + auto illegal_variable_width_2645_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2645 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2645, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2646; + auto valid_reg_overlap_2646_arg2 = LMUL_pow; + auto valid_reg_overlap_2646_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2646 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2646, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2647; + auto valid_reg_overlap_2647_arg2 = LMUL_pow; + auto valid_reg_overlap_2647_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2647 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2647, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2645, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2646)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2647)); + setArg(call_illegal_variable_width_2645, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2645, 1, vd); + setArg(call_illegal_variable_width_2645, 2, vm); + setArg(call_illegal_variable_width_2645, 3, illegal_variable_width_2645_arg2); + setArg(call_illegal_variable_width_2645, 4, illegal_variable_width_2645_arg3); + setRet(call_illegal_variable_width_2645, 0, ret_val_illegal_variable_width_2645); + setArg(call_valid_reg_overlap_2646, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2646, 1, vs1); + setArg(call_valid_reg_overlap_2646, 2, vd); + setArg(call_valid_reg_overlap_2646, 3, valid_reg_overlap_2646_arg2); + setArg(call_valid_reg_overlap_2646, 4, valid_reg_overlap_2646_arg3); + setRet(call_valid_reg_overlap_2646, 0, ret_val_valid_reg_overlap_2646); + setArg(call_valid_reg_overlap_2647, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2647, 1, vs2); + setArg(call_valid_reg_overlap_2647, 2, vd); + setArg(call_valid_reg_overlap_2647, 3, valid_reg_overlap_2647_arg2); + setArg(call_valid_reg_overlap_2647, 4, valid_reg_overlap_2647_arg3); + setRet(call_valid_reg_overlap_2647, 0, ret_val_valid_reg_overlap_2647); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2649; + x86::Gp ret_val_sew_2649 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2649, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2648; + auto vector_vector_wv_2648_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2648_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2648_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2648_arg10 = ret_val_sew_2649; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2648, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2649, 0, reinterpret_cast(this)); + setRet(call_sew_2649, 0, ret_val_sew_2649); + setArg(call_vector_vector_wv_2648, 0, V); + setArg(call_vector_vector_wv_2648, 1, 59); + setArg(call_vector_vector_wv_2648, 2, 2); + setArg(call_vector_vector_wv_2648, 3, vector_vector_wv_2648_arg3); + setArg(call_vector_vector_wv_2648, 4, vector_vector_wv_2648_arg4); + setArg(call_vector_vector_wv_2648, 5, vector_vector_wv_2648_arg5); + setArg(call_vector_vector_wv_2648, 6, vm); + setArg(call_vector_vector_wv_2648, 7, vd); + setArg(call_vector_vector_wv_2648, 8, vs2); + setArg(call_vector_vector_wv_2648, 9, vs1); + setArg(call_vector_vector_wv_2648, 10, vector_vector_wv_2648_arg10); + } + cc.bind(label_merge); + } + auto tmp2650 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2650, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2650, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 625); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 626: VWMUL__VX */ + continuation_e __vwmul__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMUL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 626); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2651; + x86::Gp ret_val_get_sew_pow_2651 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2651, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2652 = get_reg(cc, 8, false); + mov(cc, tmp2652, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2652, ret_val_get_sew_pow_2651)), 8, false), ~ 1); + setArg(call_get_sew_pow_2651, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2651, 0, ret_val_get_sew_pow_2651); + InvokeNode* call_get_lmul_pow_2653; + x86::Gp ret_val_get_lmul_pow_2653 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2653, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2653; + setArg(call_get_lmul_pow_2653, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2653, 0, ret_val_get_lmul_pow_2653); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2654; + auto illegal_variable_width_2654_arg2 = SEW_widen; + auto illegal_variable_width_2654_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2654 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2654, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2655; + auto valid_reg_overlap_2655_arg2 = LMUL_pow; + auto valid_reg_overlap_2655_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2655 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2655, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2654, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2655)); + setArg(call_illegal_variable_width_2654, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2654, 1, vd); + setArg(call_illegal_variable_width_2654, 2, vm); + setArg(call_illegal_variable_width_2654, 3, illegal_variable_width_2654_arg2); + setArg(call_illegal_variable_width_2654, 4, illegal_variable_width_2654_arg3); + setRet(call_illegal_variable_width_2654, 0, ret_val_illegal_variable_width_2654); + setArg(call_valid_reg_overlap_2655, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2655, 1, vs2); + setArg(call_valid_reg_overlap_2655, 2, vd); + setArg(call_valid_reg_overlap_2655, 3, valid_reg_overlap_2655_arg2); + setArg(call_valid_reg_overlap_2655, 4, valid_reg_overlap_2655_arg3); + setRet(call_valid_reg_overlap_2655, 0, ret_val_valid_reg_overlap_2655); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2657; + x86::Gp ret_val_sew_2657 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2657, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2656; + auto vector_imm_wv_2656_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2656_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2656_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2656_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2656_arg10 = ret_val_sew_2657; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2656, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2657, 0, reinterpret_cast(this)); + setRet(call_sew_2657, 0, ret_val_sew_2657); + setArg(call_vector_imm_wv_2656, 0, V); + setArg(call_vector_imm_wv_2656, 1, 59); + setArg(call_vector_imm_wv_2656, 2, 6); + setArg(call_vector_imm_wv_2656, 3, vector_imm_wv_2656_arg3); + setArg(call_vector_imm_wv_2656, 4, vector_imm_wv_2656_arg4); + setArg(call_vector_imm_wv_2656, 5, vector_imm_wv_2656_arg5); + setArg(call_vector_imm_wv_2656, 6, vm); + setArg(call_vector_imm_wv_2656, 7, vd); + setArg(call_vector_imm_wv_2656, 8, vs2); + setArg(call_vector_imm_wv_2656, 9, vector_imm_wv_2656_arg9); + setArg(call_vector_imm_wv_2656, 10, vector_imm_wv_2656_arg10); + } + cc.bind(label_merge); + } + auto tmp2658 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2658, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2658, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 626); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 627: VWMULU__VV */ + continuation_e __vwmulu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmulu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMULU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 627); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2659; + x86::Gp ret_val_get_sew_pow_2659 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2659, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2660 = get_reg(cc, 8, false); + mov(cc, tmp2660, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2660, ret_val_get_sew_pow_2659)), 8, false), ~ 1); + setArg(call_get_sew_pow_2659, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2659, 0, ret_val_get_sew_pow_2659); + InvokeNode* call_get_lmul_pow_2661; + x86::Gp ret_val_get_lmul_pow_2661 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2661, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2661; + setArg(call_get_lmul_pow_2661, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2661, 0, ret_val_get_lmul_pow_2661); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2662; + auto illegal_variable_width_2662_arg2 = SEW_widen; + auto illegal_variable_width_2662_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2662 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2662, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2663; + auto valid_reg_overlap_2663_arg2 = LMUL_pow; + auto valid_reg_overlap_2663_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2663 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2663, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2664; + auto valid_reg_overlap_2664_arg2 = LMUL_pow; + auto valid_reg_overlap_2664_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2664 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2664, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2662, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2663)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2664)); + setArg(call_illegal_variable_width_2662, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2662, 1, vd); + setArg(call_illegal_variable_width_2662, 2, vm); + setArg(call_illegal_variable_width_2662, 3, illegal_variable_width_2662_arg2); + setArg(call_illegal_variable_width_2662, 4, illegal_variable_width_2662_arg3); + setRet(call_illegal_variable_width_2662, 0, ret_val_illegal_variable_width_2662); + setArg(call_valid_reg_overlap_2663, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2663, 1, vs1); + setArg(call_valid_reg_overlap_2663, 2, vd); + setArg(call_valid_reg_overlap_2663, 3, valid_reg_overlap_2663_arg2); + setArg(call_valid_reg_overlap_2663, 4, valid_reg_overlap_2663_arg3); + setRet(call_valid_reg_overlap_2663, 0, ret_val_valid_reg_overlap_2663); + setArg(call_valid_reg_overlap_2664, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2664, 1, vs2); + setArg(call_valid_reg_overlap_2664, 2, vd); + setArg(call_valid_reg_overlap_2664, 3, valid_reg_overlap_2664_arg2); + setArg(call_valid_reg_overlap_2664, 4, valid_reg_overlap_2664_arg3); + setRet(call_valid_reg_overlap_2664, 0, ret_val_valid_reg_overlap_2664); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2666; + x86::Gp ret_val_sew_2666 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2666, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2665; + auto vector_vector_wv_2665_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2665_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2665_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2665_arg10 = ret_val_sew_2666; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2665, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2666, 0, reinterpret_cast(this)); + setRet(call_sew_2666, 0, ret_val_sew_2666); + setArg(call_vector_vector_wv_2665, 0, V); + setArg(call_vector_vector_wv_2665, 1, 56); + setArg(call_vector_vector_wv_2665, 2, 2); + setArg(call_vector_vector_wv_2665, 3, vector_vector_wv_2665_arg3); + setArg(call_vector_vector_wv_2665, 4, vector_vector_wv_2665_arg4); + setArg(call_vector_vector_wv_2665, 5, vector_vector_wv_2665_arg5); + setArg(call_vector_vector_wv_2665, 6, vm); + setArg(call_vector_vector_wv_2665, 7, vd); + setArg(call_vector_vector_wv_2665, 8, vs2); + setArg(call_vector_vector_wv_2665, 9, vs1); + setArg(call_vector_vector_wv_2665, 10, vector_vector_wv_2665_arg10); + } + cc.bind(label_merge); + } + auto tmp2667 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2667, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2667, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 627); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 628: VWMULU__VX */ + continuation_e __vwmulu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmulu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMULU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 628); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2668; + x86::Gp ret_val_get_sew_pow_2668 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2668, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2669 = get_reg(cc, 8, false); + mov(cc, tmp2669, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2669, ret_val_get_sew_pow_2668)), 8, false), ~ 1); + setArg(call_get_sew_pow_2668, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2668, 0, ret_val_get_sew_pow_2668); + InvokeNode* call_get_lmul_pow_2670; + x86::Gp ret_val_get_lmul_pow_2670 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2670, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2670; + setArg(call_get_lmul_pow_2670, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2670, 0, ret_val_get_lmul_pow_2670); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2671; + auto illegal_variable_width_2671_arg2 = SEW_widen; + auto illegal_variable_width_2671_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2671 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2671, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2672; + auto valid_reg_overlap_2672_arg2 = LMUL_pow; + auto valid_reg_overlap_2672_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2672 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2672, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2671, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2672)); + setArg(call_illegal_variable_width_2671, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2671, 1, vd); + setArg(call_illegal_variable_width_2671, 2, vm); + setArg(call_illegal_variable_width_2671, 3, illegal_variable_width_2671_arg2); + setArg(call_illegal_variable_width_2671, 4, illegal_variable_width_2671_arg3); + setRet(call_illegal_variable_width_2671, 0, ret_val_illegal_variable_width_2671); + setArg(call_valid_reg_overlap_2672, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2672, 1, vs2); + setArg(call_valid_reg_overlap_2672, 2, vd); + setArg(call_valid_reg_overlap_2672, 3, valid_reg_overlap_2672_arg2); + setArg(call_valid_reg_overlap_2672, 4, valid_reg_overlap_2672_arg3); + setRet(call_valid_reg_overlap_2672, 0, ret_val_valid_reg_overlap_2672); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2674; + x86::Gp ret_val_sew_2674 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2674, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2673; + auto vector_imm_wv_2673_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2673_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2673_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2673_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2673_arg10 = ret_val_sew_2674; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2673, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2674, 0, reinterpret_cast(this)); + setRet(call_sew_2674, 0, ret_val_sew_2674); + setArg(call_vector_imm_wv_2673, 0, V); + setArg(call_vector_imm_wv_2673, 1, 56); + setArg(call_vector_imm_wv_2673, 2, 6); + setArg(call_vector_imm_wv_2673, 3, vector_imm_wv_2673_arg3); + setArg(call_vector_imm_wv_2673, 4, vector_imm_wv_2673_arg4); + setArg(call_vector_imm_wv_2673, 5, vector_imm_wv_2673_arg5); + setArg(call_vector_imm_wv_2673, 6, vm); + setArg(call_vector_imm_wv_2673, 7, vd); + setArg(call_vector_imm_wv_2673, 8, vs2); + setArg(call_vector_imm_wv_2673, 9, vector_imm_wv_2673_arg9); + setArg(call_vector_imm_wv_2673, 10, vector_imm_wv_2673_arg10); + } + cc.bind(label_merge); + } + auto tmp2675 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2675, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2675, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 628); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 629: VWMULSU__VV */ + continuation_e __vwmulsu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmulsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMULSU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 629); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2676; + x86::Gp ret_val_get_sew_pow_2676 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2676, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2677 = get_reg(cc, 8, false); + mov(cc, tmp2677, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2677, ret_val_get_sew_pow_2676)), 8, false), ~ 1); + setArg(call_get_sew_pow_2676, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2676, 0, ret_val_get_sew_pow_2676); + InvokeNode* call_get_lmul_pow_2678; + x86::Gp ret_val_get_lmul_pow_2678 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2678, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2678; + setArg(call_get_lmul_pow_2678, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2678, 0, ret_val_get_lmul_pow_2678); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2679; + auto illegal_variable_width_2679_arg2 = SEW_widen; + auto illegal_variable_width_2679_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2679 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2679, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2680; + auto valid_reg_overlap_2680_arg2 = LMUL_pow; + auto valid_reg_overlap_2680_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2680 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2680, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2681; + auto valid_reg_overlap_2681_arg2 = LMUL_pow; + auto valid_reg_overlap_2681_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2681 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2681, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2679, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2680)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2681)); + setArg(call_illegal_variable_width_2679, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2679, 1, vd); + setArg(call_illegal_variable_width_2679, 2, vm); + setArg(call_illegal_variable_width_2679, 3, illegal_variable_width_2679_arg2); + setArg(call_illegal_variable_width_2679, 4, illegal_variable_width_2679_arg3); + setRet(call_illegal_variable_width_2679, 0, ret_val_illegal_variable_width_2679); + setArg(call_valid_reg_overlap_2680, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2680, 1, vs1); + setArg(call_valid_reg_overlap_2680, 2, vd); + setArg(call_valid_reg_overlap_2680, 3, valid_reg_overlap_2680_arg2); + setArg(call_valid_reg_overlap_2680, 4, valid_reg_overlap_2680_arg3); + setRet(call_valid_reg_overlap_2680, 0, ret_val_valid_reg_overlap_2680); + setArg(call_valid_reg_overlap_2681, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2681, 1, vs2); + setArg(call_valid_reg_overlap_2681, 2, vd); + setArg(call_valid_reg_overlap_2681, 3, valid_reg_overlap_2681_arg2); + setArg(call_valid_reg_overlap_2681, 4, valid_reg_overlap_2681_arg3); + setRet(call_valid_reg_overlap_2681, 0, ret_val_valid_reg_overlap_2681); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2683; + x86::Gp ret_val_sew_2683 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2683, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2682; + auto vector_vector_wv_2682_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2682_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2682_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2682_arg10 = ret_val_sew_2683; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2682, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2683, 0, reinterpret_cast(this)); + setRet(call_sew_2683, 0, ret_val_sew_2683); + setArg(call_vector_vector_wv_2682, 0, V); + setArg(call_vector_vector_wv_2682, 1, 58); + setArg(call_vector_vector_wv_2682, 2, 2); + setArg(call_vector_vector_wv_2682, 3, vector_vector_wv_2682_arg3); + setArg(call_vector_vector_wv_2682, 4, vector_vector_wv_2682_arg4); + setArg(call_vector_vector_wv_2682, 5, vector_vector_wv_2682_arg5); + setArg(call_vector_vector_wv_2682, 6, vm); + setArg(call_vector_vector_wv_2682, 7, vd); + setArg(call_vector_vector_wv_2682, 8, vs2); + setArg(call_vector_vector_wv_2682, 9, vs1); + setArg(call_vector_vector_wv_2682, 10, vector_vector_wv_2682_arg10); + } + cc.bind(label_merge); + } + auto tmp2684 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2684, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2684, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 629); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 630: VWMULSU__VX */ + continuation_e __vwmulsu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmulsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMULSU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 630); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2685; + x86::Gp ret_val_get_sew_pow_2685 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2685, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2686 = get_reg(cc, 8, false); + mov(cc, tmp2686, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2686, ret_val_get_sew_pow_2685)), 8, false), ~ 1); + setArg(call_get_sew_pow_2685, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2685, 0, ret_val_get_sew_pow_2685); + InvokeNode* call_get_lmul_pow_2687; + x86::Gp ret_val_get_lmul_pow_2687 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2687, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2687; + setArg(call_get_lmul_pow_2687, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2687, 0, ret_val_get_lmul_pow_2687); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2688; + auto illegal_variable_width_2688_arg2 = SEW_widen; + auto illegal_variable_width_2688_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2688 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2688, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2689; + auto valid_reg_overlap_2689_arg2 = LMUL_pow; + auto valid_reg_overlap_2689_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2689 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2689, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2688, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2689)); + setArg(call_illegal_variable_width_2688, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2688, 1, vd); + setArg(call_illegal_variable_width_2688, 2, vm); + setArg(call_illegal_variable_width_2688, 3, illegal_variable_width_2688_arg2); + setArg(call_illegal_variable_width_2688, 4, illegal_variable_width_2688_arg3); + setRet(call_illegal_variable_width_2688, 0, ret_val_illegal_variable_width_2688); + setArg(call_valid_reg_overlap_2689, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2689, 1, vs2); + setArg(call_valid_reg_overlap_2689, 2, vd); + setArg(call_valid_reg_overlap_2689, 3, valid_reg_overlap_2689_arg2); + setArg(call_valid_reg_overlap_2689, 4, valid_reg_overlap_2689_arg3); + setRet(call_valid_reg_overlap_2689, 0, ret_val_valid_reg_overlap_2689); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2691; + x86::Gp ret_val_sew_2691 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2691, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2690; + auto vector_imm_wv_2690_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2690_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2690_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2690_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2690_arg10 = ret_val_sew_2691; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2690, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2691, 0, reinterpret_cast(this)); + setRet(call_sew_2691, 0, ret_val_sew_2691); + setArg(call_vector_imm_wv_2690, 0, V); + setArg(call_vector_imm_wv_2690, 1, 58); + setArg(call_vector_imm_wv_2690, 2, 6); + setArg(call_vector_imm_wv_2690, 3, vector_imm_wv_2690_arg3); + setArg(call_vector_imm_wv_2690, 4, vector_imm_wv_2690_arg4); + setArg(call_vector_imm_wv_2690, 5, vector_imm_wv_2690_arg5); + setArg(call_vector_imm_wv_2690, 6, vm); + setArg(call_vector_imm_wv_2690, 7, vd); + setArg(call_vector_imm_wv_2690, 8, vs2); + setArg(call_vector_imm_wv_2690, 9, vector_imm_wv_2690_arg9); + setArg(call_vector_imm_wv_2690, 10, vector_imm_wv_2690_arg10); + } + cc.bind(label_merge); + } + auto tmp2692 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2692, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2692, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 630); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 631: VMACC__VV */ + continuation_e __vmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 631); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2693; + x86::Gp ret_val_illegal_normal_2693 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2693, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2693; + setArg(call_illegal_normal_2693, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2693, 1, vd); + setArg(call_illegal_normal_2693, 2, vm); + setRet(call_illegal_normal_2693, 0, ret_val_illegal_normal_2693); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2695; + x86::Gp ret_val_sew_2695 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2695, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2694; + auto vector_vector_op_2694_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2694_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2694_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2694_arg10 = ret_val_sew_2695; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2694, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2695, 0, reinterpret_cast(this)); + setRet(call_sew_2695, 0, ret_val_sew_2695); + setArg(call_vector_vector_op_2694, 0, V); + setArg(call_vector_vector_op_2694, 1, 45); + setArg(call_vector_vector_op_2694, 2, 2); + setArg(call_vector_vector_op_2694, 3, vector_vector_op_2694_arg3); + setArg(call_vector_vector_op_2694, 4, vector_vector_op_2694_arg4); + setArg(call_vector_vector_op_2694, 5, vector_vector_op_2694_arg5); + setArg(call_vector_vector_op_2694, 6, vm); + setArg(call_vector_vector_op_2694, 7, vd); + setArg(call_vector_vector_op_2694, 8, vs2); + setArg(call_vector_vector_op_2694, 9, vs1); + setArg(call_vector_vector_op_2694, 10, vector_vector_op_2694_arg10); + } + cc.bind(label_merge); + } + auto tmp2696 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2696, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2696, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 631); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 632: VMACC__VX */ + continuation_e __vmacc__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmacc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMACC__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 632); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2697; + x86::Gp ret_val_illegal_normal_2697 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2697, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2698 = get_reg(cc, 8, false); + mov(cc, tmp2698, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2698, ret_val_illegal_normal_2697); + setArg(call_illegal_normal_2697, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2697, 1, vd); + setArg(call_illegal_normal_2697, 2, vm); + setRet(call_illegal_normal_2697, 0, ret_val_illegal_normal_2697); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2700; + x86::Gp ret_val_sew_2700 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2700, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2699; + auto vector_imm_op_2699_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2699_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2699_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2699_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2699_arg10 = ret_val_sew_2700; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2699, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2700, 0, reinterpret_cast(this)); + setRet(call_sew_2700, 0, ret_val_sew_2700); + setArg(call_vector_imm_op_2699, 0, V); + setArg(call_vector_imm_op_2699, 1, 45); + setArg(call_vector_imm_op_2699, 2, 6); + setArg(call_vector_imm_op_2699, 3, vector_imm_op_2699_arg3); + setArg(call_vector_imm_op_2699, 4, vector_imm_op_2699_arg4); + setArg(call_vector_imm_op_2699, 5, vector_imm_op_2699_arg5); + setArg(call_vector_imm_op_2699, 6, vm); + setArg(call_vector_imm_op_2699, 7, vd); + setArg(call_vector_imm_op_2699, 8, vs2); + setArg(call_vector_imm_op_2699, 9, vector_imm_op_2699_arg9); + setArg(call_vector_imm_op_2699, 10, vector_imm_op_2699_arg10); + } + cc.bind(label_merge); + } + auto tmp2701 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2701, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2701, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 632); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 633: VNMSAC__VV */ + continuation_e __vnmsac__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNMSAC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 633); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2702; + x86::Gp ret_val_illegal_normal_2702 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2702, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2702; + setArg(call_illegal_normal_2702, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2702, 1, vd); + setArg(call_illegal_normal_2702, 2, vm); + setRet(call_illegal_normal_2702, 0, ret_val_illegal_normal_2702); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2704; + x86::Gp ret_val_sew_2704 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2704, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2703; + auto vector_vector_op_2703_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2703_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2703_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2703_arg10 = ret_val_sew_2704; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2703, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2704, 0, reinterpret_cast(this)); + setRet(call_sew_2704, 0, ret_val_sew_2704); + setArg(call_vector_vector_op_2703, 0, V); + setArg(call_vector_vector_op_2703, 1, 47); + setArg(call_vector_vector_op_2703, 2, 2); + setArg(call_vector_vector_op_2703, 3, vector_vector_op_2703_arg3); + setArg(call_vector_vector_op_2703, 4, vector_vector_op_2703_arg4); + setArg(call_vector_vector_op_2703, 5, vector_vector_op_2703_arg5); + setArg(call_vector_vector_op_2703, 6, vm); + setArg(call_vector_vector_op_2703, 7, vd); + setArg(call_vector_vector_op_2703, 8, vs2); + setArg(call_vector_vector_op_2703, 9, vs1); + setArg(call_vector_vector_op_2703, 10, vector_vector_op_2703_arg10); + } + cc.bind(label_merge); + } + auto tmp2705 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2705, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2705, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 633); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 634: VNMSAC__VX */ + continuation_e __vnmsac__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnmsac.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNMSAC__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 634); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2706; + x86::Gp ret_val_illegal_normal_2706 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2706, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2707 = get_reg(cc, 8, false); + mov(cc, tmp2707, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2707, ret_val_illegal_normal_2706); + setArg(call_illegal_normal_2706, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2706, 1, vd); + setArg(call_illegal_normal_2706, 2, vm); + setRet(call_illegal_normal_2706, 0, ret_val_illegal_normal_2706); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2709; + x86::Gp ret_val_sew_2709 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2709, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2708; + auto vector_imm_op_2708_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2708_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2708_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2708_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2708_arg10 = ret_val_sew_2709; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2708, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2709, 0, reinterpret_cast(this)); + setRet(call_sew_2709, 0, ret_val_sew_2709); + setArg(call_vector_imm_op_2708, 0, V); + setArg(call_vector_imm_op_2708, 1, 47); + setArg(call_vector_imm_op_2708, 2, 6); + setArg(call_vector_imm_op_2708, 3, vector_imm_op_2708_arg3); + setArg(call_vector_imm_op_2708, 4, vector_imm_op_2708_arg4); + setArg(call_vector_imm_op_2708, 5, vector_imm_op_2708_arg5); + setArg(call_vector_imm_op_2708, 6, vm); + setArg(call_vector_imm_op_2708, 7, vd); + setArg(call_vector_imm_op_2708, 8, vs2); + setArg(call_vector_imm_op_2708, 9, vector_imm_op_2708_arg9); + setArg(call_vector_imm_op_2708, 10, vector_imm_op_2708_arg10); + } + cc.bind(label_merge); + } + auto tmp2710 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2710, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2710, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 634); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 635: VMADD__VV */ + continuation_e __vmadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 635); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2711; + x86::Gp ret_val_illegal_normal_2711 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2711, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2711; + setArg(call_illegal_normal_2711, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2711, 1, vd); + setArg(call_illegal_normal_2711, 2, vm); + setRet(call_illegal_normal_2711, 0, ret_val_illegal_normal_2711); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2713; + x86::Gp ret_val_sew_2713 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2713, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2712; + auto vector_vector_op_2712_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2712_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2712_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2712_arg10 = ret_val_sew_2713; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2712, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2713, 0, reinterpret_cast(this)); + setRet(call_sew_2713, 0, ret_val_sew_2713); + setArg(call_vector_vector_op_2712, 0, V); + setArg(call_vector_vector_op_2712, 1, 41); + setArg(call_vector_vector_op_2712, 2, 2); + setArg(call_vector_vector_op_2712, 3, vector_vector_op_2712_arg3); + setArg(call_vector_vector_op_2712, 4, vector_vector_op_2712_arg4); + setArg(call_vector_vector_op_2712, 5, vector_vector_op_2712_arg5); + setArg(call_vector_vector_op_2712, 6, vm); + setArg(call_vector_vector_op_2712, 7, vd); + setArg(call_vector_vector_op_2712, 8, vs2); + setArg(call_vector_vector_op_2712, 9, vs1); + setArg(call_vector_vector_op_2712, 10, vector_vector_op_2712_arg10); + } + cc.bind(label_merge); + } + auto tmp2714 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2714, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2714, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 635); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 636: VMADD__VX */ + continuation_e __vmadd__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMADD__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 636); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2715; + x86::Gp ret_val_illegal_normal_2715 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2715, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2716 = get_reg(cc, 8, false); + mov(cc, tmp2716, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2716, ret_val_illegal_normal_2715); + setArg(call_illegal_normal_2715, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2715, 1, vd); + setArg(call_illegal_normal_2715, 2, vm); + setRet(call_illegal_normal_2715, 0, ret_val_illegal_normal_2715); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2718; + x86::Gp ret_val_sew_2718 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2718, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2717; + auto vector_imm_op_2717_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2717_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2717_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2717_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2717_arg10 = ret_val_sew_2718; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2717, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2718, 0, reinterpret_cast(this)); + setRet(call_sew_2718, 0, ret_val_sew_2718); + setArg(call_vector_imm_op_2717, 0, V); + setArg(call_vector_imm_op_2717, 1, 41); + setArg(call_vector_imm_op_2717, 2, 6); + setArg(call_vector_imm_op_2717, 3, vector_imm_op_2717_arg3); + setArg(call_vector_imm_op_2717, 4, vector_imm_op_2717_arg4); + setArg(call_vector_imm_op_2717, 5, vector_imm_op_2717_arg5); + setArg(call_vector_imm_op_2717, 6, vm); + setArg(call_vector_imm_op_2717, 7, vd); + setArg(call_vector_imm_op_2717, 8, vs2); + setArg(call_vector_imm_op_2717, 9, vector_imm_op_2717_arg9); + setArg(call_vector_imm_op_2717, 10, vector_imm_op_2717_arg10); + } + cc.bind(label_merge); + } + auto tmp2719 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2719, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2719, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 636); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 637: VNMSUB__VV */ + continuation_e __vnmsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNMSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 637); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2720; + x86::Gp ret_val_illegal_normal_2720 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2720, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2720; + setArg(call_illegal_normal_2720, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2720, 1, vd); + setArg(call_illegal_normal_2720, 2, vm); + setRet(call_illegal_normal_2720, 0, ret_val_illegal_normal_2720); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2722; + x86::Gp ret_val_sew_2722 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2722, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_op_2721; + auto vector_vector_op_2721_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_op_2721_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_op_2721_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_op_2721_arg10 = ret_val_sew_2722; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_op_2721, &vector_vector_op, FuncSignature::build()); + setArg(call_sew_2722, 0, reinterpret_cast(this)); + setRet(call_sew_2722, 0, ret_val_sew_2722); + setArg(call_vector_vector_op_2721, 0, V); + setArg(call_vector_vector_op_2721, 1, 43); + setArg(call_vector_vector_op_2721, 2, 2); + setArg(call_vector_vector_op_2721, 3, vector_vector_op_2721_arg3); + setArg(call_vector_vector_op_2721, 4, vector_vector_op_2721_arg4); + setArg(call_vector_vector_op_2721, 5, vector_vector_op_2721_arg5); + setArg(call_vector_vector_op_2721, 6, vm); + setArg(call_vector_vector_op_2721, 7, vd); + setArg(call_vector_vector_op_2721, 8, vs2); + setArg(call_vector_vector_op_2721, 9, vs1); + setArg(call_vector_vector_op_2721, 10, vector_vector_op_2721_arg10); + } + cc.bind(label_merge); + } + auto tmp2723 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2723, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2723, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 637); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 638: VNMSUB__VX */ + continuation_e __vnmsub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnmsub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNMSUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 638); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2724; + x86::Gp ret_val_illegal_normal_2724 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2724, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2725 = get_reg(cc, 8, false); + mov(cc, tmp2725, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2725, ret_val_illegal_normal_2724); + setArg(call_illegal_normal_2724, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2724, 1, vd); + setArg(call_illegal_normal_2724, 2, vm); + setRet(call_illegal_normal_2724, 0, ret_val_illegal_normal_2724); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2727; + x86::Gp ret_val_sew_2727 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2727, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_op_2726; + auto vector_imm_op_2726_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_op_2726_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_op_2726_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_op_2726_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_op_2726_arg10 = ret_val_sew_2727; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_op_2726, &vector_imm_op, FuncSignature::build()); + setArg(call_sew_2727, 0, reinterpret_cast(this)); + setRet(call_sew_2727, 0, ret_val_sew_2727); + setArg(call_vector_imm_op_2726, 0, V); + setArg(call_vector_imm_op_2726, 1, 43); + setArg(call_vector_imm_op_2726, 2, 6); + setArg(call_vector_imm_op_2726, 3, vector_imm_op_2726_arg3); + setArg(call_vector_imm_op_2726, 4, vector_imm_op_2726_arg4); + setArg(call_vector_imm_op_2726, 5, vector_imm_op_2726_arg5); + setArg(call_vector_imm_op_2726, 6, vm); + setArg(call_vector_imm_op_2726, 7, vd); + setArg(call_vector_imm_op_2726, 8, vs2); + setArg(call_vector_imm_op_2726, 9, vector_imm_op_2726_arg9); + setArg(call_vector_imm_op_2726, 10, vector_imm_op_2726_arg10); + } + cc.bind(label_merge); + } + auto tmp2728 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2728, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2728, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 638); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 639: VWMACCU__VV */ + continuation_e __vwmaccu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmaccu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACCU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 639); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2729; + x86::Gp ret_val_get_sew_pow_2729 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2729, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2730 = get_reg(cc, 8, false); + mov(cc, tmp2730, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2730, ret_val_get_sew_pow_2729)), 8, false), ~ 1); + setArg(call_get_sew_pow_2729, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2729, 0, ret_val_get_sew_pow_2729); + InvokeNode* call_get_lmul_pow_2731; + x86::Gp ret_val_get_lmul_pow_2731 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2731, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2731; + setArg(call_get_lmul_pow_2731, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2731, 0, ret_val_get_lmul_pow_2731); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2732; + auto illegal_variable_width_2732_arg2 = SEW_widen; + auto illegal_variable_width_2732_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2732 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2732, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2733; + auto valid_reg_overlap_2733_arg2 = LMUL_pow; + auto valid_reg_overlap_2733_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2733 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2733, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2734; + auto valid_reg_overlap_2734_arg2 = LMUL_pow; + auto valid_reg_overlap_2734_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2734 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2734, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2732, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2733)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2734)); + setArg(call_illegal_variable_width_2732, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2732, 1, vd); + setArg(call_illegal_variable_width_2732, 2, vm); + setArg(call_illegal_variable_width_2732, 3, illegal_variable_width_2732_arg2); + setArg(call_illegal_variable_width_2732, 4, illegal_variable_width_2732_arg3); + setRet(call_illegal_variable_width_2732, 0, ret_val_illegal_variable_width_2732); + setArg(call_valid_reg_overlap_2733, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2733, 1, vs1); + setArg(call_valid_reg_overlap_2733, 2, vd); + setArg(call_valid_reg_overlap_2733, 3, valid_reg_overlap_2733_arg2); + setArg(call_valid_reg_overlap_2733, 4, valid_reg_overlap_2733_arg3); + setRet(call_valid_reg_overlap_2733, 0, ret_val_valid_reg_overlap_2733); + setArg(call_valid_reg_overlap_2734, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2734, 1, vs2); + setArg(call_valid_reg_overlap_2734, 2, vd); + setArg(call_valid_reg_overlap_2734, 3, valid_reg_overlap_2734_arg2); + setArg(call_valid_reg_overlap_2734, 4, valid_reg_overlap_2734_arg3); + setRet(call_valid_reg_overlap_2734, 0, ret_val_valid_reg_overlap_2734); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2736; + x86::Gp ret_val_sew_2736 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2736, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2735; + auto vector_vector_wv_2735_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2735_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2735_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2735_arg10 = ret_val_sew_2736; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2735, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2736, 0, reinterpret_cast(this)); + setRet(call_sew_2736, 0, ret_val_sew_2736); + setArg(call_vector_vector_wv_2735, 0, V); + setArg(call_vector_vector_wv_2735, 1, 60); + setArg(call_vector_vector_wv_2735, 2, 2); + setArg(call_vector_vector_wv_2735, 3, vector_vector_wv_2735_arg3); + setArg(call_vector_vector_wv_2735, 4, vector_vector_wv_2735_arg4); + setArg(call_vector_vector_wv_2735, 5, vector_vector_wv_2735_arg5); + setArg(call_vector_vector_wv_2735, 6, vm); + setArg(call_vector_vector_wv_2735, 7, vd); + setArg(call_vector_vector_wv_2735, 8, vs2); + setArg(call_vector_vector_wv_2735, 9, vs1); + setArg(call_vector_vector_wv_2735, 10, vector_vector_wv_2735_arg10); + } + cc.bind(label_merge); + } + auto tmp2737 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2737, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2737, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 639); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 640: VWMACCU__VX */ + continuation_e __vwmaccu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACCU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 640); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2738; + x86::Gp ret_val_get_sew_pow_2738 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2738, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2739 = get_reg(cc, 8, false); + mov(cc, tmp2739, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2739, ret_val_get_sew_pow_2738)), 8, false), ~ 1); + setArg(call_get_sew_pow_2738, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2738, 0, ret_val_get_sew_pow_2738); + InvokeNode* call_get_lmul_pow_2740; + x86::Gp ret_val_get_lmul_pow_2740 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2740, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2740; + setArg(call_get_lmul_pow_2740, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2740, 0, ret_val_get_lmul_pow_2740); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2741; + auto illegal_variable_width_2741_arg2 = SEW_widen; + auto illegal_variable_width_2741_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2741 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2741, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2742; + auto valid_reg_overlap_2742_arg2 = LMUL_pow; + auto valid_reg_overlap_2742_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2742 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2742, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2741, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2742)); + setArg(call_illegal_variable_width_2741, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2741, 1, vd); + setArg(call_illegal_variable_width_2741, 2, vm); + setArg(call_illegal_variable_width_2741, 3, illegal_variable_width_2741_arg2); + setArg(call_illegal_variable_width_2741, 4, illegal_variable_width_2741_arg3); + setRet(call_illegal_variable_width_2741, 0, ret_val_illegal_variable_width_2741); + setArg(call_valid_reg_overlap_2742, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2742, 1, vs2); + setArg(call_valid_reg_overlap_2742, 2, vd); + setArg(call_valid_reg_overlap_2742, 3, valid_reg_overlap_2742_arg2); + setArg(call_valid_reg_overlap_2742, 4, valid_reg_overlap_2742_arg3); + setRet(call_valid_reg_overlap_2742, 0, ret_val_valid_reg_overlap_2742); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2744; + x86::Gp ret_val_sew_2744 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2744, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2743; + auto vector_imm_wv_2743_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2743_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2743_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2743_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2743_arg10 = ret_val_sew_2744; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2743, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2744, 0, reinterpret_cast(this)); + setRet(call_sew_2744, 0, ret_val_sew_2744); + setArg(call_vector_imm_wv_2743, 0, V); + setArg(call_vector_imm_wv_2743, 1, 60); + setArg(call_vector_imm_wv_2743, 2, 6); + setArg(call_vector_imm_wv_2743, 3, vector_imm_wv_2743_arg3); + setArg(call_vector_imm_wv_2743, 4, vector_imm_wv_2743_arg4); + setArg(call_vector_imm_wv_2743, 5, vector_imm_wv_2743_arg5); + setArg(call_vector_imm_wv_2743, 6, vm); + setArg(call_vector_imm_wv_2743, 7, vd); + setArg(call_vector_imm_wv_2743, 8, vs2); + setArg(call_vector_imm_wv_2743, 9, vector_imm_wv_2743_arg9); + setArg(call_vector_imm_wv_2743, 10, vector_imm_wv_2743_arg10); + } + cc.bind(label_merge); + } + auto tmp2745 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2745, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2745, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 640); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 641: VWMACC__VV */ + continuation_e __vwmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 641); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2746; + x86::Gp ret_val_get_sew_pow_2746 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2746, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2747 = get_reg(cc, 8, false); + mov(cc, tmp2747, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2747, ret_val_get_sew_pow_2746)), 8, false), ~ 1); + setArg(call_get_sew_pow_2746, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2746, 0, ret_val_get_sew_pow_2746); + InvokeNode* call_get_lmul_pow_2748; + x86::Gp ret_val_get_lmul_pow_2748 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2748, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2748; + setArg(call_get_lmul_pow_2748, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2748, 0, ret_val_get_lmul_pow_2748); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2749; + auto illegal_variable_width_2749_arg2 = SEW_widen; + auto illegal_variable_width_2749_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2749 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2749, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2750; + auto valid_reg_overlap_2750_arg2 = LMUL_pow; + auto valid_reg_overlap_2750_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2750 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2750, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2751; + auto valid_reg_overlap_2751_arg2 = LMUL_pow; + auto valid_reg_overlap_2751_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2751 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2751, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2749, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2750)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2751)); + setArg(call_illegal_variable_width_2749, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2749, 1, vd); + setArg(call_illegal_variable_width_2749, 2, vm); + setArg(call_illegal_variable_width_2749, 3, illegal_variable_width_2749_arg2); + setArg(call_illegal_variable_width_2749, 4, illegal_variable_width_2749_arg3); + setRet(call_illegal_variable_width_2749, 0, ret_val_illegal_variable_width_2749); + setArg(call_valid_reg_overlap_2750, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2750, 1, vs1); + setArg(call_valid_reg_overlap_2750, 2, vd); + setArg(call_valid_reg_overlap_2750, 3, valid_reg_overlap_2750_arg2); + setArg(call_valid_reg_overlap_2750, 4, valid_reg_overlap_2750_arg3); + setRet(call_valid_reg_overlap_2750, 0, ret_val_valid_reg_overlap_2750); + setArg(call_valid_reg_overlap_2751, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2751, 1, vs2); + setArg(call_valid_reg_overlap_2751, 2, vd); + setArg(call_valid_reg_overlap_2751, 3, valid_reg_overlap_2751_arg2); + setArg(call_valid_reg_overlap_2751, 4, valid_reg_overlap_2751_arg3); + setRet(call_valid_reg_overlap_2751, 0, ret_val_valid_reg_overlap_2751); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2753; + x86::Gp ret_val_sew_2753 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2753, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2752; + auto vector_vector_wv_2752_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2752_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2752_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2752_arg10 = ret_val_sew_2753; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2752, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2753, 0, reinterpret_cast(this)); + setRet(call_sew_2753, 0, ret_val_sew_2753); + setArg(call_vector_vector_wv_2752, 0, V); + setArg(call_vector_vector_wv_2752, 1, 61); + setArg(call_vector_vector_wv_2752, 2, 2); + setArg(call_vector_vector_wv_2752, 3, vector_vector_wv_2752_arg3); + setArg(call_vector_vector_wv_2752, 4, vector_vector_wv_2752_arg4); + setArg(call_vector_vector_wv_2752, 5, vector_vector_wv_2752_arg5); + setArg(call_vector_vector_wv_2752, 6, vm); + setArg(call_vector_vector_wv_2752, 7, vd); + setArg(call_vector_vector_wv_2752, 8, vs2); + setArg(call_vector_vector_wv_2752, 9, vs1); + setArg(call_vector_vector_wv_2752, 10, vector_vector_wv_2752_arg10); + } + cc.bind(label_merge); + } + auto tmp2754 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2754, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2754, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 641); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 642: VWMACC__VX */ + continuation_e __vwmacc__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmacc.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACC__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 642); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2755; + x86::Gp ret_val_get_sew_pow_2755 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2755, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2756 = get_reg(cc, 8, false); + mov(cc, tmp2756, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2756, ret_val_get_sew_pow_2755)), 8, false), ~ 1); + setArg(call_get_sew_pow_2755, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2755, 0, ret_val_get_sew_pow_2755); + InvokeNode* call_get_lmul_pow_2757; + x86::Gp ret_val_get_lmul_pow_2757 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2757, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2757; + setArg(call_get_lmul_pow_2757, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2757, 0, ret_val_get_lmul_pow_2757); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2758; + auto illegal_variable_width_2758_arg2 = SEW_widen; + auto illegal_variable_width_2758_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2758 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2758, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2759; + auto valid_reg_overlap_2759_arg2 = LMUL_pow; + auto valid_reg_overlap_2759_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2759 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2759, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2758, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2759)); + setArg(call_illegal_variable_width_2758, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2758, 1, vd); + setArg(call_illegal_variable_width_2758, 2, vm); + setArg(call_illegal_variable_width_2758, 3, illegal_variable_width_2758_arg2); + setArg(call_illegal_variable_width_2758, 4, illegal_variable_width_2758_arg3); + setRet(call_illegal_variable_width_2758, 0, ret_val_illegal_variable_width_2758); + setArg(call_valid_reg_overlap_2759, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2759, 1, vs2); + setArg(call_valid_reg_overlap_2759, 2, vd); + setArg(call_valid_reg_overlap_2759, 3, valid_reg_overlap_2759_arg2); + setArg(call_valid_reg_overlap_2759, 4, valid_reg_overlap_2759_arg3); + setRet(call_valid_reg_overlap_2759, 0, ret_val_valid_reg_overlap_2759); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2761; + x86::Gp ret_val_sew_2761 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2761, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2760; + auto vector_imm_wv_2760_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2760_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2760_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2760_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2760_arg10 = ret_val_sew_2761; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2760, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2761, 0, reinterpret_cast(this)); + setRet(call_sew_2761, 0, ret_val_sew_2761); + setArg(call_vector_imm_wv_2760, 0, V); + setArg(call_vector_imm_wv_2760, 1, 61); + setArg(call_vector_imm_wv_2760, 2, 6); + setArg(call_vector_imm_wv_2760, 3, vector_imm_wv_2760_arg3); + setArg(call_vector_imm_wv_2760, 4, vector_imm_wv_2760_arg4); + setArg(call_vector_imm_wv_2760, 5, vector_imm_wv_2760_arg5); + setArg(call_vector_imm_wv_2760, 6, vm); + setArg(call_vector_imm_wv_2760, 7, vd); + setArg(call_vector_imm_wv_2760, 8, vs2); + setArg(call_vector_imm_wv_2760, 9, vector_imm_wv_2760_arg9); + setArg(call_vector_imm_wv_2760, 10, vector_imm_wv_2760_arg10); + } + cc.bind(label_merge); + } + auto tmp2762 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2762, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2762, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 642); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 643: VWMACCSU__VV */ + continuation_e __vwmaccsu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwmaccsu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACCSU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 643); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2763; + x86::Gp ret_val_get_sew_pow_2763 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2763, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2764 = get_reg(cc, 8, false); + mov(cc, tmp2764, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2764, ret_val_get_sew_pow_2763)), 8, false), ~ 1); + setArg(call_get_sew_pow_2763, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2763, 0, ret_val_get_sew_pow_2763); + InvokeNode* call_get_lmul_pow_2765; + x86::Gp ret_val_get_lmul_pow_2765 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2765, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2765; + setArg(call_get_lmul_pow_2765, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2765, 0, ret_val_get_lmul_pow_2765); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2766; + auto illegal_variable_width_2766_arg2 = SEW_widen; + auto illegal_variable_width_2766_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2766 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2766, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2767; + auto valid_reg_overlap_2767_arg2 = LMUL_pow; + auto valid_reg_overlap_2767_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2767 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2767, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2768; + auto valid_reg_overlap_2768_arg2 = LMUL_pow; + auto valid_reg_overlap_2768_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2768 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2768, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_variable_width_2766, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2767)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_2768)); + setArg(call_illegal_variable_width_2766, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2766, 1, vd); + setArg(call_illegal_variable_width_2766, 2, vm); + setArg(call_illegal_variable_width_2766, 3, illegal_variable_width_2766_arg2); + setArg(call_illegal_variable_width_2766, 4, illegal_variable_width_2766_arg3); + setRet(call_illegal_variable_width_2766, 0, ret_val_illegal_variable_width_2766); + setArg(call_valid_reg_overlap_2767, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2767, 1, vs1); + setArg(call_valid_reg_overlap_2767, 2, vd); + setArg(call_valid_reg_overlap_2767, 3, valid_reg_overlap_2767_arg2); + setArg(call_valid_reg_overlap_2767, 4, valid_reg_overlap_2767_arg3); + setRet(call_valid_reg_overlap_2767, 0, ret_val_valid_reg_overlap_2767); + setArg(call_valid_reg_overlap_2768, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2768, 1, vs2); + setArg(call_valid_reg_overlap_2768, 2, vd); + setArg(call_valid_reg_overlap_2768, 3, valid_reg_overlap_2768_arg2); + setArg(call_valid_reg_overlap_2768, 4, valid_reg_overlap_2768_arg3); + setRet(call_valid_reg_overlap_2768, 0, ret_val_valid_reg_overlap_2768); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2770; + x86::Gp ret_val_sew_2770 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2770, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_wv_2769; + auto vector_vector_wv_2769_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_wv_2769_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_wv_2769_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_wv_2769_arg10 = ret_val_sew_2770; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_wv_2769, &vector_vector_wv, FuncSignature::build()); + setArg(call_sew_2770, 0, reinterpret_cast(this)); + setRet(call_sew_2770, 0, ret_val_sew_2770); + setArg(call_vector_vector_wv_2769, 0, V); + setArg(call_vector_vector_wv_2769, 1, 63); + setArg(call_vector_vector_wv_2769, 2, 2); + setArg(call_vector_vector_wv_2769, 3, vector_vector_wv_2769_arg3); + setArg(call_vector_vector_wv_2769, 4, vector_vector_wv_2769_arg4); + setArg(call_vector_vector_wv_2769, 5, vector_vector_wv_2769_arg5); + setArg(call_vector_vector_wv_2769, 6, vm); + setArg(call_vector_vector_wv_2769, 7, vd); + setArg(call_vector_vector_wv_2769, 8, vs2); + setArg(call_vector_vector_wv_2769, 9, vs1); + setArg(call_vector_vector_wv_2769, 10, vector_vector_wv_2769_arg10); + } + cc.bind(label_merge); + } + auto tmp2771 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2771, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2771, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 643); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 644: VWMACCSU__VX */ + continuation_e __vwmaccsu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccsu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACCSU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 644); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2772; + x86::Gp ret_val_get_sew_pow_2772 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2772, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2773 = get_reg(cc, 8, false); + mov(cc, tmp2773, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2773, ret_val_get_sew_pow_2772)), 8, false), ~ 1); + setArg(call_get_sew_pow_2772, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2772, 0, ret_val_get_sew_pow_2772); + InvokeNode* call_get_lmul_pow_2774; + x86::Gp ret_val_get_lmul_pow_2774 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2774, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2774; + setArg(call_get_lmul_pow_2774, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2774, 0, ret_val_get_lmul_pow_2774); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2775; + auto illegal_variable_width_2775_arg2 = SEW_widen; + auto illegal_variable_width_2775_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2775 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2775, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2776; + auto valid_reg_overlap_2776_arg2 = LMUL_pow; + auto valid_reg_overlap_2776_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2776 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2776, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2775, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2776)); + setArg(call_illegal_variable_width_2775, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2775, 1, vd); + setArg(call_illegal_variable_width_2775, 2, vm); + setArg(call_illegal_variable_width_2775, 3, illegal_variable_width_2775_arg2); + setArg(call_illegal_variable_width_2775, 4, illegal_variable_width_2775_arg3); + setRet(call_illegal_variable_width_2775, 0, ret_val_illegal_variable_width_2775); + setArg(call_valid_reg_overlap_2776, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2776, 1, vs2); + setArg(call_valid_reg_overlap_2776, 2, vd); + setArg(call_valid_reg_overlap_2776, 3, valid_reg_overlap_2776_arg2); + setArg(call_valid_reg_overlap_2776, 4, valid_reg_overlap_2776_arg3); + setRet(call_valid_reg_overlap_2776, 0, ret_val_valid_reg_overlap_2776); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2778; + x86::Gp ret_val_sew_2778 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2778, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2777; + auto vector_imm_wv_2777_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2777_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2777_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2777_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2777_arg10 = ret_val_sew_2778; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2777, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2778, 0, reinterpret_cast(this)); + setRet(call_sew_2778, 0, ret_val_sew_2778); + setArg(call_vector_imm_wv_2777, 0, V); + setArg(call_vector_imm_wv_2777, 1, 63); + setArg(call_vector_imm_wv_2777, 2, 6); + setArg(call_vector_imm_wv_2777, 3, vector_imm_wv_2777_arg3); + setArg(call_vector_imm_wv_2777, 4, vector_imm_wv_2777_arg4); + setArg(call_vector_imm_wv_2777, 5, vector_imm_wv_2777_arg5); + setArg(call_vector_imm_wv_2777, 6, vm); + setArg(call_vector_imm_wv_2777, 7, vd); + setArg(call_vector_imm_wv_2777, 8, vs2); + setArg(call_vector_imm_wv_2777, 9, vector_imm_wv_2777_arg9); + setArg(call_vector_imm_wv_2777, 10, vector_imm_wv_2777_arg10); + } + cc.bind(label_merge); + } + auto tmp2779 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2779, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2779, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 644); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 645: VWMACCUS__VX */ + continuation_e __vwmaccus__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vwmaccus.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWMACCUS__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 645); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2780; + x86::Gp ret_val_get_sew_pow_2780 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2780, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2781 = get_reg(cc, 8, false); + mov(cc, tmp2781, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2781, ret_val_get_sew_pow_2780)), 5, false), ~ 1); + setArg(call_get_sew_pow_2780, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2780, 0, ret_val_get_sew_pow_2780); + InvokeNode* call_get_lmul_pow_2782; + x86::Gp ret_val_get_lmul_pow_2782 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2782, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2782; + setArg(call_get_lmul_pow_2782, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2782, 0, ret_val_get_lmul_pow_2782); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2783; + auto illegal_variable_width_2783_arg2 = SEW_widen; + auto illegal_variable_width_2783_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2783 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2783, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2784; + auto valid_reg_overlap_2784_arg2 = LMUL_pow; + auto valid_reg_overlap_2784_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_2784 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2784, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2783, gen_operation(cc, lnot, ret_val_valid_reg_overlap_2784)); + setArg(call_illegal_variable_width_2783, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2783, 1, vd); + setArg(call_illegal_variable_width_2783, 2, vm); + setArg(call_illegal_variable_width_2783, 3, illegal_variable_width_2783_arg2); + setArg(call_illegal_variable_width_2783, 4, illegal_variable_width_2783_arg3); + setRet(call_illegal_variable_width_2783, 0, ret_val_illegal_variable_width_2783); + setArg(call_valid_reg_overlap_2784, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2784, 1, vs2); + setArg(call_valid_reg_overlap_2784, 2, vd); + setArg(call_valid_reg_overlap_2784, 3, valid_reg_overlap_2784_arg2); + setArg(call_valid_reg_overlap_2784, 4, valid_reg_overlap_2784_arg3); + setRet(call_valid_reg_overlap_2784, 0, ret_val_valid_reg_overlap_2784); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2786; + x86::Gp ret_val_sew_2786 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2786, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_wv_2785; + auto vector_imm_wv_2785_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_wv_2785_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_wv_2785_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_wv_2785_arg9 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto vector_imm_wv_2785_arg10 = ret_val_sew_2786; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_wv_2785, &vector_imm_wv, FuncSignature::build()); + setArg(call_sew_2786, 0, reinterpret_cast(this)); + setRet(call_sew_2786, 0, ret_val_sew_2786); + setArg(call_vector_imm_wv_2785, 0, V); + setArg(call_vector_imm_wv_2785, 1, 62); + setArg(call_vector_imm_wv_2785, 2, 6); + setArg(call_vector_imm_wv_2785, 3, vector_imm_wv_2785_arg3); + setArg(call_vector_imm_wv_2785, 4, vector_imm_wv_2785_arg4); + setArg(call_vector_imm_wv_2785, 5, vector_imm_wv_2785_arg5); + setArg(call_vector_imm_wv_2785, 6, vm); + setArg(call_vector_imm_wv_2785, 7, vd); + setArg(call_vector_imm_wv_2785, 8, vs2); + setArg(call_vector_imm_wv_2785, 9, vector_imm_wv_2785_arg9); + setArg(call_vector_imm_wv_2785, 10, vector_imm_wv_2785_arg10); + } + cc.bind(label_merge); + } + auto tmp2787 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2787, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2787, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 645); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 646: VMERGE__VIM */ + continuation_e __vmerge__vim(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}", fmt::arg("mnemonic", "vmerge.vim"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMERGE__VIM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 646); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2788; + x86::Gp ret_val_illegal_vd_masked_2788 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2788, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_masked_2788; + setArg(call_illegal_vd_masked_2788, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2788, 1, vd); + setRet(call_illegal_vd_masked_2788, 0, ret_val_illegal_vd_masked_2788); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2790; + x86::Gp ret_val_sew_2790 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2790, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_2789; + auto vector_imm_merge_2789_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_2789_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_2789_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_2789_arg8 = ret_val_sew_2790; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_2789, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_2790, 0, reinterpret_cast(this)); + setRet(call_sew_2790, 0, ret_val_sew_2790); + setArg(call_vector_imm_merge_2789, 0, V); + setArg(call_vector_imm_merge_2789, 1, vector_imm_merge_2789_arg1); + setArg(call_vector_imm_merge_2789, 2, vector_imm_merge_2789_arg2); + setArg(call_vector_imm_merge_2789, 3, vector_imm_merge_2789_arg3); + setArg(call_vector_imm_merge_2789, 4, 0); + setArg(call_vector_imm_merge_2789, 5, vd); + setArg(call_vector_imm_merge_2789, 6, vs2); + setArg(call_vector_imm_merge_2789, 7, (uint64_t)(int64_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_merge_2789, 8, vector_imm_merge_2789_arg8); + } + cc.bind(label_merge); + } + auto tmp2791 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2791, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2791, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 646); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 647: VMERGE__VVM */ + continuation_e __vmerge__vvm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmerge.vvm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMERGE__VVM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 647); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2792; + x86::Gp ret_val_illegal_vd_masked_2792 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2792, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_masked_2792; + setArg(call_illegal_vd_masked_2792, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2792, 1, vd); + setRet(call_illegal_vd_masked_2792, 0, ret_val_illegal_vd_masked_2792); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2794; + x86::Gp ret_val_sew_2794 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2794, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_merge_2793; + auto vector_vector_merge_2793_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_merge_2793_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_merge_2793_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_merge_2793_arg8 = ret_val_sew_2794; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_merge_2793, &vector_vector_merge, FuncSignature::build()); + setArg(call_sew_2794, 0, reinterpret_cast(this)); + setRet(call_sew_2794, 0, ret_val_sew_2794); + setArg(call_vector_vector_merge_2793, 0, V); + setArg(call_vector_vector_merge_2793, 1, vector_vector_merge_2793_arg1); + setArg(call_vector_vector_merge_2793, 2, vector_vector_merge_2793_arg2); + setArg(call_vector_vector_merge_2793, 3, vector_vector_merge_2793_arg3); + setArg(call_vector_vector_merge_2793, 4, 0); + setArg(call_vector_vector_merge_2793, 5, vd); + setArg(call_vector_vector_merge_2793, 6, vs2); + setArg(call_vector_vector_merge_2793, 7, vs1); + setArg(call_vector_vector_merge_2793, 8, vector_vector_merge_2793_arg8); + } + cc.bind(label_merge); + } + auto tmp2795 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2795, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2795, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 647); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 648: VMERGE__VXM */ + continuation_e __vmerge__vxm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vmerge.vxm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMERGE__VXM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 648); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_masked_2796; + x86::Gp ret_val_illegal_vd_masked_2796 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_masked_2796, (uintptr_t)&vm_impl::_illegal_vd_masked, FuncSignature::build()); + auto tmp2797 = get_reg(cc, 8, false); + mov(cc, tmp2797, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2797, ret_val_illegal_vd_masked_2796); + setArg(call_illegal_vd_masked_2796, 0, reinterpret_cast(this)); + setArg(call_illegal_vd_masked_2796, 1, vd); + setRet(call_illegal_vd_masked_2796, 0, ret_val_illegal_vd_masked_2796); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2799; + x86::Gp ret_val_sew_2799 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2799, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_2798; + auto vector_imm_merge_2798_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_2798_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_2798_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_2798_arg7 = gen_ext(cc, + gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true), 64, true); + auto vector_imm_merge_2798_arg8 = ret_val_sew_2799; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_2798, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_2799, 0, reinterpret_cast(this)); + setRet(call_sew_2799, 0, ret_val_sew_2799); + setArg(call_vector_imm_merge_2798, 0, V); + setArg(call_vector_imm_merge_2798, 1, vector_imm_merge_2798_arg1); + setArg(call_vector_imm_merge_2798, 2, vector_imm_merge_2798_arg2); + setArg(call_vector_imm_merge_2798, 3, vector_imm_merge_2798_arg3); + setArg(call_vector_imm_merge_2798, 4, 0); + setArg(call_vector_imm_merge_2798, 5, vd); + setArg(call_vector_imm_merge_2798, 6, vs2); + setArg(call_vector_imm_merge_2798, 7, vector_imm_merge_2798_arg7); + setArg(call_vector_imm_merge_2798, 8, vector_imm_merge_2798_arg8); + } + cc.bind(label_merge); + } + auto tmp2800 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2800, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2800, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 648); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 649: VMV__V__I */ + continuation_e __vmv__v__i(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {simm}", fmt::arg("mnemonic", "vmv.v.i"), + fmt::arg("vd", vname(vd)), fmt::arg("simm", simm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV__V__I_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 649); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2801; + x86::Gp ret_val_illegal_vd_unmasked_2801 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2801, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2801; + setArg(call_illegal_vd_unmasked_2801, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2801, 0, ret_val_illegal_vd_unmasked_2801); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2803; + x86::Gp ret_val_sew_2803 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2803, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_2802; + auto vector_imm_merge_2802_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_2802_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_2802_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_2802_arg8 = ret_val_sew_2803; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_2802, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_2803, 0, reinterpret_cast(this)); + setRet(call_sew_2803, 0, ret_val_sew_2803); + setArg(call_vector_imm_merge_2802, 0, V); + setArg(call_vector_imm_merge_2802, 1, vector_imm_merge_2802_arg1); + setArg(call_vector_imm_merge_2802, 2, vector_imm_merge_2802_arg2); + setArg(call_vector_imm_merge_2802, 3, vector_imm_merge_2802_arg3); + setArg(call_vector_imm_merge_2802, 4, 1); + setArg(call_vector_imm_merge_2802, 5, vd); + setArg(call_vector_imm_merge_2802, 6, 0); + setArg(call_vector_imm_merge_2802, 7, (uint64_t)(int64_t)(int8_t)sext<5>(simm)); + setArg(call_vector_imm_merge_2802, 8, vector_imm_merge_2802_arg8); + } + cc.bind(label_merge); + } + auto tmp2804 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2804, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2804, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 649); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 650: VMV__V__V */ + continuation_e __vmv__v__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs1}", fmt::arg("mnemonic", "vmv.v.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV__V__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 650); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2805; + x86::Gp ret_val_illegal_vd_unmasked_2805 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2805, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_2805; + setArg(call_illegal_vd_unmasked_2805, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2805, 0, ret_val_illegal_vd_unmasked_2805); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2807; + x86::Gp ret_val_sew_2807 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2807, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_merge_2806; + auto vector_vector_merge_2806_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_merge_2806_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_merge_2806_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_merge_2806_arg8 = ret_val_sew_2807; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_merge_2806, &vector_vector_merge, FuncSignature::build()); + setArg(call_sew_2807, 0, reinterpret_cast(this)); + setRet(call_sew_2807, 0, ret_val_sew_2807); + setArg(call_vector_vector_merge_2806, 0, V); + setArg(call_vector_vector_merge_2806, 1, vector_vector_merge_2806_arg1); + setArg(call_vector_vector_merge_2806, 2, vector_vector_merge_2806_arg2); + setArg(call_vector_vector_merge_2806, 3, vector_vector_merge_2806_arg3); + setArg(call_vector_vector_merge_2806, 4, 1); + setArg(call_vector_vector_merge_2806, 5, vd); + setArg(call_vector_vector_merge_2806, 6, 0); + setArg(call_vector_vector_merge_2806, 7, vs1); + setArg(call_vector_vector_merge_2806, 8, vector_vector_merge_2806_arg8); + } + cc.bind(label_merge); + } + auto tmp2808 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2808, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2808, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 650); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 651: VMV__V__X */ + continuation_e __vmv__v__x(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vmv.v.x"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV__V__X_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 651); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_2809; + x86::Gp ret_val_illegal_vd_unmasked_2809 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_2809, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp2810 = get_reg(cc, 8, false); + mov(cc, tmp2810, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2810, ret_val_illegal_vd_unmasked_2809); + setArg(call_illegal_vd_unmasked_2809, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_2809, 0, ret_val_illegal_vd_unmasked_2809); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2812; + x86::Gp ret_val_sew_2812 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2812, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_2811; + auto vector_imm_merge_2811_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_2811_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_2811_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_2811_arg7 = gen_ext(cc, + gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true), 64, true); + auto vector_imm_merge_2811_arg8 = ret_val_sew_2812; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_2811, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_2812, 0, reinterpret_cast(this)); + setRet(call_sew_2812, 0, ret_val_sew_2812); + setArg(call_vector_imm_merge_2811, 0, V); + setArg(call_vector_imm_merge_2811, 1, vector_imm_merge_2811_arg1); + setArg(call_vector_imm_merge_2811, 2, vector_imm_merge_2811_arg2); + setArg(call_vector_imm_merge_2811, 3, vector_imm_merge_2811_arg3); + setArg(call_vector_imm_merge_2811, 4, 1); + setArg(call_vector_imm_merge_2811, 5, vd); + setArg(call_vector_imm_merge_2811, 6, 0); + setArg(call_vector_imm_merge_2811, 7, vector_imm_merge_2811_arg7); + setArg(call_vector_imm_merge_2811, 8, vector_imm_merge_2811_arg8); + } + cc.bind(label_merge); + } + auto tmp2813 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2813, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2813, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 651); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 652: VSADDU__VI */ + continuation_e __vsaddu__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vsaddu.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADDU__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 652); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2814; + x86::Gp ret_val_illegal_normal_2814 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2814, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2814; + setArg(call_illegal_normal_2814, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2814, 1, vd); + setArg(call_illegal_normal_2814, 2, vm); + setRet(call_illegal_normal_2814, 0, ret_val_illegal_normal_2814); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2816; + x86::Gp ret_val_sew_2816 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2816, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2815; + auto sat_vector_imm_op_2815_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2815_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2815_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2815_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2815_arg11 = ret_val_sew_2816; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2815 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2815, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2815, 64, false) + , traits::vxsat); + setArg(call_sew_2816, 0, reinterpret_cast(this)); + setRet(call_sew_2816, 0, ret_val_sew_2816); + setArg(call_sat_vector_imm_op_2815, 0, V); + setArg(call_sat_vector_imm_op_2815, 1, 32); + setArg(call_sat_vector_imm_op_2815, 2, 3); + setArg(call_sat_vector_imm_op_2815, 3, sat_vector_imm_op_2815_arg3); + setArg(call_sat_vector_imm_op_2815, 4, sat_vector_imm_op_2815_arg4); + setArg(call_sat_vector_imm_op_2815, 5, sat_vector_imm_op_2815_arg5); + setArg(call_sat_vector_imm_op_2815, 6, sat_vector_imm_op_2815_arg6); + setArg(call_sat_vector_imm_op_2815, 7, vm); + setArg(call_sat_vector_imm_op_2815, 8, vd); + setArg(call_sat_vector_imm_op_2815, 9, vs2); + setArg(call_sat_vector_imm_op_2815, 10, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_sat_vector_imm_op_2815, 11, sat_vector_imm_op_2815_arg11); + setRet(call_sat_vector_imm_op_2815, 0, ret_val_sat_vector_imm_op_2815); + } + cc.bind(label_merge); + } + auto tmp2817 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2817, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2817, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 652); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 653: VSADDU__VV */ + continuation_e __vsaddu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADDU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 653); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2818; + x86::Gp ret_val_illegal_normal_2818 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2818, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2818; + setArg(call_illegal_normal_2818, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2818, 1, vd); + setArg(call_illegal_normal_2818, 2, vm); + setRet(call_illegal_normal_2818, 0, ret_val_illegal_normal_2818); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2820; + x86::Gp ret_val_sew_2820 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2820, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2819; + auto sat_vector_vector_op_2819_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2819_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2819_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2819_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2819_arg11 = ret_val_sew_2820; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2819 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2819, &sat_vector_vector_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_op_2819, 64, false) + , traits::vxsat); + setArg(call_sew_2820, 0, reinterpret_cast(this)); + setRet(call_sew_2820, 0, ret_val_sew_2820); + setArg(call_sat_vector_vector_op_2819, 0, V); + setArg(call_sat_vector_vector_op_2819, 1, 32); + setArg(call_sat_vector_vector_op_2819, 2, 0); + setArg(call_sat_vector_vector_op_2819, 3, sat_vector_vector_op_2819_arg3); + setArg(call_sat_vector_vector_op_2819, 4, sat_vector_vector_op_2819_arg4); + setArg(call_sat_vector_vector_op_2819, 5, sat_vector_vector_op_2819_arg5); + setArg(call_sat_vector_vector_op_2819, 6, sat_vector_vector_op_2819_arg6); + setArg(call_sat_vector_vector_op_2819, 7, vm); + setArg(call_sat_vector_vector_op_2819, 8, vd); + setArg(call_sat_vector_vector_op_2819, 9, vs2); + setArg(call_sat_vector_vector_op_2819, 10, vs1); + setArg(call_sat_vector_vector_op_2819, 11, sat_vector_vector_op_2819_arg11); + setRet(call_sat_vector_vector_op_2819, 0, ret_val_sat_vector_vector_op_2819); + } + cc.bind(label_merge); + } + auto tmp2821 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2821, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2821, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 653); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 654: VSADDU__VX */ + continuation_e __vsaddu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADDU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 654); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2822; + x86::Gp ret_val_illegal_normal_2822 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2822, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2823 = get_reg(cc, 8, false); + mov(cc, tmp2823, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2823, ret_val_illegal_normal_2822); + setArg(call_illegal_normal_2822, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2822, 1, vd); + setArg(call_illegal_normal_2822, 2, vm); + setRet(call_illegal_normal_2822, 0, ret_val_illegal_normal_2822); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2825; + x86::Gp ret_val_sew_2825 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2825, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2824; + auto sat_vector_imm_op_2824_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2824_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2824_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2824_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2824_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto sat_vector_imm_op_2824_arg11 = ret_val_sew_2825; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2824 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2824, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2824, 64, false) + , traits::vxsat); + setArg(call_sew_2825, 0, reinterpret_cast(this)); + setRet(call_sew_2825, 0, ret_val_sew_2825); + setArg(call_sat_vector_imm_op_2824, 0, V); + setArg(call_sat_vector_imm_op_2824, 1, 32); + setArg(call_sat_vector_imm_op_2824, 2, 4); + setArg(call_sat_vector_imm_op_2824, 3, sat_vector_imm_op_2824_arg3); + setArg(call_sat_vector_imm_op_2824, 4, sat_vector_imm_op_2824_arg4); + setArg(call_sat_vector_imm_op_2824, 5, sat_vector_imm_op_2824_arg5); + setArg(call_sat_vector_imm_op_2824, 6, sat_vector_imm_op_2824_arg6); + setArg(call_sat_vector_imm_op_2824, 7, vm); + setArg(call_sat_vector_imm_op_2824, 8, vd); + setArg(call_sat_vector_imm_op_2824, 9, vs2); + setArg(call_sat_vector_imm_op_2824, 10, sat_vector_imm_op_2824_arg10); + setArg(call_sat_vector_imm_op_2824, 11, sat_vector_imm_op_2824_arg11); + setRet(call_sat_vector_imm_op_2824, 0, ret_val_sat_vector_imm_op_2824); + } + cc.bind(label_merge); + } + auto tmp2826 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2826, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2826, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 654); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 655: VSADD__VI */ + continuation_e __vsadd__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vsadd.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADD__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 655); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2827; + x86::Gp ret_val_illegal_normal_2827 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2827, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2827; + setArg(call_illegal_normal_2827, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2827, 1, vd); + setArg(call_illegal_normal_2827, 2, vm); + setRet(call_illegal_normal_2827, 0, ret_val_illegal_normal_2827); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2829; + x86::Gp ret_val_sew_2829 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2829, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2828; + auto sat_vector_imm_op_2828_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2828_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2828_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2828_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2828_arg11 = ret_val_sew_2829; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2828 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2828, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2828, 64, false) + , traits::vxsat); + setArg(call_sew_2829, 0, reinterpret_cast(this)); + setRet(call_sew_2829, 0, ret_val_sew_2829); + setArg(call_sat_vector_imm_op_2828, 0, V); + setArg(call_sat_vector_imm_op_2828, 1, 33); + setArg(call_sat_vector_imm_op_2828, 2, 3); + setArg(call_sat_vector_imm_op_2828, 3, sat_vector_imm_op_2828_arg3); + setArg(call_sat_vector_imm_op_2828, 4, sat_vector_imm_op_2828_arg4); + setArg(call_sat_vector_imm_op_2828, 5, sat_vector_imm_op_2828_arg5); + setArg(call_sat_vector_imm_op_2828, 6, sat_vector_imm_op_2828_arg6); + setArg(call_sat_vector_imm_op_2828, 7, vm); + setArg(call_sat_vector_imm_op_2828, 8, vd); + setArg(call_sat_vector_imm_op_2828, 9, vs2); + setArg(call_sat_vector_imm_op_2828, 10, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_sat_vector_imm_op_2828, 11, sat_vector_imm_op_2828_arg11); + setRet(call_sat_vector_imm_op_2828, 0, ret_val_sat_vector_imm_op_2828); + } + cc.bind(label_merge); + } + auto tmp2830 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2830, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2830, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 655); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 656: VSADD__VV */ + continuation_e __vsadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 656); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2831; + x86::Gp ret_val_illegal_normal_2831 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2831, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2831; + setArg(call_illegal_normal_2831, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2831, 1, vd); + setArg(call_illegal_normal_2831, 2, vm); + setRet(call_illegal_normal_2831, 0, ret_val_illegal_normal_2831); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2833; + x86::Gp ret_val_sew_2833 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2833, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2832; + auto sat_vector_vector_op_2832_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2832_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2832_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2832_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2832_arg11 = ret_val_sew_2833; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2832 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2832, &sat_vector_vector_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_op_2832, 64, false) + , traits::vxsat); + setArg(call_sew_2833, 0, reinterpret_cast(this)); + setRet(call_sew_2833, 0, ret_val_sew_2833); + setArg(call_sat_vector_vector_op_2832, 0, V); + setArg(call_sat_vector_vector_op_2832, 1, 33); + setArg(call_sat_vector_vector_op_2832, 2, 0); + setArg(call_sat_vector_vector_op_2832, 3, sat_vector_vector_op_2832_arg3); + setArg(call_sat_vector_vector_op_2832, 4, sat_vector_vector_op_2832_arg4); + setArg(call_sat_vector_vector_op_2832, 5, sat_vector_vector_op_2832_arg5); + setArg(call_sat_vector_vector_op_2832, 6, sat_vector_vector_op_2832_arg6); + setArg(call_sat_vector_vector_op_2832, 7, vm); + setArg(call_sat_vector_vector_op_2832, 8, vd); + setArg(call_sat_vector_vector_op_2832, 9, vs2); + setArg(call_sat_vector_vector_op_2832, 10, vs1); + setArg(call_sat_vector_vector_op_2832, 11, sat_vector_vector_op_2832_arg11); + setRet(call_sat_vector_vector_op_2832, 0, ret_val_sat_vector_vector_op_2832); + } + cc.bind(label_merge); + } + auto tmp2834 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2834, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2834, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 656); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 657: VSADD__VX */ + continuation_e __vsadd__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSADD__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 657); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2835; + x86::Gp ret_val_illegal_normal_2835 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2835, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2836 = get_reg(cc, 8, false); + mov(cc, tmp2836, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2836, ret_val_illegal_normal_2835); + setArg(call_illegal_normal_2835, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2835, 1, vd); + setArg(call_illegal_normal_2835, 2, vm); + setRet(call_illegal_normal_2835, 0, ret_val_illegal_normal_2835); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2838; + x86::Gp ret_val_sew_2838 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2838, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2837; + auto sat_vector_imm_op_2837_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2837_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2837_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2837_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2837_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto sat_vector_imm_op_2837_arg11 = ret_val_sew_2838; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2837 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2837, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2837, 64, false) + , traits::vxsat); + setArg(call_sew_2838, 0, reinterpret_cast(this)); + setRet(call_sew_2838, 0, ret_val_sew_2838); + setArg(call_sat_vector_imm_op_2837, 0, V); + setArg(call_sat_vector_imm_op_2837, 1, 33); + setArg(call_sat_vector_imm_op_2837, 2, 4); + setArg(call_sat_vector_imm_op_2837, 3, sat_vector_imm_op_2837_arg3); + setArg(call_sat_vector_imm_op_2837, 4, sat_vector_imm_op_2837_arg4); + setArg(call_sat_vector_imm_op_2837, 5, sat_vector_imm_op_2837_arg5); + setArg(call_sat_vector_imm_op_2837, 6, sat_vector_imm_op_2837_arg6); + setArg(call_sat_vector_imm_op_2837, 7, vm); + setArg(call_sat_vector_imm_op_2837, 8, vd); + setArg(call_sat_vector_imm_op_2837, 9, vs2); + setArg(call_sat_vector_imm_op_2837, 10, sat_vector_imm_op_2837_arg10); + setArg(call_sat_vector_imm_op_2837, 11, sat_vector_imm_op_2837_arg11); + setRet(call_sat_vector_imm_op_2837, 0, ret_val_sat_vector_imm_op_2837); + } + cc.bind(label_merge); + } + auto tmp2839 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2839, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2839, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 657); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 658: VSSUBU__VV */ + continuation_e __vssubu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSUBU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 658); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2840; + x86::Gp ret_val_illegal_normal_2840 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2840, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2840; + setArg(call_illegal_normal_2840, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2840, 1, vd); + setArg(call_illegal_normal_2840, 2, vm); + setRet(call_illegal_normal_2840, 0, ret_val_illegal_normal_2840); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2842; + x86::Gp ret_val_sew_2842 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2842, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2841; + auto sat_vector_vector_op_2841_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2841_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2841_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2841_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2841_arg11 = ret_val_sew_2842; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2841 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2841, &sat_vector_vector_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_op_2841, 64, false) + , traits::vxsat); + setArg(call_sew_2842, 0, reinterpret_cast(this)); + setRet(call_sew_2842, 0, ret_val_sew_2842); + setArg(call_sat_vector_vector_op_2841, 0, V); + setArg(call_sat_vector_vector_op_2841, 1, 34); + setArg(call_sat_vector_vector_op_2841, 2, 0); + setArg(call_sat_vector_vector_op_2841, 3, sat_vector_vector_op_2841_arg3); + setArg(call_sat_vector_vector_op_2841, 4, sat_vector_vector_op_2841_arg4); + setArg(call_sat_vector_vector_op_2841, 5, sat_vector_vector_op_2841_arg5); + setArg(call_sat_vector_vector_op_2841, 6, sat_vector_vector_op_2841_arg6); + setArg(call_sat_vector_vector_op_2841, 7, vm); + setArg(call_sat_vector_vector_op_2841, 8, vd); + setArg(call_sat_vector_vector_op_2841, 9, vs2); + setArg(call_sat_vector_vector_op_2841, 10, vs1); + setArg(call_sat_vector_vector_op_2841, 11, sat_vector_vector_op_2841_arg11); + setRet(call_sat_vector_vector_op_2841, 0, ret_val_sat_vector_vector_op_2841); + } + cc.bind(label_merge); + } + auto tmp2843 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2843, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2843, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 658); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 659: VSSUBU__VX */ + continuation_e __vssubu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSUBU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 659); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2844; + x86::Gp ret_val_illegal_normal_2844 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2844, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2845 = get_reg(cc, 8, false); + mov(cc, tmp2845, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2845, ret_val_illegal_normal_2844); + setArg(call_illegal_normal_2844, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2844, 1, vd); + setArg(call_illegal_normal_2844, 2, vm); + setRet(call_illegal_normal_2844, 0, ret_val_illegal_normal_2844); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2847; + x86::Gp ret_val_sew_2847 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2847, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2846; + auto sat_vector_imm_op_2846_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2846_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2846_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2846_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2846_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto sat_vector_imm_op_2846_arg11 = ret_val_sew_2847; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2846 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2846, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2846, 64, false) + , traits::vxsat); + setArg(call_sew_2847, 0, reinterpret_cast(this)); + setRet(call_sew_2847, 0, ret_val_sew_2847); + setArg(call_sat_vector_imm_op_2846, 0, V); + setArg(call_sat_vector_imm_op_2846, 1, 34); + setArg(call_sat_vector_imm_op_2846, 2, 4); + setArg(call_sat_vector_imm_op_2846, 3, sat_vector_imm_op_2846_arg3); + setArg(call_sat_vector_imm_op_2846, 4, sat_vector_imm_op_2846_arg4); + setArg(call_sat_vector_imm_op_2846, 5, sat_vector_imm_op_2846_arg5); + setArg(call_sat_vector_imm_op_2846, 6, sat_vector_imm_op_2846_arg6); + setArg(call_sat_vector_imm_op_2846, 7, vm); + setArg(call_sat_vector_imm_op_2846, 8, vd); + setArg(call_sat_vector_imm_op_2846, 9, vs2); + setArg(call_sat_vector_imm_op_2846, 10, sat_vector_imm_op_2846_arg10); + setArg(call_sat_vector_imm_op_2846, 11, sat_vector_imm_op_2846_arg11); + setRet(call_sat_vector_imm_op_2846, 0, ret_val_sat_vector_imm_op_2846); + } + cc.bind(label_merge); + } + auto tmp2848 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2848, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2848, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 659); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 660: VSSUB__VV */ + continuation_e __vssub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 660); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2849; + x86::Gp ret_val_illegal_normal_2849 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2849, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2849; + setArg(call_illegal_normal_2849, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2849, 1, vd); + setArg(call_illegal_normal_2849, 2, vm); + setRet(call_illegal_normal_2849, 0, ret_val_illegal_normal_2849); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2851; + x86::Gp ret_val_sew_2851 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2851, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2850; + auto sat_vector_vector_op_2850_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2850_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2850_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2850_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2850_arg11 = ret_val_sew_2851; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2850 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2850, &sat_vector_vector_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_op_2850, 64, false) + , traits::vxsat); + setArg(call_sew_2851, 0, reinterpret_cast(this)); + setRet(call_sew_2851, 0, ret_val_sew_2851); + setArg(call_sat_vector_vector_op_2850, 0, V); + setArg(call_sat_vector_vector_op_2850, 1, 35); + setArg(call_sat_vector_vector_op_2850, 2, 0); + setArg(call_sat_vector_vector_op_2850, 3, sat_vector_vector_op_2850_arg3); + setArg(call_sat_vector_vector_op_2850, 4, sat_vector_vector_op_2850_arg4); + setArg(call_sat_vector_vector_op_2850, 5, sat_vector_vector_op_2850_arg5); + setArg(call_sat_vector_vector_op_2850, 6, sat_vector_vector_op_2850_arg6); + setArg(call_sat_vector_vector_op_2850, 7, vm); + setArg(call_sat_vector_vector_op_2850, 8, vd); + setArg(call_sat_vector_vector_op_2850, 9, vs2); + setArg(call_sat_vector_vector_op_2850, 10, vs1); + setArg(call_sat_vector_vector_op_2850, 11, sat_vector_vector_op_2850_arg11); + setRet(call_sat_vector_vector_op_2850, 0, ret_val_sat_vector_vector_op_2850); + } + cc.bind(label_merge); + } + auto tmp2852 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2852, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2852, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 660); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 661: VSSUB__VX */ + continuation_e __vssub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 661); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2853; + x86::Gp ret_val_illegal_normal_2853 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2853, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2854 = get_reg(cc, 8, false); + mov(cc, tmp2854, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2854, ret_val_illegal_normal_2853); + setArg(call_illegal_normal_2853, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2853, 1, vd); + setArg(call_illegal_normal_2853, 2, vm); + setRet(call_illegal_normal_2853, 0, ret_val_illegal_normal_2853); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2856; + x86::Gp ret_val_sew_2856 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2856, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2855; + auto sat_vector_imm_op_2855_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2855_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2855_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2855_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2855_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto sat_vector_imm_op_2855_arg11 = ret_val_sew_2856; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2855 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2855, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2855, 64, false) + , traits::vxsat); + setArg(call_sew_2856, 0, reinterpret_cast(this)); + setRet(call_sew_2856, 0, ret_val_sew_2856); + setArg(call_sat_vector_imm_op_2855, 0, V); + setArg(call_sat_vector_imm_op_2855, 1, 35); + setArg(call_sat_vector_imm_op_2855, 2, 4); + setArg(call_sat_vector_imm_op_2855, 3, sat_vector_imm_op_2855_arg3); + setArg(call_sat_vector_imm_op_2855, 4, sat_vector_imm_op_2855_arg4); + setArg(call_sat_vector_imm_op_2855, 5, sat_vector_imm_op_2855_arg5); + setArg(call_sat_vector_imm_op_2855, 6, sat_vector_imm_op_2855_arg6); + setArg(call_sat_vector_imm_op_2855, 7, vm); + setArg(call_sat_vector_imm_op_2855, 8, vd); + setArg(call_sat_vector_imm_op_2855, 9, vs2); + setArg(call_sat_vector_imm_op_2855, 10, sat_vector_imm_op_2855_arg10); + setArg(call_sat_vector_imm_op_2855, 11, sat_vector_imm_op_2855_arg11); + setRet(call_sat_vector_imm_op_2855, 0, ret_val_sat_vector_imm_op_2855); + } + cc.bind(label_merge); + } + auto tmp2857 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2857, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2857, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 661); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 662: VAADDU__VV */ + continuation_e __vaaddu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vaaddu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAADDU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 662); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2858; + x86::Gp ret_val_illegal_normal_2858 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2858, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2858; + setArg(call_illegal_normal_2858, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2858, 1, vd); + setArg(call_illegal_normal_2858, 2, vm); + setRet(call_illegal_normal_2858, 0, ret_val_illegal_normal_2858); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2860; + x86::Gp ret_val_sew_2860 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2860, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2859; + auto sat_vector_vector_op_2859_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2859_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2859_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2859_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2859_arg11 = ret_val_sew_2860; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2859 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2859, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2859; + setArg(call_sew_2860, 0, reinterpret_cast(this)); + setRet(call_sew_2860, 0, ret_val_sew_2860); + setArg(call_sat_vector_vector_op_2859, 0, V); + setArg(call_sat_vector_vector_op_2859, 1, 8); + setArg(call_sat_vector_vector_op_2859, 2, 2); + setArg(call_sat_vector_vector_op_2859, 3, sat_vector_vector_op_2859_arg3); + setArg(call_sat_vector_vector_op_2859, 4, sat_vector_vector_op_2859_arg4); + setArg(call_sat_vector_vector_op_2859, 5, sat_vector_vector_op_2859_arg5); + setArg(call_sat_vector_vector_op_2859, 6, sat_vector_vector_op_2859_arg6); + setArg(call_sat_vector_vector_op_2859, 7, vm); + setArg(call_sat_vector_vector_op_2859, 8, vd); + setArg(call_sat_vector_vector_op_2859, 9, vs2); + setArg(call_sat_vector_vector_op_2859, 10, vs1); + setArg(call_sat_vector_vector_op_2859, 11, sat_vector_vector_op_2859_arg11); + setRet(call_sat_vector_vector_op_2859, 0, ret_val_sat_vector_vector_op_2859); + } + cc.bind(label_merge); + } + auto tmp2861 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2861, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2861, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 662); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 663: VAADDU__VX */ + continuation_e __vaaddu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vaaddu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAADDU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 663); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2862; + x86::Gp ret_val_illegal_normal_2862 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2862, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2863 = get_reg(cc, 8, false); + mov(cc, tmp2863, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2863, ret_val_illegal_normal_2862); + setArg(call_illegal_normal_2862, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2862, 1, vd); + setArg(call_illegal_normal_2862, 2, vm); + setRet(call_illegal_normal_2862, 0, ret_val_illegal_normal_2862); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2865; + x86::Gp ret_val_sew_2865 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2865, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2864; + auto sat_vector_imm_op_2864_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2864_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2864_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2864_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2864_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto sat_vector_imm_op_2864_arg11 = ret_val_sew_2865; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2864 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2864, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2864; + setArg(call_sew_2865, 0, reinterpret_cast(this)); + setRet(call_sew_2865, 0, ret_val_sew_2865); + setArg(call_sat_vector_imm_op_2864, 0, V); + setArg(call_sat_vector_imm_op_2864, 1, 8); + setArg(call_sat_vector_imm_op_2864, 2, 6); + setArg(call_sat_vector_imm_op_2864, 3, sat_vector_imm_op_2864_arg3); + setArg(call_sat_vector_imm_op_2864, 4, sat_vector_imm_op_2864_arg4); + setArg(call_sat_vector_imm_op_2864, 5, sat_vector_imm_op_2864_arg5); + setArg(call_sat_vector_imm_op_2864, 6, sat_vector_imm_op_2864_arg6); + setArg(call_sat_vector_imm_op_2864, 7, vm); + setArg(call_sat_vector_imm_op_2864, 8, vd); + setArg(call_sat_vector_imm_op_2864, 9, vs2); + setArg(call_sat_vector_imm_op_2864, 10, sat_vector_imm_op_2864_arg10); + setArg(call_sat_vector_imm_op_2864, 11, sat_vector_imm_op_2864_arg11); + setRet(call_sat_vector_imm_op_2864, 0, ret_val_sat_vector_imm_op_2864); + } + cc.bind(label_merge); + } + auto tmp2866 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2866, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2866, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 663); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 664: VAADD__VV */ + continuation_e __vaadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vaadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 664); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2867; + x86::Gp ret_val_illegal_normal_2867 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2867, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2867; + setArg(call_illegal_normal_2867, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2867, 1, vd); + setArg(call_illegal_normal_2867, 2, vm); + setRet(call_illegal_normal_2867, 0, ret_val_illegal_normal_2867); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2869; + x86::Gp ret_val_sew_2869 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2869, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2868; + auto sat_vector_vector_op_2868_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2868_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2868_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2868_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2868_arg11 = ret_val_sew_2869; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2868 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2868, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2868; + setArg(call_sew_2869, 0, reinterpret_cast(this)); + setRet(call_sew_2869, 0, ret_val_sew_2869); + setArg(call_sat_vector_vector_op_2868, 0, V); + setArg(call_sat_vector_vector_op_2868, 1, 9); + setArg(call_sat_vector_vector_op_2868, 2, 2); + setArg(call_sat_vector_vector_op_2868, 3, sat_vector_vector_op_2868_arg3); + setArg(call_sat_vector_vector_op_2868, 4, sat_vector_vector_op_2868_arg4); + setArg(call_sat_vector_vector_op_2868, 5, sat_vector_vector_op_2868_arg5); + setArg(call_sat_vector_vector_op_2868, 6, sat_vector_vector_op_2868_arg6); + setArg(call_sat_vector_vector_op_2868, 7, vm); + setArg(call_sat_vector_vector_op_2868, 8, vd); + setArg(call_sat_vector_vector_op_2868, 9, vs2); + setArg(call_sat_vector_vector_op_2868, 10, vs1); + setArg(call_sat_vector_vector_op_2868, 11, sat_vector_vector_op_2868_arg11); + setRet(call_sat_vector_vector_op_2868, 0, ret_val_sat_vector_vector_op_2868); + } + cc.bind(label_merge); + } + auto tmp2870 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2870, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2870, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 664); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 665: VAADD__VX */ + continuation_e __vaadd__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vaadd.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VAADD__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 665); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2871; + x86::Gp ret_val_illegal_normal_2871 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2871, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2872 = get_reg(cc, 8, false); + mov(cc, tmp2872, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2872, ret_val_illegal_normal_2871); + setArg(call_illegal_normal_2871, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2871, 1, vd); + setArg(call_illegal_normal_2871, 2, vm); + setRet(call_illegal_normal_2871, 0, ret_val_illegal_normal_2871); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2874; + x86::Gp ret_val_sew_2874 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2874, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2873; + auto sat_vector_imm_op_2873_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2873_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2873_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2873_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2873_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto sat_vector_imm_op_2873_arg11 = ret_val_sew_2874; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2873 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2873, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2873; + setArg(call_sew_2874, 0, reinterpret_cast(this)); + setRet(call_sew_2874, 0, ret_val_sew_2874); + setArg(call_sat_vector_imm_op_2873, 0, V); + setArg(call_sat_vector_imm_op_2873, 1, 9); + setArg(call_sat_vector_imm_op_2873, 2, 6); + setArg(call_sat_vector_imm_op_2873, 3, sat_vector_imm_op_2873_arg3); + setArg(call_sat_vector_imm_op_2873, 4, sat_vector_imm_op_2873_arg4); + setArg(call_sat_vector_imm_op_2873, 5, sat_vector_imm_op_2873_arg5); + setArg(call_sat_vector_imm_op_2873, 6, sat_vector_imm_op_2873_arg6); + setArg(call_sat_vector_imm_op_2873, 7, vm); + setArg(call_sat_vector_imm_op_2873, 8, vd); + setArg(call_sat_vector_imm_op_2873, 9, vs2); + setArg(call_sat_vector_imm_op_2873, 10, sat_vector_imm_op_2873_arg10); + setArg(call_sat_vector_imm_op_2873, 11, sat_vector_imm_op_2873_arg11); + setRet(call_sat_vector_imm_op_2873, 0, ret_val_sat_vector_imm_op_2873); + } + cc.bind(label_merge); + } + auto tmp2875 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2875, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2875, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 665); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 666: VASUBU__VV */ + continuation_e __vasubu__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vasubu.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VASUBU__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 666); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2876; + x86::Gp ret_val_illegal_normal_2876 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2876, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2876; + setArg(call_illegal_normal_2876, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2876, 1, vd); + setArg(call_illegal_normal_2876, 2, vm); + setRet(call_illegal_normal_2876, 0, ret_val_illegal_normal_2876); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2878; + x86::Gp ret_val_sew_2878 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2878, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2877; + auto sat_vector_vector_op_2877_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2877_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2877_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2877_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2877_arg11 = ret_val_sew_2878; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2877 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2877, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2877; + setArg(call_sew_2878, 0, reinterpret_cast(this)); + setRet(call_sew_2878, 0, ret_val_sew_2878); + setArg(call_sat_vector_vector_op_2877, 0, V); + setArg(call_sat_vector_vector_op_2877, 1, 10); + setArg(call_sat_vector_vector_op_2877, 2, 2); + setArg(call_sat_vector_vector_op_2877, 3, sat_vector_vector_op_2877_arg3); + setArg(call_sat_vector_vector_op_2877, 4, sat_vector_vector_op_2877_arg4); + setArg(call_sat_vector_vector_op_2877, 5, sat_vector_vector_op_2877_arg5); + setArg(call_sat_vector_vector_op_2877, 6, sat_vector_vector_op_2877_arg6); + setArg(call_sat_vector_vector_op_2877, 7, vm); + setArg(call_sat_vector_vector_op_2877, 8, vd); + setArg(call_sat_vector_vector_op_2877, 9, vs2); + setArg(call_sat_vector_vector_op_2877, 10, vs1); + setArg(call_sat_vector_vector_op_2877, 11, sat_vector_vector_op_2877_arg11); + setRet(call_sat_vector_vector_op_2877, 0, ret_val_sat_vector_vector_op_2877); + } + cc.bind(label_merge); + } + auto tmp2879 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2879, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2879, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 666); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 667: VASUBU__VX */ + continuation_e __vasubu__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vasubu.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VASUBU__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 667); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2880; + x86::Gp ret_val_illegal_normal_2880 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2880, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2881 = get_reg(cc, 8, false); + mov(cc, tmp2881, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2881, ret_val_illegal_normal_2880); + setArg(call_illegal_normal_2880, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2880, 1, vd); + setArg(call_illegal_normal_2880, 2, vm); + setRet(call_illegal_normal_2880, 0, ret_val_illegal_normal_2880); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2883; + x86::Gp ret_val_sew_2883 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2883, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2882; + auto sat_vector_imm_op_2882_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2882_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2882_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2882_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2882_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto sat_vector_imm_op_2882_arg11 = ret_val_sew_2883; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2882 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2882, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2882; + setArg(call_sew_2883, 0, reinterpret_cast(this)); + setRet(call_sew_2883, 0, ret_val_sew_2883); + setArg(call_sat_vector_imm_op_2882, 0, V); + setArg(call_sat_vector_imm_op_2882, 1, 10); + setArg(call_sat_vector_imm_op_2882, 2, 6); + setArg(call_sat_vector_imm_op_2882, 3, sat_vector_imm_op_2882_arg3); + setArg(call_sat_vector_imm_op_2882, 4, sat_vector_imm_op_2882_arg4); + setArg(call_sat_vector_imm_op_2882, 5, sat_vector_imm_op_2882_arg5); + setArg(call_sat_vector_imm_op_2882, 6, sat_vector_imm_op_2882_arg6); + setArg(call_sat_vector_imm_op_2882, 7, vm); + setArg(call_sat_vector_imm_op_2882, 8, vd); + setArg(call_sat_vector_imm_op_2882, 9, vs2); + setArg(call_sat_vector_imm_op_2882, 10, sat_vector_imm_op_2882_arg10); + setArg(call_sat_vector_imm_op_2882, 11, sat_vector_imm_op_2882_arg11); + setRet(call_sat_vector_imm_op_2882, 0, ret_val_sat_vector_imm_op_2882); + } + cc.bind(label_merge); + } + auto tmp2884 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2884, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2884, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 667); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 668: VASUB__VV */ + continuation_e __vasub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vasub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VASUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 668); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2885; + x86::Gp ret_val_illegal_normal_2885 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2885, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2885; + setArg(call_illegal_normal_2885, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2885, 1, vd); + setArg(call_illegal_normal_2885, 2, vm); + setRet(call_illegal_normal_2885, 0, ret_val_illegal_normal_2885); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2887; + x86::Gp ret_val_sew_2887 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2887, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2886; + auto sat_vector_vector_op_2886_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2886_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2886_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2886_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2886_arg11 = ret_val_sew_2887; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2886 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2886, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2886; + setArg(call_sew_2887, 0, reinterpret_cast(this)); + setRet(call_sew_2887, 0, ret_val_sew_2887); + setArg(call_sat_vector_vector_op_2886, 0, V); + setArg(call_sat_vector_vector_op_2886, 1, 11); + setArg(call_sat_vector_vector_op_2886, 2, 2); + setArg(call_sat_vector_vector_op_2886, 3, sat_vector_vector_op_2886_arg3); + setArg(call_sat_vector_vector_op_2886, 4, sat_vector_vector_op_2886_arg4); + setArg(call_sat_vector_vector_op_2886, 5, sat_vector_vector_op_2886_arg5); + setArg(call_sat_vector_vector_op_2886, 6, sat_vector_vector_op_2886_arg6); + setArg(call_sat_vector_vector_op_2886, 7, vm); + setArg(call_sat_vector_vector_op_2886, 8, vd); + setArg(call_sat_vector_vector_op_2886, 9, vs2); + setArg(call_sat_vector_vector_op_2886, 10, vs1); + setArg(call_sat_vector_vector_op_2886, 11, sat_vector_vector_op_2886_arg11); + setRet(call_sat_vector_vector_op_2886, 0, ret_val_sat_vector_vector_op_2886); + } + cc.bind(label_merge); + } + auto tmp2888 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2888, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2888, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 668); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 669: VASUB__VX */ + continuation_e __vasub__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vasub.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VASUB__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 669); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2889; + x86::Gp ret_val_illegal_normal_2889 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2889, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2890 = get_reg(cc, 8, false); + mov(cc, tmp2890, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2890, ret_val_illegal_normal_2889); + setArg(call_illegal_normal_2889, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2889, 1, vd); + setArg(call_illegal_normal_2889, 2, vm); + setRet(call_illegal_normal_2889, 0, ret_val_illegal_normal_2889); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2892; + x86::Gp ret_val_sew_2892 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2892, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2891; + auto sat_vector_imm_op_2891_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2891_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2891_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2891_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2891_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto sat_vector_imm_op_2891_arg11 = ret_val_sew_2892; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2891 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2891, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2891; + setArg(call_sew_2892, 0, reinterpret_cast(this)); + setRet(call_sew_2892, 0, ret_val_sew_2892); + setArg(call_sat_vector_imm_op_2891, 0, V); + setArg(call_sat_vector_imm_op_2891, 1, 11); + setArg(call_sat_vector_imm_op_2891, 2, 6); + setArg(call_sat_vector_imm_op_2891, 3, sat_vector_imm_op_2891_arg3); + setArg(call_sat_vector_imm_op_2891, 4, sat_vector_imm_op_2891_arg4); + setArg(call_sat_vector_imm_op_2891, 5, sat_vector_imm_op_2891_arg5); + setArg(call_sat_vector_imm_op_2891, 6, sat_vector_imm_op_2891_arg6); + setArg(call_sat_vector_imm_op_2891, 7, vm); + setArg(call_sat_vector_imm_op_2891, 8, vd); + setArg(call_sat_vector_imm_op_2891, 9, vs2); + setArg(call_sat_vector_imm_op_2891, 10, sat_vector_imm_op_2891_arg10); + setArg(call_sat_vector_imm_op_2891, 11, sat_vector_imm_op_2891_arg11); + setRet(call_sat_vector_imm_op_2891, 0, ret_val_sat_vector_imm_op_2891); + } + cc.bind(label_merge); + } + auto tmp2893 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2893, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2893, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 669); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 670: VSMUL__VV */ + continuation_e __vsmul__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vsmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSMUL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 670); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2894; + x86::Gp ret_val_illegal_normal_2894 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2894, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2894; + setArg(call_illegal_normal_2894, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2894, 1, vd); + setArg(call_illegal_normal_2894, 2, vm); + setRet(call_illegal_normal_2894, 0, ret_val_illegal_normal_2894); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2896; + x86::Gp ret_val_sew_2896 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2896, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2895; + auto sat_vector_vector_op_2895_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2895_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2895_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2895_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2895_arg11 = ret_val_sew_2896; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2895 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2895, &sat_vector_vector_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_op_2895, 64, false) + , traits::vxsat); + setArg(call_sew_2896, 0, reinterpret_cast(this)); + setRet(call_sew_2896, 0, ret_val_sew_2896); + setArg(call_sat_vector_vector_op_2895, 0, V); + setArg(call_sat_vector_vector_op_2895, 1, 39); + setArg(call_sat_vector_vector_op_2895, 2, 0); + setArg(call_sat_vector_vector_op_2895, 3, sat_vector_vector_op_2895_arg3); + setArg(call_sat_vector_vector_op_2895, 4, sat_vector_vector_op_2895_arg4); + setArg(call_sat_vector_vector_op_2895, 5, sat_vector_vector_op_2895_arg5); + setArg(call_sat_vector_vector_op_2895, 6, sat_vector_vector_op_2895_arg6); + setArg(call_sat_vector_vector_op_2895, 7, vm); + setArg(call_sat_vector_vector_op_2895, 8, vd); + setArg(call_sat_vector_vector_op_2895, 9, vs2); + setArg(call_sat_vector_vector_op_2895, 10, vs1); + setArg(call_sat_vector_vector_op_2895, 11, sat_vector_vector_op_2895_arg11); + setRet(call_sat_vector_vector_op_2895, 0, ret_val_sat_vector_vector_op_2895); + } + cc.bind(label_merge); + } + auto tmp2897 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2897, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2897, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 670); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 671: VSMUL__VX */ + continuation_e __vsmul__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vsmul.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSMUL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 671); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2898; + x86::Gp ret_val_illegal_normal_2898 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2898, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2899 = get_reg(cc, 8, false); + mov(cc, tmp2899, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2899, ret_val_illegal_normal_2898); + setArg(call_illegal_normal_2898, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2898, 1, vd); + setArg(call_illegal_normal_2898, 2, vm); + setRet(call_illegal_normal_2898, 0, ret_val_illegal_normal_2898); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2901; + x86::Gp ret_val_sew_2901 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2901, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2900; + auto sat_vector_imm_op_2900_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2900_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2900_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2900_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2900_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto sat_vector_imm_op_2900_arg11 = ret_val_sew_2901; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2900 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2900, &sat_vector_imm_op, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_op_2900, 64, false) + , traits::vxsat); + setArg(call_sew_2901, 0, reinterpret_cast(this)); + setRet(call_sew_2901, 0, ret_val_sew_2901); + setArg(call_sat_vector_imm_op_2900, 0, V); + setArg(call_sat_vector_imm_op_2900, 1, 39); + setArg(call_sat_vector_imm_op_2900, 2, 4); + setArg(call_sat_vector_imm_op_2900, 3, sat_vector_imm_op_2900_arg3); + setArg(call_sat_vector_imm_op_2900, 4, sat_vector_imm_op_2900_arg4); + setArg(call_sat_vector_imm_op_2900, 5, sat_vector_imm_op_2900_arg5); + setArg(call_sat_vector_imm_op_2900, 6, sat_vector_imm_op_2900_arg6); + setArg(call_sat_vector_imm_op_2900, 7, vm); + setArg(call_sat_vector_imm_op_2900, 8, vd); + setArg(call_sat_vector_imm_op_2900, 9, vs2); + setArg(call_sat_vector_imm_op_2900, 10, sat_vector_imm_op_2900_arg10); + setArg(call_sat_vector_imm_op_2900, 11, sat_vector_imm_op_2900_arg11); + setRet(call_sat_vector_imm_op_2900, 0, ret_val_sat_vector_imm_op_2900); + } + cc.bind(label_merge); + } + auto tmp2902 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2902, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2902, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 671); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 672: VSSRL__VI */ + continuation_e __vssrl__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vssrl.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRL__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 672); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2903; + x86::Gp ret_val_illegal_normal_2903 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2903, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2903; + setArg(call_illegal_normal_2903, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2903, 1, vd); + setArg(call_illegal_normal_2903, 2, vm); + setRet(call_illegal_normal_2903, 0, ret_val_illegal_normal_2903); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2905; + x86::Gp ret_val_sew_2905 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2905, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2904; + auto sat_vector_imm_op_2904_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2904_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2904_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2904_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2904_arg11 = ret_val_sew_2905; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2904 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2904, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2904; + setArg(call_sew_2905, 0, reinterpret_cast(this)); + setRet(call_sew_2905, 0, ret_val_sew_2905); + setArg(call_sat_vector_imm_op_2904, 0, V); + setArg(call_sat_vector_imm_op_2904, 1, 42); + setArg(call_sat_vector_imm_op_2904, 2, 3); + setArg(call_sat_vector_imm_op_2904, 3, sat_vector_imm_op_2904_arg3); + setArg(call_sat_vector_imm_op_2904, 4, sat_vector_imm_op_2904_arg4); + setArg(call_sat_vector_imm_op_2904, 5, sat_vector_imm_op_2904_arg5); + setArg(call_sat_vector_imm_op_2904, 6, sat_vector_imm_op_2904_arg6); + setArg(call_sat_vector_imm_op_2904, 7, vm); + setArg(call_sat_vector_imm_op_2904, 8, vd); + setArg(call_sat_vector_imm_op_2904, 9, vs2); + setArg(call_sat_vector_imm_op_2904, 10, (int64_t)(uint64_t)simm); + setArg(call_sat_vector_imm_op_2904, 11, sat_vector_imm_op_2904_arg11); + setRet(call_sat_vector_imm_op_2904, 0, ret_val_sat_vector_imm_op_2904); + } + cc.bind(label_merge); + } + auto tmp2906 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2906, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2906, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 672); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 673: VSSRL__VV */ + continuation_e __vssrl__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssrl.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 673); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2907; + x86::Gp ret_val_illegal_normal_2907 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2907, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2907; + setArg(call_illegal_normal_2907, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2907, 1, vd); + setArg(call_illegal_normal_2907, 2, vm); + setRet(call_illegal_normal_2907, 0, ret_val_illegal_normal_2907); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2909; + x86::Gp ret_val_sew_2909 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2909, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2908; + auto sat_vector_vector_op_2908_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2908_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2908_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2908_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2908_arg11 = ret_val_sew_2909; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2908 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2908, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2908; + setArg(call_sew_2909, 0, reinterpret_cast(this)); + setRet(call_sew_2909, 0, ret_val_sew_2909); + setArg(call_sat_vector_vector_op_2908, 0, V); + setArg(call_sat_vector_vector_op_2908, 1, 42); + setArg(call_sat_vector_vector_op_2908, 2, 0); + setArg(call_sat_vector_vector_op_2908, 3, sat_vector_vector_op_2908_arg3); + setArg(call_sat_vector_vector_op_2908, 4, sat_vector_vector_op_2908_arg4); + setArg(call_sat_vector_vector_op_2908, 5, sat_vector_vector_op_2908_arg5); + setArg(call_sat_vector_vector_op_2908, 6, sat_vector_vector_op_2908_arg6); + setArg(call_sat_vector_vector_op_2908, 7, vm); + setArg(call_sat_vector_vector_op_2908, 8, vd); + setArg(call_sat_vector_vector_op_2908, 9, vs2); + setArg(call_sat_vector_vector_op_2908, 10, vs1); + setArg(call_sat_vector_vector_op_2908, 11, sat_vector_vector_op_2908_arg11); + setRet(call_sat_vector_vector_op_2908, 0, ret_val_sat_vector_vector_op_2908); + } + cc.bind(label_merge); + } + auto tmp2910 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2910, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2910, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 673); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 674: VSSRL__VX */ + continuation_e __vssrl__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssrl.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRL__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 674); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2911; + x86::Gp ret_val_illegal_normal_2911 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2911, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2912 = get_reg(cc, 8, false); + mov(cc, tmp2912, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2912, ret_val_illegal_normal_2911); + setArg(call_illegal_normal_2911, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2911, 1, vd); + setArg(call_illegal_normal_2911, 2, vm); + setRet(call_illegal_normal_2911, 0, ret_val_illegal_normal_2911); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2914; + x86::Gp ret_val_sew_2914 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2914, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2913; + auto sat_vector_imm_op_2913_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2913_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2913_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2913_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2913_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); + auto sat_vector_imm_op_2913_arg11 = ret_val_sew_2914; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2913 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2913, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2913; + setArg(call_sew_2914, 0, reinterpret_cast(this)); + setRet(call_sew_2914, 0, ret_val_sew_2914); + setArg(call_sat_vector_imm_op_2913, 0, V); + setArg(call_sat_vector_imm_op_2913, 1, 42); + setArg(call_sat_vector_imm_op_2913, 2, 4); + setArg(call_sat_vector_imm_op_2913, 3, sat_vector_imm_op_2913_arg3); + setArg(call_sat_vector_imm_op_2913, 4, sat_vector_imm_op_2913_arg4); + setArg(call_sat_vector_imm_op_2913, 5, sat_vector_imm_op_2913_arg5); + setArg(call_sat_vector_imm_op_2913, 6, sat_vector_imm_op_2913_arg6); + setArg(call_sat_vector_imm_op_2913, 7, vm); + setArg(call_sat_vector_imm_op_2913, 8, vd); + setArg(call_sat_vector_imm_op_2913, 9, vs2); + setArg(call_sat_vector_imm_op_2913, 10, sat_vector_imm_op_2913_arg10); + setArg(call_sat_vector_imm_op_2913, 11, sat_vector_imm_op_2913_arg11); + setRet(call_sat_vector_imm_op_2913, 0, ret_val_sat_vector_imm_op_2913); + } + cc.bind(label_merge); + } + auto tmp2915 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2915, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2915, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 674); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 675: VSSRA__VI */ + continuation_e __vssra__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vssra.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRA__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 675); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2916; + x86::Gp ret_val_illegal_normal_2916 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2916, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2916; + setArg(call_illegal_normal_2916, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2916, 1, vd); + setArg(call_illegal_normal_2916, 2, vm); + setRet(call_illegal_normal_2916, 0, ret_val_illegal_normal_2916); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2918; + x86::Gp ret_val_sew_2918 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2918, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2917; + auto sat_vector_imm_op_2917_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2917_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2917_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2917_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2917_arg11 = ret_val_sew_2918; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2917 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2917, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2917; + setArg(call_sew_2918, 0, reinterpret_cast(this)); + setRet(call_sew_2918, 0, ret_val_sew_2918); + setArg(call_sat_vector_imm_op_2917, 0, V); + setArg(call_sat_vector_imm_op_2917, 1, 43); + setArg(call_sat_vector_imm_op_2917, 2, 3); + setArg(call_sat_vector_imm_op_2917, 3, sat_vector_imm_op_2917_arg3); + setArg(call_sat_vector_imm_op_2917, 4, sat_vector_imm_op_2917_arg4); + setArg(call_sat_vector_imm_op_2917, 5, sat_vector_imm_op_2917_arg5); + setArg(call_sat_vector_imm_op_2917, 6, sat_vector_imm_op_2917_arg6); + setArg(call_sat_vector_imm_op_2917, 7, vm); + setArg(call_sat_vector_imm_op_2917, 8, vd); + setArg(call_sat_vector_imm_op_2917, 9, vs2); + setArg(call_sat_vector_imm_op_2917, 10, (int64_t)(uint64_t)simm); + setArg(call_sat_vector_imm_op_2917, 11, sat_vector_imm_op_2917_arg11); + setRet(call_sat_vector_imm_op_2917, 0, ret_val_sat_vector_imm_op_2917); + } + cc.bind(label_merge); + } + auto tmp2919 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2919, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2919, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 675); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 676: VSSRA__VV */ + continuation_e __vssra__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vssra.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRA__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 676); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2920; + x86::Gp ret_val_illegal_normal_2920 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2920, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2920; + setArg(call_illegal_normal_2920, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2920, 1, vd); + setArg(call_illegal_normal_2920, 2, vm); + setRet(call_illegal_normal_2920, 0, ret_val_illegal_normal_2920); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2922; + x86::Gp ret_val_sew_2922 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2922, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2921; + auto sat_vector_vector_op_2921_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2921_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2921_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2921_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2921_arg11 = ret_val_sew_2922; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_op_2921 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2921, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2921; + setArg(call_sew_2922, 0, reinterpret_cast(this)); + setRet(call_sew_2922, 0, ret_val_sew_2922); + setArg(call_sat_vector_vector_op_2921, 0, V); + setArg(call_sat_vector_vector_op_2921, 1, 43); + setArg(call_sat_vector_vector_op_2921, 2, 0); + setArg(call_sat_vector_vector_op_2921, 3, sat_vector_vector_op_2921_arg3); + setArg(call_sat_vector_vector_op_2921, 4, sat_vector_vector_op_2921_arg4); + setArg(call_sat_vector_vector_op_2921, 5, sat_vector_vector_op_2921_arg5); + setArg(call_sat_vector_vector_op_2921, 6, sat_vector_vector_op_2921_arg6); + setArg(call_sat_vector_vector_op_2921, 7, vm); + setArg(call_sat_vector_vector_op_2921, 8, vd); + setArg(call_sat_vector_vector_op_2921, 9, vs2); + setArg(call_sat_vector_vector_op_2921, 10, vs1); + setArg(call_sat_vector_vector_op_2921, 11, sat_vector_vector_op_2921_arg11); + setRet(call_sat_vector_vector_op_2921, 0, ret_val_sat_vector_vector_op_2921); + } + cc.bind(label_merge); + } + auto tmp2923 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2923, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2923, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 676); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 677: VSSRA__VX */ + continuation_e __vssra__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vssra.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSSRA__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 677); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_2924; + x86::Gp ret_val_illegal_normal_2924 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2924, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2925 = get_reg(cc, 8, false); + mov(cc, tmp2925, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2925, ret_val_illegal_normal_2924); + setArg(call_illegal_normal_2924, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2924, 1, vd); + setArg(call_illegal_normal_2924, 2, vm); + setRet(call_illegal_normal_2924, 0, ret_val_illegal_normal_2924); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2927; + x86::Gp ret_val_sew_2927 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2927, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2926; + auto sat_vector_imm_op_2926_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2926_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2926_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2926_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2926_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); + auto sat_vector_imm_op_2926_arg11 = ret_val_sew_2927; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_op_2926 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2926, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2926; + setArg(call_sew_2927, 0, reinterpret_cast(this)); + setRet(call_sew_2927, 0, ret_val_sew_2927); + setArg(call_sat_vector_imm_op_2926, 0, V); + setArg(call_sat_vector_imm_op_2926, 1, 43); + setArg(call_sat_vector_imm_op_2926, 2, 4); + setArg(call_sat_vector_imm_op_2926, 3, sat_vector_imm_op_2926_arg3); + setArg(call_sat_vector_imm_op_2926, 4, sat_vector_imm_op_2926_arg4); + setArg(call_sat_vector_imm_op_2926, 5, sat_vector_imm_op_2926_arg5); + setArg(call_sat_vector_imm_op_2926, 6, sat_vector_imm_op_2926_arg6); + setArg(call_sat_vector_imm_op_2926, 7, vm); + setArg(call_sat_vector_imm_op_2926, 8, vd); + setArg(call_sat_vector_imm_op_2926, 9, vs2); + setArg(call_sat_vector_imm_op_2926, 10, sat_vector_imm_op_2926_arg10); + setArg(call_sat_vector_imm_op_2926, 11, sat_vector_imm_op_2926_arg11); + setRet(call_sat_vector_imm_op_2926, 0, ret_val_sat_vector_imm_op_2926); + } + cc.bind(label_merge); + } + auto tmp2928 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2928, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2928, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 677); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 678: VNCLIPU__WI */ + continuation_e __vnclipu__wi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnclipu.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIPU__WI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 678); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2929; + x86::Gp ret_val_get_sew_pow_2929 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2929, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2930 = get_reg(cc, 8, false); + mov(cc, tmp2930, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2930, ret_val_get_sew_pow_2929)), 8, false), ~ 1); + setArg(call_get_sew_pow_2929, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2929, 0, ret_val_get_sew_pow_2929); + InvokeNode* call_get_lmul_pow_2931; + x86::Gp ret_val_get_lmul_pow_2931 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2931, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2931; + setArg(call_get_lmul_pow_2931, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2931, 0, ret_val_get_lmul_pow_2931); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2932; + auto illegal_variable_width_2932_arg2 = SEW_widen; + auto illegal_variable_width_2932_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2932 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2932, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2933; + auto valid_reg_overlap_2933_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2933_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2933 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2933, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2932, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2933))); + setArg(call_illegal_variable_width_2932, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2932, 1, vd); + setArg(call_illegal_variable_width_2932, 2, vm); + setArg(call_illegal_variable_width_2932, 3, illegal_variable_width_2932_arg2); + setArg(call_illegal_variable_width_2932, 4, illegal_variable_width_2932_arg3); + setRet(call_illegal_variable_width_2932, 0, ret_val_illegal_variable_width_2932); + setArg(call_valid_reg_overlap_2933, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2933, 1, vs2); + setArg(call_valid_reg_overlap_2933, 2, vd); + setArg(call_valid_reg_overlap_2933, 3, valid_reg_overlap_2933_arg2); + setArg(call_valid_reg_overlap_2933, 4, valid_reg_overlap_2933_arg3); + setRet(call_valid_reg_overlap_2933, 0, ret_val_valid_reg_overlap_2933); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2935; + x86::Gp ret_val_sew_2935 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2935, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2934; + auto sat_vector_imm_vw_2934_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2934_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2934_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2934_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2934_arg11 = ret_val_sew_2935; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_vw_2934 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2934, &sat_vector_imm_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_vw_2934, 64, false) + , traits::vxsat); + setArg(call_sew_2935, 0, reinterpret_cast(this)); + setRet(call_sew_2935, 0, ret_val_sew_2935); + setArg(call_sat_vector_imm_vw_2934, 0, V); + setArg(call_sat_vector_imm_vw_2934, 1, 46); + setArg(call_sat_vector_imm_vw_2934, 2, 3); + setArg(call_sat_vector_imm_vw_2934, 3, sat_vector_imm_vw_2934_arg3); + setArg(call_sat_vector_imm_vw_2934, 4, sat_vector_imm_vw_2934_arg4); + setArg(call_sat_vector_imm_vw_2934, 5, sat_vector_imm_vw_2934_arg5); + setArg(call_sat_vector_imm_vw_2934, 6, sat_vector_imm_vw_2934_arg6); + setArg(call_sat_vector_imm_vw_2934, 7, vm); + setArg(call_sat_vector_imm_vw_2934, 8, vd); + setArg(call_sat_vector_imm_vw_2934, 9, vs2); + setArg(call_sat_vector_imm_vw_2934, 10, (int64_t)(uint64_t)simm); + setArg(call_sat_vector_imm_vw_2934, 11, sat_vector_imm_vw_2934_arg11); + setRet(call_sat_vector_imm_vw_2934, 0, ret_val_sat_vector_imm_vw_2934); + } + cc.bind(label_merge); + } + auto tmp2936 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2936, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2936, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 678); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 679: VNCLIPU__WV */ + continuation_e __vnclipu__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnclipu.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIPU__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 679); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2937; + x86::Gp ret_val_get_sew_pow_2937 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2937, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2938 = get_reg(cc, 8, false); + mov(cc, tmp2938, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2938, ret_val_get_sew_pow_2937)), 8, false), ~ 1); + setArg(call_get_sew_pow_2937, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2937, 0, ret_val_get_sew_pow_2937); + InvokeNode* call_get_lmul_pow_2939; + x86::Gp ret_val_get_lmul_pow_2939 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2939, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2939; + setArg(call_get_lmul_pow_2939, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2939, 0, ret_val_get_lmul_pow_2939); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2940; + auto illegal_variable_width_2940_arg2 = SEW_widen; + auto illegal_variable_width_2940_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2940 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2940, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2941; + auto valid_reg_overlap_2941_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2941_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2941 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2941, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2940, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2941))); + setArg(call_illegal_variable_width_2940, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2940, 1, vd); + setArg(call_illegal_variable_width_2940, 2, vm); + setArg(call_illegal_variable_width_2940, 3, illegal_variable_width_2940_arg2); + setArg(call_illegal_variable_width_2940, 4, illegal_variable_width_2940_arg3); + setRet(call_illegal_variable_width_2940, 0, ret_val_illegal_variable_width_2940); + setArg(call_valid_reg_overlap_2941, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2941, 1, vs2); + setArg(call_valid_reg_overlap_2941, 2, vd); + setArg(call_valid_reg_overlap_2941, 3, valid_reg_overlap_2941_arg2); + setArg(call_valid_reg_overlap_2941, 4, valid_reg_overlap_2941_arg3); + setRet(call_valid_reg_overlap_2941, 0, ret_val_valid_reg_overlap_2941); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2943; + x86::Gp ret_val_sew_2943 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2943, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_vw_2942; + auto sat_vector_vector_vw_2942_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_vw_2942_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_vw_2942_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_vw_2942_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_vw_2942_arg11 = ret_val_sew_2943; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_vw_2942 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_vw_2942, &sat_vector_vector_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_vw_2942, 64, false) + , traits::vxsat); + setArg(call_sew_2943, 0, reinterpret_cast(this)); + setRet(call_sew_2943, 0, ret_val_sew_2943); + setArg(call_sat_vector_vector_vw_2942, 0, V); + setArg(call_sat_vector_vector_vw_2942, 1, 46); + setArg(call_sat_vector_vector_vw_2942, 2, 0); + setArg(call_sat_vector_vector_vw_2942, 3, sat_vector_vector_vw_2942_arg3); + setArg(call_sat_vector_vector_vw_2942, 4, sat_vector_vector_vw_2942_arg4); + setArg(call_sat_vector_vector_vw_2942, 5, sat_vector_vector_vw_2942_arg5); + setArg(call_sat_vector_vector_vw_2942, 6, sat_vector_vector_vw_2942_arg6); + setArg(call_sat_vector_vector_vw_2942, 7, vm); + setArg(call_sat_vector_vector_vw_2942, 8, vd); + setArg(call_sat_vector_vector_vw_2942, 9, vs2); + setArg(call_sat_vector_vector_vw_2942, 10, vs1); + setArg(call_sat_vector_vector_vw_2942, 11, sat_vector_vector_vw_2942_arg11); + setRet(call_sat_vector_vector_vw_2942, 0, ret_val_sat_vector_vector_vw_2942); + } + cc.bind(label_merge); + } + auto tmp2944 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2944, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2944, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 679); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 680: VNCLIPU__WX */ + continuation_e __vnclipu__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnclipu.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIPU__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 680); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2945; + x86::Gp ret_val_get_sew_pow_2945 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2945, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2946 = get_reg(cc, 8, false); + mov(cc, tmp2946, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2946, ret_val_get_sew_pow_2945)), 8, false), ~ 1); + setArg(call_get_sew_pow_2945, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2945, 0, ret_val_get_sew_pow_2945); + InvokeNode* call_get_lmul_pow_2947; + x86::Gp ret_val_get_lmul_pow_2947 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2947, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2947; + setArg(call_get_lmul_pow_2947, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2947, 0, ret_val_get_lmul_pow_2947); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2948; + auto illegal_variable_width_2948_arg2 = SEW_widen; + auto illegal_variable_width_2948_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2948 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2948, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2949; + auto valid_reg_overlap_2949_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2949_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2949 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2949, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2948, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2949))); + setArg(call_illegal_variable_width_2948, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2948, 1, vd); + setArg(call_illegal_variable_width_2948, 2, vm); + setArg(call_illegal_variable_width_2948, 3, illegal_variable_width_2948_arg2); + setArg(call_illegal_variable_width_2948, 4, illegal_variable_width_2948_arg3); + setRet(call_illegal_variable_width_2948, 0, ret_val_illegal_variable_width_2948); + setArg(call_valid_reg_overlap_2949, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2949, 1, vs2); + setArg(call_valid_reg_overlap_2949, 2, vd); + setArg(call_valid_reg_overlap_2949, 3, valid_reg_overlap_2949_arg2); + setArg(call_valid_reg_overlap_2949, 4, valid_reg_overlap_2949_arg3); + setRet(call_valid_reg_overlap_2949, 0, ret_val_valid_reg_overlap_2949); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2951; + x86::Gp ret_val_sew_2951 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2951, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2950; + auto sat_vector_imm_vw_2950_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2950_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2950_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2950_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2950_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); + auto sat_vector_imm_vw_2950_arg11 = ret_val_sew_2951; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_vw_2950 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2950, &sat_vector_imm_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_vw_2950, 64, false) + , traits::vxsat); + setArg(call_sew_2951, 0, reinterpret_cast(this)); + setRet(call_sew_2951, 0, ret_val_sew_2951); + setArg(call_sat_vector_imm_vw_2950, 0, V); + setArg(call_sat_vector_imm_vw_2950, 1, 46); + setArg(call_sat_vector_imm_vw_2950, 2, 4); + setArg(call_sat_vector_imm_vw_2950, 3, sat_vector_imm_vw_2950_arg3); + setArg(call_sat_vector_imm_vw_2950, 4, sat_vector_imm_vw_2950_arg4); + setArg(call_sat_vector_imm_vw_2950, 5, sat_vector_imm_vw_2950_arg5); + setArg(call_sat_vector_imm_vw_2950, 6, sat_vector_imm_vw_2950_arg6); + setArg(call_sat_vector_imm_vw_2950, 7, vm); + setArg(call_sat_vector_imm_vw_2950, 8, vd); + setArg(call_sat_vector_imm_vw_2950, 9, vs2); + setArg(call_sat_vector_imm_vw_2950, 10, sat_vector_imm_vw_2950_arg10); + setArg(call_sat_vector_imm_vw_2950, 11, sat_vector_imm_vw_2950_arg11); + setRet(call_sat_vector_imm_vw_2950, 0, ret_val_sat_vector_imm_vw_2950); + } + cc.bind(label_merge); + } + auto tmp2952 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2952, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2952, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 680); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 681: VNCLIP__WI */ + continuation_e __vnclip__wi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vnclip.wi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIP__WI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 681); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2953; + x86::Gp ret_val_get_sew_pow_2953 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2953, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2954 = get_reg(cc, 8, false); + mov(cc, tmp2954, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2954, ret_val_get_sew_pow_2953)), 8, false), ~ 1); + setArg(call_get_sew_pow_2953, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2953, 0, ret_val_get_sew_pow_2953); + InvokeNode* call_get_lmul_pow_2955; + x86::Gp ret_val_get_lmul_pow_2955 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2955, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2955; + setArg(call_get_lmul_pow_2955, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2955, 0, ret_val_get_lmul_pow_2955); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2956; + auto illegal_variable_width_2956_arg2 = SEW_widen; + auto illegal_variable_width_2956_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2956 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2956, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2957; + auto valid_reg_overlap_2957_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2957_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2957 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2957, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2956, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2957))); + setArg(call_illegal_variable_width_2956, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2956, 1, vd); + setArg(call_illegal_variable_width_2956, 2, vm); + setArg(call_illegal_variable_width_2956, 3, illegal_variable_width_2956_arg2); + setArg(call_illegal_variable_width_2956, 4, illegal_variable_width_2956_arg3); + setRet(call_illegal_variable_width_2956, 0, ret_val_illegal_variable_width_2956); + setArg(call_valid_reg_overlap_2957, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2957, 1, vs2); + setArg(call_valid_reg_overlap_2957, 2, vd); + setArg(call_valid_reg_overlap_2957, 3, valid_reg_overlap_2957_arg2); + setArg(call_valid_reg_overlap_2957, 4, valid_reg_overlap_2957_arg3); + setRet(call_valid_reg_overlap_2957, 0, ret_val_valid_reg_overlap_2957); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2959; + x86::Gp ret_val_sew_2959 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2959, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2958; + auto sat_vector_imm_vw_2958_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2958_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2958_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2958_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2958_arg11 = ret_val_sew_2959; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_vw_2958 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2958, &sat_vector_imm_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_vw_2958, 64, false) + , traits::vxsat); + setArg(call_sew_2959, 0, reinterpret_cast(this)); + setRet(call_sew_2959, 0, ret_val_sew_2959); + setArg(call_sat_vector_imm_vw_2958, 0, V); + setArg(call_sat_vector_imm_vw_2958, 1, 47); + setArg(call_sat_vector_imm_vw_2958, 2, 3); + setArg(call_sat_vector_imm_vw_2958, 3, sat_vector_imm_vw_2958_arg3); + setArg(call_sat_vector_imm_vw_2958, 4, sat_vector_imm_vw_2958_arg4); + setArg(call_sat_vector_imm_vw_2958, 5, sat_vector_imm_vw_2958_arg5); + setArg(call_sat_vector_imm_vw_2958, 6, sat_vector_imm_vw_2958_arg6); + setArg(call_sat_vector_imm_vw_2958, 7, vm); + setArg(call_sat_vector_imm_vw_2958, 8, vd); + setArg(call_sat_vector_imm_vw_2958, 9, vs2); + setArg(call_sat_vector_imm_vw_2958, 10, (int64_t)(uint64_t)simm); + setArg(call_sat_vector_imm_vw_2958, 11, sat_vector_imm_vw_2958_arg11); + setRet(call_sat_vector_imm_vw_2958, 0, ret_val_sat_vector_imm_vw_2958); + } + cc.bind(label_merge); + } + auto tmp2960 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2960, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2960, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 681); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 682: VNCLIP__WV */ + continuation_e __vnclip__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vnclip.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIP__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 682); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_2961; + x86::Gp ret_val_get_sew_pow_2961 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2961, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2962 = get_reg(cc, 8, false); + mov(cc, tmp2962, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2962, ret_val_get_sew_pow_2961)), 8, false), ~ 1); + setArg(call_get_sew_pow_2961, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2961, 0, ret_val_get_sew_pow_2961); + InvokeNode* call_get_lmul_pow_2963; + x86::Gp ret_val_get_lmul_pow_2963 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2963, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2963; + setArg(call_get_lmul_pow_2963, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2963, 0, ret_val_get_lmul_pow_2963); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2964; + auto illegal_variable_width_2964_arg2 = SEW_widen; + auto illegal_variable_width_2964_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2964 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2964, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2965; + auto valid_reg_overlap_2965_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2965_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2965 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2965, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2964, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2965))); + setArg(call_illegal_variable_width_2964, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2964, 1, vd); + setArg(call_illegal_variable_width_2964, 2, vm); + setArg(call_illegal_variable_width_2964, 3, illegal_variable_width_2964_arg2); + setArg(call_illegal_variable_width_2964, 4, illegal_variable_width_2964_arg3); + setRet(call_illegal_variable_width_2964, 0, ret_val_illegal_variable_width_2964); + setArg(call_valid_reg_overlap_2965, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2965, 1, vs2); + setArg(call_valid_reg_overlap_2965, 2, vd); + setArg(call_valid_reg_overlap_2965, 3, valid_reg_overlap_2965_arg2); + setArg(call_valid_reg_overlap_2965, 4, valid_reg_overlap_2965_arg3); + setRet(call_valid_reg_overlap_2965, 0, ret_val_valid_reg_overlap_2965); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2967; + x86::Gp ret_val_sew_2967 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2967, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_vw_2966; + auto sat_vector_vector_vw_2966_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_vw_2966_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_vw_2966_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_vw_2966_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_vw_2966_arg11 = ret_val_sew_2967; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_vector_vw_2966 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_vw_2966, &sat_vector_vector_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_vector_vw_2966, 64, false) + , traits::vxsat); + setArg(call_sew_2967, 0, reinterpret_cast(this)); + setRet(call_sew_2967, 0, ret_val_sew_2967); + setArg(call_sat_vector_vector_vw_2966, 0, V); + setArg(call_sat_vector_vector_vw_2966, 1, 47); + setArg(call_sat_vector_vector_vw_2966, 2, 0); + setArg(call_sat_vector_vector_vw_2966, 3, sat_vector_vector_vw_2966_arg3); + setArg(call_sat_vector_vector_vw_2966, 4, sat_vector_vector_vw_2966_arg4); + setArg(call_sat_vector_vector_vw_2966, 5, sat_vector_vector_vw_2966_arg5); + setArg(call_sat_vector_vector_vw_2966, 6, sat_vector_vector_vw_2966_arg6); + setArg(call_sat_vector_vector_vw_2966, 7, vm); + setArg(call_sat_vector_vector_vw_2966, 8, vd); + setArg(call_sat_vector_vector_vw_2966, 9, vs2); + setArg(call_sat_vector_vector_vw_2966, 10, vs1); + setArg(call_sat_vector_vector_vw_2966, 11, sat_vector_vector_vw_2966_arg11); + setRet(call_sat_vector_vector_vw_2966, 0, ret_val_sat_vector_vector_vw_2966); + } + cc.bind(label_merge); + } + auto tmp2968 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2968, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2968, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 682); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 683: VNCLIP__WX */ + continuation_e __vnclip__wx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vnclip.wx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VNCLIP__WX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 683); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(rs1>=static_cast(traits::RFS)){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_get_sew_pow_2969; + x86::Gp ret_val_get_sew_pow_2969 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2969, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2970 = get_reg(cc, 8, false); + mov(cc, tmp2970, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp2970, ret_val_get_sew_pow_2969)), 8, false), ~ 1); + setArg(call_get_sew_pow_2969, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2969, 0, ret_val_get_sew_pow_2969); + InvokeNode* call_get_lmul_pow_2971; + x86::Gp ret_val_get_lmul_pow_2971 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2971, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2971; + setArg(call_get_lmul_pow_2971, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2971, 0, ret_val_get_lmul_pow_2971); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_variable_width_2972; + auto illegal_variable_width_2972_arg2 = SEW_widen; + auto illegal_variable_width_2972_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2972 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2972, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2973; + auto valid_reg_overlap_2973_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2973_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2973 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2973, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2972, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2973))); + setArg(call_illegal_variable_width_2972, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2972, 1, vd); + setArg(call_illegal_variable_width_2972, 2, vm); + setArg(call_illegal_variable_width_2972, 3, illegal_variable_width_2972_arg2); + setArg(call_illegal_variable_width_2972, 4, illegal_variable_width_2972_arg3); + setRet(call_illegal_variable_width_2972, 0, ret_val_illegal_variable_width_2972); + setArg(call_valid_reg_overlap_2973, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2973, 1, vs2); + setArg(call_valid_reg_overlap_2973, 2, vd); + setArg(call_valid_reg_overlap_2973, 3, valid_reg_overlap_2973_arg2); + setArg(call_valid_reg_overlap_2973, 4, valid_reg_overlap_2973_arg3); + setRet(call_valid_reg_overlap_2973, 0, ret_val_valid_reg_overlap_2973); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2975; + x86::Gp ret_val_sew_2975 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2975, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2974; + auto sat_vector_imm_vw_2974_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2974_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2974_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2974_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2974_arg10 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); + auto sat_vector_imm_vw_2974_arg11 = ret_val_sew_2975; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_sat_vector_imm_vw_2974 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2974, &sat_vector_imm_vw, FuncSignature::build()); + write_reg_to_mem(jh, + gen_ext(cc, ret_val_sat_vector_imm_vw_2974, 64, false) + , traits::vxsat); + setArg(call_sew_2975, 0, reinterpret_cast(this)); + setRet(call_sew_2975, 0, ret_val_sew_2975); + setArg(call_sat_vector_imm_vw_2974, 0, V); + setArg(call_sat_vector_imm_vw_2974, 1, 47); + setArg(call_sat_vector_imm_vw_2974, 2, 4); + setArg(call_sat_vector_imm_vw_2974, 3, sat_vector_imm_vw_2974_arg3); + setArg(call_sat_vector_imm_vw_2974, 4, sat_vector_imm_vw_2974_arg4); + setArg(call_sat_vector_imm_vw_2974, 5, sat_vector_imm_vw_2974_arg5); + setArg(call_sat_vector_imm_vw_2974, 6, sat_vector_imm_vw_2974_arg6); + setArg(call_sat_vector_imm_vw_2974, 7, vm); + setArg(call_sat_vector_imm_vw_2974, 8, vd); + setArg(call_sat_vector_imm_vw_2974, 9, vs2); + setArg(call_sat_vector_imm_vw_2974, 10, sat_vector_imm_vw_2974_arg10); + setArg(call_sat_vector_imm_vw_2974, 11, sat_vector_imm_vw_2974_arg11); + setRet(call_sat_vector_imm_vw_2974, 0, ret_val_sat_vector_imm_vw_2974); + } + cc.bind(label_merge); + } + auto tmp2976 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2976, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2976, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 683); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 684: VREDSUM__VS */ + continuation_e __vredsum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredsum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 684); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2977; + x86::Gp ret_val_illegal_reduction_2977 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2977, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2977; + setArg(call_illegal_reduction_2977, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2977, 0, ret_val_illegal_reduction_2977); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2979; + x86::Gp ret_val_sew_2979 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2979, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2978; + auto vector_red_op_2978_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2978_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2978_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2978_arg10 = ret_val_sew_2979; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2978, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2979, 0, reinterpret_cast(this)); + setRet(call_sew_2979, 0, ret_val_sew_2979); + setArg(call_vector_red_op_2978, 0, V); + setArg(call_vector_red_op_2978, 1, 0); + setArg(call_vector_red_op_2978, 2, 2); + setArg(call_vector_red_op_2978, 3, vector_red_op_2978_arg3); + setArg(call_vector_red_op_2978, 4, vector_red_op_2978_arg4); + setArg(call_vector_red_op_2978, 5, vector_red_op_2978_arg5); + setArg(call_vector_red_op_2978, 6, vm); + setArg(call_vector_red_op_2978, 7, vd); + setArg(call_vector_red_op_2978, 8, vs2); + setArg(call_vector_red_op_2978, 9, vs1); + setArg(call_vector_red_op_2978, 10, vector_red_op_2978_arg10); + } + cc.bind(label_merge); + } + auto tmp2980 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2980, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2980, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 684); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 685: VREDMAXU__VS */ + continuation_e __vredmaxu__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmaxu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDMAXU__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 685); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2981; + x86::Gp ret_val_illegal_reduction_2981 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2981, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2981; + setArg(call_illegal_reduction_2981, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2981, 0, ret_val_illegal_reduction_2981); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2983; + x86::Gp ret_val_sew_2983 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2983, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2982; + auto vector_red_op_2982_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2982_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2982_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2982_arg10 = ret_val_sew_2983; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2982, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2983, 0, reinterpret_cast(this)); + setRet(call_sew_2983, 0, ret_val_sew_2983); + setArg(call_vector_red_op_2982, 0, V); + setArg(call_vector_red_op_2982, 1, 6); + setArg(call_vector_red_op_2982, 2, 2); + setArg(call_vector_red_op_2982, 3, vector_red_op_2982_arg3); + setArg(call_vector_red_op_2982, 4, vector_red_op_2982_arg4); + setArg(call_vector_red_op_2982, 5, vector_red_op_2982_arg5); + setArg(call_vector_red_op_2982, 6, vm); + setArg(call_vector_red_op_2982, 7, vd); + setArg(call_vector_red_op_2982, 8, vs2); + setArg(call_vector_red_op_2982, 9, vs1); + setArg(call_vector_red_op_2982, 10, vector_red_op_2982_arg10); + } + cc.bind(label_merge); + } + auto tmp2984 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2984, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2984, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 685); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 686: VREDMAX__VS */ + continuation_e __vredmax__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmax.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDMAX__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 686); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2985; + x86::Gp ret_val_illegal_reduction_2985 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2985, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2985; + setArg(call_illegal_reduction_2985, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2985, 0, ret_val_illegal_reduction_2985); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2987; + x86::Gp ret_val_sew_2987 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2987, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2986; + auto vector_red_op_2986_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2986_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2986_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2986_arg10 = ret_val_sew_2987; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2986, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2987, 0, reinterpret_cast(this)); + setRet(call_sew_2987, 0, ret_val_sew_2987); + setArg(call_vector_red_op_2986, 0, V); + setArg(call_vector_red_op_2986, 1, 7); + setArg(call_vector_red_op_2986, 2, 2); + setArg(call_vector_red_op_2986, 3, vector_red_op_2986_arg3); + setArg(call_vector_red_op_2986, 4, vector_red_op_2986_arg4); + setArg(call_vector_red_op_2986, 5, vector_red_op_2986_arg5); + setArg(call_vector_red_op_2986, 6, vm); + setArg(call_vector_red_op_2986, 7, vd); + setArg(call_vector_red_op_2986, 8, vs2); + setArg(call_vector_red_op_2986, 9, vs1); + setArg(call_vector_red_op_2986, 10, vector_red_op_2986_arg10); + } + cc.bind(label_merge); + } + auto tmp2988 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2988, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2988, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 686); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 687: VREDMINU__VS */ + continuation_e __vredminu__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredminu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDMINU__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 687); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2989; + x86::Gp ret_val_illegal_reduction_2989 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2989, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2989; + setArg(call_illegal_reduction_2989, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2989, 0, ret_val_illegal_reduction_2989); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2991; + x86::Gp ret_val_sew_2991 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2991, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2990; + auto vector_red_op_2990_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2990_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2990_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2990_arg10 = ret_val_sew_2991; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2990, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2991, 0, reinterpret_cast(this)); + setRet(call_sew_2991, 0, ret_val_sew_2991); + setArg(call_vector_red_op_2990, 0, V); + setArg(call_vector_red_op_2990, 1, 4); + setArg(call_vector_red_op_2990, 2, 2); + setArg(call_vector_red_op_2990, 3, vector_red_op_2990_arg3); + setArg(call_vector_red_op_2990, 4, vector_red_op_2990_arg4); + setArg(call_vector_red_op_2990, 5, vector_red_op_2990_arg5); + setArg(call_vector_red_op_2990, 6, vm); + setArg(call_vector_red_op_2990, 7, vd); + setArg(call_vector_red_op_2990, 8, vs2); + setArg(call_vector_red_op_2990, 9, vs1); + setArg(call_vector_red_op_2990, 10, vector_red_op_2990_arg10); + } + cc.bind(label_merge); + } + auto tmp2992 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2992, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2992, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 687); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 688: VREDMIN__VS */ + continuation_e __vredmin__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredmin.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDMIN__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 688); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2993; + x86::Gp ret_val_illegal_reduction_2993 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2993, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2993; + setArg(call_illegal_reduction_2993, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2993, 0, ret_val_illegal_reduction_2993); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2995; + x86::Gp ret_val_sew_2995 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2995, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2994; + auto vector_red_op_2994_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2994_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2994_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2994_arg10 = ret_val_sew_2995; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2994, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2995, 0, reinterpret_cast(this)); + setRet(call_sew_2995, 0, ret_val_sew_2995); + setArg(call_vector_red_op_2994, 0, V); + setArg(call_vector_red_op_2994, 1, 5); + setArg(call_vector_red_op_2994, 2, 2); + setArg(call_vector_red_op_2994, 3, vector_red_op_2994_arg3); + setArg(call_vector_red_op_2994, 4, vector_red_op_2994_arg4); + setArg(call_vector_red_op_2994, 5, vector_red_op_2994_arg5); + setArg(call_vector_red_op_2994, 6, vm); + setArg(call_vector_red_op_2994, 7, vd); + setArg(call_vector_red_op_2994, 8, vs2); + setArg(call_vector_red_op_2994, 9, vs1); + setArg(call_vector_red_op_2994, 10, vector_red_op_2994_arg10); + } + cc.bind(label_merge); + } + auto tmp2996 = get_reg_Gp(cc, 8, false); + mov(cc, tmp2996, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp2996, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 688); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 689: VREDAND__VS */ + continuation_e __vredand__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredand.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDAND__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 689); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_2997; + x86::Gp ret_val_illegal_reduction_2997 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2997, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2997; + setArg(call_illegal_reduction_2997, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2997, 0, ret_val_illegal_reduction_2997); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_2999; + x86::Gp ret_val_sew_2999 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2999, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2998; + auto vector_red_op_2998_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2998_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2998_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2998_arg10 = ret_val_sew_2999; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_2998, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2999, 0, reinterpret_cast(this)); + setRet(call_sew_2999, 0, ret_val_sew_2999); + setArg(call_vector_red_op_2998, 0, V); + setArg(call_vector_red_op_2998, 1, 1); + setArg(call_vector_red_op_2998, 2, 2); + setArg(call_vector_red_op_2998, 3, vector_red_op_2998_arg3); + setArg(call_vector_red_op_2998, 4, vector_red_op_2998_arg4); + setArg(call_vector_red_op_2998, 5, vector_red_op_2998_arg5); + setArg(call_vector_red_op_2998, 6, vm); + setArg(call_vector_red_op_2998, 7, vd); + setArg(call_vector_red_op_2998, 8, vs2); + setArg(call_vector_red_op_2998, 9, vs1); + setArg(call_vector_red_op_2998, 10, vector_red_op_2998_arg10); + } + cc.bind(label_merge); + } + auto tmp3000 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3000, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3000, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 689); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 690: VREDOR__VS */ + continuation_e __vredor__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredor.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDOR__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 690); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_3001; + x86::Gp ret_val_illegal_reduction_3001 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_3001, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_3001; + setArg(call_illegal_reduction_3001, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_3001, 0, ret_val_illegal_reduction_3001); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3003; + x86::Gp ret_val_sew_3003 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3003, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_3002; + auto vector_red_op_3002_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_3002_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_3002_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_3002_arg10 = ret_val_sew_3003; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_3002, &vector_red_op, FuncSignature::build()); + setArg(call_sew_3003, 0, reinterpret_cast(this)); + setRet(call_sew_3003, 0, ret_val_sew_3003); + setArg(call_vector_red_op_3002, 0, V); + setArg(call_vector_red_op_3002, 1, 2); + setArg(call_vector_red_op_3002, 2, 2); + setArg(call_vector_red_op_3002, 3, vector_red_op_3002_arg3); + setArg(call_vector_red_op_3002, 4, vector_red_op_3002_arg4); + setArg(call_vector_red_op_3002, 5, vector_red_op_3002_arg5); + setArg(call_vector_red_op_3002, 6, vm); + setArg(call_vector_red_op_3002, 7, vd); + setArg(call_vector_red_op_3002, 8, vs2); + setArg(call_vector_red_op_3002, 9, vs1); + setArg(call_vector_red_op_3002, 10, vector_red_op_3002_arg10); + } + cc.bind(label_merge); + } + auto tmp3004 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3004, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3004, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 690); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 691: VREDXOR__VS */ + continuation_e __vredxor__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vredxor.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VREDXOR__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 691); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_3005; + x86::Gp ret_val_illegal_reduction_3005 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_3005, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_3005; + setArg(call_illegal_reduction_3005, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_3005, 0, ret_val_illegal_reduction_3005); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3007; + x86::Gp ret_val_sew_3007 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3007, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_3006; + auto vector_red_op_3006_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_3006_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_3006_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_3006_arg10 = ret_val_sew_3007; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_op_3006, &vector_red_op, FuncSignature::build()); + setArg(call_sew_3007, 0, reinterpret_cast(this)); + setRet(call_sew_3007, 0, ret_val_sew_3007); + setArg(call_vector_red_op_3006, 0, V); + setArg(call_vector_red_op_3006, 1, 3); + setArg(call_vector_red_op_3006, 2, 2); + setArg(call_vector_red_op_3006, 3, vector_red_op_3006_arg3); + setArg(call_vector_red_op_3006, 4, vector_red_op_3006_arg4); + setArg(call_vector_red_op_3006, 5, vector_red_op_3006_arg5); + setArg(call_vector_red_op_3006, 6, vm); + setArg(call_vector_red_op_3006, 7, vd); + setArg(call_vector_red_op_3006, 8, vs2); + setArg(call_vector_red_op_3006, 9, vs1); + setArg(call_vector_red_op_3006, 10, vector_red_op_3006_arg10); + } + cc.bind(label_merge); + } + auto tmp3008 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3008, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3008, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 691); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 692: VWREDSUMU__VS */ + continuation_e __vwredsumu__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwredsumu.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWREDSUMU__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 692); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3009; + x86::Gp ret_val_get_sew_pow_3009 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3009, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3010 = get_reg(cc, 8, false); + mov(cc, tmp3010, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3010, ret_val_get_sew_pow_3009)), 8, false), ~ 1); + setArg(call_get_sew_pow_3009, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3009, 0, ret_val_get_sew_pow_3009); + InvokeNode* call_get_lmul_pow_3011; + x86::Gp ret_val_get_lmul_pow_3011 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3011, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3011; + setArg(call_get_lmul_pow_3011, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3011, 0, ret_val_get_lmul_pow_3011); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_widen_3012; + auto illegal_reduction_widen_3012_arg0 = SEW_widen; + auto illegal_reduction_widen_3012_arg1 = LMUL_pow_widen; + x86::Gp ret_val_illegal_reduction_widen_3012 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_widen_3012, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_widen_3012; + setArg(call_illegal_reduction_widen_3012, 0, reinterpret_cast(this)); + setArg(call_illegal_reduction_widen_3012, 1, illegal_reduction_widen_3012_arg0); + setArg(call_illegal_reduction_widen_3012, 2, illegal_reduction_widen_3012_arg1); + setRet(call_illegal_reduction_widen_3012, 0, ret_val_illegal_reduction_widen_3012); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3014; + x86::Gp ret_val_sew_3014 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3014, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_wv_3013; + auto vector_red_wv_3013_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_wv_3013_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_wv_3013_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_wv_3013_arg10 = ret_val_sew_3014; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_wv_3013, &vector_red_wv, FuncSignature::build()); + setArg(call_sew_3014, 0, reinterpret_cast(this)); + setRet(call_sew_3014, 0, ret_val_sew_3014); + setArg(call_vector_red_wv_3013, 0, V); + setArg(call_vector_red_wv_3013, 1, 48); + setArg(call_vector_red_wv_3013, 2, 0); + setArg(call_vector_red_wv_3013, 3, vector_red_wv_3013_arg3); + setArg(call_vector_red_wv_3013, 4, vector_red_wv_3013_arg4); + setArg(call_vector_red_wv_3013, 5, vector_red_wv_3013_arg5); + setArg(call_vector_red_wv_3013, 6, vm); + setArg(call_vector_red_wv_3013, 7, vd); + setArg(call_vector_red_wv_3013, 8, vs2); + setArg(call_vector_red_wv_3013, 9, vs1); + setArg(call_vector_red_wv_3013, 10, vector_red_wv_3013_arg10); + } + cc.bind(label_merge); + } + auto tmp3015 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3015, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3015, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 692); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 693: VWREDSUM__VS */ + continuation_e __vwredsum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vwredsum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VWREDSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 693); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3016; + x86::Gp ret_val_get_sew_pow_3016 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3016, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3017 = get_reg(cc, 8, false); + mov(cc, tmp3017, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3017, ret_val_get_sew_pow_3016)), 8, false), ~ 1); + setArg(call_get_sew_pow_3016, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3016, 0, ret_val_get_sew_pow_3016); + InvokeNode* call_get_lmul_pow_3018; + x86::Gp ret_val_get_lmul_pow_3018 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3018, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3018; + setArg(call_get_lmul_pow_3018, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3018, 0, ret_val_get_lmul_pow_3018); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_reduction_widen_3019; + auto illegal_reduction_widen_3019_arg0 = SEW_widen; + auto illegal_reduction_widen_3019_arg1 = LMUL_pow_widen; + x86::Gp ret_val_illegal_reduction_widen_3019 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_widen_3019, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_widen_3019; + setArg(call_illegal_reduction_widen_3019, 0, reinterpret_cast(this)); + setArg(call_illegal_reduction_widen_3019, 1, illegal_reduction_widen_3019_arg0); + setArg(call_illegal_reduction_widen_3019, 2, illegal_reduction_widen_3019_arg1); + setRet(call_illegal_reduction_widen_3019, 0, ret_val_illegal_reduction_widen_3019); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3021; + x86::Gp ret_val_sew_3021 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3021, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_wv_3020; + auto vector_red_wv_3020_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_wv_3020_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_wv_3020_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_wv_3020_arg10 = ret_val_sew_3021; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_red_wv_3020, &vector_red_wv, FuncSignature::build()); + setArg(call_sew_3021, 0, reinterpret_cast(this)); + setRet(call_sew_3021, 0, ret_val_sew_3021); + setArg(call_vector_red_wv_3020, 0, V); + setArg(call_vector_red_wv_3020, 1, 49); + setArg(call_vector_red_wv_3020, 2, 0); + setArg(call_vector_red_wv_3020, 3, vector_red_wv_3020_arg3); + setArg(call_vector_red_wv_3020, 4, vector_red_wv_3020_arg4); + setArg(call_vector_red_wv_3020, 5, vector_red_wv_3020_arg5); + setArg(call_vector_red_wv_3020, 6, vm); + setArg(call_vector_red_wv_3020, 7, vd); + setArg(call_vector_red_wv_3020, 8, vs2); + setArg(call_vector_red_wv_3020, 9, vs1); + setArg(call_vector_red_wv_3020, 10, vector_red_wv_3020_arg10); + } + cc.bind(label_merge); + } + auto tmp3022 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3022, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3022, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 693); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 694: VFREDOSUM__VS */ + continuation_e __vfredosum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredosum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFREDOSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 694); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3023; + x86::Gp ret_val_get_sew_pow_3023 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3023, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3024 = get_reg(cc, 8, false); + mov(cc, tmp3024, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3024, (ret_val_get_sew_pow_3023))), 8, false), ~ 1); + setArg(call_get_sew_pow_3023, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3023, 0, ret_val_get_sew_pow_3023); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_3025; + auto illegal_fp_reduction_3025_arg0 = SEW; + auto illegal_fp_reduction_3025_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3025 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3025, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3025; + setArg(call_illegal_fp_reduction_3025, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3025, 1, illegal_fp_reduction_3025_arg0); + setArg(call_illegal_fp_reduction_3025, 2, illegal_fp_reduction_3025_arg1); + setRet(call_illegal_fp_reduction_3025, 0, ret_val_illegal_fp_reduction_3025); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3027; + x86::Gp ret_val_sew_3027 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3027, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3026; + auto fp_vector_red_op_3026_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3026_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3026_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3026_arg10 = rm; + auto fp_vector_red_op_3026_arg11 = ret_val_sew_3027; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_op_3026, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3027, 0, reinterpret_cast(this)); + setRet(call_sew_3027, 0, ret_val_sew_3027); + setArg(call_fp_vector_red_op_3026, 0, V); + setArg(call_fp_vector_red_op_3026, 1, 3); + setArg(call_fp_vector_red_op_3026, 2, 1); + setArg(call_fp_vector_red_op_3026, 3, fp_vector_red_op_3026_arg3); + setArg(call_fp_vector_red_op_3026, 4, fp_vector_red_op_3026_arg4); + setArg(call_fp_vector_red_op_3026, 5, fp_vector_red_op_3026_arg5); + setArg(call_fp_vector_red_op_3026, 6, vm); + setArg(call_fp_vector_red_op_3026, 7, vd); + setArg(call_fp_vector_red_op_3026, 8, vs2); + setArg(call_fp_vector_red_op_3026, 9, vs1); + setArg(call_fp_vector_red_op_3026, 10, fp_vector_red_op_3026_arg10); + setArg(call_fp_vector_red_op_3026, 11, fp_vector_red_op_3026_arg11); + InvokeNode* call_fget_flags_3028; + x86::Gp ret_val_fget_flags_3028 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3028, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3028; + setRet(call_fget_flags_3028, 0, ret_val_fget_flags_3028); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3029 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3029, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3029, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 694); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 695: VFREDUSUM__VS */ + continuation_e __vfredusum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredusum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFREDUSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 695); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3030; + x86::Gp ret_val_get_sew_pow_3030 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3030, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3031 = get_reg(cc, 8, false); + mov(cc, tmp3031, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3031, (ret_val_get_sew_pow_3030))), 8, false), ~ 1); + setArg(call_get_sew_pow_3030, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3030, 0, ret_val_get_sew_pow_3030); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_3032; + auto illegal_fp_reduction_3032_arg0 = SEW; + auto illegal_fp_reduction_3032_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3032 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3032, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3032; + setArg(call_illegal_fp_reduction_3032, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3032, 1, illegal_fp_reduction_3032_arg0); + setArg(call_illegal_fp_reduction_3032, 2, illegal_fp_reduction_3032_arg1); + setRet(call_illegal_fp_reduction_3032, 0, ret_val_illegal_fp_reduction_3032); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3034; + x86::Gp ret_val_sew_3034 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3034, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3033; + auto fp_vector_red_op_3033_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3033_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3033_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3033_arg10 = rm; + auto fp_vector_red_op_3033_arg11 = ret_val_sew_3034; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_op_3033, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3034, 0, reinterpret_cast(this)); + setRet(call_sew_3034, 0, ret_val_sew_3034); + setArg(call_fp_vector_red_op_3033, 0, V); + setArg(call_fp_vector_red_op_3033, 1, 1); + setArg(call_fp_vector_red_op_3033, 2, 1); + setArg(call_fp_vector_red_op_3033, 3, fp_vector_red_op_3033_arg3); + setArg(call_fp_vector_red_op_3033, 4, fp_vector_red_op_3033_arg4); + setArg(call_fp_vector_red_op_3033, 5, fp_vector_red_op_3033_arg5); + setArg(call_fp_vector_red_op_3033, 6, vm); + setArg(call_fp_vector_red_op_3033, 7, vd); + setArg(call_fp_vector_red_op_3033, 8, vs2); + setArg(call_fp_vector_red_op_3033, 9, vs1); + setArg(call_fp_vector_red_op_3033, 10, fp_vector_red_op_3033_arg10); + setArg(call_fp_vector_red_op_3033, 11, fp_vector_red_op_3033_arg11); + InvokeNode* call_fget_flags_3035; + x86::Gp ret_val_fget_flags_3035 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3035, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3035; + setRet(call_fget_flags_3035, 0, ret_val_fget_flags_3035); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3036 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3036, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3036, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 695); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 696: VFREDMAX__VS */ + continuation_e __vfredmax__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredmax.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFREDMAX__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 696); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3037; + x86::Gp ret_val_get_sew_pow_3037 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3037, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3038 = get_reg(cc, 8, false); + mov(cc, tmp3038, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3038, (ret_val_get_sew_pow_3037))), 8, false), ~ 1); + setArg(call_get_sew_pow_3037, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3037, 0, ret_val_get_sew_pow_3037); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_3039; + auto illegal_fp_reduction_3039_arg0 = SEW; + auto illegal_fp_reduction_3039_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3039 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3039, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3039; + setArg(call_illegal_fp_reduction_3039, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3039, 1, illegal_fp_reduction_3039_arg0); + setArg(call_illegal_fp_reduction_3039, 2, illegal_fp_reduction_3039_arg1); + setRet(call_illegal_fp_reduction_3039, 0, ret_val_illegal_fp_reduction_3039); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3041; + x86::Gp ret_val_sew_3041 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3041, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3040; + auto fp_vector_red_op_3040_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3040_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3040_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3040_arg10 = rm; + auto fp_vector_red_op_3040_arg11 = ret_val_sew_3041; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_op_3040, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3041, 0, reinterpret_cast(this)); + setRet(call_sew_3041, 0, ret_val_sew_3041); + setArg(call_fp_vector_red_op_3040, 0, V); + setArg(call_fp_vector_red_op_3040, 1, 7); + setArg(call_fp_vector_red_op_3040, 2, 1); + setArg(call_fp_vector_red_op_3040, 3, fp_vector_red_op_3040_arg3); + setArg(call_fp_vector_red_op_3040, 4, fp_vector_red_op_3040_arg4); + setArg(call_fp_vector_red_op_3040, 5, fp_vector_red_op_3040_arg5); + setArg(call_fp_vector_red_op_3040, 6, vm); + setArg(call_fp_vector_red_op_3040, 7, vd); + setArg(call_fp_vector_red_op_3040, 8, vs2); + setArg(call_fp_vector_red_op_3040, 9, vs1); + setArg(call_fp_vector_red_op_3040, 10, fp_vector_red_op_3040_arg10); + setArg(call_fp_vector_red_op_3040, 11, fp_vector_red_op_3040_arg11); + } + cc.bind(label_merge); + } + auto tmp3042 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3042, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3042, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 696); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 697: VFREDMIN__VS */ + continuation_e __vfredmin__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfredmin.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFREDMIN__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 697); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3043; + x86::Gp ret_val_get_sew_pow_3043 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3043, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3044 = get_reg(cc, 8, false); + mov(cc, tmp3044, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3044, (ret_val_get_sew_pow_3043))), 8, false), ~ 1); + setArg(call_get_sew_pow_3043, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3043, 0, ret_val_get_sew_pow_3043); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_3045; + auto illegal_fp_reduction_3045_arg0 = SEW; + auto illegal_fp_reduction_3045_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3045 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3045, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3045; + setArg(call_illegal_fp_reduction_3045, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3045, 1, illegal_fp_reduction_3045_arg0); + setArg(call_illegal_fp_reduction_3045, 2, illegal_fp_reduction_3045_arg1); + setRet(call_illegal_fp_reduction_3045, 0, ret_val_illegal_fp_reduction_3045); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3047; + x86::Gp ret_val_sew_3047 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3047, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3046; + auto fp_vector_red_op_3046_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3046_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3046_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3046_arg10 = rm; + auto fp_vector_red_op_3046_arg11 = ret_val_sew_3047; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_op_3046, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3047, 0, reinterpret_cast(this)); + setRet(call_sew_3047, 0, ret_val_sew_3047); + setArg(call_fp_vector_red_op_3046, 0, V); + setArg(call_fp_vector_red_op_3046, 1, 5); + setArg(call_fp_vector_red_op_3046, 2, 1); + setArg(call_fp_vector_red_op_3046, 3, fp_vector_red_op_3046_arg3); + setArg(call_fp_vector_red_op_3046, 4, fp_vector_red_op_3046_arg4); + setArg(call_fp_vector_red_op_3046, 5, fp_vector_red_op_3046_arg5); + setArg(call_fp_vector_red_op_3046, 6, vm); + setArg(call_fp_vector_red_op_3046, 7, vd); + setArg(call_fp_vector_red_op_3046, 8, vs2); + setArg(call_fp_vector_red_op_3046, 9, vs1); + setArg(call_fp_vector_red_op_3046, 10, fp_vector_red_op_3046_arg10); + setArg(call_fp_vector_red_op_3046, 11, fp_vector_red_op_3046_arg11); + } + cc.bind(label_merge); + } + auto tmp3048 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3048, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3048, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 697); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 698: VFWREDOSUM__VS */ + continuation_e __vfwredosum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwredosum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWREDOSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 698); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3049; + x86::Gp ret_val_get_sew_pow_3049 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3049, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3050 = get_reg(cc, 8, false); + mov(cc, tmp3050, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3050, (ret_val_get_sew_pow_3049))), 8, false), ~ 1); + setArg(call_get_sew_pow_3049, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3049, 0, ret_val_get_sew_pow_3049); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_3051; + auto illegal_fp_reduction_3051_arg0 = SEW; + auto illegal_fp_reduction_3051_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3051 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3051, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3051; + setArg(call_illegal_fp_reduction_3051, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3051, 1, illegal_fp_reduction_3051_arg0); + setArg(call_illegal_fp_reduction_3051, 2, illegal_fp_reduction_3051_arg1); + setRet(call_illegal_fp_reduction_3051, 0, ret_val_illegal_fp_reduction_3051); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3053; + x86::Gp ret_val_sew_3053 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3053, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_wv_3052; + auto fp_vector_red_wv_3052_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_wv_3052_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_wv_3052_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_wv_3052_arg10 = rm; + auto fp_vector_red_wv_3052_arg11 = ret_val_sew_3053; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_wv_3052, &fp_vector_red_wv, FuncSignature::build()); + setArg(call_sew_3053, 0, reinterpret_cast(this)); + setRet(call_sew_3053, 0, ret_val_sew_3053); + setArg(call_fp_vector_red_wv_3052, 0, V); + setArg(call_fp_vector_red_wv_3052, 1, 51); + setArg(call_fp_vector_red_wv_3052, 2, 1); + setArg(call_fp_vector_red_wv_3052, 3, fp_vector_red_wv_3052_arg3); + setArg(call_fp_vector_red_wv_3052, 4, fp_vector_red_wv_3052_arg4); + setArg(call_fp_vector_red_wv_3052, 5, fp_vector_red_wv_3052_arg5); + setArg(call_fp_vector_red_wv_3052, 6, vm); + setArg(call_fp_vector_red_wv_3052, 7, vd); + setArg(call_fp_vector_red_wv_3052, 8, vs2); + setArg(call_fp_vector_red_wv_3052, 9, vs1); + setArg(call_fp_vector_red_wv_3052, 10, fp_vector_red_wv_3052_arg10); + setArg(call_fp_vector_red_wv_3052, 11, fp_vector_red_wv_3052_arg11); + InvokeNode* call_fget_flags_3054; + x86::Gp ret_val_fget_flags_3054 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3054, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3054; + setRet(call_fget_flags_3054, 0, ret_val_fget_flags_3054); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3055 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3055, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3055, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 698); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 699: VFWREDUSUM__VS */ + continuation_e __vfwredusum__vs(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwredusum.vs"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWREDUSUM__VS_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 699); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3056; + x86::Gp ret_val_get_sew_pow_3056 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3056, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3057 = get_reg(cc, 8, false); + mov(cc, tmp3057, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3057, (ret_val_get_sew_pow_3056))), 8, false), ~ 1); + setArg(call_get_sew_pow_3056, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3056, 0, ret_val_get_sew_pow_3056); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_reduction_3058; + auto illegal_fp_reduction_3058_arg0 = SEW; + auto illegal_fp_reduction_3058_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3058 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3058, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3058; + setArg(call_illegal_fp_reduction_3058, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3058, 1, illegal_fp_reduction_3058_arg0); + setArg(call_illegal_fp_reduction_3058, 2, illegal_fp_reduction_3058_arg1); + setRet(call_illegal_fp_reduction_3058, 0, ret_val_illegal_fp_reduction_3058); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3060; + x86::Gp ret_val_sew_3060 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3060, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_wv_3059; + auto fp_vector_red_wv_3059_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_wv_3059_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_wv_3059_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_wv_3059_arg10 = rm; + auto fp_vector_red_wv_3059_arg11 = ret_val_sew_3060; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_red_wv_3059, &fp_vector_red_wv, FuncSignature::build()); + setArg(call_sew_3060, 0, reinterpret_cast(this)); + setRet(call_sew_3060, 0, ret_val_sew_3060); + setArg(call_fp_vector_red_wv_3059, 0, V); + setArg(call_fp_vector_red_wv_3059, 1, 49); + setArg(call_fp_vector_red_wv_3059, 2, 1); + setArg(call_fp_vector_red_wv_3059, 3, fp_vector_red_wv_3059_arg3); + setArg(call_fp_vector_red_wv_3059, 4, fp_vector_red_wv_3059_arg4); + setArg(call_fp_vector_red_wv_3059, 5, fp_vector_red_wv_3059_arg5); + setArg(call_fp_vector_red_wv_3059, 6, vm); + setArg(call_fp_vector_red_wv_3059, 7, vd); + setArg(call_fp_vector_red_wv_3059, 8, vs2); + setArg(call_fp_vector_red_wv_3059, 9, vs1); + setArg(call_fp_vector_red_wv_3059, 10, fp_vector_red_wv_3059_arg10); + setArg(call_fp_vector_red_wv_3059, 11, fp_vector_red_wv_3059_arg11); + InvokeNode* call_fget_flags_3061; + x86::Gp ret_val_fget_flags_3061 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3061, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3061; + setRet(call_fget_flags_3061, 0, ret_val_fget_flags_3061); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3062 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3062, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3062, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 699); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 700: VMAND__MM */ + continuation_e __vmand__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmand.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMAND__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 700); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3063; + x86::Gp ret_val_illegal_vd_unmasked_3063 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3063, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3063; + setArg(call_illegal_vd_unmasked_3063, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3063, 0, ret_val_illegal_vd_unmasked_3063); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3064; + auto mask_mask_op_3064_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3064_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3064, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3064, 0, V); + setArg(call_mask_mask_op_3064, 1, 25); + setArg(call_mask_mask_op_3064, 2, 2); + setArg(call_mask_mask_op_3064, 3, mask_mask_op_3064_arg3); + setArg(call_mask_mask_op_3064, 4, mask_mask_op_3064_arg4); + setArg(call_mask_mask_op_3064, 5, vd); + setArg(call_mask_mask_op_3064, 6, vs2); + setArg(call_mask_mask_op_3064, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3065 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3065, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3065, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 700); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 701: VMNAND__MM */ + continuation_e __vmnand__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmnand.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMNAND__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 701); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3066; + x86::Gp ret_val_illegal_vd_unmasked_3066 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3066, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3066; + setArg(call_illegal_vd_unmasked_3066, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3066, 0, ret_val_illegal_vd_unmasked_3066); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3067; + auto mask_mask_op_3067_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3067_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3067, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3067, 0, V); + setArg(call_mask_mask_op_3067, 1, 29); + setArg(call_mask_mask_op_3067, 2, 2); + setArg(call_mask_mask_op_3067, 3, mask_mask_op_3067_arg3); + setArg(call_mask_mask_op_3067, 4, mask_mask_op_3067_arg4); + setArg(call_mask_mask_op_3067, 5, vd); + setArg(call_mask_mask_op_3067, 6, vs2); + setArg(call_mask_mask_op_3067, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3068 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3068, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3068, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 701); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 702: VMANDN__MM */ + continuation_e __vmandn__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmandn.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMANDN__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 702); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3069; + x86::Gp ret_val_illegal_vd_unmasked_3069 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3069, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3069; + setArg(call_illegal_vd_unmasked_3069, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3069, 0, ret_val_illegal_vd_unmasked_3069); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3070; + auto mask_mask_op_3070_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3070_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3070, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3070, 0, V); + setArg(call_mask_mask_op_3070, 1, 24); + setArg(call_mask_mask_op_3070, 2, 2); + setArg(call_mask_mask_op_3070, 3, mask_mask_op_3070_arg3); + setArg(call_mask_mask_op_3070, 4, mask_mask_op_3070_arg4); + setArg(call_mask_mask_op_3070, 5, vd); + setArg(call_mask_mask_op_3070, 6, vs2); + setArg(call_mask_mask_op_3070, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3071 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3071, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3071, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 702); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 703: VMXOR__MM */ + continuation_e __vmxor__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmxor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMXOR__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 703); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3072; + x86::Gp ret_val_illegal_vd_unmasked_3072 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3072, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3072; + setArg(call_illegal_vd_unmasked_3072, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3072, 0, ret_val_illegal_vd_unmasked_3072); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3073; + auto mask_mask_op_3073_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3073_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3073, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3073, 0, V); + setArg(call_mask_mask_op_3073, 1, 27); + setArg(call_mask_mask_op_3073, 2, 2); + setArg(call_mask_mask_op_3073, 3, mask_mask_op_3073_arg3); + setArg(call_mask_mask_op_3073, 4, mask_mask_op_3073_arg4); + setArg(call_mask_mask_op_3073, 5, vd); + setArg(call_mask_mask_op_3073, 6, vs2); + setArg(call_mask_mask_op_3073, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3074 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3074, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3074, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 703); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 704: VMOR__MM */ + continuation_e __vmor__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMOR__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 704); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3075; + x86::Gp ret_val_illegal_vd_unmasked_3075 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3075, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3075; + setArg(call_illegal_vd_unmasked_3075, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3075, 0, ret_val_illegal_vd_unmasked_3075); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3076; + auto mask_mask_op_3076_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3076_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3076, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3076, 0, V); + setArg(call_mask_mask_op_3076, 1, 26); + setArg(call_mask_mask_op_3076, 2, 2); + setArg(call_mask_mask_op_3076, 3, mask_mask_op_3076_arg3); + setArg(call_mask_mask_op_3076, 4, mask_mask_op_3076_arg4); + setArg(call_mask_mask_op_3076, 5, vd); + setArg(call_mask_mask_op_3076, 6, vs2); + setArg(call_mask_mask_op_3076, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3077 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3077, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3077, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 704); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 705: VMNOR__MM */ + continuation_e __vmnor__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmnor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMNOR__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 705); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3078; + x86::Gp ret_val_illegal_vd_unmasked_3078 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3078, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3078; + setArg(call_illegal_vd_unmasked_3078, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3078, 0, ret_val_illegal_vd_unmasked_3078); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3079; + auto mask_mask_op_3079_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3079_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3079, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3079, 0, V); + setArg(call_mask_mask_op_3079, 1, 30); + setArg(call_mask_mask_op_3079, 2, 2); + setArg(call_mask_mask_op_3079, 3, mask_mask_op_3079_arg3); + setArg(call_mask_mask_op_3079, 4, mask_mask_op_3079_arg4); + setArg(call_mask_mask_op_3079, 5, vd); + setArg(call_mask_mask_op_3079, 6, vs2); + setArg(call_mask_mask_op_3079, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3080 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3080, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3080, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 705); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 706: VMORN__MM */ + continuation_e __vmorn__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmorn.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMORN__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 706); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3081; + x86::Gp ret_val_illegal_vd_unmasked_3081 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3081, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3081; + setArg(call_illegal_vd_unmasked_3081, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3081, 0, ret_val_illegal_vd_unmasked_3081); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3082; + auto mask_mask_op_3082_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3082_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3082, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3082, 0, V); + setArg(call_mask_mask_op_3082, 1, 28); + setArg(call_mask_mask_op_3082, 2, 2); + setArg(call_mask_mask_op_3082, 3, mask_mask_op_3082_arg3); + setArg(call_mask_mask_op_3082, 4, mask_mask_op_3082_arg4); + setArg(call_mask_mask_op_3082, 5, vd); + setArg(call_mask_mask_op_3082, 6, vs2); + setArg(call_mask_mask_op_3082, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3083 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3083, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3083, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 706); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 707: VMXNOR__MM */ + continuation_e __vmxnor__mm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vmxnor.mm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMXNOR__MM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 707); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3084; + x86::Gp ret_val_illegal_vd_unmasked_3084 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3084, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3084; + setArg(call_illegal_vd_unmasked_3084, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3084, 0, ret_val_illegal_vd_unmasked_3084); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_mask_mask_op_3085; + auto mask_mask_op_3085_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3085_arg4 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_mask_op_3085, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3085, 0, V); + setArg(call_mask_mask_op_3085, 1, 31); + setArg(call_mask_mask_op_3085, 2, 2); + setArg(call_mask_mask_op_3085, 3, mask_mask_op_3085_arg3); + setArg(call_mask_mask_op_3085, 4, mask_mask_op_3085_arg4); + setArg(call_mask_mask_op_3085, 5, vd); + setArg(call_mask_mask_op_3085, 6, vs2); + setArg(call_mask_mask_op_3085, 7, vs1); + } + cc.bind(label_merge); + } + auto tmp3086 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3086, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3086, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 707); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 708: VCPOP__M */ + continuation_e __vcpop__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}, {vm},", fmt::arg("mnemonic", "vcpop.m"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VCPOP__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 708); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3087; + x86::Gp ret_val_illegal_vd_unmasked_3087 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3087, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3088 = get_reg(cc, 8, false); + mov(cc, tmp3088, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3088, ret_val_illegal_vd_unmasked_3087), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); + setArg(call_illegal_vd_unmasked_3087, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3087, 0, ret_val_illegal_vd_unmasked_3087); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + InvokeNode* call_vcpop_3089; + auto vcpop_3089_arg1 = load_reg_from_mem(jh, traits::vl); + auto vcpop_3089_arg2 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vcpop_3089 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vcpop_3089, &vcpop, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + ret_val_vcpop_3089); + setArg(call_vcpop_3089, 0, V); + setArg(call_vcpop_3089, 1, vcpop_3089_arg1); + setArg(call_vcpop_3089, 2, vcpop_3089_arg2); + setArg(call_vcpop_3089, 3, vm); + setArg(call_vcpop_3089, 4, vs2); + setRet(call_vcpop_3089, 0, ret_val_vcpop_3089); + auto tmp3090 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3090, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3090, 64, false) + , traits::vstart); + } + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 708); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 709: VFIRST__M */ + continuation_e __vfirst__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}, {vm},", fmt::arg("mnemonic", "vfirst.m"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFIRST__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 709); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3091; + x86::Gp ret_val_illegal_vd_unmasked_3091 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3091, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3092 = get_reg(cc, 8, false); + mov(cc, tmp3092, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3092, ret_val_illegal_vd_unmasked_3091), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); + setArg(call_illegal_vd_unmasked_3091, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3091, 0, ret_val_illegal_vd_unmasked_3091); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + InvokeNode* call_vfirst_3093; + auto vfirst_3093_arg1 = load_reg_from_mem(jh, traits::vl); + auto vfirst_3093_arg2 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_vfirst_3093 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vfirst_3093, &vfirst, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + ret_val_vfirst_3093); + setArg(call_vfirst_3093, 0, V); + setArg(call_vfirst_3093, 1, vfirst_3093_arg1); + setArg(call_vfirst_3093, 2, vfirst_3093_arg2); + setArg(call_vfirst_3093, 3, vm); + setArg(call_vfirst_3093, 4, vs2); + setRet(call_vfirst_3093, 0, ret_val_vfirst_3093); + auto tmp3094 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3094, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3094, 64, false) + , traits::vstart); + } + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 709); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 710: VMSBF__M */ + continuation_e __vmsbf__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsbf.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSBF__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 710); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3095; + x86::Gp ret_val_illegal_vd_unmasked_3095 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3095, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3095, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3095, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3095, 0, ret_val_illegal_vd_unmasked_3095); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_mask_set_op_3096; + auto mask_set_op_3096_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3096_arg3 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_set_op_3096, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3096, 0, V); + setArg(call_mask_set_op_3096, 1, 1); + setArg(call_mask_set_op_3096, 2, mask_set_op_3096_arg2); + setArg(call_mask_set_op_3096, 3, mask_set_op_3096_arg3); + setArg(call_mask_set_op_3096, 4, vm); + setArg(call_mask_set_op_3096, 5, vd); + setArg(call_mask_set_op_3096, 6, vs2); + auto tmp3097 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3097, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3097, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 710); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 711: VMSIF__M */ + continuation_e __vmsif__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsif.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSIF__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 711); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3098; + x86::Gp ret_val_illegal_vd_unmasked_3098 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3098, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3098, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3098, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3098, 0, ret_val_illegal_vd_unmasked_3098); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_mask_set_op_3099; + auto mask_set_op_3099_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3099_arg3 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_set_op_3099, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3099, 0, V); + setArg(call_mask_set_op_3099, 1, 3); + setArg(call_mask_set_op_3099, 2, mask_set_op_3099_arg2); + setArg(call_mask_set_op_3099, 3, mask_set_op_3099_arg3); + setArg(call_mask_set_op_3099, 4, vm); + setArg(call_mask_set_op_3099, 5, vd); + setArg(call_mask_set_op_3099, 6, vs2); + auto tmp3100 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3100, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3100, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 711); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 712: VMSOF__M */ + continuation_e __vmsof__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vmsof.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMSOF__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 712); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3101; + x86::Gp ret_val_illegal_vd_unmasked_3101 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3101, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3101, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3101, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3101, 0, ret_val_illegal_vd_unmasked_3101); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_mask_set_op_3102; + auto mask_set_op_3102_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3102_arg3 = load_reg_from_mem(jh, traits::vstart); + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_set_op_3102, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3102, 0, V); + setArg(call_mask_set_op_3102, 1, 2); + setArg(call_mask_set_op_3102, 2, mask_set_op_3102_arg2); + setArg(call_mask_set_op_3102, 3, mask_set_op_3102_arg3); + setArg(call_mask_set_op_3102, 4, vm); + setArg(call_mask_set_op_3102, 5, vd); + setArg(call_mask_set_op_3102, 6, vs2); + auto tmp3103 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3103, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3103, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 712); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 713: VIOTA__M */ + continuation_e __viota__m(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "viota.m"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VIOTA__M_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 713); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3104; + x86::Gp ret_val_illegal_vd_unmasked_3104 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3104, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3104, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3104, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3104, 0, ret_val_illegal_vd_unmasked_3104); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3106; + x86::Gp ret_val_sew_3106 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3106, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_viota_3105; + auto viota_3105_arg1 = load_reg_from_mem(jh, traits::vl); + auto viota_3105_arg2 = load_reg_from_mem(jh, traits::vstart); + auto viota_3105_arg3 = load_reg_from_mem(jh, traits::vtype); + auto viota_3105_arg7 = ret_val_sew_3106; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_viota_3105, &viota, FuncSignature::build()); + setArg(call_sew_3106, 0, reinterpret_cast(this)); + setRet(call_sew_3106, 0, ret_val_sew_3106); + setArg(call_viota_3105, 0, V); + setArg(call_viota_3105, 1, viota_3105_arg1); + setArg(call_viota_3105, 2, viota_3105_arg2); + setArg(call_viota_3105, 3, viota_3105_arg3); + setArg(call_viota_3105, 4, vm); + setArg(call_viota_3105, 5, vd); + setArg(call_viota_3105, 6, vs2); + setArg(call_viota_3105, 7, viota_3105_arg7); + auto tmp3107 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3107, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3107, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 713); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 714: VID__V */ + continuation_e __vid__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vm},", fmt::arg("mnemonic", "vid.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VID__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 714); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3108; + x86::Gp ret_val_illegal_normal_3108 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3108, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_3108; + setArg(call_illegal_normal_3108, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3108, 1, vd); + setArg(call_illegal_normal_3108, 2, vm); + setRet(call_illegal_normal_3108, 0, ret_val_illegal_normal_3108); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3110; + x86::Gp ret_val_sew_3110 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3110, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vid_3109; + auto vid_3109_arg1 = load_reg_from_mem(jh, traits::vl); + auto vid_3109_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vid_3109_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vid_3109_arg6 = ret_val_sew_3110; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vid_3109, &vid, FuncSignature::build()); + setArg(call_sew_3110, 0, reinterpret_cast(this)); + setRet(call_sew_3110, 0, ret_val_sew_3110); + setArg(call_vid_3109, 0, V); + setArg(call_vid_3109, 1, vid_3109_arg1); + setArg(call_vid_3109, 2, vid_3109_arg2); + setArg(call_vid_3109, 3, vid_3109_arg3); + setArg(call_vid_3109, 4, vm); + setArg(call_vid_3109, 5, vd); + setArg(call_vid_3109, 6, vid_3109_arg6); + auto tmp3111 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3111, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3111, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 714); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 715: VMV__S__X */ + continuation_e __vmv__s__x(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vmv.s.x"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV__S__X_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 715); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3112; + x86::Gp ret_val_illegal_vd_unmasked_3112 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3112, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3113 = get_reg(cc, 8, false); + mov(cc, tmp3113, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3113, ret_val_illegal_vd_unmasked_3112); + setArg(call_illegal_vd_unmasked_3112, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3112, 0, ret_val_illegal_vd_unmasked_3112); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3115; + x86::Gp ret_val_sew_3115 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3115, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_to_vector_3114; + auto scalar_to_vector_3114_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_to_vector_3114_arg3 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); + auto scalar_to_vector_3114_arg4 = ret_val_sew_3115; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_scalar_to_vector_3114, &scalar_to_vector, FuncSignature::build()); + setArg(call_sew_3115, 0, reinterpret_cast(this)); + setRet(call_sew_3115, 0, ret_val_sew_3115); + setArg(call_scalar_to_vector_3114, 0, V); + setArg(call_scalar_to_vector_3114, 1, scalar_to_vector_3114_arg1); + setArg(call_scalar_to_vector_3114, 2, vd); + setArg(call_scalar_to_vector_3114, 3, scalar_to_vector_3114_arg3); + setArg(call_scalar_to_vector_3114, 4, scalar_to_vector_3114_arg4); + } + cc.bind(label_merge); + } + auto tmp3116 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3116, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3116, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 715); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 716: VMV__X__S */ + continuation_e __vmv__x__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}", fmt::arg("mnemonic", "vmv.x.s"), + fmt::arg("rd", name(rd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV__X__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 716); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3117; + x86::Gp ret_val_illegal_vd_unmasked_3117 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3117, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3118 = get_reg(cc, 8, false); + mov(cc, tmp3118, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3118, ret_val_illegal_vd_unmasked_3117); + setArg(call_illegal_vd_unmasked_3117, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3117, 0, ret_val_illegal_vd_unmasked_3117); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + if(rd!=0){ + InvokeNode* call_sew_3120; + x86::Gp ret_val_sew_3120 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3120, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_from_vector_3119; + auto scalar_from_vector_3119_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_from_vector_3119_arg3 = ret_val_sew_3120; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_scalar_from_vector_3119 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_scalar_from_vector_3119, &scalar_from_vector, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::X0+ rd), + ret_val_scalar_from_vector_3119); + setArg(call_sew_3120, 0, reinterpret_cast(this)); + setRet(call_sew_3120, 0, ret_val_sew_3120); + setArg(call_scalar_from_vector_3119, 0, V); + setArg(call_scalar_from_vector_3119, 1, scalar_from_vector_3119_arg1); + setArg(call_scalar_from_vector_3119, 2, vs2); + setArg(call_scalar_from_vector_3119, 3, scalar_from_vector_3119_arg3); + setRet(call_scalar_from_vector_3119, 0, ret_val_scalar_from_vector_3119); + } + auto tmp3121 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3121, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3121, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 716); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 717: VSLIDEUP__VI */ + continuation_e __vslideup__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vslideup.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDEUP__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 717); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3122; + x86::Gp ret_val_illegal_normal_3122 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3122, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3122, vs2==vd); + setArg(call_illegal_normal_3122, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3122, 1, vd); + setArg(call_illegal_normal_3122, 2, vm); + setRet(call_illegal_normal_3122, 0, ret_val_illegal_normal_3122); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3124; + x86::Gp ret_val_sew_3124 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3124, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slideup_3123; + auto vector_slideup_3123_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slideup_3123_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slideup_3123_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slideup_3123_arg8 = ret_val_sew_3124; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slideup_3123, &vector_slideup, FuncSignature::build()); + setArg(call_sew_3124, 0, reinterpret_cast(this)); + setRet(call_sew_3124, 0, ret_val_sew_3124); + setArg(call_vector_slideup_3123, 0, V); + setArg(call_vector_slideup_3123, 1, vector_slideup_3123_arg1); + setArg(call_vector_slideup_3123, 2, vector_slideup_3123_arg2); + setArg(call_vector_slideup_3123, 3, vector_slideup_3123_arg3); + setArg(call_vector_slideup_3123, 4, vm); + setArg(call_vector_slideup_3123, 5, vd); + setArg(call_vector_slideup_3123, 6, vs2); + setArg(call_vector_slideup_3123, 7, (uint64_t)simm); + setArg(call_vector_slideup_3123, 8, vector_slideup_3123_arg8); + } + cc.bind(label_merge); + } + auto tmp3125 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3125, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3125, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 717); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 718: VSLIDEUP__VX */ + continuation_e __vslideup__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslideup.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDEUP__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 718); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3126; + x86::Gp ret_val_illegal_normal_3126 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3126, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3127 = get_reg(cc, 8, false); + mov(cc, tmp3127, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3127, ret_val_illegal_normal_3126), vs2==vd); + setArg(call_illegal_normal_3126, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3126, 1, vd); + setArg(call_illegal_normal_3126, 2, vm); + setRet(call_illegal_normal_3126, 0, ret_val_illegal_normal_3126); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3129; + x86::Gp ret_val_sew_3129 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3129, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slideup_3128; + auto vector_slideup_3128_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slideup_3128_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slideup_3128_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slideup_3128_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_slideup_3128_arg8 = ret_val_sew_3129; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slideup_3128, &vector_slideup, FuncSignature::build()); + setArg(call_sew_3129, 0, reinterpret_cast(this)); + setRet(call_sew_3129, 0, ret_val_sew_3129); + setArg(call_vector_slideup_3128, 0, V); + setArg(call_vector_slideup_3128, 1, vector_slideup_3128_arg1); + setArg(call_vector_slideup_3128, 2, vector_slideup_3128_arg2); + setArg(call_vector_slideup_3128, 3, vector_slideup_3128_arg3); + setArg(call_vector_slideup_3128, 4, vm); + setArg(call_vector_slideup_3128, 5, vd); + setArg(call_vector_slideup_3128, 6, vs2); + setArg(call_vector_slideup_3128, 7, vector_slideup_3128_arg7); + setArg(call_vector_slideup_3128, 8, vector_slideup_3128_arg8); + } + cc.bind(label_merge); + } + auto tmp3130 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3130, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3130, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 718); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 719: VSLIDEDOWN__VI */ + continuation_e __vslidedown__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vslidedown.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDEDOWN__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 719); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3131; + x86::Gp ret_val_illegal_normal_3131 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3131, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_3131; + setArg(call_illegal_normal_3131, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3131, 1, vd); + setArg(call_illegal_normal_3131, 2, vm); + setRet(call_illegal_normal_3131, 0, ret_val_illegal_normal_3131); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3133; + x86::Gp ret_val_sew_3133 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3133, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slidedown_3132; + auto vector_slidedown_3132_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slidedown_3132_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slidedown_3132_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slidedown_3132_arg8 = ret_val_sew_3133; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slidedown_3132, &vector_slidedown, FuncSignature::build()); + setArg(call_sew_3133, 0, reinterpret_cast(this)); + setRet(call_sew_3133, 0, ret_val_sew_3133); + setArg(call_vector_slidedown_3132, 0, V); + setArg(call_vector_slidedown_3132, 1, vector_slidedown_3132_arg1); + setArg(call_vector_slidedown_3132, 2, vector_slidedown_3132_arg2); + setArg(call_vector_slidedown_3132, 3, vector_slidedown_3132_arg3); + setArg(call_vector_slidedown_3132, 4, vm); + setArg(call_vector_slidedown_3132, 5, vd); + setArg(call_vector_slidedown_3132, 6, vs2); + setArg(call_vector_slidedown_3132, 7, (uint64_t)simm); + setArg(call_vector_slidedown_3132, 8, vector_slidedown_3132_arg8); + } + cc.bind(label_merge); + } + auto tmp3134 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3134, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3134, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 719); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 720: VSLIDEDOWN__VX */ + continuation_e __vslidedown__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslidedown.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDEDOWN__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 720); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3135; + x86::Gp ret_val_illegal_normal_3135 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3135, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3136 = get_reg(cc, 8, false); + mov(cc, tmp3136, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3136, ret_val_illegal_normal_3135); + setArg(call_illegal_normal_3135, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3135, 1, vd); + setArg(call_illegal_normal_3135, 2, vm); + setRet(call_illegal_normal_3135, 0, ret_val_illegal_normal_3135); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3138; + x86::Gp ret_val_sew_3138 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3138, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slidedown_3137; + auto vector_slidedown_3137_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slidedown_3137_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slidedown_3137_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slidedown_3137_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_slidedown_3137_arg8 = ret_val_sew_3138; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slidedown_3137, &vector_slidedown, FuncSignature::build()); + setArg(call_sew_3138, 0, reinterpret_cast(this)); + setRet(call_sew_3138, 0, ret_val_sew_3138); + setArg(call_vector_slidedown_3137, 0, V); + setArg(call_vector_slidedown_3137, 1, vector_slidedown_3137_arg1); + setArg(call_vector_slidedown_3137, 2, vector_slidedown_3137_arg2); + setArg(call_vector_slidedown_3137, 3, vector_slidedown_3137_arg3); + setArg(call_vector_slidedown_3137, 4, vm); + setArg(call_vector_slidedown_3137, 5, vd); + setArg(call_vector_slidedown_3137, 6, vs2); + setArg(call_vector_slidedown_3137, 7, vector_slidedown_3137_arg7); + setArg(call_vector_slidedown_3137, 8, vector_slidedown_3137_arg8); + } + cc.bind(label_merge); + } + auto tmp3139 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3139, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3139, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 720); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 721: VSLIDE1UP__VX */ + continuation_e __vslide1up__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslide1up.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDE1UP__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 721); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3140; + x86::Gp ret_val_illegal_normal_3140 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3140, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3141 = get_reg(cc, 8, false); + mov(cc, tmp3141, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3141, ret_val_illegal_normal_3140), vs2==vd); + setArg(call_illegal_normal_3140, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3140, 1, vd); + setArg(call_illegal_normal_3140, 2, vm); + setRet(call_illegal_normal_3140, 0, ret_val_illegal_normal_3140); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3143; + x86::Gp ret_val_sew_3143 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3143, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slide1up_3142; + auto vector_slide1up_3142_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slide1up_3142_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slide1up_3142_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slide1up_3142_arg7 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false); + auto vector_slide1up_3142_arg8 = ret_val_sew_3143; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slide1up_3142, &vector_slide1up, FuncSignature::build()); + setArg(call_sew_3143, 0, reinterpret_cast(this)); + setRet(call_sew_3143, 0, ret_val_sew_3143); + setArg(call_vector_slide1up_3142, 0, V); + setArg(call_vector_slide1up_3142, 1, vector_slide1up_3142_arg1); + setArg(call_vector_slide1up_3142, 2, vector_slide1up_3142_arg2); + setArg(call_vector_slide1up_3142, 3, vector_slide1up_3142_arg3); + setArg(call_vector_slide1up_3142, 4, vm); + setArg(call_vector_slide1up_3142, 5, vd); + setArg(call_vector_slide1up_3142, 6, vs2); + setArg(call_vector_slide1up_3142, 7, vector_slide1up_3142_arg7); + setArg(call_vector_slide1up_3142, 8, vector_slide1up_3142_arg8); + } + cc.bind(label_merge); + } + auto tmp3144 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3144, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3144, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 721); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 722: VSLIDE1DOWN__VX */ + continuation_e __vslide1down__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vslide1down.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VSLIDE1DOWN__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 722); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3145; + x86::Gp ret_val_illegal_normal_3145 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3145, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3146 = get_reg(cc, 8, false); + mov(cc, tmp3146, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3146, ret_val_illegal_normal_3145); + setArg(call_illegal_normal_3145, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3145, 1, vd); + setArg(call_illegal_normal_3145, 2, vm); + setRet(call_illegal_normal_3145, 0, ret_val_illegal_normal_3145); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3148; + x86::Gp ret_val_sew_3148 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3148, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slide1down_3147; + auto vector_slide1down_3147_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slide1down_3147_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slide1down_3147_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slide1down_3147_arg7 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false); + auto vector_slide1down_3147_arg8 = ret_val_sew_3148; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_slide1down_3147, &vector_slide1down, FuncSignature::build()); + setArg(call_sew_3148, 0, reinterpret_cast(this)); + setRet(call_sew_3148, 0, ret_val_sew_3148); + setArg(call_vector_slide1down_3147, 0, V); + setArg(call_vector_slide1down_3147, 1, vector_slide1down_3147_arg1); + setArg(call_vector_slide1down_3147, 2, vector_slide1down_3147_arg2); + setArg(call_vector_slide1down_3147, 3, vector_slide1down_3147_arg3); + setArg(call_vector_slide1down_3147, 4, vm); + setArg(call_vector_slide1down_3147, 5, vd); + setArg(call_vector_slide1down_3147, 6, vs2); + setArg(call_vector_slide1down_3147, 7, vector_slide1down_3147_arg7); + setArg(call_vector_slide1down_3147, 8, vector_slide1down_3147_arg8); + } + cc.bind(label_merge); + } + auto tmp3149 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3149, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3149, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 722); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 723: VRGATHER__VI */ + continuation_e __vrgather__vi(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t simm = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {simm}, {vm}", fmt::arg("mnemonic", "vrgather.vi"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("simm", simm), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRGATHER__VI_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 723); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3150; + x86::Gp ret_val_illegal_normal_3150 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3150, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3150, vs2==vd); + setArg(call_illegal_normal_3150, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3150, 1, vd); + setArg(call_illegal_normal_3150, 2, vm); + setRet(call_illegal_normal_3150, 0, ret_val_illegal_normal_3150); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3152; + x86::Gp ret_val_sew_3152 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3152, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_gather_3151; + auto vector_imm_gather_3151_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_gather_3151_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_gather_3151_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_gather_3151_arg8 = ret_val_sew_3152; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_gather_3151, &vector_imm_gather, FuncSignature::build()); + setArg(call_sew_3152, 0, reinterpret_cast(this)); + setRet(call_sew_3152, 0, ret_val_sew_3152); + setArg(call_vector_imm_gather_3151, 0, V); + setArg(call_vector_imm_gather_3151, 1, vector_imm_gather_3151_arg1); + setArg(call_vector_imm_gather_3151, 2, vector_imm_gather_3151_arg2); + setArg(call_vector_imm_gather_3151, 3, vector_imm_gather_3151_arg3); + setArg(call_vector_imm_gather_3151, 4, vm); + setArg(call_vector_imm_gather_3151, 5, vd); + setArg(call_vector_imm_gather_3151, 6, vs2); + setArg(call_vector_imm_gather_3151, 7, (uint64_t)simm); + setArg(call_vector_imm_gather_3151, 8, vector_imm_gather_3151_arg8); + auto tmp3153 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3153, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3153, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 723); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 724: VRGATHER__VV */ + continuation_e __vrgather__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrgather.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRGATHER__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 724); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3154; + x86::Gp ret_val_illegal_normal_3154 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3154, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3154, vs1==vd), vs2==vd); + setArg(call_illegal_normal_3154, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3154, 1, vd); + setArg(call_illegal_normal_3154, 2, vm); + setRet(call_illegal_normal_3154, 0, ret_val_illegal_normal_3154); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3156; + x86::Gp ret_val_sew_3156 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3156, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_gather_3155; + auto vector_vector_gather_3155_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_gather_3155_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_gather_3155_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_gather_3155_arg8 = ret_val_sew_3156; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_gather_3155, &vector_vector_gather, FuncSignature::build()); + setArg(call_sew_3156, 0, reinterpret_cast(this)); + setRet(call_sew_3156, 0, ret_val_sew_3156); + setArg(call_vector_vector_gather_3155, 0, V); + setArg(call_vector_vector_gather_3155, 1, vector_vector_gather_3155_arg1); + setArg(call_vector_vector_gather_3155, 2, vector_vector_gather_3155_arg2); + setArg(call_vector_vector_gather_3155, 3, vector_vector_gather_3155_arg3); + setArg(call_vector_vector_gather_3155, 4, vm); + setArg(call_vector_vector_gather_3155, 5, vd); + setArg(call_vector_vector_gather_3155, 6, vs2); + setArg(call_vector_vector_gather_3155, 7, vs1); + setArg(call_vector_vector_gather_3155, 8, vector_vector_gather_3155_arg8); + auto tmp3157 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3157, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3157, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 724); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 725: VRGATHER__VX */ + continuation_e __vrgather__vx(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vrgather.vx"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", name(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRGATHER__VX_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 725); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3158; + x86::Gp ret_val_illegal_normal_3158 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3158, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3159 = get_reg(cc, 8, false); + mov(cc, tmp3159, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3159, ret_val_illegal_normal_3158), vs2==vd); + setArg(call_illegal_normal_3158, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3158, 1, vd); + setArg(call_illegal_normal_3158, 2, vm); + setRet(call_illegal_normal_3158, 0, ret_val_illegal_normal_3158); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3161; + x86::Gp ret_val_sew_3161 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3161, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_gather_3160; + auto vector_imm_gather_3160_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_gather_3160_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_gather_3160_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_gather_3160_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_imm_gather_3160_arg8 = ret_val_sew_3161; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_gather_3160, &vector_imm_gather, FuncSignature::build()); + setArg(call_sew_3161, 0, reinterpret_cast(this)); + setRet(call_sew_3161, 0, ret_val_sew_3161); + setArg(call_vector_imm_gather_3160, 0, V); + setArg(call_vector_imm_gather_3160, 1, vector_imm_gather_3160_arg1); + setArg(call_vector_imm_gather_3160, 2, vector_imm_gather_3160_arg2); + setArg(call_vector_imm_gather_3160, 3, vector_imm_gather_3160_arg3); + setArg(call_vector_imm_gather_3160, 4, vm); + setArg(call_vector_imm_gather_3160, 5, vd); + setArg(call_vector_imm_gather_3160, 6, vs2); + setArg(call_vector_imm_gather_3160, 7, vector_imm_gather_3160_arg7); + setArg(call_vector_imm_gather_3160, 8, vector_imm_gather_3160_arg8); + auto tmp3162 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3162, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3162, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 725); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 726: VRGATHEREI16__VV */ + continuation_e __vrgatherei16__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vrgatherei16.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VRGATHEREI16__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 726); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_normal_3163; + x86::Gp ret_val_illegal_normal_3163 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3163, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3163, vs1==vd), vs2==vd); + setArg(call_illegal_normal_3163, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3163, 1, vd); + setArg(call_illegal_normal_3163, 2, vm); + setRet(call_illegal_normal_3163, 0, ret_val_illegal_normal_3163); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3165; + x86::Gp ret_val_sew_3165 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3165, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_gatherei16_3164; + auto vector_vector_gatherei16_3164_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_gatherei16_3164_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_gatherei16_3164_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_gatherei16_3164_arg8 = ret_val_sew_3165; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_vector_gatherei16_3164, &vector_vector_gatherei16, FuncSignature::build()); + setArg(call_sew_3165, 0, reinterpret_cast(this)); + setRet(call_sew_3165, 0, ret_val_sew_3165); + setArg(call_vector_vector_gatherei16_3164, 0, V); + setArg(call_vector_vector_gatherei16_3164, 1, vector_vector_gatherei16_3164_arg1); + setArg(call_vector_vector_gatherei16_3164, 2, vector_vector_gatherei16_3164_arg2); + setArg(call_vector_vector_gatherei16_3164, 3, vector_vector_gatherei16_3164_arg3); + setArg(call_vector_vector_gatherei16_3164, 4, vm); + setArg(call_vector_vector_gatherei16_3164, 5, vd); + setArg(call_vector_vector_gatherei16_3164, 6, vs2); + setArg(call_vector_vector_gatherei16_3164, 7, vs1); + setArg(call_vector_vector_gatherei16_3164, 8, vector_vector_gatherei16_3164_arg8); + auto tmp3166 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3166, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3166, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 726); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 727: VCOMPRESS__VM */ + continuation_e __vcompress__vm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}", fmt::arg("mnemonic", "vcompress.vm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VCOMPRESS__VM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 727); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_vd_unmasked_3167; + x86::Gp ret_val_illegal_vd_unmasked_3167 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3167, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0), vs1==vd), vs2==vd), ret_val_illegal_vd_unmasked_3167); + setArg(call_illegal_vd_unmasked_3167, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3167, 0, ret_val_illegal_vd_unmasked_3167); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, 2); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3169; + x86::Gp ret_val_sew_3169 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3169, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_compress_3168; + auto vector_compress_3168_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_compress_3168_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_compress_3168_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_compress_3168_arg7 = ret_val_sew_3169; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_compress_3168, &vector_compress, FuncSignature::build()); + setArg(call_sew_3169, 0, reinterpret_cast(this)); + setRet(call_sew_3169, 0, ret_val_sew_3169); + setArg(call_vector_compress_3168, 0, V); + setArg(call_vector_compress_3168, 1, vector_compress_3168_arg1); + setArg(call_vector_compress_3168, 2, vector_compress_3168_arg2); + setArg(call_vector_compress_3168, 3, vector_compress_3168_arg3); + setArg(call_vector_compress_3168, 4, vd); + setArg(call_vector_compress_3168, 5, vs2); + setArg(call_vector_compress_3168, 6, vs1); + setArg(call_vector_compress_3168, 7, vector_compress_3168_arg7); + } + cc.bind(label_merge); + } + auto tmp3170 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3170, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3170, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 727); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 728: VMV1R__V */ + continuation_e __vmv1r__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv1r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV1R__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 728); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_vector_whole_move_3171; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_whole_move_3171, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3171, 0, V); + setArg(call_vector_whole_move_3171, 1, vd); + setArg(call_vector_whole_move_3171, 2, vs2); + setArg(call_vector_whole_move_3171, 3, 1); + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 728); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 729: VMV2R__V */ + continuation_e __vmv2r__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv2r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV2R__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 729); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(vd%2||vs2%2){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_vector_whole_move_3172; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_whole_move_3172, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3172, 0, V); + setArg(call_vector_whole_move_3172, 1, vd); + setArg(call_vector_whole_move_3172, 2, vs2); + setArg(call_vector_whole_move_3172, 3, 2); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 729); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 730: VMV4R__V */ + continuation_e __vmv4r__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv4r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV4R__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 730); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(vd%4||vs2%4){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_vector_whole_move_3173; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_whole_move_3173, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3173, 0, V); + setArg(call_vector_whole_move_3173, 1, vd); + setArg(call_vector_whole_move_3173, 2, vs2); + setArg(call_vector_whole_move_3173, 3, 4); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 730); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 731: VMV8R__V */ + continuation_e __vmv8r__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}", fmt::arg("mnemonic", "vmv8r.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMV8R__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 731); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + if(vd%8||vs2%8){ + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + else { + InvokeNode* call_vector_whole_move_3174; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_whole_move_3174, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3174, 0, V); + setArg(call_vector_whole_move_3174, 1, vd); + setArg(call_vector_whole_move_3174, 2, vs2); + setArg(call_vector_whole_move_3174, 3, 8); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 731); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 732: VFMV__S__F */ + continuation_e __vfmv__s__f(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vfmv.s.f"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMV__S__F_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 732); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3175; + x86::Gp ret_val_get_sew_pow_3175 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3175, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3176 = get_reg(cc, 8, false); + mov(cc, tmp3176, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3176, (ret_val_get_sew_pow_3175))), 8, false), ~ 1); + setArg(call_get_sew_pow_3175, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3175, 0, ret_val_get_sew_pow_3175); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3177; + auto illegal_fp_vd_unmasked_3177_arg0 = SEW; + auto illegal_fp_vd_unmasked_3177_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3177 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3177, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3177; + setArg(call_illegal_fp_vd_unmasked_3177, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3177, 1, illegal_fp_vd_unmasked_3177_arg0); + setArg(call_illegal_fp_vd_unmasked_3177, 2, illegal_fp_vd_unmasked_3177_arg1); + setRet(call_illegal_fp_vd_unmasked_3177, 0, ret_val_illegal_fp_vd_unmasked_3177); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3179; + x86::Gp ret_val_sew_3179 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3179, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_to_vector_3178; + auto scalar_to_vector_3178_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_to_vector_3178_arg3 = gen_ext(cc, + gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false), 64, false); + auto scalar_to_vector_3178_arg4 = ret_val_sew_3179; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_scalar_to_vector_3178, &scalar_to_vector, FuncSignature::build()); + setArg(call_sew_3179, 0, reinterpret_cast(this)); + setRet(call_sew_3179, 0, ret_val_sew_3179); + setArg(call_scalar_to_vector_3178, 0, V); + setArg(call_scalar_to_vector_3178, 1, scalar_to_vector_3178_arg1); + setArg(call_scalar_to_vector_3178, 2, vd); + setArg(call_scalar_to_vector_3178, 3, scalar_to_vector_3178_arg3); + setArg(call_scalar_to_vector_3178, 4, scalar_to_vector_3178_arg4); + auto tmp3180 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3180, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3180, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 732); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 733: VFMV__F__S */ + continuation_e __vfmv__f__s(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {vs2}", fmt::arg("mnemonic", "vfmv.f.s"), + fmt::arg("rd", fname(rd)), fmt::arg("vs2", vname(vs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMV__F__S_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 733); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3181; + x86::Gp ret_val_get_sew_pow_3181 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3181, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3182 = get_reg(cc, 8, false); + mov(cc, tmp3182, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3182, (ret_val_get_sew_pow_3181))), 8, false), ~ 1); + setArg(call_get_sew_pow_3181, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3181, 0, ret_val_get_sew_pow_3181); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3183; + auto illegal_fp_vd_unmasked_3183_arg0 = SEW; + auto illegal_fp_vd_unmasked_3183_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3183 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3183, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_vd_unmasked_3183, gen_operation(cc, gtu, SEW, static_cast(traits::FLEN))); + setArg(call_illegal_fp_vd_unmasked_3183, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3183, 1, illegal_fp_vd_unmasked_3183_arg0); + setArg(call_illegal_fp_vd_unmasked_3183, 2, illegal_fp_vd_unmasked_3183_arg1); + setRet(call_illegal_fp_vd_unmasked_3183, 0, ret_val_illegal_fp_vd_unmasked_3183); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + InvokeNode* call_sew_3185; + x86::Gp ret_val_sew_3185 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3185, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_scalar_from_vector_3184; + auto fp_scalar_from_vector_3184_arg1 = load_reg_from_mem(jh, traits::vtype); + auto fp_scalar_from_vector_3184_arg3 = ret_val_sew_3185; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + x86::Gp ret_val_fp_scalar_from_vector_3184 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fp_scalar_from_vector_3184, &fp_scalar_from_vector, FuncSignature::build()); + mov(cc, get_ptr_for(jh, traits::F0+ rd), + ret_val_fp_scalar_from_vector_3184); + setArg(call_sew_3185, 0, reinterpret_cast(this)); + setRet(call_sew_3185, 0, ret_val_sew_3185); + setArg(call_fp_scalar_from_vector_3184, 0, V); + setArg(call_fp_scalar_from_vector_3184, 1, fp_scalar_from_vector_3184_arg1); + setArg(call_fp_scalar_from_vector_3184, 2, vs2); + setArg(call_fp_scalar_from_vector_3184, 3, fp_scalar_from_vector_3184_arg3); + setRet(call_fp_scalar_from_vector_3184, 0, ret_val_fp_scalar_from_vector_3184); + auto tmp3186 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3186, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3186, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 733); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 734: VFSLIDE1UP__VF */ + continuation_e __vfslide1up__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfslide1up.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSLIDE1UP__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 734); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3187; + x86::Gp ret_val_get_sew_pow_3187 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3187, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3188 = get_reg(cc, 8, false); + mov(cc, tmp3188, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3188, (ret_val_get_sew_pow_3187))), 8, false), ~ 1); + setArg(call_get_sew_pow_3187, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3187, 0, ret_val_get_sew_pow_3187); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3189; + auto illegal_fp_normal_3189_arg2 = SEW; + auto illegal_fp_normal_3189_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3189 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3189, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3189; + setArg(call_illegal_fp_normal_3189, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3189, 1, vd); + setArg(call_illegal_fp_normal_3189, 2, vm); + setArg(call_illegal_fp_normal_3189, 3, illegal_fp_normal_3189_arg2); + setArg(call_illegal_fp_normal_3189, 4, illegal_fp_normal_3189_arg3); + setRet(call_illegal_fp_normal_3189, 0, ret_val_illegal_fp_normal_3189); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3191; + x86::Gp ret_val_sew_3191 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3191, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_slide1up_3190; + auto fp_vector_slide1up_3190_arg1 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_slide1up_3190_arg2 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_slide1up_3190_arg3 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_slide1up_3190_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + auto fp_vector_slide1up_3190_arg8 = ret_val_sew_3191; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_slide1up_3190, &fp_vector_slide1up, FuncSignature::build()); + setArg(call_sew_3191, 0, reinterpret_cast(this)); + setRet(call_sew_3191, 0, ret_val_sew_3191); + setArg(call_fp_vector_slide1up_3190, 0, V); + setArg(call_fp_vector_slide1up_3190, 1, fp_vector_slide1up_3190_arg1); + setArg(call_fp_vector_slide1up_3190, 2, fp_vector_slide1up_3190_arg2); + setArg(call_fp_vector_slide1up_3190, 3, fp_vector_slide1up_3190_arg3); + setArg(call_fp_vector_slide1up_3190, 4, vm); + setArg(call_fp_vector_slide1up_3190, 5, vd); + setArg(call_fp_vector_slide1up_3190, 6, vs2); + setArg(call_fp_vector_slide1up_3190, 7, fp_vector_slide1up_3190_arg7); + setArg(call_fp_vector_slide1up_3190, 8, fp_vector_slide1up_3190_arg8); + } + cc.bind(label_merge); + } + auto tmp3192 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3192, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3192, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 734); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 735: VFSLIDE1DOWN__VF */ + continuation_e __vfslide1down__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfslide1down.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSLIDE1DOWN__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 735); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3193; + x86::Gp ret_val_get_sew_pow_3193 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3193, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3194 = get_reg(cc, 8, false); + mov(cc, tmp3194, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3194, (ret_val_get_sew_pow_3193))), 8, false), ~ 1); + setArg(call_get_sew_pow_3193, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3193, 0, ret_val_get_sew_pow_3193); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3195; + auto illegal_fp_normal_3195_arg2 = SEW; + auto illegal_fp_normal_3195_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3195 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3195, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3195; + setArg(call_illegal_fp_normal_3195, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3195, 1, vd); + setArg(call_illegal_fp_normal_3195, 2, vm); + setArg(call_illegal_fp_normal_3195, 3, illegal_fp_normal_3195_arg2); + setArg(call_illegal_fp_normal_3195, 4, illegal_fp_normal_3195_arg3); + setRet(call_illegal_fp_normal_3195, 0, ret_val_illegal_fp_normal_3195); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3197; + x86::Gp ret_val_sew_3197 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3197, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_slide1down_3196; + auto fp_vector_slide1down_3196_arg1 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_slide1down_3196_arg2 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_slide1down_3196_arg3 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_slide1down_3196_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + auto fp_vector_slide1down_3196_arg8 = ret_val_sew_3197; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_slide1down_3196, &fp_vector_slide1down, FuncSignature::build()); + setArg(call_sew_3197, 0, reinterpret_cast(this)); + setRet(call_sew_3197, 0, ret_val_sew_3197); + setArg(call_fp_vector_slide1down_3196, 0, V); + setArg(call_fp_vector_slide1down_3196, 1, fp_vector_slide1down_3196_arg1); + setArg(call_fp_vector_slide1down_3196, 2, fp_vector_slide1down_3196_arg2); + setArg(call_fp_vector_slide1down_3196, 3, fp_vector_slide1down_3196_arg3); + setArg(call_fp_vector_slide1down_3196, 4, vm); + setArg(call_fp_vector_slide1down_3196, 5, vd); + setArg(call_fp_vector_slide1down_3196, 6, vs2); + setArg(call_fp_vector_slide1down_3196, 7, fp_vector_slide1down_3196_arg7); + setArg(call_fp_vector_slide1down_3196, 8, fp_vector_slide1down_3196_arg8); + } + cc.bind(label_merge); + } + auto tmp3198 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3198, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3198, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 735); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 736: VFADD__VF */ + continuation_e __vfadd__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFADD__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 736); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3199; + x86::Gp ret_val_get_sew_pow_3199 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3199, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3200 = get_reg(cc, 8, false); + mov(cc, tmp3200, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3200, (ret_val_get_sew_pow_3199))), 8, false), ~ 1); + setArg(call_get_sew_pow_3199, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3199, 0, ret_val_get_sew_pow_3199); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3201; + auto illegal_fp_normal_3201_arg2 = SEW; + auto illegal_fp_normal_3201_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3201 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3201, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3201; + setArg(call_illegal_fp_normal_3201, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3201, 1, vd); + setArg(call_illegal_fp_normal_3201, 2, vm); + setArg(call_illegal_fp_normal_3201, 3, illegal_fp_normal_3201_arg2); + setArg(call_illegal_fp_normal_3201, 4, illegal_fp_normal_3201_arg3); + setRet(call_illegal_fp_normal_3201, 0, ret_val_illegal_fp_normal_3201); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3203; + x86::Gp ret_val_sew_3203 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3203, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3202; + auto fp_vector_imm_op_3202_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3202_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3202_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3202_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3202_arg10 = rm; + auto fp_vector_imm_op_3202_arg11 = ret_val_sew_3203; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3202, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3203, 0, reinterpret_cast(this)); + setRet(call_sew_3203, 0, ret_val_sew_3203); + setArg(call_fp_vector_imm_op_3202, 0, V); + setArg(call_fp_vector_imm_op_3202, 1, 0); + setArg(call_fp_vector_imm_op_3202, 2, 5); + setArg(call_fp_vector_imm_op_3202, 3, fp_vector_imm_op_3202_arg3); + setArg(call_fp_vector_imm_op_3202, 4, fp_vector_imm_op_3202_arg4); + setArg(call_fp_vector_imm_op_3202, 5, fp_vector_imm_op_3202_arg5); + setArg(call_fp_vector_imm_op_3202, 6, vm); + setArg(call_fp_vector_imm_op_3202, 7, vd); + setArg(call_fp_vector_imm_op_3202, 8, vs2); + setArg(call_fp_vector_imm_op_3202, 9, fp_vector_imm_op_3202_arg9); + setArg(call_fp_vector_imm_op_3202, 10, fp_vector_imm_op_3202_arg10); + setArg(call_fp_vector_imm_op_3202, 11, fp_vector_imm_op_3202_arg11); + InvokeNode* call_fget_flags_3204; + x86::Gp ret_val_fget_flags_3204 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3204, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3204; + setRet(call_fget_flags_3204, 0, ret_val_fget_flags_3204); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3205 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3205, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3205, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 736); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 737: VFADD__VV */ + continuation_e __vfadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 737); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3206; + x86::Gp ret_val_get_sew_pow_3206 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3206, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3207 = get_reg(cc, 8, false); + mov(cc, tmp3207, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3207, (ret_val_get_sew_pow_3206))), 8, false), ~ 1); + setArg(call_get_sew_pow_3206, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3206, 0, ret_val_get_sew_pow_3206); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3208; + auto illegal_fp_normal_3208_arg2 = SEW; + auto illegal_fp_normal_3208_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3208 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3208, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3208; + setArg(call_illegal_fp_normal_3208, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3208, 1, vd); + setArg(call_illegal_fp_normal_3208, 2, vm); + setArg(call_illegal_fp_normal_3208, 3, illegal_fp_normal_3208_arg2); + setArg(call_illegal_fp_normal_3208, 4, illegal_fp_normal_3208_arg3); + setRet(call_illegal_fp_normal_3208, 0, ret_val_illegal_fp_normal_3208); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3210; + x86::Gp ret_val_sew_3210 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3210, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3209; + auto fp_vector_vector_op_3209_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3209_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3209_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3209_arg10 = rm; + auto fp_vector_vector_op_3209_arg11 = ret_val_sew_3210; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3209, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3210, 0, reinterpret_cast(this)); + setRet(call_sew_3210, 0, ret_val_sew_3210); + setArg(call_fp_vector_vector_op_3209, 0, V); + setArg(call_fp_vector_vector_op_3209, 1, 0); + setArg(call_fp_vector_vector_op_3209, 2, 1); + setArg(call_fp_vector_vector_op_3209, 3, fp_vector_vector_op_3209_arg3); + setArg(call_fp_vector_vector_op_3209, 4, fp_vector_vector_op_3209_arg4); + setArg(call_fp_vector_vector_op_3209, 5, fp_vector_vector_op_3209_arg5); + setArg(call_fp_vector_vector_op_3209, 6, vm); + setArg(call_fp_vector_vector_op_3209, 7, vd); + setArg(call_fp_vector_vector_op_3209, 8, vs2); + setArg(call_fp_vector_vector_op_3209, 9, vs1); + setArg(call_fp_vector_vector_op_3209, 10, fp_vector_vector_op_3209_arg10); + setArg(call_fp_vector_vector_op_3209, 11, fp_vector_vector_op_3209_arg11); + InvokeNode* call_fget_flags_3211; + x86::Gp ret_val_fget_flags_3211 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3211, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3211; + setRet(call_fget_flags_3211, 0, ret_val_fget_flags_3211); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3212 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3212, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3212, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 737); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 738: VFSUB__VF */ + continuation_e __vfsub__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSUB__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 738); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3213; + x86::Gp ret_val_get_sew_pow_3213 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3213, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3214 = get_reg(cc, 8, false); + mov(cc, tmp3214, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3214, (ret_val_get_sew_pow_3213))), 8, false), ~ 1); + setArg(call_get_sew_pow_3213, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3213, 0, ret_val_get_sew_pow_3213); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3215; + auto illegal_fp_normal_3215_arg2 = SEW; + auto illegal_fp_normal_3215_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3215 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3215, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3215; + setArg(call_illegal_fp_normal_3215, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3215, 1, vd); + setArg(call_illegal_fp_normal_3215, 2, vm); + setArg(call_illegal_fp_normal_3215, 3, illegal_fp_normal_3215_arg2); + setArg(call_illegal_fp_normal_3215, 4, illegal_fp_normal_3215_arg3); + setRet(call_illegal_fp_normal_3215, 0, ret_val_illegal_fp_normal_3215); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3217; + x86::Gp ret_val_sew_3217 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3217, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3216; + auto fp_vector_imm_op_3216_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3216_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3216_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3216_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3216_arg10 = rm; + auto fp_vector_imm_op_3216_arg11 = ret_val_sew_3217; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3216, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3217, 0, reinterpret_cast(this)); + setRet(call_sew_3217, 0, ret_val_sew_3217); + setArg(call_fp_vector_imm_op_3216, 0, V); + setArg(call_fp_vector_imm_op_3216, 1, 2); + setArg(call_fp_vector_imm_op_3216, 2, 5); + setArg(call_fp_vector_imm_op_3216, 3, fp_vector_imm_op_3216_arg3); + setArg(call_fp_vector_imm_op_3216, 4, fp_vector_imm_op_3216_arg4); + setArg(call_fp_vector_imm_op_3216, 5, fp_vector_imm_op_3216_arg5); + setArg(call_fp_vector_imm_op_3216, 6, vm); + setArg(call_fp_vector_imm_op_3216, 7, vd); + setArg(call_fp_vector_imm_op_3216, 8, vs2); + setArg(call_fp_vector_imm_op_3216, 9, fp_vector_imm_op_3216_arg9); + setArg(call_fp_vector_imm_op_3216, 10, fp_vector_imm_op_3216_arg10); + setArg(call_fp_vector_imm_op_3216, 11, fp_vector_imm_op_3216_arg11); + InvokeNode* call_fget_flags_3218; + x86::Gp ret_val_fget_flags_3218 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3218, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3218; + setRet(call_fget_flags_3218, 0, ret_val_fget_flags_3218); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3219 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3219, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3219, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 738); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 739: VFSUB__VV */ + continuation_e __vfsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 739); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3220; + x86::Gp ret_val_get_sew_pow_3220 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3220, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3221 = get_reg(cc, 8, false); + mov(cc, tmp3221, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3221, (ret_val_get_sew_pow_3220))), 8, false), ~ 1); + setArg(call_get_sew_pow_3220, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3220, 0, ret_val_get_sew_pow_3220); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3222; + auto illegal_fp_normal_3222_arg2 = SEW; + auto illegal_fp_normal_3222_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3222 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3222, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3222; + setArg(call_illegal_fp_normal_3222, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3222, 1, vd); + setArg(call_illegal_fp_normal_3222, 2, vm); + setArg(call_illegal_fp_normal_3222, 3, illegal_fp_normal_3222_arg2); + setArg(call_illegal_fp_normal_3222, 4, illegal_fp_normal_3222_arg3); + setRet(call_illegal_fp_normal_3222, 0, ret_val_illegal_fp_normal_3222); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3224; + x86::Gp ret_val_sew_3224 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3224, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3223; + auto fp_vector_vector_op_3223_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3223_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3223_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3223_arg10 = rm; + auto fp_vector_vector_op_3223_arg11 = ret_val_sew_3224; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3223, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3224, 0, reinterpret_cast(this)); + setRet(call_sew_3224, 0, ret_val_sew_3224); + setArg(call_fp_vector_vector_op_3223, 0, V); + setArg(call_fp_vector_vector_op_3223, 1, 2); + setArg(call_fp_vector_vector_op_3223, 2, 1); + setArg(call_fp_vector_vector_op_3223, 3, fp_vector_vector_op_3223_arg3); + setArg(call_fp_vector_vector_op_3223, 4, fp_vector_vector_op_3223_arg4); + setArg(call_fp_vector_vector_op_3223, 5, fp_vector_vector_op_3223_arg5); + setArg(call_fp_vector_vector_op_3223, 6, vm); + setArg(call_fp_vector_vector_op_3223, 7, vd); + setArg(call_fp_vector_vector_op_3223, 8, vs2); + setArg(call_fp_vector_vector_op_3223, 9, vs1); + setArg(call_fp_vector_vector_op_3223, 10, fp_vector_vector_op_3223_arg10); + setArg(call_fp_vector_vector_op_3223, 11, fp_vector_vector_op_3223_arg11); + InvokeNode* call_fget_flags_3225; + x86::Gp ret_val_fget_flags_3225 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3225, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3225; + setRet(call_fget_flags_3225, 0, ret_val_fget_flags_3225); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3226 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3226, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3226, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 739); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 740: VFRSUB__VF */ + continuation_e __vfrsub__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfrsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFRSUB__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 740); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3227; + x86::Gp ret_val_get_sew_pow_3227 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3227, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3228 = get_reg(cc, 8, false); + mov(cc, tmp3228, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3228, (ret_val_get_sew_pow_3227))), 8, false), ~ 1); + setArg(call_get_sew_pow_3227, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3227, 0, ret_val_get_sew_pow_3227); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3229; + auto illegal_fp_normal_3229_arg2 = SEW; + auto illegal_fp_normal_3229_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3229 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3229, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3229; + setArg(call_illegal_fp_normal_3229, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3229, 1, vd); + setArg(call_illegal_fp_normal_3229, 2, vm); + setArg(call_illegal_fp_normal_3229, 3, illegal_fp_normal_3229_arg2); + setArg(call_illegal_fp_normal_3229, 4, illegal_fp_normal_3229_arg3); + setRet(call_illegal_fp_normal_3229, 0, ret_val_illegal_fp_normal_3229); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3231; + x86::Gp ret_val_sew_3231 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3231, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3230; + auto fp_vector_imm_op_3230_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3230_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3230_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3230_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3230_arg10 = rm; + auto fp_vector_imm_op_3230_arg11 = ret_val_sew_3231; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3230, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3231, 0, reinterpret_cast(this)); + setRet(call_sew_3231, 0, ret_val_sew_3231); + setArg(call_fp_vector_imm_op_3230, 0, V); + setArg(call_fp_vector_imm_op_3230, 1, 39); + setArg(call_fp_vector_imm_op_3230, 2, 5); + setArg(call_fp_vector_imm_op_3230, 3, fp_vector_imm_op_3230_arg3); + setArg(call_fp_vector_imm_op_3230, 4, fp_vector_imm_op_3230_arg4); + setArg(call_fp_vector_imm_op_3230, 5, fp_vector_imm_op_3230_arg5); + setArg(call_fp_vector_imm_op_3230, 6, vm); + setArg(call_fp_vector_imm_op_3230, 7, vd); + setArg(call_fp_vector_imm_op_3230, 8, vs2); + setArg(call_fp_vector_imm_op_3230, 9, fp_vector_imm_op_3230_arg9); + setArg(call_fp_vector_imm_op_3230, 10, fp_vector_imm_op_3230_arg10); + setArg(call_fp_vector_imm_op_3230, 11, fp_vector_imm_op_3230_arg11); + InvokeNode* call_fget_flags_3232; + x86::Gp ret_val_fget_flags_3232 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3232, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3232; + setRet(call_fget_flags_3232, 0, ret_val_fget_flags_3232); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3233 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3233, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3233, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 740); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 741: VFWADD__VF */ + continuation_e __vfwadd__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWADD__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 741); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3234; + x86::Gp ret_val_get_sew_pow_3234 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3234, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3235 = get_reg(cc, 8, false); + mov(cc, tmp3235, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3235, (ret_val_get_sew_pow_3234))), 8, false), ~ 1); + setArg(call_get_sew_pow_3234, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3234, 0, ret_val_get_sew_pow_3234); + InvokeNode* call_get_lmul_pow_3236; + x86::Gp ret_val_get_lmul_pow_3236 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3236, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3236; + setArg(call_get_lmul_pow_3236, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3236, 0, ret_val_get_lmul_pow_3236); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3237; + auto illegal_fp_variable_width_3237_arg2 = SEW; + auto illegal_fp_variable_width_3237_arg3 = rm; + auto illegal_fp_variable_width_3237_arg4 = SEW_widen; + auto illegal_fp_variable_width_3237_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3237 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3237, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3238; + auto valid_reg_overlap_3238_arg2 = LMUL_pow; + auto valid_reg_overlap_3238_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3238 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3238, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3237, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3238)); + setArg(call_illegal_fp_variable_width_3237, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3237, 1, vd); + setArg(call_illegal_fp_variable_width_3237, 2, vm); + setArg(call_illegal_fp_variable_width_3237, 3, illegal_fp_variable_width_3237_arg2); + setArg(call_illegal_fp_variable_width_3237, 4, illegal_fp_variable_width_3237_arg3); + setArg(call_illegal_fp_variable_width_3237, 5, illegal_fp_variable_width_3237_arg4); + setArg(call_illegal_fp_variable_width_3237, 6, illegal_fp_variable_width_3237_arg5); + setRet(call_illegal_fp_variable_width_3237, 0, ret_val_illegal_fp_variable_width_3237); + setArg(call_valid_reg_overlap_3238, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3238, 1, vs2); + setArg(call_valid_reg_overlap_3238, 2, vd); + setArg(call_valid_reg_overlap_3238, 3, valid_reg_overlap_3238_arg2); + setArg(call_valid_reg_overlap_3238, 4, valid_reg_overlap_3238_arg3); + setRet(call_valid_reg_overlap_3238, 0, ret_val_valid_reg_overlap_3238); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3240; + x86::Gp ret_val_sew_3240 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3240, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3239; + auto fp_vector_imm_wv_3239_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3239_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3239_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3239_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_wv_3239_arg10 = rm; + auto fp_vector_imm_wv_3239_arg11 = ret_val_sew_3240; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3239, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3240, 0, reinterpret_cast(this)); + setRet(call_sew_3240, 0, ret_val_sew_3240); + setArg(call_fp_vector_imm_wv_3239, 0, V); + setArg(call_fp_vector_imm_wv_3239, 1, 48); + setArg(call_fp_vector_imm_wv_3239, 2, 5); + setArg(call_fp_vector_imm_wv_3239, 3, fp_vector_imm_wv_3239_arg3); + setArg(call_fp_vector_imm_wv_3239, 4, fp_vector_imm_wv_3239_arg4); + setArg(call_fp_vector_imm_wv_3239, 5, fp_vector_imm_wv_3239_arg5); + setArg(call_fp_vector_imm_wv_3239, 6, vm); + setArg(call_fp_vector_imm_wv_3239, 7, vd); + setArg(call_fp_vector_imm_wv_3239, 8, vs2); + setArg(call_fp_vector_imm_wv_3239, 9, fp_vector_imm_wv_3239_arg9); + setArg(call_fp_vector_imm_wv_3239, 10, fp_vector_imm_wv_3239_arg10); + setArg(call_fp_vector_imm_wv_3239, 11, fp_vector_imm_wv_3239_arg11); + InvokeNode* call_fget_flags_3241; + x86::Gp ret_val_fget_flags_3241 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3241, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3241; + setRet(call_fget_flags_3241, 0, ret_val_fget_flags_3241); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3242 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3242, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3242, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 741); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 742: VFWADD__VV */ + continuation_e __vfwadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 742); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3243; + x86::Gp ret_val_get_sew_pow_3243 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3243, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3244 = get_reg(cc, 8, false); + mov(cc, tmp3244, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3244, (ret_val_get_sew_pow_3243))), 8, false), ~ 1); + setArg(call_get_sew_pow_3243, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3243, 0, ret_val_get_sew_pow_3243); + InvokeNode* call_get_lmul_pow_3245; + x86::Gp ret_val_get_lmul_pow_3245 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3245, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3245; + setArg(call_get_lmul_pow_3245, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3245, 0, ret_val_get_lmul_pow_3245); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3246; + auto illegal_fp_variable_width_3246_arg2 = SEW; + auto illegal_fp_variable_width_3246_arg3 = rm; + auto illegal_fp_variable_width_3246_arg4 = SEW_widen; + auto illegal_fp_variable_width_3246_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3246 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3246, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3247; + auto valid_reg_overlap_3247_arg2 = LMUL_pow; + auto valid_reg_overlap_3247_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3247 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3247, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3248; + auto valid_reg_overlap_3248_arg2 = LMUL_pow; + auto valid_reg_overlap_3248_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3248 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3248, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3246, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3247)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3248)); + setArg(call_illegal_fp_variable_width_3246, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3246, 1, vd); + setArg(call_illegal_fp_variable_width_3246, 2, vm); + setArg(call_illegal_fp_variable_width_3246, 3, illegal_fp_variable_width_3246_arg2); + setArg(call_illegal_fp_variable_width_3246, 4, illegal_fp_variable_width_3246_arg3); + setArg(call_illegal_fp_variable_width_3246, 5, illegal_fp_variable_width_3246_arg4); + setArg(call_illegal_fp_variable_width_3246, 6, illegal_fp_variable_width_3246_arg5); + setRet(call_illegal_fp_variable_width_3246, 0, ret_val_illegal_fp_variable_width_3246); + setArg(call_valid_reg_overlap_3247, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3247, 1, vs1); + setArg(call_valid_reg_overlap_3247, 2, vd); + setArg(call_valid_reg_overlap_3247, 3, valid_reg_overlap_3247_arg2); + setArg(call_valid_reg_overlap_3247, 4, valid_reg_overlap_3247_arg3); + setRet(call_valid_reg_overlap_3247, 0, ret_val_valid_reg_overlap_3247); + setArg(call_valid_reg_overlap_3248, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3248, 1, vs2); + setArg(call_valid_reg_overlap_3248, 2, vd); + setArg(call_valid_reg_overlap_3248, 3, valid_reg_overlap_3248_arg2); + setArg(call_valid_reg_overlap_3248, 4, valid_reg_overlap_3248_arg3); + setRet(call_valid_reg_overlap_3248, 0, ret_val_valid_reg_overlap_3248); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3250; + x86::Gp ret_val_sew_3250 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3250, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3249; + auto fp_vector_vector_wv_3249_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3249_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3249_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3249_arg10 = rm; + auto fp_vector_vector_wv_3249_arg11 = ret_val_sew_3250; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3249, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3250, 0, reinterpret_cast(this)); + setRet(call_sew_3250, 0, ret_val_sew_3250); + setArg(call_fp_vector_vector_wv_3249, 0, V); + setArg(call_fp_vector_vector_wv_3249, 1, 48); + setArg(call_fp_vector_vector_wv_3249, 2, 1); + setArg(call_fp_vector_vector_wv_3249, 3, fp_vector_vector_wv_3249_arg3); + setArg(call_fp_vector_vector_wv_3249, 4, fp_vector_vector_wv_3249_arg4); + setArg(call_fp_vector_vector_wv_3249, 5, fp_vector_vector_wv_3249_arg5); + setArg(call_fp_vector_vector_wv_3249, 6, vm); + setArg(call_fp_vector_vector_wv_3249, 7, vd); + setArg(call_fp_vector_vector_wv_3249, 8, vs2); + setArg(call_fp_vector_vector_wv_3249, 9, vs1); + setArg(call_fp_vector_vector_wv_3249, 10, fp_vector_vector_wv_3249_arg10); + setArg(call_fp_vector_vector_wv_3249, 11, fp_vector_vector_wv_3249_arg11); + InvokeNode* call_fget_flags_3251; + x86::Gp ret_val_fget_flags_3251 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3251, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3251; + setRet(call_fget_flags_3251, 0, ret_val_fget_flags_3251); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3252 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3252, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3252, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 742); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 743: VFWSUB__VF */ + continuation_e __vfwsub__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWSUB__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 743); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3253; + x86::Gp ret_val_get_sew_pow_3253 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3253, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3254 = get_reg(cc, 8, false); + mov(cc, tmp3254, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3254, (ret_val_get_sew_pow_3253))), 8, false), ~ 1); + setArg(call_get_sew_pow_3253, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3253, 0, ret_val_get_sew_pow_3253); + InvokeNode* call_get_lmul_pow_3255; + x86::Gp ret_val_get_lmul_pow_3255 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3255, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3255; + setArg(call_get_lmul_pow_3255, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3255, 0, ret_val_get_lmul_pow_3255); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3256; + auto illegal_fp_variable_width_3256_arg2 = SEW; + auto illegal_fp_variable_width_3256_arg3 = rm; + auto illegal_fp_variable_width_3256_arg4 = SEW_widen; + auto illegal_fp_variable_width_3256_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3256 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3256, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3257; + auto valid_reg_overlap_3257_arg2 = LMUL_pow; + auto valid_reg_overlap_3257_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3257 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3257, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3256, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3257)); + setArg(call_illegal_fp_variable_width_3256, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3256, 1, vd); + setArg(call_illegal_fp_variable_width_3256, 2, vm); + setArg(call_illegal_fp_variable_width_3256, 3, illegal_fp_variable_width_3256_arg2); + setArg(call_illegal_fp_variable_width_3256, 4, illegal_fp_variable_width_3256_arg3); + setArg(call_illegal_fp_variable_width_3256, 5, illegal_fp_variable_width_3256_arg4); + setArg(call_illegal_fp_variable_width_3256, 6, illegal_fp_variable_width_3256_arg5); + setRet(call_illegal_fp_variable_width_3256, 0, ret_val_illegal_fp_variable_width_3256); + setArg(call_valid_reg_overlap_3257, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3257, 1, vs2); + setArg(call_valid_reg_overlap_3257, 2, vd); + setArg(call_valid_reg_overlap_3257, 3, valid_reg_overlap_3257_arg2); + setArg(call_valid_reg_overlap_3257, 4, valid_reg_overlap_3257_arg3); + setRet(call_valid_reg_overlap_3257, 0, ret_val_valid_reg_overlap_3257); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3259; + x86::Gp ret_val_sew_3259 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3259, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3258; + auto fp_vector_imm_wv_3258_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3258_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3258_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3258_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_wv_3258_arg10 = rm; + auto fp_vector_imm_wv_3258_arg11 = ret_val_sew_3259; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3258, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3259, 0, reinterpret_cast(this)); + setRet(call_sew_3259, 0, ret_val_sew_3259); + setArg(call_fp_vector_imm_wv_3258, 0, V); + setArg(call_fp_vector_imm_wv_3258, 1, 50); + setArg(call_fp_vector_imm_wv_3258, 2, 5); + setArg(call_fp_vector_imm_wv_3258, 3, fp_vector_imm_wv_3258_arg3); + setArg(call_fp_vector_imm_wv_3258, 4, fp_vector_imm_wv_3258_arg4); + setArg(call_fp_vector_imm_wv_3258, 5, fp_vector_imm_wv_3258_arg5); + setArg(call_fp_vector_imm_wv_3258, 6, vm); + setArg(call_fp_vector_imm_wv_3258, 7, vd); + setArg(call_fp_vector_imm_wv_3258, 8, vs2); + setArg(call_fp_vector_imm_wv_3258, 9, fp_vector_imm_wv_3258_arg9); + setArg(call_fp_vector_imm_wv_3258, 10, fp_vector_imm_wv_3258_arg10); + setArg(call_fp_vector_imm_wv_3258, 11, fp_vector_imm_wv_3258_arg11); + InvokeNode* call_fget_flags_3260; + x86::Gp ret_val_fget_flags_3260 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3260, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3260; + setRet(call_fget_flags_3260, 0, ret_val_fget_flags_3260); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3261 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3261, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3261, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 743); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 744: VFWSUB__VV */ + continuation_e __vfwsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 744); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3262; + x86::Gp ret_val_get_sew_pow_3262 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3262, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3263 = get_reg(cc, 8, false); + mov(cc, tmp3263, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3263, (ret_val_get_sew_pow_3262))), 8, false), ~ 1); + setArg(call_get_sew_pow_3262, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3262, 0, ret_val_get_sew_pow_3262); + InvokeNode* call_get_lmul_pow_3264; + x86::Gp ret_val_get_lmul_pow_3264 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3264, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3264; + setArg(call_get_lmul_pow_3264, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3264, 0, ret_val_get_lmul_pow_3264); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3265; + auto illegal_fp_variable_width_3265_arg2 = SEW; + auto illegal_fp_variable_width_3265_arg3 = rm; + auto illegal_fp_variable_width_3265_arg4 = SEW_widen; + auto illegal_fp_variable_width_3265_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3265 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3265, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3266; + auto valid_reg_overlap_3266_arg2 = LMUL_pow; + auto valid_reg_overlap_3266_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3266 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3266, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3267; + auto valid_reg_overlap_3267_arg2 = LMUL_pow; + auto valid_reg_overlap_3267_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3267 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3267, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3265, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3266)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3267)); + setArg(call_illegal_fp_variable_width_3265, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3265, 1, vd); + setArg(call_illegal_fp_variable_width_3265, 2, vm); + setArg(call_illegal_fp_variable_width_3265, 3, illegal_fp_variable_width_3265_arg2); + setArg(call_illegal_fp_variable_width_3265, 4, illegal_fp_variable_width_3265_arg3); + setArg(call_illegal_fp_variable_width_3265, 5, illegal_fp_variable_width_3265_arg4); + setArg(call_illegal_fp_variable_width_3265, 6, illegal_fp_variable_width_3265_arg5); + setRet(call_illegal_fp_variable_width_3265, 0, ret_val_illegal_fp_variable_width_3265); + setArg(call_valid_reg_overlap_3266, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3266, 1, vs1); + setArg(call_valid_reg_overlap_3266, 2, vd); + setArg(call_valid_reg_overlap_3266, 3, valid_reg_overlap_3266_arg2); + setArg(call_valid_reg_overlap_3266, 4, valid_reg_overlap_3266_arg3); + setRet(call_valid_reg_overlap_3266, 0, ret_val_valid_reg_overlap_3266); + setArg(call_valid_reg_overlap_3267, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3267, 1, vs2); + setArg(call_valid_reg_overlap_3267, 2, vd); + setArg(call_valid_reg_overlap_3267, 3, valid_reg_overlap_3267_arg2); + setArg(call_valid_reg_overlap_3267, 4, valid_reg_overlap_3267_arg3); + setRet(call_valid_reg_overlap_3267, 0, ret_val_valid_reg_overlap_3267); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3269; + x86::Gp ret_val_sew_3269 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3269, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3268; + auto fp_vector_vector_wv_3268_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3268_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3268_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3268_arg10 = rm; + auto fp_vector_vector_wv_3268_arg11 = ret_val_sew_3269; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3268, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3269, 0, reinterpret_cast(this)); + setRet(call_sew_3269, 0, ret_val_sew_3269); + setArg(call_fp_vector_vector_wv_3268, 0, V); + setArg(call_fp_vector_vector_wv_3268, 1, 50); + setArg(call_fp_vector_vector_wv_3268, 2, 1); + setArg(call_fp_vector_vector_wv_3268, 3, fp_vector_vector_wv_3268_arg3); + setArg(call_fp_vector_vector_wv_3268, 4, fp_vector_vector_wv_3268_arg4); + setArg(call_fp_vector_vector_wv_3268, 5, fp_vector_vector_wv_3268_arg5); + setArg(call_fp_vector_vector_wv_3268, 6, vm); + setArg(call_fp_vector_vector_wv_3268, 7, vd); + setArg(call_fp_vector_vector_wv_3268, 8, vs2); + setArg(call_fp_vector_vector_wv_3268, 9, vs1); + setArg(call_fp_vector_vector_wv_3268, 10, fp_vector_vector_wv_3268_arg10); + setArg(call_fp_vector_vector_wv_3268, 11, fp_vector_vector_wv_3268_arg11); + InvokeNode* call_fget_flags_3270; + x86::Gp ret_val_fget_flags_3270 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3270, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3270; + setRet(call_fget_flags_3270, 0, ret_val_fget_flags_3270); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3271 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3271, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3271, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 744); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 745: VFWADD__WF */ + continuation_e __vfwadd__wf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwadd.wf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWADD__WF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 745); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3272; + x86::Gp ret_val_get_sew_pow_3272 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3272, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3273 = get_reg(cc, 8, false); + mov(cc, tmp3273, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3273, (ret_val_get_sew_pow_3272))), 8, false), ~ 1); + setArg(call_get_sew_pow_3272, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3272, 0, ret_val_get_sew_pow_3272); + InvokeNode* call_get_lmul_pow_3274; + x86::Gp ret_val_get_lmul_pow_3274 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3274, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3274; + setArg(call_get_lmul_pow_3274, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3274, 0, ret_val_get_lmul_pow_3274); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3275; + auto illegal_fp_variable_width_3275_arg2 = SEW; + auto illegal_fp_variable_width_3275_arg3 = rm; + auto illegal_fp_variable_width_3275_arg4 = SEW_widen; + auto illegal_fp_variable_width_3275_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3275 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3275, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_fp_variable_width_3275; + setArg(call_illegal_fp_variable_width_3275, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3275, 1, vd); + setArg(call_illegal_fp_variable_width_3275, 2, vm); + setArg(call_illegal_fp_variable_width_3275, 3, illegal_fp_variable_width_3275_arg2); + setArg(call_illegal_fp_variable_width_3275, 4, illegal_fp_variable_width_3275_arg3); + setArg(call_illegal_fp_variable_width_3275, 5, illegal_fp_variable_width_3275_arg4); + setArg(call_illegal_fp_variable_width_3275, 6, illegal_fp_variable_width_3275_arg5); + setRet(call_illegal_fp_variable_width_3275, 0, ret_val_illegal_fp_variable_width_3275); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3277; + x86::Gp ret_val_sew_3277 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3277, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_ww_3276; + auto fp_vector_imm_ww_3276_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_ww_3276_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_ww_3276_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_ww_3276_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_ww_3276_arg10 = rm; + auto fp_vector_imm_ww_3276_arg11 = ret_val_sew_3277; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_ww_3276, &fp_vector_imm_ww, FuncSignature::build()); + setArg(call_sew_3277, 0, reinterpret_cast(this)); + setRet(call_sew_3277, 0, ret_val_sew_3277); + setArg(call_fp_vector_imm_ww_3276, 0, V); + setArg(call_fp_vector_imm_ww_3276, 1, 52); + setArg(call_fp_vector_imm_ww_3276, 2, 5); + setArg(call_fp_vector_imm_ww_3276, 3, fp_vector_imm_ww_3276_arg3); + setArg(call_fp_vector_imm_ww_3276, 4, fp_vector_imm_ww_3276_arg4); + setArg(call_fp_vector_imm_ww_3276, 5, fp_vector_imm_ww_3276_arg5); + setArg(call_fp_vector_imm_ww_3276, 6, vm); + setArg(call_fp_vector_imm_ww_3276, 7, vd); + setArg(call_fp_vector_imm_ww_3276, 8, vs2); + setArg(call_fp_vector_imm_ww_3276, 9, fp_vector_imm_ww_3276_arg9); + setArg(call_fp_vector_imm_ww_3276, 10, fp_vector_imm_ww_3276_arg10); + setArg(call_fp_vector_imm_ww_3276, 11, fp_vector_imm_ww_3276_arg11); + InvokeNode* call_fget_flags_3278; + x86::Gp ret_val_fget_flags_3278 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3278, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3278; + setRet(call_fget_flags_3278, 0, ret_val_fget_flags_3278); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3279 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3279, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3279, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 745); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 746: VFWADD__WV */ + continuation_e __vfwadd__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwadd.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWADD__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 746); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3280; + x86::Gp ret_val_get_sew_pow_3280 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3280, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3281 = get_reg(cc, 8, false); + mov(cc, tmp3281, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3281, (ret_val_get_sew_pow_3280))), 8, false), ~ 1); + setArg(call_get_sew_pow_3280, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3280, 0, ret_val_get_sew_pow_3280); + InvokeNode* call_get_lmul_pow_3282; + x86::Gp ret_val_get_lmul_pow_3282 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3282, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3282; + setArg(call_get_lmul_pow_3282, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3282, 0, ret_val_get_lmul_pow_3282); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3283; + auto illegal_fp_variable_width_3283_arg2 = SEW; + auto illegal_fp_variable_width_3283_arg3 = rm; + auto illegal_fp_variable_width_3283_arg4 = SEW_widen; + auto illegal_fp_variable_width_3283_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3283 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3283, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3284; + auto valid_reg_overlap_3284_arg2 = LMUL_pow; + auto valid_reg_overlap_3284_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3284 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3284, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3283, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3284)); + setArg(call_illegal_fp_variable_width_3283, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3283, 1, vd); + setArg(call_illegal_fp_variable_width_3283, 2, vm); + setArg(call_illegal_fp_variable_width_3283, 3, illegal_fp_variable_width_3283_arg2); + setArg(call_illegal_fp_variable_width_3283, 4, illegal_fp_variable_width_3283_arg3); + setArg(call_illegal_fp_variable_width_3283, 5, illegal_fp_variable_width_3283_arg4); + setArg(call_illegal_fp_variable_width_3283, 6, illegal_fp_variable_width_3283_arg5); + setRet(call_illegal_fp_variable_width_3283, 0, ret_val_illegal_fp_variable_width_3283); + setArg(call_valid_reg_overlap_3284, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3284, 1, vs1); + setArg(call_valid_reg_overlap_3284, 2, vd); + setArg(call_valid_reg_overlap_3284, 3, valid_reg_overlap_3284_arg2); + setArg(call_valid_reg_overlap_3284, 4, valid_reg_overlap_3284_arg3); + setRet(call_valid_reg_overlap_3284, 0, ret_val_valid_reg_overlap_3284); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3286; + x86::Gp ret_val_sew_3286 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3286, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_ww_3285; + auto fp_vector_vector_ww_3285_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_ww_3285_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_ww_3285_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_ww_3285_arg10 = rm; + auto fp_vector_vector_ww_3285_arg11 = ret_val_sew_3286; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_ww_3285, &fp_vector_vector_ww, FuncSignature::build()); + setArg(call_sew_3286, 0, reinterpret_cast(this)); + setRet(call_sew_3286, 0, ret_val_sew_3286); + setArg(call_fp_vector_vector_ww_3285, 0, V); + setArg(call_fp_vector_vector_ww_3285, 1, 52); + setArg(call_fp_vector_vector_ww_3285, 2, 1); + setArg(call_fp_vector_vector_ww_3285, 3, fp_vector_vector_ww_3285_arg3); + setArg(call_fp_vector_vector_ww_3285, 4, fp_vector_vector_ww_3285_arg4); + setArg(call_fp_vector_vector_ww_3285, 5, fp_vector_vector_ww_3285_arg5); + setArg(call_fp_vector_vector_ww_3285, 6, vm); + setArg(call_fp_vector_vector_ww_3285, 7, vd); + setArg(call_fp_vector_vector_ww_3285, 8, vs2); + setArg(call_fp_vector_vector_ww_3285, 9, vs1); + setArg(call_fp_vector_vector_ww_3285, 10, fp_vector_vector_ww_3285_arg10); + setArg(call_fp_vector_vector_ww_3285, 11, fp_vector_vector_ww_3285_arg11); + InvokeNode* call_fget_flags_3287; + x86::Gp ret_val_fget_flags_3287 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3287, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3287; + setRet(call_fget_flags_3287, 0, ret_val_fget_flags_3287); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3288 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3288, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3288, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 746); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 747: VFWSUB__WF */ + continuation_e __vfwsub__wf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwsub.wf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWSUB__WF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 747); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3289; + x86::Gp ret_val_get_sew_pow_3289 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3289, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3290 = get_reg(cc, 8, false); + mov(cc, tmp3290, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3290, (ret_val_get_sew_pow_3289))), 8, false), ~ 1); + setArg(call_get_sew_pow_3289, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3289, 0, ret_val_get_sew_pow_3289); + InvokeNode* call_get_lmul_pow_3291; + x86::Gp ret_val_get_lmul_pow_3291 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3291, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3291; + setArg(call_get_lmul_pow_3291, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3291, 0, ret_val_get_lmul_pow_3291); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3292; + auto illegal_fp_variable_width_3292_arg2 = SEW; + auto illegal_fp_variable_width_3292_arg3 = rm; + auto illegal_fp_variable_width_3292_arg4 = SEW_widen; + auto illegal_fp_variable_width_3292_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3292 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3292, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_fp_variable_width_3292; + setArg(call_illegal_fp_variable_width_3292, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3292, 1, vd); + setArg(call_illegal_fp_variable_width_3292, 2, vm); + setArg(call_illegal_fp_variable_width_3292, 3, illegal_fp_variable_width_3292_arg2); + setArg(call_illegal_fp_variable_width_3292, 4, illegal_fp_variable_width_3292_arg3); + setArg(call_illegal_fp_variable_width_3292, 5, illegal_fp_variable_width_3292_arg4); + setArg(call_illegal_fp_variable_width_3292, 6, illegal_fp_variable_width_3292_arg5); + setRet(call_illegal_fp_variable_width_3292, 0, ret_val_illegal_fp_variable_width_3292); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3294; + x86::Gp ret_val_sew_3294 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3294, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_ww_3293; + auto fp_vector_imm_ww_3293_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_ww_3293_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_ww_3293_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_ww_3293_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_ww_3293_arg10 = rm; + auto fp_vector_imm_ww_3293_arg11 = ret_val_sew_3294; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_ww_3293, &fp_vector_imm_ww, FuncSignature::build()); + setArg(call_sew_3294, 0, reinterpret_cast(this)); + setRet(call_sew_3294, 0, ret_val_sew_3294); + setArg(call_fp_vector_imm_ww_3293, 0, V); + setArg(call_fp_vector_imm_ww_3293, 1, 54); + setArg(call_fp_vector_imm_ww_3293, 2, 5); + setArg(call_fp_vector_imm_ww_3293, 3, fp_vector_imm_ww_3293_arg3); + setArg(call_fp_vector_imm_ww_3293, 4, fp_vector_imm_ww_3293_arg4); + setArg(call_fp_vector_imm_ww_3293, 5, fp_vector_imm_ww_3293_arg5); + setArg(call_fp_vector_imm_ww_3293, 6, vm); + setArg(call_fp_vector_imm_ww_3293, 7, vd); + setArg(call_fp_vector_imm_ww_3293, 8, vs2); + setArg(call_fp_vector_imm_ww_3293, 9, fp_vector_imm_ww_3293_arg9); + setArg(call_fp_vector_imm_ww_3293, 10, fp_vector_imm_ww_3293_arg10); + setArg(call_fp_vector_imm_ww_3293, 11, fp_vector_imm_ww_3293_arg11); + InvokeNode* call_fget_flags_3295; + x86::Gp ret_val_fget_flags_3295 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3295, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3295; + setRet(call_fget_flags_3295, 0, ret_val_fget_flags_3295); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3296 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3296, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3296, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 747); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 748: VFWSUB__WV */ + continuation_e __vfwsub__wv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwsub.wv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWSUB__WV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 748); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3297; + x86::Gp ret_val_get_sew_pow_3297 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3297, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3298 = get_reg(cc, 8, false); + mov(cc, tmp3298, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3298, (ret_val_get_sew_pow_3297))), 8, false), ~ 1); + setArg(call_get_sew_pow_3297, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3297, 0, ret_val_get_sew_pow_3297); + InvokeNode* call_get_lmul_pow_3299; + x86::Gp ret_val_get_lmul_pow_3299 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3299, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3299; + setArg(call_get_lmul_pow_3299, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3299, 0, ret_val_get_lmul_pow_3299); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3300; + auto illegal_fp_variable_width_3300_arg2 = SEW; + auto illegal_fp_variable_width_3300_arg3 = rm; + auto illegal_fp_variable_width_3300_arg4 = SEW_widen; + auto illegal_fp_variable_width_3300_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3300 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3300, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3301; + auto valid_reg_overlap_3301_arg2 = LMUL_pow; + auto valid_reg_overlap_3301_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3301 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3301, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3300, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3301)); + setArg(call_illegal_fp_variable_width_3300, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3300, 1, vd); + setArg(call_illegal_fp_variable_width_3300, 2, vm); + setArg(call_illegal_fp_variable_width_3300, 3, illegal_fp_variable_width_3300_arg2); + setArg(call_illegal_fp_variable_width_3300, 4, illegal_fp_variable_width_3300_arg3); + setArg(call_illegal_fp_variable_width_3300, 5, illegal_fp_variable_width_3300_arg4); + setArg(call_illegal_fp_variable_width_3300, 6, illegal_fp_variable_width_3300_arg5); + setRet(call_illegal_fp_variable_width_3300, 0, ret_val_illegal_fp_variable_width_3300); + setArg(call_valid_reg_overlap_3301, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3301, 1, vs1); + setArg(call_valid_reg_overlap_3301, 2, vd); + setArg(call_valid_reg_overlap_3301, 3, valid_reg_overlap_3301_arg2); + setArg(call_valid_reg_overlap_3301, 4, valid_reg_overlap_3301_arg3); + setRet(call_valid_reg_overlap_3301, 0, ret_val_valid_reg_overlap_3301); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3303; + x86::Gp ret_val_sew_3303 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3303, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_ww_3302; + auto fp_vector_vector_ww_3302_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_ww_3302_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_ww_3302_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_ww_3302_arg10 = rm; + auto fp_vector_vector_ww_3302_arg11 = ret_val_sew_3303; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_ww_3302, &fp_vector_vector_ww, FuncSignature::build()); + setArg(call_sew_3303, 0, reinterpret_cast(this)); + setRet(call_sew_3303, 0, ret_val_sew_3303); + setArg(call_fp_vector_vector_ww_3302, 0, V); + setArg(call_fp_vector_vector_ww_3302, 1, 54); + setArg(call_fp_vector_vector_ww_3302, 2, 1); + setArg(call_fp_vector_vector_ww_3302, 3, fp_vector_vector_ww_3302_arg3); + setArg(call_fp_vector_vector_ww_3302, 4, fp_vector_vector_ww_3302_arg4); + setArg(call_fp_vector_vector_ww_3302, 5, fp_vector_vector_ww_3302_arg5); + setArg(call_fp_vector_vector_ww_3302, 6, vm); + setArg(call_fp_vector_vector_ww_3302, 7, vd); + setArg(call_fp_vector_vector_ww_3302, 8, vs2); + setArg(call_fp_vector_vector_ww_3302, 9, vs1); + setArg(call_fp_vector_vector_ww_3302, 10, fp_vector_vector_ww_3302_arg10); + setArg(call_fp_vector_vector_ww_3302, 11, fp_vector_vector_ww_3302_arg11); + InvokeNode* call_fget_flags_3304; + x86::Gp ret_val_fget_flags_3304 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3304, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3304; + setRet(call_fget_flags_3304, 0, ret_val_fget_flags_3304); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3305 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3305, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3305, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 748); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 749: VFMUL__VF */ + continuation_e __vfmul__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmul.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMUL__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 749); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3306; + x86::Gp ret_val_get_sew_pow_3306 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3306, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3307 = get_reg(cc, 8, false); + mov(cc, tmp3307, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3307, (ret_val_get_sew_pow_3306))), 8, false), ~ 1); + setArg(call_get_sew_pow_3306, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3306, 0, ret_val_get_sew_pow_3306); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3308; + auto illegal_fp_normal_3308_arg2 = SEW; + auto illegal_fp_normal_3308_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3308 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3308, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3308; + setArg(call_illegal_fp_normal_3308, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3308, 1, vd); + setArg(call_illegal_fp_normal_3308, 2, vm); + setArg(call_illegal_fp_normal_3308, 3, illegal_fp_normal_3308_arg2); + setArg(call_illegal_fp_normal_3308, 4, illegal_fp_normal_3308_arg3); + setRet(call_illegal_fp_normal_3308, 0, ret_val_illegal_fp_normal_3308); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3310; + x86::Gp ret_val_sew_3310 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3310, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3309; + auto fp_vector_imm_op_3309_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3309_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3309_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3309_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3309_arg10 = rm; + auto fp_vector_imm_op_3309_arg11 = ret_val_sew_3310; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3309, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3310, 0, reinterpret_cast(this)); + setRet(call_sew_3310, 0, ret_val_sew_3310); + setArg(call_fp_vector_imm_op_3309, 0, V); + setArg(call_fp_vector_imm_op_3309, 1, 36); + setArg(call_fp_vector_imm_op_3309, 2, 5); + setArg(call_fp_vector_imm_op_3309, 3, fp_vector_imm_op_3309_arg3); + setArg(call_fp_vector_imm_op_3309, 4, fp_vector_imm_op_3309_arg4); + setArg(call_fp_vector_imm_op_3309, 5, fp_vector_imm_op_3309_arg5); + setArg(call_fp_vector_imm_op_3309, 6, vm); + setArg(call_fp_vector_imm_op_3309, 7, vd); + setArg(call_fp_vector_imm_op_3309, 8, vs2); + setArg(call_fp_vector_imm_op_3309, 9, fp_vector_imm_op_3309_arg9); + setArg(call_fp_vector_imm_op_3309, 10, fp_vector_imm_op_3309_arg10); + setArg(call_fp_vector_imm_op_3309, 11, fp_vector_imm_op_3309_arg11); + InvokeNode* call_fget_flags_3311; + x86::Gp ret_val_fget_flags_3311 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3311, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3311; + setRet(call_fget_flags_3311, 0, ret_val_fget_flags_3311); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3312 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3312, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3312, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 749); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 750: VFMUL__VV */ + continuation_e __vfmul__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vfmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMUL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 750); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3313; + x86::Gp ret_val_get_sew_pow_3313 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3313, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3314 = get_reg(cc, 8, false); + mov(cc, tmp3314, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3314, (ret_val_get_sew_pow_3313))), 8, false), ~ 1); + setArg(call_get_sew_pow_3313, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3313, 0, ret_val_get_sew_pow_3313); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3315; + auto illegal_fp_normal_3315_arg2 = SEW; + auto illegal_fp_normal_3315_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3315 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3315, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3315; + setArg(call_illegal_fp_normal_3315, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3315, 1, vd); + setArg(call_illegal_fp_normal_3315, 2, vm); + setArg(call_illegal_fp_normal_3315, 3, illegal_fp_normal_3315_arg2); + setArg(call_illegal_fp_normal_3315, 4, illegal_fp_normal_3315_arg3); + setRet(call_illegal_fp_normal_3315, 0, ret_val_illegal_fp_normal_3315); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3317; + x86::Gp ret_val_sew_3317 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3317, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3316; + auto fp_vector_vector_op_3316_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3316_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3316_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3316_arg10 = rm; + auto fp_vector_vector_op_3316_arg11 = ret_val_sew_3317; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3316, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3317, 0, reinterpret_cast(this)); + setRet(call_sew_3317, 0, ret_val_sew_3317); + setArg(call_fp_vector_vector_op_3316, 0, V); + setArg(call_fp_vector_vector_op_3316, 1, 36); + setArg(call_fp_vector_vector_op_3316, 2, 1); + setArg(call_fp_vector_vector_op_3316, 3, fp_vector_vector_op_3316_arg3); + setArg(call_fp_vector_vector_op_3316, 4, fp_vector_vector_op_3316_arg4); + setArg(call_fp_vector_vector_op_3316, 5, fp_vector_vector_op_3316_arg5); + setArg(call_fp_vector_vector_op_3316, 6, vm); + setArg(call_fp_vector_vector_op_3316, 7, vd); + setArg(call_fp_vector_vector_op_3316, 8, vs2); + setArg(call_fp_vector_vector_op_3316, 9, vs1); + setArg(call_fp_vector_vector_op_3316, 10, fp_vector_vector_op_3316_arg10); + setArg(call_fp_vector_vector_op_3316, 11, fp_vector_vector_op_3316_arg11); + InvokeNode* call_fget_flags_3318; + x86::Gp ret_val_fget_flags_3318 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3318, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3318; + setRet(call_fget_flags_3318, 0, ret_val_fget_flags_3318); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3319 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3319, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3319, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 750); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 751: VFDIV__VF */ + continuation_e __vfdiv__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfdiv.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFDIV__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 751); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3320; + x86::Gp ret_val_get_sew_pow_3320 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3320, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3321 = get_reg(cc, 8, false); + mov(cc, tmp3321, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3321, (ret_val_get_sew_pow_3320))), 8, false), ~ 1); + setArg(call_get_sew_pow_3320, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3320, 0, ret_val_get_sew_pow_3320); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3322; + auto illegal_fp_normal_3322_arg2 = SEW; + auto illegal_fp_normal_3322_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3322 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3322, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3322; + setArg(call_illegal_fp_normal_3322, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3322, 1, vd); + setArg(call_illegal_fp_normal_3322, 2, vm); + setArg(call_illegal_fp_normal_3322, 3, illegal_fp_normal_3322_arg2); + setArg(call_illegal_fp_normal_3322, 4, illegal_fp_normal_3322_arg3); + setRet(call_illegal_fp_normal_3322, 0, ret_val_illegal_fp_normal_3322); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3324; + x86::Gp ret_val_sew_3324 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3324, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3323; + auto fp_vector_imm_op_3323_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3323_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3323_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3323_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3323_arg10 = rm; + auto fp_vector_imm_op_3323_arg11 = ret_val_sew_3324; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3323, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3324, 0, reinterpret_cast(this)); + setRet(call_sew_3324, 0, ret_val_sew_3324); + setArg(call_fp_vector_imm_op_3323, 0, V); + setArg(call_fp_vector_imm_op_3323, 1, 32); + setArg(call_fp_vector_imm_op_3323, 2, 5); + setArg(call_fp_vector_imm_op_3323, 3, fp_vector_imm_op_3323_arg3); + setArg(call_fp_vector_imm_op_3323, 4, fp_vector_imm_op_3323_arg4); + setArg(call_fp_vector_imm_op_3323, 5, fp_vector_imm_op_3323_arg5); + setArg(call_fp_vector_imm_op_3323, 6, vm); + setArg(call_fp_vector_imm_op_3323, 7, vd); + setArg(call_fp_vector_imm_op_3323, 8, vs2); + setArg(call_fp_vector_imm_op_3323, 9, fp_vector_imm_op_3323_arg9); + setArg(call_fp_vector_imm_op_3323, 10, fp_vector_imm_op_3323_arg10); + setArg(call_fp_vector_imm_op_3323, 11, fp_vector_imm_op_3323_arg11); + InvokeNode* call_fget_flags_3325; + x86::Gp ret_val_fget_flags_3325 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3325, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3325; + setRet(call_fget_flags_3325, 0, ret_val_fget_flags_3325); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3326 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3326, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3326, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 751); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 752: VFDIV__VV */ + continuation_e __vfdiv__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm},", fmt::arg("mnemonic", "vfdiv.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFDIV__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 752); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3327; + x86::Gp ret_val_get_sew_pow_3327 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3327, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3328 = get_reg(cc, 8, false); + mov(cc, tmp3328, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3328, (ret_val_get_sew_pow_3327))), 8, false), ~ 1); + setArg(call_get_sew_pow_3327, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3327, 0, ret_val_get_sew_pow_3327); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3329; + auto illegal_fp_normal_3329_arg2 = SEW; + auto illegal_fp_normal_3329_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3329 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3329, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3329; + setArg(call_illegal_fp_normal_3329, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3329, 1, vd); + setArg(call_illegal_fp_normal_3329, 2, vm); + setArg(call_illegal_fp_normal_3329, 3, illegal_fp_normal_3329_arg2); + setArg(call_illegal_fp_normal_3329, 4, illegal_fp_normal_3329_arg3); + setRet(call_illegal_fp_normal_3329, 0, ret_val_illegal_fp_normal_3329); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3331; + x86::Gp ret_val_sew_3331 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3331, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3330; + auto fp_vector_vector_op_3330_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3330_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3330_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3330_arg10 = rm; + auto fp_vector_vector_op_3330_arg11 = ret_val_sew_3331; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3330, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3331, 0, reinterpret_cast(this)); + setRet(call_sew_3331, 0, ret_val_sew_3331); + setArg(call_fp_vector_vector_op_3330, 0, V); + setArg(call_fp_vector_vector_op_3330, 1, 32); + setArg(call_fp_vector_vector_op_3330, 2, 1); + setArg(call_fp_vector_vector_op_3330, 3, fp_vector_vector_op_3330_arg3); + setArg(call_fp_vector_vector_op_3330, 4, fp_vector_vector_op_3330_arg4); + setArg(call_fp_vector_vector_op_3330, 5, fp_vector_vector_op_3330_arg5); + setArg(call_fp_vector_vector_op_3330, 6, vm); + setArg(call_fp_vector_vector_op_3330, 7, vd); + setArg(call_fp_vector_vector_op_3330, 8, vs2); + setArg(call_fp_vector_vector_op_3330, 9, vs1); + setArg(call_fp_vector_vector_op_3330, 10, fp_vector_vector_op_3330_arg10); + setArg(call_fp_vector_vector_op_3330, 11, fp_vector_vector_op_3330_arg11); + InvokeNode* call_fget_flags_3332; + x86::Gp ret_val_fget_flags_3332 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3332, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3332; + setRet(call_fget_flags_3332, 0, ret_val_fget_flags_3332); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3333 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3333, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3333, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 752); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 753: VFRDIV__VF */ + continuation_e __vfrdiv__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfrdiv.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFRDIV__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 753); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3334; + x86::Gp ret_val_get_sew_pow_3334 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3334, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3335 = get_reg(cc, 8, false); + mov(cc, tmp3335, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3335, (ret_val_get_sew_pow_3334))), 8, false), ~ 1); + setArg(call_get_sew_pow_3334, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3334, 0, ret_val_get_sew_pow_3334); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3336; + auto illegal_fp_normal_3336_arg2 = SEW; + auto illegal_fp_normal_3336_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3336 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3336, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3336; + setArg(call_illegal_fp_normal_3336, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3336, 1, vd); + setArg(call_illegal_fp_normal_3336, 2, vm); + setArg(call_illegal_fp_normal_3336, 3, illegal_fp_normal_3336_arg2); + setArg(call_illegal_fp_normal_3336, 4, illegal_fp_normal_3336_arg3); + setRet(call_illegal_fp_normal_3336, 0, ret_val_illegal_fp_normal_3336); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3338; + x86::Gp ret_val_sew_3338 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3338, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3337; + auto fp_vector_imm_op_3337_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3337_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3337_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3337_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3337_arg10 = rm; + auto fp_vector_imm_op_3337_arg11 = ret_val_sew_3338; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3337, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3338, 0, reinterpret_cast(this)); + setRet(call_sew_3338, 0, ret_val_sew_3338); + setArg(call_fp_vector_imm_op_3337, 0, V); + setArg(call_fp_vector_imm_op_3337, 1, 33); + setArg(call_fp_vector_imm_op_3337, 2, 5); + setArg(call_fp_vector_imm_op_3337, 3, fp_vector_imm_op_3337_arg3); + setArg(call_fp_vector_imm_op_3337, 4, fp_vector_imm_op_3337_arg4); + setArg(call_fp_vector_imm_op_3337, 5, fp_vector_imm_op_3337_arg5); + setArg(call_fp_vector_imm_op_3337, 6, vm); + setArg(call_fp_vector_imm_op_3337, 7, vd); + setArg(call_fp_vector_imm_op_3337, 8, vs2); + setArg(call_fp_vector_imm_op_3337, 9, fp_vector_imm_op_3337_arg9); + setArg(call_fp_vector_imm_op_3337, 10, fp_vector_imm_op_3337_arg10); + setArg(call_fp_vector_imm_op_3337, 11, fp_vector_imm_op_3337_arg11); + InvokeNode* call_fget_flags_3339; + x86::Gp ret_val_fget_flags_3339 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3339, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3339; + setRet(call_fget_flags_3339, 0, ret_val_fget_flags_3339); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3340 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3340, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3340, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 753); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 754: VFWMUL__VF */ + continuation_e __vfwmul__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmul.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMUL__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 754); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3341; + x86::Gp ret_val_get_sew_pow_3341 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3341, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3342 = get_reg(cc, 8, false); + mov(cc, tmp3342, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3342, (ret_val_get_sew_pow_3341))), 8, false), ~ 1); + setArg(call_get_sew_pow_3341, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3341, 0, ret_val_get_sew_pow_3341); + InvokeNode* call_get_lmul_pow_3343; + x86::Gp ret_val_get_lmul_pow_3343 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3343, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3343; + setArg(call_get_lmul_pow_3343, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3343, 0, ret_val_get_lmul_pow_3343); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3344; + auto illegal_fp_variable_width_3344_arg2 = SEW; + auto illegal_fp_variable_width_3344_arg3 = rm; + auto illegal_fp_variable_width_3344_arg4 = SEW_widen; + auto illegal_fp_variable_width_3344_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3344 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3344, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3345; + auto valid_reg_overlap_3345_arg2 = LMUL_pow; + auto valid_reg_overlap_3345_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3345 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3345, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3344, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3345)); + setArg(call_illegal_fp_variable_width_3344, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3344, 1, vd); + setArg(call_illegal_fp_variable_width_3344, 2, vm); + setArg(call_illegal_fp_variable_width_3344, 3, illegal_fp_variable_width_3344_arg2); + setArg(call_illegal_fp_variable_width_3344, 4, illegal_fp_variable_width_3344_arg3); + setArg(call_illegal_fp_variable_width_3344, 5, illegal_fp_variable_width_3344_arg4); + setArg(call_illegal_fp_variable_width_3344, 6, illegal_fp_variable_width_3344_arg5); + setRet(call_illegal_fp_variable_width_3344, 0, ret_val_illegal_fp_variable_width_3344); + setArg(call_valid_reg_overlap_3345, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3345, 1, vs2); + setArg(call_valid_reg_overlap_3345, 2, vd); + setArg(call_valid_reg_overlap_3345, 3, valid_reg_overlap_3345_arg2); + setArg(call_valid_reg_overlap_3345, 4, valid_reg_overlap_3345_arg3); + setRet(call_valid_reg_overlap_3345, 0, ret_val_valid_reg_overlap_3345); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3347; + x86::Gp ret_val_sew_3347 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3347, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3346; + auto fp_vector_imm_wv_3346_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3346_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3346_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3346_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_wv_3346_arg10 = rm; + auto fp_vector_imm_wv_3346_arg11 = ret_val_sew_3347; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3346, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3347, 0, reinterpret_cast(this)); + setRet(call_sew_3347, 0, ret_val_sew_3347); + setArg(call_fp_vector_imm_wv_3346, 0, V); + setArg(call_fp_vector_imm_wv_3346, 1, 56); + setArg(call_fp_vector_imm_wv_3346, 2, 5); + setArg(call_fp_vector_imm_wv_3346, 3, fp_vector_imm_wv_3346_arg3); + setArg(call_fp_vector_imm_wv_3346, 4, fp_vector_imm_wv_3346_arg4); + setArg(call_fp_vector_imm_wv_3346, 5, fp_vector_imm_wv_3346_arg5); + setArg(call_fp_vector_imm_wv_3346, 6, vm); + setArg(call_fp_vector_imm_wv_3346, 7, vd); + setArg(call_fp_vector_imm_wv_3346, 8, vs2); + setArg(call_fp_vector_imm_wv_3346, 9, fp_vector_imm_wv_3346_arg9); + setArg(call_fp_vector_imm_wv_3346, 10, fp_vector_imm_wv_3346_arg10); + setArg(call_fp_vector_imm_wv_3346, 11, fp_vector_imm_wv_3346_arg11); + InvokeNode* call_fget_flags_3348; + x86::Gp ret_val_fget_flags_3348 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3348, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3348; + setRet(call_fget_flags_3348, 0, ret_val_fget_flags_3348); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3349 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3349, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3349, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 754); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 755: VFWMUL__VV */ + continuation_e __vfwmul__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmul.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMUL__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 755); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3350; + x86::Gp ret_val_get_sew_pow_3350 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3350, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3351 = get_reg(cc, 8, false); + mov(cc, tmp3351, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3351, (ret_val_get_sew_pow_3350))), 8, false), ~ 1); + setArg(call_get_sew_pow_3350, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3350, 0, ret_val_get_sew_pow_3350); + InvokeNode* call_get_lmul_pow_3352; + x86::Gp ret_val_get_lmul_pow_3352 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3352, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3352; + setArg(call_get_lmul_pow_3352, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3352, 0, ret_val_get_lmul_pow_3352); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3353; + auto illegal_fp_variable_width_3353_arg2 = SEW; + auto illegal_fp_variable_width_3353_arg3 = rm; + auto illegal_fp_variable_width_3353_arg4 = SEW_widen; + auto illegal_fp_variable_width_3353_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3353 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3353, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3354; + auto valid_reg_overlap_3354_arg2 = LMUL_pow; + auto valid_reg_overlap_3354_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3354 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3354, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3355; + auto valid_reg_overlap_3355_arg2 = LMUL_pow; + auto valid_reg_overlap_3355_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3355 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3355, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3353, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3354)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3355)); + setArg(call_illegal_fp_variable_width_3353, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3353, 1, vd); + setArg(call_illegal_fp_variable_width_3353, 2, vm); + setArg(call_illegal_fp_variable_width_3353, 3, illegal_fp_variable_width_3353_arg2); + setArg(call_illegal_fp_variable_width_3353, 4, illegal_fp_variable_width_3353_arg3); + setArg(call_illegal_fp_variable_width_3353, 5, illegal_fp_variable_width_3353_arg4); + setArg(call_illegal_fp_variable_width_3353, 6, illegal_fp_variable_width_3353_arg5); + setRet(call_illegal_fp_variable_width_3353, 0, ret_val_illegal_fp_variable_width_3353); + setArg(call_valid_reg_overlap_3354, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3354, 1, vs1); + setArg(call_valid_reg_overlap_3354, 2, vd); + setArg(call_valid_reg_overlap_3354, 3, valid_reg_overlap_3354_arg2); + setArg(call_valid_reg_overlap_3354, 4, valid_reg_overlap_3354_arg3); + setRet(call_valid_reg_overlap_3354, 0, ret_val_valid_reg_overlap_3354); + setArg(call_valid_reg_overlap_3355, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3355, 1, vs2); + setArg(call_valid_reg_overlap_3355, 2, vd); + setArg(call_valid_reg_overlap_3355, 3, valid_reg_overlap_3355_arg2); + setArg(call_valid_reg_overlap_3355, 4, valid_reg_overlap_3355_arg3); + setRet(call_valid_reg_overlap_3355, 0, ret_val_valid_reg_overlap_3355); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3357; + x86::Gp ret_val_sew_3357 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3357, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3356; + auto fp_vector_vector_wv_3356_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3356_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3356_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3356_arg10 = rm; + auto fp_vector_vector_wv_3356_arg11 = ret_val_sew_3357; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3356, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3357, 0, reinterpret_cast(this)); + setRet(call_sew_3357, 0, ret_val_sew_3357); + setArg(call_fp_vector_vector_wv_3356, 0, V); + setArg(call_fp_vector_vector_wv_3356, 1, 56); + setArg(call_fp_vector_vector_wv_3356, 2, 1); + setArg(call_fp_vector_vector_wv_3356, 3, fp_vector_vector_wv_3356_arg3); + setArg(call_fp_vector_vector_wv_3356, 4, fp_vector_vector_wv_3356_arg4); + setArg(call_fp_vector_vector_wv_3356, 5, fp_vector_vector_wv_3356_arg5); + setArg(call_fp_vector_vector_wv_3356, 6, vm); + setArg(call_fp_vector_vector_wv_3356, 7, vd); + setArg(call_fp_vector_vector_wv_3356, 8, vs2); + setArg(call_fp_vector_vector_wv_3356, 9, vs1); + setArg(call_fp_vector_vector_wv_3356, 10, fp_vector_vector_wv_3356_arg10); + setArg(call_fp_vector_vector_wv_3356, 11, fp_vector_vector_wv_3356_arg11); + InvokeNode* call_fget_flags_3358; + x86::Gp ret_val_fget_flags_3358 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3358, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3358; + setRet(call_fget_flags_3358, 0, ret_val_fget_flags_3358); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3359 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3359, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3359, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 755); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 756: VFMACC__VF */ + continuation_e __vfmacc__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMACC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 756); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3360; + x86::Gp ret_val_get_sew_pow_3360 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3360, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3361 = get_reg(cc, 8, false); + mov(cc, tmp3361, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3361, (ret_val_get_sew_pow_3360))), 8, false), ~ 1); + setArg(call_get_sew_pow_3360, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3360, 0, ret_val_get_sew_pow_3360); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3362; + auto illegal_fp_normal_3362_arg2 = SEW; + auto illegal_fp_normal_3362_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3362 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3362, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3362; + setArg(call_illegal_fp_normal_3362, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3362, 1, vd); + setArg(call_illegal_fp_normal_3362, 2, vm); + setArg(call_illegal_fp_normal_3362, 3, illegal_fp_normal_3362_arg2); + setArg(call_illegal_fp_normal_3362, 4, illegal_fp_normal_3362_arg3); + setRet(call_illegal_fp_normal_3362, 0, ret_val_illegal_fp_normal_3362); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3364; + x86::Gp ret_val_sew_3364 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3364, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3363; + auto fp_vector_imm_op_3363_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3363_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3363_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3363_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3363_arg10 = rm; + auto fp_vector_imm_op_3363_arg11 = ret_val_sew_3364; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3363, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3364, 0, reinterpret_cast(this)); + setRet(call_sew_3364, 0, ret_val_sew_3364); + setArg(call_fp_vector_imm_op_3363, 0, V); + setArg(call_fp_vector_imm_op_3363, 1, 44); + setArg(call_fp_vector_imm_op_3363, 2, 5); + setArg(call_fp_vector_imm_op_3363, 3, fp_vector_imm_op_3363_arg3); + setArg(call_fp_vector_imm_op_3363, 4, fp_vector_imm_op_3363_arg4); + setArg(call_fp_vector_imm_op_3363, 5, fp_vector_imm_op_3363_arg5); + setArg(call_fp_vector_imm_op_3363, 6, vm); + setArg(call_fp_vector_imm_op_3363, 7, vd); + setArg(call_fp_vector_imm_op_3363, 8, vs2); + setArg(call_fp_vector_imm_op_3363, 9, fp_vector_imm_op_3363_arg9); + setArg(call_fp_vector_imm_op_3363, 10, fp_vector_imm_op_3363_arg10); + setArg(call_fp_vector_imm_op_3363, 11, fp_vector_imm_op_3363_arg11); + InvokeNode* call_fget_flags_3365; + x86::Gp ret_val_fget_flags_3365 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3365, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3365; + setRet(call_fget_flags_3365, 0, ret_val_fget_flags_3365); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3366 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3366, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3366, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 756); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 757: VFMACC__VV */ + continuation_e __vfmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 757); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3367; + x86::Gp ret_val_get_sew_pow_3367 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3367, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3368 = get_reg(cc, 8, false); + mov(cc, tmp3368, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3368, (ret_val_get_sew_pow_3367))), 8, false), ~ 1); + setArg(call_get_sew_pow_3367, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3367, 0, ret_val_get_sew_pow_3367); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3369; + auto illegal_fp_normal_3369_arg2 = SEW; + auto illegal_fp_normal_3369_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3369 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3369, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3369; + setArg(call_illegal_fp_normal_3369, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3369, 1, vd); + setArg(call_illegal_fp_normal_3369, 2, vm); + setArg(call_illegal_fp_normal_3369, 3, illegal_fp_normal_3369_arg2); + setArg(call_illegal_fp_normal_3369, 4, illegal_fp_normal_3369_arg3); + setRet(call_illegal_fp_normal_3369, 0, ret_val_illegal_fp_normal_3369); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3371; + x86::Gp ret_val_sew_3371 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3371, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3370; + auto fp_vector_vector_op_3370_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3370_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3370_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3370_arg10 = rm; + auto fp_vector_vector_op_3370_arg11 = ret_val_sew_3371; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3370, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3371, 0, reinterpret_cast(this)); + setRet(call_sew_3371, 0, ret_val_sew_3371); + setArg(call_fp_vector_vector_op_3370, 0, V); + setArg(call_fp_vector_vector_op_3370, 1, 44); + setArg(call_fp_vector_vector_op_3370, 2, 1); + setArg(call_fp_vector_vector_op_3370, 3, fp_vector_vector_op_3370_arg3); + setArg(call_fp_vector_vector_op_3370, 4, fp_vector_vector_op_3370_arg4); + setArg(call_fp_vector_vector_op_3370, 5, fp_vector_vector_op_3370_arg5); + setArg(call_fp_vector_vector_op_3370, 6, vm); + setArg(call_fp_vector_vector_op_3370, 7, vd); + setArg(call_fp_vector_vector_op_3370, 8, vs2); + setArg(call_fp_vector_vector_op_3370, 9, vs1); + setArg(call_fp_vector_vector_op_3370, 10, fp_vector_vector_op_3370_arg10); + setArg(call_fp_vector_vector_op_3370, 11, fp_vector_vector_op_3370_arg11); + InvokeNode* call_fget_flags_3372; + x86::Gp ret_val_fget_flags_3372 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3372, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3372; + setRet(call_fget_flags_3372, 0, ret_val_fget_flags_3372); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3373 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3373, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3373, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 757); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 758: VFNMACC__VF */ + continuation_e __vfnmacc__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMACC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 758); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3374; + x86::Gp ret_val_get_sew_pow_3374 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3374, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3375 = get_reg(cc, 8, false); + mov(cc, tmp3375, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3375, (ret_val_get_sew_pow_3374))), 8, false), ~ 1); + setArg(call_get_sew_pow_3374, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3374, 0, ret_val_get_sew_pow_3374); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3376; + auto illegal_fp_normal_3376_arg2 = SEW; + auto illegal_fp_normal_3376_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3376 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3376, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3376; + setArg(call_illegal_fp_normal_3376, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3376, 1, vd); + setArg(call_illegal_fp_normal_3376, 2, vm); + setArg(call_illegal_fp_normal_3376, 3, illegal_fp_normal_3376_arg2); + setArg(call_illegal_fp_normal_3376, 4, illegal_fp_normal_3376_arg3); + setRet(call_illegal_fp_normal_3376, 0, ret_val_illegal_fp_normal_3376); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3378; + x86::Gp ret_val_sew_3378 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3378, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3377; + auto fp_vector_imm_op_3377_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3377_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3377_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3377_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3377_arg10 = rm; + auto fp_vector_imm_op_3377_arg11 = ret_val_sew_3378; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3377, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3378, 0, reinterpret_cast(this)); + setRet(call_sew_3378, 0, ret_val_sew_3378); + setArg(call_fp_vector_imm_op_3377, 0, V); + setArg(call_fp_vector_imm_op_3377, 1, 45); + setArg(call_fp_vector_imm_op_3377, 2, 5); + setArg(call_fp_vector_imm_op_3377, 3, fp_vector_imm_op_3377_arg3); + setArg(call_fp_vector_imm_op_3377, 4, fp_vector_imm_op_3377_arg4); + setArg(call_fp_vector_imm_op_3377, 5, fp_vector_imm_op_3377_arg5); + setArg(call_fp_vector_imm_op_3377, 6, vm); + setArg(call_fp_vector_imm_op_3377, 7, vd); + setArg(call_fp_vector_imm_op_3377, 8, vs2); + setArg(call_fp_vector_imm_op_3377, 9, fp_vector_imm_op_3377_arg9); + setArg(call_fp_vector_imm_op_3377, 10, fp_vector_imm_op_3377_arg10); + setArg(call_fp_vector_imm_op_3377, 11, fp_vector_imm_op_3377_arg11); + InvokeNode* call_fget_flags_3379; + x86::Gp ret_val_fget_flags_3379 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3379, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3379; + setRet(call_fget_flags_3379, 0, ret_val_fget_flags_3379); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3380 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3380, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3380, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 758); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 759: VFNMACC__VV */ + continuation_e __vfnmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 759); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3381; + x86::Gp ret_val_get_sew_pow_3381 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3381, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3382 = get_reg(cc, 8, false); + mov(cc, tmp3382, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3382, (ret_val_get_sew_pow_3381))), 8, false), ~ 1); + setArg(call_get_sew_pow_3381, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3381, 0, ret_val_get_sew_pow_3381); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3383; + auto illegal_fp_normal_3383_arg2 = SEW; + auto illegal_fp_normal_3383_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3383 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3383, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3383; + setArg(call_illegal_fp_normal_3383, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3383, 1, vd); + setArg(call_illegal_fp_normal_3383, 2, vm); + setArg(call_illegal_fp_normal_3383, 3, illegal_fp_normal_3383_arg2); + setArg(call_illegal_fp_normal_3383, 4, illegal_fp_normal_3383_arg3); + setRet(call_illegal_fp_normal_3383, 0, ret_val_illegal_fp_normal_3383); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3385; + x86::Gp ret_val_sew_3385 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3385, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3384; + auto fp_vector_vector_op_3384_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3384_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3384_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3384_arg10 = rm; + auto fp_vector_vector_op_3384_arg11 = ret_val_sew_3385; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3384, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3385, 0, reinterpret_cast(this)); + setRet(call_sew_3385, 0, ret_val_sew_3385); + setArg(call_fp_vector_vector_op_3384, 0, V); + setArg(call_fp_vector_vector_op_3384, 1, 45); + setArg(call_fp_vector_vector_op_3384, 2, 1); + setArg(call_fp_vector_vector_op_3384, 3, fp_vector_vector_op_3384_arg3); + setArg(call_fp_vector_vector_op_3384, 4, fp_vector_vector_op_3384_arg4); + setArg(call_fp_vector_vector_op_3384, 5, fp_vector_vector_op_3384_arg5); + setArg(call_fp_vector_vector_op_3384, 6, vm); + setArg(call_fp_vector_vector_op_3384, 7, vd); + setArg(call_fp_vector_vector_op_3384, 8, vs2); + setArg(call_fp_vector_vector_op_3384, 9, vs1); + setArg(call_fp_vector_vector_op_3384, 10, fp_vector_vector_op_3384_arg10); + setArg(call_fp_vector_vector_op_3384, 11, fp_vector_vector_op_3384_arg11); + InvokeNode* call_fget_flags_3386; + x86::Gp ret_val_fget_flags_3386 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3386, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3386; + setRet(call_fget_flags_3386, 0, ret_val_fget_flags_3386); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3387 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3387, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3387, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 759); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 760: VFMSAC__VF */ + continuation_e __vfmsac__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMSAC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 760); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3388; + x86::Gp ret_val_get_sew_pow_3388 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3388, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3389 = get_reg(cc, 8, false); + mov(cc, tmp3389, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3389, (ret_val_get_sew_pow_3388))), 8, false), ~ 1); + setArg(call_get_sew_pow_3388, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3388, 0, ret_val_get_sew_pow_3388); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3390; + auto illegal_fp_normal_3390_arg2 = SEW; + auto illegal_fp_normal_3390_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3390 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3390, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3390; + setArg(call_illegal_fp_normal_3390, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3390, 1, vd); + setArg(call_illegal_fp_normal_3390, 2, vm); + setArg(call_illegal_fp_normal_3390, 3, illegal_fp_normal_3390_arg2); + setArg(call_illegal_fp_normal_3390, 4, illegal_fp_normal_3390_arg3); + setRet(call_illegal_fp_normal_3390, 0, ret_val_illegal_fp_normal_3390); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3392; + x86::Gp ret_val_sew_3392 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3392, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3391; + auto fp_vector_imm_op_3391_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3391_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3391_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3391_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3391_arg10 = rm; + auto fp_vector_imm_op_3391_arg11 = ret_val_sew_3392; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3391, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3392, 0, reinterpret_cast(this)); + setRet(call_sew_3392, 0, ret_val_sew_3392); + setArg(call_fp_vector_imm_op_3391, 0, V); + setArg(call_fp_vector_imm_op_3391, 1, 46); + setArg(call_fp_vector_imm_op_3391, 2, 5); + setArg(call_fp_vector_imm_op_3391, 3, fp_vector_imm_op_3391_arg3); + setArg(call_fp_vector_imm_op_3391, 4, fp_vector_imm_op_3391_arg4); + setArg(call_fp_vector_imm_op_3391, 5, fp_vector_imm_op_3391_arg5); + setArg(call_fp_vector_imm_op_3391, 6, vm); + setArg(call_fp_vector_imm_op_3391, 7, vd); + setArg(call_fp_vector_imm_op_3391, 8, vs2); + setArg(call_fp_vector_imm_op_3391, 9, fp_vector_imm_op_3391_arg9); + setArg(call_fp_vector_imm_op_3391, 10, fp_vector_imm_op_3391_arg10); + setArg(call_fp_vector_imm_op_3391, 11, fp_vector_imm_op_3391_arg11); + InvokeNode* call_fget_flags_3393; + x86::Gp ret_val_fget_flags_3393 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3393, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3393; + setRet(call_fget_flags_3393, 0, ret_val_fget_flags_3393); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3394 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3394, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3394, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 760); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 761: VFMSAC__VV */ + continuation_e __vfmsac__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMSAC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 761); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3395; + x86::Gp ret_val_get_sew_pow_3395 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3395, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3396 = get_reg(cc, 8, false); + mov(cc, tmp3396, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3396, (ret_val_get_sew_pow_3395))), 8, false), ~ 1); + setArg(call_get_sew_pow_3395, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3395, 0, ret_val_get_sew_pow_3395); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3397; + auto illegal_fp_normal_3397_arg2 = SEW; + auto illegal_fp_normal_3397_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3397 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3397, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3397; + setArg(call_illegal_fp_normal_3397, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3397, 1, vd); + setArg(call_illegal_fp_normal_3397, 2, vm); + setArg(call_illegal_fp_normal_3397, 3, illegal_fp_normal_3397_arg2); + setArg(call_illegal_fp_normal_3397, 4, illegal_fp_normal_3397_arg3); + setRet(call_illegal_fp_normal_3397, 0, ret_val_illegal_fp_normal_3397); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3399; + x86::Gp ret_val_sew_3399 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3399, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3398; + auto fp_vector_vector_op_3398_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3398_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3398_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3398_arg10 = rm; + auto fp_vector_vector_op_3398_arg11 = ret_val_sew_3399; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3398, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3399, 0, reinterpret_cast(this)); + setRet(call_sew_3399, 0, ret_val_sew_3399); + setArg(call_fp_vector_vector_op_3398, 0, V); + setArg(call_fp_vector_vector_op_3398, 1, 46); + setArg(call_fp_vector_vector_op_3398, 2, 1); + setArg(call_fp_vector_vector_op_3398, 3, fp_vector_vector_op_3398_arg3); + setArg(call_fp_vector_vector_op_3398, 4, fp_vector_vector_op_3398_arg4); + setArg(call_fp_vector_vector_op_3398, 5, fp_vector_vector_op_3398_arg5); + setArg(call_fp_vector_vector_op_3398, 6, vm); + setArg(call_fp_vector_vector_op_3398, 7, vd); + setArg(call_fp_vector_vector_op_3398, 8, vs2); + setArg(call_fp_vector_vector_op_3398, 9, vs1); + setArg(call_fp_vector_vector_op_3398, 10, fp_vector_vector_op_3398_arg10); + setArg(call_fp_vector_vector_op_3398, 11, fp_vector_vector_op_3398_arg11); + InvokeNode* call_fget_flags_3400; + x86::Gp ret_val_fget_flags_3400 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3400, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3400; + setRet(call_fget_flags_3400, 0, ret_val_fget_flags_3400); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3401 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3401, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3401, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 761); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 762: VFNMSAC__VF */ + continuation_e __vfnmsac__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMSAC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 762); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3402; + x86::Gp ret_val_get_sew_pow_3402 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3402, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3403 = get_reg(cc, 8, false); + mov(cc, tmp3403, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3403, (ret_val_get_sew_pow_3402))), 8, false), ~ 1); + setArg(call_get_sew_pow_3402, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3402, 0, ret_val_get_sew_pow_3402); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3404; + auto illegal_fp_normal_3404_arg2 = SEW; + auto illegal_fp_normal_3404_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3404 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3404, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3404; + setArg(call_illegal_fp_normal_3404, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3404, 1, vd); + setArg(call_illegal_fp_normal_3404, 2, vm); + setArg(call_illegal_fp_normal_3404, 3, illegal_fp_normal_3404_arg2); + setArg(call_illegal_fp_normal_3404, 4, illegal_fp_normal_3404_arg3); + setRet(call_illegal_fp_normal_3404, 0, ret_val_illegal_fp_normal_3404); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3406; + x86::Gp ret_val_sew_3406 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3406, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3405; + auto fp_vector_imm_op_3405_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3405_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3405_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3405_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3405_arg10 = rm; + auto fp_vector_imm_op_3405_arg11 = ret_val_sew_3406; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3405, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3406, 0, reinterpret_cast(this)); + setRet(call_sew_3406, 0, ret_val_sew_3406); + setArg(call_fp_vector_imm_op_3405, 0, V); + setArg(call_fp_vector_imm_op_3405, 1, 47); + setArg(call_fp_vector_imm_op_3405, 2, 5); + setArg(call_fp_vector_imm_op_3405, 3, fp_vector_imm_op_3405_arg3); + setArg(call_fp_vector_imm_op_3405, 4, fp_vector_imm_op_3405_arg4); + setArg(call_fp_vector_imm_op_3405, 5, fp_vector_imm_op_3405_arg5); + setArg(call_fp_vector_imm_op_3405, 6, vm); + setArg(call_fp_vector_imm_op_3405, 7, vd); + setArg(call_fp_vector_imm_op_3405, 8, vs2); + setArg(call_fp_vector_imm_op_3405, 9, fp_vector_imm_op_3405_arg9); + setArg(call_fp_vector_imm_op_3405, 10, fp_vector_imm_op_3405_arg10); + setArg(call_fp_vector_imm_op_3405, 11, fp_vector_imm_op_3405_arg11); + InvokeNode* call_fget_flags_3407; + x86::Gp ret_val_fget_flags_3407 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3407, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3407; + setRet(call_fget_flags_3407, 0, ret_val_fget_flags_3407); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3408 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3408, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3408, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 762); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 763: VFNMSAC__VV */ + continuation_e __vfnmsac__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMSAC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 763); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3409; + x86::Gp ret_val_get_sew_pow_3409 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3409, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3410 = get_reg(cc, 8, false); + mov(cc, tmp3410, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3410, (ret_val_get_sew_pow_3409))), 8, false), ~ 1); + setArg(call_get_sew_pow_3409, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3409, 0, ret_val_get_sew_pow_3409); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3411; + auto illegal_fp_normal_3411_arg2 = SEW; + auto illegal_fp_normal_3411_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3411 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3411, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3411; + setArg(call_illegal_fp_normal_3411, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3411, 1, vd); + setArg(call_illegal_fp_normal_3411, 2, vm); + setArg(call_illegal_fp_normal_3411, 3, illegal_fp_normal_3411_arg2); + setArg(call_illegal_fp_normal_3411, 4, illegal_fp_normal_3411_arg3); + setRet(call_illegal_fp_normal_3411, 0, ret_val_illegal_fp_normal_3411); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3413; + x86::Gp ret_val_sew_3413 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3413, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3412; + auto fp_vector_vector_op_3412_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3412_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3412_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3412_arg10 = rm; + auto fp_vector_vector_op_3412_arg11 = ret_val_sew_3413; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3412, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3413, 0, reinterpret_cast(this)); + setRet(call_sew_3413, 0, ret_val_sew_3413); + setArg(call_fp_vector_vector_op_3412, 0, V); + setArg(call_fp_vector_vector_op_3412, 1, 47); + setArg(call_fp_vector_vector_op_3412, 2, 1); + setArg(call_fp_vector_vector_op_3412, 3, fp_vector_vector_op_3412_arg3); + setArg(call_fp_vector_vector_op_3412, 4, fp_vector_vector_op_3412_arg4); + setArg(call_fp_vector_vector_op_3412, 5, fp_vector_vector_op_3412_arg5); + setArg(call_fp_vector_vector_op_3412, 6, vm); + setArg(call_fp_vector_vector_op_3412, 7, vd); + setArg(call_fp_vector_vector_op_3412, 8, vs2); + setArg(call_fp_vector_vector_op_3412, 9, vs1); + setArg(call_fp_vector_vector_op_3412, 10, fp_vector_vector_op_3412_arg10); + setArg(call_fp_vector_vector_op_3412, 11, fp_vector_vector_op_3412_arg11); + InvokeNode* call_fget_flags_3414; + x86::Gp ret_val_fget_flags_3414 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3414, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3414; + setRet(call_fget_flags_3414, 0, ret_val_fget_flags_3414); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3415 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3415, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3415, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 763); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 764: VFMADD__VF */ + continuation_e __vfmadd__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMADD__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 764); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3416; + x86::Gp ret_val_get_sew_pow_3416 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3416, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3417 = get_reg(cc, 8, false); + mov(cc, tmp3417, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3417, (ret_val_get_sew_pow_3416))), 8, false), ~ 1); + setArg(call_get_sew_pow_3416, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3416, 0, ret_val_get_sew_pow_3416); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3418; + auto illegal_fp_normal_3418_arg2 = SEW; + auto illegal_fp_normal_3418_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3418 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3418, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3418; + setArg(call_illegal_fp_normal_3418, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3418, 1, vd); + setArg(call_illegal_fp_normal_3418, 2, vm); + setArg(call_illegal_fp_normal_3418, 3, illegal_fp_normal_3418_arg2); + setArg(call_illegal_fp_normal_3418, 4, illegal_fp_normal_3418_arg3); + setRet(call_illegal_fp_normal_3418, 0, ret_val_illegal_fp_normal_3418); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3420; + x86::Gp ret_val_sew_3420 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3420, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3419; + auto fp_vector_imm_op_3419_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3419_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3419_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3419_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3419_arg10 = rm; + auto fp_vector_imm_op_3419_arg11 = ret_val_sew_3420; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3419, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3420, 0, reinterpret_cast(this)); + setRet(call_sew_3420, 0, ret_val_sew_3420); + setArg(call_fp_vector_imm_op_3419, 0, V); + setArg(call_fp_vector_imm_op_3419, 1, 40); + setArg(call_fp_vector_imm_op_3419, 2, 5); + setArg(call_fp_vector_imm_op_3419, 3, fp_vector_imm_op_3419_arg3); + setArg(call_fp_vector_imm_op_3419, 4, fp_vector_imm_op_3419_arg4); + setArg(call_fp_vector_imm_op_3419, 5, fp_vector_imm_op_3419_arg5); + setArg(call_fp_vector_imm_op_3419, 6, vm); + setArg(call_fp_vector_imm_op_3419, 7, vd); + setArg(call_fp_vector_imm_op_3419, 8, vs2); + setArg(call_fp_vector_imm_op_3419, 9, fp_vector_imm_op_3419_arg9); + setArg(call_fp_vector_imm_op_3419, 10, fp_vector_imm_op_3419_arg10); + setArg(call_fp_vector_imm_op_3419, 11, fp_vector_imm_op_3419_arg11); + InvokeNode* call_fget_flags_3421; + x86::Gp ret_val_fget_flags_3421 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3421, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3421; + setRet(call_fget_flags_3421, 0, ret_val_fget_flags_3421); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3422 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3422, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3422, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 764); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 765: VFMADD__VV */ + continuation_e __vfmadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 765); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3423; + x86::Gp ret_val_get_sew_pow_3423 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3423, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3424 = get_reg(cc, 8, false); + mov(cc, tmp3424, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3424, (ret_val_get_sew_pow_3423))), 8, false), ~ 1); + setArg(call_get_sew_pow_3423, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3423, 0, ret_val_get_sew_pow_3423); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3425; + auto illegal_fp_normal_3425_arg2 = SEW; + auto illegal_fp_normal_3425_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3425 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3425, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3425; + setArg(call_illegal_fp_normal_3425, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3425, 1, vd); + setArg(call_illegal_fp_normal_3425, 2, vm); + setArg(call_illegal_fp_normal_3425, 3, illegal_fp_normal_3425_arg2); + setArg(call_illegal_fp_normal_3425, 4, illegal_fp_normal_3425_arg3); + setRet(call_illegal_fp_normal_3425, 0, ret_val_illegal_fp_normal_3425); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3427; + x86::Gp ret_val_sew_3427 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3427, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3426; + auto fp_vector_vector_op_3426_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3426_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3426_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3426_arg10 = rm; + auto fp_vector_vector_op_3426_arg11 = ret_val_sew_3427; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3426, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3427, 0, reinterpret_cast(this)); + setRet(call_sew_3427, 0, ret_val_sew_3427); + setArg(call_fp_vector_vector_op_3426, 0, V); + setArg(call_fp_vector_vector_op_3426, 1, 40); + setArg(call_fp_vector_vector_op_3426, 2, 1); + setArg(call_fp_vector_vector_op_3426, 3, fp_vector_vector_op_3426_arg3); + setArg(call_fp_vector_vector_op_3426, 4, fp_vector_vector_op_3426_arg4); + setArg(call_fp_vector_vector_op_3426, 5, fp_vector_vector_op_3426_arg5); + setArg(call_fp_vector_vector_op_3426, 6, vm); + setArg(call_fp_vector_vector_op_3426, 7, vd); + setArg(call_fp_vector_vector_op_3426, 8, vs2); + setArg(call_fp_vector_vector_op_3426, 9, vs1); + setArg(call_fp_vector_vector_op_3426, 10, fp_vector_vector_op_3426_arg10); + setArg(call_fp_vector_vector_op_3426, 11, fp_vector_vector_op_3426_arg11); + InvokeNode* call_fget_flags_3428; + x86::Gp ret_val_fget_flags_3428 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3428, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3428; + setRet(call_fget_flags_3428, 0, ret_val_fget_flags_3428); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3429 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3429, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3429, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 765); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 766: VFNMADD__VF */ + continuation_e __vfnmadd__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmadd.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMADD__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 766); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3430; + x86::Gp ret_val_get_sew_pow_3430 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3430, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3431 = get_reg(cc, 8, false); + mov(cc, tmp3431, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3431, (ret_val_get_sew_pow_3430))), 8, false), ~ 1); + setArg(call_get_sew_pow_3430, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3430, 0, ret_val_get_sew_pow_3430); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3432; + auto illegal_fp_normal_3432_arg2 = SEW; + auto illegal_fp_normal_3432_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3432 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3432, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3432; + setArg(call_illegal_fp_normal_3432, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3432, 1, vd); + setArg(call_illegal_fp_normal_3432, 2, vm); + setArg(call_illegal_fp_normal_3432, 3, illegal_fp_normal_3432_arg2); + setArg(call_illegal_fp_normal_3432, 4, illegal_fp_normal_3432_arg3); + setRet(call_illegal_fp_normal_3432, 0, ret_val_illegal_fp_normal_3432); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3434; + x86::Gp ret_val_sew_3434 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3434, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3433; + auto fp_vector_imm_op_3433_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3433_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3433_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3433_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3433_arg10 = rm; + auto fp_vector_imm_op_3433_arg11 = ret_val_sew_3434; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3433, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3434, 0, reinterpret_cast(this)); + setRet(call_sew_3434, 0, ret_val_sew_3434); + setArg(call_fp_vector_imm_op_3433, 0, V); + setArg(call_fp_vector_imm_op_3433, 1, 41); + setArg(call_fp_vector_imm_op_3433, 2, 5); + setArg(call_fp_vector_imm_op_3433, 3, fp_vector_imm_op_3433_arg3); + setArg(call_fp_vector_imm_op_3433, 4, fp_vector_imm_op_3433_arg4); + setArg(call_fp_vector_imm_op_3433, 5, fp_vector_imm_op_3433_arg5); + setArg(call_fp_vector_imm_op_3433, 6, vm); + setArg(call_fp_vector_imm_op_3433, 7, vd); + setArg(call_fp_vector_imm_op_3433, 8, vs2); + setArg(call_fp_vector_imm_op_3433, 9, fp_vector_imm_op_3433_arg9); + setArg(call_fp_vector_imm_op_3433, 10, fp_vector_imm_op_3433_arg10); + setArg(call_fp_vector_imm_op_3433, 11, fp_vector_imm_op_3433_arg11); + InvokeNode* call_fget_flags_3435; + x86::Gp ret_val_fget_flags_3435 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3435, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3435; + setRet(call_fget_flags_3435, 0, ret_val_fget_flags_3435); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3436 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3436, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3436, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 766); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 767: VFNMADD__VV */ + continuation_e __vfnmadd__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmadd.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMADD__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 767); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3437; + x86::Gp ret_val_get_sew_pow_3437 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3437, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3438 = get_reg(cc, 8, false); + mov(cc, tmp3438, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3438, (ret_val_get_sew_pow_3437))), 8, false), ~ 1); + setArg(call_get_sew_pow_3437, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3437, 0, ret_val_get_sew_pow_3437); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3439; + auto illegal_fp_normal_3439_arg2 = SEW; + auto illegal_fp_normal_3439_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3439 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3439, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3439; + setArg(call_illegal_fp_normal_3439, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3439, 1, vd); + setArg(call_illegal_fp_normal_3439, 2, vm); + setArg(call_illegal_fp_normal_3439, 3, illegal_fp_normal_3439_arg2); + setArg(call_illegal_fp_normal_3439, 4, illegal_fp_normal_3439_arg3); + setRet(call_illegal_fp_normal_3439, 0, ret_val_illegal_fp_normal_3439); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3441; + x86::Gp ret_val_sew_3441 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3441, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3440; + auto fp_vector_vector_op_3440_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3440_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3440_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3440_arg10 = rm; + auto fp_vector_vector_op_3440_arg11 = ret_val_sew_3441; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3440, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3441, 0, reinterpret_cast(this)); + setRet(call_sew_3441, 0, ret_val_sew_3441); + setArg(call_fp_vector_vector_op_3440, 0, V); + setArg(call_fp_vector_vector_op_3440, 1, 41); + setArg(call_fp_vector_vector_op_3440, 2, 1); + setArg(call_fp_vector_vector_op_3440, 3, fp_vector_vector_op_3440_arg3); + setArg(call_fp_vector_vector_op_3440, 4, fp_vector_vector_op_3440_arg4); + setArg(call_fp_vector_vector_op_3440, 5, fp_vector_vector_op_3440_arg5); + setArg(call_fp_vector_vector_op_3440, 6, vm); + setArg(call_fp_vector_vector_op_3440, 7, vd); + setArg(call_fp_vector_vector_op_3440, 8, vs2); + setArg(call_fp_vector_vector_op_3440, 9, vs1); + setArg(call_fp_vector_vector_op_3440, 10, fp_vector_vector_op_3440_arg10); + setArg(call_fp_vector_vector_op_3440, 11, fp_vector_vector_op_3440_arg11); + InvokeNode* call_fget_flags_3442; + x86::Gp ret_val_fget_flags_3442 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3442, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3442; + setRet(call_fget_flags_3442, 0, ret_val_fget_flags_3442); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3443 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3443, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3443, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 767); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 768: VFMSUB__VF */ + continuation_e __vfmsub__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMSUB__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 768); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3444; + x86::Gp ret_val_get_sew_pow_3444 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3444, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3445 = get_reg(cc, 8, false); + mov(cc, tmp3445, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3445, (ret_val_get_sew_pow_3444))), 8, false), ~ 1); + setArg(call_get_sew_pow_3444, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3444, 0, ret_val_get_sew_pow_3444); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3446; + auto illegal_fp_normal_3446_arg2 = SEW; + auto illegal_fp_normal_3446_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3446 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3446, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3446; + setArg(call_illegal_fp_normal_3446, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3446, 1, vd); + setArg(call_illegal_fp_normal_3446, 2, vm); + setArg(call_illegal_fp_normal_3446, 3, illegal_fp_normal_3446_arg2); + setArg(call_illegal_fp_normal_3446, 4, illegal_fp_normal_3446_arg3); + setRet(call_illegal_fp_normal_3446, 0, ret_val_illegal_fp_normal_3446); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3448; + x86::Gp ret_val_sew_3448 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3448, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3447; + auto fp_vector_imm_op_3447_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3447_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3447_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3447_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3447_arg10 = rm; + auto fp_vector_imm_op_3447_arg11 = ret_val_sew_3448; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3447, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3448, 0, reinterpret_cast(this)); + setRet(call_sew_3448, 0, ret_val_sew_3448); + setArg(call_fp_vector_imm_op_3447, 0, V); + setArg(call_fp_vector_imm_op_3447, 1, 42); + setArg(call_fp_vector_imm_op_3447, 2, 5); + setArg(call_fp_vector_imm_op_3447, 3, fp_vector_imm_op_3447_arg3); + setArg(call_fp_vector_imm_op_3447, 4, fp_vector_imm_op_3447_arg4); + setArg(call_fp_vector_imm_op_3447, 5, fp_vector_imm_op_3447_arg5); + setArg(call_fp_vector_imm_op_3447, 6, vm); + setArg(call_fp_vector_imm_op_3447, 7, vd); + setArg(call_fp_vector_imm_op_3447, 8, vs2); + setArg(call_fp_vector_imm_op_3447, 9, fp_vector_imm_op_3447_arg9); + setArg(call_fp_vector_imm_op_3447, 10, fp_vector_imm_op_3447_arg10); + setArg(call_fp_vector_imm_op_3447, 11, fp_vector_imm_op_3447_arg11); + InvokeNode* call_fget_flags_3449; + x86::Gp ret_val_fget_flags_3449 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3449, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3449; + setRet(call_fget_flags_3449, 0, ret_val_fget_flags_3449); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3450 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3450, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3450, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 768); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 769: VFMSUB__VV */ + continuation_e __vfmsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 769); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3451; + x86::Gp ret_val_get_sew_pow_3451 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3451, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3452 = get_reg(cc, 8, false); + mov(cc, tmp3452, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3452, (ret_val_get_sew_pow_3451))), 8, false), ~ 1); + setArg(call_get_sew_pow_3451, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3451, 0, ret_val_get_sew_pow_3451); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3453; + auto illegal_fp_normal_3453_arg2 = SEW; + auto illegal_fp_normal_3453_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3453 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3453, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3453; + setArg(call_illegal_fp_normal_3453, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3453, 1, vd); + setArg(call_illegal_fp_normal_3453, 2, vm); + setArg(call_illegal_fp_normal_3453, 3, illegal_fp_normal_3453_arg2); + setArg(call_illegal_fp_normal_3453, 4, illegal_fp_normal_3453_arg3); + setRet(call_illegal_fp_normal_3453, 0, ret_val_illegal_fp_normal_3453); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3455; + x86::Gp ret_val_sew_3455 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3455, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3454; + auto fp_vector_vector_op_3454_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3454_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3454_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3454_arg10 = rm; + auto fp_vector_vector_op_3454_arg11 = ret_val_sew_3455; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3454, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3455, 0, reinterpret_cast(this)); + setRet(call_sew_3455, 0, ret_val_sew_3455); + setArg(call_fp_vector_vector_op_3454, 0, V); + setArg(call_fp_vector_vector_op_3454, 1, 42); + setArg(call_fp_vector_vector_op_3454, 2, 1); + setArg(call_fp_vector_vector_op_3454, 3, fp_vector_vector_op_3454_arg3); + setArg(call_fp_vector_vector_op_3454, 4, fp_vector_vector_op_3454_arg4); + setArg(call_fp_vector_vector_op_3454, 5, fp_vector_vector_op_3454_arg5); + setArg(call_fp_vector_vector_op_3454, 6, vm); + setArg(call_fp_vector_vector_op_3454, 7, vd); + setArg(call_fp_vector_vector_op_3454, 8, vs2); + setArg(call_fp_vector_vector_op_3454, 9, vs1); + setArg(call_fp_vector_vector_op_3454, 10, fp_vector_vector_op_3454_arg10); + setArg(call_fp_vector_vector_op_3454, 11, fp_vector_vector_op_3454_arg11); + InvokeNode* call_fget_flags_3456; + x86::Gp ret_val_fget_flags_3456 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3456, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3456; + setRet(call_fget_flags_3456, 0, ret_val_fget_flags_3456); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3457 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3457, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3457, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 769); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 770: VFNMSUB__VF */ + continuation_e __vfnmsub__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfnmsub.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMSUB__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 770); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3458; + x86::Gp ret_val_get_sew_pow_3458 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3458, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3459 = get_reg(cc, 8, false); + mov(cc, tmp3459, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3459, (ret_val_get_sew_pow_3458))), 8, false), ~ 1); + setArg(call_get_sew_pow_3458, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3458, 0, ret_val_get_sew_pow_3458); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3460; + auto illegal_fp_normal_3460_arg2 = SEW; + auto illegal_fp_normal_3460_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3460 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3460, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3460; + setArg(call_illegal_fp_normal_3460, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3460, 1, vd); + setArg(call_illegal_fp_normal_3460, 2, vm); + setArg(call_illegal_fp_normal_3460, 3, illegal_fp_normal_3460_arg2); + setArg(call_illegal_fp_normal_3460, 4, illegal_fp_normal_3460_arg3); + setRet(call_illegal_fp_normal_3460, 0, ret_val_illegal_fp_normal_3460); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3462; + x86::Gp ret_val_sew_3462 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3462, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3461; + auto fp_vector_imm_op_3461_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3461_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3461_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3461_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3461_arg10 = rm; + auto fp_vector_imm_op_3461_arg11 = ret_val_sew_3462; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3461, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3462, 0, reinterpret_cast(this)); + setRet(call_sew_3462, 0, ret_val_sew_3462); + setArg(call_fp_vector_imm_op_3461, 0, V); + setArg(call_fp_vector_imm_op_3461, 1, 43); + setArg(call_fp_vector_imm_op_3461, 2, 5); + setArg(call_fp_vector_imm_op_3461, 3, fp_vector_imm_op_3461_arg3); + setArg(call_fp_vector_imm_op_3461, 4, fp_vector_imm_op_3461_arg4); + setArg(call_fp_vector_imm_op_3461, 5, fp_vector_imm_op_3461_arg5); + setArg(call_fp_vector_imm_op_3461, 6, vm); + setArg(call_fp_vector_imm_op_3461, 7, vd); + setArg(call_fp_vector_imm_op_3461, 8, vs2); + setArg(call_fp_vector_imm_op_3461, 9, fp_vector_imm_op_3461_arg9); + setArg(call_fp_vector_imm_op_3461, 10, fp_vector_imm_op_3461_arg10); + setArg(call_fp_vector_imm_op_3461, 11, fp_vector_imm_op_3461_arg11); + InvokeNode* call_fget_flags_3463; + x86::Gp ret_val_fget_flags_3463 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3463, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3463; + setRet(call_fget_flags_3463, 0, ret_val_fget_flags_3463); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3464 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3464, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3464, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 770); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 771: VFNMSUB__VV */ + continuation_e __vfnmsub__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfnmsub.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNMSUB__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 771); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3465; + x86::Gp ret_val_get_sew_pow_3465 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3465, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3466 = get_reg(cc, 8, false); + mov(cc, tmp3466, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3466, (ret_val_get_sew_pow_3465))), 8, false), ~ 1); + setArg(call_get_sew_pow_3465, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3465, 0, ret_val_get_sew_pow_3465); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3467; + auto illegal_fp_normal_3467_arg2 = SEW; + auto illegal_fp_normal_3467_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3467 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3467, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3467; + setArg(call_illegal_fp_normal_3467, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3467, 1, vd); + setArg(call_illegal_fp_normal_3467, 2, vm); + setArg(call_illegal_fp_normal_3467, 3, illegal_fp_normal_3467_arg2); + setArg(call_illegal_fp_normal_3467, 4, illegal_fp_normal_3467_arg3); + setRet(call_illegal_fp_normal_3467, 0, ret_val_illegal_fp_normal_3467); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3469; + x86::Gp ret_val_sew_3469 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3469, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3468; + auto fp_vector_vector_op_3468_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3468_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3468_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3468_arg10 = rm; + auto fp_vector_vector_op_3468_arg11 = ret_val_sew_3469; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3468, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3469, 0, reinterpret_cast(this)); + setRet(call_sew_3469, 0, ret_val_sew_3469); + setArg(call_fp_vector_vector_op_3468, 0, V); + setArg(call_fp_vector_vector_op_3468, 1, 43); + setArg(call_fp_vector_vector_op_3468, 2, 1); + setArg(call_fp_vector_vector_op_3468, 3, fp_vector_vector_op_3468_arg3); + setArg(call_fp_vector_vector_op_3468, 4, fp_vector_vector_op_3468_arg4); + setArg(call_fp_vector_vector_op_3468, 5, fp_vector_vector_op_3468_arg5); + setArg(call_fp_vector_vector_op_3468, 6, vm); + setArg(call_fp_vector_vector_op_3468, 7, vd); + setArg(call_fp_vector_vector_op_3468, 8, vs2); + setArg(call_fp_vector_vector_op_3468, 9, vs1); + setArg(call_fp_vector_vector_op_3468, 10, fp_vector_vector_op_3468_arg10); + setArg(call_fp_vector_vector_op_3468, 11, fp_vector_vector_op_3468_arg11); + InvokeNode* call_fget_flags_3470; + x86::Gp ret_val_fget_flags_3470 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3470, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3470; + setRet(call_fget_flags_3470, 0, ret_val_fget_flags_3470); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3471 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3471, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3471, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 771); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 772: VFWMACC__VF */ + continuation_e __vfwmacc__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMACC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 772); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3472; + x86::Gp ret_val_get_sew_pow_3472 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3472, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3473 = get_reg(cc, 8, false); + mov(cc, tmp3473, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3473, (ret_val_get_sew_pow_3472))), 8, false), ~ 1); + setArg(call_get_sew_pow_3472, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3472, 0, ret_val_get_sew_pow_3472); + InvokeNode* call_get_lmul_pow_3474; + x86::Gp ret_val_get_lmul_pow_3474 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3474, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3474; + setArg(call_get_lmul_pow_3474, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3474, 0, ret_val_get_lmul_pow_3474); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3475; + auto illegal_fp_variable_width_3475_arg2 = SEW; + auto illegal_fp_variable_width_3475_arg3 = rm; + auto illegal_fp_variable_width_3475_arg4 = SEW_widen; + auto illegal_fp_variable_width_3475_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3475 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3475, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3476; + auto valid_reg_overlap_3476_arg2 = LMUL_pow; + auto valid_reg_overlap_3476_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3476 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3476, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3475, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3476)); + setArg(call_illegal_fp_variable_width_3475, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3475, 1, vd); + setArg(call_illegal_fp_variable_width_3475, 2, vm); + setArg(call_illegal_fp_variable_width_3475, 3, illegal_fp_variable_width_3475_arg2); + setArg(call_illegal_fp_variable_width_3475, 4, illegal_fp_variable_width_3475_arg3); + setArg(call_illegal_fp_variable_width_3475, 5, illegal_fp_variable_width_3475_arg4); + setArg(call_illegal_fp_variable_width_3475, 6, illegal_fp_variable_width_3475_arg5); + setRet(call_illegal_fp_variable_width_3475, 0, ret_val_illegal_fp_variable_width_3475); + setArg(call_valid_reg_overlap_3476, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3476, 1, vs2); + setArg(call_valid_reg_overlap_3476, 2, vd); + setArg(call_valid_reg_overlap_3476, 3, valid_reg_overlap_3476_arg2); + setArg(call_valid_reg_overlap_3476, 4, valid_reg_overlap_3476_arg3); + setRet(call_valid_reg_overlap_3476, 0, ret_val_valid_reg_overlap_3476); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3478; + x86::Gp ret_val_sew_3478 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3478, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3477; + auto fp_vector_imm_wv_3477_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3477_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3477_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3477_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_wv_3477_arg10 = rm; + auto fp_vector_imm_wv_3477_arg11 = ret_val_sew_3478; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3477, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3478, 0, reinterpret_cast(this)); + setRet(call_sew_3478, 0, ret_val_sew_3478); + setArg(call_fp_vector_imm_wv_3477, 0, V); + setArg(call_fp_vector_imm_wv_3477, 1, 60); + setArg(call_fp_vector_imm_wv_3477, 2, 5); + setArg(call_fp_vector_imm_wv_3477, 3, fp_vector_imm_wv_3477_arg3); + setArg(call_fp_vector_imm_wv_3477, 4, fp_vector_imm_wv_3477_arg4); + setArg(call_fp_vector_imm_wv_3477, 5, fp_vector_imm_wv_3477_arg5); + setArg(call_fp_vector_imm_wv_3477, 6, vm); + setArg(call_fp_vector_imm_wv_3477, 7, vd); + setArg(call_fp_vector_imm_wv_3477, 8, vs2); + setArg(call_fp_vector_imm_wv_3477, 9, fp_vector_imm_wv_3477_arg9); + setArg(call_fp_vector_imm_wv_3477, 10, fp_vector_imm_wv_3477_arg10); + setArg(call_fp_vector_imm_wv_3477, 11, fp_vector_imm_wv_3477_arg11); + InvokeNode* call_fget_flags_3479; + x86::Gp ret_val_fget_flags_3479 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3479, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3479; + setRet(call_fget_flags_3479, 0, ret_val_fget_flags_3479); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3480 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3480, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3480, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 772); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 773: VFWMACC__VV */ + continuation_e __vfwmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 773); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3481; + x86::Gp ret_val_get_sew_pow_3481 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3481, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3482 = get_reg(cc, 8, false); + mov(cc, tmp3482, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3482, (ret_val_get_sew_pow_3481))), 8, false), ~ 1); + setArg(call_get_sew_pow_3481, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3481, 0, ret_val_get_sew_pow_3481); + InvokeNode* call_get_lmul_pow_3483; + x86::Gp ret_val_get_lmul_pow_3483 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3483, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3483; + setArg(call_get_lmul_pow_3483, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3483, 0, ret_val_get_lmul_pow_3483); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3484; + auto illegal_fp_variable_width_3484_arg2 = SEW; + auto illegal_fp_variable_width_3484_arg3 = rm; + auto illegal_fp_variable_width_3484_arg4 = SEW_widen; + auto illegal_fp_variable_width_3484_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3484 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3484, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3485; + auto valid_reg_overlap_3485_arg2 = LMUL_pow; + auto valid_reg_overlap_3485_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3485 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3485, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3486; + auto valid_reg_overlap_3486_arg2 = LMUL_pow; + auto valid_reg_overlap_3486_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3486 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3486, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3484, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3485)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3486)); + setArg(call_illegal_fp_variable_width_3484, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3484, 1, vd); + setArg(call_illegal_fp_variable_width_3484, 2, vm); + setArg(call_illegal_fp_variable_width_3484, 3, illegal_fp_variable_width_3484_arg2); + setArg(call_illegal_fp_variable_width_3484, 4, illegal_fp_variable_width_3484_arg3); + setArg(call_illegal_fp_variable_width_3484, 5, illegal_fp_variable_width_3484_arg4); + setArg(call_illegal_fp_variable_width_3484, 6, illegal_fp_variable_width_3484_arg5); + setRet(call_illegal_fp_variable_width_3484, 0, ret_val_illegal_fp_variable_width_3484); + setArg(call_valid_reg_overlap_3485, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3485, 1, vs1); + setArg(call_valid_reg_overlap_3485, 2, vd); + setArg(call_valid_reg_overlap_3485, 3, valid_reg_overlap_3485_arg2); + setArg(call_valid_reg_overlap_3485, 4, valid_reg_overlap_3485_arg3); + setRet(call_valid_reg_overlap_3485, 0, ret_val_valid_reg_overlap_3485); + setArg(call_valid_reg_overlap_3486, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3486, 1, vs2); + setArg(call_valid_reg_overlap_3486, 2, vd); + setArg(call_valid_reg_overlap_3486, 3, valid_reg_overlap_3486_arg2); + setArg(call_valid_reg_overlap_3486, 4, valid_reg_overlap_3486_arg3); + setRet(call_valid_reg_overlap_3486, 0, ret_val_valid_reg_overlap_3486); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3488; + x86::Gp ret_val_sew_3488 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3488, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3487; + auto fp_vector_vector_wv_3487_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3487_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3487_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3487_arg10 = rm; + auto fp_vector_vector_wv_3487_arg11 = ret_val_sew_3488; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3487, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3488, 0, reinterpret_cast(this)); + setRet(call_sew_3488, 0, ret_val_sew_3488); + setArg(call_fp_vector_vector_wv_3487, 0, V); + setArg(call_fp_vector_vector_wv_3487, 1, 60); + setArg(call_fp_vector_vector_wv_3487, 2, 1); + setArg(call_fp_vector_vector_wv_3487, 3, fp_vector_vector_wv_3487_arg3); + setArg(call_fp_vector_vector_wv_3487, 4, fp_vector_vector_wv_3487_arg4); + setArg(call_fp_vector_vector_wv_3487, 5, fp_vector_vector_wv_3487_arg5); + setArg(call_fp_vector_vector_wv_3487, 6, vm); + setArg(call_fp_vector_vector_wv_3487, 7, vd); + setArg(call_fp_vector_vector_wv_3487, 8, vs2); + setArg(call_fp_vector_vector_wv_3487, 9, vs1); + setArg(call_fp_vector_vector_wv_3487, 10, fp_vector_vector_wv_3487_arg10); + setArg(call_fp_vector_vector_wv_3487, 11, fp_vector_vector_wv_3487_arg11); + InvokeNode* call_fget_flags_3489; + x86::Gp ret_val_fget_flags_3489 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3489, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3489; + setRet(call_fget_flags_3489, 0, ret_val_fget_flags_3489); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3490 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3490, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3490, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 773); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 774: VFWNMACC__VF */ + continuation_e __vfwnmacc__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwnmacc.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWNMACC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 774); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3491; + x86::Gp ret_val_get_sew_pow_3491 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3491, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3492 = get_reg(cc, 8, false); + mov(cc, tmp3492, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3492, (ret_val_get_sew_pow_3491))), 8, false), ~ 1); + setArg(call_get_sew_pow_3491, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3491, 0, ret_val_get_sew_pow_3491); + InvokeNode* call_get_lmul_pow_3493; + x86::Gp ret_val_get_lmul_pow_3493 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3493, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3493; + setArg(call_get_lmul_pow_3493, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3493, 0, ret_val_get_lmul_pow_3493); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3494; + auto illegal_fp_variable_width_3494_arg2 = SEW; + auto illegal_fp_variable_width_3494_arg3 = rm; + auto illegal_fp_variable_width_3494_arg4 = SEW_widen; + auto illegal_fp_variable_width_3494_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3494 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3494, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3495; + auto valid_reg_overlap_3495_arg2 = LMUL_pow; + auto valid_reg_overlap_3495_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3495 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3495, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3494, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3495)); + setArg(call_illegal_fp_variable_width_3494, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3494, 1, vd); + setArg(call_illegal_fp_variable_width_3494, 2, vm); + setArg(call_illegal_fp_variable_width_3494, 3, illegal_fp_variable_width_3494_arg2); + setArg(call_illegal_fp_variable_width_3494, 4, illegal_fp_variable_width_3494_arg3); + setArg(call_illegal_fp_variable_width_3494, 5, illegal_fp_variable_width_3494_arg4); + setArg(call_illegal_fp_variable_width_3494, 6, illegal_fp_variable_width_3494_arg5); + setRet(call_illegal_fp_variable_width_3494, 0, ret_val_illegal_fp_variable_width_3494); + setArg(call_valid_reg_overlap_3495, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3495, 1, vs2); + setArg(call_valid_reg_overlap_3495, 2, vd); + setArg(call_valid_reg_overlap_3495, 3, valid_reg_overlap_3495_arg2); + setArg(call_valid_reg_overlap_3495, 4, valid_reg_overlap_3495_arg3); + setRet(call_valid_reg_overlap_3495, 0, ret_val_valid_reg_overlap_3495); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3497; + x86::Gp ret_val_sew_3497 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3497, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3496; + auto fp_vector_imm_wv_3496_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3496_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3496_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3496_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_wv_3496_arg10 = rm; + auto fp_vector_imm_wv_3496_arg11 = ret_val_sew_3497; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3496, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3497, 0, reinterpret_cast(this)); + setRet(call_sew_3497, 0, ret_val_sew_3497); + setArg(call_fp_vector_imm_wv_3496, 0, V); + setArg(call_fp_vector_imm_wv_3496, 1, 61); + setArg(call_fp_vector_imm_wv_3496, 2, 5); + setArg(call_fp_vector_imm_wv_3496, 3, fp_vector_imm_wv_3496_arg3); + setArg(call_fp_vector_imm_wv_3496, 4, fp_vector_imm_wv_3496_arg4); + setArg(call_fp_vector_imm_wv_3496, 5, fp_vector_imm_wv_3496_arg5); + setArg(call_fp_vector_imm_wv_3496, 6, vm); + setArg(call_fp_vector_imm_wv_3496, 7, vd); + setArg(call_fp_vector_imm_wv_3496, 8, vs2); + setArg(call_fp_vector_imm_wv_3496, 9, fp_vector_imm_wv_3496_arg9); + setArg(call_fp_vector_imm_wv_3496, 10, fp_vector_imm_wv_3496_arg10); + setArg(call_fp_vector_imm_wv_3496, 11, fp_vector_imm_wv_3496_arg11); + InvokeNode* call_fget_flags_3498; + x86::Gp ret_val_fget_flags_3498 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3498, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3498; + setRet(call_fget_flags_3498, 0, ret_val_fget_flags_3498); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3499 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3499, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3499, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 774); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 775: VFWNMACC__VV */ + continuation_e __vfwnmacc__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwnmacc.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWNMACC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 775); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3500; + x86::Gp ret_val_get_sew_pow_3500 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3500, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3501 = get_reg(cc, 8, false); + mov(cc, tmp3501, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3501, (ret_val_get_sew_pow_3500))), 8, false), ~ 1); + setArg(call_get_sew_pow_3500, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3500, 0, ret_val_get_sew_pow_3500); + InvokeNode* call_get_lmul_pow_3502; + x86::Gp ret_val_get_lmul_pow_3502 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3502, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3502; + setArg(call_get_lmul_pow_3502, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3502, 0, ret_val_get_lmul_pow_3502); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3503; + auto illegal_fp_variable_width_3503_arg2 = SEW; + auto illegal_fp_variable_width_3503_arg3 = rm; + auto illegal_fp_variable_width_3503_arg4 = SEW_widen; + auto illegal_fp_variable_width_3503_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3503 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3503, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3504; + auto valid_reg_overlap_3504_arg2 = LMUL_pow; + auto valid_reg_overlap_3504_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3504 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3504, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3505; + auto valid_reg_overlap_3505_arg2 = LMUL_pow; + auto valid_reg_overlap_3505_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3505 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3505, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3503, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3504)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3505)); + setArg(call_illegal_fp_variable_width_3503, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3503, 1, vd); + setArg(call_illegal_fp_variable_width_3503, 2, vm); + setArg(call_illegal_fp_variable_width_3503, 3, illegal_fp_variable_width_3503_arg2); + setArg(call_illegal_fp_variable_width_3503, 4, illegal_fp_variable_width_3503_arg3); + setArg(call_illegal_fp_variable_width_3503, 5, illegal_fp_variable_width_3503_arg4); + setArg(call_illegal_fp_variable_width_3503, 6, illegal_fp_variable_width_3503_arg5); + setRet(call_illegal_fp_variable_width_3503, 0, ret_val_illegal_fp_variable_width_3503); + setArg(call_valid_reg_overlap_3504, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3504, 1, vs1); + setArg(call_valid_reg_overlap_3504, 2, vd); + setArg(call_valid_reg_overlap_3504, 3, valid_reg_overlap_3504_arg2); + setArg(call_valid_reg_overlap_3504, 4, valid_reg_overlap_3504_arg3); + setRet(call_valid_reg_overlap_3504, 0, ret_val_valid_reg_overlap_3504); + setArg(call_valid_reg_overlap_3505, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3505, 1, vs2); + setArg(call_valid_reg_overlap_3505, 2, vd); + setArg(call_valid_reg_overlap_3505, 3, valid_reg_overlap_3505_arg2); + setArg(call_valid_reg_overlap_3505, 4, valid_reg_overlap_3505_arg3); + setRet(call_valid_reg_overlap_3505, 0, ret_val_valid_reg_overlap_3505); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3507; + x86::Gp ret_val_sew_3507 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3507, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3506; + auto fp_vector_vector_wv_3506_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3506_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3506_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3506_arg10 = rm; + auto fp_vector_vector_wv_3506_arg11 = ret_val_sew_3507; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3506, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3507, 0, reinterpret_cast(this)); + setRet(call_sew_3507, 0, ret_val_sew_3507); + setArg(call_fp_vector_vector_wv_3506, 0, V); + setArg(call_fp_vector_vector_wv_3506, 1, 61); + setArg(call_fp_vector_vector_wv_3506, 2, 1); + setArg(call_fp_vector_vector_wv_3506, 3, fp_vector_vector_wv_3506_arg3); + setArg(call_fp_vector_vector_wv_3506, 4, fp_vector_vector_wv_3506_arg4); + setArg(call_fp_vector_vector_wv_3506, 5, fp_vector_vector_wv_3506_arg5); + setArg(call_fp_vector_vector_wv_3506, 6, vm); + setArg(call_fp_vector_vector_wv_3506, 7, vd); + setArg(call_fp_vector_vector_wv_3506, 8, vs2); + setArg(call_fp_vector_vector_wv_3506, 9, vs1); + setArg(call_fp_vector_vector_wv_3506, 10, fp_vector_vector_wv_3506_arg10); + setArg(call_fp_vector_vector_wv_3506, 11, fp_vector_vector_wv_3506_arg11); + InvokeNode* call_fget_flags_3508; + x86::Gp ret_val_fget_flags_3508 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3508, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3508; + setRet(call_fget_flags_3508, 0, ret_val_fget_flags_3508); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3509 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3509, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3509, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 775); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 776: VFWMSAC__VF */ + continuation_e __vfwmsac__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMSAC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 776); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3510; + x86::Gp ret_val_get_sew_pow_3510 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3510, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3511 = get_reg(cc, 8, false); + mov(cc, tmp3511, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3511, (ret_val_get_sew_pow_3510))), 8, false), ~ 1); + setArg(call_get_sew_pow_3510, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3510, 0, ret_val_get_sew_pow_3510); + InvokeNode* call_get_lmul_pow_3512; + x86::Gp ret_val_get_lmul_pow_3512 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3512, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3512; + setArg(call_get_lmul_pow_3512, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3512, 0, ret_val_get_lmul_pow_3512); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3513; + auto illegal_fp_variable_width_3513_arg2 = SEW; + auto illegal_fp_variable_width_3513_arg3 = rm; + auto illegal_fp_variable_width_3513_arg4 = SEW_widen; + auto illegal_fp_variable_width_3513_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3513 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3513, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3514; + auto valid_reg_overlap_3514_arg2 = LMUL_pow; + auto valid_reg_overlap_3514_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3514 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3514, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3513, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3514)); + setArg(call_illegal_fp_variable_width_3513, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3513, 1, vd); + setArg(call_illegal_fp_variable_width_3513, 2, vm); + setArg(call_illegal_fp_variable_width_3513, 3, illegal_fp_variable_width_3513_arg2); + setArg(call_illegal_fp_variable_width_3513, 4, illegal_fp_variable_width_3513_arg3); + setArg(call_illegal_fp_variable_width_3513, 5, illegal_fp_variable_width_3513_arg4); + setArg(call_illegal_fp_variable_width_3513, 6, illegal_fp_variable_width_3513_arg5); + setRet(call_illegal_fp_variable_width_3513, 0, ret_val_illegal_fp_variable_width_3513); + setArg(call_valid_reg_overlap_3514, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3514, 1, vs2); + setArg(call_valid_reg_overlap_3514, 2, vd); + setArg(call_valid_reg_overlap_3514, 3, valid_reg_overlap_3514_arg2); + setArg(call_valid_reg_overlap_3514, 4, valid_reg_overlap_3514_arg3); + setRet(call_valid_reg_overlap_3514, 0, ret_val_valid_reg_overlap_3514); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3516; + x86::Gp ret_val_sew_3516 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3516, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3515; + auto fp_vector_imm_wv_3515_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3515_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3515_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3515_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_wv_3515_arg10 = rm; + auto fp_vector_imm_wv_3515_arg11 = ret_val_sew_3516; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3515, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3516, 0, reinterpret_cast(this)); + setRet(call_sew_3516, 0, ret_val_sew_3516); + setArg(call_fp_vector_imm_wv_3515, 0, V); + setArg(call_fp_vector_imm_wv_3515, 1, 62); + setArg(call_fp_vector_imm_wv_3515, 2, 5); + setArg(call_fp_vector_imm_wv_3515, 3, fp_vector_imm_wv_3515_arg3); + setArg(call_fp_vector_imm_wv_3515, 4, fp_vector_imm_wv_3515_arg4); + setArg(call_fp_vector_imm_wv_3515, 5, fp_vector_imm_wv_3515_arg5); + setArg(call_fp_vector_imm_wv_3515, 6, vm); + setArg(call_fp_vector_imm_wv_3515, 7, vd); + setArg(call_fp_vector_imm_wv_3515, 8, vs2); + setArg(call_fp_vector_imm_wv_3515, 9, fp_vector_imm_wv_3515_arg9); + setArg(call_fp_vector_imm_wv_3515, 10, fp_vector_imm_wv_3515_arg10); + setArg(call_fp_vector_imm_wv_3515, 11, fp_vector_imm_wv_3515_arg11); + InvokeNode* call_fget_flags_3517; + x86::Gp ret_val_fget_flags_3517 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3517, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3517; + setRet(call_fget_flags_3517, 0, ret_val_fget_flags_3517); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3518 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3518, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3518, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 776); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 777: VFWMSAC__VV */ + continuation_e __vfwmsac__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWMSAC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 777); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3519; + x86::Gp ret_val_get_sew_pow_3519 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3519, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3520 = get_reg(cc, 8, false); + mov(cc, tmp3520, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3520, (ret_val_get_sew_pow_3519))), 8, false), ~ 1); + setArg(call_get_sew_pow_3519, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3519, 0, ret_val_get_sew_pow_3519); + InvokeNode* call_get_lmul_pow_3521; + x86::Gp ret_val_get_lmul_pow_3521 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3521, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3521; + setArg(call_get_lmul_pow_3521, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3521, 0, ret_val_get_lmul_pow_3521); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3522; + auto illegal_fp_variable_width_3522_arg2 = SEW; + auto illegal_fp_variable_width_3522_arg3 = rm; + auto illegal_fp_variable_width_3522_arg4 = SEW_widen; + auto illegal_fp_variable_width_3522_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3522 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3522, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3523; + auto valid_reg_overlap_3523_arg2 = LMUL_pow; + auto valid_reg_overlap_3523_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3523 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3523, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3524; + auto valid_reg_overlap_3524_arg2 = LMUL_pow; + auto valid_reg_overlap_3524_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3524 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3524, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3522, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3523)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3524)); + setArg(call_illegal_fp_variable_width_3522, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3522, 1, vd); + setArg(call_illegal_fp_variable_width_3522, 2, vm); + setArg(call_illegal_fp_variable_width_3522, 3, illegal_fp_variable_width_3522_arg2); + setArg(call_illegal_fp_variable_width_3522, 4, illegal_fp_variable_width_3522_arg3); + setArg(call_illegal_fp_variable_width_3522, 5, illegal_fp_variable_width_3522_arg4); + setArg(call_illegal_fp_variable_width_3522, 6, illegal_fp_variable_width_3522_arg5); + setRet(call_illegal_fp_variable_width_3522, 0, ret_val_illegal_fp_variable_width_3522); + setArg(call_valid_reg_overlap_3523, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3523, 1, vs1); + setArg(call_valid_reg_overlap_3523, 2, vd); + setArg(call_valid_reg_overlap_3523, 3, valid_reg_overlap_3523_arg2); + setArg(call_valid_reg_overlap_3523, 4, valid_reg_overlap_3523_arg3); + setRet(call_valid_reg_overlap_3523, 0, ret_val_valid_reg_overlap_3523); + setArg(call_valid_reg_overlap_3524, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3524, 1, vs2); + setArg(call_valid_reg_overlap_3524, 2, vd); + setArg(call_valid_reg_overlap_3524, 3, valid_reg_overlap_3524_arg2); + setArg(call_valid_reg_overlap_3524, 4, valid_reg_overlap_3524_arg3); + setRet(call_valid_reg_overlap_3524, 0, ret_val_valid_reg_overlap_3524); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3526; + x86::Gp ret_val_sew_3526 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3526, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3525; + auto fp_vector_vector_wv_3525_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3525_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3525_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3525_arg10 = rm; + auto fp_vector_vector_wv_3525_arg11 = ret_val_sew_3526; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3525, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3526, 0, reinterpret_cast(this)); + setRet(call_sew_3526, 0, ret_val_sew_3526); + setArg(call_fp_vector_vector_wv_3525, 0, V); + setArg(call_fp_vector_vector_wv_3525, 1, 62); + setArg(call_fp_vector_vector_wv_3525, 2, 1); + setArg(call_fp_vector_vector_wv_3525, 3, fp_vector_vector_wv_3525_arg3); + setArg(call_fp_vector_vector_wv_3525, 4, fp_vector_vector_wv_3525_arg4); + setArg(call_fp_vector_vector_wv_3525, 5, fp_vector_vector_wv_3525_arg5); + setArg(call_fp_vector_vector_wv_3525, 6, vm); + setArg(call_fp_vector_vector_wv_3525, 7, vd); + setArg(call_fp_vector_vector_wv_3525, 8, vs2); + setArg(call_fp_vector_vector_wv_3525, 9, vs1); + setArg(call_fp_vector_vector_wv_3525, 10, fp_vector_vector_wv_3525_arg10); + setArg(call_fp_vector_vector_wv_3525, 11, fp_vector_vector_wv_3525_arg11); + InvokeNode* call_fget_flags_3527; + x86::Gp ret_val_fget_flags_3527 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3527, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3527; + setRet(call_fget_flags_3527, 0, ret_val_fget_flags_3527); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3528 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3528, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3528, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 777); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 778: VFWNMSAC__VF */ + continuation_e __vfwnmsac__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfwnmsac.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWNMSAC__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 778); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3529; + x86::Gp ret_val_get_sew_pow_3529 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3529, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3530 = get_reg(cc, 8, false); + mov(cc, tmp3530, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3530, (ret_val_get_sew_pow_3529))), 8, false), ~ 1); + setArg(call_get_sew_pow_3529, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3529, 0, ret_val_get_sew_pow_3529); + InvokeNode* call_get_lmul_pow_3531; + x86::Gp ret_val_get_lmul_pow_3531 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3531, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3531; + setArg(call_get_lmul_pow_3531, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3531, 0, ret_val_get_lmul_pow_3531); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3532; + auto illegal_fp_variable_width_3532_arg2 = SEW; + auto illegal_fp_variable_width_3532_arg3 = rm; + auto illegal_fp_variable_width_3532_arg4 = SEW_widen; + auto illegal_fp_variable_width_3532_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3532 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3532, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3533; + auto valid_reg_overlap_3533_arg2 = LMUL_pow; + auto valid_reg_overlap_3533_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3533 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3533, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3532, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3533)); + setArg(call_illegal_fp_variable_width_3532, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3532, 1, vd); + setArg(call_illegal_fp_variable_width_3532, 2, vm); + setArg(call_illegal_fp_variable_width_3532, 3, illegal_fp_variable_width_3532_arg2); + setArg(call_illegal_fp_variable_width_3532, 4, illegal_fp_variable_width_3532_arg3); + setArg(call_illegal_fp_variable_width_3532, 5, illegal_fp_variable_width_3532_arg4); + setArg(call_illegal_fp_variable_width_3532, 6, illegal_fp_variable_width_3532_arg5); + setRet(call_illegal_fp_variable_width_3532, 0, ret_val_illegal_fp_variable_width_3532); + setArg(call_valid_reg_overlap_3533, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3533, 1, vs2); + setArg(call_valid_reg_overlap_3533, 2, vd); + setArg(call_valid_reg_overlap_3533, 3, valid_reg_overlap_3533_arg2); + setArg(call_valid_reg_overlap_3533, 4, valid_reg_overlap_3533_arg3); + setRet(call_valid_reg_overlap_3533, 0, ret_val_valid_reg_overlap_3533); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3535; + x86::Gp ret_val_sew_3535 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3535, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3534; + auto fp_vector_imm_wv_3534_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3534_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3534_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3534_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_wv_3534_arg10 = rm; + auto fp_vector_imm_wv_3534_arg11 = ret_val_sew_3535; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_wv_3534, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3535, 0, reinterpret_cast(this)); + setRet(call_sew_3535, 0, ret_val_sew_3535); + setArg(call_fp_vector_imm_wv_3534, 0, V); + setArg(call_fp_vector_imm_wv_3534, 1, 63); + setArg(call_fp_vector_imm_wv_3534, 2, 5); + setArg(call_fp_vector_imm_wv_3534, 3, fp_vector_imm_wv_3534_arg3); + setArg(call_fp_vector_imm_wv_3534, 4, fp_vector_imm_wv_3534_arg4); + setArg(call_fp_vector_imm_wv_3534, 5, fp_vector_imm_wv_3534_arg5); + setArg(call_fp_vector_imm_wv_3534, 6, vm); + setArg(call_fp_vector_imm_wv_3534, 7, vd); + setArg(call_fp_vector_imm_wv_3534, 8, vs2); + setArg(call_fp_vector_imm_wv_3534, 9, fp_vector_imm_wv_3534_arg9); + setArg(call_fp_vector_imm_wv_3534, 10, fp_vector_imm_wv_3534_arg10); + setArg(call_fp_vector_imm_wv_3534, 11, fp_vector_imm_wv_3534_arg11); + InvokeNode* call_fget_flags_3536; + x86::Gp ret_val_fget_flags_3536 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3536, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3536; + setRet(call_fget_flags_3536, 0, ret_val_fget_flags_3536); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3537 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3537, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3537, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 778); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 779: VFWNMSAC__VV */ + continuation_e __vfwnmsac__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfwnmsac.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWNMSAC__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 779); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3538; + x86::Gp ret_val_get_sew_pow_3538 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3538, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3539 = get_reg(cc, 8, false); + mov(cc, tmp3539, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3539, (ret_val_get_sew_pow_3538))), 8, false), ~ 1); + setArg(call_get_sew_pow_3538, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3538, 0, ret_val_get_sew_pow_3538); + InvokeNode* call_get_lmul_pow_3540; + x86::Gp ret_val_get_lmul_pow_3540 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3540, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3540; + setArg(call_get_lmul_pow_3540, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3540, 0, ret_val_get_lmul_pow_3540); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3541; + auto illegal_fp_variable_width_3541_arg2 = SEW; + auto illegal_fp_variable_width_3541_arg3 = rm; + auto illegal_fp_variable_width_3541_arg4 = SEW_widen; + auto illegal_fp_variable_width_3541_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3541 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3541, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3542; + auto valid_reg_overlap_3542_arg2 = LMUL_pow; + auto valid_reg_overlap_3542_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3542 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3542, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3543; + auto valid_reg_overlap_3543_arg2 = LMUL_pow; + auto valid_reg_overlap_3543_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3543 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3543, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3541, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3542)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3543)); + setArg(call_illegal_fp_variable_width_3541, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3541, 1, vd); + setArg(call_illegal_fp_variable_width_3541, 2, vm); + setArg(call_illegal_fp_variable_width_3541, 3, illegal_fp_variable_width_3541_arg2); + setArg(call_illegal_fp_variable_width_3541, 4, illegal_fp_variable_width_3541_arg3); + setArg(call_illegal_fp_variable_width_3541, 5, illegal_fp_variable_width_3541_arg4); + setArg(call_illegal_fp_variable_width_3541, 6, illegal_fp_variable_width_3541_arg5); + setRet(call_illegal_fp_variable_width_3541, 0, ret_val_illegal_fp_variable_width_3541); + setArg(call_valid_reg_overlap_3542, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3542, 1, vs1); + setArg(call_valid_reg_overlap_3542, 2, vd); + setArg(call_valid_reg_overlap_3542, 3, valid_reg_overlap_3542_arg2); + setArg(call_valid_reg_overlap_3542, 4, valid_reg_overlap_3542_arg3); + setRet(call_valid_reg_overlap_3542, 0, ret_val_valid_reg_overlap_3542); + setArg(call_valid_reg_overlap_3543, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3543, 1, vs2); + setArg(call_valid_reg_overlap_3543, 2, vd); + setArg(call_valid_reg_overlap_3543, 3, valid_reg_overlap_3543_arg2); + setArg(call_valid_reg_overlap_3543, 4, valid_reg_overlap_3543_arg3); + setRet(call_valid_reg_overlap_3543, 0, ret_val_valid_reg_overlap_3543); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3545; + x86::Gp ret_val_sew_3545 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3545, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3544; + auto fp_vector_vector_wv_3544_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3544_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3544_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3544_arg10 = rm; + auto fp_vector_vector_wv_3544_arg11 = ret_val_sew_3545; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_wv_3544, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3545, 0, reinterpret_cast(this)); + setRet(call_sew_3545, 0, ret_val_sew_3545); + setArg(call_fp_vector_vector_wv_3544, 0, V); + setArg(call_fp_vector_vector_wv_3544, 1, 63); + setArg(call_fp_vector_vector_wv_3544, 2, 1); + setArg(call_fp_vector_vector_wv_3544, 3, fp_vector_vector_wv_3544_arg3); + setArg(call_fp_vector_vector_wv_3544, 4, fp_vector_vector_wv_3544_arg4); + setArg(call_fp_vector_vector_wv_3544, 5, fp_vector_vector_wv_3544_arg5); + setArg(call_fp_vector_vector_wv_3544, 6, vm); + setArg(call_fp_vector_vector_wv_3544, 7, vd); + setArg(call_fp_vector_vector_wv_3544, 8, vs2); + setArg(call_fp_vector_vector_wv_3544, 9, vs1); + setArg(call_fp_vector_vector_wv_3544, 10, fp_vector_vector_wv_3544_arg10); + setArg(call_fp_vector_vector_wv_3544, 11, fp_vector_vector_wv_3544_arg11); + InvokeNode* call_fget_flags_3546; + x86::Gp ret_val_fget_flags_3546 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3546, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3546; + setRet(call_fget_flags_3546, 0, ret_val_fget_flags_3546); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3547 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3547, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3547, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 779); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 780: VFSQRT__V */ + continuation_e __vfsqrt__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfsqrt.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSQRT__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 780); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3548; + x86::Gp ret_val_get_sew_pow_3548 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3548, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3549 = get_reg(cc, 8, false); + mov(cc, tmp3549, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3549, (ret_val_get_sew_pow_3548))), 8, false), ~ 1); + setArg(call_get_sew_pow_3548, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3548, 0, ret_val_get_sew_pow_3548); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3550; + auto illegal_fp_normal_3550_arg2 = SEW; + auto illegal_fp_normal_3550_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3550 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3550, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3550; + setArg(call_illegal_fp_normal_3550, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3550, 1, vd); + setArg(call_illegal_fp_normal_3550, 2, vm); + setArg(call_illegal_fp_normal_3550, 3, illegal_fp_normal_3550_arg2); + setArg(call_illegal_fp_normal_3550, 4, illegal_fp_normal_3550_arg3); + setRet(call_illegal_fp_normal_3550, 0, ret_val_illegal_fp_normal_3550); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3552; + x86::Gp ret_val_sew_3552 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3552, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3551; + auto fp_vector_unary_op_3551_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3551_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3551_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3551_arg9 = rm; + auto fp_vector_unary_op_3551_arg10 = ret_val_sew_3552; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3551, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3552, 0, reinterpret_cast(this)); + setRet(call_sew_3552, 0, ret_val_sew_3552); + setArg(call_fp_vector_unary_op_3551, 0, V); + setArg(call_fp_vector_unary_op_3551, 1, 19); + setArg(call_fp_vector_unary_op_3551, 2, 0); + setArg(call_fp_vector_unary_op_3551, 3, fp_vector_unary_op_3551_arg3); + setArg(call_fp_vector_unary_op_3551, 4, fp_vector_unary_op_3551_arg4); + setArg(call_fp_vector_unary_op_3551, 5, fp_vector_unary_op_3551_arg5); + setArg(call_fp_vector_unary_op_3551, 6, vm); + setArg(call_fp_vector_unary_op_3551, 7, vd); + setArg(call_fp_vector_unary_op_3551, 8, vs2); + setArg(call_fp_vector_unary_op_3551, 9, fp_vector_unary_op_3551_arg9); + setArg(call_fp_vector_unary_op_3551, 10, fp_vector_unary_op_3551_arg10); + InvokeNode* call_fget_flags_3553; + x86::Gp ret_val_fget_flags_3553 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3553, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3553; + setRet(call_fget_flags_3553, 0, ret_val_fget_flags_3553); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3554 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3554, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3554, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 780); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 781: VFRSQRT7__V */ + continuation_e __vfrsqrt7__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfrsqrt7.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFRSQRT7__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 781); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3555; + x86::Gp ret_val_get_sew_pow_3555 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3555, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3556 = get_reg(cc, 8, false); + mov(cc, tmp3556, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3556, (ret_val_get_sew_pow_3555))), 8, false), ~ 1); + setArg(call_get_sew_pow_3555, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3555, 0, ret_val_get_sew_pow_3555); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3557; + auto illegal_fp_normal_3557_arg2 = SEW; + auto illegal_fp_normal_3557_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3557 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3557, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3557; + setArg(call_illegal_fp_normal_3557, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3557, 1, vd); + setArg(call_illegal_fp_normal_3557, 2, vm); + setArg(call_illegal_fp_normal_3557, 3, illegal_fp_normal_3557_arg2); + setArg(call_illegal_fp_normal_3557, 4, illegal_fp_normal_3557_arg3); + setRet(call_illegal_fp_normal_3557, 0, ret_val_illegal_fp_normal_3557); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3559; + x86::Gp ret_val_sew_3559 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3559, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3558; + auto fp_vector_unary_op_3558_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3558_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3558_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3558_arg9 = rm; + auto fp_vector_unary_op_3558_arg10 = ret_val_sew_3559; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3558, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3559, 0, reinterpret_cast(this)); + setRet(call_sew_3559, 0, ret_val_sew_3559); + setArg(call_fp_vector_unary_op_3558, 0, V); + setArg(call_fp_vector_unary_op_3558, 1, 19); + setArg(call_fp_vector_unary_op_3558, 2, 4); + setArg(call_fp_vector_unary_op_3558, 3, fp_vector_unary_op_3558_arg3); + setArg(call_fp_vector_unary_op_3558, 4, fp_vector_unary_op_3558_arg4); + setArg(call_fp_vector_unary_op_3558, 5, fp_vector_unary_op_3558_arg5); + setArg(call_fp_vector_unary_op_3558, 6, vm); + setArg(call_fp_vector_unary_op_3558, 7, vd); + setArg(call_fp_vector_unary_op_3558, 8, vs2); + setArg(call_fp_vector_unary_op_3558, 9, fp_vector_unary_op_3558_arg9); + setArg(call_fp_vector_unary_op_3558, 10, fp_vector_unary_op_3558_arg10); + InvokeNode* call_fget_flags_3560; + x86::Gp ret_val_fget_flags_3560 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3560, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3560; + setRet(call_fget_flags_3560, 0, ret_val_fget_flags_3560); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3561 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3561, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3561, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 781); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 782: VFREC7__V */ + continuation_e __vfrec7__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfrec7.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFREC7__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 782); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3562; + x86::Gp ret_val_get_sew_pow_3562 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3562, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3563 = get_reg(cc, 8, false); + mov(cc, tmp3563, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3563, (ret_val_get_sew_pow_3562))), 8, false), ~ 1); + setArg(call_get_sew_pow_3562, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3562, 0, ret_val_get_sew_pow_3562); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3564; + auto illegal_fp_normal_3564_arg2 = SEW; + auto illegal_fp_normal_3564_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3564 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3564, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3564; + setArg(call_illegal_fp_normal_3564, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3564, 1, vd); + setArg(call_illegal_fp_normal_3564, 2, vm); + setArg(call_illegal_fp_normal_3564, 3, illegal_fp_normal_3564_arg2); + setArg(call_illegal_fp_normal_3564, 4, illegal_fp_normal_3564_arg3); + setRet(call_illegal_fp_normal_3564, 0, ret_val_illegal_fp_normal_3564); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3566; + x86::Gp ret_val_sew_3566 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3566, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3565; + auto fp_vector_unary_op_3565_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3565_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3565_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3565_arg9 = rm; + auto fp_vector_unary_op_3565_arg10 = ret_val_sew_3566; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3565, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3566, 0, reinterpret_cast(this)); + setRet(call_sew_3566, 0, ret_val_sew_3566); + setArg(call_fp_vector_unary_op_3565, 0, V); + setArg(call_fp_vector_unary_op_3565, 1, 19); + setArg(call_fp_vector_unary_op_3565, 2, 5); + setArg(call_fp_vector_unary_op_3565, 3, fp_vector_unary_op_3565_arg3); + setArg(call_fp_vector_unary_op_3565, 4, fp_vector_unary_op_3565_arg4); + setArg(call_fp_vector_unary_op_3565, 5, fp_vector_unary_op_3565_arg5); + setArg(call_fp_vector_unary_op_3565, 6, vm); + setArg(call_fp_vector_unary_op_3565, 7, vd); + setArg(call_fp_vector_unary_op_3565, 8, vs2); + setArg(call_fp_vector_unary_op_3565, 9, fp_vector_unary_op_3565_arg9); + setArg(call_fp_vector_unary_op_3565, 10, fp_vector_unary_op_3565_arg10); + InvokeNode* call_fget_flags_3567; + x86::Gp ret_val_fget_flags_3567 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3567, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3567; + setRet(call_fget_flags_3567, 0, ret_val_fget_flags_3567); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3568 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3568, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3568, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 782); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 783: VFMIN__VF */ + continuation_e __vfmin__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmin.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMIN__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 783); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3569; + x86::Gp ret_val_get_sew_pow_3569 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3569, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3570 = get_reg(cc, 8, false); + mov(cc, tmp3570, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3570, (ret_val_get_sew_pow_3569))), 8, false), ~ 1); + setArg(call_get_sew_pow_3569, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3569, 0, ret_val_get_sew_pow_3569); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3571; + auto illegal_fp_normal_3571_arg2 = SEW; + auto illegal_fp_normal_3571_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3571 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3571, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3571; + setArg(call_illegal_fp_normal_3571, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3571, 1, vd); + setArg(call_illegal_fp_normal_3571, 2, vm); + setArg(call_illegal_fp_normal_3571, 3, illegal_fp_normal_3571_arg2); + setArg(call_illegal_fp_normal_3571, 4, illegal_fp_normal_3571_arg3); + setRet(call_illegal_fp_normal_3571, 0, ret_val_illegal_fp_normal_3571); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3573; + x86::Gp ret_val_sew_3573 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3573, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3572; + auto fp_vector_imm_op_3572_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3572_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3572_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3572_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3572_arg10 = rm; + auto fp_vector_imm_op_3572_arg11 = ret_val_sew_3573; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3572, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3573, 0, reinterpret_cast(this)); + setRet(call_sew_3573, 0, ret_val_sew_3573); + setArg(call_fp_vector_imm_op_3572, 0, V); + setArg(call_fp_vector_imm_op_3572, 1, 4); + setArg(call_fp_vector_imm_op_3572, 2, 5); + setArg(call_fp_vector_imm_op_3572, 3, fp_vector_imm_op_3572_arg3); + setArg(call_fp_vector_imm_op_3572, 4, fp_vector_imm_op_3572_arg4); + setArg(call_fp_vector_imm_op_3572, 5, fp_vector_imm_op_3572_arg5); + setArg(call_fp_vector_imm_op_3572, 6, vm); + setArg(call_fp_vector_imm_op_3572, 7, vd); + setArg(call_fp_vector_imm_op_3572, 8, vs2); + setArg(call_fp_vector_imm_op_3572, 9, fp_vector_imm_op_3572_arg9); + setArg(call_fp_vector_imm_op_3572, 10, fp_vector_imm_op_3572_arg10); + setArg(call_fp_vector_imm_op_3572, 11, fp_vector_imm_op_3572_arg11); + } + cc.bind(label_merge); + } + auto tmp3574 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3574, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3574, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 783); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 784: VFMIN__VV */ + continuation_e __vfmin__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmin.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMIN__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 784); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3575; + x86::Gp ret_val_get_sew_pow_3575 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3575, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3576 = get_reg(cc, 8, false); + mov(cc, tmp3576, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3576, (ret_val_get_sew_pow_3575))), 8, false), ~ 1); + setArg(call_get_sew_pow_3575, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3575, 0, ret_val_get_sew_pow_3575); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3577; + auto illegal_fp_normal_3577_arg2 = SEW; + auto illegal_fp_normal_3577_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3577 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3577, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3577; + setArg(call_illegal_fp_normal_3577, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3577, 1, vd); + setArg(call_illegal_fp_normal_3577, 2, vm); + setArg(call_illegal_fp_normal_3577, 3, illegal_fp_normal_3577_arg2); + setArg(call_illegal_fp_normal_3577, 4, illegal_fp_normal_3577_arg3); + setRet(call_illegal_fp_normal_3577, 0, ret_val_illegal_fp_normal_3577); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3579; + x86::Gp ret_val_sew_3579 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3579, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3578; + auto fp_vector_vector_op_3578_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3578_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3578_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3578_arg10 = rm; + auto fp_vector_vector_op_3578_arg11 = ret_val_sew_3579; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3578, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3579, 0, reinterpret_cast(this)); + setRet(call_sew_3579, 0, ret_val_sew_3579); + setArg(call_fp_vector_vector_op_3578, 0, V); + setArg(call_fp_vector_vector_op_3578, 1, 4); + setArg(call_fp_vector_vector_op_3578, 2, 1); + setArg(call_fp_vector_vector_op_3578, 3, fp_vector_vector_op_3578_arg3); + setArg(call_fp_vector_vector_op_3578, 4, fp_vector_vector_op_3578_arg4); + setArg(call_fp_vector_vector_op_3578, 5, fp_vector_vector_op_3578_arg5); + setArg(call_fp_vector_vector_op_3578, 6, vm); + setArg(call_fp_vector_vector_op_3578, 7, vd); + setArg(call_fp_vector_vector_op_3578, 8, vs2); + setArg(call_fp_vector_vector_op_3578, 9, vs1); + setArg(call_fp_vector_vector_op_3578, 10, fp_vector_vector_op_3578_arg10); + setArg(call_fp_vector_vector_op_3578, 11, fp_vector_vector_op_3578_arg11); + } + cc.bind(label_merge); + } + auto tmp3580 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3580, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3580, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 784); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 785: VFMAX__VF */ + continuation_e __vfmax__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfmax.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMAX__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 785); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3581; + x86::Gp ret_val_get_sew_pow_3581 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3581, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3582 = get_reg(cc, 8, false); + mov(cc, tmp3582, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3582, (ret_val_get_sew_pow_3581))), 8, false), ~ 1); + setArg(call_get_sew_pow_3581, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3581, 0, ret_val_get_sew_pow_3581); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3583; + auto illegal_fp_normal_3583_arg2 = SEW; + auto illegal_fp_normal_3583_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3583 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3583, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3583; + setArg(call_illegal_fp_normal_3583, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3583, 1, vd); + setArg(call_illegal_fp_normal_3583, 2, vm); + setArg(call_illegal_fp_normal_3583, 3, illegal_fp_normal_3583_arg2); + setArg(call_illegal_fp_normal_3583, 4, illegal_fp_normal_3583_arg3); + setRet(call_illegal_fp_normal_3583, 0, ret_val_illegal_fp_normal_3583); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3585; + x86::Gp ret_val_sew_3585 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3585, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3584; + auto fp_vector_imm_op_3584_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3584_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3584_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3584_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3584_arg10 = rm; + auto fp_vector_imm_op_3584_arg11 = ret_val_sew_3585; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3584, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3585, 0, reinterpret_cast(this)); + setRet(call_sew_3585, 0, ret_val_sew_3585); + setArg(call_fp_vector_imm_op_3584, 0, V); + setArg(call_fp_vector_imm_op_3584, 1, 6); + setArg(call_fp_vector_imm_op_3584, 2, 5); + setArg(call_fp_vector_imm_op_3584, 3, fp_vector_imm_op_3584_arg3); + setArg(call_fp_vector_imm_op_3584, 4, fp_vector_imm_op_3584_arg4); + setArg(call_fp_vector_imm_op_3584, 5, fp_vector_imm_op_3584_arg5); + setArg(call_fp_vector_imm_op_3584, 6, vm); + setArg(call_fp_vector_imm_op_3584, 7, vd); + setArg(call_fp_vector_imm_op_3584, 8, vs2); + setArg(call_fp_vector_imm_op_3584, 9, fp_vector_imm_op_3584_arg9); + setArg(call_fp_vector_imm_op_3584, 10, fp_vector_imm_op_3584_arg10); + setArg(call_fp_vector_imm_op_3584, 11, fp_vector_imm_op_3584_arg11); + } + cc.bind(label_merge); + } + auto tmp3586 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3586, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3586, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 785); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 786: VFMAX__VV */ + continuation_e __vfmax__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfmax.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMAX__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 786); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3587; + x86::Gp ret_val_get_sew_pow_3587 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3587, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3588 = get_reg(cc, 8, false); + mov(cc, tmp3588, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3588, (ret_val_get_sew_pow_3587))), 8, false), ~ 1); + setArg(call_get_sew_pow_3587, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3587, 0, ret_val_get_sew_pow_3587); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3589; + auto illegal_fp_normal_3589_arg2 = SEW; + auto illegal_fp_normal_3589_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3589 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3589, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3589; + setArg(call_illegal_fp_normal_3589, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3589, 1, vd); + setArg(call_illegal_fp_normal_3589, 2, vm); + setArg(call_illegal_fp_normal_3589, 3, illegal_fp_normal_3589_arg2); + setArg(call_illegal_fp_normal_3589, 4, illegal_fp_normal_3589_arg3); + setRet(call_illegal_fp_normal_3589, 0, ret_val_illegal_fp_normal_3589); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3591; + x86::Gp ret_val_sew_3591 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3591, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3590; + auto fp_vector_vector_op_3590_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3590_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3590_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3590_arg10 = rm; + auto fp_vector_vector_op_3590_arg11 = ret_val_sew_3591; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3590, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3591, 0, reinterpret_cast(this)); + setRet(call_sew_3591, 0, ret_val_sew_3591); + setArg(call_fp_vector_vector_op_3590, 0, V); + setArg(call_fp_vector_vector_op_3590, 1, 6); + setArg(call_fp_vector_vector_op_3590, 2, 1); + setArg(call_fp_vector_vector_op_3590, 3, fp_vector_vector_op_3590_arg3); + setArg(call_fp_vector_vector_op_3590, 4, fp_vector_vector_op_3590_arg4); + setArg(call_fp_vector_vector_op_3590, 5, fp_vector_vector_op_3590_arg5); + setArg(call_fp_vector_vector_op_3590, 6, vm); + setArg(call_fp_vector_vector_op_3590, 7, vd); + setArg(call_fp_vector_vector_op_3590, 8, vs2); + setArg(call_fp_vector_vector_op_3590, 9, vs1); + setArg(call_fp_vector_vector_op_3590, 10, fp_vector_vector_op_3590_arg10); + setArg(call_fp_vector_vector_op_3590, 11, fp_vector_vector_op_3590_arg11); + } + cc.bind(label_merge); + } + auto tmp3592 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3592, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3592, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 786); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 787: VFSGNJ__VF */ + continuation_e __vfsgnj__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnj.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJ__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 787); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3593; + x86::Gp ret_val_get_sew_pow_3593 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3593, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3594 = get_reg(cc, 8, false); + mov(cc, tmp3594, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3594, (ret_val_get_sew_pow_3593))), 8, false), ~ 1); + setArg(call_get_sew_pow_3593, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3593, 0, ret_val_get_sew_pow_3593); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3595; + auto illegal_fp_normal_3595_arg2 = SEW; + auto illegal_fp_normal_3595_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3595 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3595, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3595; + setArg(call_illegal_fp_normal_3595, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3595, 1, vd); + setArg(call_illegal_fp_normal_3595, 2, vm); + setArg(call_illegal_fp_normal_3595, 3, illegal_fp_normal_3595_arg2); + setArg(call_illegal_fp_normal_3595, 4, illegal_fp_normal_3595_arg3); + setRet(call_illegal_fp_normal_3595, 0, ret_val_illegal_fp_normal_3595); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3597; + x86::Gp ret_val_sew_3597 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3597, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3596; + auto fp_vector_imm_op_3596_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3596_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3596_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3596_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3596_arg10 = rm; + auto fp_vector_imm_op_3596_arg11 = ret_val_sew_3597; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3596, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3597, 0, reinterpret_cast(this)); + setRet(call_sew_3597, 0, ret_val_sew_3597); + setArg(call_fp_vector_imm_op_3596, 0, V); + setArg(call_fp_vector_imm_op_3596, 1, 8); + setArg(call_fp_vector_imm_op_3596, 2, 5); + setArg(call_fp_vector_imm_op_3596, 3, fp_vector_imm_op_3596_arg3); + setArg(call_fp_vector_imm_op_3596, 4, fp_vector_imm_op_3596_arg4); + setArg(call_fp_vector_imm_op_3596, 5, fp_vector_imm_op_3596_arg5); + setArg(call_fp_vector_imm_op_3596, 6, vm); + setArg(call_fp_vector_imm_op_3596, 7, vd); + setArg(call_fp_vector_imm_op_3596, 8, vs2); + setArg(call_fp_vector_imm_op_3596, 9, fp_vector_imm_op_3596_arg9); + setArg(call_fp_vector_imm_op_3596, 10, fp_vector_imm_op_3596_arg10); + setArg(call_fp_vector_imm_op_3596, 11, fp_vector_imm_op_3596_arg11); + } + cc.bind(label_merge); + } + auto tmp3598 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3598, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3598, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 787); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 788: VFSGNJ__VV */ + continuation_e __vfsgnj__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnj.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJ__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 788); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3599; + x86::Gp ret_val_get_sew_pow_3599 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3599, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3600 = get_reg(cc, 8, false); + mov(cc, tmp3600, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3600, (ret_val_get_sew_pow_3599))), 8, false), ~ 1); + setArg(call_get_sew_pow_3599, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3599, 0, ret_val_get_sew_pow_3599); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3601; + auto illegal_fp_normal_3601_arg2 = SEW; + auto illegal_fp_normal_3601_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3601 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3601, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3601; + setArg(call_illegal_fp_normal_3601, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3601, 1, vd); + setArg(call_illegal_fp_normal_3601, 2, vm); + setArg(call_illegal_fp_normal_3601, 3, illegal_fp_normal_3601_arg2); + setArg(call_illegal_fp_normal_3601, 4, illegal_fp_normal_3601_arg3); + setRet(call_illegal_fp_normal_3601, 0, ret_val_illegal_fp_normal_3601); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3603; + x86::Gp ret_val_sew_3603 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3603, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3602; + auto fp_vector_vector_op_3602_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3602_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3602_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3602_arg10 = rm; + auto fp_vector_vector_op_3602_arg11 = ret_val_sew_3603; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3602, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3603, 0, reinterpret_cast(this)); + setRet(call_sew_3603, 0, ret_val_sew_3603); + setArg(call_fp_vector_vector_op_3602, 0, V); + setArg(call_fp_vector_vector_op_3602, 1, 8); + setArg(call_fp_vector_vector_op_3602, 2, 1); + setArg(call_fp_vector_vector_op_3602, 3, fp_vector_vector_op_3602_arg3); + setArg(call_fp_vector_vector_op_3602, 4, fp_vector_vector_op_3602_arg4); + setArg(call_fp_vector_vector_op_3602, 5, fp_vector_vector_op_3602_arg5); + setArg(call_fp_vector_vector_op_3602, 6, vm); + setArg(call_fp_vector_vector_op_3602, 7, vd); + setArg(call_fp_vector_vector_op_3602, 8, vs2); + setArg(call_fp_vector_vector_op_3602, 9, vs1); + setArg(call_fp_vector_vector_op_3602, 10, fp_vector_vector_op_3602_arg10); + setArg(call_fp_vector_vector_op_3602, 11, fp_vector_vector_op_3602_arg11); + } + cc.bind(label_merge); + } + auto tmp3604 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3604, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3604, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 788); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 789: VFSGNJN__VF */ + continuation_e __vfsgnjn__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnjn.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJN__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 789); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3605; + x86::Gp ret_val_get_sew_pow_3605 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3605, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3606 = get_reg(cc, 8, false); + mov(cc, tmp3606, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3606, (ret_val_get_sew_pow_3605))), 8, false), ~ 1); + setArg(call_get_sew_pow_3605, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3605, 0, ret_val_get_sew_pow_3605); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3607; + auto illegal_fp_normal_3607_arg2 = SEW; + auto illegal_fp_normal_3607_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3607 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3607, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3607; + setArg(call_illegal_fp_normal_3607, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3607, 1, vd); + setArg(call_illegal_fp_normal_3607, 2, vm); + setArg(call_illegal_fp_normal_3607, 3, illegal_fp_normal_3607_arg2); + setArg(call_illegal_fp_normal_3607, 4, illegal_fp_normal_3607_arg3); + setRet(call_illegal_fp_normal_3607, 0, ret_val_illegal_fp_normal_3607); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3609; + x86::Gp ret_val_sew_3609 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3609, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3608; + auto fp_vector_imm_op_3608_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3608_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3608_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3608_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3608_arg10 = rm; + auto fp_vector_imm_op_3608_arg11 = ret_val_sew_3609; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3608, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3609, 0, reinterpret_cast(this)); + setRet(call_sew_3609, 0, ret_val_sew_3609); + setArg(call_fp_vector_imm_op_3608, 0, V); + setArg(call_fp_vector_imm_op_3608, 1, 9); + setArg(call_fp_vector_imm_op_3608, 2, 5); + setArg(call_fp_vector_imm_op_3608, 3, fp_vector_imm_op_3608_arg3); + setArg(call_fp_vector_imm_op_3608, 4, fp_vector_imm_op_3608_arg4); + setArg(call_fp_vector_imm_op_3608, 5, fp_vector_imm_op_3608_arg5); + setArg(call_fp_vector_imm_op_3608, 6, vm); + setArg(call_fp_vector_imm_op_3608, 7, vd); + setArg(call_fp_vector_imm_op_3608, 8, vs2); + setArg(call_fp_vector_imm_op_3608, 9, fp_vector_imm_op_3608_arg9); + setArg(call_fp_vector_imm_op_3608, 10, fp_vector_imm_op_3608_arg10); + setArg(call_fp_vector_imm_op_3608, 11, fp_vector_imm_op_3608_arg11); + } + cc.bind(label_merge); + } + auto tmp3610 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3610, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3610, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 789); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 790: VFSGNJN__VV */ + continuation_e __vfsgnjn__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnjn.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJN__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 790); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3611; + x86::Gp ret_val_get_sew_pow_3611 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3611, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3612 = get_reg(cc, 8, false); + mov(cc, tmp3612, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3612, (ret_val_get_sew_pow_3611))), 8, false), ~ 1); + setArg(call_get_sew_pow_3611, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3611, 0, ret_val_get_sew_pow_3611); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3613; + auto illegal_fp_normal_3613_arg2 = SEW; + auto illegal_fp_normal_3613_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3613 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3613, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3613; + setArg(call_illegal_fp_normal_3613, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3613, 1, vd); + setArg(call_illegal_fp_normal_3613, 2, vm); + setArg(call_illegal_fp_normal_3613, 3, illegal_fp_normal_3613_arg2); + setArg(call_illegal_fp_normal_3613, 4, illegal_fp_normal_3613_arg3); + setRet(call_illegal_fp_normal_3613, 0, ret_val_illegal_fp_normal_3613); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3615; + x86::Gp ret_val_sew_3615 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3615, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3614; + auto fp_vector_vector_op_3614_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3614_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3614_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3614_arg10 = rm; + auto fp_vector_vector_op_3614_arg11 = ret_val_sew_3615; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3614, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3615, 0, reinterpret_cast(this)); + setRet(call_sew_3615, 0, ret_val_sew_3615); + setArg(call_fp_vector_vector_op_3614, 0, V); + setArg(call_fp_vector_vector_op_3614, 1, 9); + setArg(call_fp_vector_vector_op_3614, 2, 1); + setArg(call_fp_vector_vector_op_3614, 3, fp_vector_vector_op_3614_arg3); + setArg(call_fp_vector_vector_op_3614, 4, fp_vector_vector_op_3614_arg4); + setArg(call_fp_vector_vector_op_3614, 5, fp_vector_vector_op_3614_arg5); + setArg(call_fp_vector_vector_op_3614, 6, vm); + setArg(call_fp_vector_vector_op_3614, 7, vd); + setArg(call_fp_vector_vector_op_3614, 8, vs2); + setArg(call_fp_vector_vector_op_3614, 9, vs1); + setArg(call_fp_vector_vector_op_3614, 10, fp_vector_vector_op_3614_arg10); + setArg(call_fp_vector_vector_op_3614, 11, fp_vector_vector_op_3614_arg11); + } + cc.bind(label_merge); + } + auto tmp3616 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3616, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3616, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 790); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 791: VFSGNJX__VF */ + continuation_e __vfsgnjx__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vfsgnjx.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJX__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 791); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3617; + x86::Gp ret_val_get_sew_pow_3617 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3617, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3618 = get_reg(cc, 8, false); + mov(cc, tmp3618, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3618, (ret_val_get_sew_pow_3617))), 8, false), ~ 1); + setArg(call_get_sew_pow_3617, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3617, 0, ret_val_get_sew_pow_3617); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3619; + auto illegal_fp_normal_3619_arg2 = SEW; + auto illegal_fp_normal_3619_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3619 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3619, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3619; + setArg(call_illegal_fp_normal_3619, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3619, 1, vd); + setArg(call_illegal_fp_normal_3619, 2, vm); + setArg(call_illegal_fp_normal_3619, 3, illegal_fp_normal_3619_arg2); + setArg(call_illegal_fp_normal_3619, 4, illegal_fp_normal_3619_arg3); + setRet(call_illegal_fp_normal_3619, 0, ret_val_illegal_fp_normal_3619); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3621; + x86::Gp ret_val_sew_3621 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3621, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3620; + auto fp_vector_imm_op_3620_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3620_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3620_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3620_arg9 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto fp_vector_imm_op_3620_arg10 = rm; + auto fp_vector_imm_op_3620_arg11 = ret_val_sew_3621; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_imm_op_3620, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3621, 0, reinterpret_cast(this)); + setRet(call_sew_3621, 0, ret_val_sew_3621); + setArg(call_fp_vector_imm_op_3620, 0, V); + setArg(call_fp_vector_imm_op_3620, 1, 10); + setArg(call_fp_vector_imm_op_3620, 2, 5); + setArg(call_fp_vector_imm_op_3620, 3, fp_vector_imm_op_3620_arg3); + setArg(call_fp_vector_imm_op_3620, 4, fp_vector_imm_op_3620_arg4); + setArg(call_fp_vector_imm_op_3620, 5, fp_vector_imm_op_3620_arg5); + setArg(call_fp_vector_imm_op_3620, 6, vm); + setArg(call_fp_vector_imm_op_3620, 7, vd); + setArg(call_fp_vector_imm_op_3620, 8, vs2); + setArg(call_fp_vector_imm_op_3620, 9, fp_vector_imm_op_3620_arg9); + setArg(call_fp_vector_imm_op_3620, 10, fp_vector_imm_op_3620_arg10); + setArg(call_fp_vector_imm_op_3620, 11, fp_vector_imm_op_3620_arg11); + } + cc.bind(label_merge); + } + auto tmp3622 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3622, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3622, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 791); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 792: VFSGNJX__VV */ + continuation_e __vfsgnjx__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vfsgnjx.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFSGNJX__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 792); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3623; + x86::Gp ret_val_get_sew_pow_3623 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3623, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3624 = get_reg(cc, 8, false); + mov(cc, tmp3624, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3624, (ret_val_get_sew_pow_3623))), 8, false), ~ 1); + setArg(call_get_sew_pow_3623, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3623, 0, ret_val_get_sew_pow_3623); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3625; + auto illegal_fp_normal_3625_arg2 = SEW; + auto illegal_fp_normal_3625_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3625 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3625, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3625; + setArg(call_illegal_fp_normal_3625, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3625, 1, vd); + setArg(call_illegal_fp_normal_3625, 2, vm); + setArg(call_illegal_fp_normal_3625, 3, illegal_fp_normal_3625_arg2); + setArg(call_illegal_fp_normal_3625, 4, illegal_fp_normal_3625_arg3); + setRet(call_illegal_fp_normal_3625, 0, ret_val_illegal_fp_normal_3625); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3627; + x86::Gp ret_val_sew_3627 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3627, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3626; + auto fp_vector_vector_op_3626_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3626_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3626_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3626_arg10 = rm; + auto fp_vector_vector_op_3626_arg11 = ret_val_sew_3627; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_vector_op_3626, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3627, 0, reinterpret_cast(this)); + setRet(call_sew_3627, 0, ret_val_sew_3627); + setArg(call_fp_vector_vector_op_3626, 0, V); + setArg(call_fp_vector_vector_op_3626, 1, 10); + setArg(call_fp_vector_vector_op_3626, 2, 1); + setArg(call_fp_vector_vector_op_3626, 3, fp_vector_vector_op_3626_arg3); + setArg(call_fp_vector_vector_op_3626, 4, fp_vector_vector_op_3626_arg4); + setArg(call_fp_vector_vector_op_3626, 5, fp_vector_vector_op_3626_arg5); + setArg(call_fp_vector_vector_op_3626, 6, vm); + setArg(call_fp_vector_vector_op_3626, 7, vd); + setArg(call_fp_vector_vector_op_3626, 8, vs2); + setArg(call_fp_vector_vector_op_3626, 9, vs1); + setArg(call_fp_vector_vector_op_3626, 10, fp_vector_vector_op_3626_arg10); + setArg(call_fp_vector_vector_op_3626, 11, fp_vector_vector_op_3626_arg11); + } + cc.bind(label_merge); + } + auto tmp3628 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3628, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3628, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 792); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 793: VMFEQ__VF */ + continuation_e __vmfeq__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfeq.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFEQ__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 793); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3629; + x86::Gp ret_val_get_sew_pow_3629 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3629, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3630 = get_reg(cc, 8, false); + mov(cc, tmp3630, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3630, (ret_val_get_sew_pow_3629))), 8, false), ~ 1); + setArg(call_get_sew_pow_3629, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3629, 0, ret_val_get_sew_pow_3629); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3631; + auto illegal_fp_vd_unmasked_3631_arg0 = SEW; + auto illegal_fp_vd_unmasked_3631_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3631 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3631, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3631; + setArg(call_illegal_fp_vd_unmasked_3631, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3631, 1, illegal_fp_vd_unmasked_3631_arg0); + setArg(call_illegal_fp_vd_unmasked_3631, 2, illegal_fp_vd_unmasked_3631_arg1); + setRet(call_illegal_fp_vd_unmasked_3631, 0, ret_val_illegal_fp_vd_unmasked_3631); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3633; + x86::Gp ret_val_sew_3633 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3633, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3632; + auto mask_fp_vector_imm_op_3632_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3632_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3632_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3632_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto mask_fp_vector_imm_op_3632_arg9 = rm; + auto mask_fp_vector_imm_op_3632_arg10 = ret_val_sew_3633; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3632, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3633, 0, reinterpret_cast(this)); + setRet(call_sew_3633, 0, ret_val_sew_3633); + setArg(call_mask_fp_vector_imm_op_3632, 0, V); + setArg(call_mask_fp_vector_imm_op_3632, 1, 24); + setArg(call_mask_fp_vector_imm_op_3632, 2, mask_fp_vector_imm_op_3632_arg2); + setArg(call_mask_fp_vector_imm_op_3632, 3, mask_fp_vector_imm_op_3632_arg3); + setArg(call_mask_fp_vector_imm_op_3632, 4, mask_fp_vector_imm_op_3632_arg4); + setArg(call_mask_fp_vector_imm_op_3632, 5, vm); + setArg(call_mask_fp_vector_imm_op_3632, 6, vd); + setArg(call_mask_fp_vector_imm_op_3632, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3632, 8, mask_fp_vector_imm_op_3632_arg8); + setArg(call_mask_fp_vector_imm_op_3632, 9, mask_fp_vector_imm_op_3632_arg9); + setArg(call_mask_fp_vector_imm_op_3632, 10, mask_fp_vector_imm_op_3632_arg10); + InvokeNode* call_fget_flags_3634; + x86::Gp ret_val_fget_flags_3634 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3634, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3634; + setRet(call_fget_flags_3634, 0, ret_val_fget_flags_3634); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3635 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3635, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3635, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 793); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 794: VMFEQ__VV */ + continuation_e __vmfeq__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfeq.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFEQ__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 794); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3636; + x86::Gp ret_val_get_sew_pow_3636 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3636, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3637 = get_reg(cc, 8, false); + mov(cc, tmp3637, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3637, (ret_val_get_sew_pow_3636))), 8, false), ~ 1); + setArg(call_get_sew_pow_3636, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3636, 0, ret_val_get_sew_pow_3636); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3638; + auto illegal_fp_vd_unmasked_3638_arg0 = SEW; + auto illegal_fp_vd_unmasked_3638_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3638 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3638, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3638; + setArg(call_illegal_fp_vd_unmasked_3638, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3638, 1, illegal_fp_vd_unmasked_3638_arg0); + setArg(call_illegal_fp_vd_unmasked_3638, 2, illegal_fp_vd_unmasked_3638_arg1); + setRet(call_illegal_fp_vd_unmasked_3638, 0, ret_val_illegal_fp_vd_unmasked_3638); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3640; + x86::Gp ret_val_sew_3640 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3640, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3639; + auto mask_fp_vector_vector_op_3639_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3639_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3639_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3639_arg9 = rm; + auto mask_fp_vector_vector_op_3639_arg10 = ret_val_sew_3640; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_vector_op_3639, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3640, 0, reinterpret_cast(this)); + setRet(call_sew_3640, 0, ret_val_sew_3640); + setArg(call_mask_fp_vector_vector_op_3639, 0, V); + setArg(call_mask_fp_vector_vector_op_3639, 1, 24); + setArg(call_mask_fp_vector_vector_op_3639, 2, mask_fp_vector_vector_op_3639_arg2); + setArg(call_mask_fp_vector_vector_op_3639, 3, mask_fp_vector_vector_op_3639_arg3); + setArg(call_mask_fp_vector_vector_op_3639, 4, mask_fp_vector_vector_op_3639_arg4); + setArg(call_mask_fp_vector_vector_op_3639, 5, vm); + setArg(call_mask_fp_vector_vector_op_3639, 6, vd); + setArg(call_mask_fp_vector_vector_op_3639, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3639, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3639, 9, mask_fp_vector_vector_op_3639_arg9); + setArg(call_mask_fp_vector_vector_op_3639, 10, mask_fp_vector_vector_op_3639_arg10); + InvokeNode* call_fget_flags_3641; + x86::Gp ret_val_fget_flags_3641 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3641, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3641; + setRet(call_fget_flags_3641, 0, ret_val_fget_flags_3641); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3642 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3642, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3642, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 794); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 795: VMFNE__VF */ + continuation_e __vmfne__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfne.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFNE__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 795); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3643; + x86::Gp ret_val_get_sew_pow_3643 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3643, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3644 = get_reg(cc, 8, false); + mov(cc, tmp3644, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3644, (ret_val_get_sew_pow_3643))), 8, false), ~ 1); + setArg(call_get_sew_pow_3643, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3643, 0, ret_val_get_sew_pow_3643); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3645; + auto illegal_fp_vd_unmasked_3645_arg0 = SEW; + auto illegal_fp_vd_unmasked_3645_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3645 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3645, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3645; + setArg(call_illegal_fp_vd_unmasked_3645, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3645, 1, illegal_fp_vd_unmasked_3645_arg0); + setArg(call_illegal_fp_vd_unmasked_3645, 2, illegal_fp_vd_unmasked_3645_arg1); + setRet(call_illegal_fp_vd_unmasked_3645, 0, ret_val_illegal_fp_vd_unmasked_3645); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3647; + x86::Gp ret_val_sew_3647 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3647, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3646; + auto mask_fp_vector_imm_op_3646_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3646_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3646_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3646_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto mask_fp_vector_imm_op_3646_arg9 = rm; + auto mask_fp_vector_imm_op_3646_arg10 = ret_val_sew_3647; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3646, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3647, 0, reinterpret_cast(this)); + setRet(call_sew_3647, 0, ret_val_sew_3647); + setArg(call_mask_fp_vector_imm_op_3646, 0, V); + setArg(call_mask_fp_vector_imm_op_3646, 1, 28); + setArg(call_mask_fp_vector_imm_op_3646, 2, mask_fp_vector_imm_op_3646_arg2); + setArg(call_mask_fp_vector_imm_op_3646, 3, mask_fp_vector_imm_op_3646_arg3); + setArg(call_mask_fp_vector_imm_op_3646, 4, mask_fp_vector_imm_op_3646_arg4); + setArg(call_mask_fp_vector_imm_op_3646, 5, vm); + setArg(call_mask_fp_vector_imm_op_3646, 6, vd); + setArg(call_mask_fp_vector_imm_op_3646, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3646, 8, mask_fp_vector_imm_op_3646_arg8); + setArg(call_mask_fp_vector_imm_op_3646, 9, mask_fp_vector_imm_op_3646_arg9); + setArg(call_mask_fp_vector_imm_op_3646, 10, mask_fp_vector_imm_op_3646_arg10); + InvokeNode* call_fget_flags_3648; + x86::Gp ret_val_fget_flags_3648 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3648, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3648; + setRet(call_fget_flags_3648, 0, ret_val_fget_flags_3648); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3649 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3649, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3649, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 795); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 796: VMFNE__VV */ + continuation_e __vmfne__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfne.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFNE__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 796); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3650; + x86::Gp ret_val_get_sew_pow_3650 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3650, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3651 = get_reg(cc, 8, false); + mov(cc, tmp3651, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3651, (ret_val_get_sew_pow_3650))), 8, false), ~ 1); + setArg(call_get_sew_pow_3650, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3650, 0, ret_val_get_sew_pow_3650); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3652; + auto illegal_fp_vd_unmasked_3652_arg0 = SEW; + auto illegal_fp_vd_unmasked_3652_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3652 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3652, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3652; + setArg(call_illegal_fp_vd_unmasked_3652, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3652, 1, illegal_fp_vd_unmasked_3652_arg0); + setArg(call_illegal_fp_vd_unmasked_3652, 2, illegal_fp_vd_unmasked_3652_arg1); + setRet(call_illegal_fp_vd_unmasked_3652, 0, ret_val_illegal_fp_vd_unmasked_3652); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3654; + x86::Gp ret_val_sew_3654 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3654, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3653; + auto mask_fp_vector_vector_op_3653_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3653_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3653_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3653_arg9 = rm; + auto mask_fp_vector_vector_op_3653_arg10 = ret_val_sew_3654; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_vector_op_3653, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3654, 0, reinterpret_cast(this)); + setRet(call_sew_3654, 0, ret_val_sew_3654); + setArg(call_mask_fp_vector_vector_op_3653, 0, V); + setArg(call_mask_fp_vector_vector_op_3653, 1, 28); + setArg(call_mask_fp_vector_vector_op_3653, 2, mask_fp_vector_vector_op_3653_arg2); + setArg(call_mask_fp_vector_vector_op_3653, 3, mask_fp_vector_vector_op_3653_arg3); + setArg(call_mask_fp_vector_vector_op_3653, 4, mask_fp_vector_vector_op_3653_arg4); + setArg(call_mask_fp_vector_vector_op_3653, 5, vm); + setArg(call_mask_fp_vector_vector_op_3653, 6, vd); + setArg(call_mask_fp_vector_vector_op_3653, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3653, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3653, 9, mask_fp_vector_vector_op_3653_arg9); + setArg(call_mask_fp_vector_vector_op_3653, 10, mask_fp_vector_vector_op_3653_arg10); + InvokeNode* call_fget_flags_3655; + x86::Gp ret_val_fget_flags_3655 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3655, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3655; + setRet(call_fget_flags_3655, 0, ret_val_fget_flags_3655); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3656 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3656, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3656, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 796); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 797: VMFLT__VF */ + continuation_e __vmflt__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmflt.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFLT__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 797); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3657; + x86::Gp ret_val_get_sew_pow_3657 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3657, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3658 = get_reg(cc, 8, false); + mov(cc, tmp3658, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3658, (ret_val_get_sew_pow_3657))), 8, false), ~ 1); + setArg(call_get_sew_pow_3657, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3657, 0, ret_val_get_sew_pow_3657); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3659; + auto illegal_fp_vd_unmasked_3659_arg0 = SEW; + auto illegal_fp_vd_unmasked_3659_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3659 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3659, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3659; + setArg(call_illegal_fp_vd_unmasked_3659, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3659, 1, illegal_fp_vd_unmasked_3659_arg0); + setArg(call_illegal_fp_vd_unmasked_3659, 2, illegal_fp_vd_unmasked_3659_arg1); + setRet(call_illegal_fp_vd_unmasked_3659, 0, ret_val_illegal_fp_vd_unmasked_3659); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3661; + x86::Gp ret_val_sew_3661 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3661, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3660; + auto mask_fp_vector_imm_op_3660_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3660_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3660_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3660_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto mask_fp_vector_imm_op_3660_arg9 = rm; + auto mask_fp_vector_imm_op_3660_arg10 = ret_val_sew_3661; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3660, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3661, 0, reinterpret_cast(this)); + setRet(call_sew_3661, 0, ret_val_sew_3661); + setArg(call_mask_fp_vector_imm_op_3660, 0, V); + setArg(call_mask_fp_vector_imm_op_3660, 1, 27); + setArg(call_mask_fp_vector_imm_op_3660, 2, mask_fp_vector_imm_op_3660_arg2); + setArg(call_mask_fp_vector_imm_op_3660, 3, mask_fp_vector_imm_op_3660_arg3); + setArg(call_mask_fp_vector_imm_op_3660, 4, mask_fp_vector_imm_op_3660_arg4); + setArg(call_mask_fp_vector_imm_op_3660, 5, vm); + setArg(call_mask_fp_vector_imm_op_3660, 6, vd); + setArg(call_mask_fp_vector_imm_op_3660, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3660, 8, mask_fp_vector_imm_op_3660_arg8); + setArg(call_mask_fp_vector_imm_op_3660, 9, mask_fp_vector_imm_op_3660_arg9); + setArg(call_mask_fp_vector_imm_op_3660, 10, mask_fp_vector_imm_op_3660_arg10); + InvokeNode* call_fget_flags_3662; + x86::Gp ret_val_fget_flags_3662 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3662, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3662; + setRet(call_fget_flags_3662, 0, ret_val_fget_flags_3662); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3663 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3663, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3663, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 797); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 798: VMFLT__VV */ + continuation_e __vmflt__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmflt.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFLT__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 798); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3664; + x86::Gp ret_val_get_sew_pow_3664 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3664, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3665 = get_reg(cc, 8, false); + mov(cc, tmp3665, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3665, (ret_val_get_sew_pow_3664))), 8, false), ~ 1); + setArg(call_get_sew_pow_3664, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3664, 0, ret_val_get_sew_pow_3664); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3666; + auto illegal_fp_vd_unmasked_3666_arg0 = SEW; + auto illegal_fp_vd_unmasked_3666_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3666 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3666, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3666; + setArg(call_illegal_fp_vd_unmasked_3666, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3666, 1, illegal_fp_vd_unmasked_3666_arg0); + setArg(call_illegal_fp_vd_unmasked_3666, 2, illegal_fp_vd_unmasked_3666_arg1); + setRet(call_illegal_fp_vd_unmasked_3666, 0, ret_val_illegal_fp_vd_unmasked_3666); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3668; + x86::Gp ret_val_sew_3668 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3668, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3667; + auto mask_fp_vector_vector_op_3667_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3667_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3667_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3667_arg9 = rm; + auto mask_fp_vector_vector_op_3667_arg10 = ret_val_sew_3668; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_vector_op_3667, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3668, 0, reinterpret_cast(this)); + setRet(call_sew_3668, 0, ret_val_sew_3668); + setArg(call_mask_fp_vector_vector_op_3667, 0, V); + setArg(call_mask_fp_vector_vector_op_3667, 1, 27); + setArg(call_mask_fp_vector_vector_op_3667, 2, mask_fp_vector_vector_op_3667_arg2); + setArg(call_mask_fp_vector_vector_op_3667, 3, mask_fp_vector_vector_op_3667_arg3); + setArg(call_mask_fp_vector_vector_op_3667, 4, mask_fp_vector_vector_op_3667_arg4); + setArg(call_mask_fp_vector_vector_op_3667, 5, vm); + setArg(call_mask_fp_vector_vector_op_3667, 6, vd); + setArg(call_mask_fp_vector_vector_op_3667, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3667, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3667, 9, mask_fp_vector_vector_op_3667_arg9); + setArg(call_mask_fp_vector_vector_op_3667, 10, mask_fp_vector_vector_op_3667_arg10); + InvokeNode* call_fget_flags_3669; + x86::Gp ret_val_fget_flags_3669 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3669, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3669; + setRet(call_fget_flags_3669, 0, ret_val_fget_flags_3669); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3670 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3670, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3670, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 798); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 799: VMFLE__VF */ + continuation_e __vmfle__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfle.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFLE__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 799); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3671; + x86::Gp ret_val_get_sew_pow_3671 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3671, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3672 = get_reg(cc, 8, false); + mov(cc, tmp3672, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3672, (ret_val_get_sew_pow_3671))), 8, false), ~ 1); + setArg(call_get_sew_pow_3671, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3671, 0, ret_val_get_sew_pow_3671); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3673; + auto illegal_fp_vd_unmasked_3673_arg0 = SEW; + auto illegal_fp_vd_unmasked_3673_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3673 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3673, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3673; + setArg(call_illegal_fp_vd_unmasked_3673, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3673, 1, illegal_fp_vd_unmasked_3673_arg0); + setArg(call_illegal_fp_vd_unmasked_3673, 2, illegal_fp_vd_unmasked_3673_arg1); + setRet(call_illegal_fp_vd_unmasked_3673, 0, ret_val_illegal_fp_vd_unmasked_3673); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3675; + x86::Gp ret_val_sew_3675 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3675, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3674; + auto mask_fp_vector_imm_op_3674_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3674_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3674_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3674_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto mask_fp_vector_imm_op_3674_arg9 = rm; + auto mask_fp_vector_imm_op_3674_arg10 = ret_val_sew_3675; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3674, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3675, 0, reinterpret_cast(this)); + setRet(call_sew_3675, 0, ret_val_sew_3675); + setArg(call_mask_fp_vector_imm_op_3674, 0, V); + setArg(call_mask_fp_vector_imm_op_3674, 1, 25); + setArg(call_mask_fp_vector_imm_op_3674, 2, mask_fp_vector_imm_op_3674_arg2); + setArg(call_mask_fp_vector_imm_op_3674, 3, mask_fp_vector_imm_op_3674_arg3); + setArg(call_mask_fp_vector_imm_op_3674, 4, mask_fp_vector_imm_op_3674_arg4); + setArg(call_mask_fp_vector_imm_op_3674, 5, vm); + setArg(call_mask_fp_vector_imm_op_3674, 6, vd); + setArg(call_mask_fp_vector_imm_op_3674, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3674, 8, mask_fp_vector_imm_op_3674_arg8); + setArg(call_mask_fp_vector_imm_op_3674, 9, mask_fp_vector_imm_op_3674_arg9); + setArg(call_mask_fp_vector_imm_op_3674, 10, mask_fp_vector_imm_op_3674_arg10); + InvokeNode* call_fget_flags_3676; + x86::Gp ret_val_fget_flags_3676 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3676, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3676; + setRet(call_fget_flags_3676, 0, ret_val_fget_flags_3676); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3677 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3677, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3677, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 799); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 800: VMFLE__VV */ + continuation_e __vmfle__vv(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vs1}, {vm}", fmt::arg("mnemonic", "vmfle.vv"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vs1", vname(vs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFLE__VV_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 800); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3678; + x86::Gp ret_val_get_sew_pow_3678 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3678, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3679 = get_reg(cc, 8, false); + mov(cc, tmp3679, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3679, (ret_val_get_sew_pow_3678))), 8, false), ~ 1); + setArg(call_get_sew_pow_3678, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3678, 0, ret_val_get_sew_pow_3678); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3680; + auto illegal_fp_vd_unmasked_3680_arg0 = SEW; + auto illegal_fp_vd_unmasked_3680_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3680 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3680, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3680; + setArg(call_illegal_fp_vd_unmasked_3680, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3680, 1, illegal_fp_vd_unmasked_3680_arg0); + setArg(call_illegal_fp_vd_unmasked_3680, 2, illegal_fp_vd_unmasked_3680_arg1); + setRet(call_illegal_fp_vd_unmasked_3680, 0, ret_val_illegal_fp_vd_unmasked_3680); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3682; + x86::Gp ret_val_sew_3682 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3682, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3681; + auto mask_fp_vector_vector_op_3681_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3681_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3681_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3681_arg9 = rm; + auto mask_fp_vector_vector_op_3681_arg10 = ret_val_sew_3682; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_vector_op_3681, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3682, 0, reinterpret_cast(this)); + setRet(call_sew_3682, 0, ret_val_sew_3682); + setArg(call_mask_fp_vector_vector_op_3681, 0, V); + setArg(call_mask_fp_vector_vector_op_3681, 1, 25); + setArg(call_mask_fp_vector_vector_op_3681, 2, mask_fp_vector_vector_op_3681_arg2); + setArg(call_mask_fp_vector_vector_op_3681, 3, mask_fp_vector_vector_op_3681_arg3); + setArg(call_mask_fp_vector_vector_op_3681, 4, mask_fp_vector_vector_op_3681_arg4); + setArg(call_mask_fp_vector_vector_op_3681, 5, vm); + setArg(call_mask_fp_vector_vector_op_3681, 6, vd); + setArg(call_mask_fp_vector_vector_op_3681, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3681, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3681, 9, mask_fp_vector_vector_op_3681_arg9); + setArg(call_mask_fp_vector_vector_op_3681, 10, mask_fp_vector_vector_op_3681_arg10); + InvokeNode* call_fget_flags_3683; + x86::Gp ret_val_fget_flags_3683 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3683, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3683; + setRet(call_fget_flags_3683, 0, ret_val_fget_flags_3683); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3684 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3684, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3684, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 800); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 801: VMFGT__VF */ + continuation_e __vmfgt__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfgt.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFGT__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 801); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3685; + x86::Gp ret_val_get_sew_pow_3685 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3685, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3686 = get_reg(cc, 8, false); + mov(cc, tmp3686, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3686, (ret_val_get_sew_pow_3685))), 8, false), ~ 1); + setArg(call_get_sew_pow_3685, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3685, 0, ret_val_get_sew_pow_3685); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3687; + auto illegal_fp_vd_unmasked_3687_arg0 = SEW; + auto illegal_fp_vd_unmasked_3687_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3687 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3687, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3687; + setArg(call_illegal_fp_vd_unmasked_3687, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3687, 1, illegal_fp_vd_unmasked_3687_arg0); + setArg(call_illegal_fp_vd_unmasked_3687, 2, illegal_fp_vd_unmasked_3687_arg1); + setRet(call_illegal_fp_vd_unmasked_3687, 0, ret_val_illegal_fp_vd_unmasked_3687); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3689; + x86::Gp ret_val_sew_3689 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3689, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3688; + auto mask_fp_vector_imm_op_3688_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3688_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3688_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3688_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto mask_fp_vector_imm_op_3688_arg9 = rm; + auto mask_fp_vector_imm_op_3688_arg10 = ret_val_sew_3689; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3688, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3689, 0, reinterpret_cast(this)); + setRet(call_sew_3689, 0, ret_val_sew_3689); + setArg(call_mask_fp_vector_imm_op_3688, 0, V); + setArg(call_mask_fp_vector_imm_op_3688, 1, 29); + setArg(call_mask_fp_vector_imm_op_3688, 2, mask_fp_vector_imm_op_3688_arg2); + setArg(call_mask_fp_vector_imm_op_3688, 3, mask_fp_vector_imm_op_3688_arg3); + setArg(call_mask_fp_vector_imm_op_3688, 4, mask_fp_vector_imm_op_3688_arg4); + setArg(call_mask_fp_vector_imm_op_3688, 5, vm); + setArg(call_mask_fp_vector_imm_op_3688, 6, vd); + setArg(call_mask_fp_vector_imm_op_3688, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3688, 8, mask_fp_vector_imm_op_3688_arg8); + setArg(call_mask_fp_vector_imm_op_3688, 9, mask_fp_vector_imm_op_3688_arg9); + setArg(call_mask_fp_vector_imm_op_3688, 10, mask_fp_vector_imm_op_3688_arg10); + InvokeNode* call_fget_flags_3690; + x86::Gp ret_val_fget_flags_3690 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3690, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3690; + setRet(call_fget_flags_3690, 0, ret_val_fget_flags_3690); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3691 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3691, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3691, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 801); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 802: VMFGE__VF */ + continuation_e __vmfge__vf(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}, {vm}", fmt::arg("mnemonic", "vmfge.vf"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VMFGE__VF_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 802); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3692; + x86::Gp ret_val_get_sew_pow_3692 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3692, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3693 = get_reg(cc, 8, false); + mov(cc, tmp3693, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3693, (ret_val_get_sew_pow_3692))), 8, false), ~ 1); + setArg(call_get_sew_pow_3692, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3692, 0, ret_val_get_sew_pow_3692); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3694; + auto illegal_fp_vd_unmasked_3694_arg0 = SEW; + auto illegal_fp_vd_unmasked_3694_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3694 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3694, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3694; + setArg(call_illegal_fp_vd_unmasked_3694, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3694, 1, illegal_fp_vd_unmasked_3694_arg0); + setArg(call_illegal_fp_vd_unmasked_3694, 2, illegal_fp_vd_unmasked_3694_arg1); + setRet(call_illegal_fp_vd_unmasked_3694, 0, ret_val_illegal_fp_vd_unmasked_3694); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3696; + x86::Gp ret_val_sew_3696 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3696, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3695; + auto mask_fp_vector_imm_op_3695_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3695_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3695_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3695_arg8 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto mask_fp_vector_imm_op_3695_arg9 = rm; + auto mask_fp_vector_imm_op_3695_arg10 = ret_val_sew_3696; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_mask_fp_vector_imm_op_3695, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3696, 0, reinterpret_cast(this)); + setRet(call_sew_3696, 0, ret_val_sew_3696); + setArg(call_mask_fp_vector_imm_op_3695, 0, V); + setArg(call_mask_fp_vector_imm_op_3695, 1, 31); + setArg(call_mask_fp_vector_imm_op_3695, 2, mask_fp_vector_imm_op_3695_arg2); + setArg(call_mask_fp_vector_imm_op_3695, 3, mask_fp_vector_imm_op_3695_arg3); + setArg(call_mask_fp_vector_imm_op_3695, 4, mask_fp_vector_imm_op_3695_arg4); + setArg(call_mask_fp_vector_imm_op_3695, 5, vm); + setArg(call_mask_fp_vector_imm_op_3695, 6, vd); + setArg(call_mask_fp_vector_imm_op_3695, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3695, 8, mask_fp_vector_imm_op_3695_arg8); + setArg(call_mask_fp_vector_imm_op_3695, 9, mask_fp_vector_imm_op_3695_arg9); + setArg(call_mask_fp_vector_imm_op_3695, 10, mask_fp_vector_imm_op_3695_arg10); + InvokeNode* call_fget_flags_3697; + x86::Gp ret_val_fget_flags_3697 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3697, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3697; + setRet(call_fget_flags_3697, 0, ret_val_fget_flags_3697); + mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); + } + cc.bind(label_merge); + } + auto tmp3698 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3698, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3698, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 802); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 803: VFCLASS__V */ + continuation_e __vfclass__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfclass.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCLASS__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 803); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3699; + x86::Gp ret_val_get_sew_pow_3699 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3699, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3700 = get_reg(cc, 8, false); + mov(cc, tmp3700, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3700, (ret_val_get_sew_pow_3699))), 8, false), ~ 1); + setArg(call_get_sew_pow_3699, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3699, 0, ret_val_get_sew_pow_3699); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3701; + auto illegal_fp_normal_3701_arg2 = SEW; + auto illegal_fp_normal_3701_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3701 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3701, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3701; + setArg(call_illegal_fp_normal_3701, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3701, 1, vd); + setArg(call_illegal_fp_normal_3701, 2, vm); + setArg(call_illegal_fp_normal_3701, 3, illegal_fp_normal_3701_arg2); + setArg(call_illegal_fp_normal_3701, 4, illegal_fp_normal_3701_arg3); + setRet(call_illegal_fp_normal_3701, 0, ret_val_illegal_fp_normal_3701); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3703; + x86::Gp ret_val_sew_3703 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3703, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3702; + auto fp_vector_unary_op_3702_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3702_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3702_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3702_arg9 = rm; + auto fp_vector_unary_op_3702_arg10 = ret_val_sew_3703; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3702, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3703, 0, reinterpret_cast(this)); + setRet(call_sew_3703, 0, ret_val_sew_3703); + setArg(call_fp_vector_unary_op_3702, 0, V); + setArg(call_fp_vector_unary_op_3702, 1, 19); + setArg(call_fp_vector_unary_op_3702, 2, 16); + setArg(call_fp_vector_unary_op_3702, 3, fp_vector_unary_op_3702_arg3); + setArg(call_fp_vector_unary_op_3702, 4, fp_vector_unary_op_3702_arg4); + setArg(call_fp_vector_unary_op_3702, 5, fp_vector_unary_op_3702_arg5); + setArg(call_fp_vector_unary_op_3702, 6, vm); + setArg(call_fp_vector_unary_op_3702, 7, vd); + setArg(call_fp_vector_unary_op_3702, 8, vs2); + setArg(call_fp_vector_unary_op_3702, 9, fp_vector_unary_op_3702_arg9); + setArg(call_fp_vector_unary_op_3702, 10, fp_vector_unary_op_3702_arg10); + } + cc.bind(label_merge); + } + auto tmp3704 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3704, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3704, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 803); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 804: VFMERGE__VFM */ + continuation_e __vfmerge__vfm(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {rs1}", fmt::arg("mnemonic", "vfmerge.vfm"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMERGE__VFM_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 804); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3705; + x86::Gp ret_val_get_sew_pow_3705 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3705, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3706 = get_reg(cc, 8, false); + mov(cc, tmp3706, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3706, (ret_val_get_sew_pow_3705))), 8, false), ~ 1); + setArg(call_get_sew_pow_3705, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3705, 0, ret_val_get_sew_pow_3705); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_masked_3707; + auto illegal_fp_vd_masked_3707_arg1 = SEW; + auto illegal_fp_vd_masked_3707_arg2 = rm; + x86::Gp ret_val_illegal_fp_vd_masked_3707 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_masked_3707, (uintptr_t)&vm_impl::_illegal_fp_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_masked_3707; + setArg(call_illegal_fp_vd_masked_3707, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_masked_3707, 1, vd); + setArg(call_illegal_fp_vd_masked_3707, 2, illegal_fp_vd_masked_3707_arg1); + setArg(call_illegal_fp_vd_masked_3707, 3, illegal_fp_vd_masked_3707_arg2); + setRet(call_illegal_fp_vd_masked_3707, 0, ret_val_illegal_fp_vd_masked_3707); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3709; + x86::Gp ret_val_sew_3709 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3709, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_3708; + auto vector_imm_merge_3708_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_3708_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_3708_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_3708_arg7 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto vector_imm_merge_3708_arg8 = ret_val_sew_3709; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_3708, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_3709, 0, reinterpret_cast(this)); + setRet(call_sew_3709, 0, ret_val_sew_3709); + setArg(call_vector_imm_merge_3708, 0, V); + setArg(call_vector_imm_merge_3708, 1, vector_imm_merge_3708_arg1); + setArg(call_vector_imm_merge_3708, 2, vector_imm_merge_3708_arg2); + setArg(call_vector_imm_merge_3708, 3, vector_imm_merge_3708_arg3); + setArg(call_vector_imm_merge_3708, 4, 0); + setArg(call_vector_imm_merge_3708, 5, vd); + setArg(call_vector_imm_merge_3708, 6, vs2); + setArg(call_vector_imm_merge_3708, 7, vector_imm_merge_3708_arg7); + setArg(call_vector_imm_merge_3708, 8, vector_imm_merge_3708_arg8); + } + cc.bind(label_merge); + } + auto tmp3710 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3710, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3710, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 804); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 805: VFMV__V__F */ + continuation_e __vfmv__v__f(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {rs1}", fmt::arg("mnemonic", "vfmv.v.f"), + fmt::arg("vd", vname(vd)), fmt::arg("rs1", fname(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFMV__V__F_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 805); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3711; + x86::Gp ret_val_get_sew_pow_3711 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3711, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3712 = get_reg(cc, 8, false); + mov(cc, tmp3712, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3712, (ret_val_get_sew_pow_3711))), 8, false), ~ 1); + setArg(call_get_sew_pow_3711, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3711, 0, ret_val_get_sew_pow_3711); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_vd_unmasked_3713; + auto illegal_fp_vd_unmasked_3713_arg0 = SEW; + auto illegal_fp_vd_unmasked_3713_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3713 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3713, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3713; + setArg(call_illegal_fp_vd_unmasked_3713, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3713, 1, illegal_fp_vd_unmasked_3713_arg0); + setArg(call_illegal_fp_vd_unmasked_3713, 2, illegal_fp_vd_unmasked_3713_arg1); + setRet(call_illegal_fp_vd_unmasked_3713, 0, ret_val_illegal_fp_vd_unmasked_3713); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3715; + x86::Gp ret_val_sew_3715 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3715, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_3714; + auto vector_imm_merge_3714_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_3714_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_3714_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_3714_arg7 = gen_ext(cc, + load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); + auto vector_imm_merge_3714_arg8 = ret_val_sew_3715; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_vector_imm_merge_3714, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_3715, 0, reinterpret_cast(this)); + setRet(call_sew_3715, 0, ret_val_sew_3715); + setArg(call_vector_imm_merge_3714, 0, V); + setArg(call_vector_imm_merge_3714, 1, vector_imm_merge_3714_arg1); + setArg(call_vector_imm_merge_3714, 2, vector_imm_merge_3714_arg2); + setArg(call_vector_imm_merge_3714, 3, vector_imm_merge_3714_arg3); + setArg(call_vector_imm_merge_3714, 4, 1); + setArg(call_vector_imm_merge_3714, 5, vd); + setArg(call_vector_imm_merge_3714, 6, 0); + setArg(call_vector_imm_merge_3714, 7, vector_imm_merge_3714_arg7); + setArg(call_vector_imm_merge_3714, 8, vector_imm_merge_3714_arg8); + } + cc.bind(label_merge); + } + auto tmp3716 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3716, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3716, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 805); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 806: VFCVT__XU__F__V */ + continuation_e __vfcvt__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__XU__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 806); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3717; + x86::Gp ret_val_get_sew_pow_3717 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3717, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3718 = get_reg(cc, 8, false); + mov(cc, tmp3718, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3718, (ret_val_get_sew_pow_3717))), 8, false), ~ 1); + setArg(call_get_sew_pow_3717, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3717, 0, ret_val_get_sew_pow_3717); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3719; + auto illegal_fp_normal_3719_arg2 = SEW; + auto illegal_fp_normal_3719_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3719 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3719, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3719; + setArg(call_illegal_fp_normal_3719, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3719, 1, vd); + setArg(call_illegal_fp_normal_3719, 2, vm); + setArg(call_illegal_fp_normal_3719, 3, illegal_fp_normal_3719_arg2); + setArg(call_illegal_fp_normal_3719, 4, illegal_fp_normal_3719_arg3); + setRet(call_illegal_fp_normal_3719, 0, ret_val_illegal_fp_normal_3719); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3721; + x86::Gp ret_val_sew_3721 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3721, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3720; + auto fp_vector_unary_op_3720_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3720_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3720_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3720_arg9 = rm; + auto fp_vector_unary_op_3720_arg10 = ret_val_sew_3721; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3720, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3721, 0, reinterpret_cast(this)); + setRet(call_sew_3721, 0, ret_val_sew_3721); + setArg(call_fp_vector_unary_op_3720, 0, V); + setArg(call_fp_vector_unary_op_3720, 1, 18); + setArg(call_fp_vector_unary_op_3720, 2, 0); + setArg(call_fp_vector_unary_op_3720, 3, fp_vector_unary_op_3720_arg3); + setArg(call_fp_vector_unary_op_3720, 4, fp_vector_unary_op_3720_arg4); + setArg(call_fp_vector_unary_op_3720, 5, fp_vector_unary_op_3720_arg5); + setArg(call_fp_vector_unary_op_3720, 6, vm); + setArg(call_fp_vector_unary_op_3720, 7, vd); + setArg(call_fp_vector_unary_op_3720, 8, vs2); + setArg(call_fp_vector_unary_op_3720, 9, fp_vector_unary_op_3720_arg9); + setArg(call_fp_vector_unary_op_3720, 10, fp_vector_unary_op_3720_arg10); + } + cc.bind(label_merge); + } + auto tmp3722 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3722, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3722, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 806); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 807: VFCVT__X__F__V */ + continuation_e __vfcvt__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 807); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3723; + x86::Gp ret_val_get_sew_pow_3723 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3723, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3724 = get_reg(cc, 8, false); + mov(cc, tmp3724, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3724, (ret_val_get_sew_pow_3723))), 8, false), ~ 1); + setArg(call_get_sew_pow_3723, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3723, 0, ret_val_get_sew_pow_3723); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3725; + auto illegal_fp_normal_3725_arg2 = SEW; + auto illegal_fp_normal_3725_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3725 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3725, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3725; + setArg(call_illegal_fp_normal_3725, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3725, 1, vd); + setArg(call_illegal_fp_normal_3725, 2, vm); + setArg(call_illegal_fp_normal_3725, 3, illegal_fp_normal_3725_arg2); + setArg(call_illegal_fp_normal_3725, 4, illegal_fp_normal_3725_arg3); + setRet(call_illegal_fp_normal_3725, 0, ret_val_illegal_fp_normal_3725); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3727; + x86::Gp ret_val_sew_3727 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3727, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3726; + auto fp_vector_unary_op_3726_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3726_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3726_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3726_arg9 = rm; + auto fp_vector_unary_op_3726_arg10 = ret_val_sew_3727; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3726, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3727, 0, reinterpret_cast(this)); + setRet(call_sew_3727, 0, ret_val_sew_3727); + setArg(call_fp_vector_unary_op_3726, 0, V); + setArg(call_fp_vector_unary_op_3726, 1, 18); + setArg(call_fp_vector_unary_op_3726, 2, 1); + setArg(call_fp_vector_unary_op_3726, 3, fp_vector_unary_op_3726_arg3); + setArg(call_fp_vector_unary_op_3726, 4, fp_vector_unary_op_3726_arg4); + setArg(call_fp_vector_unary_op_3726, 5, fp_vector_unary_op_3726_arg5); + setArg(call_fp_vector_unary_op_3726, 6, vm); + setArg(call_fp_vector_unary_op_3726, 7, vd); + setArg(call_fp_vector_unary_op_3726, 8, vs2); + setArg(call_fp_vector_unary_op_3726, 9, fp_vector_unary_op_3726_arg9); + setArg(call_fp_vector_unary_op_3726, 10, fp_vector_unary_op_3726_arg10); + } + cc.bind(label_merge); + } + auto tmp3728 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3728, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3728, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 807); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 808: VFCVT__RTZ__XU__F__V */ + continuation_e __vfcvt__rtz__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.rtz.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__RTZ__XU__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 808); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3729; + x86::Gp ret_val_get_sew_pow_3729 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3729, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3730 = get_reg(cc, 8, false); + mov(cc, tmp3730, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3730, (ret_val_get_sew_pow_3729))), 8, false), ~ 1); + setArg(call_get_sew_pow_3729, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3729, 0, ret_val_get_sew_pow_3729); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3731; + auto illegal_fp_normal_3731_arg2 = SEW; + x86::Gp ret_val_illegal_fp_normal_3731 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3731, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3731; + setArg(call_illegal_fp_normal_3731, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3731, 1, vd); + setArg(call_illegal_fp_normal_3731, 2, vm); + setArg(call_illegal_fp_normal_3731, 3, illegal_fp_normal_3731_arg2); + setArg(call_illegal_fp_normal_3731, 4, rm); + setRet(call_illegal_fp_normal_3731, 0, ret_val_illegal_fp_normal_3731); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3733; + x86::Gp ret_val_sew_3733 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3733, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3732; + auto fp_vector_unary_op_3732_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3732_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3732_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3732_arg10 = ret_val_sew_3733; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3732, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3733, 0, reinterpret_cast(this)); + setRet(call_sew_3733, 0, ret_val_sew_3733); + setArg(call_fp_vector_unary_op_3732, 0, V); + setArg(call_fp_vector_unary_op_3732, 1, 18); + setArg(call_fp_vector_unary_op_3732, 2, 6); + setArg(call_fp_vector_unary_op_3732, 3, fp_vector_unary_op_3732_arg3); + setArg(call_fp_vector_unary_op_3732, 4, fp_vector_unary_op_3732_arg4); + setArg(call_fp_vector_unary_op_3732, 5, fp_vector_unary_op_3732_arg5); + setArg(call_fp_vector_unary_op_3732, 6, vm); + setArg(call_fp_vector_unary_op_3732, 7, vd); + setArg(call_fp_vector_unary_op_3732, 8, vs2); + setArg(call_fp_vector_unary_op_3732, 9, rm); + setArg(call_fp_vector_unary_op_3732, 10, fp_vector_unary_op_3732_arg10); + } + cc.bind(label_merge); + } + auto tmp3734 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3734, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3734, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 808); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 809: VFCVT__RTZ__X__F__V */ + continuation_e __vfcvt__rtz__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.rtz.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__RTZ__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 809); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3735; + x86::Gp ret_val_get_sew_pow_3735 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3735, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3736 = get_reg(cc, 8, false); + mov(cc, tmp3736, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3736, (ret_val_get_sew_pow_3735))), 8, false), ~ 1); + setArg(call_get_sew_pow_3735, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3735, 0, ret_val_get_sew_pow_3735); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3737; + auto illegal_fp_normal_3737_arg2 = SEW; + x86::Gp ret_val_illegal_fp_normal_3737 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3737, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3737; + setArg(call_illegal_fp_normal_3737, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3737, 1, vd); + setArg(call_illegal_fp_normal_3737, 2, vm); + setArg(call_illegal_fp_normal_3737, 3, illegal_fp_normal_3737_arg2); + setArg(call_illegal_fp_normal_3737, 4, rm); + setRet(call_illegal_fp_normal_3737, 0, ret_val_illegal_fp_normal_3737); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3739; + x86::Gp ret_val_sew_3739 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3739, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3738; + auto fp_vector_unary_op_3738_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3738_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3738_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3738_arg10 = ret_val_sew_3739; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3738, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3739, 0, reinterpret_cast(this)); + setRet(call_sew_3739, 0, ret_val_sew_3739); + setArg(call_fp_vector_unary_op_3738, 0, V); + setArg(call_fp_vector_unary_op_3738, 1, 18); + setArg(call_fp_vector_unary_op_3738, 2, 7); + setArg(call_fp_vector_unary_op_3738, 3, fp_vector_unary_op_3738_arg3); + setArg(call_fp_vector_unary_op_3738, 4, fp_vector_unary_op_3738_arg4); + setArg(call_fp_vector_unary_op_3738, 5, fp_vector_unary_op_3738_arg5); + setArg(call_fp_vector_unary_op_3738, 6, vm); + setArg(call_fp_vector_unary_op_3738, 7, vd); + setArg(call_fp_vector_unary_op_3738, 8, vs2); + setArg(call_fp_vector_unary_op_3738, 9, rm); + setArg(call_fp_vector_unary_op_3738, 10, fp_vector_unary_op_3738_arg10); + } + cc.bind(label_merge); + } + auto tmp3740 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3740, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3740, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 809); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 810: VFCVT__F__XU__V */ + continuation_e __vfcvt__f__xu__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.f.xu.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__F__XU__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 810); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3741; + x86::Gp ret_val_get_sew_pow_3741 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3741, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3742 = get_reg(cc, 8, false); + mov(cc, tmp3742, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3742, (ret_val_get_sew_pow_3741))), 8, false), ~ 1); + setArg(call_get_sew_pow_3741, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3741, 0, ret_val_get_sew_pow_3741); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3743; + auto illegal_fp_normal_3743_arg2 = SEW; + auto illegal_fp_normal_3743_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3743 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3743, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3743; + setArg(call_illegal_fp_normal_3743, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3743, 1, vd); + setArg(call_illegal_fp_normal_3743, 2, vm); + setArg(call_illegal_fp_normal_3743, 3, illegal_fp_normal_3743_arg2); + setArg(call_illegal_fp_normal_3743, 4, illegal_fp_normal_3743_arg3); + setRet(call_illegal_fp_normal_3743, 0, ret_val_illegal_fp_normal_3743); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3745; + x86::Gp ret_val_sew_3745 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3745, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3744; + auto fp_vector_unary_op_3744_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3744_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3744_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3744_arg9 = rm; + auto fp_vector_unary_op_3744_arg10 = ret_val_sew_3745; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3744, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3745, 0, reinterpret_cast(this)); + setRet(call_sew_3745, 0, ret_val_sew_3745); + setArg(call_fp_vector_unary_op_3744, 0, V); + setArg(call_fp_vector_unary_op_3744, 1, 18); + setArg(call_fp_vector_unary_op_3744, 2, 2); + setArg(call_fp_vector_unary_op_3744, 3, fp_vector_unary_op_3744_arg3); + setArg(call_fp_vector_unary_op_3744, 4, fp_vector_unary_op_3744_arg4); + setArg(call_fp_vector_unary_op_3744, 5, fp_vector_unary_op_3744_arg5); + setArg(call_fp_vector_unary_op_3744, 6, vm); + setArg(call_fp_vector_unary_op_3744, 7, vd); + setArg(call_fp_vector_unary_op_3744, 8, vs2); + setArg(call_fp_vector_unary_op_3744, 9, fp_vector_unary_op_3744_arg9); + setArg(call_fp_vector_unary_op_3744, 10, fp_vector_unary_op_3744_arg10); + } + cc.bind(label_merge); + } + auto tmp3746 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3746, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3746, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 810); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 811: VFCVT__F__X__V */ + continuation_e __vfcvt__f__x__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfcvt.f.x.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFCVT__F__X__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 811); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3747; + x86::Gp ret_val_get_sew_pow_3747 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3747, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3748 = get_reg(cc, 8, false); + mov(cc, tmp3748, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3748, (ret_val_get_sew_pow_3747))), 8, false), ~ 1); + setArg(call_get_sew_pow_3747, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3747, 0, ret_val_get_sew_pow_3747); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_normal_3749; + auto illegal_fp_normal_3749_arg2 = SEW; + auto illegal_fp_normal_3749_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3749 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3749, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3749; + setArg(call_illegal_fp_normal_3749, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3749, 1, vd); + setArg(call_illegal_fp_normal_3749, 2, vm); + setArg(call_illegal_fp_normal_3749, 3, illegal_fp_normal_3749_arg2); + setArg(call_illegal_fp_normal_3749, 4, illegal_fp_normal_3749_arg3); + setRet(call_illegal_fp_normal_3749, 0, ret_val_illegal_fp_normal_3749); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3751; + x86::Gp ret_val_sew_3751 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3751, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3750; + auto fp_vector_unary_op_3750_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3750_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3750_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3750_arg9 = rm; + auto fp_vector_unary_op_3750_arg10 = ret_val_sew_3751; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_op_3750, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3751, 0, reinterpret_cast(this)); + setRet(call_sew_3751, 0, ret_val_sew_3751); + setArg(call_fp_vector_unary_op_3750, 0, V); + setArg(call_fp_vector_unary_op_3750, 1, 18); + setArg(call_fp_vector_unary_op_3750, 2, 3); + setArg(call_fp_vector_unary_op_3750, 3, fp_vector_unary_op_3750_arg3); + setArg(call_fp_vector_unary_op_3750, 4, fp_vector_unary_op_3750_arg4); + setArg(call_fp_vector_unary_op_3750, 5, fp_vector_unary_op_3750_arg5); + setArg(call_fp_vector_unary_op_3750, 6, vm); + setArg(call_fp_vector_unary_op_3750, 7, vd); + setArg(call_fp_vector_unary_op_3750, 8, vs2); + setArg(call_fp_vector_unary_op_3750, 9, fp_vector_unary_op_3750_arg9); + setArg(call_fp_vector_unary_op_3750, 10, fp_vector_unary_op_3750_arg10); + } + cc.bind(label_merge); + } + auto tmp3752 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3752, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3752, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 811); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 812: VFWCVT__XU__F__V */ + continuation_e __vfwcvt__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__XU__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 812); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3753; + x86::Gp ret_val_get_sew_pow_3753 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3753, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3754 = get_reg(cc, 8, false); + mov(cc, tmp3754, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3754, (ret_val_get_sew_pow_3753))), 8, false), ~ 1); + setArg(call_get_sew_pow_3753, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3753, 0, ret_val_get_sew_pow_3753); + InvokeNode* call_get_lmul_pow_3755; + x86::Gp ret_val_get_lmul_pow_3755 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3755, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3755; + setArg(call_get_lmul_pow_3755, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3755, 0, ret_val_get_lmul_pow_3755); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3756; + auto illegal_fp_variable_width_3756_arg2 = SEW; + auto illegal_fp_variable_width_3756_arg3 = rm; + auto illegal_fp_variable_width_3756_arg4 = SEW_widen; + auto illegal_fp_variable_width_3756_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3756 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3756, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3757; + auto valid_reg_overlap_3757_arg2 = LMUL_pow; + auto valid_reg_overlap_3757_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3757 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3757, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3756, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3757)); + setArg(call_illegal_fp_variable_width_3756, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3756, 1, vd); + setArg(call_illegal_fp_variable_width_3756, 2, vm); + setArg(call_illegal_fp_variable_width_3756, 3, illegal_fp_variable_width_3756_arg2); + setArg(call_illegal_fp_variable_width_3756, 4, illegal_fp_variable_width_3756_arg3); + setArg(call_illegal_fp_variable_width_3756, 5, illegal_fp_variable_width_3756_arg4); + setArg(call_illegal_fp_variable_width_3756, 6, illegal_fp_variable_width_3756_arg5); + setRet(call_illegal_fp_variable_width_3756, 0, ret_val_illegal_fp_variable_width_3756); + setArg(call_valid_reg_overlap_3757, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3757, 1, vs2); + setArg(call_valid_reg_overlap_3757, 2, vd); + setArg(call_valid_reg_overlap_3757, 3, valid_reg_overlap_3757_arg2); + setArg(call_valid_reg_overlap_3757, 4, valid_reg_overlap_3757_arg3); + setRet(call_valid_reg_overlap_3757, 0, ret_val_valid_reg_overlap_3757); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3759; + x86::Gp ret_val_sew_3759 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3759, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3758; + auto fp_vector_unary_w_3758_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3758_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3758_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3758_arg8 = rm; + auto fp_vector_unary_w_3758_arg9 = ret_val_sew_3759; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3758, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3759, 0, reinterpret_cast(this)); + setRet(call_sew_3759, 0, ret_val_sew_3759); + setArg(call_fp_vector_unary_w_3758, 0, V); + setArg(call_fp_vector_unary_w_3758, 1, 8); + setArg(call_fp_vector_unary_w_3758, 2, fp_vector_unary_w_3758_arg2); + setArg(call_fp_vector_unary_w_3758, 3, fp_vector_unary_w_3758_arg3); + setArg(call_fp_vector_unary_w_3758, 4, fp_vector_unary_w_3758_arg4); + setArg(call_fp_vector_unary_w_3758, 5, vm); + setArg(call_fp_vector_unary_w_3758, 6, vd); + setArg(call_fp_vector_unary_w_3758, 7, vs2); + setArg(call_fp_vector_unary_w_3758, 8, fp_vector_unary_w_3758_arg8); + setArg(call_fp_vector_unary_w_3758, 9, fp_vector_unary_w_3758_arg9); + } + cc.bind(label_merge); + } + auto tmp3760 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3760, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3760, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 812); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 813: VFWCVT__X__F__V */ + continuation_e __vfwcvt__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 813); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3761; + x86::Gp ret_val_get_sew_pow_3761 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3761, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3762 = get_reg(cc, 8, false); + mov(cc, tmp3762, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3762, (ret_val_get_sew_pow_3761))), 8, false), ~ 1); + setArg(call_get_sew_pow_3761, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3761, 0, ret_val_get_sew_pow_3761); + InvokeNode* call_get_lmul_pow_3763; + x86::Gp ret_val_get_lmul_pow_3763 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3763, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3763; + setArg(call_get_lmul_pow_3763, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3763, 0, ret_val_get_lmul_pow_3763); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3764; + auto illegal_fp_variable_width_3764_arg2 = SEW; + auto illegal_fp_variable_width_3764_arg3 = rm; + auto illegal_fp_variable_width_3764_arg4 = SEW_widen; + auto illegal_fp_variable_width_3764_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3764 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3764, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3765; + auto valid_reg_overlap_3765_arg2 = LMUL_pow; + auto valid_reg_overlap_3765_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3765 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3765, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3764, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3765)); + setArg(call_illegal_fp_variable_width_3764, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3764, 1, vd); + setArg(call_illegal_fp_variable_width_3764, 2, vm); + setArg(call_illegal_fp_variable_width_3764, 3, illegal_fp_variable_width_3764_arg2); + setArg(call_illegal_fp_variable_width_3764, 4, illegal_fp_variable_width_3764_arg3); + setArg(call_illegal_fp_variable_width_3764, 5, illegal_fp_variable_width_3764_arg4); + setArg(call_illegal_fp_variable_width_3764, 6, illegal_fp_variable_width_3764_arg5); + setRet(call_illegal_fp_variable_width_3764, 0, ret_val_illegal_fp_variable_width_3764); + setArg(call_valid_reg_overlap_3765, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3765, 1, vs2); + setArg(call_valid_reg_overlap_3765, 2, vd); + setArg(call_valid_reg_overlap_3765, 3, valid_reg_overlap_3765_arg2); + setArg(call_valid_reg_overlap_3765, 4, valid_reg_overlap_3765_arg3); + setRet(call_valid_reg_overlap_3765, 0, ret_val_valid_reg_overlap_3765); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3767; + x86::Gp ret_val_sew_3767 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3767, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3766; + auto fp_vector_unary_w_3766_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3766_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3766_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3766_arg8 = rm; + auto fp_vector_unary_w_3766_arg9 = ret_val_sew_3767; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3766, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3767, 0, reinterpret_cast(this)); + setRet(call_sew_3767, 0, ret_val_sew_3767); + setArg(call_fp_vector_unary_w_3766, 0, V); + setArg(call_fp_vector_unary_w_3766, 1, 9); + setArg(call_fp_vector_unary_w_3766, 2, fp_vector_unary_w_3766_arg2); + setArg(call_fp_vector_unary_w_3766, 3, fp_vector_unary_w_3766_arg3); + setArg(call_fp_vector_unary_w_3766, 4, fp_vector_unary_w_3766_arg4); + setArg(call_fp_vector_unary_w_3766, 5, vm); + setArg(call_fp_vector_unary_w_3766, 6, vd); + setArg(call_fp_vector_unary_w_3766, 7, vs2); + setArg(call_fp_vector_unary_w_3766, 8, fp_vector_unary_w_3766_arg8); + setArg(call_fp_vector_unary_w_3766, 9, fp_vector_unary_w_3766_arg9); + } + cc.bind(label_merge); + } + auto tmp3768 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3768, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3768, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 813); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 814: VFWCVT__RTZ__XU__F__V */ + continuation_e __vfwcvt__rtz__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.xu.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__RTZ__XU__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 814); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3769; + x86::Gp ret_val_get_sew_pow_3769 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3769, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3770 = get_reg(cc, 8, false); + mov(cc, tmp3770, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3770, (ret_val_get_sew_pow_3769))), 8, false), ~ 1); + setArg(call_get_sew_pow_3769, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3769, 0, ret_val_get_sew_pow_3769); + InvokeNode* call_get_lmul_pow_3771; + x86::Gp ret_val_get_lmul_pow_3771 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3771, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3771; + setArg(call_get_lmul_pow_3771, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3771, 0, ret_val_get_lmul_pow_3771); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3772; + auto illegal_fp_variable_width_3772_arg2 = SEW; + auto illegal_fp_variable_width_3772_arg4 = SEW_widen; + auto illegal_fp_variable_width_3772_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3772 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3772, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3773; + auto valid_reg_overlap_3773_arg2 = LMUL_pow; + auto valid_reg_overlap_3773_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3773 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3773, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3772, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3773)); + setArg(call_illegal_fp_variable_width_3772, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3772, 1, vd); + setArg(call_illegal_fp_variable_width_3772, 2, vm); + setArg(call_illegal_fp_variable_width_3772, 3, illegal_fp_variable_width_3772_arg2); + setArg(call_illegal_fp_variable_width_3772, 4, rm); + setArg(call_illegal_fp_variable_width_3772, 5, illegal_fp_variable_width_3772_arg4); + setArg(call_illegal_fp_variable_width_3772, 6, illegal_fp_variable_width_3772_arg5); + setRet(call_illegal_fp_variable_width_3772, 0, ret_val_illegal_fp_variable_width_3772); + setArg(call_valid_reg_overlap_3773, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3773, 1, vs2); + setArg(call_valid_reg_overlap_3773, 2, vd); + setArg(call_valid_reg_overlap_3773, 3, valid_reg_overlap_3773_arg2); + setArg(call_valid_reg_overlap_3773, 4, valid_reg_overlap_3773_arg3); + setRet(call_valid_reg_overlap_3773, 0, ret_val_valid_reg_overlap_3773); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3775; + x86::Gp ret_val_sew_3775 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3775, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3774; + auto fp_vector_unary_w_3774_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3774_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3774_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3774_arg9 = ret_val_sew_3775; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3774, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3775, 0, reinterpret_cast(this)); + setRet(call_sew_3775, 0, ret_val_sew_3775); + setArg(call_fp_vector_unary_w_3774, 0, V); + setArg(call_fp_vector_unary_w_3774, 1, 14); + setArg(call_fp_vector_unary_w_3774, 2, fp_vector_unary_w_3774_arg2); + setArg(call_fp_vector_unary_w_3774, 3, fp_vector_unary_w_3774_arg3); + setArg(call_fp_vector_unary_w_3774, 4, fp_vector_unary_w_3774_arg4); + setArg(call_fp_vector_unary_w_3774, 5, vm); + setArg(call_fp_vector_unary_w_3774, 6, vd); + setArg(call_fp_vector_unary_w_3774, 7, vs2); + setArg(call_fp_vector_unary_w_3774, 8, rm); + setArg(call_fp_vector_unary_w_3774, 9, fp_vector_unary_w_3774_arg9); + } + cc.bind(label_merge); + } + auto tmp3776 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3776, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3776, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 814); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 815: VFWCVT__RTZ__X__F__V */ + continuation_e __vfwcvt__rtz__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.x.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__RTZ__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 815); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3777; + x86::Gp ret_val_get_sew_pow_3777 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3777, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3778 = get_reg(cc, 8, false); + mov(cc, tmp3778, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3778, (ret_val_get_sew_pow_3777))), 8, false), ~ 1); + setArg(call_get_sew_pow_3777, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3777, 0, ret_val_get_sew_pow_3777); + InvokeNode* call_get_lmul_pow_3779; + x86::Gp ret_val_get_lmul_pow_3779 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3779, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3779; + setArg(call_get_lmul_pow_3779, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3779, 0, ret_val_get_lmul_pow_3779); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3780; + auto illegal_fp_variable_width_3780_arg2 = SEW; + auto illegal_fp_variable_width_3780_arg4 = SEW_widen; + auto illegal_fp_variable_width_3780_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3780 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3780, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3781; + auto valid_reg_overlap_3781_arg2 = LMUL_pow; + auto valid_reg_overlap_3781_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3781 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3781, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3780, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3781)); + setArg(call_illegal_fp_variable_width_3780, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3780, 1, vd); + setArg(call_illegal_fp_variable_width_3780, 2, vm); + setArg(call_illegal_fp_variable_width_3780, 3, illegal_fp_variable_width_3780_arg2); + setArg(call_illegal_fp_variable_width_3780, 4, rm); + setArg(call_illegal_fp_variable_width_3780, 5, illegal_fp_variable_width_3780_arg4); + setArg(call_illegal_fp_variable_width_3780, 6, illegal_fp_variable_width_3780_arg5); + setRet(call_illegal_fp_variable_width_3780, 0, ret_val_illegal_fp_variable_width_3780); + setArg(call_valid_reg_overlap_3781, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3781, 1, vs2); + setArg(call_valid_reg_overlap_3781, 2, vd); + setArg(call_valid_reg_overlap_3781, 3, valid_reg_overlap_3781_arg2); + setArg(call_valid_reg_overlap_3781, 4, valid_reg_overlap_3781_arg3); + setRet(call_valid_reg_overlap_3781, 0, ret_val_valid_reg_overlap_3781); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3783; + x86::Gp ret_val_sew_3783 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3783, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3782; + auto fp_vector_unary_w_3782_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3782_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3782_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3782_arg9 = ret_val_sew_3783; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3782, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3783, 0, reinterpret_cast(this)); + setRet(call_sew_3783, 0, ret_val_sew_3783); + setArg(call_fp_vector_unary_w_3782, 0, V); + setArg(call_fp_vector_unary_w_3782, 1, 15); + setArg(call_fp_vector_unary_w_3782, 2, fp_vector_unary_w_3782_arg2); + setArg(call_fp_vector_unary_w_3782, 3, fp_vector_unary_w_3782_arg3); + setArg(call_fp_vector_unary_w_3782, 4, fp_vector_unary_w_3782_arg4); + setArg(call_fp_vector_unary_w_3782, 5, vm); + setArg(call_fp_vector_unary_w_3782, 6, vd); + setArg(call_fp_vector_unary_w_3782, 7, vs2); + setArg(call_fp_vector_unary_w_3782, 8, rm); + setArg(call_fp_vector_unary_w_3782, 9, fp_vector_unary_w_3782_arg9); + } + cc.bind(label_merge); + } + auto tmp3784 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3784, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3784, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 815); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 816: VFWCVT__F__XU__V */ + continuation_e __vfwcvt__f__xu__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.xu.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__F__XU__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 816); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3785; + x86::Gp ret_val_get_sew_pow_3785 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3785, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3786 = get_reg(cc, 8, false); + mov(cc, tmp3786, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3786, (ret_val_get_sew_pow_3785))), 8, false), ~ 1); + setArg(call_get_sew_pow_3785, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3785, 0, ret_val_get_sew_pow_3785); + InvokeNode* call_get_lmul_pow_3787; + x86::Gp ret_val_get_lmul_pow_3787 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3787, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3787; + setArg(call_get_lmul_pow_3787, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3787, 0, ret_val_get_lmul_pow_3787); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3788; + auto illegal_fp_variable_width_3788_arg2 = SEW; + auto illegal_fp_variable_width_3788_arg3 = rm; + auto illegal_fp_variable_width_3788_arg4 = SEW_widen; + auto illegal_fp_variable_width_3788_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3788 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3788, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3789; + auto valid_reg_overlap_3789_arg2 = LMUL_pow; + auto valid_reg_overlap_3789_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3789 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3789, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3788, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3789)); + setArg(call_illegal_fp_variable_width_3788, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3788, 1, vd); + setArg(call_illegal_fp_variable_width_3788, 2, vm); + setArg(call_illegal_fp_variable_width_3788, 3, illegal_fp_variable_width_3788_arg2); + setArg(call_illegal_fp_variable_width_3788, 4, illegal_fp_variable_width_3788_arg3); + setArg(call_illegal_fp_variable_width_3788, 5, illegal_fp_variable_width_3788_arg4); + setArg(call_illegal_fp_variable_width_3788, 6, illegal_fp_variable_width_3788_arg5); + setRet(call_illegal_fp_variable_width_3788, 0, ret_val_illegal_fp_variable_width_3788); + setArg(call_valid_reg_overlap_3789, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3789, 1, vs2); + setArg(call_valid_reg_overlap_3789, 2, vd); + setArg(call_valid_reg_overlap_3789, 3, valid_reg_overlap_3789_arg2); + setArg(call_valid_reg_overlap_3789, 4, valid_reg_overlap_3789_arg3); + setRet(call_valid_reg_overlap_3789, 0, ret_val_valid_reg_overlap_3789); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3791; + x86::Gp ret_val_sew_3791 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3791, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3790; + auto fp_vector_unary_w_3790_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3790_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3790_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3790_arg8 = rm; + auto fp_vector_unary_w_3790_arg9 = ret_val_sew_3791; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3790, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3791, 0, reinterpret_cast(this)); + setRet(call_sew_3791, 0, ret_val_sew_3791); + setArg(call_fp_vector_unary_w_3790, 0, V); + setArg(call_fp_vector_unary_w_3790, 1, 10); + setArg(call_fp_vector_unary_w_3790, 2, fp_vector_unary_w_3790_arg2); + setArg(call_fp_vector_unary_w_3790, 3, fp_vector_unary_w_3790_arg3); + setArg(call_fp_vector_unary_w_3790, 4, fp_vector_unary_w_3790_arg4); + setArg(call_fp_vector_unary_w_3790, 5, vm); + setArg(call_fp_vector_unary_w_3790, 6, vd); + setArg(call_fp_vector_unary_w_3790, 7, vs2); + setArg(call_fp_vector_unary_w_3790, 8, fp_vector_unary_w_3790_arg8); + setArg(call_fp_vector_unary_w_3790, 9, fp_vector_unary_w_3790_arg9); + } + cc.bind(label_merge); + } + auto tmp3792 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3792, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3792, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 816); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 817: VFWCVT__F__X__V */ + continuation_e __vfwcvt__f__x__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.x.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__F__X__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 817); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3793; + x86::Gp ret_val_get_sew_pow_3793 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3793, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3794 = get_reg(cc, 8, false); + mov(cc, tmp3794, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3794, (ret_val_get_sew_pow_3793))), 8, false), ~ 1); + setArg(call_get_sew_pow_3793, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3793, 0, ret_val_get_sew_pow_3793); + InvokeNode* call_get_lmul_pow_3795; + x86::Gp ret_val_get_lmul_pow_3795 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3795, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3795; + setArg(call_get_lmul_pow_3795, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3795, 0, ret_val_get_lmul_pow_3795); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3796; + auto illegal_fp_variable_width_3796_arg2 = SEW; + auto illegal_fp_variable_width_3796_arg3 = rm; + auto illegal_fp_variable_width_3796_arg4 = SEW_widen; + auto illegal_fp_variable_width_3796_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3796 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3796, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3797; + auto valid_reg_overlap_3797_arg2 = LMUL_pow; + auto valid_reg_overlap_3797_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3797 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3797, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3796, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3797)); + setArg(call_illegal_fp_variable_width_3796, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3796, 1, vd); + setArg(call_illegal_fp_variable_width_3796, 2, vm); + setArg(call_illegal_fp_variable_width_3796, 3, illegal_fp_variable_width_3796_arg2); + setArg(call_illegal_fp_variable_width_3796, 4, illegal_fp_variable_width_3796_arg3); + setArg(call_illegal_fp_variable_width_3796, 5, illegal_fp_variable_width_3796_arg4); + setArg(call_illegal_fp_variable_width_3796, 6, illegal_fp_variable_width_3796_arg5); + setRet(call_illegal_fp_variable_width_3796, 0, ret_val_illegal_fp_variable_width_3796); + setArg(call_valid_reg_overlap_3797, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3797, 1, vs2); + setArg(call_valid_reg_overlap_3797, 2, vd); + setArg(call_valid_reg_overlap_3797, 3, valid_reg_overlap_3797_arg2); + setArg(call_valid_reg_overlap_3797, 4, valid_reg_overlap_3797_arg3); + setRet(call_valid_reg_overlap_3797, 0, ret_val_valid_reg_overlap_3797); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3799; + x86::Gp ret_val_sew_3799 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3799, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3798; + auto fp_vector_unary_w_3798_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3798_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3798_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3798_arg8 = rm; + auto fp_vector_unary_w_3798_arg9 = ret_val_sew_3799; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3798, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3799, 0, reinterpret_cast(this)); + setRet(call_sew_3799, 0, ret_val_sew_3799); + setArg(call_fp_vector_unary_w_3798, 0, V); + setArg(call_fp_vector_unary_w_3798, 1, 11); + setArg(call_fp_vector_unary_w_3798, 2, fp_vector_unary_w_3798_arg2); + setArg(call_fp_vector_unary_w_3798, 3, fp_vector_unary_w_3798_arg3); + setArg(call_fp_vector_unary_w_3798, 4, fp_vector_unary_w_3798_arg4); + setArg(call_fp_vector_unary_w_3798, 5, vm); + setArg(call_fp_vector_unary_w_3798, 6, vd); + setArg(call_fp_vector_unary_w_3798, 7, vs2); + setArg(call_fp_vector_unary_w_3798, 8, fp_vector_unary_w_3798_arg8); + setArg(call_fp_vector_unary_w_3798, 9, fp_vector_unary_w_3798_arg9); + } + cc.bind(label_merge); + } + auto tmp3800 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3800, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3800, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 817); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 818: VFWCVT__F__F__V */ + continuation_e __vfwcvt__f__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.f.v"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFWCVT__F__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 818); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3801; + x86::Gp ret_val_get_sew_pow_3801 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3801, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3802 = get_reg(cc, 8, false); + mov(cc, tmp3802, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3802, (ret_val_get_sew_pow_3801))), 8, false), ~ 1); + setArg(call_get_sew_pow_3801, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3801, 0, ret_val_get_sew_pow_3801); + InvokeNode* call_get_lmul_pow_3803; + x86::Gp ret_val_get_lmul_pow_3803 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3803, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3803; + setArg(call_get_lmul_pow_3803, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3803, 0, ret_val_get_lmul_pow_3803); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3804; + auto illegal_fp_variable_width_3804_arg2 = SEW; + auto illegal_fp_variable_width_3804_arg3 = rm; + auto illegal_fp_variable_width_3804_arg4 = SEW_widen; + auto illegal_fp_variable_width_3804_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3804 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3804, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3805; + auto valid_reg_overlap_3805_arg2 = LMUL_pow; + auto valid_reg_overlap_3805_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3805 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3805, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3804, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3805)); + setArg(call_illegal_fp_variable_width_3804, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3804, 1, vd); + setArg(call_illegal_fp_variable_width_3804, 2, vm); + setArg(call_illegal_fp_variable_width_3804, 3, illegal_fp_variable_width_3804_arg2); + setArg(call_illegal_fp_variable_width_3804, 4, illegal_fp_variable_width_3804_arg3); + setArg(call_illegal_fp_variable_width_3804, 5, illegal_fp_variable_width_3804_arg4); + setArg(call_illegal_fp_variable_width_3804, 6, illegal_fp_variable_width_3804_arg5); + setRet(call_illegal_fp_variable_width_3804, 0, ret_val_illegal_fp_variable_width_3804); + setArg(call_valid_reg_overlap_3805, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3805, 1, vs2); + setArg(call_valid_reg_overlap_3805, 2, vd); + setArg(call_valid_reg_overlap_3805, 3, valid_reg_overlap_3805_arg2); + setArg(call_valid_reg_overlap_3805, 4, valid_reg_overlap_3805_arg3); + setRet(call_valid_reg_overlap_3805, 0, ret_val_valid_reg_overlap_3805); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3807; + x86::Gp ret_val_sew_3807 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3807, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_w_3806; + auto fp_vector_unary_w_3806_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3806_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3806_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3806_arg8 = rm; + auto fp_vector_unary_w_3806_arg9 = ret_val_sew_3807; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_w_3806, &fp_vector_unary_w, FuncSignature::build()); + setArg(call_sew_3807, 0, reinterpret_cast(this)); + setRet(call_sew_3807, 0, ret_val_sew_3807); + setArg(call_fp_vector_unary_w_3806, 0, V); + setArg(call_fp_vector_unary_w_3806, 1, 12); + setArg(call_fp_vector_unary_w_3806, 2, fp_vector_unary_w_3806_arg2); + setArg(call_fp_vector_unary_w_3806, 3, fp_vector_unary_w_3806_arg3); + setArg(call_fp_vector_unary_w_3806, 4, fp_vector_unary_w_3806_arg4); + setArg(call_fp_vector_unary_w_3806, 5, vm); + setArg(call_fp_vector_unary_w_3806, 6, vd); + setArg(call_fp_vector_unary_w_3806, 7, vs2); + setArg(call_fp_vector_unary_w_3806, 8, fp_vector_unary_w_3806_arg8); + setArg(call_fp_vector_unary_w_3806, 9, fp_vector_unary_w_3806_arg9); + } + cc.bind(label_merge); + } + auto tmp3808 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3808, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3808, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 818); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 819: VFNCVT__X__F__W */ + continuation_e __vfncvt__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.x.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__X__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 819); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3809; + x86::Gp ret_val_get_sew_pow_3809 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3809, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3810 = get_reg(cc, 8, false); + mov(cc, tmp3810, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3810, (ret_val_get_sew_pow_3809))), 8, false), ~ 1); + setArg(call_get_sew_pow_3809, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3809, 0, ret_val_get_sew_pow_3809); + InvokeNode* call_get_lmul_pow_3811; + x86::Gp ret_val_get_lmul_pow_3811 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3811, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3811; + setArg(call_get_lmul_pow_3811, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3811, 0, ret_val_get_lmul_pow_3811); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3812; + auto illegal_fp_variable_width_3812_arg2 = SEW; + auto illegal_fp_variable_width_3812_arg3 = rm; + auto illegal_fp_variable_width_3812_arg4 = SEW_widen; + auto illegal_fp_variable_width_3812_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3812 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3812, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3813; + auto valid_reg_overlap_3813_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3813_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3813 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3813, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3812, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3813)); + setArg(call_illegal_fp_variable_width_3812, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3812, 1, vd); + setArg(call_illegal_fp_variable_width_3812, 2, vm); + setArg(call_illegal_fp_variable_width_3812, 3, illegal_fp_variable_width_3812_arg2); + setArg(call_illegal_fp_variable_width_3812, 4, illegal_fp_variable_width_3812_arg3); + setArg(call_illegal_fp_variable_width_3812, 5, illegal_fp_variable_width_3812_arg4); + setArg(call_illegal_fp_variable_width_3812, 6, illegal_fp_variable_width_3812_arg5); + setRet(call_illegal_fp_variable_width_3812, 0, ret_val_illegal_fp_variable_width_3812); + setArg(call_valid_reg_overlap_3813, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3813, 1, vs2); + setArg(call_valid_reg_overlap_3813, 2, vd); + setArg(call_valid_reg_overlap_3813, 3, valid_reg_overlap_3813_arg2); + setArg(call_valid_reg_overlap_3813, 4, valid_reg_overlap_3813_arg3); + setRet(call_valid_reg_overlap_3813, 0, ret_val_valid_reg_overlap_3813); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3815; + x86::Gp ret_val_sew_3815 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3815, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3814; + auto fp_vector_unary_n_3814_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3814_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3814_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3814_arg8 = rm; + auto fp_vector_unary_n_3814_arg9 = ret_val_sew_3815; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3814, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3815, 0, reinterpret_cast(this)); + setRet(call_sew_3815, 0, ret_val_sew_3815); + setArg(call_fp_vector_unary_n_3814, 0, V); + setArg(call_fp_vector_unary_n_3814, 1, 17); + setArg(call_fp_vector_unary_n_3814, 2, fp_vector_unary_n_3814_arg2); + setArg(call_fp_vector_unary_n_3814, 3, fp_vector_unary_n_3814_arg3); + setArg(call_fp_vector_unary_n_3814, 4, fp_vector_unary_n_3814_arg4); + setArg(call_fp_vector_unary_n_3814, 5, vm); + setArg(call_fp_vector_unary_n_3814, 6, vd); + setArg(call_fp_vector_unary_n_3814, 7, vs2); + setArg(call_fp_vector_unary_n_3814, 8, fp_vector_unary_n_3814_arg8); + setArg(call_fp_vector_unary_n_3814, 9, fp_vector_unary_n_3814_arg9); + } + cc.bind(label_merge); + } + auto tmp3816 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3816, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3816, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 819); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 820: VFNCVT__XU__F__W */ + continuation_e __vfncvt__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.xu.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__XU__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 820); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3817; + x86::Gp ret_val_get_sew_pow_3817 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3817, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3818 = get_reg(cc, 8, false); + mov(cc, tmp3818, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3818, (ret_val_get_sew_pow_3817))), 8, false), ~ 1); + setArg(call_get_sew_pow_3817, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3817, 0, ret_val_get_sew_pow_3817); + InvokeNode* call_get_lmul_pow_3819; + x86::Gp ret_val_get_lmul_pow_3819 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3819, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3819; + setArg(call_get_lmul_pow_3819, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3819, 0, ret_val_get_lmul_pow_3819); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3820; + auto illegal_fp_variable_width_3820_arg2 = SEW; + auto illegal_fp_variable_width_3820_arg3 = rm; + auto illegal_fp_variable_width_3820_arg4 = SEW_widen; + auto illegal_fp_variable_width_3820_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3820 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3820, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3821; + auto valid_reg_overlap_3821_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3821_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3821 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3821, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3820, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3821)); + setArg(call_illegal_fp_variable_width_3820, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3820, 1, vd); + setArg(call_illegal_fp_variable_width_3820, 2, vm); + setArg(call_illegal_fp_variable_width_3820, 3, illegal_fp_variable_width_3820_arg2); + setArg(call_illegal_fp_variable_width_3820, 4, illegal_fp_variable_width_3820_arg3); + setArg(call_illegal_fp_variable_width_3820, 5, illegal_fp_variable_width_3820_arg4); + setArg(call_illegal_fp_variable_width_3820, 6, illegal_fp_variable_width_3820_arg5); + setRet(call_illegal_fp_variable_width_3820, 0, ret_val_illegal_fp_variable_width_3820); + setArg(call_valid_reg_overlap_3821, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3821, 1, vs2); + setArg(call_valid_reg_overlap_3821, 2, vd); + setArg(call_valid_reg_overlap_3821, 3, valid_reg_overlap_3821_arg2); + setArg(call_valid_reg_overlap_3821, 4, valid_reg_overlap_3821_arg3); + setRet(call_valid_reg_overlap_3821, 0, ret_val_valid_reg_overlap_3821); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3823; + x86::Gp ret_val_sew_3823 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3823, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3822; + auto fp_vector_unary_n_3822_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3822_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3822_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3822_arg8 = rm; + auto fp_vector_unary_n_3822_arg9 = ret_val_sew_3823; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3822, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3823, 0, reinterpret_cast(this)); + setRet(call_sew_3823, 0, ret_val_sew_3823); + setArg(call_fp_vector_unary_n_3822, 0, V); + setArg(call_fp_vector_unary_n_3822, 1, 16); + setArg(call_fp_vector_unary_n_3822, 2, fp_vector_unary_n_3822_arg2); + setArg(call_fp_vector_unary_n_3822, 3, fp_vector_unary_n_3822_arg3); + setArg(call_fp_vector_unary_n_3822, 4, fp_vector_unary_n_3822_arg4); + setArg(call_fp_vector_unary_n_3822, 5, vm); + setArg(call_fp_vector_unary_n_3822, 6, vd); + setArg(call_fp_vector_unary_n_3822, 7, vs2); + setArg(call_fp_vector_unary_n_3822, 8, fp_vector_unary_n_3822_arg8); + setArg(call_fp_vector_unary_n_3822, 9, fp_vector_unary_n_3822_arg9); + } + cc.bind(label_merge); + } + auto tmp3824 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3824, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3824, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 820); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 821: VFNCVT__RTZ__XU__F__W */ + continuation_e __vfncvt__rtz__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.xu.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__RTZ__XU__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 821); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3825; + x86::Gp ret_val_get_sew_pow_3825 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3825, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3826 = get_reg(cc, 8, false); + mov(cc, tmp3826, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3826, (ret_val_get_sew_pow_3825))), 8, false), ~ 1); + setArg(call_get_sew_pow_3825, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3825, 0, ret_val_get_sew_pow_3825); + InvokeNode* call_get_lmul_pow_3827; + x86::Gp ret_val_get_lmul_pow_3827 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3827, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3827; + setArg(call_get_lmul_pow_3827, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3827, 0, ret_val_get_lmul_pow_3827); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3828; + auto illegal_fp_variable_width_3828_arg2 = SEW; + auto illegal_fp_variable_width_3828_arg4 = SEW_widen; + auto illegal_fp_variable_width_3828_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3828 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3828, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3829; + auto valid_reg_overlap_3829_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3829_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3829 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3829, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3828, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3829)); + setArg(call_illegal_fp_variable_width_3828, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3828, 1, vd); + setArg(call_illegal_fp_variable_width_3828, 2, vm); + setArg(call_illegal_fp_variable_width_3828, 3, illegal_fp_variable_width_3828_arg2); + setArg(call_illegal_fp_variable_width_3828, 4, rm); + setArg(call_illegal_fp_variable_width_3828, 5, illegal_fp_variable_width_3828_arg4); + setArg(call_illegal_fp_variable_width_3828, 6, illegal_fp_variable_width_3828_arg5); + setRet(call_illegal_fp_variable_width_3828, 0, ret_val_illegal_fp_variable_width_3828); + setArg(call_valid_reg_overlap_3829, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3829, 1, vs2); + setArg(call_valid_reg_overlap_3829, 2, vd); + setArg(call_valid_reg_overlap_3829, 3, valid_reg_overlap_3829_arg2); + setArg(call_valid_reg_overlap_3829, 4, valid_reg_overlap_3829_arg3); + setRet(call_valid_reg_overlap_3829, 0, ret_val_valid_reg_overlap_3829); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3831; + x86::Gp ret_val_sew_3831 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3831, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3830; + auto fp_vector_unary_n_3830_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3830_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3830_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3830_arg9 = ret_val_sew_3831; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3830, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3831, 0, reinterpret_cast(this)); + setRet(call_sew_3831, 0, ret_val_sew_3831); + setArg(call_fp_vector_unary_n_3830, 0, V); + setArg(call_fp_vector_unary_n_3830, 1, 22); + setArg(call_fp_vector_unary_n_3830, 2, fp_vector_unary_n_3830_arg2); + setArg(call_fp_vector_unary_n_3830, 3, fp_vector_unary_n_3830_arg3); + setArg(call_fp_vector_unary_n_3830, 4, fp_vector_unary_n_3830_arg4); + setArg(call_fp_vector_unary_n_3830, 5, vm); + setArg(call_fp_vector_unary_n_3830, 6, vd); + setArg(call_fp_vector_unary_n_3830, 7, vs2); + setArg(call_fp_vector_unary_n_3830, 8, rm); + setArg(call_fp_vector_unary_n_3830, 9, fp_vector_unary_n_3830_arg9); + } + cc.bind(label_merge); + } + auto tmp3832 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3832, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3832, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 821); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 822: VFNCVT__RTZ__X__F__W */ + continuation_e __vfncvt__rtz__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.x.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__RTZ__X__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 822); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3833; + x86::Gp ret_val_get_sew_pow_3833 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3833, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3834 = get_reg(cc, 8, false); + mov(cc, tmp3834, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3834, (ret_val_get_sew_pow_3833))), 8, false), ~ 1); + setArg(call_get_sew_pow_3833, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3833, 0, ret_val_get_sew_pow_3833); + InvokeNode* call_get_lmul_pow_3835; + x86::Gp ret_val_get_lmul_pow_3835 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3835, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3835; + setArg(call_get_lmul_pow_3835, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3835, 0, ret_val_get_lmul_pow_3835); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = 1; + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3836; + auto illegal_fp_variable_width_3836_arg2 = SEW; + auto illegal_fp_variable_width_3836_arg4 = SEW_widen; + auto illegal_fp_variable_width_3836_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3836 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3836, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3837; + auto valid_reg_overlap_3837_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3837_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3837 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3837, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3836, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3837)); + setArg(call_illegal_fp_variable_width_3836, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3836, 1, vd); + setArg(call_illegal_fp_variable_width_3836, 2, vm); + setArg(call_illegal_fp_variable_width_3836, 3, illegal_fp_variable_width_3836_arg2); + setArg(call_illegal_fp_variable_width_3836, 4, rm); + setArg(call_illegal_fp_variable_width_3836, 5, illegal_fp_variable_width_3836_arg4); + setArg(call_illegal_fp_variable_width_3836, 6, illegal_fp_variable_width_3836_arg5); + setRet(call_illegal_fp_variable_width_3836, 0, ret_val_illegal_fp_variable_width_3836); + setArg(call_valid_reg_overlap_3837, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3837, 1, vs2); + setArg(call_valid_reg_overlap_3837, 2, vd); + setArg(call_valid_reg_overlap_3837, 3, valid_reg_overlap_3837_arg2); + setArg(call_valid_reg_overlap_3837, 4, valid_reg_overlap_3837_arg3); + setRet(call_valid_reg_overlap_3837, 0, ret_val_valid_reg_overlap_3837); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3839; + x86::Gp ret_val_sew_3839 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3839, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3838; + auto fp_vector_unary_n_3838_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3838_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3838_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3838_arg9 = ret_val_sew_3839; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3838, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3839, 0, reinterpret_cast(this)); + setRet(call_sew_3839, 0, ret_val_sew_3839); + setArg(call_fp_vector_unary_n_3838, 0, V); + setArg(call_fp_vector_unary_n_3838, 1, 23); + setArg(call_fp_vector_unary_n_3838, 2, fp_vector_unary_n_3838_arg2); + setArg(call_fp_vector_unary_n_3838, 3, fp_vector_unary_n_3838_arg3); + setArg(call_fp_vector_unary_n_3838, 4, fp_vector_unary_n_3838_arg4); + setArg(call_fp_vector_unary_n_3838, 5, vm); + setArg(call_fp_vector_unary_n_3838, 6, vd); + setArg(call_fp_vector_unary_n_3838, 7, vs2); + setArg(call_fp_vector_unary_n_3838, 8, rm); + setArg(call_fp_vector_unary_n_3838, 9, fp_vector_unary_n_3838_arg9); + } + cc.bind(label_merge); + } + auto tmp3840 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3840, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3840, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 822); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 823: VFNCVT__F__XU__W */ + continuation_e __vfncvt__f__xu__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.xu.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__F__XU__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 823); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3841; + x86::Gp ret_val_get_sew_pow_3841 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3841, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3842 = get_reg(cc, 8, false); + mov(cc, tmp3842, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3842, (ret_val_get_sew_pow_3841))), 8, false), ~ 1); + setArg(call_get_sew_pow_3841, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3841, 0, ret_val_get_sew_pow_3841); + InvokeNode* call_get_lmul_pow_3843; + x86::Gp ret_val_get_lmul_pow_3843 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3843, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3843; + setArg(call_get_lmul_pow_3843, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3843, 0, ret_val_get_lmul_pow_3843); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3844; + auto illegal_fp_variable_width_3844_arg2 = SEW; + auto illegal_fp_variable_width_3844_arg3 = rm; + auto illegal_fp_variable_width_3844_arg4 = SEW_widen; + auto illegal_fp_variable_width_3844_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3844 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3844, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3845; + auto valid_reg_overlap_3845_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3845_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3845 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3845, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3844, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3845)); + setArg(call_illegal_fp_variable_width_3844, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3844, 1, vd); + setArg(call_illegal_fp_variable_width_3844, 2, vm); + setArg(call_illegal_fp_variable_width_3844, 3, illegal_fp_variable_width_3844_arg2); + setArg(call_illegal_fp_variable_width_3844, 4, illegal_fp_variable_width_3844_arg3); + setArg(call_illegal_fp_variable_width_3844, 5, illegal_fp_variable_width_3844_arg4); + setArg(call_illegal_fp_variable_width_3844, 6, illegal_fp_variable_width_3844_arg5); + setRet(call_illegal_fp_variable_width_3844, 0, ret_val_illegal_fp_variable_width_3844); + setArg(call_valid_reg_overlap_3845, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3845, 1, vs2); + setArg(call_valid_reg_overlap_3845, 2, vd); + setArg(call_valid_reg_overlap_3845, 3, valid_reg_overlap_3845_arg2); + setArg(call_valid_reg_overlap_3845, 4, valid_reg_overlap_3845_arg3); + setRet(call_valid_reg_overlap_3845, 0, ret_val_valid_reg_overlap_3845); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3847; + x86::Gp ret_val_sew_3847 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3847, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3846; + auto fp_vector_unary_n_3846_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3846_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3846_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3846_arg8 = rm; + auto fp_vector_unary_n_3846_arg9 = ret_val_sew_3847; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3846, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3847, 0, reinterpret_cast(this)); + setRet(call_sew_3847, 0, ret_val_sew_3847); + setArg(call_fp_vector_unary_n_3846, 0, V); + setArg(call_fp_vector_unary_n_3846, 1, 18); + setArg(call_fp_vector_unary_n_3846, 2, fp_vector_unary_n_3846_arg2); + setArg(call_fp_vector_unary_n_3846, 3, fp_vector_unary_n_3846_arg3); + setArg(call_fp_vector_unary_n_3846, 4, fp_vector_unary_n_3846_arg4); + setArg(call_fp_vector_unary_n_3846, 5, vm); + setArg(call_fp_vector_unary_n_3846, 6, vd); + setArg(call_fp_vector_unary_n_3846, 7, vs2); + setArg(call_fp_vector_unary_n_3846, 8, fp_vector_unary_n_3846_arg8); + setArg(call_fp_vector_unary_n_3846, 9, fp_vector_unary_n_3846_arg9); + } + cc.bind(label_merge); + } + auto tmp3848 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3848, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3848, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 823); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 824: VFNCVT__F__X__W */ + continuation_e __vfncvt__f__x__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.x.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__F__X__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 824); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3849; + x86::Gp ret_val_get_sew_pow_3849 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3849, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3850 = get_reg(cc, 8, false); + mov(cc, tmp3850, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3850, (ret_val_get_sew_pow_3849))), 8, false), ~ 1); + setArg(call_get_sew_pow_3849, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3849, 0, ret_val_get_sew_pow_3849); + InvokeNode* call_get_lmul_pow_3851; + x86::Gp ret_val_get_lmul_pow_3851 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3851, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3851; + setArg(call_get_lmul_pow_3851, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3851, 0, ret_val_get_lmul_pow_3851); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3852; + auto illegal_fp_variable_width_3852_arg2 = SEW; + auto illegal_fp_variable_width_3852_arg3 = rm; + auto illegal_fp_variable_width_3852_arg4 = SEW_widen; + auto illegal_fp_variable_width_3852_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3852 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3852, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3853; + auto valid_reg_overlap_3853_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3853_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3853 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3853, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3852, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3853)); + setArg(call_illegal_fp_variable_width_3852, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3852, 1, vd); + setArg(call_illegal_fp_variable_width_3852, 2, vm); + setArg(call_illegal_fp_variable_width_3852, 3, illegal_fp_variable_width_3852_arg2); + setArg(call_illegal_fp_variable_width_3852, 4, illegal_fp_variable_width_3852_arg3); + setArg(call_illegal_fp_variable_width_3852, 5, illegal_fp_variable_width_3852_arg4); + setArg(call_illegal_fp_variable_width_3852, 6, illegal_fp_variable_width_3852_arg5); + setRet(call_illegal_fp_variable_width_3852, 0, ret_val_illegal_fp_variable_width_3852); + setArg(call_valid_reg_overlap_3853, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3853, 1, vs2); + setArg(call_valid_reg_overlap_3853, 2, vd); + setArg(call_valid_reg_overlap_3853, 3, valid_reg_overlap_3853_arg2); + setArg(call_valid_reg_overlap_3853, 4, valid_reg_overlap_3853_arg3); + setRet(call_valid_reg_overlap_3853, 0, ret_val_valid_reg_overlap_3853); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3855; + x86::Gp ret_val_sew_3855 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3855, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3854; + auto fp_vector_unary_n_3854_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3854_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3854_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3854_arg8 = rm; + auto fp_vector_unary_n_3854_arg9 = ret_val_sew_3855; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3854, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3855, 0, reinterpret_cast(this)); + setRet(call_sew_3855, 0, ret_val_sew_3855); + setArg(call_fp_vector_unary_n_3854, 0, V); + setArg(call_fp_vector_unary_n_3854, 1, 19); + setArg(call_fp_vector_unary_n_3854, 2, fp_vector_unary_n_3854_arg2); + setArg(call_fp_vector_unary_n_3854, 3, fp_vector_unary_n_3854_arg3); + setArg(call_fp_vector_unary_n_3854, 4, fp_vector_unary_n_3854_arg4); + setArg(call_fp_vector_unary_n_3854, 5, vm); + setArg(call_fp_vector_unary_n_3854, 6, vd); + setArg(call_fp_vector_unary_n_3854, 7, vs2); + setArg(call_fp_vector_unary_n_3854, 8, fp_vector_unary_n_3854_arg8); + setArg(call_fp_vector_unary_n_3854, 9, fp_vector_unary_n_3854_arg9); + } + cc.bind(label_merge); + } + auto tmp3856 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3856, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3856, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 824); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 825: VFNCVT__F__F__W */ + continuation_e __vfncvt__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__F__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 825); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3857; + x86::Gp ret_val_get_sew_pow_3857 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3857, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3858 = get_reg(cc, 8, false); + mov(cc, tmp3858, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3858, (ret_val_get_sew_pow_3857))), 8, false), ~ 1); + setArg(call_get_sew_pow_3857, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3857, 0, ret_val_get_sew_pow_3857); + InvokeNode* call_get_lmul_pow_3859; + x86::Gp ret_val_get_lmul_pow_3859 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3859, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3859; + setArg(call_get_lmul_pow_3859, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3859, 0, ret_val_get_lmul_pow_3859); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3860; + auto illegal_fp_variable_width_3860_arg2 = SEW; + auto illegal_fp_variable_width_3860_arg3 = rm; + auto illegal_fp_variable_width_3860_arg4 = SEW_widen; + auto illegal_fp_variable_width_3860_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3860 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3860, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3861; + auto valid_reg_overlap_3861_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3861_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3861 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3861, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3860, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3861)); + setArg(call_illegal_fp_variable_width_3860, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3860, 1, vd); + setArg(call_illegal_fp_variable_width_3860, 2, vm); + setArg(call_illegal_fp_variable_width_3860, 3, illegal_fp_variable_width_3860_arg2); + setArg(call_illegal_fp_variable_width_3860, 4, illegal_fp_variable_width_3860_arg3); + setArg(call_illegal_fp_variable_width_3860, 5, illegal_fp_variable_width_3860_arg4); + setArg(call_illegal_fp_variable_width_3860, 6, illegal_fp_variable_width_3860_arg5); + setRet(call_illegal_fp_variable_width_3860, 0, ret_val_illegal_fp_variable_width_3860); + setArg(call_valid_reg_overlap_3861, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3861, 1, vs2); + setArg(call_valid_reg_overlap_3861, 2, vd); + setArg(call_valid_reg_overlap_3861, 3, valid_reg_overlap_3861_arg2); + setArg(call_valid_reg_overlap_3861, 4, valid_reg_overlap_3861_arg3); + setRet(call_valid_reg_overlap_3861, 0, ret_val_valid_reg_overlap_3861); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3863; + x86::Gp ret_val_sew_3863 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3863, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3862; + auto fp_vector_unary_n_3862_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3862_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3862_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3862_arg8 = rm; + auto fp_vector_unary_n_3862_arg9 = ret_val_sew_3863; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3862, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3863, 0, reinterpret_cast(this)); + setRet(call_sew_3863, 0, ret_val_sew_3863); + setArg(call_fp_vector_unary_n_3862, 0, V); + setArg(call_fp_vector_unary_n_3862, 1, 20); + setArg(call_fp_vector_unary_n_3862, 2, fp_vector_unary_n_3862_arg2); + setArg(call_fp_vector_unary_n_3862, 3, fp_vector_unary_n_3862_arg3); + setArg(call_fp_vector_unary_n_3862, 4, fp_vector_unary_n_3862_arg4); + setArg(call_fp_vector_unary_n_3862, 5, vm); + setArg(call_fp_vector_unary_n_3862, 6, vd); + setArg(call_fp_vector_unary_n_3862, 7, vs2); + setArg(call_fp_vector_unary_n_3862, 8, fp_vector_unary_n_3862_arg8); + setArg(call_fp_vector_unary_n_3862, 9, fp_vector_unary_n_3862_arg9); + } + cc.bind(label_merge); + } + auto tmp3864 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3864, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3864, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 825); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 826: VFNCVT__ROD__F__F__W */ + continuation_e __vfncvt__rod__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rod.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__ROD__F__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 826); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3865; + x86::Gp ret_val_get_sew_pow_3865 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3865, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3866 = get_reg(cc, 8, false); + mov(cc, tmp3866, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3866, (ret_val_get_sew_pow_3865))), 8, false), ~ 1); + setArg(call_get_sew_pow_3865, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3865, 0, ret_val_get_sew_pow_3865); + InvokeNode* call_get_lmul_pow_3867; + x86::Gp ret_val_get_lmul_pow_3867 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3867, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3867; + setArg(call_get_lmul_pow_3867, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3867, 0, ret_val_get_lmul_pow_3867); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3868; + auto illegal_fp_variable_width_3868_arg2 = SEW; + auto illegal_fp_variable_width_3868_arg3 = rm; + auto illegal_fp_variable_width_3868_arg4 = SEW_widen; + auto illegal_fp_variable_width_3868_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3868 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3868, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3869; + auto valid_reg_overlap_3869_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3869_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3869 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3869, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3868, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3869)); + setArg(call_illegal_fp_variable_width_3868, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3868, 1, vd); + setArg(call_illegal_fp_variable_width_3868, 2, vm); + setArg(call_illegal_fp_variable_width_3868, 3, illegal_fp_variable_width_3868_arg2); + setArg(call_illegal_fp_variable_width_3868, 4, illegal_fp_variable_width_3868_arg3); + setArg(call_illegal_fp_variable_width_3868, 5, illegal_fp_variable_width_3868_arg4); + setArg(call_illegal_fp_variable_width_3868, 6, illegal_fp_variable_width_3868_arg5); + setRet(call_illegal_fp_variable_width_3868, 0, ret_val_illegal_fp_variable_width_3868); + setArg(call_valid_reg_overlap_3869, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3869, 1, vs2); + setArg(call_valid_reg_overlap_3869, 2, vd); + setArg(call_valid_reg_overlap_3869, 3, valid_reg_overlap_3869_arg2); + setArg(call_valid_reg_overlap_3869, 4, valid_reg_overlap_3869_arg3); + setRet(call_valid_reg_overlap_3869, 0, ret_val_valid_reg_overlap_3869); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3871; + x86::Gp ret_val_sew_3871 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3871, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3870; + auto fp_vector_unary_n_3870_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3870_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3870_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3870_arg9 = ret_val_sew_3871; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3870, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3871, 0, reinterpret_cast(this)); + setRet(call_sew_3871, 0, ret_val_sew_3871); + setArg(call_fp_vector_unary_n_3870, 0, V); + setArg(call_fp_vector_unary_n_3870, 1, 21); + setArg(call_fp_vector_unary_n_3870, 2, fp_vector_unary_n_3870_arg2); + setArg(call_fp_vector_unary_n_3870, 3, fp_vector_unary_n_3870_arg3); + setArg(call_fp_vector_unary_n_3870, 4, fp_vector_unary_n_3870_arg4); + setArg(call_fp_vector_unary_n_3870, 5, vm); + setArg(call_fp_vector_unary_n_3870, 6, vd); + setArg(call_fp_vector_unary_n_3870, 7, vs2); + setArg(call_fp_vector_unary_n_3870, 8, 6); + setArg(call_fp_vector_unary_n_3870, 9, fp_vector_unary_n_3870_arg9); + } + cc.bind(label_merge); + } + auto tmp3872 = get_reg_Gp(cc, 8, false); + mov(cc, tmp3872, 0); + write_reg_to_mem(jh, + gen_ext(cc, tmp3872, 64, false) + , traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 826); + gen_instr_epilogue(jh); + return returnValue; + } + + /**************************************************************************** + * end opcode definitions + ****************************************************************************/ + continuation_e illegal_instruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) { + x86::Compiler& cc = jh.cc; + if(this->disass_enabled){ + auto mnemonic = std::string("illegal_instruction"); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } + cc.comment(fmt::format("illegal_instruction{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, instr_descr.size()); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc + ((instr & 3) == 3 ? 4 : 2); + mov(cc, jh.next_pc, pc.val); + gen_instr_prologue(jh); + gen_raise(jh, 0, 2); + gen_sync(jh, POST_SYNC, instr_descr.size()); + gen_instr_epilogue(jh); + return ILLEGAL_INSTR; + } +}; + +template vm_impl::vm_impl() { this(new ARCH()); } + +template +vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) +: vm_base(core, core_id, cluster_id) +, instr_decoder([this]() { + std::vector g_instr_descr; + g_instr_descr.reserve(instr_descr.size()); + for (uint32_t i = 0; i < instr_descr.size(); ++i) { + generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i}; + g_instr_descr.push_back(new_instr_descr); + } + return std::move(g_instr_descr); + }()) {} + +template +continuation_e vm_impl::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) { + enum {TRAP_ID=1<<16}; + code_word_t instr = 0; + phys_addr_t paddr(pc); + auto *const data = (uint8_t *)&instr; + auto res = this->core.read(paddr, 4, data); + if (res != iss::Ok) + return ILLEGAL_FETCH; + if (instr == 0x0000006f || (instr&0xffff)==0xa001) + return JUMP_TO_SELF; + uint32_t inst_index = instr_decoder.decode_instr(instr); + compile_func f = nullptr; + if(inst_index < instr_descr.size()) + f = instr_descr[inst_index].op; + if (f == nullptr) + f = &this_class::illegal_instruction; + return (this->*f)(pc, instr, jh); +} +template +void vm_impl::gen_instr_prologue(jit_holder& jh) { + auto& cc = jh.cc; + + x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE); + mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state); + cc.comment("//Instruction prologue end"); + +} +template +void vm_impl::gen_instr_epilogue(jit_holder& jh) { + auto& cc = jh.cc; + + cc.comment("//Instruction epilogue begin"); + cc.inc(get_ptr_for(jh, traits::CYCLE)); + x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE); + mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + cmp(cc, current_trap_state, 0); + cc.jne(jh.trap_entry); + cc.inc(get_ptr_for(jh, traits::ICOUNT)); + cc.inc(get_ptr_for(jh, traits::INSTRET)); + cc.comment("//Instruction epilogue end"); + +} +template +void vm_impl::gen_block_prologue(jit_holder& jh){ + jh.pc = load_reg_from_mem_Gp(jh, traits::PC); + jh.next_pc = load_reg_from_mem_Gp(jh, traits::NEXT_PC); + jh.globals.resize(GLOBALS_SIZE); + jh.globals[TVAL] = get_reg_Gp(jh.cc, 64, false); +} +template +void vm_impl::gen_block_epilogue(jit_holder& jh){ + x86::Compiler& cc = jh.cc; + cc.comment("//gen_block_epilogue"); + cc.ret(jh.next_pc); + + cc.bind(jh.trap_entry); + this->write_back(jh); + + x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE); + mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + + x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC); + mov(cc, current_pc, get_ptr_for(jh, traits::PC)); + + InvokeNode* call_enter_trap; + cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build()); + call_enter_trap->setArg(0, jh.arch_if_ptr); + call_enter_trap->setArg(1, current_trap_state); + call_enter_trap->setArg(2, current_pc); + call_enter_trap->setArg(3, jh.globals[TVAL]); + + x86_reg_t current_next_pc = get_reg_for(cc, traits::NEXT_PC); + mov(cc, current_next_pc, get_ptr_for(jh, traits::NEXT_PC)); + mov(cc, jh.next_pc, current_next_pc); + + mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast(UNKNOWN_JUMP)); + cc.ret(jh.next_pc); +} +template +inline void vm_impl::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) { + auto& cc = jh.cc; + auto tmp1 = get_reg_for(cc, traits::TRAP_STATE); + mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id); + mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1); + cc.jmp(jh.trap_entry); +} +template +inline void vm_impl::gen_lower(jit_holder& jh) { + auto& cc = jh.cc; + auto tmp1 = get_reg_for(cc, traits::TRAP_STATE); + mov(cc, tmp1, 0); + mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1); + cc.jmp(jh.trap_entry); +} +template +template +void vm_impl::gen_set_tval(jit_holder& jh, T new_tval) { + mov(jh.cc, jh.globals[TVAL], new_tval); + } +template +void vm_impl::gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) { + if(nonstd::holds_alternative(_new_tval)) { + x86::Gp new_tval = nonstd::get(_new_tval); + if(new_tval.size() < 8) + new_tval = gen_ext_Gp(jh.cc, new_tval, 64, false); + mov(jh.cc, jh.globals[TVAL], new_tval); + } else { + throw std::runtime_error("Variant not supported in gen_set_tval"); + } +} + +} // namespace tgc5c + +template <> +std::unique_ptr create(arch::rv64gcv *core, unsigned short port, bool dump) { + auto ret = new rv64gcv::vm_impl(*core, dump); + if (port != 0) debugger::server::run_server(ret, port); + return std::unique_ptr(ret); +} +} // namespace asmjit +} // namespace iss + +#include +#include +#include +#include +namespace iss { +namespace { + +volatile std::array dummy = { + core_factory::instance().register_creator("rv64gcv_msu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_msu_vp(); + auto vm = new asmjit::rv64gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("rv64gcv_m:asmjit", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_m_p(); + auto vm = new asmjit::rv64gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("rv64gcv_mu:asmjit", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_mu_p(); + auto vm = new asmjit::rv64gcv::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }) +}; +} +} +// clang-format on From 2205e490314750cc16a248941bed0abe1e06d924 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Wed, 24 Sep 2025 14:28:21 +0200 Subject: [PATCH 015/230] moves trampoline functions into class to use traits instead of template param --- CMakeLists.txt | 1 - gen_input/templates/asmjit/CORENAME.cpp.gtl | 77 +- gen_input/templates/interp/CORENAME.cpp.gtl | 76 +- src/vm/asmjit/vm_rv32gcv.cpp | 18547 +++++++++--------- src/vm/asmjit/vm_rv64gcv.cpp | 17621 ++++++++--------- src/vm/interp/vm_rv32gcv.cpp | 130 +- src/vm/interp/vm_rv64gcv.cpp | 130 +- src/vm/new_vector_functions.cpp | 934 - src/vm/new_vector_functions.h | 966 +- 9 files changed, 18724 insertions(+), 19758 deletions(-) delete mode 100644 src/vm/new_vector_functions.cpp diff --git a/CMakeLists.txt b/CMakeLists.txt index cca601e..083cdbc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -69,7 +69,6 @@ set(LIB_SOURCES src/vm/interp/vm_rv64gcv.cpp src/vm/fp_functions.cpp src/vm/vector_functions.cpp - src/vm/new_vector_functions.cpp src/iss/debugger/csr_names.cpp src/iss/semihosting/semihosting.cpp ) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 5e48a0e..4aae8d1 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -50,12 +50,7 @@ def nativeTypeSize(int size){ if(floating_point) {%> #include <%} -if(vector) { -def xlen = constants.find { it.name == 'XLEN' }?.value ?: 0 -def vlen = constants.find { it.name == 'VLEN' }?.value ?: 0 %> -#define CUR_VLEN ${vlen} -#define CUR_XLEN ${xlen} -#include +if(vector){%> #include <%} if(aes) {%> @@ -87,9 +82,8 @@ template <> struct is_unsigned { static constexpr bool value = true; namespace iss { namespace asmjit { +namespace ${coreDef.name.toLowerCase()}{ - -namespace ${coreDef.name.toLowerCase()} { using namespace ::asmjit; using namespace iss::arch; using namespace iss::debugger; @@ -104,6 +98,72 @@ public: using mem_type_e = typename super::mem_type_e; using addr_t = typename super::addr_t; +<%if(vector) {%> + static constexpr auto& vlseg = trampoline::vlseg; + static constexpr auto& vsseg = trampoline::vsseg; + static constexpr auto& vlsseg = trampoline::vlsseg; + static constexpr auto& vssseg = trampoline::vssseg; + static constexpr auto& vlxseg = trampoline::vlxseg; + static constexpr auto& vsxseg = trampoline::vsxseg; + static constexpr auto& vector_vector_op = trampoline::vector_vector_op; + static constexpr auto& vector_imm_op = trampoline::vector_imm_op; + static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; + static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; + static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; + static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; + static constexpr auto& vector_extend = trampoline::vector_extend; + static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; + static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; + static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; + static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; + static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; + static constexpr auto& vector_red_op = trampoline::vector_red_op; + static constexpr auto& vector_red_wv = trampoline::vector_red_wv; + static constexpr auto& mask_mask_op = trampoline::mask_mask_op; + static constexpr auto& vcpop = trampoline::vcpop; + static constexpr auto& vfirst = trampoline::vfirst; + static constexpr auto& mask_set_op = trampoline::mask_set_op; + static constexpr auto& viota = trampoline::viota; + static constexpr auto& vid = trampoline::vid; + static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; + static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; + static constexpr auto& vector_slideup = trampoline::vector_slideup; + static constexpr auto& vector_slidedown = trampoline::vector_slidedown; + static constexpr auto& vector_slide1up = trampoline::vector_slide1up; + static constexpr auto& vector_slide1down = trampoline::vector_slide1down; + static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; + static constexpr auto& vector_compress = trampoline::vector_compress; + static constexpr auto& vector_whole_move = trampoline::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; + static constexpr auto& vector_unary_op = trampoline::vector_unary_op; +<%}%> vm_impl(); vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); @@ -394,7 +454,6 @@ inline void vm_impl::gen_lower(jit_holder& jh) { auto tmp1 = get_reg_for(cc, traits::TRAP_STATE); mov(cc, tmp1, 0); mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1); - cc.jmp(jh.trap_entry); } template template diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 7e10961..187768f 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -48,12 +48,7 @@ def nativeTypeSize(int size){ if(floating_point) {%> #include <%} -if(vector) { -def xlen = constants.find { it.name == 'XLEN' }?.value ?: 0 -def vlen = constants.find { it.name == 'VLEN' }?.value ?: 0 %> -#define CUR_VLEN ${vlen} -#define CUR_XLEN ${xlen} -#include +if(vector) {%> #include <%} if(aes) {%> @@ -79,6 +74,7 @@ if(aes) {%> namespace iss { namespace interp { namespace ${coreDef.name.toLowerCase()} { + using namespace iss::arch; using namespace iss::debugger; using namespace std::placeholders; @@ -98,7 +94,73 @@ public: using reg_t = typename traits::reg_t; using mem_type_e = typename traits::mem_type_e; using opcode_e = typename traits::opcode_e; - + +<%if(vector) {%> + static constexpr auto& vlseg = trampoline::vlseg; + static constexpr auto& vsseg = trampoline::vsseg; + static constexpr auto& vlsseg = trampoline::vlsseg; + static constexpr auto& vssseg = trampoline::vssseg; + static constexpr auto& vlxseg = trampoline::vlxseg; + static constexpr auto& vsxseg = trampoline::vsxseg; + static constexpr auto& vector_vector_op = trampoline::vector_vector_op; + static constexpr auto& vector_imm_op = trampoline::vector_imm_op; + static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; + static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; + static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; + static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; + static constexpr auto& vector_extend = trampoline::vector_extend; + static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; + static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; + static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; + static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; + static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; + static constexpr auto& vector_red_op = trampoline::vector_red_op; + static constexpr auto& vector_red_wv = trampoline::vector_red_wv; + static constexpr auto& mask_mask_op = trampoline::mask_mask_op; + static constexpr auto& vcpop = trampoline::vcpop; + static constexpr auto& vfirst = trampoline::vfirst; + static constexpr auto& mask_set_op = trampoline::mask_set_op; + static constexpr auto& viota = trampoline::viota; + static constexpr auto& vid = trampoline::vid; + static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; + static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; + static constexpr auto& vector_slideup = trampoline::vector_slideup; + static constexpr auto& vector_slidedown = trampoline::vector_slidedown; + static constexpr auto& vector_slide1up = trampoline::vector_slide1up; + static constexpr auto& vector_slide1down = trampoline::vector_slide1down; + static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; + static constexpr auto& vector_compress = trampoline::vector_compress; + static constexpr auto& vector_whole_move = trampoline::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; + static constexpr auto& vector_unary_op = trampoline::vector_unary_op; +<%}%> vm_impl(); vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); diff --git a/src/vm/asmjit/vm_rv32gcv.cpp b/src/vm/asmjit/vm_rv32gcv.cpp index 2474b96..0f04046 100644 --- a/src/vm/asmjit/vm_rv32gcv.cpp +++ b/src/vm/asmjit/vm_rv32gcv.cpp @@ -29,7 +29,7 @@ * POSSIBILITY OF SUCH DAMAGE. * *******************************************************************************/ - + // clang-format off #include #include @@ -42,9 +42,6 @@ #include -#define CUR_VLEN 256 -#define CUR_XLEN 32 -#include #include #ifndef FMT_HEADER_ONLY @@ -73,9 +70,8 @@ template <> struct is_unsigned { static constexpr bool value = true; namespace iss { namespace asmjit { +namespace rv32gcv{ - -namespace rv32gcv { using namespace ::asmjit; using namespace iss::arch; using namespace iss::debugger; @@ -90,6 +86,72 @@ template class vm_impl : public iss::asmjit::vm_base { using mem_type_e = typename super::mem_type_e; using addr_t = typename super::addr_t; + + static constexpr auto& vlseg = trampoline::vlseg; + static constexpr auto& vsseg = trampoline::vsseg; + static constexpr auto& vlsseg = trampoline::vlsseg; + static constexpr auto& vssseg = trampoline::vssseg; + static constexpr auto& vlxseg = trampoline::vlxseg; + static constexpr auto& vsxseg = trampoline::vsxseg; + static constexpr auto& vector_vector_op = trampoline::vector_vector_op; + static constexpr auto& vector_imm_op = trampoline::vector_imm_op; + static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; + static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; + static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; + static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; + static constexpr auto& vector_extend = trampoline::vector_extend; + static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; + static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; + static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; + static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; + static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; + static constexpr auto& vector_red_op = trampoline::vector_red_op; + static constexpr auto& vector_red_wv = trampoline::vector_red_wv; + static constexpr auto& mask_mask_op = trampoline::mask_mask_op; + static constexpr auto& vcpop = trampoline::vcpop; + static constexpr auto& vfirst = trampoline::vfirst; + static constexpr auto& mask_set_op = trampoline::mask_set_op; + static constexpr auto& viota = trampoline::viota; + static constexpr auto& vid = trampoline::vid; + static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; + static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; + static constexpr auto& vector_slideup = trampoline::vector_slideup; + static constexpr auto& vector_slidedown = trampoline::vector_slidedown; + static constexpr auto& vector_slide1up = trampoline::vector_slide1up; + static constexpr auto& vector_slide1down = trampoline::vector_slide1down; + static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; + static constexpr auto& vector_compress = trampoline::vector_compress; + static constexpr auto& vector_whole_move = trampoline::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; + static constexpr auto& vector_unary_op = trampoline::vector_unary_op; + vm_impl(); vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); @@ -359,8 +421,8 @@ template class vm_impl : public iss::asmjit::vm_base { return reinterpret_cast(vm_impl_ptr)->valid_reg_overlap(rs,rd,EMUL_pow_rs,EMUL_pow_rd); } uint8_t valid_reg_overlap(uint8_t rs, uint8_t rd, int8_t EMUL_pow_rs, int8_t EMUL_pow_rd){ - uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& (1ULL << 4) : 1; - uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& (1ULL << 4) : 1; + uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& ((1ULL << 5)-1) : 1; + uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& ((1ULL << 5)-1) : 1; if(EMUL_pow_rs < EMUL_pow_rd) { return (rs + rs_group <= rd) || (rs >= rd + rd_group) || ((rs + rs_group == rd + rd_group) & (EMUL_pow_rs >= 0)); } @@ -484,11 +546,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); return ! valid_vtype() || *vstart != 0; } - static uint8_t _illegal_reduction_widen(void* vm_impl_ptr , uint8_t EEW, int8_t EMUL_pow){ - return reinterpret_cast(vm_impl_ptr)->illegal_reduction_widen(EEW,EMUL_pow); + static uint8_t _illegal_reduction_widen(void* vm_impl_ptr , uint8_t EEW){ + return reinterpret_cast(vm_impl_ptr)->illegal_reduction_widen(EEW); } - uint8_t illegal_reduction_widen(uint8_t EEW, int8_t EMUL_pow){ - return illegal_reduction() || ! valid_eew_emul(EEW, EMUL_pow); + uint8_t illegal_reduction_widen(uint8_t EEW){ + return illegal_reduction() || ! (EEW >= 8 && EEW <= traits::ELEN); } static uint8_t _illegal_fp_reduction(void* vm_impl_ptr , uint8_t SEW, uint8_t rm){ return reinterpret_cast(vm_impl_ptr)->illegal_fp_reduction(SEW,rm); @@ -497,6 +559,12 @@ template class vm_impl : public iss::asmjit::vm_base { auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); return ! valid_vtype() || *vstart != 0 || ! valid_fp_op(SEW, rm); } + static uint8_t _illegal_fp_reduction_widen(void* vm_impl_ptr , uint8_t SEW, uint8_t rm, uint8_t EEW){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_reduction_widen(SEW,rm,EEW); + } + uint8_t illegal_fp_reduction_widen(uint8_t SEW, uint8_t rm, uint8_t EEW){ + return illegal_fp_reduction(SEW, rm) || ! (EEW >= 8 && EEW <= traits::ELEN); + } static uint8_t _illegal_fp_variable_width(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm, uint8_t SEW_new, int8_t LMUL_pow_new){ return reinterpret_cast(vm_impl_ptr)->illegal_fp_variable_width(vd,vm,SEW,rm,SEW_new,LMUL_pow_new); } @@ -11567,17 +11635,15 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_240 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_240, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto orig_ratio = gen_ext(cc, - (gen_operation(cc, sub, ret_val_get_sew_pow_239, ret_val_get_lmul_pow_240)), 5, true); + (gen_operation(cc, sub, ret_val_get_sew_pow_239, ret_val_get_lmul_pow_240)), 8, true); setArg(call_get_sew_pow_239, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_239, 0, ret_val_get_sew_pow_239); setArg(call_get_lmul_pow_240, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_240, 0, ret_val_get_lmul_pow_240); auto orig_vstart = load_reg_from_mem(jh, traits::vstart); - auto tmp241 = get_reg_Gp(cc, 8, false); - mov(cc, tmp241, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp241, 32, false) - , traits::vstart); + auto tmp241 = get_reg_Gp(cc, 32, false); + mov(cc, tmp241, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp241, traits::vstart); auto tmp242 = get_reg_Gp(cc, 32, false); mov(cc, tmp242, (uint32_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul)); write_reg_to_mem(jh, tmp242, traits::vtype); @@ -11641,9 +11707,7 @@ template class vm_impl : public iss::asmjit::vm_base { } else { if(rd!=0){ - write_reg_to_mem(jh, - gen_ext(cc, VLMAX, 32, false) - , traits::vl); + write_reg_to_mem(jh, gen_ext(cc, VLMAX, 32, false), traits::vl); mov(cc, get_ptr_for(jh, traits::X0+ rd), gen_ext(cc, VLMAX, 32, false)); @@ -11656,7 +11720,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_251 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_251, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto new_ratio = gen_ext(cc, - (gen_operation(cc, sub, ret_val_get_sew_pow_250, ret_val_get_lmul_pow_251)), 5, true); + (gen_operation(cc, sub, ret_val_get_sew_pow_250, ret_val_get_lmul_pow_251)), 8, true); setArg(call_get_sew_pow_250, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_250, 0, ret_val_get_sew_pow_250); setArg(call_get_lmul_pow_251, 0, reinterpret_cast(this)); @@ -11772,20 +11836,16 @@ template class vm_impl : public iss::asmjit::vm_base { auto calculate_new_vl_260_arg1 = VLMAX; x86::Gp ret_val_calculate_new_vl_260 = get_reg_Gp(cc, 16, false); cc.invoke(&call_calculate_new_vl_260, (uintptr_t)&vm_impl::_calculate_new_vl, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_calculate_new_vl_260, 32, false) - , traits::vl); + write_reg_to_mem(jh, gen_ext(cc, ret_val_calculate_new_vl_260, 32, false), traits::vl); setArg(call_calculate_new_vl_260, 0, reinterpret_cast(this)); setArg(call_calculate_new_vl_260, 1, uimm); setArg(call_calculate_new_vl_260, 2, calculate_new_vl_260_arg1); setRet(call_calculate_new_vl_260, 0, ret_val_calculate_new_vl_260); mov(cc, get_ptr_for(jh, traits::X0+ rd), load_reg_from_mem(jh, traits::vl)); - auto tmp261 = get_reg_Gp(cc, 8, false); - mov(cc, tmp261, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp261, 32, false) - , traits::vstart); + auto tmp261 = get_reg_Gp(cc, 32, false); + mov(cc, tmp261, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp261, traits::vstart); } cc.bind(label_merge); } @@ -11840,17 +11900,15 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_263 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_263, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto orig_ratio = gen_ext(cc, - (gen_operation(cc, sub, ret_val_get_sew_pow_262, ret_val_get_lmul_pow_263)), 5, true); + (gen_operation(cc, sub, ret_val_get_sew_pow_262, ret_val_get_lmul_pow_263)), 8, true); setArg(call_get_sew_pow_262, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_262, 0, ret_val_get_sew_pow_262); setArg(call_get_lmul_pow_263, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_263, 0, ret_val_get_lmul_pow_263); auto orig_vstart = load_reg_from_mem(jh, traits::vstart); - auto tmp264 = get_reg_Gp(cc, 8, false); - mov(cc, tmp264, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp264, 32, false) - , traits::vstart); + auto tmp264 = get_reg_Gp(cc, 32, false); + mov(cc, tmp264, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp264, traits::vstart); { auto label_merge = cc.newLabel(); auto cond = gen_slice(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 8, (static_cast(traits::XLEN)-2)-8+1); @@ -11922,9 +11980,7 @@ template class vm_impl : public iss::asmjit::vm_base { } else { if(rd!=0){ - write_reg_to_mem(jh, - gen_ext(cc, VLMAX, 32, false) - , traits::vl); + write_reg_to_mem(jh, gen_ext(cc, VLMAX, 32, false), traits::vl); mov(cc, get_ptr_for(jh, traits::X0+ rd), gen_ext(cc, VLMAX, 32, false)); @@ -11937,7 +11993,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_273 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_273, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto new_ratio = gen_ext(cc, - (gen_operation(cc, sub, ret_val_get_sew_pow_272, ret_val_get_lmul_pow_273)), 5, true); + (gen_operation(cc, sub, ret_val_get_sew_pow_272, ret_val_get_lmul_pow_273)), 8, true); setArg(call_get_sew_pow_272, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_272, 0, ret_val_get_sew_pow_272); setArg(call_get_lmul_pow_273, 0, reinterpret_cast(this)); @@ -12017,7 +12073,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_277 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_277, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_275, ret_val_get_sew_pow_276), ret_val_get_lmul_pow_277)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_275, ret_val_get_sew_pow_276), ret_val_get_lmul_pow_277)), 8, true); setArg(call_get_pow_275, 0, reinterpret_cast(this)); setArg(call_get_pow_275, 1, EEW); setRet(call_get_pow_275, 0, ret_val_get_pow_275); @@ -12061,7 +12117,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_279_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_279 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_279, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_279, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_279, 32, false), traits::vstart); setArg(call_vlseg_279, 0, reinterpret_cast(this->get_arch())); @@ -12137,7 +12193,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_282 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_282, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_280, ret_val_get_sew_pow_281), ret_val_get_lmul_pow_282)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_280, ret_val_get_sew_pow_281), ret_val_get_lmul_pow_282)), 8, true); setArg(call_get_pow_280, 0, reinterpret_cast(this)); setArg(call_get_pow_280, 1, EEW); setRet(call_get_pow_280, 0, ret_val_get_pow_280); @@ -12181,7 +12237,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_284_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_284 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_284, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_284, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_284, 32, false), traits::vstart); setArg(call_vlseg_284, 0, reinterpret_cast(this->get_arch())); @@ -12257,7 +12313,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_287 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_287, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_285, ret_val_get_sew_pow_286), ret_val_get_lmul_pow_287)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_285, ret_val_get_sew_pow_286), ret_val_get_lmul_pow_287)), 8, true); setArg(call_get_pow_285, 0, reinterpret_cast(this)); setArg(call_get_pow_285, 1, EEW); setRet(call_get_pow_285, 0, ret_val_get_pow_285); @@ -12301,7 +12357,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_289_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_289 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_289, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_289, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_289, 32, false), traits::vstart); setArg(call_vlseg_289, 0, reinterpret_cast(this->get_arch())); @@ -12377,7 +12433,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_292 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_292, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_290, ret_val_get_sew_pow_291), ret_val_get_lmul_pow_292)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_290, ret_val_get_sew_pow_291), ret_val_get_lmul_pow_292)), 8, true); setArg(call_get_pow_290, 0, reinterpret_cast(this)); setArg(call_get_pow_290, 1, EEW); setRet(call_get_pow_290, 0, ret_val_get_pow_290); @@ -12421,7 +12477,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_294_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_294 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_294, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_294, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_294, 32, false), traits::vstart); setArg(call_vlseg_294, 0, reinterpret_cast(this->get_arch())); @@ -12497,7 +12553,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_297 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_297, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_295, ret_val_get_sew_pow_296), ret_val_get_lmul_pow_297)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_295, ret_val_get_sew_pow_296), ret_val_get_lmul_pow_297)), 8, true); setArg(call_get_pow_295, 0, reinterpret_cast(this)); setArg(call_get_pow_295, 1, EEW); setRet(call_get_pow_295, 0, ret_val_get_pow_295); @@ -12541,7 +12597,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_299_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_299 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_299, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_299, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_299, 32, false), traits::vstart); setArg(call_vlseg_299, 0, reinterpret_cast(this->get_arch())); @@ -12617,7 +12673,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_302 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_302, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_300, ret_val_get_sew_pow_301), ret_val_get_lmul_pow_302)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_300, ret_val_get_sew_pow_301), ret_val_get_lmul_pow_302)), 8, true); setArg(call_get_pow_300, 0, reinterpret_cast(this)); setArg(call_get_pow_300, 1, EEW); setRet(call_get_pow_300, 0, ret_val_get_pow_300); @@ -12661,7 +12717,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_304_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_304 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_304, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_304, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_304, 32, false), traits::vstart); setArg(call_vlseg_304, 0, reinterpret_cast(this->get_arch())); @@ -12737,7 +12793,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_307 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_307, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_305, ret_val_get_sew_pow_306), ret_val_get_lmul_pow_307)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_305, ret_val_get_sew_pow_306), ret_val_get_lmul_pow_307)), 8, true); setArg(call_get_pow_305, 0, reinterpret_cast(this)); setArg(call_get_pow_305, 1, EEW); setRet(call_get_pow_305, 0, ret_val_get_pow_305); @@ -12781,7 +12837,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_309_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_309 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_309, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_309, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_309, 32, false), traits::vstart); setArg(call_vlseg_309, 0, reinterpret_cast(this->get_arch())); @@ -12857,7 +12913,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_312 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_312, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_310, ret_val_get_sew_pow_311), ret_val_get_lmul_pow_312)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_310, ret_val_get_sew_pow_311), ret_val_get_lmul_pow_312)), 8, true); setArg(call_get_pow_310, 0, reinterpret_cast(this)); setArg(call_get_pow_310, 1, EEW); setRet(call_get_pow_310, 0, ret_val_get_pow_310); @@ -12901,7 +12957,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_314_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_314 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_314, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_314, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_314, 32, false), traits::vstart); setArg(call_vlseg_314, 0, reinterpret_cast(this->get_arch())); @@ -12977,7 +13033,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_317 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_317, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_315, ret_val_get_sew_pow_316), ret_val_get_lmul_pow_317)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_315, ret_val_get_sew_pow_316), ret_val_get_lmul_pow_317)), 8, true); setArg(call_get_pow_315, 0, reinterpret_cast(this)); setArg(call_get_pow_315, 1, EEW); setRet(call_get_pow_315, 0, ret_val_get_pow_315); @@ -13021,7 +13077,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_319_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_319 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_319, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_319, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_319, 32, false), traits::vstart); setArg(call_vlseg_319, 0, reinterpret_cast(this->get_arch())); @@ -13097,7 +13153,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_322 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_322, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_320, ret_val_get_sew_pow_321), ret_val_get_lmul_pow_322)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_320, ret_val_get_sew_pow_321), ret_val_get_lmul_pow_322)), 8, true); setArg(call_get_pow_320, 0, reinterpret_cast(this)); setArg(call_get_pow_320, 1, EEW); setRet(call_get_pow_320, 0, ret_val_get_pow_320); @@ -13141,7 +13197,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_324_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_324 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_324, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_324, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_324, 32, false), traits::vstart); setArg(call_vlseg_324, 0, reinterpret_cast(this->get_arch())); @@ -13217,7 +13273,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_327 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_327, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_325, ret_val_get_sew_pow_326), ret_val_get_lmul_pow_327)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_325, ret_val_get_sew_pow_326), ret_val_get_lmul_pow_327)), 8, true); setArg(call_get_pow_325, 0, reinterpret_cast(this)); setArg(call_get_pow_325, 1, EEW); setRet(call_get_pow_325, 0, ret_val_get_pow_325); @@ -13261,7 +13317,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_329_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_329 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_329, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_329, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_329, 32, false), traits::vstart); setArg(call_vlseg_329, 0, reinterpret_cast(this->get_arch())); @@ -13337,7 +13393,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_332 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_332, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_330, ret_val_get_sew_pow_331), ret_val_get_lmul_pow_332)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_330, ret_val_get_sew_pow_331), ret_val_get_lmul_pow_332)), 8, true); setArg(call_get_pow_330, 0, reinterpret_cast(this)); setArg(call_get_pow_330, 1, EEW); setRet(call_get_pow_330, 0, ret_val_get_pow_330); @@ -13381,7 +13437,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_334_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_334 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_334, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_334, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_334, 32, false), traits::vstart); setArg(call_vlseg_334, 0, reinterpret_cast(this->get_arch())); @@ -13457,7 +13513,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_337 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_337, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_335, ret_val_get_sew_pow_336), ret_val_get_lmul_pow_337)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_335, ret_val_get_sew_pow_336), ret_val_get_lmul_pow_337)), 8, true); setArg(call_get_pow_335, 0, reinterpret_cast(this)); setArg(call_get_pow_335, 1, EEW); setRet(call_get_pow_335, 0, ret_val_get_pow_335); @@ -13501,7 +13557,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_339_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_339 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_339, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_339, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_339, 32, false), traits::vstart); setArg(call_vlseg_339, 0, reinterpret_cast(this->get_arch())); @@ -13577,7 +13633,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_342 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_342, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_340, ret_val_get_sew_pow_341), ret_val_get_lmul_pow_342)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_340, ret_val_get_sew_pow_341), ret_val_get_lmul_pow_342)), 8, true); setArg(call_get_pow_340, 0, reinterpret_cast(this)); setArg(call_get_pow_340, 1, EEW); setRet(call_get_pow_340, 0, ret_val_get_pow_340); @@ -13621,7 +13677,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_344_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_344 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_344, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_344, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_344, 32, false), traits::vstart); setArg(call_vlseg_344, 0, reinterpret_cast(this->get_arch())); @@ -13697,7 +13753,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_347 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_347, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_345, ret_val_get_sew_pow_346), ret_val_get_lmul_pow_347)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_345, ret_val_get_sew_pow_346), ret_val_get_lmul_pow_347)), 8, true); setArg(call_get_pow_345, 0, reinterpret_cast(this)); setArg(call_get_pow_345, 1, EEW); setRet(call_get_pow_345, 0, ret_val_get_pow_345); @@ -13741,7 +13797,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_349_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_349 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_349, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_349, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_349, 32, false), traits::vstart); setArg(call_vlseg_349, 0, reinterpret_cast(this->get_arch())); @@ -13817,7 +13873,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_352 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_352, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_350, ret_val_get_sew_pow_351), ret_val_get_lmul_pow_352)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_350, ret_val_get_sew_pow_351), ret_val_get_lmul_pow_352)), 8, true); setArg(call_get_pow_350, 0, reinterpret_cast(this)); setArg(call_get_pow_350, 1, EEW); setRet(call_get_pow_350, 0, ret_val_get_pow_350); @@ -13861,7 +13917,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_354_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_354 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_354, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_354, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_354, 32, false), traits::vstart); setArg(call_vlseg_354, 0, reinterpret_cast(this->get_arch())); @@ -13937,7 +13993,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_357 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_357, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_355, ret_val_get_sew_pow_356), ret_val_get_lmul_pow_357)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_355, ret_val_get_sew_pow_356), ret_val_get_lmul_pow_357)), 8, true); setArg(call_get_pow_355, 0, reinterpret_cast(this)); setArg(call_get_pow_355, 1, EEW); setRet(call_get_pow_355, 0, ret_val_get_pow_355); @@ -13981,7 +14037,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_359_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_359 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_359, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_359, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_359, 32, false), traits::vstart); setArg(call_vlseg_359, 0, reinterpret_cast(this->get_arch())); @@ -14057,7 +14113,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_362 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_362, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_360, ret_val_get_sew_pow_361), ret_val_get_lmul_pow_362)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_360, ret_val_get_sew_pow_361), ret_val_get_lmul_pow_362)), 8, true); setArg(call_get_pow_360, 0, reinterpret_cast(this)); setArg(call_get_pow_360, 1, EEW); setRet(call_get_pow_360, 0, ret_val_get_pow_360); @@ -14101,7 +14157,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_364_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_364 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_364, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_364, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_364, 32, false), traits::vstart); setArg(call_vlseg_364, 0, reinterpret_cast(this->get_arch())); @@ -14177,7 +14233,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_367 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_367, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_365, ret_val_get_sew_pow_366), ret_val_get_lmul_pow_367)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_365, ret_val_get_sew_pow_366), ret_val_get_lmul_pow_367)), 8, true); setArg(call_get_pow_365, 0, reinterpret_cast(this)); setArg(call_get_pow_365, 1, EEW); setRet(call_get_pow_365, 0, ret_val_get_pow_365); @@ -14221,7 +14277,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_369_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_369 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_369, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_369, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_369, 32, false), traits::vstart); setArg(call_vlseg_369, 0, reinterpret_cast(this->get_arch())); @@ -14297,7 +14353,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_372 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_372, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_370, ret_val_get_sew_pow_371), ret_val_get_lmul_pow_372)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_370, ret_val_get_sew_pow_371), ret_val_get_lmul_pow_372)), 8, true); setArg(call_get_pow_370, 0, reinterpret_cast(this)); setArg(call_get_pow_370, 1, EEW); setRet(call_get_pow_370, 0, ret_val_get_pow_370); @@ -14341,7 +14397,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_374_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_374 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_374, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_374, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_374, 32, false), traits::vstart); setArg(call_vlseg_374, 0, reinterpret_cast(this->get_arch())); @@ -14417,7 +14473,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_377 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_377, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_375, ret_val_get_sew_pow_376), ret_val_get_lmul_pow_377)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_375, ret_val_get_sew_pow_376), ret_val_get_lmul_pow_377)), 8, true); setArg(call_get_pow_375, 0, reinterpret_cast(this)); setArg(call_get_pow_375, 1, EEW); setRet(call_get_pow_375, 0, ret_val_get_pow_375); @@ -14461,7 +14517,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_379_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_379 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_379, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_379, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_379, 32, false), traits::vstart); setArg(call_vlseg_379, 0, reinterpret_cast(this->get_arch())); @@ -14537,7 +14593,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_382 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_382, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_380, ret_val_get_sew_pow_381), ret_val_get_lmul_pow_382)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_380, ret_val_get_sew_pow_381), ret_val_get_lmul_pow_382)), 8, true); setArg(call_get_pow_380, 0, reinterpret_cast(this)); setArg(call_get_pow_380, 1, EEW); setRet(call_get_pow_380, 0, ret_val_get_pow_380); @@ -14581,7 +14637,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_384_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_384 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_384, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_384, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_384, 32, false), traits::vstart); setArg(call_vlseg_384, 0, reinterpret_cast(this->get_arch())); @@ -14657,7 +14713,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_387 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_387, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_385, ret_val_get_sew_pow_386), ret_val_get_lmul_pow_387)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_385, ret_val_get_sew_pow_386), ret_val_get_lmul_pow_387)), 8, true); setArg(call_get_pow_385, 0, reinterpret_cast(this)); setArg(call_get_pow_385, 1, EEW); setRet(call_get_pow_385, 0, ret_val_get_pow_385); @@ -14701,7 +14757,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_389_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_389 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_389, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_389, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_389, 32, false), traits::vstart); setArg(call_vlseg_389, 0, reinterpret_cast(this->get_arch())); @@ -14777,7 +14833,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_392 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_392, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_390, ret_val_get_sew_pow_391), ret_val_get_lmul_pow_392)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_390, ret_val_get_sew_pow_391), ret_val_get_lmul_pow_392)), 8, true); setArg(call_get_pow_390, 0, reinterpret_cast(this)); setArg(call_get_pow_390, 1, EEW); setRet(call_get_pow_390, 0, ret_val_get_pow_390); @@ -14821,7 +14877,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_394_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_394 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_394, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_394, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_394, 32, false), traits::vstart); setArg(call_vlseg_394, 0, reinterpret_cast(this->get_arch())); @@ -14897,7 +14953,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_397 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_397, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_395, ret_val_get_sew_pow_396), ret_val_get_lmul_pow_397)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_395, ret_val_get_sew_pow_396), ret_val_get_lmul_pow_397)), 8, true); setArg(call_get_pow_395, 0, reinterpret_cast(this)); setArg(call_get_pow_395, 1, EEW); setRet(call_get_pow_395, 0, ret_val_get_pow_395); @@ -14941,7 +14997,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_399_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_399 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_399, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_399, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_399, 32, false), traits::vstart); setArg(call_vlseg_399, 0, reinterpret_cast(this->get_arch())); @@ -15017,7 +15073,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_402 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_402, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_400, ret_val_get_sew_pow_401), ret_val_get_lmul_pow_402)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_400, ret_val_get_sew_pow_401), ret_val_get_lmul_pow_402)), 8, true); setArg(call_get_pow_400, 0, reinterpret_cast(this)); setArg(call_get_pow_400, 1, EEW); setRet(call_get_pow_400, 0, ret_val_get_pow_400); @@ -15061,7 +15117,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_404_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_404 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_404, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_404, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_404, 32, false), traits::vstart); setArg(call_vlseg_404, 0, reinterpret_cast(this->get_arch())); @@ -15137,7 +15193,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_407 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_407, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_405, ret_val_get_sew_pow_406), ret_val_get_lmul_pow_407)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_405, ret_val_get_sew_pow_406), ret_val_get_lmul_pow_407)), 8, true); setArg(call_get_pow_405, 0, reinterpret_cast(this)); setArg(call_get_pow_405, 1, EEW); setRet(call_get_pow_405, 0, ret_val_get_pow_405); @@ -15181,7 +15237,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_409_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_409 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_409, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_409, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_409, 32, false), traits::vstart); setArg(call_vlseg_409, 0, reinterpret_cast(this->get_arch())); @@ -15257,7 +15313,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_412 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_412, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_410, ret_val_get_sew_pow_411), ret_val_get_lmul_pow_412)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_410, ret_val_get_sew_pow_411), ret_val_get_lmul_pow_412)), 8, true); setArg(call_get_pow_410, 0, reinterpret_cast(this)); setArg(call_get_pow_410, 1, EEW); setRet(call_get_pow_410, 0, ret_val_get_pow_410); @@ -15301,7 +15357,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_414_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_414 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_414, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_414, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_414, 32, false), traits::vstart); setArg(call_vlseg_414, 0, reinterpret_cast(this->get_arch())); @@ -15377,7 +15433,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_417 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_417, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_415, ret_val_get_sew_pow_416), ret_val_get_lmul_pow_417)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_415, ret_val_get_sew_pow_416), ret_val_get_lmul_pow_417)), 8, true); setArg(call_get_pow_415, 0, reinterpret_cast(this)); setArg(call_get_pow_415, 1, EEW); setRet(call_get_pow_415, 0, ret_val_get_pow_415); @@ -15421,7 +15477,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_419_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_419 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_419, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_419, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_419, 32, false), traits::vstart); setArg(call_vlseg_419, 0, reinterpret_cast(this->get_arch())); @@ -15497,7 +15553,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_422 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_422, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_420, ret_val_get_sew_pow_421), ret_val_get_lmul_pow_422)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_420, ret_val_get_sew_pow_421), ret_val_get_lmul_pow_422)), 8, true); setArg(call_get_pow_420, 0, reinterpret_cast(this)); setArg(call_get_pow_420, 1, EEW); setRet(call_get_pow_420, 0, ret_val_get_pow_420); @@ -15541,7 +15597,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_424_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_424 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_424, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_424, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_424, 32, false), traits::vstart); setArg(call_vlseg_424, 0, reinterpret_cast(this->get_arch())); @@ -15617,7 +15673,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_427 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_427, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_425, ret_val_get_sew_pow_426), ret_val_get_lmul_pow_427)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_425, ret_val_get_sew_pow_426), ret_val_get_lmul_pow_427)), 8, true); setArg(call_get_pow_425, 0, reinterpret_cast(this)); setArg(call_get_pow_425, 1, EEW); setRet(call_get_pow_425, 0, ret_val_get_pow_425); @@ -15661,7 +15717,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_429_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_429 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_429, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_429, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_429, 32, false), traits::vstart); setArg(call_vlseg_429, 0, reinterpret_cast(this->get_arch())); @@ -15737,7 +15793,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_432 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_432, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_430, ret_val_get_sew_pow_431), ret_val_get_lmul_pow_432)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_430, ret_val_get_sew_pow_431), ret_val_get_lmul_pow_432)), 8, true); setArg(call_get_pow_430, 0, reinterpret_cast(this)); setArg(call_get_pow_430, 1, EEW); setRet(call_get_pow_430, 0, ret_val_get_pow_430); @@ -15781,7 +15837,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_434_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_434 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_434, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_434, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_434, 32, false), traits::vstart); setArg(call_vlseg_434, 0, reinterpret_cast(this->get_arch())); @@ -15857,7 +15913,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_437 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_437, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_435, ret_val_get_sew_pow_436), ret_val_get_lmul_pow_437)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_435, ret_val_get_sew_pow_436), ret_val_get_lmul_pow_437)), 8, true); setArg(call_get_pow_435, 0, reinterpret_cast(this)); setArg(call_get_pow_435, 1, EEW); setRet(call_get_pow_435, 0, ret_val_get_pow_435); @@ -15899,7 +15955,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_439_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_439 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_439, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_439, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_439, 32, false), traits::vstart); setArg(call_vsseg_439, 0, reinterpret_cast(this->get_arch())); @@ -15975,7 +16031,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_442 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_442, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_440, ret_val_get_sew_pow_441), ret_val_get_lmul_pow_442)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_440, ret_val_get_sew_pow_441), ret_val_get_lmul_pow_442)), 8, true); setArg(call_get_pow_440, 0, reinterpret_cast(this)); setArg(call_get_pow_440, 1, EEW); setRet(call_get_pow_440, 0, ret_val_get_pow_440); @@ -16017,7 +16073,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_444_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_444 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_444, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_444, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_444, 32, false), traits::vstart); setArg(call_vsseg_444, 0, reinterpret_cast(this->get_arch())); @@ -16093,7 +16149,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_447 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_447, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_445, ret_val_get_sew_pow_446), ret_val_get_lmul_pow_447)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_445, ret_val_get_sew_pow_446), ret_val_get_lmul_pow_447)), 8, true); setArg(call_get_pow_445, 0, reinterpret_cast(this)); setArg(call_get_pow_445, 1, EEW); setRet(call_get_pow_445, 0, ret_val_get_pow_445); @@ -16135,7 +16191,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_449_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_449 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_449, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_449, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_449, 32, false), traits::vstart); setArg(call_vsseg_449, 0, reinterpret_cast(this->get_arch())); @@ -16211,7 +16267,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_452 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_452, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_450, ret_val_get_sew_pow_451), ret_val_get_lmul_pow_452)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_450, ret_val_get_sew_pow_451), ret_val_get_lmul_pow_452)), 8, true); setArg(call_get_pow_450, 0, reinterpret_cast(this)); setArg(call_get_pow_450, 1, EEW); setRet(call_get_pow_450, 0, ret_val_get_pow_450); @@ -16253,7 +16309,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_454_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_454 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_454, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_454, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_454, 32, false), traits::vstart); setArg(call_vsseg_454, 0, reinterpret_cast(this->get_arch())); @@ -16329,7 +16385,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_457 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_457, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_455, ret_val_get_sew_pow_456), ret_val_get_lmul_pow_457)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_455, ret_val_get_sew_pow_456), ret_val_get_lmul_pow_457)), 8, true); setArg(call_get_pow_455, 0, reinterpret_cast(this)); setArg(call_get_pow_455, 1, EEW); setRet(call_get_pow_455, 0, ret_val_get_pow_455); @@ -16371,7 +16427,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_459_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_459 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_459, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_459, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_459, 32, false), traits::vstart); setArg(call_vsseg_459, 0, reinterpret_cast(this->get_arch())); @@ -16447,7 +16503,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_462 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_462, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_460, ret_val_get_sew_pow_461), ret_val_get_lmul_pow_462)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_460, ret_val_get_sew_pow_461), ret_val_get_lmul_pow_462)), 8, true); setArg(call_get_pow_460, 0, reinterpret_cast(this)); setArg(call_get_pow_460, 1, EEW); setRet(call_get_pow_460, 0, ret_val_get_pow_460); @@ -16489,7 +16545,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_464_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_464 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_464, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_464, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_464, 32, false), traits::vstart); setArg(call_vsseg_464, 0, reinterpret_cast(this->get_arch())); @@ -16565,7 +16621,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_467 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_467, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_465, ret_val_get_sew_pow_466), ret_val_get_lmul_pow_467)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_465, ret_val_get_sew_pow_466), ret_val_get_lmul_pow_467)), 8, true); setArg(call_get_pow_465, 0, reinterpret_cast(this)); setArg(call_get_pow_465, 1, EEW); setRet(call_get_pow_465, 0, ret_val_get_pow_465); @@ -16607,7 +16663,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_469_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_469 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_469, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_469, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_469, 32, false), traits::vstart); setArg(call_vsseg_469, 0, reinterpret_cast(this->get_arch())); @@ -16683,7 +16739,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_472 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_472, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_470, ret_val_get_sew_pow_471), ret_val_get_lmul_pow_472)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_470, ret_val_get_sew_pow_471), ret_val_get_lmul_pow_472)), 8, true); setArg(call_get_pow_470, 0, reinterpret_cast(this)); setArg(call_get_pow_470, 1, EEW); setRet(call_get_pow_470, 0, ret_val_get_pow_470); @@ -16725,7 +16781,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_474_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_474 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_474, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_474, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_474, 32, false), traits::vstart); setArg(call_vsseg_474, 0, reinterpret_cast(this->get_arch())); @@ -16801,7 +16857,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_477 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_477, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_475, ret_val_get_sew_pow_476), ret_val_get_lmul_pow_477)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_475, ret_val_get_sew_pow_476), ret_val_get_lmul_pow_477)), 8, true); setArg(call_get_pow_475, 0, reinterpret_cast(this)); setArg(call_get_pow_475, 1, EEW); setRet(call_get_pow_475, 0, ret_val_get_pow_475); @@ -16843,7 +16899,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_479_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_479 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_479, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_479, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_479, 32, false), traits::vstart); setArg(call_vsseg_479, 0, reinterpret_cast(this->get_arch())); @@ -16919,7 +16975,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_482 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_482, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_480, ret_val_get_sew_pow_481), ret_val_get_lmul_pow_482)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_480, ret_val_get_sew_pow_481), ret_val_get_lmul_pow_482)), 8, true); setArg(call_get_pow_480, 0, reinterpret_cast(this)); setArg(call_get_pow_480, 1, EEW); setRet(call_get_pow_480, 0, ret_val_get_pow_480); @@ -16961,7 +17017,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_484_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_484 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_484, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_484, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_484, 32, false), traits::vstart); setArg(call_vsseg_484, 0, reinterpret_cast(this->get_arch())); @@ -17037,7 +17093,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_487 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_487, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_485, ret_val_get_sew_pow_486), ret_val_get_lmul_pow_487)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_485, ret_val_get_sew_pow_486), ret_val_get_lmul_pow_487)), 8, true); setArg(call_get_pow_485, 0, reinterpret_cast(this)); setArg(call_get_pow_485, 1, EEW); setRet(call_get_pow_485, 0, ret_val_get_pow_485); @@ -17079,7 +17135,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_489_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_489 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_489, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_489, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_489, 32, false), traits::vstart); setArg(call_vsseg_489, 0, reinterpret_cast(this->get_arch())); @@ -17155,7 +17211,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_492 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_492, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_490, ret_val_get_sew_pow_491), ret_val_get_lmul_pow_492)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_490, ret_val_get_sew_pow_491), ret_val_get_lmul_pow_492)), 8, true); setArg(call_get_pow_490, 0, reinterpret_cast(this)); setArg(call_get_pow_490, 1, EEW); setRet(call_get_pow_490, 0, ret_val_get_pow_490); @@ -17197,7 +17253,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_494_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_494 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_494, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_494, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_494, 32, false), traits::vstart); setArg(call_vsseg_494, 0, reinterpret_cast(this->get_arch())); @@ -17273,7 +17329,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_497 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_497, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_495, ret_val_get_sew_pow_496), ret_val_get_lmul_pow_497)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_495, ret_val_get_sew_pow_496), ret_val_get_lmul_pow_497)), 8, true); setArg(call_get_pow_495, 0, reinterpret_cast(this)); setArg(call_get_pow_495, 1, EEW); setRet(call_get_pow_495, 0, ret_val_get_pow_495); @@ -17315,7 +17371,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_499_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_499 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_499, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_499, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_499, 32, false), traits::vstart); setArg(call_vsseg_499, 0, reinterpret_cast(this->get_arch())); @@ -17391,7 +17447,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_502 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_502, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_500, ret_val_get_sew_pow_501), ret_val_get_lmul_pow_502)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_500, ret_val_get_sew_pow_501), ret_val_get_lmul_pow_502)), 8, true); setArg(call_get_pow_500, 0, reinterpret_cast(this)); setArg(call_get_pow_500, 1, EEW); setRet(call_get_pow_500, 0, ret_val_get_pow_500); @@ -17433,7 +17489,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_504_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_504 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_504, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_504, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_504, 32, false), traits::vstart); setArg(call_vsseg_504, 0, reinterpret_cast(this->get_arch())); @@ -17509,7 +17565,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_507 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_507, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_505, ret_val_get_sew_pow_506), ret_val_get_lmul_pow_507)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_505, ret_val_get_sew_pow_506), ret_val_get_lmul_pow_507)), 8, true); setArg(call_get_pow_505, 0, reinterpret_cast(this)); setArg(call_get_pow_505, 1, EEW); setRet(call_get_pow_505, 0, ret_val_get_pow_505); @@ -17551,7 +17607,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_509_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_509 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_509, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_509, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_509, 32, false), traits::vstart); setArg(call_vsseg_509, 0, reinterpret_cast(this->get_arch())); @@ -17627,7 +17683,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_512 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_512, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_510, ret_val_get_sew_pow_511), ret_val_get_lmul_pow_512)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_510, ret_val_get_sew_pow_511), ret_val_get_lmul_pow_512)), 8, true); setArg(call_get_pow_510, 0, reinterpret_cast(this)); setArg(call_get_pow_510, 1, EEW); setRet(call_get_pow_510, 0, ret_val_get_pow_510); @@ -17669,7 +17725,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_514_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_514 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_514, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_514, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_514, 32, false), traits::vstart); setArg(call_vsseg_514, 0, reinterpret_cast(this->get_arch())); @@ -17745,7 +17801,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_517 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_517, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_515, ret_val_get_sew_pow_516), ret_val_get_lmul_pow_517)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_515, ret_val_get_sew_pow_516), ret_val_get_lmul_pow_517)), 8, true); setArg(call_get_pow_515, 0, reinterpret_cast(this)); setArg(call_get_pow_515, 1, EEW); setRet(call_get_pow_515, 0, ret_val_get_pow_515); @@ -17787,7 +17843,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_519_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_519 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_519, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_519, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_519, 32, false), traits::vstart); setArg(call_vsseg_519, 0, reinterpret_cast(this->get_arch())); @@ -17863,7 +17919,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_522 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_522, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_520, ret_val_get_sew_pow_521), ret_val_get_lmul_pow_522)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_520, ret_val_get_sew_pow_521), ret_val_get_lmul_pow_522)), 8, true); setArg(call_get_pow_520, 0, reinterpret_cast(this)); setArg(call_get_pow_520, 1, EEW); setRet(call_get_pow_520, 0, ret_val_get_pow_520); @@ -17905,7 +17961,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_524_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_524 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_524, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_524, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_524, 32, false), traits::vstart); setArg(call_vsseg_524, 0, reinterpret_cast(this->get_arch())); @@ -17981,7 +18037,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_527 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_527, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_525, ret_val_get_sew_pow_526), ret_val_get_lmul_pow_527)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_525, ret_val_get_sew_pow_526), ret_val_get_lmul_pow_527)), 8, true); setArg(call_get_pow_525, 0, reinterpret_cast(this)); setArg(call_get_pow_525, 1, EEW); setRet(call_get_pow_525, 0, ret_val_get_pow_525); @@ -18023,7 +18079,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_529_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_529 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_529, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_529, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_529, 32, false), traits::vstart); setArg(call_vsseg_529, 0, reinterpret_cast(this->get_arch())); @@ -18099,7 +18155,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_532 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_532, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_530, ret_val_get_sew_pow_531), ret_val_get_lmul_pow_532)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_530, ret_val_get_sew_pow_531), ret_val_get_lmul_pow_532)), 8, true); setArg(call_get_pow_530, 0, reinterpret_cast(this)); setArg(call_get_pow_530, 1, EEW); setRet(call_get_pow_530, 0, ret_val_get_pow_530); @@ -18141,7 +18197,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_534_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_534 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_534, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_534, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_534, 32, false), traits::vstart); setArg(call_vsseg_534, 0, reinterpret_cast(this->get_arch())); @@ -18217,7 +18273,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_537 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_537, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_535, ret_val_get_sew_pow_536), ret_val_get_lmul_pow_537)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_535, ret_val_get_sew_pow_536), ret_val_get_lmul_pow_537)), 8, true); setArg(call_get_pow_535, 0, reinterpret_cast(this)); setArg(call_get_pow_535, 1, EEW); setRet(call_get_pow_535, 0, ret_val_get_pow_535); @@ -18259,7 +18315,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_539_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_539 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_539, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_539, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_539, 32, false), traits::vstart); setArg(call_vsseg_539, 0, reinterpret_cast(this->get_arch())); @@ -18335,7 +18391,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_542 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_542, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_540, ret_val_get_sew_pow_541), ret_val_get_lmul_pow_542)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_540, ret_val_get_sew_pow_541), ret_val_get_lmul_pow_542)), 8, true); setArg(call_get_pow_540, 0, reinterpret_cast(this)); setArg(call_get_pow_540, 1, EEW); setRet(call_get_pow_540, 0, ret_val_get_pow_540); @@ -18377,7 +18433,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_544_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_544 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_544, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_544, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_544, 32, false), traits::vstart); setArg(call_vsseg_544, 0, reinterpret_cast(this->get_arch())); @@ -18453,7 +18509,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_547 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_547, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_545, ret_val_get_sew_pow_546), ret_val_get_lmul_pow_547)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_545, ret_val_get_sew_pow_546), ret_val_get_lmul_pow_547)), 8, true); setArg(call_get_pow_545, 0, reinterpret_cast(this)); setArg(call_get_pow_545, 1, EEW); setRet(call_get_pow_545, 0, ret_val_get_pow_545); @@ -18495,7 +18551,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_549_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_549 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_549, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_549, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_549, 32, false), traits::vstart); setArg(call_vsseg_549, 0, reinterpret_cast(this->get_arch())); @@ -18571,7 +18627,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_552 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_552, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_550, ret_val_get_sew_pow_551), ret_val_get_lmul_pow_552)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_550, ret_val_get_sew_pow_551), ret_val_get_lmul_pow_552)), 8, true); setArg(call_get_pow_550, 0, reinterpret_cast(this)); setArg(call_get_pow_550, 1, EEW); setRet(call_get_pow_550, 0, ret_val_get_pow_550); @@ -18613,7 +18669,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_554_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_554 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_554, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_554, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_554, 32, false), traits::vstart); setArg(call_vsseg_554, 0, reinterpret_cast(this->get_arch())); @@ -18689,7 +18745,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_557 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_557, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_555, ret_val_get_sew_pow_556), ret_val_get_lmul_pow_557)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_555, ret_val_get_sew_pow_556), ret_val_get_lmul_pow_557)), 8, true); setArg(call_get_pow_555, 0, reinterpret_cast(this)); setArg(call_get_pow_555, 1, EEW); setRet(call_get_pow_555, 0, ret_val_get_pow_555); @@ -18731,7 +18787,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_559_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_559 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_559, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_559, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_559, 32, false), traits::vstart); setArg(call_vsseg_559, 0, reinterpret_cast(this->get_arch())); @@ -18807,7 +18863,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_562 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_562, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_560, ret_val_get_sew_pow_561), ret_val_get_lmul_pow_562)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_560, ret_val_get_sew_pow_561), ret_val_get_lmul_pow_562)), 8, true); setArg(call_get_pow_560, 0, reinterpret_cast(this)); setArg(call_get_pow_560, 1, EEW); setRet(call_get_pow_560, 0, ret_val_get_pow_560); @@ -18849,7 +18905,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_564_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_564 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_564, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_564, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_564, 32, false), traits::vstart); setArg(call_vsseg_564, 0, reinterpret_cast(this->get_arch())); @@ -18925,7 +18981,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_567 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_567, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_565, ret_val_get_sew_pow_566), ret_val_get_lmul_pow_567)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_565, ret_val_get_sew_pow_566), ret_val_get_lmul_pow_567)), 8, true); setArg(call_get_pow_565, 0, reinterpret_cast(this)); setArg(call_get_pow_565, 1, EEW); setRet(call_get_pow_565, 0, ret_val_get_pow_565); @@ -18967,7 +19023,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_569_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_569 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_569, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_569, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_569, 32, false), traits::vstart); setArg(call_vsseg_569, 0, reinterpret_cast(this->get_arch())); @@ -19043,7 +19099,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_572 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_572, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_570, ret_val_get_sew_pow_571), ret_val_get_lmul_pow_572)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_570, ret_val_get_sew_pow_571), ret_val_get_lmul_pow_572)), 8, true); setArg(call_get_pow_570, 0, reinterpret_cast(this)); setArg(call_get_pow_570, 1, EEW); setRet(call_get_pow_570, 0, ret_val_get_pow_570); @@ -19085,7 +19141,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_574_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_574 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_574, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_574, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_574, 32, false), traits::vstart); setArg(call_vsseg_574, 0, reinterpret_cast(this->get_arch())); @@ -19161,7 +19217,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_577 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_577, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_575, ret_val_get_sew_pow_576), ret_val_get_lmul_pow_577)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_575, ret_val_get_sew_pow_576), ret_val_get_lmul_pow_577)), 8, true); setArg(call_get_pow_575, 0, reinterpret_cast(this)); setArg(call_get_pow_575, 1, EEW); setRet(call_get_pow_575, 0, ret_val_get_pow_575); @@ -19203,7 +19259,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_579_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_579 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_579, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_579, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_579, 32, false), traits::vstart); setArg(call_vsseg_579, 0, reinterpret_cast(this->get_arch())); @@ -19279,7 +19335,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_582 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_582, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_580, ret_val_get_sew_pow_581), ret_val_get_lmul_pow_582)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_580, ret_val_get_sew_pow_581), ret_val_get_lmul_pow_582)), 8, true); setArg(call_get_pow_580, 0, reinterpret_cast(this)); setArg(call_get_pow_580, 1, EEW); setRet(call_get_pow_580, 0, ret_val_get_pow_580); @@ -19321,7 +19377,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_584_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_584 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_584, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_584, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_584, 32, false), traits::vstart); setArg(call_vsseg_584, 0, reinterpret_cast(this->get_arch())); @@ -19397,7 +19453,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_587 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_587, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_585, ret_val_get_sew_pow_586), ret_val_get_lmul_pow_587)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_585, ret_val_get_sew_pow_586), ret_val_get_lmul_pow_587)), 8, true); setArg(call_get_pow_585, 0, reinterpret_cast(this)); setArg(call_get_pow_585, 1, EEW); setRet(call_get_pow_585, 0, ret_val_get_pow_585); @@ -19439,7 +19495,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_589_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_589 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_589, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_589, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_589, 32, false), traits::vstart); setArg(call_vsseg_589, 0, reinterpret_cast(this->get_arch())); @@ -19515,7 +19571,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_592 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_592, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_590, ret_val_get_sew_pow_591), ret_val_get_lmul_pow_592)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_590, ret_val_get_sew_pow_591), ret_val_get_lmul_pow_592)), 8, true); setArg(call_get_pow_590, 0, reinterpret_cast(this)); setArg(call_get_pow_590, 1, EEW); setRet(call_get_pow_590, 0, ret_val_get_pow_590); @@ -19557,7 +19613,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_594_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_594 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_594, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_594, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_594, 32, false), traits::vstart); setArg(call_vsseg_594, 0, reinterpret_cast(this->get_arch())); @@ -19634,7 +19690,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_597 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_597, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_595, ret_val_get_sew_pow_596), ret_val_get_lmul_pow_597)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_595, ret_val_get_sew_pow_596), ret_val_get_lmul_pow_597)), 8, true); setArg(call_get_pow_595, 0, reinterpret_cast(this)); setArg(call_get_pow_595, 1, EEW); setRet(call_get_pow_595, 0, ret_val_get_pow_595); @@ -19679,7 +19735,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_599_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_599 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_599, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_599, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_599, 32, false), traits::vstart); setArg(call_vlsseg_599, 0, reinterpret_cast(this->get_arch())); @@ -19757,7 +19813,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_602 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_602, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_600, ret_val_get_sew_pow_601), ret_val_get_lmul_pow_602)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_600, ret_val_get_sew_pow_601), ret_val_get_lmul_pow_602)), 8, true); setArg(call_get_pow_600, 0, reinterpret_cast(this)); setArg(call_get_pow_600, 1, EEW); setRet(call_get_pow_600, 0, ret_val_get_pow_600); @@ -19802,7 +19858,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_604_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_604 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_604, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_604, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_604, 32, false), traits::vstart); setArg(call_vlsseg_604, 0, reinterpret_cast(this->get_arch())); @@ -19880,7 +19936,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_607 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_607, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_605, ret_val_get_sew_pow_606), ret_val_get_lmul_pow_607)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_605, ret_val_get_sew_pow_606), ret_val_get_lmul_pow_607)), 8, true); setArg(call_get_pow_605, 0, reinterpret_cast(this)); setArg(call_get_pow_605, 1, EEW); setRet(call_get_pow_605, 0, ret_val_get_pow_605); @@ -19925,7 +19981,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_609_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_609 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_609, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_609, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_609, 32, false), traits::vstart); setArg(call_vlsseg_609, 0, reinterpret_cast(this->get_arch())); @@ -20003,7 +20059,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_612 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_612, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_610, ret_val_get_sew_pow_611), ret_val_get_lmul_pow_612)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_610, ret_val_get_sew_pow_611), ret_val_get_lmul_pow_612)), 8, true); setArg(call_get_pow_610, 0, reinterpret_cast(this)); setArg(call_get_pow_610, 1, EEW); setRet(call_get_pow_610, 0, ret_val_get_pow_610); @@ -20048,7 +20104,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_614_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_614 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_614, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_614, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_614, 32, false), traits::vstart); setArg(call_vlsseg_614, 0, reinterpret_cast(this->get_arch())); @@ -20126,7 +20182,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_617 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_617, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_615, ret_val_get_sew_pow_616), ret_val_get_lmul_pow_617)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_615, ret_val_get_sew_pow_616), ret_val_get_lmul_pow_617)), 8, true); setArg(call_get_pow_615, 0, reinterpret_cast(this)); setArg(call_get_pow_615, 1, EEW); setRet(call_get_pow_615, 0, ret_val_get_pow_615); @@ -20171,7 +20227,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_619_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_619 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_619, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_619, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_619, 32, false), traits::vstart); setArg(call_vlsseg_619, 0, reinterpret_cast(this->get_arch())); @@ -20249,7 +20305,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_622 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_622, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_620, ret_val_get_sew_pow_621), ret_val_get_lmul_pow_622)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_620, ret_val_get_sew_pow_621), ret_val_get_lmul_pow_622)), 8, true); setArg(call_get_pow_620, 0, reinterpret_cast(this)); setArg(call_get_pow_620, 1, EEW); setRet(call_get_pow_620, 0, ret_val_get_pow_620); @@ -20294,7 +20350,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_624_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_624 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_624, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_624, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_624, 32, false), traits::vstart); setArg(call_vlsseg_624, 0, reinterpret_cast(this->get_arch())); @@ -20372,7 +20428,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_627 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_627, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_625, ret_val_get_sew_pow_626), ret_val_get_lmul_pow_627)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_625, ret_val_get_sew_pow_626), ret_val_get_lmul_pow_627)), 8, true); setArg(call_get_pow_625, 0, reinterpret_cast(this)); setArg(call_get_pow_625, 1, EEW); setRet(call_get_pow_625, 0, ret_val_get_pow_625); @@ -20417,7 +20473,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_629_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_629 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_629, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_629, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_629, 32, false), traits::vstart); setArg(call_vlsseg_629, 0, reinterpret_cast(this->get_arch())); @@ -20495,7 +20551,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_632 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_632, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_630, ret_val_get_sew_pow_631), ret_val_get_lmul_pow_632)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_630, ret_val_get_sew_pow_631), ret_val_get_lmul_pow_632)), 8, true); setArg(call_get_pow_630, 0, reinterpret_cast(this)); setArg(call_get_pow_630, 1, EEW); setRet(call_get_pow_630, 0, ret_val_get_pow_630); @@ -20540,7 +20596,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_634_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_634 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_634, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_634, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_634, 32, false), traits::vstart); setArg(call_vlsseg_634, 0, reinterpret_cast(this->get_arch())); @@ -20618,7 +20674,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_637 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_637, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_635, ret_val_get_sew_pow_636), ret_val_get_lmul_pow_637)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_635, ret_val_get_sew_pow_636), ret_val_get_lmul_pow_637)), 8, true); setArg(call_get_pow_635, 0, reinterpret_cast(this)); setArg(call_get_pow_635, 1, EEW); setRet(call_get_pow_635, 0, ret_val_get_pow_635); @@ -20663,7 +20719,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_639_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_639 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_639, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_639, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_639, 32, false), traits::vstart); setArg(call_vlsseg_639, 0, reinterpret_cast(this->get_arch())); @@ -20741,7 +20797,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_642 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_642, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_640, ret_val_get_sew_pow_641), ret_val_get_lmul_pow_642)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_640, ret_val_get_sew_pow_641), ret_val_get_lmul_pow_642)), 8, true); setArg(call_get_pow_640, 0, reinterpret_cast(this)); setArg(call_get_pow_640, 1, EEW); setRet(call_get_pow_640, 0, ret_val_get_pow_640); @@ -20786,7 +20842,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_644_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_644 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_644, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_644, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_644, 32, false), traits::vstart); setArg(call_vlsseg_644, 0, reinterpret_cast(this->get_arch())); @@ -20864,7 +20920,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_647 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_647, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_645, ret_val_get_sew_pow_646), ret_val_get_lmul_pow_647)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_645, ret_val_get_sew_pow_646), ret_val_get_lmul_pow_647)), 8, true); setArg(call_get_pow_645, 0, reinterpret_cast(this)); setArg(call_get_pow_645, 1, EEW); setRet(call_get_pow_645, 0, ret_val_get_pow_645); @@ -20909,7 +20965,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_649_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_649 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_649, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_649, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_649, 32, false), traits::vstart); setArg(call_vlsseg_649, 0, reinterpret_cast(this->get_arch())); @@ -20987,7 +21043,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_652 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_652, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_650, ret_val_get_sew_pow_651), ret_val_get_lmul_pow_652)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_650, ret_val_get_sew_pow_651), ret_val_get_lmul_pow_652)), 8, true); setArg(call_get_pow_650, 0, reinterpret_cast(this)); setArg(call_get_pow_650, 1, EEW); setRet(call_get_pow_650, 0, ret_val_get_pow_650); @@ -21032,7 +21088,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_654_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_654 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_654, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_654, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_654, 32, false), traits::vstart); setArg(call_vlsseg_654, 0, reinterpret_cast(this->get_arch())); @@ -21110,7 +21166,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_657 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_657, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_655, ret_val_get_sew_pow_656), ret_val_get_lmul_pow_657)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_655, ret_val_get_sew_pow_656), ret_val_get_lmul_pow_657)), 8, true); setArg(call_get_pow_655, 0, reinterpret_cast(this)); setArg(call_get_pow_655, 1, EEW); setRet(call_get_pow_655, 0, ret_val_get_pow_655); @@ -21155,7 +21211,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_659_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_659 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_659, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_659, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_659, 32, false), traits::vstart); setArg(call_vlsseg_659, 0, reinterpret_cast(this->get_arch())); @@ -21233,7 +21289,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_662 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_662, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_660, ret_val_get_sew_pow_661), ret_val_get_lmul_pow_662)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_660, ret_val_get_sew_pow_661), ret_val_get_lmul_pow_662)), 8, true); setArg(call_get_pow_660, 0, reinterpret_cast(this)); setArg(call_get_pow_660, 1, EEW); setRet(call_get_pow_660, 0, ret_val_get_pow_660); @@ -21278,7 +21334,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_664_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_664 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_664, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_664, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_664, 32, false), traits::vstart); setArg(call_vlsseg_664, 0, reinterpret_cast(this->get_arch())); @@ -21356,7 +21412,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_667 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_667, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_665, ret_val_get_sew_pow_666), ret_val_get_lmul_pow_667)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_665, ret_val_get_sew_pow_666), ret_val_get_lmul_pow_667)), 8, true); setArg(call_get_pow_665, 0, reinterpret_cast(this)); setArg(call_get_pow_665, 1, EEW); setRet(call_get_pow_665, 0, ret_val_get_pow_665); @@ -21401,7 +21457,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_669_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_669 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_669, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_669, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_669, 32, false), traits::vstart); setArg(call_vlsseg_669, 0, reinterpret_cast(this->get_arch())); @@ -21479,7 +21535,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_672 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_672, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_670, ret_val_get_sew_pow_671), ret_val_get_lmul_pow_672)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_670, ret_val_get_sew_pow_671), ret_val_get_lmul_pow_672)), 8, true); setArg(call_get_pow_670, 0, reinterpret_cast(this)); setArg(call_get_pow_670, 1, EEW); setRet(call_get_pow_670, 0, ret_val_get_pow_670); @@ -21524,7 +21580,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_674_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_674 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_674, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_674, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_674, 32, false), traits::vstart); setArg(call_vlsseg_674, 0, reinterpret_cast(this->get_arch())); @@ -21602,7 +21658,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_677 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_677, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_675, ret_val_get_sew_pow_676), ret_val_get_lmul_pow_677)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_675, ret_val_get_sew_pow_676), ret_val_get_lmul_pow_677)), 8, true); setArg(call_get_pow_675, 0, reinterpret_cast(this)); setArg(call_get_pow_675, 1, EEW); setRet(call_get_pow_675, 0, ret_val_get_pow_675); @@ -21647,7 +21703,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_679_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_679 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_679, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_679, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_679, 32, false), traits::vstart); setArg(call_vlsseg_679, 0, reinterpret_cast(this->get_arch())); @@ -21725,7 +21781,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_682 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_682, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_680, ret_val_get_sew_pow_681), ret_val_get_lmul_pow_682)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_680, ret_val_get_sew_pow_681), ret_val_get_lmul_pow_682)), 8, true); setArg(call_get_pow_680, 0, reinterpret_cast(this)); setArg(call_get_pow_680, 1, EEW); setRet(call_get_pow_680, 0, ret_val_get_pow_680); @@ -21770,7 +21826,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_684_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_684 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_684, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_684, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_684, 32, false), traits::vstart); setArg(call_vlsseg_684, 0, reinterpret_cast(this->get_arch())); @@ -21848,7 +21904,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_687 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_687, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_685, ret_val_get_sew_pow_686), ret_val_get_lmul_pow_687)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_685, ret_val_get_sew_pow_686), ret_val_get_lmul_pow_687)), 8, true); setArg(call_get_pow_685, 0, reinterpret_cast(this)); setArg(call_get_pow_685, 1, EEW); setRet(call_get_pow_685, 0, ret_val_get_pow_685); @@ -21893,7 +21949,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_689_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_689 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_689, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_689, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_689, 32, false), traits::vstart); setArg(call_vlsseg_689, 0, reinterpret_cast(this->get_arch())); @@ -21971,7 +22027,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_692 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_692, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_690, ret_val_get_sew_pow_691), ret_val_get_lmul_pow_692)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_690, ret_val_get_sew_pow_691), ret_val_get_lmul_pow_692)), 8, true); setArg(call_get_pow_690, 0, reinterpret_cast(this)); setArg(call_get_pow_690, 1, EEW); setRet(call_get_pow_690, 0, ret_val_get_pow_690); @@ -22016,7 +22072,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_694_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_694 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_694, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_694, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_694, 32, false), traits::vstart); setArg(call_vlsseg_694, 0, reinterpret_cast(this->get_arch())); @@ -22094,7 +22150,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_697 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_697, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_695, ret_val_get_sew_pow_696), ret_val_get_lmul_pow_697)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_695, ret_val_get_sew_pow_696), ret_val_get_lmul_pow_697)), 8, true); setArg(call_get_pow_695, 0, reinterpret_cast(this)); setArg(call_get_pow_695, 1, EEW); setRet(call_get_pow_695, 0, ret_val_get_pow_695); @@ -22139,7 +22195,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_699_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_699 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_699, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_699, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_699, 32, false), traits::vstart); setArg(call_vlsseg_699, 0, reinterpret_cast(this->get_arch())); @@ -22217,7 +22273,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_702 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_702, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_700, ret_val_get_sew_pow_701), ret_val_get_lmul_pow_702)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_700, ret_val_get_sew_pow_701), ret_val_get_lmul_pow_702)), 8, true); setArg(call_get_pow_700, 0, reinterpret_cast(this)); setArg(call_get_pow_700, 1, EEW); setRet(call_get_pow_700, 0, ret_val_get_pow_700); @@ -22262,7 +22318,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_704_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_704 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_704, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_704, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_704, 32, false), traits::vstart); setArg(call_vlsseg_704, 0, reinterpret_cast(this->get_arch())); @@ -22340,7 +22396,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_707 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_707, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_705, ret_val_get_sew_pow_706), ret_val_get_lmul_pow_707)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_705, ret_val_get_sew_pow_706), ret_val_get_lmul_pow_707)), 8, true); setArg(call_get_pow_705, 0, reinterpret_cast(this)); setArg(call_get_pow_705, 1, EEW); setRet(call_get_pow_705, 0, ret_val_get_pow_705); @@ -22385,7 +22441,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_709_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_709 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_709, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_709, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_709, 32, false), traits::vstart); setArg(call_vlsseg_709, 0, reinterpret_cast(this->get_arch())); @@ -22463,7 +22519,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_712 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_712, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_710, ret_val_get_sew_pow_711), ret_val_get_lmul_pow_712)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_710, ret_val_get_sew_pow_711), ret_val_get_lmul_pow_712)), 8, true); setArg(call_get_pow_710, 0, reinterpret_cast(this)); setArg(call_get_pow_710, 1, EEW); setRet(call_get_pow_710, 0, ret_val_get_pow_710); @@ -22508,7 +22564,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_714_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_714 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_714, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_714, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_714, 32, false), traits::vstart); setArg(call_vlsseg_714, 0, reinterpret_cast(this->get_arch())); @@ -22586,7 +22642,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_717 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_717, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_715, ret_val_get_sew_pow_716), ret_val_get_lmul_pow_717)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_715, ret_val_get_sew_pow_716), ret_val_get_lmul_pow_717)), 8, true); setArg(call_get_pow_715, 0, reinterpret_cast(this)); setArg(call_get_pow_715, 1, EEW); setRet(call_get_pow_715, 0, ret_val_get_pow_715); @@ -22631,7 +22687,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_719_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_719 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_719, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_719, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_719, 32, false), traits::vstart); setArg(call_vlsseg_719, 0, reinterpret_cast(this->get_arch())); @@ -22709,7 +22765,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_722 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_722, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_720, ret_val_get_sew_pow_721), ret_val_get_lmul_pow_722)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_720, ret_val_get_sew_pow_721), ret_val_get_lmul_pow_722)), 8, true); setArg(call_get_pow_720, 0, reinterpret_cast(this)); setArg(call_get_pow_720, 1, EEW); setRet(call_get_pow_720, 0, ret_val_get_pow_720); @@ -22754,7 +22810,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_724_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_724 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_724, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_724, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_724, 32, false), traits::vstart); setArg(call_vlsseg_724, 0, reinterpret_cast(this->get_arch())); @@ -22832,7 +22888,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_727 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_727, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_725, ret_val_get_sew_pow_726), ret_val_get_lmul_pow_727)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_725, ret_val_get_sew_pow_726), ret_val_get_lmul_pow_727)), 8, true); setArg(call_get_pow_725, 0, reinterpret_cast(this)); setArg(call_get_pow_725, 1, EEW); setRet(call_get_pow_725, 0, ret_val_get_pow_725); @@ -22877,7 +22933,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_729_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_729 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_729, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_729, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_729, 32, false), traits::vstart); setArg(call_vlsseg_729, 0, reinterpret_cast(this->get_arch())); @@ -22955,7 +23011,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_732 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_732, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_730, ret_val_get_sew_pow_731), ret_val_get_lmul_pow_732)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_730, ret_val_get_sew_pow_731), ret_val_get_lmul_pow_732)), 8, true); setArg(call_get_pow_730, 0, reinterpret_cast(this)); setArg(call_get_pow_730, 1, EEW); setRet(call_get_pow_730, 0, ret_val_get_pow_730); @@ -23000,7 +23056,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_734_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_734 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_734, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_734, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_734, 32, false), traits::vstart); setArg(call_vlsseg_734, 0, reinterpret_cast(this->get_arch())); @@ -23078,7 +23134,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_737 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_737, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_735, ret_val_get_sew_pow_736), ret_val_get_lmul_pow_737)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_735, ret_val_get_sew_pow_736), ret_val_get_lmul_pow_737)), 8, true); setArg(call_get_pow_735, 0, reinterpret_cast(this)); setArg(call_get_pow_735, 1, EEW); setRet(call_get_pow_735, 0, ret_val_get_pow_735); @@ -23123,7 +23179,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_739_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_739 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_739, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_739, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_739, 32, false), traits::vstart); setArg(call_vlsseg_739, 0, reinterpret_cast(this->get_arch())); @@ -23201,7 +23257,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_742 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_742, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_740, ret_val_get_sew_pow_741), ret_val_get_lmul_pow_742)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_740, ret_val_get_sew_pow_741), ret_val_get_lmul_pow_742)), 8, true); setArg(call_get_pow_740, 0, reinterpret_cast(this)); setArg(call_get_pow_740, 1, EEW); setRet(call_get_pow_740, 0, ret_val_get_pow_740); @@ -23246,7 +23302,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_744_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_744 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_744, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_744, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_744, 32, false), traits::vstart); setArg(call_vlsseg_744, 0, reinterpret_cast(this->get_arch())); @@ -23324,7 +23380,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_747 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_747, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_745, ret_val_get_sew_pow_746), ret_val_get_lmul_pow_747)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_745, ret_val_get_sew_pow_746), ret_val_get_lmul_pow_747)), 8, true); setArg(call_get_pow_745, 0, reinterpret_cast(this)); setArg(call_get_pow_745, 1, EEW); setRet(call_get_pow_745, 0, ret_val_get_pow_745); @@ -23369,7 +23425,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_749_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_749 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_749, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_749, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_749, 32, false), traits::vstart); setArg(call_vlsseg_749, 0, reinterpret_cast(this->get_arch())); @@ -23447,7 +23503,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_752 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_752, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_750, ret_val_get_sew_pow_751), ret_val_get_lmul_pow_752)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_750, ret_val_get_sew_pow_751), ret_val_get_lmul_pow_752)), 8, true); setArg(call_get_pow_750, 0, reinterpret_cast(this)); setArg(call_get_pow_750, 1, EEW); setRet(call_get_pow_750, 0, ret_val_get_pow_750); @@ -23492,7 +23548,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlsseg_754_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlsseg_754 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlsseg_754, &vlsseg, FuncSignature::build()); + cc.invoke(&call_vlsseg_754, &vlsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlsseg_754, 32, false), traits::vstart); setArg(call_vlsseg_754, 0, reinterpret_cast(this->get_arch())); @@ -23570,7 +23626,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_757 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_757, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_755, ret_val_get_sew_pow_756), ret_val_get_lmul_pow_757)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_755, ret_val_get_sew_pow_756), ret_val_get_lmul_pow_757)), 8, true); setArg(call_get_pow_755, 0, reinterpret_cast(this)); setArg(call_get_pow_755, 1, EEW); setRet(call_get_pow_755, 0, ret_val_get_pow_755); @@ -23613,7 +23669,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_759_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_759 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_759, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_759, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_759, 32, false), traits::vstart); setArg(call_vssseg_759, 0, reinterpret_cast(this->get_arch())); @@ -23691,7 +23747,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_762 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_762, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_760, ret_val_get_sew_pow_761), ret_val_get_lmul_pow_762)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_760, ret_val_get_sew_pow_761), ret_val_get_lmul_pow_762)), 8, true); setArg(call_get_pow_760, 0, reinterpret_cast(this)); setArg(call_get_pow_760, 1, EEW); setRet(call_get_pow_760, 0, ret_val_get_pow_760); @@ -23734,7 +23790,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_764_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_764 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_764, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_764, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_764, 32, false), traits::vstart); setArg(call_vssseg_764, 0, reinterpret_cast(this->get_arch())); @@ -23812,7 +23868,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_767 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_767, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_765, ret_val_get_sew_pow_766), ret_val_get_lmul_pow_767)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_765, ret_val_get_sew_pow_766), ret_val_get_lmul_pow_767)), 8, true); setArg(call_get_pow_765, 0, reinterpret_cast(this)); setArg(call_get_pow_765, 1, EEW); setRet(call_get_pow_765, 0, ret_val_get_pow_765); @@ -23855,7 +23911,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_769_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_769 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_769, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_769, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_769, 32, false), traits::vstart); setArg(call_vssseg_769, 0, reinterpret_cast(this->get_arch())); @@ -23933,7 +23989,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_772 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_772, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_770, ret_val_get_sew_pow_771), ret_val_get_lmul_pow_772)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_770, ret_val_get_sew_pow_771), ret_val_get_lmul_pow_772)), 8, true); setArg(call_get_pow_770, 0, reinterpret_cast(this)); setArg(call_get_pow_770, 1, EEW); setRet(call_get_pow_770, 0, ret_val_get_pow_770); @@ -23976,7 +24032,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_774_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_774 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_774, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_774, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_774, 32, false), traits::vstart); setArg(call_vssseg_774, 0, reinterpret_cast(this->get_arch())); @@ -24054,7 +24110,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_777 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_777, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_775, ret_val_get_sew_pow_776), ret_val_get_lmul_pow_777)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_775, ret_val_get_sew_pow_776), ret_val_get_lmul_pow_777)), 8, true); setArg(call_get_pow_775, 0, reinterpret_cast(this)); setArg(call_get_pow_775, 1, EEW); setRet(call_get_pow_775, 0, ret_val_get_pow_775); @@ -24097,7 +24153,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_779_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_779 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_779, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_779, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_779, 32, false), traits::vstart); setArg(call_vssseg_779, 0, reinterpret_cast(this->get_arch())); @@ -24175,7 +24231,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_782 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_782, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_780, ret_val_get_sew_pow_781), ret_val_get_lmul_pow_782)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_780, ret_val_get_sew_pow_781), ret_val_get_lmul_pow_782)), 8, true); setArg(call_get_pow_780, 0, reinterpret_cast(this)); setArg(call_get_pow_780, 1, EEW); setRet(call_get_pow_780, 0, ret_val_get_pow_780); @@ -24218,7 +24274,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_784_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_784 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_784, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_784, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_784, 32, false), traits::vstart); setArg(call_vssseg_784, 0, reinterpret_cast(this->get_arch())); @@ -24296,7 +24352,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_787 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_787, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_785, ret_val_get_sew_pow_786), ret_val_get_lmul_pow_787)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_785, ret_val_get_sew_pow_786), ret_val_get_lmul_pow_787)), 8, true); setArg(call_get_pow_785, 0, reinterpret_cast(this)); setArg(call_get_pow_785, 1, EEW); setRet(call_get_pow_785, 0, ret_val_get_pow_785); @@ -24339,7 +24395,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_789_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_789 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_789, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_789, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_789, 32, false), traits::vstart); setArg(call_vssseg_789, 0, reinterpret_cast(this->get_arch())); @@ -24417,7 +24473,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_792 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_792, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_790, ret_val_get_sew_pow_791), ret_val_get_lmul_pow_792)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_790, ret_val_get_sew_pow_791), ret_val_get_lmul_pow_792)), 8, true); setArg(call_get_pow_790, 0, reinterpret_cast(this)); setArg(call_get_pow_790, 1, EEW); setRet(call_get_pow_790, 0, ret_val_get_pow_790); @@ -24460,7 +24516,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_794_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_794 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_794, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_794, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_794, 32, false), traits::vstart); setArg(call_vssseg_794, 0, reinterpret_cast(this->get_arch())); @@ -24538,7 +24594,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_797 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_797, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_795, ret_val_get_sew_pow_796), ret_val_get_lmul_pow_797)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_795, ret_val_get_sew_pow_796), ret_val_get_lmul_pow_797)), 8, true); setArg(call_get_pow_795, 0, reinterpret_cast(this)); setArg(call_get_pow_795, 1, EEW); setRet(call_get_pow_795, 0, ret_val_get_pow_795); @@ -24581,7 +24637,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_799_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_799 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_799, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_799, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_799, 32, false), traits::vstart); setArg(call_vssseg_799, 0, reinterpret_cast(this->get_arch())); @@ -24659,7 +24715,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_802 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_802, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_800, ret_val_get_sew_pow_801), ret_val_get_lmul_pow_802)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_800, ret_val_get_sew_pow_801), ret_val_get_lmul_pow_802)), 8, true); setArg(call_get_pow_800, 0, reinterpret_cast(this)); setArg(call_get_pow_800, 1, EEW); setRet(call_get_pow_800, 0, ret_val_get_pow_800); @@ -24702,7 +24758,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_804_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_804 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_804, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_804, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_804, 32, false), traits::vstart); setArg(call_vssseg_804, 0, reinterpret_cast(this->get_arch())); @@ -24780,7 +24836,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_807 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_807, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_805, ret_val_get_sew_pow_806), ret_val_get_lmul_pow_807)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_805, ret_val_get_sew_pow_806), ret_val_get_lmul_pow_807)), 8, true); setArg(call_get_pow_805, 0, reinterpret_cast(this)); setArg(call_get_pow_805, 1, EEW); setRet(call_get_pow_805, 0, ret_val_get_pow_805); @@ -24823,7 +24879,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_809_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_809 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_809, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_809, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_809, 32, false), traits::vstart); setArg(call_vssseg_809, 0, reinterpret_cast(this->get_arch())); @@ -24901,7 +24957,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_812 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_812, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_810, ret_val_get_sew_pow_811), ret_val_get_lmul_pow_812)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_810, ret_val_get_sew_pow_811), ret_val_get_lmul_pow_812)), 8, true); setArg(call_get_pow_810, 0, reinterpret_cast(this)); setArg(call_get_pow_810, 1, EEW); setRet(call_get_pow_810, 0, ret_val_get_pow_810); @@ -24944,7 +25000,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_814_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_814 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_814, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_814, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_814, 32, false), traits::vstart); setArg(call_vssseg_814, 0, reinterpret_cast(this->get_arch())); @@ -25022,7 +25078,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_817 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_817, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_815, ret_val_get_sew_pow_816), ret_val_get_lmul_pow_817)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_815, ret_val_get_sew_pow_816), ret_val_get_lmul_pow_817)), 8, true); setArg(call_get_pow_815, 0, reinterpret_cast(this)); setArg(call_get_pow_815, 1, EEW); setRet(call_get_pow_815, 0, ret_val_get_pow_815); @@ -25065,7 +25121,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_819_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_819 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_819, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_819, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_819, 32, false), traits::vstart); setArg(call_vssseg_819, 0, reinterpret_cast(this->get_arch())); @@ -25143,7 +25199,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_822 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_822, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_820, ret_val_get_sew_pow_821), ret_val_get_lmul_pow_822)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_820, ret_val_get_sew_pow_821), ret_val_get_lmul_pow_822)), 8, true); setArg(call_get_pow_820, 0, reinterpret_cast(this)); setArg(call_get_pow_820, 1, EEW); setRet(call_get_pow_820, 0, ret_val_get_pow_820); @@ -25186,7 +25242,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_824_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_824 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_824, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_824, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_824, 32, false), traits::vstart); setArg(call_vssseg_824, 0, reinterpret_cast(this->get_arch())); @@ -25264,7 +25320,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_827 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_827, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_825, ret_val_get_sew_pow_826), ret_val_get_lmul_pow_827)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_825, ret_val_get_sew_pow_826), ret_val_get_lmul_pow_827)), 8, true); setArg(call_get_pow_825, 0, reinterpret_cast(this)); setArg(call_get_pow_825, 1, EEW); setRet(call_get_pow_825, 0, ret_val_get_pow_825); @@ -25307,7 +25363,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_829_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_829 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_829, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_829, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_829, 32, false), traits::vstart); setArg(call_vssseg_829, 0, reinterpret_cast(this->get_arch())); @@ -25385,7 +25441,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_832 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_832, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_830, ret_val_get_sew_pow_831), ret_val_get_lmul_pow_832)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_830, ret_val_get_sew_pow_831), ret_val_get_lmul_pow_832)), 8, true); setArg(call_get_pow_830, 0, reinterpret_cast(this)); setArg(call_get_pow_830, 1, EEW); setRet(call_get_pow_830, 0, ret_val_get_pow_830); @@ -25428,7 +25484,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_834_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_834 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_834, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_834, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_834, 32, false), traits::vstart); setArg(call_vssseg_834, 0, reinterpret_cast(this->get_arch())); @@ -25506,7 +25562,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_837 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_837, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_835, ret_val_get_sew_pow_836), ret_val_get_lmul_pow_837)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_835, ret_val_get_sew_pow_836), ret_val_get_lmul_pow_837)), 8, true); setArg(call_get_pow_835, 0, reinterpret_cast(this)); setArg(call_get_pow_835, 1, EEW); setRet(call_get_pow_835, 0, ret_val_get_pow_835); @@ -25549,7 +25605,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_839_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_839 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_839, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_839, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_839, 32, false), traits::vstart); setArg(call_vssseg_839, 0, reinterpret_cast(this->get_arch())); @@ -25627,7 +25683,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_842 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_842, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_840, ret_val_get_sew_pow_841), ret_val_get_lmul_pow_842)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_840, ret_val_get_sew_pow_841), ret_val_get_lmul_pow_842)), 8, true); setArg(call_get_pow_840, 0, reinterpret_cast(this)); setArg(call_get_pow_840, 1, EEW); setRet(call_get_pow_840, 0, ret_val_get_pow_840); @@ -25670,7 +25726,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_844_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_844 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_844, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_844, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_844, 32, false), traits::vstart); setArg(call_vssseg_844, 0, reinterpret_cast(this->get_arch())); @@ -25748,7 +25804,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_847 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_847, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_845, ret_val_get_sew_pow_846), ret_val_get_lmul_pow_847)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_845, ret_val_get_sew_pow_846), ret_val_get_lmul_pow_847)), 8, true); setArg(call_get_pow_845, 0, reinterpret_cast(this)); setArg(call_get_pow_845, 1, EEW); setRet(call_get_pow_845, 0, ret_val_get_pow_845); @@ -25791,7 +25847,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_849_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_849 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_849, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_849, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_849, 32, false), traits::vstart); setArg(call_vssseg_849, 0, reinterpret_cast(this->get_arch())); @@ -25869,7 +25925,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_852 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_852, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_850, ret_val_get_sew_pow_851), ret_val_get_lmul_pow_852)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_850, ret_val_get_sew_pow_851), ret_val_get_lmul_pow_852)), 8, true); setArg(call_get_pow_850, 0, reinterpret_cast(this)); setArg(call_get_pow_850, 1, EEW); setRet(call_get_pow_850, 0, ret_val_get_pow_850); @@ -25912,7 +25968,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_854_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_854 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_854, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_854, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_854, 32, false), traits::vstart); setArg(call_vssseg_854, 0, reinterpret_cast(this->get_arch())); @@ -25990,7 +26046,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_857 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_857, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_855, ret_val_get_sew_pow_856), ret_val_get_lmul_pow_857)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_855, ret_val_get_sew_pow_856), ret_val_get_lmul_pow_857)), 8, true); setArg(call_get_pow_855, 0, reinterpret_cast(this)); setArg(call_get_pow_855, 1, EEW); setRet(call_get_pow_855, 0, ret_val_get_pow_855); @@ -26033,7 +26089,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_859_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_859 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_859, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_859, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_859, 32, false), traits::vstart); setArg(call_vssseg_859, 0, reinterpret_cast(this->get_arch())); @@ -26111,7 +26167,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_862 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_862, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_860, ret_val_get_sew_pow_861), ret_val_get_lmul_pow_862)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_860, ret_val_get_sew_pow_861), ret_val_get_lmul_pow_862)), 8, true); setArg(call_get_pow_860, 0, reinterpret_cast(this)); setArg(call_get_pow_860, 1, EEW); setRet(call_get_pow_860, 0, ret_val_get_pow_860); @@ -26154,7 +26210,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_864_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_864 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_864, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_864, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_864, 32, false), traits::vstart); setArg(call_vssseg_864, 0, reinterpret_cast(this->get_arch())); @@ -26232,7 +26288,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_867 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_867, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_865, ret_val_get_sew_pow_866), ret_val_get_lmul_pow_867)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_865, ret_val_get_sew_pow_866), ret_val_get_lmul_pow_867)), 8, true); setArg(call_get_pow_865, 0, reinterpret_cast(this)); setArg(call_get_pow_865, 1, EEW); setRet(call_get_pow_865, 0, ret_val_get_pow_865); @@ -26275,7 +26331,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_869_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_869 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_869, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_869, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_869, 32, false), traits::vstart); setArg(call_vssseg_869, 0, reinterpret_cast(this->get_arch())); @@ -26353,7 +26409,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_872 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_872, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_870, ret_val_get_sew_pow_871), ret_val_get_lmul_pow_872)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_870, ret_val_get_sew_pow_871), ret_val_get_lmul_pow_872)), 8, true); setArg(call_get_pow_870, 0, reinterpret_cast(this)); setArg(call_get_pow_870, 1, EEW); setRet(call_get_pow_870, 0, ret_val_get_pow_870); @@ -26396,7 +26452,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_874_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_874 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_874, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_874, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_874, 32, false), traits::vstart); setArg(call_vssseg_874, 0, reinterpret_cast(this->get_arch())); @@ -26474,7 +26530,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_877 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_877, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_875, ret_val_get_sew_pow_876), ret_val_get_lmul_pow_877)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_875, ret_val_get_sew_pow_876), ret_val_get_lmul_pow_877)), 8, true); setArg(call_get_pow_875, 0, reinterpret_cast(this)); setArg(call_get_pow_875, 1, EEW); setRet(call_get_pow_875, 0, ret_val_get_pow_875); @@ -26517,7 +26573,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_879_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_879 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_879, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_879, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_879, 32, false), traits::vstart); setArg(call_vssseg_879, 0, reinterpret_cast(this->get_arch())); @@ -26595,7 +26651,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_882 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_882, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_880, ret_val_get_sew_pow_881), ret_val_get_lmul_pow_882)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_880, ret_val_get_sew_pow_881), ret_val_get_lmul_pow_882)), 8, true); setArg(call_get_pow_880, 0, reinterpret_cast(this)); setArg(call_get_pow_880, 1, EEW); setRet(call_get_pow_880, 0, ret_val_get_pow_880); @@ -26638,7 +26694,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_884_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_884 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_884, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_884, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_884, 32, false), traits::vstart); setArg(call_vssseg_884, 0, reinterpret_cast(this->get_arch())); @@ -26716,7 +26772,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_887 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_887, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_885, ret_val_get_sew_pow_886), ret_val_get_lmul_pow_887)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_885, ret_val_get_sew_pow_886), ret_val_get_lmul_pow_887)), 8, true); setArg(call_get_pow_885, 0, reinterpret_cast(this)); setArg(call_get_pow_885, 1, EEW); setRet(call_get_pow_885, 0, ret_val_get_pow_885); @@ -26759,7 +26815,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_889_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_889 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_889, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_889, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_889, 32, false), traits::vstart); setArg(call_vssseg_889, 0, reinterpret_cast(this->get_arch())); @@ -26837,7 +26893,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_892 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_892, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_890, ret_val_get_sew_pow_891), ret_val_get_lmul_pow_892)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_890, ret_val_get_sew_pow_891), ret_val_get_lmul_pow_892)), 8, true); setArg(call_get_pow_890, 0, reinterpret_cast(this)); setArg(call_get_pow_890, 1, EEW); setRet(call_get_pow_890, 0, ret_val_get_pow_890); @@ -26880,7 +26936,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_894_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_894 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_894, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_894, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_894, 32, false), traits::vstart); setArg(call_vssseg_894, 0, reinterpret_cast(this->get_arch())); @@ -26958,7 +27014,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_897 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_897, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_895, ret_val_get_sew_pow_896), ret_val_get_lmul_pow_897)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_895, ret_val_get_sew_pow_896), ret_val_get_lmul_pow_897)), 8, true); setArg(call_get_pow_895, 0, reinterpret_cast(this)); setArg(call_get_pow_895, 1, EEW); setRet(call_get_pow_895, 0, ret_val_get_pow_895); @@ -27001,7 +27057,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_899_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_899 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_899, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_899, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_899, 32, false), traits::vstart); setArg(call_vssseg_899, 0, reinterpret_cast(this->get_arch())); @@ -27079,7 +27135,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_902 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_902, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_900, ret_val_get_sew_pow_901), ret_val_get_lmul_pow_902)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_900, ret_val_get_sew_pow_901), ret_val_get_lmul_pow_902)), 8, true); setArg(call_get_pow_900, 0, reinterpret_cast(this)); setArg(call_get_pow_900, 1, EEW); setRet(call_get_pow_900, 0, ret_val_get_pow_900); @@ -27122,7 +27178,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_904_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_904 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_904, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_904, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_904, 32, false), traits::vstart); setArg(call_vssseg_904, 0, reinterpret_cast(this->get_arch())); @@ -27200,7 +27256,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_907 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_907, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_905, ret_val_get_sew_pow_906), ret_val_get_lmul_pow_907)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_905, ret_val_get_sew_pow_906), ret_val_get_lmul_pow_907)), 8, true); setArg(call_get_pow_905, 0, reinterpret_cast(this)); setArg(call_get_pow_905, 1, EEW); setRet(call_get_pow_905, 0, ret_val_get_pow_905); @@ -27243,7 +27299,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_909_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_909 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_909, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_909, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_909, 32, false), traits::vstart); setArg(call_vssseg_909, 0, reinterpret_cast(this->get_arch())); @@ -27321,7 +27377,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_912 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_912, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_910, ret_val_get_sew_pow_911), ret_val_get_lmul_pow_912)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_910, ret_val_get_sew_pow_911), ret_val_get_lmul_pow_912)), 8, true); setArg(call_get_pow_910, 0, reinterpret_cast(this)); setArg(call_get_pow_910, 1, EEW); setRet(call_get_pow_910, 0, ret_val_get_pow_910); @@ -27364,7 +27420,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vssseg_914_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 32, true); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vssseg_914 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vssseg_914, &vssseg, FuncSignature::build()); + cc.invoke(&call_vssseg_914, &vssseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vssseg_914, 32, false), traits::vstart); setArg(call_vssseg_914, 0, reinterpret_cast(this->get_arch())); @@ -27441,7 +27497,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_917 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_917, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_915, ret_val_get_sew_pow_916), ret_val_get_lmul_pow_917)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_915, ret_val_get_sew_pow_916), ret_val_get_lmul_pow_917)), 8, true); setArg(call_get_pow_915, 0, reinterpret_cast(this)); setArg(call_get_pow_915, 1, EEW); setRet(call_get_pow_915, 0, ret_val_get_pow_915); @@ -27479,7 +27535,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_919_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_919 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_919, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_919, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_919, 32, false); setArg(call_vlseg_919, 0, reinterpret_cast(this->get_arch())); @@ -27564,7 +27620,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_922 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_922, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_920, ret_val_get_sew_pow_921), ret_val_get_lmul_pow_922)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_920, ret_val_get_sew_pow_921), ret_val_get_lmul_pow_922)), 8, true); setArg(call_get_pow_920, 0, reinterpret_cast(this)); setArg(call_get_pow_920, 1, EEW); setRet(call_get_pow_920, 0, ret_val_get_pow_920); @@ -27602,7 +27658,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_924_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_924 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_924, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_924, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_924, 32, false); setArg(call_vlseg_924, 0, reinterpret_cast(this->get_arch())); @@ -27687,7 +27743,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_927 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_927, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_925, ret_val_get_sew_pow_926), ret_val_get_lmul_pow_927)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_925, ret_val_get_sew_pow_926), ret_val_get_lmul_pow_927)), 8, true); setArg(call_get_pow_925, 0, reinterpret_cast(this)); setArg(call_get_pow_925, 1, EEW); setRet(call_get_pow_925, 0, ret_val_get_pow_925); @@ -27725,7 +27781,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_929_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_929 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_929, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_929, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_929, 32, false); setArg(call_vlseg_929, 0, reinterpret_cast(this->get_arch())); @@ -27810,7 +27866,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_932 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_932, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_930, ret_val_get_sew_pow_931), ret_val_get_lmul_pow_932)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_930, ret_val_get_sew_pow_931), ret_val_get_lmul_pow_932)), 8, true); setArg(call_get_pow_930, 0, reinterpret_cast(this)); setArg(call_get_pow_930, 1, EEW); setRet(call_get_pow_930, 0, ret_val_get_pow_930); @@ -27848,7 +27904,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_934_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_934 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_934, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_934, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_934, 32, false); setArg(call_vlseg_934, 0, reinterpret_cast(this->get_arch())); @@ -27933,7 +27989,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_937 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_937, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_935, ret_val_get_sew_pow_936), ret_val_get_lmul_pow_937)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_935, ret_val_get_sew_pow_936), ret_val_get_lmul_pow_937)), 8, true); setArg(call_get_pow_935, 0, reinterpret_cast(this)); setArg(call_get_pow_935, 1, EEW); setRet(call_get_pow_935, 0, ret_val_get_pow_935); @@ -27971,7 +28027,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_939_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_939 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_939, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_939, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_939, 32, false); setArg(call_vlseg_939, 0, reinterpret_cast(this->get_arch())); @@ -28056,7 +28112,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_942 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_942, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_940, ret_val_get_sew_pow_941), ret_val_get_lmul_pow_942)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_940, ret_val_get_sew_pow_941), ret_val_get_lmul_pow_942)), 8, true); setArg(call_get_pow_940, 0, reinterpret_cast(this)); setArg(call_get_pow_940, 1, EEW); setRet(call_get_pow_940, 0, ret_val_get_pow_940); @@ -28094,7 +28150,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_944_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_944 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_944, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_944, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_944, 32, false); setArg(call_vlseg_944, 0, reinterpret_cast(this->get_arch())); @@ -28179,7 +28235,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_947 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_947, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_945, ret_val_get_sew_pow_946), ret_val_get_lmul_pow_947)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_945, ret_val_get_sew_pow_946), ret_val_get_lmul_pow_947)), 8, true); setArg(call_get_pow_945, 0, reinterpret_cast(this)); setArg(call_get_pow_945, 1, EEW); setRet(call_get_pow_945, 0, ret_val_get_pow_945); @@ -28217,7 +28273,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_949_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_949 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_949, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_949, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_949, 32, false); setArg(call_vlseg_949, 0, reinterpret_cast(this->get_arch())); @@ -28302,7 +28358,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_952 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_952, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_950, ret_val_get_sew_pow_951), ret_val_get_lmul_pow_952)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_950, ret_val_get_sew_pow_951), ret_val_get_lmul_pow_952)), 8, true); setArg(call_get_pow_950, 0, reinterpret_cast(this)); setArg(call_get_pow_950, 1, EEW); setRet(call_get_pow_950, 0, ret_val_get_pow_950); @@ -28340,7 +28396,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_954_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_954 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_954, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_954, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_954, 32, false); setArg(call_vlseg_954, 0, reinterpret_cast(this->get_arch())); @@ -28425,7 +28481,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_957 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_957, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_955, ret_val_get_sew_pow_956), ret_val_get_lmul_pow_957)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_955, ret_val_get_sew_pow_956), ret_val_get_lmul_pow_957)), 8, true); setArg(call_get_pow_955, 0, reinterpret_cast(this)); setArg(call_get_pow_955, 1, EEW); setRet(call_get_pow_955, 0, ret_val_get_pow_955); @@ -28463,7 +28519,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_959_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_959 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_959, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_959, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_959, 32, false); setArg(call_vlseg_959, 0, reinterpret_cast(this->get_arch())); @@ -28548,7 +28604,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_962 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_962, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_960, ret_val_get_sew_pow_961), ret_val_get_lmul_pow_962)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_960, ret_val_get_sew_pow_961), ret_val_get_lmul_pow_962)), 8, true); setArg(call_get_pow_960, 0, reinterpret_cast(this)); setArg(call_get_pow_960, 1, EEW); setRet(call_get_pow_960, 0, ret_val_get_pow_960); @@ -28586,7 +28642,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_964_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_964 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_964, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_964, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_964, 32, false); setArg(call_vlseg_964, 0, reinterpret_cast(this->get_arch())); @@ -28671,7 +28727,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_967 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_967, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_965, ret_val_get_sew_pow_966), ret_val_get_lmul_pow_967)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_965, ret_val_get_sew_pow_966), ret_val_get_lmul_pow_967)), 8, true); setArg(call_get_pow_965, 0, reinterpret_cast(this)); setArg(call_get_pow_965, 1, EEW); setRet(call_get_pow_965, 0, ret_val_get_pow_965); @@ -28709,7 +28765,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_969_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_969 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_969, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_969, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_969, 32, false); setArg(call_vlseg_969, 0, reinterpret_cast(this->get_arch())); @@ -28794,7 +28850,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_972 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_972, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_970, ret_val_get_sew_pow_971), ret_val_get_lmul_pow_972)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_970, ret_val_get_sew_pow_971), ret_val_get_lmul_pow_972)), 8, true); setArg(call_get_pow_970, 0, reinterpret_cast(this)); setArg(call_get_pow_970, 1, EEW); setRet(call_get_pow_970, 0, ret_val_get_pow_970); @@ -28832,7 +28888,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_974_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_974 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_974, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_974, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_974, 32, false); setArg(call_vlseg_974, 0, reinterpret_cast(this->get_arch())); @@ -28917,7 +28973,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_977 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_977, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_975, ret_val_get_sew_pow_976), ret_val_get_lmul_pow_977)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_975, ret_val_get_sew_pow_976), ret_val_get_lmul_pow_977)), 8, true); setArg(call_get_pow_975, 0, reinterpret_cast(this)); setArg(call_get_pow_975, 1, EEW); setRet(call_get_pow_975, 0, ret_val_get_pow_975); @@ -28955,7 +29011,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_979_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_979 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_979, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_979, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_979, 32, false); setArg(call_vlseg_979, 0, reinterpret_cast(this->get_arch())); @@ -29040,7 +29096,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_982 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_982, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_980, ret_val_get_sew_pow_981), ret_val_get_lmul_pow_982)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_980, ret_val_get_sew_pow_981), ret_val_get_lmul_pow_982)), 8, true); setArg(call_get_pow_980, 0, reinterpret_cast(this)); setArg(call_get_pow_980, 1, EEW); setRet(call_get_pow_980, 0, ret_val_get_pow_980); @@ -29078,7 +29134,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_984_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_984 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_984, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_984, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_984, 32, false); setArg(call_vlseg_984, 0, reinterpret_cast(this->get_arch())); @@ -29163,7 +29219,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_987 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_987, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_985, ret_val_get_sew_pow_986), ret_val_get_lmul_pow_987)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_985, ret_val_get_sew_pow_986), ret_val_get_lmul_pow_987)), 8, true); setArg(call_get_pow_985, 0, reinterpret_cast(this)); setArg(call_get_pow_985, 1, EEW); setRet(call_get_pow_985, 0, ret_val_get_pow_985); @@ -29201,7 +29257,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_989_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_989 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_989, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_989, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_989, 32, false); setArg(call_vlseg_989, 0, reinterpret_cast(this->get_arch())); @@ -29286,7 +29342,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_992 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_992, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_990, ret_val_get_sew_pow_991), ret_val_get_lmul_pow_992)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_990, ret_val_get_sew_pow_991), ret_val_get_lmul_pow_992)), 8, true); setArg(call_get_pow_990, 0, reinterpret_cast(this)); setArg(call_get_pow_990, 1, EEW); setRet(call_get_pow_990, 0, ret_val_get_pow_990); @@ -29324,7 +29380,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_994_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_994 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_994, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_994, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_994, 32, false); setArg(call_vlseg_994, 0, reinterpret_cast(this->get_arch())); @@ -29409,7 +29465,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_997 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_997, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_995, ret_val_get_sew_pow_996), ret_val_get_lmul_pow_997)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_995, ret_val_get_sew_pow_996), ret_val_get_lmul_pow_997)), 8, true); setArg(call_get_pow_995, 0, reinterpret_cast(this)); setArg(call_get_pow_995, 1, EEW); setRet(call_get_pow_995, 0, ret_val_get_pow_995); @@ -29447,7 +29503,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_999_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_999 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_999, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_999, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_999, 32, false); setArg(call_vlseg_999, 0, reinterpret_cast(this->get_arch())); @@ -29532,7 +29588,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1002 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1002, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1000, ret_val_get_sew_pow_1001), ret_val_get_lmul_pow_1002)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1000, ret_val_get_sew_pow_1001), ret_val_get_lmul_pow_1002)), 8, true); setArg(call_get_pow_1000, 0, reinterpret_cast(this)); setArg(call_get_pow_1000, 1, EEW); setRet(call_get_pow_1000, 0, ret_val_get_pow_1000); @@ -29570,7 +29626,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1004_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1004 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1004, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1004, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1004, 32, false); setArg(call_vlseg_1004, 0, reinterpret_cast(this->get_arch())); @@ -29655,7 +29711,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1007 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1007, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1005, ret_val_get_sew_pow_1006), ret_val_get_lmul_pow_1007)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1005, ret_val_get_sew_pow_1006), ret_val_get_lmul_pow_1007)), 8, true); setArg(call_get_pow_1005, 0, reinterpret_cast(this)); setArg(call_get_pow_1005, 1, EEW); setRet(call_get_pow_1005, 0, ret_val_get_pow_1005); @@ -29693,7 +29749,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1009_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1009 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1009, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1009, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1009, 32, false); setArg(call_vlseg_1009, 0, reinterpret_cast(this->get_arch())); @@ -29778,7 +29834,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1012 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1012, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1010, ret_val_get_sew_pow_1011), ret_val_get_lmul_pow_1012)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1010, ret_val_get_sew_pow_1011), ret_val_get_lmul_pow_1012)), 8, true); setArg(call_get_pow_1010, 0, reinterpret_cast(this)); setArg(call_get_pow_1010, 1, EEW); setRet(call_get_pow_1010, 0, ret_val_get_pow_1010); @@ -29816,7 +29872,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1014_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1014 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1014, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1014, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1014, 32, false); setArg(call_vlseg_1014, 0, reinterpret_cast(this->get_arch())); @@ -29901,7 +29957,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1017 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1017, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1015, ret_val_get_sew_pow_1016), ret_val_get_lmul_pow_1017)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1015, ret_val_get_sew_pow_1016), ret_val_get_lmul_pow_1017)), 8, true); setArg(call_get_pow_1015, 0, reinterpret_cast(this)); setArg(call_get_pow_1015, 1, EEW); setRet(call_get_pow_1015, 0, ret_val_get_pow_1015); @@ -29939,7 +29995,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1019_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1019 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1019, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1019, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1019, 32, false); setArg(call_vlseg_1019, 0, reinterpret_cast(this->get_arch())); @@ -30024,7 +30080,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1022 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1022, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1020, ret_val_get_sew_pow_1021), ret_val_get_lmul_pow_1022)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1020, ret_val_get_sew_pow_1021), ret_val_get_lmul_pow_1022)), 8, true); setArg(call_get_pow_1020, 0, reinterpret_cast(this)); setArg(call_get_pow_1020, 1, EEW); setRet(call_get_pow_1020, 0, ret_val_get_pow_1020); @@ -30062,7 +30118,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1024_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1024 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1024, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1024, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1024, 32, false); setArg(call_vlseg_1024, 0, reinterpret_cast(this->get_arch())); @@ -30147,7 +30203,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1027 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1027, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1025, ret_val_get_sew_pow_1026), ret_val_get_lmul_pow_1027)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1025, ret_val_get_sew_pow_1026), ret_val_get_lmul_pow_1027)), 8, true); setArg(call_get_pow_1025, 0, reinterpret_cast(this)); setArg(call_get_pow_1025, 1, EEW); setRet(call_get_pow_1025, 0, ret_val_get_pow_1025); @@ -30185,7 +30241,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1029_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1029 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1029, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1029, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1029, 32, false); setArg(call_vlseg_1029, 0, reinterpret_cast(this->get_arch())); @@ -30270,7 +30326,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1032 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1032, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1030, ret_val_get_sew_pow_1031), ret_val_get_lmul_pow_1032)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1030, ret_val_get_sew_pow_1031), ret_val_get_lmul_pow_1032)), 8, true); setArg(call_get_pow_1030, 0, reinterpret_cast(this)); setArg(call_get_pow_1030, 1, EEW); setRet(call_get_pow_1030, 0, ret_val_get_pow_1030); @@ -30308,7 +30364,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1034_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1034 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1034, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1034, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1034, 32, false); setArg(call_vlseg_1034, 0, reinterpret_cast(this->get_arch())); @@ -30393,7 +30449,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1037 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1037, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1035, ret_val_get_sew_pow_1036), ret_val_get_lmul_pow_1037)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1035, ret_val_get_sew_pow_1036), ret_val_get_lmul_pow_1037)), 8, true); setArg(call_get_pow_1035, 0, reinterpret_cast(this)); setArg(call_get_pow_1035, 1, EEW); setRet(call_get_pow_1035, 0, ret_val_get_pow_1035); @@ -30431,7 +30487,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1039_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1039 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1039, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1039, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1039, 32, false); setArg(call_vlseg_1039, 0, reinterpret_cast(this->get_arch())); @@ -30516,7 +30572,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1042 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1042, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1040, ret_val_get_sew_pow_1041), ret_val_get_lmul_pow_1042)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1040, ret_val_get_sew_pow_1041), ret_val_get_lmul_pow_1042)), 8, true); setArg(call_get_pow_1040, 0, reinterpret_cast(this)); setArg(call_get_pow_1040, 1, EEW); setRet(call_get_pow_1040, 0, ret_val_get_pow_1040); @@ -30554,7 +30610,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1044_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1044 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1044, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1044, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1044, 32, false); setArg(call_vlseg_1044, 0, reinterpret_cast(this->get_arch())); @@ -30639,7 +30695,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1047 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1047, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1045, ret_val_get_sew_pow_1046), ret_val_get_lmul_pow_1047)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1045, ret_val_get_sew_pow_1046), ret_val_get_lmul_pow_1047)), 8, true); setArg(call_get_pow_1045, 0, reinterpret_cast(this)); setArg(call_get_pow_1045, 1, EEW); setRet(call_get_pow_1045, 0, ret_val_get_pow_1045); @@ -30677,7 +30733,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1049_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1049 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1049, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1049, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1049, 32, false); setArg(call_vlseg_1049, 0, reinterpret_cast(this->get_arch())); @@ -30762,7 +30818,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1052 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1052, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1050, ret_val_get_sew_pow_1051), ret_val_get_lmul_pow_1052)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1050, ret_val_get_sew_pow_1051), ret_val_get_lmul_pow_1052)), 8, true); setArg(call_get_pow_1050, 0, reinterpret_cast(this)); setArg(call_get_pow_1050, 1, EEW); setRet(call_get_pow_1050, 0, ret_val_get_pow_1050); @@ -30800,7 +30856,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1054_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1054 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1054, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1054, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1054, 32, false); setArg(call_vlseg_1054, 0, reinterpret_cast(this->get_arch())); @@ -30885,7 +30941,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1057 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1057, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1055, ret_val_get_sew_pow_1056), ret_val_get_lmul_pow_1057)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1055, ret_val_get_sew_pow_1056), ret_val_get_lmul_pow_1057)), 8, true); setArg(call_get_pow_1055, 0, reinterpret_cast(this)); setArg(call_get_pow_1055, 1, EEW); setRet(call_get_pow_1055, 0, ret_val_get_pow_1055); @@ -30923,7 +30979,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1059_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1059 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1059, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1059, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1059, 32, false); setArg(call_vlseg_1059, 0, reinterpret_cast(this->get_arch())); @@ -31008,7 +31064,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1062 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1062, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1060, ret_val_get_sew_pow_1061), ret_val_get_lmul_pow_1062)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1060, ret_val_get_sew_pow_1061), ret_val_get_lmul_pow_1062)), 8, true); setArg(call_get_pow_1060, 0, reinterpret_cast(this)); setArg(call_get_pow_1060, 1, EEW); setRet(call_get_pow_1060, 0, ret_val_get_pow_1060); @@ -31046,7 +31102,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1064_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1064 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1064, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1064, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1064, 32, false); setArg(call_vlseg_1064, 0, reinterpret_cast(this->get_arch())); @@ -31131,7 +31187,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1067 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1067, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1065, ret_val_get_sew_pow_1066), ret_val_get_lmul_pow_1067)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1065, ret_val_get_sew_pow_1066), ret_val_get_lmul_pow_1067)), 8, true); setArg(call_get_pow_1065, 0, reinterpret_cast(this)); setArg(call_get_pow_1065, 1, EEW); setRet(call_get_pow_1065, 0, ret_val_get_pow_1065); @@ -31169,7 +31225,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1069_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1069 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1069, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1069, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1069, 32, false); setArg(call_vlseg_1069, 0, reinterpret_cast(this->get_arch())); @@ -31254,7 +31310,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1072 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1072, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1070, ret_val_get_sew_pow_1071), ret_val_get_lmul_pow_1072)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1070, ret_val_get_sew_pow_1071), ret_val_get_lmul_pow_1072)), 8, true); setArg(call_get_pow_1070, 0, reinterpret_cast(this)); setArg(call_get_pow_1070, 1, EEW); setRet(call_get_pow_1070, 0, ret_val_get_pow_1070); @@ -31292,7 +31348,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1074_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1074 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1074, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1074, &vlseg, FuncSignature::build()); auto trapped_idx = gen_ext(cc, ret_val_vlseg_1074, 32, false); setArg(call_vlseg_1074, 0, reinterpret_cast(this->get_arch())); @@ -31400,7 +31456,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_1077_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_1077 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_1077, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_1077, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_1077, 32, false), traits::vstart); setArg(call_vsseg_1077, 0, reinterpret_cast(this->get_arch())); @@ -31493,7 +31549,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1080_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1080 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1080, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1080, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1080, 32, false), traits::vstart); setArg(call_vlseg_1080, 0, reinterpret_cast(this->get_arch())); @@ -31566,7 +31622,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1082_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1082 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1082, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1082, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1082, 32, false), traits::vstart); setArg(call_vlseg_1082, 0, reinterpret_cast(this->get_arch())); @@ -31642,7 +31698,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1084_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1084 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1084, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1084, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1084, 32, false), traits::vstart); setArg(call_vlseg_1084, 0, reinterpret_cast(this->get_arch())); @@ -31718,7 +31774,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1086_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1086 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1086, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1086, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1086, 32, false), traits::vstart); setArg(call_vlseg_1086, 0, reinterpret_cast(this->get_arch())); @@ -31794,7 +31850,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1088_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1088 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1088, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1088, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1088, 32, false), traits::vstart); setArg(call_vlseg_1088, 0, reinterpret_cast(this->get_arch())); @@ -31874,7 +31930,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1090_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1090 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1090, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1090, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1090, 32, false), traits::vstart); setArg(call_vlseg_1090, 0, reinterpret_cast(this->get_arch())); @@ -31955,7 +32011,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1092_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1092 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1092, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1092, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1092, 32, false), traits::vstart); setArg(call_vlseg_1092, 0, reinterpret_cast(this->get_arch())); @@ -32036,7 +32092,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1094_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1094 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1094, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1094, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1094, 32, false), traits::vstart); setArg(call_vlseg_1094, 0, reinterpret_cast(this->get_arch())); @@ -32117,7 +32173,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1096_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1096 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1096, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1096, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1096, 32, false), traits::vstart); setArg(call_vlseg_1096, 0, reinterpret_cast(this->get_arch())); @@ -32198,7 +32254,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1098_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1098 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1098, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1098, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1098, 32, false), traits::vstart); setArg(call_vlseg_1098, 0, reinterpret_cast(this->get_arch())); @@ -32279,7 +32335,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1100_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1100 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1100, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1100, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1100, 32, false), traits::vstart); setArg(call_vlseg_1100, 0, reinterpret_cast(this->get_arch())); @@ -32360,7 +32416,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1102_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1102 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1102, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1102, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1102, 32, false), traits::vstart); setArg(call_vlseg_1102, 0, reinterpret_cast(this->get_arch())); @@ -32441,7 +32497,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1104_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1104 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1104, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1104, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1104, 32, false), traits::vstart); setArg(call_vlseg_1104, 0, reinterpret_cast(this->get_arch())); @@ -32522,7 +32578,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1106_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1106 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1106, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1106, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1106, 32, false), traits::vstart); setArg(call_vlseg_1106, 0, reinterpret_cast(this->get_arch())); @@ -32603,7 +32659,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1108_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1108 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1108, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1108, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1108, 32, false), traits::vstart); setArg(call_vlseg_1108, 0, reinterpret_cast(this->get_arch())); @@ -32684,7 +32740,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1110_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1110 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1110, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1110, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1110, 32, false), traits::vstart); setArg(call_vlseg_1110, 0, reinterpret_cast(this->get_arch())); @@ -32765,7 +32821,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlseg_1112_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlseg_1112 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlseg_1112, &vlseg, FuncSignature::build()); + cc.invoke(&call_vlseg_1112, &vlseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlseg_1112, 32, false), traits::vstart); setArg(call_vlseg_1112, 0, reinterpret_cast(this->get_arch())); @@ -32841,7 +32897,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_1114_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_1114 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_1114, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_1114, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_1114, 32, false), traits::vstart); setArg(call_vsseg_1114, 0, reinterpret_cast(this->get_arch())); @@ -32920,7 +32976,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_1116_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_1116 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_1116, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_1116, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_1116, 32, false), traits::vstart); setArg(call_vsseg_1116, 0, reinterpret_cast(this->get_arch())); @@ -33000,7 +33056,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_1118_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_1118 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_1118, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_1118, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_1118, 32, false), traits::vstart); setArg(call_vsseg_1118, 0, reinterpret_cast(this->get_arch())); @@ -33080,7 +33136,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsseg_1120_arg6 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsseg_1120 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsseg_1120, &vsseg, FuncSignature::build()); + cc.invoke(&call_vsseg_1120, &vsseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsseg_1120, 32, false), traits::vstart); setArg(call_vsseg_1120, 0, reinterpret_cast(this->get_arch())); @@ -33155,7 +33211,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1123 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1123, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1121, ret_val_get_sew_pow_1122), ret_val_get_lmul_pow_1123)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1121, ret_val_get_sew_pow_1122), ret_val_get_lmul_pow_1123)), 8, true); setArg(call_get_pow_1121, 0, reinterpret_cast(this)); setArg(call_get_pow_1121, 1, EEW); setRet(call_get_pow_1121, 0, ret_val_get_pow_1121); @@ -33210,7 +33266,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1126_arg10 = ret_val_sew_1127; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1126 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1126, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1126, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1126, 32, false), traits::vstart); setArg(call_sew_1127, 0, reinterpret_cast(this)); @@ -33292,7 +33348,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1130 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1130, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1128, ret_val_get_sew_pow_1129), ret_val_get_lmul_pow_1130)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1128, ret_val_get_sew_pow_1129), ret_val_get_lmul_pow_1130)), 8, true); setArg(call_get_pow_1128, 0, reinterpret_cast(this)); setArg(call_get_pow_1128, 1, EEW); setRet(call_get_pow_1128, 0, ret_val_get_pow_1128); @@ -33347,7 +33403,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1133_arg10 = ret_val_sew_1134; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1133 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1133, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1133, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1133, 32, false), traits::vstart); setArg(call_sew_1134, 0, reinterpret_cast(this)); @@ -33429,7 +33485,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1137 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1137, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1135, ret_val_get_sew_pow_1136), ret_val_get_lmul_pow_1137)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1135, ret_val_get_sew_pow_1136), ret_val_get_lmul_pow_1137)), 8, true); setArg(call_get_pow_1135, 0, reinterpret_cast(this)); setArg(call_get_pow_1135, 1, EEW); setRet(call_get_pow_1135, 0, ret_val_get_pow_1135); @@ -33484,7 +33540,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1140_arg10 = ret_val_sew_1141; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1140 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1140, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1140, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1140, 32, false), traits::vstart); setArg(call_sew_1141, 0, reinterpret_cast(this)); @@ -33566,7 +33622,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1144 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1144, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1142, ret_val_get_sew_pow_1143), ret_val_get_lmul_pow_1144)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1142, ret_val_get_sew_pow_1143), ret_val_get_lmul_pow_1144)), 8, true); setArg(call_get_pow_1142, 0, reinterpret_cast(this)); setArg(call_get_pow_1142, 1, EEW); setRet(call_get_pow_1142, 0, ret_val_get_pow_1142); @@ -33621,7 +33677,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1147_arg10 = ret_val_sew_1148; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1147 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1147, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1147, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1147, 32, false), traits::vstart); setArg(call_sew_1148, 0, reinterpret_cast(this)); @@ -33703,7 +33759,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1151 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1151, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1149, ret_val_get_sew_pow_1150), ret_val_get_lmul_pow_1151)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1149, ret_val_get_sew_pow_1150), ret_val_get_lmul_pow_1151)), 8, true); setArg(call_get_pow_1149, 0, reinterpret_cast(this)); setArg(call_get_pow_1149, 1, EEW); setRet(call_get_pow_1149, 0, ret_val_get_pow_1149); @@ -33758,7 +33814,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1154_arg10 = ret_val_sew_1155; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1154 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1154, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1154, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1154, 32, false), traits::vstart); setArg(call_sew_1155, 0, reinterpret_cast(this)); @@ -33840,7 +33896,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1158 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1158, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1156, ret_val_get_sew_pow_1157), ret_val_get_lmul_pow_1158)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1156, ret_val_get_sew_pow_1157), ret_val_get_lmul_pow_1158)), 8, true); setArg(call_get_pow_1156, 0, reinterpret_cast(this)); setArg(call_get_pow_1156, 1, EEW); setRet(call_get_pow_1156, 0, ret_val_get_pow_1156); @@ -33895,7 +33951,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1161_arg10 = ret_val_sew_1162; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1161 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1161, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1161, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1161, 32, false), traits::vstart); setArg(call_sew_1162, 0, reinterpret_cast(this)); @@ -33977,7 +34033,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1165 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1165, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1163, ret_val_get_sew_pow_1164), ret_val_get_lmul_pow_1165)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1163, ret_val_get_sew_pow_1164), ret_val_get_lmul_pow_1165)), 8, true); setArg(call_get_pow_1163, 0, reinterpret_cast(this)); setArg(call_get_pow_1163, 1, EEW); setRet(call_get_pow_1163, 0, ret_val_get_pow_1163); @@ -34032,7 +34088,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1168_arg10 = ret_val_sew_1169; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1168 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1168, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1168, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1168, 32, false), traits::vstart); setArg(call_sew_1169, 0, reinterpret_cast(this)); @@ -34114,7 +34170,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1172 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1172, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1170, ret_val_get_sew_pow_1171), ret_val_get_lmul_pow_1172)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1170, ret_val_get_sew_pow_1171), ret_val_get_lmul_pow_1172)), 8, true); setArg(call_get_pow_1170, 0, reinterpret_cast(this)); setArg(call_get_pow_1170, 1, EEW); setRet(call_get_pow_1170, 0, ret_val_get_pow_1170); @@ -34169,7 +34225,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1175_arg10 = ret_val_sew_1176; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1175 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1175, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1175, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1175, 32, false), traits::vstart); setArg(call_sew_1176, 0, reinterpret_cast(this)); @@ -34251,7 +34307,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1179 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1179, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1177, ret_val_get_sew_pow_1178), ret_val_get_lmul_pow_1179)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1177, ret_val_get_sew_pow_1178), ret_val_get_lmul_pow_1179)), 8, true); setArg(call_get_pow_1177, 0, reinterpret_cast(this)); setArg(call_get_pow_1177, 1, EEW); setRet(call_get_pow_1177, 0, ret_val_get_pow_1177); @@ -34306,7 +34362,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1182_arg10 = ret_val_sew_1183; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1182 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1182, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1182, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1182, 32, false), traits::vstart); setArg(call_sew_1183, 0, reinterpret_cast(this)); @@ -34388,7 +34444,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1186 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1186, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1184, ret_val_get_sew_pow_1185), ret_val_get_lmul_pow_1186)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1184, ret_val_get_sew_pow_1185), ret_val_get_lmul_pow_1186)), 8, true); setArg(call_get_pow_1184, 0, reinterpret_cast(this)); setArg(call_get_pow_1184, 1, EEW); setRet(call_get_pow_1184, 0, ret_val_get_pow_1184); @@ -34443,7 +34499,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1189_arg10 = ret_val_sew_1190; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1189 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1189, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1189, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1189, 32, false), traits::vstart); setArg(call_sew_1190, 0, reinterpret_cast(this)); @@ -34525,7 +34581,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1193 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1193, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1191, ret_val_get_sew_pow_1192), ret_val_get_lmul_pow_1193)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1191, ret_val_get_sew_pow_1192), ret_val_get_lmul_pow_1193)), 8, true); setArg(call_get_pow_1191, 0, reinterpret_cast(this)); setArg(call_get_pow_1191, 1, EEW); setRet(call_get_pow_1191, 0, ret_val_get_pow_1191); @@ -34580,7 +34636,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1196_arg10 = ret_val_sew_1197; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1196 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1196, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1196, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1196, 32, false), traits::vstart); setArg(call_sew_1197, 0, reinterpret_cast(this)); @@ -34662,7 +34718,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1200 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1200, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1198, ret_val_get_sew_pow_1199), ret_val_get_lmul_pow_1200)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1198, ret_val_get_sew_pow_1199), ret_val_get_lmul_pow_1200)), 8, true); setArg(call_get_pow_1198, 0, reinterpret_cast(this)); setArg(call_get_pow_1198, 1, EEW); setRet(call_get_pow_1198, 0, ret_val_get_pow_1198); @@ -34717,7 +34773,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1203_arg10 = ret_val_sew_1204; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1203 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1203, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1203, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1203, 32, false), traits::vstart); setArg(call_sew_1204, 0, reinterpret_cast(this)); @@ -34799,7 +34855,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1207 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1207, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1205, ret_val_get_sew_pow_1206), ret_val_get_lmul_pow_1207)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1205, ret_val_get_sew_pow_1206), ret_val_get_lmul_pow_1207)), 8, true); setArg(call_get_pow_1205, 0, reinterpret_cast(this)); setArg(call_get_pow_1205, 1, EEW); setRet(call_get_pow_1205, 0, ret_val_get_pow_1205); @@ -34854,7 +34910,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1210_arg10 = ret_val_sew_1211; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1210 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1210, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1210, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1210, 32, false), traits::vstart); setArg(call_sew_1211, 0, reinterpret_cast(this)); @@ -34936,7 +34992,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1214 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1214, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1212, ret_val_get_sew_pow_1213), ret_val_get_lmul_pow_1214)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1212, ret_val_get_sew_pow_1213), ret_val_get_lmul_pow_1214)), 8, true); setArg(call_get_pow_1212, 0, reinterpret_cast(this)); setArg(call_get_pow_1212, 1, EEW); setRet(call_get_pow_1212, 0, ret_val_get_pow_1212); @@ -34991,7 +35047,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1217_arg10 = ret_val_sew_1218; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1217 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1217, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1217, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1217, 32, false), traits::vstart); setArg(call_sew_1218, 0, reinterpret_cast(this)); @@ -35073,7 +35129,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1221 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1221, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1219, ret_val_get_sew_pow_1220), ret_val_get_lmul_pow_1221)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1219, ret_val_get_sew_pow_1220), ret_val_get_lmul_pow_1221)), 8, true); setArg(call_get_pow_1219, 0, reinterpret_cast(this)); setArg(call_get_pow_1219, 1, EEW); setRet(call_get_pow_1219, 0, ret_val_get_pow_1219); @@ -35128,7 +35184,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1224_arg10 = ret_val_sew_1225; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1224 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1224, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1224, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1224, 32, false), traits::vstart); setArg(call_sew_1225, 0, reinterpret_cast(this)); @@ -35210,7 +35266,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1228 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1228, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1226, ret_val_get_sew_pow_1227), ret_val_get_lmul_pow_1228)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1226, ret_val_get_sew_pow_1227), ret_val_get_lmul_pow_1228)), 8, true); setArg(call_get_pow_1226, 0, reinterpret_cast(this)); setArg(call_get_pow_1226, 1, EEW); setRet(call_get_pow_1226, 0, ret_val_get_pow_1226); @@ -35265,7 +35321,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1231_arg10 = ret_val_sew_1232; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1231 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1231, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1231, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1231, 32, false), traits::vstart); setArg(call_sew_1232, 0, reinterpret_cast(this)); @@ -35347,7 +35403,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1235 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1235, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1233, ret_val_get_sew_pow_1234), ret_val_get_lmul_pow_1235)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1233, ret_val_get_sew_pow_1234), ret_val_get_lmul_pow_1235)), 8, true); setArg(call_get_pow_1233, 0, reinterpret_cast(this)); setArg(call_get_pow_1233, 1, EEW); setRet(call_get_pow_1233, 0, ret_val_get_pow_1233); @@ -35402,7 +35458,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1238_arg10 = ret_val_sew_1239; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1238 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1238, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1238, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1238, 32, false), traits::vstart); setArg(call_sew_1239, 0, reinterpret_cast(this)); @@ -35484,7 +35540,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1242 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1242, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1240, ret_val_get_sew_pow_1241), ret_val_get_lmul_pow_1242)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1240, ret_val_get_sew_pow_1241), ret_val_get_lmul_pow_1242)), 8, true); setArg(call_get_pow_1240, 0, reinterpret_cast(this)); setArg(call_get_pow_1240, 1, EEW); setRet(call_get_pow_1240, 0, ret_val_get_pow_1240); @@ -35539,7 +35595,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1245_arg10 = ret_val_sew_1246; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1245 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1245, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1245, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1245, 32, false), traits::vstart); setArg(call_sew_1246, 0, reinterpret_cast(this)); @@ -35621,7 +35677,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1249 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1249, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1247, ret_val_get_sew_pow_1248), ret_val_get_lmul_pow_1249)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1247, ret_val_get_sew_pow_1248), ret_val_get_lmul_pow_1249)), 8, true); setArg(call_get_pow_1247, 0, reinterpret_cast(this)); setArg(call_get_pow_1247, 1, EEW); setRet(call_get_pow_1247, 0, ret_val_get_pow_1247); @@ -35676,7 +35732,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1252_arg10 = ret_val_sew_1253; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1252 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1252, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1252, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1252, 32, false), traits::vstart); setArg(call_sew_1253, 0, reinterpret_cast(this)); @@ -35758,7 +35814,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1256 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1256, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1254, ret_val_get_sew_pow_1255), ret_val_get_lmul_pow_1256)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1254, ret_val_get_sew_pow_1255), ret_val_get_lmul_pow_1256)), 8, true); setArg(call_get_pow_1254, 0, reinterpret_cast(this)); setArg(call_get_pow_1254, 1, EEW); setRet(call_get_pow_1254, 0, ret_val_get_pow_1254); @@ -35813,7 +35869,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1259_arg10 = ret_val_sew_1260; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1259 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1259, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1259, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1259, 32, false), traits::vstart); setArg(call_sew_1260, 0, reinterpret_cast(this)); @@ -35895,7 +35951,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1263 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1263, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1261, ret_val_get_sew_pow_1262), ret_val_get_lmul_pow_1263)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1261, ret_val_get_sew_pow_1262), ret_val_get_lmul_pow_1263)), 8, true); setArg(call_get_pow_1261, 0, reinterpret_cast(this)); setArg(call_get_pow_1261, 1, EEW); setRet(call_get_pow_1261, 0, ret_val_get_pow_1261); @@ -35950,7 +36006,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1266_arg10 = ret_val_sew_1267; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1266 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1266, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1266, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1266, 32, false), traits::vstart); setArg(call_sew_1267, 0, reinterpret_cast(this)); @@ -36032,7 +36088,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1270 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1270, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1268, ret_val_get_sew_pow_1269), ret_val_get_lmul_pow_1270)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1268, ret_val_get_sew_pow_1269), ret_val_get_lmul_pow_1270)), 8, true); setArg(call_get_pow_1268, 0, reinterpret_cast(this)); setArg(call_get_pow_1268, 1, EEW); setRet(call_get_pow_1268, 0, ret_val_get_pow_1268); @@ -36087,7 +36143,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1273_arg10 = ret_val_sew_1274; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1273 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1273, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1273, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1273, 32, false), traits::vstart); setArg(call_sew_1274, 0, reinterpret_cast(this)); @@ -36169,7 +36225,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1277 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1277, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1275, ret_val_get_sew_pow_1276), ret_val_get_lmul_pow_1277)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1275, ret_val_get_sew_pow_1276), ret_val_get_lmul_pow_1277)), 8, true); setArg(call_get_pow_1275, 0, reinterpret_cast(this)); setArg(call_get_pow_1275, 1, EEW); setRet(call_get_pow_1275, 0, ret_val_get_pow_1275); @@ -36224,7 +36280,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1280_arg10 = ret_val_sew_1281; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1280 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1280, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1280, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1280, 32, false), traits::vstart); setArg(call_sew_1281, 0, reinterpret_cast(this)); @@ -36306,7 +36362,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1284 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1284, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1282, ret_val_get_sew_pow_1283), ret_val_get_lmul_pow_1284)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1282, ret_val_get_sew_pow_1283), ret_val_get_lmul_pow_1284)), 8, true); setArg(call_get_pow_1282, 0, reinterpret_cast(this)); setArg(call_get_pow_1282, 1, EEW); setRet(call_get_pow_1282, 0, ret_val_get_pow_1282); @@ -36361,7 +36417,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1287_arg10 = ret_val_sew_1288; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1287 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1287, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1287, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1287, 32, false), traits::vstart); setArg(call_sew_1288, 0, reinterpret_cast(this)); @@ -36443,7 +36499,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1291 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1291, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1289, ret_val_get_sew_pow_1290), ret_val_get_lmul_pow_1291)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1289, ret_val_get_sew_pow_1290), ret_val_get_lmul_pow_1291)), 8, true); setArg(call_get_pow_1289, 0, reinterpret_cast(this)); setArg(call_get_pow_1289, 1, EEW); setRet(call_get_pow_1289, 0, ret_val_get_pow_1289); @@ -36498,7 +36554,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1294_arg10 = ret_val_sew_1295; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1294 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1294, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1294, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1294, 32, false), traits::vstart); setArg(call_sew_1295, 0, reinterpret_cast(this)); @@ -36580,7 +36636,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1298 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1298, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1296, ret_val_get_sew_pow_1297), ret_val_get_lmul_pow_1298)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1296, ret_val_get_sew_pow_1297), ret_val_get_lmul_pow_1298)), 8, true); setArg(call_get_pow_1296, 0, reinterpret_cast(this)); setArg(call_get_pow_1296, 1, EEW); setRet(call_get_pow_1296, 0, ret_val_get_pow_1296); @@ -36635,7 +36691,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1301_arg10 = ret_val_sew_1302; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1301 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1301, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1301, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1301, 32, false), traits::vstart); setArg(call_sew_1302, 0, reinterpret_cast(this)); @@ -36717,7 +36773,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1305 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1305, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1303, ret_val_get_sew_pow_1304), ret_val_get_lmul_pow_1305)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1303, ret_val_get_sew_pow_1304), ret_val_get_lmul_pow_1305)), 8, true); setArg(call_get_pow_1303, 0, reinterpret_cast(this)); setArg(call_get_pow_1303, 1, EEW); setRet(call_get_pow_1303, 0, ret_val_get_pow_1303); @@ -36772,7 +36828,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1308_arg10 = ret_val_sew_1309; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1308 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1308, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1308, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1308, 32, false), traits::vstart); setArg(call_sew_1309, 0, reinterpret_cast(this)); @@ -36854,7 +36910,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1312 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1312, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1310, ret_val_get_sew_pow_1311), ret_val_get_lmul_pow_1312)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1310, ret_val_get_sew_pow_1311), ret_val_get_lmul_pow_1312)), 8, true); setArg(call_get_pow_1310, 0, reinterpret_cast(this)); setArg(call_get_pow_1310, 1, EEW); setRet(call_get_pow_1310, 0, ret_val_get_pow_1310); @@ -36909,7 +36965,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1315_arg10 = ret_val_sew_1316; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1315 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1315, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1315, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1315, 32, false), traits::vstart); setArg(call_sew_1316, 0, reinterpret_cast(this)); @@ -36991,7 +37047,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1319 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1319, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1317, ret_val_get_sew_pow_1318), ret_val_get_lmul_pow_1319)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1317, ret_val_get_sew_pow_1318), ret_val_get_lmul_pow_1319)), 8, true); setArg(call_get_pow_1317, 0, reinterpret_cast(this)); setArg(call_get_pow_1317, 1, EEW); setRet(call_get_pow_1317, 0, ret_val_get_pow_1317); @@ -37046,7 +37102,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1322_arg10 = ret_val_sew_1323; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1322 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1322, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1322, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1322, 32, false), traits::vstart); setArg(call_sew_1323, 0, reinterpret_cast(this)); @@ -37128,7 +37184,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1326 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1326, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1324, ret_val_get_sew_pow_1325), ret_val_get_lmul_pow_1326)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1324, ret_val_get_sew_pow_1325), ret_val_get_lmul_pow_1326)), 8, true); setArg(call_get_pow_1324, 0, reinterpret_cast(this)); setArg(call_get_pow_1324, 1, EEW); setRet(call_get_pow_1324, 0, ret_val_get_pow_1324); @@ -37183,7 +37239,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1329_arg10 = ret_val_sew_1330; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1329 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1329, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1329, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1329, 32, false), traits::vstart); setArg(call_sew_1330, 0, reinterpret_cast(this)); @@ -37265,7 +37321,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1333 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1333, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1331, ret_val_get_sew_pow_1332), ret_val_get_lmul_pow_1333)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1331, ret_val_get_sew_pow_1332), ret_val_get_lmul_pow_1333)), 8, true); setArg(call_get_pow_1331, 0, reinterpret_cast(this)); setArg(call_get_pow_1331, 1, EEW); setRet(call_get_pow_1331, 0, ret_val_get_pow_1331); @@ -37320,7 +37376,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1336_arg10 = ret_val_sew_1337; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1336 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1336, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1336, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1336, 32, false), traits::vstart); setArg(call_sew_1337, 0, reinterpret_cast(this)); @@ -37402,7 +37458,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1340 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1340, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1338, ret_val_get_sew_pow_1339), ret_val_get_lmul_pow_1340)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1338, ret_val_get_sew_pow_1339), ret_val_get_lmul_pow_1340)), 8, true); setArg(call_get_pow_1338, 0, reinterpret_cast(this)); setArg(call_get_pow_1338, 1, EEW); setRet(call_get_pow_1338, 0, ret_val_get_pow_1338); @@ -37457,7 +37513,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1343_arg10 = ret_val_sew_1344; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1343 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1343, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1343, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1343, 32, false), traits::vstart); setArg(call_sew_1344, 0, reinterpret_cast(this)); @@ -37539,7 +37595,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1347 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1347, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1345, ret_val_get_sew_pow_1346), ret_val_get_lmul_pow_1347)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1345, ret_val_get_sew_pow_1346), ret_val_get_lmul_pow_1347)), 8, true); setArg(call_get_pow_1345, 0, reinterpret_cast(this)); setArg(call_get_pow_1345, 1, EEW); setRet(call_get_pow_1345, 0, ret_val_get_pow_1345); @@ -37592,7 +37648,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1350_arg10 = ret_val_sew_1351; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1350 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1350, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1350, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1350, 32, false), traits::vstart); setArg(call_sew_1351, 0, reinterpret_cast(this)); @@ -37674,7 +37730,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1354 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1354, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1352, ret_val_get_sew_pow_1353), ret_val_get_lmul_pow_1354)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1352, ret_val_get_sew_pow_1353), ret_val_get_lmul_pow_1354)), 8, true); setArg(call_get_pow_1352, 0, reinterpret_cast(this)); setArg(call_get_pow_1352, 1, EEW); setRet(call_get_pow_1352, 0, ret_val_get_pow_1352); @@ -37727,7 +37783,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1357_arg10 = ret_val_sew_1358; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1357 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1357, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1357, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1357, 32, false), traits::vstart); setArg(call_sew_1358, 0, reinterpret_cast(this)); @@ -37809,7 +37865,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1361 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1361, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1359, ret_val_get_sew_pow_1360), ret_val_get_lmul_pow_1361)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1359, ret_val_get_sew_pow_1360), ret_val_get_lmul_pow_1361)), 8, true); setArg(call_get_pow_1359, 0, reinterpret_cast(this)); setArg(call_get_pow_1359, 1, EEW); setRet(call_get_pow_1359, 0, ret_val_get_pow_1359); @@ -37862,7 +37918,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1364_arg10 = ret_val_sew_1365; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1364 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1364, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1364, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1364, 32, false), traits::vstart); setArg(call_sew_1365, 0, reinterpret_cast(this)); @@ -37944,7 +38000,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1368 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1368, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1366, ret_val_get_sew_pow_1367), ret_val_get_lmul_pow_1368)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1366, ret_val_get_sew_pow_1367), ret_val_get_lmul_pow_1368)), 8, true); setArg(call_get_pow_1366, 0, reinterpret_cast(this)); setArg(call_get_pow_1366, 1, EEW); setRet(call_get_pow_1366, 0, ret_val_get_pow_1366); @@ -37997,7 +38053,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1371_arg10 = ret_val_sew_1372; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1371 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1371, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1371, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1371, 32, false), traits::vstart); setArg(call_sew_1372, 0, reinterpret_cast(this)); @@ -38079,7 +38135,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1375 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1375, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1373, ret_val_get_sew_pow_1374), ret_val_get_lmul_pow_1375)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1373, ret_val_get_sew_pow_1374), ret_val_get_lmul_pow_1375)), 8, true); setArg(call_get_pow_1373, 0, reinterpret_cast(this)); setArg(call_get_pow_1373, 1, EEW); setRet(call_get_pow_1373, 0, ret_val_get_pow_1373); @@ -38132,7 +38188,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1378_arg10 = ret_val_sew_1379; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1378 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1378, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1378, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1378, 32, false), traits::vstart); setArg(call_sew_1379, 0, reinterpret_cast(this)); @@ -38214,7 +38270,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1382 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1382, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1380, ret_val_get_sew_pow_1381), ret_val_get_lmul_pow_1382)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1380, ret_val_get_sew_pow_1381), ret_val_get_lmul_pow_1382)), 8, true); setArg(call_get_pow_1380, 0, reinterpret_cast(this)); setArg(call_get_pow_1380, 1, EEW); setRet(call_get_pow_1380, 0, ret_val_get_pow_1380); @@ -38267,7 +38323,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1385_arg10 = ret_val_sew_1386; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1385 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1385, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1385, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1385, 32, false), traits::vstart); setArg(call_sew_1386, 0, reinterpret_cast(this)); @@ -38349,7 +38405,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1389 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1389, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1387, ret_val_get_sew_pow_1388), ret_val_get_lmul_pow_1389)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1387, ret_val_get_sew_pow_1388), ret_val_get_lmul_pow_1389)), 8, true); setArg(call_get_pow_1387, 0, reinterpret_cast(this)); setArg(call_get_pow_1387, 1, EEW); setRet(call_get_pow_1387, 0, ret_val_get_pow_1387); @@ -38402,7 +38458,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1392_arg10 = ret_val_sew_1393; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1392 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1392, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1392, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1392, 32, false), traits::vstart); setArg(call_sew_1393, 0, reinterpret_cast(this)); @@ -38484,7 +38540,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1396 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1396, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1394, ret_val_get_sew_pow_1395), ret_val_get_lmul_pow_1396)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1394, ret_val_get_sew_pow_1395), ret_val_get_lmul_pow_1396)), 8, true); setArg(call_get_pow_1394, 0, reinterpret_cast(this)); setArg(call_get_pow_1394, 1, EEW); setRet(call_get_pow_1394, 0, ret_val_get_pow_1394); @@ -38537,7 +38593,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1399_arg10 = ret_val_sew_1400; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1399 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1399, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1399, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1399, 32, false), traits::vstart); setArg(call_sew_1400, 0, reinterpret_cast(this)); @@ -38619,7 +38675,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1403 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1403, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1401, ret_val_get_sew_pow_1402), ret_val_get_lmul_pow_1403)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1401, ret_val_get_sew_pow_1402), ret_val_get_lmul_pow_1403)), 8, true); setArg(call_get_pow_1401, 0, reinterpret_cast(this)); setArg(call_get_pow_1401, 1, EEW); setRet(call_get_pow_1401, 0, ret_val_get_pow_1401); @@ -38672,7 +38728,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1406_arg10 = ret_val_sew_1407; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1406 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1406, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1406, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1406, 32, false), traits::vstart); setArg(call_sew_1407, 0, reinterpret_cast(this)); @@ -38754,7 +38810,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1410 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1410, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1408, ret_val_get_sew_pow_1409), ret_val_get_lmul_pow_1410)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1408, ret_val_get_sew_pow_1409), ret_val_get_lmul_pow_1410)), 8, true); setArg(call_get_pow_1408, 0, reinterpret_cast(this)); setArg(call_get_pow_1408, 1, EEW); setRet(call_get_pow_1408, 0, ret_val_get_pow_1408); @@ -38807,7 +38863,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1413_arg10 = ret_val_sew_1414; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1413 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1413, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1413, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1413, 32, false), traits::vstart); setArg(call_sew_1414, 0, reinterpret_cast(this)); @@ -38889,7 +38945,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1417 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1417, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1415, ret_val_get_sew_pow_1416), ret_val_get_lmul_pow_1417)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1415, ret_val_get_sew_pow_1416), ret_val_get_lmul_pow_1417)), 8, true); setArg(call_get_pow_1415, 0, reinterpret_cast(this)); setArg(call_get_pow_1415, 1, EEW); setRet(call_get_pow_1415, 0, ret_val_get_pow_1415); @@ -38942,7 +38998,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1420_arg10 = ret_val_sew_1421; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1420 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1420, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1420, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1420, 32, false), traits::vstart); setArg(call_sew_1421, 0, reinterpret_cast(this)); @@ -39024,7 +39080,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1424 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1424, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1422, ret_val_get_sew_pow_1423), ret_val_get_lmul_pow_1424)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1422, ret_val_get_sew_pow_1423), ret_val_get_lmul_pow_1424)), 8, true); setArg(call_get_pow_1422, 0, reinterpret_cast(this)); setArg(call_get_pow_1422, 1, EEW); setRet(call_get_pow_1422, 0, ret_val_get_pow_1422); @@ -39077,7 +39133,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1427_arg10 = ret_val_sew_1428; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1427 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1427, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1427, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1427, 32, false), traits::vstart); setArg(call_sew_1428, 0, reinterpret_cast(this)); @@ -39159,7 +39215,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1431 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1431, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1429, ret_val_get_sew_pow_1430), ret_val_get_lmul_pow_1431)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1429, ret_val_get_sew_pow_1430), ret_val_get_lmul_pow_1431)), 8, true); setArg(call_get_pow_1429, 0, reinterpret_cast(this)); setArg(call_get_pow_1429, 1, EEW); setRet(call_get_pow_1429, 0, ret_val_get_pow_1429); @@ -39212,7 +39268,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1434_arg10 = ret_val_sew_1435; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1434 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1434, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1434, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1434, 32, false), traits::vstart); setArg(call_sew_1435, 0, reinterpret_cast(this)); @@ -39294,7 +39350,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1438 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1438, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1436, ret_val_get_sew_pow_1437), ret_val_get_lmul_pow_1438)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1436, ret_val_get_sew_pow_1437), ret_val_get_lmul_pow_1438)), 8, true); setArg(call_get_pow_1436, 0, reinterpret_cast(this)); setArg(call_get_pow_1436, 1, EEW); setRet(call_get_pow_1436, 0, ret_val_get_pow_1436); @@ -39347,7 +39403,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1441_arg10 = ret_val_sew_1442; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1441 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1441, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1441, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1441, 32, false), traits::vstart); setArg(call_sew_1442, 0, reinterpret_cast(this)); @@ -39429,7 +39485,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1445 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1445, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1443, ret_val_get_sew_pow_1444), ret_val_get_lmul_pow_1445)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1443, ret_val_get_sew_pow_1444), ret_val_get_lmul_pow_1445)), 8, true); setArg(call_get_pow_1443, 0, reinterpret_cast(this)); setArg(call_get_pow_1443, 1, EEW); setRet(call_get_pow_1443, 0, ret_val_get_pow_1443); @@ -39482,7 +39538,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1448_arg10 = ret_val_sew_1449; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1448 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1448, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1448, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1448, 32, false), traits::vstart); setArg(call_sew_1449, 0, reinterpret_cast(this)); @@ -39564,7 +39620,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1452 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1452, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1450, ret_val_get_sew_pow_1451), ret_val_get_lmul_pow_1452)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1450, ret_val_get_sew_pow_1451), ret_val_get_lmul_pow_1452)), 8, true); setArg(call_get_pow_1450, 0, reinterpret_cast(this)); setArg(call_get_pow_1450, 1, EEW); setRet(call_get_pow_1450, 0, ret_val_get_pow_1450); @@ -39617,7 +39673,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1455_arg10 = ret_val_sew_1456; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1455 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1455, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1455, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1455, 32, false), traits::vstart); setArg(call_sew_1456, 0, reinterpret_cast(this)); @@ -39699,7 +39755,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1459 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1459, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1457, ret_val_get_sew_pow_1458), ret_val_get_lmul_pow_1459)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1457, ret_val_get_sew_pow_1458), ret_val_get_lmul_pow_1459)), 8, true); setArg(call_get_pow_1457, 0, reinterpret_cast(this)); setArg(call_get_pow_1457, 1, EEW); setRet(call_get_pow_1457, 0, ret_val_get_pow_1457); @@ -39752,7 +39808,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1462_arg10 = ret_val_sew_1463; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1462 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1462, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1462, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1462, 32, false), traits::vstart); setArg(call_sew_1463, 0, reinterpret_cast(this)); @@ -39834,7 +39890,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1466 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1466, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1464, ret_val_get_sew_pow_1465), ret_val_get_lmul_pow_1466)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1464, ret_val_get_sew_pow_1465), ret_val_get_lmul_pow_1466)), 8, true); setArg(call_get_pow_1464, 0, reinterpret_cast(this)); setArg(call_get_pow_1464, 1, EEW); setRet(call_get_pow_1464, 0, ret_val_get_pow_1464); @@ -39887,7 +39943,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1469_arg10 = ret_val_sew_1470; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1469 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1469, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1469, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1469, 32, false), traits::vstart); setArg(call_sew_1470, 0, reinterpret_cast(this)); @@ -39969,7 +40025,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1473 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1473, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1471, ret_val_get_sew_pow_1472), ret_val_get_lmul_pow_1473)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1471, ret_val_get_sew_pow_1472), ret_val_get_lmul_pow_1473)), 8, true); setArg(call_get_pow_1471, 0, reinterpret_cast(this)); setArg(call_get_pow_1471, 1, EEW); setRet(call_get_pow_1471, 0, ret_val_get_pow_1471); @@ -40022,7 +40078,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1476_arg10 = ret_val_sew_1477; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1476 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1476, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1476, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1476, 32, false), traits::vstart); setArg(call_sew_1477, 0, reinterpret_cast(this)); @@ -40104,7 +40160,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1480 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1480, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1478, ret_val_get_sew_pow_1479), ret_val_get_lmul_pow_1480)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1478, ret_val_get_sew_pow_1479), ret_val_get_lmul_pow_1480)), 8, true); setArg(call_get_pow_1478, 0, reinterpret_cast(this)); setArg(call_get_pow_1478, 1, EEW); setRet(call_get_pow_1478, 0, ret_val_get_pow_1478); @@ -40157,7 +40213,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1483_arg10 = ret_val_sew_1484; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1483 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1483, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1483, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1483, 32, false), traits::vstart); setArg(call_sew_1484, 0, reinterpret_cast(this)); @@ -40239,7 +40295,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1487 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1487, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1485, ret_val_get_sew_pow_1486), ret_val_get_lmul_pow_1487)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1485, ret_val_get_sew_pow_1486), ret_val_get_lmul_pow_1487)), 8, true); setArg(call_get_pow_1485, 0, reinterpret_cast(this)); setArg(call_get_pow_1485, 1, EEW); setRet(call_get_pow_1485, 0, ret_val_get_pow_1485); @@ -40292,7 +40348,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1490_arg10 = ret_val_sew_1491; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1490 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1490, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1490, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1490, 32, false), traits::vstart); setArg(call_sew_1491, 0, reinterpret_cast(this)); @@ -40374,7 +40430,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1494 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1494, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1492, ret_val_get_sew_pow_1493), ret_val_get_lmul_pow_1494)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1492, ret_val_get_sew_pow_1493), ret_val_get_lmul_pow_1494)), 8, true); setArg(call_get_pow_1492, 0, reinterpret_cast(this)); setArg(call_get_pow_1492, 1, EEW); setRet(call_get_pow_1492, 0, ret_val_get_pow_1492); @@ -40427,7 +40483,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1497_arg10 = ret_val_sew_1498; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1497 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1497, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1497, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1497, 32, false), traits::vstart); setArg(call_sew_1498, 0, reinterpret_cast(this)); @@ -40509,7 +40565,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1501 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1501, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1499, ret_val_get_sew_pow_1500), ret_val_get_lmul_pow_1501)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1499, ret_val_get_sew_pow_1500), ret_val_get_lmul_pow_1501)), 8, true); setArg(call_get_pow_1499, 0, reinterpret_cast(this)); setArg(call_get_pow_1499, 1, EEW); setRet(call_get_pow_1499, 0, ret_val_get_pow_1499); @@ -40562,7 +40618,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1504_arg10 = ret_val_sew_1505; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1504 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1504, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1504, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1504, 32, false), traits::vstart); setArg(call_sew_1505, 0, reinterpret_cast(this)); @@ -40644,7 +40700,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1508 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1508, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1506, ret_val_get_sew_pow_1507), ret_val_get_lmul_pow_1508)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1506, ret_val_get_sew_pow_1507), ret_val_get_lmul_pow_1508)), 8, true); setArg(call_get_pow_1506, 0, reinterpret_cast(this)); setArg(call_get_pow_1506, 1, EEW); setRet(call_get_pow_1506, 0, ret_val_get_pow_1506); @@ -40697,7 +40753,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1511_arg10 = ret_val_sew_1512; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1511 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1511, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1511, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1511, 32, false), traits::vstart); setArg(call_sew_1512, 0, reinterpret_cast(this)); @@ -40779,7 +40835,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1515 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1515, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1513, ret_val_get_sew_pow_1514), ret_val_get_lmul_pow_1515)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1513, ret_val_get_sew_pow_1514), ret_val_get_lmul_pow_1515)), 8, true); setArg(call_get_pow_1513, 0, reinterpret_cast(this)); setArg(call_get_pow_1513, 1, EEW); setRet(call_get_pow_1513, 0, ret_val_get_pow_1513); @@ -40832,7 +40888,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1518_arg10 = ret_val_sew_1519; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1518 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1518, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1518, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1518, 32, false), traits::vstart); setArg(call_sew_1519, 0, reinterpret_cast(this)); @@ -40914,7 +40970,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1522 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1522, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1520, ret_val_get_sew_pow_1521), ret_val_get_lmul_pow_1522)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1520, ret_val_get_sew_pow_1521), ret_val_get_lmul_pow_1522)), 8, true); setArg(call_get_pow_1520, 0, reinterpret_cast(this)); setArg(call_get_pow_1520, 1, EEW); setRet(call_get_pow_1520, 0, ret_val_get_pow_1520); @@ -40967,7 +41023,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1525_arg10 = ret_val_sew_1526; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1525 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1525, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1525, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1525, 32, false), traits::vstart); setArg(call_sew_1526, 0, reinterpret_cast(this)); @@ -41049,7 +41105,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1529 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1529, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1527, ret_val_get_sew_pow_1528), ret_val_get_lmul_pow_1529)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1527, ret_val_get_sew_pow_1528), ret_val_get_lmul_pow_1529)), 8, true); setArg(call_get_pow_1527, 0, reinterpret_cast(this)); setArg(call_get_pow_1527, 1, EEW); setRet(call_get_pow_1527, 0, ret_val_get_pow_1527); @@ -41102,7 +41158,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1532_arg10 = ret_val_sew_1533; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1532 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1532, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1532, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1532, 32, false), traits::vstart); setArg(call_sew_1533, 0, reinterpret_cast(this)); @@ -41184,7 +41240,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1536 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1536, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1534, ret_val_get_sew_pow_1535), ret_val_get_lmul_pow_1536)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1534, ret_val_get_sew_pow_1535), ret_val_get_lmul_pow_1536)), 8, true); setArg(call_get_pow_1534, 0, reinterpret_cast(this)); setArg(call_get_pow_1534, 1, EEW); setRet(call_get_pow_1534, 0, ret_val_get_pow_1534); @@ -41237,7 +41293,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1539_arg10 = ret_val_sew_1540; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1539 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1539, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1539, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1539, 32, false), traits::vstart); setArg(call_sew_1540, 0, reinterpret_cast(this)); @@ -41319,7 +41375,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1543 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1543, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1541, ret_val_get_sew_pow_1542), ret_val_get_lmul_pow_1543)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1541, ret_val_get_sew_pow_1542), ret_val_get_lmul_pow_1543)), 8, true); setArg(call_get_pow_1541, 0, reinterpret_cast(this)); setArg(call_get_pow_1541, 1, EEW); setRet(call_get_pow_1541, 0, ret_val_get_pow_1541); @@ -41372,7 +41428,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1546_arg10 = ret_val_sew_1547; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1546 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1546, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1546, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1546, 32, false), traits::vstart); setArg(call_sew_1547, 0, reinterpret_cast(this)); @@ -41454,7 +41510,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1550 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1550, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1548, ret_val_get_sew_pow_1549), ret_val_get_lmul_pow_1550)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1548, ret_val_get_sew_pow_1549), ret_val_get_lmul_pow_1550)), 8, true); setArg(call_get_pow_1548, 0, reinterpret_cast(this)); setArg(call_get_pow_1548, 1, EEW); setRet(call_get_pow_1548, 0, ret_val_get_pow_1548); @@ -41507,7 +41563,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1553_arg10 = ret_val_sew_1554; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1553 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1553, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1553, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1553, 32, false), traits::vstart); setArg(call_sew_1554, 0, reinterpret_cast(this)); @@ -41589,7 +41645,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1557 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1557, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1555, ret_val_get_sew_pow_1556), ret_val_get_lmul_pow_1557)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1555, ret_val_get_sew_pow_1556), ret_val_get_lmul_pow_1557)), 8, true); setArg(call_get_pow_1555, 0, reinterpret_cast(this)); setArg(call_get_pow_1555, 1, EEW); setRet(call_get_pow_1555, 0, ret_val_get_pow_1555); @@ -41642,7 +41698,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1560_arg10 = ret_val_sew_1561; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1560 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1560, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1560, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1560, 32, false), traits::vstart); setArg(call_sew_1561, 0, reinterpret_cast(this)); @@ -41724,7 +41780,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1564 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1564, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1562, ret_val_get_sew_pow_1563), ret_val_get_lmul_pow_1564)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1562, ret_val_get_sew_pow_1563), ret_val_get_lmul_pow_1564)), 8, true); setArg(call_get_pow_1562, 0, reinterpret_cast(this)); setArg(call_get_pow_1562, 1, EEW); setRet(call_get_pow_1562, 0, ret_val_get_pow_1562); @@ -41777,7 +41833,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1567_arg10 = ret_val_sew_1568; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1567 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1567, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1567, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1567, 32, false), traits::vstart); setArg(call_sew_1568, 0, reinterpret_cast(this)); @@ -41859,7 +41915,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1571 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1571, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1569, ret_val_get_sew_pow_1570), ret_val_get_lmul_pow_1571)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1569, ret_val_get_sew_pow_1570), ret_val_get_lmul_pow_1571)), 8, true); setArg(call_get_pow_1569, 0, reinterpret_cast(this)); setArg(call_get_pow_1569, 1, EEW); setRet(call_get_pow_1569, 0, ret_val_get_pow_1569); @@ -41914,7 +41970,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1574_arg10 = ret_val_sew_1575; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1574 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1574, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1574, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1574, 32, false), traits::vstart); setArg(call_sew_1575, 0, reinterpret_cast(this)); @@ -41996,7 +42052,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1578 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1578, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1576, ret_val_get_sew_pow_1577), ret_val_get_lmul_pow_1578)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1576, ret_val_get_sew_pow_1577), ret_val_get_lmul_pow_1578)), 8, true); setArg(call_get_pow_1576, 0, reinterpret_cast(this)); setArg(call_get_pow_1576, 1, EEW); setRet(call_get_pow_1576, 0, ret_val_get_pow_1576); @@ -42051,7 +42107,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1581_arg10 = ret_val_sew_1582; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1581 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1581, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1581, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1581, 32, false), traits::vstart); setArg(call_sew_1582, 0, reinterpret_cast(this)); @@ -42133,7 +42189,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1585 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1585, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1583, ret_val_get_sew_pow_1584), ret_val_get_lmul_pow_1585)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1583, ret_val_get_sew_pow_1584), ret_val_get_lmul_pow_1585)), 8, true); setArg(call_get_pow_1583, 0, reinterpret_cast(this)); setArg(call_get_pow_1583, 1, EEW); setRet(call_get_pow_1583, 0, ret_val_get_pow_1583); @@ -42188,7 +42244,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1588_arg10 = ret_val_sew_1589; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1588 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1588, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1588, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1588, 32, false), traits::vstart); setArg(call_sew_1589, 0, reinterpret_cast(this)); @@ -42270,7 +42326,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1592 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1592, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1590, ret_val_get_sew_pow_1591), ret_val_get_lmul_pow_1592)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1590, ret_val_get_sew_pow_1591), ret_val_get_lmul_pow_1592)), 8, true); setArg(call_get_pow_1590, 0, reinterpret_cast(this)); setArg(call_get_pow_1590, 1, EEW); setRet(call_get_pow_1590, 0, ret_val_get_pow_1590); @@ -42325,7 +42381,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1595_arg10 = ret_val_sew_1596; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1595 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1595, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1595, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1595, 32, false), traits::vstart); setArg(call_sew_1596, 0, reinterpret_cast(this)); @@ -42407,7 +42463,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1599 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1599, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1597, ret_val_get_sew_pow_1598), ret_val_get_lmul_pow_1599)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1597, ret_val_get_sew_pow_1598), ret_val_get_lmul_pow_1599)), 8, true); setArg(call_get_pow_1597, 0, reinterpret_cast(this)); setArg(call_get_pow_1597, 1, EEW); setRet(call_get_pow_1597, 0, ret_val_get_pow_1597); @@ -42462,7 +42518,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1602_arg10 = ret_val_sew_1603; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1602 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1602, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1602, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1602, 32, false), traits::vstart); setArg(call_sew_1603, 0, reinterpret_cast(this)); @@ -42544,7 +42600,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1606 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1606, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1604, ret_val_get_sew_pow_1605), ret_val_get_lmul_pow_1606)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1604, ret_val_get_sew_pow_1605), ret_val_get_lmul_pow_1606)), 8, true); setArg(call_get_pow_1604, 0, reinterpret_cast(this)); setArg(call_get_pow_1604, 1, EEW); setRet(call_get_pow_1604, 0, ret_val_get_pow_1604); @@ -42599,7 +42655,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1609_arg10 = ret_val_sew_1610; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1609 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1609, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1609, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1609, 32, false), traits::vstart); setArg(call_sew_1610, 0, reinterpret_cast(this)); @@ -42681,7 +42737,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1613 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1613, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1611, ret_val_get_sew_pow_1612), ret_val_get_lmul_pow_1613)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1611, ret_val_get_sew_pow_1612), ret_val_get_lmul_pow_1613)), 8, true); setArg(call_get_pow_1611, 0, reinterpret_cast(this)); setArg(call_get_pow_1611, 1, EEW); setRet(call_get_pow_1611, 0, ret_val_get_pow_1611); @@ -42736,7 +42792,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1616_arg10 = ret_val_sew_1617; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1616 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1616, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1616, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1616, 32, false), traits::vstart); setArg(call_sew_1617, 0, reinterpret_cast(this)); @@ -42818,7 +42874,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1620 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1620, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1618, ret_val_get_sew_pow_1619), ret_val_get_lmul_pow_1620)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1618, ret_val_get_sew_pow_1619), ret_val_get_lmul_pow_1620)), 8, true); setArg(call_get_pow_1618, 0, reinterpret_cast(this)); setArg(call_get_pow_1618, 1, EEW); setRet(call_get_pow_1618, 0, ret_val_get_pow_1618); @@ -42873,7 +42929,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1623_arg10 = ret_val_sew_1624; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1623 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1623, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1623, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1623, 32, false), traits::vstart); setArg(call_sew_1624, 0, reinterpret_cast(this)); @@ -42955,7 +43011,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1627 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1627, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1625, ret_val_get_sew_pow_1626), ret_val_get_lmul_pow_1627)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1625, ret_val_get_sew_pow_1626), ret_val_get_lmul_pow_1627)), 8, true); setArg(call_get_pow_1625, 0, reinterpret_cast(this)); setArg(call_get_pow_1625, 1, EEW); setRet(call_get_pow_1625, 0, ret_val_get_pow_1625); @@ -43010,7 +43066,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1630_arg10 = ret_val_sew_1631; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1630 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1630, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1630, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1630, 32, false), traits::vstart); setArg(call_sew_1631, 0, reinterpret_cast(this)); @@ -43092,7 +43148,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1634 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1634, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1632, ret_val_get_sew_pow_1633), ret_val_get_lmul_pow_1634)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1632, ret_val_get_sew_pow_1633), ret_val_get_lmul_pow_1634)), 8, true); setArg(call_get_pow_1632, 0, reinterpret_cast(this)); setArg(call_get_pow_1632, 1, EEW); setRet(call_get_pow_1632, 0, ret_val_get_pow_1632); @@ -43147,7 +43203,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1637_arg10 = ret_val_sew_1638; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1637 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1637, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1637, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1637, 32, false), traits::vstart); setArg(call_sew_1638, 0, reinterpret_cast(this)); @@ -43229,7 +43285,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1641 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1641, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1639, ret_val_get_sew_pow_1640), ret_val_get_lmul_pow_1641)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1639, ret_val_get_sew_pow_1640), ret_val_get_lmul_pow_1641)), 8, true); setArg(call_get_pow_1639, 0, reinterpret_cast(this)); setArg(call_get_pow_1639, 1, EEW); setRet(call_get_pow_1639, 0, ret_val_get_pow_1639); @@ -43284,7 +43340,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1644_arg10 = ret_val_sew_1645; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1644 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1644, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1644, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1644, 32, false), traits::vstart); setArg(call_sew_1645, 0, reinterpret_cast(this)); @@ -43366,7 +43422,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1648 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1648, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1646, ret_val_get_sew_pow_1647), ret_val_get_lmul_pow_1648)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1646, ret_val_get_sew_pow_1647), ret_val_get_lmul_pow_1648)), 8, true); setArg(call_get_pow_1646, 0, reinterpret_cast(this)); setArg(call_get_pow_1646, 1, EEW); setRet(call_get_pow_1646, 0, ret_val_get_pow_1646); @@ -43421,7 +43477,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1651_arg10 = ret_val_sew_1652; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1651 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1651, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1651, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1651, 32, false), traits::vstart); setArg(call_sew_1652, 0, reinterpret_cast(this)); @@ -43503,7 +43559,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1655 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1655, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1653, ret_val_get_sew_pow_1654), ret_val_get_lmul_pow_1655)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1653, ret_val_get_sew_pow_1654), ret_val_get_lmul_pow_1655)), 8, true); setArg(call_get_pow_1653, 0, reinterpret_cast(this)); setArg(call_get_pow_1653, 1, EEW); setRet(call_get_pow_1653, 0, ret_val_get_pow_1653); @@ -43558,7 +43614,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1658_arg10 = ret_val_sew_1659; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1658 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1658, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1658, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1658, 32, false), traits::vstart); setArg(call_sew_1659, 0, reinterpret_cast(this)); @@ -43640,7 +43696,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1662 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1662, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1660, ret_val_get_sew_pow_1661), ret_val_get_lmul_pow_1662)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1660, ret_val_get_sew_pow_1661), ret_val_get_lmul_pow_1662)), 8, true); setArg(call_get_pow_1660, 0, reinterpret_cast(this)); setArg(call_get_pow_1660, 1, EEW); setRet(call_get_pow_1660, 0, ret_val_get_pow_1660); @@ -43695,7 +43751,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1665_arg10 = ret_val_sew_1666; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1665 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1665, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1665, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1665, 32, false), traits::vstart); setArg(call_sew_1666, 0, reinterpret_cast(this)); @@ -43777,7 +43833,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1669 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1669, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1667, ret_val_get_sew_pow_1668), ret_val_get_lmul_pow_1669)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1667, ret_val_get_sew_pow_1668), ret_val_get_lmul_pow_1669)), 8, true); setArg(call_get_pow_1667, 0, reinterpret_cast(this)); setArg(call_get_pow_1667, 1, EEW); setRet(call_get_pow_1667, 0, ret_val_get_pow_1667); @@ -43832,7 +43888,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1672_arg10 = ret_val_sew_1673; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1672 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1672, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1672, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1672, 32, false), traits::vstart); setArg(call_sew_1673, 0, reinterpret_cast(this)); @@ -43914,7 +43970,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1676 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1676, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1674, ret_val_get_sew_pow_1675), ret_val_get_lmul_pow_1676)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1674, ret_val_get_sew_pow_1675), ret_val_get_lmul_pow_1676)), 8, true); setArg(call_get_pow_1674, 0, reinterpret_cast(this)); setArg(call_get_pow_1674, 1, EEW); setRet(call_get_pow_1674, 0, ret_val_get_pow_1674); @@ -43969,7 +44025,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1679_arg10 = ret_val_sew_1680; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1679 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1679, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1679, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1679, 32, false), traits::vstart); setArg(call_sew_1680, 0, reinterpret_cast(this)); @@ -44051,7 +44107,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1683 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1683, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1681, ret_val_get_sew_pow_1682), ret_val_get_lmul_pow_1683)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1681, ret_val_get_sew_pow_1682), ret_val_get_lmul_pow_1683)), 8, true); setArg(call_get_pow_1681, 0, reinterpret_cast(this)); setArg(call_get_pow_1681, 1, EEW); setRet(call_get_pow_1681, 0, ret_val_get_pow_1681); @@ -44106,7 +44162,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1686_arg10 = ret_val_sew_1687; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1686 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1686, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1686, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1686, 32, false), traits::vstart); setArg(call_sew_1687, 0, reinterpret_cast(this)); @@ -44188,7 +44244,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1690 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1690, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1688, ret_val_get_sew_pow_1689), ret_val_get_lmul_pow_1690)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1688, ret_val_get_sew_pow_1689), ret_val_get_lmul_pow_1690)), 8, true); setArg(call_get_pow_1688, 0, reinterpret_cast(this)); setArg(call_get_pow_1688, 1, EEW); setRet(call_get_pow_1688, 0, ret_val_get_pow_1688); @@ -44243,7 +44299,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1693_arg10 = ret_val_sew_1694; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1693 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1693, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1693, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1693, 32, false), traits::vstart); setArg(call_sew_1694, 0, reinterpret_cast(this)); @@ -44325,7 +44381,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1697 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1697, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1695, ret_val_get_sew_pow_1696), ret_val_get_lmul_pow_1697)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1695, ret_val_get_sew_pow_1696), ret_val_get_lmul_pow_1697)), 8, true); setArg(call_get_pow_1695, 0, reinterpret_cast(this)); setArg(call_get_pow_1695, 1, EEW); setRet(call_get_pow_1695, 0, ret_val_get_pow_1695); @@ -44380,7 +44436,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1700_arg10 = ret_val_sew_1701; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1700 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1700, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1700, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1700, 32, false), traits::vstart); setArg(call_sew_1701, 0, reinterpret_cast(this)); @@ -44462,7 +44518,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1704 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1704, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1702, ret_val_get_sew_pow_1703), ret_val_get_lmul_pow_1704)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1702, ret_val_get_sew_pow_1703), ret_val_get_lmul_pow_1704)), 8, true); setArg(call_get_pow_1702, 0, reinterpret_cast(this)); setArg(call_get_pow_1702, 1, EEW); setRet(call_get_pow_1702, 0, ret_val_get_pow_1702); @@ -44517,7 +44573,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1707_arg10 = ret_val_sew_1708; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1707 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1707, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1707, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1707, 32, false), traits::vstart); setArg(call_sew_1708, 0, reinterpret_cast(this)); @@ -44599,7 +44655,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1711 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1711, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1709, ret_val_get_sew_pow_1710), ret_val_get_lmul_pow_1711)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1709, ret_val_get_sew_pow_1710), ret_val_get_lmul_pow_1711)), 8, true); setArg(call_get_pow_1709, 0, reinterpret_cast(this)); setArg(call_get_pow_1709, 1, EEW); setRet(call_get_pow_1709, 0, ret_val_get_pow_1709); @@ -44654,7 +44710,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1714_arg10 = ret_val_sew_1715; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1714 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1714, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1714, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1714, 32, false), traits::vstart); setArg(call_sew_1715, 0, reinterpret_cast(this)); @@ -44736,7 +44792,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1718 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1718, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1716, ret_val_get_sew_pow_1717), ret_val_get_lmul_pow_1718)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1716, ret_val_get_sew_pow_1717), ret_val_get_lmul_pow_1718)), 8, true); setArg(call_get_pow_1716, 0, reinterpret_cast(this)); setArg(call_get_pow_1716, 1, EEW); setRet(call_get_pow_1716, 0, ret_val_get_pow_1716); @@ -44791,7 +44847,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1721_arg10 = ret_val_sew_1722; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1721 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1721, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1721, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1721, 32, false), traits::vstart); setArg(call_sew_1722, 0, reinterpret_cast(this)); @@ -44873,7 +44929,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1725 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1725, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1723, ret_val_get_sew_pow_1724), ret_val_get_lmul_pow_1725)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1723, ret_val_get_sew_pow_1724), ret_val_get_lmul_pow_1725)), 8, true); setArg(call_get_pow_1723, 0, reinterpret_cast(this)); setArg(call_get_pow_1723, 1, EEW); setRet(call_get_pow_1723, 0, ret_val_get_pow_1723); @@ -44928,7 +44984,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1728_arg10 = ret_val_sew_1729; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1728 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1728, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1728, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1728, 32, false), traits::vstart); setArg(call_sew_1729, 0, reinterpret_cast(this)); @@ -45010,7 +45066,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1732 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1732, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1730, ret_val_get_sew_pow_1731), ret_val_get_lmul_pow_1732)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1730, ret_val_get_sew_pow_1731), ret_val_get_lmul_pow_1732)), 8, true); setArg(call_get_pow_1730, 0, reinterpret_cast(this)); setArg(call_get_pow_1730, 1, EEW); setRet(call_get_pow_1730, 0, ret_val_get_pow_1730); @@ -45065,7 +45121,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1735_arg10 = ret_val_sew_1736; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1735 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1735, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1735, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1735, 32, false), traits::vstart); setArg(call_sew_1736, 0, reinterpret_cast(this)); @@ -45147,7 +45203,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1739 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1739, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1737, ret_val_get_sew_pow_1738), ret_val_get_lmul_pow_1739)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1737, ret_val_get_sew_pow_1738), ret_val_get_lmul_pow_1739)), 8, true); setArg(call_get_pow_1737, 0, reinterpret_cast(this)); setArg(call_get_pow_1737, 1, EEW); setRet(call_get_pow_1737, 0, ret_val_get_pow_1737); @@ -45202,7 +45258,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1742_arg10 = ret_val_sew_1743; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1742 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1742, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1742, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1742, 32, false), traits::vstart); setArg(call_sew_1743, 0, reinterpret_cast(this)); @@ -45284,7 +45340,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1746 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1746, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1744, ret_val_get_sew_pow_1745), ret_val_get_lmul_pow_1746)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1744, ret_val_get_sew_pow_1745), ret_val_get_lmul_pow_1746)), 8, true); setArg(call_get_pow_1744, 0, reinterpret_cast(this)); setArg(call_get_pow_1744, 1, EEW); setRet(call_get_pow_1744, 0, ret_val_get_pow_1744); @@ -45339,7 +45395,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1749_arg10 = ret_val_sew_1750; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1749 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1749, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1749, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1749, 32, false), traits::vstart); setArg(call_sew_1750, 0, reinterpret_cast(this)); @@ -45421,7 +45477,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1753 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1753, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1751, ret_val_get_sew_pow_1752), ret_val_get_lmul_pow_1753)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1751, ret_val_get_sew_pow_1752), ret_val_get_lmul_pow_1753)), 8, true); setArg(call_get_pow_1751, 0, reinterpret_cast(this)); setArg(call_get_pow_1751, 1, EEW); setRet(call_get_pow_1751, 0, ret_val_get_pow_1751); @@ -45476,7 +45532,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1756_arg10 = ret_val_sew_1757; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1756 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1756, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1756, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1756, 32, false), traits::vstart); setArg(call_sew_1757, 0, reinterpret_cast(this)); @@ -45558,7 +45614,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1760 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1760, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1758, ret_val_get_sew_pow_1759), ret_val_get_lmul_pow_1760)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1758, ret_val_get_sew_pow_1759), ret_val_get_lmul_pow_1760)), 8, true); setArg(call_get_pow_1758, 0, reinterpret_cast(this)); setArg(call_get_pow_1758, 1, EEW); setRet(call_get_pow_1758, 0, ret_val_get_pow_1758); @@ -45613,7 +45669,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1763_arg10 = ret_val_sew_1764; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1763 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1763, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1763, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1763, 32, false), traits::vstart); setArg(call_sew_1764, 0, reinterpret_cast(this)); @@ -45695,7 +45751,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1767 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1767, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1765, ret_val_get_sew_pow_1766), ret_val_get_lmul_pow_1767)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1765, ret_val_get_sew_pow_1766), ret_val_get_lmul_pow_1767)), 8, true); setArg(call_get_pow_1765, 0, reinterpret_cast(this)); setArg(call_get_pow_1765, 1, EEW); setRet(call_get_pow_1765, 0, ret_val_get_pow_1765); @@ -45750,7 +45806,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1770_arg10 = ret_val_sew_1771; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1770 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1770, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1770, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1770, 32, false), traits::vstart); setArg(call_sew_1771, 0, reinterpret_cast(this)); @@ -45832,7 +45888,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1774 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1774, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1772, ret_val_get_sew_pow_1773), ret_val_get_lmul_pow_1774)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1772, ret_val_get_sew_pow_1773), ret_val_get_lmul_pow_1774)), 8, true); setArg(call_get_pow_1772, 0, reinterpret_cast(this)); setArg(call_get_pow_1772, 1, EEW); setRet(call_get_pow_1772, 0, ret_val_get_pow_1772); @@ -45887,7 +45943,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1777_arg10 = ret_val_sew_1778; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1777 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1777, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1777, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1777, 32, false), traits::vstart); setArg(call_sew_1778, 0, reinterpret_cast(this)); @@ -45969,7 +46025,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1781 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1781, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1779, ret_val_get_sew_pow_1780), ret_val_get_lmul_pow_1781)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1779, ret_val_get_sew_pow_1780), ret_val_get_lmul_pow_1781)), 8, true); setArg(call_get_pow_1779, 0, reinterpret_cast(this)); setArg(call_get_pow_1779, 1, EEW); setRet(call_get_pow_1779, 0, ret_val_get_pow_1779); @@ -46024,7 +46080,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1784_arg10 = ret_val_sew_1785; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1784 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1784, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1784, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1784, 32, false), traits::vstart); setArg(call_sew_1785, 0, reinterpret_cast(this)); @@ -46106,7 +46162,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1788 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1788, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1786, ret_val_get_sew_pow_1787), ret_val_get_lmul_pow_1788)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1786, ret_val_get_sew_pow_1787), ret_val_get_lmul_pow_1788)), 8, true); setArg(call_get_pow_1786, 0, reinterpret_cast(this)); setArg(call_get_pow_1786, 1, EEW); setRet(call_get_pow_1786, 0, ret_val_get_pow_1786); @@ -46161,7 +46217,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vlxseg_1791_arg10 = ret_val_sew_1792; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vlxseg_1791 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vlxseg_1791, &vlxseg, FuncSignature::build()); + cc.invoke(&call_vlxseg_1791, &vlxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vlxseg_1791, 32, false), traits::vstart); setArg(call_sew_1792, 0, reinterpret_cast(this)); @@ -46243,7 +46299,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1795 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1795, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1793, ret_val_get_sew_pow_1794), ret_val_get_lmul_pow_1795)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1793, ret_val_get_sew_pow_1794), ret_val_get_lmul_pow_1795)), 8, true); setArg(call_get_pow_1793, 0, reinterpret_cast(this)); setArg(call_get_pow_1793, 1, EEW); setRet(call_get_pow_1793, 0, ret_val_get_pow_1793); @@ -46296,7 +46352,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1798_arg10 = ret_val_sew_1799; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1798 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1798, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1798, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1798, 32, false), traits::vstart); setArg(call_sew_1799, 0, reinterpret_cast(this)); @@ -46378,7 +46434,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1802 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1802, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1800, ret_val_get_sew_pow_1801), ret_val_get_lmul_pow_1802)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1800, ret_val_get_sew_pow_1801), ret_val_get_lmul_pow_1802)), 8, true); setArg(call_get_pow_1800, 0, reinterpret_cast(this)); setArg(call_get_pow_1800, 1, EEW); setRet(call_get_pow_1800, 0, ret_val_get_pow_1800); @@ -46431,7 +46487,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1805_arg10 = ret_val_sew_1806; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1805 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1805, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1805, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1805, 32, false), traits::vstart); setArg(call_sew_1806, 0, reinterpret_cast(this)); @@ -46513,7 +46569,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1809 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1809, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1807, ret_val_get_sew_pow_1808), ret_val_get_lmul_pow_1809)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1807, ret_val_get_sew_pow_1808), ret_val_get_lmul_pow_1809)), 8, true); setArg(call_get_pow_1807, 0, reinterpret_cast(this)); setArg(call_get_pow_1807, 1, EEW); setRet(call_get_pow_1807, 0, ret_val_get_pow_1807); @@ -46566,7 +46622,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1812_arg10 = ret_val_sew_1813; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1812 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1812, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1812, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1812, 32, false), traits::vstart); setArg(call_sew_1813, 0, reinterpret_cast(this)); @@ -46648,7 +46704,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1816 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1816, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1814, ret_val_get_sew_pow_1815), ret_val_get_lmul_pow_1816)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1814, ret_val_get_sew_pow_1815), ret_val_get_lmul_pow_1816)), 8, true); setArg(call_get_pow_1814, 0, reinterpret_cast(this)); setArg(call_get_pow_1814, 1, EEW); setRet(call_get_pow_1814, 0, ret_val_get_pow_1814); @@ -46701,7 +46757,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1819_arg10 = ret_val_sew_1820; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1819 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1819, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1819, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1819, 32, false), traits::vstart); setArg(call_sew_1820, 0, reinterpret_cast(this)); @@ -46783,7 +46839,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1823 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1823, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1821, ret_val_get_sew_pow_1822), ret_val_get_lmul_pow_1823)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1821, ret_val_get_sew_pow_1822), ret_val_get_lmul_pow_1823)), 8, true); setArg(call_get_pow_1821, 0, reinterpret_cast(this)); setArg(call_get_pow_1821, 1, EEW); setRet(call_get_pow_1821, 0, ret_val_get_pow_1821); @@ -46836,7 +46892,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1826_arg10 = ret_val_sew_1827; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1826 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1826, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1826, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1826, 32, false), traits::vstart); setArg(call_sew_1827, 0, reinterpret_cast(this)); @@ -46918,7 +46974,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1830 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1830, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1828, ret_val_get_sew_pow_1829), ret_val_get_lmul_pow_1830)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1828, ret_val_get_sew_pow_1829), ret_val_get_lmul_pow_1830)), 8, true); setArg(call_get_pow_1828, 0, reinterpret_cast(this)); setArg(call_get_pow_1828, 1, EEW); setRet(call_get_pow_1828, 0, ret_val_get_pow_1828); @@ -46971,7 +47027,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1833_arg10 = ret_val_sew_1834; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1833 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1833, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1833, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1833, 32, false), traits::vstart); setArg(call_sew_1834, 0, reinterpret_cast(this)); @@ -47053,7 +47109,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1837 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1837, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1835, ret_val_get_sew_pow_1836), ret_val_get_lmul_pow_1837)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1835, ret_val_get_sew_pow_1836), ret_val_get_lmul_pow_1837)), 8, true); setArg(call_get_pow_1835, 0, reinterpret_cast(this)); setArg(call_get_pow_1835, 1, EEW); setRet(call_get_pow_1835, 0, ret_val_get_pow_1835); @@ -47106,7 +47162,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1840_arg10 = ret_val_sew_1841; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1840 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1840, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1840, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1840, 32, false), traits::vstart); setArg(call_sew_1841, 0, reinterpret_cast(this)); @@ -47188,7 +47244,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1844 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1844, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1842, ret_val_get_sew_pow_1843), ret_val_get_lmul_pow_1844)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1842, ret_val_get_sew_pow_1843), ret_val_get_lmul_pow_1844)), 8, true); setArg(call_get_pow_1842, 0, reinterpret_cast(this)); setArg(call_get_pow_1842, 1, EEW); setRet(call_get_pow_1842, 0, ret_val_get_pow_1842); @@ -47241,7 +47297,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1847_arg10 = ret_val_sew_1848; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1847 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1847, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1847, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1847, 32, false), traits::vstart); setArg(call_sew_1848, 0, reinterpret_cast(this)); @@ -47323,7 +47379,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1851 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1851, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1849, ret_val_get_sew_pow_1850), ret_val_get_lmul_pow_1851)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1849, ret_val_get_sew_pow_1850), ret_val_get_lmul_pow_1851)), 8, true); setArg(call_get_pow_1849, 0, reinterpret_cast(this)); setArg(call_get_pow_1849, 1, EEW); setRet(call_get_pow_1849, 0, ret_val_get_pow_1849); @@ -47376,7 +47432,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1854_arg10 = ret_val_sew_1855; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1854 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1854, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1854, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1854, 32, false), traits::vstart); setArg(call_sew_1855, 0, reinterpret_cast(this)); @@ -47458,7 +47514,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1858 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1858, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1856, ret_val_get_sew_pow_1857), ret_val_get_lmul_pow_1858)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1856, ret_val_get_sew_pow_1857), ret_val_get_lmul_pow_1858)), 8, true); setArg(call_get_pow_1856, 0, reinterpret_cast(this)); setArg(call_get_pow_1856, 1, EEW); setRet(call_get_pow_1856, 0, ret_val_get_pow_1856); @@ -47511,7 +47567,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1861_arg10 = ret_val_sew_1862; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1861 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1861, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1861, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1861, 32, false), traits::vstart); setArg(call_sew_1862, 0, reinterpret_cast(this)); @@ -47593,7 +47649,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1865 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1865, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1863, ret_val_get_sew_pow_1864), ret_val_get_lmul_pow_1865)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1863, ret_val_get_sew_pow_1864), ret_val_get_lmul_pow_1865)), 8, true); setArg(call_get_pow_1863, 0, reinterpret_cast(this)); setArg(call_get_pow_1863, 1, EEW); setRet(call_get_pow_1863, 0, ret_val_get_pow_1863); @@ -47646,7 +47702,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1868_arg10 = ret_val_sew_1869; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1868 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1868, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1868, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1868, 32, false), traits::vstart); setArg(call_sew_1869, 0, reinterpret_cast(this)); @@ -47728,7 +47784,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1872 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1872, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1870, ret_val_get_sew_pow_1871), ret_val_get_lmul_pow_1872)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1870, ret_val_get_sew_pow_1871), ret_val_get_lmul_pow_1872)), 8, true); setArg(call_get_pow_1870, 0, reinterpret_cast(this)); setArg(call_get_pow_1870, 1, EEW); setRet(call_get_pow_1870, 0, ret_val_get_pow_1870); @@ -47781,7 +47837,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1875_arg10 = ret_val_sew_1876; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1875 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1875, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1875, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1875, 32, false), traits::vstart); setArg(call_sew_1876, 0, reinterpret_cast(this)); @@ -47863,7 +47919,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1879 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1879, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1877, ret_val_get_sew_pow_1878), ret_val_get_lmul_pow_1879)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1877, ret_val_get_sew_pow_1878), ret_val_get_lmul_pow_1879)), 8, true); setArg(call_get_pow_1877, 0, reinterpret_cast(this)); setArg(call_get_pow_1877, 1, EEW); setRet(call_get_pow_1877, 0, ret_val_get_pow_1877); @@ -47916,7 +47972,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1882_arg10 = ret_val_sew_1883; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1882 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1882, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1882, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1882, 32, false), traits::vstart); setArg(call_sew_1883, 0, reinterpret_cast(this)); @@ -47998,7 +48054,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1886 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1886, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1884, ret_val_get_sew_pow_1885), ret_val_get_lmul_pow_1886)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1884, ret_val_get_sew_pow_1885), ret_val_get_lmul_pow_1886)), 8, true); setArg(call_get_pow_1884, 0, reinterpret_cast(this)); setArg(call_get_pow_1884, 1, EEW); setRet(call_get_pow_1884, 0, ret_val_get_pow_1884); @@ -48051,7 +48107,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1889_arg10 = ret_val_sew_1890; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1889 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1889, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1889, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1889, 32, false), traits::vstart); setArg(call_sew_1890, 0, reinterpret_cast(this)); @@ -48133,7 +48189,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1893 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1893, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1891, ret_val_get_sew_pow_1892), ret_val_get_lmul_pow_1893)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1891, ret_val_get_sew_pow_1892), ret_val_get_lmul_pow_1893)), 8, true); setArg(call_get_pow_1891, 0, reinterpret_cast(this)); setArg(call_get_pow_1891, 1, EEW); setRet(call_get_pow_1891, 0, ret_val_get_pow_1891); @@ -48186,7 +48242,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1896_arg10 = ret_val_sew_1897; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1896 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1896, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1896, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1896, 32, false), traits::vstart); setArg(call_sew_1897, 0, reinterpret_cast(this)); @@ -48268,7 +48324,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1900 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1900, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1898, ret_val_get_sew_pow_1899), ret_val_get_lmul_pow_1900)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1898, ret_val_get_sew_pow_1899), ret_val_get_lmul_pow_1900)), 8, true); setArg(call_get_pow_1898, 0, reinterpret_cast(this)); setArg(call_get_pow_1898, 1, EEW); setRet(call_get_pow_1898, 0, ret_val_get_pow_1898); @@ -48321,7 +48377,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1903_arg10 = ret_val_sew_1904; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1903 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1903, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1903, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1903, 32, false), traits::vstart); setArg(call_sew_1904, 0, reinterpret_cast(this)); @@ -48403,7 +48459,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1907 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1907, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1905, ret_val_get_sew_pow_1906), ret_val_get_lmul_pow_1907)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1905, ret_val_get_sew_pow_1906), ret_val_get_lmul_pow_1907)), 8, true); setArg(call_get_pow_1905, 0, reinterpret_cast(this)); setArg(call_get_pow_1905, 1, EEW); setRet(call_get_pow_1905, 0, ret_val_get_pow_1905); @@ -48456,7 +48512,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1910_arg10 = ret_val_sew_1911; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1910 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1910, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1910, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1910, 32, false), traits::vstart); setArg(call_sew_1911, 0, reinterpret_cast(this)); @@ -48538,7 +48594,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1914 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1914, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1912, ret_val_get_sew_pow_1913), ret_val_get_lmul_pow_1914)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1912, ret_val_get_sew_pow_1913), ret_val_get_lmul_pow_1914)), 8, true); setArg(call_get_pow_1912, 0, reinterpret_cast(this)); setArg(call_get_pow_1912, 1, EEW); setRet(call_get_pow_1912, 0, ret_val_get_pow_1912); @@ -48591,7 +48647,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1917_arg10 = ret_val_sew_1918; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1917 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1917, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1917, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1917, 32, false), traits::vstart); setArg(call_sew_1918, 0, reinterpret_cast(this)); @@ -48673,7 +48729,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1921 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1921, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1919, ret_val_get_sew_pow_1920), ret_val_get_lmul_pow_1921)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1919, ret_val_get_sew_pow_1920), ret_val_get_lmul_pow_1921)), 8, true); setArg(call_get_pow_1919, 0, reinterpret_cast(this)); setArg(call_get_pow_1919, 1, EEW); setRet(call_get_pow_1919, 0, ret_val_get_pow_1919); @@ -48726,7 +48782,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1924_arg10 = ret_val_sew_1925; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1924 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1924, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1924, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1924, 32, false), traits::vstart); setArg(call_sew_1925, 0, reinterpret_cast(this)); @@ -48808,7 +48864,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1928 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1928, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1926, ret_val_get_sew_pow_1927), ret_val_get_lmul_pow_1928)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1926, ret_val_get_sew_pow_1927), ret_val_get_lmul_pow_1928)), 8, true); setArg(call_get_pow_1926, 0, reinterpret_cast(this)); setArg(call_get_pow_1926, 1, EEW); setRet(call_get_pow_1926, 0, ret_val_get_pow_1926); @@ -48861,7 +48917,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1931_arg10 = ret_val_sew_1932; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1931 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1931, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1931, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1931, 32, false), traits::vstart); setArg(call_sew_1932, 0, reinterpret_cast(this)); @@ -48943,7 +48999,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1935 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1935, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1933, ret_val_get_sew_pow_1934), ret_val_get_lmul_pow_1935)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1933, ret_val_get_sew_pow_1934), ret_val_get_lmul_pow_1935)), 8, true); setArg(call_get_pow_1933, 0, reinterpret_cast(this)); setArg(call_get_pow_1933, 1, EEW); setRet(call_get_pow_1933, 0, ret_val_get_pow_1933); @@ -48996,7 +49052,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1938_arg10 = ret_val_sew_1939; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1938 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1938, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1938, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1938, 32, false), traits::vstart); setArg(call_sew_1939, 0, reinterpret_cast(this)); @@ -49078,7 +49134,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1942 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1942, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1940, ret_val_get_sew_pow_1941), ret_val_get_lmul_pow_1942)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1940, ret_val_get_sew_pow_1941), ret_val_get_lmul_pow_1942)), 8, true); setArg(call_get_pow_1940, 0, reinterpret_cast(this)); setArg(call_get_pow_1940, 1, EEW); setRet(call_get_pow_1940, 0, ret_val_get_pow_1940); @@ -49131,7 +49187,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1945_arg10 = ret_val_sew_1946; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1945 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1945, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1945, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1945, 32, false), traits::vstart); setArg(call_sew_1946, 0, reinterpret_cast(this)); @@ -49213,7 +49269,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1949 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1949, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1947, ret_val_get_sew_pow_1948), ret_val_get_lmul_pow_1949)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1947, ret_val_get_sew_pow_1948), ret_val_get_lmul_pow_1949)), 8, true); setArg(call_get_pow_1947, 0, reinterpret_cast(this)); setArg(call_get_pow_1947, 1, EEW); setRet(call_get_pow_1947, 0, ret_val_get_pow_1947); @@ -49266,7 +49322,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1952_arg10 = ret_val_sew_1953; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1952 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1952, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1952, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1952, 32, false), traits::vstart); setArg(call_sew_1953, 0, reinterpret_cast(this)); @@ -49348,7 +49404,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1956 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1956, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1954, ret_val_get_sew_pow_1955), ret_val_get_lmul_pow_1956)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1954, ret_val_get_sew_pow_1955), ret_val_get_lmul_pow_1956)), 8, true); setArg(call_get_pow_1954, 0, reinterpret_cast(this)); setArg(call_get_pow_1954, 1, EEW); setRet(call_get_pow_1954, 0, ret_val_get_pow_1954); @@ -49401,7 +49457,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1959_arg10 = ret_val_sew_1960; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1959 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1959, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1959, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1959, 32, false), traits::vstart); setArg(call_sew_1960, 0, reinterpret_cast(this)); @@ -49483,7 +49539,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1963 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1963, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1961, ret_val_get_sew_pow_1962), ret_val_get_lmul_pow_1963)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1961, ret_val_get_sew_pow_1962), ret_val_get_lmul_pow_1963)), 8, true); setArg(call_get_pow_1961, 0, reinterpret_cast(this)); setArg(call_get_pow_1961, 1, EEW); setRet(call_get_pow_1961, 0, ret_val_get_pow_1961); @@ -49536,7 +49592,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1966_arg10 = ret_val_sew_1967; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1966 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1966, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1966, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1966, 32, false), traits::vstart); setArg(call_sew_1967, 0, reinterpret_cast(this)); @@ -49618,7 +49674,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1970 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1970, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1968, ret_val_get_sew_pow_1969), ret_val_get_lmul_pow_1970)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1968, ret_val_get_sew_pow_1969), ret_val_get_lmul_pow_1970)), 8, true); setArg(call_get_pow_1968, 0, reinterpret_cast(this)); setArg(call_get_pow_1968, 1, EEW); setRet(call_get_pow_1968, 0, ret_val_get_pow_1968); @@ -49671,7 +49727,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1973_arg10 = ret_val_sew_1974; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1973 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1973, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1973, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1973, 32, false), traits::vstart); setArg(call_sew_1974, 0, reinterpret_cast(this)); @@ -49753,7 +49809,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1977 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1977, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1975, ret_val_get_sew_pow_1976), ret_val_get_lmul_pow_1977)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1975, ret_val_get_sew_pow_1976), ret_val_get_lmul_pow_1977)), 8, true); setArg(call_get_pow_1975, 0, reinterpret_cast(this)); setArg(call_get_pow_1975, 1, EEW); setRet(call_get_pow_1975, 0, ret_val_get_pow_1975); @@ -49806,7 +49862,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1980_arg10 = ret_val_sew_1981; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1980 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1980, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1980, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1980, 32, false), traits::vstart); setArg(call_sew_1981, 0, reinterpret_cast(this)); @@ -49888,7 +49944,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1984 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1984, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1982, ret_val_get_sew_pow_1983), ret_val_get_lmul_pow_1984)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1982, ret_val_get_sew_pow_1983), ret_val_get_lmul_pow_1984)), 8, true); setArg(call_get_pow_1982, 0, reinterpret_cast(this)); setArg(call_get_pow_1982, 1, EEW); setRet(call_get_pow_1982, 0, ret_val_get_pow_1982); @@ -49941,7 +49997,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1987_arg10 = ret_val_sew_1988; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1987 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1987, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1987, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1987, 32, false), traits::vstart); setArg(call_sew_1988, 0, reinterpret_cast(this)); @@ -50023,7 +50079,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1991 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1991, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1989, ret_val_get_sew_pow_1990), ret_val_get_lmul_pow_1991)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1989, ret_val_get_sew_pow_1990), ret_val_get_lmul_pow_1991)), 8, true); setArg(call_get_pow_1989, 0, reinterpret_cast(this)); setArg(call_get_pow_1989, 1, EEW); setRet(call_get_pow_1989, 0, ret_val_get_pow_1989); @@ -50076,7 +50132,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_1994_arg10 = ret_val_sew_1995; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_1994 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_1994, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_1994, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_1994, 32, false), traits::vstart); setArg(call_sew_1995, 0, reinterpret_cast(this)); @@ -50158,7 +50214,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1998 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1998, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1996, ret_val_get_sew_pow_1997), ret_val_get_lmul_pow_1998)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1996, ret_val_get_sew_pow_1997), ret_val_get_lmul_pow_1998)), 8, true); setArg(call_get_pow_1996, 0, reinterpret_cast(this)); setArg(call_get_pow_1996, 1, EEW); setRet(call_get_pow_1996, 0, ret_val_get_pow_1996); @@ -50211,7 +50267,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_2001_arg10 = ret_val_sew_2002; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_2001 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_2001, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_2001, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_2001, 32, false), traits::vstart); setArg(call_sew_2002, 0, reinterpret_cast(this)); @@ -50293,7 +50349,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_2005 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2005, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2003, ret_val_get_sew_pow_2004), ret_val_get_lmul_pow_2005)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2003, ret_val_get_sew_pow_2004), ret_val_get_lmul_pow_2005)), 8, true); setArg(call_get_pow_2003, 0, reinterpret_cast(this)); setArg(call_get_pow_2003, 1, EEW); setRet(call_get_pow_2003, 0, ret_val_get_pow_2003); @@ -50346,7 +50402,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_2008_arg10 = ret_val_sew_2009; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_2008 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_2008, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_2008, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_2008, 32, false), traits::vstart); setArg(call_sew_2009, 0, reinterpret_cast(this)); @@ -50428,7 +50484,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_2012 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2012, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2010, ret_val_get_sew_pow_2011), ret_val_get_lmul_pow_2012)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2010, ret_val_get_sew_pow_2011), ret_val_get_lmul_pow_2012)), 8, true); setArg(call_get_pow_2010, 0, reinterpret_cast(this)); setArg(call_get_pow_2010, 1, EEW); setRet(call_get_pow_2010, 0, ret_val_get_pow_2010); @@ -50481,7 +50537,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vsxseg_2015_arg10 = ret_val_sew_2016; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_vsxseg_2015 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vsxseg_2015, &vsxseg, FuncSignature::build()); + cc.invoke(&call_vsxseg_2015, &vsxseg, FuncSignature::build()); write_reg_to_mem(jh, gen_ext(cc, ret_val_vsxseg_2015, 32, false), traits::vstart); setArg(call_sew_2016, 0, reinterpret_cast(this)); @@ -50581,7 +50637,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_op_2018_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_op_2018_arg10 = ret_val_sew_2019; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2018, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2018, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2019, 0, reinterpret_cast(this)); setRet(call_sew_2019, 0, ret_val_sew_2019); setArg(call_vector_imm_op_2018, 0, V); @@ -50598,11 +50654,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2020 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2020, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2020, 32, false) - , traits::vstart); + auto tmp2020 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2020, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2020, traits::vstart); } cc.bind(label_merge); } @@ -50680,7 +50734,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2022_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2022_arg10 = ret_val_sew_2023; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2022, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2022, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2023, 0, reinterpret_cast(this)); setRet(call_sew_2023, 0, ret_val_sew_2023); setArg(call_vector_vector_op_2022, 0, V); @@ -50697,11 +50751,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2024 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2024, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2024, 32, false) - , traits::vstart); + auto tmp2024 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2024, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2024, traits::vstart); } cc.bind(label_merge); } @@ -50784,7 +50836,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2027_arg10 = ret_val_sew_2028; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2027, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2027, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2028, 0, reinterpret_cast(this)); setRet(call_sew_2028, 0, ret_val_sew_2028); setArg(call_vector_imm_op_2027, 0, V); @@ -50801,11 +50853,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2029 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2029, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2029, 32, false) - , traits::vstart); + auto tmp2029 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2029, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2029, traits::vstart); } cc.bind(label_merge); } @@ -50883,7 +50933,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2031_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2031_arg10 = ret_val_sew_2032; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2031, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2031, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2032, 0, reinterpret_cast(this)); setRet(call_sew_2032, 0, ret_val_sew_2032); setArg(call_vector_vector_op_2031, 0, V); @@ -50900,11 +50950,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2033 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2033, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2033, 32, false) - , traits::vstart); + auto tmp2033 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2033, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2033, traits::vstart); } cc.bind(label_merge); } @@ -50987,7 +51035,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2036_arg10 = ret_val_sew_2037; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2036, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2036, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2037, 0, reinterpret_cast(this)); setRet(call_sew_2037, 0, ret_val_sew_2037); setArg(call_vector_imm_op_2036, 0, V); @@ -51004,11 +51052,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2038 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2038, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2038, 32, false) - , traits::vstart); + auto tmp2038 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2038, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2038, traits::vstart); } cc.bind(label_merge); } @@ -51086,7 +51132,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_op_2040_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_op_2040_arg10 = ret_val_sew_2041; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2040, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2040, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2041, 0, reinterpret_cast(this)); setRet(call_sew_2041, 0, ret_val_sew_2041); setArg(call_vector_imm_op_2040, 0, V); @@ -51103,11 +51149,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2042 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2042, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2042, 32, false) - , traits::vstart); + auto tmp2042 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2042, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2042, traits::vstart); } cc.bind(label_merge); } @@ -51190,7 +51234,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2045_arg10 = ret_val_sew_2046; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2045, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2045, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2046, 0, reinterpret_cast(this)); setRet(call_sew_2046, 0, ret_val_sew_2046); setArg(call_vector_imm_op_2045, 0, V); @@ -51207,11 +51251,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2047 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2047, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2047, 32, false) - , traits::vstart); + auto tmp2047 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2047, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2047, traits::vstart); } cc.bind(label_merge); } @@ -51333,7 +51375,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_wv_2054_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_wv_2054_arg10 = ret_val_sew_2055; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_wv_2054, &vector_vector_wv, FuncSignature::build()); + cc.invoke(&call_vector_vector_wv_2054, &vector_vector_wv, FuncSignature::build()); setArg(call_sew_2055, 0, reinterpret_cast(this)); setRet(call_sew_2055, 0, ret_val_sew_2055); setArg(call_vector_vector_wv_2054, 0, V); @@ -51350,11 +51392,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2056 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2056, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2056, 32, false) - , traits::vstart); + auto tmp2056 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2056, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2056, traits::vstart); } cc.bind(label_merge); } @@ -51472,7 +51512,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2062_arg10 = ret_val_sew_2063; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2062, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2062, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2063, 0, reinterpret_cast(this)); setRet(call_sew_2063, 0, ret_val_sew_2063); setArg(call_vector_imm_wv_2062, 0, V); @@ -51489,11 +51529,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2064 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2064, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2064, 32, false) - , traits::vstart); + auto tmp2064 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2064, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2064, traits::vstart); } cc.bind(label_merge); } @@ -51616,7 +51654,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_wv_2071_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_wv_2071_arg10 = ret_val_sew_2072; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_wv_2071, &vector_vector_wv, FuncSignature::build()); + cc.invoke(&call_vector_vector_wv_2071, &vector_vector_wv, FuncSignature::build()); setArg(call_sew_2072, 0, reinterpret_cast(this)); setRet(call_sew_2072, 0, ret_val_sew_2072); setArg(call_vector_vector_wv_2071, 0, V); @@ -51633,11 +51671,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2073 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2073, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2073, 32, false) - , traits::vstart); + auto tmp2073 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2073, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2073, traits::vstart); } cc.bind(label_merge); } @@ -51755,7 +51791,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2079_arg10 = ret_val_sew_2080; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2079, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2079, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2080, 0, reinterpret_cast(this)); setRet(call_sew_2080, 0, ret_val_sew_2080); setArg(call_vector_imm_wv_2079, 0, V); @@ -51772,11 +51808,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2081 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2081, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2081, 32, false) - , traits::vstart); + auto tmp2081 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2081, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2081, traits::vstart); } cc.bind(label_merge); } @@ -51899,7 +51933,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_wv_2088_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_wv_2088_arg10 = ret_val_sew_2089; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_wv_2088, &vector_vector_wv, FuncSignature::build()); + cc.invoke(&call_vector_vector_wv_2088, &vector_vector_wv, FuncSignature::build()); setArg(call_sew_2089, 0, reinterpret_cast(this)); setRet(call_sew_2089, 0, ret_val_sew_2089); setArg(call_vector_vector_wv_2088, 0, V); @@ -51916,11 +51950,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2090 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2090, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2090, 32, false) - , traits::vstart); + auto tmp2090 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2090, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2090, traits::vstart); } cc.bind(label_merge); } @@ -52038,7 +52070,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2096_arg10 = ret_val_sew_2097; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2096, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2096, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2097, 0, reinterpret_cast(this)); setRet(call_sew_2097, 0, ret_val_sew_2097); setArg(call_vector_imm_wv_2096, 0, V); @@ -52055,11 +52087,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2098 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2098, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2098, 32, false) - , traits::vstart); + auto tmp2098 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2098, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2098, traits::vstart); } cc.bind(label_merge); } @@ -52182,7 +52212,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_wv_2105_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_wv_2105_arg10 = ret_val_sew_2106; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_wv_2105, &vector_vector_wv, FuncSignature::build()); + cc.invoke(&call_vector_vector_wv_2105, &vector_vector_wv, FuncSignature::build()); setArg(call_sew_2106, 0, reinterpret_cast(this)); setRet(call_sew_2106, 0, ret_val_sew_2106); setArg(call_vector_vector_wv_2105, 0, V); @@ -52199,11 +52229,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2107 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2107, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2107, 32, false) - , traits::vstart); + auto tmp2107 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2107, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2107, traits::vstart); } cc.bind(label_merge); } @@ -52321,7 +52349,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2113_arg10 = ret_val_sew_2114; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2113, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2113, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2114, 0, reinterpret_cast(this)); setRet(call_sew_2114, 0, ret_val_sew_2114); setArg(call_vector_imm_wv_2113, 0, V); @@ -52338,11 +52366,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2115 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2115, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2115, 32, false) - , traits::vstart); + auto tmp2115 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2115, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2115, traits::vstart); } cc.bind(label_merge); } @@ -52454,7 +52480,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_ww_2121_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_ww_2121_arg10 = ret_val_sew_2122; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_ww_2121, &vector_vector_ww, FuncSignature::build()); + cc.invoke(&call_vector_vector_ww_2121, &vector_vector_ww, FuncSignature::build()); setArg(call_sew_2122, 0, reinterpret_cast(this)); setRet(call_sew_2122, 0, ret_val_sew_2122); setArg(call_vector_vector_ww_2121, 0, V); @@ -52471,11 +52497,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2123 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2123, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2123, 32, false) - , traits::vstart); + auto tmp2123 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2123, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2123, traits::vstart); } cc.bind(label_merge); } @@ -52582,7 +52606,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_ww_2128_arg10 = ret_val_sew_2129; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_ww_2128, &vector_imm_ww, FuncSignature::build()); + cc.invoke(&call_vector_imm_ww_2128, &vector_imm_ww, FuncSignature::build()); setArg(call_sew_2129, 0, reinterpret_cast(this)); setRet(call_sew_2129, 0, ret_val_sew_2129); setArg(call_vector_imm_ww_2128, 0, V); @@ -52599,11 +52623,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2130 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2130, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2130, 32, false) - , traits::vstart); + auto tmp2130 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2130, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2130, traits::vstart); } cc.bind(label_merge); } @@ -52715,7 +52737,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_ww_2136_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_ww_2136_arg10 = ret_val_sew_2137; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_ww_2136, &vector_vector_ww, FuncSignature::build()); + cc.invoke(&call_vector_vector_ww_2136, &vector_vector_ww, FuncSignature::build()); setArg(call_sew_2137, 0, reinterpret_cast(this)); setRet(call_sew_2137, 0, ret_val_sew_2137); setArg(call_vector_vector_ww_2136, 0, V); @@ -52732,11 +52754,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2138 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2138, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2138, 32, false) - , traits::vstart); + auto tmp2138 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2138, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2138, traits::vstart); } cc.bind(label_merge); } @@ -52843,7 +52863,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_ww_2143_arg10 = ret_val_sew_2144; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_ww_2143, &vector_imm_ww, FuncSignature::build()); + cc.invoke(&call_vector_imm_ww_2143, &vector_imm_ww, FuncSignature::build()); setArg(call_sew_2144, 0, reinterpret_cast(this)); setRet(call_sew_2144, 0, ret_val_sew_2144); setArg(call_vector_imm_ww_2143, 0, V); @@ -52860,11 +52880,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2145 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2145, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2145, 32, false) - , traits::vstart); + auto tmp2145 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2145, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2145, traits::vstart); } cc.bind(label_merge); } @@ -52976,7 +52994,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_ww_2151_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_ww_2151_arg10 = ret_val_sew_2152; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_ww_2151, &vector_vector_ww, FuncSignature::build()); + cc.invoke(&call_vector_vector_ww_2151, &vector_vector_ww, FuncSignature::build()); setArg(call_sew_2152, 0, reinterpret_cast(this)); setRet(call_sew_2152, 0, ret_val_sew_2152); setArg(call_vector_vector_ww_2151, 0, V); @@ -52993,11 +53011,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2153 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2153, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2153, 32, false) - , traits::vstart); + auto tmp2153 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2153, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2153, traits::vstart); } cc.bind(label_merge); } @@ -53104,7 +53120,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_ww_2158_arg10 = ret_val_sew_2159; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_ww_2158, &vector_imm_ww, FuncSignature::build()); + cc.invoke(&call_vector_imm_ww_2158, &vector_imm_ww, FuncSignature::build()); setArg(call_sew_2159, 0, reinterpret_cast(this)); setRet(call_sew_2159, 0, ret_val_sew_2159); setArg(call_vector_imm_ww_2158, 0, V); @@ -53121,11 +53137,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2160 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2160, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2160, 32, false) - , traits::vstart); + auto tmp2160 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2160, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2160, traits::vstart); } cc.bind(label_merge); } @@ -53237,7 +53251,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_ww_2166_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_ww_2166_arg10 = ret_val_sew_2167; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_ww_2166, &vector_vector_ww, FuncSignature::build()); + cc.invoke(&call_vector_vector_ww_2166, &vector_vector_ww, FuncSignature::build()); setArg(call_sew_2167, 0, reinterpret_cast(this)); setRet(call_sew_2167, 0, ret_val_sew_2167); setArg(call_vector_vector_ww_2166, 0, V); @@ -53254,11 +53268,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2168 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2168, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2168, 32, false) - , traits::vstart); + auto tmp2168 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2168, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2168, traits::vstart); } cc.bind(label_merge); } @@ -53365,7 +53377,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_ww_2173_arg10 = ret_val_sew_2174; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_ww_2173, &vector_imm_ww, FuncSignature::build()); + cc.invoke(&call_vector_imm_ww_2173, &vector_imm_ww, FuncSignature::build()); setArg(call_sew_2174, 0, reinterpret_cast(this)); setRet(call_sew_2174, 0, ret_val_sew_2174); setArg(call_vector_imm_ww_2173, 0, V); @@ -53382,11 +53394,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2175 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2175, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2175, 32, false) - , traits::vstart); + auto tmp2175 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2175, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2175, traits::vstart); } cc.bind(label_merge); } @@ -53438,15 +53448,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2176, 0, ret_val_get_sew_pow_2176); auto tmp2177 = get_reg(cc, 8, false); mov(cc, tmp2177, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2177, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2177, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2178; x86::Gp ret_val_get_lmul_pow_2178 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2178, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2178; setArg(call_get_lmul_pow_2178, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2178, 0, ret_val_get_lmul_pow_2178); - auto SEW_target = gen_operation(cc, udiv, SEW, 2); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 2)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 1); { auto label_merge = cc.newLabel(); @@ -53494,7 +53505,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_extend_2181_arg4 = load_reg_from_mem(jh, traits::vtype); auto vector_extend_2181_arg8 = SEW_pow; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_extend_2181, &vector_extend, FuncSignature::build()); + cc.invoke(&call_vector_extend_2181, &vector_extend, FuncSignature::build()); setArg(call_vector_extend_2181, 0, V); setArg(call_vector_extend_2181, 1, 6); setArg(call_vector_extend_2181, 2, vector_extend_2181_arg2); @@ -53508,11 +53519,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2182 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2182, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2182, 32, false) - , traits::vstart); + auto tmp2182 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2182, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2182, traits::vstart); } cc.bind(label_merge); } @@ -53563,15 +53572,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2183, 0, ret_val_get_sew_pow_2183); auto tmp2184 = get_reg(cc, 8, false); mov(cc, tmp2184, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2184, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2184, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2185; x86::Gp ret_val_get_lmul_pow_2185 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2185, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2185; setArg(call_get_lmul_pow_2185, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2185, 0, ret_val_get_lmul_pow_2185); - auto SEW_target = gen_operation(cc, udiv, SEW, 2); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 2)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 1); { auto label_merge = cc.newLabel(); @@ -53619,7 +53629,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_extend_2188_arg4 = load_reg_from_mem(jh, traits::vtype); auto vector_extend_2188_arg8 = SEW_pow; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_extend_2188, &vector_extend, FuncSignature::build()); + cc.invoke(&call_vector_extend_2188, &vector_extend, FuncSignature::build()); setArg(call_vector_extend_2188, 0, V); setArg(call_vector_extend_2188, 1, 7); setArg(call_vector_extend_2188, 2, vector_extend_2188_arg2); @@ -53633,11 +53643,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2189 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2189, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2189, 32, false) - , traits::vstart); + auto tmp2189 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2189, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2189, traits::vstart); } cc.bind(label_merge); } @@ -53688,15 +53696,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2190, 0, ret_val_get_sew_pow_2190); auto tmp2191 = get_reg(cc, 8, false); mov(cc, tmp2191, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2191, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2191, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2192; x86::Gp ret_val_get_lmul_pow_2192 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2192, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2192; setArg(call_get_lmul_pow_2192, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2192, 0, ret_val_get_lmul_pow_2192); - auto SEW_target = gen_operation(cc, udiv, SEW, 4); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 4)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 2); { auto label_merge = cc.newLabel(); @@ -53744,7 +53753,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_extend_2195_arg4 = load_reg_from_mem(jh, traits::vtype); auto vector_extend_2195_arg8 = SEW_pow; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_extend_2195, &vector_extend, FuncSignature::build()); + cc.invoke(&call_vector_extend_2195, &vector_extend, FuncSignature::build()); setArg(call_vector_extend_2195, 0, V); setArg(call_vector_extend_2195, 1, 4); setArg(call_vector_extend_2195, 2, vector_extend_2195_arg2); @@ -53758,11 +53767,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2196 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2196, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2196, 32, false) - , traits::vstart); + auto tmp2196 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2196, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2196, traits::vstart); } cc.bind(label_merge); } @@ -53813,15 +53820,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2197, 0, ret_val_get_sew_pow_2197); auto tmp2198 = get_reg(cc, 8, false); mov(cc, tmp2198, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2198, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2198, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2199; x86::Gp ret_val_get_lmul_pow_2199 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2199, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2199; setArg(call_get_lmul_pow_2199, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2199, 0, ret_val_get_lmul_pow_2199); - auto SEW_target = gen_operation(cc, udiv, SEW, 4); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 4)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 2); { auto label_merge = cc.newLabel(); @@ -53869,7 +53877,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_extend_2202_arg4 = load_reg_from_mem(jh, traits::vtype); auto vector_extend_2202_arg8 = SEW_pow; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_extend_2202, &vector_extend, FuncSignature::build()); + cc.invoke(&call_vector_extend_2202, &vector_extend, FuncSignature::build()); setArg(call_vector_extend_2202, 0, V); setArg(call_vector_extend_2202, 1, 5); setArg(call_vector_extend_2202, 2, vector_extend_2202_arg2); @@ -53883,11 +53891,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2203 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2203, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2203, 32, false) - , traits::vstart); + auto tmp2203 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2203, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2203, traits::vstart); } cc.bind(label_merge); } @@ -53938,15 +53944,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2204, 0, ret_val_get_sew_pow_2204); auto tmp2205 = get_reg(cc, 8, false); mov(cc, tmp2205, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2205, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2205, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2206; x86::Gp ret_val_get_lmul_pow_2206 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2206, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2206; setArg(call_get_lmul_pow_2206, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2206, 0, ret_val_get_lmul_pow_2206); - auto SEW_target = gen_operation(cc, udiv, SEW, 8); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 8)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 3); { auto label_merge = cc.newLabel(); @@ -53994,7 +54001,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_extend_2209_arg4 = load_reg_from_mem(jh, traits::vtype); auto vector_extend_2209_arg8 = SEW_pow; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_extend_2209, &vector_extend, FuncSignature::build()); + cc.invoke(&call_vector_extend_2209, &vector_extend, FuncSignature::build()); setArg(call_vector_extend_2209, 0, V); setArg(call_vector_extend_2209, 1, 2); setArg(call_vector_extend_2209, 2, vector_extend_2209_arg2); @@ -54008,11 +54015,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2210 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2210, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2210, 32, false) - , traits::vstart); + auto tmp2210 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2210, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2210, traits::vstart); } cc.bind(label_merge); } @@ -54063,15 +54068,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2211, 0, ret_val_get_sew_pow_2211); auto tmp2212 = get_reg(cc, 8, false); mov(cc, tmp2212, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2212, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2212, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2213; x86::Gp ret_val_get_lmul_pow_2213 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2213, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2213; setArg(call_get_lmul_pow_2213, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2213, 0, ret_val_get_lmul_pow_2213); - auto SEW_target = gen_operation(cc, udiv, SEW, 8); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 8)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 3); { auto label_merge = cc.newLabel(); @@ -54119,7 +54125,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_extend_2216_arg4 = load_reg_from_mem(jh, traits::vtype); auto vector_extend_2216_arg8 = SEW_pow; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_extend_2216, &vector_extend, FuncSignature::build()); + cc.invoke(&call_vector_extend_2216, &vector_extend, FuncSignature::build()); setArg(call_vector_extend_2216, 0, V); setArg(call_vector_extend_2216, 1, 3); setArg(call_vector_extend_2216, 2, vector_extend_2216_arg2); @@ -54133,11 +54139,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2217 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2217, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2217, 32, false) - , traits::vstart); + auto tmp2217 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2217, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2217, traits::vstart); } cc.bind(label_merge); } @@ -54213,7 +54217,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_carry_2219_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_carry_2219_arg9 = ret_val_sew_2220; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_carry_2219, &vector_vector_carry, FuncSignature::build()); + cc.invoke(&call_vector_vector_carry_2219, &vector_vector_carry, FuncSignature::build()); setArg(call_sew_2220, 0, reinterpret_cast(this)); setRet(call_sew_2220, 0, ret_val_sew_2220); setArg(call_vector_vector_carry_2219, 0, V); @@ -54230,11 +54234,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2221 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2221, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2221, 32, false) - , traits::vstart); + auto tmp2221 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2221, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2221, traits::vstart); } cc.bind(label_merge); } @@ -54315,7 +54317,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_carry_2224_arg9 = ret_val_sew_2225; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_carry_2224, &vector_imm_carry, FuncSignature::build()); + cc.invoke(&call_vector_imm_carry_2224, &vector_imm_carry, FuncSignature::build()); setArg(call_sew_2225, 0, reinterpret_cast(this)); setRet(call_sew_2225, 0, ret_val_sew_2225); setArg(call_vector_imm_carry_2224, 0, V); @@ -54332,11 +54334,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2226 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2226, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2226, 32, false) - , traits::vstart); + auto tmp2226 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2226, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2226, traits::vstart); } cc.bind(label_merge); } @@ -54411,7 +54411,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_carry_2228_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_carry_2228_arg9 = ret_val_sew_2229; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_carry_2228, &vector_imm_carry, FuncSignature::build()); + cc.invoke(&call_vector_imm_carry_2228, &vector_imm_carry, FuncSignature::build()); setArg(call_sew_2229, 0, reinterpret_cast(this)); setRet(call_sew_2229, 0, ret_val_sew_2229); setArg(call_vector_imm_carry_2228, 0, V); @@ -54428,11 +54428,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2230 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2230, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2230, 32, false) - , traits::vstart); + auto tmp2230 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2230, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2230, traits::vstart); } cc.bind(label_merge); } @@ -54507,7 +54505,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto carry_vector_vector_op_2232_arg4 = load_reg_from_mem(jh, traits::vtype); auto carry_vector_vector_op_2232_arg9 = ret_val_sew_2233; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_carry_vector_vector_op_2232, &carry_vector_vector_op, FuncSignature::build()); + cc.invoke(&call_carry_vector_vector_op_2232, &carry_vector_vector_op, FuncSignature::build()); setArg(call_sew_2233, 0, reinterpret_cast(this)); setRet(call_sew_2233, 0, ret_val_sew_2233); setArg(call_carry_vector_vector_op_2232, 0, V); @@ -54523,11 +54521,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2234 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2234, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2234, 32, false) - , traits::vstart); + auto tmp2234 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2234, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2234, traits::vstart); } cc.bind(label_merge); } @@ -54607,7 +54603,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto carry_vector_imm_op_2237_arg9 = ret_val_sew_2238; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_carry_vector_imm_op_2237, &carry_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_carry_vector_imm_op_2237, &carry_vector_imm_op, FuncSignature::build()); setArg(call_sew_2238, 0, reinterpret_cast(this)); setRet(call_sew_2238, 0, ret_val_sew_2238); setArg(call_carry_vector_imm_op_2237, 0, V); @@ -54623,11 +54619,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2239 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2239, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2239, 32, false) - , traits::vstart); + auto tmp2239 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2239, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2239, traits::vstart); } cc.bind(label_merge); } @@ -54702,7 +54696,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto carry_vector_imm_op_2241_arg4 = load_reg_from_mem(jh, traits::vtype); auto carry_vector_imm_op_2241_arg9 = ret_val_sew_2242; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_carry_vector_imm_op_2241, &carry_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_carry_vector_imm_op_2241, &carry_vector_imm_op, FuncSignature::build()); setArg(call_sew_2242, 0, reinterpret_cast(this)); setRet(call_sew_2242, 0, ret_val_sew_2242); setArg(call_carry_vector_imm_op_2241, 0, V); @@ -54718,11 +54712,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2243 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2243, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2243, 32, false) - , traits::vstart); + auto tmp2243 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2243, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2243, traits::vstart); } cc.bind(label_merge); } @@ -54797,7 +54789,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto carry_vector_vector_op_2245_arg4 = load_reg_from_mem(jh, traits::vtype); auto carry_vector_vector_op_2245_arg9 = ret_val_sew_2246; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_carry_vector_vector_op_2245, &carry_vector_vector_op, FuncSignature::build()); + cc.invoke(&call_carry_vector_vector_op_2245, &carry_vector_vector_op, FuncSignature::build()); setArg(call_sew_2246, 0, reinterpret_cast(this)); setRet(call_sew_2246, 0, ret_val_sew_2246); setArg(call_carry_vector_vector_op_2245, 0, V); @@ -54813,11 +54805,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2247 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2247, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2247, 32, false) - , traits::vstart); + auto tmp2247 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2247, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2247, traits::vstart); } cc.bind(label_merge); } @@ -54897,7 +54887,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto carry_vector_imm_op_2250_arg9 = ret_val_sew_2251; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_carry_vector_imm_op_2250, &carry_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_carry_vector_imm_op_2250, &carry_vector_imm_op, FuncSignature::build()); setArg(call_sew_2251, 0, reinterpret_cast(this)); setRet(call_sew_2251, 0, ret_val_sew_2251); setArg(call_carry_vector_imm_op_2250, 0, V); @@ -54913,11 +54903,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2252 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2252, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2252, 32, false) - , traits::vstart); + auto tmp2252 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2252, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2252, traits::vstart); } cc.bind(label_merge); } @@ -54992,7 +54980,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto carry_vector_imm_op_2254_arg4 = load_reg_from_mem(jh, traits::vtype); auto carry_vector_imm_op_2254_arg9 = ret_val_sew_2255; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_carry_vector_imm_op_2254, &carry_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_carry_vector_imm_op_2254, &carry_vector_imm_op, FuncSignature::build()); setArg(call_sew_2255, 0, reinterpret_cast(this)); setRet(call_sew_2255, 0, ret_val_sew_2255); setArg(call_carry_vector_imm_op_2254, 0, V); @@ -55008,11 +54996,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2256 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2256, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2256, 32, false) - , traits::vstart); + auto tmp2256 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2256, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2256, traits::vstart); } cc.bind(label_merge); } @@ -55088,7 +55074,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_carry_2258_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_carry_2258_arg9 = ret_val_sew_2259; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_carry_2258, &vector_vector_carry, FuncSignature::build()); + cc.invoke(&call_vector_vector_carry_2258, &vector_vector_carry, FuncSignature::build()); setArg(call_sew_2259, 0, reinterpret_cast(this)); setRet(call_sew_2259, 0, ret_val_sew_2259); setArg(call_vector_vector_carry_2258, 0, V); @@ -55105,11 +55091,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2260 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2260, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2260, 32, false) - , traits::vstart); + auto tmp2260 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2260, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2260, traits::vstart); } cc.bind(label_merge); } @@ -55190,7 +55174,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_carry_2263_arg9 = ret_val_sew_2264; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_carry_2263, &vector_imm_carry, FuncSignature::build()); + cc.invoke(&call_vector_imm_carry_2263, &vector_imm_carry, FuncSignature::build()); setArg(call_sew_2264, 0, reinterpret_cast(this)); setRet(call_sew_2264, 0, ret_val_sew_2264); setArg(call_vector_imm_carry_2263, 0, V); @@ -55207,11 +55191,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2265 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2265, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2265, 32, false) - , traits::vstart); + auto tmp2265 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2265, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2265, traits::vstart); } cc.bind(label_merge); } @@ -55286,7 +55268,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto carry_vector_vector_op_2267_arg4 = load_reg_from_mem(jh, traits::vtype); auto carry_vector_vector_op_2267_arg9 = ret_val_sew_2268; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_carry_vector_vector_op_2267, &carry_vector_vector_op, FuncSignature::build()); + cc.invoke(&call_carry_vector_vector_op_2267, &carry_vector_vector_op, FuncSignature::build()); setArg(call_sew_2268, 0, reinterpret_cast(this)); setRet(call_sew_2268, 0, ret_val_sew_2268); setArg(call_carry_vector_vector_op_2267, 0, V); @@ -55302,11 +55284,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2269 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2269, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2269, 32, false) - , traits::vstart); + auto tmp2269 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2269, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2269, traits::vstart); } cc.bind(label_merge); } @@ -55386,7 +55366,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto carry_vector_imm_op_2272_arg9 = ret_val_sew_2273; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_carry_vector_imm_op_2272, &carry_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_carry_vector_imm_op_2272, &carry_vector_imm_op, FuncSignature::build()); setArg(call_sew_2273, 0, reinterpret_cast(this)); setRet(call_sew_2273, 0, ret_val_sew_2273); setArg(call_carry_vector_imm_op_2272, 0, V); @@ -55402,11 +55382,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2274 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2274, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2274, 32, false) - , traits::vstart); + auto tmp2274 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2274, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2274, traits::vstart); } cc.bind(label_merge); } @@ -55481,7 +55459,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto carry_vector_vector_op_2276_arg4 = load_reg_from_mem(jh, traits::vtype); auto carry_vector_vector_op_2276_arg9 = ret_val_sew_2277; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_carry_vector_vector_op_2276, &carry_vector_vector_op, FuncSignature::build()); + cc.invoke(&call_carry_vector_vector_op_2276, &carry_vector_vector_op, FuncSignature::build()); setArg(call_sew_2277, 0, reinterpret_cast(this)); setRet(call_sew_2277, 0, ret_val_sew_2277); setArg(call_carry_vector_vector_op_2276, 0, V); @@ -55497,11 +55475,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2278 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2278, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2278, 32, false) - , traits::vstart); + auto tmp2278 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2278, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2278, traits::vstart); } cc.bind(label_merge); } @@ -55581,7 +55557,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto carry_vector_imm_op_2281_arg9 = ret_val_sew_2282; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_carry_vector_imm_op_2281, &carry_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_carry_vector_imm_op_2281, &carry_vector_imm_op, FuncSignature::build()); setArg(call_sew_2282, 0, reinterpret_cast(this)); setRet(call_sew_2282, 0, ret_val_sew_2282); setArg(call_carry_vector_imm_op_2281, 0, V); @@ -55597,11 +55573,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2283 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2283, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2283, 32, false) - , traits::vstart); + auto tmp2283 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2283, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2283, traits::vstart); } cc.bind(label_merge); } @@ -55679,7 +55653,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_op_2285_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_op_2285_arg10 = ret_val_sew_2286; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2285, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2285, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2286, 0, reinterpret_cast(this)); setRet(call_sew_2286, 0, ret_val_sew_2286); setArg(call_vector_imm_op_2285, 0, V); @@ -55696,11 +55670,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2287 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2287, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2287, 32, false) - , traits::vstart); + auto tmp2287 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2287, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2287, traits::vstart); } cc.bind(label_merge); } @@ -55778,7 +55750,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2289_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2289_arg10 = ret_val_sew_2290; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2289, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2289, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2290, 0, reinterpret_cast(this)); setRet(call_sew_2290, 0, ret_val_sew_2290); setArg(call_vector_vector_op_2289, 0, V); @@ -55795,11 +55767,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2291 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2291, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2291, 32, false) - , traits::vstart); + auto tmp2291 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2291, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2291, traits::vstart); } cc.bind(label_merge); } @@ -55882,7 +55852,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2294_arg10 = ret_val_sew_2295; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2294, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2294, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2295, 0, reinterpret_cast(this)); setRet(call_sew_2295, 0, ret_val_sew_2295); setArg(call_vector_imm_op_2294, 0, V); @@ -55899,11 +55869,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2296 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2296, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2296, 32, false) - , traits::vstart); + auto tmp2296 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2296, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2296, traits::vstart); } cc.bind(label_merge); } @@ -55981,7 +55949,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_op_2298_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_op_2298_arg10 = ret_val_sew_2299; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2298, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2298, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2299, 0, reinterpret_cast(this)); setRet(call_sew_2299, 0, ret_val_sew_2299); setArg(call_vector_imm_op_2298, 0, V); @@ -55998,11 +55966,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2300 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2300, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2300, 32, false) - , traits::vstart); + auto tmp2300 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2300, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2300, traits::vstart); } cc.bind(label_merge); } @@ -56080,7 +56046,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2302_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2302_arg10 = ret_val_sew_2303; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2302, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2302, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2303, 0, reinterpret_cast(this)); setRet(call_sew_2303, 0, ret_val_sew_2303); setArg(call_vector_vector_op_2302, 0, V); @@ -56097,11 +56063,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2304 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2304, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2304, 32, false) - , traits::vstart); + auto tmp2304 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2304, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2304, traits::vstart); } cc.bind(label_merge); } @@ -56184,7 +56148,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2307_arg10 = ret_val_sew_2308; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2307, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2307, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2308, 0, reinterpret_cast(this)); setRet(call_sew_2308, 0, ret_val_sew_2308); setArg(call_vector_imm_op_2307, 0, V); @@ -56201,11 +56165,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2309 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2309, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2309, 32, false) - , traits::vstart); + auto tmp2309 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2309, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2309, traits::vstart); } cc.bind(label_merge); } @@ -56283,7 +56245,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_op_2311_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_op_2311_arg10 = ret_val_sew_2312; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2311, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2311, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2312, 0, reinterpret_cast(this)); setRet(call_sew_2312, 0, ret_val_sew_2312); setArg(call_vector_imm_op_2311, 0, V); @@ -56300,11 +56262,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2313 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2313, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2313, 32, false) - , traits::vstart); + auto tmp2313 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2313, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2313, traits::vstart); } cc.bind(label_merge); } @@ -56382,7 +56342,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2315_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2315_arg10 = ret_val_sew_2316; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2315, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2315, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2316, 0, reinterpret_cast(this)); setRet(call_sew_2316, 0, ret_val_sew_2316); setArg(call_vector_vector_op_2315, 0, V); @@ -56399,11 +56359,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2317 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2317, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2317, 32, false) - , traits::vstart); + auto tmp2317 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2317, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2317, traits::vstart); } cc.bind(label_merge); } @@ -56486,7 +56444,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2320_arg10 = ret_val_sew_2321; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2320, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2320, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2321, 0, reinterpret_cast(this)); setRet(call_sew_2321, 0, ret_val_sew_2321); setArg(call_vector_imm_op_2320, 0, V); @@ -56503,11 +56461,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2322 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2322, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2322, 32, false) - , traits::vstart); + auto tmp2322 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2322, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2322, traits::vstart); } cc.bind(label_merge); } @@ -56585,7 +56541,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_op_2324_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_op_2324_arg10 = ret_val_sew_2325; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2324, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2324, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2325, 0, reinterpret_cast(this)); setRet(call_sew_2325, 0, ret_val_sew_2325); setArg(call_vector_imm_op_2324, 0, V); @@ -56602,11 +56558,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2326 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2326, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2326, 32, false) - , traits::vstart); + auto tmp2326 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2326, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2326, traits::vstart); } cc.bind(label_merge); } @@ -56684,7 +56638,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2328_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2328_arg10 = ret_val_sew_2329; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2328, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2328, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2329, 0, reinterpret_cast(this)); setRet(call_sew_2329, 0, ret_val_sew_2329); setArg(call_vector_vector_op_2328, 0, V); @@ -56701,11 +56655,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2330 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2330, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2330, 32, false) - , traits::vstart); + auto tmp2330 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2330, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2330, traits::vstart); } cc.bind(label_merge); } @@ -56788,7 +56740,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); auto vector_imm_op_2333_arg10 = ret_val_sew_2334; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2333, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2333, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2334, 0, reinterpret_cast(this)); setRet(call_sew_2334, 0, ret_val_sew_2334); setArg(call_vector_imm_op_2333, 0, V); @@ -56805,11 +56757,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2335 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2335, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2335, 32, false) - , traits::vstart); + auto tmp2335 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2335, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2335, traits::vstart); } cc.bind(label_merge); } @@ -56887,7 +56837,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_op_2337_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_op_2337_arg10 = ret_val_sew_2338; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2337, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2337, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2338, 0, reinterpret_cast(this)); setRet(call_sew_2338, 0, ret_val_sew_2338); setArg(call_vector_imm_op_2337, 0, V); @@ -56904,11 +56854,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2339 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2339, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2339, 32, false) - , traits::vstart); + auto tmp2339 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2339, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2339, traits::vstart); } cc.bind(label_merge); } @@ -56986,7 +56934,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2341_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2341_arg10 = ret_val_sew_2342; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2341, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2341, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2342, 0, reinterpret_cast(this)); setRet(call_sew_2342, 0, ret_val_sew_2342); setArg(call_vector_vector_op_2341, 0, V); @@ -57003,11 +56951,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2343 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2343, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2343, 32, false) - , traits::vstart); + auto tmp2343 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2343, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2343, traits::vstart); } cc.bind(label_merge); } @@ -57090,7 +57036,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); auto vector_imm_op_2346_arg10 = ret_val_sew_2347; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2346, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2346, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2347, 0, reinterpret_cast(this)); setRet(call_sew_2347, 0, ret_val_sew_2347); setArg(call_vector_imm_op_2346, 0, V); @@ -57107,11 +57053,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2348 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2348, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2348, 32, false) - , traits::vstart); + auto tmp2348 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2348, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2348, traits::vstart); } cc.bind(label_merge); } @@ -57189,7 +57133,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_op_2350_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_op_2350_arg10 = ret_val_sew_2351; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2350, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2350, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2351, 0, reinterpret_cast(this)); setRet(call_sew_2351, 0, ret_val_sew_2351); setArg(call_vector_imm_op_2350, 0, V); @@ -57206,11 +57150,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2352 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2352, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2352, 32, false) - , traits::vstart); + auto tmp2352 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2352, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2352, traits::vstart); } cc.bind(label_merge); } @@ -57288,7 +57230,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2354_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2354_arg10 = ret_val_sew_2355; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2354, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2354, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2355, 0, reinterpret_cast(this)); setRet(call_sew_2355, 0, ret_val_sew_2355); setArg(call_vector_vector_op_2354, 0, V); @@ -57305,11 +57247,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2356 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2356, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2356, 32, false) - , traits::vstart); + auto tmp2356 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2356, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2356, traits::vstart); } cc.bind(label_merge); } @@ -57392,7 +57332,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); auto vector_imm_op_2359_arg10 = ret_val_sew_2360; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2359, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2359, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2360, 0, reinterpret_cast(this)); setRet(call_sew_2360, 0, ret_val_sew_2360); setArg(call_vector_imm_op_2359, 0, V); @@ -57409,11 +57349,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2361 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2361, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2361, 32, false) - , traits::vstart); + auto tmp2361 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2361, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2361, traits::vstart); } cc.bind(label_merge); } @@ -57524,7 +57462,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_vw_2367_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_vw_2367_arg10 = ret_val_sew_2368; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_vw_2367, &vector_imm_vw, FuncSignature::build()); + cc.invoke(&call_vector_imm_vw_2367, &vector_imm_vw, FuncSignature::build()); setArg(call_sew_2368, 0, reinterpret_cast(this)); setRet(call_sew_2368, 0, ret_val_sew_2368); setArg(call_vector_imm_vw_2367, 0, V); @@ -57541,11 +57479,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2369 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2369, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2369, 32, false) - , traits::vstart); + auto tmp2369 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2369, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2369, traits::vstart); } cc.bind(label_merge); } @@ -57656,7 +57592,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_vw_2375_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_vw_2375_arg10 = ret_val_sew_2376; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_vw_2375, &vector_vector_vw, FuncSignature::build()); + cc.invoke(&call_vector_vector_vw_2375, &vector_vector_vw, FuncSignature::build()); setArg(call_sew_2376, 0, reinterpret_cast(this)); setRet(call_sew_2376, 0, ret_val_sew_2376); setArg(call_vector_vector_vw_2375, 0, V); @@ -57673,11 +57609,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2377 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2377, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2377, 32, false) - , traits::vstart); + auto tmp2377 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2377, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2377, traits::vstart); } cc.bind(label_merge); } @@ -57795,7 +57729,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); auto vector_imm_vw_2383_arg10 = ret_val_sew_2384; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_vw_2383, &vector_imm_vw, FuncSignature::build()); + cc.invoke(&call_vector_imm_vw_2383, &vector_imm_vw, FuncSignature::build()); setArg(call_sew_2384, 0, reinterpret_cast(this)); setRet(call_sew_2384, 0, ret_val_sew_2384); setArg(call_vector_imm_vw_2383, 0, V); @@ -57812,11 +57746,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2385 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2385, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2385, 32, false) - , traits::vstart); + auto tmp2385 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2385, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2385, traits::vstart); } cc.bind(label_merge); } @@ -57928,7 +57860,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_vw_2391_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_vw_2391_arg10 = ret_val_sew_2392; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_vw_2391, &vector_imm_vw, FuncSignature::build()); + cc.invoke(&call_vector_imm_vw_2391, &vector_imm_vw, FuncSignature::build()); setArg(call_sew_2392, 0, reinterpret_cast(this)); setRet(call_sew_2392, 0, ret_val_sew_2392); setArg(call_vector_imm_vw_2391, 0, V); @@ -57945,11 +57877,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2393 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2393, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2393, 32, false) - , traits::vstart); + auto tmp2393 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2393, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2393, traits::vstart); } cc.bind(label_merge); } @@ -58060,7 +57990,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_vw_2399_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_vw_2399_arg10 = ret_val_sew_2400; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_vw_2399, &vector_vector_vw, FuncSignature::build()); + cc.invoke(&call_vector_vector_vw_2399, &vector_vector_vw, FuncSignature::build()); setArg(call_sew_2400, 0, reinterpret_cast(this)); setRet(call_sew_2400, 0, ret_val_sew_2400); setArg(call_vector_vector_vw_2399, 0, V); @@ -58077,11 +58007,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2401 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2401, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2401, 32, false) - , traits::vstart); + auto tmp2401 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2401, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2401, traits::vstart); } cc.bind(label_merge); } @@ -58199,7 +58127,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); auto vector_imm_vw_2407_arg10 = ret_val_sew_2408; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_vw_2407, &vector_imm_vw, FuncSignature::build()); + cc.invoke(&call_vector_imm_vw_2407, &vector_imm_vw, FuncSignature::build()); setArg(call_sew_2408, 0, reinterpret_cast(this)); setRet(call_sew_2408, 0, ret_val_sew_2408); setArg(call_vector_imm_vw_2407, 0, V); @@ -58216,11 +58144,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2409 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2409, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2409, 32, false) - , traits::vstart); + auto tmp2409 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2409, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2409, traits::vstart); } cc.bind(label_merge); } @@ -58297,7 +58223,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_imm_op_2411_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_imm_op_2411_arg10 = ret_val_sew_2412; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2411, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2411, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2412, 0, reinterpret_cast(this)); setRet(call_sew_2412, 0, ret_val_sew_2412); setArg(call_mask_vector_imm_op_2411, 0, V); @@ -58314,11 +58240,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2413 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2413, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2413, 32, false) - , traits::vstart); + auto tmp2413 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2413, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2413, traits::vstart); } cc.bind(label_merge); } @@ -58394,7 +58318,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_vector_op_2415_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_vector_op_2415_arg10 = ret_val_sew_2416; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_vector_op_2415, &mask_vector_vector_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_vector_op_2415, &mask_vector_vector_op, FuncSignature::build()); setArg(call_sew_2416, 0, reinterpret_cast(this)); setRet(call_sew_2416, 0, ret_val_sew_2416); setArg(call_mask_vector_vector_op_2415, 0, V); @@ -58411,11 +58335,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2417 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2417, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2417, 32, false) - , traits::vstart); + auto tmp2417 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2417, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2417, traits::vstart); } cc.bind(label_merge); } @@ -58496,7 +58418,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto mask_vector_imm_op_2420_arg10 = ret_val_sew_2421; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2420, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2420, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2421, 0, reinterpret_cast(this)); setRet(call_sew_2421, 0, ret_val_sew_2421); setArg(call_mask_vector_imm_op_2420, 0, V); @@ -58513,11 +58435,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2422 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2422, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2422, 32, false) - , traits::vstart); + auto tmp2422 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2422, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2422, traits::vstart); } cc.bind(label_merge); } @@ -58593,7 +58513,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_imm_op_2424_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_imm_op_2424_arg10 = ret_val_sew_2425; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2424, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2424, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2425, 0, reinterpret_cast(this)); setRet(call_sew_2425, 0, ret_val_sew_2425); setArg(call_mask_vector_imm_op_2424, 0, V); @@ -58610,11 +58530,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2426 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2426, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2426, 32, false) - , traits::vstart); + auto tmp2426 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2426, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2426, traits::vstart); } cc.bind(label_merge); } @@ -58690,7 +58608,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_vector_op_2428_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_vector_op_2428_arg10 = ret_val_sew_2429; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_vector_op_2428, &mask_vector_vector_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_vector_op_2428, &mask_vector_vector_op, FuncSignature::build()); setArg(call_sew_2429, 0, reinterpret_cast(this)); setRet(call_sew_2429, 0, ret_val_sew_2429); setArg(call_mask_vector_vector_op_2428, 0, V); @@ -58707,11 +58625,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2430 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2430, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2430, 32, false) - , traits::vstart); + auto tmp2430 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2430, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2430, traits::vstart); } cc.bind(label_merge); } @@ -58792,7 +58708,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto mask_vector_imm_op_2433_arg10 = ret_val_sew_2434; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2433, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2433, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2434, 0, reinterpret_cast(this)); setRet(call_sew_2434, 0, ret_val_sew_2434); setArg(call_mask_vector_imm_op_2433, 0, V); @@ -58809,11 +58725,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2435 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2435, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2435, 32, false) - , traits::vstart); + auto tmp2435 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2435, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2435, traits::vstart); } cc.bind(label_merge); } @@ -58889,7 +58803,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_vector_op_2437_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_vector_op_2437_arg10 = ret_val_sew_2438; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_vector_op_2437, &mask_vector_vector_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_vector_op_2437, &mask_vector_vector_op, FuncSignature::build()); setArg(call_sew_2438, 0, reinterpret_cast(this)); setRet(call_sew_2438, 0, ret_val_sew_2438); setArg(call_mask_vector_vector_op_2437, 0, V); @@ -58906,11 +58820,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2439 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2439, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2439, 32, false) - , traits::vstart); + auto tmp2439 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2439, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2439, traits::vstart); } cc.bind(label_merge); } @@ -58991,7 +58903,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto mask_vector_imm_op_2442_arg10 = ret_val_sew_2443; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2442, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2442, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2443, 0, reinterpret_cast(this)); setRet(call_sew_2443, 0, ret_val_sew_2443); setArg(call_mask_vector_imm_op_2442, 0, V); @@ -59008,11 +58920,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2444 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2444, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2444, 32, false) - , traits::vstart); + auto tmp2444 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2444, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2444, traits::vstart); } cc.bind(label_merge); } @@ -59088,7 +58998,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_vector_op_2446_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_vector_op_2446_arg10 = ret_val_sew_2447; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_vector_op_2446, &mask_vector_vector_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_vector_op_2446, &mask_vector_vector_op, FuncSignature::build()); setArg(call_sew_2447, 0, reinterpret_cast(this)); setRet(call_sew_2447, 0, ret_val_sew_2447); setArg(call_mask_vector_vector_op_2446, 0, V); @@ -59105,11 +59015,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2448 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2448, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2448, 32, false) - , traits::vstart); + auto tmp2448 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2448, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2448, traits::vstart); } cc.bind(label_merge); } @@ -59190,7 +59098,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto mask_vector_imm_op_2451_arg10 = ret_val_sew_2452; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2451, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2451, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2452, 0, reinterpret_cast(this)); setRet(call_sew_2452, 0, ret_val_sew_2452); setArg(call_mask_vector_imm_op_2451, 0, V); @@ -59207,11 +59115,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2453 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2453, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2453, 32, false) - , traits::vstart); + auto tmp2453 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2453, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2453, traits::vstart); } cc.bind(label_merge); } @@ -59287,7 +59193,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_imm_op_2455_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_imm_op_2455_arg10 = ret_val_sew_2456; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2455, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2455, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2456, 0, reinterpret_cast(this)); setRet(call_sew_2456, 0, ret_val_sew_2456); setArg(call_mask_vector_imm_op_2455, 0, V); @@ -59304,11 +59210,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2457 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2457, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2457, 32, false) - , traits::vstart); + auto tmp2457 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2457, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2457, traits::vstart); } cc.bind(label_merge); } @@ -59384,7 +59288,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_vector_op_2459_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_vector_op_2459_arg10 = ret_val_sew_2460; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_vector_op_2459, &mask_vector_vector_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_vector_op_2459, &mask_vector_vector_op, FuncSignature::build()); setArg(call_sew_2460, 0, reinterpret_cast(this)); setRet(call_sew_2460, 0, ret_val_sew_2460); setArg(call_mask_vector_vector_op_2459, 0, V); @@ -59401,11 +59305,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2461 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2461, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2461, 32, false) - , traits::vstart); + auto tmp2461 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2461, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2461, traits::vstart); } cc.bind(label_merge); } @@ -59486,7 +59388,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto mask_vector_imm_op_2464_arg10 = ret_val_sew_2465; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2464, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2464, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2465, 0, reinterpret_cast(this)); setRet(call_sew_2465, 0, ret_val_sew_2465); setArg(call_mask_vector_imm_op_2464, 0, V); @@ -59503,11 +59405,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2466 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2466, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2466, 32, false) - , traits::vstart); + auto tmp2466 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2466, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2466, traits::vstart); } cc.bind(label_merge); } @@ -59583,7 +59483,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_imm_op_2468_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_imm_op_2468_arg10 = ret_val_sew_2469; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2468, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2468, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2469, 0, reinterpret_cast(this)); setRet(call_sew_2469, 0, ret_val_sew_2469); setArg(call_mask_vector_imm_op_2468, 0, V); @@ -59600,11 +59500,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2470 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2470, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2470, 32, false) - , traits::vstart); + auto tmp2470 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2470, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2470, traits::vstart); } cc.bind(label_merge); } @@ -59680,7 +59578,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_vector_op_2472_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_vector_op_2472_arg10 = ret_val_sew_2473; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_vector_op_2472, &mask_vector_vector_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_vector_op_2472, &mask_vector_vector_op, FuncSignature::build()); setArg(call_sew_2473, 0, reinterpret_cast(this)); setRet(call_sew_2473, 0, ret_val_sew_2473); setArg(call_mask_vector_vector_op_2472, 0, V); @@ -59697,11 +59595,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2474 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2474, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2474, 32, false) - , traits::vstart); + auto tmp2474 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2474, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2474, traits::vstart); } cc.bind(label_merge); } @@ -59782,7 +59678,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto mask_vector_imm_op_2477_arg10 = ret_val_sew_2478; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2477, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2477, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2478, 0, reinterpret_cast(this)); setRet(call_sew_2478, 0, ret_val_sew_2478); setArg(call_mask_vector_imm_op_2477, 0, V); @@ -59799,11 +59695,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2479 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2479, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2479, 32, false) - , traits::vstart); + auto tmp2479 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2479, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2479, traits::vstart); } cc.bind(label_merge); } @@ -59879,7 +59773,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_imm_op_2481_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_imm_op_2481_arg10 = ret_val_sew_2482; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2481, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2481, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2482, 0, reinterpret_cast(this)); setRet(call_sew_2482, 0, ret_val_sew_2482); setArg(call_mask_vector_imm_op_2481, 0, V); @@ -59896,11 +59790,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2483 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2483, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2483, 32, false) - , traits::vstart); + auto tmp2483 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2483, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2483, traits::vstart); } cc.bind(label_merge); } @@ -59981,7 +59873,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto mask_vector_imm_op_2486_arg10 = ret_val_sew_2487; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2486, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2486, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2487, 0, reinterpret_cast(this)); setRet(call_sew_2487, 0, ret_val_sew_2487); setArg(call_mask_vector_imm_op_2486, 0, V); @@ -59998,11 +59890,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2488 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2488, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2488, 32, false) - , traits::vstart); + auto tmp2488 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2488, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2488, traits::vstart); } cc.bind(label_merge); } @@ -60078,7 +59968,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto mask_vector_imm_op_2490_arg5 = load_reg_from_mem(jh, traits::vtype); auto mask_vector_imm_op_2490_arg10 = ret_val_sew_2491; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2490, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2490, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2491, 0, reinterpret_cast(this)); setRet(call_sew_2491, 0, ret_val_sew_2491); setArg(call_mask_vector_imm_op_2490, 0, V); @@ -60095,11 +59985,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2492 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2492, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2492, 32, false) - , traits::vstart); + auto tmp2492 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2492, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2492, traits::vstart); } cc.bind(label_merge); } @@ -60180,7 +60068,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto mask_vector_imm_op_2495_arg10 = ret_val_sew_2496; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_vector_imm_op_2495, &mask_vector_imm_op, FuncSignature::build()); + cc.invoke(&call_mask_vector_imm_op_2495, &mask_vector_imm_op, FuncSignature::build()); setArg(call_sew_2496, 0, reinterpret_cast(this)); setRet(call_sew_2496, 0, ret_val_sew_2496); setArg(call_mask_vector_imm_op_2495, 0, V); @@ -60197,11 +60085,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2497 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2497, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2497, 32, false) - , traits::vstart); + auto tmp2497 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2497, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2497, traits::vstart); } cc.bind(label_merge); } @@ -60279,7 +60165,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2499_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2499_arg10 = ret_val_sew_2500; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2499, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2499, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2500, 0, reinterpret_cast(this)); setRet(call_sew_2500, 0, ret_val_sew_2500); setArg(call_vector_vector_op_2499, 0, V); @@ -60296,11 +60182,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2501 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2501, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2501, 32, false) - , traits::vstart); + auto tmp2501 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2501, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2501, traits::vstart); } cc.bind(label_merge); } @@ -60383,7 +60267,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2504_arg10 = ret_val_sew_2505; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2504, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2504, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2505, 0, reinterpret_cast(this)); setRet(call_sew_2505, 0, ret_val_sew_2505); setArg(call_vector_imm_op_2504, 0, V); @@ -60400,11 +60284,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2506 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2506, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2506, 32, false) - , traits::vstart); + auto tmp2506 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2506, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2506, traits::vstart); } cc.bind(label_merge); } @@ -60482,7 +60364,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2508_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2508_arg10 = ret_val_sew_2509; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2508, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2508, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2509, 0, reinterpret_cast(this)); setRet(call_sew_2509, 0, ret_val_sew_2509); setArg(call_vector_vector_op_2508, 0, V); @@ -60499,11 +60381,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2510 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2510, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2510, 32, false) - , traits::vstart); + auto tmp2510 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2510, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2510, traits::vstart); } cc.bind(label_merge); } @@ -60586,7 +60466,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2513_arg10 = ret_val_sew_2514; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2513, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2513, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2514, 0, reinterpret_cast(this)); setRet(call_sew_2514, 0, ret_val_sew_2514); setArg(call_vector_imm_op_2513, 0, V); @@ -60603,11 +60483,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2515 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2515, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2515, 32, false) - , traits::vstart); + auto tmp2515 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2515, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2515, traits::vstart); } cc.bind(label_merge); } @@ -60685,7 +60563,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2517_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2517_arg10 = ret_val_sew_2518; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2517, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2517, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2518, 0, reinterpret_cast(this)); setRet(call_sew_2518, 0, ret_val_sew_2518); setArg(call_vector_vector_op_2517, 0, V); @@ -60702,11 +60580,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2519 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2519, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2519, 32, false) - , traits::vstart); + auto tmp2519 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2519, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2519, traits::vstart); } cc.bind(label_merge); } @@ -60789,7 +60665,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2522_arg10 = ret_val_sew_2523; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2522, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2522, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2523, 0, reinterpret_cast(this)); setRet(call_sew_2523, 0, ret_val_sew_2523); setArg(call_vector_imm_op_2522, 0, V); @@ -60806,11 +60682,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2524 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2524, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2524, 32, false) - , traits::vstart); + auto tmp2524 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2524, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2524, traits::vstart); } cc.bind(label_merge); } @@ -60888,7 +60762,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2526_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2526_arg10 = ret_val_sew_2527; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2526, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2526, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2527, 0, reinterpret_cast(this)); setRet(call_sew_2527, 0, ret_val_sew_2527); setArg(call_vector_vector_op_2526, 0, V); @@ -60905,11 +60779,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2528 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2528, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2528, 32, false) - , traits::vstart); + auto tmp2528 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2528, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2528, traits::vstart); } cc.bind(label_merge); } @@ -60992,7 +60864,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2531_arg10 = ret_val_sew_2532; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2531, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2531, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2532, 0, reinterpret_cast(this)); setRet(call_sew_2532, 0, ret_val_sew_2532); setArg(call_vector_imm_op_2531, 0, V); @@ -61009,11 +60881,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2533 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2533, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2533, 32, false) - , traits::vstart); + auto tmp2533 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2533, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2533, traits::vstart); } cc.bind(label_merge); } @@ -61091,7 +60961,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2535_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2535_arg10 = ret_val_sew_2536; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2535, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2535, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2536, 0, reinterpret_cast(this)); setRet(call_sew_2536, 0, ret_val_sew_2536); setArg(call_vector_vector_op_2535, 0, V); @@ -61108,11 +60978,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2537 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2537, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2537, 32, false) - , traits::vstart); + auto tmp2537 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2537, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2537, traits::vstart); } cc.bind(label_merge); } @@ -61195,7 +61063,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2540_arg10 = ret_val_sew_2541; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2540, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2540, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2541, 0, reinterpret_cast(this)); setRet(call_sew_2541, 0, ret_val_sew_2541); setArg(call_vector_imm_op_2540, 0, V); @@ -61212,11 +61080,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2542 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2542, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2542, 32, false) - , traits::vstart); + auto tmp2542 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2542, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2542, traits::vstart); } cc.bind(label_merge); } @@ -61294,7 +61160,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2544_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2544_arg10 = ret_val_sew_2545; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2544, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2544, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2545, 0, reinterpret_cast(this)); setRet(call_sew_2545, 0, ret_val_sew_2545); setArg(call_vector_vector_op_2544, 0, V); @@ -61311,11 +61177,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2546 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2546, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2546, 32, false) - , traits::vstart); + auto tmp2546 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2546, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2546, traits::vstart); } cc.bind(label_merge); } @@ -61398,7 +61262,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2549_arg10 = ret_val_sew_2550; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2549, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2549, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2550, 0, reinterpret_cast(this)); setRet(call_sew_2550, 0, ret_val_sew_2550); setArg(call_vector_imm_op_2549, 0, V); @@ -61415,11 +61279,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2551 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2551, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2551, 32, false) - , traits::vstart); + auto tmp2551 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2551, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2551, traits::vstart); } cc.bind(label_merge); } @@ -61497,7 +61359,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2553_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2553_arg10 = ret_val_sew_2554; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2553, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2553, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2554, 0, reinterpret_cast(this)); setRet(call_sew_2554, 0, ret_val_sew_2554); setArg(call_vector_vector_op_2553, 0, V); @@ -61514,11 +61376,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2555 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2555, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2555, 32, false) - , traits::vstart); + auto tmp2555 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2555, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2555, traits::vstart); } cc.bind(label_merge); } @@ -61601,7 +61461,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2558_arg10 = ret_val_sew_2559; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2558, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2558, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2559, 0, reinterpret_cast(this)); setRet(call_sew_2559, 0, ret_val_sew_2559); setArg(call_vector_imm_op_2558, 0, V); @@ -61618,11 +61478,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2560 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2560, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2560, 32, false) - , traits::vstart); + auto tmp2560 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2560, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2560, traits::vstart); } cc.bind(label_merge); } @@ -61700,7 +61558,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2562_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2562_arg10 = ret_val_sew_2563; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2562, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2562, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2563, 0, reinterpret_cast(this)); setRet(call_sew_2563, 0, ret_val_sew_2563); setArg(call_vector_vector_op_2562, 0, V); @@ -61717,11 +61575,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2564 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2564, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2564, 32, false) - , traits::vstart); + auto tmp2564 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2564, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2564, traits::vstart); } cc.bind(label_merge); } @@ -61804,7 +61660,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2567_arg10 = ret_val_sew_2568; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2567, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2567, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2568, 0, reinterpret_cast(this)); setRet(call_sew_2568, 0, ret_val_sew_2568); setArg(call_vector_imm_op_2567, 0, V); @@ -61821,11 +61677,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2569 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2569, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2569, 32, false) - , traits::vstart); + auto tmp2569 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2569, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2569, traits::vstart); } cc.bind(label_merge); } @@ -61903,7 +61757,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2571_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2571_arg10 = ret_val_sew_2572; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2571, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2571, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2572, 0, reinterpret_cast(this)); setRet(call_sew_2572, 0, ret_val_sew_2572); setArg(call_vector_vector_op_2571, 0, V); @@ -61920,11 +61774,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2573 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2573, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2573, 32, false) - , traits::vstart); + auto tmp2573 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2573, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2573, traits::vstart); } cc.bind(label_merge); } @@ -62007,7 +61859,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2576_arg10 = ret_val_sew_2577; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2576, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2576, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2577, 0, reinterpret_cast(this)); setRet(call_sew_2577, 0, ret_val_sew_2577); setArg(call_vector_imm_op_2576, 0, V); @@ -62024,11 +61876,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2578 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2578, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2578, 32, false) - , traits::vstart); + auto tmp2578 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2578, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2578, traits::vstart); } cc.bind(label_merge); } @@ -62106,7 +61956,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2580_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2580_arg10 = ret_val_sew_2581; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2580, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2580, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2581, 0, reinterpret_cast(this)); setRet(call_sew_2581, 0, ret_val_sew_2581); setArg(call_vector_vector_op_2580, 0, V); @@ -62123,11 +61973,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2582 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2582, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2582, 32, false) - , traits::vstart); + auto tmp2582 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2582, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2582, traits::vstart); } cc.bind(label_merge); } @@ -62210,7 +62058,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2585_arg10 = ret_val_sew_2586; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2585, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2585, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2586, 0, reinterpret_cast(this)); setRet(call_sew_2586, 0, ret_val_sew_2586); setArg(call_vector_imm_op_2585, 0, V); @@ -62227,11 +62075,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2587 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2587, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2587, 32, false) - , traits::vstart); + auto tmp2587 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2587, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2587, traits::vstart); } cc.bind(label_merge); } @@ -62309,7 +62155,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2589_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2589_arg10 = ret_val_sew_2590; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2589, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2589, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2590, 0, reinterpret_cast(this)); setRet(call_sew_2590, 0, ret_val_sew_2590); setArg(call_vector_vector_op_2589, 0, V); @@ -62326,11 +62172,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2591 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2591, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2591, 32, false) - , traits::vstart); + auto tmp2591 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2591, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2591, traits::vstart); } cc.bind(label_merge); } @@ -62413,7 +62257,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2594_arg10 = ret_val_sew_2595; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2594, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2594, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2595, 0, reinterpret_cast(this)); setRet(call_sew_2595, 0, ret_val_sew_2595); setArg(call_vector_imm_op_2594, 0, V); @@ -62430,11 +62274,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2596 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2596, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2596, 32, false) - , traits::vstart); + auto tmp2596 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2596, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2596, traits::vstart); } cc.bind(label_merge); } @@ -62512,7 +62354,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2598_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2598_arg10 = ret_val_sew_2599; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2598, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2598, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2599, 0, reinterpret_cast(this)); setRet(call_sew_2599, 0, ret_val_sew_2599); setArg(call_vector_vector_op_2598, 0, V); @@ -62529,11 +62371,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2600 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2600, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2600, 32, false) - , traits::vstart); + auto tmp2600 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2600, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2600, traits::vstart); } cc.bind(label_merge); } @@ -62616,7 +62456,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2603_arg10 = ret_val_sew_2604; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2603, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2603, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2604, 0, reinterpret_cast(this)); setRet(call_sew_2604, 0, ret_val_sew_2604); setArg(call_vector_imm_op_2603, 0, V); @@ -62633,11 +62473,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2605 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2605, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2605, 32, false) - , traits::vstart); + auto tmp2605 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2605, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2605, traits::vstart); } cc.bind(label_merge); } @@ -62759,7 +62597,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_wv_2612_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_wv_2612_arg10 = ret_val_sew_2613; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_wv_2612, &vector_vector_wv, FuncSignature::build()); + cc.invoke(&call_vector_vector_wv_2612, &vector_vector_wv, FuncSignature::build()); setArg(call_sew_2613, 0, reinterpret_cast(this)); setRet(call_sew_2613, 0, ret_val_sew_2613); setArg(call_vector_vector_wv_2612, 0, V); @@ -62776,11 +62614,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2614 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2614, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2614, 32, false) - , traits::vstart); + auto tmp2614 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2614, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2614, traits::vstart); } cc.bind(label_merge); } @@ -62898,7 +62734,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2620_arg10 = ret_val_sew_2621; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2620, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2620, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2621, 0, reinterpret_cast(this)); setRet(call_sew_2621, 0, ret_val_sew_2621); setArg(call_vector_imm_wv_2620, 0, V); @@ -62915,11 +62751,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2622 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2622, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2622, 32, false) - , traits::vstart); + auto tmp2622 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2622, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2622, traits::vstart); } cc.bind(label_merge); } @@ -63042,7 +62876,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_wv_2629_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_wv_2629_arg10 = ret_val_sew_2630; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_wv_2629, &vector_vector_wv, FuncSignature::build()); + cc.invoke(&call_vector_vector_wv_2629, &vector_vector_wv, FuncSignature::build()); setArg(call_sew_2630, 0, reinterpret_cast(this)); setRet(call_sew_2630, 0, ret_val_sew_2630); setArg(call_vector_vector_wv_2629, 0, V); @@ -63059,11 +62893,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2631 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2631, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2631, 32, false) - , traits::vstart); + auto tmp2631 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2631, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2631, traits::vstart); } cc.bind(label_merge); } @@ -63181,7 +63013,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2637_arg10 = ret_val_sew_2638; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2637, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2637, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2638, 0, reinterpret_cast(this)); setRet(call_sew_2638, 0, ret_val_sew_2638); setArg(call_vector_imm_wv_2637, 0, V); @@ -63198,11 +63030,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2639 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2639, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2639, 32, false) - , traits::vstart); + auto tmp2639 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2639, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2639, traits::vstart); } cc.bind(label_merge); } @@ -63325,7 +63155,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_wv_2646_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_wv_2646_arg10 = ret_val_sew_2647; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_wv_2646, &vector_vector_wv, FuncSignature::build()); + cc.invoke(&call_vector_vector_wv_2646, &vector_vector_wv, FuncSignature::build()); setArg(call_sew_2647, 0, reinterpret_cast(this)); setRet(call_sew_2647, 0, ret_val_sew_2647); setArg(call_vector_vector_wv_2646, 0, V); @@ -63342,11 +63172,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2648 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2648, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2648, 32, false) - , traits::vstart); + auto tmp2648 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2648, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2648, traits::vstart); } cc.bind(label_merge); } @@ -63464,7 +63292,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2654_arg10 = ret_val_sew_2655; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2654, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2654, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2655, 0, reinterpret_cast(this)); setRet(call_sew_2655, 0, ret_val_sew_2655); setArg(call_vector_imm_wv_2654, 0, V); @@ -63481,11 +63309,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2656 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2656, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2656, 32, false) - , traits::vstart); + auto tmp2656 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2656, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2656, traits::vstart); } cc.bind(label_merge); } @@ -63564,7 +63390,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2658_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2658_arg10 = ret_val_sew_2659; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2658, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2658, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2659, 0, reinterpret_cast(this)); setRet(call_sew_2659, 0, ret_val_sew_2659); setArg(call_vector_vector_op_2658, 0, V); @@ -63581,11 +63407,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2660 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2660, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2660, 32, false) - , traits::vstart); + auto tmp2660 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2660, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2660, traits::vstart); } cc.bind(label_merge); } @@ -63668,7 +63492,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2663_arg10 = ret_val_sew_2664; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2663, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2663, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2664, 0, reinterpret_cast(this)); setRet(call_sew_2664, 0, ret_val_sew_2664); setArg(call_vector_imm_op_2663, 0, V); @@ -63685,11 +63509,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2665 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2665, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2665, 32, false) - , traits::vstart); + auto tmp2665 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2665, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2665, traits::vstart); } cc.bind(label_merge); } @@ -63767,7 +63589,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2667_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2667_arg10 = ret_val_sew_2668; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2667, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2667, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2668, 0, reinterpret_cast(this)); setRet(call_sew_2668, 0, ret_val_sew_2668); setArg(call_vector_vector_op_2667, 0, V); @@ -63784,11 +63606,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2669 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2669, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2669, 32, false) - , traits::vstart); + auto tmp2669 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2669, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2669, traits::vstart); } cc.bind(label_merge); } @@ -63871,7 +63691,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2672_arg10 = ret_val_sew_2673; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2672, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2672, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2673, 0, reinterpret_cast(this)); setRet(call_sew_2673, 0, ret_val_sew_2673); setArg(call_vector_imm_op_2672, 0, V); @@ -63888,11 +63708,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2674 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2674, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2674, 32, false) - , traits::vstart); + auto tmp2674 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2674, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2674, traits::vstart); } cc.bind(label_merge); } @@ -63970,7 +63788,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2676_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2676_arg10 = ret_val_sew_2677; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2676, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2676, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2677, 0, reinterpret_cast(this)); setRet(call_sew_2677, 0, ret_val_sew_2677); setArg(call_vector_vector_op_2676, 0, V); @@ -63987,11 +63805,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2678 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2678, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2678, 32, false) - , traits::vstart); + auto tmp2678 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2678, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2678, traits::vstart); } cc.bind(label_merge); } @@ -64074,7 +63890,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2681_arg10 = ret_val_sew_2682; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2681, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2681, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2682, 0, reinterpret_cast(this)); setRet(call_sew_2682, 0, ret_val_sew_2682); setArg(call_vector_imm_op_2681, 0, V); @@ -64091,11 +63907,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2683 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2683, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2683, 32, false) - , traits::vstart); + auto tmp2683 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2683, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2683, traits::vstart); } cc.bind(label_merge); } @@ -64173,7 +63987,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_op_2685_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_op_2685_arg10 = ret_val_sew_2686; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_op_2685, &vector_vector_op, FuncSignature::build()); + cc.invoke(&call_vector_vector_op_2685, &vector_vector_op, FuncSignature::build()); setArg(call_sew_2686, 0, reinterpret_cast(this)); setRet(call_sew_2686, 0, ret_val_sew_2686); setArg(call_vector_vector_op_2685, 0, V); @@ -64190,11 +64004,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2687 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2687, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2687, 32, false) - , traits::vstart); + auto tmp2687 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2687, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2687, traits::vstart); } cc.bind(label_merge); } @@ -64277,7 +64089,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_op_2690_arg10 = ret_val_sew_2691; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_op_2690, &vector_imm_op, FuncSignature::build()); + cc.invoke(&call_vector_imm_op_2690, &vector_imm_op, FuncSignature::build()); setArg(call_sew_2691, 0, reinterpret_cast(this)); setRet(call_sew_2691, 0, ret_val_sew_2691); setArg(call_vector_imm_op_2690, 0, V); @@ -64294,11 +64106,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2692 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2692, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2692, 32, false) - , traits::vstart); + auto tmp2692 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2692, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2692, traits::vstart); } cc.bind(label_merge); } @@ -64420,7 +64230,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_wv_2699_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_wv_2699_arg10 = ret_val_sew_2700; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_wv_2699, &vector_vector_wv, FuncSignature::build()); + cc.invoke(&call_vector_vector_wv_2699, &vector_vector_wv, FuncSignature::build()); setArg(call_sew_2700, 0, reinterpret_cast(this)); setRet(call_sew_2700, 0, ret_val_sew_2700); setArg(call_vector_vector_wv_2699, 0, V); @@ -64437,11 +64247,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2701 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2701, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2701, 32, false) - , traits::vstart); + auto tmp2701 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2701, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2701, traits::vstart); } cc.bind(label_merge); } @@ -64559,7 +64367,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2707_arg10 = ret_val_sew_2708; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2707, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2707, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2708, 0, reinterpret_cast(this)); setRet(call_sew_2708, 0, ret_val_sew_2708); setArg(call_vector_imm_wv_2707, 0, V); @@ -64576,11 +64384,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2709 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2709, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2709, 32, false) - , traits::vstart); + auto tmp2709 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2709, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2709, traits::vstart); } cc.bind(label_merge); } @@ -64703,7 +64509,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_wv_2716_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_wv_2716_arg10 = ret_val_sew_2717; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_wv_2716, &vector_vector_wv, FuncSignature::build()); + cc.invoke(&call_vector_vector_wv_2716, &vector_vector_wv, FuncSignature::build()); setArg(call_sew_2717, 0, reinterpret_cast(this)); setRet(call_sew_2717, 0, ret_val_sew_2717); setArg(call_vector_vector_wv_2716, 0, V); @@ -64720,11 +64526,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2718 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2718, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2718, 32, false) - , traits::vstart); + auto tmp2718 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2718, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2718, traits::vstart); } cc.bind(label_merge); } @@ -64842,7 +64646,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2724_arg10 = ret_val_sew_2725; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2724, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2724, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2725, 0, reinterpret_cast(this)); setRet(call_sew_2725, 0, ret_val_sew_2725); setArg(call_vector_imm_wv_2724, 0, V); @@ -64859,11 +64663,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2726 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2726, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2726, 32, false) - , traits::vstart); + auto tmp2726 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2726, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2726, traits::vstart); } cc.bind(label_merge); } @@ -64986,7 +64788,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_wv_2733_arg5 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_wv_2733_arg10 = ret_val_sew_2734; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_wv_2733, &vector_vector_wv, FuncSignature::build()); + cc.invoke(&call_vector_vector_wv_2733, &vector_vector_wv, FuncSignature::build()); setArg(call_sew_2734, 0, reinterpret_cast(this)); setRet(call_sew_2734, 0, ret_val_sew_2734); setArg(call_vector_vector_wv_2733, 0, V); @@ -65003,11 +64805,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2735 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2735, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2735, 32, false) - , traits::vstart); + auto tmp2735 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2735, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2735, traits::vstart); } cc.bind(label_merge); } @@ -65125,7 +64925,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2741_arg10 = ret_val_sew_2742; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2741, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2741, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2742, 0, reinterpret_cast(this)); setRet(call_sew_2742, 0, ret_val_sew_2742); setArg(call_vector_imm_wv_2741, 0, V); @@ -65142,11 +64942,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2743 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2743, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2743, 32, false) - , traits::vstart); + auto tmp2743 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2743, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2743, traits::vstart); } cc.bind(label_merge); } @@ -65201,7 +64999,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto tmp2745 = get_reg(cc, 8, false); mov(cc, tmp2745, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2745, ret_val_get_sew_pow_2744)), 5, false), ~ 1); + (gen_operation(cc, shl, tmp2745, ret_val_get_sew_pow_2744)), 8, false), ~ 1); setArg(call_get_sew_pow_2744, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_2744, 0, ret_val_get_sew_pow_2744); InvokeNode* call_get_lmul_pow_2746; @@ -65265,7 +65063,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); auto vector_imm_wv_2749_arg10 = ret_val_sew_2750; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_wv_2749, &vector_imm_wv, FuncSignature::build()); + cc.invoke(&call_vector_imm_wv_2749, &vector_imm_wv, FuncSignature::build()); setArg(call_sew_2750, 0, reinterpret_cast(this)); setRet(call_sew_2750, 0, ret_val_sew_2750); setArg(call_vector_imm_wv_2749, 0, V); @@ -65282,11 +65080,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2751 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2751, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2751, 32, false) - , traits::vstart); + auto tmp2751 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2751, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2751, traits::vstart); } cc.bind(label_merge); } @@ -65363,7 +65159,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_merge_2753_arg3 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_merge_2753_arg8 = ret_val_sew_2754; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_merge_2753, &vector_imm_merge, FuncSignature::build()); + cc.invoke(&call_vector_imm_merge_2753, &vector_imm_merge, FuncSignature::build()); setArg(call_sew_2754, 0, reinterpret_cast(this)); setRet(call_sew_2754, 0, ret_val_sew_2754); setArg(call_vector_imm_merge_2753, 0, V); @@ -65378,11 +65174,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2755 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2755, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2755, 32, false) - , traits::vstart); + auto tmp2755 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2755, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2755, traits::vstart); } cc.bind(label_merge); } @@ -65458,7 +65252,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_merge_2757_arg3 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_merge_2757_arg8 = ret_val_sew_2758; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_merge_2757, &vector_vector_merge, FuncSignature::build()); + cc.invoke(&call_vector_vector_merge_2757, &vector_vector_merge, FuncSignature::build()); setArg(call_sew_2758, 0, reinterpret_cast(this)); setRet(call_sew_2758, 0, ret_val_sew_2758); setArg(call_vector_vector_merge_2757, 0, V); @@ -65473,11 +65267,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2759 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2759, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2759, 32, false) - , traits::vstart); + auto tmp2759 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2759, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2759, traits::vstart); } cc.bind(label_merge); } @@ -65559,7 +65351,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true), 32, true); auto vector_imm_merge_2762_arg8 = ret_val_sew_2763; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_merge_2762, &vector_imm_merge, FuncSignature::build()); + cc.invoke(&call_vector_imm_merge_2762, &vector_imm_merge, FuncSignature::build()); setArg(call_sew_2763, 0, reinterpret_cast(this)); setRet(call_sew_2763, 0, ret_val_sew_2763); setArg(call_vector_imm_merge_2762, 0, V); @@ -65574,11 +65366,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2764 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2764, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2764, 32, false) - , traits::vstart); + auto tmp2764 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2764, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2764, traits::vstart); } cc.bind(label_merge); } @@ -65652,7 +65442,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_imm_merge_2766_arg3 = load_reg_from_mem(jh, traits::vtype); auto vector_imm_merge_2766_arg8 = ret_val_sew_2767; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_merge_2766, &vector_imm_merge, FuncSignature::build()); + cc.invoke(&call_vector_imm_merge_2766, &vector_imm_merge, FuncSignature::build()); setArg(call_sew_2767, 0, reinterpret_cast(this)); setRet(call_sew_2767, 0, ret_val_sew_2767); setArg(call_vector_imm_merge_2766, 0, V); @@ -65667,11 +65457,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2768 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2768, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2768, 32, false) - , traits::vstart); + auto tmp2768 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2768, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2768, traits::vstart); } cc.bind(label_merge); } @@ -65745,7 +65533,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto vector_vector_merge_2770_arg3 = load_reg_from_mem(jh, traits::vtype); auto vector_vector_merge_2770_arg8 = ret_val_sew_2771; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_merge_2770, &vector_vector_merge, FuncSignature::build()); + cc.invoke(&call_vector_vector_merge_2770, &vector_vector_merge, FuncSignature::build()); setArg(call_sew_2771, 0, reinterpret_cast(this)); setRet(call_sew_2771, 0, ret_val_sew_2771); setArg(call_vector_vector_merge_2770, 0, V); @@ -65760,11 +65548,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2772 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2772, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2772, 32, false) - , traits::vstart); + auto tmp2772 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2772, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2772, traits::vstart); } cc.bind(label_merge); } @@ -65844,7 +65630,7 @@ template class vm_impl : public iss::asmjit::vm_base { load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true), 32, true); auto vector_imm_merge_2775_arg8 = ret_val_sew_2776; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_merge_2775, &vector_imm_merge, FuncSignature::build()); + cc.invoke(&call_vector_imm_merge_2775, &vector_imm_merge, FuncSignature::build()); setArg(call_sew_2776, 0, reinterpret_cast(this)); setRet(call_sew_2776, 0, ret_val_sew_2776); setArg(call_vector_imm_merge_2775, 0, V); @@ -65859,11 +65645,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2777 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2777, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2777, 32, false) - , traits::vstart); + auto tmp2777 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2777, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2777, traits::vstart); } cc.bind(label_merge); } @@ -65943,10 +65727,9 @@ template class vm_impl : public iss::asmjit::vm_base { auto sat_vector_imm_op_2779_arg11 = ret_val_sew_2780; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_sat_vector_imm_op_2779 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2779, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2779, 32, false) - , traits::vxsat); + cc.invoke(&call_sat_vector_imm_op_2779, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2781 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2779, 32, false)); + write_reg_to_mem(jh, tmp2781, traits::vxsat); setArg(call_sew_2780, 0, reinterpret_cast(this)); setRet(call_sew_2780, 0, ret_val_sew_2780); setArg(call_sat_vector_imm_op_2779, 0, V); @@ -65965,11 +65748,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2781 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2781, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2781, 32, false) - , traits::vstart); + auto tmp2782 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2782, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2782, traits::vstart); } cc.bind(label_merge); } @@ -66015,14 +65796,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2782; - x86::Gp ret_val_illegal_normal_2782 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2782, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2782; - setArg(call_illegal_normal_2782, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2782, 1, vd); - setArg(call_illegal_normal_2782, 2, vm); - setRet(call_illegal_normal_2782, 0, ret_val_illegal_normal_2782); + InvokeNode* call_illegal_normal_2783; + x86::Gp ret_val_illegal_normal_2783 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2783, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2783; + setArg(call_illegal_normal_2783, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2783, 1, vd); + setArg(call_illegal_normal_2783, 2, vm); + setRet(call_illegal_normal_2783, 0, ret_val_illegal_normal_2783); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -66038,44 +65819,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2784; - x86::Gp ret_val_sew_2784 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2784, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2783; - auto sat_vector_vector_op_2783_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2783_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2783_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2783_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2783_arg11 = ret_val_sew_2784; + InvokeNode* call_sew_2785; + x86::Gp ret_val_sew_2785 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2785, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2784; + auto sat_vector_vector_op_2784_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2784_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2784_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2784_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2784_arg11 = ret_val_sew_2785; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2783 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2783, &sat_vector_vector_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_op_2783, 32, false) - , traits::vxsat); - setArg(call_sew_2784, 0, reinterpret_cast(this)); - setRet(call_sew_2784, 0, ret_val_sew_2784); - setArg(call_sat_vector_vector_op_2783, 0, V); - setArg(call_sat_vector_vector_op_2783, 1, 32); - setArg(call_sat_vector_vector_op_2783, 2, 0); - setArg(call_sat_vector_vector_op_2783, 3, sat_vector_vector_op_2783_arg3); - setArg(call_sat_vector_vector_op_2783, 4, sat_vector_vector_op_2783_arg4); - setArg(call_sat_vector_vector_op_2783, 5, sat_vector_vector_op_2783_arg5); - setArg(call_sat_vector_vector_op_2783, 6, sat_vector_vector_op_2783_arg6); - setArg(call_sat_vector_vector_op_2783, 7, vm); - setArg(call_sat_vector_vector_op_2783, 8, vd); - setArg(call_sat_vector_vector_op_2783, 9, vs2); - setArg(call_sat_vector_vector_op_2783, 10, vs1); - setArg(call_sat_vector_vector_op_2783, 11, sat_vector_vector_op_2783_arg11); - setRet(call_sat_vector_vector_op_2783, 0, ret_val_sat_vector_vector_op_2783); + x86::Gp ret_val_sat_vector_vector_op_2784 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2784, &sat_vector_vector_op, FuncSignature::build()); + auto tmp2786 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_op_2784, 32, false)); + write_reg_to_mem(jh, tmp2786, traits::vxsat); + setArg(call_sew_2785, 0, reinterpret_cast(this)); + setRet(call_sew_2785, 0, ret_val_sew_2785); + setArg(call_sat_vector_vector_op_2784, 0, V); + setArg(call_sat_vector_vector_op_2784, 1, 32); + setArg(call_sat_vector_vector_op_2784, 2, 0); + setArg(call_sat_vector_vector_op_2784, 3, sat_vector_vector_op_2784_arg3); + setArg(call_sat_vector_vector_op_2784, 4, sat_vector_vector_op_2784_arg4); + setArg(call_sat_vector_vector_op_2784, 5, sat_vector_vector_op_2784_arg5); + setArg(call_sat_vector_vector_op_2784, 6, sat_vector_vector_op_2784_arg6); + setArg(call_sat_vector_vector_op_2784, 7, vm); + setArg(call_sat_vector_vector_op_2784, 8, vd); + setArg(call_sat_vector_vector_op_2784, 9, vs2); + setArg(call_sat_vector_vector_op_2784, 10, vs1); + setArg(call_sat_vector_vector_op_2784, 11, sat_vector_vector_op_2784_arg11); + setRet(call_sat_vector_vector_op_2784, 0, ret_val_sat_vector_vector_op_2784); } cc.bind(label_merge); } - auto tmp2785 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2785, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2785, 32, false) - , traits::vstart); + auto tmp2787 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2787, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2787, traits::vstart); } cc.bind(label_merge); } @@ -66121,16 +65899,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2786; - x86::Gp ret_val_illegal_normal_2786 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2786, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2787 = get_reg(cc, 8, false); - mov(cc, tmp2787, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2787, ret_val_illegal_normal_2786); - setArg(call_illegal_normal_2786, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2786, 1, vd); - setArg(call_illegal_normal_2786, 2, vm); - setRet(call_illegal_normal_2786, 0, ret_val_illegal_normal_2786); + InvokeNode* call_illegal_normal_2788; + x86::Gp ret_val_illegal_normal_2788 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2788, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2789 = get_reg(cc, 8, false); + mov(cc, tmp2789, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2789, ret_val_illegal_normal_2788); + setArg(call_illegal_normal_2788, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2788, 1, vd); + setArg(call_illegal_normal_2788, 2, vm); + setRet(call_illegal_normal_2788, 0, ret_val_illegal_normal_2788); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -66146,47 +65924,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2789; - x86::Gp ret_val_sew_2789 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2789, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2788; - auto sat_vector_imm_op_2788_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2788_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2788_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2788_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2788_arg10 = gen_ext(cc, + InvokeNode* call_sew_2791; + x86::Gp ret_val_sew_2791 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2791, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2790; + auto sat_vector_imm_op_2790_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2790_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2790_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2790_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2790_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); - auto sat_vector_imm_op_2788_arg11 = ret_val_sew_2789; + auto sat_vector_imm_op_2790_arg11 = ret_val_sew_2791; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2788 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2788, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2788, 32, false) - , traits::vxsat); - setArg(call_sew_2789, 0, reinterpret_cast(this)); - setRet(call_sew_2789, 0, ret_val_sew_2789); - setArg(call_sat_vector_imm_op_2788, 0, V); - setArg(call_sat_vector_imm_op_2788, 1, 32); - setArg(call_sat_vector_imm_op_2788, 2, 4); - setArg(call_sat_vector_imm_op_2788, 3, sat_vector_imm_op_2788_arg3); - setArg(call_sat_vector_imm_op_2788, 4, sat_vector_imm_op_2788_arg4); - setArg(call_sat_vector_imm_op_2788, 5, sat_vector_imm_op_2788_arg5); - setArg(call_sat_vector_imm_op_2788, 6, sat_vector_imm_op_2788_arg6); - setArg(call_sat_vector_imm_op_2788, 7, vm); - setArg(call_sat_vector_imm_op_2788, 8, vd); - setArg(call_sat_vector_imm_op_2788, 9, vs2); - setArg(call_sat_vector_imm_op_2788, 10, sat_vector_imm_op_2788_arg10); - setArg(call_sat_vector_imm_op_2788, 11, sat_vector_imm_op_2788_arg11); - setRet(call_sat_vector_imm_op_2788, 0, ret_val_sat_vector_imm_op_2788); + x86::Gp ret_val_sat_vector_imm_op_2790 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2790, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2792 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2790, 32, false)); + write_reg_to_mem(jh, tmp2792, traits::vxsat); + setArg(call_sew_2791, 0, reinterpret_cast(this)); + setRet(call_sew_2791, 0, ret_val_sew_2791); + setArg(call_sat_vector_imm_op_2790, 0, V); + setArg(call_sat_vector_imm_op_2790, 1, 32); + setArg(call_sat_vector_imm_op_2790, 2, 4); + setArg(call_sat_vector_imm_op_2790, 3, sat_vector_imm_op_2790_arg3); + setArg(call_sat_vector_imm_op_2790, 4, sat_vector_imm_op_2790_arg4); + setArg(call_sat_vector_imm_op_2790, 5, sat_vector_imm_op_2790_arg5); + setArg(call_sat_vector_imm_op_2790, 6, sat_vector_imm_op_2790_arg6); + setArg(call_sat_vector_imm_op_2790, 7, vm); + setArg(call_sat_vector_imm_op_2790, 8, vd); + setArg(call_sat_vector_imm_op_2790, 9, vs2); + setArg(call_sat_vector_imm_op_2790, 10, sat_vector_imm_op_2790_arg10); + setArg(call_sat_vector_imm_op_2790, 11, sat_vector_imm_op_2790_arg11); + setRet(call_sat_vector_imm_op_2790, 0, ret_val_sat_vector_imm_op_2790); } cc.bind(label_merge); } - auto tmp2790 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2790, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2790, 32, false) - , traits::vstart); + auto tmp2793 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2793, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2793, traits::vstart); } cc.bind(label_merge); } @@ -66232,14 +66007,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2791; - x86::Gp ret_val_illegal_normal_2791 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2791, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2791; - setArg(call_illegal_normal_2791, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2791, 1, vd); - setArg(call_illegal_normal_2791, 2, vm); - setRet(call_illegal_normal_2791, 0, ret_val_illegal_normal_2791); + InvokeNode* call_illegal_normal_2794; + x86::Gp ret_val_illegal_normal_2794 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2794, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2794; + setArg(call_illegal_normal_2794, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2794, 1, vd); + setArg(call_illegal_normal_2794, 2, vm); + setRet(call_illegal_normal_2794, 0, ret_val_illegal_normal_2794); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -66255,44 +66030,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2793; - x86::Gp ret_val_sew_2793 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2793, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2792; - auto sat_vector_imm_op_2792_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2792_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2792_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2792_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2792_arg11 = ret_val_sew_2793; + InvokeNode* call_sew_2796; + x86::Gp ret_val_sew_2796 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2796, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2795; + auto sat_vector_imm_op_2795_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2795_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2795_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2795_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2795_arg11 = ret_val_sew_2796; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2792 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2792, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2792, 32, false) - , traits::vxsat); - setArg(call_sew_2793, 0, reinterpret_cast(this)); - setRet(call_sew_2793, 0, ret_val_sew_2793); - setArg(call_sat_vector_imm_op_2792, 0, V); - setArg(call_sat_vector_imm_op_2792, 1, 33); - setArg(call_sat_vector_imm_op_2792, 2, 3); - setArg(call_sat_vector_imm_op_2792, 3, sat_vector_imm_op_2792_arg3); - setArg(call_sat_vector_imm_op_2792, 4, sat_vector_imm_op_2792_arg4); - setArg(call_sat_vector_imm_op_2792, 5, sat_vector_imm_op_2792_arg5); - setArg(call_sat_vector_imm_op_2792, 6, sat_vector_imm_op_2792_arg6); - setArg(call_sat_vector_imm_op_2792, 7, vm); - setArg(call_sat_vector_imm_op_2792, 8, vd); - setArg(call_sat_vector_imm_op_2792, 9, vs2); - setArg(call_sat_vector_imm_op_2792, 10, (int32_t)(int8_t)sext<5>(simm)); - setArg(call_sat_vector_imm_op_2792, 11, sat_vector_imm_op_2792_arg11); - setRet(call_sat_vector_imm_op_2792, 0, ret_val_sat_vector_imm_op_2792); + x86::Gp ret_val_sat_vector_imm_op_2795 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2795, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2797 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2795, 32, false)); + write_reg_to_mem(jh, tmp2797, traits::vxsat); + setArg(call_sew_2796, 0, reinterpret_cast(this)); + setRet(call_sew_2796, 0, ret_val_sew_2796); + setArg(call_sat_vector_imm_op_2795, 0, V); + setArg(call_sat_vector_imm_op_2795, 1, 33); + setArg(call_sat_vector_imm_op_2795, 2, 3); + setArg(call_sat_vector_imm_op_2795, 3, sat_vector_imm_op_2795_arg3); + setArg(call_sat_vector_imm_op_2795, 4, sat_vector_imm_op_2795_arg4); + setArg(call_sat_vector_imm_op_2795, 5, sat_vector_imm_op_2795_arg5); + setArg(call_sat_vector_imm_op_2795, 6, sat_vector_imm_op_2795_arg6); + setArg(call_sat_vector_imm_op_2795, 7, vm); + setArg(call_sat_vector_imm_op_2795, 8, vd); + setArg(call_sat_vector_imm_op_2795, 9, vs2); + setArg(call_sat_vector_imm_op_2795, 10, (int32_t)(int8_t)sext<5>(simm)); + setArg(call_sat_vector_imm_op_2795, 11, sat_vector_imm_op_2795_arg11); + setRet(call_sat_vector_imm_op_2795, 0, ret_val_sat_vector_imm_op_2795); } cc.bind(label_merge); } - auto tmp2794 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2794, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2794, 32, false) - , traits::vstart); + auto tmp2798 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2798, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2798, traits::vstart); } cc.bind(label_merge); } @@ -66338,14 +66110,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2795; - x86::Gp ret_val_illegal_normal_2795 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2795, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2795; - setArg(call_illegal_normal_2795, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2795, 1, vd); - setArg(call_illegal_normal_2795, 2, vm); - setRet(call_illegal_normal_2795, 0, ret_val_illegal_normal_2795); + InvokeNode* call_illegal_normal_2799; + x86::Gp ret_val_illegal_normal_2799 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2799, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2799; + setArg(call_illegal_normal_2799, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2799, 1, vd); + setArg(call_illegal_normal_2799, 2, vm); + setRet(call_illegal_normal_2799, 0, ret_val_illegal_normal_2799); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -66361,44 +66133,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2797; - x86::Gp ret_val_sew_2797 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2797, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2796; - auto sat_vector_vector_op_2796_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2796_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2796_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2796_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2796_arg11 = ret_val_sew_2797; + InvokeNode* call_sew_2801; + x86::Gp ret_val_sew_2801 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2801, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2800; + auto sat_vector_vector_op_2800_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2800_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2800_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2800_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2800_arg11 = ret_val_sew_2801; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2796 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2796, &sat_vector_vector_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_op_2796, 32, false) - , traits::vxsat); - setArg(call_sew_2797, 0, reinterpret_cast(this)); - setRet(call_sew_2797, 0, ret_val_sew_2797); - setArg(call_sat_vector_vector_op_2796, 0, V); - setArg(call_sat_vector_vector_op_2796, 1, 33); - setArg(call_sat_vector_vector_op_2796, 2, 0); - setArg(call_sat_vector_vector_op_2796, 3, sat_vector_vector_op_2796_arg3); - setArg(call_sat_vector_vector_op_2796, 4, sat_vector_vector_op_2796_arg4); - setArg(call_sat_vector_vector_op_2796, 5, sat_vector_vector_op_2796_arg5); - setArg(call_sat_vector_vector_op_2796, 6, sat_vector_vector_op_2796_arg6); - setArg(call_sat_vector_vector_op_2796, 7, vm); - setArg(call_sat_vector_vector_op_2796, 8, vd); - setArg(call_sat_vector_vector_op_2796, 9, vs2); - setArg(call_sat_vector_vector_op_2796, 10, vs1); - setArg(call_sat_vector_vector_op_2796, 11, sat_vector_vector_op_2796_arg11); - setRet(call_sat_vector_vector_op_2796, 0, ret_val_sat_vector_vector_op_2796); + x86::Gp ret_val_sat_vector_vector_op_2800 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2800, &sat_vector_vector_op, FuncSignature::build()); + auto tmp2802 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_op_2800, 32, false)); + write_reg_to_mem(jh, tmp2802, traits::vxsat); + setArg(call_sew_2801, 0, reinterpret_cast(this)); + setRet(call_sew_2801, 0, ret_val_sew_2801); + setArg(call_sat_vector_vector_op_2800, 0, V); + setArg(call_sat_vector_vector_op_2800, 1, 33); + setArg(call_sat_vector_vector_op_2800, 2, 0); + setArg(call_sat_vector_vector_op_2800, 3, sat_vector_vector_op_2800_arg3); + setArg(call_sat_vector_vector_op_2800, 4, sat_vector_vector_op_2800_arg4); + setArg(call_sat_vector_vector_op_2800, 5, sat_vector_vector_op_2800_arg5); + setArg(call_sat_vector_vector_op_2800, 6, sat_vector_vector_op_2800_arg6); + setArg(call_sat_vector_vector_op_2800, 7, vm); + setArg(call_sat_vector_vector_op_2800, 8, vd); + setArg(call_sat_vector_vector_op_2800, 9, vs2); + setArg(call_sat_vector_vector_op_2800, 10, vs1); + setArg(call_sat_vector_vector_op_2800, 11, sat_vector_vector_op_2800_arg11); + setRet(call_sat_vector_vector_op_2800, 0, ret_val_sat_vector_vector_op_2800); } cc.bind(label_merge); } - auto tmp2798 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2798, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2798, 32, false) - , traits::vstart); + auto tmp2803 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2803, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2803, traits::vstart); } cc.bind(label_merge); } @@ -66444,16 +66213,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2799; - x86::Gp ret_val_illegal_normal_2799 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2799, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2800 = get_reg(cc, 8, false); - mov(cc, tmp2800, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2800, ret_val_illegal_normal_2799); - setArg(call_illegal_normal_2799, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2799, 1, vd); - setArg(call_illegal_normal_2799, 2, vm); - setRet(call_illegal_normal_2799, 0, ret_val_illegal_normal_2799); + InvokeNode* call_illegal_normal_2804; + x86::Gp ret_val_illegal_normal_2804 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2804, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2805 = get_reg(cc, 8, false); + mov(cc, tmp2805, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2805, ret_val_illegal_normal_2804); + setArg(call_illegal_normal_2804, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2804, 1, vd); + setArg(call_illegal_normal_2804, 2, vm); + setRet(call_illegal_normal_2804, 0, ret_val_illegal_normal_2804); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -66469,47 +66238,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2802; - x86::Gp ret_val_sew_2802 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2802, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2801; - auto sat_vector_imm_op_2801_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2801_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2801_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2801_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2801_arg10 = gen_ext(cc, + InvokeNode* call_sew_2807; + x86::Gp ret_val_sew_2807 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2807, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2806; + auto sat_vector_imm_op_2806_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2806_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2806_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2806_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2806_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); - auto sat_vector_imm_op_2801_arg11 = ret_val_sew_2802; + auto sat_vector_imm_op_2806_arg11 = ret_val_sew_2807; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2801 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2801, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2801, 32, false) - , traits::vxsat); - setArg(call_sew_2802, 0, reinterpret_cast(this)); - setRet(call_sew_2802, 0, ret_val_sew_2802); - setArg(call_sat_vector_imm_op_2801, 0, V); - setArg(call_sat_vector_imm_op_2801, 1, 33); - setArg(call_sat_vector_imm_op_2801, 2, 4); - setArg(call_sat_vector_imm_op_2801, 3, sat_vector_imm_op_2801_arg3); - setArg(call_sat_vector_imm_op_2801, 4, sat_vector_imm_op_2801_arg4); - setArg(call_sat_vector_imm_op_2801, 5, sat_vector_imm_op_2801_arg5); - setArg(call_sat_vector_imm_op_2801, 6, sat_vector_imm_op_2801_arg6); - setArg(call_sat_vector_imm_op_2801, 7, vm); - setArg(call_sat_vector_imm_op_2801, 8, vd); - setArg(call_sat_vector_imm_op_2801, 9, vs2); - setArg(call_sat_vector_imm_op_2801, 10, sat_vector_imm_op_2801_arg10); - setArg(call_sat_vector_imm_op_2801, 11, sat_vector_imm_op_2801_arg11); - setRet(call_sat_vector_imm_op_2801, 0, ret_val_sat_vector_imm_op_2801); + x86::Gp ret_val_sat_vector_imm_op_2806 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2806, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2808 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2806, 32, false)); + write_reg_to_mem(jh, tmp2808, traits::vxsat); + setArg(call_sew_2807, 0, reinterpret_cast(this)); + setRet(call_sew_2807, 0, ret_val_sew_2807); + setArg(call_sat_vector_imm_op_2806, 0, V); + setArg(call_sat_vector_imm_op_2806, 1, 33); + setArg(call_sat_vector_imm_op_2806, 2, 4); + setArg(call_sat_vector_imm_op_2806, 3, sat_vector_imm_op_2806_arg3); + setArg(call_sat_vector_imm_op_2806, 4, sat_vector_imm_op_2806_arg4); + setArg(call_sat_vector_imm_op_2806, 5, sat_vector_imm_op_2806_arg5); + setArg(call_sat_vector_imm_op_2806, 6, sat_vector_imm_op_2806_arg6); + setArg(call_sat_vector_imm_op_2806, 7, vm); + setArg(call_sat_vector_imm_op_2806, 8, vd); + setArg(call_sat_vector_imm_op_2806, 9, vs2); + setArg(call_sat_vector_imm_op_2806, 10, sat_vector_imm_op_2806_arg10); + setArg(call_sat_vector_imm_op_2806, 11, sat_vector_imm_op_2806_arg11); + setRet(call_sat_vector_imm_op_2806, 0, ret_val_sat_vector_imm_op_2806); } cc.bind(label_merge); } - auto tmp2803 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2803, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2803, 32, false) - , traits::vstart); + auto tmp2809 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2809, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2809, traits::vstart); } cc.bind(label_merge); } @@ -66555,14 +66321,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2804; - x86::Gp ret_val_illegal_normal_2804 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2804, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2804; - setArg(call_illegal_normal_2804, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2804, 1, vd); - setArg(call_illegal_normal_2804, 2, vm); - setRet(call_illegal_normal_2804, 0, ret_val_illegal_normal_2804); + InvokeNode* call_illegal_normal_2810; + x86::Gp ret_val_illegal_normal_2810 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2810, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2810; + setArg(call_illegal_normal_2810, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2810, 1, vd); + setArg(call_illegal_normal_2810, 2, vm); + setRet(call_illegal_normal_2810, 0, ret_val_illegal_normal_2810); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -66578,44 +66344,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2806; - x86::Gp ret_val_sew_2806 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2806, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2805; - auto sat_vector_vector_op_2805_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2805_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2805_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2805_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2805_arg11 = ret_val_sew_2806; + InvokeNode* call_sew_2812; + x86::Gp ret_val_sew_2812 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2812, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2811; + auto sat_vector_vector_op_2811_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2811_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2811_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2811_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2811_arg11 = ret_val_sew_2812; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2805 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2805, &sat_vector_vector_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_op_2805, 32, false) - , traits::vxsat); - setArg(call_sew_2806, 0, reinterpret_cast(this)); - setRet(call_sew_2806, 0, ret_val_sew_2806); - setArg(call_sat_vector_vector_op_2805, 0, V); - setArg(call_sat_vector_vector_op_2805, 1, 34); - setArg(call_sat_vector_vector_op_2805, 2, 0); - setArg(call_sat_vector_vector_op_2805, 3, sat_vector_vector_op_2805_arg3); - setArg(call_sat_vector_vector_op_2805, 4, sat_vector_vector_op_2805_arg4); - setArg(call_sat_vector_vector_op_2805, 5, sat_vector_vector_op_2805_arg5); - setArg(call_sat_vector_vector_op_2805, 6, sat_vector_vector_op_2805_arg6); - setArg(call_sat_vector_vector_op_2805, 7, vm); - setArg(call_sat_vector_vector_op_2805, 8, vd); - setArg(call_sat_vector_vector_op_2805, 9, vs2); - setArg(call_sat_vector_vector_op_2805, 10, vs1); - setArg(call_sat_vector_vector_op_2805, 11, sat_vector_vector_op_2805_arg11); - setRet(call_sat_vector_vector_op_2805, 0, ret_val_sat_vector_vector_op_2805); + x86::Gp ret_val_sat_vector_vector_op_2811 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2811, &sat_vector_vector_op, FuncSignature::build()); + auto tmp2813 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_op_2811, 32, false)); + write_reg_to_mem(jh, tmp2813, traits::vxsat); + setArg(call_sew_2812, 0, reinterpret_cast(this)); + setRet(call_sew_2812, 0, ret_val_sew_2812); + setArg(call_sat_vector_vector_op_2811, 0, V); + setArg(call_sat_vector_vector_op_2811, 1, 34); + setArg(call_sat_vector_vector_op_2811, 2, 0); + setArg(call_sat_vector_vector_op_2811, 3, sat_vector_vector_op_2811_arg3); + setArg(call_sat_vector_vector_op_2811, 4, sat_vector_vector_op_2811_arg4); + setArg(call_sat_vector_vector_op_2811, 5, sat_vector_vector_op_2811_arg5); + setArg(call_sat_vector_vector_op_2811, 6, sat_vector_vector_op_2811_arg6); + setArg(call_sat_vector_vector_op_2811, 7, vm); + setArg(call_sat_vector_vector_op_2811, 8, vd); + setArg(call_sat_vector_vector_op_2811, 9, vs2); + setArg(call_sat_vector_vector_op_2811, 10, vs1); + setArg(call_sat_vector_vector_op_2811, 11, sat_vector_vector_op_2811_arg11); + setRet(call_sat_vector_vector_op_2811, 0, ret_val_sat_vector_vector_op_2811); } cc.bind(label_merge); } - auto tmp2807 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2807, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2807, 32, false) - , traits::vstart); + auto tmp2814 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2814, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2814, traits::vstart); } cc.bind(label_merge); } @@ -66661,16 +66424,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2808; - x86::Gp ret_val_illegal_normal_2808 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2808, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2809 = get_reg(cc, 8, false); - mov(cc, tmp2809, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2809, ret_val_illegal_normal_2808); - setArg(call_illegal_normal_2808, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2808, 1, vd); - setArg(call_illegal_normal_2808, 2, vm); - setRet(call_illegal_normal_2808, 0, ret_val_illegal_normal_2808); + InvokeNode* call_illegal_normal_2815; + x86::Gp ret_val_illegal_normal_2815 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2815, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2816 = get_reg(cc, 8, false); + mov(cc, tmp2816, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2816, ret_val_illegal_normal_2815); + setArg(call_illegal_normal_2815, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2815, 1, vd); + setArg(call_illegal_normal_2815, 2, vm); + setRet(call_illegal_normal_2815, 0, ret_val_illegal_normal_2815); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -66686,47 +66449,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2811; - x86::Gp ret_val_sew_2811 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2811, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2810; - auto sat_vector_imm_op_2810_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2810_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2810_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2810_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2810_arg10 = gen_ext(cc, + InvokeNode* call_sew_2818; + x86::Gp ret_val_sew_2818 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2818, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2817; + auto sat_vector_imm_op_2817_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2817_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2817_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2817_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2817_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); - auto sat_vector_imm_op_2810_arg11 = ret_val_sew_2811; + auto sat_vector_imm_op_2817_arg11 = ret_val_sew_2818; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2810 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2810, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2810, 32, false) - , traits::vxsat); - setArg(call_sew_2811, 0, reinterpret_cast(this)); - setRet(call_sew_2811, 0, ret_val_sew_2811); - setArg(call_sat_vector_imm_op_2810, 0, V); - setArg(call_sat_vector_imm_op_2810, 1, 34); - setArg(call_sat_vector_imm_op_2810, 2, 4); - setArg(call_sat_vector_imm_op_2810, 3, sat_vector_imm_op_2810_arg3); - setArg(call_sat_vector_imm_op_2810, 4, sat_vector_imm_op_2810_arg4); - setArg(call_sat_vector_imm_op_2810, 5, sat_vector_imm_op_2810_arg5); - setArg(call_sat_vector_imm_op_2810, 6, sat_vector_imm_op_2810_arg6); - setArg(call_sat_vector_imm_op_2810, 7, vm); - setArg(call_sat_vector_imm_op_2810, 8, vd); - setArg(call_sat_vector_imm_op_2810, 9, vs2); - setArg(call_sat_vector_imm_op_2810, 10, sat_vector_imm_op_2810_arg10); - setArg(call_sat_vector_imm_op_2810, 11, sat_vector_imm_op_2810_arg11); - setRet(call_sat_vector_imm_op_2810, 0, ret_val_sat_vector_imm_op_2810); + x86::Gp ret_val_sat_vector_imm_op_2817 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2817, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2819 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2817, 32, false)); + write_reg_to_mem(jh, tmp2819, traits::vxsat); + setArg(call_sew_2818, 0, reinterpret_cast(this)); + setRet(call_sew_2818, 0, ret_val_sew_2818); + setArg(call_sat_vector_imm_op_2817, 0, V); + setArg(call_sat_vector_imm_op_2817, 1, 34); + setArg(call_sat_vector_imm_op_2817, 2, 4); + setArg(call_sat_vector_imm_op_2817, 3, sat_vector_imm_op_2817_arg3); + setArg(call_sat_vector_imm_op_2817, 4, sat_vector_imm_op_2817_arg4); + setArg(call_sat_vector_imm_op_2817, 5, sat_vector_imm_op_2817_arg5); + setArg(call_sat_vector_imm_op_2817, 6, sat_vector_imm_op_2817_arg6); + setArg(call_sat_vector_imm_op_2817, 7, vm); + setArg(call_sat_vector_imm_op_2817, 8, vd); + setArg(call_sat_vector_imm_op_2817, 9, vs2); + setArg(call_sat_vector_imm_op_2817, 10, sat_vector_imm_op_2817_arg10); + setArg(call_sat_vector_imm_op_2817, 11, sat_vector_imm_op_2817_arg11); + setRet(call_sat_vector_imm_op_2817, 0, ret_val_sat_vector_imm_op_2817); } cc.bind(label_merge); } - auto tmp2812 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2812, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2812, 32, false) - , traits::vstart); + auto tmp2820 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2820, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2820, traits::vstart); } cc.bind(label_merge); } @@ -66772,14 +66532,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2813; - x86::Gp ret_val_illegal_normal_2813 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2813, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2813; - setArg(call_illegal_normal_2813, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2813, 1, vd); - setArg(call_illegal_normal_2813, 2, vm); - setRet(call_illegal_normal_2813, 0, ret_val_illegal_normal_2813); + InvokeNode* call_illegal_normal_2821; + x86::Gp ret_val_illegal_normal_2821 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2821, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2821; + setArg(call_illegal_normal_2821, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2821, 1, vd); + setArg(call_illegal_normal_2821, 2, vm); + setRet(call_illegal_normal_2821, 0, ret_val_illegal_normal_2821); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -66795,44 +66555,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2815; - x86::Gp ret_val_sew_2815 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2815, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2814; - auto sat_vector_vector_op_2814_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2814_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2814_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2814_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2814_arg11 = ret_val_sew_2815; + InvokeNode* call_sew_2823; + x86::Gp ret_val_sew_2823 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2823, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2822; + auto sat_vector_vector_op_2822_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2822_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2822_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2822_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2822_arg11 = ret_val_sew_2823; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2814 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2814, &sat_vector_vector_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_op_2814, 32, false) - , traits::vxsat); - setArg(call_sew_2815, 0, reinterpret_cast(this)); - setRet(call_sew_2815, 0, ret_val_sew_2815); - setArg(call_sat_vector_vector_op_2814, 0, V); - setArg(call_sat_vector_vector_op_2814, 1, 35); - setArg(call_sat_vector_vector_op_2814, 2, 0); - setArg(call_sat_vector_vector_op_2814, 3, sat_vector_vector_op_2814_arg3); - setArg(call_sat_vector_vector_op_2814, 4, sat_vector_vector_op_2814_arg4); - setArg(call_sat_vector_vector_op_2814, 5, sat_vector_vector_op_2814_arg5); - setArg(call_sat_vector_vector_op_2814, 6, sat_vector_vector_op_2814_arg6); - setArg(call_sat_vector_vector_op_2814, 7, vm); - setArg(call_sat_vector_vector_op_2814, 8, vd); - setArg(call_sat_vector_vector_op_2814, 9, vs2); - setArg(call_sat_vector_vector_op_2814, 10, vs1); - setArg(call_sat_vector_vector_op_2814, 11, sat_vector_vector_op_2814_arg11); - setRet(call_sat_vector_vector_op_2814, 0, ret_val_sat_vector_vector_op_2814); + x86::Gp ret_val_sat_vector_vector_op_2822 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2822, &sat_vector_vector_op, FuncSignature::build()); + auto tmp2824 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_op_2822, 32, false)); + write_reg_to_mem(jh, tmp2824, traits::vxsat); + setArg(call_sew_2823, 0, reinterpret_cast(this)); + setRet(call_sew_2823, 0, ret_val_sew_2823); + setArg(call_sat_vector_vector_op_2822, 0, V); + setArg(call_sat_vector_vector_op_2822, 1, 35); + setArg(call_sat_vector_vector_op_2822, 2, 0); + setArg(call_sat_vector_vector_op_2822, 3, sat_vector_vector_op_2822_arg3); + setArg(call_sat_vector_vector_op_2822, 4, sat_vector_vector_op_2822_arg4); + setArg(call_sat_vector_vector_op_2822, 5, sat_vector_vector_op_2822_arg5); + setArg(call_sat_vector_vector_op_2822, 6, sat_vector_vector_op_2822_arg6); + setArg(call_sat_vector_vector_op_2822, 7, vm); + setArg(call_sat_vector_vector_op_2822, 8, vd); + setArg(call_sat_vector_vector_op_2822, 9, vs2); + setArg(call_sat_vector_vector_op_2822, 10, vs1); + setArg(call_sat_vector_vector_op_2822, 11, sat_vector_vector_op_2822_arg11); + setRet(call_sat_vector_vector_op_2822, 0, ret_val_sat_vector_vector_op_2822); } cc.bind(label_merge); } - auto tmp2816 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2816, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2816, 32, false) - , traits::vstart); + auto tmp2825 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2825, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2825, traits::vstart); } cc.bind(label_merge); } @@ -66878,16 +66635,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2817; - x86::Gp ret_val_illegal_normal_2817 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2817, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2818 = get_reg(cc, 8, false); - mov(cc, tmp2818, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2818, ret_val_illegal_normal_2817); - setArg(call_illegal_normal_2817, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2817, 1, vd); - setArg(call_illegal_normal_2817, 2, vm); - setRet(call_illegal_normal_2817, 0, ret_val_illegal_normal_2817); + InvokeNode* call_illegal_normal_2826; + x86::Gp ret_val_illegal_normal_2826 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2826, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2827 = get_reg(cc, 8, false); + mov(cc, tmp2827, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2827, ret_val_illegal_normal_2826); + setArg(call_illegal_normal_2826, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2826, 1, vd); + setArg(call_illegal_normal_2826, 2, vm); + setRet(call_illegal_normal_2826, 0, ret_val_illegal_normal_2826); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -66903,47 +66660,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2820; - x86::Gp ret_val_sew_2820 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2820, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2819; - auto sat_vector_imm_op_2819_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2819_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2819_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2819_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2819_arg10 = gen_ext(cc, + InvokeNode* call_sew_2829; + x86::Gp ret_val_sew_2829 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2829, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2828; + auto sat_vector_imm_op_2828_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2828_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2828_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2828_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2828_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); - auto sat_vector_imm_op_2819_arg11 = ret_val_sew_2820; + auto sat_vector_imm_op_2828_arg11 = ret_val_sew_2829; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2819 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2819, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2819, 32, false) - , traits::vxsat); - setArg(call_sew_2820, 0, reinterpret_cast(this)); - setRet(call_sew_2820, 0, ret_val_sew_2820); - setArg(call_sat_vector_imm_op_2819, 0, V); - setArg(call_sat_vector_imm_op_2819, 1, 35); - setArg(call_sat_vector_imm_op_2819, 2, 4); - setArg(call_sat_vector_imm_op_2819, 3, sat_vector_imm_op_2819_arg3); - setArg(call_sat_vector_imm_op_2819, 4, sat_vector_imm_op_2819_arg4); - setArg(call_sat_vector_imm_op_2819, 5, sat_vector_imm_op_2819_arg5); - setArg(call_sat_vector_imm_op_2819, 6, sat_vector_imm_op_2819_arg6); - setArg(call_sat_vector_imm_op_2819, 7, vm); - setArg(call_sat_vector_imm_op_2819, 8, vd); - setArg(call_sat_vector_imm_op_2819, 9, vs2); - setArg(call_sat_vector_imm_op_2819, 10, sat_vector_imm_op_2819_arg10); - setArg(call_sat_vector_imm_op_2819, 11, sat_vector_imm_op_2819_arg11); - setRet(call_sat_vector_imm_op_2819, 0, ret_val_sat_vector_imm_op_2819); + x86::Gp ret_val_sat_vector_imm_op_2828 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2828, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2830 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2828, 32, false)); + write_reg_to_mem(jh, tmp2830, traits::vxsat); + setArg(call_sew_2829, 0, reinterpret_cast(this)); + setRet(call_sew_2829, 0, ret_val_sew_2829); + setArg(call_sat_vector_imm_op_2828, 0, V); + setArg(call_sat_vector_imm_op_2828, 1, 35); + setArg(call_sat_vector_imm_op_2828, 2, 4); + setArg(call_sat_vector_imm_op_2828, 3, sat_vector_imm_op_2828_arg3); + setArg(call_sat_vector_imm_op_2828, 4, sat_vector_imm_op_2828_arg4); + setArg(call_sat_vector_imm_op_2828, 5, sat_vector_imm_op_2828_arg5); + setArg(call_sat_vector_imm_op_2828, 6, sat_vector_imm_op_2828_arg6); + setArg(call_sat_vector_imm_op_2828, 7, vm); + setArg(call_sat_vector_imm_op_2828, 8, vd); + setArg(call_sat_vector_imm_op_2828, 9, vs2); + setArg(call_sat_vector_imm_op_2828, 10, sat_vector_imm_op_2828_arg10); + setArg(call_sat_vector_imm_op_2828, 11, sat_vector_imm_op_2828_arg11); + setRet(call_sat_vector_imm_op_2828, 0, ret_val_sat_vector_imm_op_2828); } cc.bind(label_merge); } - auto tmp2821 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2821, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2821, 32, false) - , traits::vstart); + auto tmp2831 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2831, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2831, traits::vstart); } cc.bind(label_merge); } @@ -66989,14 +66743,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2822; - x86::Gp ret_val_illegal_normal_2822 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2822, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2822; - setArg(call_illegal_normal_2822, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2822, 1, vd); - setArg(call_illegal_normal_2822, 2, vm); - setRet(call_illegal_normal_2822, 0, ret_val_illegal_normal_2822); + InvokeNode* call_illegal_normal_2832; + x86::Gp ret_val_illegal_normal_2832 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2832, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2832; + setArg(call_illegal_normal_2832, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2832, 1, vd); + setArg(call_illegal_normal_2832, 2, vm); + setRet(call_illegal_normal_2832, 0, ret_val_illegal_normal_2832); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -67012,42 +66766,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2824; - x86::Gp ret_val_sew_2824 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2824, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2823; - auto sat_vector_vector_op_2823_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2823_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2823_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2823_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2823_arg11 = ret_val_sew_2824; + InvokeNode* call_sew_2834; + x86::Gp ret_val_sew_2834 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2834, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2833; + auto sat_vector_vector_op_2833_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2833_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2833_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2833_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2833_arg11 = ret_val_sew_2834; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2823 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2823, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2823; - setArg(call_sew_2824, 0, reinterpret_cast(this)); - setRet(call_sew_2824, 0, ret_val_sew_2824); - setArg(call_sat_vector_vector_op_2823, 0, V); - setArg(call_sat_vector_vector_op_2823, 1, 8); - setArg(call_sat_vector_vector_op_2823, 2, 2); - setArg(call_sat_vector_vector_op_2823, 3, sat_vector_vector_op_2823_arg3); - setArg(call_sat_vector_vector_op_2823, 4, sat_vector_vector_op_2823_arg4); - setArg(call_sat_vector_vector_op_2823, 5, sat_vector_vector_op_2823_arg5); - setArg(call_sat_vector_vector_op_2823, 6, sat_vector_vector_op_2823_arg6); - setArg(call_sat_vector_vector_op_2823, 7, vm); - setArg(call_sat_vector_vector_op_2823, 8, vd); - setArg(call_sat_vector_vector_op_2823, 9, vs2); - setArg(call_sat_vector_vector_op_2823, 10, vs1); - setArg(call_sat_vector_vector_op_2823, 11, sat_vector_vector_op_2823_arg11); - setRet(call_sat_vector_vector_op_2823, 0, ret_val_sat_vector_vector_op_2823); + x86::Gp ret_val_sat_vector_vector_op_2833 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2833, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2833; + setArg(call_sew_2834, 0, reinterpret_cast(this)); + setRet(call_sew_2834, 0, ret_val_sew_2834); + setArg(call_sat_vector_vector_op_2833, 0, V); + setArg(call_sat_vector_vector_op_2833, 1, 8); + setArg(call_sat_vector_vector_op_2833, 2, 2); + setArg(call_sat_vector_vector_op_2833, 3, sat_vector_vector_op_2833_arg3); + setArg(call_sat_vector_vector_op_2833, 4, sat_vector_vector_op_2833_arg4); + setArg(call_sat_vector_vector_op_2833, 5, sat_vector_vector_op_2833_arg5); + setArg(call_sat_vector_vector_op_2833, 6, sat_vector_vector_op_2833_arg6); + setArg(call_sat_vector_vector_op_2833, 7, vm); + setArg(call_sat_vector_vector_op_2833, 8, vd); + setArg(call_sat_vector_vector_op_2833, 9, vs2); + setArg(call_sat_vector_vector_op_2833, 10, vs1); + setArg(call_sat_vector_vector_op_2833, 11, sat_vector_vector_op_2833_arg11); + setRet(call_sat_vector_vector_op_2833, 0, ret_val_sat_vector_vector_op_2833); } cc.bind(label_merge); } - auto tmp2825 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2825, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2825, 32, false) - , traits::vstart); + auto tmp2835 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2835, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2835, traits::vstart); } cc.bind(label_merge); } @@ -67093,16 +66845,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2826; - x86::Gp ret_val_illegal_normal_2826 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2826, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2827 = get_reg(cc, 8, false); - mov(cc, tmp2827, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2827, ret_val_illegal_normal_2826); - setArg(call_illegal_normal_2826, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2826, 1, vd); - setArg(call_illegal_normal_2826, 2, vm); - setRet(call_illegal_normal_2826, 0, ret_val_illegal_normal_2826); + InvokeNode* call_illegal_normal_2836; + x86::Gp ret_val_illegal_normal_2836 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2836, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2837 = get_reg(cc, 8, false); + mov(cc, tmp2837, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2837, ret_val_illegal_normal_2836); + setArg(call_illegal_normal_2836, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2836, 1, vd); + setArg(call_illegal_normal_2836, 2, vm); + setRet(call_illegal_normal_2836, 0, ret_val_illegal_normal_2836); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -67118,45 +66870,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2829; - x86::Gp ret_val_sew_2829 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2829, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2828; - auto sat_vector_imm_op_2828_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2828_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2828_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2828_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2828_arg10 = gen_ext(cc, + InvokeNode* call_sew_2839; + x86::Gp ret_val_sew_2839 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2839, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2838; + auto sat_vector_imm_op_2838_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2838_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2838_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2838_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2838_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); - auto sat_vector_imm_op_2828_arg11 = ret_val_sew_2829; + auto sat_vector_imm_op_2838_arg11 = ret_val_sew_2839; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2828 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2828, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2828; - setArg(call_sew_2829, 0, reinterpret_cast(this)); - setRet(call_sew_2829, 0, ret_val_sew_2829); - setArg(call_sat_vector_imm_op_2828, 0, V); - setArg(call_sat_vector_imm_op_2828, 1, 8); - setArg(call_sat_vector_imm_op_2828, 2, 6); - setArg(call_sat_vector_imm_op_2828, 3, sat_vector_imm_op_2828_arg3); - setArg(call_sat_vector_imm_op_2828, 4, sat_vector_imm_op_2828_arg4); - setArg(call_sat_vector_imm_op_2828, 5, sat_vector_imm_op_2828_arg5); - setArg(call_sat_vector_imm_op_2828, 6, sat_vector_imm_op_2828_arg6); - setArg(call_sat_vector_imm_op_2828, 7, vm); - setArg(call_sat_vector_imm_op_2828, 8, vd); - setArg(call_sat_vector_imm_op_2828, 9, vs2); - setArg(call_sat_vector_imm_op_2828, 10, sat_vector_imm_op_2828_arg10); - setArg(call_sat_vector_imm_op_2828, 11, sat_vector_imm_op_2828_arg11); - setRet(call_sat_vector_imm_op_2828, 0, ret_val_sat_vector_imm_op_2828); + x86::Gp ret_val_sat_vector_imm_op_2838 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2838, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2838; + setArg(call_sew_2839, 0, reinterpret_cast(this)); + setRet(call_sew_2839, 0, ret_val_sew_2839); + setArg(call_sat_vector_imm_op_2838, 0, V); + setArg(call_sat_vector_imm_op_2838, 1, 8); + setArg(call_sat_vector_imm_op_2838, 2, 6); + setArg(call_sat_vector_imm_op_2838, 3, sat_vector_imm_op_2838_arg3); + setArg(call_sat_vector_imm_op_2838, 4, sat_vector_imm_op_2838_arg4); + setArg(call_sat_vector_imm_op_2838, 5, sat_vector_imm_op_2838_arg5); + setArg(call_sat_vector_imm_op_2838, 6, sat_vector_imm_op_2838_arg6); + setArg(call_sat_vector_imm_op_2838, 7, vm); + setArg(call_sat_vector_imm_op_2838, 8, vd); + setArg(call_sat_vector_imm_op_2838, 9, vs2); + setArg(call_sat_vector_imm_op_2838, 10, sat_vector_imm_op_2838_arg10); + setArg(call_sat_vector_imm_op_2838, 11, sat_vector_imm_op_2838_arg11); + setRet(call_sat_vector_imm_op_2838, 0, ret_val_sat_vector_imm_op_2838); } cc.bind(label_merge); } - auto tmp2830 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2830, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2830, 32, false) - , traits::vstart); + auto tmp2840 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2840, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2840, traits::vstart); } cc.bind(label_merge); } @@ -67202,14 +66952,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2831; - x86::Gp ret_val_illegal_normal_2831 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2831, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2831; - setArg(call_illegal_normal_2831, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2831, 1, vd); - setArg(call_illegal_normal_2831, 2, vm); - setRet(call_illegal_normal_2831, 0, ret_val_illegal_normal_2831); + InvokeNode* call_illegal_normal_2841; + x86::Gp ret_val_illegal_normal_2841 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2841, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2841; + setArg(call_illegal_normal_2841, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2841, 1, vd); + setArg(call_illegal_normal_2841, 2, vm); + setRet(call_illegal_normal_2841, 0, ret_val_illegal_normal_2841); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -67225,42 +66975,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2833; - x86::Gp ret_val_sew_2833 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2833, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2832; - auto sat_vector_vector_op_2832_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2832_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2832_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2832_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2832_arg11 = ret_val_sew_2833; + InvokeNode* call_sew_2843; + x86::Gp ret_val_sew_2843 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2843, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2842; + auto sat_vector_vector_op_2842_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2842_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2842_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2842_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2842_arg11 = ret_val_sew_2843; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2832 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2832, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2832; - setArg(call_sew_2833, 0, reinterpret_cast(this)); - setRet(call_sew_2833, 0, ret_val_sew_2833); - setArg(call_sat_vector_vector_op_2832, 0, V); - setArg(call_sat_vector_vector_op_2832, 1, 9); - setArg(call_sat_vector_vector_op_2832, 2, 2); - setArg(call_sat_vector_vector_op_2832, 3, sat_vector_vector_op_2832_arg3); - setArg(call_sat_vector_vector_op_2832, 4, sat_vector_vector_op_2832_arg4); - setArg(call_sat_vector_vector_op_2832, 5, sat_vector_vector_op_2832_arg5); - setArg(call_sat_vector_vector_op_2832, 6, sat_vector_vector_op_2832_arg6); - setArg(call_sat_vector_vector_op_2832, 7, vm); - setArg(call_sat_vector_vector_op_2832, 8, vd); - setArg(call_sat_vector_vector_op_2832, 9, vs2); - setArg(call_sat_vector_vector_op_2832, 10, vs1); - setArg(call_sat_vector_vector_op_2832, 11, sat_vector_vector_op_2832_arg11); - setRet(call_sat_vector_vector_op_2832, 0, ret_val_sat_vector_vector_op_2832); + x86::Gp ret_val_sat_vector_vector_op_2842 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2842, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2842; + setArg(call_sew_2843, 0, reinterpret_cast(this)); + setRet(call_sew_2843, 0, ret_val_sew_2843); + setArg(call_sat_vector_vector_op_2842, 0, V); + setArg(call_sat_vector_vector_op_2842, 1, 9); + setArg(call_sat_vector_vector_op_2842, 2, 2); + setArg(call_sat_vector_vector_op_2842, 3, sat_vector_vector_op_2842_arg3); + setArg(call_sat_vector_vector_op_2842, 4, sat_vector_vector_op_2842_arg4); + setArg(call_sat_vector_vector_op_2842, 5, sat_vector_vector_op_2842_arg5); + setArg(call_sat_vector_vector_op_2842, 6, sat_vector_vector_op_2842_arg6); + setArg(call_sat_vector_vector_op_2842, 7, vm); + setArg(call_sat_vector_vector_op_2842, 8, vd); + setArg(call_sat_vector_vector_op_2842, 9, vs2); + setArg(call_sat_vector_vector_op_2842, 10, vs1); + setArg(call_sat_vector_vector_op_2842, 11, sat_vector_vector_op_2842_arg11); + setRet(call_sat_vector_vector_op_2842, 0, ret_val_sat_vector_vector_op_2842); } cc.bind(label_merge); } - auto tmp2834 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2834, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2834, 32, false) - , traits::vstart); + auto tmp2844 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2844, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2844, traits::vstart); } cc.bind(label_merge); } @@ -67306,16 +67054,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2835; - x86::Gp ret_val_illegal_normal_2835 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2835, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2836 = get_reg(cc, 8, false); - mov(cc, tmp2836, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2836, ret_val_illegal_normal_2835); - setArg(call_illegal_normal_2835, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2835, 1, vd); - setArg(call_illegal_normal_2835, 2, vm); - setRet(call_illegal_normal_2835, 0, ret_val_illegal_normal_2835); + InvokeNode* call_illegal_normal_2845; + x86::Gp ret_val_illegal_normal_2845 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2845, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2846 = get_reg(cc, 8, false); + mov(cc, tmp2846, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2846, ret_val_illegal_normal_2845); + setArg(call_illegal_normal_2845, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2845, 1, vd); + setArg(call_illegal_normal_2845, 2, vm); + setRet(call_illegal_normal_2845, 0, ret_val_illegal_normal_2845); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -67331,45 +67079,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2838; - x86::Gp ret_val_sew_2838 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2838, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2837; - auto sat_vector_imm_op_2837_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2837_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2837_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2837_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2837_arg10 = gen_ext(cc, + InvokeNode* call_sew_2848; + x86::Gp ret_val_sew_2848 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2848, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2847; + auto sat_vector_imm_op_2847_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2847_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2847_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2847_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2847_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); - auto sat_vector_imm_op_2837_arg11 = ret_val_sew_2838; + auto sat_vector_imm_op_2847_arg11 = ret_val_sew_2848; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2837 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2837, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2837; - setArg(call_sew_2838, 0, reinterpret_cast(this)); - setRet(call_sew_2838, 0, ret_val_sew_2838); - setArg(call_sat_vector_imm_op_2837, 0, V); - setArg(call_sat_vector_imm_op_2837, 1, 9); - setArg(call_sat_vector_imm_op_2837, 2, 6); - setArg(call_sat_vector_imm_op_2837, 3, sat_vector_imm_op_2837_arg3); - setArg(call_sat_vector_imm_op_2837, 4, sat_vector_imm_op_2837_arg4); - setArg(call_sat_vector_imm_op_2837, 5, sat_vector_imm_op_2837_arg5); - setArg(call_sat_vector_imm_op_2837, 6, sat_vector_imm_op_2837_arg6); - setArg(call_sat_vector_imm_op_2837, 7, vm); - setArg(call_sat_vector_imm_op_2837, 8, vd); - setArg(call_sat_vector_imm_op_2837, 9, vs2); - setArg(call_sat_vector_imm_op_2837, 10, sat_vector_imm_op_2837_arg10); - setArg(call_sat_vector_imm_op_2837, 11, sat_vector_imm_op_2837_arg11); - setRet(call_sat_vector_imm_op_2837, 0, ret_val_sat_vector_imm_op_2837); + x86::Gp ret_val_sat_vector_imm_op_2847 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2847, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2847; + setArg(call_sew_2848, 0, reinterpret_cast(this)); + setRet(call_sew_2848, 0, ret_val_sew_2848); + setArg(call_sat_vector_imm_op_2847, 0, V); + setArg(call_sat_vector_imm_op_2847, 1, 9); + setArg(call_sat_vector_imm_op_2847, 2, 6); + setArg(call_sat_vector_imm_op_2847, 3, sat_vector_imm_op_2847_arg3); + setArg(call_sat_vector_imm_op_2847, 4, sat_vector_imm_op_2847_arg4); + setArg(call_sat_vector_imm_op_2847, 5, sat_vector_imm_op_2847_arg5); + setArg(call_sat_vector_imm_op_2847, 6, sat_vector_imm_op_2847_arg6); + setArg(call_sat_vector_imm_op_2847, 7, vm); + setArg(call_sat_vector_imm_op_2847, 8, vd); + setArg(call_sat_vector_imm_op_2847, 9, vs2); + setArg(call_sat_vector_imm_op_2847, 10, sat_vector_imm_op_2847_arg10); + setArg(call_sat_vector_imm_op_2847, 11, sat_vector_imm_op_2847_arg11); + setRet(call_sat_vector_imm_op_2847, 0, ret_val_sat_vector_imm_op_2847); } cc.bind(label_merge); } - auto tmp2839 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2839, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2839, 32, false) - , traits::vstart); + auto tmp2849 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2849, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2849, traits::vstart); } cc.bind(label_merge); } @@ -67415,14 +67161,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2840; - x86::Gp ret_val_illegal_normal_2840 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2840, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2840; - setArg(call_illegal_normal_2840, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2840, 1, vd); - setArg(call_illegal_normal_2840, 2, vm); - setRet(call_illegal_normal_2840, 0, ret_val_illegal_normal_2840); + InvokeNode* call_illegal_normal_2850; + x86::Gp ret_val_illegal_normal_2850 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2850, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2850; + setArg(call_illegal_normal_2850, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2850, 1, vd); + setArg(call_illegal_normal_2850, 2, vm); + setRet(call_illegal_normal_2850, 0, ret_val_illegal_normal_2850); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -67438,42 +67184,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2842; - x86::Gp ret_val_sew_2842 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2842, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2841; - auto sat_vector_vector_op_2841_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2841_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2841_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2841_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2841_arg11 = ret_val_sew_2842; + InvokeNode* call_sew_2852; + x86::Gp ret_val_sew_2852 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2852, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2851; + auto sat_vector_vector_op_2851_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2851_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2851_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2851_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2851_arg11 = ret_val_sew_2852; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2841 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2841, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2841; - setArg(call_sew_2842, 0, reinterpret_cast(this)); - setRet(call_sew_2842, 0, ret_val_sew_2842); - setArg(call_sat_vector_vector_op_2841, 0, V); - setArg(call_sat_vector_vector_op_2841, 1, 10); - setArg(call_sat_vector_vector_op_2841, 2, 2); - setArg(call_sat_vector_vector_op_2841, 3, sat_vector_vector_op_2841_arg3); - setArg(call_sat_vector_vector_op_2841, 4, sat_vector_vector_op_2841_arg4); - setArg(call_sat_vector_vector_op_2841, 5, sat_vector_vector_op_2841_arg5); - setArg(call_sat_vector_vector_op_2841, 6, sat_vector_vector_op_2841_arg6); - setArg(call_sat_vector_vector_op_2841, 7, vm); - setArg(call_sat_vector_vector_op_2841, 8, vd); - setArg(call_sat_vector_vector_op_2841, 9, vs2); - setArg(call_sat_vector_vector_op_2841, 10, vs1); - setArg(call_sat_vector_vector_op_2841, 11, sat_vector_vector_op_2841_arg11); - setRet(call_sat_vector_vector_op_2841, 0, ret_val_sat_vector_vector_op_2841); + x86::Gp ret_val_sat_vector_vector_op_2851 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2851, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2851; + setArg(call_sew_2852, 0, reinterpret_cast(this)); + setRet(call_sew_2852, 0, ret_val_sew_2852); + setArg(call_sat_vector_vector_op_2851, 0, V); + setArg(call_sat_vector_vector_op_2851, 1, 10); + setArg(call_sat_vector_vector_op_2851, 2, 2); + setArg(call_sat_vector_vector_op_2851, 3, sat_vector_vector_op_2851_arg3); + setArg(call_sat_vector_vector_op_2851, 4, sat_vector_vector_op_2851_arg4); + setArg(call_sat_vector_vector_op_2851, 5, sat_vector_vector_op_2851_arg5); + setArg(call_sat_vector_vector_op_2851, 6, sat_vector_vector_op_2851_arg6); + setArg(call_sat_vector_vector_op_2851, 7, vm); + setArg(call_sat_vector_vector_op_2851, 8, vd); + setArg(call_sat_vector_vector_op_2851, 9, vs2); + setArg(call_sat_vector_vector_op_2851, 10, vs1); + setArg(call_sat_vector_vector_op_2851, 11, sat_vector_vector_op_2851_arg11); + setRet(call_sat_vector_vector_op_2851, 0, ret_val_sat_vector_vector_op_2851); } cc.bind(label_merge); } - auto tmp2843 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2843, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2843, 32, false) - , traits::vstart); + auto tmp2853 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2853, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2853, traits::vstart); } cc.bind(label_merge); } @@ -67519,16 +67263,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2844; - x86::Gp ret_val_illegal_normal_2844 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2844, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2845 = get_reg(cc, 8, false); - mov(cc, tmp2845, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2845, ret_val_illegal_normal_2844); - setArg(call_illegal_normal_2844, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2844, 1, vd); - setArg(call_illegal_normal_2844, 2, vm); - setRet(call_illegal_normal_2844, 0, ret_val_illegal_normal_2844); + InvokeNode* call_illegal_normal_2854; + x86::Gp ret_val_illegal_normal_2854 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2854, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2855 = get_reg(cc, 8, false); + mov(cc, tmp2855, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2855, ret_val_illegal_normal_2854); + setArg(call_illegal_normal_2854, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2854, 1, vd); + setArg(call_illegal_normal_2854, 2, vm); + setRet(call_illegal_normal_2854, 0, ret_val_illegal_normal_2854); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -67544,45 +67288,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2847; - x86::Gp ret_val_sew_2847 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2847, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2846; - auto sat_vector_imm_op_2846_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2846_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2846_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2846_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2846_arg10 = gen_ext(cc, + InvokeNode* call_sew_2857; + x86::Gp ret_val_sew_2857 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2857, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2856; + auto sat_vector_imm_op_2856_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2856_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2856_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2856_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2856_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); - auto sat_vector_imm_op_2846_arg11 = ret_val_sew_2847; + auto sat_vector_imm_op_2856_arg11 = ret_val_sew_2857; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2846 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2846, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2846; - setArg(call_sew_2847, 0, reinterpret_cast(this)); - setRet(call_sew_2847, 0, ret_val_sew_2847); - setArg(call_sat_vector_imm_op_2846, 0, V); - setArg(call_sat_vector_imm_op_2846, 1, 10); - setArg(call_sat_vector_imm_op_2846, 2, 6); - setArg(call_sat_vector_imm_op_2846, 3, sat_vector_imm_op_2846_arg3); - setArg(call_sat_vector_imm_op_2846, 4, sat_vector_imm_op_2846_arg4); - setArg(call_sat_vector_imm_op_2846, 5, sat_vector_imm_op_2846_arg5); - setArg(call_sat_vector_imm_op_2846, 6, sat_vector_imm_op_2846_arg6); - setArg(call_sat_vector_imm_op_2846, 7, vm); - setArg(call_sat_vector_imm_op_2846, 8, vd); - setArg(call_sat_vector_imm_op_2846, 9, vs2); - setArg(call_sat_vector_imm_op_2846, 10, sat_vector_imm_op_2846_arg10); - setArg(call_sat_vector_imm_op_2846, 11, sat_vector_imm_op_2846_arg11); - setRet(call_sat_vector_imm_op_2846, 0, ret_val_sat_vector_imm_op_2846); + x86::Gp ret_val_sat_vector_imm_op_2856 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2856, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2856; + setArg(call_sew_2857, 0, reinterpret_cast(this)); + setRet(call_sew_2857, 0, ret_val_sew_2857); + setArg(call_sat_vector_imm_op_2856, 0, V); + setArg(call_sat_vector_imm_op_2856, 1, 10); + setArg(call_sat_vector_imm_op_2856, 2, 6); + setArg(call_sat_vector_imm_op_2856, 3, sat_vector_imm_op_2856_arg3); + setArg(call_sat_vector_imm_op_2856, 4, sat_vector_imm_op_2856_arg4); + setArg(call_sat_vector_imm_op_2856, 5, sat_vector_imm_op_2856_arg5); + setArg(call_sat_vector_imm_op_2856, 6, sat_vector_imm_op_2856_arg6); + setArg(call_sat_vector_imm_op_2856, 7, vm); + setArg(call_sat_vector_imm_op_2856, 8, vd); + setArg(call_sat_vector_imm_op_2856, 9, vs2); + setArg(call_sat_vector_imm_op_2856, 10, sat_vector_imm_op_2856_arg10); + setArg(call_sat_vector_imm_op_2856, 11, sat_vector_imm_op_2856_arg11); + setRet(call_sat_vector_imm_op_2856, 0, ret_val_sat_vector_imm_op_2856); } cc.bind(label_merge); } - auto tmp2848 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2848, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2848, 32, false) - , traits::vstart); + auto tmp2858 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2858, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2858, traits::vstart); } cc.bind(label_merge); } @@ -67628,14 +67370,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2849; - x86::Gp ret_val_illegal_normal_2849 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2849, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2849; - setArg(call_illegal_normal_2849, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2849, 1, vd); - setArg(call_illegal_normal_2849, 2, vm); - setRet(call_illegal_normal_2849, 0, ret_val_illegal_normal_2849); + InvokeNode* call_illegal_normal_2859; + x86::Gp ret_val_illegal_normal_2859 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2859, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2859; + setArg(call_illegal_normal_2859, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2859, 1, vd); + setArg(call_illegal_normal_2859, 2, vm); + setRet(call_illegal_normal_2859, 0, ret_val_illegal_normal_2859); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -67651,42 +67393,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2851; - x86::Gp ret_val_sew_2851 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2851, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2850; - auto sat_vector_vector_op_2850_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2850_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2850_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2850_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2850_arg11 = ret_val_sew_2851; + InvokeNode* call_sew_2861; + x86::Gp ret_val_sew_2861 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2861, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2860; + auto sat_vector_vector_op_2860_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2860_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2860_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2860_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2860_arg11 = ret_val_sew_2861; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2850 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2850, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2850; - setArg(call_sew_2851, 0, reinterpret_cast(this)); - setRet(call_sew_2851, 0, ret_val_sew_2851); - setArg(call_sat_vector_vector_op_2850, 0, V); - setArg(call_sat_vector_vector_op_2850, 1, 11); - setArg(call_sat_vector_vector_op_2850, 2, 2); - setArg(call_sat_vector_vector_op_2850, 3, sat_vector_vector_op_2850_arg3); - setArg(call_sat_vector_vector_op_2850, 4, sat_vector_vector_op_2850_arg4); - setArg(call_sat_vector_vector_op_2850, 5, sat_vector_vector_op_2850_arg5); - setArg(call_sat_vector_vector_op_2850, 6, sat_vector_vector_op_2850_arg6); - setArg(call_sat_vector_vector_op_2850, 7, vm); - setArg(call_sat_vector_vector_op_2850, 8, vd); - setArg(call_sat_vector_vector_op_2850, 9, vs2); - setArg(call_sat_vector_vector_op_2850, 10, vs1); - setArg(call_sat_vector_vector_op_2850, 11, sat_vector_vector_op_2850_arg11); - setRet(call_sat_vector_vector_op_2850, 0, ret_val_sat_vector_vector_op_2850); + x86::Gp ret_val_sat_vector_vector_op_2860 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2860, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2860; + setArg(call_sew_2861, 0, reinterpret_cast(this)); + setRet(call_sew_2861, 0, ret_val_sew_2861); + setArg(call_sat_vector_vector_op_2860, 0, V); + setArg(call_sat_vector_vector_op_2860, 1, 11); + setArg(call_sat_vector_vector_op_2860, 2, 2); + setArg(call_sat_vector_vector_op_2860, 3, sat_vector_vector_op_2860_arg3); + setArg(call_sat_vector_vector_op_2860, 4, sat_vector_vector_op_2860_arg4); + setArg(call_sat_vector_vector_op_2860, 5, sat_vector_vector_op_2860_arg5); + setArg(call_sat_vector_vector_op_2860, 6, sat_vector_vector_op_2860_arg6); + setArg(call_sat_vector_vector_op_2860, 7, vm); + setArg(call_sat_vector_vector_op_2860, 8, vd); + setArg(call_sat_vector_vector_op_2860, 9, vs2); + setArg(call_sat_vector_vector_op_2860, 10, vs1); + setArg(call_sat_vector_vector_op_2860, 11, sat_vector_vector_op_2860_arg11); + setRet(call_sat_vector_vector_op_2860, 0, ret_val_sat_vector_vector_op_2860); } cc.bind(label_merge); } - auto tmp2852 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2852, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2852, 32, false) - , traits::vstart); + auto tmp2862 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2862, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2862, traits::vstart); } cc.bind(label_merge); } @@ -67732,16 +67472,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2853; - x86::Gp ret_val_illegal_normal_2853 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2853, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2854 = get_reg(cc, 8, false); - mov(cc, tmp2854, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2854, ret_val_illegal_normal_2853); - setArg(call_illegal_normal_2853, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2853, 1, vd); - setArg(call_illegal_normal_2853, 2, vm); - setRet(call_illegal_normal_2853, 0, ret_val_illegal_normal_2853); + InvokeNode* call_illegal_normal_2863; + x86::Gp ret_val_illegal_normal_2863 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2863, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2864 = get_reg(cc, 8, false); + mov(cc, tmp2864, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2864, ret_val_illegal_normal_2863); + setArg(call_illegal_normal_2863, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2863, 1, vd); + setArg(call_illegal_normal_2863, 2, vm); + setRet(call_illegal_normal_2863, 0, ret_val_illegal_normal_2863); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -67757,45 +67497,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2856; - x86::Gp ret_val_sew_2856 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2856, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2855; - auto sat_vector_imm_op_2855_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2855_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2855_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2855_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2855_arg10 = gen_ext(cc, + InvokeNode* call_sew_2866; + x86::Gp ret_val_sew_2866 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2866, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2865; + auto sat_vector_imm_op_2865_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2865_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2865_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2865_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2865_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); - auto sat_vector_imm_op_2855_arg11 = ret_val_sew_2856; + auto sat_vector_imm_op_2865_arg11 = ret_val_sew_2866; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2855 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2855, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2855; - setArg(call_sew_2856, 0, reinterpret_cast(this)); - setRet(call_sew_2856, 0, ret_val_sew_2856); - setArg(call_sat_vector_imm_op_2855, 0, V); - setArg(call_sat_vector_imm_op_2855, 1, 11); - setArg(call_sat_vector_imm_op_2855, 2, 6); - setArg(call_sat_vector_imm_op_2855, 3, sat_vector_imm_op_2855_arg3); - setArg(call_sat_vector_imm_op_2855, 4, sat_vector_imm_op_2855_arg4); - setArg(call_sat_vector_imm_op_2855, 5, sat_vector_imm_op_2855_arg5); - setArg(call_sat_vector_imm_op_2855, 6, sat_vector_imm_op_2855_arg6); - setArg(call_sat_vector_imm_op_2855, 7, vm); - setArg(call_sat_vector_imm_op_2855, 8, vd); - setArg(call_sat_vector_imm_op_2855, 9, vs2); - setArg(call_sat_vector_imm_op_2855, 10, sat_vector_imm_op_2855_arg10); - setArg(call_sat_vector_imm_op_2855, 11, sat_vector_imm_op_2855_arg11); - setRet(call_sat_vector_imm_op_2855, 0, ret_val_sat_vector_imm_op_2855); + x86::Gp ret_val_sat_vector_imm_op_2865 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2865, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2865; + setArg(call_sew_2866, 0, reinterpret_cast(this)); + setRet(call_sew_2866, 0, ret_val_sew_2866); + setArg(call_sat_vector_imm_op_2865, 0, V); + setArg(call_sat_vector_imm_op_2865, 1, 11); + setArg(call_sat_vector_imm_op_2865, 2, 6); + setArg(call_sat_vector_imm_op_2865, 3, sat_vector_imm_op_2865_arg3); + setArg(call_sat_vector_imm_op_2865, 4, sat_vector_imm_op_2865_arg4); + setArg(call_sat_vector_imm_op_2865, 5, sat_vector_imm_op_2865_arg5); + setArg(call_sat_vector_imm_op_2865, 6, sat_vector_imm_op_2865_arg6); + setArg(call_sat_vector_imm_op_2865, 7, vm); + setArg(call_sat_vector_imm_op_2865, 8, vd); + setArg(call_sat_vector_imm_op_2865, 9, vs2); + setArg(call_sat_vector_imm_op_2865, 10, sat_vector_imm_op_2865_arg10); + setArg(call_sat_vector_imm_op_2865, 11, sat_vector_imm_op_2865_arg11); + setRet(call_sat_vector_imm_op_2865, 0, ret_val_sat_vector_imm_op_2865); } cc.bind(label_merge); } - auto tmp2857 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2857, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2857, 32, false) - , traits::vstart); + auto tmp2867 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2867, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2867, traits::vstart); } cc.bind(label_merge); } @@ -67841,14 +67579,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2858; - x86::Gp ret_val_illegal_normal_2858 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2858, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2858; - setArg(call_illegal_normal_2858, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2858, 1, vd); - setArg(call_illegal_normal_2858, 2, vm); - setRet(call_illegal_normal_2858, 0, ret_val_illegal_normal_2858); + InvokeNode* call_illegal_normal_2868; + x86::Gp ret_val_illegal_normal_2868 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2868, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2868; + setArg(call_illegal_normal_2868, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2868, 1, vd); + setArg(call_illegal_normal_2868, 2, vm); + setRet(call_illegal_normal_2868, 0, ret_val_illegal_normal_2868); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -67864,44 +67602,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2860; - x86::Gp ret_val_sew_2860 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2860, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2859; - auto sat_vector_vector_op_2859_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2859_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2859_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2859_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2859_arg11 = ret_val_sew_2860; + InvokeNode* call_sew_2870; + x86::Gp ret_val_sew_2870 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2870, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2869; + auto sat_vector_vector_op_2869_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2869_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2869_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2869_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2869_arg11 = ret_val_sew_2870; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2859 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2859, &sat_vector_vector_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_op_2859, 32, false) - , traits::vxsat); - setArg(call_sew_2860, 0, reinterpret_cast(this)); - setRet(call_sew_2860, 0, ret_val_sew_2860); - setArg(call_sat_vector_vector_op_2859, 0, V); - setArg(call_sat_vector_vector_op_2859, 1, 39); - setArg(call_sat_vector_vector_op_2859, 2, 0); - setArg(call_sat_vector_vector_op_2859, 3, sat_vector_vector_op_2859_arg3); - setArg(call_sat_vector_vector_op_2859, 4, sat_vector_vector_op_2859_arg4); - setArg(call_sat_vector_vector_op_2859, 5, sat_vector_vector_op_2859_arg5); - setArg(call_sat_vector_vector_op_2859, 6, sat_vector_vector_op_2859_arg6); - setArg(call_sat_vector_vector_op_2859, 7, vm); - setArg(call_sat_vector_vector_op_2859, 8, vd); - setArg(call_sat_vector_vector_op_2859, 9, vs2); - setArg(call_sat_vector_vector_op_2859, 10, vs1); - setArg(call_sat_vector_vector_op_2859, 11, sat_vector_vector_op_2859_arg11); - setRet(call_sat_vector_vector_op_2859, 0, ret_val_sat_vector_vector_op_2859); + x86::Gp ret_val_sat_vector_vector_op_2869 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2869, &sat_vector_vector_op, FuncSignature::build()); + auto tmp2871 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_op_2869, 32, false)); + write_reg_to_mem(jh, tmp2871, traits::vxsat); + setArg(call_sew_2870, 0, reinterpret_cast(this)); + setRet(call_sew_2870, 0, ret_val_sew_2870); + setArg(call_sat_vector_vector_op_2869, 0, V); + setArg(call_sat_vector_vector_op_2869, 1, 39); + setArg(call_sat_vector_vector_op_2869, 2, 0); + setArg(call_sat_vector_vector_op_2869, 3, sat_vector_vector_op_2869_arg3); + setArg(call_sat_vector_vector_op_2869, 4, sat_vector_vector_op_2869_arg4); + setArg(call_sat_vector_vector_op_2869, 5, sat_vector_vector_op_2869_arg5); + setArg(call_sat_vector_vector_op_2869, 6, sat_vector_vector_op_2869_arg6); + setArg(call_sat_vector_vector_op_2869, 7, vm); + setArg(call_sat_vector_vector_op_2869, 8, vd); + setArg(call_sat_vector_vector_op_2869, 9, vs2); + setArg(call_sat_vector_vector_op_2869, 10, vs1); + setArg(call_sat_vector_vector_op_2869, 11, sat_vector_vector_op_2869_arg11); + setRet(call_sat_vector_vector_op_2869, 0, ret_val_sat_vector_vector_op_2869); } cc.bind(label_merge); } - auto tmp2861 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2861, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2861, 32, false) - , traits::vstart); + auto tmp2872 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2872, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2872, traits::vstart); } cc.bind(label_merge); } @@ -67947,16 +67682,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2862; - x86::Gp ret_val_illegal_normal_2862 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2862, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2863 = get_reg(cc, 8, false); - mov(cc, tmp2863, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2863, ret_val_illegal_normal_2862); - setArg(call_illegal_normal_2862, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2862, 1, vd); - setArg(call_illegal_normal_2862, 2, vm); - setRet(call_illegal_normal_2862, 0, ret_val_illegal_normal_2862); + InvokeNode* call_illegal_normal_2873; + x86::Gp ret_val_illegal_normal_2873 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2873, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2874 = get_reg(cc, 8, false); + mov(cc, tmp2874, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2874, ret_val_illegal_normal_2873); + setArg(call_illegal_normal_2873, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2873, 1, vd); + setArg(call_illegal_normal_2873, 2, vm); + setRet(call_illegal_normal_2873, 0, ret_val_illegal_normal_2873); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -67972,47 +67707,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2865; - x86::Gp ret_val_sew_2865 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2865, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2864; - auto sat_vector_imm_op_2864_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2864_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2864_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2864_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2864_arg10 = gen_ext(cc, + InvokeNode* call_sew_2876; + x86::Gp ret_val_sew_2876 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2876, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2875; + auto sat_vector_imm_op_2875_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2875_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2875_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2875_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2875_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); - auto sat_vector_imm_op_2864_arg11 = ret_val_sew_2865; + auto sat_vector_imm_op_2875_arg11 = ret_val_sew_2876; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2864 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2864, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2864, 32, false) - , traits::vxsat); - setArg(call_sew_2865, 0, reinterpret_cast(this)); - setRet(call_sew_2865, 0, ret_val_sew_2865); - setArg(call_sat_vector_imm_op_2864, 0, V); - setArg(call_sat_vector_imm_op_2864, 1, 39); - setArg(call_sat_vector_imm_op_2864, 2, 4); - setArg(call_sat_vector_imm_op_2864, 3, sat_vector_imm_op_2864_arg3); - setArg(call_sat_vector_imm_op_2864, 4, sat_vector_imm_op_2864_arg4); - setArg(call_sat_vector_imm_op_2864, 5, sat_vector_imm_op_2864_arg5); - setArg(call_sat_vector_imm_op_2864, 6, sat_vector_imm_op_2864_arg6); - setArg(call_sat_vector_imm_op_2864, 7, vm); - setArg(call_sat_vector_imm_op_2864, 8, vd); - setArg(call_sat_vector_imm_op_2864, 9, vs2); - setArg(call_sat_vector_imm_op_2864, 10, sat_vector_imm_op_2864_arg10); - setArg(call_sat_vector_imm_op_2864, 11, sat_vector_imm_op_2864_arg11); - setRet(call_sat_vector_imm_op_2864, 0, ret_val_sat_vector_imm_op_2864); + x86::Gp ret_val_sat_vector_imm_op_2875 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2875, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2877 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2875, 32, false)); + write_reg_to_mem(jh, tmp2877, traits::vxsat); + setArg(call_sew_2876, 0, reinterpret_cast(this)); + setRet(call_sew_2876, 0, ret_val_sew_2876); + setArg(call_sat_vector_imm_op_2875, 0, V); + setArg(call_sat_vector_imm_op_2875, 1, 39); + setArg(call_sat_vector_imm_op_2875, 2, 4); + setArg(call_sat_vector_imm_op_2875, 3, sat_vector_imm_op_2875_arg3); + setArg(call_sat_vector_imm_op_2875, 4, sat_vector_imm_op_2875_arg4); + setArg(call_sat_vector_imm_op_2875, 5, sat_vector_imm_op_2875_arg5); + setArg(call_sat_vector_imm_op_2875, 6, sat_vector_imm_op_2875_arg6); + setArg(call_sat_vector_imm_op_2875, 7, vm); + setArg(call_sat_vector_imm_op_2875, 8, vd); + setArg(call_sat_vector_imm_op_2875, 9, vs2); + setArg(call_sat_vector_imm_op_2875, 10, sat_vector_imm_op_2875_arg10); + setArg(call_sat_vector_imm_op_2875, 11, sat_vector_imm_op_2875_arg11); + setRet(call_sat_vector_imm_op_2875, 0, ret_val_sat_vector_imm_op_2875); } cc.bind(label_merge); } - auto tmp2866 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2866, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2866, 32, false) - , traits::vstart); + auto tmp2878 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2878, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2878, traits::vstart); } cc.bind(label_merge); } @@ -68058,14 +67790,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2867; - x86::Gp ret_val_illegal_normal_2867 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2867, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2867; - setArg(call_illegal_normal_2867, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2867, 1, vd); - setArg(call_illegal_normal_2867, 2, vm); - setRet(call_illegal_normal_2867, 0, ret_val_illegal_normal_2867); + InvokeNode* call_illegal_normal_2879; + x86::Gp ret_val_illegal_normal_2879 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2879, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2879; + setArg(call_illegal_normal_2879, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2879, 1, vd); + setArg(call_illegal_normal_2879, 2, vm); + setRet(call_illegal_normal_2879, 0, ret_val_illegal_normal_2879); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68081,42 +67813,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2869; - x86::Gp ret_val_sew_2869 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2869, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2868; - auto sat_vector_imm_op_2868_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2868_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2868_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2868_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2868_arg11 = ret_val_sew_2869; + InvokeNode* call_sew_2881; + x86::Gp ret_val_sew_2881 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2881, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2880; + auto sat_vector_imm_op_2880_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2880_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2880_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2880_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2880_arg11 = ret_val_sew_2881; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2868 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2868, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2868; - setArg(call_sew_2869, 0, reinterpret_cast(this)); - setRet(call_sew_2869, 0, ret_val_sew_2869); - setArg(call_sat_vector_imm_op_2868, 0, V); - setArg(call_sat_vector_imm_op_2868, 1, 42); - setArg(call_sat_vector_imm_op_2868, 2, 3); - setArg(call_sat_vector_imm_op_2868, 3, sat_vector_imm_op_2868_arg3); - setArg(call_sat_vector_imm_op_2868, 4, sat_vector_imm_op_2868_arg4); - setArg(call_sat_vector_imm_op_2868, 5, sat_vector_imm_op_2868_arg5); - setArg(call_sat_vector_imm_op_2868, 6, sat_vector_imm_op_2868_arg6); - setArg(call_sat_vector_imm_op_2868, 7, vm); - setArg(call_sat_vector_imm_op_2868, 8, vd); - setArg(call_sat_vector_imm_op_2868, 9, vs2); - setArg(call_sat_vector_imm_op_2868, 10, (int32_t)(uint32_t)simm); - setArg(call_sat_vector_imm_op_2868, 11, sat_vector_imm_op_2868_arg11); - setRet(call_sat_vector_imm_op_2868, 0, ret_val_sat_vector_imm_op_2868); + x86::Gp ret_val_sat_vector_imm_op_2880 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2880, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2880; + setArg(call_sew_2881, 0, reinterpret_cast(this)); + setRet(call_sew_2881, 0, ret_val_sew_2881); + setArg(call_sat_vector_imm_op_2880, 0, V); + setArg(call_sat_vector_imm_op_2880, 1, 42); + setArg(call_sat_vector_imm_op_2880, 2, 3); + setArg(call_sat_vector_imm_op_2880, 3, sat_vector_imm_op_2880_arg3); + setArg(call_sat_vector_imm_op_2880, 4, sat_vector_imm_op_2880_arg4); + setArg(call_sat_vector_imm_op_2880, 5, sat_vector_imm_op_2880_arg5); + setArg(call_sat_vector_imm_op_2880, 6, sat_vector_imm_op_2880_arg6); + setArg(call_sat_vector_imm_op_2880, 7, vm); + setArg(call_sat_vector_imm_op_2880, 8, vd); + setArg(call_sat_vector_imm_op_2880, 9, vs2); + setArg(call_sat_vector_imm_op_2880, 10, (int32_t)(uint32_t)simm); + setArg(call_sat_vector_imm_op_2880, 11, sat_vector_imm_op_2880_arg11); + setRet(call_sat_vector_imm_op_2880, 0, ret_val_sat_vector_imm_op_2880); } cc.bind(label_merge); } - auto tmp2870 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2870, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2870, 32, false) - , traits::vstart); + auto tmp2882 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2882, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2882, traits::vstart); } cc.bind(label_merge); } @@ -68162,14 +67892,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2871; - x86::Gp ret_val_illegal_normal_2871 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2871, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2871; - setArg(call_illegal_normal_2871, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2871, 1, vd); - setArg(call_illegal_normal_2871, 2, vm); - setRet(call_illegal_normal_2871, 0, ret_val_illegal_normal_2871); + InvokeNode* call_illegal_normal_2883; + x86::Gp ret_val_illegal_normal_2883 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2883, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2883; + setArg(call_illegal_normal_2883, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2883, 1, vd); + setArg(call_illegal_normal_2883, 2, vm); + setRet(call_illegal_normal_2883, 0, ret_val_illegal_normal_2883); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68185,42 +67915,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2873; - x86::Gp ret_val_sew_2873 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2873, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2872; - auto sat_vector_vector_op_2872_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2872_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2872_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2872_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2872_arg11 = ret_val_sew_2873; + InvokeNode* call_sew_2885; + x86::Gp ret_val_sew_2885 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2885, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2884; + auto sat_vector_vector_op_2884_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2884_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2884_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2884_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2884_arg11 = ret_val_sew_2885; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2872 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2872, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2872; - setArg(call_sew_2873, 0, reinterpret_cast(this)); - setRet(call_sew_2873, 0, ret_val_sew_2873); - setArg(call_sat_vector_vector_op_2872, 0, V); - setArg(call_sat_vector_vector_op_2872, 1, 42); - setArg(call_sat_vector_vector_op_2872, 2, 0); - setArg(call_sat_vector_vector_op_2872, 3, sat_vector_vector_op_2872_arg3); - setArg(call_sat_vector_vector_op_2872, 4, sat_vector_vector_op_2872_arg4); - setArg(call_sat_vector_vector_op_2872, 5, sat_vector_vector_op_2872_arg5); - setArg(call_sat_vector_vector_op_2872, 6, sat_vector_vector_op_2872_arg6); - setArg(call_sat_vector_vector_op_2872, 7, vm); - setArg(call_sat_vector_vector_op_2872, 8, vd); - setArg(call_sat_vector_vector_op_2872, 9, vs2); - setArg(call_sat_vector_vector_op_2872, 10, vs1); - setArg(call_sat_vector_vector_op_2872, 11, sat_vector_vector_op_2872_arg11); - setRet(call_sat_vector_vector_op_2872, 0, ret_val_sat_vector_vector_op_2872); + x86::Gp ret_val_sat_vector_vector_op_2884 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2884, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2884; + setArg(call_sew_2885, 0, reinterpret_cast(this)); + setRet(call_sew_2885, 0, ret_val_sew_2885); + setArg(call_sat_vector_vector_op_2884, 0, V); + setArg(call_sat_vector_vector_op_2884, 1, 42); + setArg(call_sat_vector_vector_op_2884, 2, 0); + setArg(call_sat_vector_vector_op_2884, 3, sat_vector_vector_op_2884_arg3); + setArg(call_sat_vector_vector_op_2884, 4, sat_vector_vector_op_2884_arg4); + setArg(call_sat_vector_vector_op_2884, 5, sat_vector_vector_op_2884_arg5); + setArg(call_sat_vector_vector_op_2884, 6, sat_vector_vector_op_2884_arg6); + setArg(call_sat_vector_vector_op_2884, 7, vm); + setArg(call_sat_vector_vector_op_2884, 8, vd); + setArg(call_sat_vector_vector_op_2884, 9, vs2); + setArg(call_sat_vector_vector_op_2884, 10, vs1); + setArg(call_sat_vector_vector_op_2884, 11, sat_vector_vector_op_2884_arg11); + setRet(call_sat_vector_vector_op_2884, 0, ret_val_sat_vector_vector_op_2884); } cc.bind(label_merge); } - auto tmp2874 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2874, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2874, 32, false) - , traits::vstart); + auto tmp2886 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2886, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2886, traits::vstart); } cc.bind(label_merge); } @@ -68266,16 +67994,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2875; - x86::Gp ret_val_illegal_normal_2875 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2875, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2876 = get_reg(cc, 8, false); - mov(cc, tmp2876, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2876, ret_val_illegal_normal_2875); - setArg(call_illegal_normal_2875, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2875, 1, vd); - setArg(call_illegal_normal_2875, 2, vm); - setRet(call_illegal_normal_2875, 0, ret_val_illegal_normal_2875); + InvokeNode* call_illegal_normal_2887; + x86::Gp ret_val_illegal_normal_2887 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2887, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2888 = get_reg(cc, 8, false); + mov(cc, tmp2888, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2888, ret_val_illegal_normal_2887); + setArg(call_illegal_normal_2887, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2887, 1, vd); + setArg(call_illegal_normal_2887, 2, vm); + setRet(call_illegal_normal_2887, 0, ret_val_illegal_normal_2887); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68291,45 +68019,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2878; - x86::Gp ret_val_sew_2878 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2878, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2877; - auto sat_vector_imm_op_2877_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2877_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2877_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2877_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2877_arg10 = gen_ext(cc, + InvokeNode* call_sew_2890; + x86::Gp ret_val_sew_2890 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2890, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2889; + auto sat_vector_imm_op_2889_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2889_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2889_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2889_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2889_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); - auto sat_vector_imm_op_2877_arg11 = ret_val_sew_2878; + auto sat_vector_imm_op_2889_arg11 = ret_val_sew_2890; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2877 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2877, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2877; - setArg(call_sew_2878, 0, reinterpret_cast(this)); - setRet(call_sew_2878, 0, ret_val_sew_2878); - setArg(call_sat_vector_imm_op_2877, 0, V); - setArg(call_sat_vector_imm_op_2877, 1, 42); - setArg(call_sat_vector_imm_op_2877, 2, 4); - setArg(call_sat_vector_imm_op_2877, 3, sat_vector_imm_op_2877_arg3); - setArg(call_sat_vector_imm_op_2877, 4, sat_vector_imm_op_2877_arg4); - setArg(call_sat_vector_imm_op_2877, 5, sat_vector_imm_op_2877_arg5); - setArg(call_sat_vector_imm_op_2877, 6, sat_vector_imm_op_2877_arg6); - setArg(call_sat_vector_imm_op_2877, 7, vm); - setArg(call_sat_vector_imm_op_2877, 8, vd); - setArg(call_sat_vector_imm_op_2877, 9, vs2); - setArg(call_sat_vector_imm_op_2877, 10, sat_vector_imm_op_2877_arg10); - setArg(call_sat_vector_imm_op_2877, 11, sat_vector_imm_op_2877_arg11); - setRet(call_sat_vector_imm_op_2877, 0, ret_val_sat_vector_imm_op_2877); + x86::Gp ret_val_sat_vector_imm_op_2889 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2889, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2889; + setArg(call_sew_2890, 0, reinterpret_cast(this)); + setRet(call_sew_2890, 0, ret_val_sew_2890); + setArg(call_sat_vector_imm_op_2889, 0, V); + setArg(call_sat_vector_imm_op_2889, 1, 42); + setArg(call_sat_vector_imm_op_2889, 2, 4); + setArg(call_sat_vector_imm_op_2889, 3, sat_vector_imm_op_2889_arg3); + setArg(call_sat_vector_imm_op_2889, 4, sat_vector_imm_op_2889_arg4); + setArg(call_sat_vector_imm_op_2889, 5, sat_vector_imm_op_2889_arg5); + setArg(call_sat_vector_imm_op_2889, 6, sat_vector_imm_op_2889_arg6); + setArg(call_sat_vector_imm_op_2889, 7, vm); + setArg(call_sat_vector_imm_op_2889, 8, vd); + setArg(call_sat_vector_imm_op_2889, 9, vs2); + setArg(call_sat_vector_imm_op_2889, 10, sat_vector_imm_op_2889_arg10); + setArg(call_sat_vector_imm_op_2889, 11, sat_vector_imm_op_2889_arg11); + setRet(call_sat_vector_imm_op_2889, 0, ret_val_sat_vector_imm_op_2889); } cc.bind(label_merge); } - auto tmp2879 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2879, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2879, 32, false) - , traits::vstart); + auto tmp2891 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2891, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2891, traits::vstart); } cc.bind(label_merge); } @@ -68375,14 +68101,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2880; - x86::Gp ret_val_illegal_normal_2880 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2880, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2880; - setArg(call_illegal_normal_2880, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2880, 1, vd); - setArg(call_illegal_normal_2880, 2, vm); - setRet(call_illegal_normal_2880, 0, ret_val_illegal_normal_2880); + InvokeNode* call_illegal_normal_2892; + x86::Gp ret_val_illegal_normal_2892 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2892, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2892; + setArg(call_illegal_normal_2892, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2892, 1, vd); + setArg(call_illegal_normal_2892, 2, vm); + setRet(call_illegal_normal_2892, 0, ret_val_illegal_normal_2892); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68398,42 +68124,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2882; - x86::Gp ret_val_sew_2882 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2882, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2881; - auto sat_vector_imm_op_2881_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2881_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2881_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2881_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2881_arg11 = ret_val_sew_2882; + InvokeNode* call_sew_2894; + x86::Gp ret_val_sew_2894 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2894, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2893; + auto sat_vector_imm_op_2893_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2893_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2893_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2893_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2893_arg11 = ret_val_sew_2894; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2881 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2881, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2881; - setArg(call_sew_2882, 0, reinterpret_cast(this)); - setRet(call_sew_2882, 0, ret_val_sew_2882); - setArg(call_sat_vector_imm_op_2881, 0, V); - setArg(call_sat_vector_imm_op_2881, 1, 43); - setArg(call_sat_vector_imm_op_2881, 2, 3); - setArg(call_sat_vector_imm_op_2881, 3, sat_vector_imm_op_2881_arg3); - setArg(call_sat_vector_imm_op_2881, 4, sat_vector_imm_op_2881_arg4); - setArg(call_sat_vector_imm_op_2881, 5, sat_vector_imm_op_2881_arg5); - setArg(call_sat_vector_imm_op_2881, 6, sat_vector_imm_op_2881_arg6); - setArg(call_sat_vector_imm_op_2881, 7, vm); - setArg(call_sat_vector_imm_op_2881, 8, vd); - setArg(call_sat_vector_imm_op_2881, 9, vs2); - setArg(call_sat_vector_imm_op_2881, 10, (int32_t)(uint32_t)simm); - setArg(call_sat_vector_imm_op_2881, 11, sat_vector_imm_op_2881_arg11); - setRet(call_sat_vector_imm_op_2881, 0, ret_val_sat_vector_imm_op_2881); + x86::Gp ret_val_sat_vector_imm_op_2893 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2893, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2893; + setArg(call_sew_2894, 0, reinterpret_cast(this)); + setRet(call_sew_2894, 0, ret_val_sew_2894); + setArg(call_sat_vector_imm_op_2893, 0, V); + setArg(call_sat_vector_imm_op_2893, 1, 43); + setArg(call_sat_vector_imm_op_2893, 2, 3); + setArg(call_sat_vector_imm_op_2893, 3, sat_vector_imm_op_2893_arg3); + setArg(call_sat_vector_imm_op_2893, 4, sat_vector_imm_op_2893_arg4); + setArg(call_sat_vector_imm_op_2893, 5, sat_vector_imm_op_2893_arg5); + setArg(call_sat_vector_imm_op_2893, 6, sat_vector_imm_op_2893_arg6); + setArg(call_sat_vector_imm_op_2893, 7, vm); + setArg(call_sat_vector_imm_op_2893, 8, vd); + setArg(call_sat_vector_imm_op_2893, 9, vs2); + setArg(call_sat_vector_imm_op_2893, 10, (int32_t)(uint32_t)simm); + setArg(call_sat_vector_imm_op_2893, 11, sat_vector_imm_op_2893_arg11); + setRet(call_sat_vector_imm_op_2893, 0, ret_val_sat_vector_imm_op_2893); } cc.bind(label_merge); } - auto tmp2883 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2883, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2883, 32, false) - , traits::vstart); + auto tmp2895 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2895, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2895, traits::vstart); } cc.bind(label_merge); } @@ -68479,14 +68203,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2884; - x86::Gp ret_val_illegal_normal_2884 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2884, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2884; - setArg(call_illegal_normal_2884, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2884, 1, vd); - setArg(call_illegal_normal_2884, 2, vm); - setRet(call_illegal_normal_2884, 0, ret_val_illegal_normal_2884); + InvokeNode* call_illegal_normal_2896; + x86::Gp ret_val_illegal_normal_2896 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2896, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2896; + setArg(call_illegal_normal_2896, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2896, 1, vd); + setArg(call_illegal_normal_2896, 2, vm); + setRet(call_illegal_normal_2896, 0, ret_val_illegal_normal_2896); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68502,42 +68226,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2886; - x86::Gp ret_val_sew_2886 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2886, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2885; - auto sat_vector_vector_op_2885_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2885_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2885_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2885_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2885_arg11 = ret_val_sew_2886; + InvokeNode* call_sew_2898; + x86::Gp ret_val_sew_2898 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2898, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2897; + auto sat_vector_vector_op_2897_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2897_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2897_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2897_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2897_arg11 = ret_val_sew_2898; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2885 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2885, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2885; - setArg(call_sew_2886, 0, reinterpret_cast(this)); - setRet(call_sew_2886, 0, ret_val_sew_2886); - setArg(call_sat_vector_vector_op_2885, 0, V); - setArg(call_sat_vector_vector_op_2885, 1, 43); - setArg(call_sat_vector_vector_op_2885, 2, 0); - setArg(call_sat_vector_vector_op_2885, 3, sat_vector_vector_op_2885_arg3); - setArg(call_sat_vector_vector_op_2885, 4, sat_vector_vector_op_2885_arg4); - setArg(call_sat_vector_vector_op_2885, 5, sat_vector_vector_op_2885_arg5); - setArg(call_sat_vector_vector_op_2885, 6, sat_vector_vector_op_2885_arg6); - setArg(call_sat_vector_vector_op_2885, 7, vm); - setArg(call_sat_vector_vector_op_2885, 8, vd); - setArg(call_sat_vector_vector_op_2885, 9, vs2); - setArg(call_sat_vector_vector_op_2885, 10, vs1); - setArg(call_sat_vector_vector_op_2885, 11, sat_vector_vector_op_2885_arg11); - setRet(call_sat_vector_vector_op_2885, 0, ret_val_sat_vector_vector_op_2885); + x86::Gp ret_val_sat_vector_vector_op_2897 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2897, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2897; + setArg(call_sew_2898, 0, reinterpret_cast(this)); + setRet(call_sew_2898, 0, ret_val_sew_2898); + setArg(call_sat_vector_vector_op_2897, 0, V); + setArg(call_sat_vector_vector_op_2897, 1, 43); + setArg(call_sat_vector_vector_op_2897, 2, 0); + setArg(call_sat_vector_vector_op_2897, 3, sat_vector_vector_op_2897_arg3); + setArg(call_sat_vector_vector_op_2897, 4, sat_vector_vector_op_2897_arg4); + setArg(call_sat_vector_vector_op_2897, 5, sat_vector_vector_op_2897_arg5); + setArg(call_sat_vector_vector_op_2897, 6, sat_vector_vector_op_2897_arg6); + setArg(call_sat_vector_vector_op_2897, 7, vm); + setArg(call_sat_vector_vector_op_2897, 8, vd); + setArg(call_sat_vector_vector_op_2897, 9, vs2); + setArg(call_sat_vector_vector_op_2897, 10, vs1); + setArg(call_sat_vector_vector_op_2897, 11, sat_vector_vector_op_2897_arg11); + setRet(call_sat_vector_vector_op_2897, 0, ret_val_sat_vector_vector_op_2897); } cc.bind(label_merge); } - auto tmp2887 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2887, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2887, 32, false) - , traits::vstart); + auto tmp2899 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2899, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2899, traits::vstart); } cc.bind(label_merge); } @@ -68583,16 +68305,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2888; - x86::Gp ret_val_illegal_normal_2888 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2888, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2889 = get_reg(cc, 8, false); - mov(cc, tmp2889, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2889, ret_val_illegal_normal_2888); - setArg(call_illegal_normal_2888, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2888, 1, vd); - setArg(call_illegal_normal_2888, 2, vm); - setRet(call_illegal_normal_2888, 0, ret_val_illegal_normal_2888); + InvokeNode* call_illegal_normal_2900; + x86::Gp ret_val_illegal_normal_2900 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2900, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2901 = get_reg(cc, 8, false); + mov(cc, tmp2901, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2901, ret_val_illegal_normal_2900); + setArg(call_illegal_normal_2900, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2900, 1, vd); + setArg(call_illegal_normal_2900, 2, vm); + setRet(call_illegal_normal_2900, 0, ret_val_illegal_normal_2900); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68608,45 +68330,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2891; - x86::Gp ret_val_sew_2891 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2891, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2890; - auto sat_vector_imm_op_2890_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2890_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2890_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2890_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2890_arg10 = gen_ext(cc, + InvokeNode* call_sew_2903; + x86::Gp ret_val_sew_2903 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2903, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2902; + auto sat_vector_imm_op_2902_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2902_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2902_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2902_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2902_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); - auto sat_vector_imm_op_2890_arg11 = ret_val_sew_2891; + auto sat_vector_imm_op_2902_arg11 = ret_val_sew_2903; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2890 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2890, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2890; - setArg(call_sew_2891, 0, reinterpret_cast(this)); - setRet(call_sew_2891, 0, ret_val_sew_2891); - setArg(call_sat_vector_imm_op_2890, 0, V); - setArg(call_sat_vector_imm_op_2890, 1, 43); - setArg(call_sat_vector_imm_op_2890, 2, 4); - setArg(call_sat_vector_imm_op_2890, 3, sat_vector_imm_op_2890_arg3); - setArg(call_sat_vector_imm_op_2890, 4, sat_vector_imm_op_2890_arg4); - setArg(call_sat_vector_imm_op_2890, 5, sat_vector_imm_op_2890_arg5); - setArg(call_sat_vector_imm_op_2890, 6, sat_vector_imm_op_2890_arg6); - setArg(call_sat_vector_imm_op_2890, 7, vm); - setArg(call_sat_vector_imm_op_2890, 8, vd); - setArg(call_sat_vector_imm_op_2890, 9, vs2); - setArg(call_sat_vector_imm_op_2890, 10, sat_vector_imm_op_2890_arg10); - setArg(call_sat_vector_imm_op_2890, 11, sat_vector_imm_op_2890_arg11); - setRet(call_sat_vector_imm_op_2890, 0, ret_val_sat_vector_imm_op_2890); + x86::Gp ret_val_sat_vector_imm_op_2902 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2902, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2902; + setArg(call_sew_2903, 0, reinterpret_cast(this)); + setRet(call_sew_2903, 0, ret_val_sew_2903); + setArg(call_sat_vector_imm_op_2902, 0, V); + setArg(call_sat_vector_imm_op_2902, 1, 43); + setArg(call_sat_vector_imm_op_2902, 2, 4); + setArg(call_sat_vector_imm_op_2902, 3, sat_vector_imm_op_2902_arg3); + setArg(call_sat_vector_imm_op_2902, 4, sat_vector_imm_op_2902_arg4); + setArg(call_sat_vector_imm_op_2902, 5, sat_vector_imm_op_2902_arg5); + setArg(call_sat_vector_imm_op_2902, 6, sat_vector_imm_op_2902_arg6); + setArg(call_sat_vector_imm_op_2902, 7, vm); + setArg(call_sat_vector_imm_op_2902, 8, vd); + setArg(call_sat_vector_imm_op_2902, 9, vs2); + setArg(call_sat_vector_imm_op_2902, 10, sat_vector_imm_op_2902_arg10); + setArg(call_sat_vector_imm_op_2902, 11, sat_vector_imm_op_2902_arg11); + setRet(call_sat_vector_imm_op_2902, 0, ret_val_sat_vector_imm_op_2902); } cc.bind(label_merge); } - auto tmp2892 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2892, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2892, 32, false) - , traits::vstart); + auto tmp2904 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2904, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2904, traits::vstart); } cc.bind(label_merge); } @@ -68690,49 +68410,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2893; - x86::Gp ret_val_get_sew_pow_2893 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2893, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2894 = get_reg(cc, 8, false); - mov(cc, tmp2894, 1); + InvokeNode* call_get_sew_pow_2905; + x86::Gp ret_val_get_sew_pow_2905 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2905, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2906 = get_reg(cc, 8, false); + mov(cc, tmp2906, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2894, ret_val_get_sew_pow_2893)), 8, false), ~ 1); - setArg(call_get_sew_pow_2893, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2893, 0, ret_val_get_sew_pow_2893); - InvokeNode* call_get_lmul_pow_2895; - x86::Gp ret_val_get_lmul_pow_2895 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2895, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2895; - setArg(call_get_lmul_pow_2895, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2895, 0, ret_val_get_lmul_pow_2895); + (gen_operation(cc, shl, tmp2906, ret_val_get_sew_pow_2905)), 8, false), ~ 1); + setArg(call_get_sew_pow_2905, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2905, 0, ret_val_get_sew_pow_2905); + InvokeNode* call_get_lmul_pow_2907; + x86::Gp ret_val_get_lmul_pow_2907 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2907, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2907; + setArg(call_get_lmul_pow_2907, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2907, 0, ret_val_get_lmul_pow_2907); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2896; - auto illegal_variable_width_2896_arg2 = SEW_widen; - auto illegal_variable_width_2896_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2896 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2896, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2897; - auto valid_reg_overlap_2897_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2897_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2897 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2897, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2896, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2897))); - setArg(call_illegal_variable_width_2896, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2896, 1, vd); - setArg(call_illegal_variable_width_2896, 2, vm); - setArg(call_illegal_variable_width_2896, 3, illegal_variable_width_2896_arg2); - setArg(call_illegal_variable_width_2896, 4, illegal_variable_width_2896_arg3); - setRet(call_illegal_variable_width_2896, 0, ret_val_illegal_variable_width_2896); - setArg(call_valid_reg_overlap_2897, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2897, 1, vs2); - setArg(call_valid_reg_overlap_2897, 2, vd); - setArg(call_valid_reg_overlap_2897, 3, valid_reg_overlap_2897_arg2); - setArg(call_valid_reg_overlap_2897, 4, valid_reg_overlap_2897_arg3); - setRet(call_valid_reg_overlap_2897, 0, ret_val_valid_reg_overlap_2897); + InvokeNode* call_illegal_variable_width_2908; + auto illegal_variable_width_2908_arg2 = SEW_widen; + auto illegal_variable_width_2908_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2908 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2908, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2909; + auto valid_reg_overlap_2909_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2909_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2909 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2909, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2908, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2909))); + setArg(call_illegal_variable_width_2908, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2908, 1, vd); + setArg(call_illegal_variable_width_2908, 2, vm); + setArg(call_illegal_variable_width_2908, 3, illegal_variable_width_2908_arg2); + setArg(call_illegal_variable_width_2908, 4, illegal_variable_width_2908_arg3); + setRet(call_illegal_variable_width_2908, 0, ret_val_illegal_variable_width_2908); + setArg(call_valid_reg_overlap_2909, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2909, 1, vs2); + setArg(call_valid_reg_overlap_2909, 2, vd); + setArg(call_valid_reg_overlap_2909, 3, valid_reg_overlap_2909_arg2); + setArg(call_valid_reg_overlap_2909, 4, valid_reg_overlap_2909_arg3); + setRet(call_valid_reg_overlap_2909, 0, ret_val_valid_reg_overlap_2909); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68748,44 +68468,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2899; - x86::Gp ret_val_sew_2899 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2899, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_vw_2898; - auto sat_vector_imm_vw_2898_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_vw_2898_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_vw_2898_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_vw_2898_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_vw_2898_arg11 = ret_val_sew_2899; + InvokeNode* call_sew_2911; + x86::Gp ret_val_sew_2911 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2911, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2910; + auto sat_vector_imm_vw_2910_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2910_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2910_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2910_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2910_arg11 = ret_val_sew_2911; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_vw_2898 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_vw_2898, &sat_vector_imm_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_vw_2898, 32, false) - , traits::vxsat); - setArg(call_sew_2899, 0, reinterpret_cast(this)); - setRet(call_sew_2899, 0, ret_val_sew_2899); - setArg(call_sat_vector_imm_vw_2898, 0, V); - setArg(call_sat_vector_imm_vw_2898, 1, 46); - setArg(call_sat_vector_imm_vw_2898, 2, 3); - setArg(call_sat_vector_imm_vw_2898, 3, sat_vector_imm_vw_2898_arg3); - setArg(call_sat_vector_imm_vw_2898, 4, sat_vector_imm_vw_2898_arg4); - setArg(call_sat_vector_imm_vw_2898, 5, sat_vector_imm_vw_2898_arg5); - setArg(call_sat_vector_imm_vw_2898, 6, sat_vector_imm_vw_2898_arg6); - setArg(call_sat_vector_imm_vw_2898, 7, vm); - setArg(call_sat_vector_imm_vw_2898, 8, vd); - setArg(call_sat_vector_imm_vw_2898, 9, vs2); - setArg(call_sat_vector_imm_vw_2898, 10, (int32_t)(uint32_t)simm); - setArg(call_sat_vector_imm_vw_2898, 11, sat_vector_imm_vw_2898_arg11); - setRet(call_sat_vector_imm_vw_2898, 0, ret_val_sat_vector_imm_vw_2898); + x86::Gp ret_val_sat_vector_imm_vw_2910 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2910, &sat_vector_imm_vw, FuncSignature::build()); + auto tmp2912 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_vw_2910, 32, false)); + write_reg_to_mem(jh, tmp2912, traits::vxsat); + setArg(call_sew_2911, 0, reinterpret_cast(this)); + setRet(call_sew_2911, 0, ret_val_sew_2911); + setArg(call_sat_vector_imm_vw_2910, 0, V); + setArg(call_sat_vector_imm_vw_2910, 1, 46); + setArg(call_sat_vector_imm_vw_2910, 2, 3); + setArg(call_sat_vector_imm_vw_2910, 3, sat_vector_imm_vw_2910_arg3); + setArg(call_sat_vector_imm_vw_2910, 4, sat_vector_imm_vw_2910_arg4); + setArg(call_sat_vector_imm_vw_2910, 5, sat_vector_imm_vw_2910_arg5); + setArg(call_sat_vector_imm_vw_2910, 6, sat_vector_imm_vw_2910_arg6); + setArg(call_sat_vector_imm_vw_2910, 7, vm); + setArg(call_sat_vector_imm_vw_2910, 8, vd); + setArg(call_sat_vector_imm_vw_2910, 9, vs2); + setArg(call_sat_vector_imm_vw_2910, 10, (int32_t)(uint32_t)simm); + setArg(call_sat_vector_imm_vw_2910, 11, sat_vector_imm_vw_2910_arg11); + setRet(call_sat_vector_imm_vw_2910, 0, ret_val_sat_vector_imm_vw_2910); } cc.bind(label_merge); } - auto tmp2900 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2900, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2900, 32, false) - , traits::vstart); + auto tmp2913 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2913, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2913, traits::vstart); } cc.bind(label_merge); } @@ -68829,49 +68546,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2901; - x86::Gp ret_val_get_sew_pow_2901 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2901, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2902 = get_reg(cc, 8, false); - mov(cc, tmp2902, 1); + InvokeNode* call_get_sew_pow_2914; + x86::Gp ret_val_get_sew_pow_2914 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2914, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2915 = get_reg(cc, 8, false); + mov(cc, tmp2915, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2902, ret_val_get_sew_pow_2901)), 8, false), ~ 1); - setArg(call_get_sew_pow_2901, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2901, 0, ret_val_get_sew_pow_2901); - InvokeNode* call_get_lmul_pow_2903; - x86::Gp ret_val_get_lmul_pow_2903 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2903, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2903; - setArg(call_get_lmul_pow_2903, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2903, 0, ret_val_get_lmul_pow_2903); + (gen_operation(cc, shl, tmp2915, ret_val_get_sew_pow_2914)), 8, false), ~ 1); + setArg(call_get_sew_pow_2914, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2914, 0, ret_val_get_sew_pow_2914); + InvokeNode* call_get_lmul_pow_2916; + x86::Gp ret_val_get_lmul_pow_2916 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2916, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2916; + setArg(call_get_lmul_pow_2916, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2916, 0, ret_val_get_lmul_pow_2916); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2904; - auto illegal_variable_width_2904_arg2 = SEW_widen; - auto illegal_variable_width_2904_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2904 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2904, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2905; - auto valid_reg_overlap_2905_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2905_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2905 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2905, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2904, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2905))); - setArg(call_illegal_variable_width_2904, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2904, 1, vd); - setArg(call_illegal_variable_width_2904, 2, vm); - setArg(call_illegal_variable_width_2904, 3, illegal_variable_width_2904_arg2); - setArg(call_illegal_variable_width_2904, 4, illegal_variable_width_2904_arg3); - setRet(call_illegal_variable_width_2904, 0, ret_val_illegal_variable_width_2904); - setArg(call_valid_reg_overlap_2905, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2905, 1, vs2); - setArg(call_valid_reg_overlap_2905, 2, vd); - setArg(call_valid_reg_overlap_2905, 3, valid_reg_overlap_2905_arg2); - setArg(call_valid_reg_overlap_2905, 4, valid_reg_overlap_2905_arg3); - setRet(call_valid_reg_overlap_2905, 0, ret_val_valid_reg_overlap_2905); + InvokeNode* call_illegal_variable_width_2917; + auto illegal_variable_width_2917_arg2 = SEW_widen; + auto illegal_variable_width_2917_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2917 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2917, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2918; + auto valid_reg_overlap_2918_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2918_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2918 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2918, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2917, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2918))); + setArg(call_illegal_variable_width_2917, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2917, 1, vd); + setArg(call_illegal_variable_width_2917, 2, vm); + setArg(call_illegal_variable_width_2917, 3, illegal_variable_width_2917_arg2); + setArg(call_illegal_variable_width_2917, 4, illegal_variable_width_2917_arg3); + setRet(call_illegal_variable_width_2917, 0, ret_val_illegal_variable_width_2917); + setArg(call_valid_reg_overlap_2918, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2918, 1, vs2); + setArg(call_valid_reg_overlap_2918, 2, vd); + setArg(call_valid_reg_overlap_2918, 3, valid_reg_overlap_2918_arg2); + setArg(call_valid_reg_overlap_2918, 4, valid_reg_overlap_2918_arg3); + setRet(call_valid_reg_overlap_2918, 0, ret_val_valid_reg_overlap_2918); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68887,44 +68604,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2907; - x86::Gp ret_val_sew_2907 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2907, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_vw_2906; - auto sat_vector_vector_vw_2906_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_vw_2906_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_vw_2906_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_vw_2906_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_vw_2906_arg11 = ret_val_sew_2907; + InvokeNode* call_sew_2920; + x86::Gp ret_val_sew_2920 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2920, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_vw_2919; + auto sat_vector_vector_vw_2919_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_vw_2919_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_vw_2919_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_vw_2919_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_vw_2919_arg11 = ret_val_sew_2920; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_vw_2906 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_vw_2906, &sat_vector_vector_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_vw_2906, 32, false) - , traits::vxsat); - setArg(call_sew_2907, 0, reinterpret_cast(this)); - setRet(call_sew_2907, 0, ret_val_sew_2907); - setArg(call_sat_vector_vector_vw_2906, 0, V); - setArg(call_sat_vector_vector_vw_2906, 1, 46); - setArg(call_sat_vector_vector_vw_2906, 2, 0); - setArg(call_sat_vector_vector_vw_2906, 3, sat_vector_vector_vw_2906_arg3); - setArg(call_sat_vector_vector_vw_2906, 4, sat_vector_vector_vw_2906_arg4); - setArg(call_sat_vector_vector_vw_2906, 5, sat_vector_vector_vw_2906_arg5); - setArg(call_sat_vector_vector_vw_2906, 6, sat_vector_vector_vw_2906_arg6); - setArg(call_sat_vector_vector_vw_2906, 7, vm); - setArg(call_sat_vector_vector_vw_2906, 8, vd); - setArg(call_sat_vector_vector_vw_2906, 9, vs2); - setArg(call_sat_vector_vector_vw_2906, 10, vs1); - setArg(call_sat_vector_vector_vw_2906, 11, sat_vector_vector_vw_2906_arg11); - setRet(call_sat_vector_vector_vw_2906, 0, ret_val_sat_vector_vector_vw_2906); + x86::Gp ret_val_sat_vector_vector_vw_2919 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_vw_2919, &sat_vector_vector_vw, FuncSignature::build()); + auto tmp2921 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_vw_2919, 32, false)); + write_reg_to_mem(jh, tmp2921, traits::vxsat); + setArg(call_sew_2920, 0, reinterpret_cast(this)); + setRet(call_sew_2920, 0, ret_val_sew_2920); + setArg(call_sat_vector_vector_vw_2919, 0, V); + setArg(call_sat_vector_vector_vw_2919, 1, 46); + setArg(call_sat_vector_vector_vw_2919, 2, 0); + setArg(call_sat_vector_vector_vw_2919, 3, sat_vector_vector_vw_2919_arg3); + setArg(call_sat_vector_vector_vw_2919, 4, sat_vector_vector_vw_2919_arg4); + setArg(call_sat_vector_vector_vw_2919, 5, sat_vector_vector_vw_2919_arg5); + setArg(call_sat_vector_vector_vw_2919, 6, sat_vector_vector_vw_2919_arg6); + setArg(call_sat_vector_vector_vw_2919, 7, vm); + setArg(call_sat_vector_vector_vw_2919, 8, vd); + setArg(call_sat_vector_vector_vw_2919, 9, vs2); + setArg(call_sat_vector_vector_vw_2919, 10, vs1); + setArg(call_sat_vector_vector_vw_2919, 11, sat_vector_vector_vw_2919_arg11); + setRet(call_sat_vector_vector_vw_2919, 0, ret_val_sat_vector_vector_vw_2919); } cc.bind(label_merge); } - auto tmp2908 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2908, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2908, 32, false) - , traits::vstart); + auto tmp2922 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2922, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2922, traits::vstart); } cc.bind(label_merge); } @@ -68972,49 +68686,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else { - InvokeNode* call_get_sew_pow_2909; - x86::Gp ret_val_get_sew_pow_2909 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2909, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2910 = get_reg(cc, 8, false); - mov(cc, tmp2910, 1); + InvokeNode* call_get_sew_pow_2923; + x86::Gp ret_val_get_sew_pow_2923 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2923, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2924 = get_reg(cc, 8, false); + mov(cc, tmp2924, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2910, ret_val_get_sew_pow_2909)), 8, false), ~ 1); - setArg(call_get_sew_pow_2909, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2909, 0, ret_val_get_sew_pow_2909); - InvokeNode* call_get_lmul_pow_2911; - x86::Gp ret_val_get_lmul_pow_2911 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2911, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2911; - setArg(call_get_lmul_pow_2911, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2911, 0, ret_val_get_lmul_pow_2911); + (gen_operation(cc, shl, tmp2924, ret_val_get_sew_pow_2923)), 8, false), ~ 1); + setArg(call_get_sew_pow_2923, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2923, 0, ret_val_get_sew_pow_2923); + InvokeNode* call_get_lmul_pow_2925; + x86::Gp ret_val_get_lmul_pow_2925 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2925, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2925; + setArg(call_get_lmul_pow_2925, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2925, 0, ret_val_get_lmul_pow_2925); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2912; - auto illegal_variable_width_2912_arg2 = SEW_widen; - auto illegal_variable_width_2912_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2912 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2912, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2913; - auto valid_reg_overlap_2913_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2913_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2913 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2913, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2912, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2913))); - setArg(call_illegal_variable_width_2912, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2912, 1, vd); - setArg(call_illegal_variable_width_2912, 2, vm); - setArg(call_illegal_variable_width_2912, 3, illegal_variable_width_2912_arg2); - setArg(call_illegal_variable_width_2912, 4, illegal_variable_width_2912_arg3); - setRet(call_illegal_variable_width_2912, 0, ret_val_illegal_variable_width_2912); - setArg(call_valid_reg_overlap_2913, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2913, 1, vs2); - setArg(call_valid_reg_overlap_2913, 2, vd); - setArg(call_valid_reg_overlap_2913, 3, valid_reg_overlap_2913_arg2); - setArg(call_valid_reg_overlap_2913, 4, valid_reg_overlap_2913_arg3); - setRet(call_valid_reg_overlap_2913, 0, ret_val_valid_reg_overlap_2913); + InvokeNode* call_illegal_variable_width_2926; + auto illegal_variable_width_2926_arg2 = SEW_widen; + auto illegal_variable_width_2926_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2926 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2926, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2927; + auto valid_reg_overlap_2927_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2927_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2927 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2927, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2926, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2927))); + setArg(call_illegal_variable_width_2926, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2926, 1, vd); + setArg(call_illegal_variable_width_2926, 2, vm); + setArg(call_illegal_variable_width_2926, 3, illegal_variable_width_2926_arg2); + setArg(call_illegal_variable_width_2926, 4, illegal_variable_width_2926_arg3); + setRet(call_illegal_variable_width_2926, 0, ret_val_illegal_variable_width_2926); + setArg(call_valid_reg_overlap_2927, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2927, 1, vs2); + setArg(call_valid_reg_overlap_2927, 2, vd); + setArg(call_valid_reg_overlap_2927, 3, valid_reg_overlap_2927_arg2); + setArg(call_valid_reg_overlap_2927, 4, valid_reg_overlap_2927_arg3); + setRet(call_valid_reg_overlap_2927, 0, ret_val_valid_reg_overlap_2927); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69030,47 +68744,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2915; - x86::Gp ret_val_sew_2915 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2915, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_vw_2914; - auto sat_vector_imm_vw_2914_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_vw_2914_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_vw_2914_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_vw_2914_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_vw_2914_arg10 = gen_ext(cc, + InvokeNode* call_sew_2929; + x86::Gp ret_val_sew_2929 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2929, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2928; + auto sat_vector_imm_vw_2928_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2928_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2928_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2928_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2928_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); - auto sat_vector_imm_vw_2914_arg11 = ret_val_sew_2915; + auto sat_vector_imm_vw_2928_arg11 = ret_val_sew_2929; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_vw_2914 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_vw_2914, &sat_vector_imm_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_vw_2914, 32, false) - , traits::vxsat); - setArg(call_sew_2915, 0, reinterpret_cast(this)); - setRet(call_sew_2915, 0, ret_val_sew_2915); - setArg(call_sat_vector_imm_vw_2914, 0, V); - setArg(call_sat_vector_imm_vw_2914, 1, 46); - setArg(call_sat_vector_imm_vw_2914, 2, 4); - setArg(call_sat_vector_imm_vw_2914, 3, sat_vector_imm_vw_2914_arg3); - setArg(call_sat_vector_imm_vw_2914, 4, sat_vector_imm_vw_2914_arg4); - setArg(call_sat_vector_imm_vw_2914, 5, sat_vector_imm_vw_2914_arg5); - setArg(call_sat_vector_imm_vw_2914, 6, sat_vector_imm_vw_2914_arg6); - setArg(call_sat_vector_imm_vw_2914, 7, vm); - setArg(call_sat_vector_imm_vw_2914, 8, vd); - setArg(call_sat_vector_imm_vw_2914, 9, vs2); - setArg(call_sat_vector_imm_vw_2914, 10, sat_vector_imm_vw_2914_arg10); - setArg(call_sat_vector_imm_vw_2914, 11, sat_vector_imm_vw_2914_arg11); - setRet(call_sat_vector_imm_vw_2914, 0, ret_val_sat_vector_imm_vw_2914); + x86::Gp ret_val_sat_vector_imm_vw_2928 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2928, &sat_vector_imm_vw, FuncSignature::build()); + auto tmp2930 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_vw_2928, 32, false)); + write_reg_to_mem(jh, tmp2930, traits::vxsat); + setArg(call_sew_2929, 0, reinterpret_cast(this)); + setRet(call_sew_2929, 0, ret_val_sew_2929); + setArg(call_sat_vector_imm_vw_2928, 0, V); + setArg(call_sat_vector_imm_vw_2928, 1, 46); + setArg(call_sat_vector_imm_vw_2928, 2, 4); + setArg(call_sat_vector_imm_vw_2928, 3, sat_vector_imm_vw_2928_arg3); + setArg(call_sat_vector_imm_vw_2928, 4, sat_vector_imm_vw_2928_arg4); + setArg(call_sat_vector_imm_vw_2928, 5, sat_vector_imm_vw_2928_arg5); + setArg(call_sat_vector_imm_vw_2928, 6, sat_vector_imm_vw_2928_arg6); + setArg(call_sat_vector_imm_vw_2928, 7, vm); + setArg(call_sat_vector_imm_vw_2928, 8, vd); + setArg(call_sat_vector_imm_vw_2928, 9, vs2); + setArg(call_sat_vector_imm_vw_2928, 10, sat_vector_imm_vw_2928_arg10); + setArg(call_sat_vector_imm_vw_2928, 11, sat_vector_imm_vw_2928_arg11); + setRet(call_sat_vector_imm_vw_2928, 0, ret_val_sat_vector_imm_vw_2928); } cc.bind(label_merge); } - auto tmp2916 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2916, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2916, 32, false) - , traits::vstart); + auto tmp2931 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2931, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2931, traits::vstart); } cc.bind(label_merge); } @@ -69115,49 +68826,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2917; - x86::Gp ret_val_get_sew_pow_2917 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2917, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2918 = get_reg(cc, 8, false); - mov(cc, tmp2918, 1); + InvokeNode* call_get_sew_pow_2932; + x86::Gp ret_val_get_sew_pow_2932 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2932, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2933 = get_reg(cc, 8, false); + mov(cc, tmp2933, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2918, ret_val_get_sew_pow_2917)), 8, false), ~ 1); - setArg(call_get_sew_pow_2917, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2917, 0, ret_val_get_sew_pow_2917); - InvokeNode* call_get_lmul_pow_2919; - x86::Gp ret_val_get_lmul_pow_2919 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2919, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2919; - setArg(call_get_lmul_pow_2919, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2919, 0, ret_val_get_lmul_pow_2919); + (gen_operation(cc, shl, tmp2933, ret_val_get_sew_pow_2932)), 8, false), ~ 1); + setArg(call_get_sew_pow_2932, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2932, 0, ret_val_get_sew_pow_2932); + InvokeNode* call_get_lmul_pow_2934; + x86::Gp ret_val_get_lmul_pow_2934 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2934, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2934; + setArg(call_get_lmul_pow_2934, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2934, 0, ret_val_get_lmul_pow_2934); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2920; - auto illegal_variable_width_2920_arg2 = SEW_widen; - auto illegal_variable_width_2920_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2920 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2920, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2921; - auto valid_reg_overlap_2921_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2921_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2921 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2921, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2920, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2921))); - setArg(call_illegal_variable_width_2920, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2920, 1, vd); - setArg(call_illegal_variable_width_2920, 2, vm); - setArg(call_illegal_variable_width_2920, 3, illegal_variable_width_2920_arg2); - setArg(call_illegal_variable_width_2920, 4, illegal_variable_width_2920_arg3); - setRet(call_illegal_variable_width_2920, 0, ret_val_illegal_variable_width_2920); - setArg(call_valid_reg_overlap_2921, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2921, 1, vs2); - setArg(call_valid_reg_overlap_2921, 2, vd); - setArg(call_valid_reg_overlap_2921, 3, valid_reg_overlap_2921_arg2); - setArg(call_valid_reg_overlap_2921, 4, valid_reg_overlap_2921_arg3); - setRet(call_valid_reg_overlap_2921, 0, ret_val_valid_reg_overlap_2921); + InvokeNode* call_illegal_variable_width_2935; + auto illegal_variable_width_2935_arg2 = SEW_widen; + auto illegal_variable_width_2935_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2935 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2935, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2936; + auto valid_reg_overlap_2936_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2936_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2936 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2936, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2935, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2936))); + setArg(call_illegal_variable_width_2935, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2935, 1, vd); + setArg(call_illegal_variable_width_2935, 2, vm); + setArg(call_illegal_variable_width_2935, 3, illegal_variable_width_2935_arg2); + setArg(call_illegal_variable_width_2935, 4, illegal_variable_width_2935_arg3); + setRet(call_illegal_variable_width_2935, 0, ret_val_illegal_variable_width_2935); + setArg(call_valid_reg_overlap_2936, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2936, 1, vs2); + setArg(call_valid_reg_overlap_2936, 2, vd); + setArg(call_valid_reg_overlap_2936, 3, valid_reg_overlap_2936_arg2); + setArg(call_valid_reg_overlap_2936, 4, valid_reg_overlap_2936_arg3); + setRet(call_valid_reg_overlap_2936, 0, ret_val_valid_reg_overlap_2936); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69173,44 +68884,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2923; - x86::Gp ret_val_sew_2923 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2923, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_vw_2922; - auto sat_vector_imm_vw_2922_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_vw_2922_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_vw_2922_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_vw_2922_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_vw_2922_arg11 = ret_val_sew_2923; + InvokeNode* call_sew_2938; + x86::Gp ret_val_sew_2938 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2938, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2937; + auto sat_vector_imm_vw_2937_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2937_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2937_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2937_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2937_arg11 = ret_val_sew_2938; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_vw_2922 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_vw_2922, &sat_vector_imm_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_vw_2922, 32, false) - , traits::vxsat); - setArg(call_sew_2923, 0, reinterpret_cast(this)); - setRet(call_sew_2923, 0, ret_val_sew_2923); - setArg(call_sat_vector_imm_vw_2922, 0, V); - setArg(call_sat_vector_imm_vw_2922, 1, 47); - setArg(call_sat_vector_imm_vw_2922, 2, 3); - setArg(call_sat_vector_imm_vw_2922, 3, sat_vector_imm_vw_2922_arg3); - setArg(call_sat_vector_imm_vw_2922, 4, sat_vector_imm_vw_2922_arg4); - setArg(call_sat_vector_imm_vw_2922, 5, sat_vector_imm_vw_2922_arg5); - setArg(call_sat_vector_imm_vw_2922, 6, sat_vector_imm_vw_2922_arg6); - setArg(call_sat_vector_imm_vw_2922, 7, vm); - setArg(call_sat_vector_imm_vw_2922, 8, vd); - setArg(call_sat_vector_imm_vw_2922, 9, vs2); - setArg(call_sat_vector_imm_vw_2922, 10, (int32_t)(uint32_t)simm); - setArg(call_sat_vector_imm_vw_2922, 11, sat_vector_imm_vw_2922_arg11); - setRet(call_sat_vector_imm_vw_2922, 0, ret_val_sat_vector_imm_vw_2922); + x86::Gp ret_val_sat_vector_imm_vw_2937 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2937, &sat_vector_imm_vw, FuncSignature::build()); + auto tmp2939 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_vw_2937, 32, false)); + write_reg_to_mem(jh, tmp2939, traits::vxsat); + setArg(call_sew_2938, 0, reinterpret_cast(this)); + setRet(call_sew_2938, 0, ret_val_sew_2938); + setArg(call_sat_vector_imm_vw_2937, 0, V); + setArg(call_sat_vector_imm_vw_2937, 1, 47); + setArg(call_sat_vector_imm_vw_2937, 2, 3); + setArg(call_sat_vector_imm_vw_2937, 3, sat_vector_imm_vw_2937_arg3); + setArg(call_sat_vector_imm_vw_2937, 4, sat_vector_imm_vw_2937_arg4); + setArg(call_sat_vector_imm_vw_2937, 5, sat_vector_imm_vw_2937_arg5); + setArg(call_sat_vector_imm_vw_2937, 6, sat_vector_imm_vw_2937_arg6); + setArg(call_sat_vector_imm_vw_2937, 7, vm); + setArg(call_sat_vector_imm_vw_2937, 8, vd); + setArg(call_sat_vector_imm_vw_2937, 9, vs2); + setArg(call_sat_vector_imm_vw_2937, 10, (int32_t)(uint32_t)simm); + setArg(call_sat_vector_imm_vw_2937, 11, sat_vector_imm_vw_2937_arg11); + setRet(call_sat_vector_imm_vw_2937, 0, ret_val_sat_vector_imm_vw_2937); } cc.bind(label_merge); } - auto tmp2924 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2924, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2924, 32, false) - , traits::vstart); + auto tmp2940 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2940, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2940, traits::vstart); } cc.bind(label_merge); } @@ -69254,49 +68962,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2925; - x86::Gp ret_val_get_sew_pow_2925 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2925, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2926 = get_reg(cc, 8, false); - mov(cc, tmp2926, 1); + InvokeNode* call_get_sew_pow_2941; + x86::Gp ret_val_get_sew_pow_2941 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2941, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2942 = get_reg(cc, 8, false); + mov(cc, tmp2942, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2926, ret_val_get_sew_pow_2925)), 8, false), ~ 1); - setArg(call_get_sew_pow_2925, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2925, 0, ret_val_get_sew_pow_2925); - InvokeNode* call_get_lmul_pow_2927; - x86::Gp ret_val_get_lmul_pow_2927 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2927, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2927; - setArg(call_get_lmul_pow_2927, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2927, 0, ret_val_get_lmul_pow_2927); + (gen_operation(cc, shl, tmp2942, ret_val_get_sew_pow_2941)), 8, false), ~ 1); + setArg(call_get_sew_pow_2941, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2941, 0, ret_val_get_sew_pow_2941); + InvokeNode* call_get_lmul_pow_2943; + x86::Gp ret_val_get_lmul_pow_2943 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2943, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2943; + setArg(call_get_lmul_pow_2943, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2943, 0, ret_val_get_lmul_pow_2943); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2928; - auto illegal_variable_width_2928_arg2 = SEW_widen; - auto illegal_variable_width_2928_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2928 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2928, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2929; - auto valid_reg_overlap_2929_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2929_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2929 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2929, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2928, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2929))); - setArg(call_illegal_variable_width_2928, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2928, 1, vd); - setArg(call_illegal_variable_width_2928, 2, vm); - setArg(call_illegal_variable_width_2928, 3, illegal_variable_width_2928_arg2); - setArg(call_illegal_variable_width_2928, 4, illegal_variable_width_2928_arg3); - setRet(call_illegal_variable_width_2928, 0, ret_val_illegal_variable_width_2928); - setArg(call_valid_reg_overlap_2929, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2929, 1, vs2); - setArg(call_valid_reg_overlap_2929, 2, vd); - setArg(call_valid_reg_overlap_2929, 3, valid_reg_overlap_2929_arg2); - setArg(call_valid_reg_overlap_2929, 4, valid_reg_overlap_2929_arg3); - setRet(call_valid_reg_overlap_2929, 0, ret_val_valid_reg_overlap_2929); + InvokeNode* call_illegal_variable_width_2944; + auto illegal_variable_width_2944_arg2 = SEW_widen; + auto illegal_variable_width_2944_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2944 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2944, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2945; + auto valid_reg_overlap_2945_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2945_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2945 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2945, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2944, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2945))); + setArg(call_illegal_variable_width_2944, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2944, 1, vd); + setArg(call_illegal_variable_width_2944, 2, vm); + setArg(call_illegal_variable_width_2944, 3, illegal_variable_width_2944_arg2); + setArg(call_illegal_variable_width_2944, 4, illegal_variable_width_2944_arg3); + setRet(call_illegal_variable_width_2944, 0, ret_val_illegal_variable_width_2944); + setArg(call_valid_reg_overlap_2945, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2945, 1, vs2); + setArg(call_valid_reg_overlap_2945, 2, vd); + setArg(call_valid_reg_overlap_2945, 3, valid_reg_overlap_2945_arg2); + setArg(call_valid_reg_overlap_2945, 4, valid_reg_overlap_2945_arg3); + setRet(call_valid_reg_overlap_2945, 0, ret_val_valid_reg_overlap_2945); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69312,44 +69020,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2931; - x86::Gp ret_val_sew_2931 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2931, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_vw_2930; - auto sat_vector_vector_vw_2930_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_vw_2930_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_vw_2930_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_vw_2930_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_vw_2930_arg11 = ret_val_sew_2931; + InvokeNode* call_sew_2947; + x86::Gp ret_val_sew_2947 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2947, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_vw_2946; + auto sat_vector_vector_vw_2946_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_vw_2946_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_vw_2946_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_vw_2946_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_vw_2946_arg11 = ret_val_sew_2947; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_vw_2930 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_vw_2930, &sat_vector_vector_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_vw_2930, 32, false) - , traits::vxsat); - setArg(call_sew_2931, 0, reinterpret_cast(this)); - setRet(call_sew_2931, 0, ret_val_sew_2931); - setArg(call_sat_vector_vector_vw_2930, 0, V); - setArg(call_sat_vector_vector_vw_2930, 1, 47); - setArg(call_sat_vector_vector_vw_2930, 2, 0); - setArg(call_sat_vector_vector_vw_2930, 3, sat_vector_vector_vw_2930_arg3); - setArg(call_sat_vector_vector_vw_2930, 4, sat_vector_vector_vw_2930_arg4); - setArg(call_sat_vector_vector_vw_2930, 5, sat_vector_vector_vw_2930_arg5); - setArg(call_sat_vector_vector_vw_2930, 6, sat_vector_vector_vw_2930_arg6); - setArg(call_sat_vector_vector_vw_2930, 7, vm); - setArg(call_sat_vector_vector_vw_2930, 8, vd); - setArg(call_sat_vector_vector_vw_2930, 9, vs2); - setArg(call_sat_vector_vector_vw_2930, 10, vs1); - setArg(call_sat_vector_vector_vw_2930, 11, sat_vector_vector_vw_2930_arg11); - setRet(call_sat_vector_vector_vw_2930, 0, ret_val_sat_vector_vector_vw_2930); + x86::Gp ret_val_sat_vector_vector_vw_2946 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_vw_2946, &sat_vector_vector_vw, FuncSignature::build()); + auto tmp2948 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_vw_2946, 32, false)); + write_reg_to_mem(jh, tmp2948, traits::vxsat); + setArg(call_sew_2947, 0, reinterpret_cast(this)); + setRet(call_sew_2947, 0, ret_val_sew_2947); + setArg(call_sat_vector_vector_vw_2946, 0, V); + setArg(call_sat_vector_vector_vw_2946, 1, 47); + setArg(call_sat_vector_vector_vw_2946, 2, 0); + setArg(call_sat_vector_vector_vw_2946, 3, sat_vector_vector_vw_2946_arg3); + setArg(call_sat_vector_vector_vw_2946, 4, sat_vector_vector_vw_2946_arg4); + setArg(call_sat_vector_vector_vw_2946, 5, sat_vector_vector_vw_2946_arg5); + setArg(call_sat_vector_vector_vw_2946, 6, sat_vector_vector_vw_2946_arg6); + setArg(call_sat_vector_vector_vw_2946, 7, vm); + setArg(call_sat_vector_vector_vw_2946, 8, vd); + setArg(call_sat_vector_vector_vw_2946, 9, vs2); + setArg(call_sat_vector_vector_vw_2946, 10, vs1); + setArg(call_sat_vector_vector_vw_2946, 11, sat_vector_vector_vw_2946_arg11); + setRet(call_sat_vector_vector_vw_2946, 0, ret_val_sat_vector_vector_vw_2946); } cc.bind(label_merge); } - auto tmp2932 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2932, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2932, 32, false) - , traits::vstart); + auto tmp2949 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2949, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2949, traits::vstart); } cc.bind(label_merge); } @@ -69397,49 +69102,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else { - InvokeNode* call_get_sew_pow_2933; - x86::Gp ret_val_get_sew_pow_2933 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2933, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2934 = get_reg(cc, 8, false); - mov(cc, tmp2934, 1); + InvokeNode* call_get_sew_pow_2950; + x86::Gp ret_val_get_sew_pow_2950 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2950, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2951 = get_reg(cc, 8, false); + mov(cc, tmp2951, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2934, ret_val_get_sew_pow_2933)), 8, false), ~ 1); - setArg(call_get_sew_pow_2933, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2933, 0, ret_val_get_sew_pow_2933); - InvokeNode* call_get_lmul_pow_2935; - x86::Gp ret_val_get_lmul_pow_2935 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2935, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2935; - setArg(call_get_lmul_pow_2935, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2935, 0, ret_val_get_lmul_pow_2935); + (gen_operation(cc, shl, tmp2951, ret_val_get_sew_pow_2950)), 8, false), ~ 1); + setArg(call_get_sew_pow_2950, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2950, 0, ret_val_get_sew_pow_2950); + InvokeNode* call_get_lmul_pow_2952; + x86::Gp ret_val_get_lmul_pow_2952 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2952, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2952; + setArg(call_get_lmul_pow_2952, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2952, 0, ret_val_get_lmul_pow_2952); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2936; - auto illegal_variable_width_2936_arg2 = SEW_widen; - auto illegal_variable_width_2936_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2936 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2936, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2937; - auto valid_reg_overlap_2937_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2937_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2937 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2937, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2936, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2937))); - setArg(call_illegal_variable_width_2936, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2936, 1, vd); - setArg(call_illegal_variable_width_2936, 2, vm); - setArg(call_illegal_variable_width_2936, 3, illegal_variable_width_2936_arg2); - setArg(call_illegal_variable_width_2936, 4, illegal_variable_width_2936_arg3); - setRet(call_illegal_variable_width_2936, 0, ret_val_illegal_variable_width_2936); - setArg(call_valid_reg_overlap_2937, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2937, 1, vs2); - setArg(call_valid_reg_overlap_2937, 2, vd); - setArg(call_valid_reg_overlap_2937, 3, valid_reg_overlap_2937_arg2); - setArg(call_valid_reg_overlap_2937, 4, valid_reg_overlap_2937_arg3); - setRet(call_valid_reg_overlap_2937, 0, ret_val_valid_reg_overlap_2937); + InvokeNode* call_illegal_variable_width_2953; + auto illegal_variable_width_2953_arg2 = SEW_widen; + auto illegal_variable_width_2953_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2953 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2953, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2954; + auto valid_reg_overlap_2954_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2954_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2954 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2954, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2953, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2954))); + setArg(call_illegal_variable_width_2953, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2953, 1, vd); + setArg(call_illegal_variable_width_2953, 2, vm); + setArg(call_illegal_variable_width_2953, 3, illegal_variable_width_2953_arg2); + setArg(call_illegal_variable_width_2953, 4, illegal_variable_width_2953_arg3); + setRet(call_illegal_variable_width_2953, 0, ret_val_illegal_variable_width_2953); + setArg(call_valid_reg_overlap_2954, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2954, 1, vs2); + setArg(call_valid_reg_overlap_2954, 2, vd); + setArg(call_valid_reg_overlap_2954, 3, valid_reg_overlap_2954_arg2); + setArg(call_valid_reg_overlap_2954, 4, valid_reg_overlap_2954_arg3); + setRet(call_valid_reg_overlap_2954, 0, ret_val_valid_reg_overlap_2954); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69455,47 +69160,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2939; - x86::Gp ret_val_sew_2939 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2939, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_vw_2938; - auto sat_vector_imm_vw_2938_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_vw_2938_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_vw_2938_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_vw_2938_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_vw_2938_arg10 = gen_ext(cc, + InvokeNode* call_sew_2956; + x86::Gp ret_val_sew_2956 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2956, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2955; + auto sat_vector_imm_vw_2955_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2955_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2955_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2955_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2955_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, false); - auto sat_vector_imm_vw_2938_arg11 = ret_val_sew_2939; + auto sat_vector_imm_vw_2955_arg11 = ret_val_sew_2956; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_vw_2938 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_vw_2938, &sat_vector_imm_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_vw_2938, 32, false) - , traits::vxsat); - setArg(call_sew_2939, 0, reinterpret_cast(this)); - setRet(call_sew_2939, 0, ret_val_sew_2939); - setArg(call_sat_vector_imm_vw_2938, 0, V); - setArg(call_sat_vector_imm_vw_2938, 1, 47); - setArg(call_sat_vector_imm_vw_2938, 2, 4); - setArg(call_sat_vector_imm_vw_2938, 3, sat_vector_imm_vw_2938_arg3); - setArg(call_sat_vector_imm_vw_2938, 4, sat_vector_imm_vw_2938_arg4); - setArg(call_sat_vector_imm_vw_2938, 5, sat_vector_imm_vw_2938_arg5); - setArg(call_sat_vector_imm_vw_2938, 6, sat_vector_imm_vw_2938_arg6); - setArg(call_sat_vector_imm_vw_2938, 7, vm); - setArg(call_sat_vector_imm_vw_2938, 8, vd); - setArg(call_sat_vector_imm_vw_2938, 9, vs2); - setArg(call_sat_vector_imm_vw_2938, 10, sat_vector_imm_vw_2938_arg10); - setArg(call_sat_vector_imm_vw_2938, 11, sat_vector_imm_vw_2938_arg11); - setRet(call_sat_vector_imm_vw_2938, 0, ret_val_sat_vector_imm_vw_2938); + x86::Gp ret_val_sat_vector_imm_vw_2955 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2955, &sat_vector_imm_vw, FuncSignature::build()); + auto tmp2957 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_vw_2955, 32, false)); + write_reg_to_mem(jh, tmp2957, traits::vxsat); + setArg(call_sew_2956, 0, reinterpret_cast(this)); + setRet(call_sew_2956, 0, ret_val_sew_2956); + setArg(call_sat_vector_imm_vw_2955, 0, V); + setArg(call_sat_vector_imm_vw_2955, 1, 47); + setArg(call_sat_vector_imm_vw_2955, 2, 4); + setArg(call_sat_vector_imm_vw_2955, 3, sat_vector_imm_vw_2955_arg3); + setArg(call_sat_vector_imm_vw_2955, 4, sat_vector_imm_vw_2955_arg4); + setArg(call_sat_vector_imm_vw_2955, 5, sat_vector_imm_vw_2955_arg5); + setArg(call_sat_vector_imm_vw_2955, 6, sat_vector_imm_vw_2955_arg6); + setArg(call_sat_vector_imm_vw_2955, 7, vm); + setArg(call_sat_vector_imm_vw_2955, 8, vd); + setArg(call_sat_vector_imm_vw_2955, 9, vs2); + setArg(call_sat_vector_imm_vw_2955, 10, sat_vector_imm_vw_2955_arg10); + setArg(call_sat_vector_imm_vw_2955, 11, sat_vector_imm_vw_2955_arg11); + setRet(call_sat_vector_imm_vw_2955, 0, ret_val_sat_vector_imm_vw_2955); } cc.bind(label_merge); } - auto tmp2940 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2940, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2940, 32, false) - , traits::vstart); + auto tmp2958 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2958, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2958, traits::vstart); } cc.bind(label_merge); } @@ -69542,12 +69244,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2941; - x86::Gp ret_val_illegal_reduction_2941 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2941, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2941; - setArg(call_illegal_reduction_2941, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2941, 0, ret_val_illegal_reduction_2941); + InvokeNode* call_illegal_reduction_2959; + x86::Gp ret_val_illegal_reduction_2959 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2959, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2959; + setArg(call_illegal_reduction_2959, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2959, 0, ret_val_illegal_reduction_2959); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69563,37 +69265,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2943; - x86::Gp ret_val_sew_2943 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2943, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2942; - auto vector_red_op_2942_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2942_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2942_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2942_arg10 = ret_val_sew_2943; + InvokeNode* call_sew_2961; + x86::Gp ret_val_sew_2961 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2961, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2960; + auto vector_red_op_2960_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2960_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2960_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2960_arg10 = ret_val_sew_2961; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2942, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2943, 0, reinterpret_cast(this)); - setRet(call_sew_2943, 0, ret_val_sew_2943); - setArg(call_vector_red_op_2942, 0, V); - setArg(call_vector_red_op_2942, 1, 0); - setArg(call_vector_red_op_2942, 2, 2); - setArg(call_vector_red_op_2942, 3, vector_red_op_2942_arg3); - setArg(call_vector_red_op_2942, 4, vector_red_op_2942_arg4); - setArg(call_vector_red_op_2942, 5, vector_red_op_2942_arg5); - setArg(call_vector_red_op_2942, 6, vm); - setArg(call_vector_red_op_2942, 7, vd); - setArg(call_vector_red_op_2942, 8, vs2); - setArg(call_vector_red_op_2942, 9, vs1); - setArg(call_vector_red_op_2942, 10, vector_red_op_2942_arg10); + cc.invoke(&call_vector_red_op_2960, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2961, 0, reinterpret_cast(this)); + setRet(call_sew_2961, 0, ret_val_sew_2961); + setArg(call_vector_red_op_2960, 0, V); + setArg(call_vector_red_op_2960, 1, 0); + setArg(call_vector_red_op_2960, 2, 2); + setArg(call_vector_red_op_2960, 3, vector_red_op_2960_arg3); + setArg(call_vector_red_op_2960, 4, vector_red_op_2960_arg4); + setArg(call_vector_red_op_2960, 5, vector_red_op_2960_arg5); + setArg(call_vector_red_op_2960, 6, vm); + setArg(call_vector_red_op_2960, 7, vd); + setArg(call_vector_red_op_2960, 8, vs2); + setArg(call_vector_red_op_2960, 9, vs1); + setArg(call_vector_red_op_2960, 10, vector_red_op_2960_arg10); } cc.bind(label_merge); } - auto tmp2944 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2944, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2944, 32, false) - , traits::vstart); + auto tmp2962 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2962, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2962, traits::vstart); } cc.bind(label_merge); } @@ -69639,12 +69339,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2945; - x86::Gp ret_val_illegal_reduction_2945 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2945, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2945; - setArg(call_illegal_reduction_2945, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2945, 0, ret_val_illegal_reduction_2945); + InvokeNode* call_illegal_reduction_2963; + x86::Gp ret_val_illegal_reduction_2963 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2963, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2963; + setArg(call_illegal_reduction_2963, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2963, 0, ret_val_illegal_reduction_2963); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69660,37 +69360,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2947; - x86::Gp ret_val_sew_2947 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2947, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2946; - auto vector_red_op_2946_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2946_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2946_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2946_arg10 = ret_val_sew_2947; + InvokeNode* call_sew_2965; + x86::Gp ret_val_sew_2965 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2965, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2964; + auto vector_red_op_2964_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2964_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2964_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2964_arg10 = ret_val_sew_2965; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2946, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2947, 0, reinterpret_cast(this)); - setRet(call_sew_2947, 0, ret_val_sew_2947); - setArg(call_vector_red_op_2946, 0, V); - setArg(call_vector_red_op_2946, 1, 6); - setArg(call_vector_red_op_2946, 2, 2); - setArg(call_vector_red_op_2946, 3, vector_red_op_2946_arg3); - setArg(call_vector_red_op_2946, 4, vector_red_op_2946_arg4); - setArg(call_vector_red_op_2946, 5, vector_red_op_2946_arg5); - setArg(call_vector_red_op_2946, 6, vm); - setArg(call_vector_red_op_2946, 7, vd); - setArg(call_vector_red_op_2946, 8, vs2); - setArg(call_vector_red_op_2946, 9, vs1); - setArg(call_vector_red_op_2946, 10, vector_red_op_2946_arg10); + cc.invoke(&call_vector_red_op_2964, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2965, 0, reinterpret_cast(this)); + setRet(call_sew_2965, 0, ret_val_sew_2965); + setArg(call_vector_red_op_2964, 0, V); + setArg(call_vector_red_op_2964, 1, 6); + setArg(call_vector_red_op_2964, 2, 2); + setArg(call_vector_red_op_2964, 3, vector_red_op_2964_arg3); + setArg(call_vector_red_op_2964, 4, vector_red_op_2964_arg4); + setArg(call_vector_red_op_2964, 5, vector_red_op_2964_arg5); + setArg(call_vector_red_op_2964, 6, vm); + setArg(call_vector_red_op_2964, 7, vd); + setArg(call_vector_red_op_2964, 8, vs2); + setArg(call_vector_red_op_2964, 9, vs1); + setArg(call_vector_red_op_2964, 10, vector_red_op_2964_arg10); } cc.bind(label_merge); } - auto tmp2948 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2948, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2948, 32, false) - , traits::vstart); + auto tmp2966 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2966, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2966, traits::vstart); } cc.bind(label_merge); } @@ -69736,12 +69434,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2949; - x86::Gp ret_val_illegal_reduction_2949 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2949, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2949; - setArg(call_illegal_reduction_2949, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2949, 0, ret_val_illegal_reduction_2949); + InvokeNode* call_illegal_reduction_2967; + x86::Gp ret_val_illegal_reduction_2967 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2967, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2967; + setArg(call_illegal_reduction_2967, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2967, 0, ret_val_illegal_reduction_2967); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69757,37 +69455,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2951; - x86::Gp ret_val_sew_2951 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2951, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2950; - auto vector_red_op_2950_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2950_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2950_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2950_arg10 = ret_val_sew_2951; + InvokeNode* call_sew_2969; + x86::Gp ret_val_sew_2969 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2969, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2968; + auto vector_red_op_2968_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2968_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2968_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2968_arg10 = ret_val_sew_2969; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2950, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2951, 0, reinterpret_cast(this)); - setRet(call_sew_2951, 0, ret_val_sew_2951); - setArg(call_vector_red_op_2950, 0, V); - setArg(call_vector_red_op_2950, 1, 7); - setArg(call_vector_red_op_2950, 2, 2); - setArg(call_vector_red_op_2950, 3, vector_red_op_2950_arg3); - setArg(call_vector_red_op_2950, 4, vector_red_op_2950_arg4); - setArg(call_vector_red_op_2950, 5, vector_red_op_2950_arg5); - setArg(call_vector_red_op_2950, 6, vm); - setArg(call_vector_red_op_2950, 7, vd); - setArg(call_vector_red_op_2950, 8, vs2); - setArg(call_vector_red_op_2950, 9, vs1); - setArg(call_vector_red_op_2950, 10, vector_red_op_2950_arg10); + cc.invoke(&call_vector_red_op_2968, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2969, 0, reinterpret_cast(this)); + setRet(call_sew_2969, 0, ret_val_sew_2969); + setArg(call_vector_red_op_2968, 0, V); + setArg(call_vector_red_op_2968, 1, 7); + setArg(call_vector_red_op_2968, 2, 2); + setArg(call_vector_red_op_2968, 3, vector_red_op_2968_arg3); + setArg(call_vector_red_op_2968, 4, vector_red_op_2968_arg4); + setArg(call_vector_red_op_2968, 5, vector_red_op_2968_arg5); + setArg(call_vector_red_op_2968, 6, vm); + setArg(call_vector_red_op_2968, 7, vd); + setArg(call_vector_red_op_2968, 8, vs2); + setArg(call_vector_red_op_2968, 9, vs1); + setArg(call_vector_red_op_2968, 10, vector_red_op_2968_arg10); } cc.bind(label_merge); } - auto tmp2952 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2952, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2952, 32, false) - , traits::vstart); + auto tmp2970 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2970, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2970, traits::vstart); } cc.bind(label_merge); } @@ -69833,12 +69529,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2953; - x86::Gp ret_val_illegal_reduction_2953 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2953, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2953; - setArg(call_illegal_reduction_2953, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2953, 0, ret_val_illegal_reduction_2953); + InvokeNode* call_illegal_reduction_2971; + x86::Gp ret_val_illegal_reduction_2971 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2971, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2971; + setArg(call_illegal_reduction_2971, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2971, 0, ret_val_illegal_reduction_2971); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69854,37 +69550,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2955; - x86::Gp ret_val_sew_2955 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2955, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2954; - auto vector_red_op_2954_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2954_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2954_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2954_arg10 = ret_val_sew_2955; + InvokeNode* call_sew_2973; + x86::Gp ret_val_sew_2973 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2973, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2972; + auto vector_red_op_2972_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2972_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2972_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2972_arg10 = ret_val_sew_2973; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2954, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2955, 0, reinterpret_cast(this)); - setRet(call_sew_2955, 0, ret_val_sew_2955); - setArg(call_vector_red_op_2954, 0, V); - setArg(call_vector_red_op_2954, 1, 4); - setArg(call_vector_red_op_2954, 2, 2); - setArg(call_vector_red_op_2954, 3, vector_red_op_2954_arg3); - setArg(call_vector_red_op_2954, 4, vector_red_op_2954_arg4); - setArg(call_vector_red_op_2954, 5, vector_red_op_2954_arg5); - setArg(call_vector_red_op_2954, 6, vm); - setArg(call_vector_red_op_2954, 7, vd); - setArg(call_vector_red_op_2954, 8, vs2); - setArg(call_vector_red_op_2954, 9, vs1); - setArg(call_vector_red_op_2954, 10, vector_red_op_2954_arg10); + cc.invoke(&call_vector_red_op_2972, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2973, 0, reinterpret_cast(this)); + setRet(call_sew_2973, 0, ret_val_sew_2973); + setArg(call_vector_red_op_2972, 0, V); + setArg(call_vector_red_op_2972, 1, 4); + setArg(call_vector_red_op_2972, 2, 2); + setArg(call_vector_red_op_2972, 3, vector_red_op_2972_arg3); + setArg(call_vector_red_op_2972, 4, vector_red_op_2972_arg4); + setArg(call_vector_red_op_2972, 5, vector_red_op_2972_arg5); + setArg(call_vector_red_op_2972, 6, vm); + setArg(call_vector_red_op_2972, 7, vd); + setArg(call_vector_red_op_2972, 8, vs2); + setArg(call_vector_red_op_2972, 9, vs1); + setArg(call_vector_red_op_2972, 10, vector_red_op_2972_arg10); } cc.bind(label_merge); } - auto tmp2956 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2956, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2956, 32, false) - , traits::vstart); + auto tmp2974 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2974, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2974, traits::vstart); } cc.bind(label_merge); } @@ -69930,12 +69624,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2957; - x86::Gp ret_val_illegal_reduction_2957 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2957, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2957; - setArg(call_illegal_reduction_2957, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2957, 0, ret_val_illegal_reduction_2957); + InvokeNode* call_illegal_reduction_2975; + x86::Gp ret_val_illegal_reduction_2975 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2975, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2975; + setArg(call_illegal_reduction_2975, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2975, 0, ret_val_illegal_reduction_2975); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69951,37 +69645,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2959; - x86::Gp ret_val_sew_2959 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2959, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2958; - auto vector_red_op_2958_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2958_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2958_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2958_arg10 = ret_val_sew_2959; + InvokeNode* call_sew_2977; + x86::Gp ret_val_sew_2977 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2977, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2976; + auto vector_red_op_2976_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2976_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2976_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2976_arg10 = ret_val_sew_2977; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2958, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2959, 0, reinterpret_cast(this)); - setRet(call_sew_2959, 0, ret_val_sew_2959); - setArg(call_vector_red_op_2958, 0, V); - setArg(call_vector_red_op_2958, 1, 5); - setArg(call_vector_red_op_2958, 2, 2); - setArg(call_vector_red_op_2958, 3, vector_red_op_2958_arg3); - setArg(call_vector_red_op_2958, 4, vector_red_op_2958_arg4); - setArg(call_vector_red_op_2958, 5, vector_red_op_2958_arg5); - setArg(call_vector_red_op_2958, 6, vm); - setArg(call_vector_red_op_2958, 7, vd); - setArg(call_vector_red_op_2958, 8, vs2); - setArg(call_vector_red_op_2958, 9, vs1); - setArg(call_vector_red_op_2958, 10, vector_red_op_2958_arg10); + cc.invoke(&call_vector_red_op_2976, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2977, 0, reinterpret_cast(this)); + setRet(call_sew_2977, 0, ret_val_sew_2977); + setArg(call_vector_red_op_2976, 0, V); + setArg(call_vector_red_op_2976, 1, 5); + setArg(call_vector_red_op_2976, 2, 2); + setArg(call_vector_red_op_2976, 3, vector_red_op_2976_arg3); + setArg(call_vector_red_op_2976, 4, vector_red_op_2976_arg4); + setArg(call_vector_red_op_2976, 5, vector_red_op_2976_arg5); + setArg(call_vector_red_op_2976, 6, vm); + setArg(call_vector_red_op_2976, 7, vd); + setArg(call_vector_red_op_2976, 8, vs2); + setArg(call_vector_red_op_2976, 9, vs1); + setArg(call_vector_red_op_2976, 10, vector_red_op_2976_arg10); } cc.bind(label_merge); } - auto tmp2960 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2960, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2960, 32, false) - , traits::vstart); + auto tmp2978 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2978, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2978, traits::vstart); } cc.bind(label_merge); } @@ -70027,12 +69719,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2961; - x86::Gp ret_val_illegal_reduction_2961 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2961, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2961; - setArg(call_illegal_reduction_2961, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2961, 0, ret_val_illegal_reduction_2961); + InvokeNode* call_illegal_reduction_2979; + x86::Gp ret_val_illegal_reduction_2979 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2979, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2979; + setArg(call_illegal_reduction_2979, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2979, 0, ret_val_illegal_reduction_2979); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70048,37 +69740,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2963; - x86::Gp ret_val_sew_2963 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2963, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2962; - auto vector_red_op_2962_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2962_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2962_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2962_arg10 = ret_val_sew_2963; + InvokeNode* call_sew_2981; + x86::Gp ret_val_sew_2981 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2981, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2980; + auto vector_red_op_2980_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2980_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2980_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2980_arg10 = ret_val_sew_2981; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2962, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2963, 0, reinterpret_cast(this)); - setRet(call_sew_2963, 0, ret_val_sew_2963); - setArg(call_vector_red_op_2962, 0, V); - setArg(call_vector_red_op_2962, 1, 1); - setArg(call_vector_red_op_2962, 2, 2); - setArg(call_vector_red_op_2962, 3, vector_red_op_2962_arg3); - setArg(call_vector_red_op_2962, 4, vector_red_op_2962_arg4); - setArg(call_vector_red_op_2962, 5, vector_red_op_2962_arg5); - setArg(call_vector_red_op_2962, 6, vm); - setArg(call_vector_red_op_2962, 7, vd); - setArg(call_vector_red_op_2962, 8, vs2); - setArg(call_vector_red_op_2962, 9, vs1); - setArg(call_vector_red_op_2962, 10, vector_red_op_2962_arg10); + cc.invoke(&call_vector_red_op_2980, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2981, 0, reinterpret_cast(this)); + setRet(call_sew_2981, 0, ret_val_sew_2981); + setArg(call_vector_red_op_2980, 0, V); + setArg(call_vector_red_op_2980, 1, 1); + setArg(call_vector_red_op_2980, 2, 2); + setArg(call_vector_red_op_2980, 3, vector_red_op_2980_arg3); + setArg(call_vector_red_op_2980, 4, vector_red_op_2980_arg4); + setArg(call_vector_red_op_2980, 5, vector_red_op_2980_arg5); + setArg(call_vector_red_op_2980, 6, vm); + setArg(call_vector_red_op_2980, 7, vd); + setArg(call_vector_red_op_2980, 8, vs2); + setArg(call_vector_red_op_2980, 9, vs1); + setArg(call_vector_red_op_2980, 10, vector_red_op_2980_arg10); } cc.bind(label_merge); } - auto tmp2964 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2964, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2964, 32, false) - , traits::vstart); + auto tmp2982 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2982, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2982, traits::vstart); } cc.bind(label_merge); } @@ -70124,12 +69814,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2965; - x86::Gp ret_val_illegal_reduction_2965 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2965, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2965; - setArg(call_illegal_reduction_2965, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2965, 0, ret_val_illegal_reduction_2965); + InvokeNode* call_illegal_reduction_2983; + x86::Gp ret_val_illegal_reduction_2983 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2983, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2983; + setArg(call_illegal_reduction_2983, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2983, 0, ret_val_illegal_reduction_2983); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70145,37 +69835,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2967; - x86::Gp ret_val_sew_2967 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2967, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2966; - auto vector_red_op_2966_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2966_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2966_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2966_arg10 = ret_val_sew_2967; + InvokeNode* call_sew_2985; + x86::Gp ret_val_sew_2985 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2985, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2984; + auto vector_red_op_2984_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2984_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2984_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2984_arg10 = ret_val_sew_2985; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2966, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2967, 0, reinterpret_cast(this)); - setRet(call_sew_2967, 0, ret_val_sew_2967); - setArg(call_vector_red_op_2966, 0, V); - setArg(call_vector_red_op_2966, 1, 2); - setArg(call_vector_red_op_2966, 2, 2); - setArg(call_vector_red_op_2966, 3, vector_red_op_2966_arg3); - setArg(call_vector_red_op_2966, 4, vector_red_op_2966_arg4); - setArg(call_vector_red_op_2966, 5, vector_red_op_2966_arg5); - setArg(call_vector_red_op_2966, 6, vm); - setArg(call_vector_red_op_2966, 7, vd); - setArg(call_vector_red_op_2966, 8, vs2); - setArg(call_vector_red_op_2966, 9, vs1); - setArg(call_vector_red_op_2966, 10, vector_red_op_2966_arg10); + cc.invoke(&call_vector_red_op_2984, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2985, 0, reinterpret_cast(this)); + setRet(call_sew_2985, 0, ret_val_sew_2985); + setArg(call_vector_red_op_2984, 0, V); + setArg(call_vector_red_op_2984, 1, 2); + setArg(call_vector_red_op_2984, 2, 2); + setArg(call_vector_red_op_2984, 3, vector_red_op_2984_arg3); + setArg(call_vector_red_op_2984, 4, vector_red_op_2984_arg4); + setArg(call_vector_red_op_2984, 5, vector_red_op_2984_arg5); + setArg(call_vector_red_op_2984, 6, vm); + setArg(call_vector_red_op_2984, 7, vd); + setArg(call_vector_red_op_2984, 8, vs2); + setArg(call_vector_red_op_2984, 9, vs1); + setArg(call_vector_red_op_2984, 10, vector_red_op_2984_arg10); } cc.bind(label_merge); } - auto tmp2968 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2968, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2968, 32, false) - , traits::vstart); + auto tmp2986 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2986, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2986, traits::vstart); } cc.bind(label_merge); } @@ -70221,12 +69909,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2969; - x86::Gp ret_val_illegal_reduction_2969 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2969, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2969; - setArg(call_illegal_reduction_2969, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2969, 0, ret_val_illegal_reduction_2969); + InvokeNode* call_illegal_reduction_2987; + x86::Gp ret_val_illegal_reduction_2987 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2987, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2987; + setArg(call_illegal_reduction_2987, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2987, 0, ret_val_illegal_reduction_2987); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70242,37 +69930,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2971; - x86::Gp ret_val_sew_2971 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2971, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2970; - auto vector_red_op_2970_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2970_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2970_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2970_arg10 = ret_val_sew_2971; + InvokeNode* call_sew_2989; + x86::Gp ret_val_sew_2989 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2989, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2988; + auto vector_red_op_2988_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2988_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2988_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2988_arg10 = ret_val_sew_2989; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2970, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2971, 0, reinterpret_cast(this)); - setRet(call_sew_2971, 0, ret_val_sew_2971); - setArg(call_vector_red_op_2970, 0, V); - setArg(call_vector_red_op_2970, 1, 3); - setArg(call_vector_red_op_2970, 2, 2); - setArg(call_vector_red_op_2970, 3, vector_red_op_2970_arg3); - setArg(call_vector_red_op_2970, 4, vector_red_op_2970_arg4); - setArg(call_vector_red_op_2970, 5, vector_red_op_2970_arg5); - setArg(call_vector_red_op_2970, 6, vm); - setArg(call_vector_red_op_2970, 7, vd); - setArg(call_vector_red_op_2970, 8, vs2); - setArg(call_vector_red_op_2970, 9, vs1); - setArg(call_vector_red_op_2970, 10, vector_red_op_2970_arg10); + cc.invoke(&call_vector_red_op_2988, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2989, 0, reinterpret_cast(this)); + setRet(call_sew_2989, 0, ret_val_sew_2989); + setArg(call_vector_red_op_2988, 0, V); + setArg(call_vector_red_op_2988, 1, 3); + setArg(call_vector_red_op_2988, 2, 2); + setArg(call_vector_red_op_2988, 3, vector_red_op_2988_arg3); + setArg(call_vector_red_op_2988, 4, vector_red_op_2988_arg4); + setArg(call_vector_red_op_2988, 5, vector_red_op_2988_arg5); + setArg(call_vector_red_op_2988, 6, vm); + setArg(call_vector_red_op_2988, 7, vd); + setArg(call_vector_red_op_2988, 8, vs2); + setArg(call_vector_red_op_2988, 9, vs1); + setArg(call_vector_red_op_2988, 10, vector_red_op_2988_arg10); } cc.bind(label_merge); } - auto tmp2972 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2972, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2972, 32, false) - , traits::vstart); + auto tmp2990 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2990, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2990, traits::vstart); } cc.bind(label_merge); } @@ -70316,36 +70002,27 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2973; - x86::Gp ret_val_get_sew_pow_2973 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2973, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2974 = get_reg(cc, 8, false); - mov(cc, tmp2974, 1); + InvokeNode* call_get_sew_pow_2991; + x86::Gp ret_val_get_sew_pow_2991 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2991, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2992 = get_reg(cc, 8, false); + mov(cc, tmp2992, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2974, ret_val_get_sew_pow_2973)), 8, false), ~ 1); - setArg(call_get_sew_pow_2973, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2973, 0, ret_val_get_sew_pow_2973); - InvokeNode* call_get_lmul_pow_2975; - x86::Gp ret_val_get_lmul_pow_2975 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2975, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2975; - setArg(call_get_lmul_pow_2975, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2975, 0, ret_val_get_lmul_pow_2975); + (gen_operation(cc, shl, tmp2992, ret_val_get_sew_pow_2991)), 8, false), ~ 1); + setArg(call_get_sew_pow_2991, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2991, 0, ret_val_get_sew_pow_2991); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); - auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_widen_2976; - auto illegal_reduction_widen_2976_arg0 = SEW_widen; - auto illegal_reduction_widen_2976_arg1 = LMUL_pow_widen; - x86::Gp ret_val_illegal_reduction_widen_2976 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_widen_2976, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_widen_2976; - setArg(call_illegal_reduction_widen_2976, 0, reinterpret_cast(this)); - setArg(call_illegal_reduction_widen_2976, 1, illegal_reduction_widen_2976_arg0); - setArg(call_illegal_reduction_widen_2976, 2, illegal_reduction_widen_2976_arg1); - setRet(call_illegal_reduction_widen_2976, 0, ret_val_illegal_reduction_widen_2976); + InvokeNode* call_illegal_reduction_widen_2993; + auto illegal_reduction_widen_2993_arg0 = SEW_widen; + x86::Gp ret_val_illegal_reduction_widen_2993 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_widen_2993, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_widen_2993; + setArg(call_illegal_reduction_widen_2993, 0, reinterpret_cast(this)); + setArg(call_illegal_reduction_widen_2993, 1, illegal_reduction_widen_2993_arg0); + setRet(call_illegal_reduction_widen_2993, 0, ret_val_illegal_reduction_widen_2993); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70361,37 +70038,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2978; - x86::Gp ret_val_sew_2978 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2978, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_wv_2977; - auto vector_red_wv_2977_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_wv_2977_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_wv_2977_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_wv_2977_arg10 = ret_val_sew_2978; + InvokeNode* call_sew_2995; + x86::Gp ret_val_sew_2995 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2995, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_wv_2994; + auto vector_red_wv_2994_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_wv_2994_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_wv_2994_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_wv_2994_arg10 = ret_val_sew_2995; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_wv_2977, &vector_red_wv, FuncSignature::build()); - setArg(call_sew_2978, 0, reinterpret_cast(this)); - setRet(call_sew_2978, 0, ret_val_sew_2978); - setArg(call_vector_red_wv_2977, 0, V); - setArg(call_vector_red_wv_2977, 1, 48); - setArg(call_vector_red_wv_2977, 2, 0); - setArg(call_vector_red_wv_2977, 3, vector_red_wv_2977_arg3); - setArg(call_vector_red_wv_2977, 4, vector_red_wv_2977_arg4); - setArg(call_vector_red_wv_2977, 5, vector_red_wv_2977_arg5); - setArg(call_vector_red_wv_2977, 6, vm); - setArg(call_vector_red_wv_2977, 7, vd); - setArg(call_vector_red_wv_2977, 8, vs2); - setArg(call_vector_red_wv_2977, 9, vs1); - setArg(call_vector_red_wv_2977, 10, vector_red_wv_2977_arg10); + cc.invoke(&call_vector_red_wv_2994, &vector_red_wv, FuncSignature::build()); + setArg(call_sew_2995, 0, reinterpret_cast(this)); + setRet(call_sew_2995, 0, ret_val_sew_2995); + setArg(call_vector_red_wv_2994, 0, V); + setArg(call_vector_red_wv_2994, 1, 48); + setArg(call_vector_red_wv_2994, 2, 0); + setArg(call_vector_red_wv_2994, 3, vector_red_wv_2994_arg3); + setArg(call_vector_red_wv_2994, 4, vector_red_wv_2994_arg4); + setArg(call_vector_red_wv_2994, 5, vector_red_wv_2994_arg5); + setArg(call_vector_red_wv_2994, 6, vm); + setArg(call_vector_red_wv_2994, 7, vd); + setArg(call_vector_red_wv_2994, 8, vs2); + setArg(call_vector_red_wv_2994, 9, vs1); + setArg(call_vector_red_wv_2994, 10, vector_red_wv_2994_arg10); } cc.bind(label_merge); } - auto tmp2979 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2979, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2979, 32, false) - , traits::vstart); + auto tmp2996 = get_reg_Gp(cc, 32, false); + mov(cc, tmp2996, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp2996, traits::vstart); } cc.bind(label_merge); } @@ -70435,36 +70110,27 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2980; - x86::Gp ret_val_get_sew_pow_2980 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2980, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2981 = get_reg(cc, 8, false); - mov(cc, tmp2981, 1); + InvokeNode* call_get_sew_pow_2997; + x86::Gp ret_val_get_sew_pow_2997 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2997, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2998 = get_reg(cc, 8, false); + mov(cc, tmp2998, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2981, ret_val_get_sew_pow_2980)), 8, false), ~ 1); - setArg(call_get_sew_pow_2980, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2980, 0, ret_val_get_sew_pow_2980); - InvokeNode* call_get_lmul_pow_2982; - x86::Gp ret_val_get_lmul_pow_2982 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2982, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2982; - setArg(call_get_lmul_pow_2982, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2982, 0, ret_val_get_lmul_pow_2982); + (gen_operation(cc, shl, tmp2998, ret_val_get_sew_pow_2997)), 8, false), ~ 1); + setArg(call_get_sew_pow_2997, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2997, 0, ret_val_get_sew_pow_2997); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); - auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_widen_2983; - auto illegal_reduction_widen_2983_arg0 = SEW_widen; - auto illegal_reduction_widen_2983_arg1 = LMUL_pow_widen; - x86::Gp ret_val_illegal_reduction_widen_2983 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_widen_2983, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_widen_2983; - setArg(call_illegal_reduction_widen_2983, 0, reinterpret_cast(this)); - setArg(call_illegal_reduction_widen_2983, 1, illegal_reduction_widen_2983_arg0); - setArg(call_illegal_reduction_widen_2983, 2, illegal_reduction_widen_2983_arg1); - setRet(call_illegal_reduction_widen_2983, 0, ret_val_illegal_reduction_widen_2983); + InvokeNode* call_illegal_reduction_widen_2999; + auto illegal_reduction_widen_2999_arg0 = SEW_widen; + x86::Gp ret_val_illegal_reduction_widen_2999 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_widen_2999, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_widen_2999; + setArg(call_illegal_reduction_widen_2999, 0, reinterpret_cast(this)); + setArg(call_illegal_reduction_widen_2999, 1, illegal_reduction_widen_2999_arg0); + setRet(call_illegal_reduction_widen_2999, 0, ret_val_illegal_reduction_widen_2999); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70480,37 +70146,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2985; - x86::Gp ret_val_sew_2985 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2985, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_wv_2984; - auto vector_red_wv_2984_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_wv_2984_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_wv_2984_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_wv_2984_arg10 = ret_val_sew_2985; + InvokeNode* call_sew_3001; + x86::Gp ret_val_sew_3001 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3001, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_wv_3000; + auto vector_red_wv_3000_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_wv_3000_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_wv_3000_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_wv_3000_arg10 = ret_val_sew_3001; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_wv_2984, &vector_red_wv, FuncSignature::build()); - setArg(call_sew_2985, 0, reinterpret_cast(this)); - setRet(call_sew_2985, 0, ret_val_sew_2985); - setArg(call_vector_red_wv_2984, 0, V); - setArg(call_vector_red_wv_2984, 1, 49); - setArg(call_vector_red_wv_2984, 2, 0); - setArg(call_vector_red_wv_2984, 3, vector_red_wv_2984_arg3); - setArg(call_vector_red_wv_2984, 4, vector_red_wv_2984_arg4); - setArg(call_vector_red_wv_2984, 5, vector_red_wv_2984_arg5); - setArg(call_vector_red_wv_2984, 6, vm); - setArg(call_vector_red_wv_2984, 7, vd); - setArg(call_vector_red_wv_2984, 8, vs2); - setArg(call_vector_red_wv_2984, 9, vs1); - setArg(call_vector_red_wv_2984, 10, vector_red_wv_2984_arg10); + cc.invoke(&call_vector_red_wv_3000, &vector_red_wv, FuncSignature::build()); + setArg(call_sew_3001, 0, reinterpret_cast(this)); + setRet(call_sew_3001, 0, ret_val_sew_3001); + setArg(call_vector_red_wv_3000, 0, V); + setArg(call_vector_red_wv_3000, 1, 49); + setArg(call_vector_red_wv_3000, 2, 0); + setArg(call_vector_red_wv_3000, 3, vector_red_wv_3000_arg3); + setArg(call_vector_red_wv_3000, 4, vector_red_wv_3000_arg4); + setArg(call_vector_red_wv_3000, 5, vector_red_wv_3000_arg5); + setArg(call_vector_red_wv_3000, 6, vm); + setArg(call_vector_red_wv_3000, 7, vd); + setArg(call_vector_red_wv_3000, 8, vs2); + setArg(call_vector_red_wv_3000, 9, vs1); + setArg(call_vector_red_wv_3000, 10, vector_red_wv_3000_arg10); } cc.bind(label_merge); } - auto tmp2986 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2986, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2986, 32, false) - , traits::vstart); + auto tmp3002 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3002, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3002, traits::vstart); } cc.bind(label_merge); } @@ -70554,28 +70218,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2987; - x86::Gp ret_val_get_sew_pow_2987 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2987, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2988 = get_reg(cc, 8, false); - mov(cc, tmp2988, 1); + InvokeNode* call_get_sew_pow_3003; + x86::Gp ret_val_get_sew_pow_3003 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3003, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3004 = get_reg(cc, 8, false); + mov(cc, tmp3004, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2988, (ret_val_get_sew_pow_2987))), 8, false), ~ 1); - setArg(call_get_sew_pow_2987, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2987, 0, ret_val_get_sew_pow_2987); + (gen_operation(cc, shl, tmp3004, (ret_val_get_sew_pow_3003))), 8, false), ~ 1); + setArg(call_get_sew_pow_3003, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3003, 0, ret_val_get_sew_pow_3003); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_2989; - auto illegal_fp_reduction_2989_arg0 = SEW; - auto illegal_fp_reduction_2989_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_2989 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_2989, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_2989; - setArg(call_illegal_fp_reduction_2989, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_2989, 1, illegal_fp_reduction_2989_arg0); - setArg(call_illegal_fp_reduction_2989, 2, illegal_fp_reduction_2989_arg1); - setRet(call_illegal_fp_reduction_2989, 0, ret_val_illegal_fp_reduction_2989); + InvokeNode* call_illegal_fp_reduction_3005; + auto illegal_fp_reduction_3005_arg0 = SEW; + auto illegal_fp_reduction_3005_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3005 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3005, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3005; + setArg(call_illegal_fp_reduction_3005, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3005, 1, illegal_fp_reduction_3005_arg0); + setArg(call_illegal_fp_reduction_3005, 2, illegal_fp_reduction_3005_arg1); + setRet(call_illegal_fp_reduction_3005, 0, ret_val_illegal_fp_reduction_3005); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70591,45 +70255,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2991; - x86::Gp ret_val_sew_2991 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2991, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_op_2990; - auto fp_vector_red_op_2990_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_op_2990_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_op_2990_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_op_2990_arg10 = rm; - auto fp_vector_red_op_2990_arg11 = ret_val_sew_2991; + InvokeNode* call_sew_3007; + x86::Gp ret_val_sew_3007 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3007, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3006; + auto fp_vector_red_op_3006_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3006_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3006_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3006_arg10 = rm; + auto fp_vector_red_op_3006_arg11 = ret_val_sew_3007; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_op_2990, &fp_vector_red_op, FuncSignature::build()); - setArg(call_sew_2991, 0, reinterpret_cast(this)); - setRet(call_sew_2991, 0, ret_val_sew_2991); - setArg(call_fp_vector_red_op_2990, 0, V); - setArg(call_fp_vector_red_op_2990, 1, 3); - setArg(call_fp_vector_red_op_2990, 2, 1); - setArg(call_fp_vector_red_op_2990, 3, fp_vector_red_op_2990_arg3); - setArg(call_fp_vector_red_op_2990, 4, fp_vector_red_op_2990_arg4); - setArg(call_fp_vector_red_op_2990, 5, fp_vector_red_op_2990_arg5); - setArg(call_fp_vector_red_op_2990, 6, vm); - setArg(call_fp_vector_red_op_2990, 7, vd); - setArg(call_fp_vector_red_op_2990, 8, vs2); - setArg(call_fp_vector_red_op_2990, 9, vs1); - setArg(call_fp_vector_red_op_2990, 10, fp_vector_red_op_2990_arg10); - setArg(call_fp_vector_red_op_2990, 11, fp_vector_red_op_2990_arg11); - InvokeNode* call_fget_flags_2992; - x86::Gp ret_val_fget_flags_2992 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_2992, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_2992; - setRet(call_fget_flags_2992, 0, ret_val_fget_flags_2992); + cc.invoke(&call_fp_vector_red_op_3006, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3007, 0, reinterpret_cast(this)); + setRet(call_sew_3007, 0, ret_val_sew_3007); + setArg(call_fp_vector_red_op_3006, 0, V); + setArg(call_fp_vector_red_op_3006, 1, 3); + setArg(call_fp_vector_red_op_3006, 2, 1); + setArg(call_fp_vector_red_op_3006, 3, fp_vector_red_op_3006_arg3); + setArg(call_fp_vector_red_op_3006, 4, fp_vector_red_op_3006_arg4); + setArg(call_fp_vector_red_op_3006, 5, fp_vector_red_op_3006_arg5); + setArg(call_fp_vector_red_op_3006, 6, vm); + setArg(call_fp_vector_red_op_3006, 7, vd); + setArg(call_fp_vector_red_op_3006, 8, vs2); + setArg(call_fp_vector_red_op_3006, 9, vs1); + setArg(call_fp_vector_red_op_3006, 10, fp_vector_red_op_3006_arg10); + setArg(call_fp_vector_red_op_3006, 11, fp_vector_red_op_3006_arg11); + InvokeNode* call_fget_flags_3008; + x86::Gp ret_val_fget_flags_3008 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3008, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3008; + setRet(call_fget_flags_3008, 0, ret_val_fget_flags_3008); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp2993 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2993, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2993, 32, false) - , traits::vstart); + auto tmp3009 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3009, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3009, traits::vstart); } cc.bind(label_merge); } @@ -70673,28 +70335,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2994; - x86::Gp ret_val_get_sew_pow_2994 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2994, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2995 = get_reg(cc, 8, false); - mov(cc, tmp2995, 1); + InvokeNode* call_get_sew_pow_3010; + x86::Gp ret_val_get_sew_pow_3010 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3010, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3011 = get_reg(cc, 8, false); + mov(cc, tmp3011, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2995, (ret_val_get_sew_pow_2994))), 8, false), ~ 1); - setArg(call_get_sew_pow_2994, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2994, 0, ret_val_get_sew_pow_2994); + (gen_operation(cc, shl, tmp3011, (ret_val_get_sew_pow_3010))), 8, false), ~ 1); + setArg(call_get_sew_pow_3010, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3010, 0, ret_val_get_sew_pow_3010); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_2996; - auto illegal_fp_reduction_2996_arg0 = SEW; - auto illegal_fp_reduction_2996_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_2996 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_2996, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_2996; - setArg(call_illegal_fp_reduction_2996, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_2996, 1, illegal_fp_reduction_2996_arg0); - setArg(call_illegal_fp_reduction_2996, 2, illegal_fp_reduction_2996_arg1); - setRet(call_illegal_fp_reduction_2996, 0, ret_val_illegal_fp_reduction_2996); + InvokeNode* call_illegal_fp_reduction_3012; + auto illegal_fp_reduction_3012_arg0 = SEW; + auto illegal_fp_reduction_3012_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3012 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3012, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3012; + setArg(call_illegal_fp_reduction_3012, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3012, 1, illegal_fp_reduction_3012_arg0); + setArg(call_illegal_fp_reduction_3012, 2, illegal_fp_reduction_3012_arg1); + setRet(call_illegal_fp_reduction_3012, 0, ret_val_illegal_fp_reduction_3012); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70710,45 +70372,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2998; - x86::Gp ret_val_sew_2998 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2998, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_op_2997; - auto fp_vector_red_op_2997_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_op_2997_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_op_2997_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_op_2997_arg10 = rm; - auto fp_vector_red_op_2997_arg11 = ret_val_sew_2998; + InvokeNode* call_sew_3014; + x86::Gp ret_val_sew_3014 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3014, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3013; + auto fp_vector_red_op_3013_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3013_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3013_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3013_arg10 = rm; + auto fp_vector_red_op_3013_arg11 = ret_val_sew_3014; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_op_2997, &fp_vector_red_op, FuncSignature::build()); - setArg(call_sew_2998, 0, reinterpret_cast(this)); - setRet(call_sew_2998, 0, ret_val_sew_2998); - setArg(call_fp_vector_red_op_2997, 0, V); - setArg(call_fp_vector_red_op_2997, 1, 1); - setArg(call_fp_vector_red_op_2997, 2, 1); - setArg(call_fp_vector_red_op_2997, 3, fp_vector_red_op_2997_arg3); - setArg(call_fp_vector_red_op_2997, 4, fp_vector_red_op_2997_arg4); - setArg(call_fp_vector_red_op_2997, 5, fp_vector_red_op_2997_arg5); - setArg(call_fp_vector_red_op_2997, 6, vm); - setArg(call_fp_vector_red_op_2997, 7, vd); - setArg(call_fp_vector_red_op_2997, 8, vs2); - setArg(call_fp_vector_red_op_2997, 9, vs1); - setArg(call_fp_vector_red_op_2997, 10, fp_vector_red_op_2997_arg10); - setArg(call_fp_vector_red_op_2997, 11, fp_vector_red_op_2997_arg11); - InvokeNode* call_fget_flags_2999; - x86::Gp ret_val_fget_flags_2999 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_2999, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_2999; - setRet(call_fget_flags_2999, 0, ret_val_fget_flags_2999); + cc.invoke(&call_fp_vector_red_op_3013, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3014, 0, reinterpret_cast(this)); + setRet(call_sew_3014, 0, ret_val_sew_3014); + setArg(call_fp_vector_red_op_3013, 0, V); + setArg(call_fp_vector_red_op_3013, 1, 1); + setArg(call_fp_vector_red_op_3013, 2, 1); + setArg(call_fp_vector_red_op_3013, 3, fp_vector_red_op_3013_arg3); + setArg(call_fp_vector_red_op_3013, 4, fp_vector_red_op_3013_arg4); + setArg(call_fp_vector_red_op_3013, 5, fp_vector_red_op_3013_arg5); + setArg(call_fp_vector_red_op_3013, 6, vm); + setArg(call_fp_vector_red_op_3013, 7, vd); + setArg(call_fp_vector_red_op_3013, 8, vs2); + setArg(call_fp_vector_red_op_3013, 9, vs1); + setArg(call_fp_vector_red_op_3013, 10, fp_vector_red_op_3013_arg10); + setArg(call_fp_vector_red_op_3013, 11, fp_vector_red_op_3013_arg11); + InvokeNode* call_fget_flags_3015; + x86::Gp ret_val_fget_flags_3015 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3015, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3015; + setRet(call_fget_flags_3015, 0, ret_val_fget_flags_3015); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3000 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3000, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3000, 32, false) - , traits::vstart); + auto tmp3016 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3016, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3016, traits::vstart); } cc.bind(label_merge); } @@ -70792,28 +70452,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3001; - x86::Gp ret_val_get_sew_pow_3001 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3001, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3002 = get_reg(cc, 8, false); - mov(cc, tmp3002, 1); + InvokeNode* call_get_sew_pow_3017; + x86::Gp ret_val_get_sew_pow_3017 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3017, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3018 = get_reg(cc, 8, false); + mov(cc, tmp3018, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3002, (ret_val_get_sew_pow_3001))), 8, false), ~ 1); - setArg(call_get_sew_pow_3001, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3001, 0, ret_val_get_sew_pow_3001); + (gen_operation(cc, shl, tmp3018, (ret_val_get_sew_pow_3017))), 8, false), ~ 1); + setArg(call_get_sew_pow_3017, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3017, 0, ret_val_get_sew_pow_3017); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_3003; - auto illegal_fp_reduction_3003_arg0 = SEW; - auto illegal_fp_reduction_3003_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_3003 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_3003, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_3003; - setArg(call_illegal_fp_reduction_3003, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_3003, 1, illegal_fp_reduction_3003_arg0); - setArg(call_illegal_fp_reduction_3003, 2, illegal_fp_reduction_3003_arg1); - setRet(call_illegal_fp_reduction_3003, 0, ret_val_illegal_fp_reduction_3003); + InvokeNode* call_illegal_fp_reduction_3019; + auto illegal_fp_reduction_3019_arg0 = SEW; + auto illegal_fp_reduction_3019_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3019 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3019, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3019; + setArg(call_illegal_fp_reduction_3019, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3019, 1, illegal_fp_reduction_3019_arg0); + setArg(call_illegal_fp_reduction_3019, 2, illegal_fp_reduction_3019_arg1); + setRet(call_illegal_fp_reduction_3019, 0, ret_val_illegal_fp_reduction_3019); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70829,39 +70489,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3005; - x86::Gp ret_val_sew_3005 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3005, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_op_3004; - auto fp_vector_red_op_3004_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_op_3004_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_op_3004_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_op_3004_arg10 = rm; - auto fp_vector_red_op_3004_arg11 = ret_val_sew_3005; + InvokeNode* call_sew_3021; + x86::Gp ret_val_sew_3021 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3021, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3020; + auto fp_vector_red_op_3020_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3020_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3020_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3020_arg10 = rm; + auto fp_vector_red_op_3020_arg11 = ret_val_sew_3021; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_op_3004, &fp_vector_red_op, FuncSignature::build()); - setArg(call_sew_3005, 0, reinterpret_cast(this)); - setRet(call_sew_3005, 0, ret_val_sew_3005); - setArg(call_fp_vector_red_op_3004, 0, V); - setArg(call_fp_vector_red_op_3004, 1, 7); - setArg(call_fp_vector_red_op_3004, 2, 1); - setArg(call_fp_vector_red_op_3004, 3, fp_vector_red_op_3004_arg3); - setArg(call_fp_vector_red_op_3004, 4, fp_vector_red_op_3004_arg4); - setArg(call_fp_vector_red_op_3004, 5, fp_vector_red_op_3004_arg5); - setArg(call_fp_vector_red_op_3004, 6, vm); - setArg(call_fp_vector_red_op_3004, 7, vd); - setArg(call_fp_vector_red_op_3004, 8, vs2); - setArg(call_fp_vector_red_op_3004, 9, vs1); - setArg(call_fp_vector_red_op_3004, 10, fp_vector_red_op_3004_arg10); - setArg(call_fp_vector_red_op_3004, 11, fp_vector_red_op_3004_arg11); + cc.invoke(&call_fp_vector_red_op_3020, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3021, 0, reinterpret_cast(this)); + setRet(call_sew_3021, 0, ret_val_sew_3021); + setArg(call_fp_vector_red_op_3020, 0, V); + setArg(call_fp_vector_red_op_3020, 1, 7); + setArg(call_fp_vector_red_op_3020, 2, 1); + setArg(call_fp_vector_red_op_3020, 3, fp_vector_red_op_3020_arg3); + setArg(call_fp_vector_red_op_3020, 4, fp_vector_red_op_3020_arg4); + setArg(call_fp_vector_red_op_3020, 5, fp_vector_red_op_3020_arg5); + setArg(call_fp_vector_red_op_3020, 6, vm); + setArg(call_fp_vector_red_op_3020, 7, vd); + setArg(call_fp_vector_red_op_3020, 8, vs2); + setArg(call_fp_vector_red_op_3020, 9, vs1); + setArg(call_fp_vector_red_op_3020, 10, fp_vector_red_op_3020_arg10); + setArg(call_fp_vector_red_op_3020, 11, fp_vector_red_op_3020_arg11); } cc.bind(label_merge); } - auto tmp3006 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3006, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3006, 32, false) - , traits::vstart); + auto tmp3022 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3022, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3022, traits::vstart); } cc.bind(label_merge); } @@ -70905,28 +70563,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3007; - x86::Gp ret_val_get_sew_pow_3007 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3007, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3008 = get_reg(cc, 8, false); - mov(cc, tmp3008, 1); + InvokeNode* call_get_sew_pow_3023; + x86::Gp ret_val_get_sew_pow_3023 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3023, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3024 = get_reg(cc, 8, false); + mov(cc, tmp3024, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3008, (ret_val_get_sew_pow_3007))), 8, false), ~ 1); - setArg(call_get_sew_pow_3007, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3007, 0, ret_val_get_sew_pow_3007); + (gen_operation(cc, shl, tmp3024, (ret_val_get_sew_pow_3023))), 8, false), ~ 1); + setArg(call_get_sew_pow_3023, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3023, 0, ret_val_get_sew_pow_3023); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_3009; - auto illegal_fp_reduction_3009_arg0 = SEW; - auto illegal_fp_reduction_3009_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_3009 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_3009, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_3009; - setArg(call_illegal_fp_reduction_3009, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_3009, 1, illegal_fp_reduction_3009_arg0); - setArg(call_illegal_fp_reduction_3009, 2, illegal_fp_reduction_3009_arg1); - setRet(call_illegal_fp_reduction_3009, 0, ret_val_illegal_fp_reduction_3009); + InvokeNode* call_illegal_fp_reduction_3025; + auto illegal_fp_reduction_3025_arg0 = SEW; + auto illegal_fp_reduction_3025_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3025 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3025, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3025; + setArg(call_illegal_fp_reduction_3025, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3025, 1, illegal_fp_reduction_3025_arg0); + setArg(call_illegal_fp_reduction_3025, 2, illegal_fp_reduction_3025_arg1); + setRet(call_illegal_fp_reduction_3025, 0, ret_val_illegal_fp_reduction_3025); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70942,39 +70600,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3011; - x86::Gp ret_val_sew_3011 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3011, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_op_3010; - auto fp_vector_red_op_3010_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_op_3010_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_op_3010_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_op_3010_arg10 = rm; - auto fp_vector_red_op_3010_arg11 = ret_val_sew_3011; + InvokeNode* call_sew_3027; + x86::Gp ret_val_sew_3027 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3027, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3026; + auto fp_vector_red_op_3026_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3026_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3026_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3026_arg10 = rm; + auto fp_vector_red_op_3026_arg11 = ret_val_sew_3027; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_op_3010, &fp_vector_red_op, FuncSignature::build()); - setArg(call_sew_3011, 0, reinterpret_cast(this)); - setRet(call_sew_3011, 0, ret_val_sew_3011); - setArg(call_fp_vector_red_op_3010, 0, V); - setArg(call_fp_vector_red_op_3010, 1, 5); - setArg(call_fp_vector_red_op_3010, 2, 1); - setArg(call_fp_vector_red_op_3010, 3, fp_vector_red_op_3010_arg3); - setArg(call_fp_vector_red_op_3010, 4, fp_vector_red_op_3010_arg4); - setArg(call_fp_vector_red_op_3010, 5, fp_vector_red_op_3010_arg5); - setArg(call_fp_vector_red_op_3010, 6, vm); - setArg(call_fp_vector_red_op_3010, 7, vd); - setArg(call_fp_vector_red_op_3010, 8, vs2); - setArg(call_fp_vector_red_op_3010, 9, vs1); - setArg(call_fp_vector_red_op_3010, 10, fp_vector_red_op_3010_arg10); - setArg(call_fp_vector_red_op_3010, 11, fp_vector_red_op_3010_arg11); + cc.invoke(&call_fp_vector_red_op_3026, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3027, 0, reinterpret_cast(this)); + setRet(call_sew_3027, 0, ret_val_sew_3027); + setArg(call_fp_vector_red_op_3026, 0, V); + setArg(call_fp_vector_red_op_3026, 1, 5); + setArg(call_fp_vector_red_op_3026, 2, 1); + setArg(call_fp_vector_red_op_3026, 3, fp_vector_red_op_3026_arg3); + setArg(call_fp_vector_red_op_3026, 4, fp_vector_red_op_3026_arg4); + setArg(call_fp_vector_red_op_3026, 5, fp_vector_red_op_3026_arg5); + setArg(call_fp_vector_red_op_3026, 6, vm); + setArg(call_fp_vector_red_op_3026, 7, vd); + setArg(call_fp_vector_red_op_3026, 8, vs2); + setArg(call_fp_vector_red_op_3026, 9, vs1); + setArg(call_fp_vector_red_op_3026, 10, fp_vector_red_op_3026_arg10); + setArg(call_fp_vector_red_op_3026, 11, fp_vector_red_op_3026_arg11); } cc.bind(label_merge); } - auto tmp3012 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3012, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3012, 32, false) - , traits::vstart); + auto tmp3028 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3028, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3028, traits::vstart); } cc.bind(label_merge); } @@ -71018,28 +70674,32 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3013; - x86::Gp ret_val_get_sew_pow_3013 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3013, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3014 = get_reg(cc, 8, false); - mov(cc, tmp3014, 1); + InvokeNode* call_get_sew_pow_3029; + x86::Gp ret_val_get_sew_pow_3029 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3029, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3030 = get_reg(cc, 8, false); + mov(cc, tmp3030, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3014, (ret_val_get_sew_pow_3013))), 8, false), ~ 1); - setArg(call_get_sew_pow_3013, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3013, 0, ret_val_get_sew_pow_3013); + (gen_operation(cc, shl, tmp3030, (ret_val_get_sew_pow_3029))), 8, false), ~ 1); + setArg(call_get_sew_pow_3029, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3029, 0, ret_val_get_sew_pow_3029); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_3015; - auto illegal_fp_reduction_3015_arg0 = SEW; - auto illegal_fp_reduction_3015_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_3015 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_3015, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_3015; - setArg(call_illegal_fp_reduction_3015, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_3015, 1, illegal_fp_reduction_3015_arg0); - setArg(call_illegal_fp_reduction_3015, 2, illegal_fp_reduction_3015_arg1); - setRet(call_illegal_fp_reduction_3015, 0, ret_val_illegal_fp_reduction_3015); + InvokeNode* call_illegal_fp_reduction_widen_3031; + auto illegal_fp_reduction_widen_3031_arg0 = SEW; + auto illegal_fp_reduction_widen_3031_arg1 = rm; + auto illegal_fp_reduction_widen_3031_arg2 = SEW_widen; + x86::Gp ret_val_illegal_fp_reduction_widen_3031 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_widen_3031, (uintptr_t)&vm_impl::_illegal_fp_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_widen_3031; + setArg(call_illegal_fp_reduction_widen_3031, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_widen_3031, 1, illegal_fp_reduction_widen_3031_arg0); + setArg(call_illegal_fp_reduction_widen_3031, 2, illegal_fp_reduction_widen_3031_arg1); + setArg(call_illegal_fp_reduction_widen_3031, 3, illegal_fp_reduction_widen_3031_arg2); + setRet(call_illegal_fp_reduction_widen_3031, 0, ret_val_illegal_fp_reduction_widen_3031); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71055,45 +70715,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3017; - x86::Gp ret_val_sew_3017 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3017, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_wv_3016; - auto fp_vector_red_wv_3016_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_wv_3016_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_wv_3016_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_wv_3016_arg10 = rm; - auto fp_vector_red_wv_3016_arg11 = ret_val_sew_3017; + InvokeNode* call_sew_3033; + x86::Gp ret_val_sew_3033 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3033, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_wv_3032; + auto fp_vector_red_wv_3032_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_wv_3032_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_wv_3032_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_wv_3032_arg10 = rm; + auto fp_vector_red_wv_3032_arg11 = ret_val_sew_3033; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_wv_3016, &fp_vector_red_wv, FuncSignature::build()); - setArg(call_sew_3017, 0, reinterpret_cast(this)); - setRet(call_sew_3017, 0, ret_val_sew_3017); - setArg(call_fp_vector_red_wv_3016, 0, V); - setArg(call_fp_vector_red_wv_3016, 1, 51); - setArg(call_fp_vector_red_wv_3016, 2, 1); - setArg(call_fp_vector_red_wv_3016, 3, fp_vector_red_wv_3016_arg3); - setArg(call_fp_vector_red_wv_3016, 4, fp_vector_red_wv_3016_arg4); - setArg(call_fp_vector_red_wv_3016, 5, fp_vector_red_wv_3016_arg5); - setArg(call_fp_vector_red_wv_3016, 6, vm); - setArg(call_fp_vector_red_wv_3016, 7, vd); - setArg(call_fp_vector_red_wv_3016, 8, vs2); - setArg(call_fp_vector_red_wv_3016, 9, vs1); - setArg(call_fp_vector_red_wv_3016, 10, fp_vector_red_wv_3016_arg10); - setArg(call_fp_vector_red_wv_3016, 11, fp_vector_red_wv_3016_arg11); - InvokeNode* call_fget_flags_3018; - x86::Gp ret_val_fget_flags_3018 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3018, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3018; - setRet(call_fget_flags_3018, 0, ret_val_fget_flags_3018); + cc.invoke(&call_fp_vector_red_wv_3032, &fp_vector_red_wv, FuncSignature::build()); + setArg(call_sew_3033, 0, reinterpret_cast(this)); + setRet(call_sew_3033, 0, ret_val_sew_3033); + setArg(call_fp_vector_red_wv_3032, 0, V); + setArg(call_fp_vector_red_wv_3032, 1, 51); + setArg(call_fp_vector_red_wv_3032, 2, 1); + setArg(call_fp_vector_red_wv_3032, 3, fp_vector_red_wv_3032_arg3); + setArg(call_fp_vector_red_wv_3032, 4, fp_vector_red_wv_3032_arg4); + setArg(call_fp_vector_red_wv_3032, 5, fp_vector_red_wv_3032_arg5); + setArg(call_fp_vector_red_wv_3032, 6, vm); + setArg(call_fp_vector_red_wv_3032, 7, vd); + setArg(call_fp_vector_red_wv_3032, 8, vs2); + setArg(call_fp_vector_red_wv_3032, 9, vs1); + setArg(call_fp_vector_red_wv_3032, 10, fp_vector_red_wv_3032_arg10); + setArg(call_fp_vector_red_wv_3032, 11, fp_vector_red_wv_3032_arg11); + InvokeNode* call_fget_flags_3034; + x86::Gp ret_val_fget_flags_3034 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3034, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3034; + setRet(call_fget_flags_3034, 0, ret_val_fget_flags_3034); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3019 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3019, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3019, 32, false) - , traits::vstart); + auto tmp3035 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3035, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3035, traits::vstart); } cc.bind(label_merge); } @@ -71137,28 +70795,32 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3020; - x86::Gp ret_val_get_sew_pow_3020 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3020, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3021 = get_reg(cc, 8, false); - mov(cc, tmp3021, 1); + InvokeNode* call_get_sew_pow_3036; + x86::Gp ret_val_get_sew_pow_3036 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3036, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3037 = get_reg(cc, 8, false); + mov(cc, tmp3037, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3021, (ret_val_get_sew_pow_3020))), 8, false), ~ 1); - setArg(call_get_sew_pow_3020, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3020, 0, ret_val_get_sew_pow_3020); + (gen_operation(cc, shl, tmp3037, (ret_val_get_sew_pow_3036))), 8, false), ~ 1); + setArg(call_get_sew_pow_3036, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3036, 0, ret_val_get_sew_pow_3036); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_3022; - auto illegal_fp_reduction_3022_arg0 = SEW; - auto illegal_fp_reduction_3022_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_3022 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_3022, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_3022; - setArg(call_illegal_fp_reduction_3022, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_3022, 1, illegal_fp_reduction_3022_arg0); - setArg(call_illegal_fp_reduction_3022, 2, illegal_fp_reduction_3022_arg1); - setRet(call_illegal_fp_reduction_3022, 0, ret_val_illegal_fp_reduction_3022); + InvokeNode* call_illegal_fp_reduction_widen_3038; + auto illegal_fp_reduction_widen_3038_arg0 = SEW; + auto illegal_fp_reduction_widen_3038_arg1 = rm; + auto illegal_fp_reduction_widen_3038_arg2 = SEW_widen; + x86::Gp ret_val_illegal_fp_reduction_widen_3038 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_widen_3038, (uintptr_t)&vm_impl::_illegal_fp_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_widen_3038; + setArg(call_illegal_fp_reduction_widen_3038, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_widen_3038, 1, illegal_fp_reduction_widen_3038_arg0); + setArg(call_illegal_fp_reduction_widen_3038, 2, illegal_fp_reduction_widen_3038_arg1); + setArg(call_illegal_fp_reduction_widen_3038, 3, illegal_fp_reduction_widen_3038_arg2); + setRet(call_illegal_fp_reduction_widen_3038, 0, ret_val_illegal_fp_reduction_widen_3038); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71174,45 +70836,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3024; - x86::Gp ret_val_sew_3024 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3024, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_wv_3023; - auto fp_vector_red_wv_3023_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_wv_3023_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_wv_3023_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_wv_3023_arg10 = rm; - auto fp_vector_red_wv_3023_arg11 = ret_val_sew_3024; + InvokeNode* call_sew_3040; + x86::Gp ret_val_sew_3040 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3040, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_wv_3039; + auto fp_vector_red_wv_3039_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_wv_3039_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_wv_3039_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_wv_3039_arg10 = rm; + auto fp_vector_red_wv_3039_arg11 = ret_val_sew_3040; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_wv_3023, &fp_vector_red_wv, FuncSignature::build()); - setArg(call_sew_3024, 0, reinterpret_cast(this)); - setRet(call_sew_3024, 0, ret_val_sew_3024); - setArg(call_fp_vector_red_wv_3023, 0, V); - setArg(call_fp_vector_red_wv_3023, 1, 49); - setArg(call_fp_vector_red_wv_3023, 2, 1); - setArg(call_fp_vector_red_wv_3023, 3, fp_vector_red_wv_3023_arg3); - setArg(call_fp_vector_red_wv_3023, 4, fp_vector_red_wv_3023_arg4); - setArg(call_fp_vector_red_wv_3023, 5, fp_vector_red_wv_3023_arg5); - setArg(call_fp_vector_red_wv_3023, 6, vm); - setArg(call_fp_vector_red_wv_3023, 7, vd); - setArg(call_fp_vector_red_wv_3023, 8, vs2); - setArg(call_fp_vector_red_wv_3023, 9, vs1); - setArg(call_fp_vector_red_wv_3023, 10, fp_vector_red_wv_3023_arg10); - setArg(call_fp_vector_red_wv_3023, 11, fp_vector_red_wv_3023_arg11); - InvokeNode* call_fget_flags_3025; - x86::Gp ret_val_fget_flags_3025 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3025, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3025; - setRet(call_fget_flags_3025, 0, ret_val_fget_flags_3025); + cc.invoke(&call_fp_vector_red_wv_3039, &fp_vector_red_wv, FuncSignature::build()); + setArg(call_sew_3040, 0, reinterpret_cast(this)); + setRet(call_sew_3040, 0, ret_val_sew_3040); + setArg(call_fp_vector_red_wv_3039, 0, V); + setArg(call_fp_vector_red_wv_3039, 1, 49); + setArg(call_fp_vector_red_wv_3039, 2, 1); + setArg(call_fp_vector_red_wv_3039, 3, fp_vector_red_wv_3039_arg3); + setArg(call_fp_vector_red_wv_3039, 4, fp_vector_red_wv_3039_arg4); + setArg(call_fp_vector_red_wv_3039, 5, fp_vector_red_wv_3039_arg5); + setArg(call_fp_vector_red_wv_3039, 6, vm); + setArg(call_fp_vector_red_wv_3039, 7, vd); + setArg(call_fp_vector_red_wv_3039, 8, vs2); + setArg(call_fp_vector_red_wv_3039, 9, vs1); + setArg(call_fp_vector_red_wv_3039, 10, fp_vector_red_wv_3039_arg10); + setArg(call_fp_vector_red_wv_3039, 11, fp_vector_red_wv_3039_arg11); + InvokeNode* call_fget_flags_3041; + x86::Gp ret_val_fget_flags_3041 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3041, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3041; + setRet(call_fget_flags_3041, 0, ret_val_fget_flags_3041); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3026 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3026, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3026, 32, false) - , traits::vstart); + auto tmp3042 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3042, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3042, traits::vstart); } cc.bind(label_merge); } @@ -71257,12 +70917,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3027; - x86::Gp ret_val_illegal_vd_unmasked_3027 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3027, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3027; - setArg(call_illegal_vd_unmasked_3027, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3027, 0, ret_val_illegal_vd_unmasked_3027); + InvokeNode* call_illegal_vd_unmasked_3043; + x86::Gp ret_val_illegal_vd_unmasked_3043 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3043, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3043; + setArg(call_illegal_vd_unmasked_3043, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3043, 0, ret_val_illegal_vd_unmasked_3043); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71278,27 +70938,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3028; - auto mask_mask_op_3028_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3028_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3044; + auto mask_mask_op_3044_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3044_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3028, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3028, 0, V); - setArg(call_mask_mask_op_3028, 1, 25); - setArg(call_mask_mask_op_3028, 2, 2); - setArg(call_mask_mask_op_3028, 3, mask_mask_op_3028_arg3); - setArg(call_mask_mask_op_3028, 4, mask_mask_op_3028_arg4); - setArg(call_mask_mask_op_3028, 5, vd); - setArg(call_mask_mask_op_3028, 6, vs2); - setArg(call_mask_mask_op_3028, 7, vs1); + cc.invoke(&call_mask_mask_op_3044, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3044, 0, V); + setArg(call_mask_mask_op_3044, 1, 25); + setArg(call_mask_mask_op_3044, 2, 2); + setArg(call_mask_mask_op_3044, 3, mask_mask_op_3044_arg3); + setArg(call_mask_mask_op_3044, 4, mask_mask_op_3044_arg4); + setArg(call_mask_mask_op_3044, 5, vd); + setArg(call_mask_mask_op_3044, 6, vs2); + setArg(call_mask_mask_op_3044, 7, vs1); } cc.bind(label_merge); } - auto tmp3029 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3029, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3029, 32, false) - , traits::vstart); + auto tmp3045 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3045, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3045, traits::vstart); } cc.bind(label_merge); } @@ -71343,12 +71001,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3030; - x86::Gp ret_val_illegal_vd_unmasked_3030 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3030, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3030; - setArg(call_illegal_vd_unmasked_3030, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3030, 0, ret_val_illegal_vd_unmasked_3030); + InvokeNode* call_illegal_vd_unmasked_3046; + x86::Gp ret_val_illegal_vd_unmasked_3046 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3046, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3046; + setArg(call_illegal_vd_unmasked_3046, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3046, 0, ret_val_illegal_vd_unmasked_3046); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71364,27 +71022,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3031; - auto mask_mask_op_3031_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3031_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3047; + auto mask_mask_op_3047_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3047_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3031, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3031, 0, V); - setArg(call_mask_mask_op_3031, 1, 29); - setArg(call_mask_mask_op_3031, 2, 2); - setArg(call_mask_mask_op_3031, 3, mask_mask_op_3031_arg3); - setArg(call_mask_mask_op_3031, 4, mask_mask_op_3031_arg4); - setArg(call_mask_mask_op_3031, 5, vd); - setArg(call_mask_mask_op_3031, 6, vs2); - setArg(call_mask_mask_op_3031, 7, vs1); + cc.invoke(&call_mask_mask_op_3047, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3047, 0, V); + setArg(call_mask_mask_op_3047, 1, 29); + setArg(call_mask_mask_op_3047, 2, 2); + setArg(call_mask_mask_op_3047, 3, mask_mask_op_3047_arg3); + setArg(call_mask_mask_op_3047, 4, mask_mask_op_3047_arg4); + setArg(call_mask_mask_op_3047, 5, vd); + setArg(call_mask_mask_op_3047, 6, vs2); + setArg(call_mask_mask_op_3047, 7, vs1); } cc.bind(label_merge); } - auto tmp3032 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3032, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3032, 32, false) - , traits::vstart); + auto tmp3048 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3048, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3048, traits::vstart); } cc.bind(label_merge); } @@ -71429,12 +71085,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3033; - x86::Gp ret_val_illegal_vd_unmasked_3033 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3033, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3033; - setArg(call_illegal_vd_unmasked_3033, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3033, 0, ret_val_illegal_vd_unmasked_3033); + InvokeNode* call_illegal_vd_unmasked_3049; + x86::Gp ret_val_illegal_vd_unmasked_3049 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3049, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3049; + setArg(call_illegal_vd_unmasked_3049, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3049, 0, ret_val_illegal_vd_unmasked_3049); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71450,27 +71106,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3034; - auto mask_mask_op_3034_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3034_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3050; + auto mask_mask_op_3050_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3050_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3034, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3034, 0, V); - setArg(call_mask_mask_op_3034, 1, 24); - setArg(call_mask_mask_op_3034, 2, 2); - setArg(call_mask_mask_op_3034, 3, mask_mask_op_3034_arg3); - setArg(call_mask_mask_op_3034, 4, mask_mask_op_3034_arg4); - setArg(call_mask_mask_op_3034, 5, vd); - setArg(call_mask_mask_op_3034, 6, vs2); - setArg(call_mask_mask_op_3034, 7, vs1); + cc.invoke(&call_mask_mask_op_3050, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3050, 0, V); + setArg(call_mask_mask_op_3050, 1, 24); + setArg(call_mask_mask_op_3050, 2, 2); + setArg(call_mask_mask_op_3050, 3, mask_mask_op_3050_arg3); + setArg(call_mask_mask_op_3050, 4, mask_mask_op_3050_arg4); + setArg(call_mask_mask_op_3050, 5, vd); + setArg(call_mask_mask_op_3050, 6, vs2); + setArg(call_mask_mask_op_3050, 7, vs1); } cc.bind(label_merge); } - auto tmp3035 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3035, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3035, 32, false) - , traits::vstart); + auto tmp3051 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3051, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3051, traits::vstart); } cc.bind(label_merge); } @@ -71515,12 +71169,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3036; - x86::Gp ret_val_illegal_vd_unmasked_3036 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3036, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3036; - setArg(call_illegal_vd_unmasked_3036, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3036, 0, ret_val_illegal_vd_unmasked_3036); + InvokeNode* call_illegal_vd_unmasked_3052; + x86::Gp ret_val_illegal_vd_unmasked_3052 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3052, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3052; + setArg(call_illegal_vd_unmasked_3052, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3052, 0, ret_val_illegal_vd_unmasked_3052); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71536,27 +71190,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3037; - auto mask_mask_op_3037_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3037_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3053; + auto mask_mask_op_3053_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3053_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3037, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3037, 0, V); - setArg(call_mask_mask_op_3037, 1, 27); - setArg(call_mask_mask_op_3037, 2, 2); - setArg(call_mask_mask_op_3037, 3, mask_mask_op_3037_arg3); - setArg(call_mask_mask_op_3037, 4, mask_mask_op_3037_arg4); - setArg(call_mask_mask_op_3037, 5, vd); - setArg(call_mask_mask_op_3037, 6, vs2); - setArg(call_mask_mask_op_3037, 7, vs1); + cc.invoke(&call_mask_mask_op_3053, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3053, 0, V); + setArg(call_mask_mask_op_3053, 1, 27); + setArg(call_mask_mask_op_3053, 2, 2); + setArg(call_mask_mask_op_3053, 3, mask_mask_op_3053_arg3); + setArg(call_mask_mask_op_3053, 4, mask_mask_op_3053_arg4); + setArg(call_mask_mask_op_3053, 5, vd); + setArg(call_mask_mask_op_3053, 6, vs2); + setArg(call_mask_mask_op_3053, 7, vs1); } cc.bind(label_merge); } - auto tmp3038 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3038, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3038, 32, false) - , traits::vstart); + auto tmp3054 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3054, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3054, traits::vstart); } cc.bind(label_merge); } @@ -71601,12 +71253,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3039; - x86::Gp ret_val_illegal_vd_unmasked_3039 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3039, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3039; - setArg(call_illegal_vd_unmasked_3039, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3039, 0, ret_val_illegal_vd_unmasked_3039); + InvokeNode* call_illegal_vd_unmasked_3055; + x86::Gp ret_val_illegal_vd_unmasked_3055 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3055, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3055; + setArg(call_illegal_vd_unmasked_3055, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3055, 0, ret_val_illegal_vd_unmasked_3055); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71622,27 +71274,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3040; - auto mask_mask_op_3040_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3040_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3056; + auto mask_mask_op_3056_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3056_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3040, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3040, 0, V); - setArg(call_mask_mask_op_3040, 1, 26); - setArg(call_mask_mask_op_3040, 2, 2); - setArg(call_mask_mask_op_3040, 3, mask_mask_op_3040_arg3); - setArg(call_mask_mask_op_3040, 4, mask_mask_op_3040_arg4); - setArg(call_mask_mask_op_3040, 5, vd); - setArg(call_mask_mask_op_3040, 6, vs2); - setArg(call_mask_mask_op_3040, 7, vs1); + cc.invoke(&call_mask_mask_op_3056, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3056, 0, V); + setArg(call_mask_mask_op_3056, 1, 26); + setArg(call_mask_mask_op_3056, 2, 2); + setArg(call_mask_mask_op_3056, 3, mask_mask_op_3056_arg3); + setArg(call_mask_mask_op_3056, 4, mask_mask_op_3056_arg4); + setArg(call_mask_mask_op_3056, 5, vd); + setArg(call_mask_mask_op_3056, 6, vs2); + setArg(call_mask_mask_op_3056, 7, vs1); } cc.bind(label_merge); } - auto tmp3041 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3041, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3041, 32, false) - , traits::vstart); + auto tmp3057 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3057, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3057, traits::vstart); } cc.bind(label_merge); } @@ -71687,12 +71337,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3042; - x86::Gp ret_val_illegal_vd_unmasked_3042 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3042, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3042; - setArg(call_illegal_vd_unmasked_3042, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3042, 0, ret_val_illegal_vd_unmasked_3042); + InvokeNode* call_illegal_vd_unmasked_3058; + x86::Gp ret_val_illegal_vd_unmasked_3058 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3058, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3058; + setArg(call_illegal_vd_unmasked_3058, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3058, 0, ret_val_illegal_vd_unmasked_3058); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71708,27 +71358,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3043; - auto mask_mask_op_3043_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3043_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3059; + auto mask_mask_op_3059_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3059_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3043, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3043, 0, V); - setArg(call_mask_mask_op_3043, 1, 30); - setArg(call_mask_mask_op_3043, 2, 2); - setArg(call_mask_mask_op_3043, 3, mask_mask_op_3043_arg3); - setArg(call_mask_mask_op_3043, 4, mask_mask_op_3043_arg4); - setArg(call_mask_mask_op_3043, 5, vd); - setArg(call_mask_mask_op_3043, 6, vs2); - setArg(call_mask_mask_op_3043, 7, vs1); + cc.invoke(&call_mask_mask_op_3059, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3059, 0, V); + setArg(call_mask_mask_op_3059, 1, 30); + setArg(call_mask_mask_op_3059, 2, 2); + setArg(call_mask_mask_op_3059, 3, mask_mask_op_3059_arg3); + setArg(call_mask_mask_op_3059, 4, mask_mask_op_3059_arg4); + setArg(call_mask_mask_op_3059, 5, vd); + setArg(call_mask_mask_op_3059, 6, vs2); + setArg(call_mask_mask_op_3059, 7, vs1); } cc.bind(label_merge); } - auto tmp3044 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3044, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3044, 32, false) - , traits::vstart); + auto tmp3060 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3060, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3060, traits::vstart); } cc.bind(label_merge); } @@ -71773,12 +71421,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3045; - x86::Gp ret_val_illegal_vd_unmasked_3045 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3045, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3045; - setArg(call_illegal_vd_unmasked_3045, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3045, 0, ret_val_illegal_vd_unmasked_3045); + InvokeNode* call_illegal_vd_unmasked_3061; + x86::Gp ret_val_illegal_vd_unmasked_3061 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3061, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3061; + setArg(call_illegal_vd_unmasked_3061, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3061, 0, ret_val_illegal_vd_unmasked_3061); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71794,27 +71442,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3046; - auto mask_mask_op_3046_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3046_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3062; + auto mask_mask_op_3062_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3062_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3046, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3046, 0, V); - setArg(call_mask_mask_op_3046, 1, 28); - setArg(call_mask_mask_op_3046, 2, 2); - setArg(call_mask_mask_op_3046, 3, mask_mask_op_3046_arg3); - setArg(call_mask_mask_op_3046, 4, mask_mask_op_3046_arg4); - setArg(call_mask_mask_op_3046, 5, vd); - setArg(call_mask_mask_op_3046, 6, vs2); - setArg(call_mask_mask_op_3046, 7, vs1); + cc.invoke(&call_mask_mask_op_3062, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3062, 0, V); + setArg(call_mask_mask_op_3062, 1, 28); + setArg(call_mask_mask_op_3062, 2, 2); + setArg(call_mask_mask_op_3062, 3, mask_mask_op_3062_arg3); + setArg(call_mask_mask_op_3062, 4, mask_mask_op_3062_arg4); + setArg(call_mask_mask_op_3062, 5, vd); + setArg(call_mask_mask_op_3062, 6, vs2); + setArg(call_mask_mask_op_3062, 7, vs1); } cc.bind(label_merge); } - auto tmp3047 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3047, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3047, 32, false) - , traits::vstart); + auto tmp3063 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3063, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3063, traits::vstart); } cc.bind(label_merge); } @@ -71859,12 +71505,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3048; - x86::Gp ret_val_illegal_vd_unmasked_3048 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3048, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3048; - setArg(call_illegal_vd_unmasked_3048, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3048, 0, ret_val_illegal_vd_unmasked_3048); + InvokeNode* call_illegal_vd_unmasked_3064; + x86::Gp ret_val_illegal_vd_unmasked_3064 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3064, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3064; + setArg(call_illegal_vd_unmasked_3064, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3064, 0, ret_val_illegal_vd_unmasked_3064); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71880,27 +71526,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3049; - auto mask_mask_op_3049_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3049_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3065; + auto mask_mask_op_3065_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3065_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3049, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3049, 0, V); - setArg(call_mask_mask_op_3049, 1, 31); - setArg(call_mask_mask_op_3049, 2, 2); - setArg(call_mask_mask_op_3049, 3, mask_mask_op_3049_arg3); - setArg(call_mask_mask_op_3049, 4, mask_mask_op_3049_arg4); - setArg(call_mask_mask_op_3049, 5, vd); - setArg(call_mask_mask_op_3049, 6, vs2); - setArg(call_mask_mask_op_3049, 7, vs1); + cc.invoke(&call_mask_mask_op_3065, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3065, 0, V); + setArg(call_mask_mask_op_3065, 1, 31); + setArg(call_mask_mask_op_3065, 2, 2); + setArg(call_mask_mask_op_3065, 3, mask_mask_op_3065_arg3); + setArg(call_mask_mask_op_3065, 4, mask_mask_op_3065_arg4); + setArg(call_mask_mask_op_3065, 5, vd); + setArg(call_mask_mask_op_3065, 6, vs2); + setArg(call_mask_mask_op_3065, 7, vs1); } cc.bind(label_merge); } - auto tmp3050 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3050, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3050, 32, false) - , traits::vstart); + auto tmp3066 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3066, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3066, traits::vstart); } cc.bind(label_merge); } @@ -71945,14 +71589,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3051; - x86::Gp ret_val_illegal_vd_unmasked_3051 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3051, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto tmp3052 = get_reg(cc, 8, false); - mov(cc, tmp3052, rd>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3052, ret_val_illegal_vd_unmasked_3051), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); - setArg(call_illegal_vd_unmasked_3051, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3051, 0, ret_val_illegal_vd_unmasked_3051); + InvokeNode* call_illegal_vd_unmasked_3067; + x86::Gp ret_val_illegal_vd_unmasked_3067 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3067, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3068 = get_reg(cc, 8, false); + mov(cc, tmp3068, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3068, ret_val_illegal_vd_unmasked_3067), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); + setArg(call_illegal_vd_unmasked_3067, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3067, 0, ret_val_illegal_vd_unmasked_3067); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71963,25 +71607,23 @@ template class vm_impl : public iss::asmjit::vm_base { cc.bind(label_else); { if(rd!=0){ - InvokeNode* call_vcpop_3053; - auto vcpop_3053_arg1 = load_reg_from_mem(jh, traits::vl); - auto vcpop_3053_arg2 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_vcpop_3069; + auto vcpop_3069_arg1 = load_reg_from_mem(jh, traits::vl); + auto vcpop_3069_arg2 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_vcpop_3053 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_vcpop_3053, &vcpop, FuncSignature::build()); + x86::Gp ret_val_vcpop_3069 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_vcpop_3069, &vcpop, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::X0+ rd), - ret_val_vcpop_3053); - setArg(call_vcpop_3053, 0, V); - setArg(call_vcpop_3053, 1, vcpop_3053_arg1); - setArg(call_vcpop_3053, 2, vcpop_3053_arg2); - setArg(call_vcpop_3053, 3, vm); - setArg(call_vcpop_3053, 4, vs2); - setRet(call_vcpop_3053, 0, ret_val_vcpop_3053); - auto tmp3054 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3054, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3054, 32, false) - , traits::vstart); + ret_val_vcpop_3069); + setArg(call_vcpop_3069, 0, V); + setArg(call_vcpop_3069, 1, vcpop_3069_arg1); + setArg(call_vcpop_3069, 2, vcpop_3069_arg2); + setArg(call_vcpop_3069, 3, vm); + setArg(call_vcpop_3069, 4, vs2); + setRet(call_vcpop_3069, 0, ret_val_vcpop_3069); + auto tmp3070 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3070, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3070, traits::vstart); } } cc.bind(label_merge); @@ -72027,14 +71669,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3055; - x86::Gp ret_val_illegal_vd_unmasked_3055 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3055, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto tmp3056 = get_reg(cc, 8, false); - mov(cc, tmp3056, rd>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3056, ret_val_illegal_vd_unmasked_3055), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); - setArg(call_illegal_vd_unmasked_3055, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3055, 0, ret_val_illegal_vd_unmasked_3055); + InvokeNode* call_illegal_vd_unmasked_3071; + x86::Gp ret_val_illegal_vd_unmasked_3071 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3071, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3072 = get_reg(cc, 8, false); + mov(cc, tmp3072, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3072, ret_val_illegal_vd_unmasked_3071), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); + setArg(call_illegal_vd_unmasked_3071, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3071, 0, ret_val_illegal_vd_unmasked_3071); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72045,25 +71687,23 @@ template class vm_impl : public iss::asmjit::vm_base { cc.bind(label_else); { if(rd!=0){ - InvokeNode* call_vfirst_3057; - auto vfirst_3057_arg1 = load_reg_from_mem(jh, traits::vl); - auto vfirst_3057_arg2 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_vfirst_3073; + auto vfirst_3073_arg1 = load_reg_from_mem(jh, traits::vl); + auto vfirst_3073_arg2 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_vfirst_3057 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_vfirst_3057, &vfirst, FuncSignature::build()); + x86::Gp ret_val_vfirst_3073 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_vfirst_3073, &vfirst, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::X0+ rd), - ret_val_vfirst_3057); - setArg(call_vfirst_3057, 0, V); - setArg(call_vfirst_3057, 1, vfirst_3057_arg1); - setArg(call_vfirst_3057, 2, vfirst_3057_arg2); - setArg(call_vfirst_3057, 3, vm); - setArg(call_vfirst_3057, 4, vs2); - setRet(call_vfirst_3057, 0, ret_val_vfirst_3057); - auto tmp3058 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3058, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3058, 32, false) - , traits::vstart); + ret_val_vfirst_3073); + setArg(call_vfirst_3073, 0, V); + setArg(call_vfirst_3073, 1, vfirst_3073_arg1); + setArg(call_vfirst_3073, 2, vfirst_3073_arg2); + setArg(call_vfirst_3073, 3, vm); + setArg(call_vfirst_3073, 4, vs2); + setRet(call_vfirst_3073, 0, ret_val_vfirst_3073); + auto tmp3074 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3074, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3074, traits::vstart); } } cc.bind(label_merge); @@ -72109,12 +71749,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3059; - x86::Gp ret_val_illegal_vd_unmasked_3059 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3059, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3059, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); - setArg(call_illegal_vd_unmasked_3059, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3059, 0, ret_val_illegal_vd_unmasked_3059); + InvokeNode* call_illegal_vd_unmasked_3075; + x86::Gp ret_val_illegal_vd_unmasked_3075 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3075, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3075, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3075, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3075, 0, ret_val_illegal_vd_unmasked_3075); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72124,23 +71764,21 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_mask_set_op_3060; - auto mask_set_op_3060_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_set_op_3060_arg3 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_set_op_3076; + auto mask_set_op_3076_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3076_arg3 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_set_op_3060, &mask_set_op, FuncSignature::build()); - setArg(call_mask_set_op_3060, 0, V); - setArg(call_mask_set_op_3060, 1, 1); - setArg(call_mask_set_op_3060, 2, mask_set_op_3060_arg2); - setArg(call_mask_set_op_3060, 3, mask_set_op_3060_arg3); - setArg(call_mask_set_op_3060, 4, vm); - setArg(call_mask_set_op_3060, 5, vd); - setArg(call_mask_set_op_3060, 6, vs2); - auto tmp3061 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3061, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3061, 32, false) - , traits::vstart); + cc.invoke(&call_mask_set_op_3076, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3076, 0, V); + setArg(call_mask_set_op_3076, 1, 1); + setArg(call_mask_set_op_3076, 2, mask_set_op_3076_arg2); + setArg(call_mask_set_op_3076, 3, mask_set_op_3076_arg3); + setArg(call_mask_set_op_3076, 4, vm); + setArg(call_mask_set_op_3076, 5, vd); + setArg(call_mask_set_op_3076, 6, vs2); + auto tmp3077 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3077, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3077, traits::vstart); } cc.bind(label_merge); } @@ -72185,12 +71823,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3062; - x86::Gp ret_val_illegal_vd_unmasked_3062 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3062, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3062, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); - setArg(call_illegal_vd_unmasked_3062, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3062, 0, ret_val_illegal_vd_unmasked_3062); + InvokeNode* call_illegal_vd_unmasked_3078; + x86::Gp ret_val_illegal_vd_unmasked_3078 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3078, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3078, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3078, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3078, 0, ret_val_illegal_vd_unmasked_3078); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72200,23 +71838,21 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_mask_set_op_3063; - auto mask_set_op_3063_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_set_op_3063_arg3 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_set_op_3079; + auto mask_set_op_3079_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3079_arg3 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_set_op_3063, &mask_set_op, FuncSignature::build()); - setArg(call_mask_set_op_3063, 0, V); - setArg(call_mask_set_op_3063, 1, 3); - setArg(call_mask_set_op_3063, 2, mask_set_op_3063_arg2); - setArg(call_mask_set_op_3063, 3, mask_set_op_3063_arg3); - setArg(call_mask_set_op_3063, 4, vm); - setArg(call_mask_set_op_3063, 5, vd); - setArg(call_mask_set_op_3063, 6, vs2); - auto tmp3064 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3064, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3064, 32, false) - , traits::vstart); + cc.invoke(&call_mask_set_op_3079, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3079, 0, V); + setArg(call_mask_set_op_3079, 1, 3); + setArg(call_mask_set_op_3079, 2, mask_set_op_3079_arg2); + setArg(call_mask_set_op_3079, 3, mask_set_op_3079_arg3); + setArg(call_mask_set_op_3079, 4, vm); + setArg(call_mask_set_op_3079, 5, vd); + setArg(call_mask_set_op_3079, 6, vs2); + auto tmp3080 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3080, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3080, traits::vstart); } cc.bind(label_merge); } @@ -72261,12 +71897,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3065; - x86::Gp ret_val_illegal_vd_unmasked_3065 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3065, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3065, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); - setArg(call_illegal_vd_unmasked_3065, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3065, 0, ret_val_illegal_vd_unmasked_3065); + InvokeNode* call_illegal_vd_unmasked_3081; + x86::Gp ret_val_illegal_vd_unmasked_3081 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3081, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3081, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3081, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3081, 0, ret_val_illegal_vd_unmasked_3081); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72276,23 +71912,21 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_mask_set_op_3066; - auto mask_set_op_3066_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_set_op_3066_arg3 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_set_op_3082; + auto mask_set_op_3082_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3082_arg3 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_set_op_3066, &mask_set_op, FuncSignature::build()); - setArg(call_mask_set_op_3066, 0, V); - setArg(call_mask_set_op_3066, 1, 2); - setArg(call_mask_set_op_3066, 2, mask_set_op_3066_arg2); - setArg(call_mask_set_op_3066, 3, mask_set_op_3066_arg3); - setArg(call_mask_set_op_3066, 4, vm); - setArg(call_mask_set_op_3066, 5, vd); - setArg(call_mask_set_op_3066, 6, vs2); - auto tmp3067 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3067, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3067, 32, false) - , traits::vstart); + cc.invoke(&call_mask_set_op_3082, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3082, 0, V); + setArg(call_mask_set_op_3082, 1, 2); + setArg(call_mask_set_op_3082, 2, mask_set_op_3082_arg2); + setArg(call_mask_set_op_3082, 3, mask_set_op_3082_arg3); + setArg(call_mask_set_op_3082, 4, vm); + setArg(call_mask_set_op_3082, 5, vd); + setArg(call_mask_set_op_3082, 6, vs2); + auto tmp3083 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3083, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3083, traits::vstart); } cc.bind(label_merge); } @@ -72337,12 +71971,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3068; - x86::Gp ret_val_illegal_vd_unmasked_3068 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3068, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3068, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); - setArg(call_illegal_vd_unmasked_3068, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3068, 0, ret_val_illegal_vd_unmasked_3068); + InvokeNode* call_illegal_vd_unmasked_3084; + x86::Gp ret_val_illegal_vd_unmasked_3084 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3084, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3084, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3084, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3084, 0, ret_val_illegal_vd_unmasked_3084); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72352,31 +71986,29 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3070; - x86::Gp ret_val_sew_3070 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3070, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_viota_3069; - auto viota_3069_arg1 = load_reg_from_mem(jh, traits::vl); - auto viota_3069_arg2 = load_reg_from_mem(jh, traits::vstart); - auto viota_3069_arg3 = load_reg_from_mem(jh, traits::vtype); - auto viota_3069_arg7 = ret_val_sew_3070; + InvokeNode* call_sew_3086; + x86::Gp ret_val_sew_3086 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3086, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_viota_3085; + auto viota_3085_arg1 = load_reg_from_mem(jh, traits::vl); + auto viota_3085_arg2 = load_reg_from_mem(jh, traits::vstart); + auto viota_3085_arg3 = load_reg_from_mem(jh, traits::vtype); + auto viota_3085_arg7 = ret_val_sew_3086; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_viota_3069, &viota, FuncSignature::build()); - setArg(call_sew_3070, 0, reinterpret_cast(this)); - setRet(call_sew_3070, 0, ret_val_sew_3070); - setArg(call_viota_3069, 0, V); - setArg(call_viota_3069, 1, viota_3069_arg1); - setArg(call_viota_3069, 2, viota_3069_arg2); - setArg(call_viota_3069, 3, viota_3069_arg3); - setArg(call_viota_3069, 4, vm); - setArg(call_viota_3069, 5, vd); - setArg(call_viota_3069, 6, vs2); - setArg(call_viota_3069, 7, viota_3069_arg7); - auto tmp3071 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3071, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3071, 32, false) - , traits::vstart); + cc.invoke(&call_viota_3085, &viota, FuncSignature::build()); + setArg(call_sew_3086, 0, reinterpret_cast(this)); + setRet(call_sew_3086, 0, ret_val_sew_3086); + setArg(call_viota_3085, 0, V); + setArg(call_viota_3085, 1, viota_3085_arg1); + setArg(call_viota_3085, 2, viota_3085_arg2); + setArg(call_viota_3085, 3, viota_3085_arg3); + setArg(call_viota_3085, 4, vm); + setArg(call_viota_3085, 5, vd); + setArg(call_viota_3085, 6, vs2); + setArg(call_viota_3085, 7, viota_3085_arg7); + auto tmp3087 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3087, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3087, traits::vstart); } cc.bind(label_merge); } @@ -72420,14 +72052,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3072; - x86::Gp ret_val_illegal_normal_3072 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3072, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_3072; - setArg(call_illegal_normal_3072, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3072, 1, vd); - setArg(call_illegal_normal_3072, 2, vm); - setRet(call_illegal_normal_3072, 0, ret_val_illegal_normal_3072); + InvokeNode* call_illegal_normal_3088; + x86::Gp ret_val_illegal_normal_3088 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3088, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_3088; + setArg(call_illegal_normal_3088, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3088, 1, vd); + setArg(call_illegal_normal_3088, 2, vm); + setRet(call_illegal_normal_3088, 0, ret_val_illegal_normal_3088); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72437,30 +72069,28 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3074; - x86::Gp ret_val_sew_3074 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3074, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vid_3073; - auto vid_3073_arg1 = load_reg_from_mem(jh, traits::vl); - auto vid_3073_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vid_3073_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vid_3073_arg6 = ret_val_sew_3074; + InvokeNode* call_sew_3090; + x86::Gp ret_val_sew_3090 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3090, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vid_3089; + auto vid_3089_arg1 = load_reg_from_mem(jh, traits::vl); + auto vid_3089_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vid_3089_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vid_3089_arg6 = ret_val_sew_3090; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vid_3073, &vid, FuncSignature::build()); - setArg(call_sew_3074, 0, reinterpret_cast(this)); - setRet(call_sew_3074, 0, ret_val_sew_3074); - setArg(call_vid_3073, 0, V); - setArg(call_vid_3073, 1, vid_3073_arg1); - setArg(call_vid_3073, 2, vid_3073_arg2); - setArg(call_vid_3073, 3, vid_3073_arg3); - setArg(call_vid_3073, 4, vm); - setArg(call_vid_3073, 5, vd); - setArg(call_vid_3073, 6, vid_3073_arg6); - auto tmp3075 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3075, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3075, 32, false) - , traits::vstart); + cc.invoke(&call_vid_3089, &vid, FuncSignature::build()); + setArg(call_sew_3090, 0, reinterpret_cast(this)); + setRet(call_sew_3090, 0, ret_val_sew_3090); + setArg(call_vid_3089, 0, V); + setArg(call_vid_3089, 1, vid_3089_arg1); + setArg(call_vid_3089, 2, vid_3089_arg2); + setArg(call_vid_3089, 3, vid_3089_arg3); + setArg(call_vid_3089, 4, vm); + setArg(call_vid_3089, 5, vd); + setArg(call_vid_3089, 6, vid_3089_arg6); + auto tmp3091 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3091, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3091, traits::vstart); } cc.bind(label_merge); } @@ -72504,14 +72134,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3076; - x86::Gp ret_val_illegal_vd_unmasked_3076 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3076, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto tmp3077 = get_reg(cc, 8, false); - mov(cc, tmp3077, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp3077, ret_val_illegal_vd_unmasked_3076); - setArg(call_illegal_vd_unmasked_3076, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3076, 0, ret_val_illegal_vd_unmasked_3076); + InvokeNode* call_illegal_vd_unmasked_3092; + x86::Gp ret_val_illegal_vd_unmasked_3092 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3092, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3093 = get_reg(cc, 8, false); + mov(cc, tmp3093, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3093, ret_val_illegal_vd_unmasked_3092); + setArg(call_illegal_vd_unmasked_3092, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3092, 0, ret_val_illegal_vd_unmasked_3092); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72527,32 +72157,30 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3079; - x86::Gp ret_val_sew_3079 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3079, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_scalar_to_vector_3078; - auto scalar_to_vector_3078_arg1 = load_reg_from_mem(jh, traits::vtype); - auto scalar_to_vector_3078_arg3 = gen_ext(cc, + InvokeNode* call_sew_3095; + x86::Gp ret_val_sew_3095 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3095, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_to_vector_3094; + auto scalar_to_vector_3094_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_to_vector_3094_arg3 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false), 32, true); - auto scalar_to_vector_3078_arg4 = ret_val_sew_3079; + auto scalar_to_vector_3094_arg4 = ret_val_sew_3095; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_scalar_to_vector_3078, &scalar_to_vector, FuncSignature::build()); - setArg(call_sew_3079, 0, reinterpret_cast(this)); - setRet(call_sew_3079, 0, ret_val_sew_3079); - setArg(call_scalar_to_vector_3078, 0, V); - setArg(call_scalar_to_vector_3078, 1, scalar_to_vector_3078_arg1); - setArg(call_scalar_to_vector_3078, 2, vd); - setArg(call_scalar_to_vector_3078, 3, scalar_to_vector_3078_arg3); - setArg(call_scalar_to_vector_3078, 4, scalar_to_vector_3078_arg4); + cc.invoke(&call_scalar_to_vector_3094, &scalar_to_vector, FuncSignature::build()); + setArg(call_sew_3095, 0, reinterpret_cast(this)); + setRet(call_sew_3095, 0, ret_val_sew_3095); + setArg(call_scalar_to_vector_3094, 0, V); + setArg(call_scalar_to_vector_3094, 1, scalar_to_vector_3094_arg1); + setArg(call_scalar_to_vector_3094, 2, vd); + setArg(call_scalar_to_vector_3094, 3, scalar_to_vector_3094_arg3); + setArg(call_scalar_to_vector_3094, 4, scalar_to_vector_3094_arg4); } cc.bind(label_merge); } - auto tmp3080 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3080, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3080, 32, false) - , traits::vstart); + auto tmp3096 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3096, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3096, traits::vstart); } cc.bind(label_merge); } @@ -72596,14 +72224,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3081; - x86::Gp ret_val_illegal_vd_unmasked_3081 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3081, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto tmp3082 = get_reg(cc, 8, false); - mov(cc, tmp3082, rd>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp3082, ret_val_illegal_vd_unmasked_3081); - setArg(call_illegal_vd_unmasked_3081, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3081, 0, ret_val_illegal_vd_unmasked_3081); + InvokeNode* call_illegal_vd_unmasked_3097; + x86::Gp ret_val_illegal_vd_unmasked_3097 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3097, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3098 = get_reg(cc, 8, false); + mov(cc, tmp3098, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3098, ret_val_illegal_vd_unmasked_3097); + setArg(call_illegal_vd_unmasked_3097, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3097, 0, ret_val_illegal_vd_unmasked_3097); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72614,30 +72242,28 @@ template class vm_impl : public iss::asmjit::vm_base { cc.bind(label_else); { if(rd!=0){ - InvokeNode* call_sew_3084; - x86::Gp ret_val_sew_3084 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3084, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_scalar_from_vector_3083; - auto scalar_from_vector_3083_arg1 = load_reg_from_mem(jh, traits::vtype); - auto scalar_from_vector_3083_arg3 = ret_val_sew_3084; + InvokeNode* call_sew_3100; + x86::Gp ret_val_sew_3100 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3100, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_from_vector_3099; + auto scalar_from_vector_3099_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_from_vector_3099_arg3 = ret_val_sew_3100; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_scalar_from_vector_3083 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_scalar_from_vector_3083, &scalar_from_vector, FuncSignature::build()); + x86::Gp ret_val_scalar_from_vector_3099 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_scalar_from_vector_3099, &scalar_from_vector, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::X0+ rd), - ret_val_scalar_from_vector_3083); - setArg(call_sew_3084, 0, reinterpret_cast(this)); - setRet(call_sew_3084, 0, ret_val_sew_3084); - setArg(call_scalar_from_vector_3083, 0, V); - setArg(call_scalar_from_vector_3083, 1, scalar_from_vector_3083_arg1); - setArg(call_scalar_from_vector_3083, 2, vs2); - setArg(call_scalar_from_vector_3083, 3, scalar_from_vector_3083_arg3); - setRet(call_scalar_from_vector_3083, 0, ret_val_scalar_from_vector_3083); - } - auto tmp3085 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3085, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3085, 32, false) - , traits::vstart); + ret_val_scalar_from_vector_3099); + setArg(call_sew_3100, 0, reinterpret_cast(this)); + setRet(call_sew_3100, 0, ret_val_sew_3100); + setArg(call_scalar_from_vector_3099, 0, V); + setArg(call_scalar_from_vector_3099, 1, scalar_from_vector_3099_arg1); + setArg(call_scalar_from_vector_3099, 2, vs2); + setArg(call_scalar_from_vector_3099, 3, scalar_from_vector_3099_arg3); + setRet(call_scalar_from_vector_3099, 0, ret_val_scalar_from_vector_3099); + } + auto tmp3101 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3101, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3101, traits::vstart); } cc.bind(label_merge); } @@ -72683,14 +72309,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3086; - x86::Gp ret_val_illegal_normal_3086 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3086, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3086, vs2==vd); - setArg(call_illegal_normal_3086, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3086, 1, vd); - setArg(call_illegal_normal_3086, 2, vm); - setRet(call_illegal_normal_3086, 0, ret_val_illegal_normal_3086); + InvokeNode* call_illegal_normal_3102; + x86::Gp ret_val_illegal_normal_3102 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3102, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3102, vs2==vd); + setArg(call_illegal_normal_3102, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3102, 1, vd); + setArg(call_illegal_normal_3102, 2, vm); + setRet(call_illegal_normal_3102, 0, ret_val_illegal_normal_3102); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72706,35 +72332,33 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3088; - x86::Gp ret_val_sew_3088 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3088, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slideup_3087; - auto vector_slideup_3087_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slideup_3087_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slideup_3087_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slideup_3087_arg8 = ret_val_sew_3088; + InvokeNode* call_sew_3104; + x86::Gp ret_val_sew_3104 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3104, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slideup_3103; + auto vector_slideup_3103_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slideup_3103_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slideup_3103_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slideup_3103_arg8 = ret_val_sew_3104; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slideup_3087, &vector_slideup, FuncSignature::build()); - setArg(call_sew_3088, 0, reinterpret_cast(this)); - setRet(call_sew_3088, 0, ret_val_sew_3088); - setArg(call_vector_slideup_3087, 0, V); - setArg(call_vector_slideup_3087, 1, vector_slideup_3087_arg1); - setArg(call_vector_slideup_3087, 2, vector_slideup_3087_arg2); - setArg(call_vector_slideup_3087, 3, vector_slideup_3087_arg3); - setArg(call_vector_slideup_3087, 4, vm); - setArg(call_vector_slideup_3087, 5, vd); - setArg(call_vector_slideup_3087, 6, vs2); - setArg(call_vector_slideup_3087, 7, (uint32_t)simm); - setArg(call_vector_slideup_3087, 8, vector_slideup_3087_arg8); + cc.invoke(&call_vector_slideup_3103, &vector_slideup, FuncSignature::build()); + setArg(call_sew_3104, 0, reinterpret_cast(this)); + setRet(call_sew_3104, 0, ret_val_sew_3104); + setArg(call_vector_slideup_3103, 0, V); + setArg(call_vector_slideup_3103, 1, vector_slideup_3103_arg1); + setArg(call_vector_slideup_3103, 2, vector_slideup_3103_arg2); + setArg(call_vector_slideup_3103, 3, vector_slideup_3103_arg3); + setArg(call_vector_slideup_3103, 4, vm); + setArg(call_vector_slideup_3103, 5, vd); + setArg(call_vector_slideup_3103, 6, vs2); + setArg(call_vector_slideup_3103, 7, (uint32_t)simm); + setArg(call_vector_slideup_3103, 8, vector_slideup_3103_arg8); } cc.bind(label_merge); } - auto tmp3089 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3089, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3089, 32, false) - , traits::vstart); + auto tmp3105 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3105, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3105, traits::vstart); } cc.bind(label_merge); } @@ -72780,16 +72404,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3090; - x86::Gp ret_val_illegal_normal_3090 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3090, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp3091 = get_reg(cc, 8, false); - mov(cc, tmp3091, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3091, ret_val_illegal_normal_3090), vs2==vd); - setArg(call_illegal_normal_3090, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3090, 1, vd); - setArg(call_illegal_normal_3090, 2, vm); - setRet(call_illegal_normal_3090, 0, ret_val_illegal_normal_3090); + InvokeNode* call_illegal_normal_3106; + x86::Gp ret_val_illegal_normal_3106 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3106, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3107 = get_reg(cc, 8, false); + mov(cc, tmp3107, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3107, ret_val_illegal_normal_3106), vs2==vd); + setArg(call_illegal_normal_3106, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3106, 1, vd); + setArg(call_illegal_normal_3106, 2, vm); + setRet(call_illegal_normal_3106, 0, ret_val_illegal_normal_3106); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72805,36 +72429,34 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3093; - x86::Gp ret_val_sew_3093 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3093, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slideup_3092; - auto vector_slideup_3092_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slideup_3092_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slideup_3092_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slideup_3092_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); - auto vector_slideup_3092_arg8 = ret_val_sew_3093; + InvokeNode* call_sew_3109; + x86::Gp ret_val_sew_3109 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3109, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slideup_3108; + auto vector_slideup_3108_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slideup_3108_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slideup_3108_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slideup_3108_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_slideup_3108_arg8 = ret_val_sew_3109; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slideup_3092, &vector_slideup, FuncSignature::build()); - setArg(call_sew_3093, 0, reinterpret_cast(this)); - setRet(call_sew_3093, 0, ret_val_sew_3093); - setArg(call_vector_slideup_3092, 0, V); - setArg(call_vector_slideup_3092, 1, vector_slideup_3092_arg1); - setArg(call_vector_slideup_3092, 2, vector_slideup_3092_arg2); - setArg(call_vector_slideup_3092, 3, vector_slideup_3092_arg3); - setArg(call_vector_slideup_3092, 4, vm); - setArg(call_vector_slideup_3092, 5, vd); - setArg(call_vector_slideup_3092, 6, vs2); - setArg(call_vector_slideup_3092, 7, vector_slideup_3092_arg7); - setArg(call_vector_slideup_3092, 8, vector_slideup_3092_arg8); + cc.invoke(&call_vector_slideup_3108, &vector_slideup, FuncSignature::build()); + setArg(call_sew_3109, 0, reinterpret_cast(this)); + setRet(call_sew_3109, 0, ret_val_sew_3109); + setArg(call_vector_slideup_3108, 0, V); + setArg(call_vector_slideup_3108, 1, vector_slideup_3108_arg1); + setArg(call_vector_slideup_3108, 2, vector_slideup_3108_arg2); + setArg(call_vector_slideup_3108, 3, vector_slideup_3108_arg3); + setArg(call_vector_slideup_3108, 4, vm); + setArg(call_vector_slideup_3108, 5, vd); + setArg(call_vector_slideup_3108, 6, vs2); + setArg(call_vector_slideup_3108, 7, vector_slideup_3108_arg7); + setArg(call_vector_slideup_3108, 8, vector_slideup_3108_arg8); } cc.bind(label_merge); } - auto tmp3094 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3094, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3094, 32, false) - , traits::vstart); + auto tmp3110 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3110, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3110, traits::vstart); } cc.bind(label_merge); } @@ -72880,14 +72502,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3095; - x86::Gp ret_val_illegal_normal_3095 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3095, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_3095; - setArg(call_illegal_normal_3095, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3095, 1, vd); - setArg(call_illegal_normal_3095, 2, vm); - setRet(call_illegal_normal_3095, 0, ret_val_illegal_normal_3095); + InvokeNode* call_illegal_normal_3111; + x86::Gp ret_val_illegal_normal_3111 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3111, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_3111; + setArg(call_illegal_normal_3111, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3111, 1, vd); + setArg(call_illegal_normal_3111, 2, vm); + setRet(call_illegal_normal_3111, 0, ret_val_illegal_normal_3111); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72903,35 +72525,33 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3097; - x86::Gp ret_val_sew_3097 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3097, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slidedown_3096; - auto vector_slidedown_3096_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slidedown_3096_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slidedown_3096_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slidedown_3096_arg8 = ret_val_sew_3097; + InvokeNode* call_sew_3113; + x86::Gp ret_val_sew_3113 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3113, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slidedown_3112; + auto vector_slidedown_3112_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slidedown_3112_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slidedown_3112_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slidedown_3112_arg8 = ret_val_sew_3113; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slidedown_3096, &vector_slidedown, FuncSignature::build()); - setArg(call_sew_3097, 0, reinterpret_cast(this)); - setRet(call_sew_3097, 0, ret_val_sew_3097); - setArg(call_vector_slidedown_3096, 0, V); - setArg(call_vector_slidedown_3096, 1, vector_slidedown_3096_arg1); - setArg(call_vector_slidedown_3096, 2, vector_slidedown_3096_arg2); - setArg(call_vector_slidedown_3096, 3, vector_slidedown_3096_arg3); - setArg(call_vector_slidedown_3096, 4, vm); - setArg(call_vector_slidedown_3096, 5, vd); - setArg(call_vector_slidedown_3096, 6, vs2); - setArg(call_vector_slidedown_3096, 7, (uint32_t)simm); - setArg(call_vector_slidedown_3096, 8, vector_slidedown_3096_arg8); + cc.invoke(&call_vector_slidedown_3112, &vector_slidedown, FuncSignature::build()); + setArg(call_sew_3113, 0, reinterpret_cast(this)); + setRet(call_sew_3113, 0, ret_val_sew_3113); + setArg(call_vector_slidedown_3112, 0, V); + setArg(call_vector_slidedown_3112, 1, vector_slidedown_3112_arg1); + setArg(call_vector_slidedown_3112, 2, vector_slidedown_3112_arg2); + setArg(call_vector_slidedown_3112, 3, vector_slidedown_3112_arg3); + setArg(call_vector_slidedown_3112, 4, vm); + setArg(call_vector_slidedown_3112, 5, vd); + setArg(call_vector_slidedown_3112, 6, vs2); + setArg(call_vector_slidedown_3112, 7, (uint32_t)simm); + setArg(call_vector_slidedown_3112, 8, vector_slidedown_3112_arg8); } cc.bind(label_merge); } - auto tmp3098 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3098, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3098, 32, false) - , traits::vstart); + auto tmp3114 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3114, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3114, traits::vstart); } cc.bind(label_merge); } @@ -72977,16 +72597,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3099; - x86::Gp ret_val_illegal_normal_3099 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3099, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp3100 = get_reg(cc, 8, false); - mov(cc, tmp3100, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp3100, ret_val_illegal_normal_3099); - setArg(call_illegal_normal_3099, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3099, 1, vd); - setArg(call_illegal_normal_3099, 2, vm); - setRet(call_illegal_normal_3099, 0, ret_val_illegal_normal_3099); + InvokeNode* call_illegal_normal_3115; + x86::Gp ret_val_illegal_normal_3115 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3115, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3116 = get_reg(cc, 8, false); + mov(cc, tmp3116, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3116, ret_val_illegal_normal_3115); + setArg(call_illegal_normal_3115, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3115, 1, vd); + setArg(call_illegal_normal_3115, 2, vm); + setRet(call_illegal_normal_3115, 0, ret_val_illegal_normal_3115); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73002,36 +72622,34 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3102; - x86::Gp ret_val_sew_3102 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3102, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slidedown_3101; - auto vector_slidedown_3101_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slidedown_3101_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slidedown_3101_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slidedown_3101_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); - auto vector_slidedown_3101_arg8 = ret_val_sew_3102; + InvokeNode* call_sew_3118; + x86::Gp ret_val_sew_3118 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3118, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slidedown_3117; + auto vector_slidedown_3117_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slidedown_3117_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slidedown_3117_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slidedown_3117_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_slidedown_3117_arg8 = ret_val_sew_3118; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slidedown_3101, &vector_slidedown, FuncSignature::build()); - setArg(call_sew_3102, 0, reinterpret_cast(this)); - setRet(call_sew_3102, 0, ret_val_sew_3102); - setArg(call_vector_slidedown_3101, 0, V); - setArg(call_vector_slidedown_3101, 1, vector_slidedown_3101_arg1); - setArg(call_vector_slidedown_3101, 2, vector_slidedown_3101_arg2); - setArg(call_vector_slidedown_3101, 3, vector_slidedown_3101_arg3); - setArg(call_vector_slidedown_3101, 4, vm); - setArg(call_vector_slidedown_3101, 5, vd); - setArg(call_vector_slidedown_3101, 6, vs2); - setArg(call_vector_slidedown_3101, 7, vector_slidedown_3101_arg7); - setArg(call_vector_slidedown_3101, 8, vector_slidedown_3101_arg8); + cc.invoke(&call_vector_slidedown_3117, &vector_slidedown, FuncSignature::build()); + setArg(call_sew_3118, 0, reinterpret_cast(this)); + setRet(call_sew_3118, 0, ret_val_sew_3118); + setArg(call_vector_slidedown_3117, 0, V); + setArg(call_vector_slidedown_3117, 1, vector_slidedown_3117_arg1); + setArg(call_vector_slidedown_3117, 2, vector_slidedown_3117_arg2); + setArg(call_vector_slidedown_3117, 3, vector_slidedown_3117_arg3); + setArg(call_vector_slidedown_3117, 4, vm); + setArg(call_vector_slidedown_3117, 5, vd); + setArg(call_vector_slidedown_3117, 6, vs2); + setArg(call_vector_slidedown_3117, 7, vector_slidedown_3117_arg7); + setArg(call_vector_slidedown_3117, 8, vector_slidedown_3117_arg8); } cc.bind(label_merge); } - auto tmp3103 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3103, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3103, 32, false) - , traits::vstart); + auto tmp3119 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3119, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3119, traits::vstart); } cc.bind(label_merge); } @@ -73077,16 +72695,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3104; - x86::Gp ret_val_illegal_normal_3104 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3104, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp3105 = get_reg(cc, 8, false); - mov(cc, tmp3105, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3105, ret_val_illegal_normal_3104), vs2==vd); - setArg(call_illegal_normal_3104, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3104, 1, vd); - setArg(call_illegal_normal_3104, 2, vm); - setRet(call_illegal_normal_3104, 0, ret_val_illegal_normal_3104); + InvokeNode* call_illegal_normal_3120; + x86::Gp ret_val_illegal_normal_3120 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3120, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3121 = get_reg(cc, 8, false); + mov(cc, tmp3121, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3121, ret_val_illegal_normal_3120), vs2==vd); + setArg(call_illegal_normal_3120, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3120, 1, vd); + setArg(call_illegal_normal_3120, 2, vm); + setRet(call_illegal_normal_3120, 0, ret_val_illegal_normal_3120); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73102,37 +72720,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3107; - x86::Gp ret_val_sew_3107 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3107, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slide1up_3106; - auto vector_slide1up_3106_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slide1up_3106_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slide1up_3106_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slide1up_3106_arg7 = gen_ext(cc, + InvokeNode* call_sew_3123; + x86::Gp ret_val_sew_3123 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3123, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slide1up_3122; + auto vector_slide1up_3122_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slide1up_3122_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slide1up_3122_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slide1up_3122_arg7 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); - auto vector_slide1up_3106_arg8 = ret_val_sew_3107; + auto vector_slide1up_3122_arg8 = ret_val_sew_3123; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slide1up_3106, &vector_slide1up, FuncSignature::build()); - setArg(call_sew_3107, 0, reinterpret_cast(this)); - setRet(call_sew_3107, 0, ret_val_sew_3107); - setArg(call_vector_slide1up_3106, 0, V); - setArg(call_vector_slide1up_3106, 1, vector_slide1up_3106_arg1); - setArg(call_vector_slide1up_3106, 2, vector_slide1up_3106_arg2); - setArg(call_vector_slide1up_3106, 3, vector_slide1up_3106_arg3); - setArg(call_vector_slide1up_3106, 4, vm); - setArg(call_vector_slide1up_3106, 5, vd); - setArg(call_vector_slide1up_3106, 6, vs2); - setArg(call_vector_slide1up_3106, 7, vector_slide1up_3106_arg7); - setArg(call_vector_slide1up_3106, 8, vector_slide1up_3106_arg8); + cc.invoke(&call_vector_slide1up_3122, &vector_slide1up, FuncSignature::build()); + setArg(call_sew_3123, 0, reinterpret_cast(this)); + setRet(call_sew_3123, 0, ret_val_sew_3123); + setArg(call_vector_slide1up_3122, 0, V); + setArg(call_vector_slide1up_3122, 1, vector_slide1up_3122_arg1); + setArg(call_vector_slide1up_3122, 2, vector_slide1up_3122_arg2); + setArg(call_vector_slide1up_3122, 3, vector_slide1up_3122_arg3); + setArg(call_vector_slide1up_3122, 4, vm); + setArg(call_vector_slide1up_3122, 5, vd); + setArg(call_vector_slide1up_3122, 6, vs2); + setArg(call_vector_slide1up_3122, 7, vector_slide1up_3122_arg7); + setArg(call_vector_slide1up_3122, 8, vector_slide1up_3122_arg8); } cc.bind(label_merge); } - auto tmp3108 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3108, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3108, 32, false) - , traits::vstart); + auto tmp3124 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3124, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3124, traits::vstart); } cc.bind(label_merge); } @@ -73178,16 +72794,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3109; - x86::Gp ret_val_illegal_normal_3109 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3109, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp3110 = get_reg(cc, 8, false); - mov(cc, tmp3110, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp3110, ret_val_illegal_normal_3109); - setArg(call_illegal_normal_3109, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3109, 1, vd); - setArg(call_illegal_normal_3109, 2, vm); - setRet(call_illegal_normal_3109, 0, ret_val_illegal_normal_3109); + InvokeNode* call_illegal_normal_3125; + x86::Gp ret_val_illegal_normal_3125 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3125, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3126 = get_reg(cc, 8, false); + mov(cc, tmp3126, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3126, ret_val_illegal_normal_3125); + setArg(call_illegal_normal_3125, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3125, 1, vd); + setArg(call_illegal_normal_3125, 2, vm); + setRet(call_illegal_normal_3125, 0, ret_val_illegal_normal_3125); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73203,37 +72819,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3112; - x86::Gp ret_val_sew_3112 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3112, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slide1down_3111; - auto vector_slide1down_3111_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slide1down_3111_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slide1down_3111_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slide1down_3111_arg7 = gen_ext(cc, + InvokeNode* call_sew_3128; + x86::Gp ret_val_sew_3128 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3128, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slide1down_3127; + auto vector_slide1down_3127_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slide1down_3127_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slide1down_3127_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slide1down_3127_arg7 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 32, false); - auto vector_slide1down_3111_arg8 = ret_val_sew_3112; + auto vector_slide1down_3127_arg8 = ret_val_sew_3128; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slide1down_3111, &vector_slide1down, FuncSignature::build()); - setArg(call_sew_3112, 0, reinterpret_cast(this)); - setRet(call_sew_3112, 0, ret_val_sew_3112); - setArg(call_vector_slide1down_3111, 0, V); - setArg(call_vector_slide1down_3111, 1, vector_slide1down_3111_arg1); - setArg(call_vector_slide1down_3111, 2, vector_slide1down_3111_arg2); - setArg(call_vector_slide1down_3111, 3, vector_slide1down_3111_arg3); - setArg(call_vector_slide1down_3111, 4, vm); - setArg(call_vector_slide1down_3111, 5, vd); - setArg(call_vector_slide1down_3111, 6, vs2); - setArg(call_vector_slide1down_3111, 7, vector_slide1down_3111_arg7); - setArg(call_vector_slide1down_3111, 8, vector_slide1down_3111_arg8); + cc.invoke(&call_vector_slide1down_3127, &vector_slide1down, FuncSignature::build()); + setArg(call_sew_3128, 0, reinterpret_cast(this)); + setRet(call_sew_3128, 0, ret_val_sew_3128); + setArg(call_vector_slide1down_3127, 0, V); + setArg(call_vector_slide1down_3127, 1, vector_slide1down_3127_arg1); + setArg(call_vector_slide1down_3127, 2, vector_slide1down_3127_arg2); + setArg(call_vector_slide1down_3127, 3, vector_slide1down_3127_arg3); + setArg(call_vector_slide1down_3127, 4, vm); + setArg(call_vector_slide1down_3127, 5, vd); + setArg(call_vector_slide1down_3127, 6, vs2); + setArg(call_vector_slide1down_3127, 7, vector_slide1down_3127_arg7); + setArg(call_vector_slide1down_3127, 8, vector_slide1down_3127_arg8); } cc.bind(label_merge); } - auto tmp3113 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3113, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3113, 32, false) - , traits::vstart); + auto tmp3129 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3129, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3129, traits::vstart); } cc.bind(label_merge); } @@ -73279,14 +72893,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3114; - x86::Gp ret_val_illegal_normal_3114 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3114, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3114, vs2==vd); - setArg(call_illegal_normal_3114, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3114, 1, vd); - setArg(call_illegal_normal_3114, 2, vm); - setRet(call_illegal_normal_3114, 0, ret_val_illegal_normal_3114); + InvokeNode* call_illegal_normal_3130; + x86::Gp ret_val_illegal_normal_3130 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3130, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3130, vs2==vd); + setArg(call_illegal_normal_3130, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3130, 1, vd); + setArg(call_illegal_normal_3130, 2, vm); + setRet(call_illegal_normal_3130, 0, ret_val_illegal_normal_3130); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73296,32 +72910,30 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3116; - x86::Gp ret_val_sew_3116 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3116, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_imm_gather_3115; - auto vector_imm_gather_3115_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_imm_gather_3115_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_imm_gather_3115_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_imm_gather_3115_arg8 = ret_val_sew_3116; + InvokeNode* call_sew_3132; + x86::Gp ret_val_sew_3132 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3132, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_gather_3131; + auto vector_imm_gather_3131_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_gather_3131_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_gather_3131_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_gather_3131_arg8 = ret_val_sew_3132; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_gather_3115, &vector_imm_gather, FuncSignature::build()); - setArg(call_sew_3116, 0, reinterpret_cast(this)); - setRet(call_sew_3116, 0, ret_val_sew_3116); - setArg(call_vector_imm_gather_3115, 0, V); - setArg(call_vector_imm_gather_3115, 1, vector_imm_gather_3115_arg1); - setArg(call_vector_imm_gather_3115, 2, vector_imm_gather_3115_arg2); - setArg(call_vector_imm_gather_3115, 3, vector_imm_gather_3115_arg3); - setArg(call_vector_imm_gather_3115, 4, vm); - setArg(call_vector_imm_gather_3115, 5, vd); - setArg(call_vector_imm_gather_3115, 6, vs2); - setArg(call_vector_imm_gather_3115, 7, (uint32_t)simm); - setArg(call_vector_imm_gather_3115, 8, vector_imm_gather_3115_arg8); - auto tmp3117 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3117, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3117, 32, false) - , traits::vstart); + cc.invoke(&call_vector_imm_gather_3131, &vector_imm_gather, FuncSignature::build()); + setArg(call_sew_3132, 0, reinterpret_cast(this)); + setRet(call_sew_3132, 0, ret_val_sew_3132); + setArg(call_vector_imm_gather_3131, 0, V); + setArg(call_vector_imm_gather_3131, 1, vector_imm_gather_3131_arg1); + setArg(call_vector_imm_gather_3131, 2, vector_imm_gather_3131_arg2); + setArg(call_vector_imm_gather_3131, 3, vector_imm_gather_3131_arg3); + setArg(call_vector_imm_gather_3131, 4, vm); + setArg(call_vector_imm_gather_3131, 5, vd); + setArg(call_vector_imm_gather_3131, 6, vs2); + setArg(call_vector_imm_gather_3131, 7, (uint32_t)simm); + setArg(call_vector_imm_gather_3131, 8, vector_imm_gather_3131_arg8); + auto tmp3133 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3133, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3133, traits::vstart); } cc.bind(label_merge); } @@ -73367,14 +72979,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3118; - x86::Gp ret_val_illegal_normal_3118 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3118, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3118, vs1==vd), vs2==vd); - setArg(call_illegal_normal_3118, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3118, 1, vd); - setArg(call_illegal_normal_3118, 2, vm); - setRet(call_illegal_normal_3118, 0, ret_val_illegal_normal_3118); + InvokeNode* call_illegal_normal_3134; + x86::Gp ret_val_illegal_normal_3134 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3134, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3134, vs1==vd), vs2==vd); + setArg(call_illegal_normal_3134, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3134, 1, vd); + setArg(call_illegal_normal_3134, 2, vm); + setRet(call_illegal_normal_3134, 0, ret_val_illegal_normal_3134); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73384,32 +72996,30 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3120; - x86::Gp ret_val_sew_3120 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3120, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_vector_gather_3119; - auto vector_vector_gather_3119_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_vector_gather_3119_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_vector_gather_3119_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_vector_gather_3119_arg8 = ret_val_sew_3120; + InvokeNode* call_sew_3136; + x86::Gp ret_val_sew_3136 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3136, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_gather_3135; + auto vector_vector_gather_3135_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_gather_3135_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_gather_3135_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_gather_3135_arg8 = ret_val_sew_3136; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_gather_3119, &vector_vector_gather, FuncSignature::build()); - setArg(call_sew_3120, 0, reinterpret_cast(this)); - setRet(call_sew_3120, 0, ret_val_sew_3120); - setArg(call_vector_vector_gather_3119, 0, V); - setArg(call_vector_vector_gather_3119, 1, vector_vector_gather_3119_arg1); - setArg(call_vector_vector_gather_3119, 2, vector_vector_gather_3119_arg2); - setArg(call_vector_vector_gather_3119, 3, vector_vector_gather_3119_arg3); - setArg(call_vector_vector_gather_3119, 4, vm); - setArg(call_vector_vector_gather_3119, 5, vd); - setArg(call_vector_vector_gather_3119, 6, vs2); - setArg(call_vector_vector_gather_3119, 7, vs1); - setArg(call_vector_vector_gather_3119, 8, vector_vector_gather_3119_arg8); - auto tmp3121 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3121, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3121, 32, false) - , traits::vstart); + cc.invoke(&call_vector_vector_gather_3135, &vector_vector_gather, FuncSignature::build()); + setArg(call_sew_3136, 0, reinterpret_cast(this)); + setRet(call_sew_3136, 0, ret_val_sew_3136); + setArg(call_vector_vector_gather_3135, 0, V); + setArg(call_vector_vector_gather_3135, 1, vector_vector_gather_3135_arg1); + setArg(call_vector_vector_gather_3135, 2, vector_vector_gather_3135_arg2); + setArg(call_vector_vector_gather_3135, 3, vector_vector_gather_3135_arg3); + setArg(call_vector_vector_gather_3135, 4, vm); + setArg(call_vector_vector_gather_3135, 5, vd); + setArg(call_vector_vector_gather_3135, 6, vs2); + setArg(call_vector_vector_gather_3135, 7, vs1); + setArg(call_vector_vector_gather_3135, 8, vector_vector_gather_3135_arg8); + auto tmp3137 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3137, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3137, traits::vstart); } cc.bind(label_merge); } @@ -73455,16 +73065,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3122; - x86::Gp ret_val_illegal_normal_3122 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3122, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp3123 = get_reg(cc, 8, false); - mov(cc, tmp3123, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3123, ret_val_illegal_normal_3122), vs2==vd); - setArg(call_illegal_normal_3122, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3122, 1, vd); - setArg(call_illegal_normal_3122, 2, vm); - setRet(call_illegal_normal_3122, 0, ret_val_illegal_normal_3122); + InvokeNode* call_illegal_normal_3138; + x86::Gp ret_val_illegal_normal_3138 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3138, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3139 = get_reg(cc, 8, false); + mov(cc, tmp3139, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3139, ret_val_illegal_normal_3138), vs2==vd); + setArg(call_illegal_normal_3138, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3138, 1, vd); + setArg(call_illegal_normal_3138, 2, vm); + setRet(call_illegal_normal_3138, 0, ret_val_illegal_normal_3138); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73474,33 +73084,31 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3125; - x86::Gp ret_val_sew_3125 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3125, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_imm_gather_3124; - auto vector_imm_gather_3124_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_imm_gather_3124_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_imm_gather_3124_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_imm_gather_3124_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); - auto vector_imm_gather_3124_arg8 = ret_val_sew_3125; + InvokeNode* call_sew_3141; + x86::Gp ret_val_sew_3141 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3141, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_gather_3140; + auto vector_imm_gather_3140_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_gather_3140_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_gather_3140_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_gather_3140_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_imm_gather_3140_arg8 = ret_val_sew_3141; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_gather_3124, &vector_imm_gather, FuncSignature::build()); - setArg(call_sew_3125, 0, reinterpret_cast(this)); - setRet(call_sew_3125, 0, ret_val_sew_3125); - setArg(call_vector_imm_gather_3124, 0, V); - setArg(call_vector_imm_gather_3124, 1, vector_imm_gather_3124_arg1); - setArg(call_vector_imm_gather_3124, 2, vector_imm_gather_3124_arg2); - setArg(call_vector_imm_gather_3124, 3, vector_imm_gather_3124_arg3); - setArg(call_vector_imm_gather_3124, 4, vm); - setArg(call_vector_imm_gather_3124, 5, vd); - setArg(call_vector_imm_gather_3124, 6, vs2); - setArg(call_vector_imm_gather_3124, 7, vector_imm_gather_3124_arg7); - setArg(call_vector_imm_gather_3124, 8, vector_imm_gather_3124_arg8); - auto tmp3126 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3126, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3126, 32, false) - , traits::vstart); + cc.invoke(&call_vector_imm_gather_3140, &vector_imm_gather, FuncSignature::build()); + setArg(call_sew_3141, 0, reinterpret_cast(this)); + setRet(call_sew_3141, 0, ret_val_sew_3141); + setArg(call_vector_imm_gather_3140, 0, V); + setArg(call_vector_imm_gather_3140, 1, vector_imm_gather_3140_arg1); + setArg(call_vector_imm_gather_3140, 2, vector_imm_gather_3140_arg2); + setArg(call_vector_imm_gather_3140, 3, vector_imm_gather_3140_arg3); + setArg(call_vector_imm_gather_3140, 4, vm); + setArg(call_vector_imm_gather_3140, 5, vd); + setArg(call_vector_imm_gather_3140, 6, vs2); + setArg(call_vector_imm_gather_3140, 7, vector_imm_gather_3140_arg7); + setArg(call_vector_imm_gather_3140, 8, vector_imm_gather_3140_arg8); + auto tmp3142 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3142, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3142, traits::vstart); } cc.bind(label_merge); } @@ -73546,14 +73154,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3127; - x86::Gp ret_val_illegal_normal_3127 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3127, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3127, vs1==vd), vs2==vd); - setArg(call_illegal_normal_3127, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3127, 1, vd); - setArg(call_illegal_normal_3127, 2, vm); - setRet(call_illegal_normal_3127, 0, ret_val_illegal_normal_3127); + InvokeNode* call_illegal_normal_3143; + x86::Gp ret_val_illegal_normal_3143 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3143, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3143, vs1==vd), vs2==vd); + setArg(call_illegal_normal_3143, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3143, 1, vd); + setArg(call_illegal_normal_3143, 2, vm); + setRet(call_illegal_normal_3143, 0, ret_val_illegal_normal_3143); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73563,32 +73171,30 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3129; - x86::Gp ret_val_sew_3129 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3129, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_vector_gatherei16_3128; - auto vector_vector_gatherei16_3128_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_vector_gatherei16_3128_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_vector_gatherei16_3128_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_vector_gatherei16_3128_arg8 = ret_val_sew_3129; + InvokeNode* call_sew_3145; + x86::Gp ret_val_sew_3145 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3145, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_gatherei16_3144; + auto vector_vector_gatherei16_3144_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_gatherei16_3144_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_gatherei16_3144_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_gatherei16_3144_arg8 = ret_val_sew_3145; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_gatherei16_3128, &vector_vector_gatherei16, FuncSignature::build()); - setArg(call_sew_3129, 0, reinterpret_cast(this)); - setRet(call_sew_3129, 0, ret_val_sew_3129); - setArg(call_vector_vector_gatherei16_3128, 0, V); - setArg(call_vector_vector_gatherei16_3128, 1, vector_vector_gatherei16_3128_arg1); - setArg(call_vector_vector_gatherei16_3128, 2, vector_vector_gatherei16_3128_arg2); - setArg(call_vector_vector_gatherei16_3128, 3, vector_vector_gatherei16_3128_arg3); - setArg(call_vector_vector_gatherei16_3128, 4, vm); - setArg(call_vector_vector_gatherei16_3128, 5, vd); - setArg(call_vector_vector_gatherei16_3128, 6, vs2); - setArg(call_vector_vector_gatherei16_3128, 7, vs1); - setArg(call_vector_vector_gatherei16_3128, 8, vector_vector_gatherei16_3128_arg8); - auto tmp3130 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3130, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3130, 32, false) - , traits::vstart); + cc.invoke(&call_vector_vector_gatherei16_3144, &vector_vector_gatherei16, FuncSignature::build()); + setArg(call_sew_3145, 0, reinterpret_cast(this)); + setRet(call_sew_3145, 0, ret_val_sew_3145); + setArg(call_vector_vector_gatherei16_3144, 0, V); + setArg(call_vector_vector_gatherei16_3144, 1, vector_vector_gatherei16_3144_arg1); + setArg(call_vector_vector_gatherei16_3144, 2, vector_vector_gatherei16_3144_arg2); + setArg(call_vector_vector_gatherei16_3144, 3, vector_vector_gatherei16_3144_arg3); + setArg(call_vector_vector_gatherei16_3144, 4, vm); + setArg(call_vector_vector_gatherei16_3144, 5, vd); + setArg(call_vector_vector_gatherei16_3144, 6, vs2); + setArg(call_vector_vector_gatherei16_3144, 7, vs1); + setArg(call_vector_vector_gatherei16_3144, 8, vector_vector_gatherei16_3144_arg8); + auto tmp3146 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3146, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3146, traits::vstart); } cc.bind(label_merge); } @@ -73633,12 +73239,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3131; - x86::Gp ret_val_illegal_vd_unmasked_3131 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3131, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0), vs1==vd), vs2==vd), ret_val_illegal_vd_unmasked_3131); - setArg(call_illegal_vd_unmasked_3131, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3131, 0, ret_val_illegal_vd_unmasked_3131); + InvokeNode* call_illegal_vd_unmasked_3147; + x86::Gp ret_val_illegal_vd_unmasked_3147 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3147, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0), vs1==vd), vs2==vd), ret_val_illegal_vd_unmasked_3147); + setArg(call_illegal_vd_unmasked_3147, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3147, 0, ret_val_illegal_vd_unmasked_3147); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73654,34 +73260,32 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3133; - x86::Gp ret_val_sew_3133 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3133, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_compress_3132; - auto vector_compress_3132_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_compress_3132_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_compress_3132_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_compress_3132_arg7 = ret_val_sew_3133; + InvokeNode* call_sew_3149; + x86::Gp ret_val_sew_3149 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3149, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_compress_3148; + auto vector_compress_3148_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_compress_3148_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_compress_3148_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_compress_3148_arg7 = ret_val_sew_3149; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_compress_3132, &vector_compress, FuncSignature::build()); - setArg(call_sew_3133, 0, reinterpret_cast(this)); - setRet(call_sew_3133, 0, ret_val_sew_3133); - setArg(call_vector_compress_3132, 0, V); - setArg(call_vector_compress_3132, 1, vector_compress_3132_arg1); - setArg(call_vector_compress_3132, 2, vector_compress_3132_arg2); - setArg(call_vector_compress_3132, 3, vector_compress_3132_arg3); - setArg(call_vector_compress_3132, 4, vd); - setArg(call_vector_compress_3132, 5, vs2); - setArg(call_vector_compress_3132, 6, vs1); - setArg(call_vector_compress_3132, 7, vector_compress_3132_arg7); + cc.invoke(&call_vector_compress_3148, &vector_compress, FuncSignature::build()); + setArg(call_sew_3149, 0, reinterpret_cast(this)); + setRet(call_sew_3149, 0, ret_val_sew_3149); + setArg(call_vector_compress_3148, 0, V); + setArg(call_vector_compress_3148, 1, vector_compress_3148_arg1); + setArg(call_vector_compress_3148, 2, vector_compress_3148_arg2); + setArg(call_vector_compress_3148, 3, vector_compress_3148_arg3); + setArg(call_vector_compress_3148, 4, vd); + setArg(call_vector_compress_3148, 5, vs2); + setArg(call_vector_compress_3148, 6, vs1); + setArg(call_vector_compress_3148, 7, vector_compress_3148_arg7); } cc.bind(label_merge); } - auto tmp3134 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3134, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3134, 32, false) - , traits::vstart); + auto tmp3150 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3150, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3150, traits::vstart); } cc.bind(label_merge); } @@ -73723,13 +73327,13 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_vector_whole_move_3135; + InvokeNode* call_vector_whole_move_3151; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_whole_move_3135, &vector_whole_move, FuncSignature::build()); - setArg(call_vector_whole_move_3135, 0, V); - setArg(call_vector_whole_move_3135, 1, vd); - setArg(call_vector_whole_move_3135, 2, vs2); - setArg(call_vector_whole_move_3135, 3, 1); + cc.invoke(&call_vector_whole_move_3151, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3151, 0, V); + setArg(call_vector_whole_move_3151, 1, vd); + setArg(call_vector_whole_move_3151, 2, vs2); + setArg(call_vector_whole_move_3151, 3, 1); auto returnValue = CONT; gen_sync(jh, POST_SYNC, 688); @@ -73772,13 +73376,13 @@ template class vm_impl : public iss::asmjit::vm_base { gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else { - InvokeNode* call_vector_whole_move_3136; + InvokeNode* call_vector_whole_move_3152; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_whole_move_3136, &vector_whole_move, FuncSignature::build()); - setArg(call_vector_whole_move_3136, 0, V); - setArg(call_vector_whole_move_3136, 1, vd); - setArg(call_vector_whole_move_3136, 2, vs2); - setArg(call_vector_whole_move_3136, 3, 2); + cc.invoke(&call_vector_whole_move_3152, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3152, 0, V); + setArg(call_vector_whole_move_3152, 1, vd); + setArg(call_vector_whole_move_3152, 2, vs2); + setArg(call_vector_whole_move_3152, 3, 2); } auto returnValue = CONT; @@ -73822,13 +73426,13 @@ template class vm_impl : public iss::asmjit::vm_base { gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else { - InvokeNode* call_vector_whole_move_3137; + InvokeNode* call_vector_whole_move_3153; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_whole_move_3137, &vector_whole_move, FuncSignature::build()); - setArg(call_vector_whole_move_3137, 0, V); - setArg(call_vector_whole_move_3137, 1, vd); - setArg(call_vector_whole_move_3137, 2, vs2); - setArg(call_vector_whole_move_3137, 3, 4); + cc.invoke(&call_vector_whole_move_3153, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3153, 0, V); + setArg(call_vector_whole_move_3153, 1, vd); + setArg(call_vector_whole_move_3153, 2, vs2); + setArg(call_vector_whole_move_3153, 3, 4); } auto returnValue = CONT; @@ -73872,13 +73476,13 @@ template class vm_impl : public iss::asmjit::vm_base { gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else { - InvokeNode* call_vector_whole_move_3138; + InvokeNode* call_vector_whole_move_3154; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_whole_move_3138, &vector_whole_move, FuncSignature::build()); - setArg(call_vector_whole_move_3138, 0, V); - setArg(call_vector_whole_move_3138, 1, vd); - setArg(call_vector_whole_move_3138, 2, vs2); - setArg(call_vector_whole_move_3138, 3, 8); + cc.invoke(&call_vector_whole_move_3154, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3154, 0, V); + setArg(call_vector_whole_move_3154, 1, vd); + setArg(call_vector_whole_move_3154, 2, vs2); + setArg(call_vector_whole_move_3154, 3, 8); } auto returnValue = CONT; @@ -73918,28 +73522,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3139; - x86::Gp ret_val_get_sew_pow_3139 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3139, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3140 = get_reg(cc, 8, false); - mov(cc, tmp3140, 1); + InvokeNode* call_get_sew_pow_3155; + x86::Gp ret_val_get_sew_pow_3155 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3155, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3156 = get_reg(cc, 8, false); + mov(cc, tmp3156, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3140, (ret_val_get_sew_pow_3139))), 8, false), ~ 1); - setArg(call_get_sew_pow_3139, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3139, 0, ret_val_get_sew_pow_3139); + (gen_operation(cc, shl, tmp3156, (ret_val_get_sew_pow_3155))), 8, false), ~ 1); + setArg(call_get_sew_pow_3155, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3155, 0, ret_val_get_sew_pow_3155); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3141; - auto illegal_fp_vd_unmasked_3141_arg0 = SEW; - auto illegal_fp_vd_unmasked_3141_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3141 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3141, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3141; - setArg(call_illegal_fp_vd_unmasked_3141, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3141, 1, illegal_fp_vd_unmasked_3141_arg0); - setArg(call_illegal_fp_vd_unmasked_3141, 2, illegal_fp_vd_unmasked_3141_arg1); - setRet(call_illegal_fp_vd_unmasked_3141, 0, ret_val_illegal_fp_vd_unmasked_3141); + InvokeNode* call_illegal_fp_vd_unmasked_3157; + auto illegal_fp_vd_unmasked_3157_arg0 = SEW; + auto illegal_fp_vd_unmasked_3157_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3157 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3157, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3157; + setArg(call_illegal_fp_vd_unmasked_3157, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3157, 1, illegal_fp_vd_unmasked_3157_arg0); + setArg(call_illegal_fp_vd_unmasked_3157, 2, illegal_fp_vd_unmasked_3157_arg1); + setRet(call_illegal_fp_vd_unmasked_3157, 0, ret_val_illegal_fp_vd_unmasked_3157); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73955,29 +73559,27 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3143; - x86::Gp ret_val_sew_3143 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3143, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_scalar_to_vector_3142; - auto scalar_to_vector_3142_arg1 = load_reg_from_mem(jh, traits::vtype); - auto scalar_to_vector_3142_arg3 = gen_ext(cc, + InvokeNode* call_sew_3159; + x86::Gp ret_val_sew_3159 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3159, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_to_vector_3158; + auto scalar_to_vector_3158_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_to_vector_3158_arg3 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false), 32, false); - auto scalar_to_vector_3142_arg4 = ret_val_sew_3143; + auto scalar_to_vector_3158_arg4 = ret_val_sew_3159; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_scalar_to_vector_3142, &scalar_to_vector, FuncSignature::build()); - setArg(call_sew_3143, 0, reinterpret_cast(this)); - setRet(call_sew_3143, 0, ret_val_sew_3143); - setArg(call_scalar_to_vector_3142, 0, V); - setArg(call_scalar_to_vector_3142, 1, scalar_to_vector_3142_arg1); - setArg(call_scalar_to_vector_3142, 2, vd); - setArg(call_scalar_to_vector_3142, 3, scalar_to_vector_3142_arg3); - setArg(call_scalar_to_vector_3142, 4, scalar_to_vector_3142_arg4); - auto tmp3144 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3144, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3144, 32, false) - , traits::vstart); + cc.invoke(&call_scalar_to_vector_3158, &scalar_to_vector, FuncSignature::build()); + setArg(call_sew_3159, 0, reinterpret_cast(this)); + setRet(call_sew_3159, 0, ret_val_sew_3159); + setArg(call_scalar_to_vector_3158, 0, V); + setArg(call_scalar_to_vector_3158, 1, scalar_to_vector_3158_arg1); + setArg(call_scalar_to_vector_3158, 2, vd); + setArg(call_scalar_to_vector_3158, 3, scalar_to_vector_3158_arg3); + setArg(call_scalar_to_vector_3158, 4, scalar_to_vector_3158_arg4); + auto tmp3160 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3160, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3160, traits::vstart); } cc.bind(label_merge); } @@ -74022,28 +73624,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3145; - x86::Gp ret_val_get_sew_pow_3145 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3145, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3146 = get_reg(cc, 8, false); - mov(cc, tmp3146, 1); + InvokeNode* call_get_sew_pow_3161; + x86::Gp ret_val_get_sew_pow_3161 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3161, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3162 = get_reg(cc, 8, false); + mov(cc, tmp3162, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3146, (ret_val_get_sew_pow_3145))), 8, false), ~ 1); - setArg(call_get_sew_pow_3145, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3145, 0, ret_val_get_sew_pow_3145); + (gen_operation(cc, shl, tmp3162, (ret_val_get_sew_pow_3161))), 8, false), ~ 1); + setArg(call_get_sew_pow_3161, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3161, 0, ret_val_get_sew_pow_3161); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3147; - auto illegal_fp_vd_unmasked_3147_arg0 = SEW; - auto illegal_fp_vd_unmasked_3147_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3147 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3147, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_vd_unmasked_3147, gen_operation(cc, gtu, SEW, static_cast(traits::FLEN))); - setArg(call_illegal_fp_vd_unmasked_3147, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3147, 1, illegal_fp_vd_unmasked_3147_arg0); - setArg(call_illegal_fp_vd_unmasked_3147, 2, illegal_fp_vd_unmasked_3147_arg1); - setRet(call_illegal_fp_vd_unmasked_3147, 0, ret_val_illegal_fp_vd_unmasked_3147); + InvokeNode* call_illegal_fp_vd_unmasked_3163; + auto illegal_fp_vd_unmasked_3163_arg0 = SEW; + auto illegal_fp_vd_unmasked_3163_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3163 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3163, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_vd_unmasked_3163, gen_operation(cc, gtu, SEW, static_cast(traits::FLEN))); + setArg(call_illegal_fp_vd_unmasked_3163, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3163, 1, illegal_fp_vd_unmasked_3163_arg0); + setArg(call_illegal_fp_vd_unmasked_3163, 2, illegal_fp_vd_unmasked_3163_arg1); + setRet(call_illegal_fp_vd_unmasked_3163, 0, ret_val_illegal_fp_vd_unmasked_3163); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74053,29 +73655,27 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3149; - x86::Gp ret_val_sew_3149 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3149, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_scalar_from_vector_3148; - auto fp_scalar_from_vector_3148_arg1 = load_reg_from_mem(jh, traits::vtype); - auto fp_scalar_from_vector_3148_arg3 = ret_val_sew_3149; + InvokeNode* call_sew_3165; + x86::Gp ret_val_sew_3165 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3165, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_scalar_from_vector_3164; + auto fp_scalar_from_vector_3164_arg1 = load_reg_from_mem(jh, traits::vtype); + auto fp_scalar_from_vector_3164_arg3 = ret_val_sew_3165; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_fp_scalar_from_vector_3148 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_fp_scalar_from_vector_3148, &fp_scalar_from_vector, FuncSignature::build()); + x86::Gp ret_val_fp_scalar_from_vector_3164 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fp_scalar_from_vector_3164, &fp_scalar_from_vector, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::F0+ rd), - ret_val_fp_scalar_from_vector_3148); - setArg(call_sew_3149, 0, reinterpret_cast(this)); - setRet(call_sew_3149, 0, ret_val_sew_3149); - setArg(call_fp_scalar_from_vector_3148, 0, V); - setArg(call_fp_scalar_from_vector_3148, 1, fp_scalar_from_vector_3148_arg1); - setArg(call_fp_scalar_from_vector_3148, 2, vs2); - setArg(call_fp_scalar_from_vector_3148, 3, fp_scalar_from_vector_3148_arg3); - setRet(call_fp_scalar_from_vector_3148, 0, ret_val_fp_scalar_from_vector_3148); - auto tmp3150 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3150, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3150, 32, false) - , traits::vstart); + ret_val_fp_scalar_from_vector_3164); + setArg(call_sew_3165, 0, reinterpret_cast(this)); + setRet(call_sew_3165, 0, ret_val_sew_3165); + setArg(call_fp_scalar_from_vector_3164, 0, V); + setArg(call_fp_scalar_from_vector_3164, 1, fp_scalar_from_vector_3164_arg1); + setArg(call_fp_scalar_from_vector_3164, 2, vs2); + setArg(call_fp_scalar_from_vector_3164, 3, fp_scalar_from_vector_3164_arg3); + setRet(call_fp_scalar_from_vector_3164, 0, ret_val_fp_scalar_from_vector_3164); + auto tmp3166 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3166, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3166, traits::vstart); } cc.bind(label_merge); } @@ -74119,30 +73719,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3151; - x86::Gp ret_val_get_sew_pow_3151 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3151, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3152 = get_reg(cc, 8, false); - mov(cc, tmp3152, 1); + InvokeNode* call_get_sew_pow_3167; + x86::Gp ret_val_get_sew_pow_3167 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3167, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3168 = get_reg(cc, 8, false); + mov(cc, tmp3168, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3152, (ret_val_get_sew_pow_3151))), 8, false), ~ 1); - setArg(call_get_sew_pow_3151, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3151, 0, ret_val_get_sew_pow_3151); + (gen_operation(cc, shl, tmp3168, (ret_val_get_sew_pow_3167))), 8, false), ~ 1); + setArg(call_get_sew_pow_3167, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3167, 0, ret_val_get_sew_pow_3167); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3153; - auto illegal_fp_normal_3153_arg2 = SEW; - auto illegal_fp_normal_3153_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3153 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3153, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3153; - setArg(call_illegal_fp_normal_3153, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3153, 1, vd); - setArg(call_illegal_fp_normal_3153, 2, vm); - setArg(call_illegal_fp_normal_3153, 3, illegal_fp_normal_3153_arg2); - setArg(call_illegal_fp_normal_3153, 4, illegal_fp_normal_3153_arg3); - setRet(call_illegal_fp_normal_3153, 0, ret_val_illegal_fp_normal_3153); + InvokeNode* call_illegal_fp_normal_3169; + auto illegal_fp_normal_3169_arg2 = SEW; + auto illegal_fp_normal_3169_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3169 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3169, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3169; + setArg(call_illegal_fp_normal_3169, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3169, 1, vd); + setArg(call_illegal_fp_normal_3169, 2, vm); + setArg(call_illegal_fp_normal_3169, 3, illegal_fp_normal_3169_arg2); + setArg(call_illegal_fp_normal_3169, 4, illegal_fp_normal_3169_arg3); + setRet(call_illegal_fp_normal_3169, 0, ret_val_illegal_fp_normal_3169); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74158,36 +73758,34 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3155; - x86::Gp ret_val_sew_3155 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3155, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_slide1up_3154; - auto fp_vector_slide1up_3154_arg1 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_slide1up_3154_arg2 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_slide1up_3154_arg3 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_slide1up_3154_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); - auto fp_vector_slide1up_3154_arg8 = ret_val_sew_3155; + InvokeNode* call_sew_3171; + x86::Gp ret_val_sew_3171 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3171, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_slide1up_3170; + auto fp_vector_slide1up_3170_arg1 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_slide1up_3170_arg2 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_slide1up_3170_arg3 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_slide1up_3170_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + auto fp_vector_slide1up_3170_arg8 = ret_val_sew_3171; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_slide1up_3154, &fp_vector_slide1up, FuncSignature::build()); - setArg(call_sew_3155, 0, reinterpret_cast(this)); - setRet(call_sew_3155, 0, ret_val_sew_3155); - setArg(call_fp_vector_slide1up_3154, 0, V); - setArg(call_fp_vector_slide1up_3154, 1, fp_vector_slide1up_3154_arg1); - setArg(call_fp_vector_slide1up_3154, 2, fp_vector_slide1up_3154_arg2); - setArg(call_fp_vector_slide1up_3154, 3, fp_vector_slide1up_3154_arg3); - setArg(call_fp_vector_slide1up_3154, 4, vm); - setArg(call_fp_vector_slide1up_3154, 5, vd); - setArg(call_fp_vector_slide1up_3154, 6, vs2); - setArg(call_fp_vector_slide1up_3154, 7, fp_vector_slide1up_3154_arg7); - setArg(call_fp_vector_slide1up_3154, 8, fp_vector_slide1up_3154_arg8); + cc.invoke(&call_fp_vector_slide1up_3170, &fp_vector_slide1up, FuncSignature::build()); + setArg(call_sew_3171, 0, reinterpret_cast(this)); + setRet(call_sew_3171, 0, ret_val_sew_3171); + setArg(call_fp_vector_slide1up_3170, 0, V); + setArg(call_fp_vector_slide1up_3170, 1, fp_vector_slide1up_3170_arg1); + setArg(call_fp_vector_slide1up_3170, 2, fp_vector_slide1up_3170_arg2); + setArg(call_fp_vector_slide1up_3170, 3, fp_vector_slide1up_3170_arg3); + setArg(call_fp_vector_slide1up_3170, 4, vm); + setArg(call_fp_vector_slide1up_3170, 5, vd); + setArg(call_fp_vector_slide1up_3170, 6, vs2); + setArg(call_fp_vector_slide1up_3170, 7, fp_vector_slide1up_3170_arg7); + setArg(call_fp_vector_slide1up_3170, 8, fp_vector_slide1up_3170_arg8); } cc.bind(label_merge); } - auto tmp3156 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3156, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3156, 32, false) - , traits::vstart); + auto tmp3172 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3172, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3172, traits::vstart); } cc.bind(label_merge); } @@ -74231,30 +73829,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3157; - x86::Gp ret_val_get_sew_pow_3157 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3157, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3158 = get_reg(cc, 8, false); - mov(cc, tmp3158, 1); + InvokeNode* call_get_sew_pow_3173; + x86::Gp ret_val_get_sew_pow_3173 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3173, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3174 = get_reg(cc, 8, false); + mov(cc, tmp3174, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3158, (ret_val_get_sew_pow_3157))), 8, false), ~ 1); - setArg(call_get_sew_pow_3157, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3157, 0, ret_val_get_sew_pow_3157); + (gen_operation(cc, shl, tmp3174, (ret_val_get_sew_pow_3173))), 8, false), ~ 1); + setArg(call_get_sew_pow_3173, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3173, 0, ret_val_get_sew_pow_3173); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3159; - auto illegal_fp_normal_3159_arg2 = SEW; - auto illegal_fp_normal_3159_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3159 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3159, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3159; - setArg(call_illegal_fp_normal_3159, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3159, 1, vd); - setArg(call_illegal_fp_normal_3159, 2, vm); - setArg(call_illegal_fp_normal_3159, 3, illegal_fp_normal_3159_arg2); - setArg(call_illegal_fp_normal_3159, 4, illegal_fp_normal_3159_arg3); - setRet(call_illegal_fp_normal_3159, 0, ret_val_illegal_fp_normal_3159); + InvokeNode* call_illegal_fp_normal_3175; + auto illegal_fp_normal_3175_arg2 = SEW; + auto illegal_fp_normal_3175_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3175 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3175, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3175; + setArg(call_illegal_fp_normal_3175, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3175, 1, vd); + setArg(call_illegal_fp_normal_3175, 2, vm); + setArg(call_illegal_fp_normal_3175, 3, illegal_fp_normal_3175_arg2); + setArg(call_illegal_fp_normal_3175, 4, illegal_fp_normal_3175_arg3); + setRet(call_illegal_fp_normal_3175, 0, ret_val_illegal_fp_normal_3175); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74270,36 +73868,34 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3161; - x86::Gp ret_val_sew_3161 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3161, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_slide1down_3160; - auto fp_vector_slide1down_3160_arg1 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_slide1down_3160_arg2 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_slide1down_3160_arg3 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_slide1down_3160_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); - auto fp_vector_slide1down_3160_arg8 = ret_val_sew_3161; + InvokeNode* call_sew_3177; + x86::Gp ret_val_sew_3177 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3177, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_slide1down_3176; + auto fp_vector_slide1down_3176_arg1 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_slide1down_3176_arg2 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_slide1down_3176_arg3 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_slide1down_3176_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + auto fp_vector_slide1down_3176_arg8 = ret_val_sew_3177; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_slide1down_3160, &fp_vector_slide1down, FuncSignature::build()); - setArg(call_sew_3161, 0, reinterpret_cast(this)); - setRet(call_sew_3161, 0, ret_val_sew_3161); - setArg(call_fp_vector_slide1down_3160, 0, V); - setArg(call_fp_vector_slide1down_3160, 1, fp_vector_slide1down_3160_arg1); - setArg(call_fp_vector_slide1down_3160, 2, fp_vector_slide1down_3160_arg2); - setArg(call_fp_vector_slide1down_3160, 3, fp_vector_slide1down_3160_arg3); - setArg(call_fp_vector_slide1down_3160, 4, vm); - setArg(call_fp_vector_slide1down_3160, 5, vd); - setArg(call_fp_vector_slide1down_3160, 6, vs2); - setArg(call_fp_vector_slide1down_3160, 7, fp_vector_slide1down_3160_arg7); - setArg(call_fp_vector_slide1down_3160, 8, fp_vector_slide1down_3160_arg8); + cc.invoke(&call_fp_vector_slide1down_3176, &fp_vector_slide1down, FuncSignature::build()); + setArg(call_sew_3177, 0, reinterpret_cast(this)); + setRet(call_sew_3177, 0, ret_val_sew_3177); + setArg(call_fp_vector_slide1down_3176, 0, V); + setArg(call_fp_vector_slide1down_3176, 1, fp_vector_slide1down_3176_arg1); + setArg(call_fp_vector_slide1down_3176, 2, fp_vector_slide1down_3176_arg2); + setArg(call_fp_vector_slide1down_3176, 3, fp_vector_slide1down_3176_arg3); + setArg(call_fp_vector_slide1down_3176, 4, vm); + setArg(call_fp_vector_slide1down_3176, 5, vd); + setArg(call_fp_vector_slide1down_3176, 6, vs2); + setArg(call_fp_vector_slide1down_3176, 7, fp_vector_slide1down_3176_arg7); + setArg(call_fp_vector_slide1down_3176, 8, fp_vector_slide1down_3176_arg8); } cc.bind(label_merge); } - auto tmp3162 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3162, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3162, 32, false) - , traits::vstart); + auto tmp3178 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3178, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3178, traits::vstart); } cc.bind(label_merge); } @@ -74343,30 +73939,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3163; - x86::Gp ret_val_get_sew_pow_3163 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3163, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3164 = get_reg(cc, 8, false); - mov(cc, tmp3164, 1); + InvokeNode* call_get_sew_pow_3179; + x86::Gp ret_val_get_sew_pow_3179 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3179, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3180 = get_reg(cc, 8, false); + mov(cc, tmp3180, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3164, (ret_val_get_sew_pow_3163))), 8, false), ~ 1); - setArg(call_get_sew_pow_3163, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3163, 0, ret_val_get_sew_pow_3163); + (gen_operation(cc, shl, tmp3180, (ret_val_get_sew_pow_3179))), 8, false), ~ 1); + setArg(call_get_sew_pow_3179, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3179, 0, ret_val_get_sew_pow_3179); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3165; - auto illegal_fp_normal_3165_arg2 = SEW; - auto illegal_fp_normal_3165_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3165 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3165, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3165; - setArg(call_illegal_fp_normal_3165, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3165, 1, vd); - setArg(call_illegal_fp_normal_3165, 2, vm); - setArg(call_illegal_fp_normal_3165, 3, illegal_fp_normal_3165_arg2); - setArg(call_illegal_fp_normal_3165, 4, illegal_fp_normal_3165_arg3); - setRet(call_illegal_fp_normal_3165, 0, ret_val_illegal_fp_normal_3165); + InvokeNode* call_illegal_fp_normal_3181; + auto illegal_fp_normal_3181_arg2 = SEW; + auto illegal_fp_normal_3181_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3181 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3181, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3181; + setArg(call_illegal_fp_normal_3181, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3181, 1, vd); + setArg(call_illegal_fp_normal_3181, 2, vm); + setArg(call_illegal_fp_normal_3181, 3, illegal_fp_normal_3181_arg2); + setArg(call_illegal_fp_normal_3181, 4, illegal_fp_normal_3181_arg3); + setRet(call_illegal_fp_normal_3181, 0, ret_val_illegal_fp_normal_3181); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74382,47 +73978,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3167; - x86::Gp ret_val_sew_3167 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3167, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3166; - auto fp_vector_imm_op_3166_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3166_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3166_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3166_arg9 = gen_ext(cc, + InvokeNode* call_sew_3183; + x86::Gp ret_val_sew_3183 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3183, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3182; + auto fp_vector_imm_op_3182_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3182_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3182_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3182_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3166_arg10 = rm; - auto fp_vector_imm_op_3166_arg11 = ret_val_sew_3167; + auto fp_vector_imm_op_3182_arg10 = rm; + auto fp_vector_imm_op_3182_arg11 = ret_val_sew_3183; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3166, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3167, 0, reinterpret_cast(this)); - setRet(call_sew_3167, 0, ret_val_sew_3167); - setArg(call_fp_vector_imm_op_3166, 0, V); - setArg(call_fp_vector_imm_op_3166, 1, 0); - setArg(call_fp_vector_imm_op_3166, 2, 5); - setArg(call_fp_vector_imm_op_3166, 3, fp_vector_imm_op_3166_arg3); - setArg(call_fp_vector_imm_op_3166, 4, fp_vector_imm_op_3166_arg4); - setArg(call_fp_vector_imm_op_3166, 5, fp_vector_imm_op_3166_arg5); - setArg(call_fp_vector_imm_op_3166, 6, vm); - setArg(call_fp_vector_imm_op_3166, 7, vd); - setArg(call_fp_vector_imm_op_3166, 8, vs2); - setArg(call_fp_vector_imm_op_3166, 9, fp_vector_imm_op_3166_arg9); - setArg(call_fp_vector_imm_op_3166, 10, fp_vector_imm_op_3166_arg10); - setArg(call_fp_vector_imm_op_3166, 11, fp_vector_imm_op_3166_arg11); - InvokeNode* call_fget_flags_3168; - x86::Gp ret_val_fget_flags_3168 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3168, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3168; - setRet(call_fget_flags_3168, 0, ret_val_fget_flags_3168); + cc.invoke(&call_fp_vector_imm_op_3182, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3183, 0, reinterpret_cast(this)); + setRet(call_sew_3183, 0, ret_val_sew_3183); + setArg(call_fp_vector_imm_op_3182, 0, V); + setArg(call_fp_vector_imm_op_3182, 1, 0); + setArg(call_fp_vector_imm_op_3182, 2, 5); + setArg(call_fp_vector_imm_op_3182, 3, fp_vector_imm_op_3182_arg3); + setArg(call_fp_vector_imm_op_3182, 4, fp_vector_imm_op_3182_arg4); + setArg(call_fp_vector_imm_op_3182, 5, fp_vector_imm_op_3182_arg5); + setArg(call_fp_vector_imm_op_3182, 6, vm); + setArg(call_fp_vector_imm_op_3182, 7, vd); + setArg(call_fp_vector_imm_op_3182, 8, vs2); + setArg(call_fp_vector_imm_op_3182, 9, fp_vector_imm_op_3182_arg9); + setArg(call_fp_vector_imm_op_3182, 10, fp_vector_imm_op_3182_arg10); + setArg(call_fp_vector_imm_op_3182, 11, fp_vector_imm_op_3182_arg11); + InvokeNode* call_fget_flags_3184; + x86::Gp ret_val_fget_flags_3184 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3184, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3184; + setRet(call_fget_flags_3184, 0, ret_val_fget_flags_3184); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3169 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3169, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3169, 32, false) - , traits::vstart); + auto tmp3185 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3185, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3185, traits::vstart); } cc.bind(label_merge); } @@ -74466,30 +74060,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3170; - x86::Gp ret_val_get_sew_pow_3170 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3170, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3171 = get_reg(cc, 8, false); - mov(cc, tmp3171, 1); + InvokeNode* call_get_sew_pow_3186; + x86::Gp ret_val_get_sew_pow_3186 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3186, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3187 = get_reg(cc, 8, false); + mov(cc, tmp3187, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3171, (ret_val_get_sew_pow_3170))), 8, false), ~ 1); - setArg(call_get_sew_pow_3170, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3170, 0, ret_val_get_sew_pow_3170); + (gen_operation(cc, shl, tmp3187, (ret_val_get_sew_pow_3186))), 8, false), ~ 1); + setArg(call_get_sew_pow_3186, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3186, 0, ret_val_get_sew_pow_3186); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3172; - auto illegal_fp_normal_3172_arg2 = SEW; - auto illegal_fp_normal_3172_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3172 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3172, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3172; - setArg(call_illegal_fp_normal_3172, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3172, 1, vd); - setArg(call_illegal_fp_normal_3172, 2, vm); - setArg(call_illegal_fp_normal_3172, 3, illegal_fp_normal_3172_arg2); - setArg(call_illegal_fp_normal_3172, 4, illegal_fp_normal_3172_arg3); - setRet(call_illegal_fp_normal_3172, 0, ret_val_illegal_fp_normal_3172); + InvokeNode* call_illegal_fp_normal_3188; + auto illegal_fp_normal_3188_arg2 = SEW; + auto illegal_fp_normal_3188_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3188 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3188, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3188; + setArg(call_illegal_fp_normal_3188, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3188, 1, vd); + setArg(call_illegal_fp_normal_3188, 2, vm); + setArg(call_illegal_fp_normal_3188, 3, illegal_fp_normal_3188_arg2); + setArg(call_illegal_fp_normal_3188, 4, illegal_fp_normal_3188_arg3); + setRet(call_illegal_fp_normal_3188, 0, ret_val_illegal_fp_normal_3188); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74505,45 +74099,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3174; - x86::Gp ret_val_sew_3174 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3174, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3173; - auto fp_vector_vector_op_3173_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3173_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3173_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3173_arg10 = rm; - auto fp_vector_vector_op_3173_arg11 = ret_val_sew_3174; + InvokeNode* call_sew_3190; + x86::Gp ret_val_sew_3190 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3190, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3189; + auto fp_vector_vector_op_3189_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3189_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3189_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3189_arg10 = rm; + auto fp_vector_vector_op_3189_arg11 = ret_val_sew_3190; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3173, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3174, 0, reinterpret_cast(this)); - setRet(call_sew_3174, 0, ret_val_sew_3174); - setArg(call_fp_vector_vector_op_3173, 0, V); - setArg(call_fp_vector_vector_op_3173, 1, 0); - setArg(call_fp_vector_vector_op_3173, 2, 1); - setArg(call_fp_vector_vector_op_3173, 3, fp_vector_vector_op_3173_arg3); - setArg(call_fp_vector_vector_op_3173, 4, fp_vector_vector_op_3173_arg4); - setArg(call_fp_vector_vector_op_3173, 5, fp_vector_vector_op_3173_arg5); - setArg(call_fp_vector_vector_op_3173, 6, vm); - setArg(call_fp_vector_vector_op_3173, 7, vd); - setArg(call_fp_vector_vector_op_3173, 8, vs2); - setArg(call_fp_vector_vector_op_3173, 9, vs1); - setArg(call_fp_vector_vector_op_3173, 10, fp_vector_vector_op_3173_arg10); - setArg(call_fp_vector_vector_op_3173, 11, fp_vector_vector_op_3173_arg11); - InvokeNode* call_fget_flags_3175; - x86::Gp ret_val_fget_flags_3175 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3175, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3175; - setRet(call_fget_flags_3175, 0, ret_val_fget_flags_3175); + cc.invoke(&call_fp_vector_vector_op_3189, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3190, 0, reinterpret_cast(this)); + setRet(call_sew_3190, 0, ret_val_sew_3190); + setArg(call_fp_vector_vector_op_3189, 0, V); + setArg(call_fp_vector_vector_op_3189, 1, 0); + setArg(call_fp_vector_vector_op_3189, 2, 1); + setArg(call_fp_vector_vector_op_3189, 3, fp_vector_vector_op_3189_arg3); + setArg(call_fp_vector_vector_op_3189, 4, fp_vector_vector_op_3189_arg4); + setArg(call_fp_vector_vector_op_3189, 5, fp_vector_vector_op_3189_arg5); + setArg(call_fp_vector_vector_op_3189, 6, vm); + setArg(call_fp_vector_vector_op_3189, 7, vd); + setArg(call_fp_vector_vector_op_3189, 8, vs2); + setArg(call_fp_vector_vector_op_3189, 9, vs1); + setArg(call_fp_vector_vector_op_3189, 10, fp_vector_vector_op_3189_arg10); + setArg(call_fp_vector_vector_op_3189, 11, fp_vector_vector_op_3189_arg11); + InvokeNode* call_fget_flags_3191; + x86::Gp ret_val_fget_flags_3191 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3191, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3191; + setRet(call_fget_flags_3191, 0, ret_val_fget_flags_3191); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3176 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3176, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3176, 32, false) - , traits::vstart); + auto tmp3192 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3192, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3192, traits::vstart); } cc.bind(label_merge); } @@ -74587,30 +74179,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3177; - x86::Gp ret_val_get_sew_pow_3177 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3177, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3178 = get_reg(cc, 8, false); - mov(cc, tmp3178, 1); + InvokeNode* call_get_sew_pow_3193; + x86::Gp ret_val_get_sew_pow_3193 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3193, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3194 = get_reg(cc, 8, false); + mov(cc, tmp3194, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3178, (ret_val_get_sew_pow_3177))), 8, false), ~ 1); - setArg(call_get_sew_pow_3177, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3177, 0, ret_val_get_sew_pow_3177); + (gen_operation(cc, shl, tmp3194, (ret_val_get_sew_pow_3193))), 8, false), ~ 1); + setArg(call_get_sew_pow_3193, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3193, 0, ret_val_get_sew_pow_3193); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3179; - auto illegal_fp_normal_3179_arg2 = SEW; - auto illegal_fp_normal_3179_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3179 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3179, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3179; - setArg(call_illegal_fp_normal_3179, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3179, 1, vd); - setArg(call_illegal_fp_normal_3179, 2, vm); - setArg(call_illegal_fp_normal_3179, 3, illegal_fp_normal_3179_arg2); - setArg(call_illegal_fp_normal_3179, 4, illegal_fp_normal_3179_arg3); - setRet(call_illegal_fp_normal_3179, 0, ret_val_illegal_fp_normal_3179); + InvokeNode* call_illegal_fp_normal_3195; + auto illegal_fp_normal_3195_arg2 = SEW; + auto illegal_fp_normal_3195_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3195 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3195, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3195; + setArg(call_illegal_fp_normal_3195, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3195, 1, vd); + setArg(call_illegal_fp_normal_3195, 2, vm); + setArg(call_illegal_fp_normal_3195, 3, illegal_fp_normal_3195_arg2); + setArg(call_illegal_fp_normal_3195, 4, illegal_fp_normal_3195_arg3); + setRet(call_illegal_fp_normal_3195, 0, ret_val_illegal_fp_normal_3195); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74626,47 +74218,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3181; - x86::Gp ret_val_sew_3181 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3181, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3180; - auto fp_vector_imm_op_3180_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3180_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3180_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3180_arg9 = gen_ext(cc, + InvokeNode* call_sew_3197; + x86::Gp ret_val_sew_3197 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3197, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3196; + auto fp_vector_imm_op_3196_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3196_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3196_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3196_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3180_arg10 = rm; - auto fp_vector_imm_op_3180_arg11 = ret_val_sew_3181; + auto fp_vector_imm_op_3196_arg10 = rm; + auto fp_vector_imm_op_3196_arg11 = ret_val_sew_3197; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3180, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3181, 0, reinterpret_cast(this)); - setRet(call_sew_3181, 0, ret_val_sew_3181); - setArg(call_fp_vector_imm_op_3180, 0, V); - setArg(call_fp_vector_imm_op_3180, 1, 2); - setArg(call_fp_vector_imm_op_3180, 2, 5); - setArg(call_fp_vector_imm_op_3180, 3, fp_vector_imm_op_3180_arg3); - setArg(call_fp_vector_imm_op_3180, 4, fp_vector_imm_op_3180_arg4); - setArg(call_fp_vector_imm_op_3180, 5, fp_vector_imm_op_3180_arg5); - setArg(call_fp_vector_imm_op_3180, 6, vm); - setArg(call_fp_vector_imm_op_3180, 7, vd); - setArg(call_fp_vector_imm_op_3180, 8, vs2); - setArg(call_fp_vector_imm_op_3180, 9, fp_vector_imm_op_3180_arg9); - setArg(call_fp_vector_imm_op_3180, 10, fp_vector_imm_op_3180_arg10); - setArg(call_fp_vector_imm_op_3180, 11, fp_vector_imm_op_3180_arg11); - InvokeNode* call_fget_flags_3182; - x86::Gp ret_val_fget_flags_3182 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3182, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3182; - setRet(call_fget_flags_3182, 0, ret_val_fget_flags_3182); + cc.invoke(&call_fp_vector_imm_op_3196, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3197, 0, reinterpret_cast(this)); + setRet(call_sew_3197, 0, ret_val_sew_3197); + setArg(call_fp_vector_imm_op_3196, 0, V); + setArg(call_fp_vector_imm_op_3196, 1, 2); + setArg(call_fp_vector_imm_op_3196, 2, 5); + setArg(call_fp_vector_imm_op_3196, 3, fp_vector_imm_op_3196_arg3); + setArg(call_fp_vector_imm_op_3196, 4, fp_vector_imm_op_3196_arg4); + setArg(call_fp_vector_imm_op_3196, 5, fp_vector_imm_op_3196_arg5); + setArg(call_fp_vector_imm_op_3196, 6, vm); + setArg(call_fp_vector_imm_op_3196, 7, vd); + setArg(call_fp_vector_imm_op_3196, 8, vs2); + setArg(call_fp_vector_imm_op_3196, 9, fp_vector_imm_op_3196_arg9); + setArg(call_fp_vector_imm_op_3196, 10, fp_vector_imm_op_3196_arg10); + setArg(call_fp_vector_imm_op_3196, 11, fp_vector_imm_op_3196_arg11); + InvokeNode* call_fget_flags_3198; + x86::Gp ret_val_fget_flags_3198 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3198, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3198; + setRet(call_fget_flags_3198, 0, ret_val_fget_flags_3198); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3183 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3183, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3183, 32, false) - , traits::vstart); + auto tmp3199 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3199, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3199, traits::vstart); } cc.bind(label_merge); } @@ -74710,30 +74300,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3184; - x86::Gp ret_val_get_sew_pow_3184 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3184, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3185 = get_reg(cc, 8, false); - mov(cc, tmp3185, 1); + InvokeNode* call_get_sew_pow_3200; + x86::Gp ret_val_get_sew_pow_3200 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3200, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3201 = get_reg(cc, 8, false); + mov(cc, tmp3201, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3185, (ret_val_get_sew_pow_3184))), 8, false), ~ 1); - setArg(call_get_sew_pow_3184, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3184, 0, ret_val_get_sew_pow_3184); + (gen_operation(cc, shl, tmp3201, (ret_val_get_sew_pow_3200))), 8, false), ~ 1); + setArg(call_get_sew_pow_3200, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3200, 0, ret_val_get_sew_pow_3200); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3186; - auto illegal_fp_normal_3186_arg2 = SEW; - auto illegal_fp_normal_3186_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3186 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3186, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3186; - setArg(call_illegal_fp_normal_3186, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3186, 1, vd); - setArg(call_illegal_fp_normal_3186, 2, vm); - setArg(call_illegal_fp_normal_3186, 3, illegal_fp_normal_3186_arg2); - setArg(call_illegal_fp_normal_3186, 4, illegal_fp_normal_3186_arg3); - setRet(call_illegal_fp_normal_3186, 0, ret_val_illegal_fp_normal_3186); + InvokeNode* call_illegal_fp_normal_3202; + auto illegal_fp_normal_3202_arg2 = SEW; + auto illegal_fp_normal_3202_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3202 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3202, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3202; + setArg(call_illegal_fp_normal_3202, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3202, 1, vd); + setArg(call_illegal_fp_normal_3202, 2, vm); + setArg(call_illegal_fp_normal_3202, 3, illegal_fp_normal_3202_arg2); + setArg(call_illegal_fp_normal_3202, 4, illegal_fp_normal_3202_arg3); + setRet(call_illegal_fp_normal_3202, 0, ret_val_illegal_fp_normal_3202); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74749,45 +74339,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3188; - x86::Gp ret_val_sew_3188 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3188, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3187; - auto fp_vector_vector_op_3187_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3187_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3187_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3187_arg10 = rm; - auto fp_vector_vector_op_3187_arg11 = ret_val_sew_3188; + InvokeNode* call_sew_3204; + x86::Gp ret_val_sew_3204 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3204, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3203; + auto fp_vector_vector_op_3203_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3203_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3203_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3203_arg10 = rm; + auto fp_vector_vector_op_3203_arg11 = ret_val_sew_3204; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3187, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3188, 0, reinterpret_cast(this)); - setRet(call_sew_3188, 0, ret_val_sew_3188); - setArg(call_fp_vector_vector_op_3187, 0, V); - setArg(call_fp_vector_vector_op_3187, 1, 2); - setArg(call_fp_vector_vector_op_3187, 2, 1); - setArg(call_fp_vector_vector_op_3187, 3, fp_vector_vector_op_3187_arg3); - setArg(call_fp_vector_vector_op_3187, 4, fp_vector_vector_op_3187_arg4); - setArg(call_fp_vector_vector_op_3187, 5, fp_vector_vector_op_3187_arg5); - setArg(call_fp_vector_vector_op_3187, 6, vm); - setArg(call_fp_vector_vector_op_3187, 7, vd); - setArg(call_fp_vector_vector_op_3187, 8, vs2); - setArg(call_fp_vector_vector_op_3187, 9, vs1); - setArg(call_fp_vector_vector_op_3187, 10, fp_vector_vector_op_3187_arg10); - setArg(call_fp_vector_vector_op_3187, 11, fp_vector_vector_op_3187_arg11); - InvokeNode* call_fget_flags_3189; - x86::Gp ret_val_fget_flags_3189 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3189, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3189; - setRet(call_fget_flags_3189, 0, ret_val_fget_flags_3189); + cc.invoke(&call_fp_vector_vector_op_3203, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3204, 0, reinterpret_cast(this)); + setRet(call_sew_3204, 0, ret_val_sew_3204); + setArg(call_fp_vector_vector_op_3203, 0, V); + setArg(call_fp_vector_vector_op_3203, 1, 2); + setArg(call_fp_vector_vector_op_3203, 2, 1); + setArg(call_fp_vector_vector_op_3203, 3, fp_vector_vector_op_3203_arg3); + setArg(call_fp_vector_vector_op_3203, 4, fp_vector_vector_op_3203_arg4); + setArg(call_fp_vector_vector_op_3203, 5, fp_vector_vector_op_3203_arg5); + setArg(call_fp_vector_vector_op_3203, 6, vm); + setArg(call_fp_vector_vector_op_3203, 7, vd); + setArg(call_fp_vector_vector_op_3203, 8, vs2); + setArg(call_fp_vector_vector_op_3203, 9, vs1); + setArg(call_fp_vector_vector_op_3203, 10, fp_vector_vector_op_3203_arg10); + setArg(call_fp_vector_vector_op_3203, 11, fp_vector_vector_op_3203_arg11); + InvokeNode* call_fget_flags_3205; + x86::Gp ret_val_fget_flags_3205 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3205, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3205; + setRet(call_fget_flags_3205, 0, ret_val_fget_flags_3205); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3190 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3190, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3190, 32, false) - , traits::vstart); + auto tmp3206 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3206, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3206, traits::vstart); } cc.bind(label_merge); } @@ -74831,30 +74419,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3191; - x86::Gp ret_val_get_sew_pow_3191 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3191, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3192 = get_reg(cc, 8, false); - mov(cc, tmp3192, 1); + InvokeNode* call_get_sew_pow_3207; + x86::Gp ret_val_get_sew_pow_3207 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3207, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3208 = get_reg(cc, 8, false); + mov(cc, tmp3208, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3192, (ret_val_get_sew_pow_3191))), 8, false), ~ 1); - setArg(call_get_sew_pow_3191, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3191, 0, ret_val_get_sew_pow_3191); + (gen_operation(cc, shl, tmp3208, (ret_val_get_sew_pow_3207))), 8, false), ~ 1); + setArg(call_get_sew_pow_3207, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3207, 0, ret_val_get_sew_pow_3207); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3193; - auto illegal_fp_normal_3193_arg2 = SEW; - auto illegal_fp_normal_3193_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3193 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3193, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3193; - setArg(call_illegal_fp_normal_3193, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3193, 1, vd); - setArg(call_illegal_fp_normal_3193, 2, vm); - setArg(call_illegal_fp_normal_3193, 3, illegal_fp_normal_3193_arg2); - setArg(call_illegal_fp_normal_3193, 4, illegal_fp_normal_3193_arg3); - setRet(call_illegal_fp_normal_3193, 0, ret_val_illegal_fp_normal_3193); + InvokeNode* call_illegal_fp_normal_3209; + auto illegal_fp_normal_3209_arg2 = SEW; + auto illegal_fp_normal_3209_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3209 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3209, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3209; + setArg(call_illegal_fp_normal_3209, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3209, 1, vd); + setArg(call_illegal_fp_normal_3209, 2, vm); + setArg(call_illegal_fp_normal_3209, 3, illegal_fp_normal_3209_arg2); + setArg(call_illegal_fp_normal_3209, 4, illegal_fp_normal_3209_arg3); + setRet(call_illegal_fp_normal_3209, 0, ret_val_illegal_fp_normal_3209); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74870,47 +74458,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3195; - x86::Gp ret_val_sew_3195 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3195, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3194; - auto fp_vector_imm_op_3194_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3194_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3194_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3194_arg9 = gen_ext(cc, + InvokeNode* call_sew_3211; + x86::Gp ret_val_sew_3211 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3211, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3210; + auto fp_vector_imm_op_3210_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3210_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3210_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3210_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3194_arg10 = rm; - auto fp_vector_imm_op_3194_arg11 = ret_val_sew_3195; + auto fp_vector_imm_op_3210_arg10 = rm; + auto fp_vector_imm_op_3210_arg11 = ret_val_sew_3211; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3194, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3195, 0, reinterpret_cast(this)); - setRet(call_sew_3195, 0, ret_val_sew_3195); - setArg(call_fp_vector_imm_op_3194, 0, V); - setArg(call_fp_vector_imm_op_3194, 1, 39); - setArg(call_fp_vector_imm_op_3194, 2, 5); - setArg(call_fp_vector_imm_op_3194, 3, fp_vector_imm_op_3194_arg3); - setArg(call_fp_vector_imm_op_3194, 4, fp_vector_imm_op_3194_arg4); - setArg(call_fp_vector_imm_op_3194, 5, fp_vector_imm_op_3194_arg5); - setArg(call_fp_vector_imm_op_3194, 6, vm); - setArg(call_fp_vector_imm_op_3194, 7, vd); - setArg(call_fp_vector_imm_op_3194, 8, vs2); - setArg(call_fp_vector_imm_op_3194, 9, fp_vector_imm_op_3194_arg9); - setArg(call_fp_vector_imm_op_3194, 10, fp_vector_imm_op_3194_arg10); - setArg(call_fp_vector_imm_op_3194, 11, fp_vector_imm_op_3194_arg11); - InvokeNode* call_fget_flags_3196; - x86::Gp ret_val_fget_flags_3196 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3196, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3196; - setRet(call_fget_flags_3196, 0, ret_val_fget_flags_3196); + cc.invoke(&call_fp_vector_imm_op_3210, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3211, 0, reinterpret_cast(this)); + setRet(call_sew_3211, 0, ret_val_sew_3211); + setArg(call_fp_vector_imm_op_3210, 0, V); + setArg(call_fp_vector_imm_op_3210, 1, 39); + setArg(call_fp_vector_imm_op_3210, 2, 5); + setArg(call_fp_vector_imm_op_3210, 3, fp_vector_imm_op_3210_arg3); + setArg(call_fp_vector_imm_op_3210, 4, fp_vector_imm_op_3210_arg4); + setArg(call_fp_vector_imm_op_3210, 5, fp_vector_imm_op_3210_arg5); + setArg(call_fp_vector_imm_op_3210, 6, vm); + setArg(call_fp_vector_imm_op_3210, 7, vd); + setArg(call_fp_vector_imm_op_3210, 8, vs2); + setArg(call_fp_vector_imm_op_3210, 9, fp_vector_imm_op_3210_arg9); + setArg(call_fp_vector_imm_op_3210, 10, fp_vector_imm_op_3210_arg10); + setArg(call_fp_vector_imm_op_3210, 11, fp_vector_imm_op_3210_arg11); + InvokeNode* call_fget_flags_3212; + x86::Gp ret_val_fget_flags_3212 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3212, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3212; + setRet(call_fget_flags_3212, 0, ret_val_fget_flags_3212); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3197 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3197, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3197, 32, false) - , traits::vstart); + auto tmp3213 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3213, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3213, traits::vstart); } cc.bind(label_merge); } @@ -74954,54 +74540,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3198; - x86::Gp ret_val_get_sew_pow_3198 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3198, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3199 = get_reg(cc, 8, false); - mov(cc, tmp3199, 1); + InvokeNode* call_get_sew_pow_3214; + x86::Gp ret_val_get_sew_pow_3214 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3214, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3215 = get_reg(cc, 8, false); + mov(cc, tmp3215, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3199, (ret_val_get_sew_pow_3198))), 8, false), ~ 1); - setArg(call_get_sew_pow_3198, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3198, 0, ret_val_get_sew_pow_3198); - InvokeNode* call_get_lmul_pow_3200; - x86::Gp ret_val_get_lmul_pow_3200 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3200, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3200; - setArg(call_get_lmul_pow_3200, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3200, 0, ret_val_get_lmul_pow_3200); + (gen_operation(cc, shl, tmp3215, (ret_val_get_sew_pow_3214))), 8, false), ~ 1); + setArg(call_get_sew_pow_3214, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3214, 0, ret_val_get_sew_pow_3214); + InvokeNode* call_get_lmul_pow_3216; + x86::Gp ret_val_get_lmul_pow_3216 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3216, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3216; + setArg(call_get_lmul_pow_3216, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3216, 0, ret_val_get_lmul_pow_3216); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3201; - auto illegal_fp_variable_width_3201_arg2 = SEW; - auto illegal_fp_variable_width_3201_arg3 = rm; - auto illegal_fp_variable_width_3201_arg4 = SEW_widen; - auto illegal_fp_variable_width_3201_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3201 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3201, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3202; - auto valid_reg_overlap_3202_arg2 = LMUL_pow; - auto valid_reg_overlap_3202_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3202 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3202, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3201, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3202)); - setArg(call_illegal_fp_variable_width_3201, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3201, 1, vd); - setArg(call_illegal_fp_variable_width_3201, 2, vm); - setArg(call_illegal_fp_variable_width_3201, 3, illegal_fp_variable_width_3201_arg2); - setArg(call_illegal_fp_variable_width_3201, 4, illegal_fp_variable_width_3201_arg3); - setArg(call_illegal_fp_variable_width_3201, 5, illegal_fp_variable_width_3201_arg4); - setArg(call_illegal_fp_variable_width_3201, 6, illegal_fp_variable_width_3201_arg5); - setRet(call_illegal_fp_variable_width_3201, 0, ret_val_illegal_fp_variable_width_3201); - setArg(call_valid_reg_overlap_3202, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3202, 1, vs2); - setArg(call_valid_reg_overlap_3202, 2, vd); - setArg(call_valid_reg_overlap_3202, 3, valid_reg_overlap_3202_arg2); - setArg(call_valid_reg_overlap_3202, 4, valid_reg_overlap_3202_arg3); - setRet(call_valid_reg_overlap_3202, 0, ret_val_valid_reg_overlap_3202); + InvokeNode* call_illegal_fp_variable_width_3217; + auto illegal_fp_variable_width_3217_arg2 = SEW; + auto illegal_fp_variable_width_3217_arg3 = rm; + auto illegal_fp_variable_width_3217_arg4 = SEW_widen; + auto illegal_fp_variable_width_3217_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3217 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3217, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3218; + auto valid_reg_overlap_3218_arg2 = LMUL_pow; + auto valid_reg_overlap_3218_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3218 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3218, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3217, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3218)); + setArg(call_illegal_fp_variable_width_3217, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3217, 1, vd); + setArg(call_illegal_fp_variable_width_3217, 2, vm); + setArg(call_illegal_fp_variable_width_3217, 3, illegal_fp_variable_width_3217_arg2); + setArg(call_illegal_fp_variable_width_3217, 4, illegal_fp_variable_width_3217_arg3); + setArg(call_illegal_fp_variable_width_3217, 5, illegal_fp_variable_width_3217_arg4); + setArg(call_illegal_fp_variable_width_3217, 6, illegal_fp_variable_width_3217_arg5); + setRet(call_illegal_fp_variable_width_3217, 0, ret_val_illegal_fp_variable_width_3217); + setArg(call_valid_reg_overlap_3218, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3218, 1, vs2); + setArg(call_valid_reg_overlap_3218, 2, vd); + setArg(call_valid_reg_overlap_3218, 3, valid_reg_overlap_3218_arg2); + setArg(call_valid_reg_overlap_3218, 4, valid_reg_overlap_3218_arg3); + setRet(call_valid_reg_overlap_3218, 0, ret_val_valid_reg_overlap_3218); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75017,47 +74603,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3204; - x86::Gp ret_val_sew_3204 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3204, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3203; - auto fp_vector_imm_wv_3203_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3203_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3203_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3203_arg9 = gen_ext(cc, + InvokeNode* call_sew_3220; + x86::Gp ret_val_sew_3220 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3220, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3219; + auto fp_vector_imm_wv_3219_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3219_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3219_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3219_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_wv_3203_arg10 = rm; - auto fp_vector_imm_wv_3203_arg11 = ret_val_sew_3204; + auto fp_vector_imm_wv_3219_arg10 = rm; + auto fp_vector_imm_wv_3219_arg11 = ret_val_sew_3220; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3203, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3204, 0, reinterpret_cast(this)); - setRet(call_sew_3204, 0, ret_val_sew_3204); - setArg(call_fp_vector_imm_wv_3203, 0, V); - setArg(call_fp_vector_imm_wv_3203, 1, 48); - setArg(call_fp_vector_imm_wv_3203, 2, 5); - setArg(call_fp_vector_imm_wv_3203, 3, fp_vector_imm_wv_3203_arg3); - setArg(call_fp_vector_imm_wv_3203, 4, fp_vector_imm_wv_3203_arg4); - setArg(call_fp_vector_imm_wv_3203, 5, fp_vector_imm_wv_3203_arg5); - setArg(call_fp_vector_imm_wv_3203, 6, vm); - setArg(call_fp_vector_imm_wv_3203, 7, vd); - setArg(call_fp_vector_imm_wv_3203, 8, vs2); - setArg(call_fp_vector_imm_wv_3203, 9, fp_vector_imm_wv_3203_arg9); - setArg(call_fp_vector_imm_wv_3203, 10, fp_vector_imm_wv_3203_arg10); - setArg(call_fp_vector_imm_wv_3203, 11, fp_vector_imm_wv_3203_arg11); - InvokeNode* call_fget_flags_3205; - x86::Gp ret_val_fget_flags_3205 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3205, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3205; - setRet(call_fget_flags_3205, 0, ret_val_fget_flags_3205); + cc.invoke(&call_fp_vector_imm_wv_3219, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3220, 0, reinterpret_cast(this)); + setRet(call_sew_3220, 0, ret_val_sew_3220); + setArg(call_fp_vector_imm_wv_3219, 0, V); + setArg(call_fp_vector_imm_wv_3219, 1, 48); + setArg(call_fp_vector_imm_wv_3219, 2, 5); + setArg(call_fp_vector_imm_wv_3219, 3, fp_vector_imm_wv_3219_arg3); + setArg(call_fp_vector_imm_wv_3219, 4, fp_vector_imm_wv_3219_arg4); + setArg(call_fp_vector_imm_wv_3219, 5, fp_vector_imm_wv_3219_arg5); + setArg(call_fp_vector_imm_wv_3219, 6, vm); + setArg(call_fp_vector_imm_wv_3219, 7, vd); + setArg(call_fp_vector_imm_wv_3219, 8, vs2); + setArg(call_fp_vector_imm_wv_3219, 9, fp_vector_imm_wv_3219_arg9); + setArg(call_fp_vector_imm_wv_3219, 10, fp_vector_imm_wv_3219_arg10); + setArg(call_fp_vector_imm_wv_3219, 11, fp_vector_imm_wv_3219_arg11); + InvokeNode* call_fget_flags_3221; + x86::Gp ret_val_fget_flags_3221 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3221, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3221; + setRet(call_fget_flags_3221, 0, ret_val_fget_flags_3221); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3206 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3206, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3206, 32, false) - , traits::vstart); + auto tmp3222 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3222, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3222, traits::vstart); } cc.bind(label_merge); } @@ -75101,65 +74685,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3207; - x86::Gp ret_val_get_sew_pow_3207 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3207, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3208 = get_reg(cc, 8, false); - mov(cc, tmp3208, 1); + InvokeNode* call_get_sew_pow_3223; + x86::Gp ret_val_get_sew_pow_3223 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3223, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3224 = get_reg(cc, 8, false); + mov(cc, tmp3224, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3208, (ret_val_get_sew_pow_3207))), 8, false), ~ 1); - setArg(call_get_sew_pow_3207, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3207, 0, ret_val_get_sew_pow_3207); - InvokeNode* call_get_lmul_pow_3209; - x86::Gp ret_val_get_lmul_pow_3209 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3209, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3209; - setArg(call_get_lmul_pow_3209, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3209, 0, ret_val_get_lmul_pow_3209); + (gen_operation(cc, shl, tmp3224, (ret_val_get_sew_pow_3223))), 8, false), ~ 1); + setArg(call_get_sew_pow_3223, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3223, 0, ret_val_get_sew_pow_3223); + InvokeNode* call_get_lmul_pow_3225; + x86::Gp ret_val_get_lmul_pow_3225 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3225, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3225; + setArg(call_get_lmul_pow_3225, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3225, 0, ret_val_get_lmul_pow_3225); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3210; - auto illegal_fp_variable_width_3210_arg2 = SEW; - auto illegal_fp_variable_width_3210_arg3 = rm; - auto illegal_fp_variable_width_3210_arg4 = SEW_widen; - auto illegal_fp_variable_width_3210_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3210 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3210, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3211; - auto valid_reg_overlap_3211_arg2 = LMUL_pow; - auto valid_reg_overlap_3211_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3211 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3211, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3212; - auto valid_reg_overlap_3212_arg2 = LMUL_pow; - auto valid_reg_overlap_3212_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3212 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3212, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3210, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3211)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3212)); - setArg(call_illegal_fp_variable_width_3210, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3210, 1, vd); - setArg(call_illegal_fp_variable_width_3210, 2, vm); - setArg(call_illegal_fp_variable_width_3210, 3, illegal_fp_variable_width_3210_arg2); - setArg(call_illegal_fp_variable_width_3210, 4, illegal_fp_variable_width_3210_arg3); - setArg(call_illegal_fp_variable_width_3210, 5, illegal_fp_variable_width_3210_arg4); - setArg(call_illegal_fp_variable_width_3210, 6, illegal_fp_variable_width_3210_arg5); - setRet(call_illegal_fp_variable_width_3210, 0, ret_val_illegal_fp_variable_width_3210); - setArg(call_valid_reg_overlap_3211, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3211, 1, vs1); - setArg(call_valid_reg_overlap_3211, 2, vd); - setArg(call_valid_reg_overlap_3211, 3, valid_reg_overlap_3211_arg2); - setArg(call_valid_reg_overlap_3211, 4, valid_reg_overlap_3211_arg3); - setRet(call_valid_reg_overlap_3211, 0, ret_val_valid_reg_overlap_3211); - setArg(call_valid_reg_overlap_3212, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3212, 1, vs2); - setArg(call_valid_reg_overlap_3212, 2, vd); - setArg(call_valid_reg_overlap_3212, 3, valid_reg_overlap_3212_arg2); - setArg(call_valid_reg_overlap_3212, 4, valid_reg_overlap_3212_arg3); - setRet(call_valid_reg_overlap_3212, 0, ret_val_valid_reg_overlap_3212); + InvokeNode* call_illegal_fp_variable_width_3226; + auto illegal_fp_variable_width_3226_arg2 = SEW; + auto illegal_fp_variable_width_3226_arg3 = rm; + auto illegal_fp_variable_width_3226_arg4 = SEW_widen; + auto illegal_fp_variable_width_3226_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3226 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3226, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3227; + auto valid_reg_overlap_3227_arg2 = LMUL_pow; + auto valid_reg_overlap_3227_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3227 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3227, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3228; + auto valid_reg_overlap_3228_arg2 = LMUL_pow; + auto valid_reg_overlap_3228_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3228 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3228, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3226, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3227)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3228)); + setArg(call_illegal_fp_variable_width_3226, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3226, 1, vd); + setArg(call_illegal_fp_variable_width_3226, 2, vm); + setArg(call_illegal_fp_variable_width_3226, 3, illegal_fp_variable_width_3226_arg2); + setArg(call_illegal_fp_variable_width_3226, 4, illegal_fp_variable_width_3226_arg3); + setArg(call_illegal_fp_variable_width_3226, 5, illegal_fp_variable_width_3226_arg4); + setArg(call_illegal_fp_variable_width_3226, 6, illegal_fp_variable_width_3226_arg5); + setRet(call_illegal_fp_variable_width_3226, 0, ret_val_illegal_fp_variable_width_3226); + setArg(call_valid_reg_overlap_3227, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3227, 1, vs1); + setArg(call_valid_reg_overlap_3227, 2, vd); + setArg(call_valid_reg_overlap_3227, 3, valid_reg_overlap_3227_arg2); + setArg(call_valid_reg_overlap_3227, 4, valid_reg_overlap_3227_arg3); + setRet(call_valid_reg_overlap_3227, 0, ret_val_valid_reg_overlap_3227); + setArg(call_valid_reg_overlap_3228, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3228, 1, vs2); + setArg(call_valid_reg_overlap_3228, 2, vd); + setArg(call_valid_reg_overlap_3228, 3, valid_reg_overlap_3228_arg2); + setArg(call_valid_reg_overlap_3228, 4, valid_reg_overlap_3228_arg3); + setRet(call_valid_reg_overlap_3228, 0, ret_val_valid_reg_overlap_3228); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75175,45 +74759,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3214; - x86::Gp ret_val_sew_3214 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3214, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3213; - auto fp_vector_vector_wv_3213_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3213_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3213_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3213_arg10 = rm; - auto fp_vector_vector_wv_3213_arg11 = ret_val_sew_3214; + InvokeNode* call_sew_3230; + x86::Gp ret_val_sew_3230 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3230, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3229; + auto fp_vector_vector_wv_3229_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3229_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3229_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3229_arg10 = rm; + auto fp_vector_vector_wv_3229_arg11 = ret_val_sew_3230; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3213, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3214, 0, reinterpret_cast(this)); - setRet(call_sew_3214, 0, ret_val_sew_3214); - setArg(call_fp_vector_vector_wv_3213, 0, V); - setArg(call_fp_vector_vector_wv_3213, 1, 48); - setArg(call_fp_vector_vector_wv_3213, 2, 1); - setArg(call_fp_vector_vector_wv_3213, 3, fp_vector_vector_wv_3213_arg3); - setArg(call_fp_vector_vector_wv_3213, 4, fp_vector_vector_wv_3213_arg4); - setArg(call_fp_vector_vector_wv_3213, 5, fp_vector_vector_wv_3213_arg5); - setArg(call_fp_vector_vector_wv_3213, 6, vm); - setArg(call_fp_vector_vector_wv_3213, 7, vd); - setArg(call_fp_vector_vector_wv_3213, 8, vs2); - setArg(call_fp_vector_vector_wv_3213, 9, vs1); - setArg(call_fp_vector_vector_wv_3213, 10, fp_vector_vector_wv_3213_arg10); - setArg(call_fp_vector_vector_wv_3213, 11, fp_vector_vector_wv_3213_arg11); - InvokeNode* call_fget_flags_3215; - x86::Gp ret_val_fget_flags_3215 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3215, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3215; - setRet(call_fget_flags_3215, 0, ret_val_fget_flags_3215); + cc.invoke(&call_fp_vector_vector_wv_3229, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3230, 0, reinterpret_cast(this)); + setRet(call_sew_3230, 0, ret_val_sew_3230); + setArg(call_fp_vector_vector_wv_3229, 0, V); + setArg(call_fp_vector_vector_wv_3229, 1, 48); + setArg(call_fp_vector_vector_wv_3229, 2, 1); + setArg(call_fp_vector_vector_wv_3229, 3, fp_vector_vector_wv_3229_arg3); + setArg(call_fp_vector_vector_wv_3229, 4, fp_vector_vector_wv_3229_arg4); + setArg(call_fp_vector_vector_wv_3229, 5, fp_vector_vector_wv_3229_arg5); + setArg(call_fp_vector_vector_wv_3229, 6, vm); + setArg(call_fp_vector_vector_wv_3229, 7, vd); + setArg(call_fp_vector_vector_wv_3229, 8, vs2); + setArg(call_fp_vector_vector_wv_3229, 9, vs1); + setArg(call_fp_vector_vector_wv_3229, 10, fp_vector_vector_wv_3229_arg10); + setArg(call_fp_vector_vector_wv_3229, 11, fp_vector_vector_wv_3229_arg11); + InvokeNode* call_fget_flags_3231; + x86::Gp ret_val_fget_flags_3231 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3231, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3231; + setRet(call_fget_flags_3231, 0, ret_val_fget_flags_3231); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3216 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3216, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3216, 32, false) - , traits::vstart); + auto tmp3232 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3232, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3232, traits::vstart); } cc.bind(label_merge); } @@ -75257,54 +74839,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3217; - x86::Gp ret_val_get_sew_pow_3217 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3217, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3218 = get_reg(cc, 8, false); - mov(cc, tmp3218, 1); + InvokeNode* call_get_sew_pow_3233; + x86::Gp ret_val_get_sew_pow_3233 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3233, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3234 = get_reg(cc, 8, false); + mov(cc, tmp3234, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3218, (ret_val_get_sew_pow_3217))), 8, false), ~ 1); - setArg(call_get_sew_pow_3217, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3217, 0, ret_val_get_sew_pow_3217); - InvokeNode* call_get_lmul_pow_3219; - x86::Gp ret_val_get_lmul_pow_3219 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3219, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3219; - setArg(call_get_lmul_pow_3219, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3219, 0, ret_val_get_lmul_pow_3219); + (gen_operation(cc, shl, tmp3234, (ret_val_get_sew_pow_3233))), 8, false), ~ 1); + setArg(call_get_sew_pow_3233, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3233, 0, ret_val_get_sew_pow_3233); + InvokeNode* call_get_lmul_pow_3235; + x86::Gp ret_val_get_lmul_pow_3235 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3235, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3235; + setArg(call_get_lmul_pow_3235, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3235, 0, ret_val_get_lmul_pow_3235); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3220; - auto illegal_fp_variable_width_3220_arg2 = SEW; - auto illegal_fp_variable_width_3220_arg3 = rm; - auto illegal_fp_variable_width_3220_arg4 = SEW_widen; - auto illegal_fp_variable_width_3220_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3220 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3220, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3221; - auto valid_reg_overlap_3221_arg2 = LMUL_pow; - auto valid_reg_overlap_3221_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3221 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3221, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3220, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3221)); - setArg(call_illegal_fp_variable_width_3220, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3220, 1, vd); - setArg(call_illegal_fp_variable_width_3220, 2, vm); - setArg(call_illegal_fp_variable_width_3220, 3, illegal_fp_variable_width_3220_arg2); - setArg(call_illegal_fp_variable_width_3220, 4, illegal_fp_variable_width_3220_arg3); - setArg(call_illegal_fp_variable_width_3220, 5, illegal_fp_variable_width_3220_arg4); - setArg(call_illegal_fp_variable_width_3220, 6, illegal_fp_variable_width_3220_arg5); - setRet(call_illegal_fp_variable_width_3220, 0, ret_val_illegal_fp_variable_width_3220); - setArg(call_valid_reg_overlap_3221, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3221, 1, vs2); - setArg(call_valid_reg_overlap_3221, 2, vd); - setArg(call_valid_reg_overlap_3221, 3, valid_reg_overlap_3221_arg2); - setArg(call_valid_reg_overlap_3221, 4, valid_reg_overlap_3221_arg3); - setRet(call_valid_reg_overlap_3221, 0, ret_val_valid_reg_overlap_3221); + InvokeNode* call_illegal_fp_variable_width_3236; + auto illegal_fp_variable_width_3236_arg2 = SEW; + auto illegal_fp_variable_width_3236_arg3 = rm; + auto illegal_fp_variable_width_3236_arg4 = SEW_widen; + auto illegal_fp_variable_width_3236_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3236 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3236, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3237; + auto valid_reg_overlap_3237_arg2 = LMUL_pow; + auto valid_reg_overlap_3237_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3237 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3237, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3236, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3237)); + setArg(call_illegal_fp_variable_width_3236, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3236, 1, vd); + setArg(call_illegal_fp_variable_width_3236, 2, vm); + setArg(call_illegal_fp_variable_width_3236, 3, illegal_fp_variable_width_3236_arg2); + setArg(call_illegal_fp_variable_width_3236, 4, illegal_fp_variable_width_3236_arg3); + setArg(call_illegal_fp_variable_width_3236, 5, illegal_fp_variable_width_3236_arg4); + setArg(call_illegal_fp_variable_width_3236, 6, illegal_fp_variable_width_3236_arg5); + setRet(call_illegal_fp_variable_width_3236, 0, ret_val_illegal_fp_variable_width_3236); + setArg(call_valid_reg_overlap_3237, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3237, 1, vs2); + setArg(call_valid_reg_overlap_3237, 2, vd); + setArg(call_valid_reg_overlap_3237, 3, valid_reg_overlap_3237_arg2); + setArg(call_valid_reg_overlap_3237, 4, valid_reg_overlap_3237_arg3); + setRet(call_valid_reg_overlap_3237, 0, ret_val_valid_reg_overlap_3237); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75320,47 +74902,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3223; - x86::Gp ret_val_sew_3223 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3223, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3222; - auto fp_vector_imm_wv_3222_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3222_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3222_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3222_arg9 = gen_ext(cc, + InvokeNode* call_sew_3239; + x86::Gp ret_val_sew_3239 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3239, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3238; + auto fp_vector_imm_wv_3238_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3238_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3238_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3238_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_wv_3222_arg10 = rm; - auto fp_vector_imm_wv_3222_arg11 = ret_val_sew_3223; + auto fp_vector_imm_wv_3238_arg10 = rm; + auto fp_vector_imm_wv_3238_arg11 = ret_val_sew_3239; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3222, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3223, 0, reinterpret_cast(this)); - setRet(call_sew_3223, 0, ret_val_sew_3223); - setArg(call_fp_vector_imm_wv_3222, 0, V); - setArg(call_fp_vector_imm_wv_3222, 1, 50); - setArg(call_fp_vector_imm_wv_3222, 2, 5); - setArg(call_fp_vector_imm_wv_3222, 3, fp_vector_imm_wv_3222_arg3); - setArg(call_fp_vector_imm_wv_3222, 4, fp_vector_imm_wv_3222_arg4); - setArg(call_fp_vector_imm_wv_3222, 5, fp_vector_imm_wv_3222_arg5); - setArg(call_fp_vector_imm_wv_3222, 6, vm); - setArg(call_fp_vector_imm_wv_3222, 7, vd); - setArg(call_fp_vector_imm_wv_3222, 8, vs2); - setArg(call_fp_vector_imm_wv_3222, 9, fp_vector_imm_wv_3222_arg9); - setArg(call_fp_vector_imm_wv_3222, 10, fp_vector_imm_wv_3222_arg10); - setArg(call_fp_vector_imm_wv_3222, 11, fp_vector_imm_wv_3222_arg11); - InvokeNode* call_fget_flags_3224; - x86::Gp ret_val_fget_flags_3224 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3224, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3224; - setRet(call_fget_flags_3224, 0, ret_val_fget_flags_3224); + cc.invoke(&call_fp_vector_imm_wv_3238, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3239, 0, reinterpret_cast(this)); + setRet(call_sew_3239, 0, ret_val_sew_3239); + setArg(call_fp_vector_imm_wv_3238, 0, V); + setArg(call_fp_vector_imm_wv_3238, 1, 50); + setArg(call_fp_vector_imm_wv_3238, 2, 5); + setArg(call_fp_vector_imm_wv_3238, 3, fp_vector_imm_wv_3238_arg3); + setArg(call_fp_vector_imm_wv_3238, 4, fp_vector_imm_wv_3238_arg4); + setArg(call_fp_vector_imm_wv_3238, 5, fp_vector_imm_wv_3238_arg5); + setArg(call_fp_vector_imm_wv_3238, 6, vm); + setArg(call_fp_vector_imm_wv_3238, 7, vd); + setArg(call_fp_vector_imm_wv_3238, 8, vs2); + setArg(call_fp_vector_imm_wv_3238, 9, fp_vector_imm_wv_3238_arg9); + setArg(call_fp_vector_imm_wv_3238, 10, fp_vector_imm_wv_3238_arg10); + setArg(call_fp_vector_imm_wv_3238, 11, fp_vector_imm_wv_3238_arg11); + InvokeNode* call_fget_flags_3240; + x86::Gp ret_val_fget_flags_3240 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3240, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3240; + setRet(call_fget_flags_3240, 0, ret_val_fget_flags_3240); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3225 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3225, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3225, 32, false) - , traits::vstart); + auto tmp3241 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3241, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3241, traits::vstart); } cc.bind(label_merge); } @@ -75404,65 +74984,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3226; - x86::Gp ret_val_get_sew_pow_3226 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3226, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3227 = get_reg(cc, 8, false); - mov(cc, tmp3227, 1); + InvokeNode* call_get_sew_pow_3242; + x86::Gp ret_val_get_sew_pow_3242 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3242, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3243 = get_reg(cc, 8, false); + mov(cc, tmp3243, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3227, (ret_val_get_sew_pow_3226))), 8, false), ~ 1); - setArg(call_get_sew_pow_3226, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3226, 0, ret_val_get_sew_pow_3226); - InvokeNode* call_get_lmul_pow_3228; - x86::Gp ret_val_get_lmul_pow_3228 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3228, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3228; - setArg(call_get_lmul_pow_3228, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3228, 0, ret_val_get_lmul_pow_3228); + (gen_operation(cc, shl, tmp3243, (ret_val_get_sew_pow_3242))), 8, false), ~ 1); + setArg(call_get_sew_pow_3242, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3242, 0, ret_val_get_sew_pow_3242); + InvokeNode* call_get_lmul_pow_3244; + x86::Gp ret_val_get_lmul_pow_3244 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3244, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3244; + setArg(call_get_lmul_pow_3244, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3244, 0, ret_val_get_lmul_pow_3244); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3229; - auto illegal_fp_variable_width_3229_arg2 = SEW; - auto illegal_fp_variable_width_3229_arg3 = rm; - auto illegal_fp_variable_width_3229_arg4 = SEW_widen; - auto illegal_fp_variable_width_3229_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3229 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3229, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3230; - auto valid_reg_overlap_3230_arg2 = LMUL_pow; - auto valid_reg_overlap_3230_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3230 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3230, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3231; - auto valid_reg_overlap_3231_arg2 = LMUL_pow; - auto valid_reg_overlap_3231_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3231 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3231, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3229, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3230)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3231)); - setArg(call_illegal_fp_variable_width_3229, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3229, 1, vd); - setArg(call_illegal_fp_variable_width_3229, 2, vm); - setArg(call_illegal_fp_variable_width_3229, 3, illegal_fp_variable_width_3229_arg2); - setArg(call_illegal_fp_variable_width_3229, 4, illegal_fp_variable_width_3229_arg3); - setArg(call_illegal_fp_variable_width_3229, 5, illegal_fp_variable_width_3229_arg4); - setArg(call_illegal_fp_variable_width_3229, 6, illegal_fp_variable_width_3229_arg5); - setRet(call_illegal_fp_variable_width_3229, 0, ret_val_illegal_fp_variable_width_3229); - setArg(call_valid_reg_overlap_3230, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3230, 1, vs1); - setArg(call_valid_reg_overlap_3230, 2, vd); - setArg(call_valid_reg_overlap_3230, 3, valid_reg_overlap_3230_arg2); - setArg(call_valid_reg_overlap_3230, 4, valid_reg_overlap_3230_arg3); - setRet(call_valid_reg_overlap_3230, 0, ret_val_valid_reg_overlap_3230); - setArg(call_valid_reg_overlap_3231, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3231, 1, vs2); - setArg(call_valid_reg_overlap_3231, 2, vd); - setArg(call_valid_reg_overlap_3231, 3, valid_reg_overlap_3231_arg2); - setArg(call_valid_reg_overlap_3231, 4, valid_reg_overlap_3231_arg3); - setRet(call_valid_reg_overlap_3231, 0, ret_val_valid_reg_overlap_3231); + InvokeNode* call_illegal_fp_variable_width_3245; + auto illegal_fp_variable_width_3245_arg2 = SEW; + auto illegal_fp_variable_width_3245_arg3 = rm; + auto illegal_fp_variable_width_3245_arg4 = SEW_widen; + auto illegal_fp_variable_width_3245_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3245 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3245, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3246; + auto valid_reg_overlap_3246_arg2 = LMUL_pow; + auto valid_reg_overlap_3246_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3246 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3246, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3247; + auto valid_reg_overlap_3247_arg2 = LMUL_pow; + auto valid_reg_overlap_3247_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3247 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3247, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3245, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3246)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3247)); + setArg(call_illegal_fp_variable_width_3245, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3245, 1, vd); + setArg(call_illegal_fp_variable_width_3245, 2, vm); + setArg(call_illegal_fp_variable_width_3245, 3, illegal_fp_variable_width_3245_arg2); + setArg(call_illegal_fp_variable_width_3245, 4, illegal_fp_variable_width_3245_arg3); + setArg(call_illegal_fp_variable_width_3245, 5, illegal_fp_variable_width_3245_arg4); + setArg(call_illegal_fp_variable_width_3245, 6, illegal_fp_variable_width_3245_arg5); + setRet(call_illegal_fp_variable_width_3245, 0, ret_val_illegal_fp_variable_width_3245); + setArg(call_valid_reg_overlap_3246, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3246, 1, vs1); + setArg(call_valid_reg_overlap_3246, 2, vd); + setArg(call_valid_reg_overlap_3246, 3, valid_reg_overlap_3246_arg2); + setArg(call_valid_reg_overlap_3246, 4, valid_reg_overlap_3246_arg3); + setRet(call_valid_reg_overlap_3246, 0, ret_val_valid_reg_overlap_3246); + setArg(call_valid_reg_overlap_3247, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3247, 1, vs2); + setArg(call_valid_reg_overlap_3247, 2, vd); + setArg(call_valid_reg_overlap_3247, 3, valid_reg_overlap_3247_arg2); + setArg(call_valid_reg_overlap_3247, 4, valid_reg_overlap_3247_arg3); + setRet(call_valid_reg_overlap_3247, 0, ret_val_valid_reg_overlap_3247); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75478,45 +75058,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3233; - x86::Gp ret_val_sew_3233 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3233, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3232; - auto fp_vector_vector_wv_3232_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3232_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3232_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3232_arg10 = rm; - auto fp_vector_vector_wv_3232_arg11 = ret_val_sew_3233; + InvokeNode* call_sew_3249; + x86::Gp ret_val_sew_3249 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3249, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3248; + auto fp_vector_vector_wv_3248_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3248_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3248_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3248_arg10 = rm; + auto fp_vector_vector_wv_3248_arg11 = ret_val_sew_3249; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3232, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3233, 0, reinterpret_cast(this)); - setRet(call_sew_3233, 0, ret_val_sew_3233); - setArg(call_fp_vector_vector_wv_3232, 0, V); - setArg(call_fp_vector_vector_wv_3232, 1, 50); - setArg(call_fp_vector_vector_wv_3232, 2, 1); - setArg(call_fp_vector_vector_wv_3232, 3, fp_vector_vector_wv_3232_arg3); - setArg(call_fp_vector_vector_wv_3232, 4, fp_vector_vector_wv_3232_arg4); - setArg(call_fp_vector_vector_wv_3232, 5, fp_vector_vector_wv_3232_arg5); - setArg(call_fp_vector_vector_wv_3232, 6, vm); - setArg(call_fp_vector_vector_wv_3232, 7, vd); - setArg(call_fp_vector_vector_wv_3232, 8, vs2); - setArg(call_fp_vector_vector_wv_3232, 9, vs1); - setArg(call_fp_vector_vector_wv_3232, 10, fp_vector_vector_wv_3232_arg10); - setArg(call_fp_vector_vector_wv_3232, 11, fp_vector_vector_wv_3232_arg11); - InvokeNode* call_fget_flags_3234; - x86::Gp ret_val_fget_flags_3234 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3234, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3234; - setRet(call_fget_flags_3234, 0, ret_val_fget_flags_3234); + cc.invoke(&call_fp_vector_vector_wv_3248, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3249, 0, reinterpret_cast(this)); + setRet(call_sew_3249, 0, ret_val_sew_3249); + setArg(call_fp_vector_vector_wv_3248, 0, V); + setArg(call_fp_vector_vector_wv_3248, 1, 50); + setArg(call_fp_vector_vector_wv_3248, 2, 1); + setArg(call_fp_vector_vector_wv_3248, 3, fp_vector_vector_wv_3248_arg3); + setArg(call_fp_vector_vector_wv_3248, 4, fp_vector_vector_wv_3248_arg4); + setArg(call_fp_vector_vector_wv_3248, 5, fp_vector_vector_wv_3248_arg5); + setArg(call_fp_vector_vector_wv_3248, 6, vm); + setArg(call_fp_vector_vector_wv_3248, 7, vd); + setArg(call_fp_vector_vector_wv_3248, 8, vs2); + setArg(call_fp_vector_vector_wv_3248, 9, vs1); + setArg(call_fp_vector_vector_wv_3248, 10, fp_vector_vector_wv_3248_arg10); + setArg(call_fp_vector_vector_wv_3248, 11, fp_vector_vector_wv_3248_arg11); + InvokeNode* call_fget_flags_3250; + x86::Gp ret_val_fget_flags_3250 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3250, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3250; + setRet(call_fget_flags_3250, 0, ret_val_fget_flags_3250); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3235 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3235, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3235, 32, false) - , traits::vstart); + auto tmp3251 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3251, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3251, traits::vstart); } cc.bind(label_merge); } @@ -75560,43 +75138,43 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3236; - x86::Gp ret_val_get_sew_pow_3236 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3236, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3237 = get_reg(cc, 8, false); - mov(cc, tmp3237, 1); + InvokeNode* call_get_sew_pow_3252; + x86::Gp ret_val_get_sew_pow_3252 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3252, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3253 = get_reg(cc, 8, false); + mov(cc, tmp3253, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3237, (ret_val_get_sew_pow_3236))), 8, false), ~ 1); - setArg(call_get_sew_pow_3236, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3236, 0, ret_val_get_sew_pow_3236); - InvokeNode* call_get_lmul_pow_3238; - x86::Gp ret_val_get_lmul_pow_3238 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3238, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3238; - setArg(call_get_lmul_pow_3238, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3238, 0, ret_val_get_lmul_pow_3238); + (gen_operation(cc, shl, tmp3253, (ret_val_get_sew_pow_3252))), 8, false), ~ 1); + setArg(call_get_sew_pow_3252, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3252, 0, ret_val_get_sew_pow_3252); + InvokeNode* call_get_lmul_pow_3254; + x86::Gp ret_val_get_lmul_pow_3254 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3254, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3254; + setArg(call_get_lmul_pow_3254, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3254, 0, ret_val_get_lmul_pow_3254); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3239; - auto illegal_fp_variable_width_3239_arg2 = SEW; - auto illegal_fp_variable_width_3239_arg3 = rm; - auto illegal_fp_variable_width_3239_arg4 = SEW_widen; - auto illegal_fp_variable_width_3239_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3239 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3239, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - auto cond = ret_val_illegal_fp_variable_width_3239; - setArg(call_illegal_fp_variable_width_3239, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3239, 1, vd); - setArg(call_illegal_fp_variable_width_3239, 2, vm); - setArg(call_illegal_fp_variable_width_3239, 3, illegal_fp_variable_width_3239_arg2); - setArg(call_illegal_fp_variable_width_3239, 4, illegal_fp_variable_width_3239_arg3); - setArg(call_illegal_fp_variable_width_3239, 5, illegal_fp_variable_width_3239_arg4); - setArg(call_illegal_fp_variable_width_3239, 6, illegal_fp_variable_width_3239_arg5); - setRet(call_illegal_fp_variable_width_3239, 0, ret_val_illegal_fp_variable_width_3239); + InvokeNode* call_illegal_fp_variable_width_3255; + auto illegal_fp_variable_width_3255_arg2 = SEW; + auto illegal_fp_variable_width_3255_arg3 = rm; + auto illegal_fp_variable_width_3255_arg4 = SEW_widen; + auto illegal_fp_variable_width_3255_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3255 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3255, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_fp_variable_width_3255; + setArg(call_illegal_fp_variable_width_3255, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3255, 1, vd); + setArg(call_illegal_fp_variable_width_3255, 2, vm); + setArg(call_illegal_fp_variable_width_3255, 3, illegal_fp_variable_width_3255_arg2); + setArg(call_illegal_fp_variable_width_3255, 4, illegal_fp_variable_width_3255_arg3); + setArg(call_illegal_fp_variable_width_3255, 5, illegal_fp_variable_width_3255_arg4); + setArg(call_illegal_fp_variable_width_3255, 6, illegal_fp_variable_width_3255_arg5); + setRet(call_illegal_fp_variable_width_3255, 0, ret_val_illegal_fp_variable_width_3255); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75612,47 +75190,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3241; - x86::Gp ret_val_sew_3241 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3241, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_ww_3240; - auto fp_vector_imm_ww_3240_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_ww_3240_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_ww_3240_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_ww_3240_arg9 = gen_ext(cc, + InvokeNode* call_sew_3257; + x86::Gp ret_val_sew_3257 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3257, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_ww_3256; + auto fp_vector_imm_ww_3256_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_ww_3256_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_ww_3256_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_ww_3256_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_ww_3240_arg10 = rm; - auto fp_vector_imm_ww_3240_arg11 = ret_val_sew_3241; + auto fp_vector_imm_ww_3256_arg10 = rm; + auto fp_vector_imm_ww_3256_arg11 = ret_val_sew_3257; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_ww_3240, &fp_vector_imm_ww, FuncSignature::build()); - setArg(call_sew_3241, 0, reinterpret_cast(this)); - setRet(call_sew_3241, 0, ret_val_sew_3241); - setArg(call_fp_vector_imm_ww_3240, 0, V); - setArg(call_fp_vector_imm_ww_3240, 1, 52); - setArg(call_fp_vector_imm_ww_3240, 2, 5); - setArg(call_fp_vector_imm_ww_3240, 3, fp_vector_imm_ww_3240_arg3); - setArg(call_fp_vector_imm_ww_3240, 4, fp_vector_imm_ww_3240_arg4); - setArg(call_fp_vector_imm_ww_3240, 5, fp_vector_imm_ww_3240_arg5); - setArg(call_fp_vector_imm_ww_3240, 6, vm); - setArg(call_fp_vector_imm_ww_3240, 7, vd); - setArg(call_fp_vector_imm_ww_3240, 8, vs2); - setArg(call_fp_vector_imm_ww_3240, 9, fp_vector_imm_ww_3240_arg9); - setArg(call_fp_vector_imm_ww_3240, 10, fp_vector_imm_ww_3240_arg10); - setArg(call_fp_vector_imm_ww_3240, 11, fp_vector_imm_ww_3240_arg11); - InvokeNode* call_fget_flags_3242; - x86::Gp ret_val_fget_flags_3242 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3242, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3242; - setRet(call_fget_flags_3242, 0, ret_val_fget_flags_3242); + cc.invoke(&call_fp_vector_imm_ww_3256, &fp_vector_imm_ww, FuncSignature::build()); + setArg(call_sew_3257, 0, reinterpret_cast(this)); + setRet(call_sew_3257, 0, ret_val_sew_3257); + setArg(call_fp_vector_imm_ww_3256, 0, V); + setArg(call_fp_vector_imm_ww_3256, 1, 52); + setArg(call_fp_vector_imm_ww_3256, 2, 5); + setArg(call_fp_vector_imm_ww_3256, 3, fp_vector_imm_ww_3256_arg3); + setArg(call_fp_vector_imm_ww_3256, 4, fp_vector_imm_ww_3256_arg4); + setArg(call_fp_vector_imm_ww_3256, 5, fp_vector_imm_ww_3256_arg5); + setArg(call_fp_vector_imm_ww_3256, 6, vm); + setArg(call_fp_vector_imm_ww_3256, 7, vd); + setArg(call_fp_vector_imm_ww_3256, 8, vs2); + setArg(call_fp_vector_imm_ww_3256, 9, fp_vector_imm_ww_3256_arg9); + setArg(call_fp_vector_imm_ww_3256, 10, fp_vector_imm_ww_3256_arg10); + setArg(call_fp_vector_imm_ww_3256, 11, fp_vector_imm_ww_3256_arg11); + InvokeNode* call_fget_flags_3258; + x86::Gp ret_val_fget_flags_3258 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3258, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3258; + setRet(call_fget_flags_3258, 0, ret_val_fget_flags_3258); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3243 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3243, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3243, 32, false) - , traits::vstart); + auto tmp3259 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3259, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3259, traits::vstart); } cc.bind(label_merge); } @@ -75696,54 +75272,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3244; - x86::Gp ret_val_get_sew_pow_3244 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3244, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3245 = get_reg(cc, 8, false); - mov(cc, tmp3245, 1); + InvokeNode* call_get_sew_pow_3260; + x86::Gp ret_val_get_sew_pow_3260 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3260, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3261 = get_reg(cc, 8, false); + mov(cc, tmp3261, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3245, (ret_val_get_sew_pow_3244))), 8, false), ~ 1); - setArg(call_get_sew_pow_3244, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3244, 0, ret_val_get_sew_pow_3244); - InvokeNode* call_get_lmul_pow_3246; - x86::Gp ret_val_get_lmul_pow_3246 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3246, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3246; - setArg(call_get_lmul_pow_3246, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3246, 0, ret_val_get_lmul_pow_3246); + (gen_operation(cc, shl, tmp3261, (ret_val_get_sew_pow_3260))), 8, false), ~ 1); + setArg(call_get_sew_pow_3260, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3260, 0, ret_val_get_sew_pow_3260); + InvokeNode* call_get_lmul_pow_3262; + x86::Gp ret_val_get_lmul_pow_3262 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3262, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3262; + setArg(call_get_lmul_pow_3262, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3262, 0, ret_val_get_lmul_pow_3262); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3247; - auto illegal_fp_variable_width_3247_arg2 = SEW; - auto illegal_fp_variable_width_3247_arg3 = rm; - auto illegal_fp_variable_width_3247_arg4 = SEW_widen; - auto illegal_fp_variable_width_3247_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3247 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3247, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3248; - auto valid_reg_overlap_3248_arg2 = LMUL_pow; - auto valid_reg_overlap_3248_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3248 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3248, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3247, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3248)); - setArg(call_illegal_fp_variable_width_3247, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3247, 1, vd); - setArg(call_illegal_fp_variable_width_3247, 2, vm); - setArg(call_illegal_fp_variable_width_3247, 3, illegal_fp_variable_width_3247_arg2); - setArg(call_illegal_fp_variable_width_3247, 4, illegal_fp_variable_width_3247_arg3); - setArg(call_illegal_fp_variable_width_3247, 5, illegal_fp_variable_width_3247_arg4); - setArg(call_illegal_fp_variable_width_3247, 6, illegal_fp_variable_width_3247_arg5); - setRet(call_illegal_fp_variable_width_3247, 0, ret_val_illegal_fp_variable_width_3247); - setArg(call_valid_reg_overlap_3248, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3248, 1, vs1); - setArg(call_valid_reg_overlap_3248, 2, vd); - setArg(call_valid_reg_overlap_3248, 3, valid_reg_overlap_3248_arg2); - setArg(call_valid_reg_overlap_3248, 4, valid_reg_overlap_3248_arg3); - setRet(call_valid_reg_overlap_3248, 0, ret_val_valid_reg_overlap_3248); + InvokeNode* call_illegal_fp_variable_width_3263; + auto illegal_fp_variable_width_3263_arg2 = SEW; + auto illegal_fp_variable_width_3263_arg3 = rm; + auto illegal_fp_variable_width_3263_arg4 = SEW_widen; + auto illegal_fp_variable_width_3263_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3263 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3263, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3264; + auto valid_reg_overlap_3264_arg2 = LMUL_pow; + auto valid_reg_overlap_3264_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3264 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3264, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3263, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3264)); + setArg(call_illegal_fp_variable_width_3263, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3263, 1, vd); + setArg(call_illegal_fp_variable_width_3263, 2, vm); + setArg(call_illegal_fp_variable_width_3263, 3, illegal_fp_variable_width_3263_arg2); + setArg(call_illegal_fp_variable_width_3263, 4, illegal_fp_variable_width_3263_arg3); + setArg(call_illegal_fp_variable_width_3263, 5, illegal_fp_variable_width_3263_arg4); + setArg(call_illegal_fp_variable_width_3263, 6, illegal_fp_variable_width_3263_arg5); + setRet(call_illegal_fp_variable_width_3263, 0, ret_val_illegal_fp_variable_width_3263); + setArg(call_valid_reg_overlap_3264, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3264, 1, vs1); + setArg(call_valid_reg_overlap_3264, 2, vd); + setArg(call_valid_reg_overlap_3264, 3, valid_reg_overlap_3264_arg2); + setArg(call_valid_reg_overlap_3264, 4, valid_reg_overlap_3264_arg3); + setRet(call_valid_reg_overlap_3264, 0, ret_val_valid_reg_overlap_3264); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75759,45 +75335,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3250; - x86::Gp ret_val_sew_3250 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3250, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_ww_3249; - auto fp_vector_vector_ww_3249_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_ww_3249_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_ww_3249_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_ww_3249_arg10 = rm; - auto fp_vector_vector_ww_3249_arg11 = ret_val_sew_3250; + InvokeNode* call_sew_3266; + x86::Gp ret_val_sew_3266 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3266, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_ww_3265; + auto fp_vector_vector_ww_3265_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_ww_3265_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_ww_3265_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_ww_3265_arg10 = rm; + auto fp_vector_vector_ww_3265_arg11 = ret_val_sew_3266; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_ww_3249, &fp_vector_vector_ww, FuncSignature::build()); - setArg(call_sew_3250, 0, reinterpret_cast(this)); - setRet(call_sew_3250, 0, ret_val_sew_3250); - setArg(call_fp_vector_vector_ww_3249, 0, V); - setArg(call_fp_vector_vector_ww_3249, 1, 52); - setArg(call_fp_vector_vector_ww_3249, 2, 1); - setArg(call_fp_vector_vector_ww_3249, 3, fp_vector_vector_ww_3249_arg3); - setArg(call_fp_vector_vector_ww_3249, 4, fp_vector_vector_ww_3249_arg4); - setArg(call_fp_vector_vector_ww_3249, 5, fp_vector_vector_ww_3249_arg5); - setArg(call_fp_vector_vector_ww_3249, 6, vm); - setArg(call_fp_vector_vector_ww_3249, 7, vd); - setArg(call_fp_vector_vector_ww_3249, 8, vs2); - setArg(call_fp_vector_vector_ww_3249, 9, vs1); - setArg(call_fp_vector_vector_ww_3249, 10, fp_vector_vector_ww_3249_arg10); - setArg(call_fp_vector_vector_ww_3249, 11, fp_vector_vector_ww_3249_arg11); - InvokeNode* call_fget_flags_3251; - x86::Gp ret_val_fget_flags_3251 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3251, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3251; - setRet(call_fget_flags_3251, 0, ret_val_fget_flags_3251); + cc.invoke(&call_fp_vector_vector_ww_3265, &fp_vector_vector_ww, FuncSignature::build()); + setArg(call_sew_3266, 0, reinterpret_cast(this)); + setRet(call_sew_3266, 0, ret_val_sew_3266); + setArg(call_fp_vector_vector_ww_3265, 0, V); + setArg(call_fp_vector_vector_ww_3265, 1, 52); + setArg(call_fp_vector_vector_ww_3265, 2, 1); + setArg(call_fp_vector_vector_ww_3265, 3, fp_vector_vector_ww_3265_arg3); + setArg(call_fp_vector_vector_ww_3265, 4, fp_vector_vector_ww_3265_arg4); + setArg(call_fp_vector_vector_ww_3265, 5, fp_vector_vector_ww_3265_arg5); + setArg(call_fp_vector_vector_ww_3265, 6, vm); + setArg(call_fp_vector_vector_ww_3265, 7, vd); + setArg(call_fp_vector_vector_ww_3265, 8, vs2); + setArg(call_fp_vector_vector_ww_3265, 9, vs1); + setArg(call_fp_vector_vector_ww_3265, 10, fp_vector_vector_ww_3265_arg10); + setArg(call_fp_vector_vector_ww_3265, 11, fp_vector_vector_ww_3265_arg11); + InvokeNode* call_fget_flags_3267; + x86::Gp ret_val_fget_flags_3267 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3267, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3267; + setRet(call_fget_flags_3267, 0, ret_val_fget_flags_3267); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3252 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3252, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3252, 32, false) - , traits::vstart); + auto tmp3268 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3268, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3268, traits::vstart); } cc.bind(label_merge); } @@ -75841,43 +75415,43 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3253; - x86::Gp ret_val_get_sew_pow_3253 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3253, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3254 = get_reg(cc, 8, false); - mov(cc, tmp3254, 1); + InvokeNode* call_get_sew_pow_3269; + x86::Gp ret_val_get_sew_pow_3269 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3269, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3270 = get_reg(cc, 8, false); + mov(cc, tmp3270, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3254, (ret_val_get_sew_pow_3253))), 8, false), ~ 1); - setArg(call_get_sew_pow_3253, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3253, 0, ret_val_get_sew_pow_3253); - InvokeNode* call_get_lmul_pow_3255; - x86::Gp ret_val_get_lmul_pow_3255 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3255, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3255; - setArg(call_get_lmul_pow_3255, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3255, 0, ret_val_get_lmul_pow_3255); + (gen_operation(cc, shl, tmp3270, (ret_val_get_sew_pow_3269))), 8, false), ~ 1); + setArg(call_get_sew_pow_3269, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3269, 0, ret_val_get_sew_pow_3269); + InvokeNode* call_get_lmul_pow_3271; + x86::Gp ret_val_get_lmul_pow_3271 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3271, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3271; + setArg(call_get_lmul_pow_3271, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3271, 0, ret_val_get_lmul_pow_3271); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3256; - auto illegal_fp_variable_width_3256_arg2 = SEW; - auto illegal_fp_variable_width_3256_arg3 = rm; - auto illegal_fp_variable_width_3256_arg4 = SEW_widen; - auto illegal_fp_variable_width_3256_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3256 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3256, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - auto cond = ret_val_illegal_fp_variable_width_3256; - setArg(call_illegal_fp_variable_width_3256, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3256, 1, vd); - setArg(call_illegal_fp_variable_width_3256, 2, vm); - setArg(call_illegal_fp_variable_width_3256, 3, illegal_fp_variable_width_3256_arg2); - setArg(call_illegal_fp_variable_width_3256, 4, illegal_fp_variable_width_3256_arg3); - setArg(call_illegal_fp_variable_width_3256, 5, illegal_fp_variable_width_3256_arg4); - setArg(call_illegal_fp_variable_width_3256, 6, illegal_fp_variable_width_3256_arg5); - setRet(call_illegal_fp_variable_width_3256, 0, ret_val_illegal_fp_variable_width_3256); + InvokeNode* call_illegal_fp_variable_width_3272; + auto illegal_fp_variable_width_3272_arg2 = SEW; + auto illegal_fp_variable_width_3272_arg3 = rm; + auto illegal_fp_variable_width_3272_arg4 = SEW_widen; + auto illegal_fp_variable_width_3272_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3272 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3272, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_fp_variable_width_3272; + setArg(call_illegal_fp_variable_width_3272, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3272, 1, vd); + setArg(call_illegal_fp_variable_width_3272, 2, vm); + setArg(call_illegal_fp_variable_width_3272, 3, illegal_fp_variable_width_3272_arg2); + setArg(call_illegal_fp_variable_width_3272, 4, illegal_fp_variable_width_3272_arg3); + setArg(call_illegal_fp_variable_width_3272, 5, illegal_fp_variable_width_3272_arg4); + setArg(call_illegal_fp_variable_width_3272, 6, illegal_fp_variable_width_3272_arg5); + setRet(call_illegal_fp_variable_width_3272, 0, ret_val_illegal_fp_variable_width_3272); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75893,47 +75467,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3258; - x86::Gp ret_val_sew_3258 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3258, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_ww_3257; - auto fp_vector_imm_ww_3257_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_ww_3257_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_ww_3257_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_ww_3257_arg9 = gen_ext(cc, + InvokeNode* call_sew_3274; + x86::Gp ret_val_sew_3274 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3274, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_ww_3273; + auto fp_vector_imm_ww_3273_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_ww_3273_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_ww_3273_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_ww_3273_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_ww_3257_arg10 = rm; - auto fp_vector_imm_ww_3257_arg11 = ret_val_sew_3258; + auto fp_vector_imm_ww_3273_arg10 = rm; + auto fp_vector_imm_ww_3273_arg11 = ret_val_sew_3274; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_ww_3257, &fp_vector_imm_ww, FuncSignature::build()); - setArg(call_sew_3258, 0, reinterpret_cast(this)); - setRet(call_sew_3258, 0, ret_val_sew_3258); - setArg(call_fp_vector_imm_ww_3257, 0, V); - setArg(call_fp_vector_imm_ww_3257, 1, 54); - setArg(call_fp_vector_imm_ww_3257, 2, 5); - setArg(call_fp_vector_imm_ww_3257, 3, fp_vector_imm_ww_3257_arg3); - setArg(call_fp_vector_imm_ww_3257, 4, fp_vector_imm_ww_3257_arg4); - setArg(call_fp_vector_imm_ww_3257, 5, fp_vector_imm_ww_3257_arg5); - setArg(call_fp_vector_imm_ww_3257, 6, vm); - setArg(call_fp_vector_imm_ww_3257, 7, vd); - setArg(call_fp_vector_imm_ww_3257, 8, vs2); - setArg(call_fp_vector_imm_ww_3257, 9, fp_vector_imm_ww_3257_arg9); - setArg(call_fp_vector_imm_ww_3257, 10, fp_vector_imm_ww_3257_arg10); - setArg(call_fp_vector_imm_ww_3257, 11, fp_vector_imm_ww_3257_arg11); - InvokeNode* call_fget_flags_3259; - x86::Gp ret_val_fget_flags_3259 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3259, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3259; - setRet(call_fget_flags_3259, 0, ret_val_fget_flags_3259); + cc.invoke(&call_fp_vector_imm_ww_3273, &fp_vector_imm_ww, FuncSignature::build()); + setArg(call_sew_3274, 0, reinterpret_cast(this)); + setRet(call_sew_3274, 0, ret_val_sew_3274); + setArg(call_fp_vector_imm_ww_3273, 0, V); + setArg(call_fp_vector_imm_ww_3273, 1, 54); + setArg(call_fp_vector_imm_ww_3273, 2, 5); + setArg(call_fp_vector_imm_ww_3273, 3, fp_vector_imm_ww_3273_arg3); + setArg(call_fp_vector_imm_ww_3273, 4, fp_vector_imm_ww_3273_arg4); + setArg(call_fp_vector_imm_ww_3273, 5, fp_vector_imm_ww_3273_arg5); + setArg(call_fp_vector_imm_ww_3273, 6, vm); + setArg(call_fp_vector_imm_ww_3273, 7, vd); + setArg(call_fp_vector_imm_ww_3273, 8, vs2); + setArg(call_fp_vector_imm_ww_3273, 9, fp_vector_imm_ww_3273_arg9); + setArg(call_fp_vector_imm_ww_3273, 10, fp_vector_imm_ww_3273_arg10); + setArg(call_fp_vector_imm_ww_3273, 11, fp_vector_imm_ww_3273_arg11); + InvokeNode* call_fget_flags_3275; + x86::Gp ret_val_fget_flags_3275 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3275, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3275; + setRet(call_fget_flags_3275, 0, ret_val_fget_flags_3275); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3260 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3260, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3260, 32, false) - , traits::vstart); + auto tmp3276 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3276, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3276, traits::vstart); } cc.bind(label_merge); } @@ -75977,54 +75549,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3261; - x86::Gp ret_val_get_sew_pow_3261 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3261, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3262 = get_reg(cc, 8, false); - mov(cc, tmp3262, 1); + InvokeNode* call_get_sew_pow_3277; + x86::Gp ret_val_get_sew_pow_3277 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3277, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3278 = get_reg(cc, 8, false); + mov(cc, tmp3278, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3262, (ret_val_get_sew_pow_3261))), 8, false), ~ 1); - setArg(call_get_sew_pow_3261, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3261, 0, ret_val_get_sew_pow_3261); - InvokeNode* call_get_lmul_pow_3263; - x86::Gp ret_val_get_lmul_pow_3263 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3263, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3263; - setArg(call_get_lmul_pow_3263, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3263, 0, ret_val_get_lmul_pow_3263); + (gen_operation(cc, shl, tmp3278, (ret_val_get_sew_pow_3277))), 8, false), ~ 1); + setArg(call_get_sew_pow_3277, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3277, 0, ret_val_get_sew_pow_3277); + InvokeNode* call_get_lmul_pow_3279; + x86::Gp ret_val_get_lmul_pow_3279 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3279, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3279; + setArg(call_get_lmul_pow_3279, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3279, 0, ret_val_get_lmul_pow_3279); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3264; - auto illegal_fp_variable_width_3264_arg2 = SEW; - auto illegal_fp_variable_width_3264_arg3 = rm; - auto illegal_fp_variable_width_3264_arg4 = SEW_widen; - auto illegal_fp_variable_width_3264_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3264 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3264, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3265; - auto valid_reg_overlap_3265_arg2 = LMUL_pow; - auto valid_reg_overlap_3265_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3265 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3265, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3264, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3265)); - setArg(call_illegal_fp_variable_width_3264, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3264, 1, vd); - setArg(call_illegal_fp_variable_width_3264, 2, vm); - setArg(call_illegal_fp_variable_width_3264, 3, illegal_fp_variable_width_3264_arg2); - setArg(call_illegal_fp_variable_width_3264, 4, illegal_fp_variable_width_3264_arg3); - setArg(call_illegal_fp_variable_width_3264, 5, illegal_fp_variable_width_3264_arg4); - setArg(call_illegal_fp_variable_width_3264, 6, illegal_fp_variable_width_3264_arg5); - setRet(call_illegal_fp_variable_width_3264, 0, ret_val_illegal_fp_variable_width_3264); - setArg(call_valid_reg_overlap_3265, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3265, 1, vs1); - setArg(call_valid_reg_overlap_3265, 2, vd); - setArg(call_valid_reg_overlap_3265, 3, valid_reg_overlap_3265_arg2); - setArg(call_valid_reg_overlap_3265, 4, valid_reg_overlap_3265_arg3); - setRet(call_valid_reg_overlap_3265, 0, ret_val_valid_reg_overlap_3265); + InvokeNode* call_illegal_fp_variable_width_3280; + auto illegal_fp_variable_width_3280_arg2 = SEW; + auto illegal_fp_variable_width_3280_arg3 = rm; + auto illegal_fp_variable_width_3280_arg4 = SEW_widen; + auto illegal_fp_variable_width_3280_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3280 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3280, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3281; + auto valid_reg_overlap_3281_arg2 = LMUL_pow; + auto valid_reg_overlap_3281_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3281 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3281, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3280, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3281)); + setArg(call_illegal_fp_variable_width_3280, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3280, 1, vd); + setArg(call_illegal_fp_variable_width_3280, 2, vm); + setArg(call_illegal_fp_variable_width_3280, 3, illegal_fp_variable_width_3280_arg2); + setArg(call_illegal_fp_variable_width_3280, 4, illegal_fp_variable_width_3280_arg3); + setArg(call_illegal_fp_variable_width_3280, 5, illegal_fp_variable_width_3280_arg4); + setArg(call_illegal_fp_variable_width_3280, 6, illegal_fp_variable_width_3280_arg5); + setRet(call_illegal_fp_variable_width_3280, 0, ret_val_illegal_fp_variable_width_3280); + setArg(call_valid_reg_overlap_3281, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3281, 1, vs1); + setArg(call_valid_reg_overlap_3281, 2, vd); + setArg(call_valid_reg_overlap_3281, 3, valid_reg_overlap_3281_arg2); + setArg(call_valid_reg_overlap_3281, 4, valid_reg_overlap_3281_arg3); + setRet(call_valid_reg_overlap_3281, 0, ret_val_valid_reg_overlap_3281); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76040,45 +75612,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3267; - x86::Gp ret_val_sew_3267 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3267, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_ww_3266; - auto fp_vector_vector_ww_3266_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_ww_3266_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_ww_3266_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_ww_3266_arg10 = rm; - auto fp_vector_vector_ww_3266_arg11 = ret_val_sew_3267; + InvokeNode* call_sew_3283; + x86::Gp ret_val_sew_3283 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3283, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_ww_3282; + auto fp_vector_vector_ww_3282_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_ww_3282_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_ww_3282_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_ww_3282_arg10 = rm; + auto fp_vector_vector_ww_3282_arg11 = ret_val_sew_3283; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_ww_3266, &fp_vector_vector_ww, FuncSignature::build()); - setArg(call_sew_3267, 0, reinterpret_cast(this)); - setRet(call_sew_3267, 0, ret_val_sew_3267); - setArg(call_fp_vector_vector_ww_3266, 0, V); - setArg(call_fp_vector_vector_ww_3266, 1, 54); - setArg(call_fp_vector_vector_ww_3266, 2, 1); - setArg(call_fp_vector_vector_ww_3266, 3, fp_vector_vector_ww_3266_arg3); - setArg(call_fp_vector_vector_ww_3266, 4, fp_vector_vector_ww_3266_arg4); - setArg(call_fp_vector_vector_ww_3266, 5, fp_vector_vector_ww_3266_arg5); - setArg(call_fp_vector_vector_ww_3266, 6, vm); - setArg(call_fp_vector_vector_ww_3266, 7, vd); - setArg(call_fp_vector_vector_ww_3266, 8, vs2); - setArg(call_fp_vector_vector_ww_3266, 9, vs1); - setArg(call_fp_vector_vector_ww_3266, 10, fp_vector_vector_ww_3266_arg10); - setArg(call_fp_vector_vector_ww_3266, 11, fp_vector_vector_ww_3266_arg11); - InvokeNode* call_fget_flags_3268; - x86::Gp ret_val_fget_flags_3268 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3268, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3268; - setRet(call_fget_flags_3268, 0, ret_val_fget_flags_3268); + cc.invoke(&call_fp_vector_vector_ww_3282, &fp_vector_vector_ww, FuncSignature::build()); + setArg(call_sew_3283, 0, reinterpret_cast(this)); + setRet(call_sew_3283, 0, ret_val_sew_3283); + setArg(call_fp_vector_vector_ww_3282, 0, V); + setArg(call_fp_vector_vector_ww_3282, 1, 54); + setArg(call_fp_vector_vector_ww_3282, 2, 1); + setArg(call_fp_vector_vector_ww_3282, 3, fp_vector_vector_ww_3282_arg3); + setArg(call_fp_vector_vector_ww_3282, 4, fp_vector_vector_ww_3282_arg4); + setArg(call_fp_vector_vector_ww_3282, 5, fp_vector_vector_ww_3282_arg5); + setArg(call_fp_vector_vector_ww_3282, 6, vm); + setArg(call_fp_vector_vector_ww_3282, 7, vd); + setArg(call_fp_vector_vector_ww_3282, 8, vs2); + setArg(call_fp_vector_vector_ww_3282, 9, vs1); + setArg(call_fp_vector_vector_ww_3282, 10, fp_vector_vector_ww_3282_arg10); + setArg(call_fp_vector_vector_ww_3282, 11, fp_vector_vector_ww_3282_arg11); + InvokeNode* call_fget_flags_3284; + x86::Gp ret_val_fget_flags_3284 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3284, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3284; + setRet(call_fget_flags_3284, 0, ret_val_fget_flags_3284); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3269 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3269, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3269, 32, false) - , traits::vstart); + auto tmp3285 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3285, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3285, traits::vstart); } cc.bind(label_merge); } @@ -76122,30 +75692,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3270; - x86::Gp ret_val_get_sew_pow_3270 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3270, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3271 = get_reg(cc, 8, false); - mov(cc, tmp3271, 1); + InvokeNode* call_get_sew_pow_3286; + x86::Gp ret_val_get_sew_pow_3286 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3286, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3287 = get_reg(cc, 8, false); + mov(cc, tmp3287, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3271, (ret_val_get_sew_pow_3270))), 8, false), ~ 1); - setArg(call_get_sew_pow_3270, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3270, 0, ret_val_get_sew_pow_3270); + (gen_operation(cc, shl, tmp3287, (ret_val_get_sew_pow_3286))), 8, false), ~ 1); + setArg(call_get_sew_pow_3286, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3286, 0, ret_val_get_sew_pow_3286); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3272; - auto illegal_fp_normal_3272_arg2 = SEW; - auto illegal_fp_normal_3272_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3272 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3272, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3272; - setArg(call_illegal_fp_normal_3272, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3272, 1, vd); - setArg(call_illegal_fp_normal_3272, 2, vm); - setArg(call_illegal_fp_normal_3272, 3, illegal_fp_normal_3272_arg2); - setArg(call_illegal_fp_normal_3272, 4, illegal_fp_normal_3272_arg3); - setRet(call_illegal_fp_normal_3272, 0, ret_val_illegal_fp_normal_3272); + InvokeNode* call_illegal_fp_normal_3288; + auto illegal_fp_normal_3288_arg2 = SEW; + auto illegal_fp_normal_3288_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3288 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3288, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3288; + setArg(call_illegal_fp_normal_3288, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3288, 1, vd); + setArg(call_illegal_fp_normal_3288, 2, vm); + setArg(call_illegal_fp_normal_3288, 3, illegal_fp_normal_3288_arg2); + setArg(call_illegal_fp_normal_3288, 4, illegal_fp_normal_3288_arg3); + setRet(call_illegal_fp_normal_3288, 0, ret_val_illegal_fp_normal_3288); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76161,47 +75731,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3274; - x86::Gp ret_val_sew_3274 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3274, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3273; - auto fp_vector_imm_op_3273_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3273_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3273_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3273_arg9 = gen_ext(cc, + InvokeNode* call_sew_3290; + x86::Gp ret_val_sew_3290 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3290, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3289; + auto fp_vector_imm_op_3289_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3289_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3289_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3289_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3273_arg10 = rm; - auto fp_vector_imm_op_3273_arg11 = ret_val_sew_3274; + auto fp_vector_imm_op_3289_arg10 = rm; + auto fp_vector_imm_op_3289_arg11 = ret_val_sew_3290; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3273, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3274, 0, reinterpret_cast(this)); - setRet(call_sew_3274, 0, ret_val_sew_3274); - setArg(call_fp_vector_imm_op_3273, 0, V); - setArg(call_fp_vector_imm_op_3273, 1, 36); - setArg(call_fp_vector_imm_op_3273, 2, 5); - setArg(call_fp_vector_imm_op_3273, 3, fp_vector_imm_op_3273_arg3); - setArg(call_fp_vector_imm_op_3273, 4, fp_vector_imm_op_3273_arg4); - setArg(call_fp_vector_imm_op_3273, 5, fp_vector_imm_op_3273_arg5); - setArg(call_fp_vector_imm_op_3273, 6, vm); - setArg(call_fp_vector_imm_op_3273, 7, vd); - setArg(call_fp_vector_imm_op_3273, 8, vs2); - setArg(call_fp_vector_imm_op_3273, 9, fp_vector_imm_op_3273_arg9); - setArg(call_fp_vector_imm_op_3273, 10, fp_vector_imm_op_3273_arg10); - setArg(call_fp_vector_imm_op_3273, 11, fp_vector_imm_op_3273_arg11); - InvokeNode* call_fget_flags_3275; - x86::Gp ret_val_fget_flags_3275 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3275, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3275; - setRet(call_fget_flags_3275, 0, ret_val_fget_flags_3275); + cc.invoke(&call_fp_vector_imm_op_3289, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3290, 0, reinterpret_cast(this)); + setRet(call_sew_3290, 0, ret_val_sew_3290); + setArg(call_fp_vector_imm_op_3289, 0, V); + setArg(call_fp_vector_imm_op_3289, 1, 36); + setArg(call_fp_vector_imm_op_3289, 2, 5); + setArg(call_fp_vector_imm_op_3289, 3, fp_vector_imm_op_3289_arg3); + setArg(call_fp_vector_imm_op_3289, 4, fp_vector_imm_op_3289_arg4); + setArg(call_fp_vector_imm_op_3289, 5, fp_vector_imm_op_3289_arg5); + setArg(call_fp_vector_imm_op_3289, 6, vm); + setArg(call_fp_vector_imm_op_3289, 7, vd); + setArg(call_fp_vector_imm_op_3289, 8, vs2); + setArg(call_fp_vector_imm_op_3289, 9, fp_vector_imm_op_3289_arg9); + setArg(call_fp_vector_imm_op_3289, 10, fp_vector_imm_op_3289_arg10); + setArg(call_fp_vector_imm_op_3289, 11, fp_vector_imm_op_3289_arg11); + InvokeNode* call_fget_flags_3291; + x86::Gp ret_val_fget_flags_3291 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3291, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3291; + setRet(call_fget_flags_3291, 0, ret_val_fget_flags_3291); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3276 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3276, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3276, 32, false) - , traits::vstart); + auto tmp3292 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3292, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3292, traits::vstart); } cc.bind(label_merge); } @@ -76245,30 +75813,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3277; - x86::Gp ret_val_get_sew_pow_3277 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3277, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3278 = get_reg(cc, 8, false); - mov(cc, tmp3278, 1); + InvokeNode* call_get_sew_pow_3293; + x86::Gp ret_val_get_sew_pow_3293 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3293, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3294 = get_reg(cc, 8, false); + mov(cc, tmp3294, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3278, (ret_val_get_sew_pow_3277))), 8, false), ~ 1); - setArg(call_get_sew_pow_3277, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3277, 0, ret_val_get_sew_pow_3277); + (gen_operation(cc, shl, tmp3294, (ret_val_get_sew_pow_3293))), 8, false), ~ 1); + setArg(call_get_sew_pow_3293, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3293, 0, ret_val_get_sew_pow_3293); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3279; - auto illegal_fp_normal_3279_arg2 = SEW; - auto illegal_fp_normal_3279_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3279 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3279, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3279; - setArg(call_illegal_fp_normal_3279, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3279, 1, vd); - setArg(call_illegal_fp_normal_3279, 2, vm); - setArg(call_illegal_fp_normal_3279, 3, illegal_fp_normal_3279_arg2); - setArg(call_illegal_fp_normal_3279, 4, illegal_fp_normal_3279_arg3); - setRet(call_illegal_fp_normal_3279, 0, ret_val_illegal_fp_normal_3279); + InvokeNode* call_illegal_fp_normal_3295; + auto illegal_fp_normal_3295_arg2 = SEW; + auto illegal_fp_normal_3295_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3295 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3295, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3295; + setArg(call_illegal_fp_normal_3295, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3295, 1, vd); + setArg(call_illegal_fp_normal_3295, 2, vm); + setArg(call_illegal_fp_normal_3295, 3, illegal_fp_normal_3295_arg2); + setArg(call_illegal_fp_normal_3295, 4, illegal_fp_normal_3295_arg3); + setRet(call_illegal_fp_normal_3295, 0, ret_val_illegal_fp_normal_3295); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76284,45 +75852,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3281; - x86::Gp ret_val_sew_3281 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3281, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3280; - auto fp_vector_vector_op_3280_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3280_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3280_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3280_arg10 = rm; - auto fp_vector_vector_op_3280_arg11 = ret_val_sew_3281; + InvokeNode* call_sew_3297; + x86::Gp ret_val_sew_3297 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3297, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3296; + auto fp_vector_vector_op_3296_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3296_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3296_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3296_arg10 = rm; + auto fp_vector_vector_op_3296_arg11 = ret_val_sew_3297; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3280, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3281, 0, reinterpret_cast(this)); - setRet(call_sew_3281, 0, ret_val_sew_3281); - setArg(call_fp_vector_vector_op_3280, 0, V); - setArg(call_fp_vector_vector_op_3280, 1, 36); - setArg(call_fp_vector_vector_op_3280, 2, 1); - setArg(call_fp_vector_vector_op_3280, 3, fp_vector_vector_op_3280_arg3); - setArg(call_fp_vector_vector_op_3280, 4, fp_vector_vector_op_3280_arg4); - setArg(call_fp_vector_vector_op_3280, 5, fp_vector_vector_op_3280_arg5); - setArg(call_fp_vector_vector_op_3280, 6, vm); - setArg(call_fp_vector_vector_op_3280, 7, vd); - setArg(call_fp_vector_vector_op_3280, 8, vs2); - setArg(call_fp_vector_vector_op_3280, 9, vs1); - setArg(call_fp_vector_vector_op_3280, 10, fp_vector_vector_op_3280_arg10); - setArg(call_fp_vector_vector_op_3280, 11, fp_vector_vector_op_3280_arg11); - InvokeNode* call_fget_flags_3282; - x86::Gp ret_val_fget_flags_3282 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3282, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3282; - setRet(call_fget_flags_3282, 0, ret_val_fget_flags_3282); + cc.invoke(&call_fp_vector_vector_op_3296, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3297, 0, reinterpret_cast(this)); + setRet(call_sew_3297, 0, ret_val_sew_3297); + setArg(call_fp_vector_vector_op_3296, 0, V); + setArg(call_fp_vector_vector_op_3296, 1, 36); + setArg(call_fp_vector_vector_op_3296, 2, 1); + setArg(call_fp_vector_vector_op_3296, 3, fp_vector_vector_op_3296_arg3); + setArg(call_fp_vector_vector_op_3296, 4, fp_vector_vector_op_3296_arg4); + setArg(call_fp_vector_vector_op_3296, 5, fp_vector_vector_op_3296_arg5); + setArg(call_fp_vector_vector_op_3296, 6, vm); + setArg(call_fp_vector_vector_op_3296, 7, vd); + setArg(call_fp_vector_vector_op_3296, 8, vs2); + setArg(call_fp_vector_vector_op_3296, 9, vs1); + setArg(call_fp_vector_vector_op_3296, 10, fp_vector_vector_op_3296_arg10); + setArg(call_fp_vector_vector_op_3296, 11, fp_vector_vector_op_3296_arg11); + InvokeNode* call_fget_flags_3298; + x86::Gp ret_val_fget_flags_3298 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3298, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3298; + setRet(call_fget_flags_3298, 0, ret_val_fget_flags_3298); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3283 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3283, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3283, 32, false) - , traits::vstart); + auto tmp3299 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3299, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3299, traits::vstart); } cc.bind(label_merge); } @@ -76366,30 +75932,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3284; - x86::Gp ret_val_get_sew_pow_3284 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3284, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3285 = get_reg(cc, 8, false); - mov(cc, tmp3285, 1); + InvokeNode* call_get_sew_pow_3300; + x86::Gp ret_val_get_sew_pow_3300 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3300, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3301 = get_reg(cc, 8, false); + mov(cc, tmp3301, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3285, (ret_val_get_sew_pow_3284))), 8, false), ~ 1); - setArg(call_get_sew_pow_3284, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3284, 0, ret_val_get_sew_pow_3284); + (gen_operation(cc, shl, tmp3301, (ret_val_get_sew_pow_3300))), 8, false), ~ 1); + setArg(call_get_sew_pow_3300, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3300, 0, ret_val_get_sew_pow_3300); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3286; - auto illegal_fp_normal_3286_arg2 = SEW; - auto illegal_fp_normal_3286_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3286 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3286, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3286; - setArg(call_illegal_fp_normal_3286, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3286, 1, vd); - setArg(call_illegal_fp_normal_3286, 2, vm); - setArg(call_illegal_fp_normal_3286, 3, illegal_fp_normal_3286_arg2); - setArg(call_illegal_fp_normal_3286, 4, illegal_fp_normal_3286_arg3); - setRet(call_illegal_fp_normal_3286, 0, ret_val_illegal_fp_normal_3286); + InvokeNode* call_illegal_fp_normal_3302; + auto illegal_fp_normal_3302_arg2 = SEW; + auto illegal_fp_normal_3302_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3302 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3302, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3302; + setArg(call_illegal_fp_normal_3302, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3302, 1, vd); + setArg(call_illegal_fp_normal_3302, 2, vm); + setArg(call_illegal_fp_normal_3302, 3, illegal_fp_normal_3302_arg2); + setArg(call_illegal_fp_normal_3302, 4, illegal_fp_normal_3302_arg3); + setRet(call_illegal_fp_normal_3302, 0, ret_val_illegal_fp_normal_3302); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76405,47 +75971,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3288; - x86::Gp ret_val_sew_3288 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3288, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3287; - auto fp_vector_imm_op_3287_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3287_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3287_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3287_arg9 = gen_ext(cc, + InvokeNode* call_sew_3304; + x86::Gp ret_val_sew_3304 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3304, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3303; + auto fp_vector_imm_op_3303_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3303_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3303_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3303_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3287_arg10 = rm; - auto fp_vector_imm_op_3287_arg11 = ret_val_sew_3288; + auto fp_vector_imm_op_3303_arg10 = rm; + auto fp_vector_imm_op_3303_arg11 = ret_val_sew_3304; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3287, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3288, 0, reinterpret_cast(this)); - setRet(call_sew_3288, 0, ret_val_sew_3288); - setArg(call_fp_vector_imm_op_3287, 0, V); - setArg(call_fp_vector_imm_op_3287, 1, 32); - setArg(call_fp_vector_imm_op_3287, 2, 5); - setArg(call_fp_vector_imm_op_3287, 3, fp_vector_imm_op_3287_arg3); - setArg(call_fp_vector_imm_op_3287, 4, fp_vector_imm_op_3287_arg4); - setArg(call_fp_vector_imm_op_3287, 5, fp_vector_imm_op_3287_arg5); - setArg(call_fp_vector_imm_op_3287, 6, vm); - setArg(call_fp_vector_imm_op_3287, 7, vd); - setArg(call_fp_vector_imm_op_3287, 8, vs2); - setArg(call_fp_vector_imm_op_3287, 9, fp_vector_imm_op_3287_arg9); - setArg(call_fp_vector_imm_op_3287, 10, fp_vector_imm_op_3287_arg10); - setArg(call_fp_vector_imm_op_3287, 11, fp_vector_imm_op_3287_arg11); - InvokeNode* call_fget_flags_3289; - x86::Gp ret_val_fget_flags_3289 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3289, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3289; - setRet(call_fget_flags_3289, 0, ret_val_fget_flags_3289); + cc.invoke(&call_fp_vector_imm_op_3303, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3304, 0, reinterpret_cast(this)); + setRet(call_sew_3304, 0, ret_val_sew_3304); + setArg(call_fp_vector_imm_op_3303, 0, V); + setArg(call_fp_vector_imm_op_3303, 1, 32); + setArg(call_fp_vector_imm_op_3303, 2, 5); + setArg(call_fp_vector_imm_op_3303, 3, fp_vector_imm_op_3303_arg3); + setArg(call_fp_vector_imm_op_3303, 4, fp_vector_imm_op_3303_arg4); + setArg(call_fp_vector_imm_op_3303, 5, fp_vector_imm_op_3303_arg5); + setArg(call_fp_vector_imm_op_3303, 6, vm); + setArg(call_fp_vector_imm_op_3303, 7, vd); + setArg(call_fp_vector_imm_op_3303, 8, vs2); + setArg(call_fp_vector_imm_op_3303, 9, fp_vector_imm_op_3303_arg9); + setArg(call_fp_vector_imm_op_3303, 10, fp_vector_imm_op_3303_arg10); + setArg(call_fp_vector_imm_op_3303, 11, fp_vector_imm_op_3303_arg11); + InvokeNode* call_fget_flags_3305; + x86::Gp ret_val_fget_flags_3305 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3305, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3305; + setRet(call_fget_flags_3305, 0, ret_val_fget_flags_3305); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3290 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3290, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3290, 32, false) - , traits::vstart); + auto tmp3306 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3306, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3306, traits::vstart); } cc.bind(label_merge); } @@ -76489,30 +76053,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3291; - x86::Gp ret_val_get_sew_pow_3291 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3291, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3292 = get_reg(cc, 8, false); - mov(cc, tmp3292, 1); + InvokeNode* call_get_sew_pow_3307; + x86::Gp ret_val_get_sew_pow_3307 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3307, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3308 = get_reg(cc, 8, false); + mov(cc, tmp3308, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3292, (ret_val_get_sew_pow_3291))), 8, false), ~ 1); - setArg(call_get_sew_pow_3291, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3291, 0, ret_val_get_sew_pow_3291); + (gen_operation(cc, shl, tmp3308, (ret_val_get_sew_pow_3307))), 8, false), ~ 1); + setArg(call_get_sew_pow_3307, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3307, 0, ret_val_get_sew_pow_3307); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3293; - auto illegal_fp_normal_3293_arg2 = SEW; - auto illegal_fp_normal_3293_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3293 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3293, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3293; - setArg(call_illegal_fp_normal_3293, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3293, 1, vd); - setArg(call_illegal_fp_normal_3293, 2, vm); - setArg(call_illegal_fp_normal_3293, 3, illegal_fp_normal_3293_arg2); - setArg(call_illegal_fp_normal_3293, 4, illegal_fp_normal_3293_arg3); - setRet(call_illegal_fp_normal_3293, 0, ret_val_illegal_fp_normal_3293); + InvokeNode* call_illegal_fp_normal_3309; + auto illegal_fp_normal_3309_arg2 = SEW; + auto illegal_fp_normal_3309_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3309 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3309, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3309; + setArg(call_illegal_fp_normal_3309, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3309, 1, vd); + setArg(call_illegal_fp_normal_3309, 2, vm); + setArg(call_illegal_fp_normal_3309, 3, illegal_fp_normal_3309_arg2); + setArg(call_illegal_fp_normal_3309, 4, illegal_fp_normal_3309_arg3); + setRet(call_illegal_fp_normal_3309, 0, ret_val_illegal_fp_normal_3309); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76528,45 +76092,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3295; - x86::Gp ret_val_sew_3295 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3295, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3294; - auto fp_vector_vector_op_3294_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3294_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3294_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3294_arg10 = rm; - auto fp_vector_vector_op_3294_arg11 = ret_val_sew_3295; + InvokeNode* call_sew_3311; + x86::Gp ret_val_sew_3311 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3311, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3310; + auto fp_vector_vector_op_3310_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3310_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3310_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3310_arg10 = rm; + auto fp_vector_vector_op_3310_arg11 = ret_val_sew_3311; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3294, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3295, 0, reinterpret_cast(this)); - setRet(call_sew_3295, 0, ret_val_sew_3295); - setArg(call_fp_vector_vector_op_3294, 0, V); - setArg(call_fp_vector_vector_op_3294, 1, 32); - setArg(call_fp_vector_vector_op_3294, 2, 1); - setArg(call_fp_vector_vector_op_3294, 3, fp_vector_vector_op_3294_arg3); - setArg(call_fp_vector_vector_op_3294, 4, fp_vector_vector_op_3294_arg4); - setArg(call_fp_vector_vector_op_3294, 5, fp_vector_vector_op_3294_arg5); - setArg(call_fp_vector_vector_op_3294, 6, vm); - setArg(call_fp_vector_vector_op_3294, 7, vd); - setArg(call_fp_vector_vector_op_3294, 8, vs2); - setArg(call_fp_vector_vector_op_3294, 9, vs1); - setArg(call_fp_vector_vector_op_3294, 10, fp_vector_vector_op_3294_arg10); - setArg(call_fp_vector_vector_op_3294, 11, fp_vector_vector_op_3294_arg11); - InvokeNode* call_fget_flags_3296; - x86::Gp ret_val_fget_flags_3296 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3296, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3296; - setRet(call_fget_flags_3296, 0, ret_val_fget_flags_3296); + cc.invoke(&call_fp_vector_vector_op_3310, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3311, 0, reinterpret_cast(this)); + setRet(call_sew_3311, 0, ret_val_sew_3311); + setArg(call_fp_vector_vector_op_3310, 0, V); + setArg(call_fp_vector_vector_op_3310, 1, 32); + setArg(call_fp_vector_vector_op_3310, 2, 1); + setArg(call_fp_vector_vector_op_3310, 3, fp_vector_vector_op_3310_arg3); + setArg(call_fp_vector_vector_op_3310, 4, fp_vector_vector_op_3310_arg4); + setArg(call_fp_vector_vector_op_3310, 5, fp_vector_vector_op_3310_arg5); + setArg(call_fp_vector_vector_op_3310, 6, vm); + setArg(call_fp_vector_vector_op_3310, 7, vd); + setArg(call_fp_vector_vector_op_3310, 8, vs2); + setArg(call_fp_vector_vector_op_3310, 9, vs1); + setArg(call_fp_vector_vector_op_3310, 10, fp_vector_vector_op_3310_arg10); + setArg(call_fp_vector_vector_op_3310, 11, fp_vector_vector_op_3310_arg11); + InvokeNode* call_fget_flags_3312; + x86::Gp ret_val_fget_flags_3312 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3312, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3312; + setRet(call_fget_flags_3312, 0, ret_val_fget_flags_3312); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3297 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3297, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3297, 32, false) - , traits::vstart); + auto tmp3313 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3313, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3313, traits::vstart); } cc.bind(label_merge); } @@ -76610,30 +76172,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3298; - x86::Gp ret_val_get_sew_pow_3298 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3298, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3299 = get_reg(cc, 8, false); - mov(cc, tmp3299, 1); + InvokeNode* call_get_sew_pow_3314; + x86::Gp ret_val_get_sew_pow_3314 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3314, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3315 = get_reg(cc, 8, false); + mov(cc, tmp3315, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3299, (ret_val_get_sew_pow_3298))), 8, false), ~ 1); - setArg(call_get_sew_pow_3298, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3298, 0, ret_val_get_sew_pow_3298); + (gen_operation(cc, shl, tmp3315, (ret_val_get_sew_pow_3314))), 8, false), ~ 1); + setArg(call_get_sew_pow_3314, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3314, 0, ret_val_get_sew_pow_3314); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3300; - auto illegal_fp_normal_3300_arg2 = SEW; - auto illegal_fp_normal_3300_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3300 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3300, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3300; - setArg(call_illegal_fp_normal_3300, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3300, 1, vd); - setArg(call_illegal_fp_normal_3300, 2, vm); - setArg(call_illegal_fp_normal_3300, 3, illegal_fp_normal_3300_arg2); - setArg(call_illegal_fp_normal_3300, 4, illegal_fp_normal_3300_arg3); - setRet(call_illegal_fp_normal_3300, 0, ret_val_illegal_fp_normal_3300); + InvokeNode* call_illegal_fp_normal_3316; + auto illegal_fp_normal_3316_arg2 = SEW; + auto illegal_fp_normal_3316_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3316 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3316, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3316; + setArg(call_illegal_fp_normal_3316, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3316, 1, vd); + setArg(call_illegal_fp_normal_3316, 2, vm); + setArg(call_illegal_fp_normal_3316, 3, illegal_fp_normal_3316_arg2); + setArg(call_illegal_fp_normal_3316, 4, illegal_fp_normal_3316_arg3); + setRet(call_illegal_fp_normal_3316, 0, ret_val_illegal_fp_normal_3316); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76649,47 +76211,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3302; - x86::Gp ret_val_sew_3302 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3302, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3301; - auto fp_vector_imm_op_3301_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3301_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3301_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3301_arg9 = gen_ext(cc, + InvokeNode* call_sew_3318; + x86::Gp ret_val_sew_3318 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3318, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3317; + auto fp_vector_imm_op_3317_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3317_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3317_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3317_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3301_arg10 = rm; - auto fp_vector_imm_op_3301_arg11 = ret_val_sew_3302; + auto fp_vector_imm_op_3317_arg10 = rm; + auto fp_vector_imm_op_3317_arg11 = ret_val_sew_3318; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3301, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3302, 0, reinterpret_cast(this)); - setRet(call_sew_3302, 0, ret_val_sew_3302); - setArg(call_fp_vector_imm_op_3301, 0, V); - setArg(call_fp_vector_imm_op_3301, 1, 33); - setArg(call_fp_vector_imm_op_3301, 2, 5); - setArg(call_fp_vector_imm_op_3301, 3, fp_vector_imm_op_3301_arg3); - setArg(call_fp_vector_imm_op_3301, 4, fp_vector_imm_op_3301_arg4); - setArg(call_fp_vector_imm_op_3301, 5, fp_vector_imm_op_3301_arg5); - setArg(call_fp_vector_imm_op_3301, 6, vm); - setArg(call_fp_vector_imm_op_3301, 7, vd); - setArg(call_fp_vector_imm_op_3301, 8, vs2); - setArg(call_fp_vector_imm_op_3301, 9, fp_vector_imm_op_3301_arg9); - setArg(call_fp_vector_imm_op_3301, 10, fp_vector_imm_op_3301_arg10); - setArg(call_fp_vector_imm_op_3301, 11, fp_vector_imm_op_3301_arg11); - InvokeNode* call_fget_flags_3303; - x86::Gp ret_val_fget_flags_3303 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3303, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3303; - setRet(call_fget_flags_3303, 0, ret_val_fget_flags_3303); + cc.invoke(&call_fp_vector_imm_op_3317, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3318, 0, reinterpret_cast(this)); + setRet(call_sew_3318, 0, ret_val_sew_3318); + setArg(call_fp_vector_imm_op_3317, 0, V); + setArg(call_fp_vector_imm_op_3317, 1, 33); + setArg(call_fp_vector_imm_op_3317, 2, 5); + setArg(call_fp_vector_imm_op_3317, 3, fp_vector_imm_op_3317_arg3); + setArg(call_fp_vector_imm_op_3317, 4, fp_vector_imm_op_3317_arg4); + setArg(call_fp_vector_imm_op_3317, 5, fp_vector_imm_op_3317_arg5); + setArg(call_fp_vector_imm_op_3317, 6, vm); + setArg(call_fp_vector_imm_op_3317, 7, vd); + setArg(call_fp_vector_imm_op_3317, 8, vs2); + setArg(call_fp_vector_imm_op_3317, 9, fp_vector_imm_op_3317_arg9); + setArg(call_fp_vector_imm_op_3317, 10, fp_vector_imm_op_3317_arg10); + setArg(call_fp_vector_imm_op_3317, 11, fp_vector_imm_op_3317_arg11); + InvokeNode* call_fget_flags_3319; + x86::Gp ret_val_fget_flags_3319 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3319, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3319; + setRet(call_fget_flags_3319, 0, ret_val_fget_flags_3319); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3304 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3304, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3304, 32, false) - , traits::vstart); + auto tmp3320 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3320, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3320, traits::vstart); } cc.bind(label_merge); } @@ -76733,54 +76293,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3305; - x86::Gp ret_val_get_sew_pow_3305 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3305, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3306 = get_reg(cc, 8, false); - mov(cc, tmp3306, 1); + InvokeNode* call_get_sew_pow_3321; + x86::Gp ret_val_get_sew_pow_3321 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3321, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3322 = get_reg(cc, 8, false); + mov(cc, tmp3322, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3306, (ret_val_get_sew_pow_3305))), 8, false), ~ 1); - setArg(call_get_sew_pow_3305, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3305, 0, ret_val_get_sew_pow_3305); - InvokeNode* call_get_lmul_pow_3307; - x86::Gp ret_val_get_lmul_pow_3307 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3307, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3307; - setArg(call_get_lmul_pow_3307, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3307, 0, ret_val_get_lmul_pow_3307); + (gen_operation(cc, shl, tmp3322, (ret_val_get_sew_pow_3321))), 8, false), ~ 1); + setArg(call_get_sew_pow_3321, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3321, 0, ret_val_get_sew_pow_3321); + InvokeNode* call_get_lmul_pow_3323; + x86::Gp ret_val_get_lmul_pow_3323 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3323, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3323; + setArg(call_get_lmul_pow_3323, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3323, 0, ret_val_get_lmul_pow_3323); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3308; - auto illegal_fp_variable_width_3308_arg2 = SEW; - auto illegal_fp_variable_width_3308_arg3 = rm; - auto illegal_fp_variable_width_3308_arg4 = SEW_widen; - auto illegal_fp_variable_width_3308_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3308 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3308, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3309; - auto valid_reg_overlap_3309_arg2 = LMUL_pow; - auto valid_reg_overlap_3309_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3309 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3309, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3308, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3309)); - setArg(call_illegal_fp_variable_width_3308, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3308, 1, vd); - setArg(call_illegal_fp_variable_width_3308, 2, vm); - setArg(call_illegal_fp_variable_width_3308, 3, illegal_fp_variable_width_3308_arg2); - setArg(call_illegal_fp_variable_width_3308, 4, illegal_fp_variable_width_3308_arg3); - setArg(call_illegal_fp_variable_width_3308, 5, illegal_fp_variable_width_3308_arg4); - setArg(call_illegal_fp_variable_width_3308, 6, illegal_fp_variable_width_3308_arg5); - setRet(call_illegal_fp_variable_width_3308, 0, ret_val_illegal_fp_variable_width_3308); - setArg(call_valid_reg_overlap_3309, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3309, 1, vs2); - setArg(call_valid_reg_overlap_3309, 2, vd); - setArg(call_valid_reg_overlap_3309, 3, valid_reg_overlap_3309_arg2); - setArg(call_valid_reg_overlap_3309, 4, valid_reg_overlap_3309_arg3); - setRet(call_valid_reg_overlap_3309, 0, ret_val_valid_reg_overlap_3309); + InvokeNode* call_illegal_fp_variable_width_3324; + auto illegal_fp_variable_width_3324_arg2 = SEW; + auto illegal_fp_variable_width_3324_arg3 = rm; + auto illegal_fp_variable_width_3324_arg4 = SEW_widen; + auto illegal_fp_variable_width_3324_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3324 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3324, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3325; + auto valid_reg_overlap_3325_arg2 = LMUL_pow; + auto valid_reg_overlap_3325_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3325 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3325, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3324, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3325)); + setArg(call_illegal_fp_variable_width_3324, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3324, 1, vd); + setArg(call_illegal_fp_variable_width_3324, 2, vm); + setArg(call_illegal_fp_variable_width_3324, 3, illegal_fp_variable_width_3324_arg2); + setArg(call_illegal_fp_variable_width_3324, 4, illegal_fp_variable_width_3324_arg3); + setArg(call_illegal_fp_variable_width_3324, 5, illegal_fp_variable_width_3324_arg4); + setArg(call_illegal_fp_variable_width_3324, 6, illegal_fp_variable_width_3324_arg5); + setRet(call_illegal_fp_variable_width_3324, 0, ret_val_illegal_fp_variable_width_3324); + setArg(call_valid_reg_overlap_3325, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3325, 1, vs2); + setArg(call_valid_reg_overlap_3325, 2, vd); + setArg(call_valid_reg_overlap_3325, 3, valid_reg_overlap_3325_arg2); + setArg(call_valid_reg_overlap_3325, 4, valid_reg_overlap_3325_arg3); + setRet(call_valid_reg_overlap_3325, 0, ret_val_valid_reg_overlap_3325); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76796,47 +76356,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3311; - x86::Gp ret_val_sew_3311 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3311, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3310; - auto fp_vector_imm_wv_3310_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3310_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3310_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3310_arg9 = gen_ext(cc, + InvokeNode* call_sew_3327; + x86::Gp ret_val_sew_3327 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3327, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3326; + auto fp_vector_imm_wv_3326_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3326_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3326_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3326_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_wv_3310_arg10 = rm; - auto fp_vector_imm_wv_3310_arg11 = ret_val_sew_3311; + auto fp_vector_imm_wv_3326_arg10 = rm; + auto fp_vector_imm_wv_3326_arg11 = ret_val_sew_3327; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3310, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3311, 0, reinterpret_cast(this)); - setRet(call_sew_3311, 0, ret_val_sew_3311); - setArg(call_fp_vector_imm_wv_3310, 0, V); - setArg(call_fp_vector_imm_wv_3310, 1, 56); - setArg(call_fp_vector_imm_wv_3310, 2, 5); - setArg(call_fp_vector_imm_wv_3310, 3, fp_vector_imm_wv_3310_arg3); - setArg(call_fp_vector_imm_wv_3310, 4, fp_vector_imm_wv_3310_arg4); - setArg(call_fp_vector_imm_wv_3310, 5, fp_vector_imm_wv_3310_arg5); - setArg(call_fp_vector_imm_wv_3310, 6, vm); - setArg(call_fp_vector_imm_wv_3310, 7, vd); - setArg(call_fp_vector_imm_wv_3310, 8, vs2); - setArg(call_fp_vector_imm_wv_3310, 9, fp_vector_imm_wv_3310_arg9); - setArg(call_fp_vector_imm_wv_3310, 10, fp_vector_imm_wv_3310_arg10); - setArg(call_fp_vector_imm_wv_3310, 11, fp_vector_imm_wv_3310_arg11); - InvokeNode* call_fget_flags_3312; - x86::Gp ret_val_fget_flags_3312 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3312, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3312; - setRet(call_fget_flags_3312, 0, ret_val_fget_flags_3312); + cc.invoke(&call_fp_vector_imm_wv_3326, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3327, 0, reinterpret_cast(this)); + setRet(call_sew_3327, 0, ret_val_sew_3327); + setArg(call_fp_vector_imm_wv_3326, 0, V); + setArg(call_fp_vector_imm_wv_3326, 1, 56); + setArg(call_fp_vector_imm_wv_3326, 2, 5); + setArg(call_fp_vector_imm_wv_3326, 3, fp_vector_imm_wv_3326_arg3); + setArg(call_fp_vector_imm_wv_3326, 4, fp_vector_imm_wv_3326_arg4); + setArg(call_fp_vector_imm_wv_3326, 5, fp_vector_imm_wv_3326_arg5); + setArg(call_fp_vector_imm_wv_3326, 6, vm); + setArg(call_fp_vector_imm_wv_3326, 7, vd); + setArg(call_fp_vector_imm_wv_3326, 8, vs2); + setArg(call_fp_vector_imm_wv_3326, 9, fp_vector_imm_wv_3326_arg9); + setArg(call_fp_vector_imm_wv_3326, 10, fp_vector_imm_wv_3326_arg10); + setArg(call_fp_vector_imm_wv_3326, 11, fp_vector_imm_wv_3326_arg11); + InvokeNode* call_fget_flags_3328; + x86::Gp ret_val_fget_flags_3328 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3328, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3328; + setRet(call_fget_flags_3328, 0, ret_val_fget_flags_3328); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3313 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3313, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3313, 32, false) - , traits::vstart); + auto tmp3329 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3329, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3329, traits::vstart); } cc.bind(label_merge); } @@ -76880,65 +76438,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3314; - x86::Gp ret_val_get_sew_pow_3314 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3314, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3315 = get_reg(cc, 8, false); - mov(cc, tmp3315, 1); + InvokeNode* call_get_sew_pow_3330; + x86::Gp ret_val_get_sew_pow_3330 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3330, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3331 = get_reg(cc, 8, false); + mov(cc, tmp3331, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3315, (ret_val_get_sew_pow_3314))), 8, false), ~ 1); - setArg(call_get_sew_pow_3314, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3314, 0, ret_val_get_sew_pow_3314); - InvokeNode* call_get_lmul_pow_3316; - x86::Gp ret_val_get_lmul_pow_3316 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3316, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3316; - setArg(call_get_lmul_pow_3316, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3316, 0, ret_val_get_lmul_pow_3316); + (gen_operation(cc, shl, tmp3331, (ret_val_get_sew_pow_3330))), 8, false), ~ 1); + setArg(call_get_sew_pow_3330, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3330, 0, ret_val_get_sew_pow_3330); + InvokeNode* call_get_lmul_pow_3332; + x86::Gp ret_val_get_lmul_pow_3332 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3332, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3332; + setArg(call_get_lmul_pow_3332, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3332, 0, ret_val_get_lmul_pow_3332); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3317; - auto illegal_fp_variable_width_3317_arg2 = SEW; - auto illegal_fp_variable_width_3317_arg3 = rm; - auto illegal_fp_variable_width_3317_arg4 = SEW_widen; - auto illegal_fp_variable_width_3317_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3317 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3317, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3318; - auto valid_reg_overlap_3318_arg2 = LMUL_pow; - auto valid_reg_overlap_3318_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3318 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3318, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3319; - auto valid_reg_overlap_3319_arg2 = LMUL_pow; - auto valid_reg_overlap_3319_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3319 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3319, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3317, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3318)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3319)); - setArg(call_illegal_fp_variable_width_3317, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3317, 1, vd); - setArg(call_illegal_fp_variable_width_3317, 2, vm); - setArg(call_illegal_fp_variable_width_3317, 3, illegal_fp_variable_width_3317_arg2); - setArg(call_illegal_fp_variable_width_3317, 4, illegal_fp_variable_width_3317_arg3); - setArg(call_illegal_fp_variable_width_3317, 5, illegal_fp_variable_width_3317_arg4); - setArg(call_illegal_fp_variable_width_3317, 6, illegal_fp_variable_width_3317_arg5); - setRet(call_illegal_fp_variable_width_3317, 0, ret_val_illegal_fp_variable_width_3317); - setArg(call_valid_reg_overlap_3318, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3318, 1, vs1); - setArg(call_valid_reg_overlap_3318, 2, vd); - setArg(call_valid_reg_overlap_3318, 3, valid_reg_overlap_3318_arg2); - setArg(call_valid_reg_overlap_3318, 4, valid_reg_overlap_3318_arg3); - setRet(call_valid_reg_overlap_3318, 0, ret_val_valid_reg_overlap_3318); - setArg(call_valid_reg_overlap_3319, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3319, 1, vs2); - setArg(call_valid_reg_overlap_3319, 2, vd); - setArg(call_valid_reg_overlap_3319, 3, valid_reg_overlap_3319_arg2); - setArg(call_valid_reg_overlap_3319, 4, valid_reg_overlap_3319_arg3); - setRet(call_valid_reg_overlap_3319, 0, ret_val_valid_reg_overlap_3319); + InvokeNode* call_illegal_fp_variable_width_3333; + auto illegal_fp_variable_width_3333_arg2 = SEW; + auto illegal_fp_variable_width_3333_arg3 = rm; + auto illegal_fp_variable_width_3333_arg4 = SEW_widen; + auto illegal_fp_variable_width_3333_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3333 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3333, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3334; + auto valid_reg_overlap_3334_arg2 = LMUL_pow; + auto valid_reg_overlap_3334_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3334 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3334, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3335; + auto valid_reg_overlap_3335_arg2 = LMUL_pow; + auto valid_reg_overlap_3335_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3335 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3335, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3333, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3334)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3335)); + setArg(call_illegal_fp_variable_width_3333, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3333, 1, vd); + setArg(call_illegal_fp_variable_width_3333, 2, vm); + setArg(call_illegal_fp_variable_width_3333, 3, illegal_fp_variable_width_3333_arg2); + setArg(call_illegal_fp_variable_width_3333, 4, illegal_fp_variable_width_3333_arg3); + setArg(call_illegal_fp_variable_width_3333, 5, illegal_fp_variable_width_3333_arg4); + setArg(call_illegal_fp_variable_width_3333, 6, illegal_fp_variable_width_3333_arg5); + setRet(call_illegal_fp_variable_width_3333, 0, ret_val_illegal_fp_variable_width_3333); + setArg(call_valid_reg_overlap_3334, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3334, 1, vs1); + setArg(call_valid_reg_overlap_3334, 2, vd); + setArg(call_valid_reg_overlap_3334, 3, valid_reg_overlap_3334_arg2); + setArg(call_valid_reg_overlap_3334, 4, valid_reg_overlap_3334_arg3); + setRet(call_valid_reg_overlap_3334, 0, ret_val_valid_reg_overlap_3334); + setArg(call_valid_reg_overlap_3335, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3335, 1, vs2); + setArg(call_valid_reg_overlap_3335, 2, vd); + setArg(call_valid_reg_overlap_3335, 3, valid_reg_overlap_3335_arg2); + setArg(call_valid_reg_overlap_3335, 4, valid_reg_overlap_3335_arg3); + setRet(call_valid_reg_overlap_3335, 0, ret_val_valid_reg_overlap_3335); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76954,45 +76512,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3321; - x86::Gp ret_val_sew_3321 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3321, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3320; - auto fp_vector_vector_wv_3320_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3320_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3320_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3320_arg10 = rm; - auto fp_vector_vector_wv_3320_arg11 = ret_val_sew_3321; + InvokeNode* call_sew_3337; + x86::Gp ret_val_sew_3337 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3337, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3336; + auto fp_vector_vector_wv_3336_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3336_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3336_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3336_arg10 = rm; + auto fp_vector_vector_wv_3336_arg11 = ret_val_sew_3337; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3320, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3321, 0, reinterpret_cast(this)); - setRet(call_sew_3321, 0, ret_val_sew_3321); - setArg(call_fp_vector_vector_wv_3320, 0, V); - setArg(call_fp_vector_vector_wv_3320, 1, 56); - setArg(call_fp_vector_vector_wv_3320, 2, 1); - setArg(call_fp_vector_vector_wv_3320, 3, fp_vector_vector_wv_3320_arg3); - setArg(call_fp_vector_vector_wv_3320, 4, fp_vector_vector_wv_3320_arg4); - setArg(call_fp_vector_vector_wv_3320, 5, fp_vector_vector_wv_3320_arg5); - setArg(call_fp_vector_vector_wv_3320, 6, vm); - setArg(call_fp_vector_vector_wv_3320, 7, vd); - setArg(call_fp_vector_vector_wv_3320, 8, vs2); - setArg(call_fp_vector_vector_wv_3320, 9, vs1); - setArg(call_fp_vector_vector_wv_3320, 10, fp_vector_vector_wv_3320_arg10); - setArg(call_fp_vector_vector_wv_3320, 11, fp_vector_vector_wv_3320_arg11); - InvokeNode* call_fget_flags_3322; - x86::Gp ret_val_fget_flags_3322 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3322, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3322; - setRet(call_fget_flags_3322, 0, ret_val_fget_flags_3322); + cc.invoke(&call_fp_vector_vector_wv_3336, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3337, 0, reinterpret_cast(this)); + setRet(call_sew_3337, 0, ret_val_sew_3337); + setArg(call_fp_vector_vector_wv_3336, 0, V); + setArg(call_fp_vector_vector_wv_3336, 1, 56); + setArg(call_fp_vector_vector_wv_3336, 2, 1); + setArg(call_fp_vector_vector_wv_3336, 3, fp_vector_vector_wv_3336_arg3); + setArg(call_fp_vector_vector_wv_3336, 4, fp_vector_vector_wv_3336_arg4); + setArg(call_fp_vector_vector_wv_3336, 5, fp_vector_vector_wv_3336_arg5); + setArg(call_fp_vector_vector_wv_3336, 6, vm); + setArg(call_fp_vector_vector_wv_3336, 7, vd); + setArg(call_fp_vector_vector_wv_3336, 8, vs2); + setArg(call_fp_vector_vector_wv_3336, 9, vs1); + setArg(call_fp_vector_vector_wv_3336, 10, fp_vector_vector_wv_3336_arg10); + setArg(call_fp_vector_vector_wv_3336, 11, fp_vector_vector_wv_3336_arg11); + InvokeNode* call_fget_flags_3338; + x86::Gp ret_val_fget_flags_3338 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3338, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3338; + setRet(call_fget_flags_3338, 0, ret_val_fget_flags_3338); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3323 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3323, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3323, 32, false) - , traits::vstart); + auto tmp3339 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3339, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3339, traits::vstart); } cc.bind(label_merge); } @@ -77036,30 +76592,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3324; - x86::Gp ret_val_get_sew_pow_3324 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3324, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3325 = get_reg(cc, 8, false); - mov(cc, tmp3325, 1); + InvokeNode* call_get_sew_pow_3340; + x86::Gp ret_val_get_sew_pow_3340 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3340, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3341 = get_reg(cc, 8, false); + mov(cc, tmp3341, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3325, (ret_val_get_sew_pow_3324))), 8, false), ~ 1); - setArg(call_get_sew_pow_3324, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3324, 0, ret_val_get_sew_pow_3324); + (gen_operation(cc, shl, tmp3341, (ret_val_get_sew_pow_3340))), 8, false), ~ 1); + setArg(call_get_sew_pow_3340, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3340, 0, ret_val_get_sew_pow_3340); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3326; - auto illegal_fp_normal_3326_arg2 = SEW; - auto illegal_fp_normal_3326_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3326 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3326, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3326; - setArg(call_illegal_fp_normal_3326, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3326, 1, vd); - setArg(call_illegal_fp_normal_3326, 2, vm); - setArg(call_illegal_fp_normal_3326, 3, illegal_fp_normal_3326_arg2); - setArg(call_illegal_fp_normal_3326, 4, illegal_fp_normal_3326_arg3); - setRet(call_illegal_fp_normal_3326, 0, ret_val_illegal_fp_normal_3326); + InvokeNode* call_illegal_fp_normal_3342; + auto illegal_fp_normal_3342_arg2 = SEW; + auto illegal_fp_normal_3342_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3342 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3342, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3342; + setArg(call_illegal_fp_normal_3342, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3342, 1, vd); + setArg(call_illegal_fp_normal_3342, 2, vm); + setArg(call_illegal_fp_normal_3342, 3, illegal_fp_normal_3342_arg2); + setArg(call_illegal_fp_normal_3342, 4, illegal_fp_normal_3342_arg3); + setRet(call_illegal_fp_normal_3342, 0, ret_val_illegal_fp_normal_3342); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77075,47 +76631,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3328; - x86::Gp ret_val_sew_3328 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3328, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3327; - auto fp_vector_imm_op_3327_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3327_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3327_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3327_arg9 = gen_ext(cc, + InvokeNode* call_sew_3344; + x86::Gp ret_val_sew_3344 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3344, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3343; + auto fp_vector_imm_op_3343_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3343_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3343_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3343_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3327_arg10 = rm; - auto fp_vector_imm_op_3327_arg11 = ret_val_sew_3328; + auto fp_vector_imm_op_3343_arg10 = rm; + auto fp_vector_imm_op_3343_arg11 = ret_val_sew_3344; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3327, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3328, 0, reinterpret_cast(this)); - setRet(call_sew_3328, 0, ret_val_sew_3328); - setArg(call_fp_vector_imm_op_3327, 0, V); - setArg(call_fp_vector_imm_op_3327, 1, 44); - setArg(call_fp_vector_imm_op_3327, 2, 5); - setArg(call_fp_vector_imm_op_3327, 3, fp_vector_imm_op_3327_arg3); - setArg(call_fp_vector_imm_op_3327, 4, fp_vector_imm_op_3327_arg4); - setArg(call_fp_vector_imm_op_3327, 5, fp_vector_imm_op_3327_arg5); - setArg(call_fp_vector_imm_op_3327, 6, vm); - setArg(call_fp_vector_imm_op_3327, 7, vd); - setArg(call_fp_vector_imm_op_3327, 8, vs2); - setArg(call_fp_vector_imm_op_3327, 9, fp_vector_imm_op_3327_arg9); - setArg(call_fp_vector_imm_op_3327, 10, fp_vector_imm_op_3327_arg10); - setArg(call_fp_vector_imm_op_3327, 11, fp_vector_imm_op_3327_arg11); - InvokeNode* call_fget_flags_3329; - x86::Gp ret_val_fget_flags_3329 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3329, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3329; - setRet(call_fget_flags_3329, 0, ret_val_fget_flags_3329); + cc.invoke(&call_fp_vector_imm_op_3343, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3344, 0, reinterpret_cast(this)); + setRet(call_sew_3344, 0, ret_val_sew_3344); + setArg(call_fp_vector_imm_op_3343, 0, V); + setArg(call_fp_vector_imm_op_3343, 1, 44); + setArg(call_fp_vector_imm_op_3343, 2, 5); + setArg(call_fp_vector_imm_op_3343, 3, fp_vector_imm_op_3343_arg3); + setArg(call_fp_vector_imm_op_3343, 4, fp_vector_imm_op_3343_arg4); + setArg(call_fp_vector_imm_op_3343, 5, fp_vector_imm_op_3343_arg5); + setArg(call_fp_vector_imm_op_3343, 6, vm); + setArg(call_fp_vector_imm_op_3343, 7, vd); + setArg(call_fp_vector_imm_op_3343, 8, vs2); + setArg(call_fp_vector_imm_op_3343, 9, fp_vector_imm_op_3343_arg9); + setArg(call_fp_vector_imm_op_3343, 10, fp_vector_imm_op_3343_arg10); + setArg(call_fp_vector_imm_op_3343, 11, fp_vector_imm_op_3343_arg11); + InvokeNode* call_fget_flags_3345; + x86::Gp ret_val_fget_flags_3345 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3345, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3345; + setRet(call_fget_flags_3345, 0, ret_val_fget_flags_3345); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3330 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3330, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3330, 32, false) - , traits::vstart); + auto tmp3346 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3346, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3346, traits::vstart); } cc.bind(label_merge); } @@ -77159,30 +76713,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3331; - x86::Gp ret_val_get_sew_pow_3331 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3331, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3332 = get_reg(cc, 8, false); - mov(cc, tmp3332, 1); + InvokeNode* call_get_sew_pow_3347; + x86::Gp ret_val_get_sew_pow_3347 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3347, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3348 = get_reg(cc, 8, false); + mov(cc, tmp3348, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3332, (ret_val_get_sew_pow_3331))), 8, false), ~ 1); - setArg(call_get_sew_pow_3331, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3331, 0, ret_val_get_sew_pow_3331); + (gen_operation(cc, shl, tmp3348, (ret_val_get_sew_pow_3347))), 8, false), ~ 1); + setArg(call_get_sew_pow_3347, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3347, 0, ret_val_get_sew_pow_3347); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3333; - auto illegal_fp_normal_3333_arg2 = SEW; - auto illegal_fp_normal_3333_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3333 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3333, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3333; - setArg(call_illegal_fp_normal_3333, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3333, 1, vd); - setArg(call_illegal_fp_normal_3333, 2, vm); - setArg(call_illegal_fp_normal_3333, 3, illegal_fp_normal_3333_arg2); - setArg(call_illegal_fp_normal_3333, 4, illegal_fp_normal_3333_arg3); - setRet(call_illegal_fp_normal_3333, 0, ret_val_illegal_fp_normal_3333); + InvokeNode* call_illegal_fp_normal_3349; + auto illegal_fp_normal_3349_arg2 = SEW; + auto illegal_fp_normal_3349_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3349 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3349, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3349; + setArg(call_illegal_fp_normal_3349, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3349, 1, vd); + setArg(call_illegal_fp_normal_3349, 2, vm); + setArg(call_illegal_fp_normal_3349, 3, illegal_fp_normal_3349_arg2); + setArg(call_illegal_fp_normal_3349, 4, illegal_fp_normal_3349_arg3); + setRet(call_illegal_fp_normal_3349, 0, ret_val_illegal_fp_normal_3349); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77198,45 +76752,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3335; - x86::Gp ret_val_sew_3335 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3335, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3334; - auto fp_vector_vector_op_3334_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3334_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3334_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3334_arg10 = rm; - auto fp_vector_vector_op_3334_arg11 = ret_val_sew_3335; + InvokeNode* call_sew_3351; + x86::Gp ret_val_sew_3351 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3351, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3350; + auto fp_vector_vector_op_3350_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3350_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3350_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3350_arg10 = rm; + auto fp_vector_vector_op_3350_arg11 = ret_val_sew_3351; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3334, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3335, 0, reinterpret_cast(this)); - setRet(call_sew_3335, 0, ret_val_sew_3335); - setArg(call_fp_vector_vector_op_3334, 0, V); - setArg(call_fp_vector_vector_op_3334, 1, 44); - setArg(call_fp_vector_vector_op_3334, 2, 1); - setArg(call_fp_vector_vector_op_3334, 3, fp_vector_vector_op_3334_arg3); - setArg(call_fp_vector_vector_op_3334, 4, fp_vector_vector_op_3334_arg4); - setArg(call_fp_vector_vector_op_3334, 5, fp_vector_vector_op_3334_arg5); - setArg(call_fp_vector_vector_op_3334, 6, vm); - setArg(call_fp_vector_vector_op_3334, 7, vd); - setArg(call_fp_vector_vector_op_3334, 8, vs2); - setArg(call_fp_vector_vector_op_3334, 9, vs1); - setArg(call_fp_vector_vector_op_3334, 10, fp_vector_vector_op_3334_arg10); - setArg(call_fp_vector_vector_op_3334, 11, fp_vector_vector_op_3334_arg11); - InvokeNode* call_fget_flags_3336; - x86::Gp ret_val_fget_flags_3336 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3336, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3336; - setRet(call_fget_flags_3336, 0, ret_val_fget_flags_3336); + cc.invoke(&call_fp_vector_vector_op_3350, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3351, 0, reinterpret_cast(this)); + setRet(call_sew_3351, 0, ret_val_sew_3351); + setArg(call_fp_vector_vector_op_3350, 0, V); + setArg(call_fp_vector_vector_op_3350, 1, 44); + setArg(call_fp_vector_vector_op_3350, 2, 1); + setArg(call_fp_vector_vector_op_3350, 3, fp_vector_vector_op_3350_arg3); + setArg(call_fp_vector_vector_op_3350, 4, fp_vector_vector_op_3350_arg4); + setArg(call_fp_vector_vector_op_3350, 5, fp_vector_vector_op_3350_arg5); + setArg(call_fp_vector_vector_op_3350, 6, vm); + setArg(call_fp_vector_vector_op_3350, 7, vd); + setArg(call_fp_vector_vector_op_3350, 8, vs2); + setArg(call_fp_vector_vector_op_3350, 9, vs1); + setArg(call_fp_vector_vector_op_3350, 10, fp_vector_vector_op_3350_arg10); + setArg(call_fp_vector_vector_op_3350, 11, fp_vector_vector_op_3350_arg11); + InvokeNode* call_fget_flags_3352; + x86::Gp ret_val_fget_flags_3352 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3352, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3352; + setRet(call_fget_flags_3352, 0, ret_val_fget_flags_3352); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3337 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3337, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3337, 32, false) - , traits::vstart); + auto tmp3353 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3353, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3353, traits::vstart); } cc.bind(label_merge); } @@ -77280,30 +76832,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3338; - x86::Gp ret_val_get_sew_pow_3338 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3338, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3339 = get_reg(cc, 8, false); - mov(cc, tmp3339, 1); + InvokeNode* call_get_sew_pow_3354; + x86::Gp ret_val_get_sew_pow_3354 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3354, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3355 = get_reg(cc, 8, false); + mov(cc, tmp3355, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3339, (ret_val_get_sew_pow_3338))), 8, false), ~ 1); - setArg(call_get_sew_pow_3338, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3338, 0, ret_val_get_sew_pow_3338); + (gen_operation(cc, shl, tmp3355, (ret_val_get_sew_pow_3354))), 8, false), ~ 1); + setArg(call_get_sew_pow_3354, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3354, 0, ret_val_get_sew_pow_3354); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3340; - auto illegal_fp_normal_3340_arg2 = SEW; - auto illegal_fp_normal_3340_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3340 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3340, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3340; - setArg(call_illegal_fp_normal_3340, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3340, 1, vd); - setArg(call_illegal_fp_normal_3340, 2, vm); - setArg(call_illegal_fp_normal_3340, 3, illegal_fp_normal_3340_arg2); - setArg(call_illegal_fp_normal_3340, 4, illegal_fp_normal_3340_arg3); - setRet(call_illegal_fp_normal_3340, 0, ret_val_illegal_fp_normal_3340); + InvokeNode* call_illegal_fp_normal_3356; + auto illegal_fp_normal_3356_arg2 = SEW; + auto illegal_fp_normal_3356_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3356 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3356, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3356; + setArg(call_illegal_fp_normal_3356, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3356, 1, vd); + setArg(call_illegal_fp_normal_3356, 2, vm); + setArg(call_illegal_fp_normal_3356, 3, illegal_fp_normal_3356_arg2); + setArg(call_illegal_fp_normal_3356, 4, illegal_fp_normal_3356_arg3); + setRet(call_illegal_fp_normal_3356, 0, ret_val_illegal_fp_normal_3356); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77319,47 +76871,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3342; - x86::Gp ret_val_sew_3342 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3342, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3341; - auto fp_vector_imm_op_3341_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3341_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3341_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3341_arg9 = gen_ext(cc, + InvokeNode* call_sew_3358; + x86::Gp ret_val_sew_3358 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3358, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3357; + auto fp_vector_imm_op_3357_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3357_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3357_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3357_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3341_arg10 = rm; - auto fp_vector_imm_op_3341_arg11 = ret_val_sew_3342; + auto fp_vector_imm_op_3357_arg10 = rm; + auto fp_vector_imm_op_3357_arg11 = ret_val_sew_3358; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3341, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3342, 0, reinterpret_cast(this)); - setRet(call_sew_3342, 0, ret_val_sew_3342); - setArg(call_fp_vector_imm_op_3341, 0, V); - setArg(call_fp_vector_imm_op_3341, 1, 45); - setArg(call_fp_vector_imm_op_3341, 2, 5); - setArg(call_fp_vector_imm_op_3341, 3, fp_vector_imm_op_3341_arg3); - setArg(call_fp_vector_imm_op_3341, 4, fp_vector_imm_op_3341_arg4); - setArg(call_fp_vector_imm_op_3341, 5, fp_vector_imm_op_3341_arg5); - setArg(call_fp_vector_imm_op_3341, 6, vm); - setArg(call_fp_vector_imm_op_3341, 7, vd); - setArg(call_fp_vector_imm_op_3341, 8, vs2); - setArg(call_fp_vector_imm_op_3341, 9, fp_vector_imm_op_3341_arg9); - setArg(call_fp_vector_imm_op_3341, 10, fp_vector_imm_op_3341_arg10); - setArg(call_fp_vector_imm_op_3341, 11, fp_vector_imm_op_3341_arg11); - InvokeNode* call_fget_flags_3343; - x86::Gp ret_val_fget_flags_3343 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3343, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3343; - setRet(call_fget_flags_3343, 0, ret_val_fget_flags_3343); + cc.invoke(&call_fp_vector_imm_op_3357, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3358, 0, reinterpret_cast(this)); + setRet(call_sew_3358, 0, ret_val_sew_3358); + setArg(call_fp_vector_imm_op_3357, 0, V); + setArg(call_fp_vector_imm_op_3357, 1, 45); + setArg(call_fp_vector_imm_op_3357, 2, 5); + setArg(call_fp_vector_imm_op_3357, 3, fp_vector_imm_op_3357_arg3); + setArg(call_fp_vector_imm_op_3357, 4, fp_vector_imm_op_3357_arg4); + setArg(call_fp_vector_imm_op_3357, 5, fp_vector_imm_op_3357_arg5); + setArg(call_fp_vector_imm_op_3357, 6, vm); + setArg(call_fp_vector_imm_op_3357, 7, vd); + setArg(call_fp_vector_imm_op_3357, 8, vs2); + setArg(call_fp_vector_imm_op_3357, 9, fp_vector_imm_op_3357_arg9); + setArg(call_fp_vector_imm_op_3357, 10, fp_vector_imm_op_3357_arg10); + setArg(call_fp_vector_imm_op_3357, 11, fp_vector_imm_op_3357_arg11); + InvokeNode* call_fget_flags_3359; + x86::Gp ret_val_fget_flags_3359 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3359, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3359; + setRet(call_fget_flags_3359, 0, ret_val_fget_flags_3359); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3344 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3344, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3344, 32, false) - , traits::vstart); + auto tmp3360 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3360, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3360, traits::vstart); } cc.bind(label_merge); } @@ -77403,30 +76953,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3345; - x86::Gp ret_val_get_sew_pow_3345 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3345, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3346 = get_reg(cc, 8, false); - mov(cc, tmp3346, 1); + InvokeNode* call_get_sew_pow_3361; + x86::Gp ret_val_get_sew_pow_3361 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3361, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3362 = get_reg(cc, 8, false); + mov(cc, tmp3362, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3346, (ret_val_get_sew_pow_3345))), 8, false), ~ 1); - setArg(call_get_sew_pow_3345, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3345, 0, ret_val_get_sew_pow_3345); + (gen_operation(cc, shl, tmp3362, (ret_val_get_sew_pow_3361))), 8, false), ~ 1); + setArg(call_get_sew_pow_3361, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3361, 0, ret_val_get_sew_pow_3361); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3347; - auto illegal_fp_normal_3347_arg2 = SEW; - auto illegal_fp_normal_3347_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3347 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3347, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3347; - setArg(call_illegal_fp_normal_3347, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3347, 1, vd); - setArg(call_illegal_fp_normal_3347, 2, vm); - setArg(call_illegal_fp_normal_3347, 3, illegal_fp_normal_3347_arg2); - setArg(call_illegal_fp_normal_3347, 4, illegal_fp_normal_3347_arg3); - setRet(call_illegal_fp_normal_3347, 0, ret_val_illegal_fp_normal_3347); + InvokeNode* call_illegal_fp_normal_3363; + auto illegal_fp_normal_3363_arg2 = SEW; + auto illegal_fp_normal_3363_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3363 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3363, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3363; + setArg(call_illegal_fp_normal_3363, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3363, 1, vd); + setArg(call_illegal_fp_normal_3363, 2, vm); + setArg(call_illegal_fp_normal_3363, 3, illegal_fp_normal_3363_arg2); + setArg(call_illegal_fp_normal_3363, 4, illegal_fp_normal_3363_arg3); + setRet(call_illegal_fp_normal_3363, 0, ret_val_illegal_fp_normal_3363); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77442,45 +76992,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3349; - x86::Gp ret_val_sew_3349 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3349, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3348; - auto fp_vector_vector_op_3348_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3348_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3348_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3348_arg10 = rm; - auto fp_vector_vector_op_3348_arg11 = ret_val_sew_3349; + InvokeNode* call_sew_3365; + x86::Gp ret_val_sew_3365 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3365, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3364; + auto fp_vector_vector_op_3364_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3364_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3364_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3364_arg10 = rm; + auto fp_vector_vector_op_3364_arg11 = ret_val_sew_3365; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3348, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3349, 0, reinterpret_cast(this)); - setRet(call_sew_3349, 0, ret_val_sew_3349); - setArg(call_fp_vector_vector_op_3348, 0, V); - setArg(call_fp_vector_vector_op_3348, 1, 45); - setArg(call_fp_vector_vector_op_3348, 2, 1); - setArg(call_fp_vector_vector_op_3348, 3, fp_vector_vector_op_3348_arg3); - setArg(call_fp_vector_vector_op_3348, 4, fp_vector_vector_op_3348_arg4); - setArg(call_fp_vector_vector_op_3348, 5, fp_vector_vector_op_3348_arg5); - setArg(call_fp_vector_vector_op_3348, 6, vm); - setArg(call_fp_vector_vector_op_3348, 7, vd); - setArg(call_fp_vector_vector_op_3348, 8, vs2); - setArg(call_fp_vector_vector_op_3348, 9, vs1); - setArg(call_fp_vector_vector_op_3348, 10, fp_vector_vector_op_3348_arg10); - setArg(call_fp_vector_vector_op_3348, 11, fp_vector_vector_op_3348_arg11); - InvokeNode* call_fget_flags_3350; - x86::Gp ret_val_fget_flags_3350 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3350, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3350; - setRet(call_fget_flags_3350, 0, ret_val_fget_flags_3350); + cc.invoke(&call_fp_vector_vector_op_3364, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3365, 0, reinterpret_cast(this)); + setRet(call_sew_3365, 0, ret_val_sew_3365); + setArg(call_fp_vector_vector_op_3364, 0, V); + setArg(call_fp_vector_vector_op_3364, 1, 45); + setArg(call_fp_vector_vector_op_3364, 2, 1); + setArg(call_fp_vector_vector_op_3364, 3, fp_vector_vector_op_3364_arg3); + setArg(call_fp_vector_vector_op_3364, 4, fp_vector_vector_op_3364_arg4); + setArg(call_fp_vector_vector_op_3364, 5, fp_vector_vector_op_3364_arg5); + setArg(call_fp_vector_vector_op_3364, 6, vm); + setArg(call_fp_vector_vector_op_3364, 7, vd); + setArg(call_fp_vector_vector_op_3364, 8, vs2); + setArg(call_fp_vector_vector_op_3364, 9, vs1); + setArg(call_fp_vector_vector_op_3364, 10, fp_vector_vector_op_3364_arg10); + setArg(call_fp_vector_vector_op_3364, 11, fp_vector_vector_op_3364_arg11); + InvokeNode* call_fget_flags_3366; + x86::Gp ret_val_fget_flags_3366 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3366, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3366; + setRet(call_fget_flags_3366, 0, ret_val_fget_flags_3366); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3351 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3351, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3351, 32, false) - , traits::vstart); + auto tmp3367 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3367, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3367, traits::vstart); } cc.bind(label_merge); } @@ -77524,30 +77072,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3352; - x86::Gp ret_val_get_sew_pow_3352 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3352, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3353 = get_reg(cc, 8, false); - mov(cc, tmp3353, 1); + InvokeNode* call_get_sew_pow_3368; + x86::Gp ret_val_get_sew_pow_3368 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3368, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3369 = get_reg(cc, 8, false); + mov(cc, tmp3369, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3353, (ret_val_get_sew_pow_3352))), 8, false), ~ 1); - setArg(call_get_sew_pow_3352, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3352, 0, ret_val_get_sew_pow_3352); + (gen_operation(cc, shl, tmp3369, (ret_val_get_sew_pow_3368))), 8, false), ~ 1); + setArg(call_get_sew_pow_3368, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3368, 0, ret_val_get_sew_pow_3368); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3354; - auto illegal_fp_normal_3354_arg2 = SEW; - auto illegal_fp_normal_3354_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3354 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3354, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3354; - setArg(call_illegal_fp_normal_3354, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3354, 1, vd); - setArg(call_illegal_fp_normal_3354, 2, vm); - setArg(call_illegal_fp_normal_3354, 3, illegal_fp_normal_3354_arg2); - setArg(call_illegal_fp_normal_3354, 4, illegal_fp_normal_3354_arg3); - setRet(call_illegal_fp_normal_3354, 0, ret_val_illegal_fp_normal_3354); + InvokeNode* call_illegal_fp_normal_3370; + auto illegal_fp_normal_3370_arg2 = SEW; + auto illegal_fp_normal_3370_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3370 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3370, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3370; + setArg(call_illegal_fp_normal_3370, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3370, 1, vd); + setArg(call_illegal_fp_normal_3370, 2, vm); + setArg(call_illegal_fp_normal_3370, 3, illegal_fp_normal_3370_arg2); + setArg(call_illegal_fp_normal_3370, 4, illegal_fp_normal_3370_arg3); + setRet(call_illegal_fp_normal_3370, 0, ret_val_illegal_fp_normal_3370); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77563,47 +77111,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3356; - x86::Gp ret_val_sew_3356 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3356, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3355; - auto fp_vector_imm_op_3355_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3355_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3355_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3355_arg9 = gen_ext(cc, + InvokeNode* call_sew_3372; + x86::Gp ret_val_sew_3372 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3372, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3371; + auto fp_vector_imm_op_3371_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3371_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3371_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3371_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3355_arg10 = rm; - auto fp_vector_imm_op_3355_arg11 = ret_val_sew_3356; + auto fp_vector_imm_op_3371_arg10 = rm; + auto fp_vector_imm_op_3371_arg11 = ret_val_sew_3372; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3355, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3356, 0, reinterpret_cast(this)); - setRet(call_sew_3356, 0, ret_val_sew_3356); - setArg(call_fp_vector_imm_op_3355, 0, V); - setArg(call_fp_vector_imm_op_3355, 1, 46); - setArg(call_fp_vector_imm_op_3355, 2, 5); - setArg(call_fp_vector_imm_op_3355, 3, fp_vector_imm_op_3355_arg3); - setArg(call_fp_vector_imm_op_3355, 4, fp_vector_imm_op_3355_arg4); - setArg(call_fp_vector_imm_op_3355, 5, fp_vector_imm_op_3355_arg5); - setArg(call_fp_vector_imm_op_3355, 6, vm); - setArg(call_fp_vector_imm_op_3355, 7, vd); - setArg(call_fp_vector_imm_op_3355, 8, vs2); - setArg(call_fp_vector_imm_op_3355, 9, fp_vector_imm_op_3355_arg9); - setArg(call_fp_vector_imm_op_3355, 10, fp_vector_imm_op_3355_arg10); - setArg(call_fp_vector_imm_op_3355, 11, fp_vector_imm_op_3355_arg11); - InvokeNode* call_fget_flags_3357; - x86::Gp ret_val_fget_flags_3357 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3357, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3357; - setRet(call_fget_flags_3357, 0, ret_val_fget_flags_3357); + cc.invoke(&call_fp_vector_imm_op_3371, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3372, 0, reinterpret_cast(this)); + setRet(call_sew_3372, 0, ret_val_sew_3372); + setArg(call_fp_vector_imm_op_3371, 0, V); + setArg(call_fp_vector_imm_op_3371, 1, 46); + setArg(call_fp_vector_imm_op_3371, 2, 5); + setArg(call_fp_vector_imm_op_3371, 3, fp_vector_imm_op_3371_arg3); + setArg(call_fp_vector_imm_op_3371, 4, fp_vector_imm_op_3371_arg4); + setArg(call_fp_vector_imm_op_3371, 5, fp_vector_imm_op_3371_arg5); + setArg(call_fp_vector_imm_op_3371, 6, vm); + setArg(call_fp_vector_imm_op_3371, 7, vd); + setArg(call_fp_vector_imm_op_3371, 8, vs2); + setArg(call_fp_vector_imm_op_3371, 9, fp_vector_imm_op_3371_arg9); + setArg(call_fp_vector_imm_op_3371, 10, fp_vector_imm_op_3371_arg10); + setArg(call_fp_vector_imm_op_3371, 11, fp_vector_imm_op_3371_arg11); + InvokeNode* call_fget_flags_3373; + x86::Gp ret_val_fget_flags_3373 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3373, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3373; + setRet(call_fget_flags_3373, 0, ret_val_fget_flags_3373); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3358 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3358, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3358, 32, false) - , traits::vstart); + auto tmp3374 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3374, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3374, traits::vstart); } cc.bind(label_merge); } @@ -77647,30 +77193,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3359; - x86::Gp ret_val_get_sew_pow_3359 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3359, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3360 = get_reg(cc, 8, false); - mov(cc, tmp3360, 1); + InvokeNode* call_get_sew_pow_3375; + x86::Gp ret_val_get_sew_pow_3375 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3375, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3376 = get_reg(cc, 8, false); + mov(cc, tmp3376, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3360, (ret_val_get_sew_pow_3359))), 8, false), ~ 1); - setArg(call_get_sew_pow_3359, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3359, 0, ret_val_get_sew_pow_3359); + (gen_operation(cc, shl, tmp3376, (ret_val_get_sew_pow_3375))), 8, false), ~ 1); + setArg(call_get_sew_pow_3375, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3375, 0, ret_val_get_sew_pow_3375); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3361; - auto illegal_fp_normal_3361_arg2 = SEW; - auto illegal_fp_normal_3361_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3361 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3361, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3361; - setArg(call_illegal_fp_normal_3361, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3361, 1, vd); - setArg(call_illegal_fp_normal_3361, 2, vm); - setArg(call_illegal_fp_normal_3361, 3, illegal_fp_normal_3361_arg2); - setArg(call_illegal_fp_normal_3361, 4, illegal_fp_normal_3361_arg3); - setRet(call_illegal_fp_normal_3361, 0, ret_val_illegal_fp_normal_3361); + InvokeNode* call_illegal_fp_normal_3377; + auto illegal_fp_normal_3377_arg2 = SEW; + auto illegal_fp_normal_3377_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3377 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3377, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3377; + setArg(call_illegal_fp_normal_3377, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3377, 1, vd); + setArg(call_illegal_fp_normal_3377, 2, vm); + setArg(call_illegal_fp_normal_3377, 3, illegal_fp_normal_3377_arg2); + setArg(call_illegal_fp_normal_3377, 4, illegal_fp_normal_3377_arg3); + setRet(call_illegal_fp_normal_3377, 0, ret_val_illegal_fp_normal_3377); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77686,45 +77232,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3363; - x86::Gp ret_val_sew_3363 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3363, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3362; - auto fp_vector_vector_op_3362_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3362_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3362_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3362_arg10 = rm; - auto fp_vector_vector_op_3362_arg11 = ret_val_sew_3363; + InvokeNode* call_sew_3379; + x86::Gp ret_val_sew_3379 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3379, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3378; + auto fp_vector_vector_op_3378_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3378_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3378_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3378_arg10 = rm; + auto fp_vector_vector_op_3378_arg11 = ret_val_sew_3379; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3362, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3363, 0, reinterpret_cast(this)); - setRet(call_sew_3363, 0, ret_val_sew_3363); - setArg(call_fp_vector_vector_op_3362, 0, V); - setArg(call_fp_vector_vector_op_3362, 1, 46); - setArg(call_fp_vector_vector_op_3362, 2, 1); - setArg(call_fp_vector_vector_op_3362, 3, fp_vector_vector_op_3362_arg3); - setArg(call_fp_vector_vector_op_3362, 4, fp_vector_vector_op_3362_arg4); - setArg(call_fp_vector_vector_op_3362, 5, fp_vector_vector_op_3362_arg5); - setArg(call_fp_vector_vector_op_3362, 6, vm); - setArg(call_fp_vector_vector_op_3362, 7, vd); - setArg(call_fp_vector_vector_op_3362, 8, vs2); - setArg(call_fp_vector_vector_op_3362, 9, vs1); - setArg(call_fp_vector_vector_op_3362, 10, fp_vector_vector_op_3362_arg10); - setArg(call_fp_vector_vector_op_3362, 11, fp_vector_vector_op_3362_arg11); - InvokeNode* call_fget_flags_3364; - x86::Gp ret_val_fget_flags_3364 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3364, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3364; - setRet(call_fget_flags_3364, 0, ret_val_fget_flags_3364); + cc.invoke(&call_fp_vector_vector_op_3378, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3379, 0, reinterpret_cast(this)); + setRet(call_sew_3379, 0, ret_val_sew_3379); + setArg(call_fp_vector_vector_op_3378, 0, V); + setArg(call_fp_vector_vector_op_3378, 1, 46); + setArg(call_fp_vector_vector_op_3378, 2, 1); + setArg(call_fp_vector_vector_op_3378, 3, fp_vector_vector_op_3378_arg3); + setArg(call_fp_vector_vector_op_3378, 4, fp_vector_vector_op_3378_arg4); + setArg(call_fp_vector_vector_op_3378, 5, fp_vector_vector_op_3378_arg5); + setArg(call_fp_vector_vector_op_3378, 6, vm); + setArg(call_fp_vector_vector_op_3378, 7, vd); + setArg(call_fp_vector_vector_op_3378, 8, vs2); + setArg(call_fp_vector_vector_op_3378, 9, vs1); + setArg(call_fp_vector_vector_op_3378, 10, fp_vector_vector_op_3378_arg10); + setArg(call_fp_vector_vector_op_3378, 11, fp_vector_vector_op_3378_arg11); + InvokeNode* call_fget_flags_3380; + x86::Gp ret_val_fget_flags_3380 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3380, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3380; + setRet(call_fget_flags_3380, 0, ret_val_fget_flags_3380); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3365 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3365, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3365, 32, false) - , traits::vstart); + auto tmp3381 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3381, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3381, traits::vstart); } cc.bind(label_merge); } @@ -77768,30 +77312,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3366; - x86::Gp ret_val_get_sew_pow_3366 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3366, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3367 = get_reg(cc, 8, false); - mov(cc, tmp3367, 1); + InvokeNode* call_get_sew_pow_3382; + x86::Gp ret_val_get_sew_pow_3382 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3382, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3383 = get_reg(cc, 8, false); + mov(cc, tmp3383, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3367, (ret_val_get_sew_pow_3366))), 8, false), ~ 1); - setArg(call_get_sew_pow_3366, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3366, 0, ret_val_get_sew_pow_3366); + (gen_operation(cc, shl, tmp3383, (ret_val_get_sew_pow_3382))), 8, false), ~ 1); + setArg(call_get_sew_pow_3382, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3382, 0, ret_val_get_sew_pow_3382); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3368; - auto illegal_fp_normal_3368_arg2 = SEW; - auto illegal_fp_normal_3368_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3368 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3368, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3368; - setArg(call_illegal_fp_normal_3368, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3368, 1, vd); - setArg(call_illegal_fp_normal_3368, 2, vm); - setArg(call_illegal_fp_normal_3368, 3, illegal_fp_normal_3368_arg2); - setArg(call_illegal_fp_normal_3368, 4, illegal_fp_normal_3368_arg3); - setRet(call_illegal_fp_normal_3368, 0, ret_val_illegal_fp_normal_3368); + InvokeNode* call_illegal_fp_normal_3384; + auto illegal_fp_normal_3384_arg2 = SEW; + auto illegal_fp_normal_3384_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3384 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3384, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3384; + setArg(call_illegal_fp_normal_3384, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3384, 1, vd); + setArg(call_illegal_fp_normal_3384, 2, vm); + setArg(call_illegal_fp_normal_3384, 3, illegal_fp_normal_3384_arg2); + setArg(call_illegal_fp_normal_3384, 4, illegal_fp_normal_3384_arg3); + setRet(call_illegal_fp_normal_3384, 0, ret_val_illegal_fp_normal_3384); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77807,47 +77351,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3370; - x86::Gp ret_val_sew_3370 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3370, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3369; - auto fp_vector_imm_op_3369_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3369_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3369_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3369_arg9 = gen_ext(cc, + InvokeNode* call_sew_3386; + x86::Gp ret_val_sew_3386 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3386, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3385; + auto fp_vector_imm_op_3385_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3385_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3385_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3385_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3369_arg10 = rm; - auto fp_vector_imm_op_3369_arg11 = ret_val_sew_3370; + auto fp_vector_imm_op_3385_arg10 = rm; + auto fp_vector_imm_op_3385_arg11 = ret_val_sew_3386; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3369, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3370, 0, reinterpret_cast(this)); - setRet(call_sew_3370, 0, ret_val_sew_3370); - setArg(call_fp_vector_imm_op_3369, 0, V); - setArg(call_fp_vector_imm_op_3369, 1, 47); - setArg(call_fp_vector_imm_op_3369, 2, 5); - setArg(call_fp_vector_imm_op_3369, 3, fp_vector_imm_op_3369_arg3); - setArg(call_fp_vector_imm_op_3369, 4, fp_vector_imm_op_3369_arg4); - setArg(call_fp_vector_imm_op_3369, 5, fp_vector_imm_op_3369_arg5); - setArg(call_fp_vector_imm_op_3369, 6, vm); - setArg(call_fp_vector_imm_op_3369, 7, vd); - setArg(call_fp_vector_imm_op_3369, 8, vs2); - setArg(call_fp_vector_imm_op_3369, 9, fp_vector_imm_op_3369_arg9); - setArg(call_fp_vector_imm_op_3369, 10, fp_vector_imm_op_3369_arg10); - setArg(call_fp_vector_imm_op_3369, 11, fp_vector_imm_op_3369_arg11); - InvokeNode* call_fget_flags_3371; - x86::Gp ret_val_fget_flags_3371 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3371, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3371; - setRet(call_fget_flags_3371, 0, ret_val_fget_flags_3371); + cc.invoke(&call_fp_vector_imm_op_3385, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3386, 0, reinterpret_cast(this)); + setRet(call_sew_3386, 0, ret_val_sew_3386); + setArg(call_fp_vector_imm_op_3385, 0, V); + setArg(call_fp_vector_imm_op_3385, 1, 47); + setArg(call_fp_vector_imm_op_3385, 2, 5); + setArg(call_fp_vector_imm_op_3385, 3, fp_vector_imm_op_3385_arg3); + setArg(call_fp_vector_imm_op_3385, 4, fp_vector_imm_op_3385_arg4); + setArg(call_fp_vector_imm_op_3385, 5, fp_vector_imm_op_3385_arg5); + setArg(call_fp_vector_imm_op_3385, 6, vm); + setArg(call_fp_vector_imm_op_3385, 7, vd); + setArg(call_fp_vector_imm_op_3385, 8, vs2); + setArg(call_fp_vector_imm_op_3385, 9, fp_vector_imm_op_3385_arg9); + setArg(call_fp_vector_imm_op_3385, 10, fp_vector_imm_op_3385_arg10); + setArg(call_fp_vector_imm_op_3385, 11, fp_vector_imm_op_3385_arg11); + InvokeNode* call_fget_flags_3387; + x86::Gp ret_val_fget_flags_3387 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3387, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3387; + setRet(call_fget_flags_3387, 0, ret_val_fget_flags_3387); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3372 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3372, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3372, 32, false) - , traits::vstart); + auto tmp3388 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3388, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3388, traits::vstart); } cc.bind(label_merge); } @@ -77891,30 +77433,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3373; - x86::Gp ret_val_get_sew_pow_3373 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3373, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3374 = get_reg(cc, 8, false); - mov(cc, tmp3374, 1); + InvokeNode* call_get_sew_pow_3389; + x86::Gp ret_val_get_sew_pow_3389 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3389, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3390 = get_reg(cc, 8, false); + mov(cc, tmp3390, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3374, (ret_val_get_sew_pow_3373))), 8, false), ~ 1); - setArg(call_get_sew_pow_3373, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3373, 0, ret_val_get_sew_pow_3373); + (gen_operation(cc, shl, tmp3390, (ret_val_get_sew_pow_3389))), 8, false), ~ 1); + setArg(call_get_sew_pow_3389, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3389, 0, ret_val_get_sew_pow_3389); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3375; - auto illegal_fp_normal_3375_arg2 = SEW; - auto illegal_fp_normal_3375_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3375 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3375, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3375; - setArg(call_illegal_fp_normal_3375, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3375, 1, vd); - setArg(call_illegal_fp_normal_3375, 2, vm); - setArg(call_illegal_fp_normal_3375, 3, illegal_fp_normal_3375_arg2); - setArg(call_illegal_fp_normal_3375, 4, illegal_fp_normal_3375_arg3); - setRet(call_illegal_fp_normal_3375, 0, ret_val_illegal_fp_normal_3375); + InvokeNode* call_illegal_fp_normal_3391; + auto illegal_fp_normal_3391_arg2 = SEW; + auto illegal_fp_normal_3391_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3391 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3391, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3391; + setArg(call_illegal_fp_normal_3391, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3391, 1, vd); + setArg(call_illegal_fp_normal_3391, 2, vm); + setArg(call_illegal_fp_normal_3391, 3, illegal_fp_normal_3391_arg2); + setArg(call_illegal_fp_normal_3391, 4, illegal_fp_normal_3391_arg3); + setRet(call_illegal_fp_normal_3391, 0, ret_val_illegal_fp_normal_3391); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77930,45 +77472,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3377; - x86::Gp ret_val_sew_3377 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3377, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3376; - auto fp_vector_vector_op_3376_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3376_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3376_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3376_arg10 = rm; - auto fp_vector_vector_op_3376_arg11 = ret_val_sew_3377; + InvokeNode* call_sew_3393; + x86::Gp ret_val_sew_3393 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3393, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3392; + auto fp_vector_vector_op_3392_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3392_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3392_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3392_arg10 = rm; + auto fp_vector_vector_op_3392_arg11 = ret_val_sew_3393; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3376, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3377, 0, reinterpret_cast(this)); - setRet(call_sew_3377, 0, ret_val_sew_3377); - setArg(call_fp_vector_vector_op_3376, 0, V); - setArg(call_fp_vector_vector_op_3376, 1, 47); - setArg(call_fp_vector_vector_op_3376, 2, 1); - setArg(call_fp_vector_vector_op_3376, 3, fp_vector_vector_op_3376_arg3); - setArg(call_fp_vector_vector_op_3376, 4, fp_vector_vector_op_3376_arg4); - setArg(call_fp_vector_vector_op_3376, 5, fp_vector_vector_op_3376_arg5); - setArg(call_fp_vector_vector_op_3376, 6, vm); - setArg(call_fp_vector_vector_op_3376, 7, vd); - setArg(call_fp_vector_vector_op_3376, 8, vs2); - setArg(call_fp_vector_vector_op_3376, 9, vs1); - setArg(call_fp_vector_vector_op_3376, 10, fp_vector_vector_op_3376_arg10); - setArg(call_fp_vector_vector_op_3376, 11, fp_vector_vector_op_3376_arg11); - InvokeNode* call_fget_flags_3378; - x86::Gp ret_val_fget_flags_3378 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3378, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3378; - setRet(call_fget_flags_3378, 0, ret_val_fget_flags_3378); + cc.invoke(&call_fp_vector_vector_op_3392, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3393, 0, reinterpret_cast(this)); + setRet(call_sew_3393, 0, ret_val_sew_3393); + setArg(call_fp_vector_vector_op_3392, 0, V); + setArg(call_fp_vector_vector_op_3392, 1, 47); + setArg(call_fp_vector_vector_op_3392, 2, 1); + setArg(call_fp_vector_vector_op_3392, 3, fp_vector_vector_op_3392_arg3); + setArg(call_fp_vector_vector_op_3392, 4, fp_vector_vector_op_3392_arg4); + setArg(call_fp_vector_vector_op_3392, 5, fp_vector_vector_op_3392_arg5); + setArg(call_fp_vector_vector_op_3392, 6, vm); + setArg(call_fp_vector_vector_op_3392, 7, vd); + setArg(call_fp_vector_vector_op_3392, 8, vs2); + setArg(call_fp_vector_vector_op_3392, 9, vs1); + setArg(call_fp_vector_vector_op_3392, 10, fp_vector_vector_op_3392_arg10); + setArg(call_fp_vector_vector_op_3392, 11, fp_vector_vector_op_3392_arg11); + InvokeNode* call_fget_flags_3394; + x86::Gp ret_val_fget_flags_3394 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3394, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3394; + setRet(call_fget_flags_3394, 0, ret_val_fget_flags_3394); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3379 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3379, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3379, 32, false) - , traits::vstart); + auto tmp3395 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3395, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3395, traits::vstart); } cc.bind(label_merge); } @@ -78012,30 +77552,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3380; - x86::Gp ret_val_get_sew_pow_3380 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3380, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3381 = get_reg(cc, 8, false); - mov(cc, tmp3381, 1); + InvokeNode* call_get_sew_pow_3396; + x86::Gp ret_val_get_sew_pow_3396 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3396, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3397 = get_reg(cc, 8, false); + mov(cc, tmp3397, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3381, (ret_val_get_sew_pow_3380))), 8, false), ~ 1); - setArg(call_get_sew_pow_3380, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3380, 0, ret_val_get_sew_pow_3380); + (gen_operation(cc, shl, tmp3397, (ret_val_get_sew_pow_3396))), 8, false), ~ 1); + setArg(call_get_sew_pow_3396, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3396, 0, ret_val_get_sew_pow_3396); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3382; - auto illegal_fp_normal_3382_arg2 = SEW; - auto illegal_fp_normal_3382_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3382 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3382, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3382; - setArg(call_illegal_fp_normal_3382, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3382, 1, vd); - setArg(call_illegal_fp_normal_3382, 2, vm); - setArg(call_illegal_fp_normal_3382, 3, illegal_fp_normal_3382_arg2); - setArg(call_illegal_fp_normal_3382, 4, illegal_fp_normal_3382_arg3); - setRet(call_illegal_fp_normal_3382, 0, ret_val_illegal_fp_normal_3382); + InvokeNode* call_illegal_fp_normal_3398; + auto illegal_fp_normal_3398_arg2 = SEW; + auto illegal_fp_normal_3398_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3398 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3398, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3398; + setArg(call_illegal_fp_normal_3398, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3398, 1, vd); + setArg(call_illegal_fp_normal_3398, 2, vm); + setArg(call_illegal_fp_normal_3398, 3, illegal_fp_normal_3398_arg2); + setArg(call_illegal_fp_normal_3398, 4, illegal_fp_normal_3398_arg3); + setRet(call_illegal_fp_normal_3398, 0, ret_val_illegal_fp_normal_3398); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78051,47 +77591,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3384; - x86::Gp ret_val_sew_3384 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3384, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3383; - auto fp_vector_imm_op_3383_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3383_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3383_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3383_arg9 = gen_ext(cc, + InvokeNode* call_sew_3400; + x86::Gp ret_val_sew_3400 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3400, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3399; + auto fp_vector_imm_op_3399_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3399_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3399_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3399_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3383_arg10 = rm; - auto fp_vector_imm_op_3383_arg11 = ret_val_sew_3384; + auto fp_vector_imm_op_3399_arg10 = rm; + auto fp_vector_imm_op_3399_arg11 = ret_val_sew_3400; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3383, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3384, 0, reinterpret_cast(this)); - setRet(call_sew_3384, 0, ret_val_sew_3384); - setArg(call_fp_vector_imm_op_3383, 0, V); - setArg(call_fp_vector_imm_op_3383, 1, 40); - setArg(call_fp_vector_imm_op_3383, 2, 5); - setArg(call_fp_vector_imm_op_3383, 3, fp_vector_imm_op_3383_arg3); - setArg(call_fp_vector_imm_op_3383, 4, fp_vector_imm_op_3383_arg4); - setArg(call_fp_vector_imm_op_3383, 5, fp_vector_imm_op_3383_arg5); - setArg(call_fp_vector_imm_op_3383, 6, vm); - setArg(call_fp_vector_imm_op_3383, 7, vd); - setArg(call_fp_vector_imm_op_3383, 8, vs2); - setArg(call_fp_vector_imm_op_3383, 9, fp_vector_imm_op_3383_arg9); - setArg(call_fp_vector_imm_op_3383, 10, fp_vector_imm_op_3383_arg10); - setArg(call_fp_vector_imm_op_3383, 11, fp_vector_imm_op_3383_arg11); - InvokeNode* call_fget_flags_3385; - x86::Gp ret_val_fget_flags_3385 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3385, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3385; - setRet(call_fget_flags_3385, 0, ret_val_fget_flags_3385); + cc.invoke(&call_fp_vector_imm_op_3399, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3400, 0, reinterpret_cast(this)); + setRet(call_sew_3400, 0, ret_val_sew_3400); + setArg(call_fp_vector_imm_op_3399, 0, V); + setArg(call_fp_vector_imm_op_3399, 1, 40); + setArg(call_fp_vector_imm_op_3399, 2, 5); + setArg(call_fp_vector_imm_op_3399, 3, fp_vector_imm_op_3399_arg3); + setArg(call_fp_vector_imm_op_3399, 4, fp_vector_imm_op_3399_arg4); + setArg(call_fp_vector_imm_op_3399, 5, fp_vector_imm_op_3399_arg5); + setArg(call_fp_vector_imm_op_3399, 6, vm); + setArg(call_fp_vector_imm_op_3399, 7, vd); + setArg(call_fp_vector_imm_op_3399, 8, vs2); + setArg(call_fp_vector_imm_op_3399, 9, fp_vector_imm_op_3399_arg9); + setArg(call_fp_vector_imm_op_3399, 10, fp_vector_imm_op_3399_arg10); + setArg(call_fp_vector_imm_op_3399, 11, fp_vector_imm_op_3399_arg11); + InvokeNode* call_fget_flags_3401; + x86::Gp ret_val_fget_flags_3401 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3401, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3401; + setRet(call_fget_flags_3401, 0, ret_val_fget_flags_3401); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3386 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3386, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3386, 32, false) - , traits::vstart); + auto tmp3402 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3402, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3402, traits::vstart); } cc.bind(label_merge); } @@ -78135,30 +77673,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3387; - x86::Gp ret_val_get_sew_pow_3387 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3387, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3388 = get_reg(cc, 8, false); - mov(cc, tmp3388, 1); + InvokeNode* call_get_sew_pow_3403; + x86::Gp ret_val_get_sew_pow_3403 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3403, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3404 = get_reg(cc, 8, false); + mov(cc, tmp3404, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3388, (ret_val_get_sew_pow_3387))), 8, false), ~ 1); - setArg(call_get_sew_pow_3387, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3387, 0, ret_val_get_sew_pow_3387); + (gen_operation(cc, shl, tmp3404, (ret_val_get_sew_pow_3403))), 8, false), ~ 1); + setArg(call_get_sew_pow_3403, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3403, 0, ret_val_get_sew_pow_3403); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3389; - auto illegal_fp_normal_3389_arg2 = SEW; - auto illegal_fp_normal_3389_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3389 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3389, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3389; - setArg(call_illegal_fp_normal_3389, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3389, 1, vd); - setArg(call_illegal_fp_normal_3389, 2, vm); - setArg(call_illegal_fp_normal_3389, 3, illegal_fp_normal_3389_arg2); - setArg(call_illegal_fp_normal_3389, 4, illegal_fp_normal_3389_arg3); - setRet(call_illegal_fp_normal_3389, 0, ret_val_illegal_fp_normal_3389); + InvokeNode* call_illegal_fp_normal_3405; + auto illegal_fp_normal_3405_arg2 = SEW; + auto illegal_fp_normal_3405_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3405 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3405, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3405; + setArg(call_illegal_fp_normal_3405, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3405, 1, vd); + setArg(call_illegal_fp_normal_3405, 2, vm); + setArg(call_illegal_fp_normal_3405, 3, illegal_fp_normal_3405_arg2); + setArg(call_illegal_fp_normal_3405, 4, illegal_fp_normal_3405_arg3); + setRet(call_illegal_fp_normal_3405, 0, ret_val_illegal_fp_normal_3405); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78174,45 +77712,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3391; - x86::Gp ret_val_sew_3391 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3391, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3390; - auto fp_vector_vector_op_3390_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3390_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3390_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3390_arg10 = rm; - auto fp_vector_vector_op_3390_arg11 = ret_val_sew_3391; + InvokeNode* call_sew_3407; + x86::Gp ret_val_sew_3407 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3407, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3406; + auto fp_vector_vector_op_3406_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3406_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3406_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3406_arg10 = rm; + auto fp_vector_vector_op_3406_arg11 = ret_val_sew_3407; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3390, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3391, 0, reinterpret_cast(this)); - setRet(call_sew_3391, 0, ret_val_sew_3391); - setArg(call_fp_vector_vector_op_3390, 0, V); - setArg(call_fp_vector_vector_op_3390, 1, 40); - setArg(call_fp_vector_vector_op_3390, 2, 1); - setArg(call_fp_vector_vector_op_3390, 3, fp_vector_vector_op_3390_arg3); - setArg(call_fp_vector_vector_op_3390, 4, fp_vector_vector_op_3390_arg4); - setArg(call_fp_vector_vector_op_3390, 5, fp_vector_vector_op_3390_arg5); - setArg(call_fp_vector_vector_op_3390, 6, vm); - setArg(call_fp_vector_vector_op_3390, 7, vd); - setArg(call_fp_vector_vector_op_3390, 8, vs2); - setArg(call_fp_vector_vector_op_3390, 9, vs1); - setArg(call_fp_vector_vector_op_3390, 10, fp_vector_vector_op_3390_arg10); - setArg(call_fp_vector_vector_op_3390, 11, fp_vector_vector_op_3390_arg11); - InvokeNode* call_fget_flags_3392; - x86::Gp ret_val_fget_flags_3392 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3392, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3392; - setRet(call_fget_flags_3392, 0, ret_val_fget_flags_3392); + cc.invoke(&call_fp_vector_vector_op_3406, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3407, 0, reinterpret_cast(this)); + setRet(call_sew_3407, 0, ret_val_sew_3407); + setArg(call_fp_vector_vector_op_3406, 0, V); + setArg(call_fp_vector_vector_op_3406, 1, 40); + setArg(call_fp_vector_vector_op_3406, 2, 1); + setArg(call_fp_vector_vector_op_3406, 3, fp_vector_vector_op_3406_arg3); + setArg(call_fp_vector_vector_op_3406, 4, fp_vector_vector_op_3406_arg4); + setArg(call_fp_vector_vector_op_3406, 5, fp_vector_vector_op_3406_arg5); + setArg(call_fp_vector_vector_op_3406, 6, vm); + setArg(call_fp_vector_vector_op_3406, 7, vd); + setArg(call_fp_vector_vector_op_3406, 8, vs2); + setArg(call_fp_vector_vector_op_3406, 9, vs1); + setArg(call_fp_vector_vector_op_3406, 10, fp_vector_vector_op_3406_arg10); + setArg(call_fp_vector_vector_op_3406, 11, fp_vector_vector_op_3406_arg11); + InvokeNode* call_fget_flags_3408; + x86::Gp ret_val_fget_flags_3408 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3408, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3408; + setRet(call_fget_flags_3408, 0, ret_val_fget_flags_3408); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3393 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3393, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3393, 32, false) - , traits::vstart); + auto tmp3409 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3409, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3409, traits::vstart); } cc.bind(label_merge); } @@ -78256,30 +77792,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3394; - x86::Gp ret_val_get_sew_pow_3394 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3394, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3395 = get_reg(cc, 8, false); - mov(cc, tmp3395, 1); + InvokeNode* call_get_sew_pow_3410; + x86::Gp ret_val_get_sew_pow_3410 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3410, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3411 = get_reg(cc, 8, false); + mov(cc, tmp3411, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3395, (ret_val_get_sew_pow_3394))), 8, false), ~ 1); - setArg(call_get_sew_pow_3394, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3394, 0, ret_val_get_sew_pow_3394); + (gen_operation(cc, shl, tmp3411, (ret_val_get_sew_pow_3410))), 8, false), ~ 1); + setArg(call_get_sew_pow_3410, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3410, 0, ret_val_get_sew_pow_3410); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3396; - auto illegal_fp_normal_3396_arg2 = SEW; - auto illegal_fp_normal_3396_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3396 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3396, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3396; - setArg(call_illegal_fp_normal_3396, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3396, 1, vd); - setArg(call_illegal_fp_normal_3396, 2, vm); - setArg(call_illegal_fp_normal_3396, 3, illegal_fp_normal_3396_arg2); - setArg(call_illegal_fp_normal_3396, 4, illegal_fp_normal_3396_arg3); - setRet(call_illegal_fp_normal_3396, 0, ret_val_illegal_fp_normal_3396); + InvokeNode* call_illegal_fp_normal_3412; + auto illegal_fp_normal_3412_arg2 = SEW; + auto illegal_fp_normal_3412_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3412 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3412, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3412; + setArg(call_illegal_fp_normal_3412, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3412, 1, vd); + setArg(call_illegal_fp_normal_3412, 2, vm); + setArg(call_illegal_fp_normal_3412, 3, illegal_fp_normal_3412_arg2); + setArg(call_illegal_fp_normal_3412, 4, illegal_fp_normal_3412_arg3); + setRet(call_illegal_fp_normal_3412, 0, ret_val_illegal_fp_normal_3412); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78295,47 +77831,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3398; - x86::Gp ret_val_sew_3398 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3398, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3397; - auto fp_vector_imm_op_3397_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3397_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3397_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3397_arg9 = gen_ext(cc, + InvokeNode* call_sew_3414; + x86::Gp ret_val_sew_3414 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3414, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3413; + auto fp_vector_imm_op_3413_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3413_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3413_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3413_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3397_arg10 = rm; - auto fp_vector_imm_op_3397_arg11 = ret_val_sew_3398; + auto fp_vector_imm_op_3413_arg10 = rm; + auto fp_vector_imm_op_3413_arg11 = ret_val_sew_3414; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3397, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3398, 0, reinterpret_cast(this)); - setRet(call_sew_3398, 0, ret_val_sew_3398); - setArg(call_fp_vector_imm_op_3397, 0, V); - setArg(call_fp_vector_imm_op_3397, 1, 41); - setArg(call_fp_vector_imm_op_3397, 2, 5); - setArg(call_fp_vector_imm_op_3397, 3, fp_vector_imm_op_3397_arg3); - setArg(call_fp_vector_imm_op_3397, 4, fp_vector_imm_op_3397_arg4); - setArg(call_fp_vector_imm_op_3397, 5, fp_vector_imm_op_3397_arg5); - setArg(call_fp_vector_imm_op_3397, 6, vm); - setArg(call_fp_vector_imm_op_3397, 7, vd); - setArg(call_fp_vector_imm_op_3397, 8, vs2); - setArg(call_fp_vector_imm_op_3397, 9, fp_vector_imm_op_3397_arg9); - setArg(call_fp_vector_imm_op_3397, 10, fp_vector_imm_op_3397_arg10); - setArg(call_fp_vector_imm_op_3397, 11, fp_vector_imm_op_3397_arg11); - InvokeNode* call_fget_flags_3399; - x86::Gp ret_val_fget_flags_3399 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3399, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3399; - setRet(call_fget_flags_3399, 0, ret_val_fget_flags_3399); + cc.invoke(&call_fp_vector_imm_op_3413, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3414, 0, reinterpret_cast(this)); + setRet(call_sew_3414, 0, ret_val_sew_3414); + setArg(call_fp_vector_imm_op_3413, 0, V); + setArg(call_fp_vector_imm_op_3413, 1, 41); + setArg(call_fp_vector_imm_op_3413, 2, 5); + setArg(call_fp_vector_imm_op_3413, 3, fp_vector_imm_op_3413_arg3); + setArg(call_fp_vector_imm_op_3413, 4, fp_vector_imm_op_3413_arg4); + setArg(call_fp_vector_imm_op_3413, 5, fp_vector_imm_op_3413_arg5); + setArg(call_fp_vector_imm_op_3413, 6, vm); + setArg(call_fp_vector_imm_op_3413, 7, vd); + setArg(call_fp_vector_imm_op_3413, 8, vs2); + setArg(call_fp_vector_imm_op_3413, 9, fp_vector_imm_op_3413_arg9); + setArg(call_fp_vector_imm_op_3413, 10, fp_vector_imm_op_3413_arg10); + setArg(call_fp_vector_imm_op_3413, 11, fp_vector_imm_op_3413_arg11); + InvokeNode* call_fget_flags_3415; + x86::Gp ret_val_fget_flags_3415 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3415, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3415; + setRet(call_fget_flags_3415, 0, ret_val_fget_flags_3415); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3400 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3400, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3400, 32, false) - , traits::vstart); + auto tmp3416 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3416, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3416, traits::vstart); } cc.bind(label_merge); } @@ -78379,30 +77913,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3401; - x86::Gp ret_val_get_sew_pow_3401 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3401, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3402 = get_reg(cc, 8, false); - mov(cc, tmp3402, 1); + InvokeNode* call_get_sew_pow_3417; + x86::Gp ret_val_get_sew_pow_3417 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3417, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3418 = get_reg(cc, 8, false); + mov(cc, tmp3418, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3402, (ret_val_get_sew_pow_3401))), 8, false), ~ 1); - setArg(call_get_sew_pow_3401, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3401, 0, ret_val_get_sew_pow_3401); + (gen_operation(cc, shl, tmp3418, (ret_val_get_sew_pow_3417))), 8, false), ~ 1); + setArg(call_get_sew_pow_3417, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3417, 0, ret_val_get_sew_pow_3417); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3403; - auto illegal_fp_normal_3403_arg2 = SEW; - auto illegal_fp_normal_3403_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3403 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3403, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3403; - setArg(call_illegal_fp_normal_3403, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3403, 1, vd); - setArg(call_illegal_fp_normal_3403, 2, vm); - setArg(call_illegal_fp_normal_3403, 3, illegal_fp_normal_3403_arg2); - setArg(call_illegal_fp_normal_3403, 4, illegal_fp_normal_3403_arg3); - setRet(call_illegal_fp_normal_3403, 0, ret_val_illegal_fp_normal_3403); + InvokeNode* call_illegal_fp_normal_3419; + auto illegal_fp_normal_3419_arg2 = SEW; + auto illegal_fp_normal_3419_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3419 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3419, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3419; + setArg(call_illegal_fp_normal_3419, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3419, 1, vd); + setArg(call_illegal_fp_normal_3419, 2, vm); + setArg(call_illegal_fp_normal_3419, 3, illegal_fp_normal_3419_arg2); + setArg(call_illegal_fp_normal_3419, 4, illegal_fp_normal_3419_arg3); + setRet(call_illegal_fp_normal_3419, 0, ret_val_illegal_fp_normal_3419); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78418,45 +77952,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3405; - x86::Gp ret_val_sew_3405 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3405, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3404; - auto fp_vector_vector_op_3404_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3404_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3404_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3404_arg10 = rm; - auto fp_vector_vector_op_3404_arg11 = ret_val_sew_3405; + InvokeNode* call_sew_3421; + x86::Gp ret_val_sew_3421 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3421, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3420; + auto fp_vector_vector_op_3420_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3420_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3420_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3420_arg10 = rm; + auto fp_vector_vector_op_3420_arg11 = ret_val_sew_3421; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3404, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3405, 0, reinterpret_cast(this)); - setRet(call_sew_3405, 0, ret_val_sew_3405); - setArg(call_fp_vector_vector_op_3404, 0, V); - setArg(call_fp_vector_vector_op_3404, 1, 41); - setArg(call_fp_vector_vector_op_3404, 2, 1); - setArg(call_fp_vector_vector_op_3404, 3, fp_vector_vector_op_3404_arg3); - setArg(call_fp_vector_vector_op_3404, 4, fp_vector_vector_op_3404_arg4); - setArg(call_fp_vector_vector_op_3404, 5, fp_vector_vector_op_3404_arg5); - setArg(call_fp_vector_vector_op_3404, 6, vm); - setArg(call_fp_vector_vector_op_3404, 7, vd); - setArg(call_fp_vector_vector_op_3404, 8, vs2); - setArg(call_fp_vector_vector_op_3404, 9, vs1); - setArg(call_fp_vector_vector_op_3404, 10, fp_vector_vector_op_3404_arg10); - setArg(call_fp_vector_vector_op_3404, 11, fp_vector_vector_op_3404_arg11); - InvokeNode* call_fget_flags_3406; - x86::Gp ret_val_fget_flags_3406 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3406, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3406; - setRet(call_fget_flags_3406, 0, ret_val_fget_flags_3406); + cc.invoke(&call_fp_vector_vector_op_3420, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3421, 0, reinterpret_cast(this)); + setRet(call_sew_3421, 0, ret_val_sew_3421); + setArg(call_fp_vector_vector_op_3420, 0, V); + setArg(call_fp_vector_vector_op_3420, 1, 41); + setArg(call_fp_vector_vector_op_3420, 2, 1); + setArg(call_fp_vector_vector_op_3420, 3, fp_vector_vector_op_3420_arg3); + setArg(call_fp_vector_vector_op_3420, 4, fp_vector_vector_op_3420_arg4); + setArg(call_fp_vector_vector_op_3420, 5, fp_vector_vector_op_3420_arg5); + setArg(call_fp_vector_vector_op_3420, 6, vm); + setArg(call_fp_vector_vector_op_3420, 7, vd); + setArg(call_fp_vector_vector_op_3420, 8, vs2); + setArg(call_fp_vector_vector_op_3420, 9, vs1); + setArg(call_fp_vector_vector_op_3420, 10, fp_vector_vector_op_3420_arg10); + setArg(call_fp_vector_vector_op_3420, 11, fp_vector_vector_op_3420_arg11); + InvokeNode* call_fget_flags_3422; + x86::Gp ret_val_fget_flags_3422 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3422, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3422; + setRet(call_fget_flags_3422, 0, ret_val_fget_flags_3422); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3407 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3407, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3407, 32, false) - , traits::vstart); + auto tmp3423 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3423, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3423, traits::vstart); } cc.bind(label_merge); } @@ -78500,30 +78032,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3408; - x86::Gp ret_val_get_sew_pow_3408 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3408, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3409 = get_reg(cc, 8, false); - mov(cc, tmp3409, 1); + InvokeNode* call_get_sew_pow_3424; + x86::Gp ret_val_get_sew_pow_3424 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3424, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3425 = get_reg(cc, 8, false); + mov(cc, tmp3425, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3409, (ret_val_get_sew_pow_3408))), 8, false), ~ 1); - setArg(call_get_sew_pow_3408, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3408, 0, ret_val_get_sew_pow_3408); + (gen_operation(cc, shl, tmp3425, (ret_val_get_sew_pow_3424))), 8, false), ~ 1); + setArg(call_get_sew_pow_3424, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3424, 0, ret_val_get_sew_pow_3424); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3410; - auto illegal_fp_normal_3410_arg2 = SEW; - auto illegal_fp_normal_3410_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3410 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3410, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3410; - setArg(call_illegal_fp_normal_3410, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3410, 1, vd); - setArg(call_illegal_fp_normal_3410, 2, vm); - setArg(call_illegal_fp_normal_3410, 3, illegal_fp_normal_3410_arg2); - setArg(call_illegal_fp_normal_3410, 4, illegal_fp_normal_3410_arg3); - setRet(call_illegal_fp_normal_3410, 0, ret_val_illegal_fp_normal_3410); + InvokeNode* call_illegal_fp_normal_3426; + auto illegal_fp_normal_3426_arg2 = SEW; + auto illegal_fp_normal_3426_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3426 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3426, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3426; + setArg(call_illegal_fp_normal_3426, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3426, 1, vd); + setArg(call_illegal_fp_normal_3426, 2, vm); + setArg(call_illegal_fp_normal_3426, 3, illegal_fp_normal_3426_arg2); + setArg(call_illegal_fp_normal_3426, 4, illegal_fp_normal_3426_arg3); + setRet(call_illegal_fp_normal_3426, 0, ret_val_illegal_fp_normal_3426); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78539,47 +78071,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3412; - x86::Gp ret_val_sew_3412 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3412, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3411; - auto fp_vector_imm_op_3411_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3411_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3411_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3411_arg9 = gen_ext(cc, + InvokeNode* call_sew_3428; + x86::Gp ret_val_sew_3428 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3428, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3427; + auto fp_vector_imm_op_3427_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3427_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3427_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3427_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3411_arg10 = rm; - auto fp_vector_imm_op_3411_arg11 = ret_val_sew_3412; + auto fp_vector_imm_op_3427_arg10 = rm; + auto fp_vector_imm_op_3427_arg11 = ret_val_sew_3428; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3411, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3412, 0, reinterpret_cast(this)); - setRet(call_sew_3412, 0, ret_val_sew_3412); - setArg(call_fp_vector_imm_op_3411, 0, V); - setArg(call_fp_vector_imm_op_3411, 1, 42); - setArg(call_fp_vector_imm_op_3411, 2, 5); - setArg(call_fp_vector_imm_op_3411, 3, fp_vector_imm_op_3411_arg3); - setArg(call_fp_vector_imm_op_3411, 4, fp_vector_imm_op_3411_arg4); - setArg(call_fp_vector_imm_op_3411, 5, fp_vector_imm_op_3411_arg5); - setArg(call_fp_vector_imm_op_3411, 6, vm); - setArg(call_fp_vector_imm_op_3411, 7, vd); - setArg(call_fp_vector_imm_op_3411, 8, vs2); - setArg(call_fp_vector_imm_op_3411, 9, fp_vector_imm_op_3411_arg9); - setArg(call_fp_vector_imm_op_3411, 10, fp_vector_imm_op_3411_arg10); - setArg(call_fp_vector_imm_op_3411, 11, fp_vector_imm_op_3411_arg11); - InvokeNode* call_fget_flags_3413; - x86::Gp ret_val_fget_flags_3413 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3413, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3413; - setRet(call_fget_flags_3413, 0, ret_val_fget_flags_3413); + cc.invoke(&call_fp_vector_imm_op_3427, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3428, 0, reinterpret_cast(this)); + setRet(call_sew_3428, 0, ret_val_sew_3428); + setArg(call_fp_vector_imm_op_3427, 0, V); + setArg(call_fp_vector_imm_op_3427, 1, 42); + setArg(call_fp_vector_imm_op_3427, 2, 5); + setArg(call_fp_vector_imm_op_3427, 3, fp_vector_imm_op_3427_arg3); + setArg(call_fp_vector_imm_op_3427, 4, fp_vector_imm_op_3427_arg4); + setArg(call_fp_vector_imm_op_3427, 5, fp_vector_imm_op_3427_arg5); + setArg(call_fp_vector_imm_op_3427, 6, vm); + setArg(call_fp_vector_imm_op_3427, 7, vd); + setArg(call_fp_vector_imm_op_3427, 8, vs2); + setArg(call_fp_vector_imm_op_3427, 9, fp_vector_imm_op_3427_arg9); + setArg(call_fp_vector_imm_op_3427, 10, fp_vector_imm_op_3427_arg10); + setArg(call_fp_vector_imm_op_3427, 11, fp_vector_imm_op_3427_arg11); + InvokeNode* call_fget_flags_3429; + x86::Gp ret_val_fget_flags_3429 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3429, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3429; + setRet(call_fget_flags_3429, 0, ret_val_fget_flags_3429); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3414 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3414, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3414, 32, false) - , traits::vstart); + auto tmp3430 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3430, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3430, traits::vstart); } cc.bind(label_merge); } @@ -78623,30 +78153,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3415; - x86::Gp ret_val_get_sew_pow_3415 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3415, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3416 = get_reg(cc, 8, false); - mov(cc, tmp3416, 1); + InvokeNode* call_get_sew_pow_3431; + x86::Gp ret_val_get_sew_pow_3431 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3431, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3432 = get_reg(cc, 8, false); + mov(cc, tmp3432, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3416, (ret_val_get_sew_pow_3415))), 8, false), ~ 1); - setArg(call_get_sew_pow_3415, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3415, 0, ret_val_get_sew_pow_3415); + (gen_operation(cc, shl, tmp3432, (ret_val_get_sew_pow_3431))), 8, false), ~ 1); + setArg(call_get_sew_pow_3431, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3431, 0, ret_val_get_sew_pow_3431); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3417; - auto illegal_fp_normal_3417_arg2 = SEW; - auto illegal_fp_normal_3417_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3417 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3417, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3417; - setArg(call_illegal_fp_normal_3417, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3417, 1, vd); - setArg(call_illegal_fp_normal_3417, 2, vm); - setArg(call_illegal_fp_normal_3417, 3, illegal_fp_normal_3417_arg2); - setArg(call_illegal_fp_normal_3417, 4, illegal_fp_normal_3417_arg3); - setRet(call_illegal_fp_normal_3417, 0, ret_val_illegal_fp_normal_3417); + InvokeNode* call_illegal_fp_normal_3433; + auto illegal_fp_normal_3433_arg2 = SEW; + auto illegal_fp_normal_3433_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3433 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3433, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3433; + setArg(call_illegal_fp_normal_3433, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3433, 1, vd); + setArg(call_illegal_fp_normal_3433, 2, vm); + setArg(call_illegal_fp_normal_3433, 3, illegal_fp_normal_3433_arg2); + setArg(call_illegal_fp_normal_3433, 4, illegal_fp_normal_3433_arg3); + setRet(call_illegal_fp_normal_3433, 0, ret_val_illegal_fp_normal_3433); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78662,45 +78192,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3419; - x86::Gp ret_val_sew_3419 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3419, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3418; - auto fp_vector_vector_op_3418_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3418_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3418_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3418_arg10 = rm; - auto fp_vector_vector_op_3418_arg11 = ret_val_sew_3419; + InvokeNode* call_sew_3435; + x86::Gp ret_val_sew_3435 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3435, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3434; + auto fp_vector_vector_op_3434_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3434_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3434_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3434_arg10 = rm; + auto fp_vector_vector_op_3434_arg11 = ret_val_sew_3435; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3418, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3419, 0, reinterpret_cast(this)); - setRet(call_sew_3419, 0, ret_val_sew_3419); - setArg(call_fp_vector_vector_op_3418, 0, V); - setArg(call_fp_vector_vector_op_3418, 1, 42); - setArg(call_fp_vector_vector_op_3418, 2, 1); - setArg(call_fp_vector_vector_op_3418, 3, fp_vector_vector_op_3418_arg3); - setArg(call_fp_vector_vector_op_3418, 4, fp_vector_vector_op_3418_arg4); - setArg(call_fp_vector_vector_op_3418, 5, fp_vector_vector_op_3418_arg5); - setArg(call_fp_vector_vector_op_3418, 6, vm); - setArg(call_fp_vector_vector_op_3418, 7, vd); - setArg(call_fp_vector_vector_op_3418, 8, vs2); - setArg(call_fp_vector_vector_op_3418, 9, vs1); - setArg(call_fp_vector_vector_op_3418, 10, fp_vector_vector_op_3418_arg10); - setArg(call_fp_vector_vector_op_3418, 11, fp_vector_vector_op_3418_arg11); - InvokeNode* call_fget_flags_3420; - x86::Gp ret_val_fget_flags_3420 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3420, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3420; - setRet(call_fget_flags_3420, 0, ret_val_fget_flags_3420); + cc.invoke(&call_fp_vector_vector_op_3434, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3435, 0, reinterpret_cast(this)); + setRet(call_sew_3435, 0, ret_val_sew_3435); + setArg(call_fp_vector_vector_op_3434, 0, V); + setArg(call_fp_vector_vector_op_3434, 1, 42); + setArg(call_fp_vector_vector_op_3434, 2, 1); + setArg(call_fp_vector_vector_op_3434, 3, fp_vector_vector_op_3434_arg3); + setArg(call_fp_vector_vector_op_3434, 4, fp_vector_vector_op_3434_arg4); + setArg(call_fp_vector_vector_op_3434, 5, fp_vector_vector_op_3434_arg5); + setArg(call_fp_vector_vector_op_3434, 6, vm); + setArg(call_fp_vector_vector_op_3434, 7, vd); + setArg(call_fp_vector_vector_op_3434, 8, vs2); + setArg(call_fp_vector_vector_op_3434, 9, vs1); + setArg(call_fp_vector_vector_op_3434, 10, fp_vector_vector_op_3434_arg10); + setArg(call_fp_vector_vector_op_3434, 11, fp_vector_vector_op_3434_arg11); + InvokeNode* call_fget_flags_3436; + x86::Gp ret_val_fget_flags_3436 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3436, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3436; + setRet(call_fget_flags_3436, 0, ret_val_fget_flags_3436); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3421 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3421, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3421, 32, false) - , traits::vstart); + auto tmp3437 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3437, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3437, traits::vstart); } cc.bind(label_merge); } @@ -78744,30 +78272,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3422; - x86::Gp ret_val_get_sew_pow_3422 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3422, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3423 = get_reg(cc, 8, false); - mov(cc, tmp3423, 1); + InvokeNode* call_get_sew_pow_3438; + x86::Gp ret_val_get_sew_pow_3438 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3438, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3439 = get_reg(cc, 8, false); + mov(cc, tmp3439, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3423, (ret_val_get_sew_pow_3422))), 8, false), ~ 1); - setArg(call_get_sew_pow_3422, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3422, 0, ret_val_get_sew_pow_3422); + (gen_operation(cc, shl, tmp3439, (ret_val_get_sew_pow_3438))), 8, false), ~ 1); + setArg(call_get_sew_pow_3438, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3438, 0, ret_val_get_sew_pow_3438); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3424; - auto illegal_fp_normal_3424_arg2 = SEW; - auto illegal_fp_normal_3424_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3424 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3424, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3424; - setArg(call_illegal_fp_normal_3424, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3424, 1, vd); - setArg(call_illegal_fp_normal_3424, 2, vm); - setArg(call_illegal_fp_normal_3424, 3, illegal_fp_normal_3424_arg2); - setArg(call_illegal_fp_normal_3424, 4, illegal_fp_normal_3424_arg3); - setRet(call_illegal_fp_normal_3424, 0, ret_val_illegal_fp_normal_3424); + InvokeNode* call_illegal_fp_normal_3440; + auto illegal_fp_normal_3440_arg2 = SEW; + auto illegal_fp_normal_3440_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3440 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3440, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3440; + setArg(call_illegal_fp_normal_3440, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3440, 1, vd); + setArg(call_illegal_fp_normal_3440, 2, vm); + setArg(call_illegal_fp_normal_3440, 3, illegal_fp_normal_3440_arg2); + setArg(call_illegal_fp_normal_3440, 4, illegal_fp_normal_3440_arg3); + setRet(call_illegal_fp_normal_3440, 0, ret_val_illegal_fp_normal_3440); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78783,47 +78311,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3426; - x86::Gp ret_val_sew_3426 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3426, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3425; - auto fp_vector_imm_op_3425_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3425_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3425_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3425_arg9 = gen_ext(cc, + InvokeNode* call_sew_3442; + x86::Gp ret_val_sew_3442 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3442, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3441; + auto fp_vector_imm_op_3441_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3441_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3441_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3441_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3425_arg10 = rm; - auto fp_vector_imm_op_3425_arg11 = ret_val_sew_3426; + auto fp_vector_imm_op_3441_arg10 = rm; + auto fp_vector_imm_op_3441_arg11 = ret_val_sew_3442; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3425, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3426, 0, reinterpret_cast(this)); - setRet(call_sew_3426, 0, ret_val_sew_3426); - setArg(call_fp_vector_imm_op_3425, 0, V); - setArg(call_fp_vector_imm_op_3425, 1, 43); - setArg(call_fp_vector_imm_op_3425, 2, 5); - setArg(call_fp_vector_imm_op_3425, 3, fp_vector_imm_op_3425_arg3); - setArg(call_fp_vector_imm_op_3425, 4, fp_vector_imm_op_3425_arg4); - setArg(call_fp_vector_imm_op_3425, 5, fp_vector_imm_op_3425_arg5); - setArg(call_fp_vector_imm_op_3425, 6, vm); - setArg(call_fp_vector_imm_op_3425, 7, vd); - setArg(call_fp_vector_imm_op_3425, 8, vs2); - setArg(call_fp_vector_imm_op_3425, 9, fp_vector_imm_op_3425_arg9); - setArg(call_fp_vector_imm_op_3425, 10, fp_vector_imm_op_3425_arg10); - setArg(call_fp_vector_imm_op_3425, 11, fp_vector_imm_op_3425_arg11); - InvokeNode* call_fget_flags_3427; - x86::Gp ret_val_fget_flags_3427 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3427, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3427; - setRet(call_fget_flags_3427, 0, ret_val_fget_flags_3427); + cc.invoke(&call_fp_vector_imm_op_3441, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3442, 0, reinterpret_cast(this)); + setRet(call_sew_3442, 0, ret_val_sew_3442); + setArg(call_fp_vector_imm_op_3441, 0, V); + setArg(call_fp_vector_imm_op_3441, 1, 43); + setArg(call_fp_vector_imm_op_3441, 2, 5); + setArg(call_fp_vector_imm_op_3441, 3, fp_vector_imm_op_3441_arg3); + setArg(call_fp_vector_imm_op_3441, 4, fp_vector_imm_op_3441_arg4); + setArg(call_fp_vector_imm_op_3441, 5, fp_vector_imm_op_3441_arg5); + setArg(call_fp_vector_imm_op_3441, 6, vm); + setArg(call_fp_vector_imm_op_3441, 7, vd); + setArg(call_fp_vector_imm_op_3441, 8, vs2); + setArg(call_fp_vector_imm_op_3441, 9, fp_vector_imm_op_3441_arg9); + setArg(call_fp_vector_imm_op_3441, 10, fp_vector_imm_op_3441_arg10); + setArg(call_fp_vector_imm_op_3441, 11, fp_vector_imm_op_3441_arg11); + InvokeNode* call_fget_flags_3443; + x86::Gp ret_val_fget_flags_3443 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3443, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3443; + setRet(call_fget_flags_3443, 0, ret_val_fget_flags_3443); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3428 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3428, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3428, 32, false) - , traits::vstart); + auto tmp3444 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3444, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3444, traits::vstart); } cc.bind(label_merge); } @@ -78867,30 +78393,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3429; - x86::Gp ret_val_get_sew_pow_3429 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3429, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3430 = get_reg(cc, 8, false); - mov(cc, tmp3430, 1); + InvokeNode* call_get_sew_pow_3445; + x86::Gp ret_val_get_sew_pow_3445 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3445, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3446 = get_reg(cc, 8, false); + mov(cc, tmp3446, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3430, (ret_val_get_sew_pow_3429))), 8, false), ~ 1); - setArg(call_get_sew_pow_3429, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3429, 0, ret_val_get_sew_pow_3429); + (gen_operation(cc, shl, tmp3446, (ret_val_get_sew_pow_3445))), 8, false), ~ 1); + setArg(call_get_sew_pow_3445, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3445, 0, ret_val_get_sew_pow_3445); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3431; - auto illegal_fp_normal_3431_arg2 = SEW; - auto illegal_fp_normal_3431_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3431 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3431, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3431; - setArg(call_illegal_fp_normal_3431, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3431, 1, vd); - setArg(call_illegal_fp_normal_3431, 2, vm); - setArg(call_illegal_fp_normal_3431, 3, illegal_fp_normal_3431_arg2); - setArg(call_illegal_fp_normal_3431, 4, illegal_fp_normal_3431_arg3); - setRet(call_illegal_fp_normal_3431, 0, ret_val_illegal_fp_normal_3431); + InvokeNode* call_illegal_fp_normal_3447; + auto illegal_fp_normal_3447_arg2 = SEW; + auto illegal_fp_normal_3447_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3447 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3447, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3447; + setArg(call_illegal_fp_normal_3447, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3447, 1, vd); + setArg(call_illegal_fp_normal_3447, 2, vm); + setArg(call_illegal_fp_normal_3447, 3, illegal_fp_normal_3447_arg2); + setArg(call_illegal_fp_normal_3447, 4, illegal_fp_normal_3447_arg3); + setRet(call_illegal_fp_normal_3447, 0, ret_val_illegal_fp_normal_3447); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78906,45 +78432,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3433; - x86::Gp ret_val_sew_3433 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3433, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3432; - auto fp_vector_vector_op_3432_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3432_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3432_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3432_arg10 = rm; - auto fp_vector_vector_op_3432_arg11 = ret_val_sew_3433; + InvokeNode* call_sew_3449; + x86::Gp ret_val_sew_3449 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3449, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3448; + auto fp_vector_vector_op_3448_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3448_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3448_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3448_arg10 = rm; + auto fp_vector_vector_op_3448_arg11 = ret_val_sew_3449; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3432, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3433, 0, reinterpret_cast(this)); - setRet(call_sew_3433, 0, ret_val_sew_3433); - setArg(call_fp_vector_vector_op_3432, 0, V); - setArg(call_fp_vector_vector_op_3432, 1, 43); - setArg(call_fp_vector_vector_op_3432, 2, 1); - setArg(call_fp_vector_vector_op_3432, 3, fp_vector_vector_op_3432_arg3); - setArg(call_fp_vector_vector_op_3432, 4, fp_vector_vector_op_3432_arg4); - setArg(call_fp_vector_vector_op_3432, 5, fp_vector_vector_op_3432_arg5); - setArg(call_fp_vector_vector_op_3432, 6, vm); - setArg(call_fp_vector_vector_op_3432, 7, vd); - setArg(call_fp_vector_vector_op_3432, 8, vs2); - setArg(call_fp_vector_vector_op_3432, 9, vs1); - setArg(call_fp_vector_vector_op_3432, 10, fp_vector_vector_op_3432_arg10); - setArg(call_fp_vector_vector_op_3432, 11, fp_vector_vector_op_3432_arg11); - InvokeNode* call_fget_flags_3434; - x86::Gp ret_val_fget_flags_3434 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3434, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3434; - setRet(call_fget_flags_3434, 0, ret_val_fget_flags_3434); + cc.invoke(&call_fp_vector_vector_op_3448, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3449, 0, reinterpret_cast(this)); + setRet(call_sew_3449, 0, ret_val_sew_3449); + setArg(call_fp_vector_vector_op_3448, 0, V); + setArg(call_fp_vector_vector_op_3448, 1, 43); + setArg(call_fp_vector_vector_op_3448, 2, 1); + setArg(call_fp_vector_vector_op_3448, 3, fp_vector_vector_op_3448_arg3); + setArg(call_fp_vector_vector_op_3448, 4, fp_vector_vector_op_3448_arg4); + setArg(call_fp_vector_vector_op_3448, 5, fp_vector_vector_op_3448_arg5); + setArg(call_fp_vector_vector_op_3448, 6, vm); + setArg(call_fp_vector_vector_op_3448, 7, vd); + setArg(call_fp_vector_vector_op_3448, 8, vs2); + setArg(call_fp_vector_vector_op_3448, 9, vs1); + setArg(call_fp_vector_vector_op_3448, 10, fp_vector_vector_op_3448_arg10); + setArg(call_fp_vector_vector_op_3448, 11, fp_vector_vector_op_3448_arg11); + InvokeNode* call_fget_flags_3450; + x86::Gp ret_val_fget_flags_3450 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3450, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3450; + setRet(call_fget_flags_3450, 0, ret_val_fget_flags_3450); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3435 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3435, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3435, 32, false) - , traits::vstart); + auto tmp3451 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3451, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3451, traits::vstart); } cc.bind(label_merge); } @@ -78988,54 +78512,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3436; - x86::Gp ret_val_get_sew_pow_3436 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3436, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3437 = get_reg(cc, 8, false); - mov(cc, tmp3437, 1); + InvokeNode* call_get_sew_pow_3452; + x86::Gp ret_val_get_sew_pow_3452 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3452, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3453 = get_reg(cc, 8, false); + mov(cc, tmp3453, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3437, (ret_val_get_sew_pow_3436))), 8, false), ~ 1); - setArg(call_get_sew_pow_3436, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3436, 0, ret_val_get_sew_pow_3436); - InvokeNode* call_get_lmul_pow_3438; - x86::Gp ret_val_get_lmul_pow_3438 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3438, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3438; - setArg(call_get_lmul_pow_3438, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3438, 0, ret_val_get_lmul_pow_3438); + (gen_operation(cc, shl, tmp3453, (ret_val_get_sew_pow_3452))), 8, false), ~ 1); + setArg(call_get_sew_pow_3452, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3452, 0, ret_val_get_sew_pow_3452); + InvokeNode* call_get_lmul_pow_3454; + x86::Gp ret_val_get_lmul_pow_3454 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3454, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3454; + setArg(call_get_lmul_pow_3454, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3454, 0, ret_val_get_lmul_pow_3454); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3439; - auto illegal_fp_variable_width_3439_arg2 = SEW; - auto illegal_fp_variable_width_3439_arg3 = rm; - auto illegal_fp_variable_width_3439_arg4 = SEW_widen; - auto illegal_fp_variable_width_3439_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3439 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3439, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3440; - auto valid_reg_overlap_3440_arg2 = LMUL_pow; - auto valid_reg_overlap_3440_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3440 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3440, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3439, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3440)); - setArg(call_illegal_fp_variable_width_3439, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3439, 1, vd); - setArg(call_illegal_fp_variable_width_3439, 2, vm); - setArg(call_illegal_fp_variable_width_3439, 3, illegal_fp_variable_width_3439_arg2); - setArg(call_illegal_fp_variable_width_3439, 4, illegal_fp_variable_width_3439_arg3); - setArg(call_illegal_fp_variable_width_3439, 5, illegal_fp_variable_width_3439_arg4); - setArg(call_illegal_fp_variable_width_3439, 6, illegal_fp_variable_width_3439_arg5); - setRet(call_illegal_fp_variable_width_3439, 0, ret_val_illegal_fp_variable_width_3439); - setArg(call_valid_reg_overlap_3440, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3440, 1, vs2); - setArg(call_valid_reg_overlap_3440, 2, vd); - setArg(call_valid_reg_overlap_3440, 3, valid_reg_overlap_3440_arg2); - setArg(call_valid_reg_overlap_3440, 4, valid_reg_overlap_3440_arg3); - setRet(call_valid_reg_overlap_3440, 0, ret_val_valid_reg_overlap_3440); + InvokeNode* call_illegal_fp_variable_width_3455; + auto illegal_fp_variable_width_3455_arg2 = SEW; + auto illegal_fp_variable_width_3455_arg3 = rm; + auto illegal_fp_variable_width_3455_arg4 = SEW_widen; + auto illegal_fp_variable_width_3455_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3455 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3455, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3456; + auto valid_reg_overlap_3456_arg2 = LMUL_pow; + auto valid_reg_overlap_3456_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3456 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3456, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3455, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3456)); + setArg(call_illegal_fp_variable_width_3455, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3455, 1, vd); + setArg(call_illegal_fp_variable_width_3455, 2, vm); + setArg(call_illegal_fp_variable_width_3455, 3, illegal_fp_variable_width_3455_arg2); + setArg(call_illegal_fp_variable_width_3455, 4, illegal_fp_variable_width_3455_arg3); + setArg(call_illegal_fp_variable_width_3455, 5, illegal_fp_variable_width_3455_arg4); + setArg(call_illegal_fp_variable_width_3455, 6, illegal_fp_variable_width_3455_arg5); + setRet(call_illegal_fp_variable_width_3455, 0, ret_val_illegal_fp_variable_width_3455); + setArg(call_valid_reg_overlap_3456, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3456, 1, vs2); + setArg(call_valid_reg_overlap_3456, 2, vd); + setArg(call_valid_reg_overlap_3456, 3, valid_reg_overlap_3456_arg2); + setArg(call_valid_reg_overlap_3456, 4, valid_reg_overlap_3456_arg3); + setRet(call_valid_reg_overlap_3456, 0, ret_val_valid_reg_overlap_3456); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79051,47 +78575,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3442; - x86::Gp ret_val_sew_3442 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3442, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3441; - auto fp_vector_imm_wv_3441_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3441_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3441_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3441_arg9 = gen_ext(cc, + InvokeNode* call_sew_3458; + x86::Gp ret_val_sew_3458 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3458, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3457; + auto fp_vector_imm_wv_3457_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3457_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3457_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3457_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_wv_3441_arg10 = rm; - auto fp_vector_imm_wv_3441_arg11 = ret_val_sew_3442; + auto fp_vector_imm_wv_3457_arg10 = rm; + auto fp_vector_imm_wv_3457_arg11 = ret_val_sew_3458; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3441, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3442, 0, reinterpret_cast(this)); - setRet(call_sew_3442, 0, ret_val_sew_3442); - setArg(call_fp_vector_imm_wv_3441, 0, V); - setArg(call_fp_vector_imm_wv_3441, 1, 60); - setArg(call_fp_vector_imm_wv_3441, 2, 5); - setArg(call_fp_vector_imm_wv_3441, 3, fp_vector_imm_wv_3441_arg3); - setArg(call_fp_vector_imm_wv_3441, 4, fp_vector_imm_wv_3441_arg4); - setArg(call_fp_vector_imm_wv_3441, 5, fp_vector_imm_wv_3441_arg5); - setArg(call_fp_vector_imm_wv_3441, 6, vm); - setArg(call_fp_vector_imm_wv_3441, 7, vd); - setArg(call_fp_vector_imm_wv_3441, 8, vs2); - setArg(call_fp_vector_imm_wv_3441, 9, fp_vector_imm_wv_3441_arg9); - setArg(call_fp_vector_imm_wv_3441, 10, fp_vector_imm_wv_3441_arg10); - setArg(call_fp_vector_imm_wv_3441, 11, fp_vector_imm_wv_3441_arg11); - InvokeNode* call_fget_flags_3443; - x86::Gp ret_val_fget_flags_3443 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3443, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3443; - setRet(call_fget_flags_3443, 0, ret_val_fget_flags_3443); + cc.invoke(&call_fp_vector_imm_wv_3457, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3458, 0, reinterpret_cast(this)); + setRet(call_sew_3458, 0, ret_val_sew_3458); + setArg(call_fp_vector_imm_wv_3457, 0, V); + setArg(call_fp_vector_imm_wv_3457, 1, 60); + setArg(call_fp_vector_imm_wv_3457, 2, 5); + setArg(call_fp_vector_imm_wv_3457, 3, fp_vector_imm_wv_3457_arg3); + setArg(call_fp_vector_imm_wv_3457, 4, fp_vector_imm_wv_3457_arg4); + setArg(call_fp_vector_imm_wv_3457, 5, fp_vector_imm_wv_3457_arg5); + setArg(call_fp_vector_imm_wv_3457, 6, vm); + setArg(call_fp_vector_imm_wv_3457, 7, vd); + setArg(call_fp_vector_imm_wv_3457, 8, vs2); + setArg(call_fp_vector_imm_wv_3457, 9, fp_vector_imm_wv_3457_arg9); + setArg(call_fp_vector_imm_wv_3457, 10, fp_vector_imm_wv_3457_arg10); + setArg(call_fp_vector_imm_wv_3457, 11, fp_vector_imm_wv_3457_arg11); + InvokeNode* call_fget_flags_3459; + x86::Gp ret_val_fget_flags_3459 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3459, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3459; + setRet(call_fget_flags_3459, 0, ret_val_fget_flags_3459); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3444 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3444, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3444, 32, false) - , traits::vstart); + auto tmp3460 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3460, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3460, traits::vstart); } cc.bind(label_merge); } @@ -79135,65 +78657,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3445; - x86::Gp ret_val_get_sew_pow_3445 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3445, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3446 = get_reg(cc, 8, false); - mov(cc, tmp3446, 1); + InvokeNode* call_get_sew_pow_3461; + x86::Gp ret_val_get_sew_pow_3461 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3461, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3462 = get_reg(cc, 8, false); + mov(cc, tmp3462, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3446, (ret_val_get_sew_pow_3445))), 8, false), ~ 1); - setArg(call_get_sew_pow_3445, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3445, 0, ret_val_get_sew_pow_3445); - InvokeNode* call_get_lmul_pow_3447; - x86::Gp ret_val_get_lmul_pow_3447 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3447, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3447; - setArg(call_get_lmul_pow_3447, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3447, 0, ret_val_get_lmul_pow_3447); + (gen_operation(cc, shl, tmp3462, (ret_val_get_sew_pow_3461))), 8, false), ~ 1); + setArg(call_get_sew_pow_3461, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3461, 0, ret_val_get_sew_pow_3461); + InvokeNode* call_get_lmul_pow_3463; + x86::Gp ret_val_get_lmul_pow_3463 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3463, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3463; + setArg(call_get_lmul_pow_3463, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3463, 0, ret_val_get_lmul_pow_3463); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3448; - auto illegal_fp_variable_width_3448_arg2 = SEW; - auto illegal_fp_variable_width_3448_arg3 = rm; - auto illegal_fp_variable_width_3448_arg4 = SEW_widen; - auto illegal_fp_variable_width_3448_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3448 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3448, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3449; - auto valid_reg_overlap_3449_arg2 = LMUL_pow; - auto valid_reg_overlap_3449_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3449 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3449, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3450; - auto valid_reg_overlap_3450_arg2 = LMUL_pow; - auto valid_reg_overlap_3450_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3450 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3450, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3448, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3449)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3450)); - setArg(call_illegal_fp_variable_width_3448, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3448, 1, vd); - setArg(call_illegal_fp_variable_width_3448, 2, vm); - setArg(call_illegal_fp_variable_width_3448, 3, illegal_fp_variable_width_3448_arg2); - setArg(call_illegal_fp_variable_width_3448, 4, illegal_fp_variable_width_3448_arg3); - setArg(call_illegal_fp_variable_width_3448, 5, illegal_fp_variable_width_3448_arg4); - setArg(call_illegal_fp_variable_width_3448, 6, illegal_fp_variable_width_3448_arg5); - setRet(call_illegal_fp_variable_width_3448, 0, ret_val_illegal_fp_variable_width_3448); - setArg(call_valid_reg_overlap_3449, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3449, 1, vs1); - setArg(call_valid_reg_overlap_3449, 2, vd); - setArg(call_valid_reg_overlap_3449, 3, valid_reg_overlap_3449_arg2); - setArg(call_valid_reg_overlap_3449, 4, valid_reg_overlap_3449_arg3); - setRet(call_valid_reg_overlap_3449, 0, ret_val_valid_reg_overlap_3449); - setArg(call_valid_reg_overlap_3450, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3450, 1, vs2); - setArg(call_valid_reg_overlap_3450, 2, vd); - setArg(call_valid_reg_overlap_3450, 3, valid_reg_overlap_3450_arg2); - setArg(call_valid_reg_overlap_3450, 4, valid_reg_overlap_3450_arg3); - setRet(call_valid_reg_overlap_3450, 0, ret_val_valid_reg_overlap_3450); + InvokeNode* call_illegal_fp_variable_width_3464; + auto illegal_fp_variable_width_3464_arg2 = SEW; + auto illegal_fp_variable_width_3464_arg3 = rm; + auto illegal_fp_variable_width_3464_arg4 = SEW_widen; + auto illegal_fp_variable_width_3464_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3464 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3464, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3465; + auto valid_reg_overlap_3465_arg2 = LMUL_pow; + auto valid_reg_overlap_3465_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3465 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3465, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3466; + auto valid_reg_overlap_3466_arg2 = LMUL_pow; + auto valid_reg_overlap_3466_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3466 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3466, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3464, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3465)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3466)); + setArg(call_illegal_fp_variable_width_3464, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3464, 1, vd); + setArg(call_illegal_fp_variable_width_3464, 2, vm); + setArg(call_illegal_fp_variable_width_3464, 3, illegal_fp_variable_width_3464_arg2); + setArg(call_illegal_fp_variable_width_3464, 4, illegal_fp_variable_width_3464_arg3); + setArg(call_illegal_fp_variable_width_3464, 5, illegal_fp_variable_width_3464_arg4); + setArg(call_illegal_fp_variable_width_3464, 6, illegal_fp_variable_width_3464_arg5); + setRet(call_illegal_fp_variable_width_3464, 0, ret_val_illegal_fp_variable_width_3464); + setArg(call_valid_reg_overlap_3465, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3465, 1, vs1); + setArg(call_valid_reg_overlap_3465, 2, vd); + setArg(call_valid_reg_overlap_3465, 3, valid_reg_overlap_3465_arg2); + setArg(call_valid_reg_overlap_3465, 4, valid_reg_overlap_3465_arg3); + setRet(call_valid_reg_overlap_3465, 0, ret_val_valid_reg_overlap_3465); + setArg(call_valid_reg_overlap_3466, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3466, 1, vs2); + setArg(call_valid_reg_overlap_3466, 2, vd); + setArg(call_valid_reg_overlap_3466, 3, valid_reg_overlap_3466_arg2); + setArg(call_valid_reg_overlap_3466, 4, valid_reg_overlap_3466_arg3); + setRet(call_valid_reg_overlap_3466, 0, ret_val_valid_reg_overlap_3466); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79209,45 +78731,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3452; - x86::Gp ret_val_sew_3452 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3452, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3451; - auto fp_vector_vector_wv_3451_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3451_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3451_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3451_arg10 = rm; - auto fp_vector_vector_wv_3451_arg11 = ret_val_sew_3452; + InvokeNode* call_sew_3468; + x86::Gp ret_val_sew_3468 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3468, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3467; + auto fp_vector_vector_wv_3467_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3467_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3467_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3467_arg10 = rm; + auto fp_vector_vector_wv_3467_arg11 = ret_val_sew_3468; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3451, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3452, 0, reinterpret_cast(this)); - setRet(call_sew_3452, 0, ret_val_sew_3452); - setArg(call_fp_vector_vector_wv_3451, 0, V); - setArg(call_fp_vector_vector_wv_3451, 1, 60); - setArg(call_fp_vector_vector_wv_3451, 2, 1); - setArg(call_fp_vector_vector_wv_3451, 3, fp_vector_vector_wv_3451_arg3); - setArg(call_fp_vector_vector_wv_3451, 4, fp_vector_vector_wv_3451_arg4); - setArg(call_fp_vector_vector_wv_3451, 5, fp_vector_vector_wv_3451_arg5); - setArg(call_fp_vector_vector_wv_3451, 6, vm); - setArg(call_fp_vector_vector_wv_3451, 7, vd); - setArg(call_fp_vector_vector_wv_3451, 8, vs2); - setArg(call_fp_vector_vector_wv_3451, 9, vs1); - setArg(call_fp_vector_vector_wv_3451, 10, fp_vector_vector_wv_3451_arg10); - setArg(call_fp_vector_vector_wv_3451, 11, fp_vector_vector_wv_3451_arg11); - InvokeNode* call_fget_flags_3453; - x86::Gp ret_val_fget_flags_3453 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3453, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3453; - setRet(call_fget_flags_3453, 0, ret_val_fget_flags_3453); + cc.invoke(&call_fp_vector_vector_wv_3467, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3468, 0, reinterpret_cast(this)); + setRet(call_sew_3468, 0, ret_val_sew_3468); + setArg(call_fp_vector_vector_wv_3467, 0, V); + setArg(call_fp_vector_vector_wv_3467, 1, 60); + setArg(call_fp_vector_vector_wv_3467, 2, 1); + setArg(call_fp_vector_vector_wv_3467, 3, fp_vector_vector_wv_3467_arg3); + setArg(call_fp_vector_vector_wv_3467, 4, fp_vector_vector_wv_3467_arg4); + setArg(call_fp_vector_vector_wv_3467, 5, fp_vector_vector_wv_3467_arg5); + setArg(call_fp_vector_vector_wv_3467, 6, vm); + setArg(call_fp_vector_vector_wv_3467, 7, vd); + setArg(call_fp_vector_vector_wv_3467, 8, vs2); + setArg(call_fp_vector_vector_wv_3467, 9, vs1); + setArg(call_fp_vector_vector_wv_3467, 10, fp_vector_vector_wv_3467_arg10); + setArg(call_fp_vector_vector_wv_3467, 11, fp_vector_vector_wv_3467_arg11); + InvokeNode* call_fget_flags_3469; + x86::Gp ret_val_fget_flags_3469 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3469, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3469; + setRet(call_fget_flags_3469, 0, ret_val_fget_flags_3469); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3454 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3454, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3454, 32, false) - , traits::vstart); + auto tmp3470 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3470, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3470, traits::vstart); } cc.bind(label_merge); } @@ -79291,54 +78811,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3455; - x86::Gp ret_val_get_sew_pow_3455 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3455, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3456 = get_reg(cc, 8, false); - mov(cc, tmp3456, 1); + InvokeNode* call_get_sew_pow_3471; + x86::Gp ret_val_get_sew_pow_3471 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3471, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3472 = get_reg(cc, 8, false); + mov(cc, tmp3472, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3456, (ret_val_get_sew_pow_3455))), 8, false), ~ 1); - setArg(call_get_sew_pow_3455, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3455, 0, ret_val_get_sew_pow_3455); - InvokeNode* call_get_lmul_pow_3457; - x86::Gp ret_val_get_lmul_pow_3457 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3457, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3457; - setArg(call_get_lmul_pow_3457, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3457, 0, ret_val_get_lmul_pow_3457); + (gen_operation(cc, shl, tmp3472, (ret_val_get_sew_pow_3471))), 8, false), ~ 1); + setArg(call_get_sew_pow_3471, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3471, 0, ret_val_get_sew_pow_3471); + InvokeNode* call_get_lmul_pow_3473; + x86::Gp ret_val_get_lmul_pow_3473 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3473, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3473; + setArg(call_get_lmul_pow_3473, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3473, 0, ret_val_get_lmul_pow_3473); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3458; - auto illegal_fp_variable_width_3458_arg2 = SEW; - auto illegal_fp_variable_width_3458_arg3 = rm; - auto illegal_fp_variable_width_3458_arg4 = SEW_widen; - auto illegal_fp_variable_width_3458_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3458 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3458, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3459; - auto valid_reg_overlap_3459_arg2 = LMUL_pow; - auto valid_reg_overlap_3459_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3459 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3459, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3458, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3459)); - setArg(call_illegal_fp_variable_width_3458, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3458, 1, vd); - setArg(call_illegal_fp_variable_width_3458, 2, vm); - setArg(call_illegal_fp_variable_width_3458, 3, illegal_fp_variable_width_3458_arg2); - setArg(call_illegal_fp_variable_width_3458, 4, illegal_fp_variable_width_3458_arg3); - setArg(call_illegal_fp_variable_width_3458, 5, illegal_fp_variable_width_3458_arg4); - setArg(call_illegal_fp_variable_width_3458, 6, illegal_fp_variable_width_3458_arg5); - setRet(call_illegal_fp_variable_width_3458, 0, ret_val_illegal_fp_variable_width_3458); - setArg(call_valid_reg_overlap_3459, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3459, 1, vs2); - setArg(call_valid_reg_overlap_3459, 2, vd); - setArg(call_valid_reg_overlap_3459, 3, valid_reg_overlap_3459_arg2); - setArg(call_valid_reg_overlap_3459, 4, valid_reg_overlap_3459_arg3); - setRet(call_valid_reg_overlap_3459, 0, ret_val_valid_reg_overlap_3459); + InvokeNode* call_illegal_fp_variable_width_3474; + auto illegal_fp_variable_width_3474_arg2 = SEW; + auto illegal_fp_variable_width_3474_arg3 = rm; + auto illegal_fp_variable_width_3474_arg4 = SEW_widen; + auto illegal_fp_variable_width_3474_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3474 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3474, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3475; + auto valid_reg_overlap_3475_arg2 = LMUL_pow; + auto valid_reg_overlap_3475_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3475 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3475, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3474, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3475)); + setArg(call_illegal_fp_variable_width_3474, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3474, 1, vd); + setArg(call_illegal_fp_variable_width_3474, 2, vm); + setArg(call_illegal_fp_variable_width_3474, 3, illegal_fp_variable_width_3474_arg2); + setArg(call_illegal_fp_variable_width_3474, 4, illegal_fp_variable_width_3474_arg3); + setArg(call_illegal_fp_variable_width_3474, 5, illegal_fp_variable_width_3474_arg4); + setArg(call_illegal_fp_variable_width_3474, 6, illegal_fp_variable_width_3474_arg5); + setRet(call_illegal_fp_variable_width_3474, 0, ret_val_illegal_fp_variable_width_3474); + setArg(call_valid_reg_overlap_3475, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3475, 1, vs2); + setArg(call_valid_reg_overlap_3475, 2, vd); + setArg(call_valid_reg_overlap_3475, 3, valid_reg_overlap_3475_arg2); + setArg(call_valid_reg_overlap_3475, 4, valid_reg_overlap_3475_arg3); + setRet(call_valid_reg_overlap_3475, 0, ret_val_valid_reg_overlap_3475); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79354,47 +78874,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3461; - x86::Gp ret_val_sew_3461 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3461, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3460; - auto fp_vector_imm_wv_3460_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3460_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3460_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3460_arg9 = gen_ext(cc, + InvokeNode* call_sew_3477; + x86::Gp ret_val_sew_3477 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3477, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3476; + auto fp_vector_imm_wv_3476_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3476_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3476_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3476_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_wv_3460_arg10 = rm; - auto fp_vector_imm_wv_3460_arg11 = ret_val_sew_3461; + auto fp_vector_imm_wv_3476_arg10 = rm; + auto fp_vector_imm_wv_3476_arg11 = ret_val_sew_3477; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3460, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3461, 0, reinterpret_cast(this)); - setRet(call_sew_3461, 0, ret_val_sew_3461); - setArg(call_fp_vector_imm_wv_3460, 0, V); - setArg(call_fp_vector_imm_wv_3460, 1, 61); - setArg(call_fp_vector_imm_wv_3460, 2, 5); - setArg(call_fp_vector_imm_wv_3460, 3, fp_vector_imm_wv_3460_arg3); - setArg(call_fp_vector_imm_wv_3460, 4, fp_vector_imm_wv_3460_arg4); - setArg(call_fp_vector_imm_wv_3460, 5, fp_vector_imm_wv_3460_arg5); - setArg(call_fp_vector_imm_wv_3460, 6, vm); - setArg(call_fp_vector_imm_wv_3460, 7, vd); - setArg(call_fp_vector_imm_wv_3460, 8, vs2); - setArg(call_fp_vector_imm_wv_3460, 9, fp_vector_imm_wv_3460_arg9); - setArg(call_fp_vector_imm_wv_3460, 10, fp_vector_imm_wv_3460_arg10); - setArg(call_fp_vector_imm_wv_3460, 11, fp_vector_imm_wv_3460_arg11); - InvokeNode* call_fget_flags_3462; - x86::Gp ret_val_fget_flags_3462 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3462, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3462; - setRet(call_fget_flags_3462, 0, ret_val_fget_flags_3462); + cc.invoke(&call_fp_vector_imm_wv_3476, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3477, 0, reinterpret_cast(this)); + setRet(call_sew_3477, 0, ret_val_sew_3477); + setArg(call_fp_vector_imm_wv_3476, 0, V); + setArg(call_fp_vector_imm_wv_3476, 1, 61); + setArg(call_fp_vector_imm_wv_3476, 2, 5); + setArg(call_fp_vector_imm_wv_3476, 3, fp_vector_imm_wv_3476_arg3); + setArg(call_fp_vector_imm_wv_3476, 4, fp_vector_imm_wv_3476_arg4); + setArg(call_fp_vector_imm_wv_3476, 5, fp_vector_imm_wv_3476_arg5); + setArg(call_fp_vector_imm_wv_3476, 6, vm); + setArg(call_fp_vector_imm_wv_3476, 7, vd); + setArg(call_fp_vector_imm_wv_3476, 8, vs2); + setArg(call_fp_vector_imm_wv_3476, 9, fp_vector_imm_wv_3476_arg9); + setArg(call_fp_vector_imm_wv_3476, 10, fp_vector_imm_wv_3476_arg10); + setArg(call_fp_vector_imm_wv_3476, 11, fp_vector_imm_wv_3476_arg11); + InvokeNode* call_fget_flags_3478; + x86::Gp ret_val_fget_flags_3478 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3478, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3478; + setRet(call_fget_flags_3478, 0, ret_val_fget_flags_3478); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3463 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3463, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3463, 32, false) - , traits::vstart); + auto tmp3479 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3479, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3479, traits::vstart); } cc.bind(label_merge); } @@ -79438,65 +78956,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3464; - x86::Gp ret_val_get_sew_pow_3464 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3464, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3465 = get_reg(cc, 8, false); - mov(cc, tmp3465, 1); + InvokeNode* call_get_sew_pow_3480; + x86::Gp ret_val_get_sew_pow_3480 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3480, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3481 = get_reg(cc, 8, false); + mov(cc, tmp3481, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3465, (ret_val_get_sew_pow_3464))), 8, false), ~ 1); - setArg(call_get_sew_pow_3464, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3464, 0, ret_val_get_sew_pow_3464); - InvokeNode* call_get_lmul_pow_3466; - x86::Gp ret_val_get_lmul_pow_3466 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3466, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3466; - setArg(call_get_lmul_pow_3466, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3466, 0, ret_val_get_lmul_pow_3466); + (gen_operation(cc, shl, tmp3481, (ret_val_get_sew_pow_3480))), 8, false), ~ 1); + setArg(call_get_sew_pow_3480, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3480, 0, ret_val_get_sew_pow_3480); + InvokeNode* call_get_lmul_pow_3482; + x86::Gp ret_val_get_lmul_pow_3482 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3482, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3482; + setArg(call_get_lmul_pow_3482, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3482, 0, ret_val_get_lmul_pow_3482); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3467; - auto illegal_fp_variable_width_3467_arg2 = SEW; - auto illegal_fp_variable_width_3467_arg3 = rm; - auto illegal_fp_variable_width_3467_arg4 = SEW_widen; - auto illegal_fp_variable_width_3467_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3467 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3467, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3468; - auto valid_reg_overlap_3468_arg2 = LMUL_pow; - auto valid_reg_overlap_3468_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3468 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3468, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3469; - auto valid_reg_overlap_3469_arg2 = LMUL_pow; - auto valid_reg_overlap_3469_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3469 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3469, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3467, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3468)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3469)); - setArg(call_illegal_fp_variable_width_3467, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3467, 1, vd); - setArg(call_illegal_fp_variable_width_3467, 2, vm); - setArg(call_illegal_fp_variable_width_3467, 3, illegal_fp_variable_width_3467_arg2); - setArg(call_illegal_fp_variable_width_3467, 4, illegal_fp_variable_width_3467_arg3); - setArg(call_illegal_fp_variable_width_3467, 5, illegal_fp_variable_width_3467_arg4); - setArg(call_illegal_fp_variable_width_3467, 6, illegal_fp_variable_width_3467_arg5); - setRet(call_illegal_fp_variable_width_3467, 0, ret_val_illegal_fp_variable_width_3467); - setArg(call_valid_reg_overlap_3468, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3468, 1, vs1); - setArg(call_valid_reg_overlap_3468, 2, vd); - setArg(call_valid_reg_overlap_3468, 3, valid_reg_overlap_3468_arg2); - setArg(call_valid_reg_overlap_3468, 4, valid_reg_overlap_3468_arg3); - setRet(call_valid_reg_overlap_3468, 0, ret_val_valid_reg_overlap_3468); - setArg(call_valid_reg_overlap_3469, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3469, 1, vs2); - setArg(call_valid_reg_overlap_3469, 2, vd); - setArg(call_valid_reg_overlap_3469, 3, valid_reg_overlap_3469_arg2); - setArg(call_valid_reg_overlap_3469, 4, valid_reg_overlap_3469_arg3); - setRet(call_valid_reg_overlap_3469, 0, ret_val_valid_reg_overlap_3469); + InvokeNode* call_illegal_fp_variable_width_3483; + auto illegal_fp_variable_width_3483_arg2 = SEW; + auto illegal_fp_variable_width_3483_arg3 = rm; + auto illegal_fp_variable_width_3483_arg4 = SEW_widen; + auto illegal_fp_variable_width_3483_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3483 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3483, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3484; + auto valid_reg_overlap_3484_arg2 = LMUL_pow; + auto valid_reg_overlap_3484_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3484 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3484, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3485; + auto valid_reg_overlap_3485_arg2 = LMUL_pow; + auto valid_reg_overlap_3485_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3485 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3485, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3483, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3484)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3485)); + setArg(call_illegal_fp_variable_width_3483, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3483, 1, vd); + setArg(call_illegal_fp_variable_width_3483, 2, vm); + setArg(call_illegal_fp_variable_width_3483, 3, illegal_fp_variable_width_3483_arg2); + setArg(call_illegal_fp_variable_width_3483, 4, illegal_fp_variable_width_3483_arg3); + setArg(call_illegal_fp_variable_width_3483, 5, illegal_fp_variable_width_3483_arg4); + setArg(call_illegal_fp_variable_width_3483, 6, illegal_fp_variable_width_3483_arg5); + setRet(call_illegal_fp_variable_width_3483, 0, ret_val_illegal_fp_variable_width_3483); + setArg(call_valid_reg_overlap_3484, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3484, 1, vs1); + setArg(call_valid_reg_overlap_3484, 2, vd); + setArg(call_valid_reg_overlap_3484, 3, valid_reg_overlap_3484_arg2); + setArg(call_valid_reg_overlap_3484, 4, valid_reg_overlap_3484_arg3); + setRet(call_valid_reg_overlap_3484, 0, ret_val_valid_reg_overlap_3484); + setArg(call_valid_reg_overlap_3485, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3485, 1, vs2); + setArg(call_valid_reg_overlap_3485, 2, vd); + setArg(call_valid_reg_overlap_3485, 3, valid_reg_overlap_3485_arg2); + setArg(call_valid_reg_overlap_3485, 4, valid_reg_overlap_3485_arg3); + setRet(call_valid_reg_overlap_3485, 0, ret_val_valid_reg_overlap_3485); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79512,45 +79030,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3471; - x86::Gp ret_val_sew_3471 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3471, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3470; - auto fp_vector_vector_wv_3470_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3470_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3470_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3470_arg10 = rm; - auto fp_vector_vector_wv_3470_arg11 = ret_val_sew_3471; + InvokeNode* call_sew_3487; + x86::Gp ret_val_sew_3487 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3487, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3486; + auto fp_vector_vector_wv_3486_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3486_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3486_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3486_arg10 = rm; + auto fp_vector_vector_wv_3486_arg11 = ret_val_sew_3487; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3470, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3471, 0, reinterpret_cast(this)); - setRet(call_sew_3471, 0, ret_val_sew_3471); - setArg(call_fp_vector_vector_wv_3470, 0, V); - setArg(call_fp_vector_vector_wv_3470, 1, 61); - setArg(call_fp_vector_vector_wv_3470, 2, 1); - setArg(call_fp_vector_vector_wv_3470, 3, fp_vector_vector_wv_3470_arg3); - setArg(call_fp_vector_vector_wv_3470, 4, fp_vector_vector_wv_3470_arg4); - setArg(call_fp_vector_vector_wv_3470, 5, fp_vector_vector_wv_3470_arg5); - setArg(call_fp_vector_vector_wv_3470, 6, vm); - setArg(call_fp_vector_vector_wv_3470, 7, vd); - setArg(call_fp_vector_vector_wv_3470, 8, vs2); - setArg(call_fp_vector_vector_wv_3470, 9, vs1); - setArg(call_fp_vector_vector_wv_3470, 10, fp_vector_vector_wv_3470_arg10); - setArg(call_fp_vector_vector_wv_3470, 11, fp_vector_vector_wv_3470_arg11); - InvokeNode* call_fget_flags_3472; - x86::Gp ret_val_fget_flags_3472 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3472, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3472; - setRet(call_fget_flags_3472, 0, ret_val_fget_flags_3472); + cc.invoke(&call_fp_vector_vector_wv_3486, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3487, 0, reinterpret_cast(this)); + setRet(call_sew_3487, 0, ret_val_sew_3487); + setArg(call_fp_vector_vector_wv_3486, 0, V); + setArg(call_fp_vector_vector_wv_3486, 1, 61); + setArg(call_fp_vector_vector_wv_3486, 2, 1); + setArg(call_fp_vector_vector_wv_3486, 3, fp_vector_vector_wv_3486_arg3); + setArg(call_fp_vector_vector_wv_3486, 4, fp_vector_vector_wv_3486_arg4); + setArg(call_fp_vector_vector_wv_3486, 5, fp_vector_vector_wv_3486_arg5); + setArg(call_fp_vector_vector_wv_3486, 6, vm); + setArg(call_fp_vector_vector_wv_3486, 7, vd); + setArg(call_fp_vector_vector_wv_3486, 8, vs2); + setArg(call_fp_vector_vector_wv_3486, 9, vs1); + setArg(call_fp_vector_vector_wv_3486, 10, fp_vector_vector_wv_3486_arg10); + setArg(call_fp_vector_vector_wv_3486, 11, fp_vector_vector_wv_3486_arg11); + InvokeNode* call_fget_flags_3488; + x86::Gp ret_val_fget_flags_3488 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3488, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3488; + setRet(call_fget_flags_3488, 0, ret_val_fget_flags_3488); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3473 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3473, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3473, 32, false) - , traits::vstart); + auto tmp3489 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3489, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3489, traits::vstart); } cc.bind(label_merge); } @@ -79594,54 +79110,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3474; - x86::Gp ret_val_get_sew_pow_3474 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3474, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3475 = get_reg(cc, 8, false); - mov(cc, tmp3475, 1); + InvokeNode* call_get_sew_pow_3490; + x86::Gp ret_val_get_sew_pow_3490 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3490, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3491 = get_reg(cc, 8, false); + mov(cc, tmp3491, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3475, (ret_val_get_sew_pow_3474))), 8, false), ~ 1); - setArg(call_get_sew_pow_3474, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3474, 0, ret_val_get_sew_pow_3474); - InvokeNode* call_get_lmul_pow_3476; - x86::Gp ret_val_get_lmul_pow_3476 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3476, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3476; - setArg(call_get_lmul_pow_3476, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3476, 0, ret_val_get_lmul_pow_3476); + (gen_operation(cc, shl, tmp3491, (ret_val_get_sew_pow_3490))), 8, false), ~ 1); + setArg(call_get_sew_pow_3490, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3490, 0, ret_val_get_sew_pow_3490); + InvokeNode* call_get_lmul_pow_3492; + x86::Gp ret_val_get_lmul_pow_3492 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3492, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3492; + setArg(call_get_lmul_pow_3492, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3492, 0, ret_val_get_lmul_pow_3492); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3477; - auto illegal_fp_variable_width_3477_arg2 = SEW; - auto illegal_fp_variable_width_3477_arg3 = rm; - auto illegal_fp_variable_width_3477_arg4 = SEW_widen; - auto illegal_fp_variable_width_3477_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3477 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3477, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3478; - auto valid_reg_overlap_3478_arg2 = LMUL_pow; - auto valid_reg_overlap_3478_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3478 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3478, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3477, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3478)); - setArg(call_illegal_fp_variable_width_3477, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3477, 1, vd); - setArg(call_illegal_fp_variable_width_3477, 2, vm); - setArg(call_illegal_fp_variable_width_3477, 3, illegal_fp_variable_width_3477_arg2); - setArg(call_illegal_fp_variable_width_3477, 4, illegal_fp_variable_width_3477_arg3); - setArg(call_illegal_fp_variable_width_3477, 5, illegal_fp_variable_width_3477_arg4); - setArg(call_illegal_fp_variable_width_3477, 6, illegal_fp_variable_width_3477_arg5); - setRet(call_illegal_fp_variable_width_3477, 0, ret_val_illegal_fp_variable_width_3477); - setArg(call_valid_reg_overlap_3478, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3478, 1, vs2); - setArg(call_valid_reg_overlap_3478, 2, vd); - setArg(call_valid_reg_overlap_3478, 3, valid_reg_overlap_3478_arg2); - setArg(call_valid_reg_overlap_3478, 4, valid_reg_overlap_3478_arg3); - setRet(call_valid_reg_overlap_3478, 0, ret_val_valid_reg_overlap_3478); + InvokeNode* call_illegal_fp_variable_width_3493; + auto illegal_fp_variable_width_3493_arg2 = SEW; + auto illegal_fp_variable_width_3493_arg3 = rm; + auto illegal_fp_variable_width_3493_arg4 = SEW_widen; + auto illegal_fp_variable_width_3493_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3493 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3493, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3494; + auto valid_reg_overlap_3494_arg2 = LMUL_pow; + auto valid_reg_overlap_3494_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3494 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3494, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3493, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3494)); + setArg(call_illegal_fp_variable_width_3493, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3493, 1, vd); + setArg(call_illegal_fp_variable_width_3493, 2, vm); + setArg(call_illegal_fp_variable_width_3493, 3, illegal_fp_variable_width_3493_arg2); + setArg(call_illegal_fp_variable_width_3493, 4, illegal_fp_variable_width_3493_arg3); + setArg(call_illegal_fp_variable_width_3493, 5, illegal_fp_variable_width_3493_arg4); + setArg(call_illegal_fp_variable_width_3493, 6, illegal_fp_variable_width_3493_arg5); + setRet(call_illegal_fp_variable_width_3493, 0, ret_val_illegal_fp_variable_width_3493); + setArg(call_valid_reg_overlap_3494, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3494, 1, vs2); + setArg(call_valid_reg_overlap_3494, 2, vd); + setArg(call_valid_reg_overlap_3494, 3, valid_reg_overlap_3494_arg2); + setArg(call_valid_reg_overlap_3494, 4, valid_reg_overlap_3494_arg3); + setRet(call_valid_reg_overlap_3494, 0, ret_val_valid_reg_overlap_3494); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79657,47 +79173,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3480; - x86::Gp ret_val_sew_3480 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3480, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3479; - auto fp_vector_imm_wv_3479_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3479_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3479_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3479_arg9 = gen_ext(cc, + InvokeNode* call_sew_3496; + x86::Gp ret_val_sew_3496 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3496, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3495; + auto fp_vector_imm_wv_3495_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3495_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3495_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3495_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_wv_3479_arg10 = rm; - auto fp_vector_imm_wv_3479_arg11 = ret_val_sew_3480; + auto fp_vector_imm_wv_3495_arg10 = rm; + auto fp_vector_imm_wv_3495_arg11 = ret_val_sew_3496; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3479, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3480, 0, reinterpret_cast(this)); - setRet(call_sew_3480, 0, ret_val_sew_3480); - setArg(call_fp_vector_imm_wv_3479, 0, V); - setArg(call_fp_vector_imm_wv_3479, 1, 62); - setArg(call_fp_vector_imm_wv_3479, 2, 5); - setArg(call_fp_vector_imm_wv_3479, 3, fp_vector_imm_wv_3479_arg3); - setArg(call_fp_vector_imm_wv_3479, 4, fp_vector_imm_wv_3479_arg4); - setArg(call_fp_vector_imm_wv_3479, 5, fp_vector_imm_wv_3479_arg5); - setArg(call_fp_vector_imm_wv_3479, 6, vm); - setArg(call_fp_vector_imm_wv_3479, 7, vd); - setArg(call_fp_vector_imm_wv_3479, 8, vs2); - setArg(call_fp_vector_imm_wv_3479, 9, fp_vector_imm_wv_3479_arg9); - setArg(call_fp_vector_imm_wv_3479, 10, fp_vector_imm_wv_3479_arg10); - setArg(call_fp_vector_imm_wv_3479, 11, fp_vector_imm_wv_3479_arg11); - InvokeNode* call_fget_flags_3481; - x86::Gp ret_val_fget_flags_3481 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3481, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3481; - setRet(call_fget_flags_3481, 0, ret_val_fget_flags_3481); + cc.invoke(&call_fp_vector_imm_wv_3495, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3496, 0, reinterpret_cast(this)); + setRet(call_sew_3496, 0, ret_val_sew_3496); + setArg(call_fp_vector_imm_wv_3495, 0, V); + setArg(call_fp_vector_imm_wv_3495, 1, 62); + setArg(call_fp_vector_imm_wv_3495, 2, 5); + setArg(call_fp_vector_imm_wv_3495, 3, fp_vector_imm_wv_3495_arg3); + setArg(call_fp_vector_imm_wv_3495, 4, fp_vector_imm_wv_3495_arg4); + setArg(call_fp_vector_imm_wv_3495, 5, fp_vector_imm_wv_3495_arg5); + setArg(call_fp_vector_imm_wv_3495, 6, vm); + setArg(call_fp_vector_imm_wv_3495, 7, vd); + setArg(call_fp_vector_imm_wv_3495, 8, vs2); + setArg(call_fp_vector_imm_wv_3495, 9, fp_vector_imm_wv_3495_arg9); + setArg(call_fp_vector_imm_wv_3495, 10, fp_vector_imm_wv_3495_arg10); + setArg(call_fp_vector_imm_wv_3495, 11, fp_vector_imm_wv_3495_arg11); + InvokeNode* call_fget_flags_3497; + x86::Gp ret_val_fget_flags_3497 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3497, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3497; + setRet(call_fget_flags_3497, 0, ret_val_fget_flags_3497); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3482 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3482, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3482, 32, false) - , traits::vstart); + auto tmp3498 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3498, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3498, traits::vstart); } cc.bind(label_merge); } @@ -79741,65 +79255,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3483; - x86::Gp ret_val_get_sew_pow_3483 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3483, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3484 = get_reg(cc, 8, false); - mov(cc, tmp3484, 1); + InvokeNode* call_get_sew_pow_3499; + x86::Gp ret_val_get_sew_pow_3499 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3499, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3500 = get_reg(cc, 8, false); + mov(cc, tmp3500, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3484, (ret_val_get_sew_pow_3483))), 8, false), ~ 1); - setArg(call_get_sew_pow_3483, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3483, 0, ret_val_get_sew_pow_3483); - InvokeNode* call_get_lmul_pow_3485; - x86::Gp ret_val_get_lmul_pow_3485 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3485, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3485; - setArg(call_get_lmul_pow_3485, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3485, 0, ret_val_get_lmul_pow_3485); + (gen_operation(cc, shl, tmp3500, (ret_val_get_sew_pow_3499))), 8, false), ~ 1); + setArg(call_get_sew_pow_3499, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3499, 0, ret_val_get_sew_pow_3499); + InvokeNode* call_get_lmul_pow_3501; + x86::Gp ret_val_get_lmul_pow_3501 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3501, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3501; + setArg(call_get_lmul_pow_3501, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3501, 0, ret_val_get_lmul_pow_3501); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3486; - auto illegal_fp_variable_width_3486_arg2 = SEW; - auto illegal_fp_variable_width_3486_arg3 = rm; - auto illegal_fp_variable_width_3486_arg4 = SEW_widen; - auto illegal_fp_variable_width_3486_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3486 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3486, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3487; - auto valid_reg_overlap_3487_arg2 = LMUL_pow; - auto valid_reg_overlap_3487_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3487 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3487, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3488; - auto valid_reg_overlap_3488_arg2 = LMUL_pow; - auto valid_reg_overlap_3488_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3488 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3488, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3486, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3487)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3488)); - setArg(call_illegal_fp_variable_width_3486, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3486, 1, vd); - setArg(call_illegal_fp_variable_width_3486, 2, vm); - setArg(call_illegal_fp_variable_width_3486, 3, illegal_fp_variable_width_3486_arg2); - setArg(call_illegal_fp_variable_width_3486, 4, illegal_fp_variable_width_3486_arg3); - setArg(call_illegal_fp_variable_width_3486, 5, illegal_fp_variable_width_3486_arg4); - setArg(call_illegal_fp_variable_width_3486, 6, illegal_fp_variable_width_3486_arg5); - setRet(call_illegal_fp_variable_width_3486, 0, ret_val_illegal_fp_variable_width_3486); - setArg(call_valid_reg_overlap_3487, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3487, 1, vs1); - setArg(call_valid_reg_overlap_3487, 2, vd); - setArg(call_valid_reg_overlap_3487, 3, valid_reg_overlap_3487_arg2); - setArg(call_valid_reg_overlap_3487, 4, valid_reg_overlap_3487_arg3); - setRet(call_valid_reg_overlap_3487, 0, ret_val_valid_reg_overlap_3487); - setArg(call_valid_reg_overlap_3488, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3488, 1, vs2); - setArg(call_valid_reg_overlap_3488, 2, vd); - setArg(call_valid_reg_overlap_3488, 3, valid_reg_overlap_3488_arg2); - setArg(call_valid_reg_overlap_3488, 4, valid_reg_overlap_3488_arg3); - setRet(call_valid_reg_overlap_3488, 0, ret_val_valid_reg_overlap_3488); + InvokeNode* call_illegal_fp_variable_width_3502; + auto illegal_fp_variable_width_3502_arg2 = SEW; + auto illegal_fp_variable_width_3502_arg3 = rm; + auto illegal_fp_variable_width_3502_arg4 = SEW_widen; + auto illegal_fp_variable_width_3502_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3502 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3502, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3503; + auto valid_reg_overlap_3503_arg2 = LMUL_pow; + auto valid_reg_overlap_3503_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3503 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3503, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3504; + auto valid_reg_overlap_3504_arg2 = LMUL_pow; + auto valid_reg_overlap_3504_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3504 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3504, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3502, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3503)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3504)); + setArg(call_illegal_fp_variable_width_3502, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3502, 1, vd); + setArg(call_illegal_fp_variable_width_3502, 2, vm); + setArg(call_illegal_fp_variable_width_3502, 3, illegal_fp_variable_width_3502_arg2); + setArg(call_illegal_fp_variable_width_3502, 4, illegal_fp_variable_width_3502_arg3); + setArg(call_illegal_fp_variable_width_3502, 5, illegal_fp_variable_width_3502_arg4); + setArg(call_illegal_fp_variable_width_3502, 6, illegal_fp_variable_width_3502_arg5); + setRet(call_illegal_fp_variable_width_3502, 0, ret_val_illegal_fp_variable_width_3502); + setArg(call_valid_reg_overlap_3503, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3503, 1, vs1); + setArg(call_valid_reg_overlap_3503, 2, vd); + setArg(call_valid_reg_overlap_3503, 3, valid_reg_overlap_3503_arg2); + setArg(call_valid_reg_overlap_3503, 4, valid_reg_overlap_3503_arg3); + setRet(call_valid_reg_overlap_3503, 0, ret_val_valid_reg_overlap_3503); + setArg(call_valid_reg_overlap_3504, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3504, 1, vs2); + setArg(call_valid_reg_overlap_3504, 2, vd); + setArg(call_valid_reg_overlap_3504, 3, valid_reg_overlap_3504_arg2); + setArg(call_valid_reg_overlap_3504, 4, valid_reg_overlap_3504_arg3); + setRet(call_valid_reg_overlap_3504, 0, ret_val_valid_reg_overlap_3504); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79815,45 +79329,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3490; - x86::Gp ret_val_sew_3490 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3490, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3489; - auto fp_vector_vector_wv_3489_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3489_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3489_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3489_arg10 = rm; - auto fp_vector_vector_wv_3489_arg11 = ret_val_sew_3490; + InvokeNode* call_sew_3506; + x86::Gp ret_val_sew_3506 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3506, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3505; + auto fp_vector_vector_wv_3505_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3505_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3505_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3505_arg10 = rm; + auto fp_vector_vector_wv_3505_arg11 = ret_val_sew_3506; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3489, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3490, 0, reinterpret_cast(this)); - setRet(call_sew_3490, 0, ret_val_sew_3490); - setArg(call_fp_vector_vector_wv_3489, 0, V); - setArg(call_fp_vector_vector_wv_3489, 1, 62); - setArg(call_fp_vector_vector_wv_3489, 2, 1); - setArg(call_fp_vector_vector_wv_3489, 3, fp_vector_vector_wv_3489_arg3); - setArg(call_fp_vector_vector_wv_3489, 4, fp_vector_vector_wv_3489_arg4); - setArg(call_fp_vector_vector_wv_3489, 5, fp_vector_vector_wv_3489_arg5); - setArg(call_fp_vector_vector_wv_3489, 6, vm); - setArg(call_fp_vector_vector_wv_3489, 7, vd); - setArg(call_fp_vector_vector_wv_3489, 8, vs2); - setArg(call_fp_vector_vector_wv_3489, 9, vs1); - setArg(call_fp_vector_vector_wv_3489, 10, fp_vector_vector_wv_3489_arg10); - setArg(call_fp_vector_vector_wv_3489, 11, fp_vector_vector_wv_3489_arg11); - InvokeNode* call_fget_flags_3491; - x86::Gp ret_val_fget_flags_3491 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3491, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3491; - setRet(call_fget_flags_3491, 0, ret_val_fget_flags_3491); + cc.invoke(&call_fp_vector_vector_wv_3505, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3506, 0, reinterpret_cast(this)); + setRet(call_sew_3506, 0, ret_val_sew_3506); + setArg(call_fp_vector_vector_wv_3505, 0, V); + setArg(call_fp_vector_vector_wv_3505, 1, 62); + setArg(call_fp_vector_vector_wv_3505, 2, 1); + setArg(call_fp_vector_vector_wv_3505, 3, fp_vector_vector_wv_3505_arg3); + setArg(call_fp_vector_vector_wv_3505, 4, fp_vector_vector_wv_3505_arg4); + setArg(call_fp_vector_vector_wv_3505, 5, fp_vector_vector_wv_3505_arg5); + setArg(call_fp_vector_vector_wv_3505, 6, vm); + setArg(call_fp_vector_vector_wv_3505, 7, vd); + setArg(call_fp_vector_vector_wv_3505, 8, vs2); + setArg(call_fp_vector_vector_wv_3505, 9, vs1); + setArg(call_fp_vector_vector_wv_3505, 10, fp_vector_vector_wv_3505_arg10); + setArg(call_fp_vector_vector_wv_3505, 11, fp_vector_vector_wv_3505_arg11); + InvokeNode* call_fget_flags_3507; + x86::Gp ret_val_fget_flags_3507 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3507, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3507; + setRet(call_fget_flags_3507, 0, ret_val_fget_flags_3507); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3492 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3492, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3492, 32, false) - , traits::vstart); + auto tmp3508 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3508, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3508, traits::vstart); } cc.bind(label_merge); } @@ -79897,54 +79409,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3493; - x86::Gp ret_val_get_sew_pow_3493 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3493, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3494 = get_reg(cc, 8, false); - mov(cc, tmp3494, 1); + InvokeNode* call_get_sew_pow_3509; + x86::Gp ret_val_get_sew_pow_3509 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3509, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3510 = get_reg(cc, 8, false); + mov(cc, tmp3510, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3494, (ret_val_get_sew_pow_3493))), 8, false), ~ 1); - setArg(call_get_sew_pow_3493, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3493, 0, ret_val_get_sew_pow_3493); - InvokeNode* call_get_lmul_pow_3495; - x86::Gp ret_val_get_lmul_pow_3495 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3495, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3495; - setArg(call_get_lmul_pow_3495, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3495, 0, ret_val_get_lmul_pow_3495); + (gen_operation(cc, shl, tmp3510, (ret_val_get_sew_pow_3509))), 8, false), ~ 1); + setArg(call_get_sew_pow_3509, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3509, 0, ret_val_get_sew_pow_3509); + InvokeNode* call_get_lmul_pow_3511; + x86::Gp ret_val_get_lmul_pow_3511 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3511, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3511; + setArg(call_get_lmul_pow_3511, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3511, 0, ret_val_get_lmul_pow_3511); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3496; - auto illegal_fp_variable_width_3496_arg2 = SEW; - auto illegal_fp_variable_width_3496_arg3 = rm; - auto illegal_fp_variable_width_3496_arg4 = SEW_widen; - auto illegal_fp_variable_width_3496_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3496 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3496, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3497; - auto valid_reg_overlap_3497_arg2 = LMUL_pow; - auto valid_reg_overlap_3497_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3497 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3497, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3496, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3497)); - setArg(call_illegal_fp_variable_width_3496, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3496, 1, vd); - setArg(call_illegal_fp_variable_width_3496, 2, vm); - setArg(call_illegal_fp_variable_width_3496, 3, illegal_fp_variable_width_3496_arg2); - setArg(call_illegal_fp_variable_width_3496, 4, illegal_fp_variable_width_3496_arg3); - setArg(call_illegal_fp_variable_width_3496, 5, illegal_fp_variable_width_3496_arg4); - setArg(call_illegal_fp_variable_width_3496, 6, illegal_fp_variable_width_3496_arg5); - setRet(call_illegal_fp_variable_width_3496, 0, ret_val_illegal_fp_variable_width_3496); - setArg(call_valid_reg_overlap_3497, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3497, 1, vs2); - setArg(call_valid_reg_overlap_3497, 2, vd); - setArg(call_valid_reg_overlap_3497, 3, valid_reg_overlap_3497_arg2); - setArg(call_valid_reg_overlap_3497, 4, valid_reg_overlap_3497_arg3); - setRet(call_valid_reg_overlap_3497, 0, ret_val_valid_reg_overlap_3497); + InvokeNode* call_illegal_fp_variable_width_3512; + auto illegal_fp_variable_width_3512_arg2 = SEW; + auto illegal_fp_variable_width_3512_arg3 = rm; + auto illegal_fp_variable_width_3512_arg4 = SEW_widen; + auto illegal_fp_variable_width_3512_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3512 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3512, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3513; + auto valid_reg_overlap_3513_arg2 = LMUL_pow; + auto valid_reg_overlap_3513_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3513 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3513, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3512, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3513)); + setArg(call_illegal_fp_variable_width_3512, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3512, 1, vd); + setArg(call_illegal_fp_variable_width_3512, 2, vm); + setArg(call_illegal_fp_variable_width_3512, 3, illegal_fp_variable_width_3512_arg2); + setArg(call_illegal_fp_variable_width_3512, 4, illegal_fp_variable_width_3512_arg3); + setArg(call_illegal_fp_variable_width_3512, 5, illegal_fp_variable_width_3512_arg4); + setArg(call_illegal_fp_variable_width_3512, 6, illegal_fp_variable_width_3512_arg5); + setRet(call_illegal_fp_variable_width_3512, 0, ret_val_illegal_fp_variable_width_3512); + setArg(call_valid_reg_overlap_3513, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3513, 1, vs2); + setArg(call_valid_reg_overlap_3513, 2, vd); + setArg(call_valid_reg_overlap_3513, 3, valid_reg_overlap_3513_arg2); + setArg(call_valid_reg_overlap_3513, 4, valid_reg_overlap_3513_arg3); + setRet(call_valid_reg_overlap_3513, 0, ret_val_valid_reg_overlap_3513); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79960,47 +79472,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3499; - x86::Gp ret_val_sew_3499 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3499, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3498; - auto fp_vector_imm_wv_3498_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3498_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3498_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3498_arg9 = gen_ext(cc, + InvokeNode* call_sew_3515; + x86::Gp ret_val_sew_3515 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3515, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3514; + auto fp_vector_imm_wv_3514_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3514_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3514_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3514_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_wv_3498_arg10 = rm; - auto fp_vector_imm_wv_3498_arg11 = ret_val_sew_3499; + auto fp_vector_imm_wv_3514_arg10 = rm; + auto fp_vector_imm_wv_3514_arg11 = ret_val_sew_3515; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3498, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3499, 0, reinterpret_cast(this)); - setRet(call_sew_3499, 0, ret_val_sew_3499); - setArg(call_fp_vector_imm_wv_3498, 0, V); - setArg(call_fp_vector_imm_wv_3498, 1, 63); - setArg(call_fp_vector_imm_wv_3498, 2, 5); - setArg(call_fp_vector_imm_wv_3498, 3, fp_vector_imm_wv_3498_arg3); - setArg(call_fp_vector_imm_wv_3498, 4, fp_vector_imm_wv_3498_arg4); - setArg(call_fp_vector_imm_wv_3498, 5, fp_vector_imm_wv_3498_arg5); - setArg(call_fp_vector_imm_wv_3498, 6, vm); - setArg(call_fp_vector_imm_wv_3498, 7, vd); - setArg(call_fp_vector_imm_wv_3498, 8, vs2); - setArg(call_fp_vector_imm_wv_3498, 9, fp_vector_imm_wv_3498_arg9); - setArg(call_fp_vector_imm_wv_3498, 10, fp_vector_imm_wv_3498_arg10); - setArg(call_fp_vector_imm_wv_3498, 11, fp_vector_imm_wv_3498_arg11); - InvokeNode* call_fget_flags_3500; - x86::Gp ret_val_fget_flags_3500 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3500, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3500; - setRet(call_fget_flags_3500, 0, ret_val_fget_flags_3500); + cc.invoke(&call_fp_vector_imm_wv_3514, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3515, 0, reinterpret_cast(this)); + setRet(call_sew_3515, 0, ret_val_sew_3515); + setArg(call_fp_vector_imm_wv_3514, 0, V); + setArg(call_fp_vector_imm_wv_3514, 1, 63); + setArg(call_fp_vector_imm_wv_3514, 2, 5); + setArg(call_fp_vector_imm_wv_3514, 3, fp_vector_imm_wv_3514_arg3); + setArg(call_fp_vector_imm_wv_3514, 4, fp_vector_imm_wv_3514_arg4); + setArg(call_fp_vector_imm_wv_3514, 5, fp_vector_imm_wv_3514_arg5); + setArg(call_fp_vector_imm_wv_3514, 6, vm); + setArg(call_fp_vector_imm_wv_3514, 7, vd); + setArg(call_fp_vector_imm_wv_3514, 8, vs2); + setArg(call_fp_vector_imm_wv_3514, 9, fp_vector_imm_wv_3514_arg9); + setArg(call_fp_vector_imm_wv_3514, 10, fp_vector_imm_wv_3514_arg10); + setArg(call_fp_vector_imm_wv_3514, 11, fp_vector_imm_wv_3514_arg11); + InvokeNode* call_fget_flags_3516; + x86::Gp ret_val_fget_flags_3516 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3516, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3516; + setRet(call_fget_flags_3516, 0, ret_val_fget_flags_3516); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3501 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3501, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3501, 32, false) - , traits::vstart); + auto tmp3517 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3517, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3517, traits::vstart); } cc.bind(label_merge); } @@ -80044,65 +79554,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3502; - x86::Gp ret_val_get_sew_pow_3502 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3502, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3503 = get_reg(cc, 8, false); - mov(cc, tmp3503, 1); + InvokeNode* call_get_sew_pow_3518; + x86::Gp ret_val_get_sew_pow_3518 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3518, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3519 = get_reg(cc, 8, false); + mov(cc, tmp3519, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3503, (ret_val_get_sew_pow_3502))), 8, false), ~ 1); - setArg(call_get_sew_pow_3502, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3502, 0, ret_val_get_sew_pow_3502); - InvokeNode* call_get_lmul_pow_3504; - x86::Gp ret_val_get_lmul_pow_3504 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3504, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3504; - setArg(call_get_lmul_pow_3504, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3504, 0, ret_val_get_lmul_pow_3504); + (gen_operation(cc, shl, tmp3519, (ret_val_get_sew_pow_3518))), 8, false), ~ 1); + setArg(call_get_sew_pow_3518, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3518, 0, ret_val_get_sew_pow_3518); + InvokeNode* call_get_lmul_pow_3520; + x86::Gp ret_val_get_lmul_pow_3520 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3520, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3520; + setArg(call_get_lmul_pow_3520, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3520, 0, ret_val_get_lmul_pow_3520); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3505; - auto illegal_fp_variable_width_3505_arg2 = SEW; - auto illegal_fp_variable_width_3505_arg3 = rm; - auto illegal_fp_variable_width_3505_arg4 = SEW_widen; - auto illegal_fp_variable_width_3505_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3505 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3505, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3506; - auto valid_reg_overlap_3506_arg2 = LMUL_pow; - auto valid_reg_overlap_3506_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3506 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3506, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3507; - auto valid_reg_overlap_3507_arg2 = LMUL_pow; - auto valid_reg_overlap_3507_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3507 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3507, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3505, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3506)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3507)); - setArg(call_illegal_fp_variable_width_3505, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3505, 1, vd); - setArg(call_illegal_fp_variable_width_3505, 2, vm); - setArg(call_illegal_fp_variable_width_3505, 3, illegal_fp_variable_width_3505_arg2); - setArg(call_illegal_fp_variable_width_3505, 4, illegal_fp_variable_width_3505_arg3); - setArg(call_illegal_fp_variable_width_3505, 5, illegal_fp_variable_width_3505_arg4); - setArg(call_illegal_fp_variable_width_3505, 6, illegal_fp_variable_width_3505_arg5); - setRet(call_illegal_fp_variable_width_3505, 0, ret_val_illegal_fp_variable_width_3505); - setArg(call_valid_reg_overlap_3506, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3506, 1, vs1); - setArg(call_valid_reg_overlap_3506, 2, vd); - setArg(call_valid_reg_overlap_3506, 3, valid_reg_overlap_3506_arg2); - setArg(call_valid_reg_overlap_3506, 4, valid_reg_overlap_3506_arg3); - setRet(call_valid_reg_overlap_3506, 0, ret_val_valid_reg_overlap_3506); - setArg(call_valid_reg_overlap_3507, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3507, 1, vs2); - setArg(call_valid_reg_overlap_3507, 2, vd); - setArg(call_valid_reg_overlap_3507, 3, valid_reg_overlap_3507_arg2); - setArg(call_valid_reg_overlap_3507, 4, valid_reg_overlap_3507_arg3); - setRet(call_valid_reg_overlap_3507, 0, ret_val_valid_reg_overlap_3507); + InvokeNode* call_illegal_fp_variable_width_3521; + auto illegal_fp_variable_width_3521_arg2 = SEW; + auto illegal_fp_variable_width_3521_arg3 = rm; + auto illegal_fp_variable_width_3521_arg4 = SEW_widen; + auto illegal_fp_variable_width_3521_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3521 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3521, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3522; + auto valid_reg_overlap_3522_arg2 = LMUL_pow; + auto valid_reg_overlap_3522_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3522 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3522, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3523; + auto valid_reg_overlap_3523_arg2 = LMUL_pow; + auto valid_reg_overlap_3523_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3523 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3523, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3521, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3522)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3523)); + setArg(call_illegal_fp_variable_width_3521, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3521, 1, vd); + setArg(call_illegal_fp_variable_width_3521, 2, vm); + setArg(call_illegal_fp_variable_width_3521, 3, illegal_fp_variable_width_3521_arg2); + setArg(call_illegal_fp_variable_width_3521, 4, illegal_fp_variable_width_3521_arg3); + setArg(call_illegal_fp_variable_width_3521, 5, illegal_fp_variable_width_3521_arg4); + setArg(call_illegal_fp_variable_width_3521, 6, illegal_fp_variable_width_3521_arg5); + setRet(call_illegal_fp_variable_width_3521, 0, ret_val_illegal_fp_variable_width_3521); + setArg(call_valid_reg_overlap_3522, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3522, 1, vs1); + setArg(call_valid_reg_overlap_3522, 2, vd); + setArg(call_valid_reg_overlap_3522, 3, valid_reg_overlap_3522_arg2); + setArg(call_valid_reg_overlap_3522, 4, valid_reg_overlap_3522_arg3); + setRet(call_valid_reg_overlap_3522, 0, ret_val_valid_reg_overlap_3522); + setArg(call_valid_reg_overlap_3523, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3523, 1, vs2); + setArg(call_valid_reg_overlap_3523, 2, vd); + setArg(call_valid_reg_overlap_3523, 3, valid_reg_overlap_3523_arg2); + setArg(call_valid_reg_overlap_3523, 4, valid_reg_overlap_3523_arg3); + setRet(call_valid_reg_overlap_3523, 0, ret_val_valid_reg_overlap_3523); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80118,45 +79628,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3509; - x86::Gp ret_val_sew_3509 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3509, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3508; - auto fp_vector_vector_wv_3508_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3508_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3508_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3508_arg10 = rm; - auto fp_vector_vector_wv_3508_arg11 = ret_val_sew_3509; + InvokeNode* call_sew_3525; + x86::Gp ret_val_sew_3525 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3525, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3524; + auto fp_vector_vector_wv_3524_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3524_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3524_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3524_arg10 = rm; + auto fp_vector_vector_wv_3524_arg11 = ret_val_sew_3525; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3508, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3509, 0, reinterpret_cast(this)); - setRet(call_sew_3509, 0, ret_val_sew_3509); - setArg(call_fp_vector_vector_wv_3508, 0, V); - setArg(call_fp_vector_vector_wv_3508, 1, 63); - setArg(call_fp_vector_vector_wv_3508, 2, 1); - setArg(call_fp_vector_vector_wv_3508, 3, fp_vector_vector_wv_3508_arg3); - setArg(call_fp_vector_vector_wv_3508, 4, fp_vector_vector_wv_3508_arg4); - setArg(call_fp_vector_vector_wv_3508, 5, fp_vector_vector_wv_3508_arg5); - setArg(call_fp_vector_vector_wv_3508, 6, vm); - setArg(call_fp_vector_vector_wv_3508, 7, vd); - setArg(call_fp_vector_vector_wv_3508, 8, vs2); - setArg(call_fp_vector_vector_wv_3508, 9, vs1); - setArg(call_fp_vector_vector_wv_3508, 10, fp_vector_vector_wv_3508_arg10); - setArg(call_fp_vector_vector_wv_3508, 11, fp_vector_vector_wv_3508_arg11); - InvokeNode* call_fget_flags_3510; - x86::Gp ret_val_fget_flags_3510 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3510, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3510; - setRet(call_fget_flags_3510, 0, ret_val_fget_flags_3510); + cc.invoke(&call_fp_vector_vector_wv_3524, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3525, 0, reinterpret_cast(this)); + setRet(call_sew_3525, 0, ret_val_sew_3525); + setArg(call_fp_vector_vector_wv_3524, 0, V); + setArg(call_fp_vector_vector_wv_3524, 1, 63); + setArg(call_fp_vector_vector_wv_3524, 2, 1); + setArg(call_fp_vector_vector_wv_3524, 3, fp_vector_vector_wv_3524_arg3); + setArg(call_fp_vector_vector_wv_3524, 4, fp_vector_vector_wv_3524_arg4); + setArg(call_fp_vector_vector_wv_3524, 5, fp_vector_vector_wv_3524_arg5); + setArg(call_fp_vector_vector_wv_3524, 6, vm); + setArg(call_fp_vector_vector_wv_3524, 7, vd); + setArg(call_fp_vector_vector_wv_3524, 8, vs2); + setArg(call_fp_vector_vector_wv_3524, 9, vs1); + setArg(call_fp_vector_vector_wv_3524, 10, fp_vector_vector_wv_3524_arg10); + setArg(call_fp_vector_vector_wv_3524, 11, fp_vector_vector_wv_3524_arg11); + InvokeNode* call_fget_flags_3526; + x86::Gp ret_val_fget_flags_3526 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3526, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3526; + setRet(call_fget_flags_3526, 0, ret_val_fget_flags_3526); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3511 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3511, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3511, 32, false) - , traits::vstart); + auto tmp3527 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3527, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3527, traits::vstart); } cc.bind(label_merge); } @@ -80199,30 +79707,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3512; - x86::Gp ret_val_get_sew_pow_3512 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3512, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3513 = get_reg(cc, 8, false); - mov(cc, tmp3513, 1); + InvokeNode* call_get_sew_pow_3528; + x86::Gp ret_val_get_sew_pow_3528 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3528, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3529 = get_reg(cc, 8, false); + mov(cc, tmp3529, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3513, (ret_val_get_sew_pow_3512))), 8, false), ~ 1); - setArg(call_get_sew_pow_3512, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3512, 0, ret_val_get_sew_pow_3512); + (gen_operation(cc, shl, tmp3529, (ret_val_get_sew_pow_3528))), 8, false), ~ 1); + setArg(call_get_sew_pow_3528, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3528, 0, ret_val_get_sew_pow_3528); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3514; - auto illegal_fp_normal_3514_arg2 = SEW; - auto illegal_fp_normal_3514_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3514 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3514, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3514; - setArg(call_illegal_fp_normal_3514, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3514, 1, vd); - setArg(call_illegal_fp_normal_3514, 2, vm); - setArg(call_illegal_fp_normal_3514, 3, illegal_fp_normal_3514_arg2); - setArg(call_illegal_fp_normal_3514, 4, illegal_fp_normal_3514_arg3); - setRet(call_illegal_fp_normal_3514, 0, ret_val_illegal_fp_normal_3514); + InvokeNode* call_illegal_fp_normal_3530; + auto illegal_fp_normal_3530_arg2 = SEW; + auto illegal_fp_normal_3530_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3530 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3530, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3530; + setArg(call_illegal_fp_normal_3530, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3530, 1, vd); + setArg(call_illegal_fp_normal_3530, 2, vm); + setArg(call_illegal_fp_normal_3530, 3, illegal_fp_normal_3530_arg2); + setArg(call_illegal_fp_normal_3530, 4, illegal_fp_normal_3530_arg3); + setRet(call_illegal_fp_normal_3530, 0, ret_val_illegal_fp_normal_3530); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80238,44 +79746,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3516; - x86::Gp ret_val_sew_3516 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3516, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3515; - auto fp_vector_unary_op_3515_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3515_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3515_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3515_arg9 = rm; - auto fp_vector_unary_op_3515_arg10 = ret_val_sew_3516; + InvokeNode* call_sew_3532; + x86::Gp ret_val_sew_3532 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3532, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3531; + auto fp_vector_unary_op_3531_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3531_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3531_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3531_arg9 = rm; + auto fp_vector_unary_op_3531_arg10 = ret_val_sew_3532; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3515, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3516, 0, reinterpret_cast(this)); - setRet(call_sew_3516, 0, ret_val_sew_3516); - setArg(call_fp_vector_unary_op_3515, 0, V); - setArg(call_fp_vector_unary_op_3515, 1, 19); - setArg(call_fp_vector_unary_op_3515, 2, 0); - setArg(call_fp_vector_unary_op_3515, 3, fp_vector_unary_op_3515_arg3); - setArg(call_fp_vector_unary_op_3515, 4, fp_vector_unary_op_3515_arg4); - setArg(call_fp_vector_unary_op_3515, 5, fp_vector_unary_op_3515_arg5); - setArg(call_fp_vector_unary_op_3515, 6, vm); - setArg(call_fp_vector_unary_op_3515, 7, vd); - setArg(call_fp_vector_unary_op_3515, 8, vs2); - setArg(call_fp_vector_unary_op_3515, 9, fp_vector_unary_op_3515_arg9); - setArg(call_fp_vector_unary_op_3515, 10, fp_vector_unary_op_3515_arg10); - InvokeNode* call_fget_flags_3517; - x86::Gp ret_val_fget_flags_3517 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3517, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3517; - setRet(call_fget_flags_3517, 0, ret_val_fget_flags_3517); + cc.invoke(&call_fp_vector_unary_op_3531, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3532, 0, reinterpret_cast(this)); + setRet(call_sew_3532, 0, ret_val_sew_3532); + setArg(call_fp_vector_unary_op_3531, 0, V); + setArg(call_fp_vector_unary_op_3531, 1, 19); + setArg(call_fp_vector_unary_op_3531, 2, 0); + setArg(call_fp_vector_unary_op_3531, 3, fp_vector_unary_op_3531_arg3); + setArg(call_fp_vector_unary_op_3531, 4, fp_vector_unary_op_3531_arg4); + setArg(call_fp_vector_unary_op_3531, 5, fp_vector_unary_op_3531_arg5); + setArg(call_fp_vector_unary_op_3531, 6, vm); + setArg(call_fp_vector_unary_op_3531, 7, vd); + setArg(call_fp_vector_unary_op_3531, 8, vs2); + setArg(call_fp_vector_unary_op_3531, 9, fp_vector_unary_op_3531_arg9); + setArg(call_fp_vector_unary_op_3531, 10, fp_vector_unary_op_3531_arg10); + InvokeNode* call_fget_flags_3533; + x86::Gp ret_val_fget_flags_3533 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3533, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3533; + setRet(call_fget_flags_3533, 0, ret_val_fget_flags_3533); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3518 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3518, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3518, 32, false) - , traits::vstart); + auto tmp3534 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3534, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3534, traits::vstart); } cc.bind(label_merge); } @@ -80318,30 +79824,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3519; - x86::Gp ret_val_get_sew_pow_3519 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3519, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3520 = get_reg(cc, 8, false); - mov(cc, tmp3520, 1); + InvokeNode* call_get_sew_pow_3535; + x86::Gp ret_val_get_sew_pow_3535 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3535, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3536 = get_reg(cc, 8, false); + mov(cc, tmp3536, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3520, (ret_val_get_sew_pow_3519))), 8, false), ~ 1); - setArg(call_get_sew_pow_3519, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3519, 0, ret_val_get_sew_pow_3519); + (gen_operation(cc, shl, tmp3536, (ret_val_get_sew_pow_3535))), 8, false), ~ 1); + setArg(call_get_sew_pow_3535, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3535, 0, ret_val_get_sew_pow_3535); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3521; - auto illegal_fp_normal_3521_arg2 = SEW; - auto illegal_fp_normal_3521_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3521 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3521, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3521; - setArg(call_illegal_fp_normal_3521, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3521, 1, vd); - setArg(call_illegal_fp_normal_3521, 2, vm); - setArg(call_illegal_fp_normal_3521, 3, illegal_fp_normal_3521_arg2); - setArg(call_illegal_fp_normal_3521, 4, illegal_fp_normal_3521_arg3); - setRet(call_illegal_fp_normal_3521, 0, ret_val_illegal_fp_normal_3521); + InvokeNode* call_illegal_fp_normal_3537; + auto illegal_fp_normal_3537_arg2 = SEW; + auto illegal_fp_normal_3537_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3537 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3537, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3537; + setArg(call_illegal_fp_normal_3537, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3537, 1, vd); + setArg(call_illegal_fp_normal_3537, 2, vm); + setArg(call_illegal_fp_normal_3537, 3, illegal_fp_normal_3537_arg2); + setArg(call_illegal_fp_normal_3537, 4, illegal_fp_normal_3537_arg3); + setRet(call_illegal_fp_normal_3537, 0, ret_val_illegal_fp_normal_3537); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80357,44 +79863,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3523; - x86::Gp ret_val_sew_3523 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3523, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3522; - auto fp_vector_unary_op_3522_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3522_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3522_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3522_arg9 = rm; - auto fp_vector_unary_op_3522_arg10 = ret_val_sew_3523; + InvokeNode* call_sew_3539; + x86::Gp ret_val_sew_3539 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3539, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3538; + auto fp_vector_unary_op_3538_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3538_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3538_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3538_arg9 = rm; + auto fp_vector_unary_op_3538_arg10 = ret_val_sew_3539; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3522, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3523, 0, reinterpret_cast(this)); - setRet(call_sew_3523, 0, ret_val_sew_3523); - setArg(call_fp_vector_unary_op_3522, 0, V); - setArg(call_fp_vector_unary_op_3522, 1, 19); - setArg(call_fp_vector_unary_op_3522, 2, 4); - setArg(call_fp_vector_unary_op_3522, 3, fp_vector_unary_op_3522_arg3); - setArg(call_fp_vector_unary_op_3522, 4, fp_vector_unary_op_3522_arg4); - setArg(call_fp_vector_unary_op_3522, 5, fp_vector_unary_op_3522_arg5); - setArg(call_fp_vector_unary_op_3522, 6, vm); - setArg(call_fp_vector_unary_op_3522, 7, vd); - setArg(call_fp_vector_unary_op_3522, 8, vs2); - setArg(call_fp_vector_unary_op_3522, 9, fp_vector_unary_op_3522_arg9); - setArg(call_fp_vector_unary_op_3522, 10, fp_vector_unary_op_3522_arg10); - InvokeNode* call_fget_flags_3524; - x86::Gp ret_val_fget_flags_3524 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3524, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3524; - setRet(call_fget_flags_3524, 0, ret_val_fget_flags_3524); + cc.invoke(&call_fp_vector_unary_op_3538, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3539, 0, reinterpret_cast(this)); + setRet(call_sew_3539, 0, ret_val_sew_3539); + setArg(call_fp_vector_unary_op_3538, 0, V); + setArg(call_fp_vector_unary_op_3538, 1, 19); + setArg(call_fp_vector_unary_op_3538, 2, 4); + setArg(call_fp_vector_unary_op_3538, 3, fp_vector_unary_op_3538_arg3); + setArg(call_fp_vector_unary_op_3538, 4, fp_vector_unary_op_3538_arg4); + setArg(call_fp_vector_unary_op_3538, 5, fp_vector_unary_op_3538_arg5); + setArg(call_fp_vector_unary_op_3538, 6, vm); + setArg(call_fp_vector_unary_op_3538, 7, vd); + setArg(call_fp_vector_unary_op_3538, 8, vs2); + setArg(call_fp_vector_unary_op_3538, 9, fp_vector_unary_op_3538_arg9); + setArg(call_fp_vector_unary_op_3538, 10, fp_vector_unary_op_3538_arg10); + InvokeNode* call_fget_flags_3540; + x86::Gp ret_val_fget_flags_3540 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3540, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3540; + setRet(call_fget_flags_3540, 0, ret_val_fget_flags_3540); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3525 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3525, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3525, 32, false) - , traits::vstart); + auto tmp3541 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3541, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3541, traits::vstart); } cc.bind(label_merge); } @@ -80437,30 +79941,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3526; - x86::Gp ret_val_get_sew_pow_3526 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3526, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3527 = get_reg(cc, 8, false); - mov(cc, tmp3527, 1); + InvokeNode* call_get_sew_pow_3542; + x86::Gp ret_val_get_sew_pow_3542 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3542, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3543 = get_reg(cc, 8, false); + mov(cc, tmp3543, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3527, (ret_val_get_sew_pow_3526))), 8, false), ~ 1); - setArg(call_get_sew_pow_3526, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3526, 0, ret_val_get_sew_pow_3526); + (gen_operation(cc, shl, tmp3543, (ret_val_get_sew_pow_3542))), 8, false), ~ 1); + setArg(call_get_sew_pow_3542, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3542, 0, ret_val_get_sew_pow_3542); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3528; - auto illegal_fp_normal_3528_arg2 = SEW; - auto illegal_fp_normal_3528_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3528 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3528, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3528; - setArg(call_illegal_fp_normal_3528, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3528, 1, vd); - setArg(call_illegal_fp_normal_3528, 2, vm); - setArg(call_illegal_fp_normal_3528, 3, illegal_fp_normal_3528_arg2); - setArg(call_illegal_fp_normal_3528, 4, illegal_fp_normal_3528_arg3); - setRet(call_illegal_fp_normal_3528, 0, ret_val_illegal_fp_normal_3528); + InvokeNode* call_illegal_fp_normal_3544; + auto illegal_fp_normal_3544_arg2 = SEW; + auto illegal_fp_normal_3544_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3544 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3544, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3544; + setArg(call_illegal_fp_normal_3544, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3544, 1, vd); + setArg(call_illegal_fp_normal_3544, 2, vm); + setArg(call_illegal_fp_normal_3544, 3, illegal_fp_normal_3544_arg2); + setArg(call_illegal_fp_normal_3544, 4, illegal_fp_normal_3544_arg3); + setRet(call_illegal_fp_normal_3544, 0, ret_val_illegal_fp_normal_3544); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80476,44 +79980,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3530; - x86::Gp ret_val_sew_3530 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3530, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3529; - auto fp_vector_unary_op_3529_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3529_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3529_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3529_arg9 = rm; - auto fp_vector_unary_op_3529_arg10 = ret_val_sew_3530; + InvokeNode* call_sew_3546; + x86::Gp ret_val_sew_3546 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3546, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3545; + auto fp_vector_unary_op_3545_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3545_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3545_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3545_arg9 = rm; + auto fp_vector_unary_op_3545_arg10 = ret_val_sew_3546; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3529, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3530, 0, reinterpret_cast(this)); - setRet(call_sew_3530, 0, ret_val_sew_3530); - setArg(call_fp_vector_unary_op_3529, 0, V); - setArg(call_fp_vector_unary_op_3529, 1, 19); - setArg(call_fp_vector_unary_op_3529, 2, 5); - setArg(call_fp_vector_unary_op_3529, 3, fp_vector_unary_op_3529_arg3); - setArg(call_fp_vector_unary_op_3529, 4, fp_vector_unary_op_3529_arg4); - setArg(call_fp_vector_unary_op_3529, 5, fp_vector_unary_op_3529_arg5); - setArg(call_fp_vector_unary_op_3529, 6, vm); - setArg(call_fp_vector_unary_op_3529, 7, vd); - setArg(call_fp_vector_unary_op_3529, 8, vs2); - setArg(call_fp_vector_unary_op_3529, 9, fp_vector_unary_op_3529_arg9); - setArg(call_fp_vector_unary_op_3529, 10, fp_vector_unary_op_3529_arg10); - InvokeNode* call_fget_flags_3531; - x86::Gp ret_val_fget_flags_3531 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3531, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3531; - setRet(call_fget_flags_3531, 0, ret_val_fget_flags_3531); + cc.invoke(&call_fp_vector_unary_op_3545, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3546, 0, reinterpret_cast(this)); + setRet(call_sew_3546, 0, ret_val_sew_3546); + setArg(call_fp_vector_unary_op_3545, 0, V); + setArg(call_fp_vector_unary_op_3545, 1, 19); + setArg(call_fp_vector_unary_op_3545, 2, 5); + setArg(call_fp_vector_unary_op_3545, 3, fp_vector_unary_op_3545_arg3); + setArg(call_fp_vector_unary_op_3545, 4, fp_vector_unary_op_3545_arg4); + setArg(call_fp_vector_unary_op_3545, 5, fp_vector_unary_op_3545_arg5); + setArg(call_fp_vector_unary_op_3545, 6, vm); + setArg(call_fp_vector_unary_op_3545, 7, vd); + setArg(call_fp_vector_unary_op_3545, 8, vs2); + setArg(call_fp_vector_unary_op_3545, 9, fp_vector_unary_op_3545_arg9); + setArg(call_fp_vector_unary_op_3545, 10, fp_vector_unary_op_3545_arg10); + InvokeNode* call_fget_flags_3547; + x86::Gp ret_val_fget_flags_3547 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3547, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3547; + setRet(call_fget_flags_3547, 0, ret_val_fget_flags_3547); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3532 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3532, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3532, 32, false) - , traits::vstart); + auto tmp3548 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3548, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3548, traits::vstart); } cc.bind(label_merge); } @@ -80557,30 +80059,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3533; - x86::Gp ret_val_get_sew_pow_3533 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3533, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3534 = get_reg(cc, 8, false); - mov(cc, tmp3534, 1); + InvokeNode* call_get_sew_pow_3549; + x86::Gp ret_val_get_sew_pow_3549 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3549, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3550 = get_reg(cc, 8, false); + mov(cc, tmp3550, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3534, (ret_val_get_sew_pow_3533))), 8, false), ~ 1); - setArg(call_get_sew_pow_3533, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3533, 0, ret_val_get_sew_pow_3533); + (gen_operation(cc, shl, tmp3550, (ret_val_get_sew_pow_3549))), 8, false), ~ 1); + setArg(call_get_sew_pow_3549, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3549, 0, ret_val_get_sew_pow_3549); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3535; - auto illegal_fp_normal_3535_arg2 = SEW; - auto illegal_fp_normal_3535_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3535 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3535, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3535; - setArg(call_illegal_fp_normal_3535, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3535, 1, vd); - setArg(call_illegal_fp_normal_3535, 2, vm); - setArg(call_illegal_fp_normal_3535, 3, illegal_fp_normal_3535_arg2); - setArg(call_illegal_fp_normal_3535, 4, illegal_fp_normal_3535_arg3); - setRet(call_illegal_fp_normal_3535, 0, ret_val_illegal_fp_normal_3535); + InvokeNode* call_illegal_fp_normal_3551; + auto illegal_fp_normal_3551_arg2 = SEW; + auto illegal_fp_normal_3551_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3551 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3551, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3551; + setArg(call_illegal_fp_normal_3551, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3551, 1, vd); + setArg(call_illegal_fp_normal_3551, 2, vm); + setArg(call_illegal_fp_normal_3551, 3, illegal_fp_normal_3551_arg2); + setArg(call_illegal_fp_normal_3551, 4, illegal_fp_normal_3551_arg3); + setRet(call_illegal_fp_normal_3551, 0, ret_val_illegal_fp_normal_3551); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80596,41 +80098,39 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3537; - x86::Gp ret_val_sew_3537 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3537, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3536; - auto fp_vector_imm_op_3536_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3536_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3536_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3536_arg9 = gen_ext(cc, + InvokeNode* call_sew_3553; + x86::Gp ret_val_sew_3553 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3553, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3552; + auto fp_vector_imm_op_3552_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3552_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3552_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3552_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3536_arg10 = rm; - auto fp_vector_imm_op_3536_arg11 = ret_val_sew_3537; + auto fp_vector_imm_op_3552_arg10 = rm; + auto fp_vector_imm_op_3552_arg11 = ret_val_sew_3553; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3536, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3537, 0, reinterpret_cast(this)); - setRet(call_sew_3537, 0, ret_val_sew_3537); - setArg(call_fp_vector_imm_op_3536, 0, V); - setArg(call_fp_vector_imm_op_3536, 1, 4); - setArg(call_fp_vector_imm_op_3536, 2, 5); - setArg(call_fp_vector_imm_op_3536, 3, fp_vector_imm_op_3536_arg3); - setArg(call_fp_vector_imm_op_3536, 4, fp_vector_imm_op_3536_arg4); - setArg(call_fp_vector_imm_op_3536, 5, fp_vector_imm_op_3536_arg5); - setArg(call_fp_vector_imm_op_3536, 6, vm); - setArg(call_fp_vector_imm_op_3536, 7, vd); - setArg(call_fp_vector_imm_op_3536, 8, vs2); - setArg(call_fp_vector_imm_op_3536, 9, fp_vector_imm_op_3536_arg9); - setArg(call_fp_vector_imm_op_3536, 10, fp_vector_imm_op_3536_arg10); - setArg(call_fp_vector_imm_op_3536, 11, fp_vector_imm_op_3536_arg11); + cc.invoke(&call_fp_vector_imm_op_3552, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3553, 0, reinterpret_cast(this)); + setRet(call_sew_3553, 0, ret_val_sew_3553); + setArg(call_fp_vector_imm_op_3552, 0, V); + setArg(call_fp_vector_imm_op_3552, 1, 4); + setArg(call_fp_vector_imm_op_3552, 2, 5); + setArg(call_fp_vector_imm_op_3552, 3, fp_vector_imm_op_3552_arg3); + setArg(call_fp_vector_imm_op_3552, 4, fp_vector_imm_op_3552_arg4); + setArg(call_fp_vector_imm_op_3552, 5, fp_vector_imm_op_3552_arg5); + setArg(call_fp_vector_imm_op_3552, 6, vm); + setArg(call_fp_vector_imm_op_3552, 7, vd); + setArg(call_fp_vector_imm_op_3552, 8, vs2); + setArg(call_fp_vector_imm_op_3552, 9, fp_vector_imm_op_3552_arg9); + setArg(call_fp_vector_imm_op_3552, 10, fp_vector_imm_op_3552_arg10); + setArg(call_fp_vector_imm_op_3552, 11, fp_vector_imm_op_3552_arg11); } cc.bind(label_merge); } - auto tmp3538 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3538, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3538, 32, false) - , traits::vstart); + auto tmp3554 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3554, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3554, traits::vstart); } cc.bind(label_merge); } @@ -80674,30 +80174,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3539; - x86::Gp ret_val_get_sew_pow_3539 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3539, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3540 = get_reg(cc, 8, false); - mov(cc, tmp3540, 1); + InvokeNode* call_get_sew_pow_3555; + x86::Gp ret_val_get_sew_pow_3555 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3555, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3556 = get_reg(cc, 8, false); + mov(cc, tmp3556, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3540, (ret_val_get_sew_pow_3539))), 8, false), ~ 1); - setArg(call_get_sew_pow_3539, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3539, 0, ret_val_get_sew_pow_3539); + (gen_operation(cc, shl, tmp3556, (ret_val_get_sew_pow_3555))), 8, false), ~ 1); + setArg(call_get_sew_pow_3555, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3555, 0, ret_val_get_sew_pow_3555); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3541; - auto illegal_fp_normal_3541_arg2 = SEW; - auto illegal_fp_normal_3541_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3541 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3541, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3541; - setArg(call_illegal_fp_normal_3541, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3541, 1, vd); - setArg(call_illegal_fp_normal_3541, 2, vm); - setArg(call_illegal_fp_normal_3541, 3, illegal_fp_normal_3541_arg2); - setArg(call_illegal_fp_normal_3541, 4, illegal_fp_normal_3541_arg3); - setRet(call_illegal_fp_normal_3541, 0, ret_val_illegal_fp_normal_3541); + InvokeNode* call_illegal_fp_normal_3557; + auto illegal_fp_normal_3557_arg2 = SEW; + auto illegal_fp_normal_3557_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3557 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3557, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3557; + setArg(call_illegal_fp_normal_3557, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3557, 1, vd); + setArg(call_illegal_fp_normal_3557, 2, vm); + setArg(call_illegal_fp_normal_3557, 3, illegal_fp_normal_3557_arg2); + setArg(call_illegal_fp_normal_3557, 4, illegal_fp_normal_3557_arg3); + setRet(call_illegal_fp_normal_3557, 0, ret_val_illegal_fp_normal_3557); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80713,39 +80213,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3543; - x86::Gp ret_val_sew_3543 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3543, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3542; - auto fp_vector_vector_op_3542_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3542_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3542_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3542_arg10 = rm; - auto fp_vector_vector_op_3542_arg11 = ret_val_sew_3543; + InvokeNode* call_sew_3559; + x86::Gp ret_val_sew_3559 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3559, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3558; + auto fp_vector_vector_op_3558_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3558_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3558_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3558_arg10 = rm; + auto fp_vector_vector_op_3558_arg11 = ret_val_sew_3559; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3542, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3543, 0, reinterpret_cast(this)); - setRet(call_sew_3543, 0, ret_val_sew_3543); - setArg(call_fp_vector_vector_op_3542, 0, V); - setArg(call_fp_vector_vector_op_3542, 1, 4); - setArg(call_fp_vector_vector_op_3542, 2, 1); - setArg(call_fp_vector_vector_op_3542, 3, fp_vector_vector_op_3542_arg3); - setArg(call_fp_vector_vector_op_3542, 4, fp_vector_vector_op_3542_arg4); - setArg(call_fp_vector_vector_op_3542, 5, fp_vector_vector_op_3542_arg5); - setArg(call_fp_vector_vector_op_3542, 6, vm); - setArg(call_fp_vector_vector_op_3542, 7, vd); - setArg(call_fp_vector_vector_op_3542, 8, vs2); - setArg(call_fp_vector_vector_op_3542, 9, vs1); - setArg(call_fp_vector_vector_op_3542, 10, fp_vector_vector_op_3542_arg10); - setArg(call_fp_vector_vector_op_3542, 11, fp_vector_vector_op_3542_arg11); + cc.invoke(&call_fp_vector_vector_op_3558, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3559, 0, reinterpret_cast(this)); + setRet(call_sew_3559, 0, ret_val_sew_3559); + setArg(call_fp_vector_vector_op_3558, 0, V); + setArg(call_fp_vector_vector_op_3558, 1, 4); + setArg(call_fp_vector_vector_op_3558, 2, 1); + setArg(call_fp_vector_vector_op_3558, 3, fp_vector_vector_op_3558_arg3); + setArg(call_fp_vector_vector_op_3558, 4, fp_vector_vector_op_3558_arg4); + setArg(call_fp_vector_vector_op_3558, 5, fp_vector_vector_op_3558_arg5); + setArg(call_fp_vector_vector_op_3558, 6, vm); + setArg(call_fp_vector_vector_op_3558, 7, vd); + setArg(call_fp_vector_vector_op_3558, 8, vs2); + setArg(call_fp_vector_vector_op_3558, 9, vs1); + setArg(call_fp_vector_vector_op_3558, 10, fp_vector_vector_op_3558_arg10); + setArg(call_fp_vector_vector_op_3558, 11, fp_vector_vector_op_3558_arg11); } cc.bind(label_merge); } - auto tmp3544 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3544, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3544, 32, false) - , traits::vstart); + auto tmp3560 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3560, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3560, traits::vstart); } cc.bind(label_merge); } @@ -80789,30 +80287,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3545; - x86::Gp ret_val_get_sew_pow_3545 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3545, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3546 = get_reg(cc, 8, false); - mov(cc, tmp3546, 1); + InvokeNode* call_get_sew_pow_3561; + x86::Gp ret_val_get_sew_pow_3561 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3561, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3562 = get_reg(cc, 8, false); + mov(cc, tmp3562, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3546, (ret_val_get_sew_pow_3545))), 8, false), ~ 1); - setArg(call_get_sew_pow_3545, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3545, 0, ret_val_get_sew_pow_3545); + (gen_operation(cc, shl, tmp3562, (ret_val_get_sew_pow_3561))), 8, false), ~ 1); + setArg(call_get_sew_pow_3561, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3561, 0, ret_val_get_sew_pow_3561); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3547; - auto illegal_fp_normal_3547_arg2 = SEW; - auto illegal_fp_normal_3547_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3547 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3547, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3547; - setArg(call_illegal_fp_normal_3547, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3547, 1, vd); - setArg(call_illegal_fp_normal_3547, 2, vm); - setArg(call_illegal_fp_normal_3547, 3, illegal_fp_normal_3547_arg2); - setArg(call_illegal_fp_normal_3547, 4, illegal_fp_normal_3547_arg3); - setRet(call_illegal_fp_normal_3547, 0, ret_val_illegal_fp_normal_3547); + InvokeNode* call_illegal_fp_normal_3563; + auto illegal_fp_normal_3563_arg2 = SEW; + auto illegal_fp_normal_3563_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3563 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3563, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3563; + setArg(call_illegal_fp_normal_3563, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3563, 1, vd); + setArg(call_illegal_fp_normal_3563, 2, vm); + setArg(call_illegal_fp_normal_3563, 3, illegal_fp_normal_3563_arg2); + setArg(call_illegal_fp_normal_3563, 4, illegal_fp_normal_3563_arg3); + setRet(call_illegal_fp_normal_3563, 0, ret_val_illegal_fp_normal_3563); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80828,41 +80326,39 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3549; - x86::Gp ret_val_sew_3549 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3549, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3548; - auto fp_vector_imm_op_3548_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3548_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3548_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3548_arg9 = gen_ext(cc, + InvokeNode* call_sew_3565; + x86::Gp ret_val_sew_3565 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3565, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3564; + auto fp_vector_imm_op_3564_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3564_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3564_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3564_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3548_arg10 = rm; - auto fp_vector_imm_op_3548_arg11 = ret_val_sew_3549; + auto fp_vector_imm_op_3564_arg10 = rm; + auto fp_vector_imm_op_3564_arg11 = ret_val_sew_3565; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3548, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3549, 0, reinterpret_cast(this)); - setRet(call_sew_3549, 0, ret_val_sew_3549); - setArg(call_fp_vector_imm_op_3548, 0, V); - setArg(call_fp_vector_imm_op_3548, 1, 6); - setArg(call_fp_vector_imm_op_3548, 2, 5); - setArg(call_fp_vector_imm_op_3548, 3, fp_vector_imm_op_3548_arg3); - setArg(call_fp_vector_imm_op_3548, 4, fp_vector_imm_op_3548_arg4); - setArg(call_fp_vector_imm_op_3548, 5, fp_vector_imm_op_3548_arg5); - setArg(call_fp_vector_imm_op_3548, 6, vm); - setArg(call_fp_vector_imm_op_3548, 7, vd); - setArg(call_fp_vector_imm_op_3548, 8, vs2); - setArg(call_fp_vector_imm_op_3548, 9, fp_vector_imm_op_3548_arg9); - setArg(call_fp_vector_imm_op_3548, 10, fp_vector_imm_op_3548_arg10); - setArg(call_fp_vector_imm_op_3548, 11, fp_vector_imm_op_3548_arg11); + cc.invoke(&call_fp_vector_imm_op_3564, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3565, 0, reinterpret_cast(this)); + setRet(call_sew_3565, 0, ret_val_sew_3565); + setArg(call_fp_vector_imm_op_3564, 0, V); + setArg(call_fp_vector_imm_op_3564, 1, 6); + setArg(call_fp_vector_imm_op_3564, 2, 5); + setArg(call_fp_vector_imm_op_3564, 3, fp_vector_imm_op_3564_arg3); + setArg(call_fp_vector_imm_op_3564, 4, fp_vector_imm_op_3564_arg4); + setArg(call_fp_vector_imm_op_3564, 5, fp_vector_imm_op_3564_arg5); + setArg(call_fp_vector_imm_op_3564, 6, vm); + setArg(call_fp_vector_imm_op_3564, 7, vd); + setArg(call_fp_vector_imm_op_3564, 8, vs2); + setArg(call_fp_vector_imm_op_3564, 9, fp_vector_imm_op_3564_arg9); + setArg(call_fp_vector_imm_op_3564, 10, fp_vector_imm_op_3564_arg10); + setArg(call_fp_vector_imm_op_3564, 11, fp_vector_imm_op_3564_arg11); } cc.bind(label_merge); } - auto tmp3550 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3550, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3550, 32, false) - , traits::vstart); + auto tmp3566 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3566, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3566, traits::vstart); } cc.bind(label_merge); } @@ -80906,30 +80402,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3551; - x86::Gp ret_val_get_sew_pow_3551 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3551, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3552 = get_reg(cc, 8, false); - mov(cc, tmp3552, 1); + InvokeNode* call_get_sew_pow_3567; + x86::Gp ret_val_get_sew_pow_3567 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3567, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3568 = get_reg(cc, 8, false); + mov(cc, tmp3568, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3552, (ret_val_get_sew_pow_3551))), 8, false), ~ 1); - setArg(call_get_sew_pow_3551, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3551, 0, ret_val_get_sew_pow_3551); + (gen_operation(cc, shl, tmp3568, (ret_val_get_sew_pow_3567))), 8, false), ~ 1); + setArg(call_get_sew_pow_3567, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3567, 0, ret_val_get_sew_pow_3567); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3553; - auto illegal_fp_normal_3553_arg2 = SEW; - auto illegal_fp_normal_3553_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3553 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3553, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3553; - setArg(call_illegal_fp_normal_3553, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3553, 1, vd); - setArg(call_illegal_fp_normal_3553, 2, vm); - setArg(call_illegal_fp_normal_3553, 3, illegal_fp_normal_3553_arg2); - setArg(call_illegal_fp_normal_3553, 4, illegal_fp_normal_3553_arg3); - setRet(call_illegal_fp_normal_3553, 0, ret_val_illegal_fp_normal_3553); + InvokeNode* call_illegal_fp_normal_3569; + auto illegal_fp_normal_3569_arg2 = SEW; + auto illegal_fp_normal_3569_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3569 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3569, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3569; + setArg(call_illegal_fp_normal_3569, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3569, 1, vd); + setArg(call_illegal_fp_normal_3569, 2, vm); + setArg(call_illegal_fp_normal_3569, 3, illegal_fp_normal_3569_arg2); + setArg(call_illegal_fp_normal_3569, 4, illegal_fp_normal_3569_arg3); + setRet(call_illegal_fp_normal_3569, 0, ret_val_illegal_fp_normal_3569); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80945,39 +80441,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3555; - x86::Gp ret_val_sew_3555 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3555, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3554; - auto fp_vector_vector_op_3554_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3554_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3554_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3554_arg10 = rm; - auto fp_vector_vector_op_3554_arg11 = ret_val_sew_3555; + InvokeNode* call_sew_3571; + x86::Gp ret_val_sew_3571 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3571, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3570; + auto fp_vector_vector_op_3570_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3570_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3570_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3570_arg10 = rm; + auto fp_vector_vector_op_3570_arg11 = ret_val_sew_3571; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3554, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3555, 0, reinterpret_cast(this)); - setRet(call_sew_3555, 0, ret_val_sew_3555); - setArg(call_fp_vector_vector_op_3554, 0, V); - setArg(call_fp_vector_vector_op_3554, 1, 6); - setArg(call_fp_vector_vector_op_3554, 2, 1); - setArg(call_fp_vector_vector_op_3554, 3, fp_vector_vector_op_3554_arg3); - setArg(call_fp_vector_vector_op_3554, 4, fp_vector_vector_op_3554_arg4); - setArg(call_fp_vector_vector_op_3554, 5, fp_vector_vector_op_3554_arg5); - setArg(call_fp_vector_vector_op_3554, 6, vm); - setArg(call_fp_vector_vector_op_3554, 7, vd); - setArg(call_fp_vector_vector_op_3554, 8, vs2); - setArg(call_fp_vector_vector_op_3554, 9, vs1); - setArg(call_fp_vector_vector_op_3554, 10, fp_vector_vector_op_3554_arg10); - setArg(call_fp_vector_vector_op_3554, 11, fp_vector_vector_op_3554_arg11); + cc.invoke(&call_fp_vector_vector_op_3570, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3571, 0, reinterpret_cast(this)); + setRet(call_sew_3571, 0, ret_val_sew_3571); + setArg(call_fp_vector_vector_op_3570, 0, V); + setArg(call_fp_vector_vector_op_3570, 1, 6); + setArg(call_fp_vector_vector_op_3570, 2, 1); + setArg(call_fp_vector_vector_op_3570, 3, fp_vector_vector_op_3570_arg3); + setArg(call_fp_vector_vector_op_3570, 4, fp_vector_vector_op_3570_arg4); + setArg(call_fp_vector_vector_op_3570, 5, fp_vector_vector_op_3570_arg5); + setArg(call_fp_vector_vector_op_3570, 6, vm); + setArg(call_fp_vector_vector_op_3570, 7, vd); + setArg(call_fp_vector_vector_op_3570, 8, vs2); + setArg(call_fp_vector_vector_op_3570, 9, vs1); + setArg(call_fp_vector_vector_op_3570, 10, fp_vector_vector_op_3570_arg10); + setArg(call_fp_vector_vector_op_3570, 11, fp_vector_vector_op_3570_arg11); } cc.bind(label_merge); } - auto tmp3556 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3556, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3556, 32, false) - , traits::vstart); + auto tmp3572 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3572, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3572, traits::vstart); } cc.bind(label_merge); } @@ -81021,30 +80515,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3557; - x86::Gp ret_val_get_sew_pow_3557 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3557, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3558 = get_reg(cc, 8, false); - mov(cc, tmp3558, 1); + InvokeNode* call_get_sew_pow_3573; + x86::Gp ret_val_get_sew_pow_3573 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3573, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3574 = get_reg(cc, 8, false); + mov(cc, tmp3574, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3558, (ret_val_get_sew_pow_3557))), 8, false), ~ 1); - setArg(call_get_sew_pow_3557, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3557, 0, ret_val_get_sew_pow_3557); + (gen_operation(cc, shl, tmp3574, (ret_val_get_sew_pow_3573))), 8, false), ~ 1); + setArg(call_get_sew_pow_3573, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3573, 0, ret_val_get_sew_pow_3573); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3559; - auto illegal_fp_normal_3559_arg2 = SEW; - auto illegal_fp_normal_3559_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3559 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3559, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3559; - setArg(call_illegal_fp_normal_3559, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3559, 1, vd); - setArg(call_illegal_fp_normal_3559, 2, vm); - setArg(call_illegal_fp_normal_3559, 3, illegal_fp_normal_3559_arg2); - setArg(call_illegal_fp_normal_3559, 4, illegal_fp_normal_3559_arg3); - setRet(call_illegal_fp_normal_3559, 0, ret_val_illegal_fp_normal_3559); + InvokeNode* call_illegal_fp_normal_3575; + auto illegal_fp_normal_3575_arg2 = SEW; + auto illegal_fp_normal_3575_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3575 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3575, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3575; + setArg(call_illegal_fp_normal_3575, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3575, 1, vd); + setArg(call_illegal_fp_normal_3575, 2, vm); + setArg(call_illegal_fp_normal_3575, 3, illegal_fp_normal_3575_arg2); + setArg(call_illegal_fp_normal_3575, 4, illegal_fp_normal_3575_arg3); + setRet(call_illegal_fp_normal_3575, 0, ret_val_illegal_fp_normal_3575); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81060,41 +80554,39 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3561; - x86::Gp ret_val_sew_3561 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3561, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3560; - auto fp_vector_imm_op_3560_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3560_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3560_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3560_arg9 = gen_ext(cc, + InvokeNode* call_sew_3577; + x86::Gp ret_val_sew_3577 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3577, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3576; + auto fp_vector_imm_op_3576_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3576_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3576_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3576_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3560_arg10 = rm; - auto fp_vector_imm_op_3560_arg11 = ret_val_sew_3561; + auto fp_vector_imm_op_3576_arg10 = rm; + auto fp_vector_imm_op_3576_arg11 = ret_val_sew_3577; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3560, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3561, 0, reinterpret_cast(this)); - setRet(call_sew_3561, 0, ret_val_sew_3561); - setArg(call_fp_vector_imm_op_3560, 0, V); - setArg(call_fp_vector_imm_op_3560, 1, 8); - setArg(call_fp_vector_imm_op_3560, 2, 5); - setArg(call_fp_vector_imm_op_3560, 3, fp_vector_imm_op_3560_arg3); - setArg(call_fp_vector_imm_op_3560, 4, fp_vector_imm_op_3560_arg4); - setArg(call_fp_vector_imm_op_3560, 5, fp_vector_imm_op_3560_arg5); - setArg(call_fp_vector_imm_op_3560, 6, vm); - setArg(call_fp_vector_imm_op_3560, 7, vd); - setArg(call_fp_vector_imm_op_3560, 8, vs2); - setArg(call_fp_vector_imm_op_3560, 9, fp_vector_imm_op_3560_arg9); - setArg(call_fp_vector_imm_op_3560, 10, fp_vector_imm_op_3560_arg10); - setArg(call_fp_vector_imm_op_3560, 11, fp_vector_imm_op_3560_arg11); + cc.invoke(&call_fp_vector_imm_op_3576, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3577, 0, reinterpret_cast(this)); + setRet(call_sew_3577, 0, ret_val_sew_3577); + setArg(call_fp_vector_imm_op_3576, 0, V); + setArg(call_fp_vector_imm_op_3576, 1, 8); + setArg(call_fp_vector_imm_op_3576, 2, 5); + setArg(call_fp_vector_imm_op_3576, 3, fp_vector_imm_op_3576_arg3); + setArg(call_fp_vector_imm_op_3576, 4, fp_vector_imm_op_3576_arg4); + setArg(call_fp_vector_imm_op_3576, 5, fp_vector_imm_op_3576_arg5); + setArg(call_fp_vector_imm_op_3576, 6, vm); + setArg(call_fp_vector_imm_op_3576, 7, vd); + setArg(call_fp_vector_imm_op_3576, 8, vs2); + setArg(call_fp_vector_imm_op_3576, 9, fp_vector_imm_op_3576_arg9); + setArg(call_fp_vector_imm_op_3576, 10, fp_vector_imm_op_3576_arg10); + setArg(call_fp_vector_imm_op_3576, 11, fp_vector_imm_op_3576_arg11); } cc.bind(label_merge); } - auto tmp3562 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3562, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3562, 32, false) - , traits::vstart); + auto tmp3578 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3578, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3578, traits::vstart); } cc.bind(label_merge); } @@ -81138,30 +80630,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3563; - x86::Gp ret_val_get_sew_pow_3563 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3563, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3564 = get_reg(cc, 8, false); - mov(cc, tmp3564, 1); + InvokeNode* call_get_sew_pow_3579; + x86::Gp ret_val_get_sew_pow_3579 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3579, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3580 = get_reg(cc, 8, false); + mov(cc, tmp3580, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3564, (ret_val_get_sew_pow_3563))), 8, false), ~ 1); - setArg(call_get_sew_pow_3563, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3563, 0, ret_val_get_sew_pow_3563); + (gen_operation(cc, shl, tmp3580, (ret_val_get_sew_pow_3579))), 8, false), ~ 1); + setArg(call_get_sew_pow_3579, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3579, 0, ret_val_get_sew_pow_3579); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3565; - auto illegal_fp_normal_3565_arg2 = SEW; - auto illegal_fp_normal_3565_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3565 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3565, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3565; - setArg(call_illegal_fp_normal_3565, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3565, 1, vd); - setArg(call_illegal_fp_normal_3565, 2, vm); - setArg(call_illegal_fp_normal_3565, 3, illegal_fp_normal_3565_arg2); - setArg(call_illegal_fp_normal_3565, 4, illegal_fp_normal_3565_arg3); - setRet(call_illegal_fp_normal_3565, 0, ret_val_illegal_fp_normal_3565); + InvokeNode* call_illegal_fp_normal_3581; + auto illegal_fp_normal_3581_arg2 = SEW; + auto illegal_fp_normal_3581_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3581 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3581, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3581; + setArg(call_illegal_fp_normal_3581, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3581, 1, vd); + setArg(call_illegal_fp_normal_3581, 2, vm); + setArg(call_illegal_fp_normal_3581, 3, illegal_fp_normal_3581_arg2); + setArg(call_illegal_fp_normal_3581, 4, illegal_fp_normal_3581_arg3); + setRet(call_illegal_fp_normal_3581, 0, ret_val_illegal_fp_normal_3581); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81177,39 +80669,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3567; - x86::Gp ret_val_sew_3567 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3567, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3566; - auto fp_vector_vector_op_3566_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3566_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3566_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3566_arg10 = rm; - auto fp_vector_vector_op_3566_arg11 = ret_val_sew_3567; + InvokeNode* call_sew_3583; + x86::Gp ret_val_sew_3583 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3583, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3582; + auto fp_vector_vector_op_3582_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3582_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3582_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3582_arg10 = rm; + auto fp_vector_vector_op_3582_arg11 = ret_val_sew_3583; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3566, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3567, 0, reinterpret_cast(this)); - setRet(call_sew_3567, 0, ret_val_sew_3567); - setArg(call_fp_vector_vector_op_3566, 0, V); - setArg(call_fp_vector_vector_op_3566, 1, 8); - setArg(call_fp_vector_vector_op_3566, 2, 1); - setArg(call_fp_vector_vector_op_3566, 3, fp_vector_vector_op_3566_arg3); - setArg(call_fp_vector_vector_op_3566, 4, fp_vector_vector_op_3566_arg4); - setArg(call_fp_vector_vector_op_3566, 5, fp_vector_vector_op_3566_arg5); - setArg(call_fp_vector_vector_op_3566, 6, vm); - setArg(call_fp_vector_vector_op_3566, 7, vd); - setArg(call_fp_vector_vector_op_3566, 8, vs2); - setArg(call_fp_vector_vector_op_3566, 9, vs1); - setArg(call_fp_vector_vector_op_3566, 10, fp_vector_vector_op_3566_arg10); - setArg(call_fp_vector_vector_op_3566, 11, fp_vector_vector_op_3566_arg11); + cc.invoke(&call_fp_vector_vector_op_3582, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3583, 0, reinterpret_cast(this)); + setRet(call_sew_3583, 0, ret_val_sew_3583); + setArg(call_fp_vector_vector_op_3582, 0, V); + setArg(call_fp_vector_vector_op_3582, 1, 8); + setArg(call_fp_vector_vector_op_3582, 2, 1); + setArg(call_fp_vector_vector_op_3582, 3, fp_vector_vector_op_3582_arg3); + setArg(call_fp_vector_vector_op_3582, 4, fp_vector_vector_op_3582_arg4); + setArg(call_fp_vector_vector_op_3582, 5, fp_vector_vector_op_3582_arg5); + setArg(call_fp_vector_vector_op_3582, 6, vm); + setArg(call_fp_vector_vector_op_3582, 7, vd); + setArg(call_fp_vector_vector_op_3582, 8, vs2); + setArg(call_fp_vector_vector_op_3582, 9, vs1); + setArg(call_fp_vector_vector_op_3582, 10, fp_vector_vector_op_3582_arg10); + setArg(call_fp_vector_vector_op_3582, 11, fp_vector_vector_op_3582_arg11); } cc.bind(label_merge); } - auto tmp3568 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3568, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3568, 32, false) - , traits::vstart); + auto tmp3584 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3584, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3584, traits::vstart); } cc.bind(label_merge); } @@ -81253,30 +80743,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3569; - x86::Gp ret_val_get_sew_pow_3569 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3569, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3570 = get_reg(cc, 8, false); - mov(cc, tmp3570, 1); + InvokeNode* call_get_sew_pow_3585; + x86::Gp ret_val_get_sew_pow_3585 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3585, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3586 = get_reg(cc, 8, false); + mov(cc, tmp3586, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3570, (ret_val_get_sew_pow_3569))), 8, false), ~ 1); - setArg(call_get_sew_pow_3569, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3569, 0, ret_val_get_sew_pow_3569); + (gen_operation(cc, shl, tmp3586, (ret_val_get_sew_pow_3585))), 8, false), ~ 1); + setArg(call_get_sew_pow_3585, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3585, 0, ret_val_get_sew_pow_3585); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3571; - auto illegal_fp_normal_3571_arg2 = SEW; - auto illegal_fp_normal_3571_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3571 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3571, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3571; - setArg(call_illegal_fp_normal_3571, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3571, 1, vd); - setArg(call_illegal_fp_normal_3571, 2, vm); - setArg(call_illegal_fp_normal_3571, 3, illegal_fp_normal_3571_arg2); - setArg(call_illegal_fp_normal_3571, 4, illegal_fp_normal_3571_arg3); - setRet(call_illegal_fp_normal_3571, 0, ret_val_illegal_fp_normal_3571); + InvokeNode* call_illegal_fp_normal_3587; + auto illegal_fp_normal_3587_arg2 = SEW; + auto illegal_fp_normal_3587_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3587 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3587, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3587; + setArg(call_illegal_fp_normal_3587, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3587, 1, vd); + setArg(call_illegal_fp_normal_3587, 2, vm); + setArg(call_illegal_fp_normal_3587, 3, illegal_fp_normal_3587_arg2); + setArg(call_illegal_fp_normal_3587, 4, illegal_fp_normal_3587_arg3); + setRet(call_illegal_fp_normal_3587, 0, ret_val_illegal_fp_normal_3587); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81292,41 +80782,39 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3573; - x86::Gp ret_val_sew_3573 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3573, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3572; - auto fp_vector_imm_op_3572_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3572_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3572_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3572_arg9 = gen_ext(cc, + InvokeNode* call_sew_3589; + x86::Gp ret_val_sew_3589 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3589, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3588; + auto fp_vector_imm_op_3588_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3588_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3588_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3588_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3572_arg10 = rm; - auto fp_vector_imm_op_3572_arg11 = ret_val_sew_3573; + auto fp_vector_imm_op_3588_arg10 = rm; + auto fp_vector_imm_op_3588_arg11 = ret_val_sew_3589; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3572, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3573, 0, reinterpret_cast(this)); - setRet(call_sew_3573, 0, ret_val_sew_3573); - setArg(call_fp_vector_imm_op_3572, 0, V); - setArg(call_fp_vector_imm_op_3572, 1, 9); - setArg(call_fp_vector_imm_op_3572, 2, 5); - setArg(call_fp_vector_imm_op_3572, 3, fp_vector_imm_op_3572_arg3); - setArg(call_fp_vector_imm_op_3572, 4, fp_vector_imm_op_3572_arg4); - setArg(call_fp_vector_imm_op_3572, 5, fp_vector_imm_op_3572_arg5); - setArg(call_fp_vector_imm_op_3572, 6, vm); - setArg(call_fp_vector_imm_op_3572, 7, vd); - setArg(call_fp_vector_imm_op_3572, 8, vs2); - setArg(call_fp_vector_imm_op_3572, 9, fp_vector_imm_op_3572_arg9); - setArg(call_fp_vector_imm_op_3572, 10, fp_vector_imm_op_3572_arg10); - setArg(call_fp_vector_imm_op_3572, 11, fp_vector_imm_op_3572_arg11); + cc.invoke(&call_fp_vector_imm_op_3588, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3589, 0, reinterpret_cast(this)); + setRet(call_sew_3589, 0, ret_val_sew_3589); + setArg(call_fp_vector_imm_op_3588, 0, V); + setArg(call_fp_vector_imm_op_3588, 1, 9); + setArg(call_fp_vector_imm_op_3588, 2, 5); + setArg(call_fp_vector_imm_op_3588, 3, fp_vector_imm_op_3588_arg3); + setArg(call_fp_vector_imm_op_3588, 4, fp_vector_imm_op_3588_arg4); + setArg(call_fp_vector_imm_op_3588, 5, fp_vector_imm_op_3588_arg5); + setArg(call_fp_vector_imm_op_3588, 6, vm); + setArg(call_fp_vector_imm_op_3588, 7, vd); + setArg(call_fp_vector_imm_op_3588, 8, vs2); + setArg(call_fp_vector_imm_op_3588, 9, fp_vector_imm_op_3588_arg9); + setArg(call_fp_vector_imm_op_3588, 10, fp_vector_imm_op_3588_arg10); + setArg(call_fp_vector_imm_op_3588, 11, fp_vector_imm_op_3588_arg11); } cc.bind(label_merge); } - auto tmp3574 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3574, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3574, 32, false) - , traits::vstart); + auto tmp3590 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3590, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3590, traits::vstart); } cc.bind(label_merge); } @@ -81370,30 +80858,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3575; - x86::Gp ret_val_get_sew_pow_3575 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3575, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3576 = get_reg(cc, 8, false); - mov(cc, tmp3576, 1); + InvokeNode* call_get_sew_pow_3591; + x86::Gp ret_val_get_sew_pow_3591 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3591, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3592 = get_reg(cc, 8, false); + mov(cc, tmp3592, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3576, (ret_val_get_sew_pow_3575))), 8, false), ~ 1); - setArg(call_get_sew_pow_3575, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3575, 0, ret_val_get_sew_pow_3575); + (gen_operation(cc, shl, tmp3592, (ret_val_get_sew_pow_3591))), 8, false), ~ 1); + setArg(call_get_sew_pow_3591, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3591, 0, ret_val_get_sew_pow_3591); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3577; - auto illegal_fp_normal_3577_arg2 = SEW; - auto illegal_fp_normal_3577_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3577 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3577, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3577; - setArg(call_illegal_fp_normal_3577, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3577, 1, vd); - setArg(call_illegal_fp_normal_3577, 2, vm); - setArg(call_illegal_fp_normal_3577, 3, illegal_fp_normal_3577_arg2); - setArg(call_illegal_fp_normal_3577, 4, illegal_fp_normal_3577_arg3); - setRet(call_illegal_fp_normal_3577, 0, ret_val_illegal_fp_normal_3577); + InvokeNode* call_illegal_fp_normal_3593; + auto illegal_fp_normal_3593_arg2 = SEW; + auto illegal_fp_normal_3593_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3593 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3593, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3593; + setArg(call_illegal_fp_normal_3593, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3593, 1, vd); + setArg(call_illegal_fp_normal_3593, 2, vm); + setArg(call_illegal_fp_normal_3593, 3, illegal_fp_normal_3593_arg2); + setArg(call_illegal_fp_normal_3593, 4, illegal_fp_normal_3593_arg3); + setRet(call_illegal_fp_normal_3593, 0, ret_val_illegal_fp_normal_3593); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81409,39 +80897,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3579; - x86::Gp ret_val_sew_3579 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3579, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3578; - auto fp_vector_vector_op_3578_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3578_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3578_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3578_arg10 = rm; - auto fp_vector_vector_op_3578_arg11 = ret_val_sew_3579; + InvokeNode* call_sew_3595; + x86::Gp ret_val_sew_3595 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3595, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3594; + auto fp_vector_vector_op_3594_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3594_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3594_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3594_arg10 = rm; + auto fp_vector_vector_op_3594_arg11 = ret_val_sew_3595; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3578, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3579, 0, reinterpret_cast(this)); - setRet(call_sew_3579, 0, ret_val_sew_3579); - setArg(call_fp_vector_vector_op_3578, 0, V); - setArg(call_fp_vector_vector_op_3578, 1, 9); - setArg(call_fp_vector_vector_op_3578, 2, 1); - setArg(call_fp_vector_vector_op_3578, 3, fp_vector_vector_op_3578_arg3); - setArg(call_fp_vector_vector_op_3578, 4, fp_vector_vector_op_3578_arg4); - setArg(call_fp_vector_vector_op_3578, 5, fp_vector_vector_op_3578_arg5); - setArg(call_fp_vector_vector_op_3578, 6, vm); - setArg(call_fp_vector_vector_op_3578, 7, vd); - setArg(call_fp_vector_vector_op_3578, 8, vs2); - setArg(call_fp_vector_vector_op_3578, 9, vs1); - setArg(call_fp_vector_vector_op_3578, 10, fp_vector_vector_op_3578_arg10); - setArg(call_fp_vector_vector_op_3578, 11, fp_vector_vector_op_3578_arg11); + cc.invoke(&call_fp_vector_vector_op_3594, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3595, 0, reinterpret_cast(this)); + setRet(call_sew_3595, 0, ret_val_sew_3595); + setArg(call_fp_vector_vector_op_3594, 0, V); + setArg(call_fp_vector_vector_op_3594, 1, 9); + setArg(call_fp_vector_vector_op_3594, 2, 1); + setArg(call_fp_vector_vector_op_3594, 3, fp_vector_vector_op_3594_arg3); + setArg(call_fp_vector_vector_op_3594, 4, fp_vector_vector_op_3594_arg4); + setArg(call_fp_vector_vector_op_3594, 5, fp_vector_vector_op_3594_arg5); + setArg(call_fp_vector_vector_op_3594, 6, vm); + setArg(call_fp_vector_vector_op_3594, 7, vd); + setArg(call_fp_vector_vector_op_3594, 8, vs2); + setArg(call_fp_vector_vector_op_3594, 9, vs1); + setArg(call_fp_vector_vector_op_3594, 10, fp_vector_vector_op_3594_arg10); + setArg(call_fp_vector_vector_op_3594, 11, fp_vector_vector_op_3594_arg11); } cc.bind(label_merge); } - auto tmp3580 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3580, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3580, 32, false) - , traits::vstart); + auto tmp3596 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3596, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3596, traits::vstart); } cc.bind(label_merge); } @@ -81485,30 +80971,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3581; - x86::Gp ret_val_get_sew_pow_3581 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3581, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3582 = get_reg(cc, 8, false); - mov(cc, tmp3582, 1); + InvokeNode* call_get_sew_pow_3597; + x86::Gp ret_val_get_sew_pow_3597 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3597, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3598 = get_reg(cc, 8, false); + mov(cc, tmp3598, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3582, (ret_val_get_sew_pow_3581))), 8, false), ~ 1); - setArg(call_get_sew_pow_3581, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3581, 0, ret_val_get_sew_pow_3581); + (gen_operation(cc, shl, tmp3598, (ret_val_get_sew_pow_3597))), 8, false), ~ 1); + setArg(call_get_sew_pow_3597, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3597, 0, ret_val_get_sew_pow_3597); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3583; - auto illegal_fp_normal_3583_arg2 = SEW; - auto illegal_fp_normal_3583_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3583 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3583, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3583; - setArg(call_illegal_fp_normal_3583, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3583, 1, vd); - setArg(call_illegal_fp_normal_3583, 2, vm); - setArg(call_illegal_fp_normal_3583, 3, illegal_fp_normal_3583_arg2); - setArg(call_illegal_fp_normal_3583, 4, illegal_fp_normal_3583_arg3); - setRet(call_illegal_fp_normal_3583, 0, ret_val_illegal_fp_normal_3583); + InvokeNode* call_illegal_fp_normal_3599; + auto illegal_fp_normal_3599_arg2 = SEW; + auto illegal_fp_normal_3599_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3599 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3599, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3599; + setArg(call_illegal_fp_normal_3599, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3599, 1, vd); + setArg(call_illegal_fp_normal_3599, 2, vm); + setArg(call_illegal_fp_normal_3599, 3, illegal_fp_normal_3599_arg2); + setArg(call_illegal_fp_normal_3599, 4, illegal_fp_normal_3599_arg3); + setRet(call_illegal_fp_normal_3599, 0, ret_val_illegal_fp_normal_3599); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81524,41 +81010,39 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3585; - x86::Gp ret_val_sew_3585 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3585, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3584; - auto fp_vector_imm_op_3584_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3584_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3584_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3584_arg9 = gen_ext(cc, + InvokeNode* call_sew_3601; + x86::Gp ret_val_sew_3601 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3601, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3600; + auto fp_vector_imm_op_3600_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3600_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3600_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3600_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto fp_vector_imm_op_3584_arg10 = rm; - auto fp_vector_imm_op_3584_arg11 = ret_val_sew_3585; + auto fp_vector_imm_op_3600_arg10 = rm; + auto fp_vector_imm_op_3600_arg11 = ret_val_sew_3601; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3584, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3585, 0, reinterpret_cast(this)); - setRet(call_sew_3585, 0, ret_val_sew_3585); - setArg(call_fp_vector_imm_op_3584, 0, V); - setArg(call_fp_vector_imm_op_3584, 1, 10); - setArg(call_fp_vector_imm_op_3584, 2, 5); - setArg(call_fp_vector_imm_op_3584, 3, fp_vector_imm_op_3584_arg3); - setArg(call_fp_vector_imm_op_3584, 4, fp_vector_imm_op_3584_arg4); - setArg(call_fp_vector_imm_op_3584, 5, fp_vector_imm_op_3584_arg5); - setArg(call_fp_vector_imm_op_3584, 6, vm); - setArg(call_fp_vector_imm_op_3584, 7, vd); - setArg(call_fp_vector_imm_op_3584, 8, vs2); - setArg(call_fp_vector_imm_op_3584, 9, fp_vector_imm_op_3584_arg9); - setArg(call_fp_vector_imm_op_3584, 10, fp_vector_imm_op_3584_arg10); - setArg(call_fp_vector_imm_op_3584, 11, fp_vector_imm_op_3584_arg11); + cc.invoke(&call_fp_vector_imm_op_3600, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3601, 0, reinterpret_cast(this)); + setRet(call_sew_3601, 0, ret_val_sew_3601); + setArg(call_fp_vector_imm_op_3600, 0, V); + setArg(call_fp_vector_imm_op_3600, 1, 10); + setArg(call_fp_vector_imm_op_3600, 2, 5); + setArg(call_fp_vector_imm_op_3600, 3, fp_vector_imm_op_3600_arg3); + setArg(call_fp_vector_imm_op_3600, 4, fp_vector_imm_op_3600_arg4); + setArg(call_fp_vector_imm_op_3600, 5, fp_vector_imm_op_3600_arg5); + setArg(call_fp_vector_imm_op_3600, 6, vm); + setArg(call_fp_vector_imm_op_3600, 7, vd); + setArg(call_fp_vector_imm_op_3600, 8, vs2); + setArg(call_fp_vector_imm_op_3600, 9, fp_vector_imm_op_3600_arg9); + setArg(call_fp_vector_imm_op_3600, 10, fp_vector_imm_op_3600_arg10); + setArg(call_fp_vector_imm_op_3600, 11, fp_vector_imm_op_3600_arg11); } cc.bind(label_merge); } - auto tmp3586 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3586, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3586, 32, false) - , traits::vstart); + auto tmp3602 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3602, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3602, traits::vstart); } cc.bind(label_merge); } @@ -81602,30 +81086,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3587; - x86::Gp ret_val_get_sew_pow_3587 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3587, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3588 = get_reg(cc, 8, false); - mov(cc, tmp3588, 1); + InvokeNode* call_get_sew_pow_3603; + x86::Gp ret_val_get_sew_pow_3603 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3603, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3604 = get_reg(cc, 8, false); + mov(cc, tmp3604, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3588, (ret_val_get_sew_pow_3587))), 8, false), ~ 1); - setArg(call_get_sew_pow_3587, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3587, 0, ret_val_get_sew_pow_3587); + (gen_operation(cc, shl, tmp3604, (ret_val_get_sew_pow_3603))), 8, false), ~ 1); + setArg(call_get_sew_pow_3603, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3603, 0, ret_val_get_sew_pow_3603); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3589; - auto illegal_fp_normal_3589_arg2 = SEW; - auto illegal_fp_normal_3589_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3589 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3589, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3589; - setArg(call_illegal_fp_normal_3589, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3589, 1, vd); - setArg(call_illegal_fp_normal_3589, 2, vm); - setArg(call_illegal_fp_normal_3589, 3, illegal_fp_normal_3589_arg2); - setArg(call_illegal_fp_normal_3589, 4, illegal_fp_normal_3589_arg3); - setRet(call_illegal_fp_normal_3589, 0, ret_val_illegal_fp_normal_3589); + InvokeNode* call_illegal_fp_normal_3605; + auto illegal_fp_normal_3605_arg2 = SEW; + auto illegal_fp_normal_3605_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3605 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3605, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3605; + setArg(call_illegal_fp_normal_3605, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3605, 1, vd); + setArg(call_illegal_fp_normal_3605, 2, vm); + setArg(call_illegal_fp_normal_3605, 3, illegal_fp_normal_3605_arg2); + setArg(call_illegal_fp_normal_3605, 4, illegal_fp_normal_3605_arg3); + setRet(call_illegal_fp_normal_3605, 0, ret_val_illegal_fp_normal_3605); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81641,39 +81125,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3591; - x86::Gp ret_val_sew_3591 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3591, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3590; - auto fp_vector_vector_op_3590_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3590_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3590_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3590_arg10 = rm; - auto fp_vector_vector_op_3590_arg11 = ret_val_sew_3591; + InvokeNode* call_sew_3607; + x86::Gp ret_val_sew_3607 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3607, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3606; + auto fp_vector_vector_op_3606_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3606_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3606_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3606_arg10 = rm; + auto fp_vector_vector_op_3606_arg11 = ret_val_sew_3607; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3590, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3591, 0, reinterpret_cast(this)); - setRet(call_sew_3591, 0, ret_val_sew_3591); - setArg(call_fp_vector_vector_op_3590, 0, V); - setArg(call_fp_vector_vector_op_3590, 1, 10); - setArg(call_fp_vector_vector_op_3590, 2, 1); - setArg(call_fp_vector_vector_op_3590, 3, fp_vector_vector_op_3590_arg3); - setArg(call_fp_vector_vector_op_3590, 4, fp_vector_vector_op_3590_arg4); - setArg(call_fp_vector_vector_op_3590, 5, fp_vector_vector_op_3590_arg5); - setArg(call_fp_vector_vector_op_3590, 6, vm); - setArg(call_fp_vector_vector_op_3590, 7, vd); - setArg(call_fp_vector_vector_op_3590, 8, vs2); - setArg(call_fp_vector_vector_op_3590, 9, vs1); - setArg(call_fp_vector_vector_op_3590, 10, fp_vector_vector_op_3590_arg10); - setArg(call_fp_vector_vector_op_3590, 11, fp_vector_vector_op_3590_arg11); + cc.invoke(&call_fp_vector_vector_op_3606, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3607, 0, reinterpret_cast(this)); + setRet(call_sew_3607, 0, ret_val_sew_3607); + setArg(call_fp_vector_vector_op_3606, 0, V); + setArg(call_fp_vector_vector_op_3606, 1, 10); + setArg(call_fp_vector_vector_op_3606, 2, 1); + setArg(call_fp_vector_vector_op_3606, 3, fp_vector_vector_op_3606_arg3); + setArg(call_fp_vector_vector_op_3606, 4, fp_vector_vector_op_3606_arg4); + setArg(call_fp_vector_vector_op_3606, 5, fp_vector_vector_op_3606_arg5); + setArg(call_fp_vector_vector_op_3606, 6, vm); + setArg(call_fp_vector_vector_op_3606, 7, vd); + setArg(call_fp_vector_vector_op_3606, 8, vs2); + setArg(call_fp_vector_vector_op_3606, 9, vs1); + setArg(call_fp_vector_vector_op_3606, 10, fp_vector_vector_op_3606_arg10); + setArg(call_fp_vector_vector_op_3606, 11, fp_vector_vector_op_3606_arg11); } cc.bind(label_merge); } - auto tmp3592 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3592, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3592, 32, false) - , traits::vstart); + auto tmp3608 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3608, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3608, traits::vstart); } cc.bind(label_merge); } @@ -81717,28 +81199,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3593; - x86::Gp ret_val_get_sew_pow_3593 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3593, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3594 = get_reg(cc, 8, false); - mov(cc, tmp3594, 1); + InvokeNode* call_get_sew_pow_3609; + x86::Gp ret_val_get_sew_pow_3609 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3609, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3610 = get_reg(cc, 8, false); + mov(cc, tmp3610, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3594, (ret_val_get_sew_pow_3593))), 8, false), ~ 1); - setArg(call_get_sew_pow_3593, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3593, 0, ret_val_get_sew_pow_3593); + (gen_operation(cc, shl, tmp3610, (ret_val_get_sew_pow_3609))), 8, false), ~ 1); + setArg(call_get_sew_pow_3609, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3609, 0, ret_val_get_sew_pow_3609); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3595; - auto illegal_fp_vd_unmasked_3595_arg0 = SEW; - auto illegal_fp_vd_unmasked_3595_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3595 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3595, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3595; - setArg(call_illegal_fp_vd_unmasked_3595, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3595, 1, illegal_fp_vd_unmasked_3595_arg0); - setArg(call_illegal_fp_vd_unmasked_3595, 2, illegal_fp_vd_unmasked_3595_arg1); - setRet(call_illegal_fp_vd_unmasked_3595, 0, ret_val_illegal_fp_vd_unmasked_3595); + InvokeNode* call_illegal_fp_vd_unmasked_3611; + auto illegal_fp_vd_unmasked_3611_arg0 = SEW; + auto illegal_fp_vd_unmasked_3611_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3611 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3611, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3611; + setArg(call_illegal_fp_vd_unmasked_3611, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3611, 1, illegal_fp_vd_unmasked_3611_arg0); + setArg(call_illegal_fp_vd_unmasked_3611, 2, illegal_fp_vd_unmasked_3611_arg1); + setRet(call_illegal_fp_vd_unmasked_3611, 0, ret_val_illegal_fp_vd_unmasked_3611); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81754,46 +81236,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3597; - x86::Gp ret_val_sew_3597 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3597, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3596; - auto mask_fp_vector_imm_op_3596_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3596_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3596_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3596_arg8 = gen_ext(cc, + InvokeNode* call_sew_3613; + x86::Gp ret_val_sew_3613 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3613, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3612; + auto mask_fp_vector_imm_op_3612_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3612_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3612_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3612_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto mask_fp_vector_imm_op_3596_arg9 = rm; - auto mask_fp_vector_imm_op_3596_arg10 = ret_val_sew_3597; + auto mask_fp_vector_imm_op_3612_arg9 = rm; + auto mask_fp_vector_imm_op_3612_arg10 = ret_val_sew_3613; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3596, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3597, 0, reinterpret_cast(this)); - setRet(call_sew_3597, 0, ret_val_sew_3597); - setArg(call_mask_fp_vector_imm_op_3596, 0, V); - setArg(call_mask_fp_vector_imm_op_3596, 1, 24); - setArg(call_mask_fp_vector_imm_op_3596, 2, mask_fp_vector_imm_op_3596_arg2); - setArg(call_mask_fp_vector_imm_op_3596, 3, mask_fp_vector_imm_op_3596_arg3); - setArg(call_mask_fp_vector_imm_op_3596, 4, mask_fp_vector_imm_op_3596_arg4); - setArg(call_mask_fp_vector_imm_op_3596, 5, vm); - setArg(call_mask_fp_vector_imm_op_3596, 6, vd); - setArg(call_mask_fp_vector_imm_op_3596, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3596, 8, mask_fp_vector_imm_op_3596_arg8); - setArg(call_mask_fp_vector_imm_op_3596, 9, mask_fp_vector_imm_op_3596_arg9); - setArg(call_mask_fp_vector_imm_op_3596, 10, mask_fp_vector_imm_op_3596_arg10); - InvokeNode* call_fget_flags_3598; - x86::Gp ret_val_fget_flags_3598 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3598, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3598; - setRet(call_fget_flags_3598, 0, ret_val_fget_flags_3598); + cc.invoke(&call_mask_fp_vector_imm_op_3612, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3613, 0, reinterpret_cast(this)); + setRet(call_sew_3613, 0, ret_val_sew_3613); + setArg(call_mask_fp_vector_imm_op_3612, 0, V); + setArg(call_mask_fp_vector_imm_op_3612, 1, 24); + setArg(call_mask_fp_vector_imm_op_3612, 2, mask_fp_vector_imm_op_3612_arg2); + setArg(call_mask_fp_vector_imm_op_3612, 3, mask_fp_vector_imm_op_3612_arg3); + setArg(call_mask_fp_vector_imm_op_3612, 4, mask_fp_vector_imm_op_3612_arg4); + setArg(call_mask_fp_vector_imm_op_3612, 5, vm); + setArg(call_mask_fp_vector_imm_op_3612, 6, vd); + setArg(call_mask_fp_vector_imm_op_3612, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3612, 8, mask_fp_vector_imm_op_3612_arg8); + setArg(call_mask_fp_vector_imm_op_3612, 9, mask_fp_vector_imm_op_3612_arg9); + setArg(call_mask_fp_vector_imm_op_3612, 10, mask_fp_vector_imm_op_3612_arg10); + InvokeNode* call_fget_flags_3614; + x86::Gp ret_val_fget_flags_3614 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3614, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3614; + setRet(call_fget_flags_3614, 0, ret_val_fget_flags_3614); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3599 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3599, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3599, 32, false) - , traits::vstart); + auto tmp3615 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3615, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3615, traits::vstart); } cc.bind(label_merge); } @@ -81837,28 +81317,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3600; - x86::Gp ret_val_get_sew_pow_3600 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3600, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3601 = get_reg(cc, 8, false); - mov(cc, tmp3601, 1); + InvokeNode* call_get_sew_pow_3616; + x86::Gp ret_val_get_sew_pow_3616 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3616, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3617 = get_reg(cc, 8, false); + mov(cc, tmp3617, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3601, (ret_val_get_sew_pow_3600))), 8, false), ~ 1); - setArg(call_get_sew_pow_3600, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3600, 0, ret_val_get_sew_pow_3600); + (gen_operation(cc, shl, tmp3617, (ret_val_get_sew_pow_3616))), 8, false), ~ 1); + setArg(call_get_sew_pow_3616, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3616, 0, ret_val_get_sew_pow_3616); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3602; - auto illegal_fp_vd_unmasked_3602_arg0 = SEW; - auto illegal_fp_vd_unmasked_3602_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3602 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3602, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3602; - setArg(call_illegal_fp_vd_unmasked_3602, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3602, 1, illegal_fp_vd_unmasked_3602_arg0); - setArg(call_illegal_fp_vd_unmasked_3602, 2, illegal_fp_vd_unmasked_3602_arg1); - setRet(call_illegal_fp_vd_unmasked_3602, 0, ret_val_illegal_fp_vd_unmasked_3602); + InvokeNode* call_illegal_fp_vd_unmasked_3618; + auto illegal_fp_vd_unmasked_3618_arg0 = SEW; + auto illegal_fp_vd_unmasked_3618_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3618 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3618, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3618; + setArg(call_illegal_fp_vd_unmasked_3618, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3618, 1, illegal_fp_vd_unmasked_3618_arg0); + setArg(call_illegal_fp_vd_unmasked_3618, 2, illegal_fp_vd_unmasked_3618_arg1); + setRet(call_illegal_fp_vd_unmasked_3618, 0, ret_val_illegal_fp_vd_unmasked_3618); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81874,44 +81354,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3604; - x86::Gp ret_val_sew_3604 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3604, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_vector_op_3603; - auto mask_fp_vector_vector_op_3603_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_vector_op_3603_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_vector_op_3603_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_vector_op_3603_arg9 = rm; - auto mask_fp_vector_vector_op_3603_arg10 = ret_val_sew_3604; + InvokeNode* call_sew_3620; + x86::Gp ret_val_sew_3620 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3620, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3619; + auto mask_fp_vector_vector_op_3619_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3619_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3619_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3619_arg9 = rm; + auto mask_fp_vector_vector_op_3619_arg10 = ret_val_sew_3620; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_vector_op_3603, &mask_fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3604, 0, reinterpret_cast(this)); - setRet(call_sew_3604, 0, ret_val_sew_3604); - setArg(call_mask_fp_vector_vector_op_3603, 0, V); - setArg(call_mask_fp_vector_vector_op_3603, 1, 24); - setArg(call_mask_fp_vector_vector_op_3603, 2, mask_fp_vector_vector_op_3603_arg2); - setArg(call_mask_fp_vector_vector_op_3603, 3, mask_fp_vector_vector_op_3603_arg3); - setArg(call_mask_fp_vector_vector_op_3603, 4, mask_fp_vector_vector_op_3603_arg4); - setArg(call_mask_fp_vector_vector_op_3603, 5, vm); - setArg(call_mask_fp_vector_vector_op_3603, 6, vd); - setArg(call_mask_fp_vector_vector_op_3603, 7, vs2); - setArg(call_mask_fp_vector_vector_op_3603, 8, vs1); - setArg(call_mask_fp_vector_vector_op_3603, 9, mask_fp_vector_vector_op_3603_arg9); - setArg(call_mask_fp_vector_vector_op_3603, 10, mask_fp_vector_vector_op_3603_arg10); - InvokeNode* call_fget_flags_3605; - x86::Gp ret_val_fget_flags_3605 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3605, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3605; - setRet(call_fget_flags_3605, 0, ret_val_fget_flags_3605); + cc.invoke(&call_mask_fp_vector_vector_op_3619, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3620, 0, reinterpret_cast(this)); + setRet(call_sew_3620, 0, ret_val_sew_3620); + setArg(call_mask_fp_vector_vector_op_3619, 0, V); + setArg(call_mask_fp_vector_vector_op_3619, 1, 24); + setArg(call_mask_fp_vector_vector_op_3619, 2, mask_fp_vector_vector_op_3619_arg2); + setArg(call_mask_fp_vector_vector_op_3619, 3, mask_fp_vector_vector_op_3619_arg3); + setArg(call_mask_fp_vector_vector_op_3619, 4, mask_fp_vector_vector_op_3619_arg4); + setArg(call_mask_fp_vector_vector_op_3619, 5, vm); + setArg(call_mask_fp_vector_vector_op_3619, 6, vd); + setArg(call_mask_fp_vector_vector_op_3619, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3619, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3619, 9, mask_fp_vector_vector_op_3619_arg9); + setArg(call_mask_fp_vector_vector_op_3619, 10, mask_fp_vector_vector_op_3619_arg10); + InvokeNode* call_fget_flags_3621; + x86::Gp ret_val_fget_flags_3621 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3621, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3621; + setRet(call_fget_flags_3621, 0, ret_val_fget_flags_3621); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3606 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3606, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3606, 32, false) - , traits::vstart); + auto tmp3622 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3622, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3622, traits::vstart); } cc.bind(label_merge); } @@ -81955,28 +81433,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3607; - x86::Gp ret_val_get_sew_pow_3607 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3607, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3608 = get_reg(cc, 8, false); - mov(cc, tmp3608, 1); + InvokeNode* call_get_sew_pow_3623; + x86::Gp ret_val_get_sew_pow_3623 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3623, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3624 = get_reg(cc, 8, false); + mov(cc, tmp3624, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3608, (ret_val_get_sew_pow_3607))), 8, false), ~ 1); - setArg(call_get_sew_pow_3607, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3607, 0, ret_val_get_sew_pow_3607); + (gen_operation(cc, shl, tmp3624, (ret_val_get_sew_pow_3623))), 8, false), ~ 1); + setArg(call_get_sew_pow_3623, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3623, 0, ret_val_get_sew_pow_3623); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3609; - auto illegal_fp_vd_unmasked_3609_arg0 = SEW; - auto illegal_fp_vd_unmasked_3609_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3609 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3609, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3609; - setArg(call_illegal_fp_vd_unmasked_3609, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3609, 1, illegal_fp_vd_unmasked_3609_arg0); - setArg(call_illegal_fp_vd_unmasked_3609, 2, illegal_fp_vd_unmasked_3609_arg1); - setRet(call_illegal_fp_vd_unmasked_3609, 0, ret_val_illegal_fp_vd_unmasked_3609); + InvokeNode* call_illegal_fp_vd_unmasked_3625; + auto illegal_fp_vd_unmasked_3625_arg0 = SEW; + auto illegal_fp_vd_unmasked_3625_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3625 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3625, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3625; + setArg(call_illegal_fp_vd_unmasked_3625, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3625, 1, illegal_fp_vd_unmasked_3625_arg0); + setArg(call_illegal_fp_vd_unmasked_3625, 2, illegal_fp_vd_unmasked_3625_arg1); + setRet(call_illegal_fp_vd_unmasked_3625, 0, ret_val_illegal_fp_vd_unmasked_3625); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81992,46 +81470,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3611; - x86::Gp ret_val_sew_3611 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3611, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3610; - auto mask_fp_vector_imm_op_3610_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3610_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3610_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3610_arg8 = gen_ext(cc, + InvokeNode* call_sew_3627; + x86::Gp ret_val_sew_3627 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3627, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3626; + auto mask_fp_vector_imm_op_3626_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3626_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3626_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3626_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto mask_fp_vector_imm_op_3610_arg9 = rm; - auto mask_fp_vector_imm_op_3610_arg10 = ret_val_sew_3611; + auto mask_fp_vector_imm_op_3626_arg9 = rm; + auto mask_fp_vector_imm_op_3626_arg10 = ret_val_sew_3627; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3610, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3611, 0, reinterpret_cast(this)); - setRet(call_sew_3611, 0, ret_val_sew_3611); - setArg(call_mask_fp_vector_imm_op_3610, 0, V); - setArg(call_mask_fp_vector_imm_op_3610, 1, 28); - setArg(call_mask_fp_vector_imm_op_3610, 2, mask_fp_vector_imm_op_3610_arg2); - setArg(call_mask_fp_vector_imm_op_3610, 3, mask_fp_vector_imm_op_3610_arg3); - setArg(call_mask_fp_vector_imm_op_3610, 4, mask_fp_vector_imm_op_3610_arg4); - setArg(call_mask_fp_vector_imm_op_3610, 5, vm); - setArg(call_mask_fp_vector_imm_op_3610, 6, vd); - setArg(call_mask_fp_vector_imm_op_3610, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3610, 8, mask_fp_vector_imm_op_3610_arg8); - setArg(call_mask_fp_vector_imm_op_3610, 9, mask_fp_vector_imm_op_3610_arg9); - setArg(call_mask_fp_vector_imm_op_3610, 10, mask_fp_vector_imm_op_3610_arg10); - InvokeNode* call_fget_flags_3612; - x86::Gp ret_val_fget_flags_3612 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3612, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3612; - setRet(call_fget_flags_3612, 0, ret_val_fget_flags_3612); + cc.invoke(&call_mask_fp_vector_imm_op_3626, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3627, 0, reinterpret_cast(this)); + setRet(call_sew_3627, 0, ret_val_sew_3627); + setArg(call_mask_fp_vector_imm_op_3626, 0, V); + setArg(call_mask_fp_vector_imm_op_3626, 1, 28); + setArg(call_mask_fp_vector_imm_op_3626, 2, mask_fp_vector_imm_op_3626_arg2); + setArg(call_mask_fp_vector_imm_op_3626, 3, mask_fp_vector_imm_op_3626_arg3); + setArg(call_mask_fp_vector_imm_op_3626, 4, mask_fp_vector_imm_op_3626_arg4); + setArg(call_mask_fp_vector_imm_op_3626, 5, vm); + setArg(call_mask_fp_vector_imm_op_3626, 6, vd); + setArg(call_mask_fp_vector_imm_op_3626, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3626, 8, mask_fp_vector_imm_op_3626_arg8); + setArg(call_mask_fp_vector_imm_op_3626, 9, mask_fp_vector_imm_op_3626_arg9); + setArg(call_mask_fp_vector_imm_op_3626, 10, mask_fp_vector_imm_op_3626_arg10); + InvokeNode* call_fget_flags_3628; + x86::Gp ret_val_fget_flags_3628 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3628, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3628; + setRet(call_fget_flags_3628, 0, ret_val_fget_flags_3628); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3613 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3613, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3613, 32, false) - , traits::vstart); + auto tmp3629 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3629, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3629, traits::vstart); } cc.bind(label_merge); } @@ -82075,28 +81551,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3614; - x86::Gp ret_val_get_sew_pow_3614 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3614, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3615 = get_reg(cc, 8, false); - mov(cc, tmp3615, 1); + InvokeNode* call_get_sew_pow_3630; + x86::Gp ret_val_get_sew_pow_3630 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3630, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3631 = get_reg(cc, 8, false); + mov(cc, tmp3631, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3615, (ret_val_get_sew_pow_3614))), 8, false), ~ 1); - setArg(call_get_sew_pow_3614, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3614, 0, ret_val_get_sew_pow_3614); + (gen_operation(cc, shl, tmp3631, (ret_val_get_sew_pow_3630))), 8, false), ~ 1); + setArg(call_get_sew_pow_3630, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3630, 0, ret_val_get_sew_pow_3630); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3616; - auto illegal_fp_vd_unmasked_3616_arg0 = SEW; - auto illegal_fp_vd_unmasked_3616_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3616 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3616, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3616; - setArg(call_illegal_fp_vd_unmasked_3616, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3616, 1, illegal_fp_vd_unmasked_3616_arg0); - setArg(call_illegal_fp_vd_unmasked_3616, 2, illegal_fp_vd_unmasked_3616_arg1); - setRet(call_illegal_fp_vd_unmasked_3616, 0, ret_val_illegal_fp_vd_unmasked_3616); + InvokeNode* call_illegal_fp_vd_unmasked_3632; + auto illegal_fp_vd_unmasked_3632_arg0 = SEW; + auto illegal_fp_vd_unmasked_3632_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3632 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3632, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3632; + setArg(call_illegal_fp_vd_unmasked_3632, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3632, 1, illegal_fp_vd_unmasked_3632_arg0); + setArg(call_illegal_fp_vd_unmasked_3632, 2, illegal_fp_vd_unmasked_3632_arg1); + setRet(call_illegal_fp_vd_unmasked_3632, 0, ret_val_illegal_fp_vd_unmasked_3632); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82112,44 +81588,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3618; - x86::Gp ret_val_sew_3618 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3618, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_vector_op_3617; - auto mask_fp_vector_vector_op_3617_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_vector_op_3617_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_vector_op_3617_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_vector_op_3617_arg9 = rm; - auto mask_fp_vector_vector_op_3617_arg10 = ret_val_sew_3618; + InvokeNode* call_sew_3634; + x86::Gp ret_val_sew_3634 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3634, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3633; + auto mask_fp_vector_vector_op_3633_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3633_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3633_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3633_arg9 = rm; + auto mask_fp_vector_vector_op_3633_arg10 = ret_val_sew_3634; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_vector_op_3617, &mask_fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3618, 0, reinterpret_cast(this)); - setRet(call_sew_3618, 0, ret_val_sew_3618); - setArg(call_mask_fp_vector_vector_op_3617, 0, V); - setArg(call_mask_fp_vector_vector_op_3617, 1, 28); - setArg(call_mask_fp_vector_vector_op_3617, 2, mask_fp_vector_vector_op_3617_arg2); - setArg(call_mask_fp_vector_vector_op_3617, 3, mask_fp_vector_vector_op_3617_arg3); - setArg(call_mask_fp_vector_vector_op_3617, 4, mask_fp_vector_vector_op_3617_arg4); - setArg(call_mask_fp_vector_vector_op_3617, 5, vm); - setArg(call_mask_fp_vector_vector_op_3617, 6, vd); - setArg(call_mask_fp_vector_vector_op_3617, 7, vs2); - setArg(call_mask_fp_vector_vector_op_3617, 8, vs1); - setArg(call_mask_fp_vector_vector_op_3617, 9, mask_fp_vector_vector_op_3617_arg9); - setArg(call_mask_fp_vector_vector_op_3617, 10, mask_fp_vector_vector_op_3617_arg10); - InvokeNode* call_fget_flags_3619; - x86::Gp ret_val_fget_flags_3619 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3619, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3619; - setRet(call_fget_flags_3619, 0, ret_val_fget_flags_3619); + cc.invoke(&call_mask_fp_vector_vector_op_3633, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3634, 0, reinterpret_cast(this)); + setRet(call_sew_3634, 0, ret_val_sew_3634); + setArg(call_mask_fp_vector_vector_op_3633, 0, V); + setArg(call_mask_fp_vector_vector_op_3633, 1, 28); + setArg(call_mask_fp_vector_vector_op_3633, 2, mask_fp_vector_vector_op_3633_arg2); + setArg(call_mask_fp_vector_vector_op_3633, 3, mask_fp_vector_vector_op_3633_arg3); + setArg(call_mask_fp_vector_vector_op_3633, 4, mask_fp_vector_vector_op_3633_arg4); + setArg(call_mask_fp_vector_vector_op_3633, 5, vm); + setArg(call_mask_fp_vector_vector_op_3633, 6, vd); + setArg(call_mask_fp_vector_vector_op_3633, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3633, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3633, 9, mask_fp_vector_vector_op_3633_arg9); + setArg(call_mask_fp_vector_vector_op_3633, 10, mask_fp_vector_vector_op_3633_arg10); + InvokeNode* call_fget_flags_3635; + x86::Gp ret_val_fget_flags_3635 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3635, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3635; + setRet(call_fget_flags_3635, 0, ret_val_fget_flags_3635); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3620 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3620, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3620, 32, false) - , traits::vstart); + auto tmp3636 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3636, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3636, traits::vstart); } cc.bind(label_merge); } @@ -82193,28 +81667,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3621; - x86::Gp ret_val_get_sew_pow_3621 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3621, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3622 = get_reg(cc, 8, false); - mov(cc, tmp3622, 1); + InvokeNode* call_get_sew_pow_3637; + x86::Gp ret_val_get_sew_pow_3637 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3637, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3638 = get_reg(cc, 8, false); + mov(cc, tmp3638, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3622, (ret_val_get_sew_pow_3621))), 8, false), ~ 1); - setArg(call_get_sew_pow_3621, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3621, 0, ret_val_get_sew_pow_3621); + (gen_operation(cc, shl, tmp3638, (ret_val_get_sew_pow_3637))), 8, false), ~ 1); + setArg(call_get_sew_pow_3637, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3637, 0, ret_val_get_sew_pow_3637); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3623; - auto illegal_fp_vd_unmasked_3623_arg0 = SEW; - auto illegal_fp_vd_unmasked_3623_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3623 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3623, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3623; - setArg(call_illegal_fp_vd_unmasked_3623, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3623, 1, illegal_fp_vd_unmasked_3623_arg0); - setArg(call_illegal_fp_vd_unmasked_3623, 2, illegal_fp_vd_unmasked_3623_arg1); - setRet(call_illegal_fp_vd_unmasked_3623, 0, ret_val_illegal_fp_vd_unmasked_3623); + InvokeNode* call_illegal_fp_vd_unmasked_3639; + auto illegal_fp_vd_unmasked_3639_arg0 = SEW; + auto illegal_fp_vd_unmasked_3639_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3639 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3639, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3639; + setArg(call_illegal_fp_vd_unmasked_3639, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3639, 1, illegal_fp_vd_unmasked_3639_arg0); + setArg(call_illegal_fp_vd_unmasked_3639, 2, illegal_fp_vd_unmasked_3639_arg1); + setRet(call_illegal_fp_vd_unmasked_3639, 0, ret_val_illegal_fp_vd_unmasked_3639); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82230,46 +81704,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3625; - x86::Gp ret_val_sew_3625 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3625, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3624; - auto mask_fp_vector_imm_op_3624_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3624_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3624_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3624_arg8 = gen_ext(cc, + InvokeNode* call_sew_3641; + x86::Gp ret_val_sew_3641 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3641, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3640; + auto mask_fp_vector_imm_op_3640_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3640_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3640_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3640_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto mask_fp_vector_imm_op_3624_arg9 = rm; - auto mask_fp_vector_imm_op_3624_arg10 = ret_val_sew_3625; + auto mask_fp_vector_imm_op_3640_arg9 = rm; + auto mask_fp_vector_imm_op_3640_arg10 = ret_val_sew_3641; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3624, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3625, 0, reinterpret_cast(this)); - setRet(call_sew_3625, 0, ret_val_sew_3625); - setArg(call_mask_fp_vector_imm_op_3624, 0, V); - setArg(call_mask_fp_vector_imm_op_3624, 1, 27); - setArg(call_mask_fp_vector_imm_op_3624, 2, mask_fp_vector_imm_op_3624_arg2); - setArg(call_mask_fp_vector_imm_op_3624, 3, mask_fp_vector_imm_op_3624_arg3); - setArg(call_mask_fp_vector_imm_op_3624, 4, mask_fp_vector_imm_op_3624_arg4); - setArg(call_mask_fp_vector_imm_op_3624, 5, vm); - setArg(call_mask_fp_vector_imm_op_3624, 6, vd); - setArg(call_mask_fp_vector_imm_op_3624, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3624, 8, mask_fp_vector_imm_op_3624_arg8); - setArg(call_mask_fp_vector_imm_op_3624, 9, mask_fp_vector_imm_op_3624_arg9); - setArg(call_mask_fp_vector_imm_op_3624, 10, mask_fp_vector_imm_op_3624_arg10); - InvokeNode* call_fget_flags_3626; - x86::Gp ret_val_fget_flags_3626 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3626, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3626; - setRet(call_fget_flags_3626, 0, ret_val_fget_flags_3626); + cc.invoke(&call_mask_fp_vector_imm_op_3640, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3641, 0, reinterpret_cast(this)); + setRet(call_sew_3641, 0, ret_val_sew_3641); + setArg(call_mask_fp_vector_imm_op_3640, 0, V); + setArg(call_mask_fp_vector_imm_op_3640, 1, 27); + setArg(call_mask_fp_vector_imm_op_3640, 2, mask_fp_vector_imm_op_3640_arg2); + setArg(call_mask_fp_vector_imm_op_3640, 3, mask_fp_vector_imm_op_3640_arg3); + setArg(call_mask_fp_vector_imm_op_3640, 4, mask_fp_vector_imm_op_3640_arg4); + setArg(call_mask_fp_vector_imm_op_3640, 5, vm); + setArg(call_mask_fp_vector_imm_op_3640, 6, vd); + setArg(call_mask_fp_vector_imm_op_3640, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3640, 8, mask_fp_vector_imm_op_3640_arg8); + setArg(call_mask_fp_vector_imm_op_3640, 9, mask_fp_vector_imm_op_3640_arg9); + setArg(call_mask_fp_vector_imm_op_3640, 10, mask_fp_vector_imm_op_3640_arg10); + InvokeNode* call_fget_flags_3642; + x86::Gp ret_val_fget_flags_3642 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3642, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3642; + setRet(call_fget_flags_3642, 0, ret_val_fget_flags_3642); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3627 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3627, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3627, 32, false) - , traits::vstart); + auto tmp3643 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3643, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3643, traits::vstart); } cc.bind(label_merge); } @@ -82313,28 +81785,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3628; - x86::Gp ret_val_get_sew_pow_3628 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3628, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3629 = get_reg(cc, 8, false); - mov(cc, tmp3629, 1); + InvokeNode* call_get_sew_pow_3644; + x86::Gp ret_val_get_sew_pow_3644 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3644, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3645 = get_reg(cc, 8, false); + mov(cc, tmp3645, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3629, (ret_val_get_sew_pow_3628))), 8, false), ~ 1); - setArg(call_get_sew_pow_3628, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3628, 0, ret_val_get_sew_pow_3628); + (gen_operation(cc, shl, tmp3645, (ret_val_get_sew_pow_3644))), 8, false), ~ 1); + setArg(call_get_sew_pow_3644, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3644, 0, ret_val_get_sew_pow_3644); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3630; - auto illegal_fp_vd_unmasked_3630_arg0 = SEW; - auto illegal_fp_vd_unmasked_3630_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3630 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3630, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3630; - setArg(call_illegal_fp_vd_unmasked_3630, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3630, 1, illegal_fp_vd_unmasked_3630_arg0); - setArg(call_illegal_fp_vd_unmasked_3630, 2, illegal_fp_vd_unmasked_3630_arg1); - setRet(call_illegal_fp_vd_unmasked_3630, 0, ret_val_illegal_fp_vd_unmasked_3630); + InvokeNode* call_illegal_fp_vd_unmasked_3646; + auto illegal_fp_vd_unmasked_3646_arg0 = SEW; + auto illegal_fp_vd_unmasked_3646_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3646 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3646, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3646; + setArg(call_illegal_fp_vd_unmasked_3646, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3646, 1, illegal_fp_vd_unmasked_3646_arg0); + setArg(call_illegal_fp_vd_unmasked_3646, 2, illegal_fp_vd_unmasked_3646_arg1); + setRet(call_illegal_fp_vd_unmasked_3646, 0, ret_val_illegal_fp_vd_unmasked_3646); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82350,44 +81822,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3632; - x86::Gp ret_val_sew_3632 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3632, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_vector_op_3631; - auto mask_fp_vector_vector_op_3631_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_vector_op_3631_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_vector_op_3631_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_vector_op_3631_arg9 = rm; - auto mask_fp_vector_vector_op_3631_arg10 = ret_val_sew_3632; + InvokeNode* call_sew_3648; + x86::Gp ret_val_sew_3648 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3648, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3647; + auto mask_fp_vector_vector_op_3647_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3647_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3647_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3647_arg9 = rm; + auto mask_fp_vector_vector_op_3647_arg10 = ret_val_sew_3648; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_vector_op_3631, &mask_fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3632, 0, reinterpret_cast(this)); - setRet(call_sew_3632, 0, ret_val_sew_3632); - setArg(call_mask_fp_vector_vector_op_3631, 0, V); - setArg(call_mask_fp_vector_vector_op_3631, 1, 27); - setArg(call_mask_fp_vector_vector_op_3631, 2, mask_fp_vector_vector_op_3631_arg2); - setArg(call_mask_fp_vector_vector_op_3631, 3, mask_fp_vector_vector_op_3631_arg3); - setArg(call_mask_fp_vector_vector_op_3631, 4, mask_fp_vector_vector_op_3631_arg4); - setArg(call_mask_fp_vector_vector_op_3631, 5, vm); - setArg(call_mask_fp_vector_vector_op_3631, 6, vd); - setArg(call_mask_fp_vector_vector_op_3631, 7, vs2); - setArg(call_mask_fp_vector_vector_op_3631, 8, vs1); - setArg(call_mask_fp_vector_vector_op_3631, 9, mask_fp_vector_vector_op_3631_arg9); - setArg(call_mask_fp_vector_vector_op_3631, 10, mask_fp_vector_vector_op_3631_arg10); - InvokeNode* call_fget_flags_3633; - x86::Gp ret_val_fget_flags_3633 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3633, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3633; - setRet(call_fget_flags_3633, 0, ret_val_fget_flags_3633); + cc.invoke(&call_mask_fp_vector_vector_op_3647, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3648, 0, reinterpret_cast(this)); + setRet(call_sew_3648, 0, ret_val_sew_3648); + setArg(call_mask_fp_vector_vector_op_3647, 0, V); + setArg(call_mask_fp_vector_vector_op_3647, 1, 27); + setArg(call_mask_fp_vector_vector_op_3647, 2, mask_fp_vector_vector_op_3647_arg2); + setArg(call_mask_fp_vector_vector_op_3647, 3, mask_fp_vector_vector_op_3647_arg3); + setArg(call_mask_fp_vector_vector_op_3647, 4, mask_fp_vector_vector_op_3647_arg4); + setArg(call_mask_fp_vector_vector_op_3647, 5, vm); + setArg(call_mask_fp_vector_vector_op_3647, 6, vd); + setArg(call_mask_fp_vector_vector_op_3647, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3647, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3647, 9, mask_fp_vector_vector_op_3647_arg9); + setArg(call_mask_fp_vector_vector_op_3647, 10, mask_fp_vector_vector_op_3647_arg10); + InvokeNode* call_fget_flags_3649; + x86::Gp ret_val_fget_flags_3649 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3649, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3649; + setRet(call_fget_flags_3649, 0, ret_val_fget_flags_3649); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3634 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3634, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3634, 32, false) - , traits::vstart); + auto tmp3650 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3650, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3650, traits::vstart); } cc.bind(label_merge); } @@ -82431,28 +81901,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3635; - x86::Gp ret_val_get_sew_pow_3635 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3635, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3636 = get_reg(cc, 8, false); - mov(cc, tmp3636, 1); + InvokeNode* call_get_sew_pow_3651; + x86::Gp ret_val_get_sew_pow_3651 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3651, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3652 = get_reg(cc, 8, false); + mov(cc, tmp3652, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3636, (ret_val_get_sew_pow_3635))), 8, false), ~ 1); - setArg(call_get_sew_pow_3635, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3635, 0, ret_val_get_sew_pow_3635); + (gen_operation(cc, shl, tmp3652, (ret_val_get_sew_pow_3651))), 8, false), ~ 1); + setArg(call_get_sew_pow_3651, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3651, 0, ret_val_get_sew_pow_3651); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3637; - auto illegal_fp_vd_unmasked_3637_arg0 = SEW; - auto illegal_fp_vd_unmasked_3637_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3637 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3637, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3637; - setArg(call_illegal_fp_vd_unmasked_3637, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3637, 1, illegal_fp_vd_unmasked_3637_arg0); - setArg(call_illegal_fp_vd_unmasked_3637, 2, illegal_fp_vd_unmasked_3637_arg1); - setRet(call_illegal_fp_vd_unmasked_3637, 0, ret_val_illegal_fp_vd_unmasked_3637); + InvokeNode* call_illegal_fp_vd_unmasked_3653; + auto illegal_fp_vd_unmasked_3653_arg0 = SEW; + auto illegal_fp_vd_unmasked_3653_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3653 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3653, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3653; + setArg(call_illegal_fp_vd_unmasked_3653, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3653, 1, illegal_fp_vd_unmasked_3653_arg0); + setArg(call_illegal_fp_vd_unmasked_3653, 2, illegal_fp_vd_unmasked_3653_arg1); + setRet(call_illegal_fp_vd_unmasked_3653, 0, ret_val_illegal_fp_vd_unmasked_3653); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82468,46 +81938,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3639; - x86::Gp ret_val_sew_3639 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3639, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3638; - auto mask_fp_vector_imm_op_3638_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3638_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3638_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3638_arg8 = gen_ext(cc, + InvokeNode* call_sew_3655; + x86::Gp ret_val_sew_3655 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3655, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3654; + auto mask_fp_vector_imm_op_3654_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3654_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3654_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3654_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto mask_fp_vector_imm_op_3638_arg9 = rm; - auto mask_fp_vector_imm_op_3638_arg10 = ret_val_sew_3639; + auto mask_fp_vector_imm_op_3654_arg9 = rm; + auto mask_fp_vector_imm_op_3654_arg10 = ret_val_sew_3655; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3638, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3639, 0, reinterpret_cast(this)); - setRet(call_sew_3639, 0, ret_val_sew_3639); - setArg(call_mask_fp_vector_imm_op_3638, 0, V); - setArg(call_mask_fp_vector_imm_op_3638, 1, 25); - setArg(call_mask_fp_vector_imm_op_3638, 2, mask_fp_vector_imm_op_3638_arg2); - setArg(call_mask_fp_vector_imm_op_3638, 3, mask_fp_vector_imm_op_3638_arg3); - setArg(call_mask_fp_vector_imm_op_3638, 4, mask_fp_vector_imm_op_3638_arg4); - setArg(call_mask_fp_vector_imm_op_3638, 5, vm); - setArg(call_mask_fp_vector_imm_op_3638, 6, vd); - setArg(call_mask_fp_vector_imm_op_3638, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3638, 8, mask_fp_vector_imm_op_3638_arg8); - setArg(call_mask_fp_vector_imm_op_3638, 9, mask_fp_vector_imm_op_3638_arg9); - setArg(call_mask_fp_vector_imm_op_3638, 10, mask_fp_vector_imm_op_3638_arg10); - InvokeNode* call_fget_flags_3640; - x86::Gp ret_val_fget_flags_3640 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3640, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3640; - setRet(call_fget_flags_3640, 0, ret_val_fget_flags_3640); + cc.invoke(&call_mask_fp_vector_imm_op_3654, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3655, 0, reinterpret_cast(this)); + setRet(call_sew_3655, 0, ret_val_sew_3655); + setArg(call_mask_fp_vector_imm_op_3654, 0, V); + setArg(call_mask_fp_vector_imm_op_3654, 1, 25); + setArg(call_mask_fp_vector_imm_op_3654, 2, mask_fp_vector_imm_op_3654_arg2); + setArg(call_mask_fp_vector_imm_op_3654, 3, mask_fp_vector_imm_op_3654_arg3); + setArg(call_mask_fp_vector_imm_op_3654, 4, mask_fp_vector_imm_op_3654_arg4); + setArg(call_mask_fp_vector_imm_op_3654, 5, vm); + setArg(call_mask_fp_vector_imm_op_3654, 6, vd); + setArg(call_mask_fp_vector_imm_op_3654, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3654, 8, mask_fp_vector_imm_op_3654_arg8); + setArg(call_mask_fp_vector_imm_op_3654, 9, mask_fp_vector_imm_op_3654_arg9); + setArg(call_mask_fp_vector_imm_op_3654, 10, mask_fp_vector_imm_op_3654_arg10); + InvokeNode* call_fget_flags_3656; + x86::Gp ret_val_fget_flags_3656 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3656, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3656; + setRet(call_fget_flags_3656, 0, ret_val_fget_flags_3656); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3641 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3641, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3641, 32, false) - , traits::vstart); + auto tmp3657 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3657, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3657, traits::vstart); } cc.bind(label_merge); } @@ -82551,28 +82019,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3642; - x86::Gp ret_val_get_sew_pow_3642 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3642, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3643 = get_reg(cc, 8, false); - mov(cc, tmp3643, 1); + InvokeNode* call_get_sew_pow_3658; + x86::Gp ret_val_get_sew_pow_3658 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3658, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3659 = get_reg(cc, 8, false); + mov(cc, tmp3659, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3643, (ret_val_get_sew_pow_3642))), 8, false), ~ 1); - setArg(call_get_sew_pow_3642, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3642, 0, ret_val_get_sew_pow_3642); + (gen_operation(cc, shl, tmp3659, (ret_val_get_sew_pow_3658))), 8, false), ~ 1); + setArg(call_get_sew_pow_3658, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3658, 0, ret_val_get_sew_pow_3658); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3644; - auto illegal_fp_vd_unmasked_3644_arg0 = SEW; - auto illegal_fp_vd_unmasked_3644_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3644 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3644, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3644; - setArg(call_illegal_fp_vd_unmasked_3644, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3644, 1, illegal_fp_vd_unmasked_3644_arg0); - setArg(call_illegal_fp_vd_unmasked_3644, 2, illegal_fp_vd_unmasked_3644_arg1); - setRet(call_illegal_fp_vd_unmasked_3644, 0, ret_val_illegal_fp_vd_unmasked_3644); + InvokeNode* call_illegal_fp_vd_unmasked_3660; + auto illegal_fp_vd_unmasked_3660_arg0 = SEW; + auto illegal_fp_vd_unmasked_3660_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3660 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3660, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3660; + setArg(call_illegal_fp_vd_unmasked_3660, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3660, 1, illegal_fp_vd_unmasked_3660_arg0); + setArg(call_illegal_fp_vd_unmasked_3660, 2, illegal_fp_vd_unmasked_3660_arg1); + setRet(call_illegal_fp_vd_unmasked_3660, 0, ret_val_illegal_fp_vd_unmasked_3660); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82588,44 +82056,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3646; - x86::Gp ret_val_sew_3646 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3646, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_vector_op_3645; - auto mask_fp_vector_vector_op_3645_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_vector_op_3645_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_vector_op_3645_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_vector_op_3645_arg9 = rm; - auto mask_fp_vector_vector_op_3645_arg10 = ret_val_sew_3646; + InvokeNode* call_sew_3662; + x86::Gp ret_val_sew_3662 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3662, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3661; + auto mask_fp_vector_vector_op_3661_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3661_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3661_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3661_arg9 = rm; + auto mask_fp_vector_vector_op_3661_arg10 = ret_val_sew_3662; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_vector_op_3645, &mask_fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3646, 0, reinterpret_cast(this)); - setRet(call_sew_3646, 0, ret_val_sew_3646); - setArg(call_mask_fp_vector_vector_op_3645, 0, V); - setArg(call_mask_fp_vector_vector_op_3645, 1, 25); - setArg(call_mask_fp_vector_vector_op_3645, 2, mask_fp_vector_vector_op_3645_arg2); - setArg(call_mask_fp_vector_vector_op_3645, 3, mask_fp_vector_vector_op_3645_arg3); - setArg(call_mask_fp_vector_vector_op_3645, 4, mask_fp_vector_vector_op_3645_arg4); - setArg(call_mask_fp_vector_vector_op_3645, 5, vm); - setArg(call_mask_fp_vector_vector_op_3645, 6, vd); - setArg(call_mask_fp_vector_vector_op_3645, 7, vs2); - setArg(call_mask_fp_vector_vector_op_3645, 8, vs1); - setArg(call_mask_fp_vector_vector_op_3645, 9, mask_fp_vector_vector_op_3645_arg9); - setArg(call_mask_fp_vector_vector_op_3645, 10, mask_fp_vector_vector_op_3645_arg10); - InvokeNode* call_fget_flags_3647; - x86::Gp ret_val_fget_flags_3647 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3647, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3647; - setRet(call_fget_flags_3647, 0, ret_val_fget_flags_3647); + cc.invoke(&call_mask_fp_vector_vector_op_3661, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3662, 0, reinterpret_cast(this)); + setRet(call_sew_3662, 0, ret_val_sew_3662); + setArg(call_mask_fp_vector_vector_op_3661, 0, V); + setArg(call_mask_fp_vector_vector_op_3661, 1, 25); + setArg(call_mask_fp_vector_vector_op_3661, 2, mask_fp_vector_vector_op_3661_arg2); + setArg(call_mask_fp_vector_vector_op_3661, 3, mask_fp_vector_vector_op_3661_arg3); + setArg(call_mask_fp_vector_vector_op_3661, 4, mask_fp_vector_vector_op_3661_arg4); + setArg(call_mask_fp_vector_vector_op_3661, 5, vm); + setArg(call_mask_fp_vector_vector_op_3661, 6, vd); + setArg(call_mask_fp_vector_vector_op_3661, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3661, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3661, 9, mask_fp_vector_vector_op_3661_arg9); + setArg(call_mask_fp_vector_vector_op_3661, 10, mask_fp_vector_vector_op_3661_arg10); + InvokeNode* call_fget_flags_3663; + x86::Gp ret_val_fget_flags_3663 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3663, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3663; + setRet(call_fget_flags_3663, 0, ret_val_fget_flags_3663); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3648 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3648, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3648, 32, false) - , traits::vstart); + auto tmp3664 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3664, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3664, traits::vstart); } cc.bind(label_merge); } @@ -82669,28 +82135,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3649; - x86::Gp ret_val_get_sew_pow_3649 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3649, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3650 = get_reg(cc, 8, false); - mov(cc, tmp3650, 1); + InvokeNode* call_get_sew_pow_3665; + x86::Gp ret_val_get_sew_pow_3665 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3665, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3666 = get_reg(cc, 8, false); + mov(cc, tmp3666, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3650, (ret_val_get_sew_pow_3649))), 8, false), ~ 1); - setArg(call_get_sew_pow_3649, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3649, 0, ret_val_get_sew_pow_3649); + (gen_operation(cc, shl, tmp3666, (ret_val_get_sew_pow_3665))), 8, false), ~ 1); + setArg(call_get_sew_pow_3665, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3665, 0, ret_val_get_sew_pow_3665); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3651; - auto illegal_fp_vd_unmasked_3651_arg0 = SEW; - auto illegal_fp_vd_unmasked_3651_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3651 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3651, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3651; - setArg(call_illegal_fp_vd_unmasked_3651, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3651, 1, illegal_fp_vd_unmasked_3651_arg0); - setArg(call_illegal_fp_vd_unmasked_3651, 2, illegal_fp_vd_unmasked_3651_arg1); - setRet(call_illegal_fp_vd_unmasked_3651, 0, ret_val_illegal_fp_vd_unmasked_3651); + InvokeNode* call_illegal_fp_vd_unmasked_3667; + auto illegal_fp_vd_unmasked_3667_arg0 = SEW; + auto illegal_fp_vd_unmasked_3667_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3667 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3667, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3667; + setArg(call_illegal_fp_vd_unmasked_3667, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3667, 1, illegal_fp_vd_unmasked_3667_arg0); + setArg(call_illegal_fp_vd_unmasked_3667, 2, illegal_fp_vd_unmasked_3667_arg1); + setRet(call_illegal_fp_vd_unmasked_3667, 0, ret_val_illegal_fp_vd_unmasked_3667); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82706,46 +82172,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3653; - x86::Gp ret_val_sew_3653 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3653, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3652; - auto mask_fp_vector_imm_op_3652_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3652_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3652_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3652_arg8 = gen_ext(cc, + InvokeNode* call_sew_3669; + x86::Gp ret_val_sew_3669 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3669, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3668; + auto mask_fp_vector_imm_op_3668_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3668_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3668_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3668_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto mask_fp_vector_imm_op_3652_arg9 = rm; - auto mask_fp_vector_imm_op_3652_arg10 = ret_val_sew_3653; + auto mask_fp_vector_imm_op_3668_arg9 = rm; + auto mask_fp_vector_imm_op_3668_arg10 = ret_val_sew_3669; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3652, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3653, 0, reinterpret_cast(this)); - setRet(call_sew_3653, 0, ret_val_sew_3653); - setArg(call_mask_fp_vector_imm_op_3652, 0, V); - setArg(call_mask_fp_vector_imm_op_3652, 1, 29); - setArg(call_mask_fp_vector_imm_op_3652, 2, mask_fp_vector_imm_op_3652_arg2); - setArg(call_mask_fp_vector_imm_op_3652, 3, mask_fp_vector_imm_op_3652_arg3); - setArg(call_mask_fp_vector_imm_op_3652, 4, mask_fp_vector_imm_op_3652_arg4); - setArg(call_mask_fp_vector_imm_op_3652, 5, vm); - setArg(call_mask_fp_vector_imm_op_3652, 6, vd); - setArg(call_mask_fp_vector_imm_op_3652, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3652, 8, mask_fp_vector_imm_op_3652_arg8); - setArg(call_mask_fp_vector_imm_op_3652, 9, mask_fp_vector_imm_op_3652_arg9); - setArg(call_mask_fp_vector_imm_op_3652, 10, mask_fp_vector_imm_op_3652_arg10); - InvokeNode* call_fget_flags_3654; - x86::Gp ret_val_fget_flags_3654 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3654, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3654; - setRet(call_fget_flags_3654, 0, ret_val_fget_flags_3654); + cc.invoke(&call_mask_fp_vector_imm_op_3668, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3669, 0, reinterpret_cast(this)); + setRet(call_sew_3669, 0, ret_val_sew_3669); + setArg(call_mask_fp_vector_imm_op_3668, 0, V); + setArg(call_mask_fp_vector_imm_op_3668, 1, 29); + setArg(call_mask_fp_vector_imm_op_3668, 2, mask_fp_vector_imm_op_3668_arg2); + setArg(call_mask_fp_vector_imm_op_3668, 3, mask_fp_vector_imm_op_3668_arg3); + setArg(call_mask_fp_vector_imm_op_3668, 4, mask_fp_vector_imm_op_3668_arg4); + setArg(call_mask_fp_vector_imm_op_3668, 5, vm); + setArg(call_mask_fp_vector_imm_op_3668, 6, vd); + setArg(call_mask_fp_vector_imm_op_3668, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3668, 8, mask_fp_vector_imm_op_3668_arg8); + setArg(call_mask_fp_vector_imm_op_3668, 9, mask_fp_vector_imm_op_3668_arg9); + setArg(call_mask_fp_vector_imm_op_3668, 10, mask_fp_vector_imm_op_3668_arg10); + InvokeNode* call_fget_flags_3670; + x86::Gp ret_val_fget_flags_3670 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3670, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3670; + setRet(call_fget_flags_3670, 0, ret_val_fget_flags_3670); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3655 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3655, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3655, 32, false) - , traits::vstart); + auto tmp3671 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3671, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3671, traits::vstart); } cc.bind(label_merge); } @@ -82789,28 +82253,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3656; - x86::Gp ret_val_get_sew_pow_3656 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3656, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3657 = get_reg(cc, 8, false); - mov(cc, tmp3657, 1); + InvokeNode* call_get_sew_pow_3672; + x86::Gp ret_val_get_sew_pow_3672 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3672, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3673 = get_reg(cc, 8, false); + mov(cc, tmp3673, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3657, (ret_val_get_sew_pow_3656))), 8, false), ~ 1); - setArg(call_get_sew_pow_3656, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3656, 0, ret_val_get_sew_pow_3656); + (gen_operation(cc, shl, tmp3673, (ret_val_get_sew_pow_3672))), 8, false), ~ 1); + setArg(call_get_sew_pow_3672, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3672, 0, ret_val_get_sew_pow_3672); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3658; - auto illegal_fp_vd_unmasked_3658_arg0 = SEW; - auto illegal_fp_vd_unmasked_3658_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3658 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3658, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3658; - setArg(call_illegal_fp_vd_unmasked_3658, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3658, 1, illegal_fp_vd_unmasked_3658_arg0); - setArg(call_illegal_fp_vd_unmasked_3658, 2, illegal_fp_vd_unmasked_3658_arg1); - setRet(call_illegal_fp_vd_unmasked_3658, 0, ret_val_illegal_fp_vd_unmasked_3658); + InvokeNode* call_illegal_fp_vd_unmasked_3674; + auto illegal_fp_vd_unmasked_3674_arg0 = SEW; + auto illegal_fp_vd_unmasked_3674_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3674 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3674, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3674; + setArg(call_illegal_fp_vd_unmasked_3674, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3674, 1, illegal_fp_vd_unmasked_3674_arg0); + setArg(call_illegal_fp_vd_unmasked_3674, 2, illegal_fp_vd_unmasked_3674_arg1); + setRet(call_illegal_fp_vd_unmasked_3674, 0, ret_val_illegal_fp_vd_unmasked_3674); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82826,46 +82290,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3660; - x86::Gp ret_val_sew_3660 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3660, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3659; - auto mask_fp_vector_imm_op_3659_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3659_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3659_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3659_arg8 = gen_ext(cc, + InvokeNode* call_sew_3676; + x86::Gp ret_val_sew_3676 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3676, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3675; + auto mask_fp_vector_imm_op_3675_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3675_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3675_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3675_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto mask_fp_vector_imm_op_3659_arg9 = rm; - auto mask_fp_vector_imm_op_3659_arg10 = ret_val_sew_3660; + auto mask_fp_vector_imm_op_3675_arg9 = rm; + auto mask_fp_vector_imm_op_3675_arg10 = ret_val_sew_3676; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3659, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3660, 0, reinterpret_cast(this)); - setRet(call_sew_3660, 0, ret_val_sew_3660); - setArg(call_mask_fp_vector_imm_op_3659, 0, V); - setArg(call_mask_fp_vector_imm_op_3659, 1, 31); - setArg(call_mask_fp_vector_imm_op_3659, 2, mask_fp_vector_imm_op_3659_arg2); - setArg(call_mask_fp_vector_imm_op_3659, 3, mask_fp_vector_imm_op_3659_arg3); - setArg(call_mask_fp_vector_imm_op_3659, 4, mask_fp_vector_imm_op_3659_arg4); - setArg(call_mask_fp_vector_imm_op_3659, 5, vm); - setArg(call_mask_fp_vector_imm_op_3659, 6, vd); - setArg(call_mask_fp_vector_imm_op_3659, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3659, 8, mask_fp_vector_imm_op_3659_arg8); - setArg(call_mask_fp_vector_imm_op_3659, 9, mask_fp_vector_imm_op_3659_arg9); - setArg(call_mask_fp_vector_imm_op_3659, 10, mask_fp_vector_imm_op_3659_arg10); - InvokeNode* call_fget_flags_3661; - x86::Gp ret_val_fget_flags_3661 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3661, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3661; - setRet(call_fget_flags_3661, 0, ret_val_fget_flags_3661); + cc.invoke(&call_mask_fp_vector_imm_op_3675, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3676, 0, reinterpret_cast(this)); + setRet(call_sew_3676, 0, ret_val_sew_3676); + setArg(call_mask_fp_vector_imm_op_3675, 0, V); + setArg(call_mask_fp_vector_imm_op_3675, 1, 31); + setArg(call_mask_fp_vector_imm_op_3675, 2, mask_fp_vector_imm_op_3675_arg2); + setArg(call_mask_fp_vector_imm_op_3675, 3, mask_fp_vector_imm_op_3675_arg3); + setArg(call_mask_fp_vector_imm_op_3675, 4, mask_fp_vector_imm_op_3675_arg4); + setArg(call_mask_fp_vector_imm_op_3675, 5, vm); + setArg(call_mask_fp_vector_imm_op_3675, 6, vd); + setArg(call_mask_fp_vector_imm_op_3675, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3675, 8, mask_fp_vector_imm_op_3675_arg8); + setArg(call_mask_fp_vector_imm_op_3675, 9, mask_fp_vector_imm_op_3675_arg9); + setArg(call_mask_fp_vector_imm_op_3675, 10, mask_fp_vector_imm_op_3675_arg10); + InvokeNode* call_fget_flags_3677; + x86::Gp ret_val_fget_flags_3677 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3677, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3677; + setRet(call_fget_flags_3677, 0, ret_val_fget_flags_3677); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3662 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3662, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3662, 32, false) - , traits::vstart); + auto tmp3678 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3678, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3678, traits::vstart); } cc.bind(label_merge); } @@ -82908,30 +82370,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3663; - x86::Gp ret_val_get_sew_pow_3663 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3663, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3664 = get_reg(cc, 8, false); - mov(cc, tmp3664, 1); + InvokeNode* call_get_sew_pow_3679; + x86::Gp ret_val_get_sew_pow_3679 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3679, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3680 = get_reg(cc, 8, false); + mov(cc, tmp3680, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3664, (ret_val_get_sew_pow_3663))), 8, false), ~ 1); - setArg(call_get_sew_pow_3663, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3663, 0, ret_val_get_sew_pow_3663); + (gen_operation(cc, shl, tmp3680, (ret_val_get_sew_pow_3679))), 8, false), ~ 1); + setArg(call_get_sew_pow_3679, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3679, 0, ret_val_get_sew_pow_3679); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3665; - auto illegal_fp_normal_3665_arg2 = SEW; - auto illegal_fp_normal_3665_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3665 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3665, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3665; - setArg(call_illegal_fp_normal_3665, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3665, 1, vd); - setArg(call_illegal_fp_normal_3665, 2, vm); - setArg(call_illegal_fp_normal_3665, 3, illegal_fp_normal_3665_arg2); - setArg(call_illegal_fp_normal_3665, 4, illegal_fp_normal_3665_arg3); - setRet(call_illegal_fp_normal_3665, 0, ret_val_illegal_fp_normal_3665); + InvokeNode* call_illegal_fp_normal_3681; + auto illegal_fp_normal_3681_arg2 = SEW; + auto illegal_fp_normal_3681_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3681 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3681, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3681; + setArg(call_illegal_fp_normal_3681, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3681, 1, vd); + setArg(call_illegal_fp_normal_3681, 2, vm); + setArg(call_illegal_fp_normal_3681, 3, illegal_fp_normal_3681_arg2); + setArg(call_illegal_fp_normal_3681, 4, illegal_fp_normal_3681_arg3); + setRet(call_illegal_fp_normal_3681, 0, ret_val_illegal_fp_normal_3681); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82947,38 +82409,36 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3667; - x86::Gp ret_val_sew_3667 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3667, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3666; - auto fp_vector_unary_op_3666_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3666_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3666_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3666_arg9 = rm; - auto fp_vector_unary_op_3666_arg10 = ret_val_sew_3667; + InvokeNode* call_sew_3683; + x86::Gp ret_val_sew_3683 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3683, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3682; + auto fp_vector_unary_op_3682_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3682_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3682_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3682_arg9 = rm; + auto fp_vector_unary_op_3682_arg10 = ret_val_sew_3683; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3666, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3667, 0, reinterpret_cast(this)); - setRet(call_sew_3667, 0, ret_val_sew_3667); - setArg(call_fp_vector_unary_op_3666, 0, V); - setArg(call_fp_vector_unary_op_3666, 1, 19); - setArg(call_fp_vector_unary_op_3666, 2, 16); - setArg(call_fp_vector_unary_op_3666, 3, fp_vector_unary_op_3666_arg3); - setArg(call_fp_vector_unary_op_3666, 4, fp_vector_unary_op_3666_arg4); - setArg(call_fp_vector_unary_op_3666, 5, fp_vector_unary_op_3666_arg5); - setArg(call_fp_vector_unary_op_3666, 6, vm); - setArg(call_fp_vector_unary_op_3666, 7, vd); - setArg(call_fp_vector_unary_op_3666, 8, vs2); - setArg(call_fp_vector_unary_op_3666, 9, fp_vector_unary_op_3666_arg9); - setArg(call_fp_vector_unary_op_3666, 10, fp_vector_unary_op_3666_arg10); + cc.invoke(&call_fp_vector_unary_op_3682, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3683, 0, reinterpret_cast(this)); + setRet(call_sew_3683, 0, ret_val_sew_3683); + setArg(call_fp_vector_unary_op_3682, 0, V); + setArg(call_fp_vector_unary_op_3682, 1, 19); + setArg(call_fp_vector_unary_op_3682, 2, 16); + setArg(call_fp_vector_unary_op_3682, 3, fp_vector_unary_op_3682_arg3); + setArg(call_fp_vector_unary_op_3682, 4, fp_vector_unary_op_3682_arg4); + setArg(call_fp_vector_unary_op_3682, 5, fp_vector_unary_op_3682_arg5); + setArg(call_fp_vector_unary_op_3682, 6, vm); + setArg(call_fp_vector_unary_op_3682, 7, vd); + setArg(call_fp_vector_unary_op_3682, 8, vs2); + setArg(call_fp_vector_unary_op_3682, 9, fp_vector_unary_op_3682_arg9); + setArg(call_fp_vector_unary_op_3682, 10, fp_vector_unary_op_3682_arg10); } cc.bind(label_merge); } - auto tmp3668 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3668, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3668, 32, false) - , traits::vstart); + auto tmp3684 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3684, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3684, traits::vstart); } cc.bind(label_merge); } @@ -83021,29 +82481,29 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3669; - x86::Gp ret_val_get_sew_pow_3669 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3669, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3670 = get_reg(cc, 8, false); - mov(cc, tmp3670, 1); + InvokeNode* call_get_sew_pow_3685; + x86::Gp ret_val_get_sew_pow_3685 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3685, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3686 = get_reg(cc, 8, false); + mov(cc, tmp3686, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3670, (ret_val_get_sew_pow_3669))), 8, false), ~ 1); - setArg(call_get_sew_pow_3669, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3669, 0, ret_val_get_sew_pow_3669); + (gen_operation(cc, shl, tmp3686, (ret_val_get_sew_pow_3685))), 8, false), ~ 1); + setArg(call_get_sew_pow_3685, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3685, 0, ret_val_get_sew_pow_3685); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_masked_3671; - auto illegal_fp_vd_masked_3671_arg1 = SEW; - auto illegal_fp_vd_masked_3671_arg2 = rm; - x86::Gp ret_val_illegal_fp_vd_masked_3671 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_masked_3671, (uintptr_t)&vm_impl::_illegal_fp_vd_masked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_masked_3671; - setArg(call_illegal_fp_vd_masked_3671, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_masked_3671, 1, vd); - setArg(call_illegal_fp_vd_masked_3671, 2, illegal_fp_vd_masked_3671_arg1); - setArg(call_illegal_fp_vd_masked_3671, 3, illegal_fp_vd_masked_3671_arg2); - setRet(call_illegal_fp_vd_masked_3671, 0, ret_val_illegal_fp_vd_masked_3671); + InvokeNode* call_illegal_fp_vd_masked_3687; + auto illegal_fp_vd_masked_3687_arg1 = SEW; + auto illegal_fp_vd_masked_3687_arg2 = rm; + x86::Gp ret_val_illegal_fp_vd_masked_3687 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_masked_3687, (uintptr_t)&vm_impl::_illegal_fp_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_masked_3687; + setArg(call_illegal_fp_vd_masked_3687, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_masked_3687, 1, vd); + setArg(call_illegal_fp_vd_masked_3687, 2, illegal_fp_vd_masked_3687_arg1); + setArg(call_illegal_fp_vd_masked_3687, 3, illegal_fp_vd_masked_3687_arg2); + setRet(call_illegal_fp_vd_masked_3687, 0, ret_val_illegal_fp_vd_masked_3687); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83059,37 +82519,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3673; - x86::Gp ret_val_sew_3673 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3673, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_imm_merge_3672; - auto vector_imm_merge_3672_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_imm_merge_3672_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_imm_merge_3672_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_imm_merge_3672_arg7 = gen_ext(cc, + InvokeNode* call_sew_3689; + x86::Gp ret_val_sew_3689 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3689, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_3688; + auto vector_imm_merge_3688_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_3688_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_3688_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_3688_arg7 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto vector_imm_merge_3672_arg8 = ret_val_sew_3673; + auto vector_imm_merge_3688_arg8 = ret_val_sew_3689; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_merge_3672, &vector_imm_merge, FuncSignature::build()); - setArg(call_sew_3673, 0, reinterpret_cast(this)); - setRet(call_sew_3673, 0, ret_val_sew_3673); - setArg(call_vector_imm_merge_3672, 0, V); - setArg(call_vector_imm_merge_3672, 1, vector_imm_merge_3672_arg1); - setArg(call_vector_imm_merge_3672, 2, vector_imm_merge_3672_arg2); - setArg(call_vector_imm_merge_3672, 3, vector_imm_merge_3672_arg3); - setArg(call_vector_imm_merge_3672, 4, 0); - setArg(call_vector_imm_merge_3672, 5, vd); - setArg(call_vector_imm_merge_3672, 6, vs2); - setArg(call_vector_imm_merge_3672, 7, vector_imm_merge_3672_arg7); - setArg(call_vector_imm_merge_3672, 8, vector_imm_merge_3672_arg8); + cc.invoke(&call_vector_imm_merge_3688, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_3689, 0, reinterpret_cast(this)); + setRet(call_sew_3689, 0, ret_val_sew_3689); + setArg(call_vector_imm_merge_3688, 0, V); + setArg(call_vector_imm_merge_3688, 1, vector_imm_merge_3688_arg1); + setArg(call_vector_imm_merge_3688, 2, vector_imm_merge_3688_arg2); + setArg(call_vector_imm_merge_3688, 3, vector_imm_merge_3688_arg3); + setArg(call_vector_imm_merge_3688, 4, 0); + setArg(call_vector_imm_merge_3688, 5, vd); + setArg(call_vector_imm_merge_3688, 6, vs2); + setArg(call_vector_imm_merge_3688, 7, vector_imm_merge_3688_arg7); + setArg(call_vector_imm_merge_3688, 8, vector_imm_merge_3688_arg8); } cc.bind(label_merge); } - auto tmp3674 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3674, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3674, 32, false) - , traits::vstart); + auto tmp3690 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3690, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3690, traits::vstart); } cc.bind(label_merge); } @@ -83131,28 +82589,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3675; - x86::Gp ret_val_get_sew_pow_3675 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3675, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3676 = get_reg(cc, 8, false); - mov(cc, tmp3676, 1); + InvokeNode* call_get_sew_pow_3691; + x86::Gp ret_val_get_sew_pow_3691 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3691, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3692 = get_reg(cc, 8, false); + mov(cc, tmp3692, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3676, (ret_val_get_sew_pow_3675))), 8, false), ~ 1); - setArg(call_get_sew_pow_3675, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3675, 0, ret_val_get_sew_pow_3675); + (gen_operation(cc, shl, tmp3692, (ret_val_get_sew_pow_3691))), 8, false), ~ 1); + setArg(call_get_sew_pow_3691, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3691, 0, ret_val_get_sew_pow_3691); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3677; - auto illegal_fp_vd_unmasked_3677_arg0 = SEW; - auto illegal_fp_vd_unmasked_3677_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3677 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3677, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3677; - setArg(call_illegal_fp_vd_unmasked_3677, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3677, 1, illegal_fp_vd_unmasked_3677_arg0); - setArg(call_illegal_fp_vd_unmasked_3677, 2, illegal_fp_vd_unmasked_3677_arg1); - setRet(call_illegal_fp_vd_unmasked_3677, 0, ret_val_illegal_fp_vd_unmasked_3677); + InvokeNode* call_illegal_fp_vd_unmasked_3693; + auto illegal_fp_vd_unmasked_3693_arg0 = SEW; + auto illegal_fp_vd_unmasked_3693_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3693 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3693, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3693; + setArg(call_illegal_fp_vd_unmasked_3693, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3693, 1, illegal_fp_vd_unmasked_3693_arg0); + setArg(call_illegal_fp_vd_unmasked_3693, 2, illegal_fp_vd_unmasked_3693_arg1); + setRet(call_illegal_fp_vd_unmasked_3693, 0, ret_val_illegal_fp_vd_unmasked_3693); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83168,37 +82626,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3679; - x86::Gp ret_val_sew_3679 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3679, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_imm_merge_3678; - auto vector_imm_merge_3678_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_imm_merge_3678_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_imm_merge_3678_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_imm_merge_3678_arg7 = gen_ext(cc, + InvokeNode* call_sew_3695; + x86::Gp ret_val_sew_3695 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3695, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_3694; + auto vector_imm_merge_3694_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_3694_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_3694_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_3694_arg7 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 32, false); - auto vector_imm_merge_3678_arg8 = ret_val_sew_3679; + auto vector_imm_merge_3694_arg8 = ret_val_sew_3695; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_merge_3678, &vector_imm_merge, FuncSignature::build()); - setArg(call_sew_3679, 0, reinterpret_cast(this)); - setRet(call_sew_3679, 0, ret_val_sew_3679); - setArg(call_vector_imm_merge_3678, 0, V); - setArg(call_vector_imm_merge_3678, 1, vector_imm_merge_3678_arg1); - setArg(call_vector_imm_merge_3678, 2, vector_imm_merge_3678_arg2); - setArg(call_vector_imm_merge_3678, 3, vector_imm_merge_3678_arg3); - setArg(call_vector_imm_merge_3678, 4, 1); - setArg(call_vector_imm_merge_3678, 5, vd); - setArg(call_vector_imm_merge_3678, 6, 0); - setArg(call_vector_imm_merge_3678, 7, vector_imm_merge_3678_arg7); - setArg(call_vector_imm_merge_3678, 8, vector_imm_merge_3678_arg8); + cc.invoke(&call_vector_imm_merge_3694, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_3695, 0, reinterpret_cast(this)); + setRet(call_sew_3695, 0, ret_val_sew_3695); + setArg(call_vector_imm_merge_3694, 0, V); + setArg(call_vector_imm_merge_3694, 1, vector_imm_merge_3694_arg1); + setArg(call_vector_imm_merge_3694, 2, vector_imm_merge_3694_arg2); + setArg(call_vector_imm_merge_3694, 3, vector_imm_merge_3694_arg3); + setArg(call_vector_imm_merge_3694, 4, 1); + setArg(call_vector_imm_merge_3694, 5, vd); + setArg(call_vector_imm_merge_3694, 6, 0); + setArg(call_vector_imm_merge_3694, 7, vector_imm_merge_3694_arg7); + setArg(call_vector_imm_merge_3694, 8, vector_imm_merge_3694_arg8); } cc.bind(label_merge); } - auto tmp3680 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3680, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3680, 32, false) - , traits::vstart); + auto tmp3696 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3696, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3696, traits::vstart); } cc.bind(label_merge); } @@ -83241,30 +82697,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3681; - x86::Gp ret_val_get_sew_pow_3681 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3681, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3682 = get_reg(cc, 8, false); - mov(cc, tmp3682, 1); + InvokeNode* call_get_sew_pow_3697; + x86::Gp ret_val_get_sew_pow_3697 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3697, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3698 = get_reg(cc, 8, false); + mov(cc, tmp3698, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3682, (ret_val_get_sew_pow_3681))), 8, false), ~ 1); - setArg(call_get_sew_pow_3681, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3681, 0, ret_val_get_sew_pow_3681); + (gen_operation(cc, shl, tmp3698, (ret_val_get_sew_pow_3697))), 8, false), ~ 1); + setArg(call_get_sew_pow_3697, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3697, 0, ret_val_get_sew_pow_3697); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3683; - auto illegal_fp_normal_3683_arg2 = SEW; - auto illegal_fp_normal_3683_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3683 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3683, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3683; - setArg(call_illegal_fp_normal_3683, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3683, 1, vd); - setArg(call_illegal_fp_normal_3683, 2, vm); - setArg(call_illegal_fp_normal_3683, 3, illegal_fp_normal_3683_arg2); - setArg(call_illegal_fp_normal_3683, 4, illegal_fp_normal_3683_arg3); - setRet(call_illegal_fp_normal_3683, 0, ret_val_illegal_fp_normal_3683); + InvokeNode* call_illegal_fp_normal_3699; + auto illegal_fp_normal_3699_arg2 = SEW; + auto illegal_fp_normal_3699_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3699 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3699, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3699; + setArg(call_illegal_fp_normal_3699, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3699, 1, vd); + setArg(call_illegal_fp_normal_3699, 2, vm); + setArg(call_illegal_fp_normal_3699, 3, illegal_fp_normal_3699_arg2); + setArg(call_illegal_fp_normal_3699, 4, illegal_fp_normal_3699_arg3); + setRet(call_illegal_fp_normal_3699, 0, ret_val_illegal_fp_normal_3699); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83280,38 +82736,36 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3685; - x86::Gp ret_val_sew_3685 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3685, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3684; - auto fp_vector_unary_op_3684_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3684_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3684_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3684_arg9 = rm; - auto fp_vector_unary_op_3684_arg10 = ret_val_sew_3685; + InvokeNode* call_sew_3701; + x86::Gp ret_val_sew_3701 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3701, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3700; + auto fp_vector_unary_op_3700_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3700_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3700_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3700_arg9 = rm; + auto fp_vector_unary_op_3700_arg10 = ret_val_sew_3701; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3684, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3685, 0, reinterpret_cast(this)); - setRet(call_sew_3685, 0, ret_val_sew_3685); - setArg(call_fp_vector_unary_op_3684, 0, V); - setArg(call_fp_vector_unary_op_3684, 1, 18); - setArg(call_fp_vector_unary_op_3684, 2, 0); - setArg(call_fp_vector_unary_op_3684, 3, fp_vector_unary_op_3684_arg3); - setArg(call_fp_vector_unary_op_3684, 4, fp_vector_unary_op_3684_arg4); - setArg(call_fp_vector_unary_op_3684, 5, fp_vector_unary_op_3684_arg5); - setArg(call_fp_vector_unary_op_3684, 6, vm); - setArg(call_fp_vector_unary_op_3684, 7, vd); - setArg(call_fp_vector_unary_op_3684, 8, vs2); - setArg(call_fp_vector_unary_op_3684, 9, fp_vector_unary_op_3684_arg9); - setArg(call_fp_vector_unary_op_3684, 10, fp_vector_unary_op_3684_arg10); + cc.invoke(&call_fp_vector_unary_op_3700, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3701, 0, reinterpret_cast(this)); + setRet(call_sew_3701, 0, ret_val_sew_3701); + setArg(call_fp_vector_unary_op_3700, 0, V); + setArg(call_fp_vector_unary_op_3700, 1, 18); + setArg(call_fp_vector_unary_op_3700, 2, 0); + setArg(call_fp_vector_unary_op_3700, 3, fp_vector_unary_op_3700_arg3); + setArg(call_fp_vector_unary_op_3700, 4, fp_vector_unary_op_3700_arg4); + setArg(call_fp_vector_unary_op_3700, 5, fp_vector_unary_op_3700_arg5); + setArg(call_fp_vector_unary_op_3700, 6, vm); + setArg(call_fp_vector_unary_op_3700, 7, vd); + setArg(call_fp_vector_unary_op_3700, 8, vs2); + setArg(call_fp_vector_unary_op_3700, 9, fp_vector_unary_op_3700_arg9); + setArg(call_fp_vector_unary_op_3700, 10, fp_vector_unary_op_3700_arg10); } cc.bind(label_merge); } - auto tmp3686 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3686, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3686, 32, false) - , traits::vstart); + auto tmp3702 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3702, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3702, traits::vstart); } cc.bind(label_merge); } @@ -83354,30 +82808,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3687; - x86::Gp ret_val_get_sew_pow_3687 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3687, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3688 = get_reg(cc, 8, false); - mov(cc, tmp3688, 1); + InvokeNode* call_get_sew_pow_3703; + x86::Gp ret_val_get_sew_pow_3703 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3703, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3704 = get_reg(cc, 8, false); + mov(cc, tmp3704, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3688, (ret_val_get_sew_pow_3687))), 8, false), ~ 1); - setArg(call_get_sew_pow_3687, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3687, 0, ret_val_get_sew_pow_3687); + (gen_operation(cc, shl, tmp3704, (ret_val_get_sew_pow_3703))), 8, false), ~ 1); + setArg(call_get_sew_pow_3703, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3703, 0, ret_val_get_sew_pow_3703); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3689; - auto illegal_fp_normal_3689_arg2 = SEW; - auto illegal_fp_normal_3689_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3689 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3689, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3689; - setArg(call_illegal_fp_normal_3689, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3689, 1, vd); - setArg(call_illegal_fp_normal_3689, 2, vm); - setArg(call_illegal_fp_normal_3689, 3, illegal_fp_normal_3689_arg2); - setArg(call_illegal_fp_normal_3689, 4, illegal_fp_normal_3689_arg3); - setRet(call_illegal_fp_normal_3689, 0, ret_val_illegal_fp_normal_3689); + InvokeNode* call_illegal_fp_normal_3705; + auto illegal_fp_normal_3705_arg2 = SEW; + auto illegal_fp_normal_3705_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3705 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3705, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3705; + setArg(call_illegal_fp_normal_3705, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3705, 1, vd); + setArg(call_illegal_fp_normal_3705, 2, vm); + setArg(call_illegal_fp_normal_3705, 3, illegal_fp_normal_3705_arg2); + setArg(call_illegal_fp_normal_3705, 4, illegal_fp_normal_3705_arg3); + setRet(call_illegal_fp_normal_3705, 0, ret_val_illegal_fp_normal_3705); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83393,38 +82847,36 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3691; - x86::Gp ret_val_sew_3691 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3691, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3690; - auto fp_vector_unary_op_3690_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3690_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3690_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3690_arg9 = rm; - auto fp_vector_unary_op_3690_arg10 = ret_val_sew_3691; + InvokeNode* call_sew_3707; + x86::Gp ret_val_sew_3707 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3707, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3706; + auto fp_vector_unary_op_3706_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3706_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3706_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3706_arg9 = rm; + auto fp_vector_unary_op_3706_arg10 = ret_val_sew_3707; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3690, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3691, 0, reinterpret_cast(this)); - setRet(call_sew_3691, 0, ret_val_sew_3691); - setArg(call_fp_vector_unary_op_3690, 0, V); - setArg(call_fp_vector_unary_op_3690, 1, 18); - setArg(call_fp_vector_unary_op_3690, 2, 1); - setArg(call_fp_vector_unary_op_3690, 3, fp_vector_unary_op_3690_arg3); - setArg(call_fp_vector_unary_op_3690, 4, fp_vector_unary_op_3690_arg4); - setArg(call_fp_vector_unary_op_3690, 5, fp_vector_unary_op_3690_arg5); - setArg(call_fp_vector_unary_op_3690, 6, vm); - setArg(call_fp_vector_unary_op_3690, 7, vd); - setArg(call_fp_vector_unary_op_3690, 8, vs2); - setArg(call_fp_vector_unary_op_3690, 9, fp_vector_unary_op_3690_arg9); - setArg(call_fp_vector_unary_op_3690, 10, fp_vector_unary_op_3690_arg10); + cc.invoke(&call_fp_vector_unary_op_3706, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3707, 0, reinterpret_cast(this)); + setRet(call_sew_3707, 0, ret_val_sew_3707); + setArg(call_fp_vector_unary_op_3706, 0, V); + setArg(call_fp_vector_unary_op_3706, 1, 18); + setArg(call_fp_vector_unary_op_3706, 2, 1); + setArg(call_fp_vector_unary_op_3706, 3, fp_vector_unary_op_3706_arg3); + setArg(call_fp_vector_unary_op_3706, 4, fp_vector_unary_op_3706_arg4); + setArg(call_fp_vector_unary_op_3706, 5, fp_vector_unary_op_3706_arg5); + setArg(call_fp_vector_unary_op_3706, 6, vm); + setArg(call_fp_vector_unary_op_3706, 7, vd); + setArg(call_fp_vector_unary_op_3706, 8, vs2); + setArg(call_fp_vector_unary_op_3706, 9, fp_vector_unary_op_3706_arg9); + setArg(call_fp_vector_unary_op_3706, 10, fp_vector_unary_op_3706_arg10); } cc.bind(label_merge); } - auto tmp3692 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3692, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3692, 32, false) - , traits::vstart); + auto tmp3708 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3708, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3708, traits::vstart); } cc.bind(label_merge); } @@ -83467,29 +82919,29 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3693; - x86::Gp ret_val_get_sew_pow_3693 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3693, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3694 = get_reg(cc, 8, false); - mov(cc, tmp3694, 1); + InvokeNode* call_get_sew_pow_3709; + x86::Gp ret_val_get_sew_pow_3709 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3709, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3710 = get_reg(cc, 8, false); + mov(cc, tmp3710, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3694, (ret_val_get_sew_pow_3693))), 8, false), ~ 1); - setArg(call_get_sew_pow_3693, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3693, 0, ret_val_get_sew_pow_3693); + (gen_operation(cc, shl, tmp3710, (ret_val_get_sew_pow_3709))), 8, false), ~ 1); + setArg(call_get_sew_pow_3709, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3709, 0, ret_val_get_sew_pow_3709); auto rm = 1; { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3695; - auto illegal_fp_normal_3695_arg2 = SEW; - x86::Gp ret_val_illegal_fp_normal_3695 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3695, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3695; - setArg(call_illegal_fp_normal_3695, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3695, 1, vd); - setArg(call_illegal_fp_normal_3695, 2, vm); - setArg(call_illegal_fp_normal_3695, 3, illegal_fp_normal_3695_arg2); - setArg(call_illegal_fp_normal_3695, 4, rm); - setRet(call_illegal_fp_normal_3695, 0, ret_val_illegal_fp_normal_3695); + InvokeNode* call_illegal_fp_normal_3711; + auto illegal_fp_normal_3711_arg2 = SEW; + x86::Gp ret_val_illegal_fp_normal_3711 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3711, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3711; + setArg(call_illegal_fp_normal_3711, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3711, 1, vd); + setArg(call_illegal_fp_normal_3711, 2, vm); + setArg(call_illegal_fp_normal_3711, 3, illegal_fp_normal_3711_arg2); + setArg(call_illegal_fp_normal_3711, 4, rm); + setRet(call_illegal_fp_normal_3711, 0, ret_val_illegal_fp_normal_3711); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83505,37 +82957,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3697; - x86::Gp ret_val_sew_3697 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3697, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3696; - auto fp_vector_unary_op_3696_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3696_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3696_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3696_arg10 = ret_val_sew_3697; + InvokeNode* call_sew_3713; + x86::Gp ret_val_sew_3713 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3713, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3712; + auto fp_vector_unary_op_3712_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3712_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3712_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3712_arg10 = ret_val_sew_3713; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3696, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3697, 0, reinterpret_cast(this)); - setRet(call_sew_3697, 0, ret_val_sew_3697); - setArg(call_fp_vector_unary_op_3696, 0, V); - setArg(call_fp_vector_unary_op_3696, 1, 18); - setArg(call_fp_vector_unary_op_3696, 2, 6); - setArg(call_fp_vector_unary_op_3696, 3, fp_vector_unary_op_3696_arg3); - setArg(call_fp_vector_unary_op_3696, 4, fp_vector_unary_op_3696_arg4); - setArg(call_fp_vector_unary_op_3696, 5, fp_vector_unary_op_3696_arg5); - setArg(call_fp_vector_unary_op_3696, 6, vm); - setArg(call_fp_vector_unary_op_3696, 7, vd); - setArg(call_fp_vector_unary_op_3696, 8, vs2); - setArg(call_fp_vector_unary_op_3696, 9, rm); - setArg(call_fp_vector_unary_op_3696, 10, fp_vector_unary_op_3696_arg10); + cc.invoke(&call_fp_vector_unary_op_3712, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3713, 0, reinterpret_cast(this)); + setRet(call_sew_3713, 0, ret_val_sew_3713); + setArg(call_fp_vector_unary_op_3712, 0, V); + setArg(call_fp_vector_unary_op_3712, 1, 18); + setArg(call_fp_vector_unary_op_3712, 2, 6); + setArg(call_fp_vector_unary_op_3712, 3, fp_vector_unary_op_3712_arg3); + setArg(call_fp_vector_unary_op_3712, 4, fp_vector_unary_op_3712_arg4); + setArg(call_fp_vector_unary_op_3712, 5, fp_vector_unary_op_3712_arg5); + setArg(call_fp_vector_unary_op_3712, 6, vm); + setArg(call_fp_vector_unary_op_3712, 7, vd); + setArg(call_fp_vector_unary_op_3712, 8, vs2); + setArg(call_fp_vector_unary_op_3712, 9, rm); + setArg(call_fp_vector_unary_op_3712, 10, fp_vector_unary_op_3712_arg10); } cc.bind(label_merge); } - auto tmp3698 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3698, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3698, 32, false) - , traits::vstart); + auto tmp3714 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3714, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3714, traits::vstart); } cc.bind(label_merge); } @@ -83578,29 +83028,29 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3699; - x86::Gp ret_val_get_sew_pow_3699 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3699, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3700 = get_reg(cc, 8, false); - mov(cc, tmp3700, 1); + InvokeNode* call_get_sew_pow_3715; + x86::Gp ret_val_get_sew_pow_3715 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3715, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3716 = get_reg(cc, 8, false); + mov(cc, tmp3716, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3700, (ret_val_get_sew_pow_3699))), 8, false), ~ 1); - setArg(call_get_sew_pow_3699, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3699, 0, ret_val_get_sew_pow_3699); + (gen_operation(cc, shl, tmp3716, (ret_val_get_sew_pow_3715))), 8, false), ~ 1); + setArg(call_get_sew_pow_3715, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3715, 0, ret_val_get_sew_pow_3715); auto rm = 1; { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3701; - auto illegal_fp_normal_3701_arg2 = SEW; - x86::Gp ret_val_illegal_fp_normal_3701 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3701, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3701; - setArg(call_illegal_fp_normal_3701, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3701, 1, vd); - setArg(call_illegal_fp_normal_3701, 2, vm); - setArg(call_illegal_fp_normal_3701, 3, illegal_fp_normal_3701_arg2); - setArg(call_illegal_fp_normal_3701, 4, rm); - setRet(call_illegal_fp_normal_3701, 0, ret_val_illegal_fp_normal_3701); + InvokeNode* call_illegal_fp_normal_3717; + auto illegal_fp_normal_3717_arg2 = SEW; + x86::Gp ret_val_illegal_fp_normal_3717 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3717, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3717; + setArg(call_illegal_fp_normal_3717, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3717, 1, vd); + setArg(call_illegal_fp_normal_3717, 2, vm); + setArg(call_illegal_fp_normal_3717, 3, illegal_fp_normal_3717_arg2); + setArg(call_illegal_fp_normal_3717, 4, rm); + setRet(call_illegal_fp_normal_3717, 0, ret_val_illegal_fp_normal_3717); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83616,37 +83066,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3703; - x86::Gp ret_val_sew_3703 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3703, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3702; - auto fp_vector_unary_op_3702_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3702_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3702_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3702_arg10 = ret_val_sew_3703; + InvokeNode* call_sew_3719; + x86::Gp ret_val_sew_3719 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3719, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3718; + auto fp_vector_unary_op_3718_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3718_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3718_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3718_arg10 = ret_val_sew_3719; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3702, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3703, 0, reinterpret_cast(this)); - setRet(call_sew_3703, 0, ret_val_sew_3703); - setArg(call_fp_vector_unary_op_3702, 0, V); - setArg(call_fp_vector_unary_op_3702, 1, 18); - setArg(call_fp_vector_unary_op_3702, 2, 7); - setArg(call_fp_vector_unary_op_3702, 3, fp_vector_unary_op_3702_arg3); - setArg(call_fp_vector_unary_op_3702, 4, fp_vector_unary_op_3702_arg4); - setArg(call_fp_vector_unary_op_3702, 5, fp_vector_unary_op_3702_arg5); - setArg(call_fp_vector_unary_op_3702, 6, vm); - setArg(call_fp_vector_unary_op_3702, 7, vd); - setArg(call_fp_vector_unary_op_3702, 8, vs2); - setArg(call_fp_vector_unary_op_3702, 9, rm); - setArg(call_fp_vector_unary_op_3702, 10, fp_vector_unary_op_3702_arg10); + cc.invoke(&call_fp_vector_unary_op_3718, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3719, 0, reinterpret_cast(this)); + setRet(call_sew_3719, 0, ret_val_sew_3719); + setArg(call_fp_vector_unary_op_3718, 0, V); + setArg(call_fp_vector_unary_op_3718, 1, 18); + setArg(call_fp_vector_unary_op_3718, 2, 7); + setArg(call_fp_vector_unary_op_3718, 3, fp_vector_unary_op_3718_arg3); + setArg(call_fp_vector_unary_op_3718, 4, fp_vector_unary_op_3718_arg4); + setArg(call_fp_vector_unary_op_3718, 5, fp_vector_unary_op_3718_arg5); + setArg(call_fp_vector_unary_op_3718, 6, vm); + setArg(call_fp_vector_unary_op_3718, 7, vd); + setArg(call_fp_vector_unary_op_3718, 8, vs2); + setArg(call_fp_vector_unary_op_3718, 9, rm); + setArg(call_fp_vector_unary_op_3718, 10, fp_vector_unary_op_3718_arg10); } cc.bind(label_merge); } - auto tmp3704 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3704, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3704, 32, false) - , traits::vstart); + auto tmp3720 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3720, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3720, traits::vstart); } cc.bind(label_merge); } @@ -83689,30 +83137,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3705; - x86::Gp ret_val_get_sew_pow_3705 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3705, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3706 = get_reg(cc, 8, false); - mov(cc, tmp3706, 1); + InvokeNode* call_get_sew_pow_3721; + x86::Gp ret_val_get_sew_pow_3721 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3721, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3722 = get_reg(cc, 8, false); + mov(cc, tmp3722, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3706, (ret_val_get_sew_pow_3705))), 8, false), ~ 1); - setArg(call_get_sew_pow_3705, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3705, 0, ret_val_get_sew_pow_3705); + (gen_operation(cc, shl, tmp3722, (ret_val_get_sew_pow_3721))), 8, false), ~ 1); + setArg(call_get_sew_pow_3721, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3721, 0, ret_val_get_sew_pow_3721); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3707; - auto illegal_fp_normal_3707_arg2 = SEW; - auto illegal_fp_normal_3707_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3707 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3707, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3707; - setArg(call_illegal_fp_normal_3707, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3707, 1, vd); - setArg(call_illegal_fp_normal_3707, 2, vm); - setArg(call_illegal_fp_normal_3707, 3, illegal_fp_normal_3707_arg2); - setArg(call_illegal_fp_normal_3707, 4, illegal_fp_normal_3707_arg3); - setRet(call_illegal_fp_normal_3707, 0, ret_val_illegal_fp_normal_3707); + InvokeNode* call_illegal_fp_normal_3723; + auto illegal_fp_normal_3723_arg2 = SEW; + auto illegal_fp_normal_3723_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3723 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3723, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3723; + setArg(call_illegal_fp_normal_3723, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3723, 1, vd); + setArg(call_illegal_fp_normal_3723, 2, vm); + setArg(call_illegal_fp_normal_3723, 3, illegal_fp_normal_3723_arg2); + setArg(call_illegal_fp_normal_3723, 4, illegal_fp_normal_3723_arg3); + setRet(call_illegal_fp_normal_3723, 0, ret_val_illegal_fp_normal_3723); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83728,38 +83176,36 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3709; - x86::Gp ret_val_sew_3709 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3709, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3708; - auto fp_vector_unary_op_3708_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3708_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3708_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3708_arg9 = rm; - auto fp_vector_unary_op_3708_arg10 = ret_val_sew_3709; + InvokeNode* call_sew_3725; + x86::Gp ret_val_sew_3725 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3725, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3724; + auto fp_vector_unary_op_3724_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3724_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3724_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3724_arg9 = rm; + auto fp_vector_unary_op_3724_arg10 = ret_val_sew_3725; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3708, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3709, 0, reinterpret_cast(this)); - setRet(call_sew_3709, 0, ret_val_sew_3709); - setArg(call_fp_vector_unary_op_3708, 0, V); - setArg(call_fp_vector_unary_op_3708, 1, 18); - setArg(call_fp_vector_unary_op_3708, 2, 2); - setArg(call_fp_vector_unary_op_3708, 3, fp_vector_unary_op_3708_arg3); - setArg(call_fp_vector_unary_op_3708, 4, fp_vector_unary_op_3708_arg4); - setArg(call_fp_vector_unary_op_3708, 5, fp_vector_unary_op_3708_arg5); - setArg(call_fp_vector_unary_op_3708, 6, vm); - setArg(call_fp_vector_unary_op_3708, 7, vd); - setArg(call_fp_vector_unary_op_3708, 8, vs2); - setArg(call_fp_vector_unary_op_3708, 9, fp_vector_unary_op_3708_arg9); - setArg(call_fp_vector_unary_op_3708, 10, fp_vector_unary_op_3708_arg10); + cc.invoke(&call_fp_vector_unary_op_3724, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3725, 0, reinterpret_cast(this)); + setRet(call_sew_3725, 0, ret_val_sew_3725); + setArg(call_fp_vector_unary_op_3724, 0, V); + setArg(call_fp_vector_unary_op_3724, 1, 18); + setArg(call_fp_vector_unary_op_3724, 2, 2); + setArg(call_fp_vector_unary_op_3724, 3, fp_vector_unary_op_3724_arg3); + setArg(call_fp_vector_unary_op_3724, 4, fp_vector_unary_op_3724_arg4); + setArg(call_fp_vector_unary_op_3724, 5, fp_vector_unary_op_3724_arg5); + setArg(call_fp_vector_unary_op_3724, 6, vm); + setArg(call_fp_vector_unary_op_3724, 7, vd); + setArg(call_fp_vector_unary_op_3724, 8, vs2); + setArg(call_fp_vector_unary_op_3724, 9, fp_vector_unary_op_3724_arg9); + setArg(call_fp_vector_unary_op_3724, 10, fp_vector_unary_op_3724_arg10); } cc.bind(label_merge); } - auto tmp3710 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3710, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3710, 32, false) - , traits::vstart); + auto tmp3726 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3726, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3726, traits::vstart); } cc.bind(label_merge); } @@ -83802,30 +83248,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3711; - x86::Gp ret_val_get_sew_pow_3711 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3711, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3712 = get_reg(cc, 8, false); - mov(cc, tmp3712, 1); + InvokeNode* call_get_sew_pow_3727; + x86::Gp ret_val_get_sew_pow_3727 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3727, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3728 = get_reg(cc, 8, false); + mov(cc, tmp3728, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3712, (ret_val_get_sew_pow_3711))), 8, false), ~ 1); - setArg(call_get_sew_pow_3711, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3711, 0, ret_val_get_sew_pow_3711); + (gen_operation(cc, shl, tmp3728, (ret_val_get_sew_pow_3727))), 8, false), ~ 1); + setArg(call_get_sew_pow_3727, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3727, 0, ret_val_get_sew_pow_3727); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3713; - auto illegal_fp_normal_3713_arg2 = SEW; - auto illegal_fp_normal_3713_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3713 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3713, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3713; - setArg(call_illegal_fp_normal_3713, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3713, 1, vd); - setArg(call_illegal_fp_normal_3713, 2, vm); - setArg(call_illegal_fp_normal_3713, 3, illegal_fp_normal_3713_arg2); - setArg(call_illegal_fp_normal_3713, 4, illegal_fp_normal_3713_arg3); - setRet(call_illegal_fp_normal_3713, 0, ret_val_illegal_fp_normal_3713); + InvokeNode* call_illegal_fp_normal_3729; + auto illegal_fp_normal_3729_arg2 = SEW; + auto illegal_fp_normal_3729_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3729 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3729, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3729; + setArg(call_illegal_fp_normal_3729, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3729, 1, vd); + setArg(call_illegal_fp_normal_3729, 2, vm); + setArg(call_illegal_fp_normal_3729, 3, illegal_fp_normal_3729_arg2); + setArg(call_illegal_fp_normal_3729, 4, illegal_fp_normal_3729_arg3); + setRet(call_illegal_fp_normal_3729, 0, ret_val_illegal_fp_normal_3729); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83841,38 +83287,36 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3715; - x86::Gp ret_val_sew_3715 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3715, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3714; - auto fp_vector_unary_op_3714_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3714_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3714_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3714_arg9 = rm; - auto fp_vector_unary_op_3714_arg10 = ret_val_sew_3715; + InvokeNode* call_sew_3731; + x86::Gp ret_val_sew_3731 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3731, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3730; + auto fp_vector_unary_op_3730_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3730_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3730_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3730_arg9 = rm; + auto fp_vector_unary_op_3730_arg10 = ret_val_sew_3731; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3714, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3715, 0, reinterpret_cast(this)); - setRet(call_sew_3715, 0, ret_val_sew_3715); - setArg(call_fp_vector_unary_op_3714, 0, V); - setArg(call_fp_vector_unary_op_3714, 1, 18); - setArg(call_fp_vector_unary_op_3714, 2, 3); - setArg(call_fp_vector_unary_op_3714, 3, fp_vector_unary_op_3714_arg3); - setArg(call_fp_vector_unary_op_3714, 4, fp_vector_unary_op_3714_arg4); - setArg(call_fp_vector_unary_op_3714, 5, fp_vector_unary_op_3714_arg5); - setArg(call_fp_vector_unary_op_3714, 6, vm); - setArg(call_fp_vector_unary_op_3714, 7, vd); - setArg(call_fp_vector_unary_op_3714, 8, vs2); - setArg(call_fp_vector_unary_op_3714, 9, fp_vector_unary_op_3714_arg9); - setArg(call_fp_vector_unary_op_3714, 10, fp_vector_unary_op_3714_arg10); + cc.invoke(&call_fp_vector_unary_op_3730, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3731, 0, reinterpret_cast(this)); + setRet(call_sew_3731, 0, ret_val_sew_3731); + setArg(call_fp_vector_unary_op_3730, 0, V); + setArg(call_fp_vector_unary_op_3730, 1, 18); + setArg(call_fp_vector_unary_op_3730, 2, 3); + setArg(call_fp_vector_unary_op_3730, 3, fp_vector_unary_op_3730_arg3); + setArg(call_fp_vector_unary_op_3730, 4, fp_vector_unary_op_3730_arg4); + setArg(call_fp_vector_unary_op_3730, 5, fp_vector_unary_op_3730_arg5); + setArg(call_fp_vector_unary_op_3730, 6, vm); + setArg(call_fp_vector_unary_op_3730, 7, vd); + setArg(call_fp_vector_unary_op_3730, 8, vs2); + setArg(call_fp_vector_unary_op_3730, 9, fp_vector_unary_op_3730_arg9); + setArg(call_fp_vector_unary_op_3730, 10, fp_vector_unary_op_3730_arg10); } cc.bind(label_merge); } - auto tmp3716 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3716, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3716, 32, false) - , traits::vstart); + auto tmp3732 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3732, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3732, traits::vstart); } cc.bind(label_merge); } @@ -83913,278 +83357,6 @@ template class vm_impl : public iss::asmjit::vm_base { mov(cc, jh.next_pc, pc.val); cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); - gen_instr_prologue(jh); - /*generate behavior*/ - InvokeNode* call_get_sew_pow_3717; - x86::Gp ret_val_get_sew_pow_3717 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3717, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3718 = get_reg(cc, 8, false); - mov(cc, tmp3718, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3718, (ret_val_get_sew_pow_3717))), 8, false), ~ 1); - setArg(call_get_sew_pow_3717, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3717, 0, ret_val_get_sew_pow_3717); - InvokeNode* call_get_lmul_pow_3719; - x86::Gp ret_val_get_lmul_pow_3719 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3719, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3719; - setArg(call_get_lmul_pow_3719, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3719, 0, ret_val_get_lmul_pow_3719); - auto SEW_widen = gen_ext(cc, - (gen_operation(cc, umul, SEW, 2)), 8, false); - auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); - { - auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3720; - auto illegal_fp_variable_width_3720_arg2 = SEW; - auto illegal_fp_variable_width_3720_arg3 = rm; - auto illegal_fp_variable_width_3720_arg4 = SEW_widen; - auto illegal_fp_variable_width_3720_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3720 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3720, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3721; - auto valid_reg_overlap_3721_arg2 = LMUL_pow; - auto valid_reg_overlap_3721_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3721 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3721, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3720, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3721)); - setArg(call_illegal_fp_variable_width_3720, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3720, 1, vd); - setArg(call_illegal_fp_variable_width_3720, 2, vm); - setArg(call_illegal_fp_variable_width_3720, 3, illegal_fp_variable_width_3720_arg2); - setArg(call_illegal_fp_variable_width_3720, 4, illegal_fp_variable_width_3720_arg3); - setArg(call_illegal_fp_variable_width_3720, 5, illegal_fp_variable_width_3720_arg4); - setArg(call_illegal_fp_variable_width_3720, 6, illegal_fp_variable_width_3720_arg5); - setRet(call_illegal_fp_variable_width_3720, 0, ret_val_illegal_fp_variable_width_3720); - setArg(call_valid_reg_overlap_3721, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3721, 1, vs2); - setArg(call_valid_reg_overlap_3721, 2, vd); - setArg(call_valid_reg_overlap_3721, 3, valid_reg_overlap_3721_arg2); - setArg(call_valid_reg_overlap_3721, 4, valid_reg_overlap_3721_arg3); - setRet(call_valid_reg_overlap_3721, 0, ret_val_valid_reg_overlap_3721); - cmp(cc, cond, 0); - auto label_else = cc.newLabel(); - cc.je(label_else); - { - gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); - } - cc.jmp(label_merge); - cc.bind(label_else); - { - { - auto label_merge = cc.newLabel(); - auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); - cmp(cc, cond, 0); - cc.je(label_merge); - { - InvokeNode* call_sew_3723; - x86::Gp ret_val_sew_3723 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3723, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_w_3722; - auto fp_vector_unary_w_3722_arg2 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_w_3722_arg3 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_w_3722_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_w_3722_arg8 = rm; - auto fp_vector_unary_w_3722_arg9 = ret_val_sew_3723; - auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_w_3722, &fp_vector_unary_w, FuncSignature::build()); - setArg(call_sew_3723, 0, reinterpret_cast(this)); - setRet(call_sew_3723, 0, ret_val_sew_3723); - setArg(call_fp_vector_unary_w_3722, 0, V); - setArg(call_fp_vector_unary_w_3722, 1, 8); - setArg(call_fp_vector_unary_w_3722, 2, fp_vector_unary_w_3722_arg2); - setArg(call_fp_vector_unary_w_3722, 3, fp_vector_unary_w_3722_arg3); - setArg(call_fp_vector_unary_w_3722, 4, fp_vector_unary_w_3722_arg4); - setArg(call_fp_vector_unary_w_3722, 5, vm); - setArg(call_fp_vector_unary_w_3722, 6, vd); - setArg(call_fp_vector_unary_w_3722, 7, vs2); - setArg(call_fp_vector_unary_w_3722, 8, fp_vector_unary_w_3722_arg8); - setArg(call_fp_vector_unary_w_3722, 9, fp_vector_unary_w_3722_arg9); - } - cc.bind(label_merge); - } - auto tmp3724 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3724, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3724, 32, false) - , traits::vstart); - } - cc.bind(label_merge); - } - auto returnValue = CONT; - - gen_sync(jh, POST_SYNC, 772); - gen_instr_epilogue(jh); - return returnValue; - } - - /* instruction 773: VFWCVT__X__F__V */ - continuation_e __vfwcvt__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ - uint64_t PC = pc.val; - uint8_t vd = ((bit_sub<7,5>(instr))); - uint8_t vs2 = ((bit_sub<20,5>(instr))); - uint8_t vm = ((bit_sub<25,1>(instr))); - if(this->disass_enabled){ - /* generate disass */ - - auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.x.f.v"), - fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); - InvokeNode* call_print_disass; - char* mnemonic_ptr = strdup(mnemonic.c_str()); - jh.disass_collection.push_back(mnemonic_ptr); - jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); - call_print_disass->setArg(0, jh.arch_if_ptr); - call_print_disass->setArg(1, pc.val); - call_print_disass->setArg(2, mnemonic_ptr); - - } - x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__X__F__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 773); - mov(cc, jh.pc, pc.val); - gen_set_tval(jh, instr); - pc = pc+4; - mov(cc, jh.next_pc, pc.val); - cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); - - gen_instr_prologue(jh); - /*generate behavior*/ - InvokeNode* call_get_sew_pow_3725; - x86::Gp ret_val_get_sew_pow_3725 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3725, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3726 = get_reg(cc, 8, false); - mov(cc, tmp3726, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3726, (ret_val_get_sew_pow_3725))), 8, false), ~ 1); - setArg(call_get_sew_pow_3725, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3725, 0, ret_val_get_sew_pow_3725); - InvokeNode* call_get_lmul_pow_3727; - x86::Gp ret_val_get_lmul_pow_3727 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3727, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3727; - setArg(call_get_lmul_pow_3727, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3727, 0, ret_val_get_lmul_pow_3727); - auto SEW_widen = gen_ext(cc, - (gen_operation(cc, umul, SEW, 2)), 8, false); - auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); - { - auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3728; - auto illegal_fp_variable_width_3728_arg2 = SEW; - auto illegal_fp_variable_width_3728_arg3 = rm; - auto illegal_fp_variable_width_3728_arg4 = SEW_widen; - auto illegal_fp_variable_width_3728_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3728 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3728, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3729; - auto valid_reg_overlap_3729_arg2 = LMUL_pow; - auto valid_reg_overlap_3729_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3729 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3729, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3728, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3729)); - setArg(call_illegal_fp_variable_width_3728, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3728, 1, vd); - setArg(call_illegal_fp_variable_width_3728, 2, vm); - setArg(call_illegal_fp_variable_width_3728, 3, illegal_fp_variable_width_3728_arg2); - setArg(call_illegal_fp_variable_width_3728, 4, illegal_fp_variable_width_3728_arg3); - setArg(call_illegal_fp_variable_width_3728, 5, illegal_fp_variable_width_3728_arg4); - setArg(call_illegal_fp_variable_width_3728, 6, illegal_fp_variable_width_3728_arg5); - setRet(call_illegal_fp_variable_width_3728, 0, ret_val_illegal_fp_variable_width_3728); - setArg(call_valid_reg_overlap_3729, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3729, 1, vs2); - setArg(call_valid_reg_overlap_3729, 2, vd); - setArg(call_valid_reg_overlap_3729, 3, valid_reg_overlap_3729_arg2); - setArg(call_valid_reg_overlap_3729, 4, valid_reg_overlap_3729_arg3); - setRet(call_valid_reg_overlap_3729, 0, ret_val_valid_reg_overlap_3729); - cmp(cc, cond, 0); - auto label_else = cc.newLabel(); - cc.je(label_else); - { - gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); - } - cc.jmp(label_merge); - cc.bind(label_else); - { - { - auto label_merge = cc.newLabel(); - auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); - cmp(cc, cond, 0); - cc.je(label_merge); - { - InvokeNode* call_sew_3731; - x86::Gp ret_val_sew_3731 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3731, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_w_3730; - auto fp_vector_unary_w_3730_arg2 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_w_3730_arg3 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_w_3730_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_w_3730_arg8 = rm; - auto fp_vector_unary_w_3730_arg9 = ret_val_sew_3731; - auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_w_3730, &fp_vector_unary_w, FuncSignature::build()); - setArg(call_sew_3731, 0, reinterpret_cast(this)); - setRet(call_sew_3731, 0, ret_val_sew_3731); - setArg(call_fp_vector_unary_w_3730, 0, V); - setArg(call_fp_vector_unary_w_3730, 1, 9); - setArg(call_fp_vector_unary_w_3730, 2, fp_vector_unary_w_3730_arg2); - setArg(call_fp_vector_unary_w_3730, 3, fp_vector_unary_w_3730_arg3); - setArg(call_fp_vector_unary_w_3730, 4, fp_vector_unary_w_3730_arg4); - setArg(call_fp_vector_unary_w_3730, 5, vm); - setArg(call_fp_vector_unary_w_3730, 6, vd); - setArg(call_fp_vector_unary_w_3730, 7, vs2); - setArg(call_fp_vector_unary_w_3730, 8, fp_vector_unary_w_3730_arg8); - setArg(call_fp_vector_unary_w_3730, 9, fp_vector_unary_w_3730_arg9); - } - cc.bind(label_merge); - } - auto tmp3732 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3732, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3732, 32, false) - , traits::vstart); - } - cc.bind(label_merge); - } - auto returnValue = CONT; - - gen_sync(jh, POST_SYNC, 773); - gen_instr_epilogue(jh); - return returnValue; - } - - /* instruction 774: VFWCVT__RTZ__XU__F__V */ - continuation_e __vfwcvt__rtz__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ - uint64_t PC = pc.val; - uint8_t vd = ((bit_sub<7,5>(instr))); - uint8_t vs2 = ((bit_sub<20,5>(instr))); - uint8_t vm = ((bit_sub<25,1>(instr))); - if(this->disass_enabled){ - /* generate disass */ - - auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.xu.f.v"), - fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); - InvokeNode* call_print_disass; - char* mnemonic_ptr = strdup(mnemonic.c_str()); - jh.disass_collection.push_back(mnemonic_ptr); - jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); - call_print_disass->setArg(0, jh.arch_if_ptr); - call_print_disass->setArg(1, pc.val); - call_print_disass->setArg(2, mnemonic_ptr); - - } - x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__RTZ__XU__F__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 774); - mov(cc, jh.pc, pc.val); - gen_set_tval(jh, instr); - pc = pc+4; - mov(cc, jh.next_pc, pc.val); - cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); - gen_instr_prologue(jh); /*generate behavior*/ InvokeNode* call_get_sew_pow_3733; @@ -84205,11 +83377,12 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = 1; + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3736; auto illegal_fp_variable_width_3736_arg2 = SEW; + auto illegal_fp_variable_width_3736_arg3 = rm; auto illegal_fp_variable_width_3736_arg4 = SEW_widen; auto illegal_fp_variable_width_3736_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3736 = get_reg_Gp(cc, 8, false); @@ -84224,7 +83397,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3736, 1, vd); setArg(call_illegal_fp_variable_width_3736, 2, vm); setArg(call_illegal_fp_variable_width_3736, 3, illegal_fp_variable_width_3736_arg2); - setArg(call_illegal_fp_variable_width_3736, 4, rm); + setArg(call_illegal_fp_variable_width_3736, 4, illegal_fp_variable_width_3736_arg3); setArg(call_illegal_fp_variable_width_3736, 5, illegal_fp_variable_width_3736_arg4); setArg(call_illegal_fp_variable_width_3736, 6, illegal_fp_variable_width_3736_arg5); setRet(call_illegal_fp_variable_width_3736, 0, ret_val_illegal_fp_variable_width_3736); @@ -84256,41 +83429,40 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_w_3738_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_w_3738_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_w_3738_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3738_arg8 = rm; auto fp_vector_unary_w_3738_arg9 = ret_val_sew_3739; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_w_3738, &fp_vector_unary_w, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_w_3738, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3739, 0, reinterpret_cast(this)); setRet(call_sew_3739, 0, ret_val_sew_3739); setArg(call_fp_vector_unary_w_3738, 0, V); - setArg(call_fp_vector_unary_w_3738, 1, 14); + setArg(call_fp_vector_unary_w_3738, 1, 8); setArg(call_fp_vector_unary_w_3738, 2, fp_vector_unary_w_3738_arg2); setArg(call_fp_vector_unary_w_3738, 3, fp_vector_unary_w_3738_arg3); setArg(call_fp_vector_unary_w_3738, 4, fp_vector_unary_w_3738_arg4); setArg(call_fp_vector_unary_w_3738, 5, vm); setArg(call_fp_vector_unary_w_3738, 6, vd); setArg(call_fp_vector_unary_w_3738, 7, vs2); - setArg(call_fp_vector_unary_w_3738, 8, rm); + setArg(call_fp_vector_unary_w_3738, 8, fp_vector_unary_w_3738_arg8); setArg(call_fp_vector_unary_w_3738, 9, fp_vector_unary_w_3738_arg9); } cc.bind(label_merge); } - auto tmp3740 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3740, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3740, 32, false) - , traits::vstart); + auto tmp3740 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3740, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3740, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 774); + gen_sync(jh, POST_SYNC, 772); gen_instr_epilogue(jh); return returnValue; } - /* instruction 775: VFWCVT__RTZ__X__F__V */ - continuation_e __vfwcvt__rtz__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 773: VFWCVT__X__F__V */ + continuation_e __vfwcvt__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -84299,7 +83471,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.x.f.v"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.x.f.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -84311,8 +83483,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__RTZ__X__F__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 775); + cc.comment(fmt::format("VFWCVT__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 773); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -84339,11 +83511,12 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = 1; + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3744; auto illegal_fp_variable_width_3744_arg2 = SEW; + auto illegal_fp_variable_width_3744_arg3 = rm; auto illegal_fp_variable_width_3744_arg4 = SEW_widen; auto illegal_fp_variable_width_3744_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3744 = get_reg_Gp(cc, 8, false); @@ -84358,7 +83531,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3744, 1, vd); setArg(call_illegal_fp_variable_width_3744, 2, vm); setArg(call_illegal_fp_variable_width_3744, 3, illegal_fp_variable_width_3744_arg2); - setArg(call_illegal_fp_variable_width_3744, 4, rm); + setArg(call_illegal_fp_variable_width_3744, 4, illegal_fp_variable_width_3744_arg3); setArg(call_illegal_fp_variable_width_3744, 5, illegal_fp_variable_width_3744_arg4); setArg(call_illegal_fp_variable_width_3744, 6, illegal_fp_variable_width_3744_arg5); setRet(call_illegal_fp_variable_width_3744, 0, ret_val_illegal_fp_variable_width_3744); @@ -84390,41 +83563,40 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_w_3746_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_w_3746_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_w_3746_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3746_arg8 = rm; auto fp_vector_unary_w_3746_arg9 = ret_val_sew_3747; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_w_3746, &fp_vector_unary_w, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_w_3746, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3747, 0, reinterpret_cast(this)); setRet(call_sew_3747, 0, ret_val_sew_3747); setArg(call_fp_vector_unary_w_3746, 0, V); - setArg(call_fp_vector_unary_w_3746, 1, 15); + setArg(call_fp_vector_unary_w_3746, 1, 9); setArg(call_fp_vector_unary_w_3746, 2, fp_vector_unary_w_3746_arg2); setArg(call_fp_vector_unary_w_3746, 3, fp_vector_unary_w_3746_arg3); setArg(call_fp_vector_unary_w_3746, 4, fp_vector_unary_w_3746_arg4); setArg(call_fp_vector_unary_w_3746, 5, vm); setArg(call_fp_vector_unary_w_3746, 6, vd); setArg(call_fp_vector_unary_w_3746, 7, vs2); - setArg(call_fp_vector_unary_w_3746, 8, rm); + setArg(call_fp_vector_unary_w_3746, 8, fp_vector_unary_w_3746_arg8); setArg(call_fp_vector_unary_w_3746, 9, fp_vector_unary_w_3746_arg9); } cc.bind(label_merge); } - auto tmp3748 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3748, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3748, 32, false) - , traits::vstart); + auto tmp3748 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3748, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3748, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 775); + gen_sync(jh, POST_SYNC, 773); gen_instr_epilogue(jh); return returnValue; } - /* instruction 776: VFWCVT__F__XU__V */ - continuation_e __vfwcvt__f__xu__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 774: VFWCVT__RTZ__XU__F__V */ + continuation_e __vfwcvt__rtz__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -84433,7 +83605,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.xu.v"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.xu.f.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -84445,8 +83617,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__F__XU__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 776); + cc.comment(fmt::format("VFWCVT__RTZ__XU__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 774); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -84473,12 +83645,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = 1; { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3752; auto illegal_fp_variable_width_3752_arg2 = SEW; - auto illegal_fp_variable_width_3752_arg3 = rm; auto illegal_fp_variable_width_3752_arg4 = SEW_widen; auto illegal_fp_variable_width_3752_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3752 = get_reg_Gp(cc, 8, false); @@ -84493,7 +83664,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3752, 1, vd); setArg(call_illegal_fp_variable_width_3752, 2, vm); setArg(call_illegal_fp_variable_width_3752, 3, illegal_fp_variable_width_3752_arg2); - setArg(call_illegal_fp_variable_width_3752, 4, illegal_fp_variable_width_3752_arg3); + setArg(call_illegal_fp_variable_width_3752, 4, rm); setArg(call_illegal_fp_variable_width_3752, 5, illegal_fp_variable_width_3752_arg4); setArg(call_illegal_fp_variable_width_3752, 6, illegal_fp_variable_width_3752_arg5); setRet(call_illegal_fp_variable_width_3752, 0, ret_val_illegal_fp_variable_width_3752); @@ -84525,42 +83696,39 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_w_3754_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_w_3754_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_w_3754_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_w_3754_arg8 = rm; auto fp_vector_unary_w_3754_arg9 = ret_val_sew_3755; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_w_3754, &fp_vector_unary_w, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_w_3754, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3755, 0, reinterpret_cast(this)); setRet(call_sew_3755, 0, ret_val_sew_3755); setArg(call_fp_vector_unary_w_3754, 0, V); - setArg(call_fp_vector_unary_w_3754, 1, 10); + setArg(call_fp_vector_unary_w_3754, 1, 14); setArg(call_fp_vector_unary_w_3754, 2, fp_vector_unary_w_3754_arg2); setArg(call_fp_vector_unary_w_3754, 3, fp_vector_unary_w_3754_arg3); setArg(call_fp_vector_unary_w_3754, 4, fp_vector_unary_w_3754_arg4); setArg(call_fp_vector_unary_w_3754, 5, vm); setArg(call_fp_vector_unary_w_3754, 6, vd); setArg(call_fp_vector_unary_w_3754, 7, vs2); - setArg(call_fp_vector_unary_w_3754, 8, fp_vector_unary_w_3754_arg8); + setArg(call_fp_vector_unary_w_3754, 8, rm); setArg(call_fp_vector_unary_w_3754, 9, fp_vector_unary_w_3754_arg9); } cc.bind(label_merge); } - auto tmp3756 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3756, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3756, 32, false) - , traits::vstart); + auto tmp3756 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3756, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3756, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 776); + gen_sync(jh, POST_SYNC, 774); gen_instr_epilogue(jh); return returnValue; } - /* instruction 777: VFWCVT__F__X__V */ - continuation_e __vfwcvt__f__x__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 775: VFWCVT__RTZ__X__F__V */ + continuation_e __vfwcvt__rtz__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -84569,7 +83737,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.x.v"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.x.f.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -84581,8 +83749,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__F__X__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 777); + cc.comment(fmt::format("VFWCVT__RTZ__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 775); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -84609,12 +83777,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = 1; { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3760; auto illegal_fp_variable_width_3760_arg2 = SEW; - auto illegal_fp_variable_width_3760_arg3 = rm; auto illegal_fp_variable_width_3760_arg4 = SEW_widen; auto illegal_fp_variable_width_3760_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3760 = get_reg_Gp(cc, 8, false); @@ -84629,7 +83796,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3760, 1, vd); setArg(call_illegal_fp_variable_width_3760, 2, vm); setArg(call_illegal_fp_variable_width_3760, 3, illegal_fp_variable_width_3760_arg2); - setArg(call_illegal_fp_variable_width_3760, 4, illegal_fp_variable_width_3760_arg3); + setArg(call_illegal_fp_variable_width_3760, 4, rm); setArg(call_illegal_fp_variable_width_3760, 5, illegal_fp_variable_width_3760_arg4); setArg(call_illegal_fp_variable_width_3760, 6, illegal_fp_variable_width_3760_arg5); setRet(call_illegal_fp_variable_width_3760, 0, ret_val_illegal_fp_variable_width_3760); @@ -84661,42 +83828,39 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_w_3762_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_w_3762_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_w_3762_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_w_3762_arg8 = rm; auto fp_vector_unary_w_3762_arg9 = ret_val_sew_3763; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_w_3762, &fp_vector_unary_w, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_w_3762, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3763, 0, reinterpret_cast(this)); setRet(call_sew_3763, 0, ret_val_sew_3763); setArg(call_fp_vector_unary_w_3762, 0, V); - setArg(call_fp_vector_unary_w_3762, 1, 11); + setArg(call_fp_vector_unary_w_3762, 1, 15); setArg(call_fp_vector_unary_w_3762, 2, fp_vector_unary_w_3762_arg2); setArg(call_fp_vector_unary_w_3762, 3, fp_vector_unary_w_3762_arg3); setArg(call_fp_vector_unary_w_3762, 4, fp_vector_unary_w_3762_arg4); setArg(call_fp_vector_unary_w_3762, 5, vm); setArg(call_fp_vector_unary_w_3762, 6, vd); setArg(call_fp_vector_unary_w_3762, 7, vs2); - setArg(call_fp_vector_unary_w_3762, 8, fp_vector_unary_w_3762_arg8); + setArg(call_fp_vector_unary_w_3762, 8, rm); setArg(call_fp_vector_unary_w_3762, 9, fp_vector_unary_w_3762_arg9); } cc.bind(label_merge); } - auto tmp3764 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3764, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3764, 32, false) - , traits::vstart); + auto tmp3764 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3764, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3764, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 777); + gen_sync(jh, POST_SYNC, 775); gen_instr_epilogue(jh); return returnValue; } - /* instruction 778: VFWCVT__F__F__V */ - continuation_e __vfwcvt__f__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 776: VFWCVT__F__XU__V */ + continuation_e __vfwcvt__f__xu__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -84705,7 +83869,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.f.v"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.xu.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -84717,8 +83881,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__F__F__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 778); + cc.comment(fmt::format("VFWCVT__F__XU__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 776); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -84800,11 +83964,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_w_3770_arg8 = rm; auto fp_vector_unary_w_3770_arg9 = ret_val_sew_3771; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_w_3770, &fp_vector_unary_w, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_w_3770, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3771, 0, reinterpret_cast(this)); setRet(call_sew_3771, 0, ret_val_sew_3771); setArg(call_fp_vector_unary_w_3770, 0, V); - setArg(call_fp_vector_unary_w_3770, 1, 12); + setArg(call_fp_vector_unary_w_3770, 1, 10); setArg(call_fp_vector_unary_w_3770, 2, fp_vector_unary_w_3770_arg2); setArg(call_fp_vector_unary_w_3770, 3, fp_vector_unary_w_3770_arg3); setArg(call_fp_vector_unary_w_3770, 4, fp_vector_unary_w_3770_arg4); @@ -84816,23 +83980,21 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp3772 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3772, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3772, 32, false) - , traits::vstart); + auto tmp3772 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3772, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3772, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 778); + gen_sync(jh, POST_SYNC, 776); gen_instr_epilogue(jh); return returnValue; } - /* instruction 779: VFNCVT__X__F__W */ - continuation_e __vfncvt__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 777: VFWCVT__F__X__V */ + continuation_e __vfwcvt__f__x__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -84841,7 +84003,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.x.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.x.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -84853,8 +84015,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__X__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 779); + cc.comment(fmt::format("VFWCVT__F__X__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 777); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -84892,8 +84054,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_illegal_fp_variable_width_3776 = get_reg_Gp(cc, 8, false); cc.invoke(&call_illegal_fp_variable_width_3776, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); InvokeNode* call_valid_reg_overlap_3777; - auto valid_reg_overlap_3777_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_3777_arg3 = LMUL_pow; + auto valid_reg_overlap_3777_arg2 = LMUL_pow; + auto valid_reg_overlap_3777_arg3 = LMUL_pow_widen; x86::Gp ret_val_valid_reg_overlap_3777 = get_reg_Gp(cc, 8, false); cc.invoke(&call_valid_reg_overlap_3777, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3776, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3777)); @@ -84929,46 +84091,44 @@ template class vm_impl : public iss::asmjit::vm_base { InvokeNode* call_sew_3779; x86::Gp ret_val_sew_3779 = get_reg_Gp(cc, 8, false); cc.invoke(&call_sew_3779, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_n_3778; - auto fp_vector_unary_n_3778_arg2 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_n_3778_arg3 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_n_3778_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_n_3778_arg8 = rm; - auto fp_vector_unary_n_3778_arg9 = ret_val_sew_3779; + InvokeNode* call_fp_vector_unary_w_3778; + auto fp_vector_unary_w_3778_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3778_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3778_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3778_arg8 = rm; + auto fp_vector_unary_w_3778_arg9 = ret_val_sew_3779; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_n_3778, &fp_vector_unary_n, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_w_3778, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3779, 0, reinterpret_cast(this)); setRet(call_sew_3779, 0, ret_val_sew_3779); - setArg(call_fp_vector_unary_n_3778, 0, V); - setArg(call_fp_vector_unary_n_3778, 1, 17); - setArg(call_fp_vector_unary_n_3778, 2, fp_vector_unary_n_3778_arg2); - setArg(call_fp_vector_unary_n_3778, 3, fp_vector_unary_n_3778_arg3); - setArg(call_fp_vector_unary_n_3778, 4, fp_vector_unary_n_3778_arg4); - setArg(call_fp_vector_unary_n_3778, 5, vm); - setArg(call_fp_vector_unary_n_3778, 6, vd); - setArg(call_fp_vector_unary_n_3778, 7, vs2); - setArg(call_fp_vector_unary_n_3778, 8, fp_vector_unary_n_3778_arg8); - setArg(call_fp_vector_unary_n_3778, 9, fp_vector_unary_n_3778_arg9); + setArg(call_fp_vector_unary_w_3778, 0, V); + setArg(call_fp_vector_unary_w_3778, 1, 11); + setArg(call_fp_vector_unary_w_3778, 2, fp_vector_unary_w_3778_arg2); + setArg(call_fp_vector_unary_w_3778, 3, fp_vector_unary_w_3778_arg3); + setArg(call_fp_vector_unary_w_3778, 4, fp_vector_unary_w_3778_arg4); + setArg(call_fp_vector_unary_w_3778, 5, vm); + setArg(call_fp_vector_unary_w_3778, 6, vd); + setArg(call_fp_vector_unary_w_3778, 7, vs2); + setArg(call_fp_vector_unary_w_3778, 8, fp_vector_unary_w_3778_arg8); + setArg(call_fp_vector_unary_w_3778, 9, fp_vector_unary_w_3778_arg9); } cc.bind(label_merge); } - auto tmp3780 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3780, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3780, 32, false) - , traits::vstart); + auto tmp3780 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3780, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3780, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 779); + gen_sync(jh, POST_SYNC, 777); gen_instr_epilogue(jh); return returnValue; } - /* instruction 780: VFNCVT__XU__F__W */ - continuation_e __vfncvt__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 778: VFWCVT__F__F__V */ + continuation_e __vfwcvt__f__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -84977,7 +84137,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.xu.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.f.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -84989,8 +84149,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__XU__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 780); + cc.comment(fmt::format("VFWCVT__F__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 778); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -85028,8 +84188,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_illegal_fp_variable_width_3784 = get_reg_Gp(cc, 8, false); cc.invoke(&call_illegal_fp_variable_width_3784, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); InvokeNode* call_valid_reg_overlap_3785; - auto valid_reg_overlap_3785_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_3785_arg3 = LMUL_pow; + auto valid_reg_overlap_3785_arg2 = LMUL_pow; + auto valid_reg_overlap_3785_arg3 = LMUL_pow_widen; x86::Gp ret_val_valid_reg_overlap_3785 = get_reg_Gp(cc, 8, false); cc.invoke(&call_valid_reg_overlap_3785, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3784, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3785)); @@ -85065,46 +84225,44 @@ template class vm_impl : public iss::asmjit::vm_base { InvokeNode* call_sew_3787; x86::Gp ret_val_sew_3787 = get_reg_Gp(cc, 8, false); cc.invoke(&call_sew_3787, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_n_3786; - auto fp_vector_unary_n_3786_arg2 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_n_3786_arg3 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_n_3786_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_n_3786_arg8 = rm; - auto fp_vector_unary_n_3786_arg9 = ret_val_sew_3787; + InvokeNode* call_fp_vector_unary_w_3786; + auto fp_vector_unary_w_3786_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3786_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3786_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3786_arg8 = rm; + auto fp_vector_unary_w_3786_arg9 = ret_val_sew_3787; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_n_3786, &fp_vector_unary_n, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_w_3786, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3787, 0, reinterpret_cast(this)); setRet(call_sew_3787, 0, ret_val_sew_3787); - setArg(call_fp_vector_unary_n_3786, 0, V); - setArg(call_fp_vector_unary_n_3786, 1, 16); - setArg(call_fp_vector_unary_n_3786, 2, fp_vector_unary_n_3786_arg2); - setArg(call_fp_vector_unary_n_3786, 3, fp_vector_unary_n_3786_arg3); - setArg(call_fp_vector_unary_n_3786, 4, fp_vector_unary_n_3786_arg4); - setArg(call_fp_vector_unary_n_3786, 5, vm); - setArg(call_fp_vector_unary_n_3786, 6, vd); - setArg(call_fp_vector_unary_n_3786, 7, vs2); - setArg(call_fp_vector_unary_n_3786, 8, fp_vector_unary_n_3786_arg8); - setArg(call_fp_vector_unary_n_3786, 9, fp_vector_unary_n_3786_arg9); + setArg(call_fp_vector_unary_w_3786, 0, V); + setArg(call_fp_vector_unary_w_3786, 1, 12); + setArg(call_fp_vector_unary_w_3786, 2, fp_vector_unary_w_3786_arg2); + setArg(call_fp_vector_unary_w_3786, 3, fp_vector_unary_w_3786_arg3); + setArg(call_fp_vector_unary_w_3786, 4, fp_vector_unary_w_3786_arg4); + setArg(call_fp_vector_unary_w_3786, 5, vm); + setArg(call_fp_vector_unary_w_3786, 6, vd); + setArg(call_fp_vector_unary_w_3786, 7, vs2); + setArg(call_fp_vector_unary_w_3786, 8, fp_vector_unary_w_3786_arg8); + setArg(call_fp_vector_unary_w_3786, 9, fp_vector_unary_w_3786_arg9); } cc.bind(label_merge); } - auto tmp3788 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3788, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3788, 32, false) - , traits::vstart); + auto tmp3788 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3788, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3788, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 780); + gen_sync(jh, POST_SYNC, 778); gen_instr_epilogue(jh); return returnValue; } - /* instruction 781: VFNCVT__RTZ__XU__F__W */ - continuation_e __vfncvt__rtz__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 779: VFNCVT__X__F__W */ + continuation_e __vfncvt__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -85113,7 +84271,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.xu.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.x.f.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -85125,8 +84283,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__RTZ__XU__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 781); + cc.comment(fmt::format("VFNCVT__X__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 779); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -85153,11 +84311,12 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = 1; + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3792; auto illegal_fp_variable_width_3792_arg2 = SEW; + auto illegal_fp_variable_width_3792_arg3 = rm; auto illegal_fp_variable_width_3792_arg4 = SEW_widen; auto illegal_fp_variable_width_3792_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3792 = get_reg_Gp(cc, 8, false); @@ -85172,7 +84331,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3792, 1, vd); setArg(call_illegal_fp_variable_width_3792, 2, vm); setArg(call_illegal_fp_variable_width_3792, 3, illegal_fp_variable_width_3792_arg2); - setArg(call_illegal_fp_variable_width_3792, 4, rm); + setArg(call_illegal_fp_variable_width_3792, 4, illegal_fp_variable_width_3792_arg3); setArg(call_illegal_fp_variable_width_3792, 5, illegal_fp_variable_width_3792_arg4); setArg(call_illegal_fp_variable_width_3792, 6, illegal_fp_variable_width_3792_arg5); setRet(call_illegal_fp_variable_width_3792, 0, ret_val_illegal_fp_variable_width_3792); @@ -85204,41 +84363,40 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3794_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_n_3794_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_n_3794_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3794_arg8 = rm; auto fp_vector_unary_n_3794_arg9 = ret_val_sew_3795; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_n_3794, &fp_vector_unary_n, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_n_3794, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3795, 0, reinterpret_cast(this)); setRet(call_sew_3795, 0, ret_val_sew_3795); setArg(call_fp_vector_unary_n_3794, 0, V); - setArg(call_fp_vector_unary_n_3794, 1, 22); + setArg(call_fp_vector_unary_n_3794, 1, 17); setArg(call_fp_vector_unary_n_3794, 2, fp_vector_unary_n_3794_arg2); setArg(call_fp_vector_unary_n_3794, 3, fp_vector_unary_n_3794_arg3); setArg(call_fp_vector_unary_n_3794, 4, fp_vector_unary_n_3794_arg4); setArg(call_fp_vector_unary_n_3794, 5, vm); setArg(call_fp_vector_unary_n_3794, 6, vd); setArg(call_fp_vector_unary_n_3794, 7, vs2); - setArg(call_fp_vector_unary_n_3794, 8, rm); + setArg(call_fp_vector_unary_n_3794, 8, fp_vector_unary_n_3794_arg8); setArg(call_fp_vector_unary_n_3794, 9, fp_vector_unary_n_3794_arg9); } cc.bind(label_merge); } - auto tmp3796 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3796, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3796, 32, false) - , traits::vstart); + auto tmp3796 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3796, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3796, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 781); + gen_sync(jh, POST_SYNC, 779); gen_instr_epilogue(jh); return returnValue; } - /* instruction 782: VFNCVT__RTZ__X__F__W */ - continuation_e __vfncvt__rtz__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 780: VFNCVT__XU__F__W */ + continuation_e __vfncvt__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -85247,7 +84405,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.x.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.xu.f.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -85259,8 +84417,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__RTZ__X__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 782); + cc.comment(fmt::format("VFNCVT__XU__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 780); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -85287,11 +84445,12 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = 1; + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3800; auto illegal_fp_variable_width_3800_arg2 = SEW; + auto illegal_fp_variable_width_3800_arg3 = rm; auto illegal_fp_variable_width_3800_arg4 = SEW_widen; auto illegal_fp_variable_width_3800_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3800 = get_reg_Gp(cc, 8, false); @@ -85306,7 +84465,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3800, 1, vd); setArg(call_illegal_fp_variable_width_3800, 2, vm); setArg(call_illegal_fp_variable_width_3800, 3, illegal_fp_variable_width_3800_arg2); - setArg(call_illegal_fp_variable_width_3800, 4, rm); + setArg(call_illegal_fp_variable_width_3800, 4, illegal_fp_variable_width_3800_arg3); setArg(call_illegal_fp_variable_width_3800, 5, illegal_fp_variable_width_3800_arg4); setArg(call_illegal_fp_variable_width_3800, 6, illegal_fp_variable_width_3800_arg5); setRet(call_illegal_fp_variable_width_3800, 0, ret_val_illegal_fp_variable_width_3800); @@ -85338,41 +84497,40 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3802_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_n_3802_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_n_3802_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3802_arg8 = rm; auto fp_vector_unary_n_3802_arg9 = ret_val_sew_3803; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_n_3802, &fp_vector_unary_n, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_n_3802, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3803, 0, reinterpret_cast(this)); setRet(call_sew_3803, 0, ret_val_sew_3803); setArg(call_fp_vector_unary_n_3802, 0, V); - setArg(call_fp_vector_unary_n_3802, 1, 23); + setArg(call_fp_vector_unary_n_3802, 1, 16); setArg(call_fp_vector_unary_n_3802, 2, fp_vector_unary_n_3802_arg2); setArg(call_fp_vector_unary_n_3802, 3, fp_vector_unary_n_3802_arg3); setArg(call_fp_vector_unary_n_3802, 4, fp_vector_unary_n_3802_arg4); setArg(call_fp_vector_unary_n_3802, 5, vm); setArg(call_fp_vector_unary_n_3802, 6, vd); setArg(call_fp_vector_unary_n_3802, 7, vs2); - setArg(call_fp_vector_unary_n_3802, 8, rm); + setArg(call_fp_vector_unary_n_3802, 8, fp_vector_unary_n_3802_arg8); setArg(call_fp_vector_unary_n_3802, 9, fp_vector_unary_n_3802_arg9); } cc.bind(label_merge); } - auto tmp3804 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3804, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3804, 32, false) - , traits::vstart); + auto tmp3804 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3804, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3804, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 782); + gen_sync(jh, POST_SYNC, 780); gen_instr_epilogue(jh); return returnValue; } - /* instruction 783: VFNCVT__F__XU__W */ - continuation_e __vfncvt__f__xu__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 781: VFNCVT__RTZ__XU__F__W */ + continuation_e __vfncvt__rtz__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -85381,7 +84539,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.xu.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.xu.f.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -85393,8 +84551,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__F__XU__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 783); + cc.comment(fmt::format("VFNCVT__RTZ__XU__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 781); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -85421,12 +84579,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = 1; { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3808; auto illegal_fp_variable_width_3808_arg2 = SEW; - auto illegal_fp_variable_width_3808_arg3 = rm; auto illegal_fp_variable_width_3808_arg4 = SEW_widen; auto illegal_fp_variable_width_3808_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3808 = get_reg_Gp(cc, 8, false); @@ -85441,7 +84598,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3808, 1, vd); setArg(call_illegal_fp_variable_width_3808, 2, vm); setArg(call_illegal_fp_variable_width_3808, 3, illegal_fp_variable_width_3808_arg2); - setArg(call_illegal_fp_variable_width_3808, 4, illegal_fp_variable_width_3808_arg3); + setArg(call_illegal_fp_variable_width_3808, 4, rm); setArg(call_illegal_fp_variable_width_3808, 5, illegal_fp_variable_width_3808_arg4); setArg(call_illegal_fp_variable_width_3808, 6, illegal_fp_variable_width_3808_arg5); setRet(call_illegal_fp_variable_width_3808, 0, ret_val_illegal_fp_variable_width_3808); @@ -85473,42 +84630,39 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3810_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_n_3810_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_n_3810_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_n_3810_arg8 = rm; auto fp_vector_unary_n_3810_arg9 = ret_val_sew_3811; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_n_3810, &fp_vector_unary_n, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_n_3810, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3811, 0, reinterpret_cast(this)); setRet(call_sew_3811, 0, ret_val_sew_3811); setArg(call_fp_vector_unary_n_3810, 0, V); - setArg(call_fp_vector_unary_n_3810, 1, 18); + setArg(call_fp_vector_unary_n_3810, 1, 22); setArg(call_fp_vector_unary_n_3810, 2, fp_vector_unary_n_3810_arg2); setArg(call_fp_vector_unary_n_3810, 3, fp_vector_unary_n_3810_arg3); setArg(call_fp_vector_unary_n_3810, 4, fp_vector_unary_n_3810_arg4); setArg(call_fp_vector_unary_n_3810, 5, vm); setArg(call_fp_vector_unary_n_3810, 6, vd); setArg(call_fp_vector_unary_n_3810, 7, vs2); - setArg(call_fp_vector_unary_n_3810, 8, fp_vector_unary_n_3810_arg8); + setArg(call_fp_vector_unary_n_3810, 8, rm); setArg(call_fp_vector_unary_n_3810, 9, fp_vector_unary_n_3810_arg9); } cc.bind(label_merge); } - auto tmp3812 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3812, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3812, 32, false) - , traits::vstart); + auto tmp3812 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3812, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3812, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 783); + gen_sync(jh, POST_SYNC, 781); gen_instr_epilogue(jh); return returnValue; } - /* instruction 784: VFNCVT__F__X__W */ - continuation_e __vfncvt__f__x__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 782: VFNCVT__RTZ__X__F__W */ + continuation_e __vfncvt__rtz__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -85517,7 +84671,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.x.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.x.f.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -85529,8 +84683,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__F__X__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 784); + cc.comment(fmt::format("VFNCVT__RTZ__X__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 782); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -85557,12 +84711,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = 1; { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3816; auto illegal_fp_variable_width_3816_arg2 = SEW; - auto illegal_fp_variable_width_3816_arg3 = rm; auto illegal_fp_variable_width_3816_arg4 = SEW_widen; auto illegal_fp_variable_width_3816_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3816 = get_reg_Gp(cc, 8, false); @@ -85577,7 +84730,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3816, 1, vd); setArg(call_illegal_fp_variable_width_3816, 2, vm); setArg(call_illegal_fp_variable_width_3816, 3, illegal_fp_variable_width_3816_arg2); - setArg(call_illegal_fp_variable_width_3816, 4, illegal_fp_variable_width_3816_arg3); + setArg(call_illegal_fp_variable_width_3816, 4, rm); setArg(call_illegal_fp_variable_width_3816, 5, illegal_fp_variable_width_3816_arg4); setArg(call_illegal_fp_variable_width_3816, 6, illegal_fp_variable_width_3816_arg5); setRet(call_illegal_fp_variable_width_3816, 0, ret_val_illegal_fp_variable_width_3816); @@ -85609,42 +84762,39 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3818_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_n_3818_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_n_3818_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_n_3818_arg8 = rm; auto fp_vector_unary_n_3818_arg9 = ret_val_sew_3819; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_n_3818, &fp_vector_unary_n, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_n_3818, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3819, 0, reinterpret_cast(this)); setRet(call_sew_3819, 0, ret_val_sew_3819); setArg(call_fp_vector_unary_n_3818, 0, V); - setArg(call_fp_vector_unary_n_3818, 1, 19); + setArg(call_fp_vector_unary_n_3818, 1, 23); setArg(call_fp_vector_unary_n_3818, 2, fp_vector_unary_n_3818_arg2); setArg(call_fp_vector_unary_n_3818, 3, fp_vector_unary_n_3818_arg3); setArg(call_fp_vector_unary_n_3818, 4, fp_vector_unary_n_3818_arg4); setArg(call_fp_vector_unary_n_3818, 5, vm); setArg(call_fp_vector_unary_n_3818, 6, vd); setArg(call_fp_vector_unary_n_3818, 7, vs2); - setArg(call_fp_vector_unary_n_3818, 8, fp_vector_unary_n_3818_arg8); + setArg(call_fp_vector_unary_n_3818, 8, rm); setArg(call_fp_vector_unary_n_3818, 9, fp_vector_unary_n_3818_arg9); } cc.bind(label_merge); } - auto tmp3820 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3820, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3820, 32, false) - , traits::vstart); + auto tmp3820 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3820, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3820, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 784); + gen_sync(jh, POST_SYNC, 782); gen_instr_epilogue(jh); return returnValue; } - /* instruction 785: VFNCVT__F__F__W */ - continuation_e __vfncvt__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 783: VFNCVT__F__XU__W */ + continuation_e __vfncvt__f__xu__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -85653,7 +84803,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.xu.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -85665,8 +84815,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__F__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 785); + cc.comment(fmt::format("VFNCVT__F__XU__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 783); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -85748,11 +84898,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3826_arg8 = rm; auto fp_vector_unary_n_3826_arg9 = ret_val_sew_3827; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_n_3826, &fp_vector_unary_n, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_n_3826, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3827, 0, reinterpret_cast(this)); setRet(call_sew_3827, 0, ret_val_sew_3827); setArg(call_fp_vector_unary_n_3826, 0, V); - setArg(call_fp_vector_unary_n_3826, 1, 20); + setArg(call_fp_vector_unary_n_3826, 1, 18); setArg(call_fp_vector_unary_n_3826, 2, fp_vector_unary_n_3826_arg2); setArg(call_fp_vector_unary_n_3826, 3, fp_vector_unary_n_3826_arg3); setArg(call_fp_vector_unary_n_3826, 4, fp_vector_unary_n_3826_arg4); @@ -85764,23 +84914,21 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp3828 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3828, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3828, 32, false) - , traits::vstart); + auto tmp3828 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3828, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3828, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 785); + gen_sync(jh, POST_SYNC, 783); gen_instr_epilogue(jh); return returnValue; } - /* instruction 786: VFNCVT__ROD__F__F__W */ - continuation_e __vfncvt__rod__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 784: VFNCVT__F__X__W */ + continuation_e __vfncvt__f__x__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -85789,7 +84937,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rod.f.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.x.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -85801,8 +84949,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__ROD__F__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 786); + cc.comment(fmt::format("VFNCVT__F__X__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 784); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -85881,29 +85029,295 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3834_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_n_3834_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_n_3834_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3834_arg8 = rm; auto fp_vector_unary_n_3834_arg9 = ret_val_sew_3835; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_n_3834, &fp_vector_unary_n, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_n_3834, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3835, 0, reinterpret_cast(this)); setRet(call_sew_3835, 0, ret_val_sew_3835); setArg(call_fp_vector_unary_n_3834, 0, V); - setArg(call_fp_vector_unary_n_3834, 1, 21); + setArg(call_fp_vector_unary_n_3834, 1, 19); setArg(call_fp_vector_unary_n_3834, 2, fp_vector_unary_n_3834_arg2); setArg(call_fp_vector_unary_n_3834, 3, fp_vector_unary_n_3834_arg3); setArg(call_fp_vector_unary_n_3834, 4, fp_vector_unary_n_3834_arg4); setArg(call_fp_vector_unary_n_3834, 5, vm); setArg(call_fp_vector_unary_n_3834, 6, vd); setArg(call_fp_vector_unary_n_3834, 7, vs2); - setArg(call_fp_vector_unary_n_3834, 8, 6); + setArg(call_fp_vector_unary_n_3834, 8, fp_vector_unary_n_3834_arg8); setArg(call_fp_vector_unary_n_3834, 9, fp_vector_unary_n_3834_arg9); } cc.bind(label_merge); } - auto tmp3836 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3836, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3836, 32, false) - , traits::vstart); + auto tmp3836 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3836, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3836, traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 784); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 785: VFNCVT__F__F__W */ + continuation_e __vfncvt__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__F__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 785); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3837; + x86::Gp ret_val_get_sew_pow_3837 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3837, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3838 = get_reg(cc, 8, false); + mov(cc, tmp3838, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3838, (ret_val_get_sew_pow_3837))), 8, false), ~ 1); + setArg(call_get_sew_pow_3837, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3837, 0, ret_val_get_sew_pow_3837); + InvokeNode* call_get_lmul_pow_3839; + x86::Gp ret_val_get_lmul_pow_3839 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3839, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3839; + setArg(call_get_lmul_pow_3839, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3839, 0, ret_val_get_lmul_pow_3839); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3840; + auto illegal_fp_variable_width_3840_arg2 = SEW; + auto illegal_fp_variable_width_3840_arg3 = rm; + auto illegal_fp_variable_width_3840_arg4 = SEW_widen; + auto illegal_fp_variable_width_3840_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3840 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3840, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3841; + auto valid_reg_overlap_3841_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3841_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3841 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3841, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3840, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3841)); + setArg(call_illegal_fp_variable_width_3840, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3840, 1, vd); + setArg(call_illegal_fp_variable_width_3840, 2, vm); + setArg(call_illegal_fp_variable_width_3840, 3, illegal_fp_variable_width_3840_arg2); + setArg(call_illegal_fp_variable_width_3840, 4, illegal_fp_variable_width_3840_arg3); + setArg(call_illegal_fp_variable_width_3840, 5, illegal_fp_variable_width_3840_arg4); + setArg(call_illegal_fp_variable_width_3840, 6, illegal_fp_variable_width_3840_arg5); + setRet(call_illegal_fp_variable_width_3840, 0, ret_val_illegal_fp_variable_width_3840); + setArg(call_valid_reg_overlap_3841, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3841, 1, vs2); + setArg(call_valid_reg_overlap_3841, 2, vd); + setArg(call_valid_reg_overlap_3841, 3, valid_reg_overlap_3841_arg2); + setArg(call_valid_reg_overlap_3841, 4, valid_reg_overlap_3841_arg3); + setRet(call_valid_reg_overlap_3841, 0, ret_val_valid_reg_overlap_3841); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3843; + x86::Gp ret_val_sew_3843 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3843, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3842; + auto fp_vector_unary_n_3842_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3842_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3842_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3842_arg8 = rm; + auto fp_vector_unary_n_3842_arg9 = ret_val_sew_3843; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3842, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3843, 0, reinterpret_cast(this)); + setRet(call_sew_3843, 0, ret_val_sew_3843); + setArg(call_fp_vector_unary_n_3842, 0, V); + setArg(call_fp_vector_unary_n_3842, 1, 20); + setArg(call_fp_vector_unary_n_3842, 2, fp_vector_unary_n_3842_arg2); + setArg(call_fp_vector_unary_n_3842, 3, fp_vector_unary_n_3842_arg3); + setArg(call_fp_vector_unary_n_3842, 4, fp_vector_unary_n_3842_arg4); + setArg(call_fp_vector_unary_n_3842, 5, vm); + setArg(call_fp_vector_unary_n_3842, 6, vd); + setArg(call_fp_vector_unary_n_3842, 7, vs2); + setArg(call_fp_vector_unary_n_3842, 8, fp_vector_unary_n_3842_arg8); + setArg(call_fp_vector_unary_n_3842, 9, fp_vector_unary_n_3842_arg9); + } + cc.bind(label_merge); + } + auto tmp3844 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3844, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3844, traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 785); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 786: VFNCVT__ROD__F__F__W */ + continuation_e __vfncvt__rod__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rod.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__ROD__F__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 786); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3845; + x86::Gp ret_val_get_sew_pow_3845 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3845, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3846 = get_reg(cc, 8, false); + mov(cc, tmp3846, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3846, (ret_val_get_sew_pow_3845))), 8, false), ~ 1); + setArg(call_get_sew_pow_3845, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3845, 0, ret_val_get_sew_pow_3845); + InvokeNode* call_get_lmul_pow_3847; + x86::Gp ret_val_get_lmul_pow_3847 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3847, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3847; + setArg(call_get_lmul_pow_3847, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3847, 0, ret_val_get_lmul_pow_3847); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3848; + auto illegal_fp_variable_width_3848_arg2 = SEW; + auto illegal_fp_variable_width_3848_arg3 = rm; + auto illegal_fp_variable_width_3848_arg4 = SEW_widen; + auto illegal_fp_variable_width_3848_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3848 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3848, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3849; + auto valid_reg_overlap_3849_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3849_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3849 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3849, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3848, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3849)); + setArg(call_illegal_fp_variable_width_3848, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3848, 1, vd); + setArg(call_illegal_fp_variable_width_3848, 2, vm); + setArg(call_illegal_fp_variable_width_3848, 3, illegal_fp_variable_width_3848_arg2); + setArg(call_illegal_fp_variable_width_3848, 4, illegal_fp_variable_width_3848_arg3); + setArg(call_illegal_fp_variable_width_3848, 5, illegal_fp_variable_width_3848_arg4); + setArg(call_illegal_fp_variable_width_3848, 6, illegal_fp_variable_width_3848_arg5); + setRet(call_illegal_fp_variable_width_3848, 0, ret_val_illegal_fp_variable_width_3848); + setArg(call_valid_reg_overlap_3849, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3849, 1, vs2); + setArg(call_valid_reg_overlap_3849, 2, vd); + setArg(call_valid_reg_overlap_3849, 3, valid_reg_overlap_3849_arg2); + setArg(call_valid_reg_overlap_3849, 4, valid_reg_overlap_3849_arg3); + setRet(call_valid_reg_overlap_3849, 0, ret_val_valid_reg_overlap_3849); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3851; + x86::Gp ret_val_sew_3851 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3851, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3850; + auto fp_vector_unary_n_3850_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3850_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3850_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3850_arg9 = ret_val_sew_3851; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3850, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3851, 0, reinterpret_cast(this)); + setRet(call_sew_3851, 0, ret_val_sew_3851); + setArg(call_fp_vector_unary_n_3850, 0, V); + setArg(call_fp_vector_unary_n_3850, 1, 21); + setArg(call_fp_vector_unary_n_3850, 2, fp_vector_unary_n_3850_arg2); + setArg(call_fp_vector_unary_n_3850, 3, fp_vector_unary_n_3850_arg3); + setArg(call_fp_vector_unary_n_3850, 4, fp_vector_unary_n_3850_arg4); + setArg(call_fp_vector_unary_n_3850, 5, vm); + setArg(call_fp_vector_unary_n_3850, 6, vd); + setArg(call_fp_vector_unary_n_3850, 7, vs2); + setArg(call_fp_vector_unary_n_3850, 8, 6); + setArg(call_fp_vector_unary_n_3850, 9, fp_vector_unary_n_3850_arg9); + } + cc.bind(label_merge); + } + auto tmp3852 = get_reg_Gp(cc, 32, false); + mov(cc, tmp3852, gen_ext(cc, 0, 32, false)); + write_reg_to_mem(jh, tmp3852, traits::vstart); } cc.bind(label_merge); } @@ -86052,7 +85466,6 @@ inline void vm_impl::gen_lower(jit_holder& jh) { auto tmp1 = get_reg_for(cc, traits::TRAP_STATE); mov(cc, tmp1, 0); mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1); - cc.jmp(jh.trap_entry); } template template @@ -86083,8 +85496,8 @@ std::unique_ptr create(arch::rv32gcv *core, unsigned short } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/asmjit/vm_rv64gcv.cpp b/src/vm/asmjit/vm_rv64gcv.cpp index 8f43ee1..8ccda13 100644 --- a/src/vm/asmjit/vm_rv64gcv.cpp +++ b/src/vm/asmjit/vm_rv64gcv.cpp @@ -42,9 +42,6 @@ #include -#define CUR_VLEN 512 -#define CUR_XLEN 64 -#include #include #ifndef FMT_HEADER_ONLY @@ -73,9 +70,8 @@ template <> struct is_unsigned { static constexpr bool value = true; namespace iss { namespace asmjit { +namespace rv64gcv{ - -namespace rv64gcv { using namespace ::asmjit; using namespace iss::arch; using namespace iss::debugger; @@ -90,6 +86,72 @@ template class vm_impl : public iss::asmjit::vm_base { using mem_type_e = typename super::mem_type_e; using addr_t = typename super::addr_t; + + static constexpr auto& vlseg = trampoline::vlseg; + static constexpr auto& vsseg = trampoline::vsseg; + static constexpr auto& vlsseg = trampoline::vlsseg; + static constexpr auto& vssseg = trampoline::vssseg; + static constexpr auto& vlxseg = trampoline::vlxseg; + static constexpr auto& vsxseg = trampoline::vsxseg; + static constexpr auto& vector_vector_op = trampoline::vector_vector_op; + static constexpr auto& vector_imm_op = trampoline::vector_imm_op; + static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; + static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; + static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; + static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; + static constexpr auto& vector_extend = trampoline::vector_extend; + static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; + static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; + static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; + static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; + static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; + static constexpr auto& vector_red_op = trampoline::vector_red_op; + static constexpr auto& vector_red_wv = trampoline::vector_red_wv; + static constexpr auto& mask_mask_op = trampoline::mask_mask_op; + static constexpr auto& vcpop = trampoline::vcpop; + static constexpr auto& vfirst = trampoline::vfirst; + static constexpr auto& mask_set_op = trampoline::mask_set_op; + static constexpr auto& viota = trampoline::viota; + static constexpr auto& vid = trampoline::vid; + static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; + static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; + static constexpr auto& vector_slideup = trampoline::vector_slideup; + static constexpr auto& vector_slidedown = trampoline::vector_slidedown; + static constexpr auto& vector_slide1up = trampoline::vector_slide1up; + static constexpr auto& vector_slide1down = trampoline::vector_slide1down; + static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; + static constexpr auto& vector_compress = trampoline::vector_compress; + static constexpr auto& vector_whole_move = trampoline::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; + static constexpr auto& vector_unary_op = trampoline::vector_unary_op; + vm_impl(); vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); @@ -359,8 +421,8 @@ template class vm_impl : public iss::asmjit::vm_base { return reinterpret_cast(vm_impl_ptr)->valid_reg_overlap(rs,rd,EMUL_pow_rs,EMUL_pow_rd); } uint8_t valid_reg_overlap(uint8_t rs, uint8_t rd, int8_t EMUL_pow_rs, int8_t EMUL_pow_rd){ - uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& (1ULL << 4) : 1; - uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& (1ULL << 4) : 1; + uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& ((1ULL << 5)-1) : 1; + uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& ((1ULL << 5)-1) : 1; if(EMUL_pow_rs < EMUL_pow_rd) { return (rs + rs_group <= rd) || (rs >= rd + rd_group) || ((rs + rs_group == rd + rd_group) & (EMUL_pow_rs >= 0)); } @@ -484,11 +546,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); return ! valid_vtype() || *vstart != 0; } - static uint8_t _illegal_reduction_widen(void* vm_impl_ptr , uint8_t EEW, int8_t EMUL_pow){ - return reinterpret_cast(vm_impl_ptr)->illegal_reduction_widen(EEW,EMUL_pow); + static uint8_t _illegal_reduction_widen(void* vm_impl_ptr , uint8_t EEW){ + return reinterpret_cast(vm_impl_ptr)->illegal_reduction_widen(EEW); } - uint8_t illegal_reduction_widen(uint8_t EEW, int8_t EMUL_pow){ - return illegal_reduction() || ! valid_eew_emul(EEW, EMUL_pow); + uint8_t illegal_reduction_widen(uint8_t EEW){ + return illegal_reduction() || ! (EEW >= 8 && EEW <= traits::ELEN); } static uint8_t _illegal_fp_reduction(void* vm_impl_ptr , uint8_t SEW, uint8_t rm){ return reinterpret_cast(vm_impl_ptr)->illegal_fp_reduction(SEW,rm); @@ -497,6 +559,12 @@ template class vm_impl : public iss::asmjit::vm_base { auto* vstart = reinterpret_cast(this->regs_base_ptr+::iss::arch::traits::reg_byte_offsets[::iss::arch::traits::vstart]); return ! valid_vtype() || *vstart != 0 || ! valid_fp_op(SEW, rm); } + static uint8_t _illegal_fp_reduction_widen(void* vm_impl_ptr , uint8_t SEW, uint8_t rm, uint8_t EEW){ + return reinterpret_cast(vm_impl_ptr)->illegal_fp_reduction_widen(SEW,rm,EEW); + } + uint8_t illegal_fp_reduction_widen(uint8_t SEW, uint8_t rm, uint8_t EEW){ + return illegal_fp_reduction(SEW, rm) || ! (EEW >= 8 && EEW <= traits::ELEN); + } static uint8_t _illegal_fp_variable_width(void* vm_impl_ptr , uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm, uint8_t SEW_new, int8_t LMUL_pow_new){ return reinterpret_cast(vm_impl_ptr)->illegal_fp_variable_width(vd,vm,SEW,rm,SEW_new,LMUL_pow_new); } @@ -14148,17 +14216,15 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_276 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_276, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto orig_ratio = gen_ext(cc, - (gen_operation(cc, sub, ret_val_get_sew_pow_275, ret_val_get_lmul_pow_276)), 5, true); + (gen_operation(cc, sub, ret_val_get_sew_pow_275, ret_val_get_lmul_pow_276)), 8, true); setArg(call_get_sew_pow_275, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_275, 0, ret_val_get_sew_pow_275); setArg(call_get_lmul_pow_276, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_276, 0, ret_val_get_lmul_pow_276); auto orig_vstart = load_reg_from_mem(jh, traits::vstart); - auto tmp277 = get_reg_Gp(cc, 8, false); - mov(cc, tmp277, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp277, 64, false) - , traits::vstart); + auto tmp277 = get_reg_Gp(cc, 64, false); + mov(cc, tmp277, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp277, traits::vstart); auto tmp278 = get_reg_Gp(cc, 64, false); mov(cc, tmp278, (uint64_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul)); write_reg_to_mem(jh, tmp278, traits::vtype); @@ -14222,9 +14288,7 @@ template class vm_impl : public iss::asmjit::vm_base { } else { if(rd!=0){ - write_reg_to_mem(jh, - gen_ext(cc, VLMAX, 64, false) - , traits::vl); + write_reg_to_mem(jh, gen_ext(cc, VLMAX, 64, false), traits::vl); mov(cc, get_ptr_for(jh, traits::X0+ rd), gen_ext(cc, VLMAX, 64, false)); @@ -14237,7 +14301,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_287 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_287, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto new_ratio = gen_ext(cc, - (gen_operation(cc, sub, ret_val_get_sew_pow_286, ret_val_get_lmul_pow_287)), 5, true); + (gen_operation(cc, sub, ret_val_get_sew_pow_286, ret_val_get_lmul_pow_287)), 8, true); setArg(call_get_sew_pow_286, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_286, 0, ret_val_get_sew_pow_286); setArg(call_get_lmul_pow_287, 0, reinterpret_cast(this)); @@ -14353,20 +14417,16 @@ template class vm_impl : public iss::asmjit::vm_base { auto calculate_new_vl_296_arg1 = VLMAX; x86::Gp ret_val_calculate_new_vl_296 = get_reg_Gp(cc, 16, false); cc.invoke(&call_calculate_new_vl_296, (uintptr_t)&vm_impl::_calculate_new_vl, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_calculate_new_vl_296, 64, false) - , traits::vl); + write_reg_to_mem(jh, gen_ext(cc, ret_val_calculate_new_vl_296, 64, false), traits::vl); setArg(call_calculate_new_vl_296, 0, reinterpret_cast(this)); setArg(call_calculate_new_vl_296, 1, uimm); setArg(call_calculate_new_vl_296, 2, calculate_new_vl_296_arg1); setRet(call_calculate_new_vl_296, 0, ret_val_calculate_new_vl_296); mov(cc, get_ptr_for(jh, traits::X0+ rd), load_reg_from_mem(jh, traits::vl)); - auto tmp297 = get_reg_Gp(cc, 8, false); - mov(cc, tmp297, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp297, 64, false) - , traits::vstart); + auto tmp297 = get_reg_Gp(cc, 64, false); + mov(cc, tmp297, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp297, traits::vstart); } cc.bind(label_merge); } @@ -14421,17 +14481,15 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_299 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_299, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto orig_ratio = gen_ext(cc, - (gen_operation(cc, sub, ret_val_get_sew_pow_298, ret_val_get_lmul_pow_299)), 5, true); + (gen_operation(cc, sub, ret_val_get_sew_pow_298, ret_val_get_lmul_pow_299)), 8, true); setArg(call_get_sew_pow_298, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_298, 0, ret_val_get_sew_pow_298); setArg(call_get_lmul_pow_299, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_299, 0, ret_val_get_lmul_pow_299); auto orig_vstart = load_reg_from_mem(jh, traits::vstart); - auto tmp300 = get_reg_Gp(cc, 8, false); - mov(cc, tmp300, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp300, 64, false) - , traits::vstart); + auto tmp300 = get_reg_Gp(cc, 64, false); + mov(cc, tmp300, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp300, traits::vstart); { auto label_merge = cc.newLabel(); auto cond = gen_slice(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 8, (static_cast(traits::XLEN)-2)-8+1); @@ -14503,9 +14561,7 @@ template class vm_impl : public iss::asmjit::vm_base { } else { if(rd!=0){ - write_reg_to_mem(jh, - gen_ext(cc, VLMAX, 64, false) - , traits::vl); + write_reg_to_mem(jh, gen_ext(cc, VLMAX, 64, false), traits::vl); mov(cc, get_ptr_for(jh, traits::X0+ rd), gen_ext(cc, VLMAX, 64, false)); @@ -14518,7 +14574,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_309 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_309, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto new_ratio = gen_ext(cc, - (gen_operation(cc, sub, ret_val_get_sew_pow_308, ret_val_get_lmul_pow_309)), 5, true); + (gen_operation(cc, sub, ret_val_get_sew_pow_308, ret_val_get_lmul_pow_309)), 8, true); setArg(call_get_sew_pow_308, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_308, 0, ret_val_get_sew_pow_308); setArg(call_get_lmul_pow_309, 0, reinterpret_cast(this)); @@ -14598,7 +14654,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_313 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_313, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_311, ret_val_get_sew_pow_312), ret_val_get_lmul_pow_313)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_311, ret_val_get_sew_pow_312), ret_val_get_lmul_pow_313)), 8, true); setArg(call_get_pow_311, 0, reinterpret_cast(this)); setArg(call_get_pow_311, 1, EEW); setRet(call_get_pow_311, 0, ret_val_get_pow_311); @@ -14718,7 +14774,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_318 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_318, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_316, ret_val_get_sew_pow_317), ret_val_get_lmul_pow_318)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_316, ret_val_get_sew_pow_317), ret_val_get_lmul_pow_318)), 8, true); setArg(call_get_pow_316, 0, reinterpret_cast(this)); setArg(call_get_pow_316, 1, EEW); setRet(call_get_pow_316, 0, ret_val_get_pow_316); @@ -14838,7 +14894,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_323 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_323, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_321, ret_val_get_sew_pow_322), ret_val_get_lmul_pow_323)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_321, ret_val_get_sew_pow_322), ret_val_get_lmul_pow_323)), 8, true); setArg(call_get_pow_321, 0, reinterpret_cast(this)); setArg(call_get_pow_321, 1, EEW); setRet(call_get_pow_321, 0, ret_val_get_pow_321); @@ -14958,7 +15014,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_328 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_328, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_326, ret_val_get_sew_pow_327), ret_val_get_lmul_pow_328)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_326, ret_val_get_sew_pow_327), ret_val_get_lmul_pow_328)), 8, true); setArg(call_get_pow_326, 0, reinterpret_cast(this)); setArg(call_get_pow_326, 1, EEW); setRet(call_get_pow_326, 0, ret_val_get_pow_326); @@ -15078,7 +15134,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_333 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_333, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_331, ret_val_get_sew_pow_332), ret_val_get_lmul_pow_333)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_331, ret_val_get_sew_pow_332), ret_val_get_lmul_pow_333)), 8, true); setArg(call_get_pow_331, 0, reinterpret_cast(this)); setArg(call_get_pow_331, 1, EEW); setRet(call_get_pow_331, 0, ret_val_get_pow_331); @@ -15198,7 +15254,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_338 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_338, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_336, ret_val_get_sew_pow_337), ret_val_get_lmul_pow_338)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_336, ret_val_get_sew_pow_337), ret_val_get_lmul_pow_338)), 8, true); setArg(call_get_pow_336, 0, reinterpret_cast(this)); setArg(call_get_pow_336, 1, EEW); setRet(call_get_pow_336, 0, ret_val_get_pow_336); @@ -15318,7 +15374,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_343 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_343, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_341, ret_val_get_sew_pow_342), ret_val_get_lmul_pow_343)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_341, ret_val_get_sew_pow_342), ret_val_get_lmul_pow_343)), 8, true); setArg(call_get_pow_341, 0, reinterpret_cast(this)); setArg(call_get_pow_341, 1, EEW); setRet(call_get_pow_341, 0, ret_val_get_pow_341); @@ -15438,7 +15494,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_348 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_348, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_346, ret_val_get_sew_pow_347), ret_val_get_lmul_pow_348)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_346, ret_val_get_sew_pow_347), ret_val_get_lmul_pow_348)), 8, true); setArg(call_get_pow_346, 0, reinterpret_cast(this)); setArg(call_get_pow_346, 1, EEW); setRet(call_get_pow_346, 0, ret_val_get_pow_346); @@ -15558,7 +15614,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_353 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_353, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_351, ret_val_get_sew_pow_352), ret_val_get_lmul_pow_353)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_351, ret_val_get_sew_pow_352), ret_val_get_lmul_pow_353)), 8, true); setArg(call_get_pow_351, 0, reinterpret_cast(this)); setArg(call_get_pow_351, 1, EEW); setRet(call_get_pow_351, 0, ret_val_get_pow_351); @@ -15678,7 +15734,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_358 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_358, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_356, ret_val_get_sew_pow_357), ret_val_get_lmul_pow_358)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_356, ret_val_get_sew_pow_357), ret_val_get_lmul_pow_358)), 8, true); setArg(call_get_pow_356, 0, reinterpret_cast(this)); setArg(call_get_pow_356, 1, EEW); setRet(call_get_pow_356, 0, ret_val_get_pow_356); @@ -15798,7 +15854,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_363 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_363, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_361, ret_val_get_sew_pow_362), ret_val_get_lmul_pow_363)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_361, ret_val_get_sew_pow_362), ret_val_get_lmul_pow_363)), 8, true); setArg(call_get_pow_361, 0, reinterpret_cast(this)); setArg(call_get_pow_361, 1, EEW); setRet(call_get_pow_361, 0, ret_val_get_pow_361); @@ -15918,7 +15974,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_368 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_368, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_366, ret_val_get_sew_pow_367), ret_val_get_lmul_pow_368)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_366, ret_val_get_sew_pow_367), ret_val_get_lmul_pow_368)), 8, true); setArg(call_get_pow_366, 0, reinterpret_cast(this)); setArg(call_get_pow_366, 1, EEW); setRet(call_get_pow_366, 0, ret_val_get_pow_366); @@ -16038,7 +16094,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_373 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_373, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_371, ret_val_get_sew_pow_372), ret_val_get_lmul_pow_373)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_371, ret_val_get_sew_pow_372), ret_val_get_lmul_pow_373)), 8, true); setArg(call_get_pow_371, 0, reinterpret_cast(this)); setArg(call_get_pow_371, 1, EEW); setRet(call_get_pow_371, 0, ret_val_get_pow_371); @@ -16158,7 +16214,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_378 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_378, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_376, ret_val_get_sew_pow_377), ret_val_get_lmul_pow_378)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_376, ret_val_get_sew_pow_377), ret_val_get_lmul_pow_378)), 8, true); setArg(call_get_pow_376, 0, reinterpret_cast(this)); setArg(call_get_pow_376, 1, EEW); setRet(call_get_pow_376, 0, ret_val_get_pow_376); @@ -16278,7 +16334,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_383 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_383, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_381, ret_val_get_sew_pow_382), ret_val_get_lmul_pow_383)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_381, ret_val_get_sew_pow_382), ret_val_get_lmul_pow_383)), 8, true); setArg(call_get_pow_381, 0, reinterpret_cast(this)); setArg(call_get_pow_381, 1, EEW); setRet(call_get_pow_381, 0, ret_val_get_pow_381); @@ -16398,7 +16454,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_388 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_388, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_386, ret_val_get_sew_pow_387), ret_val_get_lmul_pow_388)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_386, ret_val_get_sew_pow_387), ret_val_get_lmul_pow_388)), 8, true); setArg(call_get_pow_386, 0, reinterpret_cast(this)); setArg(call_get_pow_386, 1, EEW); setRet(call_get_pow_386, 0, ret_val_get_pow_386); @@ -16518,7 +16574,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_393 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_393, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_391, ret_val_get_sew_pow_392), ret_val_get_lmul_pow_393)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_391, ret_val_get_sew_pow_392), ret_val_get_lmul_pow_393)), 8, true); setArg(call_get_pow_391, 0, reinterpret_cast(this)); setArg(call_get_pow_391, 1, EEW); setRet(call_get_pow_391, 0, ret_val_get_pow_391); @@ -16638,7 +16694,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_398 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_398, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_396, ret_val_get_sew_pow_397), ret_val_get_lmul_pow_398)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_396, ret_val_get_sew_pow_397), ret_val_get_lmul_pow_398)), 8, true); setArg(call_get_pow_396, 0, reinterpret_cast(this)); setArg(call_get_pow_396, 1, EEW); setRet(call_get_pow_396, 0, ret_val_get_pow_396); @@ -16758,7 +16814,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_403 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_403, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_401, ret_val_get_sew_pow_402), ret_val_get_lmul_pow_403)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_401, ret_val_get_sew_pow_402), ret_val_get_lmul_pow_403)), 8, true); setArg(call_get_pow_401, 0, reinterpret_cast(this)); setArg(call_get_pow_401, 1, EEW); setRet(call_get_pow_401, 0, ret_val_get_pow_401); @@ -16878,7 +16934,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_408 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_408, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_406, ret_val_get_sew_pow_407), ret_val_get_lmul_pow_408)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_406, ret_val_get_sew_pow_407), ret_val_get_lmul_pow_408)), 8, true); setArg(call_get_pow_406, 0, reinterpret_cast(this)); setArg(call_get_pow_406, 1, EEW); setRet(call_get_pow_406, 0, ret_val_get_pow_406); @@ -16998,7 +17054,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_413 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_413, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_411, ret_val_get_sew_pow_412), ret_val_get_lmul_pow_413)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_411, ret_val_get_sew_pow_412), ret_val_get_lmul_pow_413)), 8, true); setArg(call_get_pow_411, 0, reinterpret_cast(this)); setArg(call_get_pow_411, 1, EEW); setRet(call_get_pow_411, 0, ret_val_get_pow_411); @@ -17118,7 +17174,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_418 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_418, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_416, ret_val_get_sew_pow_417), ret_val_get_lmul_pow_418)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_416, ret_val_get_sew_pow_417), ret_val_get_lmul_pow_418)), 8, true); setArg(call_get_pow_416, 0, reinterpret_cast(this)); setArg(call_get_pow_416, 1, EEW); setRet(call_get_pow_416, 0, ret_val_get_pow_416); @@ -17238,7 +17294,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_423 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_423, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_421, ret_val_get_sew_pow_422), ret_val_get_lmul_pow_423)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_421, ret_val_get_sew_pow_422), ret_val_get_lmul_pow_423)), 8, true); setArg(call_get_pow_421, 0, reinterpret_cast(this)); setArg(call_get_pow_421, 1, EEW); setRet(call_get_pow_421, 0, ret_val_get_pow_421); @@ -17358,7 +17414,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_428 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_428, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_426, ret_val_get_sew_pow_427), ret_val_get_lmul_pow_428)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_426, ret_val_get_sew_pow_427), ret_val_get_lmul_pow_428)), 8, true); setArg(call_get_pow_426, 0, reinterpret_cast(this)); setArg(call_get_pow_426, 1, EEW); setRet(call_get_pow_426, 0, ret_val_get_pow_426); @@ -17478,7 +17534,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_433 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_433, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_431, ret_val_get_sew_pow_432), ret_val_get_lmul_pow_433)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_431, ret_val_get_sew_pow_432), ret_val_get_lmul_pow_433)), 8, true); setArg(call_get_pow_431, 0, reinterpret_cast(this)); setArg(call_get_pow_431, 1, EEW); setRet(call_get_pow_431, 0, ret_val_get_pow_431); @@ -17598,7 +17654,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_438 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_438, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_436, ret_val_get_sew_pow_437), ret_val_get_lmul_pow_438)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_436, ret_val_get_sew_pow_437), ret_val_get_lmul_pow_438)), 8, true); setArg(call_get_pow_436, 0, reinterpret_cast(this)); setArg(call_get_pow_436, 1, EEW); setRet(call_get_pow_436, 0, ret_val_get_pow_436); @@ -17718,7 +17774,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_443 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_443, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_441, ret_val_get_sew_pow_442), ret_val_get_lmul_pow_443)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_441, ret_val_get_sew_pow_442), ret_val_get_lmul_pow_443)), 8, true); setArg(call_get_pow_441, 0, reinterpret_cast(this)); setArg(call_get_pow_441, 1, EEW); setRet(call_get_pow_441, 0, ret_val_get_pow_441); @@ -17838,7 +17894,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_448 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_448, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_446, ret_val_get_sew_pow_447), ret_val_get_lmul_pow_448)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_446, ret_val_get_sew_pow_447), ret_val_get_lmul_pow_448)), 8, true); setArg(call_get_pow_446, 0, reinterpret_cast(this)); setArg(call_get_pow_446, 1, EEW); setRet(call_get_pow_446, 0, ret_val_get_pow_446); @@ -17958,7 +18014,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_453 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_453, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_451, ret_val_get_sew_pow_452), ret_val_get_lmul_pow_453)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_451, ret_val_get_sew_pow_452), ret_val_get_lmul_pow_453)), 8, true); setArg(call_get_pow_451, 0, reinterpret_cast(this)); setArg(call_get_pow_451, 1, EEW); setRet(call_get_pow_451, 0, ret_val_get_pow_451); @@ -18078,7 +18134,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_458 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_458, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_456, ret_val_get_sew_pow_457), ret_val_get_lmul_pow_458)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_456, ret_val_get_sew_pow_457), ret_val_get_lmul_pow_458)), 8, true); setArg(call_get_pow_456, 0, reinterpret_cast(this)); setArg(call_get_pow_456, 1, EEW); setRet(call_get_pow_456, 0, ret_val_get_pow_456); @@ -18198,7 +18254,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_463 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_463, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_461, ret_val_get_sew_pow_462), ret_val_get_lmul_pow_463)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_461, ret_val_get_sew_pow_462), ret_val_get_lmul_pow_463)), 8, true); setArg(call_get_pow_461, 0, reinterpret_cast(this)); setArg(call_get_pow_461, 1, EEW); setRet(call_get_pow_461, 0, ret_val_get_pow_461); @@ -18318,7 +18374,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_468 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_468, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_466, ret_val_get_sew_pow_467), ret_val_get_lmul_pow_468)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_466, ret_val_get_sew_pow_467), ret_val_get_lmul_pow_468)), 8, true); setArg(call_get_pow_466, 0, reinterpret_cast(this)); setArg(call_get_pow_466, 1, EEW); setRet(call_get_pow_466, 0, ret_val_get_pow_466); @@ -18438,7 +18494,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_473 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_473, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_471, ret_val_get_sew_pow_472), ret_val_get_lmul_pow_473)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_471, ret_val_get_sew_pow_472), ret_val_get_lmul_pow_473)), 8, true); setArg(call_get_pow_471, 0, reinterpret_cast(this)); setArg(call_get_pow_471, 1, EEW); setRet(call_get_pow_471, 0, ret_val_get_pow_471); @@ -18556,7 +18612,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_478 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_478, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_476, ret_val_get_sew_pow_477), ret_val_get_lmul_pow_478)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_476, ret_val_get_sew_pow_477), ret_val_get_lmul_pow_478)), 8, true); setArg(call_get_pow_476, 0, reinterpret_cast(this)); setArg(call_get_pow_476, 1, EEW); setRet(call_get_pow_476, 0, ret_val_get_pow_476); @@ -18674,7 +18730,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_483 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_483, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_481, ret_val_get_sew_pow_482), ret_val_get_lmul_pow_483)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_481, ret_val_get_sew_pow_482), ret_val_get_lmul_pow_483)), 8, true); setArg(call_get_pow_481, 0, reinterpret_cast(this)); setArg(call_get_pow_481, 1, EEW); setRet(call_get_pow_481, 0, ret_val_get_pow_481); @@ -18792,7 +18848,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_488 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_488, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_486, ret_val_get_sew_pow_487), ret_val_get_lmul_pow_488)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_486, ret_val_get_sew_pow_487), ret_val_get_lmul_pow_488)), 8, true); setArg(call_get_pow_486, 0, reinterpret_cast(this)); setArg(call_get_pow_486, 1, EEW); setRet(call_get_pow_486, 0, ret_val_get_pow_486); @@ -18910,7 +18966,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_493 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_493, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_491, ret_val_get_sew_pow_492), ret_val_get_lmul_pow_493)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_491, ret_val_get_sew_pow_492), ret_val_get_lmul_pow_493)), 8, true); setArg(call_get_pow_491, 0, reinterpret_cast(this)); setArg(call_get_pow_491, 1, EEW); setRet(call_get_pow_491, 0, ret_val_get_pow_491); @@ -19028,7 +19084,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_498 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_498, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_496, ret_val_get_sew_pow_497), ret_val_get_lmul_pow_498)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_496, ret_val_get_sew_pow_497), ret_val_get_lmul_pow_498)), 8, true); setArg(call_get_pow_496, 0, reinterpret_cast(this)); setArg(call_get_pow_496, 1, EEW); setRet(call_get_pow_496, 0, ret_val_get_pow_496); @@ -19146,7 +19202,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_503 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_503, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_501, ret_val_get_sew_pow_502), ret_val_get_lmul_pow_503)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_501, ret_val_get_sew_pow_502), ret_val_get_lmul_pow_503)), 8, true); setArg(call_get_pow_501, 0, reinterpret_cast(this)); setArg(call_get_pow_501, 1, EEW); setRet(call_get_pow_501, 0, ret_val_get_pow_501); @@ -19264,7 +19320,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_508 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_508, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_506, ret_val_get_sew_pow_507), ret_val_get_lmul_pow_508)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_506, ret_val_get_sew_pow_507), ret_val_get_lmul_pow_508)), 8, true); setArg(call_get_pow_506, 0, reinterpret_cast(this)); setArg(call_get_pow_506, 1, EEW); setRet(call_get_pow_506, 0, ret_val_get_pow_506); @@ -19382,7 +19438,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_513 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_513, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_511, ret_val_get_sew_pow_512), ret_val_get_lmul_pow_513)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_511, ret_val_get_sew_pow_512), ret_val_get_lmul_pow_513)), 8, true); setArg(call_get_pow_511, 0, reinterpret_cast(this)); setArg(call_get_pow_511, 1, EEW); setRet(call_get_pow_511, 0, ret_val_get_pow_511); @@ -19500,7 +19556,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_518 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_518, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_516, ret_val_get_sew_pow_517), ret_val_get_lmul_pow_518)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_516, ret_val_get_sew_pow_517), ret_val_get_lmul_pow_518)), 8, true); setArg(call_get_pow_516, 0, reinterpret_cast(this)); setArg(call_get_pow_516, 1, EEW); setRet(call_get_pow_516, 0, ret_val_get_pow_516); @@ -19618,7 +19674,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_523 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_523, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_521, ret_val_get_sew_pow_522), ret_val_get_lmul_pow_523)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_521, ret_val_get_sew_pow_522), ret_val_get_lmul_pow_523)), 8, true); setArg(call_get_pow_521, 0, reinterpret_cast(this)); setArg(call_get_pow_521, 1, EEW); setRet(call_get_pow_521, 0, ret_val_get_pow_521); @@ -19736,7 +19792,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_528 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_528, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_526, ret_val_get_sew_pow_527), ret_val_get_lmul_pow_528)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_526, ret_val_get_sew_pow_527), ret_val_get_lmul_pow_528)), 8, true); setArg(call_get_pow_526, 0, reinterpret_cast(this)); setArg(call_get_pow_526, 1, EEW); setRet(call_get_pow_526, 0, ret_val_get_pow_526); @@ -19854,7 +19910,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_533 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_533, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_531, ret_val_get_sew_pow_532), ret_val_get_lmul_pow_533)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_531, ret_val_get_sew_pow_532), ret_val_get_lmul_pow_533)), 8, true); setArg(call_get_pow_531, 0, reinterpret_cast(this)); setArg(call_get_pow_531, 1, EEW); setRet(call_get_pow_531, 0, ret_val_get_pow_531); @@ -19972,7 +20028,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_538 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_538, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_536, ret_val_get_sew_pow_537), ret_val_get_lmul_pow_538)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_536, ret_val_get_sew_pow_537), ret_val_get_lmul_pow_538)), 8, true); setArg(call_get_pow_536, 0, reinterpret_cast(this)); setArg(call_get_pow_536, 1, EEW); setRet(call_get_pow_536, 0, ret_val_get_pow_536); @@ -20090,7 +20146,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_543 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_543, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_541, ret_val_get_sew_pow_542), ret_val_get_lmul_pow_543)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_541, ret_val_get_sew_pow_542), ret_val_get_lmul_pow_543)), 8, true); setArg(call_get_pow_541, 0, reinterpret_cast(this)); setArg(call_get_pow_541, 1, EEW); setRet(call_get_pow_541, 0, ret_val_get_pow_541); @@ -20208,7 +20264,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_548 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_548, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_546, ret_val_get_sew_pow_547), ret_val_get_lmul_pow_548)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_546, ret_val_get_sew_pow_547), ret_val_get_lmul_pow_548)), 8, true); setArg(call_get_pow_546, 0, reinterpret_cast(this)); setArg(call_get_pow_546, 1, EEW); setRet(call_get_pow_546, 0, ret_val_get_pow_546); @@ -20326,7 +20382,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_553 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_553, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_551, ret_val_get_sew_pow_552), ret_val_get_lmul_pow_553)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_551, ret_val_get_sew_pow_552), ret_val_get_lmul_pow_553)), 8, true); setArg(call_get_pow_551, 0, reinterpret_cast(this)); setArg(call_get_pow_551, 1, EEW); setRet(call_get_pow_551, 0, ret_val_get_pow_551); @@ -20444,7 +20500,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_558 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_558, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_556, ret_val_get_sew_pow_557), ret_val_get_lmul_pow_558)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_556, ret_val_get_sew_pow_557), ret_val_get_lmul_pow_558)), 8, true); setArg(call_get_pow_556, 0, reinterpret_cast(this)); setArg(call_get_pow_556, 1, EEW); setRet(call_get_pow_556, 0, ret_val_get_pow_556); @@ -20562,7 +20618,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_563 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_563, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_561, ret_val_get_sew_pow_562), ret_val_get_lmul_pow_563)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_561, ret_val_get_sew_pow_562), ret_val_get_lmul_pow_563)), 8, true); setArg(call_get_pow_561, 0, reinterpret_cast(this)); setArg(call_get_pow_561, 1, EEW); setRet(call_get_pow_561, 0, ret_val_get_pow_561); @@ -20680,7 +20736,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_568 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_568, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_566, ret_val_get_sew_pow_567), ret_val_get_lmul_pow_568)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_566, ret_val_get_sew_pow_567), ret_val_get_lmul_pow_568)), 8, true); setArg(call_get_pow_566, 0, reinterpret_cast(this)); setArg(call_get_pow_566, 1, EEW); setRet(call_get_pow_566, 0, ret_val_get_pow_566); @@ -20798,7 +20854,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_573 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_573, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_571, ret_val_get_sew_pow_572), ret_val_get_lmul_pow_573)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_571, ret_val_get_sew_pow_572), ret_val_get_lmul_pow_573)), 8, true); setArg(call_get_pow_571, 0, reinterpret_cast(this)); setArg(call_get_pow_571, 1, EEW); setRet(call_get_pow_571, 0, ret_val_get_pow_571); @@ -20916,7 +20972,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_578 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_578, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_576, ret_val_get_sew_pow_577), ret_val_get_lmul_pow_578)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_576, ret_val_get_sew_pow_577), ret_val_get_lmul_pow_578)), 8, true); setArg(call_get_pow_576, 0, reinterpret_cast(this)); setArg(call_get_pow_576, 1, EEW); setRet(call_get_pow_576, 0, ret_val_get_pow_576); @@ -21034,7 +21090,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_583 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_583, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_581, ret_val_get_sew_pow_582), ret_val_get_lmul_pow_583)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_581, ret_val_get_sew_pow_582), ret_val_get_lmul_pow_583)), 8, true); setArg(call_get_pow_581, 0, reinterpret_cast(this)); setArg(call_get_pow_581, 1, EEW); setRet(call_get_pow_581, 0, ret_val_get_pow_581); @@ -21152,7 +21208,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_588 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_588, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_586, ret_val_get_sew_pow_587), ret_val_get_lmul_pow_588)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_586, ret_val_get_sew_pow_587), ret_val_get_lmul_pow_588)), 8, true); setArg(call_get_pow_586, 0, reinterpret_cast(this)); setArg(call_get_pow_586, 1, EEW); setRet(call_get_pow_586, 0, ret_val_get_pow_586); @@ -21270,7 +21326,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_593 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_593, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_591, ret_val_get_sew_pow_592), ret_val_get_lmul_pow_593)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_591, ret_val_get_sew_pow_592), ret_val_get_lmul_pow_593)), 8, true); setArg(call_get_pow_591, 0, reinterpret_cast(this)); setArg(call_get_pow_591, 1, EEW); setRet(call_get_pow_591, 0, ret_val_get_pow_591); @@ -21388,7 +21444,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_598 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_598, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_596, ret_val_get_sew_pow_597), ret_val_get_lmul_pow_598)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_596, ret_val_get_sew_pow_597), ret_val_get_lmul_pow_598)), 8, true); setArg(call_get_pow_596, 0, reinterpret_cast(this)); setArg(call_get_pow_596, 1, EEW); setRet(call_get_pow_596, 0, ret_val_get_pow_596); @@ -21506,7 +21562,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_603 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_603, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_601, ret_val_get_sew_pow_602), ret_val_get_lmul_pow_603)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_601, ret_val_get_sew_pow_602), ret_val_get_lmul_pow_603)), 8, true); setArg(call_get_pow_601, 0, reinterpret_cast(this)); setArg(call_get_pow_601, 1, EEW); setRet(call_get_pow_601, 0, ret_val_get_pow_601); @@ -21624,7 +21680,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_608 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_608, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_606, ret_val_get_sew_pow_607), ret_val_get_lmul_pow_608)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_606, ret_val_get_sew_pow_607), ret_val_get_lmul_pow_608)), 8, true); setArg(call_get_pow_606, 0, reinterpret_cast(this)); setArg(call_get_pow_606, 1, EEW); setRet(call_get_pow_606, 0, ret_val_get_pow_606); @@ -21742,7 +21798,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_613 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_613, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_611, ret_val_get_sew_pow_612), ret_val_get_lmul_pow_613)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_611, ret_val_get_sew_pow_612), ret_val_get_lmul_pow_613)), 8, true); setArg(call_get_pow_611, 0, reinterpret_cast(this)); setArg(call_get_pow_611, 1, EEW); setRet(call_get_pow_611, 0, ret_val_get_pow_611); @@ -21860,7 +21916,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_618 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_618, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_616, ret_val_get_sew_pow_617), ret_val_get_lmul_pow_618)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_616, ret_val_get_sew_pow_617), ret_val_get_lmul_pow_618)), 8, true); setArg(call_get_pow_616, 0, reinterpret_cast(this)); setArg(call_get_pow_616, 1, EEW); setRet(call_get_pow_616, 0, ret_val_get_pow_616); @@ -21978,7 +22034,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_623 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_623, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_621, ret_val_get_sew_pow_622), ret_val_get_lmul_pow_623)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_621, ret_val_get_sew_pow_622), ret_val_get_lmul_pow_623)), 8, true); setArg(call_get_pow_621, 0, reinterpret_cast(this)); setArg(call_get_pow_621, 1, EEW); setRet(call_get_pow_621, 0, ret_val_get_pow_621); @@ -22096,7 +22152,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_628 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_628, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_626, ret_val_get_sew_pow_627), ret_val_get_lmul_pow_628)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_626, ret_val_get_sew_pow_627), ret_val_get_lmul_pow_628)), 8, true); setArg(call_get_pow_626, 0, reinterpret_cast(this)); setArg(call_get_pow_626, 1, EEW); setRet(call_get_pow_626, 0, ret_val_get_pow_626); @@ -22215,7 +22271,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_633 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_633, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_631, ret_val_get_sew_pow_632), ret_val_get_lmul_pow_633)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_631, ret_val_get_sew_pow_632), ret_val_get_lmul_pow_633)), 8, true); setArg(call_get_pow_631, 0, reinterpret_cast(this)); setArg(call_get_pow_631, 1, EEW); setRet(call_get_pow_631, 0, ret_val_get_pow_631); @@ -22338,7 +22394,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_638 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_638, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_636, ret_val_get_sew_pow_637), ret_val_get_lmul_pow_638)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_636, ret_val_get_sew_pow_637), ret_val_get_lmul_pow_638)), 8, true); setArg(call_get_pow_636, 0, reinterpret_cast(this)); setArg(call_get_pow_636, 1, EEW); setRet(call_get_pow_636, 0, ret_val_get_pow_636); @@ -22461,7 +22517,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_643 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_643, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_641, ret_val_get_sew_pow_642), ret_val_get_lmul_pow_643)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_641, ret_val_get_sew_pow_642), ret_val_get_lmul_pow_643)), 8, true); setArg(call_get_pow_641, 0, reinterpret_cast(this)); setArg(call_get_pow_641, 1, EEW); setRet(call_get_pow_641, 0, ret_val_get_pow_641); @@ -22584,7 +22640,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_648 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_648, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_646, ret_val_get_sew_pow_647), ret_val_get_lmul_pow_648)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_646, ret_val_get_sew_pow_647), ret_val_get_lmul_pow_648)), 8, true); setArg(call_get_pow_646, 0, reinterpret_cast(this)); setArg(call_get_pow_646, 1, EEW); setRet(call_get_pow_646, 0, ret_val_get_pow_646); @@ -22707,7 +22763,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_653 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_653, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_651, ret_val_get_sew_pow_652), ret_val_get_lmul_pow_653)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_651, ret_val_get_sew_pow_652), ret_val_get_lmul_pow_653)), 8, true); setArg(call_get_pow_651, 0, reinterpret_cast(this)); setArg(call_get_pow_651, 1, EEW); setRet(call_get_pow_651, 0, ret_val_get_pow_651); @@ -22830,7 +22886,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_658 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_658, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_656, ret_val_get_sew_pow_657), ret_val_get_lmul_pow_658)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_656, ret_val_get_sew_pow_657), ret_val_get_lmul_pow_658)), 8, true); setArg(call_get_pow_656, 0, reinterpret_cast(this)); setArg(call_get_pow_656, 1, EEW); setRet(call_get_pow_656, 0, ret_val_get_pow_656); @@ -22953,7 +23009,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_663 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_663, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_661, ret_val_get_sew_pow_662), ret_val_get_lmul_pow_663)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_661, ret_val_get_sew_pow_662), ret_val_get_lmul_pow_663)), 8, true); setArg(call_get_pow_661, 0, reinterpret_cast(this)); setArg(call_get_pow_661, 1, EEW); setRet(call_get_pow_661, 0, ret_val_get_pow_661); @@ -23076,7 +23132,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_668 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_668, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_666, ret_val_get_sew_pow_667), ret_val_get_lmul_pow_668)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_666, ret_val_get_sew_pow_667), ret_val_get_lmul_pow_668)), 8, true); setArg(call_get_pow_666, 0, reinterpret_cast(this)); setArg(call_get_pow_666, 1, EEW); setRet(call_get_pow_666, 0, ret_val_get_pow_666); @@ -23199,7 +23255,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_673 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_673, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_671, ret_val_get_sew_pow_672), ret_val_get_lmul_pow_673)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_671, ret_val_get_sew_pow_672), ret_val_get_lmul_pow_673)), 8, true); setArg(call_get_pow_671, 0, reinterpret_cast(this)); setArg(call_get_pow_671, 1, EEW); setRet(call_get_pow_671, 0, ret_val_get_pow_671); @@ -23322,7 +23378,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_678 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_678, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_676, ret_val_get_sew_pow_677), ret_val_get_lmul_pow_678)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_676, ret_val_get_sew_pow_677), ret_val_get_lmul_pow_678)), 8, true); setArg(call_get_pow_676, 0, reinterpret_cast(this)); setArg(call_get_pow_676, 1, EEW); setRet(call_get_pow_676, 0, ret_val_get_pow_676); @@ -23445,7 +23501,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_683 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_683, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_681, ret_val_get_sew_pow_682), ret_val_get_lmul_pow_683)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_681, ret_val_get_sew_pow_682), ret_val_get_lmul_pow_683)), 8, true); setArg(call_get_pow_681, 0, reinterpret_cast(this)); setArg(call_get_pow_681, 1, EEW); setRet(call_get_pow_681, 0, ret_val_get_pow_681); @@ -23568,7 +23624,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_688 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_688, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_686, ret_val_get_sew_pow_687), ret_val_get_lmul_pow_688)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_686, ret_val_get_sew_pow_687), ret_val_get_lmul_pow_688)), 8, true); setArg(call_get_pow_686, 0, reinterpret_cast(this)); setArg(call_get_pow_686, 1, EEW); setRet(call_get_pow_686, 0, ret_val_get_pow_686); @@ -23691,7 +23747,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_693 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_693, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_691, ret_val_get_sew_pow_692), ret_val_get_lmul_pow_693)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_691, ret_val_get_sew_pow_692), ret_val_get_lmul_pow_693)), 8, true); setArg(call_get_pow_691, 0, reinterpret_cast(this)); setArg(call_get_pow_691, 1, EEW); setRet(call_get_pow_691, 0, ret_val_get_pow_691); @@ -23814,7 +23870,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_698 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_698, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_696, ret_val_get_sew_pow_697), ret_val_get_lmul_pow_698)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_696, ret_val_get_sew_pow_697), ret_val_get_lmul_pow_698)), 8, true); setArg(call_get_pow_696, 0, reinterpret_cast(this)); setArg(call_get_pow_696, 1, EEW); setRet(call_get_pow_696, 0, ret_val_get_pow_696); @@ -23937,7 +23993,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_703 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_703, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_701, ret_val_get_sew_pow_702), ret_val_get_lmul_pow_703)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_701, ret_val_get_sew_pow_702), ret_val_get_lmul_pow_703)), 8, true); setArg(call_get_pow_701, 0, reinterpret_cast(this)); setArg(call_get_pow_701, 1, EEW); setRet(call_get_pow_701, 0, ret_val_get_pow_701); @@ -24060,7 +24116,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_708 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_708, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_706, ret_val_get_sew_pow_707), ret_val_get_lmul_pow_708)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_706, ret_val_get_sew_pow_707), ret_val_get_lmul_pow_708)), 8, true); setArg(call_get_pow_706, 0, reinterpret_cast(this)); setArg(call_get_pow_706, 1, EEW); setRet(call_get_pow_706, 0, ret_val_get_pow_706); @@ -24183,7 +24239,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_713 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_713, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_711, ret_val_get_sew_pow_712), ret_val_get_lmul_pow_713)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_711, ret_val_get_sew_pow_712), ret_val_get_lmul_pow_713)), 8, true); setArg(call_get_pow_711, 0, reinterpret_cast(this)); setArg(call_get_pow_711, 1, EEW); setRet(call_get_pow_711, 0, ret_val_get_pow_711); @@ -24306,7 +24362,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_718 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_718, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_716, ret_val_get_sew_pow_717), ret_val_get_lmul_pow_718)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_716, ret_val_get_sew_pow_717), ret_val_get_lmul_pow_718)), 8, true); setArg(call_get_pow_716, 0, reinterpret_cast(this)); setArg(call_get_pow_716, 1, EEW); setRet(call_get_pow_716, 0, ret_val_get_pow_716); @@ -24429,7 +24485,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_723 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_723, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_721, ret_val_get_sew_pow_722), ret_val_get_lmul_pow_723)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_721, ret_val_get_sew_pow_722), ret_val_get_lmul_pow_723)), 8, true); setArg(call_get_pow_721, 0, reinterpret_cast(this)); setArg(call_get_pow_721, 1, EEW); setRet(call_get_pow_721, 0, ret_val_get_pow_721); @@ -24552,7 +24608,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_728 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_728, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_726, ret_val_get_sew_pow_727), ret_val_get_lmul_pow_728)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_726, ret_val_get_sew_pow_727), ret_val_get_lmul_pow_728)), 8, true); setArg(call_get_pow_726, 0, reinterpret_cast(this)); setArg(call_get_pow_726, 1, EEW); setRet(call_get_pow_726, 0, ret_val_get_pow_726); @@ -24675,7 +24731,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_733 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_733, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_731, ret_val_get_sew_pow_732), ret_val_get_lmul_pow_733)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_731, ret_val_get_sew_pow_732), ret_val_get_lmul_pow_733)), 8, true); setArg(call_get_pow_731, 0, reinterpret_cast(this)); setArg(call_get_pow_731, 1, EEW); setRet(call_get_pow_731, 0, ret_val_get_pow_731); @@ -24798,7 +24854,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_738 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_738, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_736, ret_val_get_sew_pow_737), ret_val_get_lmul_pow_738)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_736, ret_val_get_sew_pow_737), ret_val_get_lmul_pow_738)), 8, true); setArg(call_get_pow_736, 0, reinterpret_cast(this)); setArg(call_get_pow_736, 1, EEW); setRet(call_get_pow_736, 0, ret_val_get_pow_736); @@ -24921,7 +24977,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_743 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_743, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_741, ret_val_get_sew_pow_742), ret_val_get_lmul_pow_743)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_741, ret_val_get_sew_pow_742), ret_val_get_lmul_pow_743)), 8, true); setArg(call_get_pow_741, 0, reinterpret_cast(this)); setArg(call_get_pow_741, 1, EEW); setRet(call_get_pow_741, 0, ret_val_get_pow_741); @@ -25044,7 +25100,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_748 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_748, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_746, ret_val_get_sew_pow_747), ret_val_get_lmul_pow_748)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_746, ret_val_get_sew_pow_747), ret_val_get_lmul_pow_748)), 8, true); setArg(call_get_pow_746, 0, reinterpret_cast(this)); setArg(call_get_pow_746, 1, EEW); setRet(call_get_pow_746, 0, ret_val_get_pow_746); @@ -25167,7 +25223,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_753 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_753, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_751, ret_val_get_sew_pow_752), ret_val_get_lmul_pow_753)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_751, ret_val_get_sew_pow_752), ret_val_get_lmul_pow_753)), 8, true); setArg(call_get_pow_751, 0, reinterpret_cast(this)); setArg(call_get_pow_751, 1, EEW); setRet(call_get_pow_751, 0, ret_val_get_pow_751); @@ -25290,7 +25346,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_758 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_758, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_756, ret_val_get_sew_pow_757), ret_val_get_lmul_pow_758)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_756, ret_val_get_sew_pow_757), ret_val_get_lmul_pow_758)), 8, true); setArg(call_get_pow_756, 0, reinterpret_cast(this)); setArg(call_get_pow_756, 1, EEW); setRet(call_get_pow_756, 0, ret_val_get_pow_756); @@ -25413,7 +25469,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_763 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_763, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_761, ret_val_get_sew_pow_762), ret_val_get_lmul_pow_763)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_761, ret_val_get_sew_pow_762), ret_val_get_lmul_pow_763)), 8, true); setArg(call_get_pow_761, 0, reinterpret_cast(this)); setArg(call_get_pow_761, 1, EEW); setRet(call_get_pow_761, 0, ret_val_get_pow_761); @@ -25536,7 +25592,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_768 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_768, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_766, ret_val_get_sew_pow_767), ret_val_get_lmul_pow_768)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_766, ret_val_get_sew_pow_767), ret_val_get_lmul_pow_768)), 8, true); setArg(call_get_pow_766, 0, reinterpret_cast(this)); setArg(call_get_pow_766, 1, EEW); setRet(call_get_pow_766, 0, ret_val_get_pow_766); @@ -25659,7 +25715,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_773 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_773, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_771, ret_val_get_sew_pow_772), ret_val_get_lmul_pow_773)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_771, ret_val_get_sew_pow_772), ret_val_get_lmul_pow_773)), 8, true); setArg(call_get_pow_771, 0, reinterpret_cast(this)); setArg(call_get_pow_771, 1, EEW); setRet(call_get_pow_771, 0, ret_val_get_pow_771); @@ -25782,7 +25838,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_778 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_778, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_776, ret_val_get_sew_pow_777), ret_val_get_lmul_pow_778)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_776, ret_val_get_sew_pow_777), ret_val_get_lmul_pow_778)), 8, true); setArg(call_get_pow_776, 0, reinterpret_cast(this)); setArg(call_get_pow_776, 1, EEW); setRet(call_get_pow_776, 0, ret_val_get_pow_776); @@ -25905,7 +25961,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_783 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_783, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_781, ret_val_get_sew_pow_782), ret_val_get_lmul_pow_783)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_781, ret_val_get_sew_pow_782), ret_val_get_lmul_pow_783)), 8, true); setArg(call_get_pow_781, 0, reinterpret_cast(this)); setArg(call_get_pow_781, 1, EEW); setRet(call_get_pow_781, 0, ret_val_get_pow_781); @@ -26028,7 +26084,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_788 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_788, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_786, ret_val_get_sew_pow_787), ret_val_get_lmul_pow_788)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_786, ret_val_get_sew_pow_787), ret_val_get_lmul_pow_788)), 8, true); setArg(call_get_pow_786, 0, reinterpret_cast(this)); setArg(call_get_pow_786, 1, EEW); setRet(call_get_pow_786, 0, ret_val_get_pow_786); @@ -26151,7 +26207,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_793 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_793, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_791, ret_val_get_sew_pow_792), ret_val_get_lmul_pow_793)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_791, ret_val_get_sew_pow_792), ret_val_get_lmul_pow_793)), 8, true); setArg(call_get_pow_791, 0, reinterpret_cast(this)); setArg(call_get_pow_791, 1, EEW); setRet(call_get_pow_791, 0, ret_val_get_pow_791); @@ -26272,7 +26328,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_798 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_798, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_796, ret_val_get_sew_pow_797), ret_val_get_lmul_pow_798)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_796, ret_val_get_sew_pow_797), ret_val_get_lmul_pow_798)), 8, true); setArg(call_get_pow_796, 0, reinterpret_cast(this)); setArg(call_get_pow_796, 1, EEW); setRet(call_get_pow_796, 0, ret_val_get_pow_796); @@ -26393,7 +26449,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_803 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_803, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_801, ret_val_get_sew_pow_802), ret_val_get_lmul_pow_803)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_801, ret_val_get_sew_pow_802), ret_val_get_lmul_pow_803)), 8, true); setArg(call_get_pow_801, 0, reinterpret_cast(this)); setArg(call_get_pow_801, 1, EEW); setRet(call_get_pow_801, 0, ret_val_get_pow_801); @@ -26514,7 +26570,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_808 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_808, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_806, ret_val_get_sew_pow_807), ret_val_get_lmul_pow_808)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_806, ret_val_get_sew_pow_807), ret_val_get_lmul_pow_808)), 8, true); setArg(call_get_pow_806, 0, reinterpret_cast(this)); setArg(call_get_pow_806, 1, EEW); setRet(call_get_pow_806, 0, ret_val_get_pow_806); @@ -26635,7 +26691,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_813 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_813, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_811, ret_val_get_sew_pow_812), ret_val_get_lmul_pow_813)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_811, ret_val_get_sew_pow_812), ret_val_get_lmul_pow_813)), 8, true); setArg(call_get_pow_811, 0, reinterpret_cast(this)); setArg(call_get_pow_811, 1, EEW); setRet(call_get_pow_811, 0, ret_val_get_pow_811); @@ -26756,7 +26812,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_818 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_818, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_816, ret_val_get_sew_pow_817), ret_val_get_lmul_pow_818)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_816, ret_val_get_sew_pow_817), ret_val_get_lmul_pow_818)), 8, true); setArg(call_get_pow_816, 0, reinterpret_cast(this)); setArg(call_get_pow_816, 1, EEW); setRet(call_get_pow_816, 0, ret_val_get_pow_816); @@ -26877,7 +26933,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_823 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_823, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_821, ret_val_get_sew_pow_822), ret_val_get_lmul_pow_823)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_821, ret_val_get_sew_pow_822), ret_val_get_lmul_pow_823)), 8, true); setArg(call_get_pow_821, 0, reinterpret_cast(this)); setArg(call_get_pow_821, 1, EEW); setRet(call_get_pow_821, 0, ret_val_get_pow_821); @@ -26998,7 +27054,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_828 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_828, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_826, ret_val_get_sew_pow_827), ret_val_get_lmul_pow_828)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_826, ret_val_get_sew_pow_827), ret_val_get_lmul_pow_828)), 8, true); setArg(call_get_pow_826, 0, reinterpret_cast(this)); setArg(call_get_pow_826, 1, EEW); setRet(call_get_pow_826, 0, ret_val_get_pow_826); @@ -27119,7 +27175,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_833 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_833, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_831, ret_val_get_sew_pow_832), ret_val_get_lmul_pow_833)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_831, ret_val_get_sew_pow_832), ret_val_get_lmul_pow_833)), 8, true); setArg(call_get_pow_831, 0, reinterpret_cast(this)); setArg(call_get_pow_831, 1, EEW); setRet(call_get_pow_831, 0, ret_val_get_pow_831); @@ -27240,7 +27296,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_838 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_838, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_836, ret_val_get_sew_pow_837), ret_val_get_lmul_pow_838)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_836, ret_val_get_sew_pow_837), ret_val_get_lmul_pow_838)), 8, true); setArg(call_get_pow_836, 0, reinterpret_cast(this)); setArg(call_get_pow_836, 1, EEW); setRet(call_get_pow_836, 0, ret_val_get_pow_836); @@ -27361,7 +27417,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_843 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_843, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_841, ret_val_get_sew_pow_842), ret_val_get_lmul_pow_843)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_841, ret_val_get_sew_pow_842), ret_val_get_lmul_pow_843)), 8, true); setArg(call_get_pow_841, 0, reinterpret_cast(this)); setArg(call_get_pow_841, 1, EEW); setRet(call_get_pow_841, 0, ret_val_get_pow_841); @@ -27482,7 +27538,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_848 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_848, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_846, ret_val_get_sew_pow_847), ret_val_get_lmul_pow_848)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_846, ret_val_get_sew_pow_847), ret_val_get_lmul_pow_848)), 8, true); setArg(call_get_pow_846, 0, reinterpret_cast(this)); setArg(call_get_pow_846, 1, EEW); setRet(call_get_pow_846, 0, ret_val_get_pow_846); @@ -27603,7 +27659,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_853 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_853, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_851, ret_val_get_sew_pow_852), ret_val_get_lmul_pow_853)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_851, ret_val_get_sew_pow_852), ret_val_get_lmul_pow_853)), 8, true); setArg(call_get_pow_851, 0, reinterpret_cast(this)); setArg(call_get_pow_851, 1, EEW); setRet(call_get_pow_851, 0, ret_val_get_pow_851); @@ -27724,7 +27780,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_858 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_858, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_856, ret_val_get_sew_pow_857), ret_val_get_lmul_pow_858)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_856, ret_val_get_sew_pow_857), ret_val_get_lmul_pow_858)), 8, true); setArg(call_get_pow_856, 0, reinterpret_cast(this)); setArg(call_get_pow_856, 1, EEW); setRet(call_get_pow_856, 0, ret_val_get_pow_856); @@ -27845,7 +27901,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_863 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_863, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_861, ret_val_get_sew_pow_862), ret_val_get_lmul_pow_863)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_861, ret_val_get_sew_pow_862), ret_val_get_lmul_pow_863)), 8, true); setArg(call_get_pow_861, 0, reinterpret_cast(this)); setArg(call_get_pow_861, 1, EEW); setRet(call_get_pow_861, 0, ret_val_get_pow_861); @@ -27966,7 +28022,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_868 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_868, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_866, ret_val_get_sew_pow_867), ret_val_get_lmul_pow_868)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_866, ret_val_get_sew_pow_867), ret_val_get_lmul_pow_868)), 8, true); setArg(call_get_pow_866, 0, reinterpret_cast(this)); setArg(call_get_pow_866, 1, EEW); setRet(call_get_pow_866, 0, ret_val_get_pow_866); @@ -28087,7 +28143,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_873 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_873, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_871, ret_val_get_sew_pow_872), ret_val_get_lmul_pow_873)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_871, ret_val_get_sew_pow_872), ret_val_get_lmul_pow_873)), 8, true); setArg(call_get_pow_871, 0, reinterpret_cast(this)); setArg(call_get_pow_871, 1, EEW); setRet(call_get_pow_871, 0, ret_val_get_pow_871); @@ -28208,7 +28264,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_878 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_878, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_876, ret_val_get_sew_pow_877), ret_val_get_lmul_pow_878)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_876, ret_val_get_sew_pow_877), ret_val_get_lmul_pow_878)), 8, true); setArg(call_get_pow_876, 0, reinterpret_cast(this)); setArg(call_get_pow_876, 1, EEW); setRet(call_get_pow_876, 0, ret_val_get_pow_876); @@ -28329,7 +28385,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_883 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_883, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_881, ret_val_get_sew_pow_882), ret_val_get_lmul_pow_883)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_881, ret_val_get_sew_pow_882), ret_val_get_lmul_pow_883)), 8, true); setArg(call_get_pow_881, 0, reinterpret_cast(this)); setArg(call_get_pow_881, 1, EEW); setRet(call_get_pow_881, 0, ret_val_get_pow_881); @@ -28450,7 +28506,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_888 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_888, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_886, ret_val_get_sew_pow_887), ret_val_get_lmul_pow_888)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_886, ret_val_get_sew_pow_887), ret_val_get_lmul_pow_888)), 8, true); setArg(call_get_pow_886, 0, reinterpret_cast(this)); setArg(call_get_pow_886, 1, EEW); setRet(call_get_pow_886, 0, ret_val_get_pow_886); @@ -28571,7 +28627,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_893 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_893, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_891, ret_val_get_sew_pow_892), ret_val_get_lmul_pow_893)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_891, ret_val_get_sew_pow_892), ret_val_get_lmul_pow_893)), 8, true); setArg(call_get_pow_891, 0, reinterpret_cast(this)); setArg(call_get_pow_891, 1, EEW); setRet(call_get_pow_891, 0, ret_val_get_pow_891); @@ -28692,7 +28748,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_898 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_898, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_896, ret_val_get_sew_pow_897), ret_val_get_lmul_pow_898)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_896, ret_val_get_sew_pow_897), ret_val_get_lmul_pow_898)), 8, true); setArg(call_get_pow_896, 0, reinterpret_cast(this)); setArg(call_get_pow_896, 1, EEW); setRet(call_get_pow_896, 0, ret_val_get_pow_896); @@ -28813,7 +28869,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_903 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_903, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_901, ret_val_get_sew_pow_902), ret_val_get_lmul_pow_903)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_901, ret_val_get_sew_pow_902), ret_val_get_lmul_pow_903)), 8, true); setArg(call_get_pow_901, 0, reinterpret_cast(this)); setArg(call_get_pow_901, 1, EEW); setRet(call_get_pow_901, 0, ret_val_get_pow_901); @@ -28934,7 +28990,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_908 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_908, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_906, ret_val_get_sew_pow_907), ret_val_get_lmul_pow_908)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_906, ret_val_get_sew_pow_907), ret_val_get_lmul_pow_908)), 8, true); setArg(call_get_pow_906, 0, reinterpret_cast(this)); setArg(call_get_pow_906, 1, EEW); setRet(call_get_pow_906, 0, ret_val_get_pow_906); @@ -29055,7 +29111,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_913 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_913, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_911, ret_val_get_sew_pow_912), ret_val_get_lmul_pow_913)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_911, ret_val_get_sew_pow_912), ret_val_get_lmul_pow_913)), 8, true); setArg(call_get_pow_911, 0, reinterpret_cast(this)); setArg(call_get_pow_911, 1, EEW); setRet(call_get_pow_911, 0, ret_val_get_pow_911); @@ -29176,7 +29232,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_918 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_918, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_916, ret_val_get_sew_pow_917), ret_val_get_lmul_pow_918)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_916, ret_val_get_sew_pow_917), ret_val_get_lmul_pow_918)), 8, true); setArg(call_get_pow_916, 0, reinterpret_cast(this)); setArg(call_get_pow_916, 1, EEW); setRet(call_get_pow_916, 0, ret_val_get_pow_916); @@ -29297,7 +29353,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_923 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_923, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_921, ret_val_get_sew_pow_922), ret_val_get_lmul_pow_923)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_921, ret_val_get_sew_pow_922), ret_val_get_lmul_pow_923)), 8, true); setArg(call_get_pow_921, 0, reinterpret_cast(this)); setArg(call_get_pow_921, 1, EEW); setRet(call_get_pow_921, 0, ret_val_get_pow_921); @@ -29418,7 +29474,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_928 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_928, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_926, ret_val_get_sew_pow_927), ret_val_get_lmul_pow_928)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_926, ret_val_get_sew_pow_927), ret_val_get_lmul_pow_928)), 8, true); setArg(call_get_pow_926, 0, reinterpret_cast(this)); setArg(call_get_pow_926, 1, EEW); setRet(call_get_pow_926, 0, ret_val_get_pow_926); @@ -29539,7 +29595,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_933 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_933, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_931, ret_val_get_sew_pow_932), ret_val_get_lmul_pow_933)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_931, ret_val_get_sew_pow_932), ret_val_get_lmul_pow_933)), 8, true); setArg(call_get_pow_931, 0, reinterpret_cast(this)); setArg(call_get_pow_931, 1, EEW); setRet(call_get_pow_931, 0, ret_val_get_pow_931); @@ -29660,7 +29716,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_938 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_938, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_936, ret_val_get_sew_pow_937), ret_val_get_lmul_pow_938)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_936, ret_val_get_sew_pow_937), ret_val_get_lmul_pow_938)), 8, true); setArg(call_get_pow_936, 0, reinterpret_cast(this)); setArg(call_get_pow_936, 1, EEW); setRet(call_get_pow_936, 0, ret_val_get_pow_936); @@ -29781,7 +29837,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_943 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_943, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_941, ret_val_get_sew_pow_942), ret_val_get_lmul_pow_943)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_941, ret_val_get_sew_pow_942), ret_val_get_lmul_pow_943)), 8, true); setArg(call_get_pow_941, 0, reinterpret_cast(this)); setArg(call_get_pow_941, 1, EEW); setRet(call_get_pow_941, 0, ret_val_get_pow_941); @@ -29902,7 +29958,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_948 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_948, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_946, ret_val_get_sew_pow_947), ret_val_get_lmul_pow_948)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_946, ret_val_get_sew_pow_947), ret_val_get_lmul_pow_948)), 8, true); setArg(call_get_pow_946, 0, reinterpret_cast(this)); setArg(call_get_pow_946, 1, EEW); setRet(call_get_pow_946, 0, ret_val_get_pow_946); @@ -30022,7 +30078,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_953 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_953, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_951, ret_val_get_sew_pow_952), ret_val_get_lmul_pow_953)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_951, ret_val_get_sew_pow_952), ret_val_get_lmul_pow_953)), 8, true); setArg(call_get_pow_951, 0, reinterpret_cast(this)); setArg(call_get_pow_951, 1, EEW); setRet(call_get_pow_951, 0, ret_val_get_pow_951); @@ -30145,7 +30201,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_958 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_958, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_956, ret_val_get_sew_pow_957), ret_val_get_lmul_pow_958)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_956, ret_val_get_sew_pow_957), ret_val_get_lmul_pow_958)), 8, true); setArg(call_get_pow_956, 0, reinterpret_cast(this)); setArg(call_get_pow_956, 1, EEW); setRet(call_get_pow_956, 0, ret_val_get_pow_956); @@ -30268,7 +30324,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_963 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_963, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_961, ret_val_get_sew_pow_962), ret_val_get_lmul_pow_963)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_961, ret_val_get_sew_pow_962), ret_val_get_lmul_pow_963)), 8, true); setArg(call_get_pow_961, 0, reinterpret_cast(this)); setArg(call_get_pow_961, 1, EEW); setRet(call_get_pow_961, 0, ret_val_get_pow_961); @@ -30391,7 +30447,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_968 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_968, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_966, ret_val_get_sew_pow_967), ret_val_get_lmul_pow_968)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_966, ret_val_get_sew_pow_967), ret_val_get_lmul_pow_968)), 8, true); setArg(call_get_pow_966, 0, reinterpret_cast(this)); setArg(call_get_pow_966, 1, EEW); setRet(call_get_pow_966, 0, ret_val_get_pow_966); @@ -30514,7 +30570,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_973 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_973, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_971, ret_val_get_sew_pow_972), ret_val_get_lmul_pow_973)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_971, ret_val_get_sew_pow_972), ret_val_get_lmul_pow_973)), 8, true); setArg(call_get_pow_971, 0, reinterpret_cast(this)); setArg(call_get_pow_971, 1, EEW); setRet(call_get_pow_971, 0, ret_val_get_pow_971); @@ -30637,7 +30693,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_978 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_978, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_976, ret_val_get_sew_pow_977), ret_val_get_lmul_pow_978)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_976, ret_val_get_sew_pow_977), ret_val_get_lmul_pow_978)), 8, true); setArg(call_get_pow_976, 0, reinterpret_cast(this)); setArg(call_get_pow_976, 1, EEW); setRet(call_get_pow_976, 0, ret_val_get_pow_976); @@ -30760,7 +30816,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_983 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_983, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_981, ret_val_get_sew_pow_982), ret_val_get_lmul_pow_983)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_981, ret_val_get_sew_pow_982), ret_val_get_lmul_pow_983)), 8, true); setArg(call_get_pow_981, 0, reinterpret_cast(this)); setArg(call_get_pow_981, 1, EEW); setRet(call_get_pow_981, 0, ret_val_get_pow_981); @@ -30883,7 +30939,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_988 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_988, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_986, ret_val_get_sew_pow_987), ret_val_get_lmul_pow_988)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_986, ret_val_get_sew_pow_987), ret_val_get_lmul_pow_988)), 8, true); setArg(call_get_pow_986, 0, reinterpret_cast(this)); setArg(call_get_pow_986, 1, EEW); setRet(call_get_pow_986, 0, ret_val_get_pow_986); @@ -31006,7 +31062,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_993 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_993, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_991, ret_val_get_sew_pow_992), ret_val_get_lmul_pow_993)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_991, ret_val_get_sew_pow_992), ret_val_get_lmul_pow_993)), 8, true); setArg(call_get_pow_991, 0, reinterpret_cast(this)); setArg(call_get_pow_991, 1, EEW); setRet(call_get_pow_991, 0, ret_val_get_pow_991); @@ -31129,7 +31185,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_998 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_998, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_996, ret_val_get_sew_pow_997), ret_val_get_lmul_pow_998)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_996, ret_val_get_sew_pow_997), ret_val_get_lmul_pow_998)), 8, true); setArg(call_get_pow_996, 0, reinterpret_cast(this)); setArg(call_get_pow_996, 1, EEW); setRet(call_get_pow_996, 0, ret_val_get_pow_996); @@ -31252,7 +31308,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1003 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1003, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1001, ret_val_get_sew_pow_1002), ret_val_get_lmul_pow_1003)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1001, ret_val_get_sew_pow_1002), ret_val_get_lmul_pow_1003)), 8, true); setArg(call_get_pow_1001, 0, reinterpret_cast(this)); setArg(call_get_pow_1001, 1, EEW); setRet(call_get_pow_1001, 0, ret_val_get_pow_1001); @@ -31375,7 +31431,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1008 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1008, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1006, ret_val_get_sew_pow_1007), ret_val_get_lmul_pow_1008)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1006, ret_val_get_sew_pow_1007), ret_val_get_lmul_pow_1008)), 8, true); setArg(call_get_pow_1006, 0, reinterpret_cast(this)); setArg(call_get_pow_1006, 1, EEW); setRet(call_get_pow_1006, 0, ret_val_get_pow_1006); @@ -31498,7 +31554,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1013 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1013, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1011, ret_val_get_sew_pow_1012), ret_val_get_lmul_pow_1013)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1011, ret_val_get_sew_pow_1012), ret_val_get_lmul_pow_1013)), 8, true); setArg(call_get_pow_1011, 0, reinterpret_cast(this)); setArg(call_get_pow_1011, 1, EEW); setRet(call_get_pow_1011, 0, ret_val_get_pow_1011); @@ -31621,7 +31677,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1018 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1018, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1016, ret_val_get_sew_pow_1017), ret_val_get_lmul_pow_1018)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1016, ret_val_get_sew_pow_1017), ret_val_get_lmul_pow_1018)), 8, true); setArg(call_get_pow_1016, 0, reinterpret_cast(this)); setArg(call_get_pow_1016, 1, EEW); setRet(call_get_pow_1016, 0, ret_val_get_pow_1016); @@ -31744,7 +31800,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1023 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1023, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1021, ret_val_get_sew_pow_1022), ret_val_get_lmul_pow_1023)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1021, ret_val_get_sew_pow_1022), ret_val_get_lmul_pow_1023)), 8, true); setArg(call_get_pow_1021, 0, reinterpret_cast(this)); setArg(call_get_pow_1021, 1, EEW); setRet(call_get_pow_1021, 0, ret_val_get_pow_1021); @@ -31867,7 +31923,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1028 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1028, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1026, ret_val_get_sew_pow_1027), ret_val_get_lmul_pow_1028)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1026, ret_val_get_sew_pow_1027), ret_val_get_lmul_pow_1028)), 8, true); setArg(call_get_pow_1026, 0, reinterpret_cast(this)); setArg(call_get_pow_1026, 1, EEW); setRet(call_get_pow_1026, 0, ret_val_get_pow_1026); @@ -31990,7 +32046,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1033 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1033, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1031, ret_val_get_sew_pow_1032), ret_val_get_lmul_pow_1033)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1031, ret_val_get_sew_pow_1032), ret_val_get_lmul_pow_1033)), 8, true); setArg(call_get_pow_1031, 0, reinterpret_cast(this)); setArg(call_get_pow_1031, 1, EEW); setRet(call_get_pow_1031, 0, ret_val_get_pow_1031); @@ -32113,7 +32169,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1038 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1038, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1036, ret_val_get_sew_pow_1037), ret_val_get_lmul_pow_1038)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1036, ret_val_get_sew_pow_1037), ret_val_get_lmul_pow_1038)), 8, true); setArg(call_get_pow_1036, 0, reinterpret_cast(this)); setArg(call_get_pow_1036, 1, EEW); setRet(call_get_pow_1036, 0, ret_val_get_pow_1036); @@ -32236,7 +32292,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1043 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1043, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1041, ret_val_get_sew_pow_1042), ret_val_get_lmul_pow_1043)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1041, ret_val_get_sew_pow_1042), ret_val_get_lmul_pow_1043)), 8, true); setArg(call_get_pow_1041, 0, reinterpret_cast(this)); setArg(call_get_pow_1041, 1, EEW); setRet(call_get_pow_1041, 0, ret_val_get_pow_1041); @@ -32359,7 +32415,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1048 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1048, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1046, ret_val_get_sew_pow_1047), ret_val_get_lmul_pow_1048)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1046, ret_val_get_sew_pow_1047), ret_val_get_lmul_pow_1048)), 8, true); setArg(call_get_pow_1046, 0, reinterpret_cast(this)); setArg(call_get_pow_1046, 1, EEW); setRet(call_get_pow_1046, 0, ret_val_get_pow_1046); @@ -32482,7 +32538,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1053 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1053, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1051, ret_val_get_sew_pow_1052), ret_val_get_lmul_pow_1053)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1051, ret_val_get_sew_pow_1052), ret_val_get_lmul_pow_1053)), 8, true); setArg(call_get_pow_1051, 0, reinterpret_cast(this)); setArg(call_get_pow_1051, 1, EEW); setRet(call_get_pow_1051, 0, ret_val_get_pow_1051); @@ -32605,7 +32661,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1058 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1058, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1056, ret_val_get_sew_pow_1057), ret_val_get_lmul_pow_1058)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1056, ret_val_get_sew_pow_1057), ret_val_get_lmul_pow_1058)), 8, true); setArg(call_get_pow_1056, 0, reinterpret_cast(this)); setArg(call_get_pow_1056, 1, EEW); setRet(call_get_pow_1056, 0, ret_val_get_pow_1056); @@ -32728,7 +32784,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1063 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1063, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1061, ret_val_get_sew_pow_1062), ret_val_get_lmul_pow_1063)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1061, ret_val_get_sew_pow_1062), ret_val_get_lmul_pow_1063)), 8, true); setArg(call_get_pow_1061, 0, reinterpret_cast(this)); setArg(call_get_pow_1061, 1, EEW); setRet(call_get_pow_1061, 0, ret_val_get_pow_1061); @@ -32851,7 +32907,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1068 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1068, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1066, ret_val_get_sew_pow_1067), ret_val_get_lmul_pow_1068)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1066, ret_val_get_sew_pow_1067), ret_val_get_lmul_pow_1068)), 8, true); setArg(call_get_pow_1066, 0, reinterpret_cast(this)); setArg(call_get_pow_1066, 1, EEW); setRet(call_get_pow_1066, 0, ret_val_get_pow_1066); @@ -32974,7 +33030,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1073 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1073, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1071, ret_val_get_sew_pow_1072), ret_val_get_lmul_pow_1073)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1071, ret_val_get_sew_pow_1072), ret_val_get_lmul_pow_1073)), 8, true); setArg(call_get_pow_1071, 0, reinterpret_cast(this)); setArg(call_get_pow_1071, 1, EEW); setRet(call_get_pow_1071, 0, ret_val_get_pow_1071); @@ -33097,7 +33153,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1078 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1078, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1076, ret_val_get_sew_pow_1077), ret_val_get_lmul_pow_1078)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1076, ret_val_get_sew_pow_1077), ret_val_get_lmul_pow_1078)), 8, true); setArg(call_get_pow_1076, 0, reinterpret_cast(this)); setArg(call_get_pow_1076, 1, EEW); setRet(call_get_pow_1076, 0, ret_val_get_pow_1076); @@ -33220,7 +33276,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1083 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1083, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1081, ret_val_get_sew_pow_1082), ret_val_get_lmul_pow_1083)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1081, ret_val_get_sew_pow_1082), ret_val_get_lmul_pow_1083)), 8, true); setArg(call_get_pow_1081, 0, reinterpret_cast(this)); setArg(call_get_pow_1081, 1, EEW); setRet(call_get_pow_1081, 0, ret_val_get_pow_1081); @@ -33343,7 +33399,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1088 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1088, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1086, ret_val_get_sew_pow_1087), ret_val_get_lmul_pow_1088)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1086, ret_val_get_sew_pow_1087), ret_val_get_lmul_pow_1088)), 8, true); setArg(call_get_pow_1086, 0, reinterpret_cast(this)); setArg(call_get_pow_1086, 1, EEW); setRet(call_get_pow_1086, 0, ret_val_get_pow_1086); @@ -33466,7 +33522,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1093 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1093, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1091, ret_val_get_sew_pow_1092), ret_val_get_lmul_pow_1093)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1091, ret_val_get_sew_pow_1092), ret_val_get_lmul_pow_1093)), 8, true); setArg(call_get_pow_1091, 0, reinterpret_cast(this)); setArg(call_get_pow_1091, 1, EEW); setRet(call_get_pow_1091, 0, ret_val_get_pow_1091); @@ -33589,7 +33645,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1098 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1098, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1096, ret_val_get_sew_pow_1097), ret_val_get_lmul_pow_1098)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1096, ret_val_get_sew_pow_1097), ret_val_get_lmul_pow_1098)), 8, true); setArg(call_get_pow_1096, 0, reinterpret_cast(this)); setArg(call_get_pow_1096, 1, EEW); setRet(call_get_pow_1096, 0, ret_val_get_pow_1096); @@ -33712,7 +33768,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1103 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1103, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1101, ret_val_get_sew_pow_1102), ret_val_get_lmul_pow_1103)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1101, ret_val_get_sew_pow_1102), ret_val_get_lmul_pow_1103)), 8, true); setArg(call_get_pow_1101, 0, reinterpret_cast(this)); setArg(call_get_pow_1101, 1, EEW); setRet(call_get_pow_1101, 0, ret_val_get_pow_1101); @@ -33835,7 +33891,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1108 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1108, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1106, ret_val_get_sew_pow_1107), ret_val_get_lmul_pow_1108)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1106, ret_val_get_sew_pow_1107), ret_val_get_lmul_pow_1108)), 8, true); setArg(call_get_pow_1106, 0, reinterpret_cast(this)); setArg(call_get_pow_1106, 1, EEW); setRet(call_get_pow_1106, 0, ret_val_get_pow_1106); @@ -35736,7 +35792,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1159 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1159, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1157, ret_val_get_sew_pow_1158), ret_val_get_lmul_pow_1159)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1157, ret_val_get_sew_pow_1158), ret_val_get_lmul_pow_1159)), 8, true); setArg(call_get_pow_1157, 0, reinterpret_cast(this)); setArg(call_get_pow_1157, 1, EEW); setRet(call_get_pow_1157, 0, ret_val_get_pow_1157); @@ -35873,7 +35929,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1166 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1166, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1164, ret_val_get_sew_pow_1165), ret_val_get_lmul_pow_1166)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1164, ret_val_get_sew_pow_1165), ret_val_get_lmul_pow_1166)), 8, true); setArg(call_get_pow_1164, 0, reinterpret_cast(this)); setArg(call_get_pow_1164, 1, EEW); setRet(call_get_pow_1164, 0, ret_val_get_pow_1164); @@ -36010,7 +36066,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1173 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1173, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1171, ret_val_get_sew_pow_1172), ret_val_get_lmul_pow_1173)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1171, ret_val_get_sew_pow_1172), ret_val_get_lmul_pow_1173)), 8, true); setArg(call_get_pow_1171, 0, reinterpret_cast(this)); setArg(call_get_pow_1171, 1, EEW); setRet(call_get_pow_1171, 0, ret_val_get_pow_1171); @@ -36147,7 +36203,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1180 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1180, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1178, ret_val_get_sew_pow_1179), ret_val_get_lmul_pow_1180)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1178, ret_val_get_sew_pow_1179), ret_val_get_lmul_pow_1180)), 8, true); setArg(call_get_pow_1178, 0, reinterpret_cast(this)); setArg(call_get_pow_1178, 1, EEW); setRet(call_get_pow_1178, 0, ret_val_get_pow_1178); @@ -36284,7 +36340,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1187 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1187, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1185, ret_val_get_sew_pow_1186), ret_val_get_lmul_pow_1187)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1185, ret_val_get_sew_pow_1186), ret_val_get_lmul_pow_1187)), 8, true); setArg(call_get_pow_1185, 0, reinterpret_cast(this)); setArg(call_get_pow_1185, 1, EEW); setRet(call_get_pow_1185, 0, ret_val_get_pow_1185); @@ -36421,7 +36477,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1194 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1194, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1192, ret_val_get_sew_pow_1193), ret_val_get_lmul_pow_1194)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1192, ret_val_get_sew_pow_1193), ret_val_get_lmul_pow_1194)), 8, true); setArg(call_get_pow_1192, 0, reinterpret_cast(this)); setArg(call_get_pow_1192, 1, EEW); setRet(call_get_pow_1192, 0, ret_val_get_pow_1192); @@ -36558,7 +36614,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1201 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1201, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1199, ret_val_get_sew_pow_1200), ret_val_get_lmul_pow_1201)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1199, ret_val_get_sew_pow_1200), ret_val_get_lmul_pow_1201)), 8, true); setArg(call_get_pow_1199, 0, reinterpret_cast(this)); setArg(call_get_pow_1199, 1, EEW); setRet(call_get_pow_1199, 0, ret_val_get_pow_1199); @@ -36695,7 +36751,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1208 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1208, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1206, ret_val_get_sew_pow_1207), ret_val_get_lmul_pow_1208)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1206, ret_val_get_sew_pow_1207), ret_val_get_lmul_pow_1208)), 8, true); setArg(call_get_pow_1206, 0, reinterpret_cast(this)); setArg(call_get_pow_1206, 1, EEW); setRet(call_get_pow_1206, 0, ret_val_get_pow_1206); @@ -36832,7 +36888,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1215 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1215, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1213, ret_val_get_sew_pow_1214), ret_val_get_lmul_pow_1215)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1213, ret_val_get_sew_pow_1214), ret_val_get_lmul_pow_1215)), 8, true); setArg(call_get_pow_1213, 0, reinterpret_cast(this)); setArg(call_get_pow_1213, 1, EEW); setRet(call_get_pow_1213, 0, ret_val_get_pow_1213); @@ -36969,7 +37025,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1222 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1222, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1220, ret_val_get_sew_pow_1221), ret_val_get_lmul_pow_1222)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1220, ret_val_get_sew_pow_1221), ret_val_get_lmul_pow_1222)), 8, true); setArg(call_get_pow_1220, 0, reinterpret_cast(this)); setArg(call_get_pow_1220, 1, EEW); setRet(call_get_pow_1220, 0, ret_val_get_pow_1220); @@ -37106,7 +37162,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1229 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1229, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1227, ret_val_get_sew_pow_1228), ret_val_get_lmul_pow_1229)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1227, ret_val_get_sew_pow_1228), ret_val_get_lmul_pow_1229)), 8, true); setArg(call_get_pow_1227, 0, reinterpret_cast(this)); setArg(call_get_pow_1227, 1, EEW); setRet(call_get_pow_1227, 0, ret_val_get_pow_1227); @@ -37243,7 +37299,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1236 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1236, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1234, ret_val_get_sew_pow_1235), ret_val_get_lmul_pow_1236)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1234, ret_val_get_sew_pow_1235), ret_val_get_lmul_pow_1236)), 8, true); setArg(call_get_pow_1234, 0, reinterpret_cast(this)); setArg(call_get_pow_1234, 1, EEW); setRet(call_get_pow_1234, 0, ret_val_get_pow_1234); @@ -37380,7 +37436,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1243 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1243, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1241, ret_val_get_sew_pow_1242), ret_val_get_lmul_pow_1243)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1241, ret_val_get_sew_pow_1242), ret_val_get_lmul_pow_1243)), 8, true); setArg(call_get_pow_1241, 0, reinterpret_cast(this)); setArg(call_get_pow_1241, 1, EEW); setRet(call_get_pow_1241, 0, ret_val_get_pow_1241); @@ -37517,7 +37573,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1250 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1250, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1248, ret_val_get_sew_pow_1249), ret_val_get_lmul_pow_1250)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1248, ret_val_get_sew_pow_1249), ret_val_get_lmul_pow_1250)), 8, true); setArg(call_get_pow_1248, 0, reinterpret_cast(this)); setArg(call_get_pow_1248, 1, EEW); setRet(call_get_pow_1248, 0, ret_val_get_pow_1248); @@ -37654,7 +37710,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1257 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1257, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1255, ret_val_get_sew_pow_1256), ret_val_get_lmul_pow_1257)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1255, ret_val_get_sew_pow_1256), ret_val_get_lmul_pow_1257)), 8, true); setArg(call_get_pow_1255, 0, reinterpret_cast(this)); setArg(call_get_pow_1255, 1, EEW); setRet(call_get_pow_1255, 0, ret_val_get_pow_1255); @@ -37791,7 +37847,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1264 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1264, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1262, ret_val_get_sew_pow_1263), ret_val_get_lmul_pow_1264)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1262, ret_val_get_sew_pow_1263), ret_val_get_lmul_pow_1264)), 8, true); setArg(call_get_pow_1262, 0, reinterpret_cast(this)); setArg(call_get_pow_1262, 1, EEW); setRet(call_get_pow_1262, 0, ret_val_get_pow_1262); @@ -37928,7 +37984,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1271 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1271, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1269, ret_val_get_sew_pow_1270), ret_val_get_lmul_pow_1271)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1269, ret_val_get_sew_pow_1270), ret_val_get_lmul_pow_1271)), 8, true); setArg(call_get_pow_1269, 0, reinterpret_cast(this)); setArg(call_get_pow_1269, 1, EEW); setRet(call_get_pow_1269, 0, ret_val_get_pow_1269); @@ -38065,7 +38121,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1278 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1278, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1276, ret_val_get_sew_pow_1277), ret_val_get_lmul_pow_1278)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1276, ret_val_get_sew_pow_1277), ret_val_get_lmul_pow_1278)), 8, true); setArg(call_get_pow_1276, 0, reinterpret_cast(this)); setArg(call_get_pow_1276, 1, EEW); setRet(call_get_pow_1276, 0, ret_val_get_pow_1276); @@ -38202,7 +38258,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1285 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1285, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1283, ret_val_get_sew_pow_1284), ret_val_get_lmul_pow_1285)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1283, ret_val_get_sew_pow_1284), ret_val_get_lmul_pow_1285)), 8, true); setArg(call_get_pow_1283, 0, reinterpret_cast(this)); setArg(call_get_pow_1283, 1, EEW); setRet(call_get_pow_1283, 0, ret_val_get_pow_1283); @@ -38339,7 +38395,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1292 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1292, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1290, ret_val_get_sew_pow_1291), ret_val_get_lmul_pow_1292)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1290, ret_val_get_sew_pow_1291), ret_val_get_lmul_pow_1292)), 8, true); setArg(call_get_pow_1290, 0, reinterpret_cast(this)); setArg(call_get_pow_1290, 1, EEW); setRet(call_get_pow_1290, 0, ret_val_get_pow_1290); @@ -38476,7 +38532,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1299 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1299, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1297, ret_val_get_sew_pow_1298), ret_val_get_lmul_pow_1299)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1297, ret_val_get_sew_pow_1298), ret_val_get_lmul_pow_1299)), 8, true); setArg(call_get_pow_1297, 0, reinterpret_cast(this)); setArg(call_get_pow_1297, 1, EEW); setRet(call_get_pow_1297, 0, ret_val_get_pow_1297); @@ -38613,7 +38669,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1306 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1306, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1304, ret_val_get_sew_pow_1305), ret_val_get_lmul_pow_1306)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1304, ret_val_get_sew_pow_1305), ret_val_get_lmul_pow_1306)), 8, true); setArg(call_get_pow_1304, 0, reinterpret_cast(this)); setArg(call_get_pow_1304, 1, EEW); setRet(call_get_pow_1304, 0, ret_val_get_pow_1304); @@ -38750,7 +38806,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1313 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1313, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1311, ret_val_get_sew_pow_1312), ret_val_get_lmul_pow_1313)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1311, ret_val_get_sew_pow_1312), ret_val_get_lmul_pow_1313)), 8, true); setArg(call_get_pow_1311, 0, reinterpret_cast(this)); setArg(call_get_pow_1311, 1, EEW); setRet(call_get_pow_1311, 0, ret_val_get_pow_1311); @@ -38887,7 +38943,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1320 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1320, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1318, ret_val_get_sew_pow_1319), ret_val_get_lmul_pow_1320)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1318, ret_val_get_sew_pow_1319), ret_val_get_lmul_pow_1320)), 8, true); setArg(call_get_pow_1318, 0, reinterpret_cast(this)); setArg(call_get_pow_1318, 1, EEW); setRet(call_get_pow_1318, 0, ret_val_get_pow_1318); @@ -39024,7 +39080,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1327 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1327, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1325, ret_val_get_sew_pow_1326), ret_val_get_lmul_pow_1327)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1325, ret_val_get_sew_pow_1326), ret_val_get_lmul_pow_1327)), 8, true); setArg(call_get_pow_1325, 0, reinterpret_cast(this)); setArg(call_get_pow_1325, 1, EEW); setRet(call_get_pow_1325, 0, ret_val_get_pow_1325); @@ -39161,7 +39217,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1334 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1334, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1332, ret_val_get_sew_pow_1333), ret_val_get_lmul_pow_1334)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1332, ret_val_get_sew_pow_1333), ret_val_get_lmul_pow_1334)), 8, true); setArg(call_get_pow_1332, 0, reinterpret_cast(this)); setArg(call_get_pow_1332, 1, EEW); setRet(call_get_pow_1332, 0, ret_val_get_pow_1332); @@ -39298,7 +39354,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1341 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1341, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1339, ret_val_get_sew_pow_1340), ret_val_get_lmul_pow_1341)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1339, ret_val_get_sew_pow_1340), ret_val_get_lmul_pow_1341)), 8, true); setArg(call_get_pow_1339, 0, reinterpret_cast(this)); setArg(call_get_pow_1339, 1, EEW); setRet(call_get_pow_1339, 0, ret_val_get_pow_1339); @@ -39435,7 +39491,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1348 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1348, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1346, ret_val_get_sew_pow_1347), ret_val_get_lmul_pow_1348)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1346, ret_val_get_sew_pow_1347), ret_val_get_lmul_pow_1348)), 8, true); setArg(call_get_pow_1346, 0, reinterpret_cast(this)); setArg(call_get_pow_1346, 1, EEW); setRet(call_get_pow_1346, 0, ret_val_get_pow_1346); @@ -39572,7 +39628,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1355 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1355, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1353, ret_val_get_sew_pow_1354), ret_val_get_lmul_pow_1355)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1353, ret_val_get_sew_pow_1354), ret_val_get_lmul_pow_1355)), 8, true); setArg(call_get_pow_1353, 0, reinterpret_cast(this)); setArg(call_get_pow_1353, 1, EEW); setRet(call_get_pow_1353, 0, ret_val_get_pow_1353); @@ -39709,7 +39765,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1362 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1362, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1360, ret_val_get_sew_pow_1361), ret_val_get_lmul_pow_1362)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1360, ret_val_get_sew_pow_1361), ret_val_get_lmul_pow_1362)), 8, true); setArg(call_get_pow_1360, 0, reinterpret_cast(this)); setArg(call_get_pow_1360, 1, EEW); setRet(call_get_pow_1360, 0, ret_val_get_pow_1360); @@ -39846,7 +39902,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1369 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1369, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1367, ret_val_get_sew_pow_1368), ret_val_get_lmul_pow_1369)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1367, ret_val_get_sew_pow_1368), ret_val_get_lmul_pow_1369)), 8, true); setArg(call_get_pow_1367, 0, reinterpret_cast(this)); setArg(call_get_pow_1367, 1, EEW); setRet(call_get_pow_1367, 0, ret_val_get_pow_1367); @@ -39983,7 +40039,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1376 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1376, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1374, ret_val_get_sew_pow_1375), ret_val_get_lmul_pow_1376)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1374, ret_val_get_sew_pow_1375), ret_val_get_lmul_pow_1376)), 8, true); setArg(call_get_pow_1374, 0, reinterpret_cast(this)); setArg(call_get_pow_1374, 1, EEW); setRet(call_get_pow_1374, 0, ret_val_get_pow_1374); @@ -40120,7 +40176,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1383 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1383, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1381, ret_val_get_sew_pow_1382), ret_val_get_lmul_pow_1383)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1381, ret_val_get_sew_pow_1382), ret_val_get_lmul_pow_1383)), 8, true); setArg(call_get_pow_1381, 0, reinterpret_cast(this)); setArg(call_get_pow_1381, 1, EEW); setRet(call_get_pow_1381, 0, ret_val_get_pow_1381); @@ -40255,7 +40311,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1390 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1390, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1388, ret_val_get_sew_pow_1389), ret_val_get_lmul_pow_1390)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1388, ret_val_get_sew_pow_1389), ret_val_get_lmul_pow_1390)), 8, true); setArg(call_get_pow_1388, 0, reinterpret_cast(this)); setArg(call_get_pow_1388, 1, EEW); setRet(call_get_pow_1388, 0, ret_val_get_pow_1388); @@ -40390,7 +40446,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1397 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1397, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1395, ret_val_get_sew_pow_1396), ret_val_get_lmul_pow_1397)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1395, ret_val_get_sew_pow_1396), ret_val_get_lmul_pow_1397)), 8, true); setArg(call_get_pow_1395, 0, reinterpret_cast(this)); setArg(call_get_pow_1395, 1, EEW); setRet(call_get_pow_1395, 0, ret_val_get_pow_1395); @@ -40525,7 +40581,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1404 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1404, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1402, ret_val_get_sew_pow_1403), ret_val_get_lmul_pow_1404)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1402, ret_val_get_sew_pow_1403), ret_val_get_lmul_pow_1404)), 8, true); setArg(call_get_pow_1402, 0, reinterpret_cast(this)); setArg(call_get_pow_1402, 1, EEW); setRet(call_get_pow_1402, 0, ret_val_get_pow_1402); @@ -40660,7 +40716,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1411 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1411, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1409, ret_val_get_sew_pow_1410), ret_val_get_lmul_pow_1411)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1409, ret_val_get_sew_pow_1410), ret_val_get_lmul_pow_1411)), 8, true); setArg(call_get_pow_1409, 0, reinterpret_cast(this)); setArg(call_get_pow_1409, 1, EEW); setRet(call_get_pow_1409, 0, ret_val_get_pow_1409); @@ -40795,7 +40851,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1418 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1418, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1416, ret_val_get_sew_pow_1417), ret_val_get_lmul_pow_1418)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1416, ret_val_get_sew_pow_1417), ret_val_get_lmul_pow_1418)), 8, true); setArg(call_get_pow_1416, 0, reinterpret_cast(this)); setArg(call_get_pow_1416, 1, EEW); setRet(call_get_pow_1416, 0, ret_val_get_pow_1416); @@ -40930,7 +40986,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1425 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1425, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1423, ret_val_get_sew_pow_1424), ret_val_get_lmul_pow_1425)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1423, ret_val_get_sew_pow_1424), ret_val_get_lmul_pow_1425)), 8, true); setArg(call_get_pow_1423, 0, reinterpret_cast(this)); setArg(call_get_pow_1423, 1, EEW); setRet(call_get_pow_1423, 0, ret_val_get_pow_1423); @@ -41065,7 +41121,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1432 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1432, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1430, ret_val_get_sew_pow_1431), ret_val_get_lmul_pow_1432)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1430, ret_val_get_sew_pow_1431), ret_val_get_lmul_pow_1432)), 8, true); setArg(call_get_pow_1430, 0, reinterpret_cast(this)); setArg(call_get_pow_1430, 1, EEW); setRet(call_get_pow_1430, 0, ret_val_get_pow_1430); @@ -41200,7 +41256,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1439 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1439, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1437, ret_val_get_sew_pow_1438), ret_val_get_lmul_pow_1439)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1437, ret_val_get_sew_pow_1438), ret_val_get_lmul_pow_1439)), 8, true); setArg(call_get_pow_1437, 0, reinterpret_cast(this)); setArg(call_get_pow_1437, 1, EEW); setRet(call_get_pow_1437, 0, ret_val_get_pow_1437); @@ -41335,7 +41391,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1446 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1446, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1444, ret_val_get_sew_pow_1445), ret_val_get_lmul_pow_1446)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1444, ret_val_get_sew_pow_1445), ret_val_get_lmul_pow_1446)), 8, true); setArg(call_get_pow_1444, 0, reinterpret_cast(this)); setArg(call_get_pow_1444, 1, EEW); setRet(call_get_pow_1444, 0, ret_val_get_pow_1444); @@ -41470,7 +41526,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1453 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1453, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1451, ret_val_get_sew_pow_1452), ret_val_get_lmul_pow_1453)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1451, ret_val_get_sew_pow_1452), ret_val_get_lmul_pow_1453)), 8, true); setArg(call_get_pow_1451, 0, reinterpret_cast(this)); setArg(call_get_pow_1451, 1, EEW); setRet(call_get_pow_1451, 0, ret_val_get_pow_1451); @@ -41605,7 +41661,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1460 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1460, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1458, ret_val_get_sew_pow_1459), ret_val_get_lmul_pow_1460)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1458, ret_val_get_sew_pow_1459), ret_val_get_lmul_pow_1460)), 8, true); setArg(call_get_pow_1458, 0, reinterpret_cast(this)); setArg(call_get_pow_1458, 1, EEW); setRet(call_get_pow_1458, 0, ret_val_get_pow_1458); @@ -41740,7 +41796,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1467 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1467, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1465, ret_val_get_sew_pow_1466), ret_val_get_lmul_pow_1467)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1465, ret_val_get_sew_pow_1466), ret_val_get_lmul_pow_1467)), 8, true); setArg(call_get_pow_1465, 0, reinterpret_cast(this)); setArg(call_get_pow_1465, 1, EEW); setRet(call_get_pow_1465, 0, ret_val_get_pow_1465); @@ -41875,7 +41931,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1474 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1474, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1472, ret_val_get_sew_pow_1473), ret_val_get_lmul_pow_1474)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1472, ret_val_get_sew_pow_1473), ret_val_get_lmul_pow_1474)), 8, true); setArg(call_get_pow_1472, 0, reinterpret_cast(this)); setArg(call_get_pow_1472, 1, EEW); setRet(call_get_pow_1472, 0, ret_val_get_pow_1472); @@ -42010,7 +42066,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1481 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1481, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1479, ret_val_get_sew_pow_1480), ret_val_get_lmul_pow_1481)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1479, ret_val_get_sew_pow_1480), ret_val_get_lmul_pow_1481)), 8, true); setArg(call_get_pow_1479, 0, reinterpret_cast(this)); setArg(call_get_pow_1479, 1, EEW); setRet(call_get_pow_1479, 0, ret_val_get_pow_1479); @@ -42145,7 +42201,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1488 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1488, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1486, ret_val_get_sew_pow_1487), ret_val_get_lmul_pow_1488)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1486, ret_val_get_sew_pow_1487), ret_val_get_lmul_pow_1488)), 8, true); setArg(call_get_pow_1486, 0, reinterpret_cast(this)); setArg(call_get_pow_1486, 1, EEW); setRet(call_get_pow_1486, 0, ret_val_get_pow_1486); @@ -42280,7 +42336,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1495 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1495, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1493, ret_val_get_sew_pow_1494), ret_val_get_lmul_pow_1495)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1493, ret_val_get_sew_pow_1494), ret_val_get_lmul_pow_1495)), 8, true); setArg(call_get_pow_1493, 0, reinterpret_cast(this)); setArg(call_get_pow_1493, 1, EEW); setRet(call_get_pow_1493, 0, ret_val_get_pow_1493); @@ -42415,7 +42471,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1502 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1502, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1500, ret_val_get_sew_pow_1501), ret_val_get_lmul_pow_1502)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1500, ret_val_get_sew_pow_1501), ret_val_get_lmul_pow_1502)), 8, true); setArg(call_get_pow_1500, 0, reinterpret_cast(this)); setArg(call_get_pow_1500, 1, EEW); setRet(call_get_pow_1500, 0, ret_val_get_pow_1500); @@ -42550,7 +42606,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1509 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1509, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1507, ret_val_get_sew_pow_1508), ret_val_get_lmul_pow_1509)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1507, ret_val_get_sew_pow_1508), ret_val_get_lmul_pow_1509)), 8, true); setArg(call_get_pow_1507, 0, reinterpret_cast(this)); setArg(call_get_pow_1507, 1, EEW); setRet(call_get_pow_1507, 0, ret_val_get_pow_1507); @@ -42685,7 +42741,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1516 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1516, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1514, ret_val_get_sew_pow_1515), ret_val_get_lmul_pow_1516)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1514, ret_val_get_sew_pow_1515), ret_val_get_lmul_pow_1516)), 8, true); setArg(call_get_pow_1514, 0, reinterpret_cast(this)); setArg(call_get_pow_1514, 1, EEW); setRet(call_get_pow_1514, 0, ret_val_get_pow_1514); @@ -42820,7 +42876,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1523 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1523, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1521, ret_val_get_sew_pow_1522), ret_val_get_lmul_pow_1523)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1521, ret_val_get_sew_pow_1522), ret_val_get_lmul_pow_1523)), 8, true); setArg(call_get_pow_1521, 0, reinterpret_cast(this)); setArg(call_get_pow_1521, 1, EEW); setRet(call_get_pow_1521, 0, ret_val_get_pow_1521); @@ -42955,7 +43011,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1530 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1530, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1528, ret_val_get_sew_pow_1529), ret_val_get_lmul_pow_1530)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1528, ret_val_get_sew_pow_1529), ret_val_get_lmul_pow_1530)), 8, true); setArg(call_get_pow_1528, 0, reinterpret_cast(this)); setArg(call_get_pow_1528, 1, EEW); setRet(call_get_pow_1528, 0, ret_val_get_pow_1528); @@ -43090,7 +43146,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1537 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1537, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1535, ret_val_get_sew_pow_1536), ret_val_get_lmul_pow_1537)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1535, ret_val_get_sew_pow_1536), ret_val_get_lmul_pow_1537)), 8, true); setArg(call_get_pow_1535, 0, reinterpret_cast(this)); setArg(call_get_pow_1535, 1, EEW); setRet(call_get_pow_1535, 0, ret_val_get_pow_1535); @@ -43225,7 +43281,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1544 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1544, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1542, ret_val_get_sew_pow_1543), ret_val_get_lmul_pow_1544)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1542, ret_val_get_sew_pow_1543), ret_val_get_lmul_pow_1544)), 8, true); setArg(call_get_pow_1542, 0, reinterpret_cast(this)); setArg(call_get_pow_1542, 1, EEW); setRet(call_get_pow_1542, 0, ret_val_get_pow_1542); @@ -43360,7 +43416,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1551 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1551, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1549, ret_val_get_sew_pow_1550), ret_val_get_lmul_pow_1551)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1549, ret_val_get_sew_pow_1550), ret_val_get_lmul_pow_1551)), 8, true); setArg(call_get_pow_1549, 0, reinterpret_cast(this)); setArg(call_get_pow_1549, 1, EEW); setRet(call_get_pow_1549, 0, ret_val_get_pow_1549); @@ -43495,7 +43551,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1558 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1558, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1556, ret_val_get_sew_pow_1557), ret_val_get_lmul_pow_1558)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1556, ret_val_get_sew_pow_1557), ret_val_get_lmul_pow_1558)), 8, true); setArg(call_get_pow_1556, 0, reinterpret_cast(this)); setArg(call_get_pow_1556, 1, EEW); setRet(call_get_pow_1556, 0, ret_val_get_pow_1556); @@ -43630,7 +43686,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1565 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1565, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1563, ret_val_get_sew_pow_1564), ret_val_get_lmul_pow_1565)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1563, ret_val_get_sew_pow_1564), ret_val_get_lmul_pow_1565)), 8, true); setArg(call_get_pow_1563, 0, reinterpret_cast(this)); setArg(call_get_pow_1563, 1, EEW); setRet(call_get_pow_1563, 0, ret_val_get_pow_1563); @@ -43765,7 +43821,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1572 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1572, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1570, ret_val_get_sew_pow_1571), ret_val_get_lmul_pow_1572)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1570, ret_val_get_sew_pow_1571), ret_val_get_lmul_pow_1572)), 8, true); setArg(call_get_pow_1570, 0, reinterpret_cast(this)); setArg(call_get_pow_1570, 1, EEW); setRet(call_get_pow_1570, 0, ret_val_get_pow_1570); @@ -43900,7 +43956,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1579 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1579, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1577, ret_val_get_sew_pow_1578), ret_val_get_lmul_pow_1579)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1577, ret_val_get_sew_pow_1578), ret_val_get_lmul_pow_1579)), 8, true); setArg(call_get_pow_1577, 0, reinterpret_cast(this)); setArg(call_get_pow_1577, 1, EEW); setRet(call_get_pow_1577, 0, ret_val_get_pow_1577); @@ -44035,7 +44091,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1586 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1586, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1584, ret_val_get_sew_pow_1585), ret_val_get_lmul_pow_1586)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1584, ret_val_get_sew_pow_1585), ret_val_get_lmul_pow_1586)), 8, true); setArg(call_get_pow_1584, 0, reinterpret_cast(this)); setArg(call_get_pow_1584, 1, EEW); setRet(call_get_pow_1584, 0, ret_val_get_pow_1584); @@ -44170,7 +44226,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1593 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1593, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1591, ret_val_get_sew_pow_1592), ret_val_get_lmul_pow_1593)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1591, ret_val_get_sew_pow_1592), ret_val_get_lmul_pow_1593)), 8, true); setArg(call_get_pow_1591, 0, reinterpret_cast(this)); setArg(call_get_pow_1591, 1, EEW); setRet(call_get_pow_1591, 0, ret_val_get_pow_1591); @@ -44305,7 +44361,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1600 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1600, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1598, ret_val_get_sew_pow_1599), ret_val_get_lmul_pow_1600)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1598, ret_val_get_sew_pow_1599), ret_val_get_lmul_pow_1600)), 8, true); setArg(call_get_pow_1598, 0, reinterpret_cast(this)); setArg(call_get_pow_1598, 1, EEW); setRet(call_get_pow_1598, 0, ret_val_get_pow_1598); @@ -44440,7 +44496,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1607 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1607, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1605, ret_val_get_sew_pow_1606), ret_val_get_lmul_pow_1607)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1605, ret_val_get_sew_pow_1606), ret_val_get_lmul_pow_1607)), 8, true); setArg(call_get_pow_1605, 0, reinterpret_cast(this)); setArg(call_get_pow_1605, 1, EEW); setRet(call_get_pow_1605, 0, ret_val_get_pow_1605); @@ -44577,7 +44633,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1614 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1614, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1612, ret_val_get_sew_pow_1613), ret_val_get_lmul_pow_1614)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1612, ret_val_get_sew_pow_1613), ret_val_get_lmul_pow_1614)), 8, true); setArg(call_get_pow_1612, 0, reinterpret_cast(this)); setArg(call_get_pow_1612, 1, EEW); setRet(call_get_pow_1612, 0, ret_val_get_pow_1612); @@ -44714,7 +44770,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1621 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1621, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1619, ret_val_get_sew_pow_1620), ret_val_get_lmul_pow_1621)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1619, ret_val_get_sew_pow_1620), ret_val_get_lmul_pow_1621)), 8, true); setArg(call_get_pow_1619, 0, reinterpret_cast(this)); setArg(call_get_pow_1619, 1, EEW); setRet(call_get_pow_1619, 0, ret_val_get_pow_1619); @@ -44851,7 +44907,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1628 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1628, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1626, ret_val_get_sew_pow_1627), ret_val_get_lmul_pow_1628)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1626, ret_val_get_sew_pow_1627), ret_val_get_lmul_pow_1628)), 8, true); setArg(call_get_pow_1626, 0, reinterpret_cast(this)); setArg(call_get_pow_1626, 1, EEW); setRet(call_get_pow_1626, 0, ret_val_get_pow_1626); @@ -44988,7 +45044,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1635 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1635, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1633, ret_val_get_sew_pow_1634), ret_val_get_lmul_pow_1635)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1633, ret_val_get_sew_pow_1634), ret_val_get_lmul_pow_1635)), 8, true); setArg(call_get_pow_1633, 0, reinterpret_cast(this)); setArg(call_get_pow_1633, 1, EEW); setRet(call_get_pow_1633, 0, ret_val_get_pow_1633); @@ -45125,7 +45181,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1642 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1642, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1640, ret_val_get_sew_pow_1641), ret_val_get_lmul_pow_1642)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1640, ret_val_get_sew_pow_1641), ret_val_get_lmul_pow_1642)), 8, true); setArg(call_get_pow_1640, 0, reinterpret_cast(this)); setArg(call_get_pow_1640, 1, EEW); setRet(call_get_pow_1640, 0, ret_val_get_pow_1640); @@ -45262,7 +45318,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1649 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1649, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1647, ret_val_get_sew_pow_1648), ret_val_get_lmul_pow_1649)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1647, ret_val_get_sew_pow_1648), ret_val_get_lmul_pow_1649)), 8, true); setArg(call_get_pow_1647, 0, reinterpret_cast(this)); setArg(call_get_pow_1647, 1, EEW); setRet(call_get_pow_1647, 0, ret_val_get_pow_1647); @@ -45399,7 +45455,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1656 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1656, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1654, ret_val_get_sew_pow_1655), ret_val_get_lmul_pow_1656)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1654, ret_val_get_sew_pow_1655), ret_val_get_lmul_pow_1656)), 8, true); setArg(call_get_pow_1654, 0, reinterpret_cast(this)); setArg(call_get_pow_1654, 1, EEW); setRet(call_get_pow_1654, 0, ret_val_get_pow_1654); @@ -45536,7 +45592,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1663 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1663, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1661, ret_val_get_sew_pow_1662), ret_val_get_lmul_pow_1663)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1661, ret_val_get_sew_pow_1662), ret_val_get_lmul_pow_1663)), 8, true); setArg(call_get_pow_1661, 0, reinterpret_cast(this)); setArg(call_get_pow_1661, 1, EEW); setRet(call_get_pow_1661, 0, ret_val_get_pow_1661); @@ -45673,7 +45729,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1670 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1670, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1668, ret_val_get_sew_pow_1669), ret_val_get_lmul_pow_1670)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1668, ret_val_get_sew_pow_1669), ret_val_get_lmul_pow_1670)), 8, true); setArg(call_get_pow_1668, 0, reinterpret_cast(this)); setArg(call_get_pow_1668, 1, EEW); setRet(call_get_pow_1668, 0, ret_val_get_pow_1668); @@ -45810,7 +45866,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1677 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1677, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1675, ret_val_get_sew_pow_1676), ret_val_get_lmul_pow_1677)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1675, ret_val_get_sew_pow_1676), ret_val_get_lmul_pow_1677)), 8, true); setArg(call_get_pow_1675, 0, reinterpret_cast(this)); setArg(call_get_pow_1675, 1, EEW); setRet(call_get_pow_1675, 0, ret_val_get_pow_1675); @@ -45947,7 +46003,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1684 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1684, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1682, ret_val_get_sew_pow_1683), ret_val_get_lmul_pow_1684)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1682, ret_val_get_sew_pow_1683), ret_val_get_lmul_pow_1684)), 8, true); setArg(call_get_pow_1682, 0, reinterpret_cast(this)); setArg(call_get_pow_1682, 1, EEW); setRet(call_get_pow_1682, 0, ret_val_get_pow_1682); @@ -46084,7 +46140,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1691 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1691, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1689, ret_val_get_sew_pow_1690), ret_val_get_lmul_pow_1691)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1689, ret_val_get_sew_pow_1690), ret_val_get_lmul_pow_1691)), 8, true); setArg(call_get_pow_1689, 0, reinterpret_cast(this)); setArg(call_get_pow_1689, 1, EEW); setRet(call_get_pow_1689, 0, ret_val_get_pow_1689); @@ -46221,7 +46277,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1698 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1698, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1696, ret_val_get_sew_pow_1697), ret_val_get_lmul_pow_1698)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1696, ret_val_get_sew_pow_1697), ret_val_get_lmul_pow_1698)), 8, true); setArg(call_get_pow_1696, 0, reinterpret_cast(this)); setArg(call_get_pow_1696, 1, EEW); setRet(call_get_pow_1696, 0, ret_val_get_pow_1696); @@ -46358,7 +46414,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1705 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1705, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1703, ret_val_get_sew_pow_1704), ret_val_get_lmul_pow_1705)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1703, ret_val_get_sew_pow_1704), ret_val_get_lmul_pow_1705)), 8, true); setArg(call_get_pow_1703, 0, reinterpret_cast(this)); setArg(call_get_pow_1703, 1, EEW); setRet(call_get_pow_1703, 0, ret_val_get_pow_1703); @@ -46495,7 +46551,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1712 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1712, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1710, ret_val_get_sew_pow_1711), ret_val_get_lmul_pow_1712)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1710, ret_val_get_sew_pow_1711), ret_val_get_lmul_pow_1712)), 8, true); setArg(call_get_pow_1710, 0, reinterpret_cast(this)); setArg(call_get_pow_1710, 1, EEW); setRet(call_get_pow_1710, 0, ret_val_get_pow_1710); @@ -46632,7 +46688,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1719 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1719, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1717, ret_val_get_sew_pow_1718), ret_val_get_lmul_pow_1719)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1717, ret_val_get_sew_pow_1718), ret_val_get_lmul_pow_1719)), 8, true); setArg(call_get_pow_1717, 0, reinterpret_cast(this)); setArg(call_get_pow_1717, 1, EEW); setRet(call_get_pow_1717, 0, ret_val_get_pow_1717); @@ -46769,7 +46825,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1726 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1726, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1724, ret_val_get_sew_pow_1725), ret_val_get_lmul_pow_1726)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1724, ret_val_get_sew_pow_1725), ret_val_get_lmul_pow_1726)), 8, true); setArg(call_get_pow_1724, 0, reinterpret_cast(this)); setArg(call_get_pow_1724, 1, EEW); setRet(call_get_pow_1724, 0, ret_val_get_pow_1724); @@ -46906,7 +46962,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1733 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1733, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1731, ret_val_get_sew_pow_1732), ret_val_get_lmul_pow_1733)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1731, ret_val_get_sew_pow_1732), ret_val_get_lmul_pow_1733)), 8, true); setArg(call_get_pow_1731, 0, reinterpret_cast(this)); setArg(call_get_pow_1731, 1, EEW); setRet(call_get_pow_1731, 0, ret_val_get_pow_1731); @@ -47043,7 +47099,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1740 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1740, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1738, ret_val_get_sew_pow_1739), ret_val_get_lmul_pow_1740)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1738, ret_val_get_sew_pow_1739), ret_val_get_lmul_pow_1740)), 8, true); setArg(call_get_pow_1738, 0, reinterpret_cast(this)); setArg(call_get_pow_1738, 1, EEW); setRet(call_get_pow_1738, 0, ret_val_get_pow_1738); @@ -47180,7 +47236,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1747 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1747, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1745, ret_val_get_sew_pow_1746), ret_val_get_lmul_pow_1747)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1745, ret_val_get_sew_pow_1746), ret_val_get_lmul_pow_1747)), 8, true); setArg(call_get_pow_1745, 0, reinterpret_cast(this)); setArg(call_get_pow_1745, 1, EEW); setRet(call_get_pow_1745, 0, ret_val_get_pow_1745); @@ -47317,7 +47373,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1754 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1754, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1752, ret_val_get_sew_pow_1753), ret_val_get_lmul_pow_1754)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1752, ret_val_get_sew_pow_1753), ret_val_get_lmul_pow_1754)), 8, true); setArg(call_get_pow_1752, 0, reinterpret_cast(this)); setArg(call_get_pow_1752, 1, EEW); setRet(call_get_pow_1752, 0, ret_val_get_pow_1752); @@ -47454,7 +47510,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1761 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1761, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1759, ret_val_get_sew_pow_1760), ret_val_get_lmul_pow_1761)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1759, ret_val_get_sew_pow_1760), ret_val_get_lmul_pow_1761)), 8, true); setArg(call_get_pow_1759, 0, reinterpret_cast(this)); setArg(call_get_pow_1759, 1, EEW); setRet(call_get_pow_1759, 0, ret_val_get_pow_1759); @@ -47591,7 +47647,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1768 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1768, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1766, ret_val_get_sew_pow_1767), ret_val_get_lmul_pow_1768)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1766, ret_val_get_sew_pow_1767), ret_val_get_lmul_pow_1768)), 8, true); setArg(call_get_pow_1766, 0, reinterpret_cast(this)); setArg(call_get_pow_1766, 1, EEW); setRet(call_get_pow_1766, 0, ret_val_get_pow_1766); @@ -47728,7 +47784,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1775 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1775, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1773, ret_val_get_sew_pow_1774), ret_val_get_lmul_pow_1775)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1773, ret_val_get_sew_pow_1774), ret_val_get_lmul_pow_1775)), 8, true); setArg(call_get_pow_1773, 0, reinterpret_cast(this)); setArg(call_get_pow_1773, 1, EEW); setRet(call_get_pow_1773, 0, ret_val_get_pow_1773); @@ -47865,7 +47921,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1782 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1782, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1780, ret_val_get_sew_pow_1781), ret_val_get_lmul_pow_1782)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1780, ret_val_get_sew_pow_1781), ret_val_get_lmul_pow_1782)), 8, true); setArg(call_get_pow_1780, 0, reinterpret_cast(this)); setArg(call_get_pow_1780, 1, EEW); setRet(call_get_pow_1780, 0, ret_val_get_pow_1780); @@ -48002,7 +48058,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1789 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1789, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1787, ret_val_get_sew_pow_1788), ret_val_get_lmul_pow_1789)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1787, ret_val_get_sew_pow_1788), ret_val_get_lmul_pow_1789)), 8, true); setArg(call_get_pow_1787, 0, reinterpret_cast(this)); setArg(call_get_pow_1787, 1, EEW); setRet(call_get_pow_1787, 0, ret_val_get_pow_1787); @@ -48139,7 +48195,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1796 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1796, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1794, ret_val_get_sew_pow_1795), ret_val_get_lmul_pow_1796)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1794, ret_val_get_sew_pow_1795), ret_val_get_lmul_pow_1796)), 8, true); setArg(call_get_pow_1794, 0, reinterpret_cast(this)); setArg(call_get_pow_1794, 1, EEW); setRet(call_get_pow_1794, 0, ret_val_get_pow_1794); @@ -48276,7 +48332,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1803 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1803, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1801, ret_val_get_sew_pow_1802), ret_val_get_lmul_pow_1803)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1801, ret_val_get_sew_pow_1802), ret_val_get_lmul_pow_1803)), 8, true); setArg(call_get_pow_1801, 0, reinterpret_cast(this)); setArg(call_get_pow_1801, 1, EEW); setRet(call_get_pow_1801, 0, ret_val_get_pow_1801); @@ -48413,7 +48469,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1810 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1810, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1808, ret_val_get_sew_pow_1809), ret_val_get_lmul_pow_1810)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1808, ret_val_get_sew_pow_1809), ret_val_get_lmul_pow_1810)), 8, true); setArg(call_get_pow_1808, 0, reinterpret_cast(this)); setArg(call_get_pow_1808, 1, EEW); setRet(call_get_pow_1808, 0, ret_val_get_pow_1808); @@ -48550,7 +48606,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1817 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1817, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1815, ret_val_get_sew_pow_1816), ret_val_get_lmul_pow_1817)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1815, ret_val_get_sew_pow_1816), ret_val_get_lmul_pow_1817)), 8, true); setArg(call_get_pow_1815, 0, reinterpret_cast(this)); setArg(call_get_pow_1815, 1, EEW); setRet(call_get_pow_1815, 0, ret_val_get_pow_1815); @@ -48687,7 +48743,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1824 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1824, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1822, ret_val_get_sew_pow_1823), ret_val_get_lmul_pow_1824)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1822, ret_val_get_sew_pow_1823), ret_val_get_lmul_pow_1824)), 8, true); setArg(call_get_pow_1822, 0, reinterpret_cast(this)); setArg(call_get_pow_1822, 1, EEW); setRet(call_get_pow_1822, 0, ret_val_get_pow_1822); @@ -48824,7 +48880,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1831 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1831, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1829, ret_val_get_sew_pow_1830), ret_val_get_lmul_pow_1831)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1829, ret_val_get_sew_pow_1830), ret_val_get_lmul_pow_1831)), 8, true); setArg(call_get_pow_1829, 0, reinterpret_cast(this)); setArg(call_get_pow_1829, 1, EEW); setRet(call_get_pow_1829, 0, ret_val_get_pow_1829); @@ -48959,7 +49015,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1838 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1838, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1836, ret_val_get_sew_pow_1837), ret_val_get_lmul_pow_1838)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1836, ret_val_get_sew_pow_1837), ret_val_get_lmul_pow_1838)), 8, true); setArg(call_get_pow_1836, 0, reinterpret_cast(this)); setArg(call_get_pow_1836, 1, EEW); setRet(call_get_pow_1836, 0, ret_val_get_pow_1836); @@ -49094,7 +49150,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1845 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1845, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1843, ret_val_get_sew_pow_1844), ret_val_get_lmul_pow_1845)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1843, ret_val_get_sew_pow_1844), ret_val_get_lmul_pow_1845)), 8, true); setArg(call_get_pow_1843, 0, reinterpret_cast(this)); setArg(call_get_pow_1843, 1, EEW); setRet(call_get_pow_1843, 0, ret_val_get_pow_1843); @@ -49229,7 +49285,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1852 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1852, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1850, ret_val_get_sew_pow_1851), ret_val_get_lmul_pow_1852)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1850, ret_val_get_sew_pow_1851), ret_val_get_lmul_pow_1852)), 8, true); setArg(call_get_pow_1850, 0, reinterpret_cast(this)); setArg(call_get_pow_1850, 1, EEW); setRet(call_get_pow_1850, 0, ret_val_get_pow_1850); @@ -49364,7 +49420,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1859 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1859, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1857, ret_val_get_sew_pow_1858), ret_val_get_lmul_pow_1859)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1857, ret_val_get_sew_pow_1858), ret_val_get_lmul_pow_1859)), 8, true); setArg(call_get_pow_1857, 0, reinterpret_cast(this)); setArg(call_get_pow_1857, 1, EEW); setRet(call_get_pow_1857, 0, ret_val_get_pow_1857); @@ -49499,7 +49555,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1866 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1866, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1864, ret_val_get_sew_pow_1865), ret_val_get_lmul_pow_1866)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1864, ret_val_get_sew_pow_1865), ret_val_get_lmul_pow_1866)), 8, true); setArg(call_get_pow_1864, 0, reinterpret_cast(this)); setArg(call_get_pow_1864, 1, EEW); setRet(call_get_pow_1864, 0, ret_val_get_pow_1864); @@ -49634,7 +49690,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1873 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1873, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1871, ret_val_get_sew_pow_1872), ret_val_get_lmul_pow_1873)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1871, ret_val_get_sew_pow_1872), ret_val_get_lmul_pow_1873)), 8, true); setArg(call_get_pow_1871, 0, reinterpret_cast(this)); setArg(call_get_pow_1871, 1, EEW); setRet(call_get_pow_1871, 0, ret_val_get_pow_1871); @@ -49769,7 +49825,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1880 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1880, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1878, ret_val_get_sew_pow_1879), ret_val_get_lmul_pow_1880)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1878, ret_val_get_sew_pow_1879), ret_val_get_lmul_pow_1880)), 8, true); setArg(call_get_pow_1878, 0, reinterpret_cast(this)); setArg(call_get_pow_1878, 1, EEW); setRet(call_get_pow_1878, 0, ret_val_get_pow_1878); @@ -49904,7 +49960,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1887 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1887, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1885, ret_val_get_sew_pow_1886), ret_val_get_lmul_pow_1887)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1885, ret_val_get_sew_pow_1886), ret_val_get_lmul_pow_1887)), 8, true); setArg(call_get_pow_1885, 0, reinterpret_cast(this)); setArg(call_get_pow_1885, 1, EEW); setRet(call_get_pow_1885, 0, ret_val_get_pow_1885); @@ -50039,7 +50095,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1894 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1894, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1892, ret_val_get_sew_pow_1893), ret_val_get_lmul_pow_1894)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1892, ret_val_get_sew_pow_1893), ret_val_get_lmul_pow_1894)), 8, true); setArg(call_get_pow_1892, 0, reinterpret_cast(this)); setArg(call_get_pow_1892, 1, EEW); setRet(call_get_pow_1892, 0, ret_val_get_pow_1892); @@ -50174,7 +50230,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1901 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1901, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1899, ret_val_get_sew_pow_1900), ret_val_get_lmul_pow_1901)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1899, ret_val_get_sew_pow_1900), ret_val_get_lmul_pow_1901)), 8, true); setArg(call_get_pow_1899, 0, reinterpret_cast(this)); setArg(call_get_pow_1899, 1, EEW); setRet(call_get_pow_1899, 0, ret_val_get_pow_1899); @@ -50309,7 +50365,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1908 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1908, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1906, ret_val_get_sew_pow_1907), ret_val_get_lmul_pow_1908)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1906, ret_val_get_sew_pow_1907), ret_val_get_lmul_pow_1908)), 8, true); setArg(call_get_pow_1906, 0, reinterpret_cast(this)); setArg(call_get_pow_1906, 1, EEW); setRet(call_get_pow_1906, 0, ret_val_get_pow_1906); @@ -50444,7 +50500,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1915 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1915, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1913, ret_val_get_sew_pow_1914), ret_val_get_lmul_pow_1915)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1913, ret_val_get_sew_pow_1914), ret_val_get_lmul_pow_1915)), 8, true); setArg(call_get_pow_1913, 0, reinterpret_cast(this)); setArg(call_get_pow_1913, 1, EEW); setRet(call_get_pow_1913, 0, ret_val_get_pow_1913); @@ -50579,7 +50635,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1922 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1922, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1920, ret_val_get_sew_pow_1921), ret_val_get_lmul_pow_1922)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1920, ret_val_get_sew_pow_1921), ret_val_get_lmul_pow_1922)), 8, true); setArg(call_get_pow_1920, 0, reinterpret_cast(this)); setArg(call_get_pow_1920, 1, EEW); setRet(call_get_pow_1920, 0, ret_val_get_pow_1920); @@ -50714,7 +50770,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1929 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1929, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1927, ret_val_get_sew_pow_1928), ret_val_get_lmul_pow_1929)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1927, ret_val_get_sew_pow_1928), ret_val_get_lmul_pow_1929)), 8, true); setArg(call_get_pow_1927, 0, reinterpret_cast(this)); setArg(call_get_pow_1927, 1, EEW); setRet(call_get_pow_1927, 0, ret_val_get_pow_1927); @@ -50849,7 +50905,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1936 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1936, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1934, ret_val_get_sew_pow_1935), ret_val_get_lmul_pow_1936)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1934, ret_val_get_sew_pow_1935), ret_val_get_lmul_pow_1936)), 8, true); setArg(call_get_pow_1934, 0, reinterpret_cast(this)); setArg(call_get_pow_1934, 1, EEW); setRet(call_get_pow_1934, 0, ret_val_get_pow_1934); @@ -50984,7 +51040,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1943 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1943, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1941, ret_val_get_sew_pow_1942), ret_val_get_lmul_pow_1943)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1941, ret_val_get_sew_pow_1942), ret_val_get_lmul_pow_1943)), 8, true); setArg(call_get_pow_1941, 0, reinterpret_cast(this)); setArg(call_get_pow_1941, 1, EEW); setRet(call_get_pow_1941, 0, ret_val_get_pow_1941); @@ -51119,7 +51175,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1950 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1950, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1948, ret_val_get_sew_pow_1949), ret_val_get_lmul_pow_1950)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1948, ret_val_get_sew_pow_1949), ret_val_get_lmul_pow_1950)), 8, true); setArg(call_get_pow_1948, 0, reinterpret_cast(this)); setArg(call_get_pow_1948, 1, EEW); setRet(call_get_pow_1948, 0, ret_val_get_pow_1948); @@ -51254,7 +51310,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1957 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1957, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1955, ret_val_get_sew_pow_1956), ret_val_get_lmul_pow_1957)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1955, ret_val_get_sew_pow_1956), ret_val_get_lmul_pow_1957)), 8, true); setArg(call_get_pow_1955, 0, reinterpret_cast(this)); setArg(call_get_pow_1955, 1, EEW); setRet(call_get_pow_1955, 0, ret_val_get_pow_1955); @@ -51389,7 +51445,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1964 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1964, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1962, ret_val_get_sew_pow_1963), ret_val_get_lmul_pow_1964)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1962, ret_val_get_sew_pow_1963), ret_val_get_lmul_pow_1964)), 8, true); setArg(call_get_pow_1962, 0, reinterpret_cast(this)); setArg(call_get_pow_1962, 1, EEW); setRet(call_get_pow_1962, 0, ret_val_get_pow_1962); @@ -51524,7 +51580,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1971 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1971, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1969, ret_val_get_sew_pow_1970), ret_val_get_lmul_pow_1971)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1969, ret_val_get_sew_pow_1970), ret_val_get_lmul_pow_1971)), 8, true); setArg(call_get_pow_1969, 0, reinterpret_cast(this)); setArg(call_get_pow_1969, 1, EEW); setRet(call_get_pow_1969, 0, ret_val_get_pow_1969); @@ -51659,7 +51715,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1978 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1978, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1976, ret_val_get_sew_pow_1977), ret_val_get_lmul_pow_1978)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1976, ret_val_get_sew_pow_1977), ret_val_get_lmul_pow_1978)), 8, true); setArg(call_get_pow_1976, 0, reinterpret_cast(this)); setArg(call_get_pow_1976, 1, EEW); setRet(call_get_pow_1976, 0, ret_val_get_pow_1976); @@ -51794,7 +51850,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1985 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1985, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1983, ret_val_get_sew_pow_1984), ret_val_get_lmul_pow_1985)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1983, ret_val_get_sew_pow_1984), ret_val_get_lmul_pow_1985)), 8, true); setArg(call_get_pow_1983, 0, reinterpret_cast(this)); setArg(call_get_pow_1983, 1, EEW); setRet(call_get_pow_1983, 0, ret_val_get_pow_1983); @@ -51929,7 +51985,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1992 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1992, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1990, ret_val_get_sew_pow_1991), ret_val_get_lmul_pow_1992)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1990, ret_val_get_sew_pow_1991), ret_val_get_lmul_pow_1992)), 8, true); setArg(call_get_pow_1990, 0, reinterpret_cast(this)); setArg(call_get_pow_1990, 1, EEW); setRet(call_get_pow_1990, 0, ret_val_get_pow_1990); @@ -52064,7 +52120,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_1999 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_1999, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1997, ret_val_get_sew_pow_1998), ret_val_get_lmul_pow_1999)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_1997, ret_val_get_sew_pow_1998), ret_val_get_lmul_pow_1999)), 8, true); setArg(call_get_pow_1997, 0, reinterpret_cast(this)); setArg(call_get_pow_1997, 1, EEW); setRet(call_get_pow_1997, 0, ret_val_get_pow_1997); @@ -52199,7 +52255,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_2006 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2006, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2004, ret_val_get_sew_pow_2005), ret_val_get_lmul_pow_2006)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2004, ret_val_get_sew_pow_2005), ret_val_get_lmul_pow_2006)), 8, true); setArg(call_get_pow_2004, 0, reinterpret_cast(this)); setArg(call_get_pow_2004, 1, EEW); setRet(call_get_pow_2004, 0, ret_val_get_pow_2004); @@ -52334,7 +52390,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_2013 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2013, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2011, ret_val_get_sew_pow_2012), ret_val_get_lmul_pow_2013)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2011, ret_val_get_sew_pow_2012), ret_val_get_lmul_pow_2013)), 8, true); setArg(call_get_pow_2011, 0, reinterpret_cast(this)); setArg(call_get_pow_2011, 1, EEW); setRet(call_get_pow_2011, 0, ret_val_get_pow_2011); @@ -52469,7 +52525,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_2020 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2020, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2018, ret_val_get_sew_pow_2019), ret_val_get_lmul_pow_2020)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2018, ret_val_get_sew_pow_2019), ret_val_get_lmul_pow_2020)), 8, true); setArg(call_get_pow_2018, 0, reinterpret_cast(this)); setArg(call_get_pow_2018, 1, EEW); setRet(call_get_pow_2018, 0, ret_val_get_pow_2018); @@ -52604,7 +52660,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_2027 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2027, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2025, ret_val_get_sew_pow_2026), ret_val_get_lmul_pow_2027)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2025, ret_val_get_sew_pow_2026), ret_val_get_lmul_pow_2027)), 8, true); setArg(call_get_pow_2025, 0, reinterpret_cast(this)); setArg(call_get_pow_2025, 1, EEW); setRet(call_get_pow_2025, 0, ret_val_get_pow_2025); @@ -52739,7 +52795,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_2034 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2034, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2032, ret_val_get_sew_pow_2033), ret_val_get_lmul_pow_2034)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2032, ret_val_get_sew_pow_2033), ret_val_get_lmul_pow_2034)), 8, true); setArg(call_get_pow_2032, 0, reinterpret_cast(this)); setArg(call_get_pow_2032, 1, EEW); setRet(call_get_pow_2032, 0, ret_val_get_pow_2032); @@ -52874,7 +52930,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_2041 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2041, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2039, ret_val_get_sew_pow_2040), ret_val_get_lmul_pow_2041)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2039, ret_val_get_sew_pow_2040), ret_val_get_lmul_pow_2041)), 8, true); setArg(call_get_pow_2039, 0, reinterpret_cast(this)); setArg(call_get_pow_2039, 1, EEW); setRet(call_get_pow_2039, 0, ret_val_get_pow_2039); @@ -53009,7 +53065,7 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_get_lmul_pow_2048 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2048, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto EMUL_pow = gen_ext(cc, - (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2046, ret_val_get_sew_pow_2047), ret_val_get_lmul_pow_2048)), 3, true); + (gen_operation(cc, add, gen_operation(cc, sub, ret_val_get_pow_2046, ret_val_get_sew_pow_2047), ret_val_get_lmul_pow_2048)), 8, true); setArg(call_get_pow_2046, 0, reinterpret_cast(this)); setArg(call_get_pow_2046, 1, EEW); setRet(call_get_pow_2046, 0, ret_val_get_pow_2046); @@ -53179,11 +53235,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2056 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2056, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2056, 64, false) - , traits::vstart); + auto tmp2056 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2056, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2056, traits::vstart); } cc.bind(label_merge); } @@ -53278,11 +53332,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2060 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2060, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2060, 64, false) - , traits::vstart); + auto tmp2060 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2060, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2060, traits::vstart); } cc.bind(label_merge); } @@ -53382,11 +53434,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2065 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2065, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2065, 64, false) - , traits::vstart); + auto tmp2065 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2065, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2065, traits::vstart); } cc.bind(label_merge); } @@ -53481,11 +53531,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2069 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2069, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2069, 64, false) - , traits::vstart); + auto tmp2069 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2069, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2069, traits::vstart); } cc.bind(label_merge); } @@ -53585,11 +53633,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2074 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2074, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2074, 64, false) - , traits::vstart); + auto tmp2074 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2074, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2074, traits::vstart); } cc.bind(label_merge); } @@ -53684,11 +53730,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2078 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2078, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2078, 64, false) - , traits::vstart); + auto tmp2078 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2078, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2078, traits::vstart); } cc.bind(label_merge); } @@ -53788,11 +53832,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2083 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2083, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2083, 64, false) - , traits::vstart); + auto tmp2083 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2083, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2083, traits::vstart); } cc.bind(label_merge); } @@ -53931,11 +53973,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2092 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2092, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2092, 64, false) - , traits::vstart); + auto tmp2092 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2092, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2092, traits::vstart); } cc.bind(label_merge); } @@ -54070,11 +54110,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2100 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2100, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2100, 64, false) - , traits::vstart); + auto tmp2100 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2100, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2100, traits::vstart); } cc.bind(label_merge); } @@ -54214,11 +54252,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2109 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2109, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2109, 64, false) - , traits::vstart); + auto tmp2109 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2109, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2109, traits::vstart); } cc.bind(label_merge); } @@ -54353,11 +54389,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2117 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2117, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2117, 64, false) - , traits::vstart); + auto tmp2117 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2117, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2117, traits::vstart); } cc.bind(label_merge); } @@ -54497,11 +54531,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2126 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2126, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2126, 64, false) - , traits::vstart); + auto tmp2126 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2126, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2126, traits::vstart); } cc.bind(label_merge); } @@ -54636,11 +54668,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2134 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2134, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2134, 64, false) - , traits::vstart); + auto tmp2134 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2134, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2134, traits::vstart); } cc.bind(label_merge); } @@ -54780,11 +54810,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2143 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2143, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2143, 64, false) - , traits::vstart); + auto tmp2143 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2143, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2143, traits::vstart); } cc.bind(label_merge); } @@ -54919,11 +54947,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2151 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2151, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2151, 64, false) - , traits::vstart); + auto tmp2151 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2151, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2151, traits::vstart); } cc.bind(label_merge); } @@ -55052,11 +55078,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2159 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2159, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2159, 64, false) - , traits::vstart); + auto tmp2159 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2159, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2159, traits::vstart); } cc.bind(label_merge); } @@ -55180,11 +55204,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2166 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2166, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2166, 64, false) - , traits::vstart); + auto tmp2166 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2166, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2166, traits::vstart); } cc.bind(label_merge); } @@ -55313,11 +55335,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2174 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2174, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2174, 64, false) - , traits::vstart); + auto tmp2174 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2174, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2174, traits::vstart); } cc.bind(label_merge); } @@ -55441,11 +55461,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2181 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2181, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2181, 64, false) - , traits::vstart); + auto tmp2181 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2181, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2181, traits::vstart); } cc.bind(label_merge); } @@ -55574,11 +55592,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2189 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2189, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2189, 64, false) - , traits::vstart); + auto tmp2189 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2189, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2189, traits::vstart); } cc.bind(label_merge); } @@ -55702,11 +55718,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2196 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2196, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2196, 64, false) - , traits::vstart); + auto tmp2196 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2196, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2196, traits::vstart); } cc.bind(label_merge); } @@ -55835,11 +55849,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2204 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2204, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2204, 64, false) - , traits::vstart); + auto tmp2204 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2204, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2204, traits::vstart); } cc.bind(label_merge); } @@ -55963,11 +55975,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2211 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2211, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2211, 64, false) - , traits::vstart); + auto tmp2211 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2211, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2211, traits::vstart); } cc.bind(label_merge); } @@ -56019,15 +56029,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2212, 0, ret_val_get_sew_pow_2212); auto tmp2213 = get_reg(cc, 8, false); mov(cc, tmp2213, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2213, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2213, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2214; x86::Gp ret_val_get_lmul_pow_2214 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2214, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2214; setArg(call_get_lmul_pow_2214, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2214, 0, ret_val_get_lmul_pow_2214); - auto SEW_target = gen_operation(cc, udiv, SEW, 2); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 2)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 1); { auto label_merge = cc.newLabel(); @@ -56089,11 +56100,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2218 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2218, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2218, 64, false) - , traits::vstart); + auto tmp2218 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2218, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2218, traits::vstart); } cc.bind(label_merge); } @@ -56144,15 +56153,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2219, 0, ret_val_get_sew_pow_2219); auto tmp2220 = get_reg(cc, 8, false); mov(cc, tmp2220, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2220, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2220, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2221; x86::Gp ret_val_get_lmul_pow_2221 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2221, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2221; setArg(call_get_lmul_pow_2221, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2221, 0, ret_val_get_lmul_pow_2221); - auto SEW_target = gen_operation(cc, udiv, SEW, 2); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 2)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 1); { auto label_merge = cc.newLabel(); @@ -56214,11 +56224,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2225 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2225, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2225, 64, false) - , traits::vstart); + auto tmp2225 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2225, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2225, traits::vstart); } cc.bind(label_merge); } @@ -56269,15 +56277,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2226, 0, ret_val_get_sew_pow_2226); auto tmp2227 = get_reg(cc, 8, false); mov(cc, tmp2227, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2227, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2227, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2228; x86::Gp ret_val_get_lmul_pow_2228 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2228, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2228; setArg(call_get_lmul_pow_2228, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2228, 0, ret_val_get_lmul_pow_2228); - auto SEW_target = gen_operation(cc, udiv, SEW, 4); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 4)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 2); { auto label_merge = cc.newLabel(); @@ -56339,11 +56348,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2232 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2232, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2232, 64, false) - , traits::vstart); + auto tmp2232 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2232, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2232, traits::vstart); } cc.bind(label_merge); } @@ -56394,15 +56401,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2233, 0, ret_val_get_sew_pow_2233); auto tmp2234 = get_reg(cc, 8, false); mov(cc, tmp2234, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2234, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2234, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2235; x86::Gp ret_val_get_lmul_pow_2235 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2235, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2235; setArg(call_get_lmul_pow_2235, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2235, 0, ret_val_get_lmul_pow_2235); - auto SEW_target = gen_operation(cc, udiv, SEW, 4); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 4)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 2); { auto label_merge = cc.newLabel(); @@ -56464,11 +56472,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2239 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2239, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2239, 64, false) - , traits::vstart); + auto tmp2239 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2239, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2239, traits::vstart); } cc.bind(label_merge); } @@ -56519,15 +56525,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2240, 0, ret_val_get_sew_pow_2240); auto tmp2241 = get_reg(cc, 8, false); mov(cc, tmp2241, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2241, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2241, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2242; x86::Gp ret_val_get_lmul_pow_2242 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2242, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2242; setArg(call_get_lmul_pow_2242, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2242, 0, ret_val_get_lmul_pow_2242); - auto SEW_target = gen_operation(cc, udiv, SEW, 8); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 8)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 3); { auto label_merge = cc.newLabel(); @@ -56589,11 +56596,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2246 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2246, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2246, 64, false) - , traits::vstart); + auto tmp2246 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2246, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2246, traits::vstart); } cc.bind(label_merge); } @@ -56644,15 +56649,16 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_2247, 0, ret_val_get_sew_pow_2247); auto tmp2248 = get_reg(cc, 8, false); mov(cc, tmp2248, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2248, SEW_pow)), 5, false), ~ 1); + auto SEW = gen_ext(cc, + (gen_operation(cc, shl, tmp2248, SEW_pow)), 8, false); InvokeNode* call_get_lmul_pow_2249; x86::Gp ret_val_get_lmul_pow_2249 = get_reg_Gp(cc, 8, true); cc.invoke(&call_get_lmul_pow_2249, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); auto LMUL_pow = ret_val_get_lmul_pow_2249; setArg(call_get_lmul_pow_2249, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_2249, 0, ret_val_get_lmul_pow_2249); - auto SEW_target = gen_operation(cc, udiv, SEW, 8); + auto SEW_target = gen_ext(cc, + (gen_operation(cc, udiv, SEW, 8)), 8, false); auto LMUL_pow_target = gen_operation(cc, sub, LMUL_pow, 3); { auto label_merge = cc.newLabel(); @@ -56714,11 +56720,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2253 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2253, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2253, 64, false) - , traits::vstart); + auto tmp2253 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2253, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2253, traits::vstart); } cc.bind(label_merge); } @@ -56811,11 +56815,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2257 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2257, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2257, 64, false) - , traits::vstart); + auto tmp2257 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2257, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2257, traits::vstart); } cc.bind(label_merge); } @@ -56913,11 +56915,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2262 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2262, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2262, 64, false) - , traits::vstart); + auto tmp2262 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2262, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2262, traits::vstart); } cc.bind(label_merge); } @@ -57009,11 +57009,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2266 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2266, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2266, 64, false) - , traits::vstart); + auto tmp2266 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2266, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2266, traits::vstart); } cc.bind(label_merge); } @@ -57104,11 +57102,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2270 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2270, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2270, 64, false) - , traits::vstart); + auto tmp2270 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2270, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2270, traits::vstart); } cc.bind(label_merge); } @@ -57204,11 +57200,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2275 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2275, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2275, 64, false) - , traits::vstart); + auto tmp2275 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2275, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2275, traits::vstart); } cc.bind(label_merge); } @@ -57299,11 +57293,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2279 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2279, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2279, 64, false) - , traits::vstart); + auto tmp2279 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2279, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2279, traits::vstart); } cc.bind(label_merge); } @@ -57394,11 +57386,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2283 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2283, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2283, 64, false) - , traits::vstart); + auto tmp2283 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2283, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2283, traits::vstart); } cc.bind(label_merge); } @@ -57494,11 +57484,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2288 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2288, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2288, 64, false) - , traits::vstart); + auto tmp2288 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2288, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2288, traits::vstart); } cc.bind(label_merge); } @@ -57589,11 +57577,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2292 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2292, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2292, 64, false) - , traits::vstart); + auto tmp2292 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2292, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2292, traits::vstart); } cc.bind(label_merge); } @@ -57686,11 +57672,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2296 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2296, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2296, 64, false) - , traits::vstart); + auto tmp2296 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2296, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2296, traits::vstart); } cc.bind(label_merge); } @@ -57788,11 +57772,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2301 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2301, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2301, 64, false) - , traits::vstart); + auto tmp2301 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2301, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2301, traits::vstart); } cc.bind(label_merge); } @@ -57883,11 +57865,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2305 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2305, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2305, 64, false) - , traits::vstart); + auto tmp2305 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2305, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2305, traits::vstart); } cc.bind(label_merge); } @@ -57983,11 +57963,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2310 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2310, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2310, 64, false) - , traits::vstart); + auto tmp2310 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2310, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2310, traits::vstart); } cc.bind(label_merge); } @@ -58078,11 +58056,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2314 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2314, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2314, 64, false) - , traits::vstart); + auto tmp2314 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2314, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2314, traits::vstart); } cc.bind(label_merge); } @@ -58178,11 +58154,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2319 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2319, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2319, 64, false) - , traits::vstart); + auto tmp2319 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2319, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2319, traits::vstart); } cc.bind(label_merge); } @@ -58277,11 +58251,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2323 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2323, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2323, 64, false) - , traits::vstart); + auto tmp2323 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2323, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2323, traits::vstart); } cc.bind(label_merge); } @@ -58376,11 +58348,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2327 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2327, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2327, 64, false) - , traits::vstart); + auto tmp2327 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2327, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2327, traits::vstart); } cc.bind(label_merge); } @@ -58480,11 +58450,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2332 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2332, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2332, 64, false) - , traits::vstart); + auto tmp2332 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2332, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2332, traits::vstart); } cc.bind(label_merge); } @@ -58579,11 +58547,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2336 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2336, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2336, 64, false) - , traits::vstart); + auto tmp2336 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2336, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2336, traits::vstart); } cc.bind(label_merge); } @@ -58678,11 +58644,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2340 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2340, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2340, 64, false) - , traits::vstart); + auto tmp2340 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2340, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2340, traits::vstart); } cc.bind(label_merge); } @@ -58782,11 +58746,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2345 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2345, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2345, 64, false) - , traits::vstart); + auto tmp2345 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2345, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2345, traits::vstart); } cc.bind(label_merge); } @@ -58881,11 +58843,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2349 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2349, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2349, 64, false) - , traits::vstart); + auto tmp2349 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2349, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2349, traits::vstart); } cc.bind(label_merge); } @@ -58980,11 +58940,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2353 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2353, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2353, 64, false) - , traits::vstart); + auto tmp2353 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2353, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2353, traits::vstart); } cc.bind(label_merge); } @@ -59084,11 +59042,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2358 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2358, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2358, 64, false) - , traits::vstart); + auto tmp2358 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2358, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2358, traits::vstart); } cc.bind(label_merge); } @@ -59183,11 +59139,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2362 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2362, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2362, 64, false) - , traits::vstart); + auto tmp2362 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2362, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2362, traits::vstart); } cc.bind(label_merge); } @@ -59282,11 +59236,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2366 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2366, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2366, 64, false) - , traits::vstart); + auto tmp2366 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2366, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2366, traits::vstart); } cc.bind(label_merge); } @@ -59386,11 +59338,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2371 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2371, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2371, 64, false) - , traits::vstart); + auto tmp2371 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2371, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2371, traits::vstart); } cc.bind(label_merge); } @@ -59485,11 +59435,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2375 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2375, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2375, 64, false) - , traits::vstart); + auto tmp2375 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2375, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2375, traits::vstart); } cc.bind(label_merge); } @@ -59584,11 +59532,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2379 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2379, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2379, 64, false) - , traits::vstart); + auto tmp2379 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2379, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2379, traits::vstart); } cc.bind(label_merge); } @@ -59688,11 +59634,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2384 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2384, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2384, 64, false) - , traits::vstart); + auto tmp2384 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2384, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2384, traits::vstart); } cc.bind(label_merge); } @@ -59787,11 +59731,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2388 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2388, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2388, 64, false) - , traits::vstart); + auto tmp2388 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2388, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2388, traits::vstart); } cc.bind(label_merge); } @@ -59886,11 +59828,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2392 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2392, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2392, 64, false) - , traits::vstart); + auto tmp2392 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2392, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2392, traits::vstart); } cc.bind(label_merge); } @@ -59990,11 +59930,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2397 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2397, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2397, 64, false) - , traits::vstart); + auto tmp2397 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2397, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2397, traits::vstart); } cc.bind(label_merge); } @@ -60122,11 +60060,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2405 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2405, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2405, 64, false) - , traits::vstart); + auto tmp2405 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2405, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2405, traits::vstart); } cc.bind(label_merge); } @@ -60254,11 +60190,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2413 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2413, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2413, 64, false) - , traits::vstart); + auto tmp2413 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2413, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2413, traits::vstart); } cc.bind(label_merge); } @@ -60393,11 +60327,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2421 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2421, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2421, 64, false) - , traits::vstart); + auto tmp2421 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2421, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2421, traits::vstart); } cc.bind(label_merge); } @@ -60526,11 +60458,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2429 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2429, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2429, 64, false) - , traits::vstart); + auto tmp2429 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2429, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2429, traits::vstart); } cc.bind(label_merge); } @@ -60658,11 +60588,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2437 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2437, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2437, 64, false) - , traits::vstart); + auto tmp2437 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2437, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2437, traits::vstart); } cc.bind(label_merge); } @@ -60797,11 +60725,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2445 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2445, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2445, 64, false) - , traits::vstart); + auto tmp2445 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2445, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2445, traits::vstart); } cc.bind(label_merge); } @@ -60895,11 +60821,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2449 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2449, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2449, 64, false) - , traits::vstart); + auto tmp2449 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2449, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2449, traits::vstart); } cc.bind(label_merge); } @@ -60992,11 +60916,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2453 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2453, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2453, 64, false) - , traits::vstart); + auto tmp2453 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2453, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2453, traits::vstart); } cc.bind(label_merge); } @@ -61094,11 +61016,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2458 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2458, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2458, 64, false) - , traits::vstart); + auto tmp2458 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2458, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2458, traits::vstart); } cc.bind(label_merge); } @@ -61191,11 +61111,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2462 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2462, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2462, 64, false) - , traits::vstart); + auto tmp2462 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2462, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2462, traits::vstart); } cc.bind(label_merge); } @@ -61288,11 +61206,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2466 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2466, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2466, 64, false) - , traits::vstart); + auto tmp2466 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2466, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2466, traits::vstart); } cc.bind(label_merge); } @@ -61390,11 +61306,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2471 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2471, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2471, 64, false) - , traits::vstart); + auto tmp2471 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2471, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2471, traits::vstart); } cc.bind(label_merge); } @@ -61487,11 +61401,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2475 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2475, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2475, 64, false) - , traits::vstart); + auto tmp2475 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2475, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2475, traits::vstart); } cc.bind(label_merge); } @@ -61589,11 +61501,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2480 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2480, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2480, 64, false) - , traits::vstart); + auto tmp2480 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2480, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2480, traits::vstart); } cc.bind(label_merge); } @@ -61686,11 +61596,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2484 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2484, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2484, 64, false) - , traits::vstart); + auto tmp2484 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2484, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2484, traits::vstart); } cc.bind(label_merge); } @@ -61788,11 +61696,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2489 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2489, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2489, 64, false) - , traits::vstart); + auto tmp2489 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2489, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2489, traits::vstart); } cc.bind(label_merge); } @@ -61885,11 +61791,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2493 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2493, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2493, 64, false) - , traits::vstart); + auto tmp2493 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2493, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2493, traits::vstart); } cc.bind(label_merge); } @@ -61982,11 +61886,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2497 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2497, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2497, 64, false) - , traits::vstart); + auto tmp2497 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2497, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2497, traits::vstart); } cc.bind(label_merge); } @@ -62084,11 +61986,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2502 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2502, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2502, 64, false) - , traits::vstart); + auto tmp2502 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2502, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2502, traits::vstart); } cc.bind(label_merge); } @@ -62181,11 +62081,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2506 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2506, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2506, 64, false) - , traits::vstart); + auto tmp2506 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2506, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2506, traits::vstart); } cc.bind(label_merge); } @@ -62278,11 +62176,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2510 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2510, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2510, 64, false) - , traits::vstart); + auto tmp2510 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2510, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2510, traits::vstart); } cc.bind(label_merge); } @@ -62380,11 +62276,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2515 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2515, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2515, 64, false) - , traits::vstart); + auto tmp2515 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2515, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2515, traits::vstart); } cc.bind(label_merge); } @@ -62477,11 +62371,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2519 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2519, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2519, 64, false) - , traits::vstart); + auto tmp2519 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2519, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2519, traits::vstart); } cc.bind(label_merge); } @@ -62579,11 +62471,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2524 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2524, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2524, 64, false) - , traits::vstart); + auto tmp2524 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2524, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2524, traits::vstart); } cc.bind(label_merge); } @@ -62676,11 +62566,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2528 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2528, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2528, 64, false) - , traits::vstart); + auto tmp2528 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2528, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2528, traits::vstart); } cc.bind(label_merge); } @@ -62778,11 +62666,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2533 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2533, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2533, 64, false) - , traits::vstart); + auto tmp2533 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2533, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2533, traits::vstart); } cc.bind(label_merge); } @@ -62877,11 +62763,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2537 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2537, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2537, 64, false) - , traits::vstart); + auto tmp2537 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2537, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2537, traits::vstart); } cc.bind(label_merge); } @@ -62981,11 +62865,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2542 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2542, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2542, 64, false) - , traits::vstart); + auto tmp2542 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2542, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2542, traits::vstart); } cc.bind(label_merge); } @@ -63080,11 +62962,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2546 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2546, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2546, 64, false) - , traits::vstart); + auto tmp2546 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2546, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2546, traits::vstart); } cc.bind(label_merge); } @@ -63184,11 +63064,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2551 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2551, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2551, 64, false) - , traits::vstart); + auto tmp2551 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2551, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2551, traits::vstart); } cc.bind(label_merge); } @@ -63283,11 +63161,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2555 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2555, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2555, 64, false) - , traits::vstart); + auto tmp2555 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2555, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2555, traits::vstart); } cc.bind(label_merge); } @@ -63387,11 +63263,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2560 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2560, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2560, 64, false) - , traits::vstart); + auto tmp2560 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2560, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2560, traits::vstart); } cc.bind(label_merge); } @@ -63486,11 +63360,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2564 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2564, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2564, 64, false) - , traits::vstart); + auto tmp2564 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2564, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2564, traits::vstart); } cc.bind(label_merge); } @@ -63590,11 +63462,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2569 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2569, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2569, 64, false) - , traits::vstart); + auto tmp2569 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2569, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2569, traits::vstart); } cc.bind(label_merge); } @@ -63689,11 +63559,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2573 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2573, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2573, 64, false) - , traits::vstart); + auto tmp2573 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2573, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2573, traits::vstart); } cc.bind(label_merge); } @@ -63793,11 +63661,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2578 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2578, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2578, 64, false) - , traits::vstart); + auto tmp2578 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2578, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2578, traits::vstart); } cc.bind(label_merge); } @@ -63892,11 +63758,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2582 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2582, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2582, 64, false) - , traits::vstart); + auto tmp2582 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2582, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2582, traits::vstart); } cc.bind(label_merge); } @@ -63996,11 +63860,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2587 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2587, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2587, 64, false) - , traits::vstart); + auto tmp2587 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2587, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2587, traits::vstart); } cc.bind(label_merge); } @@ -64095,11 +63957,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2591 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2591, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2591, 64, false) - , traits::vstart); + auto tmp2591 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2591, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2591, traits::vstart); } cc.bind(label_merge); } @@ -64199,11 +64059,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2596 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2596, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2596, 64, false) - , traits::vstart); + auto tmp2596 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2596, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2596, traits::vstart); } cc.bind(label_merge); } @@ -64298,11 +64156,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2600 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2600, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2600, 64, false) - , traits::vstart); + auto tmp2600 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2600, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2600, traits::vstart); } cc.bind(label_merge); } @@ -64402,11 +64258,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2605 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2605, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2605, 64, false) - , traits::vstart); + auto tmp2605 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2605, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2605, traits::vstart); } cc.bind(label_merge); } @@ -64501,11 +64355,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2609 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2609, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2609, 64, false) - , traits::vstart); + auto tmp2609 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2609, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2609, traits::vstart); } cc.bind(label_merge); } @@ -64605,11 +64457,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2614 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2614, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2614, 64, false) - , traits::vstart); + auto tmp2614 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2614, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2614, traits::vstart); } cc.bind(label_merge); } @@ -64704,11 +64554,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2618 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2618, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2618, 64, false) - , traits::vstart); + auto tmp2618 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2618, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2618, traits::vstart); } cc.bind(label_merge); } @@ -64808,11 +64656,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2623 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2623, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2623, 64, false) - , traits::vstart); + auto tmp2623 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2623, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2623, traits::vstart); } cc.bind(label_merge); } @@ -64907,11 +64753,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2627 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2627, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2627, 64, false) - , traits::vstart); + auto tmp2627 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2627, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2627, traits::vstart); } cc.bind(label_merge); } @@ -65011,11 +64855,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2632 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2632, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2632, 64, false) - , traits::vstart); + auto tmp2632 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2632, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2632, traits::vstart); } cc.bind(label_merge); } @@ -65110,11 +64952,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2636 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2636, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2636, 64, false) - , traits::vstart); + auto tmp2636 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2636, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2636, traits::vstart); } cc.bind(label_merge); } @@ -65214,11 +65054,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2641 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2641, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2641, 64, false) - , traits::vstart); + auto tmp2641 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2641, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2641, traits::vstart); } cc.bind(label_merge); } @@ -65357,11 +65195,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2650 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2650, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2650, 64, false) - , traits::vstart); + auto tmp2650 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2650, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2650, traits::vstart); } cc.bind(label_merge); } @@ -65496,11 +65332,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2658 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2658, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2658, 64, false) - , traits::vstart); + auto tmp2658 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2658, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2658, traits::vstart); } cc.bind(label_merge); } @@ -65640,11 +65474,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2667 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2667, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2667, 64, false) - , traits::vstart); + auto tmp2667 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2667, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2667, traits::vstart); } cc.bind(label_merge); } @@ -65779,11 +65611,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2675 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2675, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2675, 64, false) - , traits::vstart); + auto tmp2675 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2675, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2675, traits::vstart); } cc.bind(label_merge); } @@ -65923,11 +65753,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2684 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2684, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2684, 64, false) - , traits::vstart); + auto tmp2684 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2684, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2684, traits::vstart); } cc.bind(label_merge); } @@ -66062,11 +65890,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2692 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2692, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2692, 64, false) - , traits::vstart); + auto tmp2692 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2692, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2692, traits::vstart); } cc.bind(label_merge); } @@ -66162,11 +65988,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2696 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2696, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2696, 64, false) - , traits::vstart); + auto tmp2696 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2696, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2696, traits::vstart); } cc.bind(label_merge); } @@ -66266,11 +66090,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2701 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2701, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2701, 64, false) - , traits::vstart); + auto tmp2701 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2701, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2701, traits::vstart); } cc.bind(label_merge); } @@ -66365,11 +66187,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2705 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2705, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2705, 64, false) - , traits::vstart); + auto tmp2705 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2705, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2705, traits::vstart); } cc.bind(label_merge); } @@ -66469,11 +66289,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2710 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2710, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2710, 64, false) - , traits::vstart); + auto tmp2710 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2710, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2710, traits::vstart); } cc.bind(label_merge); } @@ -66568,11 +66386,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2714 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2714, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2714, 64, false) - , traits::vstart); + auto tmp2714 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2714, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2714, traits::vstart); } cc.bind(label_merge); } @@ -66672,11 +66488,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2719 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2719, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2719, 64, false) - , traits::vstart); + auto tmp2719 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2719, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2719, traits::vstart); } cc.bind(label_merge); } @@ -66771,11 +66585,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2723 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2723, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2723, 64, false) - , traits::vstart); + auto tmp2723 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2723, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2723, traits::vstart); } cc.bind(label_merge); } @@ -66875,11 +66687,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2728 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2728, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2728, 64, false) - , traits::vstart); + auto tmp2728 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2728, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2728, traits::vstart); } cc.bind(label_merge); } @@ -67018,11 +66828,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2737 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2737, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2737, 64, false) - , traits::vstart); + auto tmp2737 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2737, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2737, traits::vstart); } cc.bind(label_merge); } @@ -67157,11 +66965,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2745 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2745, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2745, 64, false) - , traits::vstart); + auto tmp2745 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2745, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2745, traits::vstart); } cc.bind(label_merge); } @@ -67301,11 +67107,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2754 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2754, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2754, 64, false) - , traits::vstart); + auto tmp2754 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2754, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2754, traits::vstart); } cc.bind(label_merge); } @@ -67440,11 +67244,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2762 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2762, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2762, 64, false) - , traits::vstart); + auto tmp2762 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2762, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2762, traits::vstart); } cc.bind(label_merge); } @@ -67584,11 +67386,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2771 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2771, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2771, 64, false) - , traits::vstart); + auto tmp2771 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2771, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2771, traits::vstart); } cc.bind(label_merge); } @@ -67723,11 +67523,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2779 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2779, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2779, 64, false) - , traits::vstart); + auto tmp2779 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2779, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2779, traits::vstart); } cc.bind(label_merge); } @@ -67782,7 +67580,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto tmp2781 = get_reg(cc, 8, false); mov(cc, tmp2781, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2781, ret_val_get_sew_pow_2780)), 5, false), ~ 1); + (gen_operation(cc, shl, tmp2781, ret_val_get_sew_pow_2780)), 8, false), ~ 1); setArg(call_get_sew_pow_2780, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_2780, 0, ret_val_get_sew_pow_2780); InvokeNode* call_get_lmul_pow_2782; @@ -67863,11 +67661,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2787 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2787, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2787, 64, false) - , traits::vstart); + auto tmp2787 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2787, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2787, traits::vstart); } cc.bind(label_merge); } @@ -67959,11 +67755,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2791 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2791, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2791, 64, false) - , traits::vstart); + auto tmp2791 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2791, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2791, traits::vstart); } cc.bind(label_merge); } @@ -68054,11 +67848,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2795 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2795, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2795, 64, false) - , traits::vstart); + auto tmp2795 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2795, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2795, traits::vstart); } cc.bind(label_merge); } @@ -68155,11 +67947,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2800 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2800, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2800, 64, false) - , traits::vstart); + auto tmp2800 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2800, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2800, traits::vstart); } cc.bind(label_merge); } @@ -68248,11 +68038,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2804 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2804, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2804, 64, false) - , traits::vstart); + auto tmp2804 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2804, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2804, traits::vstart); } cc.bind(label_merge); } @@ -68341,11 +68129,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2808 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2808, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2808, 64, false) - , traits::vstart); + auto tmp2808 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2808, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2808, traits::vstart); } cc.bind(label_merge); } @@ -68440,11 +68226,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2813 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2813, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2813, 64, false) - , traits::vstart); + auto tmp2813 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2813, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2813, traits::vstart); } cc.bind(label_merge); } @@ -68525,9 +68309,8 @@ template class vm_impl : public iss::asmjit::vm_base { auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); x86::Gp ret_val_sat_vector_imm_op_2815 = get_reg_Gp(cc, 8, false); cc.invoke(&call_sat_vector_imm_op_2815, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2815, 64, false) - , traits::vxsat); + auto tmp2817 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2815, 64, false)); + write_reg_to_mem(jh, tmp2817, traits::vxsat); setArg(call_sew_2816, 0, reinterpret_cast(this)); setRet(call_sew_2816, 0, ret_val_sew_2816); setArg(call_sat_vector_imm_op_2815, 0, V); @@ -68546,11 +68329,9 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp2817 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2817, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2817, 64, false) - , traits::vstart); + auto tmp2818 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2818, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2818, traits::vstart); } cc.bind(label_merge); } @@ -68596,14 +68377,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2818; - x86::Gp ret_val_illegal_normal_2818 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2818, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2818; - setArg(call_illegal_normal_2818, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2818, 1, vd); - setArg(call_illegal_normal_2818, 2, vm); - setRet(call_illegal_normal_2818, 0, ret_val_illegal_normal_2818); + InvokeNode* call_illegal_normal_2819; + x86::Gp ret_val_illegal_normal_2819 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2819, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2819; + setArg(call_illegal_normal_2819, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2819, 1, vd); + setArg(call_illegal_normal_2819, 2, vm); + setRet(call_illegal_normal_2819, 0, ret_val_illegal_normal_2819); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68619,44 +68400,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2820; - x86::Gp ret_val_sew_2820 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2820, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2819; - auto sat_vector_vector_op_2819_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2819_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2819_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2819_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2819_arg11 = ret_val_sew_2820; + InvokeNode* call_sew_2821; + x86::Gp ret_val_sew_2821 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2821, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2820; + auto sat_vector_vector_op_2820_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2820_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2820_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2820_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2820_arg11 = ret_val_sew_2821; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2819 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2819, &sat_vector_vector_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_op_2819, 64, false) - , traits::vxsat); - setArg(call_sew_2820, 0, reinterpret_cast(this)); - setRet(call_sew_2820, 0, ret_val_sew_2820); - setArg(call_sat_vector_vector_op_2819, 0, V); - setArg(call_sat_vector_vector_op_2819, 1, 32); - setArg(call_sat_vector_vector_op_2819, 2, 0); - setArg(call_sat_vector_vector_op_2819, 3, sat_vector_vector_op_2819_arg3); - setArg(call_sat_vector_vector_op_2819, 4, sat_vector_vector_op_2819_arg4); - setArg(call_sat_vector_vector_op_2819, 5, sat_vector_vector_op_2819_arg5); - setArg(call_sat_vector_vector_op_2819, 6, sat_vector_vector_op_2819_arg6); - setArg(call_sat_vector_vector_op_2819, 7, vm); - setArg(call_sat_vector_vector_op_2819, 8, vd); - setArg(call_sat_vector_vector_op_2819, 9, vs2); - setArg(call_sat_vector_vector_op_2819, 10, vs1); - setArg(call_sat_vector_vector_op_2819, 11, sat_vector_vector_op_2819_arg11); - setRet(call_sat_vector_vector_op_2819, 0, ret_val_sat_vector_vector_op_2819); + x86::Gp ret_val_sat_vector_vector_op_2820 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2820, &sat_vector_vector_op, FuncSignature::build()); + auto tmp2822 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_op_2820, 64, false)); + write_reg_to_mem(jh, tmp2822, traits::vxsat); + setArg(call_sew_2821, 0, reinterpret_cast(this)); + setRet(call_sew_2821, 0, ret_val_sew_2821); + setArg(call_sat_vector_vector_op_2820, 0, V); + setArg(call_sat_vector_vector_op_2820, 1, 32); + setArg(call_sat_vector_vector_op_2820, 2, 0); + setArg(call_sat_vector_vector_op_2820, 3, sat_vector_vector_op_2820_arg3); + setArg(call_sat_vector_vector_op_2820, 4, sat_vector_vector_op_2820_arg4); + setArg(call_sat_vector_vector_op_2820, 5, sat_vector_vector_op_2820_arg5); + setArg(call_sat_vector_vector_op_2820, 6, sat_vector_vector_op_2820_arg6); + setArg(call_sat_vector_vector_op_2820, 7, vm); + setArg(call_sat_vector_vector_op_2820, 8, vd); + setArg(call_sat_vector_vector_op_2820, 9, vs2); + setArg(call_sat_vector_vector_op_2820, 10, vs1); + setArg(call_sat_vector_vector_op_2820, 11, sat_vector_vector_op_2820_arg11); + setRet(call_sat_vector_vector_op_2820, 0, ret_val_sat_vector_vector_op_2820); } cc.bind(label_merge); } - auto tmp2821 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2821, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2821, 64, false) - , traits::vstart); + auto tmp2823 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2823, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2823, traits::vstart); } cc.bind(label_merge); } @@ -68702,16 +68480,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2822; - x86::Gp ret_val_illegal_normal_2822 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2822, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2823 = get_reg(cc, 8, false); - mov(cc, tmp2823, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2823, ret_val_illegal_normal_2822); - setArg(call_illegal_normal_2822, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2822, 1, vd); - setArg(call_illegal_normal_2822, 2, vm); - setRet(call_illegal_normal_2822, 0, ret_val_illegal_normal_2822); + InvokeNode* call_illegal_normal_2824; + x86::Gp ret_val_illegal_normal_2824 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2824, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2825 = get_reg(cc, 8, false); + mov(cc, tmp2825, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2825, ret_val_illegal_normal_2824); + setArg(call_illegal_normal_2824, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2824, 1, vd); + setArg(call_illegal_normal_2824, 2, vm); + setRet(call_illegal_normal_2824, 0, ret_val_illegal_normal_2824); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68727,47 +68505,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2825; - x86::Gp ret_val_sew_2825 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2825, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2824; - auto sat_vector_imm_op_2824_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2824_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2824_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2824_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2824_arg10 = gen_ext(cc, + InvokeNode* call_sew_2827; + x86::Gp ret_val_sew_2827 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2827, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2826; + auto sat_vector_imm_op_2826_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2826_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2826_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2826_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2826_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); - auto sat_vector_imm_op_2824_arg11 = ret_val_sew_2825; + auto sat_vector_imm_op_2826_arg11 = ret_val_sew_2827; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2824 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2824, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2824, 64, false) - , traits::vxsat); - setArg(call_sew_2825, 0, reinterpret_cast(this)); - setRet(call_sew_2825, 0, ret_val_sew_2825); - setArg(call_sat_vector_imm_op_2824, 0, V); - setArg(call_sat_vector_imm_op_2824, 1, 32); - setArg(call_sat_vector_imm_op_2824, 2, 4); - setArg(call_sat_vector_imm_op_2824, 3, sat_vector_imm_op_2824_arg3); - setArg(call_sat_vector_imm_op_2824, 4, sat_vector_imm_op_2824_arg4); - setArg(call_sat_vector_imm_op_2824, 5, sat_vector_imm_op_2824_arg5); - setArg(call_sat_vector_imm_op_2824, 6, sat_vector_imm_op_2824_arg6); - setArg(call_sat_vector_imm_op_2824, 7, vm); - setArg(call_sat_vector_imm_op_2824, 8, vd); - setArg(call_sat_vector_imm_op_2824, 9, vs2); - setArg(call_sat_vector_imm_op_2824, 10, sat_vector_imm_op_2824_arg10); - setArg(call_sat_vector_imm_op_2824, 11, sat_vector_imm_op_2824_arg11); - setRet(call_sat_vector_imm_op_2824, 0, ret_val_sat_vector_imm_op_2824); + x86::Gp ret_val_sat_vector_imm_op_2826 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2826, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2828 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2826, 64, false)); + write_reg_to_mem(jh, tmp2828, traits::vxsat); + setArg(call_sew_2827, 0, reinterpret_cast(this)); + setRet(call_sew_2827, 0, ret_val_sew_2827); + setArg(call_sat_vector_imm_op_2826, 0, V); + setArg(call_sat_vector_imm_op_2826, 1, 32); + setArg(call_sat_vector_imm_op_2826, 2, 4); + setArg(call_sat_vector_imm_op_2826, 3, sat_vector_imm_op_2826_arg3); + setArg(call_sat_vector_imm_op_2826, 4, sat_vector_imm_op_2826_arg4); + setArg(call_sat_vector_imm_op_2826, 5, sat_vector_imm_op_2826_arg5); + setArg(call_sat_vector_imm_op_2826, 6, sat_vector_imm_op_2826_arg6); + setArg(call_sat_vector_imm_op_2826, 7, vm); + setArg(call_sat_vector_imm_op_2826, 8, vd); + setArg(call_sat_vector_imm_op_2826, 9, vs2); + setArg(call_sat_vector_imm_op_2826, 10, sat_vector_imm_op_2826_arg10); + setArg(call_sat_vector_imm_op_2826, 11, sat_vector_imm_op_2826_arg11); + setRet(call_sat_vector_imm_op_2826, 0, ret_val_sat_vector_imm_op_2826); } cc.bind(label_merge); } - auto tmp2826 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2826, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2826, 64, false) - , traits::vstart); + auto tmp2829 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2829, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2829, traits::vstart); } cc.bind(label_merge); } @@ -68813,14 +68588,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2827; - x86::Gp ret_val_illegal_normal_2827 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2827, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2827; - setArg(call_illegal_normal_2827, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2827, 1, vd); - setArg(call_illegal_normal_2827, 2, vm); - setRet(call_illegal_normal_2827, 0, ret_val_illegal_normal_2827); + InvokeNode* call_illegal_normal_2830; + x86::Gp ret_val_illegal_normal_2830 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2830, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2830; + setArg(call_illegal_normal_2830, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2830, 1, vd); + setArg(call_illegal_normal_2830, 2, vm); + setRet(call_illegal_normal_2830, 0, ret_val_illegal_normal_2830); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68836,44 +68611,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2829; - x86::Gp ret_val_sew_2829 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2829, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2828; - auto sat_vector_imm_op_2828_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2828_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2828_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2828_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2828_arg11 = ret_val_sew_2829; + InvokeNode* call_sew_2832; + x86::Gp ret_val_sew_2832 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2832, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2831; + auto sat_vector_imm_op_2831_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2831_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2831_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2831_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2831_arg11 = ret_val_sew_2832; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2828 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2828, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2828, 64, false) - , traits::vxsat); - setArg(call_sew_2829, 0, reinterpret_cast(this)); - setRet(call_sew_2829, 0, ret_val_sew_2829); - setArg(call_sat_vector_imm_op_2828, 0, V); - setArg(call_sat_vector_imm_op_2828, 1, 33); - setArg(call_sat_vector_imm_op_2828, 2, 3); - setArg(call_sat_vector_imm_op_2828, 3, sat_vector_imm_op_2828_arg3); - setArg(call_sat_vector_imm_op_2828, 4, sat_vector_imm_op_2828_arg4); - setArg(call_sat_vector_imm_op_2828, 5, sat_vector_imm_op_2828_arg5); - setArg(call_sat_vector_imm_op_2828, 6, sat_vector_imm_op_2828_arg6); - setArg(call_sat_vector_imm_op_2828, 7, vm); - setArg(call_sat_vector_imm_op_2828, 8, vd); - setArg(call_sat_vector_imm_op_2828, 9, vs2); - setArg(call_sat_vector_imm_op_2828, 10, (int64_t)(int8_t)sext<5>(simm)); - setArg(call_sat_vector_imm_op_2828, 11, sat_vector_imm_op_2828_arg11); - setRet(call_sat_vector_imm_op_2828, 0, ret_val_sat_vector_imm_op_2828); + x86::Gp ret_val_sat_vector_imm_op_2831 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2831, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2833 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2831, 64, false)); + write_reg_to_mem(jh, tmp2833, traits::vxsat); + setArg(call_sew_2832, 0, reinterpret_cast(this)); + setRet(call_sew_2832, 0, ret_val_sew_2832); + setArg(call_sat_vector_imm_op_2831, 0, V); + setArg(call_sat_vector_imm_op_2831, 1, 33); + setArg(call_sat_vector_imm_op_2831, 2, 3); + setArg(call_sat_vector_imm_op_2831, 3, sat_vector_imm_op_2831_arg3); + setArg(call_sat_vector_imm_op_2831, 4, sat_vector_imm_op_2831_arg4); + setArg(call_sat_vector_imm_op_2831, 5, sat_vector_imm_op_2831_arg5); + setArg(call_sat_vector_imm_op_2831, 6, sat_vector_imm_op_2831_arg6); + setArg(call_sat_vector_imm_op_2831, 7, vm); + setArg(call_sat_vector_imm_op_2831, 8, vd); + setArg(call_sat_vector_imm_op_2831, 9, vs2); + setArg(call_sat_vector_imm_op_2831, 10, (int64_t)(int8_t)sext<5>(simm)); + setArg(call_sat_vector_imm_op_2831, 11, sat_vector_imm_op_2831_arg11); + setRet(call_sat_vector_imm_op_2831, 0, ret_val_sat_vector_imm_op_2831); } cc.bind(label_merge); } - auto tmp2830 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2830, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2830, 64, false) - , traits::vstart); + auto tmp2834 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2834, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2834, traits::vstart); } cc.bind(label_merge); } @@ -68919,14 +68691,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2831; - x86::Gp ret_val_illegal_normal_2831 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2831, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2831; - setArg(call_illegal_normal_2831, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2831, 1, vd); - setArg(call_illegal_normal_2831, 2, vm); - setRet(call_illegal_normal_2831, 0, ret_val_illegal_normal_2831); + InvokeNode* call_illegal_normal_2835; + x86::Gp ret_val_illegal_normal_2835 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2835, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2835; + setArg(call_illegal_normal_2835, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2835, 1, vd); + setArg(call_illegal_normal_2835, 2, vm); + setRet(call_illegal_normal_2835, 0, ret_val_illegal_normal_2835); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -68942,44 +68714,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2833; - x86::Gp ret_val_sew_2833 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2833, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2832; - auto sat_vector_vector_op_2832_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2832_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2832_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2832_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2832_arg11 = ret_val_sew_2833; + InvokeNode* call_sew_2837; + x86::Gp ret_val_sew_2837 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2837, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2836; + auto sat_vector_vector_op_2836_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2836_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2836_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2836_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2836_arg11 = ret_val_sew_2837; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2832 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2832, &sat_vector_vector_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_op_2832, 64, false) - , traits::vxsat); - setArg(call_sew_2833, 0, reinterpret_cast(this)); - setRet(call_sew_2833, 0, ret_val_sew_2833); - setArg(call_sat_vector_vector_op_2832, 0, V); - setArg(call_sat_vector_vector_op_2832, 1, 33); - setArg(call_sat_vector_vector_op_2832, 2, 0); - setArg(call_sat_vector_vector_op_2832, 3, sat_vector_vector_op_2832_arg3); - setArg(call_sat_vector_vector_op_2832, 4, sat_vector_vector_op_2832_arg4); - setArg(call_sat_vector_vector_op_2832, 5, sat_vector_vector_op_2832_arg5); - setArg(call_sat_vector_vector_op_2832, 6, sat_vector_vector_op_2832_arg6); - setArg(call_sat_vector_vector_op_2832, 7, vm); - setArg(call_sat_vector_vector_op_2832, 8, vd); - setArg(call_sat_vector_vector_op_2832, 9, vs2); - setArg(call_sat_vector_vector_op_2832, 10, vs1); - setArg(call_sat_vector_vector_op_2832, 11, sat_vector_vector_op_2832_arg11); - setRet(call_sat_vector_vector_op_2832, 0, ret_val_sat_vector_vector_op_2832); + x86::Gp ret_val_sat_vector_vector_op_2836 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2836, &sat_vector_vector_op, FuncSignature::build()); + auto tmp2838 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_op_2836, 64, false)); + write_reg_to_mem(jh, tmp2838, traits::vxsat); + setArg(call_sew_2837, 0, reinterpret_cast(this)); + setRet(call_sew_2837, 0, ret_val_sew_2837); + setArg(call_sat_vector_vector_op_2836, 0, V); + setArg(call_sat_vector_vector_op_2836, 1, 33); + setArg(call_sat_vector_vector_op_2836, 2, 0); + setArg(call_sat_vector_vector_op_2836, 3, sat_vector_vector_op_2836_arg3); + setArg(call_sat_vector_vector_op_2836, 4, sat_vector_vector_op_2836_arg4); + setArg(call_sat_vector_vector_op_2836, 5, sat_vector_vector_op_2836_arg5); + setArg(call_sat_vector_vector_op_2836, 6, sat_vector_vector_op_2836_arg6); + setArg(call_sat_vector_vector_op_2836, 7, vm); + setArg(call_sat_vector_vector_op_2836, 8, vd); + setArg(call_sat_vector_vector_op_2836, 9, vs2); + setArg(call_sat_vector_vector_op_2836, 10, vs1); + setArg(call_sat_vector_vector_op_2836, 11, sat_vector_vector_op_2836_arg11); + setRet(call_sat_vector_vector_op_2836, 0, ret_val_sat_vector_vector_op_2836); } cc.bind(label_merge); } - auto tmp2834 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2834, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2834, 64, false) - , traits::vstart); + auto tmp2839 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2839, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2839, traits::vstart); } cc.bind(label_merge); } @@ -69025,16 +68794,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2835; - x86::Gp ret_val_illegal_normal_2835 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2835, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2836 = get_reg(cc, 8, false); - mov(cc, tmp2836, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2836, ret_val_illegal_normal_2835); - setArg(call_illegal_normal_2835, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2835, 1, vd); - setArg(call_illegal_normal_2835, 2, vm); - setRet(call_illegal_normal_2835, 0, ret_val_illegal_normal_2835); + InvokeNode* call_illegal_normal_2840; + x86::Gp ret_val_illegal_normal_2840 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2840, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2841 = get_reg(cc, 8, false); + mov(cc, tmp2841, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2841, ret_val_illegal_normal_2840); + setArg(call_illegal_normal_2840, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2840, 1, vd); + setArg(call_illegal_normal_2840, 2, vm); + setRet(call_illegal_normal_2840, 0, ret_val_illegal_normal_2840); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69050,47 +68819,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2838; - x86::Gp ret_val_sew_2838 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2838, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2837; - auto sat_vector_imm_op_2837_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2837_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2837_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2837_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2837_arg10 = gen_ext(cc, + InvokeNode* call_sew_2843; + x86::Gp ret_val_sew_2843 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2843, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2842; + auto sat_vector_imm_op_2842_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2842_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2842_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2842_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2842_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); - auto sat_vector_imm_op_2837_arg11 = ret_val_sew_2838; + auto sat_vector_imm_op_2842_arg11 = ret_val_sew_2843; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2837 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2837, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2837, 64, false) - , traits::vxsat); - setArg(call_sew_2838, 0, reinterpret_cast(this)); - setRet(call_sew_2838, 0, ret_val_sew_2838); - setArg(call_sat_vector_imm_op_2837, 0, V); - setArg(call_sat_vector_imm_op_2837, 1, 33); - setArg(call_sat_vector_imm_op_2837, 2, 4); - setArg(call_sat_vector_imm_op_2837, 3, sat_vector_imm_op_2837_arg3); - setArg(call_sat_vector_imm_op_2837, 4, sat_vector_imm_op_2837_arg4); - setArg(call_sat_vector_imm_op_2837, 5, sat_vector_imm_op_2837_arg5); - setArg(call_sat_vector_imm_op_2837, 6, sat_vector_imm_op_2837_arg6); - setArg(call_sat_vector_imm_op_2837, 7, vm); - setArg(call_sat_vector_imm_op_2837, 8, vd); - setArg(call_sat_vector_imm_op_2837, 9, vs2); - setArg(call_sat_vector_imm_op_2837, 10, sat_vector_imm_op_2837_arg10); - setArg(call_sat_vector_imm_op_2837, 11, sat_vector_imm_op_2837_arg11); - setRet(call_sat_vector_imm_op_2837, 0, ret_val_sat_vector_imm_op_2837); + x86::Gp ret_val_sat_vector_imm_op_2842 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2842, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2844 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2842, 64, false)); + write_reg_to_mem(jh, tmp2844, traits::vxsat); + setArg(call_sew_2843, 0, reinterpret_cast(this)); + setRet(call_sew_2843, 0, ret_val_sew_2843); + setArg(call_sat_vector_imm_op_2842, 0, V); + setArg(call_sat_vector_imm_op_2842, 1, 33); + setArg(call_sat_vector_imm_op_2842, 2, 4); + setArg(call_sat_vector_imm_op_2842, 3, sat_vector_imm_op_2842_arg3); + setArg(call_sat_vector_imm_op_2842, 4, sat_vector_imm_op_2842_arg4); + setArg(call_sat_vector_imm_op_2842, 5, sat_vector_imm_op_2842_arg5); + setArg(call_sat_vector_imm_op_2842, 6, sat_vector_imm_op_2842_arg6); + setArg(call_sat_vector_imm_op_2842, 7, vm); + setArg(call_sat_vector_imm_op_2842, 8, vd); + setArg(call_sat_vector_imm_op_2842, 9, vs2); + setArg(call_sat_vector_imm_op_2842, 10, sat_vector_imm_op_2842_arg10); + setArg(call_sat_vector_imm_op_2842, 11, sat_vector_imm_op_2842_arg11); + setRet(call_sat_vector_imm_op_2842, 0, ret_val_sat_vector_imm_op_2842); } cc.bind(label_merge); } - auto tmp2839 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2839, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2839, 64, false) - , traits::vstart); + auto tmp2845 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2845, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2845, traits::vstart); } cc.bind(label_merge); } @@ -69136,14 +68902,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2840; - x86::Gp ret_val_illegal_normal_2840 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2840, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2840; - setArg(call_illegal_normal_2840, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2840, 1, vd); - setArg(call_illegal_normal_2840, 2, vm); - setRet(call_illegal_normal_2840, 0, ret_val_illegal_normal_2840); + InvokeNode* call_illegal_normal_2846; + x86::Gp ret_val_illegal_normal_2846 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2846, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2846; + setArg(call_illegal_normal_2846, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2846, 1, vd); + setArg(call_illegal_normal_2846, 2, vm); + setRet(call_illegal_normal_2846, 0, ret_val_illegal_normal_2846); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69159,44 +68925,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2842; - x86::Gp ret_val_sew_2842 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2842, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2841; - auto sat_vector_vector_op_2841_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2841_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2841_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2841_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2841_arg11 = ret_val_sew_2842; + InvokeNode* call_sew_2848; + x86::Gp ret_val_sew_2848 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2848, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2847; + auto sat_vector_vector_op_2847_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2847_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2847_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2847_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2847_arg11 = ret_val_sew_2848; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2841 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2841, &sat_vector_vector_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_op_2841, 64, false) - , traits::vxsat); - setArg(call_sew_2842, 0, reinterpret_cast(this)); - setRet(call_sew_2842, 0, ret_val_sew_2842); - setArg(call_sat_vector_vector_op_2841, 0, V); - setArg(call_sat_vector_vector_op_2841, 1, 34); - setArg(call_sat_vector_vector_op_2841, 2, 0); - setArg(call_sat_vector_vector_op_2841, 3, sat_vector_vector_op_2841_arg3); - setArg(call_sat_vector_vector_op_2841, 4, sat_vector_vector_op_2841_arg4); - setArg(call_sat_vector_vector_op_2841, 5, sat_vector_vector_op_2841_arg5); - setArg(call_sat_vector_vector_op_2841, 6, sat_vector_vector_op_2841_arg6); - setArg(call_sat_vector_vector_op_2841, 7, vm); - setArg(call_sat_vector_vector_op_2841, 8, vd); - setArg(call_sat_vector_vector_op_2841, 9, vs2); - setArg(call_sat_vector_vector_op_2841, 10, vs1); - setArg(call_sat_vector_vector_op_2841, 11, sat_vector_vector_op_2841_arg11); - setRet(call_sat_vector_vector_op_2841, 0, ret_val_sat_vector_vector_op_2841); + x86::Gp ret_val_sat_vector_vector_op_2847 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2847, &sat_vector_vector_op, FuncSignature::build()); + auto tmp2849 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_op_2847, 64, false)); + write_reg_to_mem(jh, tmp2849, traits::vxsat); + setArg(call_sew_2848, 0, reinterpret_cast(this)); + setRet(call_sew_2848, 0, ret_val_sew_2848); + setArg(call_sat_vector_vector_op_2847, 0, V); + setArg(call_sat_vector_vector_op_2847, 1, 34); + setArg(call_sat_vector_vector_op_2847, 2, 0); + setArg(call_sat_vector_vector_op_2847, 3, sat_vector_vector_op_2847_arg3); + setArg(call_sat_vector_vector_op_2847, 4, sat_vector_vector_op_2847_arg4); + setArg(call_sat_vector_vector_op_2847, 5, sat_vector_vector_op_2847_arg5); + setArg(call_sat_vector_vector_op_2847, 6, sat_vector_vector_op_2847_arg6); + setArg(call_sat_vector_vector_op_2847, 7, vm); + setArg(call_sat_vector_vector_op_2847, 8, vd); + setArg(call_sat_vector_vector_op_2847, 9, vs2); + setArg(call_sat_vector_vector_op_2847, 10, vs1); + setArg(call_sat_vector_vector_op_2847, 11, sat_vector_vector_op_2847_arg11); + setRet(call_sat_vector_vector_op_2847, 0, ret_val_sat_vector_vector_op_2847); } cc.bind(label_merge); } - auto tmp2843 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2843, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2843, 64, false) - , traits::vstart); + auto tmp2850 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2850, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2850, traits::vstart); } cc.bind(label_merge); } @@ -69242,16 +69005,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2844; - x86::Gp ret_val_illegal_normal_2844 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2844, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2845 = get_reg(cc, 8, false); - mov(cc, tmp2845, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2845, ret_val_illegal_normal_2844); - setArg(call_illegal_normal_2844, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2844, 1, vd); - setArg(call_illegal_normal_2844, 2, vm); - setRet(call_illegal_normal_2844, 0, ret_val_illegal_normal_2844); + InvokeNode* call_illegal_normal_2851; + x86::Gp ret_val_illegal_normal_2851 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2851, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2852 = get_reg(cc, 8, false); + mov(cc, tmp2852, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2852, ret_val_illegal_normal_2851); + setArg(call_illegal_normal_2851, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2851, 1, vd); + setArg(call_illegal_normal_2851, 2, vm); + setRet(call_illegal_normal_2851, 0, ret_val_illegal_normal_2851); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69267,47 +69030,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2847; - x86::Gp ret_val_sew_2847 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2847, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2846; - auto sat_vector_imm_op_2846_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2846_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2846_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2846_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2846_arg10 = gen_ext(cc, + InvokeNode* call_sew_2854; + x86::Gp ret_val_sew_2854 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2854, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2853; + auto sat_vector_imm_op_2853_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2853_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2853_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2853_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2853_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); - auto sat_vector_imm_op_2846_arg11 = ret_val_sew_2847; + auto sat_vector_imm_op_2853_arg11 = ret_val_sew_2854; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2846 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2846, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2846, 64, false) - , traits::vxsat); - setArg(call_sew_2847, 0, reinterpret_cast(this)); - setRet(call_sew_2847, 0, ret_val_sew_2847); - setArg(call_sat_vector_imm_op_2846, 0, V); - setArg(call_sat_vector_imm_op_2846, 1, 34); - setArg(call_sat_vector_imm_op_2846, 2, 4); - setArg(call_sat_vector_imm_op_2846, 3, sat_vector_imm_op_2846_arg3); - setArg(call_sat_vector_imm_op_2846, 4, sat_vector_imm_op_2846_arg4); - setArg(call_sat_vector_imm_op_2846, 5, sat_vector_imm_op_2846_arg5); - setArg(call_sat_vector_imm_op_2846, 6, sat_vector_imm_op_2846_arg6); - setArg(call_sat_vector_imm_op_2846, 7, vm); - setArg(call_sat_vector_imm_op_2846, 8, vd); - setArg(call_sat_vector_imm_op_2846, 9, vs2); - setArg(call_sat_vector_imm_op_2846, 10, sat_vector_imm_op_2846_arg10); - setArg(call_sat_vector_imm_op_2846, 11, sat_vector_imm_op_2846_arg11); - setRet(call_sat_vector_imm_op_2846, 0, ret_val_sat_vector_imm_op_2846); + x86::Gp ret_val_sat_vector_imm_op_2853 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2853, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2855 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2853, 64, false)); + write_reg_to_mem(jh, tmp2855, traits::vxsat); + setArg(call_sew_2854, 0, reinterpret_cast(this)); + setRet(call_sew_2854, 0, ret_val_sew_2854); + setArg(call_sat_vector_imm_op_2853, 0, V); + setArg(call_sat_vector_imm_op_2853, 1, 34); + setArg(call_sat_vector_imm_op_2853, 2, 4); + setArg(call_sat_vector_imm_op_2853, 3, sat_vector_imm_op_2853_arg3); + setArg(call_sat_vector_imm_op_2853, 4, sat_vector_imm_op_2853_arg4); + setArg(call_sat_vector_imm_op_2853, 5, sat_vector_imm_op_2853_arg5); + setArg(call_sat_vector_imm_op_2853, 6, sat_vector_imm_op_2853_arg6); + setArg(call_sat_vector_imm_op_2853, 7, vm); + setArg(call_sat_vector_imm_op_2853, 8, vd); + setArg(call_sat_vector_imm_op_2853, 9, vs2); + setArg(call_sat_vector_imm_op_2853, 10, sat_vector_imm_op_2853_arg10); + setArg(call_sat_vector_imm_op_2853, 11, sat_vector_imm_op_2853_arg11); + setRet(call_sat_vector_imm_op_2853, 0, ret_val_sat_vector_imm_op_2853); } cc.bind(label_merge); } - auto tmp2848 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2848, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2848, 64, false) - , traits::vstart); + auto tmp2856 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2856, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2856, traits::vstart); } cc.bind(label_merge); } @@ -69353,14 +69113,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2849; - x86::Gp ret_val_illegal_normal_2849 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2849, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2849; - setArg(call_illegal_normal_2849, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2849, 1, vd); - setArg(call_illegal_normal_2849, 2, vm); - setRet(call_illegal_normal_2849, 0, ret_val_illegal_normal_2849); + InvokeNode* call_illegal_normal_2857; + x86::Gp ret_val_illegal_normal_2857 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2857, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2857; + setArg(call_illegal_normal_2857, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2857, 1, vd); + setArg(call_illegal_normal_2857, 2, vm); + setRet(call_illegal_normal_2857, 0, ret_val_illegal_normal_2857); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69376,44 +69136,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2851; - x86::Gp ret_val_sew_2851 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2851, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2850; - auto sat_vector_vector_op_2850_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2850_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2850_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2850_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2850_arg11 = ret_val_sew_2851; + InvokeNode* call_sew_2859; + x86::Gp ret_val_sew_2859 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2859, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2858; + auto sat_vector_vector_op_2858_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2858_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2858_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2858_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2858_arg11 = ret_val_sew_2859; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2850 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2850, &sat_vector_vector_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_op_2850, 64, false) - , traits::vxsat); - setArg(call_sew_2851, 0, reinterpret_cast(this)); - setRet(call_sew_2851, 0, ret_val_sew_2851); - setArg(call_sat_vector_vector_op_2850, 0, V); - setArg(call_sat_vector_vector_op_2850, 1, 35); - setArg(call_sat_vector_vector_op_2850, 2, 0); - setArg(call_sat_vector_vector_op_2850, 3, sat_vector_vector_op_2850_arg3); - setArg(call_sat_vector_vector_op_2850, 4, sat_vector_vector_op_2850_arg4); - setArg(call_sat_vector_vector_op_2850, 5, sat_vector_vector_op_2850_arg5); - setArg(call_sat_vector_vector_op_2850, 6, sat_vector_vector_op_2850_arg6); - setArg(call_sat_vector_vector_op_2850, 7, vm); - setArg(call_sat_vector_vector_op_2850, 8, vd); - setArg(call_sat_vector_vector_op_2850, 9, vs2); - setArg(call_sat_vector_vector_op_2850, 10, vs1); - setArg(call_sat_vector_vector_op_2850, 11, sat_vector_vector_op_2850_arg11); - setRet(call_sat_vector_vector_op_2850, 0, ret_val_sat_vector_vector_op_2850); + x86::Gp ret_val_sat_vector_vector_op_2858 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2858, &sat_vector_vector_op, FuncSignature::build()); + auto tmp2860 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_op_2858, 64, false)); + write_reg_to_mem(jh, tmp2860, traits::vxsat); + setArg(call_sew_2859, 0, reinterpret_cast(this)); + setRet(call_sew_2859, 0, ret_val_sew_2859); + setArg(call_sat_vector_vector_op_2858, 0, V); + setArg(call_sat_vector_vector_op_2858, 1, 35); + setArg(call_sat_vector_vector_op_2858, 2, 0); + setArg(call_sat_vector_vector_op_2858, 3, sat_vector_vector_op_2858_arg3); + setArg(call_sat_vector_vector_op_2858, 4, sat_vector_vector_op_2858_arg4); + setArg(call_sat_vector_vector_op_2858, 5, sat_vector_vector_op_2858_arg5); + setArg(call_sat_vector_vector_op_2858, 6, sat_vector_vector_op_2858_arg6); + setArg(call_sat_vector_vector_op_2858, 7, vm); + setArg(call_sat_vector_vector_op_2858, 8, vd); + setArg(call_sat_vector_vector_op_2858, 9, vs2); + setArg(call_sat_vector_vector_op_2858, 10, vs1); + setArg(call_sat_vector_vector_op_2858, 11, sat_vector_vector_op_2858_arg11); + setRet(call_sat_vector_vector_op_2858, 0, ret_val_sat_vector_vector_op_2858); } cc.bind(label_merge); } - auto tmp2852 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2852, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2852, 64, false) - , traits::vstart); + auto tmp2861 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2861, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2861, traits::vstart); } cc.bind(label_merge); } @@ -69459,16 +69216,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2853; - x86::Gp ret_val_illegal_normal_2853 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2853, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2854 = get_reg(cc, 8, false); - mov(cc, tmp2854, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2854, ret_val_illegal_normal_2853); - setArg(call_illegal_normal_2853, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2853, 1, vd); - setArg(call_illegal_normal_2853, 2, vm); - setRet(call_illegal_normal_2853, 0, ret_val_illegal_normal_2853); + InvokeNode* call_illegal_normal_2862; + x86::Gp ret_val_illegal_normal_2862 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2862, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2863 = get_reg(cc, 8, false); + mov(cc, tmp2863, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2863, ret_val_illegal_normal_2862); + setArg(call_illegal_normal_2862, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2862, 1, vd); + setArg(call_illegal_normal_2862, 2, vm); + setRet(call_illegal_normal_2862, 0, ret_val_illegal_normal_2862); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69484,47 +69241,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2856; - x86::Gp ret_val_sew_2856 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2856, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2855; - auto sat_vector_imm_op_2855_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2855_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2855_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2855_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2855_arg10 = gen_ext(cc, + InvokeNode* call_sew_2865; + x86::Gp ret_val_sew_2865 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2865, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2864; + auto sat_vector_imm_op_2864_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2864_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2864_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2864_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2864_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); - auto sat_vector_imm_op_2855_arg11 = ret_val_sew_2856; + auto sat_vector_imm_op_2864_arg11 = ret_val_sew_2865; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2855 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2855, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2855, 64, false) - , traits::vxsat); - setArg(call_sew_2856, 0, reinterpret_cast(this)); - setRet(call_sew_2856, 0, ret_val_sew_2856); - setArg(call_sat_vector_imm_op_2855, 0, V); - setArg(call_sat_vector_imm_op_2855, 1, 35); - setArg(call_sat_vector_imm_op_2855, 2, 4); - setArg(call_sat_vector_imm_op_2855, 3, sat_vector_imm_op_2855_arg3); - setArg(call_sat_vector_imm_op_2855, 4, sat_vector_imm_op_2855_arg4); - setArg(call_sat_vector_imm_op_2855, 5, sat_vector_imm_op_2855_arg5); - setArg(call_sat_vector_imm_op_2855, 6, sat_vector_imm_op_2855_arg6); - setArg(call_sat_vector_imm_op_2855, 7, vm); - setArg(call_sat_vector_imm_op_2855, 8, vd); - setArg(call_sat_vector_imm_op_2855, 9, vs2); - setArg(call_sat_vector_imm_op_2855, 10, sat_vector_imm_op_2855_arg10); - setArg(call_sat_vector_imm_op_2855, 11, sat_vector_imm_op_2855_arg11); - setRet(call_sat_vector_imm_op_2855, 0, ret_val_sat_vector_imm_op_2855); + x86::Gp ret_val_sat_vector_imm_op_2864 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2864, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2866 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2864, 64, false)); + write_reg_to_mem(jh, tmp2866, traits::vxsat); + setArg(call_sew_2865, 0, reinterpret_cast(this)); + setRet(call_sew_2865, 0, ret_val_sew_2865); + setArg(call_sat_vector_imm_op_2864, 0, V); + setArg(call_sat_vector_imm_op_2864, 1, 35); + setArg(call_sat_vector_imm_op_2864, 2, 4); + setArg(call_sat_vector_imm_op_2864, 3, sat_vector_imm_op_2864_arg3); + setArg(call_sat_vector_imm_op_2864, 4, sat_vector_imm_op_2864_arg4); + setArg(call_sat_vector_imm_op_2864, 5, sat_vector_imm_op_2864_arg5); + setArg(call_sat_vector_imm_op_2864, 6, sat_vector_imm_op_2864_arg6); + setArg(call_sat_vector_imm_op_2864, 7, vm); + setArg(call_sat_vector_imm_op_2864, 8, vd); + setArg(call_sat_vector_imm_op_2864, 9, vs2); + setArg(call_sat_vector_imm_op_2864, 10, sat_vector_imm_op_2864_arg10); + setArg(call_sat_vector_imm_op_2864, 11, sat_vector_imm_op_2864_arg11); + setRet(call_sat_vector_imm_op_2864, 0, ret_val_sat_vector_imm_op_2864); } cc.bind(label_merge); } - auto tmp2857 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2857, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2857, 64, false) - , traits::vstart); + auto tmp2867 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2867, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2867, traits::vstart); } cc.bind(label_merge); } @@ -69570,14 +69324,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2858; - x86::Gp ret_val_illegal_normal_2858 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2858, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2858; - setArg(call_illegal_normal_2858, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2858, 1, vd); - setArg(call_illegal_normal_2858, 2, vm); - setRet(call_illegal_normal_2858, 0, ret_val_illegal_normal_2858); + InvokeNode* call_illegal_normal_2868; + x86::Gp ret_val_illegal_normal_2868 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2868, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2868; + setArg(call_illegal_normal_2868, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2868, 1, vd); + setArg(call_illegal_normal_2868, 2, vm); + setRet(call_illegal_normal_2868, 0, ret_val_illegal_normal_2868); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69593,42 +69347,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2860; - x86::Gp ret_val_sew_2860 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2860, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2859; - auto sat_vector_vector_op_2859_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2859_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2859_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2859_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2859_arg11 = ret_val_sew_2860; + InvokeNode* call_sew_2870; + x86::Gp ret_val_sew_2870 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2870, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2869; + auto sat_vector_vector_op_2869_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2869_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2869_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2869_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2869_arg11 = ret_val_sew_2870; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2859 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2859, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2859; - setArg(call_sew_2860, 0, reinterpret_cast(this)); - setRet(call_sew_2860, 0, ret_val_sew_2860); - setArg(call_sat_vector_vector_op_2859, 0, V); - setArg(call_sat_vector_vector_op_2859, 1, 8); - setArg(call_sat_vector_vector_op_2859, 2, 2); - setArg(call_sat_vector_vector_op_2859, 3, sat_vector_vector_op_2859_arg3); - setArg(call_sat_vector_vector_op_2859, 4, sat_vector_vector_op_2859_arg4); - setArg(call_sat_vector_vector_op_2859, 5, sat_vector_vector_op_2859_arg5); - setArg(call_sat_vector_vector_op_2859, 6, sat_vector_vector_op_2859_arg6); - setArg(call_sat_vector_vector_op_2859, 7, vm); - setArg(call_sat_vector_vector_op_2859, 8, vd); - setArg(call_sat_vector_vector_op_2859, 9, vs2); - setArg(call_sat_vector_vector_op_2859, 10, vs1); - setArg(call_sat_vector_vector_op_2859, 11, sat_vector_vector_op_2859_arg11); - setRet(call_sat_vector_vector_op_2859, 0, ret_val_sat_vector_vector_op_2859); + x86::Gp ret_val_sat_vector_vector_op_2869 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2869, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2869; + setArg(call_sew_2870, 0, reinterpret_cast(this)); + setRet(call_sew_2870, 0, ret_val_sew_2870); + setArg(call_sat_vector_vector_op_2869, 0, V); + setArg(call_sat_vector_vector_op_2869, 1, 8); + setArg(call_sat_vector_vector_op_2869, 2, 2); + setArg(call_sat_vector_vector_op_2869, 3, sat_vector_vector_op_2869_arg3); + setArg(call_sat_vector_vector_op_2869, 4, sat_vector_vector_op_2869_arg4); + setArg(call_sat_vector_vector_op_2869, 5, sat_vector_vector_op_2869_arg5); + setArg(call_sat_vector_vector_op_2869, 6, sat_vector_vector_op_2869_arg6); + setArg(call_sat_vector_vector_op_2869, 7, vm); + setArg(call_sat_vector_vector_op_2869, 8, vd); + setArg(call_sat_vector_vector_op_2869, 9, vs2); + setArg(call_sat_vector_vector_op_2869, 10, vs1); + setArg(call_sat_vector_vector_op_2869, 11, sat_vector_vector_op_2869_arg11); + setRet(call_sat_vector_vector_op_2869, 0, ret_val_sat_vector_vector_op_2869); } cc.bind(label_merge); } - auto tmp2861 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2861, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2861, 64, false) - , traits::vstart); + auto tmp2871 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2871, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2871, traits::vstart); } cc.bind(label_merge); } @@ -69674,16 +69426,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2862; - x86::Gp ret_val_illegal_normal_2862 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2862, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2863 = get_reg(cc, 8, false); - mov(cc, tmp2863, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2863, ret_val_illegal_normal_2862); - setArg(call_illegal_normal_2862, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2862, 1, vd); - setArg(call_illegal_normal_2862, 2, vm); - setRet(call_illegal_normal_2862, 0, ret_val_illegal_normal_2862); + InvokeNode* call_illegal_normal_2872; + x86::Gp ret_val_illegal_normal_2872 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2872, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2873 = get_reg(cc, 8, false); + mov(cc, tmp2873, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2873, ret_val_illegal_normal_2872); + setArg(call_illegal_normal_2872, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2872, 1, vd); + setArg(call_illegal_normal_2872, 2, vm); + setRet(call_illegal_normal_2872, 0, ret_val_illegal_normal_2872); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69699,45 +69451,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2865; - x86::Gp ret_val_sew_2865 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2865, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2864; - auto sat_vector_imm_op_2864_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2864_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2864_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2864_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2864_arg10 = gen_ext(cc, + InvokeNode* call_sew_2875; + x86::Gp ret_val_sew_2875 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2875, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2874; + auto sat_vector_imm_op_2874_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2874_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2874_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2874_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2874_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); - auto sat_vector_imm_op_2864_arg11 = ret_val_sew_2865; + auto sat_vector_imm_op_2874_arg11 = ret_val_sew_2875; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2864 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2864, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2864; - setArg(call_sew_2865, 0, reinterpret_cast(this)); - setRet(call_sew_2865, 0, ret_val_sew_2865); - setArg(call_sat_vector_imm_op_2864, 0, V); - setArg(call_sat_vector_imm_op_2864, 1, 8); - setArg(call_sat_vector_imm_op_2864, 2, 6); - setArg(call_sat_vector_imm_op_2864, 3, sat_vector_imm_op_2864_arg3); - setArg(call_sat_vector_imm_op_2864, 4, sat_vector_imm_op_2864_arg4); - setArg(call_sat_vector_imm_op_2864, 5, sat_vector_imm_op_2864_arg5); - setArg(call_sat_vector_imm_op_2864, 6, sat_vector_imm_op_2864_arg6); - setArg(call_sat_vector_imm_op_2864, 7, vm); - setArg(call_sat_vector_imm_op_2864, 8, vd); - setArg(call_sat_vector_imm_op_2864, 9, vs2); - setArg(call_sat_vector_imm_op_2864, 10, sat_vector_imm_op_2864_arg10); - setArg(call_sat_vector_imm_op_2864, 11, sat_vector_imm_op_2864_arg11); - setRet(call_sat_vector_imm_op_2864, 0, ret_val_sat_vector_imm_op_2864); + x86::Gp ret_val_sat_vector_imm_op_2874 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2874, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2874; + setArg(call_sew_2875, 0, reinterpret_cast(this)); + setRet(call_sew_2875, 0, ret_val_sew_2875); + setArg(call_sat_vector_imm_op_2874, 0, V); + setArg(call_sat_vector_imm_op_2874, 1, 8); + setArg(call_sat_vector_imm_op_2874, 2, 6); + setArg(call_sat_vector_imm_op_2874, 3, sat_vector_imm_op_2874_arg3); + setArg(call_sat_vector_imm_op_2874, 4, sat_vector_imm_op_2874_arg4); + setArg(call_sat_vector_imm_op_2874, 5, sat_vector_imm_op_2874_arg5); + setArg(call_sat_vector_imm_op_2874, 6, sat_vector_imm_op_2874_arg6); + setArg(call_sat_vector_imm_op_2874, 7, vm); + setArg(call_sat_vector_imm_op_2874, 8, vd); + setArg(call_sat_vector_imm_op_2874, 9, vs2); + setArg(call_sat_vector_imm_op_2874, 10, sat_vector_imm_op_2874_arg10); + setArg(call_sat_vector_imm_op_2874, 11, sat_vector_imm_op_2874_arg11); + setRet(call_sat_vector_imm_op_2874, 0, ret_val_sat_vector_imm_op_2874); } cc.bind(label_merge); } - auto tmp2866 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2866, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2866, 64, false) - , traits::vstart); + auto tmp2876 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2876, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2876, traits::vstart); } cc.bind(label_merge); } @@ -69783,14 +69533,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2867; - x86::Gp ret_val_illegal_normal_2867 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2867, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2867; - setArg(call_illegal_normal_2867, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2867, 1, vd); - setArg(call_illegal_normal_2867, 2, vm); - setRet(call_illegal_normal_2867, 0, ret_val_illegal_normal_2867); + InvokeNode* call_illegal_normal_2877; + x86::Gp ret_val_illegal_normal_2877 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2877, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2877; + setArg(call_illegal_normal_2877, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2877, 1, vd); + setArg(call_illegal_normal_2877, 2, vm); + setRet(call_illegal_normal_2877, 0, ret_val_illegal_normal_2877); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69806,42 +69556,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2869; - x86::Gp ret_val_sew_2869 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2869, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2868; - auto sat_vector_vector_op_2868_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2868_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2868_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2868_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2868_arg11 = ret_val_sew_2869; + InvokeNode* call_sew_2879; + x86::Gp ret_val_sew_2879 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2879, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2878; + auto sat_vector_vector_op_2878_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2878_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2878_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2878_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2878_arg11 = ret_val_sew_2879; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2868 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2868, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2868; - setArg(call_sew_2869, 0, reinterpret_cast(this)); - setRet(call_sew_2869, 0, ret_val_sew_2869); - setArg(call_sat_vector_vector_op_2868, 0, V); - setArg(call_sat_vector_vector_op_2868, 1, 9); - setArg(call_sat_vector_vector_op_2868, 2, 2); - setArg(call_sat_vector_vector_op_2868, 3, sat_vector_vector_op_2868_arg3); - setArg(call_sat_vector_vector_op_2868, 4, sat_vector_vector_op_2868_arg4); - setArg(call_sat_vector_vector_op_2868, 5, sat_vector_vector_op_2868_arg5); - setArg(call_sat_vector_vector_op_2868, 6, sat_vector_vector_op_2868_arg6); - setArg(call_sat_vector_vector_op_2868, 7, vm); - setArg(call_sat_vector_vector_op_2868, 8, vd); - setArg(call_sat_vector_vector_op_2868, 9, vs2); - setArg(call_sat_vector_vector_op_2868, 10, vs1); - setArg(call_sat_vector_vector_op_2868, 11, sat_vector_vector_op_2868_arg11); - setRet(call_sat_vector_vector_op_2868, 0, ret_val_sat_vector_vector_op_2868); + x86::Gp ret_val_sat_vector_vector_op_2878 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2878, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2878; + setArg(call_sew_2879, 0, reinterpret_cast(this)); + setRet(call_sew_2879, 0, ret_val_sew_2879); + setArg(call_sat_vector_vector_op_2878, 0, V); + setArg(call_sat_vector_vector_op_2878, 1, 9); + setArg(call_sat_vector_vector_op_2878, 2, 2); + setArg(call_sat_vector_vector_op_2878, 3, sat_vector_vector_op_2878_arg3); + setArg(call_sat_vector_vector_op_2878, 4, sat_vector_vector_op_2878_arg4); + setArg(call_sat_vector_vector_op_2878, 5, sat_vector_vector_op_2878_arg5); + setArg(call_sat_vector_vector_op_2878, 6, sat_vector_vector_op_2878_arg6); + setArg(call_sat_vector_vector_op_2878, 7, vm); + setArg(call_sat_vector_vector_op_2878, 8, vd); + setArg(call_sat_vector_vector_op_2878, 9, vs2); + setArg(call_sat_vector_vector_op_2878, 10, vs1); + setArg(call_sat_vector_vector_op_2878, 11, sat_vector_vector_op_2878_arg11); + setRet(call_sat_vector_vector_op_2878, 0, ret_val_sat_vector_vector_op_2878); } cc.bind(label_merge); } - auto tmp2870 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2870, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2870, 64, false) - , traits::vstart); + auto tmp2880 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2880, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2880, traits::vstart); } cc.bind(label_merge); } @@ -69887,16 +69635,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2871; - x86::Gp ret_val_illegal_normal_2871 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2871, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2872 = get_reg(cc, 8, false); - mov(cc, tmp2872, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2872, ret_val_illegal_normal_2871); - setArg(call_illegal_normal_2871, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2871, 1, vd); - setArg(call_illegal_normal_2871, 2, vm); - setRet(call_illegal_normal_2871, 0, ret_val_illegal_normal_2871); + InvokeNode* call_illegal_normal_2881; + x86::Gp ret_val_illegal_normal_2881 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2881, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2882 = get_reg(cc, 8, false); + mov(cc, tmp2882, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2882, ret_val_illegal_normal_2881); + setArg(call_illegal_normal_2881, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2881, 1, vd); + setArg(call_illegal_normal_2881, 2, vm); + setRet(call_illegal_normal_2881, 0, ret_val_illegal_normal_2881); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -69912,45 +69660,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2874; - x86::Gp ret_val_sew_2874 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2874, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2873; - auto sat_vector_imm_op_2873_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2873_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2873_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2873_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2873_arg10 = gen_ext(cc, + InvokeNode* call_sew_2884; + x86::Gp ret_val_sew_2884 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2884, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2883; + auto sat_vector_imm_op_2883_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2883_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2883_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2883_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2883_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); - auto sat_vector_imm_op_2873_arg11 = ret_val_sew_2874; + auto sat_vector_imm_op_2883_arg11 = ret_val_sew_2884; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2873 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2873, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2873; - setArg(call_sew_2874, 0, reinterpret_cast(this)); - setRet(call_sew_2874, 0, ret_val_sew_2874); - setArg(call_sat_vector_imm_op_2873, 0, V); - setArg(call_sat_vector_imm_op_2873, 1, 9); - setArg(call_sat_vector_imm_op_2873, 2, 6); - setArg(call_sat_vector_imm_op_2873, 3, sat_vector_imm_op_2873_arg3); - setArg(call_sat_vector_imm_op_2873, 4, sat_vector_imm_op_2873_arg4); - setArg(call_sat_vector_imm_op_2873, 5, sat_vector_imm_op_2873_arg5); - setArg(call_sat_vector_imm_op_2873, 6, sat_vector_imm_op_2873_arg6); - setArg(call_sat_vector_imm_op_2873, 7, vm); - setArg(call_sat_vector_imm_op_2873, 8, vd); - setArg(call_sat_vector_imm_op_2873, 9, vs2); - setArg(call_sat_vector_imm_op_2873, 10, sat_vector_imm_op_2873_arg10); - setArg(call_sat_vector_imm_op_2873, 11, sat_vector_imm_op_2873_arg11); - setRet(call_sat_vector_imm_op_2873, 0, ret_val_sat_vector_imm_op_2873); + x86::Gp ret_val_sat_vector_imm_op_2883 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2883, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2883; + setArg(call_sew_2884, 0, reinterpret_cast(this)); + setRet(call_sew_2884, 0, ret_val_sew_2884); + setArg(call_sat_vector_imm_op_2883, 0, V); + setArg(call_sat_vector_imm_op_2883, 1, 9); + setArg(call_sat_vector_imm_op_2883, 2, 6); + setArg(call_sat_vector_imm_op_2883, 3, sat_vector_imm_op_2883_arg3); + setArg(call_sat_vector_imm_op_2883, 4, sat_vector_imm_op_2883_arg4); + setArg(call_sat_vector_imm_op_2883, 5, sat_vector_imm_op_2883_arg5); + setArg(call_sat_vector_imm_op_2883, 6, sat_vector_imm_op_2883_arg6); + setArg(call_sat_vector_imm_op_2883, 7, vm); + setArg(call_sat_vector_imm_op_2883, 8, vd); + setArg(call_sat_vector_imm_op_2883, 9, vs2); + setArg(call_sat_vector_imm_op_2883, 10, sat_vector_imm_op_2883_arg10); + setArg(call_sat_vector_imm_op_2883, 11, sat_vector_imm_op_2883_arg11); + setRet(call_sat_vector_imm_op_2883, 0, ret_val_sat_vector_imm_op_2883); } cc.bind(label_merge); } - auto tmp2875 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2875, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2875, 64, false) - , traits::vstart); + auto tmp2885 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2885, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2885, traits::vstart); } cc.bind(label_merge); } @@ -69996,14 +69742,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2876; - x86::Gp ret_val_illegal_normal_2876 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2876, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2876; - setArg(call_illegal_normal_2876, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2876, 1, vd); - setArg(call_illegal_normal_2876, 2, vm); - setRet(call_illegal_normal_2876, 0, ret_val_illegal_normal_2876); + InvokeNode* call_illegal_normal_2886; + x86::Gp ret_val_illegal_normal_2886 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2886, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2886; + setArg(call_illegal_normal_2886, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2886, 1, vd); + setArg(call_illegal_normal_2886, 2, vm); + setRet(call_illegal_normal_2886, 0, ret_val_illegal_normal_2886); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70019,42 +69765,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2878; - x86::Gp ret_val_sew_2878 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2878, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2877; - auto sat_vector_vector_op_2877_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2877_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2877_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2877_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2877_arg11 = ret_val_sew_2878; + InvokeNode* call_sew_2888; + x86::Gp ret_val_sew_2888 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2888, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2887; + auto sat_vector_vector_op_2887_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2887_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2887_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2887_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2887_arg11 = ret_val_sew_2888; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2877 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2877, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2877; - setArg(call_sew_2878, 0, reinterpret_cast(this)); - setRet(call_sew_2878, 0, ret_val_sew_2878); - setArg(call_sat_vector_vector_op_2877, 0, V); - setArg(call_sat_vector_vector_op_2877, 1, 10); - setArg(call_sat_vector_vector_op_2877, 2, 2); - setArg(call_sat_vector_vector_op_2877, 3, sat_vector_vector_op_2877_arg3); - setArg(call_sat_vector_vector_op_2877, 4, sat_vector_vector_op_2877_arg4); - setArg(call_sat_vector_vector_op_2877, 5, sat_vector_vector_op_2877_arg5); - setArg(call_sat_vector_vector_op_2877, 6, sat_vector_vector_op_2877_arg6); - setArg(call_sat_vector_vector_op_2877, 7, vm); - setArg(call_sat_vector_vector_op_2877, 8, vd); - setArg(call_sat_vector_vector_op_2877, 9, vs2); - setArg(call_sat_vector_vector_op_2877, 10, vs1); - setArg(call_sat_vector_vector_op_2877, 11, sat_vector_vector_op_2877_arg11); - setRet(call_sat_vector_vector_op_2877, 0, ret_val_sat_vector_vector_op_2877); + x86::Gp ret_val_sat_vector_vector_op_2887 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2887, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2887; + setArg(call_sew_2888, 0, reinterpret_cast(this)); + setRet(call_sew_2888, 0, ret_val_sew_2888); + setArg(call_sat_vector_vector_op_2887, 0, V); + setArg(call_sat_vector_vector_op_2887, 1, 10); + setArg(call_sat_vector_vector_op_2887, 2, 2); + setArg(call_sat_vector_vector_op_2887, 3, sat_vector_vector_op_2887_arg3); + setArg(call_sat_vector_vector_op_2887, 4, sat_vector_vector_op_2887_arg4); + setArg(call_sat_vector_vector_op_2887, 5, sat_vector_vector_op_2887_arg5); + setArg(call_sat_vector_vector_op_2887, 6, sat_vector_vector_op_2887_arg6); + setArg(call_sat_vector_vector_op_2887, 7, vm); + setArg(call_sat_vector_vector_op_2887, 8, vd); + setArg(call_sat_vector_vector_op_2887, 9, vs2); + setArg(call_sat_vector_vector_op_2887, 10, vs1); + setArg(call_sat_vector_vector_op_2887, 11, sat_vector_vector_op_2887_arg11); + setRet(call_sat_vector_vector_op_2887, 0, ret_val_sat_vector_vector_op_2887); } cc.bind(label_merge); } - auto tmp2879 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2879, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2879, 64, false) - , traits::vstart); + auto tmp2889 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2889, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2889, traits::vstart); } cc.bind(label_merge); } @@ -70100,16 +69844,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2880; - x86::Gp ret_val_illegal_normal_2880 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2880, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2881 = get_reg(cc, 8, false); - mov(cc, tmp2881, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2881, ret_val_illegal_normal_2880); - setArg(call_illegal_normal_2880, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2880, 1, vd); - setArg(call_illegal_normal_2880, 2, vm); - setRet(call_illegal_normal_2880, 0, ret_val_illegal_normal_2880); + InvokeNode* call_illegal_normal_2890; + x86::Gp ret_val_illegal_normal_2890 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2890, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2891 = get_reg(cc, 8, false); + mov(cc, tmp2891, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2891, ret_val_illegal_normal_2890); + setArg(call_illegal_normal_2890, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2890, 1, vd); + setArg(call_illegal_normal_2890, 2, vm); + setRet(call_illegal_normal_2890, 0, ret_val_illegal_normal_2890); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70125,45 +69869,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2883; - x86::Gp ret_val_sew_2883 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2883, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2882; - auto sat_vector_imm_op_2882_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2882_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2882_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2882_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2882_arg10 = gen_ext(cc, + InvokeNode* call_sew_2893; + x86::Gp ret_val_sew_2893 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2893, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2892; + auto sat_vector_imm_op_2892_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2892_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2892_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2892_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2892_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); - auto sat_vector_imm_op_2882_arg11 = ret_val_sew_2883; + auto sat_vector_imm_op_2892_arg11 = ret_val_sew_2893; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2882 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2882, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2882; - setArg(call_sew_2883, 0, reinterpret_cast(this)); - setRet(call_sew_2883, 0, ret_val_sew_2883); - setArg(call_sat_vector_imm_op_2882, 0, V); - setArg(call_sat_vector_imm_op_2882, 1, 10); - setArg(call_sat_vector_imm_op_2882, 2, 6); - setArg(call_sat_vector_imm_op_2882, 3, sat_vector_imm_op_2882_arg3); - setArg(call_sat_vector_imm_op_2882, 4, sat_vector_imm_op_2882_arg4); - setArg(call_sat_vector_imm_op_2882, 5, sat_vector_imm_op_2882_arg5); - setArg(call_sat_vector_imm_op_2882, 6, sat_vector_imm_op_2882_arg6); - setArg(call_sat_vector_imm_op_2882, 7, vm); - setArg(call_sat_vector_imm_op_2882, 8, vd); - setArg(call_sat_vector_imm_op_2882, 9, vs2); - setArg(call_sat_vector_imm_op_2882, 10, sat_vector_imm_op_2882_arg10); - setArg(call_sat_vector_imm_op_2882, 11, sat_vector_imm_op_2882_arg11); - setRet(call_sat_vector_imm_op_2882, 0, ret_val_sat_vector_imm_op_2882); + x86::Gp ret_val_sat_vector_imm_op_2892 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2892, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2892; + setArg(call_sew_2893, 0, reinterpret_cast(this)); + setRet(call_sew_2893, 0, ret_val_sew_2893); + setArg(call_sat_vector_imm_op_2892, 0, V); + setArg(call_sat_vector_imm_op_2892, 1, 10); + setArg(call_sat_vector_imm_op_2892, 2, 6); + setArg(call_sat_vector_imm_op_2892, 3, sat_vector_imm_op_2892_arg3); + setArg(call_sat_vector_imm_op_2892, 4, sat_vector_imm_op_2892_arg4); + setArg(call_sat_vector_imm_op_2892, 5, sat_vector_imm_op_2892_arg5); + setArg(call_sat_vector_imm_op_2892, 6, sat_vector_imm_op_2892_arg6); + setArg(call_sat_vector_imm_op_2892, 7, vm); + setArg(call_sat_vector_imm_op_2892, 8, vd); + setArg(call_sat_vector_imm_op_2892, 9, vs2); + setArg(call_sat_vector_imm_op_2892, 10, sat_vector_imm_op_2892_arg10); + setArg(call_sat_vector_imm_op_2892, 11, sat_vector_imm_op_2892_arg11); + setRet(call_sat_vector_imm_op_2892, 0, ret_val_sat_vector_imm_op_2892); } cc.bind(label_merge); } - auto tmp2884 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2884, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2884, 64, false) - , traits::vstart); + auto tmp2894 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2894, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2894, traits::vstart); } cc.bind(label_merge); } @@ -70209,14 +69951,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2885; - x86::Gp ret_val_illegal_normal_2885 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2885, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2885; - setArg(call_illegal_normal_2885, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2885, 1, vd); - setArg(call_illegal_normal_2885, 2, vm); - setRet(call_illegal_normal_2885, 0, ret_val_illegal_normal_2885); + InvokeNode* call_illegal_normal_2895; + x86::Gp ret_val_illegal_normal_2895 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2895, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2895; + setArg(call_illegal_normal_2895, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2895, 1, vd); + setArg(call_illegal_normal_2895, 2, vm); + setRet(call_illegal_normal_2895, 0, ret_val_illegal_normal_2895); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70232,42 +69974,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2887; - x86::Gp ret_val_sew_2887 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2887, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2886; - auto sat_vector_vector_op_2886_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2886_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2886_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2886_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2886_arg11 = ret_val_sew_2887; + InvokeNode* call_sew_2897; + x86::Gp ret_val_sew_2897 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2897, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2896; + auto sat_vector_vector_op_2896_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2896_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2896_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2896_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2896_arg11 = ret_val_sew_2897; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2886 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2886, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2886; - setArg(call_sew_2887, 0, reinterpret_cast(this)); - setRet(call_sew_2887, 0, ret_val_sew_2887); - setArg(call_sat_vector_vector_op_2886, 0, V); - setArg(call_sat_vector_vector_op_2886, 1, 11); - setArg(call_sat_vector_vector_op_2886, 2, 2); - setArg(call_sat_vector_vector_op_2886, 3, sat_vector_vector_op_2886_arg3); - setArg(call_sat_vector_vector_op_2886, 4, sat_vector_vector_op_2886_arg4); - setArg(call_sat_vector_vector_op_2886, 5, sat_vector_vector_op_2886_arg5); - setArg(call_sat_vector_vector_op_2886, 6, sat_vector_vector_op_2886_arg6); - setArg(call_sat_vector_vector_op_2886, 7, vm); - setArg(call_sat_vector_vector_op_2886, 8, vd); - setArg(call_sat_vector_vector_op_2886, 9, vs2); - setArg(call_sat_vector_vector_op_2886, 10, vs1); - setArg(call_sat_vector_vector_op_2886, 11, sat_vector_vector_op_2886_arg11); - setRet(call_sat_vector_vector_op_2886, 0, ret_val_sat_vector_vector_op_2886); + x86::Gp ret_val_sat_vector_vector_op_2896 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2896, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2896; + setArg(call_sew_2897, 0, reinterpret_cast(this)); + setRet(call_sew_2897, 0, ret_val_sew_2897); + setArg(call_sat_vector_vector_op_2896, 0, V); + setArg(call_sat_vector_vector_op_2896, 1, 11); + setArg(call_sat_vector_vector_op_2896, 2, 2); + setArg(call_sat_vector_vector_op_2896, 3, sat_vector_vector_op_2896_arg3); + setArg(call_sat_vector_vector_op_2896, 4, sat_vector_vector_op_2896_arg4); + setArg(call_sat_vector_vector_op_2896, 5, sat_vector_vector_op_2896_arg5); + setArg(call_sat_vector_vector_op_2896, 6, sat_vector_vector_op_2896_arg6); + setArg(call_sat_vector_vector_op_2896, 7, vm); + setArg(call_sat_vector_vector_op_2896, 8, vd); + setArg(call_sat_vector_vector_op_2896, 9, vs2); + setArg(call_sat_vector_vector_op_2896, 10, vs1); + setArg(call_sat_vector_vector_op_2896, 11, sat_vector_vector_op_2896_arg11); + setRet(call_sat_vector_vector_op_2896, 0, ret_val_sat_vector_vector_op_2896); } cc.bind(label_merge); } - auto tmp2888 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2888, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2888, 64, false) - , traits::vstart); + auto tmp2898 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2898, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2898, traits::vstart); } cc.bind(label_merge); } @@ -70313,16 +70053,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2889; - x86::Gp ret_val_illegal_normal_2889 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2889, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2890 = get_reg(cc, 8, false); - mov(cc, tmp2890, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2890, ret_val_illegal_normal_2889); - setArg(call_illegal_normal_2889, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2889, 1, vd); - setArg(call_illegal_normal_2889, 2, vm); - setRet(call_illegal_normal_2889, 0, ret_val_illegal_normal_2889); + InvokeNode* call_illegal_normal_2899; + x86::Gp ret_val_illegal_normal_2899 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2899, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2900 = get_reg(cc, 8, false); + mov(cc, tmp2900, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2900, ret_val_illegal_normal_2899); + setArg(call_illegal_normal_2899, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2899, 1, vd); + setArg(call_illegal_normal_2899, 2, vm); + setRet(call_illegal_normal_2899, 0, ret_val_illegal_normal_2899); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70338,45 +70078,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2892; - x86::Gp ret_val_sew_2892 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2892, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2891; - auto sat_vector_imm_op_2891_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2891_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2891_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2891_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2891_arg10 = gen_ext(cc, + InvokeNode* call_sew_2902; + x86::Gp ret_val_sew_2902 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2902, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2901; + auto sat_vector_imm_op_2901_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2901_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2901_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2901_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2901_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); - auto sat_vector_imm_op_2891_arg11 = ret_val_sew_2892; + auto sat_vector_imm_op_2901_arg11 = ret_val_sew_2902; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2891 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2891, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2891; - setArg(call_sew_2892, 0, reinterpret_cast(this)); - setRet(call_sew_2892, 0, ret_val_sew_2892); - setArg(call_sat_vector_imm_op_2891, 0, V); - setArg(call_sat_vector_imm_op_2891, 1, 11); - setArg(call_sat_vector_imm_op_2891, 2, 6); - setArg(call_sat_vector_imm_op_2891, 3, sat_vector_imm_op_2891_arg3); - setArg(call_sat_vector_imm_op_2891, 4, sat_vector_imm_op_2891_arg4); - setArg(call_sat_vector_imm_op_2891, 5, sat_vector_imm_op_2891_arg5); - setArg(call_sat_vector_imm_op_2891, 6, sat_vector_imm_op_2891_arg6); - setArg(call_sat_vector_imm_op_2891, 7, vm); - setArg(call_sat_vector_imm_op_2891, 8, vd); - setArg(call_sat_vector_imm_op_2891, 9, vs2); - setArg(call_sat_vector_imm_op_2891, 10, sat_vector_imm_op_2891_arg10); - setArg(call_sat_vector_imm_op_2891, 11, sat_vector_imm_op_2891_arg11); - setRet(call_sat_vector_imm_op_2891, 0, ret_val_sat_vector_imm_op_2891); + x86::Gp ret_val_sat_vector_imm_op_2901 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2901, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2901; + setArg(call_sew_2902, 0, reinterpret_cast(this)); + setRet(call_sew_2902, 0, ret_val_sew_2902); + setArg(call_sat_vector_imm_op_2901, 0, V); + setArg(call_sat_vector_imm_op_2901, 1, 11); + setArg(call_sat_vector_imm_op_2901, 2, 6); + setArg(call_sat_vector_imm_op_2901, 3, sat_vector_imm_op_2901_arg3); + setArg(call_sat_vector_imm_op_2901, 4, sat_vector_imm_op_2901_arg4); + setArg(call_sat_vector_imm_op_2901, 5, sat_vector_imm_op_2901_arg5); + setArg(call_sat_vector_imm_op_2901, 6, sat_vector_imm_op_2901_arg6); + setArg(call_sat_vector_imm_op_2901, 7, vm); + setArg(call_sat_vector_imm_op_2901, 8, vd); + setArg(call_sat_vector_imm_op_2901, 9, vs2); + setArg(call_sat_vector_imm_op_2901, 10, sat_vector_imm_op_2901_arg10); + setArg(call_sat_vector_imm_op_2901, 11, sat_vector_imm_op_2901_arg11); + setRet(call_sat_vector_imm_op_2901, 0, ret_val_sat_vector_imm_op_2901); } cc.bind(label_merge); } - auto tmp2893 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2893, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2893, 64, false) - , traits::vstart); + auto tmp2903 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2903, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2903, traits::vstart); } cc.bind(label_merge); } @@ -70422,14 +70160,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2894; - x86::Gp ret_val_illegal_normal_2894 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2894, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2894; - setArg(call_illegal_normal_2894, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2894, 1, vd); - setArg(call_illegal_normal_2894, 2, vm); - setRet(call_illegal_normal_2894, 0, ret_val_illegal_normal_2894); + InvokeNode* call_illegal_normal_2904; + x86::Gp ret_val_illegal_normal_2904 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2904, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2904; + setArg(call_illegal_normal_2904, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2904, 1, vd); + setArg(call_illegal_normal_2904, 2, vm); + setRet(call_illegal_normal_2904, 0, ret_val_illegal_normal_2904); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70445,44 +70183,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2896; - x86::Gp ret_val_sew_2896 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2896, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2895; - auto sat_vector_vector_op_2895_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2895_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2895_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2895_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2895_arg11 = ret_val_sew_2896; + InvokeNode* call_sew_2906; + x86::Gp ret_val_sew_2906 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2906, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2905; + auto sat_vector_vector_op_2905_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2905_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2905_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2905_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2905_arg11 = ret_val_sew_2906; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2895 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2895, &sat_vector_vector_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_op_2895, 64, false) - , traits::vxsat); - setArg(call_sew_2896, 0, reinterpret_cast(this)); - setRet(call_sew_2896, 0, ret_val_sew_2896); - setArg(call_sat_vector_vector_op_2895, 0, V); - setArg(call_sat_vector_vector_op_2895, 1, 39); - setArg(call_sat_vector_vector_op_2895, 2, 0); - setArg(call_sat_vector_vector_op_2895, 3, sat_vector_vector_op_2895_arg3); - setArg(call_sat_vector_vector_op_2895, 4, sat_vector_vector_op_2895_arg4); - setArg(call_sat_vector_vector_op_2895, 5, sat_vector_vector_op_2895_arg5); - setArg(call_sat_vector_vector_op_2895, 6, sat_vector_vector_op_2895_arg6); - setArg(call_sat_vector_vector_op_2895, 7, vm); - setArg(call_sat_vector_vector_op_2895, 8, vd); - setArg(call_sat_vector_vector_op_2895, 9, vs2); - setArg(call_sat_vector_vector_op_2895, 10, vs1); - setArg(call_sat_vector_vector_op_2895, 11, sat_vector_vector_op_2895_arg11); - setRet(call_sat_vector_vector_op_2895, 0, ret_val_sat_vector_vector_op_2895); + x86::Gp ret_val_sat_vector_vector_op_2905 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2905, &sat_vector_vector_op, FuncSignature::build()); + auto tmp2907 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_op_2905, 64, false)); + write_reg_to_mem(jh, tmp2907, traits::vxsat); + setArg(call_sew_2906, 0, reinterpret_cast(this)); + setRet(call_sew_2906, 0, ret_val_sew_2906); + setArg(call_sat_vector_vector_op_2905, 0, V); + setArg(call_sat_vector_vector_op_2905, 1, 39); + setArg(call_sat_vector_vector_op_2905, 2, 0); + setArg(call_sat_vector_vector_op_2905, 3, sat_vector_vector_op_2905_arg3); + setArg(call_sat_vector_vector_op_2905, 4, sat_vector_vector_op_2905_arg4); + setArg(call_sat_vector_vector_op_2905, 5, sat_vector_vector_op_2905_arg5); + setArg(call_sat_vector_vector_op_2905, 6, sat_vector_vector_op_2905_arg6); + setArg(call_sat_vector_vector_op_2905, 7, vm); + setArg(call_sat_vector_vector_op_2905, 8, vd); + setArg(call_sat_vector_vector_op_2905, 9, vs2); + setArg(call_sat_vector_vector_op_2905, 10, vs1); + setArg(call_sat_vector_vector_op_2905, 11, sat_vector_vector_op_2905_arg11); + setRet(call_sat_vector_vector_op_2905, 0, ret_val_sat_vector_vector_op_2905); } cc.bind(label_merge); } - auto tmp2897 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2897, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2897, 64, false) - , traits::vstart); + auto tmp2908 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2908, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2908, traits::vstart); } cc.bind(label_merge); } @@ -70528,16 +70263,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2898; - x86::Gp ret_val_illegal_normal_2898 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2898, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2899 = get_reg(cc, 8, false); - mov(cc, tmp2899, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2899, ret_val_illegal_normal_2898); - setArg(call_illegal_normal_2898, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2898, 1, vd); - setArg(call_illegal_normal_2898, 2, vm); - setRet(call_illegal_normal_2898, 0, ret_val_illegal_normal_2898); + InvokeNode* call_illegal_normal_2909; + x86::Gp ret_val_illegal_normal_2909 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2909, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2910 = get_reg(cc, 8, false); + mov(cc, tmp2910, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2910, ret_val_illegal_normal_2909); + setArg(call_illegal_normal_2909, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2909, 1, vd); + setArg(call_illegal_normal_2909, 2, vm); + setRet(call_illegal_normal_2909, 0, ret_val_illegal_normal_2909); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70553,47 +70288,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2901; - x86::Gp ret_val_sew_2901 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2901, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2900; - auto sat_vector_imm_op_2900_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2900_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2900_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2900_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2900_arg10 = gen_ext(cc, + InvokeNode* call_sew_2912; + x86::Gp ret_val_sew_2912 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2912, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2911; + auto sat_vector_imm_op_2911_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2911_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2911_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2911_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2911_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); - auto sat_vector_imm_op_2900_arg11 = ret_val_sew_2901; + auto sat_vector_imm_op_2911_arg11 = ret_val_sew_2912; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2900 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2900, &sat_vector_imm_op, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_op_2900, 64, false) - , traits::vxsat); - setArg(call_sew_2901, 0, reinterpret_cast(this)); - setRet(call_sew_2901, 0, ret_val_sew_2901); - setArg(call_sat_vector_imm_op_2900, 0, V); - setArg(call_sat_vector_imm_op_2900, 1, 39); - setArg(call_sat_vector_imm_op_2900, 2, 4); - setArg(call_sat_vector_imm_op_2900, 3, sat_vector_imm_op_2900_arg3); - setArg(call_sat_vector_imm_op_2900, 4, sat_vector_imm_op_2900_arg4); - setArg(call_sat_vector_imm_op_2900, 5, sat_vector_imm_op_2900_arg5); - setArg(call_sat_vector_imm_op_2900, 6, sat_vector_imm_op_2900_arg6); - setArg(call_sat_vector_imm_op_2900, 7, vm); - setArg(call_sat_vector_imm_op_2900, 8, vd); - setArg(call_sat_vector_imm_op_2900, 9, vs2); - setArg(call_sat_vector_imm_op_2900, 10, sat_vector_imm_op_2900_arg10); - setArg(call_sat_vector_imm_op_2900, 11, sat_vector_imm_op_2900_arg11); - setRet(call_sat_vector_imm_op_2900, 0, ret_val_sat_vector_imm_op_2900); + x86::Gp ret_val_sat_vector_imm_op_2911 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2911, &sat_vector_imm_op, FuncSignature::build()); + auto tmp2913 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_op_2911, 64, false)); + write_reg_to_mem(jh, tmp2913, traits::vxsat); + setArg(call_sew_2912, 0, reinterpret_cast(this)); + setRet(call_sew_2912, 0, ret_val_sew_2912); + setArg(call_sat_vector_imm_op_2911, 0, V); + setArg(call_sat_vector_imm_op_2911, 1, 39); + setArg(call_sat_vector_imm_op_2911, 2, 4); + setArg(call_sat_vector_imm_op_2911, 3, sat_vector_imm_op_2911_arg3); + setArg(call_sat_vector_imm_op_2911, 4, sat_vector_imm_op_2911_arg4); + setArg(call_sat_vector_imm_op_2911, 5, sat_vector_imm_op_2911_arg5); + setArg(call_sat_vector_imm_op_2911, 6, sat_vector_imm_op_2911_arg6); + setArg(call_sat_vector_imm_op_2911, 7, vm); + setArg(call_sat_vector_imm_op_2911, 8, vd); + setArg(call_sat_vector_imm_op_2911, 9, vs2); + setArg(call_sat_vector_imm_op_2911, 10, sat_vector_imm_op_2911_arg10); + setArg(call_sat_vector_imm_op_2911, 11, sat_vector_imm_op_2911_arg11); + setRet(call_sat_vector_imm_op_2911, 0, ret_val_sat_vector_imm_op_2911); } cc.bind(label_merge); } - auto tmp2902 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2902, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2902, 64, false) - , traits::vstart); + auto tmp2914 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2914, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2914, traits::vstart); } cc.bind(label_merge); } @@ -70639,14 +70371,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2903; - x86::Gp ret_val_illegal_normal_2903 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2903, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2903; - setArg(call_illegal_normal_2903, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2903, 1, vd); - setArg(call_illegal_normal_2903, 2, vm); - setRet(call_illegal_normal_2903, 0, ret_val_illegal_normal_2903); + InvokeNode* call_illegal_normal_2915; + x86::Gp ret_val_illegal_normal_2915 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2915, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2915; + setArg(call_illegal_normal_2915, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2915, 1, vd); + setArg(call_illegal_normal_2915, 2, vm); + setRet(call_illegal_normal_2915, 0, ret_val_illegal_normal_2915); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70662,42 +70394,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2905; - x86::Gp ret_val_sew_2905 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2905, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2904; - auto sat_vector_imm_op_2904_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2904_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2904_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2904_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2904_arg11 = ret_val_sew_2905; + InvokeNode* call_sew_2917; + x86::Gp ret_val_sew_2917 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2917, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2916; + auto sat_vector_imm_op_2916_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2916_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2916_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2916_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2916_arg11 = ret_val_sew_2917; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2904 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2904, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2904; - setArg(call_sew_2905, 0, reinterpret_cast(this)); - setRet(call_sew_2905, 0, ret_val_sew_2905); - setArg(call_sat_vector_imm_op_2904, 0, V); - setArg(call_sat_vector_imm_op_2904, 1, 42); - setArg(call_sat_vector_imm_op_2904, 2, 3); - setArg(call_sat_vector_imm_op_2904, 3, sat_vector_imm_op_2904_arg3); - setArg(call_sat_vector_imm_op_2904, 4, sat_vector_imm_op_2904_arg4); - setArg(call_sat_vector_imm_op_2904, 5, sat_vector_imm_op_2904_arg5); - setArg(call_sat_vector_imm_op_2904, 6, sat_vector_imm_op_2904_arg6); - setArg(call_sat_vector_imm_op_2904, 7, vm); - setArg(call_sat_vector_imm_op_2904, 8, vd); - setArg(call_sat_vector_imm_op_2904, 9, vs2); - setArg(call_sat_vector_imm_op_2904, 10, (int64_t)(uint64_t)simm); - setArg(call_sat_vector_imm_op_2904, 11, sat_vector_imm_op_2904_arg11); - setRet(call_sat_vector_imm_op_2904, 0, ret_val_sat_vector_imm_op_2904); + x86::Gp ret_val_sat_vector_imm_op_2916 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2916, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2916; + setArg(call_sew_2917, 0, reinterpret_cast(this)); + setRet(call_sew_2917, 0, ret_val_sew_2917); + setArg(call_sat_vector_imm_op_2916, 0, V); + setArg(call_sat_vector_imm_op_2916, 1, 42); + setArg(call_sat_vector_imm_op_2916, 2, 3); + setArg(call_sat_vector_imm_op_2916, 3, sat_vector_imm_op_2916_arg3); + setArg(call_sat_vector_imm_op_2916, 4, sat_vector_imm_op_2916_arg4); + setArg(call_sat_vector_imm_op_2916, 5, sat_vector_imm_op_2916_arg5); + setArg(call_sat_vector_imm_op_2916, 6, sat_vector_imm_op_2916_arg6); + setArg(call_sat_vector_imm_op_2916, 7, vm); + setArg(call_sat_vector_imm_op_2916, 8, vd); + setArg(call_sat_vector_imm_op_2916, 9, vs2); + setArg(call_sat_vector_imm_op_2916, 10, (int64_t)(uint64_t)simm); + setArg(call_sat_vector_imm_op_2916, 11, sat_vector_imm_op_2916_arg11); + setRet(call_sat_vector_imm_op_2916, 0, ret_val_sat_vector_imm_op_2916); } cc.bind(label_merge); } - auto tmp2906 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2906, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2906, 64, false) - , traits::vstart); + auto tmp2918 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2918, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2918, traits::vstart); } cc.bind(label_merge); } @@ -70743,14 +70473,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2907; - x86::Gp ret_val_illegal_normal_2907 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2907, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2907; - setArg(call_illegal_normal_2907, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2907, 1, vd); - setArg(call_illegal_normal_2907, 2, vm); - setRet(call_illegal_normal_2907, 0, ret_val_illegal_normal_2907); + InvokeNode* call_illegal_normal_2919; + x86::Gp ret_val_illegal_normal_2919 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2919, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2919; + setArg(call_illegal_normal_2919, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2919, 1, vd); + setArg(call_illegal_normal_2919, 2, vm); + setRet(call_illegal_normal_2919, 0, ret_val_illegal_normal_2919); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70766,42 +70496,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2909; - x86::Gp ret_val_sew_2909 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2909, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2908; - auto sat_vector_vector_op_2908_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2908_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2908_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2908_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2908_arg11 = ret_val_sew_2909; + InvokeNode* call_sew_2921; + x86::Gp ret_val_sew_2921 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2921, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2920; + auto sat_vector_vector_op_2920_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2920_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2920_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2920_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2920_arg11 = ret_val_sew_2921; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2908 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2908, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2908; - setArg(call_sew_2909, 0, reinterpret_cast(this)); - setRet(call_sew_2909, 0, ret_val_sew_2909); - setArg(call_sat_vector_vector_op_2908, 0, V); - setArg(call_sat_vector_vector_op_2908, 1, 42); - setArg(call_sat_vector_vector_op_2908, 2, 0); - setArg(call_sat_vector_vector_op_2908, 3, sat_vector_vector_op_2908_arg3); - setArg(call_sat_vector_vector_op_2908, 4, sat_vector_vector_op_2908_arg4); - setArg(call_sat_vector_vector_op_2908, 5, sat_vector_vector_op_2908_arg5); - setArg(call_sat_vector_vector_op_2908, 6, sat_vector_vector_op_2908_arg6); - setArg(call_sat_vector_vector_op_2908, 7, vm); - setArg(call_sat_vector_vector_op_2908, 8, vd); - setArg(call_sat_vector_vector_op_2908, 9, vs2); - setArg(call_sat_vector_vector_op_2908, 10, vs1); - setArg(call_sat_vector_vector_op_2908, 11, sat_vector_vector_op_2908_arg11); - setRet(call_sat_vector_vector_op_2908, 0, ret_val_sat_vector_vector_op_2908); + x86::Gp ret_val_sat_vector_vector_op_2920 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2920, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2920; + setArg(call_sew_2921, 0, reinterpret_cast(this)); + setRet(call_sew_2921, 0, ret_val_sew_2921); + setArg(call_sat_vector_vector_op_2920, 0, V); + setArg(call_sat_vector_vector_op_2920, 1, 42); + setArg(call_sat_vector_vector_op_2920, 2, 0); + setArg(call_sat_vector_vector_op_2920, 3, sat_vector_vector_op_2920_arg3); + setArg(call_sat_vector_vector_op_2920, 4, sat_vector_vector_op_2920_arg4); + setArg(call_sat_vector_vector_op_2920, 5, sat_vector_vector_op_2920_arg5); + setArg(call_sat_vector_vector_op_2920, 6, sat_vector_vector_op_2920_arg6); + setArg(call_sat_vector_vector_op_2920, 7, vm); + setArg(call_sat_vector_vector_op_2920, 8, vd); + setArg(call_sat_vector_vector_op_2920, 9, vs2); + setArg(call_sat_vector_vector_op_2920, 10, vs1); + setArg(call_sat_vector_vector_op_2920, 11, sat_vector_vector_op_2920_arg11); + setRet(call_sat_vector_vector_op_2920, 0, ret_val_sat_vector_vector_op_2920); } cc.bind(label_merge); } - auto tmp2910 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2910, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2910, 64, false) - , traits::vstart); + auto tmp2922 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2922, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2922, traits::vstart); } cc.bind(label_merge); } @@ -70847,16 +70575,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2911; - x86::Gp ret_val_illegal_normal_2911 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2911, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2912 = get_reg(cc, 8, false); - mov(cc, tmp2912, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2912, ret_val_illegal_normal_2911); - setArg(call_illegal_normal_2911, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2911, 1, vd); - setArg(call_illegal_normal_2911, 2, vm); - setRet(call_illegal_normal_2911, 0, ret_val_illegal_normal_2911); + InvokeNode* call_illegal_normal_2923; + x86::Gp ret_val_illegal_normal_2923 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2923, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2924 = get_reg(cc, 8, false); + mov(cc, tmp2924, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2924, ret_val_illegal_normal_2923); + setArg(call_illegal_normal_2923, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2923, 1, vd); + setArg(call_illegal_normal_2923, 2, vm); + setRet(call_illegal_normal_2923, 0, ret_val_illegal_normal_2923); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70872,45 +70600,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2914; - x86::Gp ret_val_sew_2914 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2914, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2913; - auto sat_vector_imm_op_2913_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2913_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2913_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2913_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2913_arg10 = gen_ext(cc, + InvokeNode* call_sew_2926; + x86::Gp ret_val_sew_2926 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2926, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2925; + auto sat_vector_imm_op_2925_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2925_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2925_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2925_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2925_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); - auto sat_vector_imm_op_2913_arg11 = ret_val_sew_2914; + auto sat_vector_imm_op_2925_arg11 = ret_val_sew_2926; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2913 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2913, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2913; - setArg(call_sew_2914, 0, reinterpret_cast(this)); - setRet(call_sew_2914, 0, ret_val_sew_2914); - setArg(call_sat_vector_imm_op_2913, 0, V); - setArg(call_sat_vector_imm_op_2913, 1, 42); - setArg(call_sat_vector_imm_op_2913, 2, 4); - setArg(call_sat_vector_imm_op_2913, 3, sat_vector_imm_op_2913_arg3); - setArg(call_sat_vector_imm_op_2913, 4, sat_vector_imm_op_2913_arg4); - setArg(call_sat_vector_imm_op_2913, 5, sat_vector_imm_op_2913_arg5); - setArg(call_sat_vector_imm_op_2913, 6, sat_vector_imm_op_2913_arg6); - setArg(call_sat_vector_imm_op_2913, 7, vm); - setArg(call_sat_vector_imm_op_2913, 8, vd); - setArg(call_sat_vector_imm_op_2913, 9, vs2); - setArg(call_sat_vector_imm_op_2913, 10, sat_vector_imm_op_2913_arg10); - setArg(call_sat_vector_imm_op_2913, 11, sat_vector_imm_op_2913_arg11); - setRet(call_sat_vector_imm_op_2913, 0, ret_val_sat_vector_imm_op_2913); + x86::Gp ret_val_sat_vector_imm_op_2925 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2925, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2925; + setArg(call_sew_2926, 0, reinterpret_cast(this)); + setRet(call_sew_2926, 0, ret_val_sew_2926); + setArg(call_sat_vector_imm_op_2925, 0, V); + setArg(call_sat_vector_imm_op_2925, 1, 42); + setArg(call_sat_vector_imm_op_2925, 2, 4); + setArg(call_sat_vector_imm_op_2925, 3, sat_vector_imm_op_2925_arg3); + setArg(call_sat_vector_imm_op_2925, 4, sat_vector_imm_op_2925_arg4); + setArg(call_sat_vector_imm_op_2925, 5, sat_vector_imm_op_2925_arg5); + setArg(call_sat_vector_imm_op_2925, 6, sat_vector_imm_op_2925_arg6); + setArg(call_sat_vector_imm_op_2925, 7, vm); + setArg(call_sat_vector_imm_op_2925, 8, vd); + setArg(call_sat_vector_imm_op_2925, 9, vs2); + setArg(call_sat_vector_imm_op_2925, 10, sat_vector_imm_op_2925_arg10); + setArg(call_sat_vector_imm_op_2925, 11, sat_vector_imm_op_2925_arg11); + setRet(call_sat_vector_imm_op_2925, 0, ret_val_sat_vector_imm_op_2925); } cc.bind(label_merge); } - auto tmp2915 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2915, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2915, 64, false) - , traits::vstart); + auto tmp2927 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2927, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2927, traits::vstart); } cc.bind(label_merge); } @@ -70956,14 +70682,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2916; - x86::Gp ret_val_illegal_normal_2916 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2916, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2916; - setArg(call_illegal_normal_2916, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2916, 1, vd); - setArg(call_illegal_normal_2916, 2, vm); - setRet(call_illegal_normal_2916, 0, ret_val_illegal_normal_2916); + InvokeNode* call_illegal_normal_2928; + x86::Gp ret_val_illegal_normal_2928 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2928, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2928; + setArg(call_illegal_normal_2928, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2928, 1, vd); + setArg(call_illegal_normal_2928, 2, vm); + setRet(call_illegal_normal_2928, 0, ret_val_illegal_normal_2928); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -70979,42 +70705,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2918; - x86::Gp ret_val_sew_2918 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2918, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2917; - auto sat_vector_imm_op_2917_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2917_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2917_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2917_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2917_arg11 = ret_val_sew_2918; + InvokeNode* call_sew_2930; + x86::Gp ret_val_sew_2930 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2930, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2929; + auto sat_vector_imm_op_2929_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2929_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2929_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2929_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2929_arg11 = ret_val_sew_2930; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2917 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2917, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2917; - setArg(call_sew_2918, 0, reinterpret_cast(this)); - setRet(call_sew_2918, 0, ret_val_sew_2918); - setArg(call_sat_vector_imm_op_2917, 0, V); - setArg(call_sat_vector_imm_op_2917, 1, 43); - setArg(call_sat_vector_imm_op_2917, 2, 3); - setArg(call_sat_vector_imm_op_2917, 3, sat_vector_imm_op_2917_arg3); - setArg(call_sat_vector_imm_op_2917, 4, sat_vector_imm_op_2917_arg4); - setArg(call_sat_vector_imm_op_2917, 5, sat_vector_imm_op_2917_arg5); - setArg(call_sat_vector_imm_op_2917, 6, sat_vector_imm_op_2917_arg6); - setArg(call_sat_vector_imm_op_2917, 7, vm); - setArg(call_sat_vector_imm_op_2917, 8, vd); - setArg(call_sat_vector_imm_op_2917, 9, vs2); - setArg(call_sat_vector_imm_op_2917, 10, (int64_t)(uint64_t)simm); - setArg(call_sat_vector_imm_op_2917, 11, sat_vector_imm_op_2917_arg11); - setRet(call_sat_vector_imm_op_2917, 0, ret_val_sat_vector_imm_op_2917); + x86::Gp ret_val_sat_vector_imm_op_2929 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2929, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2929; + setArg(call_sew_2930, 0, reinterpret_cast(this)); + setRet(call_sew_2930, 0, ret_val_sew_2930); + setArg(call_sat_vector_imm_op_2929, 0, V); + setArg(call_sat_vector_imm_op_2929, 1, 43); + setArg(call_sat_vector_imm_op_2929, 2, 3); + setArg(call_sat_vector_imm_op_2929, 3, sat_vector_imm_op_2929_arg3); + setArg(call_sat_vector_imm_op_2929, 4, sat_vector_imm_op_2929_arg4); + setArg(call_sat_vector_imm_op_2929, 5, sat_vector_imm_op_2929_arg5); + setArg(call_sat_vector_imm_op_2929, 6, sat_vector_imm_op_2929_arg6); + setArg(call_sat_vector_imm_op_2929, 7, vm); + setArg(call_sat_vector_imm_op_2929, 8, vd); + setArg(call_sat_vector_imm_op_2929, 9, vs2); + setArg(call_sat_vector_imm_op_2929, 10, (int64_t)(uint64_t)simm); + setArg(call_sat_vector_imm_op_2929, 11, sat_vector_imm_op_2929_arg11); + setRet(call_sat_vector_imm_op_2929, 0, ret_val_sat_vector_imm_op_2929); } cc.bind(label_merge); } - auto tmp2919 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2919, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2919, 64, false) - , traits::vstart); + auto tmp2931 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2931, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2931, traits::vstart); } cc.bind(label_merge); } @@ -71060,14 +70784,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2920; - x86::Gp ret_val_illegal_normal_2920 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2920, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_2920; - setArg(call_illegal_normal_2920, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2920, 1, vd); - setArg(call_illegal_normal_2920, 2, vm); - setRet(call_illegal_normal_2920, 0, ret_val_illegal_normal_2920); + InvokeNode* call_illegal_normal_2932; + x86::Gp ret_val_illegal_normal_2932 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2932, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_2932; + setArg(call_illegal_normal_2932, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2932, 1, vd); + setArg(call_illegal_normal_2932, 2, vm); + setRet(call_illegal_normal_2932, 0, ret_val_illegal_normal_2932); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71083,42 +70807,40 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2922; - x86::Gp ret_val_sew_2922 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2922, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_op_2921; - auto sat_vector_vector_op_2921_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_op_2921_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_op_2921_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_op_2921_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_op_2921_arg11 = ret_val_sew_2922; + InvokeNode* call_sew_2934; + x86::Gp ret_val_sew_2934 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2934, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_op_2933; + auto sat_vector_vector_op_2933_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_op_2933_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_op_2933_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_op_2933_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_op_2933_arg11 = ret_val_sew_2934; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_op_2921 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_op_2921, &sat_vector_vector_op, FuncSignature::build()); - ret_val_sat_vector_vector_op_2921; - setArg(call_sew_2922, 0, reinterpret_cast(this)); - setRet(call_sew_2922, 0, ret_val_sew_2922); - setArg(call_sat_vector_vector_op_2921, 0, V); - setArg(call_sat_vector_vector_op_2921, 1, 43); - setArg(call_sat_vector_vector_op_2921, 2, 0); - setArg(call_sat_vector_vector_op_2921, 3, sat_vector_vector_op_2921_arg3); - setArg(call_sat_vector_vector_op_2921, 4, sat_vector_vector_op_2921_arg4); - setArg(call_sat_vector_vector_op_2921, 5, sat_vector_vector_op_2921_arg5); - setArg(call_sat_vector_vector_op_2921, 6, sat_vector_vector_op_2921_arg6); - setArg(call_sat_vector_vector_op_2921, 7, vm); - setArg(call_sat_vector_vector_op_2921, 8, vd); - setArg(call_sat_vector_vector_op_2921, 9, vs2); - setArg(call_sat_vector_vector_op_2921, 10, vs1); - setArg(call_sat_vector_vector_op_2921, 11, sat_vector_vector_op_2921_arg11); - setRet(call_sat_vector_vector_op_2921, 0, ret_val_sat_vector_vector_op_2921); + x86::Gp ret_val_sat_vector_vector_op_2933 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_op_2933, &sat_vector_vector_op, FuncSignature::build()); + ret_val_sat_vector_vector_op_2933; + setArg(call_sew_2934, 0, reinterpret_cast(this)); + setRet(call_sew_2934, 0, ret_val_sew_2934); + setArg(call_sat_vector_vector_op_2933, 0, V); + setArg(call_sat_vector_vector_op_2933, 1, 43); + setArg(call_sat_vector_vector_op_2933, 2, 0); + setArg(call_sat_vector_vector_op_2933, 3, sat_vector_vector_op_2933_arg3); + setArg(call_sat_vector_vector_op_2933, 4, sat_vector_vector_op_2933_arg4); + setArg(call_sat_vector_vector_op_2933, 5, sat_vector_vector_op_2933_arg5); + setArg(call_sat_vector_vector_op_2933, 6, sat_vector_vector_op_2933_arg6); + setArg(call_sat_vector_vector_op_2933, 7, vm); + setArg(call_sat_vector_vector_op_2933, 8, vd); + setArg(call_sat_vector_vector_op_2933, 9, vs2); + setArg(call_sat_vector_vector_op_2933, 10, vs1); + setArg(call_sat_vector_vector_op_2933, 11, sat_vector_vector_op_2933_arg11); + setRet(call_sat_vector_vector_op_2933, 0, ret_val_sat_vector_vector_op_2933); } cc.bind(label_merge); } - auto tmp2923 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2923, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2923, 64, false) - , traits::vstart); + auto tmp2935 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2935, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2935, traits::vstart); } cc.bind(label_merge); } @@ -71164,16 +70886,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_2924; - x86::Gp ret_val_illegal_normal_2924 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_2924, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp2925 = get_reg(cc, 8, false); - mov(cc, tmp2925, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp2925, ret_val_illegal_normal_2924); - setArg(call_illegal_normal_2924, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_2924, 1, vd); - setArg(call_illegal_normal_2924, 2, vm); - setRet(call_illegal_normal_2924, 0, ret_val_illegal_normal_2924); + InvokeNode* call_illegal_normal_2936; + x86::Gp ret_val_illegal_normal_2936 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_2936, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp2937 = get_reg(cc, 8, false); + mov(cc, tmp2937, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp2937, ret_val_illegal_normal_2936); + setArg(call_illegal_normal_2936, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_2936, 1, vd); + setArg(call_illegal_normal_2936, 2, vm); + setRet(call_illegal_normal_2936, 0, ret_val_illegal_normal_2936); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71189,45 +70911,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2927; - x86::Gp ret_val_sew_2927 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2927, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_op_2926; - auto sat_vector_imm_op_2926_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_op_2926_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_op_2926_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_op_2926_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_op_2926_arg10 = gen_ext(cc, + InvokeNode* call_sew_2939; + x86::Gp ret_val_sew_2939 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2939, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_op_2938; + auto sat_vector_imm_op_2938_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_op_2938_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_op_2938_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_op_2938_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_op_2938_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); - auto sat_vector_imm_op_2926_arg11 = ret_val_sew_2927; + auto sat_vector_imm_op_2938_arg11 = ret_val_sew_2939; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_op_2926 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_op_2926, &sat_vector_imm_op, FuncSignature::build()); - ret_val_sat_vector_imm_op_2926; - setArg(call_sew_2927, 0, reinterpret_cast(this)); - setRet(call_sew_2927, 0, ret_val_sew_2927); - setArg(call_sat_vector_imm_op_2926, 0, V); - setArg(call_sat_vector_imm_op_2926, 1, 43); - setArg(call_sat_vector_imm_op_2926, 2, 4); - setArg(call_sat_vector_imm_op_2926, 3, sat_vector_imm_op_2926_arg3); - setArg(call_sat_vector_imm_op_2926, 4, sat_vector_imm_op_2926_arg4); - setArg(call_sat_vector_imm_op_2926, 5, sat_vector_imm_op_2926_arg5); - setArg(call_sat_vector_imm_op_2926, 6, sat_vector_imm_op_2926_arg6); - setArg(call_sat_vector_imm_op_2926, 7, vm); - setArg(call_sat_vector_imm_op_2926, 8, vd); - setArg(call_sat_vector_imm_op_2926, 9, vs2); - setArg(call_sat_vector_imm_op_2926, 10, sat_vector_imm_op_2926_arg10); - setArg(call_sat_vector_imm_op_2926, 11, sat_vector_imm_op_2926_arg11); - setRet(call_sat_vector_imm_op_2926, 0, ret_val_sat_vector_imm_op_2926); + x86::Gp ret_val_sat_vector_imm_op_2938 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_op_2938, &sat_vector_imm_op, FuncSignature::build()); + ret_val_sat_vector_imm_op_2938; + setArg(call_sew_2939, 0, reinterpret_cast(this)); + setRet(call_sew_2939, 0, ret_val_sew_2939); + setArg(call_sat_vector_imm_op_2938, 0, V); + setArg(call_sat_vector_imm_op_2938, 1, 43); + setArg(call_sat_vector_imm_op_2938, 2, 4); + setArg(call_sat_vector_imm_op_2938, 3, sat_vector_imm_op_2938_arg3); + setArg(call_sat_vector_imm_op_2938, 4, sat_vector_imm_op_2938_arg4); + setArg(call_sat_vector_imm_op_2938, 5, sat_vector_imm_op_2938_arg5); + setArg(call_sat_vector_imm_op_2938, 6, sat_vector_imm_op_2938_arg6); + setArg(call_sat_vector_imm_op_2938, 7, vm); + setArg(call_sat_vector_imm_op_2938, 8, vd); + setArg(call_sat_vector_imm_op_2938, 9, vs2); + setArg(call_sat_vector_imm_op_2938, 10, sat_vector_imm_op_2938_arg10); + setArg(call_sat_vector_imm_op_2938, 11, sat_vector_imm_op_2938_arg11); + setRet(call_sat_vector_imm_op_2938, 0, ret_val_sat_vector_imm_op_2938); } cc.bind(label_merge); } - auto tmp2928 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2928, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2928, 64, false) - , traits::vstart); + auto tmp2940 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2940, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2940, traits::vstart); } cc.bind(label_merge); } @@ -71271,49 +70991,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2929; - x86::Gp ret_val_get_sew_pow_2929 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2929, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2930 = get_reg(cc, 8, false); - mov(cc, tmp2930, 1); + InvokeNode* call_get_sew_pow_2941; + x86::Gp ret_val_get_sew_pow_2941 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2941, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2942 = get_reg(cc, 8, false); + mov(cc, tmp2942, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2930, ret_val_get_sew_pow_2929)), 8, false), ~ 1); - setArg(call_get_sew_pow_2929, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2929, 0, ret_val_get_sew_pow_2929); - InvokeNode* call_get_lmul_pow_2931; - x86::Gp ret_val_get_lmul_pow_2931 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2931, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2931; - setArg(call_get_lmul_pow_2931, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2931, 0, ret_val_get_lmul_pow_2931); + (gen_operation(cc, shl, tmp2942, ret_val_get_sew_pow_2941)), 8, false), ~ 1); + setArg(call_get_sew_pow_2941, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2941, 0, ret_val_get_sew_pow_2941); + InvokeNode* call_get_lmul_pow_2943; + x86::Gp ret_val_get_lmul_pow_2943 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2943, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2943; + setArg(call_get_lmul_pow_2943, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2943, 0, ret_val_get_lmul_pow_2943); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2932; - auto illegal_variable_width_2932_arg2 = SEW_widen; - auto illegal_variable_width_2932_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2932 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2932, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2933; - auto valid_reg_overlap_2933_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2933_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2933 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2933, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2932, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2933))); - setArg(call_illegal_variable_width_2932, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2932, 1, vd); - setArg(call_illegal_variable_width_2932, 2, vm); - setArg(call_illegal_variable_width_2932, 3, illegal_variable_width_2932_arg2); - setArg(call_illegal_variable_width_2932, 4, illegal_variable_width_2932_arg3); - setRet(call_illegal_variable_width_2932, 0, ret_val_illegal_variable_width_2932); - setArg(call_valid_reg_overlap_2933, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2933, 1, vs2); - setArg(call_valid_reg_overlap_2933, 2, vd); - setArg(call_valid_reg_overlap_2933, 3, valid_reg_overlap_2933_arg2); - setArg(call_valid_reg_overlap_2933, 4, valid_reg_overlap_2933_arg3); - setRet(call_valid_reg_overlap_2933, 0, ret_val_valid_reg_overlap_2933); + InvokeNode* call_illegal_variable_width_2944; + auto illegal_variable_width_2944_arg2 = SEW_widen; + auto illegal_variable_width_2944_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2944 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2944, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2945; + auto valid_reg_overlap_2945_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2945_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2945 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2945, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2944, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2945))); + setArg(call_illegal_variable_width_2944, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2944, 1, vd); + setArg(call_illegal_variable_width_2944, 2, vm); + setArg(call_illegal_variable_width_2944, 3, illegal_variable_width_2944_arg2); + setArg(call_illegal_variable_width_2944, 4, illegal_variable_width_2944_arg3); + setRet(call_illegal_variable_width_2944, 0, ret_val_illegal_variable_width_2944); + setArg(call_valid_reg_overlap_2945, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2945, 1, vs2); + setArg(call_valid_reg_overlap_2945, 2, vd); + setArg(call_valid_reg_overlap_2945, 3, valid_reg_overlap_2945_arg2); + setArg(call_valid_reg_overlap_2945, 4, valid_reg_overlap_2945_arg3); + setRet(call_valid_reg_overlap_2945, 0, ret_val_valid_reg_overlap_2945); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71329,44 +71049,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2935; - x86::Gp ret_val_sew_2935 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2935, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_vw_2934; - auto sat_vector_imm_vw_2934_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_vw_2934_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_vw_2934_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_vw_2934_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_vw_2934_arg11 = ret_val_sew_2935; + InvokeNode* call_sew_2947; + x86::Gp ret_val_sew_2947 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2947, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2946; + auto sat_vector_imm_vw_2946_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2946_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2946_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2946_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2946_arg11 = ret_val_sew_2947; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_vw_2934 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_vw_2934, &sat_vector_imm_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_vw_2934, 64, false) - , traits::vxsat); - setArg(call_sew_2935, 0, reinterpret_cast(this)); - setRet(call_sew_2935, 0, ret_val_sew_2935); - setArg(call_sat_vector_imm_vw_2934, 0, V); - setArg(call_sat_vector_imm_vw_2934, 1, 46); - setArg(call_sat_vector_imm_vw_2934, 2, 3); - setArg(call_sat_vector_imm_vw_2934, 3, sat_vector_imm_vw_2934_arg3); - setArg(call_sat_vector_imm_vw_2934, 4, sat_vector_imm_vw_2934_arg4); - setArg(call_sat_vector_imm_vw_2934, 5, sat_vector_imm_vw_2934_arg5); - setArg(call_sat_vector_imm_vw_2934, 6, sat_vector_imm_vw_2934_arg6); - setArg(call_sat_vector_imm_vw_2934, 7, vm); - setArg(call_sat_vector_imm_vw_2934, 8, vd); - setArg(call_sat_vector_imm_vw_2934, 9, vs2); - setArg(call_sat_vector_imm_vw_2934, 10, (int64_t)(uint64_t)simm); - setArg(call_sat_vector_imm_vw_2934, 11, sat_vector_imm_vw_2934_arg11); - setRet(call_sat_vector_imm_vw_2934, 0, ret_val_sat_vector_imm_vw_2934); + x86::Gp ret_val_sat_vector_imm_vw_2946 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2946, &sat_vector_imm_vw, FuncSignature::build()); + auto tmp2948 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_vw_2946, 64, false)); + write_reg_to_mem(jh, tmp2948, traits::vxsat); + setArg(call_sew_2947, 0, reinterpret_cast(this)); + setRet(call_sew_2947, 0, ret_val_sew_2947); + setArg(call_sat_vector_imm_vw_2946, 0, V); + setArg(call_sat_vector_imm_vw_2946, 1, 46); + setArg(call_sat_vector_imm_vw_2946, 2, 3); + setArg(call_sat_vector_imm_vw_2946, 3, sat_vector_imm_vw_2946_arg3); + setArg(call_sat_vector_imm_vw_2946, 4, sat_vector_imm_vw_2946_arg4); + setArg(call_sat_vector_imm_vw_2946, 5, sat_vector_imm_vw_2946_arg5); + setArg(call_sat_vector_imm_vw_2946, 6, sat_vector_imm_vw_2946_arg6); + setArg(call_sat_vector_imm_vw_2946, 7, vm); + setArg(call_sat_vector_imm_vw_2946, 8, vd); + setArg(call_sat_vector_imm_vw_2946, 9, vs2); + setArg(call_sat_vector_imm_vw_2946, 10, (int64_t)(uint64_t)simm); + setArg(call_sat_vector_imm_vw_2946, 11, sat_vector_imm_vw_2946_arg11); + setRet(call_sat_vector_imm_vw_2946, 0, ret_val_sat_vector_imm_vw_2946); } cc.bind(label_merge); } - auto tmp2936 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2936, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2936, 64, false) - , traits::vstart); + auto tmp2949 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2949, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2949, traits::vstart); } cc.bind(label_merge); } @@ -71410,49 +71127,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2937; - x86::Gp ret_val_get_sew_pow_2937 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2937, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2938 = get_reg(cc, 8, false); - mov(cc, tmp2938, 1); + InvokeNode* call_get_sew_pow_2950; + x86::Gp ret_val_get_sew_pow_2950 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2950, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2951 = get_reg(cc, 8, false); + mov(cc, tmp2951, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2938, ret_val_get_sew_pow_2937)), 8, false), ~ 1); - setArg(call_get_sew_pow_2937, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2937, 0, ret_val_get_sew_pow_2937); - InvokeNode* call_get_lmul_pow_2939; - x86::Gp ret_val_get_lmul_pow_2939 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2939, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2939; - setArg(call_get_lmul_pow_2939, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2939, 0, ret_val_get_lmul_pow_2939); + (gen_operation(cc, shl, tmp2951, ret_val_get_sew_pow_2950)), 8, false), ~ 1); + setArg(call_get_sew_pow_2950, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2950, 0, ret_val_get_sew_pow_2950); + InvokeNode* call_get_lmul_pow_2952; + x86::Gp ret_val_get_lmul_pow_2952 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2952, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2952; + setArg(call_get_lmul_pow_2952, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2952, 0, ret_val_get_lmul_pow_2952); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2940; - auto illegal_variable_width_2940_arg2 = SEW_widen; - auto illegal_variable_width_2940_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2940 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2940, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2941; - auto valid_reg_overlap_2941_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2941_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2941 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2941, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2940, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2941))); - setArg(call_illegal_variable_width_2940, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2940, 1, vd); - setArg(call_illegal_variable_width_2940, 2, vm); - setArg(call_illegal_variable_width_2940, 3, illegal_variable_width_2940_arg2); - setArg(call_illegal_variable_width_2940, 4, illegal_variable_width_2940_arg3); - setRet(call_illegal_variable_width_2940, 0, ret_val_illegal_variable_width_2940); - setArg(call_valid_reg_overlap_2941, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2941, 1, vs2); - setArg(call_valid_reg_overlap_2941, 2, vd); - setArg(call_valid_reg_overlap_2941, 3, valid_reg_overlap_2941_arg2); - setArg(call_valid_reg_overlap_2941, 4, valid_reg_overlap_2941_arg3); - setRet(call_valid_reg_overlap_2941, 0, ret_val_valid_reg_overlap_2941); + InvokeNode* call_illegal_variable_width_2953; + auto illegal_variable_width_2953_arg2 = SEW_widen; + auto illegal_variable_width_2953_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2953 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2953, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2954; + auto valid_reg_overlap_2954_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2954_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2954 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2954, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2953, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2954))); + setArg(call_illegal_variable_width_2953, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2953, 1, vd); + setArg(call_illegal_variable_width_2953, 2, vm); + setArg(call_illegal_variable_width_2953, 3, illegal_variable_width_2953_arg2); + setArg(call_illegal_variable_width_2953, 4, illegal_variable_width_2953_arg3); + setRet(call_illegal_variable_width_2953, 0, ret_val_illegal_variable_width_2953); + setArg(call_valid_reg_overlap_2954, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2954, 1, vs2); + setArg(call_valid_reg_overlap_2954, 2, vd); + setArg(call_valid_reg_overlap_2954, 3, valid_reg_overlap_2954_arg2); + setArg(call_valid_reg_overlap_2954, 4, valid_reg_overlap_2954_arg3); + setRet(call_valid_reg_overlap_2954, 0, ret_val_valid_reg_overlap_2954); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71468,44 +71185,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2943; - x86::Gp ret_val_sew_2943 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2943, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_vw_2942; - auto sat_vector_vector_vw_2942_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_vw_2942_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_vw_2942_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_vw_2942_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_vw_2942_arg11 = ret_val_sew_2943; + InvokeNode* call_sew_2956; + x86::Gp ret_val_sew_2956 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2956, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_vw_2955; + auto sat_vector_vector_vw_2955_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_vw_2955_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_vw_2955_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_vw_2955_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_vw_2955_arg11 = ret_val_sew_2956; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_vw_2942 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_vw_2942, &sat_vector_vector_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_vw_2942, 64, false) - , traits::vxsat); - setArg(call_sew_2943, 0, reinterpret_cast(this)); - setRet(call_sew_2943, 0, ret_val_sew_2943); - setArg(call_sat_vector_vector_vw_2942, 0, V); - setArg(call_sat_vector_vector_vw_2942, 1, 46); - setArg(call_sat_vector_vector_vw_2942, 2, 0); - setArg(call_sat_vector_vector_vw_2942, 3, sat_vector_vector_vw_2942_arg3); - setArg(call_sat_vector_vector_vw_2942, 4, sat_vector_vector_vw_2942_arg4); - setArg(call_sat_vector_vector_vw_2942, 5, sat_vector_vector_vw_2942_arg5); - setArg(call_sat_vector_vector_vw_2942, 6, sat_vector_vector_vw_2942_arg6); - setArg(call_sat_vector_vector_vw_2942, 7, vm); - setArg(call_sat_vector_vector_vw_2942, 8, vd); - setArg(call_sat_vector_vector_vw_2942, 9, vs2); - setArg(call_sat_vector_vector_vw_2942, 10, vs1); - setArg(call_sat_vector_vector_vw_2942, 11, sat_vector_vector_vw_2942_arg11); - setRet(call_sat_vector_vector_vw_2942, 0, ret_val_sat_vector_vector_vw_2942); + x86::Gp ret_val_sat_vector_vector_vw_2955 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_vw_2955, &sat_vector_vector_vw, FuncSignature::build()); + auto tmp2957 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_vw_2955, 64, false)); + write_reg_to_mem(jh, tmp2957, traits::vxsat); + setArg(call_sew_2956, 0, reinterpret_cast(this)); + setRet(call_sew_2956, 0, ret_val_sew_2956); + setArg(call_sat_vector_vector_vw_2955, 0, V); + setArg(call_sat_vector_vector_vw_2955, 1, 46); + setArg(call_sat_vector_vector_vw_2955, 2, 0); + setArg(call_sat_vector_vector_vw_2955, 3, sat_vector_vector_vw_2955_arg3); + setArg(call_sat_vector_vector_vw_2955, 4, sat_vector_vector_vw_2955_arg4); + setArg(call_sat_vector_vector_vw_2955, 5, sat_vector_vector_vw_2955_arg5); + setArg(call_sat_vector_vector_vw_2955, 6, sat_vector_vector_vw_2955_arg6); + setArg(call_sat_vector_vector_vw_2955, 7, vm); + setArg(call_sat_vector_vector_vw_2955, 8, vd); + setArg(call_sat_vector_vector_vw_2955, 9, vs2); + setArg(call_sat_vector_vector_vw_2955, 10, vs1); + setArg(call_sat_vector_vector_vw_2955, 11, sat_vector_vector_vw_2955_arg11); + setRet(call_sat_vector_vector_vw_2955, 0, ret_val_sat_vector_vector_vw_2955); } cc.bind(label_merge); } - auto tmp2944 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2944, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2944, 64, false) - , traits::vstart); + auto tmp2958 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2958, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2958, traits::vstart); } cc.bind(label_merge); } @@ -71553,49 +71267,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else { - InvokeNode* call_get_sew_pow_2945; - x86::Gp ret_val_get_sew_pow_2945 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2945, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2946 = get_reg(cc, 8, false); - mov(cc, tmp2946, 1); + InvokeNode* call_get_sew_pow_2959; + x86::Gp ret_val_get_sew_pow_2959 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2959, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2960 = get_reg(cc, 8, false); + mov(cc, tmp2960, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2946, ret_val_get_sew_pow_2945)), 8, false), ~ 1); - setArg(call_get_sew_pow_2945, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2945, 0, ret_val_get_sew_pow_2945); - InvokeNode* call_get_lmul_pow_2947; - x86::Gp ret_val_get_lmul_pow_2947 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2947, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2947; - setArg(call_get_lmul_pow_2947, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2947, 0, ret_val_get_lmul_pow_2947); + (gen_operation(cc, shl, tmp2960, ret_val_get_sew_pow_2959)), 8, false), ~ 1); + setArg(call_get_sew_pow_2959, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2959, 0, ret_val_get_sew_pow_2959); + InvokeNode* call_get_lmul_pow_2961; + x86::Gp ret_val_get_lmul_pow_2961 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2961, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2961; + setArg(call_get_lmul_pow_2961, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2961, 0, ret_val_get_lmul_pow_2961); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2948; - auto illegal_variable_width_2948_arg2 = SEW_widen; - auto illegal_variable_width_2948_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2948 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2948, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2949; - auto valid_reg_overlap_2949_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2949_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2949 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2949, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2948, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2949))); - setArg(call_illegal_variable_width_2948, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2948, 1, vd); - setArg(call_illegal_variable_width_2948, 2, vm); - setArg(call_illegal_variable_width_2948, 3, illegal_variable_width_2948_arg2); - setArg(call_illegal_variable_width_2948, 4, illegal_variable_width_2948_arg3); - setRet(call_illegal_variable_width_2948, 0, ret_val_illegal_variable_width_2948); - setArg(call_valid_reg_overlap_2949, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2949, 1, vs2); - setArg(call_valid_reg_overlap_2949, 2, vd); - setArg(call_valid_reg_overlap_2949, 3, valid_reg_overlap_2949_arg2); - setArg(call_valid_reg_overlap_2949, 4, valid_reg_overlap_2949_arg3); - setRet(call_valid_reg_overlap_2949, 0, ret_val_valid_reg_overlap_2949); + InvokeNode* call_illegal_variable_width_2962; + auto illegal_variable_width_2962_arg2 = SEW_widen; + auto illegal_variable_width_2962_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2962 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2962, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2963; + auto valid_reg_overlap_2963_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2963_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2963 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2963, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2962, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2963))); + setArg(call_illegal_variable_width_2962, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2962, 1, vd); + setArg(call_illegal_variable_width_2962, 2, vm); + setArg(call_illegal_variable_width_2962, 3, illegal_variable_width_2962_arg2); + setArg(call_illegal_variable_width_2962, 4, illegal_variable_width_2962_arg3); + setRet(call_illegal_variable_width_2962, 0, ret_val_illegal_variable_width_2962); + setArg(call_valid_reg_overlap_2963, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2963, 1, vs2); + setArg(call_valid_reg_overlap_2963, 2, vd); + setArg(call_valid_reg_overlap_2963, 3, valid_reg_overlap_2963_arg2); + setArg(call_valid_reg_overlap_2963, 4, valid_reg_overlap_2963_arg3); + setRet(call_valid_reg_overlap_2963, 0, ret_val_valid_reg_overlap_2963); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71611,47 +71325,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2951; - x86::Gp ret_val_sew_2951 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2951, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_vw_2950; - auto sat_vector_imm_vw_2950_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_vw_2950_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_vw_2950_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_vw_2950_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_vw_2950_arg10 = gen_ext(cc, + InvokeNode* call_sew_2965; + x86::Gp ret_val_sew_2965 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2965, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2964; + auto sat_vector_imm_vw_2964_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2964_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2964_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2964_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2964_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); - auto sat_vector_imm_vw_2950_arg11 = ret_val_sew_2951; + auto sat_vector_imm_vw_2964_arg11 = ret_val_sew_2965; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_vw_2950 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_vw_2950, &sat_vector_imm_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_vw_2950, 64, false) - , traits::vxsat); - setArg(call_sew_2951, 0, reinterpret_cast(this)); - setRet(call_sew_2951, 0, ret_val_sew_2951); - setArg(call_sat_vector_imm_vw_2950, 0, V); - setArg(call_sat_vector_imm_vw_2950, 1, 46); - setArg(call_sat_vector_imm_vw_2950, 2, 4); - setArg(call_sat_vector_imm_vw_2950, 3, sat_vector_imm_vw_2950_arg3); - setArg(call_sat_vector_imm_vw_2950, 4, sat_vector_imm_vw_2950_arg4); - setArg(call_sat_vector_imm_vw_2950, 5, sat_vector_imm_vw_2950_arg5); - setArg(call_sat_vector_imm_vw_2950, 6, sat_vector_imm_vw_2950_arg6); - setArg(call_sat_vector_imm_vw_2950, 7, vm); - setArg(call_sat_vector_imm_vw_2950, 8, vd); - setArg(call_sat_vector_imm_vw_2950, 9, vs2); - setArg(call_sat_vector_imm_vw_2950, 10, sat_vector_imm_vw_2950_arg10); - setArg(call_sat_vector_imm_vw_2950, 11, sat_vector_imm_vw_2950_arg11); - setRet(call_sat_vector_imm_vw_2950, 0, ret_val_sat_vector_imm_vw_2950); + x86::Gp ret_val_sat_vector_imm_vw_2964 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2964, &sat_vector_imm_vw, FuncSignature::build()); + auto tmp2966 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_vw_2964, 64, false)); + write_reg_to_mem(jh, tmp2966, traits::vxsat); + setArg(call_sew_2965, 0, reinterpret_cast(this)); + setRet(call_sew_2965, 0, ret_val_sew_2965); + setArg(call_sat_vector_imm_vw_2964, 0, V); + setArg(call_sat_vector_imm_vw_2964, 1, 46); + setArg(call_sat_vector_imm_vw_2964, 2, 4); + setArg(call_sat_vector_imm_vw_2964, 3, sat_vector_imm_vw_2964_arg3); + setArg(call_sat_vector_imm_vw_2964, 4, sat_vector_imm_vw_2964_arg4); + setArg(call_sat_vector_imm_vw_2964, 5, sat_vector_imm_vw_2964_arg5); + setArg(call_sat_vector_imm_vw_2964, 6, sat_vector_imm_vw_2964_arg6); + setArg(call_sat_vector_imm_vw_2964, 7, vm); + setArg(call_sat_vector_imm_vw_2964, 8, vd); + setArg(call_sat_vector_imm_vw_2964, 9, vs2); + setArg(call_sat_vector_imm_vw_2964, 10, sat_vector_imm_vw_2964_arg10); + setArg(call_sat_vector_imm_vw_2964, 11, sat_vector_imm_vw_2964_arg11); + setRet(call_sat_vector_imm_vw_2964, 0, ret_val_sat_vector_imm_vw_2964); } cc.bind(label_merge); } - auto tmp2952 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2952, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2952, 64, false) - , traits::vstart); + auto tmp2967 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2967, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2967, traits::vstart); } cc.bind(label_merge); } @@ -71696,49 +71407,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2953; - x86::Gp ret_val_get_sew_pow_2953 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2953, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2954 = get_reg(cc, 8, false); - mov(cc, tmp2954, 1); + InvokeNode* call_get_sew_pow_2968; + x86::Gp ret_val_get_sew_pow_2968 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2968, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2969 = get_reg(cc, 8, false); + mov(cc, tmp2969, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2954, ret_val_get_sew_pow_2953)), 8, false), ~ 1); - setArg(call_get_sew_pow_2953, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2953, 0, ret_val_get_sew_pow_2953); - InvokeNode* call_get_lmul_pow_2955; - x86::Gp ret_val_get_lmul_pow_2955 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2955, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2955; - setArg(call_get_lmul_pow_2955, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2955, 0, ret_val_get_lmul_pow_2955); + (gen_operation(cc, shl, tmp2969, ret_val_get_sew_pow_2968)), 8, false), ~ 1); + setArg(call_get_sew_pow_2968, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2968, 0, ret_val_get_sew_pow_2968); + InvokeNode* call_get_lmul_pow_2970; + x86::Gp ret_val_get_lmul_pow_2970 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2970, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2970; + setArg(call_get_lmul_pow_2970, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2970, 0, ret_val_get_lmul_pow_2970); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2956; - auto illegal_variable_width_2956_arg2 = SEW_widen; - auto illegal_variable_width_2956_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2956 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2956, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2957; - auto valid_reg_overlap_2957_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2957_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2957 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2957, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2956, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2957))); - setArg(call_illegal_variable_width_2956, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2956, 1, vd); - setArg(call_illegal_variable_width_2956, 2, vm); - setArg(call_illegal_variable_width_2956, 3, illegal_variable_width_2956_arg2); - setArg(call_illegal_variable_width_2956, 4, illegal_variable_width_2956_arg3); - setRet(call_illegal_variable_width_2956, 0, ret_val_illegal_variable_width_2956); - setArg(call_valid_reg_overlap_2957, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2957, 1, vs2); - setArg(call_valid_reg_overlap_2957, 2, vd); - setArg(call_valid_reg_overlap_2957, 3, valid_reg_overlap_2957_arg2); - setArg(call_valid_reg_overlap_2957, 4, valid_reg_overlap_2957_arg3); - setRet(call_valid_reg_overlap_2957, 0, ret_val_valid_reg_overlap_2957); + InvokeNode* call_illegal_variable_width_2971; + auto illegal_variable_width_2971_arg2 = SEW_widen; + auto illegal_variable_width_2971_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2971 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2971, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2972; + auto valid_reg_overlap_2972_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2972_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2972 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2972, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2971, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2972))); + setArg(call_illegal_variable_width_2971, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2971, 1, vd); + setArg(call_illegal_variable_width_2971, 2, vm); + setArg(call_illegal_variable_width_2971, 3, illegal_variable_width_2971_arg2); + setArg(call_illegal_variable_width_2971, 4, illegal_variable_width_2971_arg3); + setRet(call_illegal_variable_width_2971, 0, ret_val_illegal_variable_width_2971); + setArg(call_valid_reg_overlap_2972, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2972, 1, vs2); + setArg(call_valid_reg_overlap_2972, 2, vd); + setArg(call_valid_reg_overlap_2972, 3, valid_reg_overlap_2972_arg2); + setArg(call_valid_reg_overlap_2972, 4, valid_reg_overlap_2972_arg3); + setRet(call_valid_reg_overlap_2972, 0, ret_val_valid_reg_overlap_2972); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71754,44 +71465,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2959; - x86::Gp ret_val_sew_2959 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2959, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_vw_2958; - auto sat_vector_imm_vw_2958_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_vw_2958_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_vw_2958_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_vw_2958_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_vw_2958_arg11 = ret_val_sew_2959; + InvokeNode* call_sew_2974; + x86::Gp ret_val_sew_2974 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2974, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2973; + auto sat_vector_imm_vw_2973_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2973_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2973_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2973_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2973_arg11 = ret_val_sew_2974; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_vw_2958 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_vw_2958, &sat_vector_imm_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_vw_2958, 64, false) - , traits::vxsat); - setArg(call_sew_2959, 0, reinterpret_cast(this)); - setRet(call_sew_2959, 0, ret_val_sew_2959); - setArg(call_sat_vector_imm_vw_2958, 0, V); - setArg(call_sat_vector_imm_vw_2958, 1, 47); - setArg(call_sat_vector_imm_vw_2958, 2, 3); - setArg(call_sat_vector_imm_vw_2958, 3, sat_vector_imm_vw_2958_arg3); - setArg(call_sat_vector_imm_vw_2958, 4, sat_vector_imm_vw_2958_arg4); - setArg(call_sat_vector_imm_vw_2958, 5, sat_vector_imm_vw_2958_arg5); - setArg(call_sat_vector_imm_vw_2958, 6, sat_vector_imm_vw_2958_arg6); - setArg(call_sat_vector_imm_vw_2958, 7, vm); - setArg(call_sat_vector_imm_vw_2958, 8, vd); - setArg(call_sat_vector_imm_vw_2958, 9, vs2); - setArg(call_sat_vector_imm_vw_2958, 10, (int64_t)(uint64_t)simm); - setArg(call_sat_vector_imm_vw_2958, 11, sat_vector_imm_vw_2958_arg11); - setRet(call_sat_vector_imm_vw_2958, 0, ret_val_sat_vector_imm_vw_2958); + x86::Gp ret_val_sat_vector_imm_vw_2973 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2973, &sat_vector_imm_vw, FuncSignature::build()); + auto tmp2975 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_vw_2973, 64, false)); + write_reg_to_mem(jh, tmp2975, traits::vxsat); + setArg(call_sew_2974, 0, reinterpret_cast(this)); + setRet(call_sew_2974, 0, ret_val_sew_2974); + setArg(call_sat_vector_imm_vw_2973, 0, V); + setArg(call_sat_vector_imm_vw_2973, 1, 47); + setArg(call_sat_vector_imm_vw_2973, 2, 3); + setArg(call_sat_vector_imm_vw_2973, 3, sat_vector_imm_vw_2973_arg3); + setArg(call_sat_vector_imm_vw_2973, 4, sat_vector_imm_vw_2973_arg4); + setArg(call_sat_vector_imm_vw_2973, 5, sat_vector_imm_vw_2973_arg5); + setArg(call_sat_vector_imm_vw_2973, 6, sat_vector_imm_vw_2973_arg6); + setArg(call_sat_vector_imm_vw_2973, 7, vm); + setArg(call_sat_vector_imm_vw_2973, 8, vd); + setArg(call_sat_vector_imm_vw_2973, 9, vs2); + setArg(call_sat_vector_imm_vw_2973, 10, (int64_t)(uint64_t)simm); + setArg(call_sat_vector_imm_vw_2973, 11, sat_vector_imm_vw_2973_arg11); + setRet(call_sat_vector_imm_vw_2973, 0, ret_val_sat_vector_imm_vw_2973); } cc.bind(label_merge); } - auto tmp2960 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2960, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2960, 64, false) - , traits::vstart); + auto tmp2976 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2976, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2976, traits::vstart); } cc.bind(label_merge); } @@ -71835,49 +71543,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_2961; - x86::Gp ret_val_get_sew_pow_2961 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2961, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2962 = get_reg(cc, 8, false); - mov(cc, tmp2962, 1); + InvokeNode* call_get_sew_pow_2977; + x86::Gp ret_val_get_sew_pow_2977 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2977, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2978 = get_reg(cc, 8, false); + mov(cc, tmp2978, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2962, ret_val_get_sew_pow_2961)), 8, false), ~ 1); - setArg(call_get_sew_pow_2961, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2961, 0, ret_val_get_sew_pow_2961); - InvokeNode* call_get_lmul_pow_2963; - x86::Gp ret_val_get_lmul_pow_2963 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2963, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2963; - setArg(call_get_lmul_pow_2963, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2963, 0, ret_val_get_lmul_pow_2963); + (gen_operation(cc, shl, tmp2978, ret_val_get_sew_pow_2977)), 8, false), ~ 1); + setArg(call_get_sew_pow_2977, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2977, 0, ret_val_get_sew_pow_2977); + InvokeNode* call_get_lmul_pow_2979; + x86::Gp ret_val_get_lmul_pow_2979 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2979, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2979; + setArg(call_get_lmul_pow_2979, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2979, 0, ret_val_get_lmul_pow_2979); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2964; - auto illegal_variable_width_2964_arg2 = SEW_widen; - auto illegal_variable_width_2964_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2964 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2964, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2965; - auto valid_reg_overlap_2965_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2965_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2965 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2965, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2964, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2965))); - setArg(call_illegal_variable_width_2964, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2964, 1, vd); - setArg(call_illegal_variable_width_2964, 2, vm); - setArg(call_illegal_variable_width_2964, 3, illegal_variable_width_2964_arg2); - setArg(call_illegal_variable_width_2964, 4, illegal_variable_width_2964_arg3); - setRet(call_illegal_variable_width_2964, 0, ret_val_illegal_variable_width_2964); - setArg(call_valid_reg_overlap_2965, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2965, 1, vs2); - setArg(call_valid_reg_overlap_2965, 2, vd); - setArg(call_valid_reg_overlap_2965, 3, valid_reg_overlap_2965_arg2); - setArg(call_valid_reg_overlap_2965, 4, valid_reg_overlap_2965_arg3); - setRet(call_valid_reg_overlap_2965, 0, ret_val_valid_reg_overlap_2965); + InvokeNode* call_illegal_variable_width_2980; + auto illegal_variable_width_2980_arg2 = SEW_widen; + auto illegal_variable_width_2980_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2980 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2980, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2981; + auto valid_reg_overlap_2981_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2981_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2981 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2981, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2980, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2981))); + setArg(call_illegal_variable_width_2980, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2980, 1, vd); + setArg(call_illegal_variable_width_2980, 2, vm); + setArg(call_illegal_variable_width_2980, 3, illegal_variable_width_2980_arg2); + setArg(call_illegal_variable_width_2980, 4, illegal_variable_width_2980_arg3); + setRet(call_illegal_variable_width_2980, 0, ret_val_illegal_variable_width_2980); + setArg(call_valid_reg_overlap_2981, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2981, 1, vs2); + setArg(call_valid_reg_overlap_2981, 2, vd); + setArg(call_valid_reg_overlap_2981, 3, valid_reg_overlap_2981_arg2); + setArg(call_valid_reg_overlap_2981, 4, valid_reg_overlap_2981_arg3); + setRet(call_valid_reg_overlap_2981, 0, ret_val_valid_reg_overlap_2981); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -71893,44 +71601,41 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2967; - x86::Gp ret_val_sew_2967 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2967, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_vector_vw_2966; - auto sat_vector_vector_vw_2966_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_vector_vw_2966_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_vector_vw_2966_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_vector_vw_2966_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_vector_vw_2966_arg11 = ret_val_sew_2967; + InvokeNode* call_sew_2983; + x86::Gp ret_val_sew_2983 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2983, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_vector_vw_2982; + auto sat_vector_vector_vw_2982_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_vector_vw_2982_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_vector_vw_2982_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_vector_vw_2982_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_vector_vw_2982_arg11 = ret_val_sew_2983; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_vector_vw_2966 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_vector_vw_2966, &sat_vector_vector_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_vector_vw_2966, 64, false) - , traits::vxsat); - setArg(call_sew_2967, 0, reinterpret_cast(this)); - setRet(call_sew_2967, 0, ret_val_sew_2967); - setArg(call_sat_vector_vector_vw_2966, 0, V); - setArg(call_sat_vector_vector_vw_2966, 1, 47); - setArg(call_sat_vector_vector_vw_2966, 2, 0); - setArg(call_sat_vector_vector_vw_2966, 3, sat_vector_vector_vw_2966_arg3); - setArg(call_sat_vector_vector_vw_2966, 4, sat_vector_vector_vw_2966_arg4); - setArg(call_sat_vector_vector_vw_2966, 5, sat_vector_vector_vw_2966_arg5); - setArg(call_sat_vector_vector_vw_2966, 6, sat_vector_vector_vw_2966_arg6); - setArg(call_sat_vector_vector_vw_2966, 7, vm); - setArg(call_sat_vector_vector_vw_2966, 8, vd); - setArg(call_sat_vector_vector_vw_2966, 9, vs2); - setArg(call_sat_vector_vector_vw_2966, 10, vs1); - setArg(call_sat_vector_vector_vw_2966, 11, sat_vector_vector_vw_2966_arg11); - setRet(call_sat_vector_vector_vw_2966, 0, ret_val_sat_vector_vector_vw_2966); + x86::Gp ret_val_sat_vector_vector_vw_2982 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_vector_vw_2982, &sat_vector_vector_vw, FuncSignature::build()); + auto tmp2984 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_vector_vw_2982, 64, false)); + write_reg_to_mem(jh, tmp2984, traits::vxsat); + setArg(call_sew_2983, 0, reinterpret_cast(this)); + setRet(call_sew_2983, 0, ret_val_sew_2983); + setArg(call_sat_vector_vector_vw_2982, 0, V); + setArg(call_sat_vector_vector_vw_2982, 1, 47); + setArg(call_sat_vector_vector_vw_2982, 2, 0); + setArg(call_sat_vector_vector_vw_2982, 3, sat_vector_vector_vw_2982_arg3); + setArg(call_sat_vector_vector_vw_2982, 4, sat_vector_vector_vw_2982_arg4); + setArg(call_sat_vector_vector_vw_2982, 5, sat_vector_vector_vw_2982_arg5); + setArg(call_sat_vector_vector_vw_2982, 6, sat_vector_vector_vw_2982_arg6); + setArg(call_sat_vector_vector_vw_2982, 7, vm); + setArg(call_sat_vector_vector_vw_2982, 8, vd); + setArg(call_sat_vector_vector_vw_2982, 9, vs2); + setArg(call_sat_vector_vector_vw_2982, 10, vs1); + setArg(call_sat_vector_vector_vw_2982, 11, sat_vector_vector_vw_2982_arg11); + setRet(call_sat_vector_vector_vw_2982, 0, ret_val_sat_vector_vector_vw_2982); } cc.bind(label_merge); } - auto tmp2968 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2968, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2968, 64, false) - , traits::vstart); + auto tmp2985 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2985, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2985, traits::vstart); } cc.bind(label_merge); } @@ -71978,49 +71683,49 @@ template class vm_impl : public iss::asmjit::vm_base { gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else { - InvokeNode* call_get_sew_pow_2969; - x86::Gp ret_val_get_sew_pow_2969 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_2969, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp2970 = get_reg(cc, 8, false); - mov(cc, tmp2970, 1); + InvokeNode* call_get_sew_pow_2986; + x86::Gp ret_val_get_sew_pow_2986 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_2986, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp2987 = get_reg(cc, 8, false); + mov(cc, tmp2987, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp2970, ret_val_get_sew_pow_2969)), 8, false), ~ 1); - setArg(call_get_sew_pow_2969, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_2969, 0, ret_val_get_sew_pow_2969); - InvokeNode* call_get_lmul_pow_2971; - x86::Gp ret_val_get_lmul_pow_2971 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_2971, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_2971; - setArg(call_get_lmul_pow_2971, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_2971, 0, ret_val_get_lmul_pow_2971); + (gen_operation(cc, shl, tmp2987, ret_val_get_sew_pow_2986)), 8, false), ~ 1); + setArg(call_get_sew_pow_2986, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_2986, 0, ret_val_get_sew_pow_2986); + InvokeNode* call_get_lmul_pow_2988; + x86::Gp ret_val_get_lmul_pow_2988 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_2988, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_2988; + setArg(call_get_lmul_pow_2988, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_2988, 0, ret_val_get_lmul_pow_2988); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_variable_width_2972; - auto illegal_variable_width_2972_arg2 = SEW_widen; - auto illegal_variable_width_2972_arg3 = LMUL_pow_widen; - x86::Gp ret_val_illegal_variable_width_2972 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_variable_width_2972, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_2973; - auto valid_reg_overlap_2973_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_2973_arg3 = LMUL_pow; - x86::Gp ret_val_valid_reg_overlap_2973 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_2973, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2972, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2973))); - setArg(call_illegal_variable_width_2972, 0, reinterpret_cast(this)); - setArg(call_illegal_variable_width_2972, 1, vd); - setArg(call_illegal_variable_width_2972, 2, vm); - setArg(call_illegal_variable_width_2972, 3, illegal_variable_width_2972_arg2); - setArg(call_illegal_variable_width_2972, 4, illegal_variable_width_2972_arg3); - setRet(call_illegal_variable_width_2972, 0, ret_val_illegal_variable_width_2972); - setArg(call_valid_reg_overlap_2973, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_2973, 1, vs2); - setArg(call_valid_reg_overlap_2973, 2, vd); - setArg(call_valid_reg_overlap_2973, 3, valid_reg_overlap_2973_arg2); - setArg(call_valid_reg_overlap_2973, 4, valid_reg_overlap_2973_arg3); - setRet(call_valid_reg_overlap_2973, 0, ret_val_valid_reg_overlap_2973); + InvokeNode* call_illegal_variable_width_2989; + auto illegal_variable_width_2989_arg2 = SEW_widen; + auto illegal_variable_width_2989_arg3 = LMUL_pow_widen; + x86::Gp ret_val_illegal_variable_width_2989 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_variable_width_2989, (uintptr_t)&vm_impl::_illegal_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_2990; + auto valid_reg_overlap_2990_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_2990_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_2990 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_2990, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_variable_width_2989, gen_operation(cc, lnot, (ret_val_valid_reg_overlap_2990))); + setArg(call_illegal_variable_width_2989, 0, reinterpret_cast(this)); + setArg(call_illegal_variable_width_2989, 1, vd); + setArg(call_illegal_variable_width_2989, 2, vm); + setArg(call_illegal_variable_width_2989, 3, illegal_variable_width_2989_arg2); + setArg(call_illegal_variable_width_2989, 4, illegal_variable_width_2989_arg3); + setRet(call_illegal_variable_width_2989, 0, ret_val_illegal_variable_width_2989); + setArg(call_valid_reg_overlap_2990, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_2990, 1, vs2); + setArg(call_valid_reg_overlap_2990, 2, vd); + setArg(call_valid_reg_overlap_2990, 3, valid_reg_overlap_2990_arg2); + setArg(call_valid_reg_overlap_2990, 4, valid_reg_overlap_2990_arg3); + setRet(call_valid_reg_overlap_2990, 0, ret_val_valid_reg_overlap_2990); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72036,47 +71741,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2975; - x86::Gp ret_val_sew_2975 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2975, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_sat_vector_imm_vw_2974; - auto sat_vector_imm_vw_2974_arg3 = load_reg_from_mem(jh, traits::vl); - auto sat_vector_imm_vw_2974_arg4 = load_reg_from_mem(jh, traits::vstart); - auto sat_vector_imm_vw_2974_arg5 = load_reg_from_mem(jh, traits::vtype); - auto sat_vector_imm_vw_2974_arg6 = load_reg_from_mem(jh, traits::vxrm); - auto sat_vector_imm_vw_2974_arg10 = gen_ext(cc, + InvokeNode* call_sew_2992; + x86::Gp ret_val_sew_2992 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2992, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_sat_vector_imm_vw_2991; + auto sat_vector_imm_vw_2991_arg3 = load_reg_from_mem(jh, traits::vl); + auto sat_vector_imm_vw_2991_arg4 = load_reg_from_mem(jh, traits::vstart); + auto sat_vector_imm_vw_2991_arg5 = load_reg_from_mem(jh, traits::vtype); + auto sat_vector_imm_vw_2991_arg6 = load_reg_from_mem(jh, traits::vxrm); + auto sat_vector_imm_vw_2991_arg10 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, false); - auto sat_vector_imm_vw_2974_arg11 = ret_val_sew_2975; + auto sat_vector_imm_vw_2991_arg11 = ret_val_sew_2992; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_sat_vector_imm_vw_2974 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sat_vector_imm_vw_2974, &sat_vector_imm_vw, FuncSignature::build()); - write_reg_to_mem(jh, - gen_ext(cc, ret_val_sat_vector_imm_vw_2974, 64, false) - , traits::vxsat); - setArg(call_sew_2975, 0, reinterpret_cast(this)); - setRet(call_sew_2975, 0, ret_val_sew_2975); - setArg(call_sat_vector_imm_vw_2974, 0, V); - setArg(call_sat_vector_imm_vw_2974, 1, 47); - setArg(call_sat_vector_imm_vw_2974, 2, 4); - setArg(call_sat_vector_imm_vw_2974, 3, sat_vector_imm_vw_2974_arg3); - setArg(call_sat_vector_imm_vw_2974, 4, sat_vector_imm_vw_2974_arg4); - setArg(call_sat_vector_imm_vw_2974, 5, sat_vector_imm_vw_2974_arg5); - setArg(call_sat_vector_imm_vw_2974, 6, sat_vector_imm_vw_2974_arg6); - setArg(call_sat_vector_imm_vw_2974, 7, vm); - setArg(call_sat_vector_imm_vw_2974, 8, vd); - setArg(call_sat_vector_imm_vw_2974, 9, vs2); - setArg(call_sat_vector_imm_vw_2974, 10, sat_vector_imm_vw_2974_arg10); - setArg(call_sat_vector_imm_vw_2974, 11, sat_vector_imm_vw_2974_arg11); - setRet(call_sat_vector_imm_vw_2974, 0, ret_val_sat_vector_imm_vw_2974); + x86::Gp ret_val_sat_vector_imm_vw_2991 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sat_vector_imm_vw_2991, &sat_vector_imm_vw, FuncSignature::build()); + auto tmp2993 = gen_operation(cc, bor, load_reg_from_mem(jh, traits::vxsat), gen_ext(cc, ret_val_sat_vector_imm_vw_2991, 64, false)); + write_reg_to_mem(jh, tmp2993, traits::vxsat); + setArg(call_sew_2992, 0, reinterpret_cast(this)); + setRet(call_sew_2992, 0, ret_val_sew_2992); + setArg(call_sat_vector_imm_vw_2991, 0, V); + setArg(call_sat_vector_imm_vw_2991, 1, 47); + setArg(call_sat_vector_imm_vw_2991, 2, 4); + setArg(call_sat_vector_imm_vw_2991, 3, sat_vector_imm_vw_2991_arg3); + setArg(call_sat_vector_imm_vw_2991, 4, sat_vector_imm_vw_2991_arg4); + setArg(call_sat_vector_imm_vw_2991, 5, sat_vector_imm_vw_2991_arg5); + setArg(call_sat_vector_imm_vw_2991, 6, sat_vector_imm_vw_2991_arg6); + setArg(call_sat_vector_imm_vw_2991, 7, vm); + setArg(call_sat_vector_imm_vw_2991, 8, vd); + setArg(call_sat_vector_imm_vw_2991, 9, vs2); + setArg(call_sat_vector_imm_vw_2991, 10, sat_vector_imm_vw_2991_arg10); + setArg(call_sat_vector_imm_vw_2991, 11, sat_vector_imm_vw_2991_arg11); + setRet(call_sat_vector_imm_vw_2991, 0, ret_val_sat_vector_imm_vw_2991); } cc.bind(label_merge); } - auto tmp2976 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2976, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2976, 64, false) - , traits::vstart); + auto tmp2994 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2994, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2994, traits::vstart); } cc.bind(label_merge); } @@ -72123,12 +71825,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2977; - x86::Gp ret_val_illegal_reduction_2977 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2977, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2977; - setArg(call_illegal_reduction_2977, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2977, 0, ret_val_illegal_reduction_2977); + InvokeNode* call_illegal_reduction_2995; + x86::Gp ret_val_illegal_reduction_2995 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2995, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2995; + setArg(call_illegal_reduction_2995, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2995, 0, ret_val_illegal_reduction_2995); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72144,37 +71846,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2979; - x86::Gp ret_val_sew_2979 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2979, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2978; - auto vector_red_op_2978_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2978_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2978_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2978_arg10 = ret_val_sew_2979; + InvokeNode* call_sew_2997; + x86::Gp ret_val_sew_2997 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_2997, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_2996; + auto vector_red_op_2996_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_2996_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_2996_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_2996_arg10 = ret_val_sew_2997; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2978, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2979, 0, reinterpret_cast(this)); - setRet(call_sew_2979, 0, ret_val_sew_2979); - setArg(call_vector_red_op_2978, 0, V); - setArg(call_vector_red_op_2978, 1, 0); - setArg(call_vector_red_op_2978, 2, 2); - setArg(call_vector_red_op_2978, 3, vector_red_op_2978_arg3); - setArg(call_vector_red_op_2978, 4, vector_red_op_2978_arg4); - setArg(call_vector_red_op_2978, 5, vector_red_op_2978_arg5); - setArg(call_vector_red_op_2978, 6, vm); - setArg(call_vector_red_op_2978, 7, vd); - setArg(call_vector_red_op_2978, 8, vs2); - setArg(call_vector_red_op_2978, 9, vs1); - setArg(call_vector_red_op_2978, 10, vector_red_op_2978_arg10); + cc.invoke(&call_vector_red_op_2996, &vector_red_op, FuncSignature::build()); + setArg(call_sew_2997, 0, reinterpret_cast(this)); + setRet(call_sew_2997, 0, ret_val_sew_2997); + setArg(call_vector_red_op_2996, 0, V); + setArg(call_vector_red_op_2996, 1, 0); + setArg(call_vector_red_op_2996, 2, 2); + setArg(call_vector_red_op_2996, 3, vector_red_op_2996_arg3); + setArg(call_vector_red_op_2996, 4, vector_red_op_2996_arg4); + setArg(call_vector_red_op_2996, 5, vector_red_op_2996_arg5); + setArg(call_vector_red_op_2996, 6, vm); + setArg(call_vector_red_op_2996, 7, vd); + setArg(call_vector_red_op_2996, 8, vs2); + setArg(call_vector_red_op_2996, 9, vs1); + setArg(call_vector_red_op_2996, 10, vector_red_op_2996_arg10); } cc.bind(label_merge); } - auto tmp2980 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2980, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2980, 64, false) - , traits::vstart); + auto tmp2998 = get_reg_Gp(cc, 64, false); + mov(cc, tmp2998, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp2998, traits::vstart); } cc.bind(label_merge); } @@ -72220,12 +71920,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2981; - x86::Gp ret_val_illegal_reduction_2981 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2981, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2981; - setArg(call_illegal_reduction_2981, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2981, 0, ret_val_illegal_reduction_2981); + InvokeNode* call_illegal_reduction_2999; + x86::Gp ret_val_illegal_reduction_2999 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_2999, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_2999; + setArg(call_illegal_reduction_2999, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_2999, 0, ret_val_illegal_reduction_2999); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72241,37 +71941,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2983; - x86::Gp ret_val_sew_2983 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2983, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2982; - auto vector_red_op_2982_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2982_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2982_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2982_arg10 = ret_val_sew_2983; + InvokeNode* call_sew_3001; + x86::Gp ret_val_sew_3001 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3001, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_3000; + auto vector_red_op_3000_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_3000_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_3000_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_3000_arg10 = ret_val_sew_3001; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2982, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2983, 0, reinterpret_cast(this)); - setRet(call_sew_2983, 0, ret_val_sew_2983); - setArg(call_vector_red_op_2982, 0, V); - setArg(call_vector_red_op_2982, 1, 6); - setArg(call_vector_red_op_2982, 2, 2); - setArg(call_vector_red_op_2982, 3, vector_red_op_2982_arg3); - setArg(call_vector_red_op_2982, 4, vector_red_op_2982_arg4); - setArg(call_vector_red_op_2982, 5, vector_red_op_2982_arg5); - setArg(call_vector_red_op_2982, 6, vm); - setArg(call_vector_red_op_2982, 7, vd); - setArg(call_vector_red_op_2982, 8, vs2); - setArg(call_vector_red_op_2982, 9, vs1); - setArg(call_vector_red_op_2982, 10, vector_red_op_2982_arg10); + cc.invoke(&call_vector_red_op_3000, &vector_red_op, FuncSignature::build()); + setArg(call_sew_3001, 0, reinterpret_cast(this)); + setRet(call_sew_3001, 0, ret_val_sew_3001); + setArg(call_vector_red_op_3000, 0, V); + setArg(call_vector_red_op_3000, 1, 6); + setArg(call_vector_red_op_3000, 2, 2); + setArg(call_vector_red_op_3000, 3, vector_red_op_3000_arg3); + setArg(call_vector_red_op_3000, 4, vector_red_op_3000_arg4); + setArg(call_vector_red_op_3000, 5, vector_red_op_3000_arg5); + setArg(call_vector_red_op_3000, 6, vm); + setArg(call_vector_red_op_3000, 7, vd); + setArg(call_vector_red_op_3000, 8, vs2); + setArg(call_vector_red_op_3000, 9, vs1); + setArg(call_vector_red_op_3000, 10, vector_red_op_3000_arg10); } cc.bind(label_merge); } - auto tmp2984 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2984, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2984, 64, false) - , traits::vstart); + auto tmp3002 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3002, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3002, traits::vstart); } cc.bind(label_merge); } @@ -72317,12 +72015,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2985; - x86::Gp ret_val_illegal_reduction_2985 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2985, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2985; - setArg(call_illegal_reduction_2985, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2985, 0, ret_val_illegal_reduction_2985); + InvokeNode* call_illegal_reduction_3003; + x86::Gp ret_val_illegal_reduction_3003 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_3003, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_3003; + setArg(call_illegal_reduction_3003, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_3003, 0, ret_val_illegal_reduction_3003); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72338,37 +72036,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2987; - x86::Gp ret_val_sew_2987 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2987, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2986; - auto vector_red_op_2986_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2986_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2986_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2986_arg10 = ret_val_sew_2987; + InvokeNode* call_sew_3005; + x86::Gp ret_val_sew_3005 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3005, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_3004; + auto vector_red_op_3004_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_3004_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_3004_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_3004_arg10 = ret_val_sew_3005; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2986, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2987, 0, reinterpret_cast(this)); - setRet(call_sew_2987, 0, ret_val_sew_2987); - setArg(call_vector_red_op_2986, 0, V); - setArg(call_vector_red_op_2986, 1, 7); - setArg(call_vector_red_op_2986, 2, 2); - setArg(call_vector_red_op_2986, 3, vector_red_op_2986_arg3); - setArg(call_vector_red_op_2986, 4, vector_red_op_2986_arg4); - setArg(call_vector_red_op_2986, 5, vector_red_op_2986_arg5); - setArg(call_vector_red_op_2986, 6, vm); - setArg(call_vector_red_op_2986, 7, vd); - setArg(call_vector_red_op_2986, 8, vs2); - setArg(call_vector_red_op_2986, 9, vs1); - setArg(call_vector_red_op_2986, 10, vector_red_op_2986_arg10); + cc.invoke(&call_vector_red_op_3004, &vector_red_op, FuncSignature::build()); + setArg(call_sew_3005, 0, reinterpret_cast(this)); + setRet(call_sew_3005, 0, ret_val_sew_3005); + setArg(call_vector_red_op_3004, 0, V); + setArg(call_vector_red_op_3004, 1, 7); + setArg(call_vector_red_op_3004, 2, 2); + setArg(call_vector_red_op_3004, 3, vector_red_op_3004_arg3); + setArg(call_vector_red_op_3004, 4, vector_red_op_3004_arg4); + setArg(call_vector_red_op_3004, 5, vector_red_op_3004_arg5); + setArg(call_vector_red_op_3004, 6, vm); + setArg(call_vector_red_op_3004, 7, vd); + setArg(call_vector_red_op_3004, 8, vs2); + setArg(call_vector_red_op_3004, 9, vs1); + setArg(call_vector_red_op_3004, 10, vector_red_op_3004_arg10); } cc.bind(label_merge); } - auto tmp2988 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2988, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2988, 64, false) - , traits::vstart); + auto tmp3006 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3006, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3006, traits::vstart); } cc.bind(label_merge); } @@ -72414,12 +72110,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2989; - x86::Gp ret_val_illegal_reduction_2989 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2989, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2989; - setArg(call_illegal_reduction_2989, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2989, 0, ret_val_illegal_reduction_2989); + InvokeNode* call_illegal_reduction_3007; + x86::Gp ret_val_illegal_reduction_3007 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_3007, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_3007; + setArg(call_illegal_reduction_3007, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_3007, 0, ret_val_illegal_reduction_3007); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72435,37 +72131,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2991; - x86::Gp ret_val_sew_2991 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2991, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2990; - auto vector_red_op_2990_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2990_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2990_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2990_arg10 = ret_val_sew_2991; + InvokeNode* call_sew_3009; + x86::Gp ret_val_sew_3009 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3009, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_3008; + auto vector_red_op_3008_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_3008_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_3008_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_3008_arg10 = ret_val_sew_3009; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2990, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2991, 0, reinterpret_cast(this)); - setRet(call_sew_2991, 0, ret_val_sew_2991); - setArg(call_vector_red_op_2990, 0, V); - setArg(call_vector_red_op_2990, 1, 4); - setArg(call_vector_red_op_2990, 2, 2); - setArg(call_vector_red_op_2990, 3, vector_red_op_2990_arg3); - setArg(call_vector_red_op_2990, 4, vector_red_op_2990_arg4); - setArg(call_vector_red_op_2990, 5, vector_red_op_2990_arg5); - setArg(call_vector_red_op_2990, 6, vm); - setArg(call_vector_red_op_2990, 7, vd); - setArg(call_vector_red_op_2990, 8, vs2); - setArg(call_vector_red_op_2990, 9, vs1); - setArg(call_vector_red_op_2990, 10, vector_red_op_2990_arg10); + cc.invoke(&call_vector_red_op_3008, &vector_red_op, FuncSignature::build()); + setArg(call_sew_3009, 0, reinterpret_cast(this)); + setRet(call_sew_3009, 0, ret_val_sew_3009); + setArg(call_vector_red_op_3008, 0, V); + setArg(call_vector_red_op_3008, 1, 4); + setArg(call_vector_red_op_3008, 2, 2); + setArg(call_vector_red_op_3008, 3, vector_red_op_3008_arg3); + setArg(call_vector_red_op_3008, 4, vector_red_op_3008_arg4); + setArg(call_vector_red_op_3008, 5, vector_red_op_3008_arg5); + setArg(call_vector_red_op_3008, 6, vm); + setArg(call_vector_red_op_3008, 7, vd); + setArg(call_vector_red_op_3008, 8, vs2); + setArg(call_vector_red_op_3008, 9, vs1); + setArg(call_vector_red_op_3008, 10, vector_red_op_3008_arg10); } cc.bind(label_merge); } - auto tmp2992 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2992, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2992, 64, false) - , traits::vstart); + auto tmp3010 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3010, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3010, traits::vstart); } cc.bind(label_merge); } @@ -72511,12 +72205,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2993; - x86::Gp ret_val_illegal_reduction_2993 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2993, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2993; - setArg(call_illegal_reduction_2993, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2993, 0, ret_val_illegal_reduction_2993); + InvokeNode* call_illegal_reduction_3011; + x86::Gp ret_val_illegal_reduction_3011 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_3011, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_3011; + setArg(call_illegal_reduction_3011, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_3011, 0, ret_val_illegal_reduction_3011); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72532,37 +72226,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2995; - x86::Gp ret_val_sew_2995 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2995, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2994; - auto vector_red_op_2994_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2994_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2994_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2994_arg10 = ret_val_sew_2995; + InvokeNode* call_sew_3013; + x86::Gp ret_val_sew_3013 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3013, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_3012; + auto vector_red_op_3012_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_3012_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_3012_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_3012_arg10 = ret_val_sew_3013; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2994, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2995, 0, reinterpret_cast(this)); - setRet(call_sew_2995, 0, ret_val_sew_2995); - setArg(call_vector_red_op_2994, 0, V); - setArg(call_vector_red_op_2994, 1, 5); - setArg(call_vector_red_op_2994, 2, 2); - setArg(call_vector_red_op_2994, 3, vector_red_op_2994_arg3); - setArg(call_vector_red_op_2994, 4, vector_red_op_2994_arg4); - setArg(call_vector_red_op_2994, 5, vector_red_op_2994_arg5); - setArg(call_vector_red_op_2994, 6, vm); - setArg(call_vector_red_op_2994, 7, vd); - setArg(call_vector_red_op_2994, 8, vs2); - setArg(call_vector_red_op_2994, 9, vs1); - setArg(call_vector_red_op_2994, 10, vector_red_op_2994_arg10); + cc.invoke(&call_vector_red_op_3012, &vector_red_op, FuncSignature::build()); + setArg(call_sew_3013, 0, reinterpret_cast(this)); + setRet(call_sew_3013, 0, ret_val_sew_3013); + setArg(call_vector_red_op_3012, 0, V); + setArg(call_vector_red_op_3012, 1, 5); + setArg(call_vector_red_op_3012, 2, 2); + setArg(call_vector_red_op_3012, 3, vector_red_op_3012_arg3); + setArg(call_vector_red_op_3012, 4, vector_red_op_3012_arg4); + setArg(call_vector_red_op_3012, 5, vector_red_op_3012_arg5); + setArg(call_vector_red_op_3012, 6, vm); + setArg(call_vector_red_op_3012, 7, vd); + setArg(call_vector_red_op_3012, 8, vs2); + setArg(call_vector_red_op_3012, 9, vs1); + setArg(call_vector_red_op_3012, 10, vector_red_op_3012_arg10); } cc.bind(label_merge); } - auto tmp2996 = get_reg_Gp(cc, 8, false); - mov(cc, tmp2996, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp2996, 64, false) - , traits::vstart); + auto tmp3014 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3014, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3014, traits::vstart); } cc.bind(label_merge); } @@ -72608,12 +72300,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_2997; - x86::Gp ret_val_illegal_reduction_2997 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_2997, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_2997; - setArg(call_illegal_reduction_2997, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_2997, 0, ret_val_illegal_reduction_2997); + InvokeNode* call_illegal_reduction_3015; + x86::Gp ret_val_illegal_reduction_3015 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_3015, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_3015; + setArg(call_illegal_reduction_3015, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_3015, 0, ret_val_illegal_reduction_3015); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72629,37 +72321,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_2999; - x86::Gp ret_val_sew_2999 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_2999, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_2998; - auto vector_red_op_2998_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_2998_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_2998_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_2998_arg10 = ret_val_sew_2999; + InvokeNode* call_sew_3017; + x86::Gp ret_val_sew_3017 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3017, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_3016; + auto vector_red_op_3016_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_3016_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_3016_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_3016_arg10 = ret_val_sew_3017; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_2998, &vector_red_op, FuncSignature::build()); - setArg(call_sew_2999, 0, reinterpret_cast(this)); - setRet(call_sew_2999, 0, ret_val_sew_2999); - setArg(call_vector_red_op_2998, 0, V); - setArg(call_vector_red_op_2998, 1, 1); - setArg(call_vector_red_op_2998, 2, 2); - setArg(call_vector_red_op_2998, 3, vector_red_op_2998_arg3); - setArg(call_vector_red_op_2998, 4, vector_red_op_2998_arg4); - setArg(call_vector_red_op_2998, 5, vector_red_op_2998_arg5); - setArg(call_vector_red_op_2998, 6, vm); - setArg(call_vector_red_op_2998, 7, vd); - setArg(call_vector_red_op_2998, 8, vs2); - setArg(call_vector_red_op_2998, 9, vs1); - setArg(call_vector_red_op_2998, 10, vector_red_op_2998_arg10); + cc.invoke(&call_vector_red_op_3016, &vector_red_op, FuncSignature::build()); + setArg(call_sew_3017, 0, reinterpret_cast(this)); + setRet(call_sew_3017, 0, ret_val_sew_3017); + setArg(call_vector_red_op_3016, 0, V); + setArg(call_vector_red_op_3016, 1, 1); + setArg(call_vector_red_op_3016, 2, 2); + setArg(call_vector_red_op_3016, 3, vector_red_op_3016_arg3); + setArg(call_vector_red_op_3016, 4, vector_red_op_3016_arg4); + setArg(call_vector_red_op_3016, 5, vector_red_op_3016_arg5); + setArg(call_vector_red_op_3016, 6, vm); + setArg(call_vector_red_op_3016, 7, vd); + setArg(call_vector_red_op_3016, 8, vs2); + setArg(call_vector_red_op_3016, 9, vs1); + setArg(call_vector_red_op_3016, 10, vector_red_op_3016_arg10); } cc.bind(label_merge); } - auto tmp3000 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3000, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3000, 64, false) - , traits::vstart); + auto tmp3018 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3018, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3018, traits::vstart); } cc.bind(label_merge); } @@ -72705,12 +72395,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_3001; - x86::Gp ret_val_illegal_reduction_3001 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_3001, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_3001; - setArg(call_illegal_reduction_3001, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_3001, 0, ret_val_illegal_reduction_3001); + InvokeNode* call_illegal_reduction_3019; + x86::Gp ret_val_illegal_reduction_3019 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_3019, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_3019; + setArg(call_illegal_reduction_3019, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_3019, 0, ret_val_illegal_reduction_3019); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72726,37 +72416,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3003; - x86::Gp ret_val_sew_3003 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3003, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_3002; - auto vector_red_op_3002_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_3002_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_3002_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_3002_arg10 = ret_val_sew_3003; + InvokeNode* call_sew_3021; + x86::Gp ret_val_sew_3021 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3021, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_3020; + auto vector_red_op_3020_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_3020_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_3020_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_3020_arg10 = ret_val_sew_3021; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_3002, &vector_red_op, FuncSignature::build()); - setArg(call_sew_3003, 0, reinterpret_cast(this)); - setRet(call_sew_3003, 0, ret_val_sew_3003); - setArg(call_vector_red_op_3002, 0, V); - setArg(call_vector_red_op_3002, 1, 2); - setArg(call_vector_red_op_3002, 2, 2); - setArg(call_vector_red_op_3002, 3, vector_red_op_3002_arg3); - setArg(call_vector_red_op_3002, 4, vector_red_op_3002_arg4); - setArg(call_vector_red_op_3002, 5, vector_red_op_3002_arg5); - setArg(call_vector_red_op_3002, 6, vm); - setArg(call_vector_red_op_3002, 7, vd); - setArg(call_vector_red_op_3002, 8, vs2); - setArg(call_vector_red_op_3002, 9, vs1); - setArg(call_vector_red_op_3002, 10, vector_red_op_3002_arg10); + cc.invoke(&call_vector_red_op_3020, &vector_red_op, FuncSignature::build()); + setArg(call_sew_3021, 0, reinterpret_cast(this)); + setRet(call_sew_3021, 0, ret_val_sew_3021); + setArg(call_vector_red_op_3020, 0, V); + setArg(call_vector_red_op_3020, 1, 2); + setArg(call_vector_red_op_3020, 2, 2); + setArg(call_vector_red_op_3020, 3, vector_red_op_3020_arg3); + setArg(call_vector_red_op_3020, 4, vector_red_op_3020_arg4); + setArg(call_vector_red_op_3020, 5, vector_red_op_3020_arg5); + setArg(call_vector_red_op_3020, 6, vm); + setArg(call_vector_red_op_3020, 7, vd); + setArg(call_vector_red_op_3020, 8, vs2); + setArg(call_vector_red_op_3020, 9, vs1); + setArg(call_vector_red_op_3020, 10, vector_red_op_3020_arg10); } cc.bind(label_merge); } - auto tmp3004 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3004, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3004, 64, false) - , traits::vstart); + auto tmp3022 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3022, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3022, traits::vstart); } cc.bind(label_merge); } @@ -72802,12 +72490,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_3005; - x86::Gp ret_val_illegal_reduction_3005 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_3005, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_3005; - setArg(call_illegal_reduction_3005, 0, reinterpret_cast(this)); - setRet(call_illegal_reduction_3005, 0, ret_val_illegal_reduction_3005); + InvokeNode* call_illegal_reduction_3023; + x86::Gp ret_val_illegal_reduction_3023 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_3023, (uintptr_t)&vm_impl::_illegal_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_3023; + setArg(call_illegal_reduction_3023, 0, reinterpret_cast(this)); + setRet(call_illegal_reduction_3023, 0, ret_val_illegal_reduction_3023); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72823,37 +72511,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3007; - x86::Gp ret_val_sew_3007 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3007, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_op_3006; - auto vector_red_op_3006_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_op_3006_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_op_3006_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_op_3006_arg10 = ret_val_sew_3007; + InvokeNode* call_sew_3025; + x86::Gp ret_val_sew_3025 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3025, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_op_3024; + auto vector_red_op_3024_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_op_3024_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_op_3024_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_op_3024_arg10 = ret_val_sew_3025; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_op_3006, &vector_red_op, FuncSignature::build()); - setArg(call_sew_3007, 0, reinterpret_cast(this)); - setRet(call_sew_3007, 0, ret_val_sew_3007); - setArg(call_vector_red_op_3006, 0, V); - setArg(call_vector_red_op_3006, 1, 3); - setArg(call_vector_red_op_3006, 2, 2); - setArg(call_vector_red_op_3006, 3, vector_red_op_3006_arg3); - setArg(call_vector_red_op_3006, 4, vector_red_op_3006_arg4); - setArg(call_vector_red_op_3006, 5, vector_red_op_3006_arg5); - setArg(call_vector_red_op_3006, 6, vm); - setArg(call_vector_red_op_3006, 7, vd); - setArg(call_vector_red_op_3006, 8, vs2); - setArg(call_vector_red_op_3006, 9, vs1); - setArg(call_vector_red_op_3006, 10, vector_red_op_3006_arg10); + cc.invoke(&call_vector_red_op_3024, &vector_red_op, FuncSignature::build()); + setArg(call_sew_3025, 0, reinterpret_cast(this)); + setRet(call_sew_3025, 0, ret_val_sew_3025); + setArg(call_vector_red_op_3024, 0, V); + setArg(call_vector_red_op_3024, 1, 3); + setArg(call_vector_red_op_3024, 2, 2); + setArg(call_vector_red_op_3024, 3, vector_red_op_3024_arg3); + setArg(call_vector_red_op_3024, 4, vector_red_op_3024_arg4); + setArg(call_vector_red_op_3024, 5, vector_red_op_3024_arg5); + setArg(call_vector_red_op_3024, 6, vm); + setArg(call_vector_red_op_3024, 7, vd); + setArg(call_vector_red_op_3024, 8, vs2); + setArg(call_vector_red_op_3024, 9, vs1); + setArg(call_vector_red_op_3024, 10, vector_red_op_3024_arg10); } cc.bind(label_merge); } - auto tmp3008 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3008, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3008, 64, false) - , traits::vstart); + auto tmp3026 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3026, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3026, traits::vstart); } cc.bind(label_merge); } @@ -72897,36 +72583,27 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3009; - x86::Gp ret_val_get_sew_pow_3009 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3009, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3010 = get_reg(cc, 8, false); - mov(cc, tmp3010, 1); + InvokeNode* call_get_sew_pow_3027; + x86::Gp ret_val_get_sew_pow_3027 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3027, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3028 = get_reg(cc, 8, false); + mov(cc, tmp3028, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3010, ret_val_get_sew_pow_3009)), 8, false), ~ 1); - setArg(call_get_sew_pow_3009, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3009, 0, ret_val_get_sew_pow_3009); - InvokeNode* call_get_lmul_pow_3011; - x86::Gp ret_val_get_lmul_pow_3011 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3011, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3011; - setArg(call_get_lmul_pow_3011, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3011, 0, ret_val_get_lmul_pow_3011); + (gen_operation(cc, shl, tmp3028, ret_val_get_sew_pow_3027)), 8, false), ~ 1); + setArg(call_get_sew_pow_3027, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3027, 0, ret_val_get_sew_pow_3027); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); - auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_widen_3012; - auto illegal_reduction_widen_3012_arg0 = SEW_widen; - auto illegal_reduction_widen_3012_arg1 = LMUL_pow_widen; - x86::Gp ret_val_illegal_reduction_widen_3012 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_widen_3012, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_widen_3012; - setArg(call_illegal_reduction_widen_3012, 0, reinterpret_cast(this)); - setArg(call_illegal_reduction_widen_3012, 1, illegal_reduction_widen_3012_arg0); - setArg(call_illegal_reduction_widen_3012, 2, illegal_reduction_widen_3012_arg1); - setRet(call_illegal_reduction_widen_3012, 0, ret_val_illegal_reduction_widen_3012); + InvokeNode* call_illegal_reduction_widen_3029; + auto illegal_reduction_widen_3029_arg0 = SEW_widen; + x86::Gp ret_val_illegal_reduction_widen_3029 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_widen_3029, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_widen_3029; + setArg(call_illegal_reduction_widen_3029, 0, reinterpret_cast(this)); + setArg(call_illegal_reduction_widen_3029, 1, illegal_reduction_widen_3029_arg0); + setRet(call_illegal_reduction_widen_3029, 0, ret_val_illegal_reduction_widen_3029); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -72942,37 +72619,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3014; - x86::Gp ret_val_sew_3014 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3014, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_wv_3013; - auto vector_red_wv_3013_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_wv_3013_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_wv_3013_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_wv_3013_arg10 = ret_val_sew_3014; + InvokeNode* call_sew_3031; + x86::Gp ret_val_sew_3031 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3031, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_wv_3030; + auto vector_red_wv_3030_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_wv_3030_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_wv_3030_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_wv_3030_arg10 = ret_val_sew_3031; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_wv_3013, &vector_red_wv, FuncSignature::build()); - setArg(call_sew_3014, 0, reinterpret_cast(this)); - setRet(call_sew_3014, 0, ret_val_sew_3014); - setArg(call_vector_red_wv_3013, 0, V); - setArg(call_vector_red_wv_3013, 1, 48); - setArg(call_vector_red_wv_3013, 2, 0); - setArg(call_vector_red_wv_3013, 3, vector_red_wv_3013_arg3); - setArg(call_vector_red_wv_3013, 4, vector_red_wv_3013_arg4); - setArg(call_vector_red_wv_3013, 5, vector_red_wv_3013_arg5); - setArg(call_vector_red_wv_3013, 6, vm); - setArg(call_vector_red_wv_3013, 7, vd); - setArg(call_vector_red_wv_3013, 8, vs2); - setArg(call_vector_red_wv_3013, 9, vs1); - setArg(call_vector_red_wv_3013, 10, vector_red_wv_3013_arg10); + cc.invoke(&call_vector_red_wv_3030, &vector_red_wv, FuncSignature::build()); + setArg(call_sew_3031, 0, reinterpret_cast(this)); + setRet(call_sew_3031, 0, ret_val_sew_3031); + setArg(call_vector_red_wv_3030, 0, V); + setArg(call_vector_red_wv_3030, 1, 48); + setArg(call_vector_red_wv_3030, 2, 0); + setArg(call_vector_red_wv_3030, 3, vector_red_wv_3030_arg3); + setArg(call_vector_red_wv_3030, 4, vector_red_wv_3030_arg4); + setArg(call_vector_red_wv_3030, 5, vector_red_wv_3030_arg5); + setArg(call_vector_red_wv_3030, 6, vm); + setArg(call_vector_red_wv_3030, 7, vd); + setArg(call_vector_red_wv_3030, 8, vs2); + setArg(call_vector_red_wv_3030, 9, vs1); + setArg(call_vector_red_wv_3030, 10, vector_red_wv_3030_arg10); } cc.bind(label_merge); } - auto tmp3015 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3015, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3015, 64, false) - , traits::vstart); + auto tmp3032 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3032, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3032, traits::vstart); } cc.bind(label_merge); } @@ -73016,36 +72691,27 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3016; - x86::Gp ret_val_get_sew_pow_3016 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3016, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3017 = get_reg(cc, 8, false); - mov(cc, tmp3017, 1); + InvokeNode* call_get_sew_pow_3033; + x86::Gp ret_val_get_sew_pow_3033 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3033, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3034 = get_reg(cc, 8, false); + mov(cc, tmp3034, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3017, ret_val_get_sew_pow_3016)), 8, false), ~ 1); - setArg(call_get_sew_pow_3016, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3016, 0, ret_val_get_sew_pow_3016); - InvokeNode* call_get_lmul_pow_3018; - x86::Gp ret_val_get_lmul_pow_3018 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3018, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3018; - setArg(call_get_lmul_pow_3018, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3018, 0, ret_val_get_lmul_pow_3018); + (gen_operation(cc, shl, tmp3034, ret_val_get_sew_pow_3033)), 8, false), ~ 1); + setArg(call_get_sew_pow_3033, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3033, 0, ret_val_get_sew_pow_3033); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); - auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_reduction_widen_3019; - auto illegal_reduction_widen_3019_arg0 = SEW_widen; - auto illegal_reduction_widen_3019_arg1 = LMUL_pow_widen; - x86::Gp ret_val_illegal_reduction_widen_3019 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_reduction_widen_3019, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); - auto cond = ret_val_illegal_reduction_widen_3019; - setArg(call_illegal_reduction_widen_3019, 0, reinterpret_cast(this)); - setArg(call_illegal_reduction_widen_3019, 1, illegal_reduction_widen_3019_arg0); - setArg(call_illegal_reduction_widen_3019, 2, illegal_reduction_widen_3019_arg1); - setRet(call_illegal_reduction_widen_3019, 0, ret_val_illegal_reduction_widen_3019); + InvokeNode* call_illegal_reduction_widen_3035; + auto illegal_reduction_widen_3035_arg0 = SEW_widen; + x86::Gp ret_val_illegal_reduction_widen_3035 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_reduction_widen_3035, (uintptr_t)&vm_impl::_illegal_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_reduction_widen_3035; + setArg(call_illegal_reduction_widen_3035, 0, reinterpret_cast(this)); + setArg(call_illegal_reduction_widen_3035, 1, illegal_reduction_widen_3035_arg0); + setRet(call_illegal_reduction_widen_3035, 0, ret_val_illegal_reduction_widen_3035); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73061,37 +72727,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3021; - x86::Gp ret_val_sew_3021 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3021, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_red_wv_3020; - auto vector_red_wv_3020_arg3 = load_reg_from_mem(jh, traits::vl); - auto vector_red_wv_3020_arg4 = load_reg_from_mem(jh, traits::vstart); - auto vector_red_wv_3020_arg5 = load_reg_from_mem(jh, traits::vtype); - auto vector_red_wv_3020_arg10 = ret_val_sew_3021; + InvokeNode* call_sew_3037; + x86::Gp ret_val_sew_3037 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3037, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_red_wv_3036; + auto vector_red_wv_3036_arg3 = load_reg_from_mem(jh, traits::vl); + auto vector_red_wv_3036_arg4 = load_reg_from_mem(jh, traits::vstart); + auto vector_red_wv_3036_arg5 = load_reg_from_mem(jh, traits::vtype); + auto vector_red_wv_3036_arg10 = ret_val_sew_3037; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_red_wv_3020, &vector_red_wv, FuncSignature::build()); - setArg(call_sew_3021, 0, reinterpret_cast(this)); - setRet(call_sew_3021, 0, ret_val_sew_3021); - setArg(call_vector_red_wv_3020, 0, V); - setArg(call_vector_red_wv_3020, 1, 49); - setArg(call_vector_red_wv_3020, 2, 0); - setArg(call_vector_red_wv_3020, 3, vector_red_wv_3020_arg3); - setArg(call_vector_red_wv_3020, 4, vector_red_wv_3020_arg4); - setArg(call_vector_red_wv_3020, 5, vector_red_wv_3020_arg5); - setArg(call_vector_red_wv_3020, 6, vm); - setArg(call_vector_red_wv_3020, 7, vd); - setArg(call_vector_red_wv_3020, 8, vs2); - setArg(call_vector_red_wv_3020, 9, vs1); - setArg(call_vector_red_wv_3020, 10, vector_red_wv_3020_arg10); + cc.invoke(&call_vector_red_wv_3036, &vector_red_wv, FuncSignature::build()); + setArg(call_sew_3037, 0, reinterpret_cast(this)); + setRet(call_sew_3037, 0, ret_val_sew_3037); + setArg(call_vector_red_wv_3036, 0, V); + setArg(call_vector_red_wv_3036, 1, 49); + setArg(call_vector_red_wv_3036, 2, 0); + setArg(call_vector_red_wv_3036, 3, vector_red_wv_3036_arg3); + setArg(call_vector_red_wv_3036, 4, vector_red_wv_3036_arg4); + setArg(call_vector_red_wv_3036, 5, vector_red_wv_3036_arg5); + setArg(call_vector_red_wv_3036, 6, vm); + setArg(call_vector_red_wv_3036, 7, vd); + setArg(call_vector_red_wv_3036, 8, vs2); + setArg(call_vector_red_wv_3036, 9, vs1); + setArg(call_vector_red_wv_3036, 10, vector_red_wv_3036_arg10); } cc.bind(label_merge); } - auto tmp3022 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3022, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3022, 64, false) - , traits::vstart); + auto tmp3038 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3038, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3038, traits::vstart); } cc.bind(label_merge); } @@ -73135,28 +72799,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3023; - x86::Gp ret_val_get_sew_pow_3023 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3023, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3024 = get_reg(cc, 8, false); - mov(cc, tmp3024, 1); + InvokeNode* call_get_sew_pow_3039; + x86::Gp ret_val_get_sew_pow_3039 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3039, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3040 = get_reg(cc, 8, false); + mov(cc, tmp3040, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3024, (ret_val_get_sew_pow_3023))), 8, false), ~ 1); - setArg(call_get_sew_pow_3023, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3023, 0, ret_val_get_sew_pow_3023); + (gen_operation(cc, shl, tmp3040, (ret_val_get_sew_pow_3039))), 8, false), ~ 1); + setArg(call_get_sew_pow_3039, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3039, 0, ret_val_get_sew_pow_3039); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_3025; - auto illegal_fp_reduction_3025_arg0 = SEW; - auto illegal_fp_reduction_3025_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_3025 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_3025, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_3025; - setArg(call_illegal_fp_reduction_3025, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_3025, 1, illegal_fp_reduction_3025_arg0); - setArg(call_illegal_fp_reduction_3025, 2, illegal_fp_reduction_3025_arg1); - setRet(call_illegal_fp_reduction_3025, 0, ret_val_illegal_fp_reduction_3025); + InvokeNode* call_illegal_fp_reduction_3041; + auto illegal_fp_reduction_3041_arg0 = SEW; + auto illegal_fp_reduction_3041_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3041 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3041, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3041; + setArg(call_illegal_fp_reduction_3041, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3041, 1, illegal_fp_reduction_3041_arg0); + setArg(call_illegal_fp_reduction_3041, 2, illegal_fp_reduction_3041_arg1); + setRet(call_illegal_fp_reduction_3041, 0, ret_val_illegal_fp_reduction_3041); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73172,45 +72836,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3027; - x86::Gp ret_val_sew_3027 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3027, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_op_3026; - auto fp_vector_red_op_3026_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_op_3026_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_op_3026_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_op_3026_arg10 = rm; - auto fp_vector_red_op_3026_arg11 = ret_val_sew_3027; + InvokeNode* call_sew_3043; + x86::Gp ret_val_sew_3043 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3043, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3042; + auto fp_vector_red_op_3042_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3042_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3042_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3042_arg10 = rm; + auto fp_vector_red_op_3042_arg11 = ret_val_sew_3043; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_op_3026, &fp_vector_red_op, FuncSignature::build()); - setArg(call_sew_3027, 0, reinterpret_cast(this)); - setRet(call_sew_3027, 0, ret_val_sew_3027); - setArg(call_fp_vector_red_op_3026, 0, V); - setArg(call_fp_vector_red_op_3026, 1, 3); - setArg(call_fp_vector_red_op_3026, 2, 1); - setArg(call_fp_vector_red_op_3026, 3, fp_vector_red_op_3026_arg3); - setArg(call_fp_vector_red_op_3026, 4, fp_vector_red_op_3026_arg4); - setArg(call_fp_vector_red_op_3026, 5, fp_vector_red_op_3026_arg5); - setArg(call_fp_vector_red_op_3026, 6, vm); - setArg(call_fp_vector_red_op_3026, 7, vd); - setArg(call_fp_vector_red_op_3026, 8, vs2); - setArg(call_fp_vector_red_op_3026, 9, vs1); - setArg(call_fp_vector_red_op_3026, 10, fp_vector_red_op_3026_arg10); - setArg(call_fp_vector_red_op_3026, 11, fp_vector_red_op_3026_arg11); - InvokeNode* call_fget_flags_3028; - x86::Gp ret_val_fget_flags_3028 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3028, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3028; - setRet(call_fget_flags_3028, 0, ret_val_fget_flags_3028); + cc.invoke(&call_fp_vector_red_op_3042, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3043, 0, reinterpret_cast(this)); + setRet(call_sew_3043, 0, ret_val_sew_3043); + setArg(call_fp_vector_red_op_3042, 0, V); + setArg(call_fp_vector_red_op_3042, 1, 3); + setArg(call_fp_vector_red_op_3042, 2, 1); + setArg(call_fp_vector_red_op_3042, 3, fp_vector_red_op_3042_arg3); + setArg(call_fp_vector_red_op_3042, 4, fp_vector_red_op_3042_arg4); + setArg(call_fp_vector_red_op_3042, 5, fp_vector_red_op_3042_arg5); + setArg(call_fp_vector_red_op_3042, 6, vm); + setArg(call_fp_vector_red_op_3042, 7, vd); + setArg(call_fp_vector_red_op_3042, 8, vs2); + setArg(call_fp_vector_red_op_3042, 9, vs1); + setArg(call_fp_vector_red_op_3042, 10, fp_vector_red_op_3042_arg10); + setArg(call_fp_vector_red_op_3042, 11, fp_vector_red_op_3042_arg11); + InvokeNode* call_fget_flags_3044; + x86::Gp ret_val_fget_flags_3044 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3044, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3044; + setRet(call_fget_flags_3044, 0, ret_val_fget_flags_3044); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3029 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3029, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3029, 64, false) - , traits::vstart); + auto tmp3045 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3045, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3045, traits::vstart); } cc.bind(label_merge); } @@ -73254,28 +72916,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3030; - x86::Gp ret_val_get_sew_pow_3030 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3030, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3031 = get_reg(cc, 8, false); - mov(cc, tmp3031, 1); + InvokeNode* call_get_sew_pow_3046; + x86::Gp ret_val_get_sew_pow_3046 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3046, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3047 = get_reg(cc, 8, false); + mov(cc, tmp3047, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3031, (ret_val_get_sew_pow_3030))), 8, false), ~ 1); - setArg(call_get_sew_pow_3030, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3030, 0, ret_val_get_sew_pow_3030); + (gen_operation(cc, shl, tmp3047, (ret_val_get_sew_pow_3046))), 8, false), ~ 1); + setArg(call_get_sew_pow_3046, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3046, 0, ret_val_get_sew_pow_3046); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_3032; - auto illegal_fp_reduction_3032_arg0 = SEW; - auto illegal_fp_reduction_3032_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_3032 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_3032, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_3032; - setArg(call_illegal_fp_reduction_3032, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_3032, 1, illegal_fp_reduction_3032_arg0); - setArg(call_illegal_fp_reduction_3032, 2, illegal_fp_reduction_3032_arg1); - setRet(call_illegal_fp_reduction_3032, 0, ret_val_illegal_fp_reduction_3032); + InvokeNode* call_illegal_fp_reduction_3048; + auto illegal_fp_reduction_3048_arg0 = SEW; + auto illegal_fp_reduction_3048_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3048 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3048, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3048; + setArg(call_illegal_fp_reduction_3048, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3048, 1, illegal_fp_reduction_3048_arg0); + setArg(call_illegal_fp_reduction_3048, 2, illegal_fp_reduction_3048_arg1); + setRet(call_illegal_fp_reduction_3048, 0, ret_val_illegal_fp_reduction_3048); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73291,45 +72953,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3034; - x86::Gp ret_val_sew_3034 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3034, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_op_3033; - auto fp_vector_red_op_3033_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_op_3033_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_op_3033_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_op_3033_arg10 = rm; - auto fp_vector_red_op_3033_arg11 = ret_val_sew_3034; + InvokeNode* call_sew_3050; + x86::Gp ret_val_sew_3050 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3050, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3049; + auto fp_vector_red_op_3049_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3049_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3049_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3049_arg10 = rm; + auto fp_vector_red_op_3049_arg11 = ret_val_sew_3050; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_op_3033, &fp_vector_red_op, FuncSignature::build()); - setArg(call_sew_3034, 0, reinterpret_cast(this)); - setRet(call_sew_3034, 0, ret_val_sew_3034); - setArg(call_fp_vector_red_op_3033, 0, V); - setArg(call_fp_vector_red_op_3033, 1, 1); - setArg(call_fp_vector_red_op_3033, 2, 1); - setArg(call_fp_vector_red_op_3033, 3, fp_vector_red_op_3033_arg3); - setArg(call_fp_vector_red_op_3033, 4, fp_vector_red_op_3033_arg4); - setArg(call_fp_vector_red_op_3033, 5, fp_vector_red_op_3033_arg5); - setArg(call_fp_vector_red_op_3033, 6, vm); - setArg(call_fp_vector_red_op_3033, 7, vd); - setArg(call_fp_vector_red_op_3033, 8, vs2); - setArg(call_fp_vector_red_op_3033, 9, vs1); - setArg(call_fp_vector_red_op_3033, 10, fp_vector_red_op_3033_arg10); - setArg(call_fp_vector_red_op_3033, 11, fp_vector_red_op_3033_arg11); - InvokeNode* call_fget_flags_3035; - x86::Gp ret_val_fget_flags_3035 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3035, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3035; - setRet(call_fget_flags_3035, 0, ret_val_fget_flags_3035); + cc.invoke(&call_fp_vector_red_op_3049, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3050, 0, reinterpret_cast(this)); + setRet(call_sew_3050, 0, ret_val_sew_3050); + setArg(call_fp_vector_red_op_3049, 0, V); + setArg(call_fp_vector_red_op_3049, 1, 1); + setArg(call_fp_vector_red_op_3049, 2, 1); + setArg(call_fp_vector_red_op_3049, 3, fp_vector_red_op_3049_arg3); + setArg(call_fp_vector_red_op_3049, 4, fp_vector_red_op_3049_arg4); + setArg(call_fp_vector_red_op_3049, 5, fp_vector_red_op_3049_arg5); + setArg(call_fp_vector_red_op_3049, 6, vm); + setArg(call_fp_vector_red_op_3049, 7, vd); + setArg(call_fp_vector_red_op_3049, 8, vs2); + setArg(call_fp_vector_red_op_3049, 9, vs1); + setArg(call_fp_vector_red_op_3049, 10, fp_vector_red_op_3049_arg10); + setArg(call_fp_vector_red_op_3049, 11, fp_vector_red_op_3049_arg11); + InvokeNode* call_fget_flags_3051; + x86::Gp ret_val_fget_flags_3051 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3051, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3051; + setRet(call_fget_flags_3051, 0, ret_val_fget_flags_3051); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3036 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3036, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3036, 64, false) - , traits::vstart); + auto tmp3052 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3052, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3052, traits::vstart); } cc.bind(label_merge); } @@ -73373,28 +73033,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3037; - x86::Gp ret_val_get_sew_pow_3037 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3037, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3038 = get_reg(cc, 8, false); - mov(cc, tmp3038, 1); + InvokeNode* call_get_sew_pow_3053; + x86::Gp ret_val_get_sew_pow_3053 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3053, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3054 = get_reg(cc, 8, false); + mov(cc, tmp3054, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3038, (ret_val_get_sew_pow_3037))), 8, false), ~ 1); - setArg(call_get_sew_pow_3037, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3037, 0, ret_val_get_sew_pow_3037); + (gen_operation(cc, shl, tmp3054, (ret_val_get_sew_pow_3053))), 8, false), ~ 1); + setArg(call_get_sew_pow_3053, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3053, 0, ret_val_get_sew_pow_3053); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_3039; - auto illegal_fp_reduction_3039_arg0 = SEW; - auto illegal_fp_reduction_3039_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_3039 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_3039, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_3039; - setArg(call_illegal_fp_reduction_3039, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_3039, 1, illegal_fp_reduction_3039_arg0); - setArg(call_illegal_fp_reduction_3039, 2, illegal_fp_reduction_3039_arg1); - setRet(call_illegal_fp_reduction_3039, 0, ret_val_illegal_fp_reduction_3039); + InvokeNode* call_illegal_fp_reduction_3055; + auto illegal_fp_reduction_3055_arg0 = SEW; + auto illegal_fp_reduction_3055_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3055 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3055, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3055; + setArg(call_illegal_fp_reduction_3055, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3055, 1, illegal_fp_reduction_3055_arg0); + setArg(call_illegal_fp_reduction_3055, 2, illegal_fp_reduction_3055_arg1); + setRet(call_illegal_fp_reduction_3055, 0, ret_val_illegal_fp_reduction_3055); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73410,39 +73070,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3041; - x86::Gp ret_val_sew_3041 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3041, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_op_3040; - auto fp_vector_red_op_3040_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_op_3040_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_op_3040_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_op_3040_arg10 = rm; - auto fp_vector_red_op_3040_arg11 = ret_val_sew_3041; + InvokeNode* call_sew_3057; + x86::Gp ret_val_sew_3057 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3057, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3056; + auto fp_vector_red_op_3056_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3056_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3056_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3056_arg10 = rm; + auto fp_vector_red_op_3056_arg11 = ret_val_sew_3057; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_op_3040, &fp_vector_red_op, FuncSignature::build()); - setArg(call_sew_3041, 0, reinterpret_cast(this)); - setRet(call_sew_3041, 0, ret_val_sew_3041); - setArg(call_fp_vector_red_op_3040, 0, V); - setArg(call_fp_vector_red_op_3040, 1, 7); - setArg(call_fp_vector_red_op_3040, 2, 1); - setArg(call_fp_vector_red_op_3040, 3, fp_vector_red_op_3040_arg3); - setArg(call_fp_vector_red_op_3040, 4, fp_vector_red_op_3040_arg4); - setArg(call_fp_vector_red_op_3040, 5, fp_vector_red_op_3040_arg5); - setArg(call_fp_vector_red_op_3040, 6, vm); - setArg(call_fp_vector_red_op_3040, 7, vd); - setArg(call_fp_vector_red_op_3040, 8, vs2); - setArg(call_fp_vector_red_op_3040, 9, vs1); - setArg(call_fp_vector_red_op_3040, 10, fp_vector_red_op_3040_arg10); - setArg(call_fp_vector_red_op_3040, 11, fp_vector_red_op_3040_arg11); + cc.invoke(&call_fp_vector_red_op_3056, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3057, 0, reinterpret_cast(this)); + setRet(call_sew_3057, 0, ret_val_sew_3057); + setArg(call_fp_vector_red_op_3056, 0, V); + setArg(call_fp_vector_red_op_3056, 1, 7); + setArg(call_fp_vector_red_op_3056, 2, 1); + setArg(call_fp_vector_red_op_3056, 3, fp_vector_red_op_3056_arg3); + setArg(call_fp_vector_red_op_3056, 4, fp_vector_red_op_3056_arg4); + setArg(call_fp_vector_red_op_3056, 5, fp_vector_red_op_3056_arg5); + setArg(call_fp_vector_red_op_3056, 6, vm); + setArg(call_fp_vector_red_op_3056, 7, vd); + setArg(call_fp_vector_red_op_3056, 8, vs2); + setArg(call_fp_vector_red_op_3056, 9, vs1); + setArg(call_fp_vector_red_op_3056, 10, fp_vector_red_op_3056_arg10); + setArg(call_fp_vector_red_op_3056, 11, fp_vector_red_op_3056_arg11); } cc.bind(label_merge); } - auto tmp3042 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3042, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3042, 64, false) - , traits::vstart); + auto tmp3058 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3058, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3058, traits::vstart); } cc.bind(label_merge); } @@ -73486,28 +73144,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3043; - x86::Gp ret_val_get_sew_pow_3043 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3043, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3044 = get_reg(cc, 8, false); - mov(cc, tmp3044, 1); + InvokeNode* call_get_sew_pow_3059; + x86::Gp ret_val_get_sew_pow_3059 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3059, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3060 = get_reg(cc, 8, false); + mov(cc, tmp3060, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3044, (ret_val_get_sew_pow_3043))), 8, false), ~ 1); - setArg(call_get_sew_pow_3043, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3043, 0, ret_val_get_sew_pow_3043); + (gen_operation(cc, shl, tmp3060, (ret_val_get_sew_pow_3059))), 8, false), ~ 1); + setArg(call_get_sew_pow_3059, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3059, 0, ret_val_get_sew_pow_3059); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_3045; - auto illegal_fp_reduction_3045_arg0 = SEW; - auto illegal_fp_reduction_3045_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_3045 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_3045, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_3045; - setArg(call_illegal_fp_reduction_3045, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_3045, 1, illegal_fp_reduction_3045_arg0); - setArg(call_illegal_fp_reduction_3045, 2, illegal_fp_reduction_3045_arg1); - setRet(call_illegal_fp_reduction_3045, 0, ret_val_illegal_fp_reduction_3045); + InvokeNode* call_illegal_fp_reduction_3061; + auto illegal_fp_reduction_3061_arg0 = SEW; + auto illegal_fp_reduction_3061_arg1 = rm; + x86::Gp ret_val_illegal_fp_reduction_3061 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_3061, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_3061; + setArg(call_illegal_fp_reduction_3061, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_3061, 1, illegal_fp_reduction_3061_arg0); + setArg(call_illegal_fp_reduction_3061, 2, illegal_fp_reduction_3061_arg1); + setRet(call_illegal_fp_reduction_3061, 0, ret_val_illegal_fp_reduction_3061); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73523,39 +73181,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3047; - x86::Gp ret_val_sew_3047 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3047, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_op_3046; - auto fp_vector_red_op_3046_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_op_3046_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_op_3046_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_op_3046_arg10 = rm; - auto fp_vector_red_op_3046_arg11 = ret_val_sew_3047; + InvokeNode* call_sew_3063; + x86::Gp ret_val_sew_3063 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3063, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_op_3062; + auto fp_vector_red_op_3062_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_op_3062_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_op_3062_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_op_3062_arg10 = rm; + auto fp_vector_red_op_3062_arg11 = ret_val_sew_3063; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_op_3046, &fp_vector_red_op, FuncSignature::build()); - setArg(call_sew_3047, 0, reinterpret_cast(this)); - setRet(call_sew_3047, 0, ret_val_sew_3047); - setArg(call_fp_vector_red_op_3046, 0, V); - setArg(call_fp_vector_red_op_3046, 1, 5); - setArg(call_fp_vector_red_op_3046, 2, 1); - setArg(call_fp_vector_red_op_3046, 3, fp_vector_red_op_3046_arg3); - setArg(call_fp_vector_red_op_3046, 4, fp_vector_red_op_3046_arg4); - setArg(call_fp_vector_red_op_3046, 5, fp_vector_red_op_3046_arg5); - setArg(call_fp_vector_red_op_3046, 6, vm); - setArg(call_fp_vector_red_op_3046, 7, vd); - setArg(call_fp_vector_red_op_3046, 8, vs2); - setArg(call_fp_vector_red_op_3046, 9, vs1); - setArg(call_fp_vector_red_op_3046, 10, fp_vector_red_op_3046_arg10); - setArg(call_fp_vector_red_op_3046, 11, fp_vector_red_op_3046_arg11); + cc.invoke(&call_fp_vector_red_op_3062, &fp_vector_red_op, FuncSignature::build()); + setArg(call_sew_3063, 0, reinterpret_cast(this)); + setRet(call_sew_3063, 0, ret_val_sew_3063); + setArg(call_fp_vector_red_op_3062, 0, V); + setArg(call_fp_vector_red_op_3062, 1, 5); + setArg(call_fp_vector_red_op_3062, 2, 1); + setArg(call_fp_vector_red_op_3062, 3, fp_vector_red_op_3062_arg3); + setArg(call_fp_vector_red_op_3062, 4, fp_vector_red_op_3062_arg4); + setArg(call_fp_vector_red_op_3062, 5, fp_vector_red_op_3062_arg5); + setArg(call_fp_vector_red_op_3062, 6, vm); + setArg(call_fp_vector_red_op_3062, 7, vd); + setArg(call_fp_vector_red_op_3062, 8, vs2); + setArg(call_fp_vector_red_op_3062, 9, vs1); + setArg(call_fp_vector_red_op_3062, 10, fp_vector_red_op_3062_arg10); + setArg(call_fp_vector_red_op_3062, 11, fp_vector_red_op_3062_arg11); } cc.bind(label_merge); } - auto tmp3048 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3048, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3048, 64, false) - , traits::vstart); + auto tmp3064 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3064, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3064, traits::vstart); } cc.bind(label_merge); } @@ -73599,28 +73255,32 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3049; - x86::Gp ret_val_get_sew_pow_3049 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3049, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3050 = get_reg(cc, 8, false); - mov(cc, tmp3050, 1); + InvokeNode* call_get_sew_pow_3065; + x86::Gp ret_val_get_sew_pow_3065 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3065, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3066 = get_reg(cc, 8, false); + mov(cc, tmp3066, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3050, (ret_val_get_sew_pow_3049))), 8, false), ~ 1); - setArg(call_get_sew_pow_3049, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3049, 0, ret_val_get_sew_pow_3049); + (gen_operation(cc, shl, tmp3066, (ret_val_get_sew_pow_3065))), 8, false), ~ 1); + setArg(call_get_sew_pow_3065, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3065, 0, ret_val_get_sew_pow_3065); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_3051; - auto illegal_fp_reduction_3051_arg0 = SEW; - auto illegal_fp_reduction_3051_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_3051 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_3051, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_3051; - setArg(call_illegal_fp_reduction_3051, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_3051, 1, illegal_fp_reduction_3051_arg0); - setArg(call_illegal_fp_reduction_3051, 2, illegal_fp_reduction_3051_arg1); - setRet(call_illegal_fp_reduction_3051, 0, ret_val_illegal_fp_reduction_3051); + InvokeNode* call_illegal_fp_reduction_widen_3067; + auto illegal_fp_reduction_widen_3067_arg0 = SEW; + auto illegal_fp_reduction_widen_3067_arg1 = rm; + auto illegal_fp_reduction_widen_3067_arg2 = SEW_widen; + x86::Gp ret_val_illegal_fp_reduction_widen_3067 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_widen_3067, (uintptr_t)&vm_impl::_illegal_fp_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_widen_3067; + setArg(call_illegal_fp_reduction_widen_3067, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_widen_3067, 1, illegal_fp_reduction_widen_3067_arg0); + setArg(call_illegal_fp_reduction_widen_3067, 2, illegal_fp_reduction_widen_3067_arg1); + setArg(call_illegal_fp_reduction_widen_3067, 3, illegal_fp_reduction_widen_3067_arg2); + setRet(call_illegal_fp_reduction_widen_3067, 0, ret_val_illegal_fp_reduction_widen_3067); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73636,45 +73296,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3053; - x86::Gp ret_val_sew_3053 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3053, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_wv_3052; - auto fp_vector_red_wv_3052_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_wv_3052_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_wv_3052_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_wv_3052_arg10 = rm; - auto fp_vector_red_wv_3052_arg11 = ret_val_sew_3053; + InvokeNode* call_sew_3069; + x86::Gp ret_val_sew_3069 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3069, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_wv_3068; + auto fp_vector_red_wv_3068_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_wv_3068_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_wv_3068_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_wv_3068_arg10 = rm; + auto fp_vector_red_wv_3068_arg11 = ret_val_sew_3069; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_wv_3052, &fp_vector_red_wv, FuncSignature::build()); - setArg(call_sew_3053, 0, reinterpret_cast(this)); - setRet(call_sew_3053, 0, ret_val_sew_3053); - setArg(call_fp_vector_red_wv_3052, 0, V); - setArg(call_fp_vector_red_wv_3052, 1, 51); - setArg(call_fp_vector_red_wv_3052, 2, 1); - setArg(call_fp_vector_red_wv_3052, 3, fp_vector_red_wv_3052_arg3); - setArg(call_fp_vector_red_wv_3052, 4, fp_vector_red_wv_3052_arg4); - setArg(call_fp_vector_red_wv_3052, 5, fp_vector_red_wv_3052_arg5); - setArg(call_fp_vector_red_wv_3052, 6, vm); - setArg(call_fp_vector_red_wv_3052, 7, vd); - setArg(call_fp_vector_red_wv_3052, 8, vs2); - setArg(call_fp_vector_red_wv_3052, 9, vs1); - setArg(call_fp_vector_red_wv_3052, 10, fp_vector_red_wv_3052_arg10); - setArg(call_fp_vector_red_wv_3052, 11, fp_vector_red_wv_3052_arg11); - InvokeNode* call_fget_flags_3054; - x86::Gp ret_val_fget_flags_3054 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3054, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3054; - setRet(call_fget_flags_3054, 0, ret_val_fget_flags_3054); + cc.invoke(&call_fp_vector_red_wv_3068, &fp_vector_red_wv, FuncSignature::build()); + setArg(call_sew_3069, 0, reinterpret_cast(this)); + setRet(call_sew_3069, 0, ret_val_sew_3069); + setArg(call_fp_vector_red_wv_3068, 0, V); + setArg(call_fp_vector_red_wv_3068, 1, 51); + setArg(call_fp_vector_red_wv_3068, 2, 1); + setArg(call_fp_vector_red_wv_3068, 3, fp_vector_red_wv_3068_arg3); + setArg(call_fp_vector_red_wv_3068, 4, fp_vector_red_wv_3068_arg4); + setArg(call_fp_vector_red_wv_3068, 5, fp_vector_red_wv_3068_arg5); + setArg(call_fp_vector_red_wv_3068, 6, vm); + setArg(call_fp_vector_red_wv_3068, 7, vd); + setArg(call_fp_vector_red_wv_3068, 8, vs2); + setArg(call_fp_vector_red_wv_3068, 9, vs1); + setArg(call_fp_vector_red_wv_3068, 10, fp_vector_red_wv_3068_arg10); + setArg(call_fp_vector_red_wv_3068, 11, fp_vector_red_wv_3068_arg11); + InvokeNode* call_fget_flags_3070; + x86::Gp ret_val_fget_flags_3070 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3070, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3070; + setRet(call_fget_flags_3070, 0, ret_val_fget_flags_3070); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3055 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3055, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3055, 64, false) - , traits::vstart); + auto tmp3071 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3071, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3071, traits::vstart); } cc.bind(label_merge); } @@ -73718,28 +73376,32 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3056; - x86::Gp ret_val_get_sew_pow_3056 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3056, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3057 = get_reg(cc, 8, false); - mov(cc, tmp3057, 1); + InvokeNode* call_get_sew_pow_3072; + x86::Gp ret_val_get_sew_pow_3072 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3072, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3073 = get_reg(cc, 8, false); + mov(cc, tmp3073, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3057, (ret_val_get_sew_pow_3056))), 8, false), ~ 1); - setArg(call_get_sew_pow_3056, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3056, 0, ret_val_get_sew_pow_3056); + (gen_operation(cc, shl, tmp3073, (ret_val_get_sew_pow_3072))), 8, false), ~ 1); + setArg(call_get_sew_pow_3072, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3072, 0, ret_val_get_sew_pow_3072); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_reduction_3058; - auto illegal_fp_reduction_3058_arg0 = SEW; - auto illegal_fp_reduction_3058_arg1 = rm; - x86::Gp ret_val_illegal_fp_reduction_3058 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_reduction_3058, (uintptr_t)&vm_impl::_illegal_fp_reduction, FuncSignature::build()); - auto cond = ret_val_illegal_fp_reduction_3058; - setArg(call_illegal_fp_reduction_3058, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_reduction_3058, 1, illegal_fp_reduction_3058_arg0); - setArg(call_illegal_fp_reduction_3058, 2, illegal_fp_reduction_3058_arg1); - setRet(call_illegal_fp_reduction_3058, 0, ret_val_illegal_fp_reduction_3058); + InvokeNode* call_illegal_fp_reduction_widen_3074; + auto illegal_fp_reduction_widen_3074_arg0 = SEW; + auto illegal_fp_reduction_widen_3074_arg1 = rm; + auto illegal_fp_reduction_widen_3074_arg2 = SEW_widen; + x86::Gp ret_val_illegal_fp_reduction_widen_3074 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_reduction_widen_3074, (uintptr_t)&vm_impl::_illegal_fp_reduction_widen, FuncSignature::build()); + auto cond = ret_val_illegal_fp_reduction_widen_3074; + setArg(call_illegal_fp_reduction_widen_3074, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_reduction_widen_3074, 1, illegal_fp_reduction_widen_3074_arg0); + setArg(call_illegal_fp_reduction_widen_3074, 2, illegal_fp_reduction_widen_3074_arg1); + setArg(call_illegal_fp_reduction_widen_3074, 3, illegal_fp_reduction_widen_3074_arg2); + setRet(call_illegal_fp_reduction_widen_3074, 0, ret_val_illegal_fp_reduction_widen_3074); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73755,45 +73417,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3060; - x86::Gp ret_val_sew_3060 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3060, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_red_wv_3059; - auto fp_vector_red_wv_3059_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_red_wv_3059_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_red_wv_3059_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_red_wv_3059_arg10 = rm; - auto fp_vector_red_wv_3059_arg11 = ret_val_sew_3060; + InvokeNode* call_sew_3076; + x86::Gp ret_val_sew_3076 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3076, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_red_wv_3075; + auto fp_vector_red_wv_3075_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_red_wv_3075_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_red_wv_3075_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_red_wv_3075_arg10 = rm; + auto fp_vector_red_wv_3075_arg11 = ret_val_sew_3076; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_red_wv_3059, &fp_vector_red_wv, FuncSignature::build()); - setArg(call_sew_3060, 0, reinterpret_cast(this)); - setRet(call_sew_3060, 0, ret_val_sew_3060); - setArg(call_fp_vector_red_wv_3059, 0, V); - setArg(call_fp_vector_red_wv_3059, 1, 49); - setArg(call_fp_vector_red_wv_3059, 2, 1); - setArg(call_fp_vector_red_wv_3059, 3, fp_vector_red_wv_3059_arg3); - setArg(call_fp_vector_red_wv_3059, 4, fp_vector_red_wv_3059_arg4); - setArg(call_fp_vector_red_wv_3059, 5, fp_vector_red_wv_3059_arg5); - setArg(call_fp_vector_red_wv_3059, 6, vm); - setArg(call_fp_vector_red_wv_3059, 7, vd); - setArg(call_fp_vector_red_wv_3059, 8, vs2); - setArg(call_fp_vector_red_wv_3059, 9, vs1); - setArg(call_fp_vector_red_wv_3059, 10, fp_vector_red_wv_3059_arg10); - setArg(call_fp_vector_red_wv_3059, 11, fp_vector_red_wv_3059_arg11); - InvokeNode* call_fget_flags_3061; - x86::Gp ret_val_fget_flags_3061 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3061, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3061; - setRet(call_fget_flags_3061, 0, ret_val_fget_flags_3061); + cc.invoke(&call_fp_vector_red_wv_3075, &fp_vector_red_wv, FuncSignature::build()); + setArg(call_sew_3076, 0, reinterpret_cast(this)); + setRet(call_sew_3076, 0, ret_val_sew_3076); + setArg(call_fp_vector_red_wv_3075, 0, V); + setArg(call_fp_vector_red_wv_3075, 1, 49); + setArg(call_fp_vector_red_wv_3075, 2, 1); + setArg(call_fp_vector_red_wv_3075, 3, fp_vector_red_wv_3075_arg3); + setArg(call_fp_vector_red_wv_3075, 4, fp_vector_red_wv_3075_arg4); + setArg(call_fp_vector_red_wv_3075, 5, fp_vector_red_wv_3075_arg5); + setArg(call_fp_vector_red_wv_3075, 6, vm); + setArg(call_fp_vector_red_wv_3075, 7, vd); + setArg(call_fp_vector_red_wv_3075, 8, vs2); + setArg(call_fp_vector_red_wv_3075, 9, vs1); + setArg(call_fp_vector_red_wv_3075, 10, fp_vector_red_wv_3075_arg10); + setArg(call_fp_vector_red_wv_3075, 11, fp_vector_red_wv_3075_arg11); + InvokeNode* call_fget_flags_3077; + x86::Gp ret_val_fget_flags_3077 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3077, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3077; + setRet(call_fget_flags_3077, 0, ret_val_fget_flags_3077); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3062 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3062, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3062, 64, false) - , traits::vstart); + auto tmp3078 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3078, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3078, traits::vstart); } cc.bind(label_merge); } @@ -73838,12 +73498,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3063; - x86::Gp ret_val_illegal_vd_unmasked_3063 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3063, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3063; - setArg(call_illegal_vd_unmasked_3063, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3063, 0, ret_val_illegal_vd_unmasked_3063); + InvokeNode* call_illegal_vd_unmasked_3079; + x86::Gp ret_val_illegal_vd_unmasked_3079 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3079, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3079; + setArg(call_illegal_vd_unmasked_3079, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3079, 0, ret_val_illegal_vd_unmasked_3079); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73859,27 +73519,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3064; - auto mask_mask_op_3064_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3064_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3080; + auto mask_mask_op_3080_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3080_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3064, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3064, 0, V); - setArg(call_mask_mask_op_3064, 1, 25); - setArg(call_mask_mask_op_3064, 2, 2); - setArg(call_mask_mask_op_3064, 3, mask_mask_op_3064_arg3); - setArg(call_mask_mask_op_3064, 4, mask_mask_op_3064_arg4); - setArg(call_mask_mask_op_3064, 5, vd); - setArg(call_mask_mask_op_3064, 6, vs2); - setArg(call_mask_mask_op_3064, 7, vs1); + cc.invoke(&call_mask_mask_op_3080, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3080, 0, V); + setArg(call_mask_mask_op_3080, 1, 25); + setArg(call_mask_mask_op_3080, 2, 2); + setArg(call_mask_mask_op_3080, 3, mask_mask_op_3080_arg3); + setArg(call_mask_mask_op_3080, 4, mask_mask_op_3080_arg4); + setArg(call_mask_mask_op_3080, 5, vd); + setArg(call_mask_mask_op_3080, 6, vs2); + setArg(call_mask_mask_op_3080, 7, vs1); } cc.bind(label_merge); } - auto tmp3065 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3065, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3065, 64, false) - , traits::vstart); + auto tmp3081 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3081, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3081, traits::vstart); } cc.bind(label_merge); } @@ -73924,12 +73582,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3066; - x86::Gp ret_val_illegal_vd_unmasked_3066 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3066, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3066; - setArg(call_illegal_vd_unmasked_3066, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3066, 0, ret_val_illegal_vd_unmasked_3066); + InvokeNode* call_illegal_vd_unmasked_3082; + x86::Gp ret_val_illegal_vd_unmasked_3082 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3082, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3082; + setArg(call_illegal_vd_unmasked_3082, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3082, 0, ret_val_illegal_vd_unmasked_3082); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -73945,27 +73603,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3067; - auto mask_mask_op_3067_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3067_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3083; + auto mask_mask_op_3083_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3083_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3067, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3067, 0, V); - setArg(call_mask_mask_op_3067, 1, 29); - setArg(call_mask_mask_op_3067, 2, 2); - setArg(call_mask_mask_op_3067, 3, mask_mask_op_3067_arg3); - setArg(call_mask_mask_op_3067, 4, mask_mask_op_3067_arg4); - setArg(call_mask_mask_op_3067, 5, vd); - setArg(call_mask_mask_op_3067, 6, vs2); - setArg(call_mask_mask_op_3067, 7, vs1); + cc.invoke(&call_mask_mask_op_3083, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3083, 0, V); + setArg(call_mask_mask_op_3083, 1, 29); + setArg(call_mask_mask_op_3083, 2, 2); + setArg(call_mask_mask_op_3083, 3, mask_mask_op_3083_arg3); + setArg(call_mask_mask_op_3083, 4, mask_mask_op_3083_arg4); + setArg(call_mask_mask_op_3083, 5, vd); + setArg(call_mask_mask_op_3083, 6, vs2); + setArg(call_mask_mask_op_3083, 7, vs1); } cc.bind(label_merge); } - auto tmp3068 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3068, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3068, 64, false) - , traits::vstart); + auto tmp3084 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3084, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3084, traits::vstart); } cc.bind(label_merge); } @@ -74010,12 +73666,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3069; - x86::Gp ret_val_illegal_vd_unmasked_3069 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3069, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3069; - setArg(call_illegal_vd_unmasked_3069, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3069, 0, ret_val_illegal_vd_unmasked_3069); + InvokeNode* call_illegal_vd_unmasked_3085; + x86::Gp ret_val_illegal_vd_unmasked_3085 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3085, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3085; + setArg(call_illegal_vd_unmasked_3085, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3085, 0, ret_val_illegal_vd_unmasked_3085); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74031,27 +73687,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3070; - auto mask_mask_op_3070_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3070_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3086; + auto mask_mask_op_3086_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3086_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3070, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3070, 0, V); - setArg(call_mask_mask_op_3070, 1, 24); - setArg(call_mask_mask_op_3070, 2, 2); - setArg(call_mask_mask_op_3070, 3, mask_mask_op_3070_arg3); - setArg(call_mask_mask_op_3070, 4, mask_mask_op_3070_arg4); - setArg(call_mask_mask_op_3070, 5, vd); - setArg(call_mask_mask_op_3070, 6, vs2); - setArg(call_mask_mask_op_3070, 7, vs1); + cc.invoke(&call_mask_mask_op_3086, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3086, 0, V); + setArg(call_mask_mask_op_3086, 1, 24); + setArg(call_mask_mask_op_3086, 2, 2); + setArg(call_mask_mask_op_3086, 3, mask_mask_op_3086_arg3); + setArg(call_mask_mask_op_3086, 4, mask_mask_op_3086_arg4); + setArg(call_mask_mask_op_3086, 5, vd); + setArg(call_mask_mask_op_3086, 6, vs2); + setArg(call_mask_mask_op_3086, 7, vs1); } cc.bind(label_merge); } - auto tmp3071 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3071, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3071, 64, false) - , traits::vstart); + auto tmp3087 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3087, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3087, traits::vstart); } cc.bind(label_merge); } @@ -74096,12 +73750,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3072; - x86::Gp ret_val_illegal_vd_unmasked_3072 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3072, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3072; - setArg(call_illegal_vd_unmasked_3072, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3072, 0, ret_val_illegal_vd_unmasked_3072); + InvokeNode* call_illegal_vd_unmasked_3088; + x86::Gp ret_val_illegal_vd_unmasked_3088 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3088, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3088; + setArg(call_illegal_vd_unmasked_3088, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3088, 0, ret_val_illegal_vd_unmasked_3088); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74117,27 +73771,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3073; - auto mask_mask_op_3073_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3073_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3089; + auto mask_mask_op_3089_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3089_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3073, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3073, 0, V); - setArg(call_mask_mask_op_3073, 1, 27); - setArg(call_mask_mask_op_3073, 2, 2); - setArg(call_mask_mask_op_3073, 3, mask_mask_op_3073_arg3); - setArg(call_mask_mask_op_3073, 4, mask_mask_op_3073_arg4); - setArg(call_mask_mask_op_3073, 5, vd); - setArg(call_mask_mask_op_3073, 6, vs2); - setArg(call_mask_mask_op_3073, 7, vs1); + cc.invoke(&call_mask_mask_op_3089, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3089, 0, V); + setArg(call_mask_mask_op_3089, 1, 27); + setArg(call_mask_mask_op_3089, 2, 2); + setArg(call_mask_mask_op_3089, 3, mask_mask_op_3089_arg3); + setArg(call_mask_mask_op_3089, 4, mask_mask_op_3089_arg4); + setArg(call_mask_mask_op_3089, 5, vd); + setArg(call_mask_mask_op_3089, 6, vs2); + setArg(call_mask_mask_op_3089, 7, vs1); } cc.bind(label_merge); } - auto tmp3074 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3074, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3074, 64, false) - , traits::vstart); + auto tmp3090 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3090, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3090, traits::vstart); } cc.bind(label_merge); } @@ -74182,12 +73834,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3075; - x86::Gp ret_val_illegal_vd_unmasked_3075 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3075, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3075; - setArg(call_illegal_vd_unmasked_3075, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3075, 0, ret_val_illegal_vd_unmasked_3075); + InvokeNode* call_illegal_vd_unmasked_3091; + x86::Gp ret_val_illegal_vd_unmasked_3091 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3091, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3091; + setArg(call_illegal_vd_unmasked_3091, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3091, 0, ret_val_illegal_vd_unmasked_3091); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74203,27 +73855,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3076; - auto mask_mask_op_3076_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3076_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3092; + auto mask_mask_op_3092_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3092_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3076, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3076, 0, V); - setArg(call_mask_mask_op_3076, 1, 26); - setArg(call_mask_mask_op_3076, 2, 2); - setArg(call_mask_mask_op_3076, 3, mask_mask_op_3076_arg3); - setArg(call_mask_mask_op_3076, 4, mask_mask_op_3076_arg4); - setArg(call_mask_mask_op_3076, 5, vd); - setArg(call_mask_mask_op_3076, 6, vs2); - setArg(call_mask_mask_op_3076, 7, vs1); + cc.invoke(&call_mask_mask_op_3092, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3092, 0, V); + setArg(call_mask_mask_op_3092, 1, 26); + setArg(call_mask_mask_op_3092, 2, 2); + setArg(call_mask_mask_op_3092, 3, mask_mask_op_3092_arg3); + setArg(call_mask_mask_op_3092, 4, mask_mask_op_3092_arg4); + setArg(call_mask_mask_op_3092, 5, vd); + setArg(call_mask_mask_op_3092, 6, vs2); + setArg(call_mask_mask_op_3092, 7, vs1); } cc.bind(label_merge); } - auto tmp3077 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3077, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3077, 64, false) - , traits::vstart); + auto tmp3093 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3093, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3093, traits::vstart); } cc.bind(label_merge); } @@ -74268,12 +73918,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3078; - x86::Gp ret_val_illegal_vd_unmasked_3078 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3078, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3078; - setArg(call_illegal_vd_unmasked_3078, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3078, 0, ret_val_illegal_vd_unmasked_3078); + InvokeNode* call_illegal_vd_unmasked_3094; + x86::Gp ret_val_illegal_vd_unmasked_3094 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3094, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3094; + setArg(call_illegal_vd_unmasked_3094, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3094, 0, ret_val_illegal_vd_unmasked_3094); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74289,27 +73939,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3079; - auto mask_mask_op_3079_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3079_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3095; + auto mask_mask_op_3095_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3095_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3079, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3079, 0, V); - setArg(call_mask_mask_op_3079, 1, 30); - setArg(call_mask_mask_op_3079, 2, 2); - setArg(call_mask_mask_op_3079, 3, mask_mask_op_3079_arg3); - setArg(call_mask_mask_op_3079, 4, mask_mask_op_3079_arg4); - setArg(call_mask_mask_op_3079, 5, vd); - setArg(call_mask_mask_op_3079, 6, vs2); - setArg(call_mask_mask_op_3079, 7, vs1); + cc.invoke(&call_mask_mask_op_3095, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3095, 0, V); + setArg(call_mask_mask_op_3095, 1, 30); + setArg(call_mask_mask_op_3095, 2, 2); + setArg(call_mask_mask_op_3095, 3, mask_mask_op_3095_arg3); + setArg(call_mask_mask_op_3095, 4, mask_mask_op_3095_arg4); + setArg(call_mask_mask_op_3095, 5, vd); + setArg(call_mask_mask_op_3095, 6, vs2); + setArg(call_mask_mask_op_3095, 7, vs1); } cc.bind(label_merge); } - auto tmp3080 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3080, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3080, 64, false) - , traits::vstart); + auto tmp3096 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3096, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3096, traits::vstart); } cc.bind(label_merge); } @@ -74354,12 +74002,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3081; - x86::Gp ret_val_illegal_vd_unmasked_3081 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3081, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3081; - setArg(call_illegal_vd_unmasked_3081, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3081, 0, ret_val_illegal_vd_unmasked_3081); + InvokeNode* call_illegal_vd_unmasked_3097; + x86::Gp ret_val_illegal_vd_unmasked_3097 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3097, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3097; + setArg(call_illegal_vd_unmasked_3097, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3097, 0, ret_val_illegal_vd_unmasked_3097); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74375,27 +74023,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3082; - auto mask_mask_op_3082_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3082_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3098; + auto mask_mask_op_3098_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3098_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3082, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3082, 0, V); - setArg(call_mask_mask_op_3082, 1, 28); - setArg(call_mask_mask_op_3082, 2, 2); - setArg(call_mask_mask_op_3082, 3, mask_mask_op_3082_arg3); - setArg(call_mask_mask_op_3082, 4, mask_mask_op_3082_arg4); - setArg(call_mask_mask_op_3082, 5, vd); - setArg(call_mask_mask_op_3082, 6, vs2); - setArg(call_mask_mask_op_3082, 7, vs1); + cc.invoke(&call_mask_mask_op_3098, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3098, 0, V); + setArg(call_mask_mask_op_3098, 1, 28); + setArg(call_mask_mask_op_3098, 2, 2); + setArg(call_mask_mask_op_3098, 3, mask_mask_op_3098_arg3); + setArg(call_mask_mask_op_3098, 4, mask_mask_op_3098_arg4); + setArg(call_mask_mask_op_3098, 5, vd); + setArg(call_mask_mask_op_3098, 6, vs2); + setArg(call_mask_mask_op_3098, 7, vs1); } cc.bind(label_merge); } - auto tmp3083 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3083, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3083, 64, false) - , traits::vstart); + auto tmp3099 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3099, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3099, traits::vstart); } cc.bind(label_merge); } @@ -74440,12 +74086,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3084; - x86::Gp ret_val_illegal_vd_unmasked_3084 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3084, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_vd_unmasked_3084; - setArg(call_illegal_vd_unmasked_3084, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3084, 0, ret_val_illegal_vd_unmasked_3084); + InvokeNode* call_illegal_vd_unmasked_3100; + x86::Gp ret_val_illegal_vd_unmasked_3100 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3100, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_vd_unmasked_3100; + setArg(call_illegal_vd_unmasked_3100, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3100, 0, ret_val_illegal_vd_unmasked_3100); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74461,27 +74107,25 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_mask_mask_op_3085; - auto mask_mask_op_3085_arg3 = load_reg_from_mem(jh, traits::vl); - auto mask_mask_op_3085_arg4 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_mask_op_3101; + auto mask_mask_op_3101_arg3 = load_reg_from_mem(jh, traits::vl); + auto mask_mask_op_3101_arg4 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_mask_op_3085, &mask_mask_op, FuncSignature::build()); - setArg(call_mask_mask_op_3085, 0, V); - setArg(call_mask_mask_op_3085, 1, 31); - setArg(call_mask_mask_op_3085, 2, 2); - setArg(call_mask_mask_op_3085, 3, mask_mask_op_3085_arg3); - setArg(call_mask_mask_op_3085, 4, mask_mask_op_3085_arg4); - setArg(call_mask_mask_op_3085, 5, vd); - setArg(call_mask_mask_op_3085, 6, vs2); - setArg(call_mask_mask_op_3085, 7, vs1); + cc.invoke(&call_mask_mask_op_3101, &mask_mask_op, FuncSignature::build()); + setArg(call_mask_mask_op_3101, 0, V); + setArg(call_mask_mask_op_3101, 1, 31); + setArg(call_mask_mask_op_3101, 2, 2); + setArg(call_mask_mask_op_3101, 3, mask_mask_op_3101_arg3); + setArg(call_mask_mask_op_3101, 4, mask_mask_op_3101_arg4); + setArg(call_mask_mask_op_3101, 5, vd); + setArg(call_mask_mask_op_3101, 6, vs2); + setArg(call_mask_mask_op_3101, 7, vs1); } cc.bind(label_merge); } - auto tmp3086 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3086, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3086, 64, false) - , traits::vstart); + auto tmp3102 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3102, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3102, traits::vstart); } cc.bind(label_merge); } @@ -74526,14 +74170,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3087; - x86::Gp ret_val_illegal_vd_unmasked_3087 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3087, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto tmp3088 = get_reg(cc, 8, false); - mov(cc, tmp3088, rd>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3088, ret_val_illegal_vd_unmasked_3087), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); - setArg(call_illegal_vd_unmasked_3087, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3087, 0, ret_val_illegal_vd_unmasked_3087); + InvokeNode* call_illegal_vd_unmasked_3103; + x86::Gp ret_val_illegal_vd_unmasked_3103 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3103, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3104 = get_reg(cc, 8, false); + mov(cc, tmp3104, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3104, ret_val_illegal_vd_unmasked_3103), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); + setArg(call_illegal_vd_unmasked_3103, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3103, 0, ret_val_illegal_vd_unmasked_3103); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74544,25 +74188,23 @@ template class vm_impl : public iss::asmjit::vm_base { cc.bind(label_else); { if(rd!=0){ - InvokeNode* call_vcpop_3089; - auto vcpop_3089_arg1 = load_reg_from_mem(jh, traits::vl); - auto vcpop_3089_arg2 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_vcpop_3105; + auto vcpop_3105_arg1 = load_reg_from_mem(jh, traits::vl); + auto vcpop_3105_arg2 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_vcpop_3089 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vcpop_3089, &vcpop, FuncSignature::build()); + x86::Gp ret_val_vcpop_3105 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vcpop_3105, &vcpop, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::X0+ rd), - ret_val_vcpop_3089); - setArg(call_vcpop_3089, 0, V); - setArg(call_vcpop_3089, 1, vcpop_3089_arg1); - setArg(call_vcpop_3089, 2, vcpop_3089_arg2); - setArg(call_vcpop_3089, 3, vm); - setArg(call_vcpop_3089, 4, vs2); - setRet(call_vcpop_3089, 0, ret_val_vcpop_3089); - auto tmp3090 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3090, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3090, 64, false) - , traits::vstart); + ret_val_vcpop_3105); + setArg(call_vcpop_3105, 0, V); + setArg(call_vcpop_3105, 1, vcpop_3105_arg1); + setArg(call_vcpop_3105, 2, vcpop_3105_arg2); + setArg(call_vcpop_3105, 3, vm); + setArg(call_vcpop_3105, 4, vs2); + setRet(call_vcpop_3105, 0, ret_val_vcpop_3105); + auto tmp3106 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3106, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3106, traits::vstart); } } cc.bind(label_merge); @@ -74608,14 +74250,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3091; - x86::Gp ret_val_illegal_vd_unmasked_3091 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3091, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto tmp3092 = get_reg(cc, 8, false); - mov(cc, tmp3092, rd>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3092, ret_val_illegal_vd_unmasked_3091), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); - setArg(call_illegal_vd_unmasked_3091, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3091, 0, ret_val_illegal_vd_unmasked_3091); + InvokeNode* call_illegal_vd_unmasked_3107; + x86::Gp ret_val_illegal_vd_unmasked_3107 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3107, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3108 = get_reg(cc, 8, false); + mov(cc, tmp3108, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3108, ret_val_illegal_vd_unmasked_3107), gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)); + setArg(call_illegal_vd_unmasked_3107, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3107, 0, ret_val_illegal_vd_unmasked_3107); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74626,25 +74268,23 @@ template class vm_impl : public iss::asmjit::vm_base { cc.bind(label_else); { if(rd!=0){ - InvokeNode* call_vfirst_3093; - auto vfirst_3093_arg1 = load_reg_from_mem(jh, traits::vl); - auto vfirst_3093_arg2 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_vfirst_3109; + auto vfirst_3109_arg1 = load_reg_from_mem(jh, traits::vl); + auto vfirst_3109_arg2 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_vfirst_3093 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_vfirst_3093, &vfirst, FuncSignature::build()); + x86::Gp ret_val_vfirst_3109 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_vfirst_3109, &vfirst, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::X0+ rd), - ret_val_vfirst_3093); - setArg(call_vfirst_3093, 0, V); - setArg(call_vfirst_3093, 1, vfirst_3093_arg1); - setArg(call_vfirst_3093, 2, vfirst_3093_arg2); - setArg(call_vfirst_3093, 3, vm); - setArg(call_vfirst_3093, 4, vs2); - setRet(call_vfirst_3093, 0, ret_val_vfirst_3093); - auto tmp3094 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3094, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3094, 64, false) - , traits::vstart); + ret_val_vfirst_3109); + setArg(call_vfirst_3109, 0, V); + setArg(call_vfirst_3109, 1, vfirst_3109_arg1); + setArg(call_vfirst_3109, 2, vfirst_3109_arg2); + setArg(call_vfirst_3109, 3, vm); + setArg(call_vfirst_3109, 4, vs2); + setRet(call_vfirst_3109, 0, ret_val_vfirst_3109); + auto tmp3110 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3110, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3110, traits::vstart); } } cc.bind(label_merge); @@ -74690,12 +74330,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3095; - x86::Gp ret_val_illegal_vd_unmasked_3095 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3095, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3095, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); - setArg(call_illegal_vd_unmasked_3095, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3095, 0, ret_val_illegal_vd_unmasked_3095); + InvokeNode* call_illegal_vd_unmasked_3111; + x86::Gp ret_val_illegal_vd_unmasked_3111 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3111, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3111, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3111, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3111, 0, ret_val_illegal_vd_unmasked_3111); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74705,23 +74345,21 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_mask_set_op_3096; - auto mask_set_op_3096_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_set_op_3096_arg3 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_set_op_3112; + auto mask_set_op_3112_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3112_arg3 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_set_op_3096, &mask_set_op, FuncSignature::build()); - setArg(call_mask_set_op_3096, 0, V); - setArg(call_mask_set_op_3096, 1, 1); - setArg(call_mask_set_op_3096, 2, mask_set_op_3096_arg2); - setArg(call_mask_set_op_3096, 3, mask_set_op_3096_arg3); - setArg(call_mask_set_op_3096, 4, vm); - setArg(call_mask_set_op_3096, 5, vd); - setArg(call_mask_set_op_3096, 6, vs2); - auto tmp3097 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3097, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3097, 64, false) - , traits::vstart); + cc.invoke(&call_mask_set_op_3112, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3112, 0, V); + setArg(call_mask_set_op_3112, 1, 1); + setArg(call_mask_set_op_3112, 2, mask_set_op_3112_arg2); + setArg(call_mask_set_op_3112, 3, mask_set_op_3112_arg3); + setArg(call_mask_set_op_3112, 4, vm); + setArg(call_mask_set_op_3112, 5, vd); + setArg(call_mask_set_op_3112, 6, vs2); + auto tmp3113 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3113, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3113, traits::vstart); } cc.bind(label_merge); } @@ -74766,12 +74404,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3098; - x86::Gp ret_val_illegal_vd_unmasked_3098 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3098, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3098, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); - setArg(call_illegal_vd_unmasked_3098, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3098, 0, ret_val_illegal_vd_unmasked_3098); + InvokeNode* call_illegal_vd_unmasked_3114; + x86::Gp ret_val_illegal_vd_unmasked_3114 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3114, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3114, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3114, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3114, 0, ret_val_illegal_vd_unmasked_3114); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74781,23 +74419,21 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_mask_set_op_3099; - auto mask_set_op_3099_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_set_op_3099_arg3 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_set_op_3115; + auto mask_set_op_3115_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3115_arg3 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_set_op_3099, &mask_set_op, FuncSignature::build()); - setArg(call_mask_set_op_3099, 0, V); - setArg(call_mask_set_op_3099, 1, 3); - setArg(call_mask_set_op_3099, 2, mask_set_op_3099_arg2); - setArg(call_mask_set_op_3099, 3, mask_set_op_3099_arg3); - setArg(call_mask_set_op_3099, 4, vm); - setArg(call_mask_set_op_3099, 5, vd); - setArg(call_mask_set_op_3099, 6, vs2); - auto tmp3100 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3100, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3100, 64, false) - , traits::vstart); + cc.invoke(&call_mask_set_op_3115, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3115, 0, V); + setArg(call_mask_set_op_3115, 1, 3); + setArg(call_mask_set_op_3115, 2, mask_set_op_3115_arg2); + setArg(call_mask_set_op_3115, 3, mask_set_op_3115_arg3); + setArg(call_mask_set_op_3115, 4, vm); + setArg(call_mask_set_op_3115, 5, vd); + setArg(call_mask_set_op_3115, 6, vs2); + auto tmp3116 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3116, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3116, traits::vstart); } cc.bind(label_merge); } @@ -74842,12 +74478,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3101; - x86::Gp ret_val_illegal_vd_unmasked_3101 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3101, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3101, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); - setArg(call_illegal_vd_unmasked_3101, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3101, 0, ret_val_illegal_vd_unmasked_3101); + InvokeNode* call_illegal_vd_unmasked_3117; + x86::Gp ret_val_illegal_vd_unmasked_3117 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3117, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3117, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3117, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3117, 0, ret_val_illegal_vd_unmasked_3117); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74857,23 +74493,21 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_mask_set_op_3102; - auto mask_set_op_3102_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_set_op_3102_arg3 = load_reg_from_mem(jh, traits::vstart); + InvokeNode* call_mask_set_op_3118; + auto mask_set_op_3118_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_set_op_3118_arg3 = load_reg_from_mem(jh, traits::vstart); auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_set_op_3102, &mask_set_op, FuncSignature::build()); - setArg(call_mask_set_op_3102, 0, V); - setArg(call_mask_set_op_3102, 1, 2); - setArg(call_mask_set_op_3102, 2, mask_set_op_3102_arg2); - setArg(call_mask_set_op_3102, 3, mask_set_op_3102_arg3); - setArg(call_mask_set_op_3102, 4, vm); - setArg(call_mask_set_op_3102, 5, vd); - setArg(call_mask_set_op_3102, 6, vs2); - auto tmp3103 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3103, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3103, 64, false) - , traits::vstart); + cc.invoke(&call_mask_set_op_3118, &mask_set_op, FuncSignature::build()); + setArg(call_mask_set_op_3118, 0, V); + setArg(call_mask_set_op_3118, 1, 2); + setArg(call_mask_set_op_3118, 2, mask_set_op_3118_arg2); + setArg(call_mask_set_op_3118, 3, mask_set_op_3118_arg3); + setArg(call_mask_set_op_3118, 4, vm); + setArg(call_mask_set_op_3118, 5, vd); + setArg(call_mask_set_op_3118, 6, vs2); + auto tmp3119 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3119, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3119, traits::vstart); } cc.bind(label_merge); } @@ -74918,12 +74552,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3104; - x86::Gp ret_val_illegal_vd_unmasked_3104 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3104, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3104, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); - setArg(call_illegal_vd_unmasked_3104, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3104, 0, ret_val_illegal_vd_unmasked_3104); + InvokeNode* call_illegal_vd_unmasked_3120; + x86::Gp ret_val_illegal_vd_unmasked_3120 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3120, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_vd_unmasked_3120, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0)), vd==vs2), (vm&&vd==0)); + setArg(call_illegal_vd_unmasked_3120, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3120, 0, ret_val_illegal_vd_unmasked_3120); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -74933,31 +74567,29 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3106; - x86::Gp ret_val_sew_3106 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3106, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_viota_3105; - auto viota_3105_arg1 = load_reg_from_mem(jh, traits::vl); - auto viota_3105_arg2 = load_reg_from_mem(jh, traits::vstart); - auto viota_3105_arg3 = load_reg_from_mem(jh, traits::vtype); - auto viota_3105_arg7 = ret_val_sew_3106; + InvokeNode* call_sew_3122; + x86::Gp ret_val_sew_3122 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3122, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_viota_3121; + auto viota_3121_arg1 = load_reg_from_mem(jh, traits::vl); + auto viota_3121_arg2 = load_reg_from_mem(jh, traits::vstart); + auto viota_3121_arg3 = load_reg_from_mem(jh, traits::vtype); + auto viota_3121_arg7 = ret_val_sew_3122; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_viota_3105, &viota, FuncSignature::build()); - setArg(call_sew_3106, 0, reinterpret_cast(this)); - setRet(call_sew_3106, 0, ret_val_sew_3106); - setArg(call_viota_3105, 0, V); - setArg(call_viota_3105, 1, viota_3105_arg1); - setArg(call_viota_3105, 2, viota_3105_arg2); - setArg(call_viota_3105, 3, viota_3105_arg3); - setArg(call_viota_3105, 4, vm); - setArg(call_viota_3105, 5, vd); - setArg(call_viota_3105, 6, vs2); - setArg(call_viota_3105, 7, viota_3105_arg7); - auto tmp3107 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3107, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3107, 64, false) - , traits::vstart); + cc.invoke(&call_viota_3121, &viota, FuncSignature::build()); + setArg(call_sew_3122, 0, reinterpret_cast(this)); + setRet(call_sew_3122, 0, ret_val_sew_3122); + setArg(call_viota_3121, 0, V); + setArg(call_viota_3121, 1, viota_3121_arg1); + setArg(call_viota_3121, 2, viota_3121_arg2); + setArg(call_viota_3121, 3, viota_3121_arg3); + setArg(call_viota_3121, 4, vm); + setArg(call_viota_3121, 5, vd); + setArg(call_viota_3121, 6, vs2); + setArg(call_viota_3121, 7, viota_3121_arg7); + auto tmp3123 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3123, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3123, traits::vstart); } cc.bind(label_merge); } @@ -75001,14 +74633,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3108; - x86::Gp ret_val_illegal_normal_3108 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3108, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_3108; - setArg(call_illegal_normal_3108, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3108, 1, vd); - setArg(call_illegal_normal_3108, 2, vm); - setRet(call_illegal_normal_3108, 0, ret_val_illegal_normal_3108); + InvokeNode* call_illegal_normal_3124; + x86::Gp ret_val_illegal_normal_3124 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3124, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_3124; + setArg(call_illegal_normal_3124, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3124, 1, vd); + setArg(call_illegal_normal_3124, 2, vm); + setRet(call_illegal_normal_3124, 0, ret_val_illegal_normal_3124); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75018,30 +74650,28 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3110; - x86::Gp ret_val_sew_3110 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3110, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vid_3109; - auto vid_3109_arg1 = load_reg_from_mem(jh, traits::vl); - auto vid_3109_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vid_3109_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vid_3109_arg6 = ret_val_sew_3110; + InvokeNode* call_sew_3126; + x86::Gp ret_val_sew_3126 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3126, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vid_3125; + auto vid_3125_arg1 = load_reg_from_mem(jh, traits::vl); + auto vid_3125_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vid_3125_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vid_3125_arg6 = ret_val_sew_3126; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vid_3109, &vid, FuncSignature::build()); - setArg(call_sew_3110, 0, reinterpret_cast(this)); - setRet(call_sew_3110, 0, ret_val_sew_3110); - setArg(call_vid_3109, 0, V); - setArg(call_vid_3109, 1, vid_3109_arg1); - setArg(call_vid_3109, 2, vid_3109_arg2); - setArg(call_vid_3109, 3, vid_3109_arg3); - setArg(call_vid_3109, 4, vm); - setArg(call_vid_3109, 5, vd); - setArg(call_vid_3109, 6, vid_3109_arg6); - auto tmp3111 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3111, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3111, 64, false) - , traits::vstart); + cc.invoke(&call_vid_3125, &vid, FuncSignature::build()); + setArg(call_sew_3126, 0, reinterpret_cast(this)); + setRet(call_sew_3126, 0, ret_val_sew_3126); + setArg(call_vid_3125, 0, V); + setArg(call_vid_3125, 1, vid_3125_arg1); + setArg(call_vid_3125, 2, vid_3125_arg2); + setArg(call_vid_3125, 3, vid_3125_arg3); + setArg(call_vid_3125, 4, vm); + setArg(call_vid_3125, 5, vd); + setArg(call_vid_3125, 6, vid_3125_arg6); + auto tmp3127 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3127, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3127, traits::vstart); } cc.bind(label_merge); } @@ -75085,14 +74715,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3112; - x86::Gp ret_val_illegal_vd_unmasked_3112 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3112, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto tmp3113 = get_reg(cc, 8, false); - mov(cc, tmp3113, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp3113, ret_val_illegal_vd_unmasked_3112); - setArg(call_illegal_vd_unmasked_3112, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3112, 0, ret_val_illegal_vd_unmasked_3112); + InvokeNode* call_illegal_vd_unmasked_3128; + x86::Gp ret_val_illegal_vd_unmasked_3128 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3128, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3129 = get_reg(cc, 8, false); + mov(cc, tmp3129, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3129, ret_val_illegal_vd_unmasked_3128); + setArg(call_illegal_vd_unmasked_3128, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3128, 0, ret_val_illegal_vd_unmasked_3128); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75108,32 +74738,30 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3115; - x86::Gp ret_val_sew_3115 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3115, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_scalar_to_vector_3114; - auto scalar_to_vector_3114_arg1 = load_reg_from_mem(jh, traits::vtype); - auto scalar_to_vector_3114_arg3 = gen_ext(cc, + InvokeNode* call_sew_3131; + x86::Gp ret_val_sew_3131 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3131, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_to_vector_3130; + auto scalar_to_vector_3130_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_to_vector_3130_arg3 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false), 64, true); - auto scalar_to_vector_3114_arg4 = ret_val_sew_3115; + auto scalar_to_vector_3130_arg4 = ret_val_sew_3131; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_scalar_to_vector_3114, &scalar_to_vector, FuncSignature::build()); - setArg(call_sew_3115, 0, reinterpret_cast(this)); - setRet(call_sew_3115, 0, ret_val_sew_3115); - setArg(call_scalar_to_vector_3114, 0, V); - setArg(call_scalar_to_vector_3114, 1, scalar_to_vector_3114_arg1); - setArg(call_scalar_to_vector_3114, 2, vd); - setArg(call_scalar_to_vector_3114, 3, scalar_to_vector_3114_arg3); - setArg(call_scalar_to_vector_3114, 4, scalar_to_vector_3114_arg4); + cc.invoke(&call_scalar_to_vector_3130, &scalar_to_vector, FuncSignature::build()); + setArg(call_sew_3131, 0, reinterpret_cast(this)); + setRet(call_sew_3131, 0, ret_val_sew_3131); + setArg(call_scalar_to_vector_3130, 0, V); + setArg(call_scalar_to_vector_3130, 1, scalar_to_vector_3130_arg1); + setArg(call_scalar_to_vector_3130, 2, vd); + setArg(call_scalar_to_vector_3130, 3, scalar_to_vector_3130_arg3); + setArg(call_scalar_to_vector_3130, 4, scalar_to_vector_3130_arg4); } cc.bind(label_merge); } - auto tmp3116 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3116, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3116, 64, false) - , traits::vstart); + auto tmp3132 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3132, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3132, traits::vstart); } cc.bind(label_merge); } @@ -75177,14 +74805,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3117; - x86::Gp ret_val_illegal_vd_unmasked_3117 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3117, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto tmp3118 = get_reg(cc, 8, false); - mov(cc, tmp3118, rd>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp3118, ret_val_illegal_vd_unmasked_3117); - setArg(call_illegal_vd_unmasked_3117, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3117, 0, ret_val_illegal_vd_unmasked_3117); + InvokeNode* call_illegal_vd_unmasked_3133; + x86::Gp ret_val_illegal_vd_unmasked_3133 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3133, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto tmp3134 = get_reg(cc, 8, false); + mov(cc, tmp3134, rd>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3134, ret_val_illegal_vd_unmasked_3133); + setArg(call_illegal_vd_unmasked_3133, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3133, 0, ret_val_illegal_vd_unmasked_3133); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75195,30 +74823,28 @@ template class vm_impl : public iss::asmjit::vm_base { cc.bind(label_else); { if(rd!=0){ - InvokeNode* call_sew_3120; - x86::Gp ret_val_sew_3120 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3120, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_scalar_from_vector_3119; - auto scalar_from_vector_3119_arg1 = load_reg_from_mem(jh, traits::vtype); - auto scalar_from_vector_3119_arg3 = ret_val_sew_3120; + InvokeNode* call_sew_3136; + x86::Gp ret_val_sew_3136 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3136, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_from_vector_3135; + auto scalar_from_vector_3135_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_from_vector_3135_arg3 = ret_val_sew_3136; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_scalar_from_vector_3119 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_scalar_from_vector_3119, &scalar_from_vector, FuncSignature::build()); + x86::Gp ret_val_scalar_from_vector_3135 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_scalar_from_vector_3135, &scalar_from_vector, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::X0+ rd), - ret_val_scalar_from_vector_3119); - setArg(call_sew_3120, 0, reinterpret_cast(this)); - setRet(call_sew_3120, 0, ret_val_sew_3120); - setArg(call_scalar_from_vector_3119, 0, V); - setArg(call_scalar_from_vector_3119, 1, scalar_from_vector_3119_arg1); - setArg(call_scalar_from_vector_3119, 2, vs2); - setArg(call_scalar_from_vector_3119, 3, scalar_from_vector_3119_arg3); - setRet(call_scalar_from_vector_3119, 0, ret_val_scalar_from_vector_3119); - } - auto tmp3121 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3121, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3121, 64, false) - , traits::vstart); + ret_val_scalar_from_vector_3135); + setArg(call_sew_3136, 0, reinterpret_cast(this)); + setRet(call_sew_3136, 0, ret_val_sew_3136); + setArg(call_scalar_from_vector_3135, 0, V); + setArg(call_scalar_from_vector_3135, 1, scalar_from_vector_3135_arg1); + setArg(call_scalar_from_vector_3135, 2, vs2); + setArg(call_scalar_from_vector_3135, 3, scalar_from_vector_3135_arg3); + setRet(call_scalar_from_vector_3135, 0, ret_val_scalar_from_vector_3135); + } + auto tmp3137 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3137, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3137, traits::vstart); } cc.bind(label_merge); } @@ -75264,14 +74890,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3122; - x86::Gp ret_val_illegal_normal_3122 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3122, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3122, vs2==vd); - setArg(call_illegal_normal_3122, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3122, 1, vd); - setArg(call_illegal_normal_3122, 2, vm); - setRet(call_illegal_normal_3122, 0, ret_val_illegal_normal_3122); + InvokeNode* call_illegal_normal_3138; + x86::Gp ret_val_illegal_normal_3138 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3138, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3138, vs2==vd); + setArg(call_illegal_normal_3138, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3138, 1, vd); + setArg(call_illegal_normal_3138, 2, vm); + setRet(call_illegal_normal_3138, 0, ret_val_illegal_normal_3138); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75287,35 +74913,33 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3124; - x86::Gp ret_val_sew_3124 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3124, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slideup_3123; - auto vector_slideup_3123_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slideup_3123_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slideup_3123_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slideup_3123_arg8 = ret_val_sew_3124; + InvokeNode* call_sew_3140; + x86::Gp ret_val_sew_3140 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3140, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slideup_3139; + auto vector_slideup_3139_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slideup_3139_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slideup_3139_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slideup_3139_arg8 = ret_val_sew_3140; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slideup_3123, &vector_slideup, FuncSignature::build()); - setArg(call_sew_3124, 0, reinterpret_cast(this)); - setRet(call_sew_3124, 0, ret_val_sew_3124); - setArg(call_vector_slideup_3123, 0, V); - setArg(call_vector_slideup_3123, 1, vector_slideup_3123_arg1); - setArg(call_vector_slideup_3123, 2, vector_slideup_3123_arg2); - setArg(call_vector_slideup_3123, 3, vector_slideup_3123_arg3); - setArg(call_vector_slideup_3123, 4, vm); - setArg(call_vector_slideup_3123, 5, vd); - setArg(call_vector_slideup_3123, 6, vs2); - setArg(call_vector_slideup_3123, 7, (uint64_t)simm); - setArg(call_vector_slideup_3123, 8, vector_slideup_3123_arg8); + cc.invoke(&call_vector_slideup_3139, &vector_slideup, FuncSignature::build()); + setArg(call_sew_3140, 0, reinterpret_cast(this)); + setRet(call_sew_3140, 0, ret_val_sew_3140); + setArg(call_vector_slideup_3139, 0, V); + setArg(call_vector_slideup_3139, 1, vector_slideup_3139_arg1); + setArg(call_vector_slideup_3139, 2, vector_slideup_3139_arg2); + setArg(call_vector_slideup_3139, 3, vector_slideup_3139_arg3); + setArg(call_vector_slideup_3139, 4, vm); + setArg(call_vector_slideup_3139, 5, vd); + setArg(call_vector_slideup_3139, 6, vs2); + setArg(call_vector_slideup_3139, 7, (uint64_t)simm); + setArg(call_vector_slideup_3139, 8, vector_slideup_3139_arg8); } cc.bind(label_merge); } - auto tmp3125 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3125, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3125, 64, false) - , traits::vstart); + auto tmp3141 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3141, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3141, traits::vstart); } cc.bind(label_merge); } @@ -75361,16 +74985,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3126; - x86::Gp ret_val_illegal_normal_3126 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3126, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp3127 = get_reg(cc, 8, false); - mov(cc, tmp3127, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3127, ret_val_illegal_normal_3126), vs2==vd); - setArg(call_illegal_normal_3126, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3126, 1, vd); - setArg(call_illegal_normal_3126, 2, vm); - setRet(call_illegal_normal_3126, 0, ret_val_illegal_normal_3126); + InvokeNode* call_illegal_normal_3142; + x86::Gp ret_val_illegal_normal_3142 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3142, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3143 = get_reg(cc, 8, false); + mov(cc, tmp3143, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3143, ret_val_illegal_normal_3142), vs2==vd); + setArg(call_illegal_normal_3142, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3142, 1, vd); + setArg(call_illegal_normal_3142, 2, vm); + setRet(call_illegal_normal_3142, 0, ret_val_illegal_normal_3142); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75386,36 +75010,34 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3129; - x86::Gp ret_val_sew_3129 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3129, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slideup_3128; - auto vector_slideup_3128_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slideup_3128_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slideup_3128_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slideup_3128_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); - auto vector_slideup_3128_arg8 = ret_val_sew_3129; + InvokeNode* call_sew_3145; + x86::Gp ret_val_sew_3145 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3145, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slideup_3144; + auto vector_slideup_3144_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slideup_3144_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slideup_3144_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slideup_3144_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_slideup_3144_arg8 = ret_val_sew_3145; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slideup_3128, &vector_slideup, FuncSignature::build()); - setArg(call_sew_3129, 0, reinterpret_cast(this)); - setRet(call_sew_3129, 0, ret_val_sew_3129); - setArg(call_vector_slideup_3128, 0, V); - setArg(call_vector_slideup_3128, 1, vector_slideup_3128_arg1); - setArg(call_vector_slideup_3128, 2, vector_slideup_3128_arg2); - setArg(call_vector_slideup_3128, 3, vector_slideup_3128_arg3); - setArg(call_vector_slideup_3128, 4, vm); - setArg(call_vector_slideup_3128, 5, vd); - setArg(call_vector_slideup_3128, 6, vs2); - setArg(call_vector_slideup_3128, 7, vector_slideup_3128_arg7); - setArg(call_vector_slideup_3128, 8, vector_slideup_3128_arg8); + cc.invoke(&call_vector_slideup_3144, &vector_slideup, FuncSignature::build()); + setArg(call_sew_3145, 0, reinterpret_cast(this)); + setRet(call_sew_3145, 0, ret_val_sew_3145); + setArg(call_vector_slideup_3144, 0, V); + setArg(call_vector_slideup_3144, 1, vector_slideup_3144_arg1); + setArg(call_vector_slideup_3144, 2, vector_slideup_3144_arg2); + setArg(call_vector_slideup_3144, 3, vector_slideup_3144_arg3); + setArg(call_vector_slideup_3144, 4, vm); + setArg(call_vector_slideup_3144, 5, vd); + setArg(call_vector_slideup_3144, 6, vs2); + setArg(call_vector_slideup_3144, 7, vector_slideup_3144_arg7); + setArg(call_vector_slideup_3144, 8, vector_slideup_3144_arg8); } cc.bind(label_merge); } - auto tmp3130 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3130, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3130, 64, false) - , traits::vstart); + auto tmp3146 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3146, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3146, traits::vstart); } cc.bind(label_merge); } @@ -75461,14 +75083,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3131; - x86::Gp ret_val_illegal_normal_3131 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3131, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = ret_val_illegal_normal_3131; - setArg(call_illegal_normal_3131, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3131, 1, vd); - setArg(call_illegal_normal_3131, 2, vm); - setRet(call_illegal_normal_3131, 0, ret_val_illegal_normal_3131); + InvokeNode* call_illegal_normal_3147; + x86::Gp ret_val_illegal_normal_3147 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3147, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = ret_val_illegal_normal_3147; + setArg(call_illegal_normal_3147, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3147, 1, vd); + setArg(call_illegal_normal_3147, 2, vm); + setRet(call_illegal_normal_3147, 0, ret_val_illegal_normal_3147); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75484,35 +75106,33 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3133; - x86::Gp ret_val_sew_3133 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3133, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slidedown_3132; - auto vector_slidedown_3132_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slidedown_3132_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slidedown_3132_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slidedown_3132_arg8 = ret_val_sew_3133; + InvokeNode* call_sew_3149; + x86::Gp ret_val_sew_3149 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3149, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slidedown_3148; + auto vector_slidedown_3148_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slidedown_3148_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slidedown_3148_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slidedown_3148_arg8 = ret_val_sew_3149; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slidedown_3132, &vector_slidedown, FuncSignature::build()); - setArg(call_sew_3133, 0, reinterpret_cast(this)); - setRet(call_sew_3133, 0, ret_val_sew_3133); - setArg(call_vector_slidedown_3132, 0, V); - setArg(call_vector_slidedown_3132, 1, vector_slidedown_3132_arg1); - setArg(call_vector_slidedown_3132, 2, vector_slidedown_3132_arg2); - setArg(call_vector_slidedown_3132, 3, vector_slidedown_3132_arg3); - setArg(call_vector_slidedown_3132, 4, vm); - setArg(call_vector_slidedown_3132, 5, vd); - setArg(call_vector_slidedown_3132, 6, vs2); - setArg(call_vector_slidedown_3132, 7, (uint64_t)simm); - setArg(call_vector_slidedown_3132, 8, vector_slidedown_3132_arg8); + cc.invoke(&call_vector_slidedown_3148, &vector_slidedown, FuncSignature::build()); + setArg(call_sew_3149, 0, reinterpret_cast(this)); + setRet(call_sew_3149, 0, ret_val_sew_3149); + setArg(call_vector_slidedown_3148, 0, V); + setArg(call_vector_slidedown_3148, 1, vector_slidedown_3148_arg1); + setArg(call_vector_slidedown_3148, 2, vector_slidedown_3148_arg2); + setArg(call_vector_slidedown_3148, 3, vector_slidedown_3148_arg3); + setArg(call_vector_slidedown_3148, 4, vm); + setArg(call_vector_slidedown_3148, 5, vd); + setArg(call_vector_slidedown_3148, 6, vs2); + setArg(call_vector_slidedown_3148, 7, (uint64_t)simm); + setArg(call_vector_slidedown_3148, 8, vector_slidedown_3148_arg8); } cc.bind(label_merge); } - auto tmp3134 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3134, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3134, 64, false) - , traits::vstart); + auto tmp3150 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3150, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3150, traits::vstart); } cc.bind(label_merge); } @@ -75558,16 +75178,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3135; - x86::Gp ret_val_illegal_normal_3135 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3135, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp3136 = get_reg(cc, 8, false); - mov(cc, tmp3136, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp3136, ret_val_illegal_normal_3135); - setArg(call_illegal_normal_3135, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3135, 1, vd); - setArg(call_illegal_normal_3135, 2, vm); - setRet(call_illegal_normal_3135, 0, ret_val_illegal_normal_3135); + InvokeNode* call_illegal_normal_3151; + x86::Gp ret_val_illegal_normal_3151 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3151, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3152 = get_reg(cc, 8, false); + mov(cc, tmp3152, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3152, ret_val_illegal_normal_3151); + setArg(call_illegal_normal_3151, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3151, 1, vd); + setArg(call_illegal_normal_3151, 2, vm); + setRet(call_illegal_normal_3151, 0, ret_val_illegal_normal_3151); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75583,36 +75203,34 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3138; - x86::Gp ret_val_sew_3138 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3138, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slidedown_3137; - auto vector_slidedown_3137_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slidedown_3137_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slidedown_3137_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slidedown_3137_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); - auto vector_slidedown_3137_arg8 = ret_val_sew_3138; + InvokeNode* call_sew_3154; + x86::Gp ret_val_sew_3154 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3154, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slidedown_3153; + auto vector_slidedown_3153_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slidedown_3153_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slidedown_3153_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slidedown_3153_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_slidedown_3153_arg8 = ret_val_sew_3154; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slidedown_3137, &vector_slidedown, FuncSignature::build()); - setArg(call_sew_3138, 0, reinterpret_cast(this)); - setRet(call_sew_3138, 0, ret_val_sew_3138); - setArg(call_vector_slidedown_3137, 0, V); - setArg(call_vector_slidedown_3137, 1, vector_slidedown_3137_arg1); - setArg(call_vector_slidedown_3137, 2, vector_slidedown_3137_arg2); - setArg(call_vector_slidedown_3137, 3, vector_slidedown_3137_arg3); - setArg(call_vector_slidedown_3137, 4, vm); - setArg(call_vector_slidedown_3137, 5, vd); - setArg(call_vector_slidedown_3137, 6, vs2); - setArg(call_vector_slidedown_3137, 7, vector_slidedown_3137_arg7); - setArg(call_vector_slidedown_3137, 8, vector_slidedown_3137_arg8); + cc.invoke(&call_vector_slidedown_3153, &vector_slidedown, FuncSignature::build()); + setArg(call_sew_3154, 0, reinterpret_cast(this)); + setRet(call_sew_3154, 0, ret_val_sew_3154); + setArg(call_vector_slidedown_3153, 0, V); + setArg(call_vector_slidedown_3153, 1, vector_slidedown_3153_arg1); + setArg(call_vector_slidedown_3153, 2, vector_slidedown_3153_arg2); + setArg(call_vector_slidedown_3153, 3, vector_slidedown_3153_arg3); + setArg(call_vector_slidedown_3153, 4, vm); + setArg(call_vector_slidedown_3153, 5, vd); + setArg(call_vector_slidedown_3153, 6, vs2); + setArg(call_vector_slidedown_3153, 7, vector_slidedown_3153_arg7); + setArg(call_vector_slidedown_3153, 8, vector_slidedown_3153_arg8); } cc.bind(label_merge); } - auto tmp3139 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3139, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3139, 64, false) - , traits::vstart); + auto tmp3155 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3155, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3155, traits::vstart); } cc.bind(label_merge); } @@ -75658,16 +75276,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3140; - x86::Gp ret_val_illegal_normal_3140 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3140, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp3141 = get_reg(cc, 8, false); - mov(cc, tmp3141, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3141, ret_val_illegal_normal_3140), vs2==vd); - setArg(call_illegal_normal_3140, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3140, 1, vd); - setArg(call_illegal_normal_3140, 2, vm); - setRet(call_illegal_normal_3140, 0, ret_val_illegal_normal_3140); + InvokeNode* call_illegal_normal_3156; + x86::Gp ret_val_illegal_normal_3156 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3156, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3157 = get_reg(cc, 8, false); + mov(cc, tmp3157, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3157, ret_val_illegal_normal_3156), vs2==vd); + setArg(call_illegal_normal_3156, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3156, 1, vd); + setArg(call_illegal_normal_3156, 2, vm); + setRet(call_illegal_normal_3156, 0, ret_val_illegal_normal_3156); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75683,37 +75301,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3143; - x86::Gp ret_val_sew_3143 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3143, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slide1up_3142; - auto vector_slide1up_3142_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slide1up_3142_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slide1up_3142_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slide1up_3142_arg7 = gen_ext(cc, + InvokeNode* call_sew_3159; + x86::Gp ret_val_sew_3159 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3159, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slide1up_3158; + auto vector_slide1up_3158_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slide1up_3158_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slide1up_3158_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slide1up_3158_arg7 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false); - auto vector_slide1up_3142_arg8 = ret_val_sew_3143; + auto vector_slide1up_3158_arg8 = ret_val_sew_3159; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slide1up_3142, &vector_slide1up, FuncSignature::build()); - setArg(call_sew_3143, 0, reinterpret_cast(this)); - setRet(call_sew_3143, 0, ret_val_sew_3143); - setArg(call_vector_slide1up_3142, 0, V); - setArg(call_vector_slide1up_3142, 1, vector_slide1up_3142_arg1); - setArg(call_vector_slide1up_3142, 2, vector_slide1up_3142_arg2); - setArg(call_vector_slide1up_3142, 3, vector_slide1up_3142_arg3); - setArg(call_vector_slide1up_3142, 4, vm); - setArg(call_vector_slide1up_3142, 5, vd); - setArg(call_vector_slide1up_3142, 6, vs2); - setArg(call_vector_slide1up_3142, 7, vector_slide1up_3142_arg7); - setArg(call_vector_slide1up_3142, 8, vector_slide1up_3142_arg8); + cc.invoke(&call_vector_slide1up_3158, &vector_slide1up, FuncSignature::build()); + setArg(call_sew_3159, 0, reinterpret_cast(this)); + setRet(call_sew_3159, 0, ret_val_sew_3159); + setArg(call_vector_slide1up_3158, 0, V); + setArg(call_vector_slide1up_3158, 1, vector_slide1up_3158_arg1); + setArg(call_vector_slide1up_3158, 2, vector_slide1up_3158_arg2); + setArg(call_vector_slide1up_3158, 3, vector_slide1up_3158_arg3); + setArg(call_vector_slide1up_3158, 4, vm); + setArg(call_vector_slide1up_3158, 5, vd); + setArg(call_vector_slide1up_3158, 6, vs2); + setArg(call_vector_slide1up_3158, 7, vector_slide1up_3158_arg7); + setArg(call_vector_slide1up_3158, 8, vector_slide1up_3158_arg8); } cc.bind(label_merge); } - auto tmp3144 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3144, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3144, 64, false) - , traits::vstart); + auto tmp3160 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3160, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3160, traits::vstart); } cc.bind(label_merge); } @@ -75759,16 +75375,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3145; - x86::Gp ret_val_illegal_normal_3145 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3145, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp3146 = get_reg(cc, 8, false); - mov(cc, tmp3146, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, tmp3146, ret_val_illegal_normal_3145); - setArg(call_illegal_normal_3145, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3145, 1, vd); - setArg(call_illegal_normal_3145, 2, vm); - setRet(call_illegal_normal_3145, 0, ret_val_illegal_normal_3145); + InvokeNode* call_illegal_normal_3161; + x86::Gp ret_val_illegal_normal_3161 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3161, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3162 = get_reg(cc, 8, false); + mov(cc, tmp3162, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, tmp3162, ret_val_illegal_normal_3161); + setArg(call_illegal_normal_3161, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3161, 1, vd); + setArg(call_illegal_normal_3161, 2, vm); + setRet(call_illegal_normal_3161, 0, ret_val_illegal_normal_3161); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75784,37 +75400,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3148; - x86::Gp ret_val_sew_3148 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3148, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_slide1down_3147; - auto vector_slide1down_3147_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_slide1down_3147_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_slide1down_3147_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_slide1down_3147_arg7 = gen_ext(cc, + InvokeNode* call_sew_3164; + x86::Gp ret_val_sew_3164 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3164, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_slide1down_3163; + auto vector_slide1down_3163_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_slide1down_3163_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_slide1down_3163_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_slide1down_3163_arg7 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs1), 64, false); - auto vector_slide1down_3147_arg8 = ret_val_sew_3148; + auto vector_slide1down_3163_arg8 = ret_val_sew_3164; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_slide1down_3147, &vector_slide1down, FuncSignature::build()); - setArg(call_sew_3148, 0, reinterpret_cast(this)); - setRet(call_sew_3148, 0, ret_val_sew_3148); - setArg(call_vector_slide1down_3147, 0, V); - setArg(call_vector_slide1down_3147, 1, vector_slide1down_3147_arg1); - setArg(call_vector_slide1down_3147, 2, vector_slide1down_3147_arg2); - setArg(call_vector_slide1down_3147, 3, vector_slide1down_3147_arg3); - setArg(call_vector_slide1down_3147, 4, vm); - setArg(call_vector_slide1down_3147, 5, vd); - setArg(call_vector_slide1down_3147, 6, vs2); - setArg(call_vector_slide1down_3147, 7, vector_slide1down_3147_arg7); - setArg(call_vector_slide1down_3147, 8, vector_slide1down_3147_arg8); + cc.invoke(&call_vector_slide1down_3163, &vector_slide1down, FuncSignature::build()); + setArg(call_sew_3164, 0, reinterpret_cast(this)); + setRet(call_sew_3164, 0, ret_val_sew_3164); + setArg(call_vector_slide1down_3163, 0, V); + setArg(call_vector_slide1down_3163, 1, vector_slide1down_3163_arg1); + setArg(call_vector_slide1down_3163, 2, vector_slide1down_3163_arg2); + setArg(call_vector_slide1down_3163, 3, vector_slide1down_3163_arg3); + setArg(call_vector_slide1down_3163, 4, vm); + setArg(call_vector_slide1down_3163, 5, vd); + setArg(call_vector_slide1down_3163, 6, vs2); + setArg(call_vector_slide1down_3163, 7, vector_slide1down_3163_arg7); + setArg(call_vector_slide1down_3163, 8, vector_slide1down_3163_arg8); } cc.bind(label_merge); } - auto tmp3149 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3149, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3149, 64, false) - , traits::vstart); + auto tmp3165 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3165, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3165, traits::vstart); } cc.bind(label_merge); } @@ -75860,14 +75474,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3150; - x86::Gp ret_val_illegal_normal_3150 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3150, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3150, vs2==vd); - setArg(call_illegal_normal_3150, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3150, 1, vd); - setArg(call_illegal_normal_3150, 2, vm); - setRet(call_illegal_normal_3150, 0, ret_val_illegal_normal_3150); + InvokeNode* call_illegal_normal_3166; + x86::Gp ret_val_illegal_normal_3166 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3166, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_normal_3166, vs2==vd); + setArg(call_illegal_normal_3166, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3166, 1, vd); + setArg(call_illegal_normal_3166, 2, vm); + setRet(call_illegal_normal_3166, 0, ret_val_illegal_normal_3166); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75877,32 +75491,30 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3152; - x86::Gp ret_val_sew_3152 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3152, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_imm_gather_3151; - auto vector_imm_gather_3151_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_imm_gather_3151_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_imm_gather_3151_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_imm_gather_3151_arg8 = ret_val_sew_3152; + InvokeNode* call_sew_3168; + x86::Gp ret_val_sew_3168 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3168, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_gather_3167; + auto vector_imm_gather_3167_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_gather_3167_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_gather_3167_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_gather_3167_arg8 = ret_val_sew_3168; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_gather_3151, &vector_imm_gather, FuncSignature::build()); - setArg(call_sew_3152, 0, reinterpret_cast(this)); - setRet(call_sew_3152, 0, ret_val_sew_3152); - setArg(call_vector_imm_gather_3151, 0, V); - setArg(call_vector_imm_gather_3151, 1, vector_imm_gather_3151_arg1); - setArg(call_vector_imm_gather_3151, 2, vector_imm_gather_3151_arg2); - setArg(call_vector_imm_gather_3151, 3, vector_imm_gather_3151_arg3); - setArg(call_vector_imm_gather_3151, 4, vm); - setArg(call_vector_imm_gather_3151, 5, vd); - setArg(call_vector_imm_gather_3151, 6, vs2); - setArg(call_vector_imm_gather_3151, 7, (uint64_t)simm); - setArg(call_vector_imm_gather_3151, 8, vector_imm_gather_3151_arg8); - auto tmp3153 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3153, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3153, 64, false) - , traits::vstart); + cc.invoke(&call_vector_imm_gather_3167, &vector_imm_gather, FuncSignature::build()); + setArg(call_sew_3168, 0, reinterpret_cast(this)); + setRet(call_sew_3168, 0, ret_val_sew_3168); + setArg(call_vector_imm_gather_3167, 0, V); + setArg(call_vector_imm_gather_3167, 1, vector_imm_gather_3167_arg1); + setArg(call_vector_imm_gather_3167, 2, vector_imm_gather_3167_arg2); + setArg(call_vector_imm_gather_3167, 3, vector_imm_gather_3167_arg3); + setArg(call_vector_imm_gather_3167, 4, vm); + setArg(call_vector_imm_gather_3167, 5, vd); + setArg(call_vector_imm_gather_3167, 6, vs2); + setArg(call_vector_imm_gather_3167, 7, (uint64_t)simm); + setArg(call_vector_imm_gather_3167, 8, vector_imm_gather_3167_arg8); + auto tmp3169 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3169, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3169, traits::vstart); } cc.bind(label_merge); } @@ -75948,14 +75560,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3154; - x86::Gp ret_val_illegal_normal_3154 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3154, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3154, vs1==vd), vs2==vd); - setArg(call_illegal_normal_3154, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3154, 1, vd); - setArg(call_illegal_normal_3154, 2, vm); - setRet(call_illegal_normal_3154, 0, ret_val_illegal_normal_3154); + InvokeNode* call_illegal_normal_3170; + x86::Gp ret_val_illegal_normal_3170 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3170, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3170, vs1==vd), vs2==vd); + setArg(call_illegal_normal_3170, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3170, 1, vd); + setArg(call_illegal_normal_3170, 2, vm); + setRet(call_illegal_normal_3170, 0, ret_val_illegal_normal_3170); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -75965,32 +75577,30 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3156; - x86::Gp ret_val_sew_3156 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3156, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_vector_gather_3155; - auto vector_vector_gather_3155_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_vector_gather_3155_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_vector_gather_3155_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_vector_gather_3155_arg8 = ret_val_sew_3156; + InvokeNode* call_sew_3172; + x86::Gp ret_val_sew_3172 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3172, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_gather_3171; + auto vector_vector_gather_3171_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_gather_3171_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_gather_3171_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_gather_3171_arg8 = ret_val_sew_3172; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_gather_3155, &vector_vector_gather, FuncSignature::build()); - setArg(call_sew_3156, 0, reinterpret_cast(this)); - setRet(call_sew_3156, 0, ret_val_sew_3156); - setArg(call_vector_vector_gather_3155, 0, V); - setArg(call_vector_vector_gather_3155, 1, vector_vector_gather_3155_arg1); - setArg(call_vector_vector_gather_3155, 2, vector_vector_gather_3155_arg2); - setArg(call_vector_vector_gather_3155, 3, vector_vector_gather_3155_arg3); - setArg(call_vector_vector_gather_3155, 4, vm); - setArg(call_vector_vector_gather_3155, 5, vd); - setArg(call_vector_vector_gather_3155, 6, vs2); - setArg(call_vector_vector_gather_3155, 7, vs1); - setArg(call_vector_vector_gather_3155, 8, vector_vector_gather_3155_arg8); - auto tmp3157 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3157, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3157, 64, false) - , traits::vstart); + cc.invoke(&call_vector_vector_gather_3171, &vector_vector_gather, FuncSignature::build()); + setArg(call_sew_3172, 0, reinterpret_cast(this)); + setRet(call_sew_3172, 0, ret_val_sew_3172); + setArg(call_vector_vector_gather_3171, 0, V); + setArg(call_vector_vector_gather_3171, 1, vector_vector_gather_3171_arg1); + setArg(call_vector_vector_gather_3171, 2, vector_vector_gather_3171_arg2); + setArg(call_vector_vector_gather_3171, 3, vector_vector_gather_3171_arg3); + setArg(call_vector_vector_gather_3171, 4, vm); + setArg(call_vector_vector_gather_3171, 5, vd); + setArg(call_vector_vector_gather_3171, 6, vs2); + setArg(call_vector_vector_gather_3171, 7, vs1); + setArg(call_vector_vector_gather_3171, 8, vector_vector_gather_3171_arg8); + auto tmp3173 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3173, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3173, traits::vstart); } cc.bind(label_merge); } @@ -76036,16 +75646,16 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3158; - x86::Gp ret_val_illegal_normal_3158 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3158, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto tmp3159 = get_reg(cc, 8, false); - mov(cc, tmp3159, rs1>=static_cast(traits::RFS)); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3159, ret_val_illegal_normal_3158), vs2==vd); - setArg(call_illegal_normal_3158, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3158, 1, vd); - setArg(call_illegal_normal_3158, 2, vm); - setRet(call_illegal_normal_3158, 0, ret_val_illegal_normal_3158); + InvokeNode* call_illegal_normal_3174; + x86::Gp ret_val_illegal_normal_3174 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3174, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto tmp3175 = get_reg(cc, 8, false); + mov(cc, tmp3175, rs1>=static_cast(traits::RFS)); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, tmp3175, ret_val_illegal_normal_3174), vs2==vd); + setArg(call_illegal_normal_3174, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3174, 1, vd); + setArg(call_illegal_normal_3174, 2, vm); + setRet(call_illegal_normal_3174, 0, ret_val_illegal_normal_3174); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76055,33 +75665,31 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3161; - x86::Gp ret_val_sew_3161 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3161, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_imm_gather_3160; - auto vector_imm_gather_3160_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_imm_gather_3160_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_imm_gather_3160_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_imm_gather_3160_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); - auto vector_imm_gather_3160_arg8 = ret_val_sew_3161; + InvokeNode* call_sew_3177; + x86::Gp ret_val_sew_3177 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3177, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_gather_3176; + auto vector_imm_gather_3176_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_gather_3176_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_gather_3176_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_gather_3176_arg7 = load_reg_from_mem_Gp(jh, traits::X0 + rs1); + auto vector_imm_gather_3176_arg8 = ret_val_sew_3177; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_gather_3160, &vector_imm_gather, FuncSignature::build()); - setArg(call_sew_3161, 0, reinterpret_cast(this)); - setRet(call_sew_3161, 0, ret_val_sew_3161); - setArg(call_vector_imm_gather_3160, 0, V); - setArg(call_vector_imm_gather_3160, 1, vector_imm_gather_3160_arg1); - setArg(call_vector_imm_gather_3160, 2, vector_imm_gather_3160_arg2); - setArg(call_vector_imm_gather_3160, 3, vector_imm_gather_3160_arg3); - setArg(call_vector_imm_gather_3160, 4, vm); - setArg(call_vector_imm_gather_3160, 5, vd); - setArg(call_vector_imm_gather_3160, 6, vs2); - setArg(call_vector_imm_gather_3160, 7, vector_imm_gather_3160_arg7); - setArg(call_vector_imm_gather_3160, 8, vector_imm_gather_3160_arg8); - auto tmp3162 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3162, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3162, 64, false) - , traits::vstart); + cc.invoke(&call_vector_imm_gather_3176, &vector_imm_gather, FuncSignature::build()); + setArg(call_sew_3177, 0, reinterpret_cast(this)); + setRet(call_sew_3177, 0, ret_val_sew_3177); + setArg(call_vector_imm_gather_3176, 0, V); + setArg(call_vector_imm_gather_3176, 1, vector_imm_gather_3176_arg1); + setArg(call_vector_imm_gather_3176, 2, vector_imm_gather_3176_arg2); + setArg(call_vector_imm_gather_3176, 3, vector_imm_gather_3176_arg3); + setArg(call_vector_imm_gather_3176, 4, vm); + setArg(call_vector_imm_gather_3176, 5, vd); + setArg(call_vector_imm_gather_3176, 6, vs2); + setArg(call_vector_imm_gather_3176, 7, vector_imm_gather_3176_arg7); + setArg(call_vector_imm_gather_3176, 8, vector_imm_gather_3176_arg8); + auto tmp3178 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3178, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3178, traits::vstart); } cc.bind(label_merge); } @@ -76127,14 +75735,14 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_normal_3163; - x86::Gp ret_val_illegal_normal_3163 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_normal_3163, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3163, vs1==vd), vs2==vd); - setArg(call_illegal_normal_3163, 0, reinterpret_cast(this)); - setArg(call_illegal_normal_3163, 1, vd); - setArg(call_illegal_normal_3163, 2, vm); - setRet(call_illegal_normal_3163, 0, ret_val_illegal_normal_3163); + InvokeNode* call_illegal_normal_3179; + x86::Gp ret_val_illegal_normal_3179 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_normal_3179, (uintptr_t)&vm_impl::_illegal_normal, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_normal_3179, vs1==vd), vs2==vd); + setArg(call_illegal_normal_3179, 0, reinterpret_cast(this)); + setArg(call_illegal_normal_3179, 1, vd); + setArg(call_illegal_normal_3179, 2, vm); + setRet(call_illegal_normal_3179, 0, ret_val_illegal_normal_3179); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76144,32 +75752,30 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3165; - x86::Gp ret_val_sew_3165 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3165, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_vector_gatherei16_3164; - auto vector_vector_gatherei16_3164_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_vector_gatherei16_3164_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_vector_gatherei16_3164_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_vector_gatherei16_3164_arg8 = ret_val_sew_3165; + InvokeNode* call_sew_3181; + x86::Gp ret_val_sew_3181 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3181, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_vector_gatherei16_3180; + auto vector_vector_gatherei16_3180_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_vector_gatherei16_3180_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_vector_gatherei16_3180_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_vector_gatherei16_3180_arg8 = ret_val_sew_3181; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_vector_gatherei16_3164, &vector_vector_gatherei16, FuncSignature::build()); - setArg(call_sew_3165, 0, reinterpret_cast(this)); - setRet(call_sew_3165, 0, ret_val_sew_3165); - setArg(call_vector_vector_gatherei16_3164, 0, V); - setArg(call_vector_vector_gatherei16_3164, 1, vector_vector_gatherei16_3164_arg1); - setArg(call_vector_vector_gatherei16_3164, 2, vector_vector_gatherei16_3164_arg2); - setArg(call_vector_vector_gatherei16_3164, 3, vector_vector_gatherei16_3164_arg3); - setArg(call_vector_vector_gatherei16_3164, 4, vm); - setArg(call_vector_vector_gatherei16_3164, 5, vd); - setArg(call_vector_vector_gatherei16_3164, 6, vs2); - setArg(call_vector_vector_gatherei16_3164, 7, vs1); - setArg(call_vector_vector_gatherei16_3164, 8, vector_vector_gatherei16_3164_arg8); - auto tmp3166 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3166, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3166, 64, false) - , traits::vstart); + cc.invoke(&call_vector_vector_gatherei16_3180, &vector_vector_gatherei16, FuncSignature::build()); + setArg(call_sew_3181, 0, reinterpret_cast(this)); + setRet(call_sew_3181, 0, ret_val_sew_3181); + setArg(call_vector_vector_gatherei16_3180, 0, V); + setArg(call_vector_vector_gatherei16_3180, 1, vector_vector_gatherei16_3180_arg1); + setArg(call_vector_vector_gatherei16_3180, 2, vector_vector_gatherei16_3180_arg2); + setArg(call_vector_vector_gatherei16_3180, 3, vector_vector_gatherei16_3180_arg3); + setArg(call_vector_vector_gatherei16_3180, 4, vm); + setArg(call_vector_vector_gatherei16_3180, 5, vd); + setArg(call_vector_vector_gatherei16_3180, 6, vs2); + setArg(call_vector_vector_gatherei16_3180, 7, vs1); + setArg(call_vector_vector_gatherei16_3180, 8, vector_vector_gatherei16_3180_arg8); + auto tmp3182 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3182, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3182, traits::vstart); } cc.bind(label_merge); } @@ -76214,12 +75820,12 @@ template class vm_impl : public iss::asmjit::vm_base { /*generate behavior*/ { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_vd_unmasked_3167; - x86::Gp ret_val_illegal_vd_unmasked_3167 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_vd_unmasked_3167, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0), vs1==vd), vs2==vd), ret_val_illegal_vd_unmasked_3167); - setArg(call_illegal_vd_unmasked_3167, 0, reinterpret_cast(this)); - setRet(call_illegal_vd_unmasked_3167, 0, ret_val_illegal_vd_unmasked_3167); + InvokeNode* call_illegal_vd_unmasked_3183; + x86::Gp ret_val_illegal_vd_unmasked_3183 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_vd_unmasked_3183, (uintptr_t)&vm_impl::_illegal_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, ne, load_reg_from_mem(jh, traits::vstart), 0), vs1==vd), vs2==vd), ret_val_illegal_vd_unmasked_3183); + setArg(call_illegal_vd_unmasked_3183, 0, reinterpret_cast(this)); + setRet(call_illegal_vd_unmasked_3183, 0, ret_val_illegal_vd_unmasked_3183); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76235,34 +75841,32 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3169; - x86::Gp ret_val_sew_3169 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3169, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_compress_3168; - auto vector_compress_3168_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_compress_3168_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_compress_3168_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_compress_3168_arg7 = ret_val_sew_3169; + InvokeNode* call_sew_3185; + x86::Gp ret_val_sew_3185 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3185, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_compress_3184; + auto vector_compress_3184_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_compress_3184_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_compress_3184_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_compress_3184_arg7 = ret_val_sew_3185; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_compress_3168, &vector_compress, FuncSignature::build()); - setArg(call_sew_3169, 0, reinterpret_cast(this)); - setRet(call_sew_3169, 0, ret_val_sew_3169); - setArg(call_vector_compress_3168, 0, V); - setArg(call_vector_compress_3168, 1, vector_compress_3168_arg1); - setArg(call_vector_compress_3168, 2, vector_compress_3168_arg2); - setArg(call_vector_compress_3168, 3, vector_compress_3168_arg3); - setArg(call_vector_compress_3168, 4, vd); - setArg(call_vector_compress_3168, 5, vs2); - setArg(call_vector_compress_3168, 6, vs1); - setArg(call_vector_compress_3168, 7, vector_compress_3168_arg7); + cc.invoke(&call_vector_compress_3184, &vector_compress, FuncSignature::build()); + setArg(call_sew_3185, 0, reinterpret_cast(this)); + setRet(call_sew_3185, 0, ret_val_sew_3185); + setArg(call_vector_compress_3184, 0, V); + setArg(call_vector_compress_3184, 1, vector_compress_3184_arg1); + setArg(call_vector_compress_3184, 2, vector_compress_3184_arg2); + setArg(call_vector_compress_3184, 3, vector_compress_3184_arg3); + setArg(call_vector_compress_3184, 4, vd); + setArg(call_vector_compress_3184, 5, vs2); + setArg(call_vector_compress_3184, 6, vs1); + setArg(call_vector_compress_3184, 7, vector_compress_3184_arg7); } cc.bind(label_merge); } - auto tmp3170 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3170, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3170, 64, false) - , traits::vstart); + auto tmp3186 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3186, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3186, traits::vstart); } cc.bind(label_merge); } @@ -76304,13 +75908,13 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_vector_whole_move_3171; + InvokeNode* call_vector_whole_move_3187; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_whole_move_3171, &vector_whole_move, FuncSignature::build()); - setArg(call_vector_whole_move_3171, 0, V); - setArg(call_vector_whole_move_3171, 1, vd); - setArg(call_vector_whole_move_3171, 2, vs2); - setArg(call_vector_whole_move_3171, 3, 1); + cc.invoke(&call_vector_whole_move_3187, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3187, 0, V); + setArg(call_vector_whole_move_3187, 1, vd); + setArg(call_vector_whole_move_3187, 2, vs2); + setArg(call_vector_whole_move_3187, 3, 1); auto returnValue = CONT; gen_sync(jh, POST_SYNC, 728); @@ -76353,13 +75957,13 @@ template class vm_impl : public iss::asmjit::vm_base { gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else { - InvokeNode* call_vector_whole_move_3172; + InvokeNode* call_vector_whole_move_3188; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_whole_move_3172, &vector_whole_move, FuncSignature::build()); - setArg(call_vector_whole_move_3172, 0, V); - setArg(call_vector_whole_move_3172, 1, vd); - setArg(call_vector_whole_move_3172, 2, vs2); - setArg(call_vector_whole_move_3172, 3, 2); + cc.invoke(&call_vector_whole_move_3188, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3188, 0, V); + setArg(call_vector_whole_move_3188, 1, vd); + setArg(call_vector_whole_move_3188, 2, vs2); + setArg(call_vector_whole_move_3188, 3, 2); } auto returnValue = CONT; @@ -76403,13 +76007,13 @@ template class vm_impl : public iss::asmjit::vm_base { gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else { - InvokeNode* call_vector_whole_move_3173; + InvokeNode* call_vector_whole_move_3189; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_whole_move_3173, &vector_whole_move, FuncSignature::build()); - setArg(call_vector_whole_move_3173, 0, V); - setArg(call_vector_whole_move_3173, 1, vd); - setArg(call_vector_whole_move_3173, 2, vs2); - setArg(call_vector_whole_move_3173, 3, 4); + cc.invoke(&call_vector_whole_move_3189, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3189, 0, V); + setArg(call_vector_whole_move_3189, 1, vd); + setArg(call_vector_whole_move_3189, 2, vs2); + setArg(call_vector_whole_move_3189, 3, 4); } auto returnValue = CONT; @@ -76453,13 +76057,13 @@ template class vm_impl : public iss::asmjit::vm_base { gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); } else { - InvokeNode* call_vector_whole_move_3174; + InvokeNode* call_vector_whole_move_3190; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_whole_move_3174, &vector_whole_move, FuncSignature::build()); - setArg(call_vector_whole_move_3174, 0, V); - setArg(call_vector_whole_move_3174, 1, vd); - setArg(call_vector_whole_move_3174, 2, vs2); - setArg(call_vector_whole_move_3174, 3, 8); + cc.invoke(&call_vector_whole_move_3190, &vector_whole_move, FuncSignature::build()); + setArg(call_vector_whole_move_3190, 0, V); + setArg(call_vector_whole_move_3190, 1, vd); + setArg(call_vector_whole_move_3190, 2, vs2); + setArg(call_vector_whole_move_3190, 3, 8); } auto returnValue = CONT; @@ -76499,28 +76103,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3175; - x86::Gp ret_val_get_sew_pow_3175 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3175, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3176 = get_reg(cc, 8, false); - mov(cc, tmp3176, 1); + InvokeNode* call_get_sew_pow_3191; + x86::Gp ret_val_get_sew_pow_3191 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3191, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3192 = get_reg(cc, 8, false); + mov(cc, tmp3192, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3176, (ret_val_get_sew_pow_3175))), 8, false), ~ 1); - setArg(call_get_sew_pow_3175, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3175, 0, ret_val_get_sew_pow_3175); + (gen_operation(cc, shl, tmp3192, (ret_val_get_sew_pow_3191))), 8, false), ~ 1); + setArg(call_get_sew_pow_3191, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3191, 0, ret_val_get_sew_pow_3191); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3177; - auto illegal_fp_vd_unmasked_3177_arg0 = SEW; - auto illegal_fp_vd_unmasked_3177_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3177 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3177, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3177; - setArg(call_illegal_fp_vd_unmasked_3177, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3177, 1, illegal_fp_vd_unmasked_3177_arg0); - setArg(call_illegal_fp_vd_unmasked_3177, 2, illegal_fp_vd_unmasked_3177_arg1); - setRet(call_illegal_fp_vd_unmasked_3177, 0, ret_val_illegal_fp_vd_unmasked_3177); + InvokeNode* call_illegal_fp_vd_unmasked_3193; + auto illegal_fp_vd_unmasked_3193_arg0 = SEW; + auto illegal_fp_vd_unmasked_3193_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3193 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3193, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3193; + setArg(call_illegal_fp_vd_unmasked_3193, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3193, 1, illegal_fp_vd_unmasked_3193_arg0); + setArg(call_illegal_fp_vd_unmasked_3193, 2, illegal_fp_vd_unmasked_3193_arg1); + setRet(call_illegal_fp_vd_unmasked_3193, 0, ret_val_illegal_fp_vd_unmasked_3193); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76536,29 +76140,27 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3179; - x86::Gp ret_val_sew_3179 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3179, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_scalar_to_vector_3178; - auto scalar_to_vector_3178_arg1 = load_reg_from_mem(jh, traits::vtype); - auto scalar_to_vector_3178_arg3 = gen_ext(cc, + InvokeNode* call_sew_3195; + x86::Gp ret_val_sew_3195 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3195, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_scalar_to_vector_3194; + auto scalar_to_vector_3194_arg1 = load_reg_from_mem(jh, traits::vtype); + auto scalar_to_vector_3194_arg3 = gen_ext(cc, gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false), 64, false); - auto scalar_to_vector_3178_arg4 = ret_val_sew_3179; + auto scalar_to_vector_3194_arg4 = ret_val_sew_3195; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_scalar_to_vector_3178, &scalar_to_vector, FuncSignature::build()); - setArg(call_sew_3179, 0, reinterpret_cast(this)); - setRet(call_sew_3179, 0, ret_val_sew_3179); - setArg(call_scalar_to_vector_3178, 0, V); - setArg(call_scalar_to_vector_3178, 1, scalar_to_vector_3178_arg1); - setArg(call_scalar_to_vector_3178, 2, vd); - setArg(call_scalar_to_vector_3178, 3, scalar_to_vector_3178_arg3); - setArg(call_scalar_to_vector_3178, 4, scalar_to_vector_3178_arg4); - auto tmp3180 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3180, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3180, 64, false) - , traits::vstart); + cc.invoke(&call_scalar_to_vector_3194, &scalar_to_vector, FuncSignature::build()); + setArg(call_sew_3195, 0, reinterpret_cast(this)); + setRet(call_sew_3195, 0, ret_val_sew_3195); + setArg(call_scalar_to_vector_3194, 0, V); + setArg(call_scalar_to_vector_3194, 1, scalar_to_vector_3194_arg1); + setArg(call_scalar_to_vector_3194, 2, vd); + setArg(call_scalar_to_vector_3194, 3, scalar_to_vector_3194_arg3); + setArg(call_scalar_to_vector_3194, 4, scalar_to_vector_3194_arg4); + auto tmp3196 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3196, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3196, traits::vstart); } cc.bind(label_merge); } @@ -76603,28 +76205,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3181; - x86::Gp ret_val_get_sew_pow_3181 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3181, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3182 = get_reg(cc, 8, false); - mov(cc, tmp3182, 1); + InvokeNode* call_get_sew_pow_3197; + x86::Gp ret_val_get_sew_pow_3197 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3197, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3198 = get_reg(cc, 8, false); + mov(cc, tmp3198, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3182, (ret_val_get_sew_pow_3181))), 8, false), ~ 1); - setArg(call_get_sew_pow_3181, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3181, 0, ret_val_get_sew_pow_3181); + (gen_operation(cc, shl, tmp3198, (ret_val_get_sew_pow_3197))), 8, false), ~ 1); + setArg(call_get_sew_pow_3197, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3197, 0, ret_val_get_sew_pow_3197); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3183; - auto illegal_fp_vd_unmasked_3183_arg0 = SEW; - auto illegal_fp_vd_unmasked_3183_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3183 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3183, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_vd_unmasked_3183, gen_operation(cc, gtu, SEW, static_cast(traits::FLEN))); - setArg(call_illegal_fp_vd_unmasked_3183, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3183, 1, illegal_fp_vd_unmasked_3183_arg0); - setArg(call_illegal_fp_vd_unmasked_3183, 2, illegal_fp_vd_unmasked_3183_arg1); - setRet(call_illegal_fp_vd_unmasked_3183, 0, ret_val_illegal_fp_vd_unmasked_3183); + InvokeNode* call_illegal_fp_vd_unmasked_3199; + auto illegal_fp_vd_unmasked_3199_arg0 = SEW; + auto illegal_fp_vd_unmasked_3199_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3199 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3199, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_vd_unmasked_3199, gen_operation(cc, gtu, SEW, static_cast(traits::FLEN))); + setArg(call_illegal_fp_vd_unmasked_3199, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3199, 1, illegal_fp_vd_unmasked_3199_arg0); + setArg(call_illegal_fp_vd_unmasked_3199, 2, illegal_fp_vd_unmasked_3199_arg1); + setRet(call_illegal_fp_vd_unmasked_3199, 0, ret_val_illegal_fp_vd_unmasked_3199); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76634,29 +76236,27 @@ template class vm_impl : public iss::asmjit::vm_base { cc.jmp(label_merge); cc.bind(label_else); { - InvokeNode* call_sew_3185; - x86::Gp ret_val_sew_3185 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3185, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_scalar_from_vector_3184; - auto fp_scalar_from_vector_3184_arg1 = load_reg_from_mem(jh, traits::vtype); - auto fp_scalar_from_vector_3184_arg3 = ret_val_sew_3185; + InvokeNode* call_sew_3201; + x86::Gp ret_val_sew_3201 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3201, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_scalar_from_vector_3200; + auto fp_scalar_from_vector_3200_arg1 = load_reg_from_mem(jh, traits::vtype); + auto fp_scalar_from_vector_3200_arg3 = ret_val_sew_3201; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - x86::Gp ret_val_fp_scalar_from_vector_3184 = get_reg_Gp(cc, 64, false); - cc.invoke(&call_fp_scalar_from_vector_3184, &fp_scalar_from_vector, FuncSignature::build()); + x86::Gp ret_val_fp_scalar_from_vector_3200 = get_reg_Gp(cc, 64, false); + cc.invoke(&call_fp_scalar_from_vector_3200, &fp_scalar_from_vector, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::F0+ rd), - ret_val_fp_scalar_from_vector_3184); - setArg(call_sew_3185, 0, reinterpret_cast(this)); - setRet(call_sew_3185, 0, ret_val_sew_3185); - setArg(call_fp_scalar_from_vector_3184, 0, V); - setArg(call_fp_scalar_from_vector_3184, 1, fp_scalar_from_vector_3184_arg1); - setArg(call_fp_scalar_from_vector_3184, 2, vs2); - setArg(call_fp_scalar_from_vector_3184, 3, fp_scalar_from_vector_3184_arg3); - setRet(call_fp_scalar_from_vector_3184, 0, ret_val_fp_scalar_from_vector_3184); - auto tmp3186 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3186, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3186, 64, false) - , traits::vstart); + ret_val_fp_scalar_from_vector_3200); + setArg(call_sew_3201, 0, reinterpret_cast(this)); + setRet(call_sew_3201, 0, ret_val_sew_3201); + setArg(call_fp_scalar_from_vector_3200, 0, V); + setArg(call_fp_scalar_from_vector_3200, 1, fp_scalar_from_vector_3200_arg1); + setArg(call_fp_scalar_from_vector_3200, 2, vs2); + setArg(call_fp_scalar_from_vector_3200, 3, fp_scalar_from_vector_3200_arg3); + setRet(call_fp_scalar_from_vector_3200, 0, ret_val_fp_scalar_from_vector_3200); + auto tmp3202 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3202, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3202, traits::vstart); } cc.bind(label_merge); } @@ -76700,30 +76300,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3187; - x86::Gp ret_val_get_sew_pow_3187 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3187, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3188 = get_reg(cc, 8, false); - mov(cc, tmp3188, 1); + InvokeNode* call_get_sew_pow_3203; + x86::Gp ret_val_get_sew_pow_3203 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3203, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3204 = get_reg(cc, 8, false); + mov(cc, tmp3204, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3188, (ret_val_get_sew_pow_3187))), 8, false), ~ 1); - setArg(call_get_sew_pow_3187, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3187, 0, ret_val_get_sew_pow_3187); + (gen_operation(cc, shl, tmp3204, (ret_val_get_sew_pow_3203))), 8, false), ~ 1); + setArg(call_get_sew_pow_3203, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3203, 0, ret_val_get_sew_pow_3203); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3189; - auto illegal_fp_normal_3189_arg2 = SEW; - auto illegal_fp_normal_3189_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3189 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3189, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3189; - setArg(call_illegal_fp_normal_3189, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3189, 1, vd); - setArg(call_illegal_fp_normal_3189, 2, vm); - setArg(call_illegal_fp_normal_3189, 3, illegal_fp_normal_3189_arg2); - setArg(call_illegal_fp_normal_3189, 4, illegal_fp_normal_3189_arg3); - setRet(call_illegal_fp_normal_3189, 0, ret_val_illegal_fp_normal_3189); + InvokeNode* call_illegal_fp_normal_3205; + auto illegal_fp_normal_3205_arg2 = SEW; + auto illegal_fp_normal_3205_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3205 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3205, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3205; + setArg(call_illegal_fp_normal_3205, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3205, 1, vd); + setArg(call_illegal_fp_normal_3205, 2, vm); + setArg(call_illegal_fp_normal_3205, 3, illegal_fp_normal_3205_arg2); + setArg(call_illegal_fp_normal_3205, 4, illegal_fp_normal_3205_arg3); + setRet(call_illegal_fp_normal_3205, 0, ret_val_illegal_fp_normal_3205); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76739,36 +76339,34 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3191; - x86::Gp ret_val_sew_3191 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3191, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_slide1up_3190; - auto fp_vector_slide1up_3190_arg1 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_slide1up_3190_arg2 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_slide1up_3190_arg3 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_slide1up_3190_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); - auto fp_vector_slide1up_3190_arg8 = ret_val_sew_3191; + InvokeNode* call_sew_3207; + x86::Gp ret_val_sew_3207 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3207, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_slide1up_3206; + auto fp_vector_slide1up_3206_arg1 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_slide1up_3206_arg2 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_slide1up_3206_arg3 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_slide1up_3206_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + auto fp_vector_slide1up_3206_arg8 = ret_val_sew_3207; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_slide1up_3190, &fp_vector_slide1up, FuncSignature::build()); - setArg(call_sew_3191, 0, reinterpret_cast(this)); - setRet(call_sew_3191, 0, ret_val_sew_3191); - setArg(call_fp_vector_slide1up_3190, 0, V); - setArg(call_fp_vector_slide1up_3190, 1, fp_vector_slide1up_3190_arg1); - setArg(call_fp_vector_slide1up_3190, 2, fp_vector_slide1up_3190_arg2); - setArg(call_fp_vector_slide1up_3190, 3, fp_vector_slide1up_3190_arg3); - setArg(call_fp_vector_slide1up_3190, 4, vm); - setArg(call_fp_vector_slide1up_3190, 5, vd); - setArg(call_fp_vector_slide1up_3190, 6, vs2); - setArg(call_fp_vector_slide1up_3190, 7, fp_vector_slide1up_3190_arg7); - setArg(call_fp_vector_slide1up_3190, 8, fp_vector_slide1up_3190_arg8); + cc.invoke(&call_fp_vector_slide1up_3206, &fp_vector_slide1up, FuncSignature::build()); + setArg(call_sew_3207, 0, reinterpret_cast(this)); + setRet(call_sew_3207, 0, ret_val_sew_3207); + setArg(call_fp_vector_slide1up_3206, 0, V); + setArg(call_fp_vector_slide1up_3206, 1, fp_vector_slide1up_3206_arg1); + setArg(call_fp_vector_slide1up_3206, 2, fp_vector_slide1up_3206_arg2); + setArg(call_fp_vector_slide1up_3206, 3, fp_vector_slide1up_3206_arg3); + setArg(call_fp_vector_slide1up_3206, 4, vm); + setArg(call_fp_vector_slide1up_3206, 5, vd); + setArg(call_fp_vector_slide1up_3206, 6, vs2); + setArg(call_fp_vector_slide1up_3206, 7, fp_vector_slide1up_3206_arg7); + setArg(call_fp_vector_slide1up_3206, 8, fp_vector_slide1up_3206_arg8); } cc.bind(label_merge); } - auto tmp3192 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3192, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3192, 64, false) - , traits::vstart); + auto tmp3208 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3208, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3208, traits::vstart); } cc.bind(label_merge); } @@ -76812,30 +76410,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3193; - x86::Gp ret_val_get_sew_pow_3193 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3193, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3194 = get_reg(cc, 8, false); - mov(cc, tmp3194, 1); + InvokeNode* call_get_sew_pow_3209; + x86::Gp ret_val_get_sew_pow_3209 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3209, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3210 = get_reg(cc, 8, false); + mov(cc, tmp3210, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3194, (ret_val_get_sew_pow_3193))), 8, false), ~ 1); - setArg(call_get_sew_pow_3193, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3193, 0, ret_val_get_sew_pow_3193); + (gen_operation(cc, shl, tmp3210, (ret_val_get_sew_pow_3209))), 8, false), ~ 1); + setArg(call_get_sew_pow_3209, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3209, 0, ret_val_get_sew_pow_3209); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3195; - auto illegal_fp_normal_3195_arg2 = SEW; - auto illegal_fp_normal_3195_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3195 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3195, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3195; - setArg(call_illegal_fp_normal_3195, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3195, 1, vd); - setArg(call_illegal_fp_normal_3195, 2, vm); - setArg(call_illegal_fp_normal_3195, 3, illegal_fp_normal_3195_arg2); - setArg(call_illegal_fp_normal_3195, 4, illegal_fp_normal_3195_arg3); - setRet(call_illegal_fp_normal_3195, 0, ret_val_illegal_fp_normal_3195); + InvokeNode* call_illegal_fp_normal_3211; + auto illegal_fp_normal_3211_arg2 = SEW; + auto illegal_fp_normal_3211_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3211 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3211, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3211; + setArg(call_illegal_fp_normal_3211, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3211, 1, vd); + setArg(call_illegal_fp_normal_3211, 2, vm); + setArg(call_illegal_fp_normal_3211, 3, illegal_fp_normal_3211_arg2); + setArg(call_illegal_fp_normal_3211, 4, illegal_fp_normal_3211_arg3); + setRet(call_illegal_fp_normal_3211, 0, ret_val_illegal_fp_normal_3211); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76851,36 +76449,34 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3197; - x86::Gp ret_val_sew_3197 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3197, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_slide1down_3196; - auto fp_vector_slide1down_3196_arg1 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_slide1down_3196_arg2 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_slide1down_3196_arg3 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_slide1down_3196_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); - auto fp_vector_slide1down_3196_arg8 = ret_val_sew_3197; + InvokeNode* call_sew_3213; + x86::Gp ret_val_sew_3213 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3213, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_slide1down_3212; + auto fp_vector_slide1down_3212_arg1 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_slide1down_3212_arg2 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_slide1down_3212_arg3 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_slide1down_3212_arg7 = load_reg_from_mem_Gp(jh, traits::F0 + rs1); + auto fp_vector_slide1down_3212_arg8 = ret_val_sew_3213; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_slide1down_3196, &fp_vector_slide1down, FuncSignature::build()); - setArg(call_sew_3197, 0, reinterpret_cast(this)); - setRet(call_sew_3197, 0, ret_val_sew_3197); - setArg(call_fp_vector_slide1down_3196, 0, V); - setArg(call_fp_vector_slide1down_3196, 1, fp_vector_slide1down_3196_arg1); - setArg(call_fp_vector_slide1down_3196, 2, fp_vector_slide1down_3196_arg2); - setArg(call_fp_vector_slide1down_3196, 3, fp_vector_slide1down_3196_arg3); - setArg(call_fp_vector_slide1down_3196, 4, vm); - setArg(call_fp_vector_slide1down_3196, 5, vd); - setArg(call_fp_vector_slide1down_3196, 6, vs2); - setArg(call_fp_vector_slide1down_3196, 7, fp_vector_slide1down_3196_arg7); - setArg(call_fp_vector_slide1down_3196, 8, fp_vector_slide1down_3196_arg8); + cc.invoke(&call_fp_vector_slide1down_3212, &fp_vector_slide1down, FuncSignature::build()); + setArg(call_sew_3213, 0, reinterpret_cast(this)); + setRet(call_sew_3213, 0, ret_val_sew_3213); + setArg(call_fp_vector_slide1down_3212, 0, V); + setArg(call_fp_vector_slide1down_3212, 1, fp_vector_slide1down_3212_arg1); + setArg(call_fp_vector_slide1down_3212, 2, fp_vector_slide1down_3212_arg2); + setArg(call_fp_vector_slide1down_3212, 3, fp_vector_slide1down_3212_arg3); + setArg(call_fp_vector_slide1down_3212, 4, vm); + setArg(call_fp_vector_slide1down_3212, 5, vd); + setArg(call_fp_vector_slide1down_3212, 6, vs2); + setArg(call_fp_vector_slide1down_3212, 7, fp_vector_slide1down_3212_arg7); + setArg(call_fp_vector_slide1down_3212, 8, fp_vector_slide1down_3212_arg8); } cc.bind(label_merge); } - auto tmp3198 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3198, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3198, 64, false) - , traits::vstart); + auto tmp3214 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3214, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3214, traits::vstart); } cc.bind(label_merge); } @@ -76924,30 +76520,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3199; - x86::Gp ret_val_get_sew_pow_3199 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3199, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3200 = get_reg(cc, 8, false); - mov(cc, tmp3200, 1); + InvokeNode* call_get_sew_pow_3215; + x86::Gp ret_val_get_sew_pow_3215 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3215, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3216 = get_reg(cc, 8, false); + mov(cc, tmp3216, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3200, (ret_val_get_sew_pow_3199))), 8, false), ~ 1); - setArg(call_get_sew_pow_3199, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3199, 0, ret_val_get_sew_pow_3199); + (gen_operation(cc, shl, tmp3216, (ret_val_get_sew_pow_3215))), 8, false), ~ 1); + setArg(call_get_sew_pow_3215, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3215, 0, ret_val_get_sew_pow_3215); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3201; - auto illegal_fp_normal_3201_arg2 = SEW; - auto illegal_fp_normal_3201_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3201 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3201, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3201; - setArg(call_illegal_fp_normal_3201, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3201, 1, vd); - setArg(call_illegal_fp_normal_3201, 2, vm); - setArg(call_illegal_fp_normal_3201, 3, illegal_fp_normal_3201_arg2); - setArg(call_illegal_fp_normal_3201, 4, illegal_fp_normal_3201_arg3); - setRet(call_illegal_fp_normal_3201, 0, ret_val_illegal_fp_normal_3201); + InvokeNode* call_illegal_fp_normal_3217; + auto illegal_fp_normal_3217_arg2 = SEW; + auto illegal_fp_normal_3217_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3217 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3217, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3217; + setArg(call_illegal_fp_normal_3217, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3217, 1, vd); + setArg(call_illegal_fp_normal_3217, 2, vm); + setArg(call_illegal_fp_normal_3217, 3, illegal_fp_normal_3217_arg2); + setArg(call_illegal_fp_normal_3217, 4, illegal_fp_normal_3217_arg3); + setRet(call_illegal_fp_normal_3217, 0, ret_val_illegal_fp_normal_3217); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -76963,47 +76559,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3203; - x86::Gp ret_val_sew_3203 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3203, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3202; - auto fp_vector_imm_op_3202_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3202_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3202_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3202_arg9 = gen_ext(cc, + InvokeNode* call_sew_3219; + x86::Gp ret_val_sew_3219 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3219, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3218; + auto fp_vector_imm_op_3218_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3218_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3218_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3218_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3202_arg10 = rm; - auto fp_vector_imm_op_3202_arg11 = ret_val_sew_3203; + auto fp_vector_imm_op_3218_arg10 = rm; + auto fp_vector_imm_op_3218_arg11 = ret_val_sew_3219; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3202, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3203, 0, reinterpret_cast(this)); - setRet(call_sew_3203, 0, ret_val_sew_3203); - setArg(call_fp_vector_imm_op_3202, 0, V); - setArg(call_fp_vector_imm_op_3202, 1, 0); - setArg(call_fp_vector_imm_op_3202, 2, 5); - setArg(call_fp_vector_imm_op_3202, 3, fp_vector_imm_op_3202_arg3); - setArg(call_fp_vector_imm_op_3202, 4, fp_vector_imm_op_3202_arg4); - setArg(call_fp_vector_imm_op_3202, 5, fp_vector_imm_op_3202_arg5); - setArg(call_fp_vector_imm_op_3202, 6, vm); - setArg(call_fp_vector_imm_op_3202, 7, vd); - setArg(call_fp_vector_imm_op_3202, 8, vs2); - setArg(call_fp_vector_imm_op_3202, 9, fp_vector_imm_op_3202_arg9); - setArg(call_fp_vector_imm_op_3202, 10, fp_vector_imm_op_3202_arg10); - setArg(call_fp_vector_imm_op_3202, 11, fp_vector_imm_op_3202_arg11); - InvokeNode* call_fget_flags_3204; - x86::Gp ret_val_fget_flags_3204 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3204, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3204; - setRet(call_fget_flags_3204, 0, ret_val_fget_flags_3204); + cc.invoke(&call_fp_vector_imm_op_3218, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3219, 0, reinterpret_cast(this)); + setRet(call_sew_3219, 0, ret_val_sew_3219); + setArg(call_fp_vector_imm_op_3218, 0, V); + setArg(call_fp_vector_imm_op_3218, 1, 0); + setArg(call_fp_vector_imm_op_3218, 2, 5); + setArg(call_fp_vector_imm_op_3218, 3, fp_vector_imm_op_3218_arg3); + setArg(call_fp_vector_imm_op_3218, 4, fp_vector_imm_op_3218_arg4); + setArg(call_fp_vector_imm_op_3218, 5, fp_vector_imm_op_3218_arg5); + setArg(call_fp_vector_imm_op_3218, 6, vm); + setArg(call_fp_vector_imm_op_3218, 7, vd); + setArg(call_fp_vector_imm_op_3218, 8, vs2); + setArg(call_fp_vector_imm_op_3218, 9, fp_vector_imm_op_3218_arg9); + setArg(call_fp_vector_imm_op_3218, 10, fp_vector_imm_op_3218_arg10); + setArg(call_fp_vector_imm_op_3218, 11, fp_vector_imm_op_3218_arg11); + InvokeNode* call_fget_flags_3220; + x86::Gp ret_val_fget_flags_3220 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3220, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3220; + setRet(call_fget_flags_3220, 0, ret_val_fget_flags_3220); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3205 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3205, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3205, 64, false) - , traits::vstart); + auto tmp3221 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3221, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3221, traits::vstart); } cc.bind(label_merge); } @@ -77047,30 +76641,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3206; - x86::Gp ret_val_get_sew_pow_3206 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3206, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3207 = get_reg(cc, 8, false); - mov(cc, tmp3207, 1); + InvokeNode* call_get_sew_pow_3222; + x86::Gp ret_val_get_sew_pow_3222 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3222, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3223 = get_reg(cc, 8, false); + mov(cc, tmp3223, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3207, (ret_val_get_sew_pow_3206))), 8, false), ~ 1); - setArg(call_get_sew_pow_3206, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3206, 0, ret_val_get_sew_pow_3206); + (gen_operation(cc, shl, tmp3223, (ret_val_get_sew_pow_3222))), 8, false), ~ 1); + setArg(call_get_sew_pow_3222, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3222, 0, ret_val_get_sew_pow_3222); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3208; - auto illegal_fp_normal_3208_arg2 = SEW; - auto illegal_fp_normal_3208_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3208 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3208, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3208; - setArg(call_illegal_fp_normal_3208, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3208, 1, vd); - setArg(call_illegal_fp_normal_3208, 2, vm); - setArg(call_illegal_fp_normal_3208, 3, illegal_fp_normal_3208_arg2); - setArg(call_illegal_fp_normal_3208, 4, illegal_fp_normal_3208_arg3); - setRet(call_illegal_fp_normal_3208, 0, ret_val_illegal_fp_normal_3208); + InvokeNode* call_illegal_fp_normal_3224; + auto illegal_fp_normal_3224_arg2 = SEW; + auto illegal_fp_normal_3224_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3224 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3224, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3224; + setArg(call_illegal_fp_normal_3224, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3224, 1, vd); + setArg(call_illegal_fp_normal_3224, 2, vm); + setArg(call_illegal_fp_normal_3224, 3, illegal_fp_normal_3224_arg2); + setArg(call_illegal_fp_normal_3224, 4, illegal_fp_normal_3224_arg3); + setRet(call_illegal_fp_normal_3224, 0, ret_val_illegal_fp_normal_3224); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77086,45 +76680,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3210; - x86::Gp ret_val_sew_3210 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3210, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3209; - auto fp_vector_vector_op_3209_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3209_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3209_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3209_arg10 = rm; - auto fp_vector_vector_op_3209_arg11 = ret_val_sew_3210; + InvokeNode* call_sew_3226; + x86::Gp ret_val_sew_3226 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3226, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3225; + auto fp_vector_vector_op_3225_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3225_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3225_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3225_arg10 = rm; + auto fp_vector_vector_op_3225_arg11 = ret_val_sew_3226; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3209, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3210, 0, reinterpret_cast(this)); - setRet(call_sew_3210, 0, ret_val_sew_3210); - setArg(call_fp_vector_vector_op_3209, 0, V); - setArg(call_fp_vector_vector_op_3209, 1, 0); - setArg(call_fp_vector_vector_op_3209, 2, 1); - setArg(call_fp_vector_vector_op_3209, 3, fp_vector_vector_op_3209_arg3); - setArg(call_fp_vector_vector_op_3209, 4, fp_vector_vector_op_3209_arg4); - setArg(call_fp_vector_vector_op_3209, 5, fp_vector_vector_op_3209_arg5); - setArg(call_fp_vector_vector_op_3209, 6, vm); - setArg(call_fp_vector_vector_op_3209, 7, vd); - setArg(call_fp_vector_vector_op_3209, 8, vs2); - setArg(call_fp_vector_vector_op_3209, 9, vs1); - setArg(call_fp_vector_vector_op_3209, 10, fp_vector_vector_op_3209_arg10); - setArg(call_fp_vector_vector_op_3209, 11, fp_vector_vector_op_3209_arg11); - InvokeNode* call_fget_flags_3211; - x86::Gp ret_val_fget_flags_3211 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3211, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3211; - setRet(call_fget_flags_3211, 0, ret_val_fget_flags_3211); + cc.invoke(&call_fp_vector_vector_op_3225, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3226, 0, reinterpret_cast(this)); + setRet(call_sew_3226, 0, ret_val_sew_3226); + setArg(call_fp_vector_vector_op_3225, 0, V); + setArg(call_fp_vector_vector_op_3225, 1, 0); + setArg(call_fp_vector_vector_op_3225, 2, 1); + setArg(call_fp_vector_vector_op_3225, 3, fp_vector_vector_op_3225_arg3); + setArg(call_fp_vector_vector_op_3225, 4, fp_vector_vector_op_3225_arg4); + setArg(call_fp_vector_vector_op_3225, 5, fp_vector_vector_op_3225_arg5); + setArg(call_fp_vector_vector_op_3225, 6, vm); + setArg(call_fp_vector_vector_op_3225, 7, vd); + setArg(call_fp_vector_vector_op_3225, 8, vs2); + setArg(call_fp_vector_vector_op_3225, 9, vs1); + setArg(call_fp_vector_vector_op_3225, 10, fp_vector_vector_op_3225_arg10); + setArg(call_fp_vector_vector_op_3225, 11, fp_vector_vector_op_3225_arg11); + InvokeNode* call_fget_flags_3227; + x86::Gp ret_val_fget_flags_3227 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3227, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3227; + setRet(call_fget_flags_3227, 0, ret_val_fget_flags_3227); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3212 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3212, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3212, 64, false) - , traits::vstart); + auto tmp3228 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3228, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3228, traits::vstart); } cc.bind(label_merge); } @@ -77168,30 +76760,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3213; - x86::Gp ret_val_get_sew_pow_3213 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3213, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3214 = get_reg(cc, 8, false); - mov(cc, tmp3214, 1); + InvokeNode* call_get_sew_pow_3229; + x86::Gp ret_val_get_sew_pow_3229 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3229, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3230 = get_reg(cc, 8, false); + mov(cc, tmp3230, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3214, (ret_val_get_sew_pow_3213))), 8, false), ~ 1); - setArg(call_get_sew_pow_3213, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3213, 0, ret_val_get_sew_pow_3213); + (gen_operation(cc, shl, tmp3230, (ret_val_get_sew_pow_3229))), 8, false), ~ 1); + setArg(call_get_sew_pow_3229, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3229, 0, ret_val_get_sew_pow_3229); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3215; - auto illegal_fp_normal_3215_arg2 = SEW; - auto illegal_fp_normal_3215_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3215 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3215, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3215; - setArg(call_illegal_fp_normal_3215, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3215, 1, vd); - setArg(call_illegal_fp_normal_3215, 2, vm); - setArg(call_illegal_fp_normal_3215, 3, illegal_fp_normal_3215_arg2); - setArg(call_illegal_fp_normal_3215, 4, illegal_fp_normal_3215_arg3); - setRet(call_illegal_fp_normal_3215, 0, ret_val_illegal_fp_normal_3215); + InvokeNode* call_illegal_fp_normal_3231; + auto illegal_fp_normal_3231_arg2 = SEW; + auto illegal_fp_normal_3231_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3231 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3231, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3231; + setArg(call_illegal_fp_normal_3231, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3231, 1, vd); + setArg(call_illegal_fp_normal_3231, 2, vm); + setArg(call_illegal_fp_normal_3231, 3, illegal_fp_normal_3231_arg2); + setArg(call_illegal_fp_normal_3231, 4, illegal_fp_normal_3231_arg3); + setRet(call_illegal_fp_normal_3231, 0, ret_val_illegal_fp_normal_3231); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77207,47 +76799,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3217; - x86::Gp ret_val_sew_3217 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3217, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3216; - auto fp_vector_imm_op_3216_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3216_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3216_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3216_arg9 = gen_ext(cc, + InvokeNode* call_sew_3233; + x86::Gp ret_val_sew_3233 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3233, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3232; + auto fp_vector_imm_op_3232_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3232_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3232_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3232_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3216_arg10 = rm; - auto fp_vector_imm_op_3216_arg11 = ret_val_sew_3217; + auto fp_vector_imm_op_3232_arg10 = rm; + auto fp_vector_imm_op_3232_arg11 = ret_val_sew_3233; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3216, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3217, 0, reinterpret_cast(this)); - setRet(call_sew_3217, 0, ret_val_sew_3217); - setArg(call_fp_vector_imm_op_3216, 0, V); - setArg(call_fp_vector_imm_op_3216, 1, 2); - setArg(call_fp_vector_imm_op_3216, 2, 5); - setArg(call_fp_vector_imm_op_3216, 3, fp_vector_imm_op_3216_arg3); - setArg(call_fp_vector_imm_op_3216, 4, fp_vector_imm_op_3216_arg4); - setArg(call_fp_vector_imm_op_3216, 5, fp_vector_imm_op_3216_arg5); - setArg(call_fp_vector_imm_op_3216, 6, vm); - setArg(call_fp_vector_imm_op_3216, 7, vd); - setArg(call_fp_vector_imm_op_3216, 8, vs2); - setArg(call_fp_vector_imm_op_3216, 9, fp_vector_imm_op_3216_arg9); - setArg(call_fp_vector_imm_op_3216, 10, fp_vector_imm_op_3216_arg10); - setArg(call_fp_vector_imm_op_3216, 11, fp_vector_imm_op_3216_arg11); - InvokeNode* call_fget_flags_3218; - x86::Gp ret_val_fget_flags_3218 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3218, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3218; - setRet(call_fget_flags_3218, 0, ret_val_fget_flags_3218); + cc.invoke(&call_fp_vector_imm_op_3232, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3233, 0, reinterpret_cast(this)); + setRet(call_sew_3233, 0, ret_val_sew_3233); + setArg(call_fp_vector_imm_op_3232, 0, V); + setArg(call_fp_vector_imm_op_3232, 1, 2); + setArg(call_fp_vector_imm_op_3232, 2, 5); + setArg(call_fp_vector_imm_op_3232, 3, fp_vector_imm_op_3232_arg3); + setArg(call_fp_vector_imm_op_3232, 4, fp_vector_imm_op_3232_arg4); + setArg(call_fp_vector_imm_op_3232, 5, fp_vector_imm_op_3232_arg5); + setArg(call_fp_vector_imm_op_3232, 6, vm); + setArg(call_fp_vector_imm_op_3232, 7, vd); + setArg(call_fp_vector_imm_op_3232, 8, vs2); + setArg(call_fp_vector_imm_op_3232, 9, fp_vector_imm_op_3232_arg9); + setArg(call_fp_vector_imm_op_3232, 10, fp_vector_imm_op_3232_arg10); + setArg(call_fp_vector_imm_op_3232, 11, fp_vector_imm_op_3232_arg11); + InvokeNode* call_fget_flags_3234; + x86::Gp ret_val_fget_flags_3234 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3234, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3234; + setRet(call_fget_flags_3234, 0, ret_val_fget_flags_3234); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3219 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3219, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3219, 64, false) - , traits::vstart); + auto tmp3235 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3235, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3235, traits::vstart); } cc.bind(label_merge); } @@ -77291,30 +76881,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3220; - x86::Gp ret_val_get_sew_pow_3220 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3220, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3221 = get_reg(cc, 8, false); - mov(cc, tmp3221, 1); + InvokeNode* call_get_sew_pow_3236; + x86::Gp ret_val_get_sew_pow_3236 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3236, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3237 = get_reg(cc, 8, false); + mov(cc, tmp3237, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3221, (ret_val_get_sew_pow_3220))), 8, false), ~ 1); - setArg(call_get_sew_pow_3220, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3220, 0, ret_val_get_sew_pow_3220); + (gen_operation(cc, shl, tmp3237, (ret_val_get_sew_pow_3236))), 8, false), ~ 1); + setArg(call_get_sew_pow_3236, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3236, 0, ret_val_get_sew_pow_3236); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3222; - auto illegal_fp_normal_3222_arg2 = SEW; - auto illegal_fp_normal_3222_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3222 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3222, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3222; - setArg(call_illegal_fp_normal_3222, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3222, 1, vd); - setArg(call_illegal_fp_normal_3222, 2, vm); - setArg(call_illegal_fp_normal_3222, 3, illegal_fp_normal_3222_arg2); - setArg(call_illegal_fp_normal_3222, 4, illegal_fp_normal_3222_arg3); - setRet(call_illegal_fp_normal_3222, 0, ret_val_illegal_fp_normal_3222); + InvokeNode* call_illegal_fp_normal_3238; + auto illegal_fp_normal_3238_arg2 = SEW; + auto illegal_fp_normal_3238_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3238 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3238, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3238; + setArg(call_illegal_fp_normal_3238, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3238, 1, vd); + setArg(call_illegal_fp_normal_3238, 2, vm); + setArg(call_illegal_fp_normal_3238, 3, illegal_fp_normal_3238_arg2); + setArg(call_illegal_fp_normal_3238, 4, illegal_fp_normal_3238_arg3); + setRet(call_illegal_fp_normal_3238, 0, ret_val_illegal_fp_normal_3238); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77330,45 +76920,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3224; - x86::Gp ret_val_sew_3224 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3224, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3223; - auto fp_vector_vector_op_3223_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3223_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3223_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3223_arg10 = rm; - auto fp_vector_vector_op_3223_arg11 = ret_val_sew_3224; + InvokeNode* call_sew_3240; + x86::Gp ret_val_sew_3240 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3240, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3239; + auto fp_vector_vector_op_3239_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3239_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3239_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3239_arg10 = rm; + auto fp_vector_vector_op_3239_arg11 = ret_val_sew_3240; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3223, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3224, 0, reinterpret_cast(this)); - setRet(call_sew_3224, 0, ret_val_sew_3224); - setArg(call_fp_vector_vector_op_3223, 0, V); - setArg(call_fp_vector_vector_op_3223, 1, 2); - setArg(call_fp_vector_vector_op_3223, 2, 1); - setArg(call_fp_vector_vector_op_3223, 3, fp_vector_vector_op_3223_arg3); - setArg(call_fp_vector_vector_op_3223, 4, fp_vector_vector_op_3223_arg4); - setArg(call_fp_vector_vector_op_3223, 5, fp_vector_vector_op_3223_arg5); - setArg(call_fp_vector_vector_op_3223, 6, vm); - setArg(call_fp_vector_vector_op_3223, 7, vd); - setArg(call_fp_vector_vector_op_3223, 8, vs2); - setArg(call_fp_vector_vector_op_3223, 9, vs1); - setArg(call_fp_vector_vector_op_3223, 10, fp_vector_vector_op_3223_arg10); - setArg(call_fp_vector_vector_op_3223, 11, fp_vector_vector_op_3223_arg11); - InvokeNode* call_fget_flags_3225; - x86::Gp ret_val_fget_flags_3225 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3225, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3225; - setRet(call_fget_flags_3225, 0, ret_val_fget_flags_3225); + cc.invoke(&call_fp_vector_vector_op_3239, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3240, 0, reinterpret_cast(this)); + setRet(call_sew_3240, 0, ret_val_sew_3240); + setArg(call_fp_vector_vector_op_3239, 0, V); + setArg(call_fp_vector_vector_op_3239, 1, 2); + setArg(call_fp_vector_vector_op_3239, 2, 1); + setArg(call_fp_vector_vector_op_3239, 3, fp_vector_vector_op_3239_arg3); + setArg(call_fp_vector_vector_op_3239, 4, fp_vector_vector_op_3239_arg4); + setArg(call_fp_vector_vector_op_3239, 5, fp_vector_vector_op_3239_arg5); + setArg(call_fp_vector_vector_op_3239, 6, vm); + setArg(call_fp_vector_vector_op_3239, 7, vd); + setArg(call_fp_vector_vector_op_3239, 8, vs2); + setArg(call_fp_vector_vector_op_3239, 9, vs1); + setArg(call_fp_vector_vector_op_3239, 10, fp_vector_vector_op_3239_arg10); + setArg(call_fp_vector_vector_op_3239, 11, fp_vector_vector_op_3239_arg11); + InvokeNode* call_fget_flags_3241; + x86::Gp ret_val_fget_flags_3241 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3241, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3241; + setRet(call_fget_flags_3241, 0, ret_val_fget_flags_3241); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3226 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3226, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3226, 64, false) - , traits::vstart); + auto tmp3242 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3242, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3242, traits::vstart); } cc.bind(label_merge); } @@ -77412,30 +77000,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3227; - x86::Gp ret_val_get_sew_pow_3227 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3227, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3228 = get_reg(cc, 8, false); - mov(cc, tmp3228, 1); + InvokeNode* call_get_sew_pow_3243; + x86::Gp ret_val_get_sew_pow_3243 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3243, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3244 = get_reg(cc, 8, false); + mov(cc, tmp3244, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3228, (ret_val_get_sew_pow_3227))), 8, false), ~ 1); - setArg(call_get_sew_pow_3227, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3227, 0, ret_val_get_sew_pow_3227); + (gen_operation(cc, shl, tmp3244, (ret_val_get_sew_pow_3243))), 8, false), ~ 1); + setArg(call_get_sew_pow_3243, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3243, 0, ret_val_get_sew_pow_3243); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3229; - auto illegal_fp_normal_3229_arg2 = SEW; - auto illegal_fp_normal_3229_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3229 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3229, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3229; - setArg(call_illegal_fp_normal_3229, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3229, 1, vd); - setArg(call_illegal_fp_normal_3229, 2, vm); - setArg(call_illegal_fp_normal_3229, 3, illegal_fp_normal_3229_arg2); - setArg(call_illegal_fp_normal_3229, 4, illegal_fp_normal_3229_arg3); - setRet(call_illegal_fp_normal_3229, 0, ret_val_illegal_fp_normal_3229); + InvokeNode* call_illegal_fp_normal_3245; + auto illegal_fp_normal_3245_arg2 = SEW; + auto illegal_fp_normal_3245_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3245 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3245, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3245; + setArg(call_illegal_fp_normal_3245, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3245, 1, vd); + setArg(call_illegal_fp_normal_3245, 2, vm); + setArg(call_illegal_fp_normal_3245, 3, illegal_fp_normal_3245_arg2); + setArg(call_illegal_fp_normal_3245, 4, illegal_fp_normal_3245_arg3); + setRet(call_illegal_fp_normal_3245, 0, ret_val_illegal_fp_normal_3245); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77451,47 +77039,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3231; - x86::Gp ret_val_sew_3231 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3231, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3230; - auto fp_vector_imm_op_3230_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3230_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3230_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3230_arg9 = gen_ext(cc, + InvokeNode* call_sew_3247; + x86::Gp ret_val_sew_3247 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3247, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3246; + auto fp_vector_imm_op_3246_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3246_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3246_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3246_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3230_arg10 = rm; - auto fp_vector_imm_op_3230_arg11 = ret_val_sew_3231; + auto fp_vector_imm_op_3246_arg10 = rm; + auto fp_vector_imm_op_3246_arg11 = ret_val_sew_3247; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3230, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3231, 0, reinterpret_cast(this)); - setRet(call_sew_3231, 0, ret_val_sew_3231); - setArg(call_fp_vector_imm_op_3230, 0, V); - setArg(call_fp_vector_imm_op_3230, 1, 39); - setArg(call_fp_vector_imm_op_3230, 2, 5); - setArg(call_fp_vector_imm_op_3230, 3, fp_vector_imm_op_3230_arg3); - setArg(call_fp_vector_imm_op_3230, 4, fp_vector_imm_op_3230_arg4); - setArg(call_fp_vector_imm_op_3230, 5, fp_vector_imm_op_3230_arg5); - setArg(call_fp_vector_imm_op_3230, 6, vm); - setArg(call_fp_vector_imm_op_3230, 7, vd); - setArg(call_fp_vector_imm_op_3230, 8, vs2); - setArg(call_fp_vector_imm_op_3230, 9, fp_vector_imm_op_3230_arg9); - setArg(call_fp_vector_imm_op_3230, 10, fp_vector_imm_op_3230_arg10); - setArg(call_fp_vector_imm_op_3230, 11, fp_vector_imm_op_3230_arg11); - InvokeNode* call_fget_flags_3232; - x86::Gp ret_val_fget_flags_3232 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3232, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3232; - setRet(call_fget_flags_3232, 0, ret_val_fget_flags_3232); + cc.invoke(&call_fp_vector_imm_op_3246, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3247, 0, reinterpret_cast(this)); + setRet(call_sew_3247, 0, ret_val_sew_3247); + setArg(call_fp_vector_imm_op_3246, 0, V); + setArg(call_fp_vector_imm_op_3246, 1, 39); + setArg(call_fp_vector_imm_op_3246, 2, 5); + setArg(call_fp_vector_imm_op_3246, 3, fp_vector_imm_op_3246_arg3); + setArg(call_fp_vector_imm_op_3246, 4, fp_vector_imm_op_3246_arg4); + setArg(call_fp_vector_imm_op_3246, 5, fp_vector_imm_op_3246_arg5); + setArg(call_fp_vector_imm_op_3246, 6, vm); + setArg(call_fp_vector_imm_op_3246, 7, vd); + setArg(call_fp_vector_imm_op_3246, 8, vs2); + setArg(call_fp_vector_imm_op_3246, 9, fp_vector_imm_op_3246_arg9); + setArg(call_fp_vector_imm_op_3246, 10, fp_vector_imm_op_3246_arg10); + setArg(call_fp_vector_imm_op_3246, 11, fp_vector_imm_op_3246_arg11); + InvokeNode* call_fget_flags_3248; + x86::Gp ret_val_fget_flags_3248 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3248, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3248; + setRet(call_fget_flags_3248, 0, ret_val_fget_flags_3248); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3233 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3233, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3233, 64, false) - , traits::vstart); + auto tmp3249 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3249, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3249, traits::vstart); } cc.bind(label_merge); } @@ -77535,54 +77121,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3234; - x86::Gp ret_val_get_sew_pow_3234 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3234, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3235 = get_reg(cc, 8, false); - mov(cc, tmp3235, 1); + InvokeNode* call_get_sew_pow_3250; + x86::Gp ret_val_get_sew_pow_3250 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3250, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3251 = get_reg(cc, 8, false); + mov(cc, tmp3251, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3235, (ret_val_get_sew_pow_3234))), 8, false), ~ 1); - setArg(call_get_sew_pow_3234, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3234, 0, ret_val_get_sew_pow_3234); - InvokeNode* call_get_lmul_pow_3236; - x86::Gp ret_val_get_lmul_pow_3236 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3236, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3236; - setArg(call_get_lmul_pow_3236, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3236, 0, ret_val_get_lmul_pow_3236); + (gen_operation(cc, shl, tmp3251, (ret_val_get_sew_pow_3250))), 8, false), ~ 1); + setArg(call_get_sew_pow_3250, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3250, 0, ret_val_get_sew_pow_3250); + InvokeNode* call_get_lmul_pow_3252; + x86::Gp ret_val_get_lmul_pow_3252 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3252, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3252; + setArg(call_get_lmul_pow_3252, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3252, 0, ret_val_get_lmul_pow_3252); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3237; - auto illegal_fp_variable_width_3237_arg2 = SEW; - auto illegal_fp_variable_width_3237_arg3 = rm; - auto illegal_fp_variable_width_3237_arg4 = SEW_widen; - auto illegal_fp_variable_width_3237_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3237 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3237, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3238; - auto valid_reg_overlap_3238_arg2 = LMUL_pow; - auto valid_reg_overlap_3238_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3238 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3238, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3237, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3238)); - setArg(call_illegal_fp_variable_width_3237, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3237, 1, vd); - setArg(call_illegal_fp_variable_width_3237, 2, vm); - setArg(call_illegal_fp_variable_width_3237, 3, illegal_fp_variable_width_3237_arg2); - setArg(call_illegal_fp_variable_width_3237, 4, illegal_fp_variable_width_3237_arg3); - setArg(call_illegal_fp_variable_width_3237, 5, illegal_fp_variable_width_3237_arg4); - setArg(call_illegal_fp_variable_width_3237, 6, illegal_fp_variable_width_3237_arg5); - setRet(call_illegal_fp_variable_width_3237, 0, ret_val_illegal_fp_variable_width_3237); - setArg(call_valid_reg_overlap_3238, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3238, 1, vs2); - setArg(call_valid_reg_overlap_3238, 2, vd); - setArg(call_valid_reg_overlap_3238, 3, valid_reg_overlap_3238_arg2); - setArg(call_valid_reg_overlap_3238, 4, valid_reg_overlap_3238_arg3); - setRet(call_valid_reg_overlap_3238, 0, ret_val_valid_reg_overlap_3238); + InvokeNode* call_illegal_fp_variable_width_3253; + auto illegal_fp_variable_width_3253_arg2 = SEW; + auto illegal_fp_variable_width_3253_arg3 = rm; + auto illegal_fp_variable_width_3253_arg4 = SEW_widen; + auto illegal_fp_variable_width_3253_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3253 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3253, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3254; + auto valid_reg_overlap_3254_arg2 = LMUL_pow; + auto valid_reg_overlap_3254_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3254 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3254, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3253, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3254)); + setArg(call_illegal_fp_variable_width_3253, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3253, 1, vd); + setArg(call_illegal_fp_variable_width_3253, 2, vm); + setArg(call_illegal_fp_variable_width_3253, 3, illegal_fp_variable_width_3253_arg2); + setArg(call_illegal_fp_variable_width_3253, 4, illegal_fp_variable_width_3253_arg3); + setArg(call_illegal_fp_variable_width_3253, 5, illegal_fp_variable_width_3253_arg4); + setArg(call_illegal_fp_variable_width_3253, 6, illegal_fp_variable_width_3253_arg5); + setRet(call_illegal_fp_variable_width_3253, 0, ret_val_illegal_fp_variable_width_3253); + setArg(call_valid_reg_overlap_3254, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3254, 1, vs2); + setArg(call_valid_reg_overlap_3254, 2, vd); + setArg(call_valid_reg_overlap_3254, 3, valid_reg_overlap_3254_arg2); + setArg(call_valid_reg_overlap_3254, 4, valid_reg_overlap_3254_arg3); + setRet(call_valid_reg_overlap_3254, 0, ret_val_valid_reg_overlap_3254); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77598,47 +77184,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3240; - x86::Gp ret_val_sew_3240 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3240, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3239; - auto fp_vector_imm_wv_3239_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3239_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3239_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3239_arg9 = gen_ext(cc, + InvokeNode* call_sew_3256; + x86::Gp ret_val_sew_3256 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3256, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3255; + auto fp_vector_imm_wv_3255_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3255_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3255_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3255_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_wv_3239_arg10 = rm; - auto fp_vector_imm_wv_3239_arg11 = ret_val_sew_3240; + auto fp_vector_imm_wv_3255_arg10 = rm; + auto fp_vector_imm_wv_3255_arg11 = ret_val_sew_3256; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3239, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3240, 0, reinterpret_cast(this)); - setRet(call_sew_3240, 0, ret_val_sew_3240); - setArg(call_fp_vector_imm_wv_3239, 0, V); - setArg(call_fp_vector_imm_wv_3239, 1, 48); - setArg(call_fp_vector_imm_wv_3239, 2, 5); - setArg(call_fp_vector_imm_wv_3239, 3, fp_vector_imm_wv_3239_arg3); - setArg(call_fp_vector_imm_wv_3239, 4, fp_vector_imm_wv_3239_arg4); - setArg(call_fp_vector_imm_wv_3239, 5, fp_vector_imm_wv_3239_arg5); - setArg(call_fp_vector_imm_wv_3239, 6, vm); - setArg(call_fp_vector_imm_wv_3239, 7, vd); - setArg(call_fp_vector_imm_wv_3239, 8, vs2); - setArg(call_fp_vector_imm_wv_3239, 9, fp_vector_imm_wv_3239_arg9); - setArg(call_fp_vector_imm_wv_3239, 10, fp_vector_imm_wv_3239_arg10); - setArg(call_fp_vector_imm_wv_3239, 11, fp_vector_imm_wv_3239_arg11); - InvokeNode* call_fget_flags_3241; - x86::Gp ret_val_fget_flags_3241 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3241, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3241; - setRet(call_fget_flags_3241, 0, ret_val_fget_flags_3241); + cc.invoke(&call_fp_vector_imm_wv_3255, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3256, 0, reinterpret_cast(this)); + setRet(call_sew_3256, 0, ret_val_sew_3256); + setArg(call_fp_vector_imm_wv_3255, 0, V); + setArg(call_fp_vector_imm_wv_3255, 1, 48); + setArg(call_fp_vector_imm_wv_3255, 2, 5); + setArg(call_fp_vector_imm_wv_3255, 3, fp_vector_imm_wv_3255_arg3); + setArg(call_fp_vector_imm_wv_3255, 4, fp_vector_imm_wv_3255_arg4); + setArg(call_fp_vector_imm_wv_3255, 5, fp_vector_imm_wv_3255_arg5); + setArg(call_fp_vector_imm_wv_3255, 6, vm); + setArg(call_fp_vector_imm_wv_3255, 7, vd); + setArg(call_fp_vector_imm_wv_3255, 8, vs2); + setArg(call_fp_vector_imm_wv_3255, 9, fp_vector_imm_wv_3255_arg9); + setArg(call_fp_vector_imm_wv_3255, 10, fp_vector_imm_wv_3255_arg10); + setArg(call_fp_vector_imm_wv_3255, 11, fp_vector_imm_wv_3255_arg11); + InvokeNode* call_fget_flags_3257; + x86::Gp ret_val_fget_flags_3257 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3257, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3257; + setRet(call_fget_flags_3257, 0, ret_val_fget_flags_3257); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3242 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3242, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3242, 64, false) - , traits::vstart); + auto tmp3258 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3258, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3258, traits::vstart); } cc.bind(label_merge); } @@ -77682,65 +77266,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3243; - x86::Gp ret_val_get_sew_pow_3243 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3243, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3244 = get_reg(cc, 8, false); - mov(cc, tmp3244, 1); + InvokeNode* call_get_sew_pow_3259; + x86::Gp ret_val_get_sew_pow_3259 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3259, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3260 = get_reg(cc, 8, false); + mov(cc, tmp3260, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3244, (ret_val_get_sew_pow_3243))), 8, false), ~ 1); - setArg(call_get_sew_pow_3243, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3243, 0, ret_val_get_sew_pow_3243); - InvokeNode* call_get_lmul_pow_3245; - x86::Gp ret_val_get_lmul_pow_3245 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3245, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3245; - setArg(call_get_lmul_pow_3245, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3245, 0, ret_val_get_lmul_pow_3245); + (gen_operation(cc, shl, tmp3260, (ret_val_get_sew_pow_3259))), 8, false), ~ 1); + setArg(call_get_sew_pow_3259, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3259, 0, ret_val_get_sew_pow_3259); + InvokeNode* call_get_lmul_pow_3261; + x86::Gp ret_val_get_lmul_pow_3261 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3261, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3261; + setArg(call_get_lmul_pow_3261, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3261, 0, ret_val_get_lmul_pow_3261); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3246; - auto illegal_fp_variable_width_3246_arg2 = SEW; - auto illegal_fp_variable_width_3246_arg3 = rm; - auto illegal_fp_variable_width_3246_arg4 = SEW_widen; - auto illegal_fp_variable_width_3246_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3246 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3246, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3247; - auto valid_reg_overlap_3247_arg2 = LMUL_pow; - auto valid_reg_overlap_3247_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3247 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3247, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3248; - auto valid_reg_overlap_3248_arg2 = LMUL_pow; - auto valid_reg_overlap_3248_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3248 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3248, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3246, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3247)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3248)); - setArg(call_illegal_fp_variable_width_3246, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3246, 1, vd); - setArg(call_illegal_fp_variable_width_3246, 2, vm); - setArg(call_illegal_fp_variable_width_3246, 3, illegal_fp_variable_width_3246_arg2); - setArg(call_illegal_fp_variable_width_3246, 4, illegal_fp_variable_width_3246_arg3); - setArg(call_illegal_fp_variable_width_3246, 5, illegal_fp_variable_width_3246_arg4); - setArg(call_illegal_fp_variable_width_3246, 6, illegal_fp_variable_width_3246_arg5); - setRet(call_illegal_fp_variable_width_3246, 0, ret_val_illegal_fp_variable_width_3246); - setArg(call_valid_reg_overlap_3247, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3247, 1, vs1); - setArg(call_valid_reg_overlap_3247, 2, vd); - setArg(call_valid_reg_overlap_3247, 3, valid_reg_overlap_3247_arg2); - setArg(call_valid_reg_overlap_3247, 4, valid_reg_overlap_3247_arg3); - setRet(call_valid_reg_overlap_3247, 0, ret_val_valid_reg_overlap_3247); - setArg(call_valid_reg_overlap_3248, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3248, 1, vs2); - setArg(call_valid_reg_overlap_3248, 2, vd); - setArg(call_valid_reg_overlap_3248, 3, valid_reg_overlap_3248_arg2); - setArg(call_valid_reg_overlap_3248, 4, valid_reg_overlap_3248_arg3); - setRet(call_valid_reg_overlap_3248, 0, ret_val_valid_reg_overlap_3248); + InvokeNode* call_illegal_fp_variable_width_3262; + auto illegal_fp_variable_width_3262_arg2 = SEW; + auto illegal_fp_variable_width_3262_arg3 = rm; + auto illegal_fp_variable_width_3262_arg4 = SEW_widen; + auto illegal_fp_variable_width_3262_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3262 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3262, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3263; + auto valid_reg_overlap_3263_arg2 = LMUL_pow; + auto valid_reg_overlap_3263_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3263 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3263, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3264; + auto valid_reg_overlap_3264_arg2 = LMUL_pow; + auto valid_reg_overlap_3264_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3264 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3264, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3262, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3263)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3264)); + setArg(call_illegal_fp_variable_width_3262, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3262, 1, vd); + setArg(call_illegal_fp_variable_width_3262, 2, vm); + setArg(call_illegal_fp_variable_width_3262, 3, illegal_fp_variable_width_3262_arg2); + setArg(call_illegal_fp_variable_width_3262, 4, illegal_fp_variable_width_3262_arg3); + setArg(call_illegal_fp_variable_width_3262, 5, illegal_fp_variable_width_3262_arg4); + setArg(call_illegal_fp_variable_width_3262, 6, illegal_fp_variable_width_3262_arg5); + setRet(call_illegal_fp_variable_width_3262, 0, ret_val_illegal_fp_variable_width_3262); + setArg(call_valid_reg_overlap_3263, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3263, 1, vs1); + setArg(call_valid_reg_overlap_3263, 2, vd); + setArg(call_valid_reg_overlap_3263, 3, valid_reg_overlap_3263_arg2); + setArg(call_valid_reg_overlap_3263, 4, valid_reg_overlap_3263_arg3); + setRet(call_valid_reg_overlap_3263, 0, ret_val_valid_reg_overlap_3263); + setArg(call_valid_reg_overlap_3264, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3264, 1, vs2); + setArg(call_valid_reg_overlap_3264, 2, vd); + setArg(call_valid_reg_overlap_3264, 3, valid_reg_overlap_3264_arg2); + setArg(call_valid_reg_overlap_3264, 4, valid_reg_overlap_3264_arg3); + setRet(call_valid_reg_overlap_3264, 0, ret_val_valid_reg_overlap_3264); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77756,45 +77340,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3250; - x86::Gp ret_val_sew_3250 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3250, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3249; - auto fp_vector_vector_wv_3249_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3249_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3249_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3249_arg10 = rm; - auto fp_vector_vector_wv_3249_arg11 = ret_val_sew_3250; + InvokeNode* call_sew_3266; + x86::Gp ret_val_sew_3266 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3266, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3265; + auto fp_vector_vector_wv_3265_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3265_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3265_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3265_arg10 = rm; + auto fp_vector_vector_wv_3265_arg11 = ret_val_sew_3266; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3249, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3250, 0, reinterpret_cast(this)); - setRet(call_sew_3250, 0, ret_val_sew_3250); - setArg(call_fp_vector_vector_wv_3249, 0, V); - setArg(call_fp_vector_vector_wv_3249, 1, 48); - setArg(call_fp_vector_vector_wv_3249, 2, 1); - setArg(call_fp_vector_vector_wv_3249, 3, fp_vector_vector_wv_3249_arg3); - setArg(call_fp_vector_vector_wv_3249, 4, fp_vector_vector_wv_3249_arg4); - setArg(call_fp_vector_vector_wv_3249, 5, fp_vector_vector_wv_3249_arg5); - setArg(call_fp_vector_vector_wv_3249, 6, vm); - setArg(call_fp_vector_vector_wv_3249, 7, vd); - setArg(call_fp_vector_vector_wv_3249, 8, vs2); - setArg(call_fp_vector_vector_wv_3249, 9, vs1); - setArg(call_fp_vector_vector_wv_3249, 10, fp_vector_vector_wv_3249_arg10); - setArg(call_fp_vector_vector_wv_3249, 11, fp_vector_vector_wv_3249_arg11); - InvokeNode* call_fget_flags_3251; - x86::Gp ret_val_fget_flags_3251 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3251, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3251; - setRet(call_fget_flags_3251, 0, ret_val_fget_flags_3251); + cc.invoke(&call_fp_vector_vector_wv_3265, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3266, 0, reinterpret_cast(this)); + setRet(call_sew_3266, 0, ret_val_sew_3266); + setArg(call_fp_vector_vector_wv_3265, 0, V); + setArg(call_fp_vector_vector_wv_3265, 1, 48); + setArg(call_fp_vector_vector_wv_3265, 2, 1); + setArg(call_fp_vector_vector_wv_3265, 3, fp_vector_vector_wv_3265_arg3); + setArg(call_fp_vector_vector_wv_3265, 4, fp_vector_vector_wv_3265_arg4); + setArg(call_fp_vector_vector_wv_3265, 5, fp_vector_vector_wv_3265_arg5); + setArg(call_fp_vector_vector_wv_3265, 6, vm); + setArg(call_fp_vector_vector_wv_3265, 7, vd); + setArg(call_fp_vector_vector_wv_3265, 8, vs2); + setArg(call_fp_vector_vector_wv_3265, 9, vs1); + setArg(call_fp_vector_vector_wv_3265, 10, fp_vector_vector_wv_3265_arg10); + setArg(call_fp_vector_vector_wv_3265, 11, fp_vector_vector_wv_3265_arg11); + InvokeNode* call_fget_flags_3267; + x86::Gp ret_val_fget_flags_3267 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3267, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3267; + setRet(call_fget_flags_3267, 0, ret_val_fget_flags_3267); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3252 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3252, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3252, 64, false) - , traits::vstart); + auto tmp3268 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3268, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3268, traits::vstart); } cc.bind(label_merge); } @@ -77838,54 +77420,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3253; - x86::Gp ret_val_get_sew_pow_3253 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3253, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3254 = get_reg(cc, 8, false); - mov(cc, tmp3254, 1); + InvokeNode* call_get_sew_pow_3269; + x86::Gp ret_val_get_sew_pow_3269 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3269, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3270 = get_reg(cc, 8, false); + mov(cc, tmp3270, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3254, (ret_val_get_sew_pow_3253))), 8, false), ~ 1); - setArg(call_get_sew_pow_3253, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3253, 0, ret_val_get_sew_pow_3253); - InvokeNode* call_get_lmul_pow_3255; - x86::Gp ret_val_get_lmul_pow_3255 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3255, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3255; - setArg(call_get_lmul_pow_3255, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3255, 0, ret_val_get_lmul_pow_3255); + (gen_operation(cc, shl, tmp3270, (ret_val_get_sew_pow_3269))), 8, false), ~ 1); + setArg(call_get_sew_pow_3269, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3269, 0, ret_val_get_sew_pow_3269); + InvokeNode* call_get_lmul_pow_3271; + x86::Gp ret_val_get_lmul_pow_3271 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3271, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3271; + setArg(call_get_lmul_pow_3271, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3271, 0, ret_val_get_lmul_pow_3271); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3256; - auto illegal_fp_variable_width_3256_arg2 = SEW; - auto illegal_fp_variable_width_3256_arg3 = rm; - auto illegal_fp_variable_width_3256_arg4 = SEW_widen; - auto illegal_fp_variable_width_3256_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3256 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3256, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3257; - auto valid_reg_overlap_3257_arg2 = LMUL_pow; - auto valid_reg_overlap_3257_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3257 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3257, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3256, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3257)); - setArg(call_illegal_fp_variable_width_3256, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3256, 1, vd); - setArg(call_illegal_fp_variable_width_3256, 2, vm); - setArg(call_illegal_fp_variable_width_3256, 3, illegal_fp_variable_width_3256_arg2); - setArg(call_illegal_fp_variable_width_3256, 4, illegal_fp_variable_width_3256_arg3); - setArg(call_illegal_fp_variable_width_3256, 5, illegal_fp_variable_width_3256_arg4); - setArg(call_illegal_fp_variable_width_3256, 6, illegal_fp_variable_width_3256_arg5); - setRet(call_illegal_fp_variable_width_3256, 0, ret_val_illegal_fp_variable_width_3256); - setArg(call_valid_reg_overlap_3257, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3257, 1, vs2); - setArg(call_valid_reg_overlap_3257, 2, vd); - setArg(call_valid_reg_overlap_3257, 3, valid_reg_overlap_3257_arg2); - setArg(call_valid_reg_overlap_3257, 4, valid_reg_overlap_3257_arg3); - setRet(call_valid_reg_overlap_3257, 0, ret_val_valid_reg_overlap_3257); + InvokeNode* call_illegal_fp_variable_width_3272; + auto illegal_fp_variable_width_3272_arg2 = SEW; + auto illegal_fp_variable_width_3272_arg3 = rm; + auto illegal_fp_variable_width_3272_arg4 = SEW_widen; + auto illegal_fp_variable_width_3272_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3272 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3272, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3273; + auto valid_reg_overlap_3273_arg2 = LMUL_pow; + auto valid_reg_overlap_3273_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3273 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3273, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3272, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3273)); + setArg(call_illegal_fp_variable_width_3272, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3272, 1, vd); + setArg(call_illegal_fp_variable_width_3272, 2, vm); + setArg(call_illegal_fp_variable_width_3272, 3, illegal_fp_variable_width_3272_arg2); + setArg(call_illegal_fp_variable_width_3272, 4, illegal_fp_variable_width_3272_arg3); + setArg(call_illegal_fp_variable_width_3272, 5, illegal_fp_variable_width_3272_arg4); + setArg(call_illegal_fp_variable_width_3272, 6, illegal_fp_variable_width_3272_arg5); + setRet(call_illegal_fp_variable_width_3272, 0, ret_val_illegal_fp_variable_width_3272); + setArg(call_valid_reg_overlap_3273, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3273, 1, vs2); + setArg(call_valid_reg_overlap_3273, 2, vd); + setArg(call_valid_reg_overlap_3273, 3, valid_reg_overlap_3273_arg2); + setArg(call_valid_reg_overlap_3273, 4, valid_reg_overlap_3273_arg3); + setRet(call_valid_reg_overlap_3273, 0, ret_val_valid_reg_overlap_3273); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -77901,47 +77483,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3259; - x86::Gp ret_val_sew_3259 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3259, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3258; - auto fp_vector_imm_wv_3258_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3258_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3258_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3258_arg9 = gen_ext(cc, + InvokeNode* call_sew_3275; + x86::Gp ret_val_sew_3275 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3275, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3274; + auto fp_vector_imm_wv_3274_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3274_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3274_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3274_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_wv_3258_arg10 = rm; - auto fp_vector_imm_wv_3258_arg11 = ret_val_sew_3259; + auto fp_vector_imm_wv_3274_arg10 = rm; + auto fp_vector_imm_wv_3274_arg11 = ret_val_sew_3275; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3258, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3259, 0, reinterpret_cast(this)); - setRet(call_sew_3259, 0, ret_val_sew_3259); - setArg(call_fp_vector_imm_wv_3258, 0, V); - setArg(call_fp_vector_imm_wv_3258, 1, 50); - setArg(call_fp_vector_imm_wv_3258, 2, 5); - setArg(call_fp_vector_imm_wv_3258, 3, fp_vector_imm_wv_3258_arg3); - setArg(call_fp_vector_imm_wv_3258, 4, fp_vector_imm_wv_3258_arg4); - setArg(call_fp_vector_imm_wv_3258, 5, fp_vector_imm_wv_3258_arg5); - setArg(call_fp_vector_imm_wv_3258, 6, vm); - setArg(call_fp_vector_imm_wv_3258, 7, vd); - setArg(call_fp_vector_imm_wv_3258, 8, vs2); - setArg(call_fp_vector_imm_wv_3258, 9, fp_vector_imm_wv_3258_arg9); - setArg(call_fp_vector_imm_wv_3258, 10, fp_vector_imm_wv_3258_arg10); - setArg(call_fp_vector_imm_wv_3258, 11, fp_vector_imm_wv_3258_arg11); - InvokeNode* call_fget_flags_3260; - x86::Gp ret_val_fget_flags_3260 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3260, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3260; - setRet(call_fget_flags_3260, 0, ret_val_fget_flags_3260); + cc.invoke(&call_fp_vector_imm_wv_3274, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3275, 0, reinterpret_cast(this)); + setRet(call_sew_3275, 0, ret_val_sew_3275); + setArg(call_fp_vector_imm_wv_3274, 0, V); + setArg(call_fp_vector_imm_wv_3274, 1, 50); + setArg(call_fp_vector_imm_wv_3274, 2, 5); + setArg(call_fp_vector_imm_wv_3274, 3, fp_vector_imm_wv_3274_arg3); + setArg(call_fp_vector_imm_wv_3274, 4, fp_vector_imm_wv_3274_arg4); + setArg(call_fp_vector_imm_wv_3274, 5, fp_vector_imm_wv_3274_arg5); + setArg(call_fp_vector_imm_wv_3274, 6, vm); + setArg(call_fp_vector_imm_wv_3274, 7, vd); + setArg(call_fp_vector_imm_wv_3274, 8, vs2); + setArg(call_fp_vector_imm_wv_3274, 9, fp_vector_imm_wv_3274_arg9); + setArg(call_fp_vector_imm_wv_3274, 10, fp_vector_imm_wv_3274_arg10); + setArg(call_fp_vector_imm_wv_3274, 11, fp_vector_imm_wv_3274_arg11); + InvokeNode* call_fget_flags_3276; + x86::Gp ret_val_fget_flags_3276 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3276, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3276; + setRet(call_fget_flags_3276, 0, ret_val_fget_flags_3276); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3261 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3261, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3261, 64, false) - , traits::vstart); + auto tmp3277 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3277, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3277, traits::vstart); } cc.bind(label_merge); } @@ -77985,65 +77565,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3262; - x86::Gp ret_val_get_sew_pow_3262 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3262, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3263 = get_reg(cc, 8, false); - mov(cc, tmp3263, 1); + InvokeNode* call_get_sew_pow_3278; + x86::Gp ret_val_get_sew_pow_3278 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3278, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3279 = get_reg(cc, 8, false); + mov(cc, tmp3279, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3263, (ret_val_get_sew_pow_3262))), 8, false), ~ 1); - setArg(call_get_sew_pow_3262, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3262, 0, ret_val_get_sew_pow_3262); - InvokeNode* call_get_lmul_pow_3264; - x86::Gp ret_val_get_lmul_pow_3264 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3264, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3264; - setArg(call_get_lmul_pow_3264, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3264, 0, ret_val_get_lmul_pow_3264); + (gen_operation(cc, shl, tmp3279, (ret_val_get_sew_pow_3278))), 8, false), ~ 1); + setArg(call_get_sew_pow_3278, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3278, 0, ret_val_get_sew_pow_3278); + InvokeNode* call_get_lmul_pow_3280; + x86::Gp ret_val_get_lmul_pow_3280 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3280, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3280; + setArg(call_get_lmul_pow_3280, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3280, 0, ret_val_get_lmul_pow_3280); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3265; - auto illegal_fp_variable_width_3265_arg2 = SEW; - auto illegal_fp_variable_width_3265_arg3 = rm; - auto illegal_fp_variable_width_3265_arg4 = SEW_widen; - auto illegal_fp_variable_width_3265_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3265 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3265, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3266; - auto valid_reg_overlap_3266_arg2 = LMUL_pow; - auto valid_reg_overlap_3266_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3266 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3266, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3267; - auto valid_reg_overlap_3267_arg2 = LMUL_pow; - auto valid_reg_overlap_3267_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3267 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3267, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3265, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3266)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3267)); - setArg(call_illegal_fp_variable_width_3265, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3265, 1, vd); - setArg(call_illegal_fp_variable_width_3265, 2, vm); - setArg(call_illegal_fp_variable_width_3265, 3, illegal_fp_variable_width_3265_arg2); - setArg(call_illegal_fp_variable_width_3265, 4, illegal_fp_variable_width_3265_arg3); - setArg(call_illegal_fp_variable_width_3265, 5, illegal_fp_variable_width_3265_arg4); - setArg(call_illegal_fp_variable_width_3265, 6, illegal_fp_variable_width_3265_arg5); - setRet(call_illegal_fp_variable_width_3265, 0, ret_val_illegal_fp_variable_width_3265); - setArg(call_valid_reg_overlap_3266, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3266, 1, vs1); - setArg(call_valid_reg_overlap_3266, 2, vd); - setArg(call_valid_reg_overlap_3266, 3, valid_reg_overlap_3266_arg2); - setArg(call_valid_reg_overlap_3266, 4, valid_reg_overlap_3266_arg3); - setRet(call_valid_reg_overlap_3266, 0, ret_val_valid_reg_overlap_3266); - setArg(call_valid_reg_overlap_3267, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3267, 1, vs2); - setArg(call_valid_reg_overlap_3267, 2, vd); - setArg(call_valid_reg_overlap_3267, 3, valid_reg_overlap_3267_arg2); - setArg(call_valid_reg_overlap_3267, 4, valid_reg_overlap_3267_arg3); - setRet(call_valid_reg_overlap_3267, 0, ret_val_valid_reg_overlap_3267); + InvokeNode* call_illegal_fp_variable_width_3281; + auto illegal_fp_variable_width_3281_arg2 = SEW; + auto illegal_fp_variable_width_3281_arg3 = rm; + auto illegal_fp_variable_width_3281_arg4 = SEW_widen; + auto illegal_fp_variable_width_3281_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3281 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3281, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3282; + auto valid_reg_overlap_3282_arg2 = LMUL_pow; + auto valid_reg_overlap_3282_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3282 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3282, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3283; + auto valid_reg_overlap_3283_arg2 = LMUL_pow; + auto valid_reg_overlap_3283_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3283 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3283, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3281, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3282)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3283)); + setArg(call_illegal_fp_variable_width_3281, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3281, 1, vd); + setArg(call_illegal_fp_variable_width_3281, 2, vm); + setArg(call_illegal_fp_variable_width_3281, 3, illegal_fp_variable_width_3281_arg2); + setArg(call_illegal_fp_variable_width_3281, 4, illegal_fp_variable_width_3281_arg3); + setArg(call_illegal_fp_variable_width_3281, 5, illegal_fp_variable_width_3281_arg4); + setArg(call_illegal_fp_variable_width_3281, 6, illegal_fp_variable_width_3281_arg5); + setRet(call_illegal_fp_variable_width_3281, 0, ret_val_illegal_fp_variable_width_3281); + setArg(call_valid_reg_overlap_3282, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3282, 1, vs1); + setArg(call_valid_reg_overlap_3282, 2, vd); + setArg(call_valid_reg_overlap_3282, 3, valid_reg_overlap_3282_arg2); + setArg(call_valid_reg_overlap_3282, 4, valid_reg_overlap_3282_arg3); + setRet(call_valid_reg_overlap_3282, 0, ret_val_valid_reg_overlap_3282); + setArg(call_valid_reg_overlap_3283, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3283, 1, vs2); + setArg(call_valid_reg_overlap_3283, 2, vd); + setArg(call_valid_reg_overlap_3283, 3, valid_reg_overlap_3283_arg2); + setArg(call_valid_reg_overlap_3283, 4, valid_reg_overlap_3283_arg3); + setRet(call_valid_reg_overlap_3283, 0, ret_val_valid_reg_overlap_3283); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78059,45 +77639,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3269; - x86::Gp ret_val_sew_3269 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3269, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3268; - auto fp_vector_vector_wv_3268_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3268_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3268_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3268_arg10 = rm; - auto fp_vector_vector_wv_3268_arg11 = ret_val_sew_3269; + InvokeNode* call_sew_3285; + x86::Gp ret_val_sew_3285 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3285, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3284; + auto fp_vector_vector_wv_3284_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3284_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3284_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3284_arg10 = rm; + auto fp_vector_vector_wv_3284_arg11 = ret_val_sew_3285; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3268, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3269, 0, reinterpret_cast(this)); - setRet(call_sew_3269, 0, ret_val_sew_3269); - setArg(call_fp_vector_vector_wv_3268, 0, V); - setArg(call_fp_vector_vector_wv_3268, 1, 50); - setArg(call_fp_vector_vector_wv_3268, 2, 1); - setArg(call_fp_vector_vector_wv_3268, 3, fp_vector_vector_wv_3268_arg3); - setArg(call_fp_vector_vector_wv_3268, 4, fp_vector_vector_wv_3268_arg4); - setArg(call_fp_vector_vector_wv_3268, 5, fp_vector_vector_wv_3268_arg5); - setArg(call_fp_vector_vector_wv_3268, 6, vm); - setArg(call_fp_vector_vector_wv_3268, 7, vd); - setArg(call_fp_vector_vector_wv_3268, 8, vs2); - setArg(call_fp_vector_vector_wv_3268, 9, vs1); - setArg(call_fp_vector_vector_wv_3268, 10, fp_vector_vector_wv_3268_arg10); - setArg(call_fp_vector_vector_wv_3268, 11, fp_vector_vector_wv_3268_arg11); - InvokeNode* call_fget_flags_3270; - x86::Gp ret_val_fget_flags_3270 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3270, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3270; - setRet(call_fget_flags_3270, 0, ret_val_fget_flags_3270); + cc.invoke(&call_fp_vector_vector_wv_3284, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3285, 0, reinterpret_cast(this)); + setRet(call_sew_3285, 0, ret_val_sew_3285); + setArg(call_fp_vector_vector_wv_3284, 0, V); + setArg(call_fp_vector_vector_wv_3284, 1, 50); + setArg(call_fp_vector_vector_wv_3284, 2, 1); + setArg(call_fp_vector_vector_wv_3284, 3, fp_vector_vector_wv_3284_arg3); + setArg(call_fp_vector_vector_wv_3284, 4, fp_vector_vector_wv_3284_arg4); + setArg(call_fp_vector_vector_wv_3284, 5, fp_vector_vector_wv_3284_arg5); + setArg(call_fp_vector_vector_wv_3284, 6, vm); + setArg(call_fp_vector_vector_wv_3284, 7, vd); + setArg(call_fp_vector_vector_wv_3284, 8, vs2); + setArg(call_fp_vector_vector_wv_3284, 9, vs1); + setArg(call_fp_vector_vector_wv_3284, 10, fp_vector_vector_wv_3284_arg10); + setArg(call_fp_vector_vector_wv_3284, 11, fp_vector_vector_wv_3284_arg11); + InvokeNode* call_fget_flags_3286; + x86::Gp ret_val_fget_flags_3286 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3286, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3286; + setRet(call_fget_flags_3286, 0, ret_val_fget_flags_3286); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3271 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3271, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3271, 64, false) - , traits::vstart); + auto tmp3287 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3287, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3287, traits::vstart); } cc.bind(label_merge); } @@ -78141,43 +77719,43 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3272; - x86::Gp ret_val_get_sew_pow_3272 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3272, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3273 = get_reg(cc, 8, false); - mov(cc, tmp3273, 1); + InvokeNode* call_get_sew_pow_3288; + x86::Gp ret_val_get_sew_pow_3288 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3288, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3289 = get_reg(cc, 8, false); + mov(cc, tmp3289, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3273, (ret_val_get_sew_pow_3272))), 8, false), ~ 1); - setArg(call_get_sew_pow_3272, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3272, 0, ret_val_get_sew_pow_3272); - InvokeNode* call_get_lmul_pow_3274; - x86::Gp ret_val_get_lmul_pow_3274 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3274, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3274; - setArg(call_get_lmul_pow_3274, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3274, 0, ret_val_get_lmul_pow_3274); + (gen_operation(cc, shl, tmp3289, (ret_val_get_sew_pow_3288))), 8, false), ~ 1); + setArg(call_get_sew_pow_3288, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3288, 0, ret_val_get_sew_pow_3288); + InvokeNode* call_get_lmul_pow_3290; + x86::Gp ret_val_get_lmul_pow_3290 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3290, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3290; + setArg(call_get_lmul_pow_3290, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3290, 0, ret_val_get_lmul_pow_3290); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3275; - auto illegal_fp_variable_width_3275_arg2 = SEW; - auto illegal_fp_variable_width_3275_arg3 = rm; - auto illegal_fp_variable_width_3275_arg4 = SEW_widen; - auto illegal_fp_variable_width_3275_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3275 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3275, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - auto cond = ret_val_illegal_fp_variable_width_3275; - setArg(call_illegal_fp_variable_width_3275, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3275, 1, vd); - setArg(call_illegal_fp_variable_width_3275, 2, vm); - setArg(call_illegal_fp_variable_width_3275, 3, illegal_fp_variable_width_3275_arg2); - setArg(call_illegal_fp_variable_width_3275, 4, illegal_fp_variable_width_3275_arg3); - setArg(call_illegal_fp_variable_width_3275, 5, illegal_fp_variable_width_3275_arg4); - setArg(call_illegal_fp_variable_width_3275, 6, illegal_fp_variable_width_3275_arg5); - setRet(call_illegal_fp_variable_width_3275, 0, ret_val_illegal_fp_variable_width_3275); + InvokeNode* call_illegal_fp_variable_width_3291; + auto illegal_fp_variable_width_3291_arg2 = SEW; + auto illegal_fp_variable_width_3291_arg3 = rm; + auto illegal_fp_variable_width_3291_arg4 = SEW_widen; + auto illegal_fp_variable_width_3291_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3291 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3291, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_fp_variable_width_3291; + setArg(call_illegal_fp_variable_width_3291, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3291, 1, vd); + setArg(call_illegal_fp_variable_width_3291, 2, vm); + setArg(call_illegal_fp_variable_width_3291, 3, illegal_fp_variable_width_3291_arg2); + setArg(call_illegal_fp_variable_width_3291, 4, illegal_fp_variable_width_3291_arg3); + setArg(call_illegal_fp_variable_width_3291, 5, illegal_fp_variable_width_3291_arg4); + setArg(call_illegal_fp_variable_width_3291, 6, illegal_fp_variable_width_3291_arg5); + setRet(call_illegal_fp_variable_width_3291, 0, ret_val_illegal_fp_variable_width_3291); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78193,47 +77771,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3277; - x86::Gp ret_val_sew_3277 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3277, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_ww_3276; - auto fp_vector_imm_ww_3276_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_ww_3276_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_ww_3276_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_ww_3276_arg9 = gen_ext(cc, + InvokeNode* call_sew_3293; + x86::Gp ret_val_sew_3293 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3293, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_ww_3292; + auto fp_vector_imm_ww_3292_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_ww_3292_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_ww_3292_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_ww_3292_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_ww_3276_arg10 = rm; - auto fp_vector_imm_ww_3276_arg11 = ret_val_sew_3277; + auto fp_vector_imm_ww_3292_arg10 = rm; + auto fp_vector_imm_ww_3292_arg11 = ret_val_sew_3293; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_ww_3276, &fp_vector_imm_ww, FuncSignature::build()); - setArg(call_sew_3277, 0, reinterpret_cast(this)); - setRet(call_sew_3277, 0, ret_val_sew_3277); - setArg(call_fp_vector_imm_ww_3276, 0, V); - setArg(call_fp_vector_imm_ww_3276, 1, 52); - setArg(call_fp_vector_imm_ww_3276, 2, 5); - setArg(call_fp_vector_imm_ww_3276, 3, fp_vector_imm_ww_3276_arg3); - setArg(call_fp_vector_imm_ww_3276, 4, fp_vector_imm_ww_3276_arg4); - setArg(call_fp_vector_imm_ww_3276, 5, fp_vector_imm_ww_3276_arg5); - setArg(call_fp_vector_imm_ww_3276, 6, vm); - setArg(call_fp_vector_imm_ww_3276, 7, vd); - setArg(call_fp_vector_imm_ww_3276, 8, vs2); - setArg(call_fp_vector_imm_ww_3276, 9, fp_vector_imm_ww_3276_arg9); - setArg(call_fp_vector_imm_ww_3276, 10, fp_vector_imm_ww_3276_arg10); - setArg(call_fp_vector_imm_ww_3276, 11, fp_vector_imm_ww_3276_arg11); - InvokeNode* call_fget_flags_3278; - x86::Gp ret_val_fget_flags_3278 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3278, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3278; - setRet(call_fget_flags_3278, 0, ret_val_fget_flags_3278); + cc.invoke(&call_fp_vector_imm_ww_3292, &fp_vector_imm_ww, FuncSignature::build()); + setArg(call_sew_3293, 0, reinterpret_cast(this)); + setRet(call_sew_3293, 0, ret_val_sew_3293); + setArg(call_fp_vector_imm_ww_3292, 0, V); + setArg(call_fp_vector_imm_ww_3292, 1, 52); + setArg(call_fp_vector_imm_ww_3292, 2, 5); + setArg(call_fp_vector_imm_ww_3292, 3, fp_vector_imm_ww_3292_arg3); + setArg(call_fp_vector_imm_ww_3292, 4, fp_vector_imm_ww_3292_arg4); + setArg(call_fp_vector_imm_ww_3292, 5, fp_vector_imm_ww_3292_arg5); + setArg(call_fp_vector_imm_ww_3292, 6, vm); + setArg(call_fp_vector_imm_ww_3292, 7, vd); + setArg(call_fp_vector_imm_ww_3292, 8, vs2); + setArg(call_fp_vector_imm_ww_3292, 9, fp_vector_imm_ww_3292_arg9); + setArg(call_fp_vector_imm_ww_3292, 10, fp_vector_imm_ww_3292_arg10); + setArg(call_fp_vector_imm_ww_3292, 11, fp_vector_imm_ww_3292_arg11); + InvokeNode* call_fget_flags_3294; + x86::Gp ret_val_fget_flags_3294 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3294, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3294; + setRet(call_fget_flags_3294, 0, ret_val_fget_flags_3294); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3279 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3279, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3279, 64, false) - , traits::vstart); + auto tmp3295 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3295, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3295, traits::vstart); } cc.bind(label_merge); } @@ -78277,54 +77853,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3280; - x86::Gp ret_val_get_sew_pow_3280 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3280, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3281 = get_reg(cc, 8, false); - mov(cc, tmp3281, 1); + InvokeNode* call_get_sew_pow_3296; + x86::Gp ret_val_get_sew_pow_3296 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3296, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3297 = get_reg(cc, 8, false); + mov(cc, tmp3297, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3281, (ret_val_get_sew_pow_3280))), 8, false), ~ 1); - setArg(call_get_sew_pow_3280, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3280, 0, ret_val_get_sew_pow_3280); - InvokeNode* call_get_lmul_pow_3282; - x86::Gp ret_val_get_lmul_pow_3282 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3282, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3282; - setArg(call_get_lmul_pow_3282, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3282, 0, ret_val_get_lmul_pow_3282); + (gen_operation(cc, shl, tmp3297, (ret_val_get_sew_pow_3296))), 8, false), ~ 1); + setArg(call_get_sew_pow_3296, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3296, 0, ret_val_get_sew_pow_3296); + InvokeNode* call_get_lmul_pow_3298; + x86::Gp ret_val_get_lmul_pow_3298 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3298, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3298; + setArg(call_get_lmul_pow_3298, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3298, 0, ret_val_get_lmul_pow_3298); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3283; - auto illegal_fp_variable_width_3283_arg2 = SEW; - auto illegal_fp_variable_width_3283_arg3 = rm; - auto illegal_fp_variable_width_3283_arg4 = SEW_widen; - auto illegal_fp_variable_width_3283_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3283 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3283, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3284; - auto valid_reg_overlap_3284_arg2 = LMUL_pow; - auto valid_reg_overlap_3284_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3284 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3284, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3283, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3284)); - setArg(call_illegal_fp_variable_width_3283, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3283, 1, vd); - setArg(call_illegal_fp_variable_width_3283, 2, vm); - setArg(call_illegal_fp_variable_width_3283, 3, illegal_fp_variable_width_3283_arg2); - setArg(call_illegal_fp_variable_width_3283, 4, illegal_fp_variable_width_3283_arg3); - setArg(call_illegal_fp_variable_width_3283, 5, illegal_fp_variable_width_3283_arg4); - setArg(call_illegal_fp_variable_width_3283, 6, illegal_fp_variable_width_3283_arg5); - setRet(call_illegal_fp_variable_width_3283, 0, ret_val_illegal_fp_variable_width_3283); - setArg(call_valid_reg_overlap_3284, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3284, 1, vs1); - setArg(call_valid_reg_overlap_3284, 2, vd); - setArg(call_valid_reg_overlap_3284, 3, valid_reg_overlap_3284_arg2); - setArg(call_valid_reg_overlap_3284, 4, valid_reg_overlap_3284_arg3); - setRet(call_valid_reg_overlap_3284, 0, ret_val_valid_reg_overlap_3284); + InvokeNode* call_illegal_fp_variable_width_3299; + auto illegal_fp_variable_width_3299_arg2 = SEW; + auto illegal_fp_variable_width_3299_arg3 = rm; + auto illegal_fp_variable_width_3299_arg4 = SEW_widen; + auto illegal_fp_variable_width_3299_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3299 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3299, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3300; + auto valid_reg_overlap_3300_arg2 = LMUL_pow; + auto valid_reg_overlap_3300_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3300 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3300, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3299, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3300)); + setArg(call_illegal_fp_variable_width_3299, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3299, 1, vd); + setArg(call_illegal_fp_variable_width_3299, 2, vm); + setArg(call_illegal_fp_variable_width_3299, 3, illegal_fp_variable_width_3299_arg2); + setArg(call_illegal_fp_variable_width_3299, 4, illegal_fp_variable_width_3299_arg3); + setArg(call_illegal_fp_variable_width_3299, 5, illegal_fp_variable_width_3299_arg4); + setArg(call_illegal_fp_variable_width_3299, 6, illegal_fp_variable_width_3299_arg5); + setRet(call_illegal_fp_variable_width_3299, 0, ret_val_illegal_fp_variable_width_3299); + setArg(call_valid_reg_overlap_3300, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3300, 1, vs1); + setArg(call_valid_reg_overlap_3300, 2, vd); + setArg(call_valid_reg_overlap_3300, 3, valid_reg_overlap_3300_arg2); + setArg(call_valid_reg_overlap_3300, 4, valid_reg_overlap_3300_arg3); + setRet(call_valid_reg_overlap_3300, 0, ret_val_valid_reg_overlap_3300); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78340,45 +77916,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3286; - x86::Gp ret_val_sew_3286 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3286, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_ww_3285; - auto fp_vector_vector_ww_3285_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_ww_3285_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_ww_3285_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_ww_3285_arg10 = rm; - auto fp_vector_vector_ww_3285_arg11 = ret_val_sew_3286; + InvokeNode* call_sew_3302; + x86::Gp ret_val_sew_3302 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3302, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_ww_3301; + auto fp_vector_vector_ww_3301_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_ww_3301_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_ww_3301_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_ww_3301_arg10 = rm; + auto fp_vector_vector_ww_3301_arg11 = ret_val_sew_3302; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_ww_3285, &fp_vector_vector_ww, FuncSignature::build()); - setArg(call_sew_3286, 0, reinterpret_cast(this)); - setRet(call_sew_3286, 0, ret_val_sew_3286); - setArg(call_fp_vector_vector_ww_3285, 0, V); - setArg(call_fp_vector_vector_ww_3285, 1, 52); - setArg(call_fp_vector_vector_ww_3285, 2, 1); - setArg(call_fp_vector_vector_ww_3285, 3, fp_vector_vector_ww_3285_arg3); - setArg(call_fp_vector_vector_ww_3285, 4, fp_vector_vector_ww_3285_arg4); - setArg(call_fp_vector_vector_ww_3285, 5, fp_vector_vector_ww_3285_arg5); - setArg(call_fp_vector_vector_ww_3285, 6, vm); - setArg(call_fp_vector_vector_ww_3285, 7, vd); - setArg(call_fp_vector_vector_ww_3285, 8, vs2); - setArg(call_fp_vector_vector_ww_3285, 9, vs1); - setArg(call_fp_vector_vector_ww_3285, 10, fp_vector_vector_ww_3285_arg10); - setArg(call_fp_vector_vector_ww_3285, 11, fp_vector_vector_ww_3285_arg11); - InvokeNode* call_fget_flags_3287; - x86::Gp ret_val_fget_flags_3287 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3287, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3287; - setRet(call_fget_flags_3287, 0, ret_val_fget_flags_3287); + cc.invoke(&call_fp_vector_vector_ww_3301, &fp_vector_vector_ww, FuncSignature::build()); + setArg(call_sew_3302, 0, reinterpret_cast(this)); + setRet(call_sew_3302, 0, ret_val_sew_3302); + setArg(call_fp_vector_vector_ww_3301, 0, V); + setArg(call_fp_vector_vector_ww_3301, 1, 52); + setArg(call_fp_vector_vector_ww_3301, 2, 1); + setArg(call_fp_vector_vector_ww_3301, 3, fp_vector_vector_ww_3301_arg3); + setArg(call_fp_vector_vector_ww_3301, 4, fp_vector_vector_ww_3301_arg4); + setArg(call_fp_vector_vector_ww_3301, 5, fp_vector_vector_ww_3301_arg5); + setArg(call_fp_vector_vector_ww_3301, 6, vm); + setArg(call_fp_vector_vector_ww_3301, 7, vd); + setArg(call_fp_vector_vector_ww_3301, 8, vs2); + setArg(call_fp_vector_vector_ww_3301, 9, vs1); + setArg(call_fp_vector_vector_ww_3301, 10, fp_vector_vector_ww_3301_arg10); + setArg(call_fp_vector_vector_ww_3301, 11, fp_vector_vector_ww_3301_arg11); + InvokeNode* call_fget_flags_3303; + x86::Gp ret_val_fget_flags_3303 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3303, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3303; + setRet(call_fget_flags_3303, 0, ret_val_fget_flags_3303); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3288 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3288, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3288, 64, false) - , traits::vstart); + auto tmp3304 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3304, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3304, traits::vstart); } cc.bind(label_merge); } @@ -78422,43 +77996,43 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3289; - x86::Gp ret_val_get_sew_pow_3289 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3289, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3290 = get_reg(cc, 8, false); - mov(cc, tmp3290, 1); + InvokeNode* call_get_sew_pow_3305; + x86::Gp ret_val_get_sew_pow_3305 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3305, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3306 = get_reg(cc, 8, false); + mov(cc, tmp3306, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3290, (ret_val_get_sew_pow_3289))), 8, false), ~ 1); - setArg(call_get_sew_pow_3289, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3289, 0, ret_val_get_sew_pow_3289); - InvokeNode* call_get_lmul_pow_3291; - x86::Gp ret_val_get_lmul_pow_3291 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3291, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3291; - setArg(call_get_lmul_pow_3291, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3291, 0, ret_val_get_lmul_pow_3291); + (gen_operation(cc, shl, tmp3306, (ret_val_get_sew_pow_3305))), 8, false), ~ 1); + setArg(call_get_sew_pow_3305, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3305, 0, ret_val_get_sew_pow_3305); + InvokeNode* call_get_lmul_pow_3307; + x86::Gp ret_val_get_lmul_pow_3307 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3307, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3307; + setArg(call_get_lmul_pow_3307, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3307, 0, ret_val_get_lmul_pow_3307); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3292; - auto illegal_fp_variable_width_3292_arg2 = SEW; - auto illegal_fp_variable_width_3292_arg3 = rm; - auto illegal_fp_variable_width_3292_arg4 = SEW_widen; - auto illegal_fp_variable_width_3292_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3292 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3292, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - auto cond = ret_val_illegal_fp_variable_width_3292; - setArg(call_illegal_fp_variable_width_3292, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3292, 1, vd); - setArg(call_illegal_fp_variable_width_3292, 2, vm); - setArg(call_illegal_fp_variable_width_3292, 3, illegal_fp_variable_width_3292_arg2); - setArg(call_illegal_fp_variable_width_3292, 4, illegal_fp_variable_width_3292_arg3); - setArg(call_illegal_fp_variable_width_3292, 5, illegal_fp_variable_width_3292_arg4); - setArg(call_illegal_fp_variable_width_3292, 6, illegal_fp_variable_width_3292_arg5); - setRet(call_illegal_fp_variable_width_3292, 0, ret_val_illegal_fp_variable_width_3292); + InvokeNode* call_illegal_fp_variable_width_3308; + auto illegal_fp_variable_width_3308_arg2 = SEW; + auto illegal_fp_variable_width_3308_arg3 = rm; + auto illegal_fp_variable_width_3308_arg4 = SEW_widen; + auto illegal_fp_variable_width_3308_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3308 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3308, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + auto cond = ret_val_illegal_fp_variable_width_3308; + setArg(call_illegal_fp_variable_width_3308, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3308, 1, vd); + setArg(call_illegal_fp_variable_width_3308, 2, vm); + setArg(call_illegal_fp_variable_width_3308, 3, illegal_fp_variable_width_3308_arg2); + setArg(call_illegal_fp_variable_width_3308, 4, illegal_fp_variable_width_3308_arg3); + setArg(call_illegal_fp_variable_width_3308, 5, illegal_fp_variable_width_3308_arg4); + setArg(call_illegal_fp_variable_width_3308, 6, illegal_fp_variable_width_3308_arg5); + setRet(call_illegal_fp_variable_width_3308, 0, ret_val_illegal_fp_variable_width_3308); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78474,47 +78048,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3294; - x86::Gp ret_val_sew_3294 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3294, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_ww_3293; - auto fp_vector_imm_ww_3293_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_ww_3293_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_ww_3293_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_ww_3293_arg9 = gen_ext(cc, + InvokeNode* call_sew_3310; + x86::Gp ret_val_sew_3310 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3310, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_ww_3309; + auto fp_vector_imm_ww_3309_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_ww_3309_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_ww_3309_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_ww_3309_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_ww_3293_arg10 = rm; - auto fp_vector_imm_ww_3293_arg11 = ret_val_sew_3294; + auto fp_vector_imm_ww_3309_arg10 = rm; + auto fp_vector_imm_ww_3309_arg11 = ret_val_sew_3310; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_ww_3293, &fp_vector_imm_ww, FuncSignature::build()); - setArg(call_sew_3294, 0, reinterpret_cast(this)); - setRet(call_sew_3294, 0, ret_val_sew_3294); - setArg(call_fp_vector_imm_ww_3293, 0, V); - setArg(call_fp_vector_imm_ww_3293, 1, 54); - setArg(call_fp_vector_imm_ww_3293, 2, 5); - setArg(call_fp_vector_imm_ww_3293, 3, fp_vector_imm_ww_3293_arg3); - setArg(call_fp_vector_imm_ww_3293, 4, fp_vector_imm_ww_3293_arg4); - setArg(call_fp_vector_imm_ww_3293, 5, fp_vector_imm_ww_3293_arg5); - setArg(call_fp_vector_imm_ww_3293, 6, vm); - setArg(call_fp_vector_imm_ww_3293, 7, vd); - setArg(call_fp_vector_imm_ww_3293, 8, vs2); - setArg(call_fp_vector_imm_ww_3293, 9, fp_vector_imm_ww_3293_arg9); - setArg(call_fp_vector_imm_ww_3293, 10, fp_vector_imm_ww_3293_arg10); - setArg(call_fp_vector_imm_ww_3293, 11, fp_vector_imm_ww_3293_arg11); - InvokeNode* call_fget_flags_3295; - x86::Gp ret_val_fget_flags_3295 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3295, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3295; - setRet(call_fget_flags_3295, 0, ret_val_fget_flags_3295); + cc.invoke(&call_fp_vector_imm_ww_3309, &fp_vector_imm_ww, FuncSignature::build()); + setArg(call_sew_3310, 0, reinterpret_cast(this)); + setRet(call_sew_3310, 0, ret_val_sew_3310); + setArg(call_fp_vector_imm_ww_3309, 0, V); + setArg(call_fp_vector_imm_ww_3309, 1, 54); + setArg(call_fp_vector_imm_ww_3309, 2, 5); + setArg(call_fp_vector_imm_ww_3309, 3, fp_vector_imm_ww_3309_arg3); + setArg(call_fp_vector_imm_ww_3309, 4, fp_vector_imm_ww_3309_arg4); + setArg(call_fp_vector_imm_ww_3309, 5, fp_vector_imm_ww_3309_arg5); + setArg(call_fp_vector_imm_ww_3309, 6, vm); + setArg(call_fp_vector_imm_ww_3309, 7, vd); + setArg(call_fp_vector_imm_ww_3309, 8, vs2); + setArg(call_fp_vector_imm_ww_3309, 9, fp_vector_imm_ww_3309_arg9); + setArg(call_fp_vector_imm_ww_3309, 10, fp_vector_imm_ww_3309_arg10); + setArg(call_fp_vector_imm_ww_3309, 11, fp_vector_imm_ww_3309_arg11); + InvokeNode* call_fget_flags_3311; + x86::Gp ret_val_fget_flags_3311 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3311, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3311; + setRet(call_fget_flags_3311, 0, ret_val_fget_flags_3311); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3296 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3296, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3296, 64, false) - , traits::vstart); + auto tmp3312 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3312, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3312, traits::vstart); } cc.bind(label_merge); } @@ -78558,54 +78130,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3297; - x86::Gp ret_val_get_sew_pow_3297 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3297, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3298 = get_reg(cc, 8, false); - mov(cc, tmp3298, 1); + InvokeNode* call_get_sew_pow_3313; + x86::Gp ret_val_get_sew_pow_3313 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3313, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3314 = get_reg(cc, 8, false); + mov(cc, tmp3314, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3298, (ret_val_get_sew_pow_3297))), 8, false), ~ 1); - setArg(call_get_sew_pow_3297, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3297, 0, ret_val_get_sew_pow_3297); - InvokeNode* call_get_lmul_pow_3299; - x86::Gp ret_val_get_lmul_pow_3299 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3299, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3299; - setArg(call_get_lmul_pow_3299, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3299, 0, ret_val_get_lmul_pow_3299); + (gen_operation(cc, shl, tmp3314, (ret_val_get_sew_pow_3313))), 8, false), ~ 1); + setArg(call_get_sew_pow_3313, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3313, 0, ret_val_get_sew_pow_3313); + InvokeNode* call_get_lmul_pow_3315; + x86::Gp ret_val_get_lmul_pow_3315 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3315, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3315; + setArg(call_get_lmul_pow_3315, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3315, 0, ret_val_get_lmul_pow_3315); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3300; - auto illegal_fp_variable_width_3300_arg2 = SEW; - auto illegal_fp_variable_width_3300_arg3 = rm; - auto illegal_fp_variable_width_3300_arg4 = SEW_widen; - auto illegal_fp_variable_width_3300_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3300 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3300, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3301; - auto valid_reg_overlap_3301_arg2 = LMUL_pow; - auto valid_reg_overlap_3301_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3301 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3301, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3300, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3301)); - setArg(call_illegal_fp_variable_width_3300, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3300, 1, vd); - setArg(call_illegal_fp_variable_width_3300, 2, vm); - setArg(call_illegal_fp_variable_width_3300, 3, illegal_fp_variable_width_3300_arg2); - setArg(call_illegal_fp_variable_width_3300, 4, illegal_fp_variable_width_3300_arg3); - setArg(call_illegal_fp_variable_width_3300, 5, illegal_fp_variable_width_3300_arg4); - setArg(call_illegal_fp_variable_width_3300, 6, illegal_fp_variable_width_3300_arg5); - setRet(call_illegal_fp_variable_width_3300, 0, ret_val_illegal_fp_variable_width_3300); - setArg(call_valid_reg_overlap_3301, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3301, 1, vs1); - setArg(call_valid_reg_overlap_3301, 2, vd); - setArg(call_valid_reg_overlap_3301, 3, valid_reg_overlap_3301_arg2); - setArg(call_valid_reg_overlap_3301, 4, valid_reg_overlap_3301_arg3); - setRet(call_valid_reg_overlap_3301, 0, ret_val_valid_reg_overlap_3301); + InvokeNode* call_illegal_fp_variable_width_3316; + auto illegal_fp_variable_width_3316_arg2 = SEW; + auto illegal_fp_variable_width_3316_arg3 = rm; + auto illegal_fp_variable_width_3316_arg4 = SEW_widen; + auto illegal_fp_variable_width_3316_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3316 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3316, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3317; + auto valid_reg_overlap_3317_arg2 = LMUL_pow; + auto valid_reg_overlap_3317_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3317 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3317, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3316, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3317)); + setArg(call_illegal_fp_variable_width_3316, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3316, 1, vd); + setArg(call_illegal_fp_variable_width_3316, 2, vm); + setArg(call_illegal_fp_variable_width_3316, 3, illegal_fp_variable_width_3316_arg2); + setArg(call_illegal_fp_variable_width_3316, 4, illegal_fp_variable_width_3316_arg3); + setArg(call_illegal_fp_variable_width_3316, 5, illegal_fp_variable_width_3316_arg4); + setArg(call_illegal_fp_variable_width_3316, 6, illegal_fp_variable_width_3316_arg5); + setRet(call_illegal_fp_variable_width_3316, 0, ret_val_illegal_fp_variable_width_3316); + setArg(call_valid_reg_overlap_3317, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3317, 1, vs1); + setArg(call_valid_reg_overlap_3317, 2, vd); + setArg(call_valid_reg_overlap_3317, 3, valid_reg_overlap_3317_arg2); + setArg(call_valid_reg_overlap_3317, 4, valid_reg_overlap_3317_arg3); + setRet(call_valid_reg_overlap_3317, 0, ret_val_valid_reg_overlap_3317); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78621,45 +78193,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3303; - x86::Gp ret_val_sew_3303 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3303, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_ww_3302; - auto fp_vector_vector_ww_3302_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_ww_3302_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_ww_3302_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_ww_3302_arg10 = rm; - auto fp_vector_vector_ww_3302_arg11 = ret_val_sew_3303; + InvokeNode* call_sew_3319; + x86::Gp ret_val_sew_3319 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3319, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_ww_3318; + auto fp_vector_vector_ww_3318_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_ww_3318_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_ww_3318_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_ww_3318_arg10 = rm; + auto fp_vector_vector_ww_3318_arg11 = ret_val_sew_3319; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_ww_3302, &fp_vector_vector_ww, FuncSignature::build()); - setArg(call_sew_3303, 0, reinterpret_cast(this)); - setRet(call_sew_3303, 0, ret_val_sew_3303); - setArg(call_fp_vector_vector_ww_3302, 0, V); - setArg(call_fp_vector_vector_ww_3302, 1, 54); - setArg(call_fp_vector_vector_ww_3302, 2, 1); - setArg(call_fp_vector_vector_ww_3302, 3, fp_vector_vector_ww_3302_arg3); - setArg(call_fp_vector_vector_ww_3302, 4, fp_vector_vector_ww_3302_arg4); - setArg(call_fp_vector_vector_ww_3302, 5, fp_vector_vector_ww_3302_arg5); - setArg(call_fp_vector_vector_ww_3302, 6, vm); - setArg(call_fp_vector_vector_ww_3302, 7, vd); - setArg(call_fp_vector_vector_ww_3302, 8, vs2); - setArg(call_fp_vector_vector_ww_3302, 9, vs1); - setArg(call_fp_vector_vector_ww_3302, 10, fp_vector_vector_ww_3302_arg10); - setArg(call_fp_vector_vector_ww_3302, 11, fp_vector_vector_ww_3302_arg11); - InvokeNode* call_fget_flags_3304; - x86::Gp ret_val_fget_flags_3304 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3304, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3304; - setRet(call_fget_flags_3304, 0, ret_val_fget_flags_3304); + cc.invoke(&call_fp_vector_vector_ww_3318, &fp_vector_vector_ww, FuncSignature::build()); + setArg(call_sew_3319, 0, reinterpret_cast(this)); + setRet(call_sew_3319, 0, ret_val_sew_3319); + setArg(call_fp_vector_vector_ww_3318, 0, V); + setArg(call_fp_vector_vector_ww_3318, 1, 54); + setArg(call_fp_vector_vector_ww_3318, 2, 1); + setArg(call_fp_vector_vector_ww_3318, 3, fp_vector_vector_ww_3318_arg3); + setArg(call_fp_vector_vector_ww_3318, 4, fp_vector_vector_ww_3318_arg4); + setArg(call_fp_vector_vector_ww_3318, 5, fp_vector_vector_ww_3318_arg5); + setArg(call_fp_vector_vector_ww_3318, 6, vm); + setArg(call_fp_vector_vector_ww_3318, 7, vd); + setArg(call_fp_vector_vector_ww_3318, 8, vs2); + setArg(call_fp_vector_vector_ww_3318, 9, vs1); + setArg(call_fp_vector_vector_ww_3318, 10, fp_vector_vector_ww_3318_arg10); + setArg(call_fp_vector_vector_ww_3318, 11, fp_vector_vector_ww_3318_arg11); + InvokeNode* call_fget_flags_3320; + x86::Gp ret_val_fget_flags_3320 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3320, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3320; + setRet(call_fget_flags_3320, 0, ret_val_fget_flags_3320); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3305 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3305, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3305, 64, false) - , traits::vstart); + auto tmp3321 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3321, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3321, traits::vstart); } cc.bind(label_merge); } @@ -78703,30 +78273,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3306; - x86::Gp ret_val_get_sew_pow_3306 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3306, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3307 = get_reg(cc, 8, false); - mov(cc, tmp3307, 1); + InvokeNode* call_get_sew_pow_3322; + x86::Gp ret_val_get_sew_pow_3322 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3322, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3323 = get_reg(cc, 8, false); + mov(cc, tmp3323, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3307, (ret_val_get_sew_pow_3306))), 8, false), ~ 1); - setArg(call_get_sew_pow_3306, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3306, 0, ret_val_get_sew_pow_3306); + (gen_operation(cc, shl, tmp3323, (ret_val_get_sew_pow_3322))), 8, false), ~ 1); + setArg(call_get_sew_pow_3322, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3322, 0, ret_val_get_sew_pow_3322); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3308; - auto illegal_fp_normal_3308_arg2 = SEW; - auto illegal_fp_normal_3308_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3308 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3308, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3308; - setArg(call_illegal_fp_normal_3308, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3308, 1, vd); - setArg(call_illegal_fp_normal_3308, 2, vm); - setArg(call_illegal_fp_normal_3308, 3, illegal_fp_normal_3308_arg2); - setArg(call_illegal_fp_normal_3308, 4, illegal_fp_normal_3308_arg3); - setRet(call_illegal_fp_normal_3308, 0, ret_val_illegal_fp_normal_3308); + InvokeNode* call_illegal_fp_normal_3324; + auto illegal_fp_normal_3324_arg2 = SEW; + auto illegal_fp_normal_3324_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3324 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3324, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3324; + setArg(call_illegal_fp_normal_3324, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3324, 1, vd); + setArg(call_illegal_fp_normal_3324, 2, vm); + setArg(call_illegal_fp_normal_3324, 3, illegal_fp_normal_3324_arg2); + setArg(call_illegal_fp_normal_3324, 4, illegal_fp_normal_3324_arg3); + setRet(call_illegal_fp_normal_3324, 0, ret_val_illegal_fp_normal_3324); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78742,47 +78312,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3310; - x86::Gp ret_val_sew_3310 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3310, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3309; - auto fp_vector_imm_op_3309_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3309_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3309_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3309_arg9 = gen_ext(cc, + InvokeNode* call_sew_3326; + x86::Gp ret_val_sew_3326 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3326, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3325; + auto fp_vector_imm_op_3325_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3325_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3325_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3325_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3309_arg10 = rm; - auto fp_vector_imm_op_3309_arg11 = ret_val_sew_3310; + auto fp_vector_imm_op_3325_arg10 = rm; + auto fp_vector_imm_op_3325_arg11 = ret_val_sew_3326; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3309, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3310, 0, reinterpret_cast(this)); - setRet(call_sew_3310, 0, ret_val_sew_3310); - setArg(call_fp_vector_imm_op_3309, 0, V); - setArg(call_fp_vector_imm_op_3309, 1, 36); - setArg(call_fp_vector_imm_op_3309, 2, 5); - setArg(call_fp_vector_imm_op_3309, 3, fp_vector_imm_op_3309_arg3); - setArg(call_fp_vector_imm_op_3309, 4, fp_vector_imm_op_3309_arg4); - setArg(call_fp_vector_imm_op_3309, 5, fp_vector_imm_op_3309_arg5); - setArg(call_fp_vector_imm_op_3309, 6, vm); - setArg(call_fp_vector_imm_op_3309, 7, vd); - setArg(call_fp_vector_imm_op_3309, 8, vs2); - setArg(call_fp_vector_imm_op_3309, 9, fp_vector_imm_op_3309_arg9); - setArg(call_fp_vector_imm_op_3309, 10, fp_vector_imm_op_3309_arg10); - setArg(call_fp_vector_imm_op_3309, 11, fp_vector_imm_op_3309_arg11); - InvokeNode* call_fget_flags_3311; - x86::Gp ret_val_fget_flags_3311 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3311, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3311; - setRet(call_fget_flags_3311, 0, ret_val_fget_flags_3311); + cc.invoke(&call_fp_vector_imm_op_3325, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3326, 0, reinterpret_cast(this)); + setRet(call_sew_3326, 0, ret_val_sew_3326); + setArg(call_fp_vector_imm_op_3325, 0, V); + setArg(call_fp_vector_imm_op_3325, 1, 36); + setArg(call_fp_vector_imm_op_3325, 2, 5); + setArg(call_fp_vector_imm_op_3325, 3, fp_vector_imm_op_3325_arg3); + setArg(call_fp_vector_imm_op_3325, 4, fp_vector_imm_op_3325_arg4); + setArg(call_fp_vector_imm_op_3325, 5, fp_vector_imm_op_3325_arg5); + setArg(call_fp_vector_imm_op_3325, 6, vm); + setArg(call_fp_vector_imm_op_3325, 7, vd); + setArg(call_fp_vector_imm_op_3325, 8, vs2); + setArg(call_fp_vector_imm_op_3325, 9, fp_vector_imm_op_3325_arg9); + setArg(call_fp_vector_imm_op_3325, 10, fp_vector_imm_op_3325_arg10); + setArg(call_fp_vector_imm_op_3325, 11, fp_vector_imm_op_3325_arg11); + InvokeNode* call_fget_flags_3327; + x86::Gp ret_val_fget_flags_3327 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3327, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3327; + setRet(call_fget_flags_3327, 0, ret_val_fget_flags_3327); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3312 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3312, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3312, 64, false) - , traits::vstart); + auto tmp3328 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3328, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3328, traits::vstart); } cc.bind(label_merge); } @@ -78826,30 +78394,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3313; - x86::Gp ret_val_get_sew_pow_3313 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3313, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3314 = get_reg(cc, 8, false); - mov(cc, tmp3314, 1); + InvokeNode* call_get_sew_pow_3329; + x86::Gp ret_val_get_sew_pow_3329 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3329, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3330 = get_reg(cc, 8, false); + mov(cc, tmp3330, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3314, (ret_val_get_sew_pow_3313))), 8, false), ~ 1); - setArg(call_get_sew_pow_3313, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3313, 0, ret_val_get_sew_pow_3313); + (gen_operation(cc, shl, tmp3330, (ret_val_get_sew_pow_3329))), 8, false), ~ 1); + setArg(call_get_sew_pow_3329, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3329, 0, ret_val_get_sew_pow_3329); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3315; - auto illegal_fp_normal_3315_arg2 = SEW; - auto illegal_fp_normal_3315_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3315 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3315, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3315; - setArg(call_illegal_fp_normal_3315, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3315, 1, vd); - setArg(call_illegal_fp_normal_3315, 2, vm); - setArg(call_illegal_fp_normal_3315, 3, illegal_fp_normal_3315_arg2); - setArg(call_illegal_fp_normal_3315, 4, illegal_fp_normal_3315_arg3); - setRet(call_illegal_fp_normal_3315, 0, ret_val_illegal_fp_normal_3315); + InvokeNode* call_illegal_fp_normal_3331; + auto illegal_fp_normal_3331_arg2 = SEW; + auto illegal_fp_normal_3331_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3331 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3331, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3331; + setArg(call_illegal_fp_normal_3331, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3331, 1, vd); + setArg(call_illegal_fp_normal_3331, 2, vm); + setArg(call_illegal_fp_normal_3331, 3, illegal_fp_normal_3331_arg2); + setArg(call_illegal_fp_normal_3331, 4, illegal_fp_normal_3331_arg3); + setRet(call_illegal_fp_normal_3331, 0, ret_val_illegal_fp_normal_3331); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78865,45 +78433,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3317; - x86::Gp ret_val_sew_3317 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3317, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3316; - auto fp_vector_vector_op_3316_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3316_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3316_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3316_arg10 = rm; - auto fp_vector_vector_op_3316_arg11 = ret_val_sew_3317; + InvokeNode* call_sew_3333; + x86::Gp ret_val_sew_3333 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3333, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3332; + auto fp_vector_vector_op_3332_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3332_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3332_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3332_arg10 = rm; + auto fp_vector_vector_op_3332_arg11 = ret_val_sew_3333; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3316, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3317, 0, reinterpret_cast(this)); - setRet(call_sew_3317, 0, ret_val_sew_3317); - setArg(call_fp_vector_vector_op_3316, 0, V); - setArg(call_fp_vector_vector_op_3316, 1, 36); - setArg(call_fp_vector_vector_op_3316, 2, 1); - setArg(call_fp_vector_vector_op_3316, 3, fp_vector_vector_op_3316_arg3); - setArg(call_fp_vector_vector_op_3316, 4, fp_vector_vector_op_3316_arg4); - setArg(call_fp_vector_vector_op_3316, 5, fp_vector_vector_op_3316_arg5); - setArg(call_fp_vector_vector_op_3316, 6, vm); - setArg(call_fp_vector_vector_op_3316, 7, vd); - setArg(call_fp_vector_vector_op_3316, 8, vs2); - setArg(call_fp_vector_vector_op_3316, 9, vs1); - setArg(call_fp_vector_vector_op_3316, 10, fp_vector_vector_op_3316_arg10); - setArg(call_fp_vector_vector_op_3316, 11, fp_vector_vector_op_3316_arg11); - InvokeNode* call_fget_flags_3318; - x86::Gp ret_val_fget_flags_3318 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3318, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3318; - setRet(call_fget_flags_3318, 0, ret_val_fget_flags_3318); + cc.invoke(&call_fp_vector_vector_op_3332, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3333, 0, reinterpret_cast(this)); + setRet(call_sew_3333, 0, ret_val_sew_3333); + setArg(call_fp_vector_vector_op_3332, 0, V); + setArg(call_fp_vector_vector_op_3332, 1, 36); + setArg(call_fp_vector_vector_op_3332, 2, 1); + setArg(call_fp_vector_vector_op_3332, 3, fp_vector_vector_op_3332_arg3); + setArg(call_fp_vector_vector_op_3332, 4, fp_vector_vector_op_3332_arg4); + setArg(call_fp_vector_vector_op_3332, 5, fp_vector_vector_op_3332_arg5); + setArg(call_fp_vector_vector_op_3332, 6, vm); + setArg(call_fp_vector_vector_op_3332, 7, vd); + setArg(call_fp_vector_vector_op_3332, 8, vs2); + setArg(call_fp_vector_vector_op_3332, 9, vs1); + setArg(call_fp_vector_vector_op_3332, 10, fp_vector_vector_op_3332_arg10); + setArg(call_fp_vector_vector_op_3332, 11, fp_vector_vector_op_3332_arg11); + InvokeNode* call_fget_flags_3334; + x86::Gp ret_val_fget_flags_3334 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3334, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3334; + setRet(call_fget_flags_3334, 0, ret_val_fget_flags_3334); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3319 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3319, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3319, 64, false) - , traits::vstart); + auto tmp3335 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3335, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3335, traits::vstart); } cc.bind(label_merge); } @@ -78947,30 +78513,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3320; - x86::Gp ret_val_get_sew_pow_3320 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3320, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3321 = get_reg(cc, 8, false); - mov(cc, tmp3321, 1); + InvokeNode* call_get_sew_pow_3336; + x86::Gp ret_val_get_sew_pow_3336 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3336, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3337 = get_reg(cc, 8, false); + mov(cc, tmp3337, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3321, (ret_val_get_sew_pow_3320))), 8, false), ~ 1); - setArg(call_get_sew_pow_3320, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3320, 0, ret_val_get_sew_pow_3320); + (gen_operation(cc, shl, tmp3337, (ret_val_get_sew_pow_3336))), 8, false), ~ 1); + setArg(call_get_sew_pow_3336, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3336, 0, ret_val_get_sew_pow_3336); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3322; - auto illegal_fp_normal_3322_arg2 = SEW; - auto illegal_fp_normal_3322_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3322 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3322, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3322; - setArg(call_illegal_fp_normal_3322, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3322, 1, vd); - setArg(call_illegal_fp_normal_3322, 2, vm); - setArg(call_illegal_fp_normal_3322, 3, illegal_fp_normal_3322_arg2); - setArg(call_illegal_fp_normal_3322, 4, illegal_fp_normal_3322_arg3); - setRet(call_illegal_fp_normal_3322, 0, ret_val_illegal_fp_normal_3322); + InvokeNode* call_illegal_fp_normal_3338; + auto illegal_fp_normal_3338_arg2 = SEW; + auto illegal_fp_normal_3338_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3338 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3338, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3338; + setArg(call_illegal_fp_normal_3338, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3338, 1, vd); + setArg(call_illegal_fp_normal_3338, 2, vm); + setArg(call_illegal_fp_normal_3338, 3, illegal_fp_normal_3338_arg2); + setArg(call_illegal_fp_normal_3338, 4, illegal_fp_normal_3338_arg3); + setRet(call_illegal_fp_normal_3338, 0, ret_val_illegal_fp_normal_3338); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -78986,47 +78552,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3324; - x86::Gp ret_val_sew_3324 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3324, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3323; - auto fp_vector_imm_op_3323_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3323_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3323_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3323_arg9 = gen_ext(cc, + InvokeNode* call_sew_3340; + x86::Gp ret_val_sew_3340 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3340, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3339; + auto fp_vector_imm_op_3339_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3339_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3339_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3339_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3323_arg10 = rm; - auto fp_vector_imm_op_3323_arg11 = ret_val_sew_3324; + auto fp_vector_imm_op_3339_arg10 = rm; + auto fp_vector_imm_op_3339_arg11 = ret_val_sew_3340; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3323, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3324, 0, reinterpret_cast(this)); - setRet(call_sew_3324, 0, ret_val_sew_3324); - setArg(call_fp_vector_imm_op_3323, 0, V); - setArg(call_fp_vector_imm_op_3323, 1, 32); - setArg(call_fp_vector_imm_op_3323, 2, 5); - setArg(call_fp_vector_imm_op_3323, 3, fp_vector_imm_op_3323_arg3); - setArg(call_fp_vector_imm_op_3323, 4, fp_vector_imm_op_3323_arg4); - setArg(call_fp_vector_imm_op_3323, 5, fp_vector_imm_op_3323_arg5); - setArg(call_fp_vector_imm_op_3323, 6, vm); - setArg(call_fp_vector_imm_op_3323, 7, vd); - setArg(call_fp_vector_imm_op_3323, 8, vs2); - setArg(call_fp_vector_imm_op_3323, 9, fp_vector_imm_op_3323_arg9); - setArg(call_fp_vector_imm_op_3323, 10, fp_vector_imm_op_3323_arg10); - setArg(call_fp_vector_imm_op_3323, 11, fp_vector_imm_op_3323_arg11); - InvokeNode* call_fget_flags_3325; - x86::Gp ret_val_fget_flags_3325 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3325, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3325; - setRet(call_fget_flags_3325, 0, ret_val_fget_flags_3325); + cc.invoke(&call_fp_vector_imm_op_3339, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3340, 0, reinterpret_cast(this)); + setRet(call_sew_3340, 0, ret_val_sew_3340); + setArg(call_fp_vector_imm_op_3339, 0, V); + setArg(call_fp_vector_imm_op_3339, 1, 32); + setArg(call_fp_vector_imm_op_3339, 2, 5); + setArg(call_fp_vector_imm_op_3339, 3, fp_vector_imm_op_3339_arg3); + setArg(call_fp_vector_imm_op_3339, 4, fp_vector_imm_op_3339_arg4); + setArg(call_fp_vector_imm_op_3339, 5, fp_vector_imm_op_3339_arg5); + setArg(call_fp_vector_imm_op_3339, 6, vm); + setArg(call_fp_vector_imm_op_3339, 7, vd); + setArg(call_fp_vector_imm_op_3339, 8, vs2); + setArg(call_fp_vector_imm_op_3339, 9, fp_vector_imm_op_3339_arg9); + setArg(call_fp_vector_imm_op_3339, 10, fp_vector_imm_op_3339_arg10); + setArg(call_fp_vector_imm_op_3339, 11, fp_vector_imm_op_3339_arg11); + InvokeNode* call_fget_flags_3341; + x86::Gp ret_val_fget_flags_3341 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3341, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3341; + setRet(call_fget_flags_3341, 0, ret_val_fget_flags_3341); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3326 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3326, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3326, 64, false) - , traits::vstart); + auto tmp3342 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3342, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3342, traits::vstart); } cc.bind(label_merge); } @@ -79070,30 +78634,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3327; - x86::Gp ret_val_get_sew_pow_3327 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3327, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3328 = get_reg(cc, 8, false); - mov(cc, tmp3328, 1); + InvokeNode* call_get_sew_pow_3343; + x86::Gp ret_val_get_sew_pow_3343 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3343, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3344 = get_reg(cc, 8, false); + mov(cc, tmp3344, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3328, (ret_val_get_sew_pow_3327))), 8, false), ~ 1); - setArg(call_get_sew_pow_3327, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3327, 0, ret_val_get_sew_pow_3327); + (gen_operation(cc, shl, tmp3344, (ret_val_get_sew_pow_3343))), 8, false), ~ 1); + setArg(call_get_sew_pow_3343, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3343, 0, ret_val_get_sew_pow_3343); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3329; - auto illegal_fp_normal_3329_arg2 = SEW; - auto illegal_fp_normal_3329_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3329 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3329, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3329; - setArg(call_illegal_fp_normal_3329, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3329, 1, vd); - setArg(call_illegal_fp_normal_3329, 2, vm); - setArg(call_illegal_fp_normal_3329, 3, illegal_fp_normal_3329_arg2); - setArg(call_illegal_fp_normal_3329, 4, illegal_fp_normal_3329_arg3); - setRet(call_illegal_fp_normal_3329, 0, ret_val_illegal_fp_normal_3329); + InvokeNode* call_illegal_fp_normal_3345; + auto illegal_fp_normal_3345_arg2 = SEW; + auto illegal_fp_normal_3345_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3345 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3345, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3345; + setArg(call_illegal_fp_normal_3345, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3345, 1, vd); + setArg(call_illegal_fp_normal_3345, 2, vm); + setArg(call_illegal_fp_normal_3345, 3, illegal_fp_normal_3345_arg2); + setArg(call_illegal_fp_normal_3345, 4, illegal_fp_normal_3345_arg3); + setRet(call_illegal_fp_normal_3345, 0, ret_val_illegal_fp_normal_3345); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79109,45 +78673,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3331; - x86::Gp ret_val_sew_3331 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3331, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3330; - auto fp_vector_vector_op_3330_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3330_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3330_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3330_arg10 = rm; - auto fp_vector_vector_op_3330_arg11 = ret_val_sew_3331; + InvokeNode* call_sew_3347; + x86::Gp ret_val_sew_3347 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3347, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3346; + auto fp_vector_vector_op_3346_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3346_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3346_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3346_arg10 = rm; + auto fp_vector_vector_op_3346_arg11 = ret_val_sew_3347; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3330, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3331, 0, reinterpret_cast(this)); - setRet(call_sew_3331, 0, ret_val_sew_3331); - setArg(call_fp_vector_vector_op_3330, 0, V); - setArg(call_fp_vector_vector_op_3330, 1, 32); - setArg(call_fp_vector_vector_op_3330, 2, 1); - setArg(call_fp_vector_vector_op_3330, 3, fp_vector_vector_op_3330_arg3); - setArg(call_fp_vector_vector_op_3330, 4, fp_vector_vector_op_3330_arg4); - setArg(call_fp_vector_vector_op_3330, 5, fp_vector_vector_op_3330_arg5); - setArg(call_fp_vector_vector_op_3330, 6, vm); - setArg(call_fp_vector_vector_op_3330, 7, vd); - setArg(call_fp_vector_vector_op_3330, 8, vs2); - setArg(call_fp_vector_vector_op_3330, 9, vs1); - setArg(call_fp_vector_vector_op_3330, 10, fp_vector_vector_op_3330_arg10); - setArg(call_fp_vector_vector_op_3330, 11, fp_vector_vector_op_3330_arg11); - InvokeNode* call_fget_flags_3332; - x86::Gp ret_val_fget_flags_3332 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3332, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3332; - setRet(call_fget_flags_3332, 0, ret_val_fget_flags_3332); + cc.invoke(&call_fp_vector_vector_op_3346, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3347, 0, reinterpret_cast(this)); + setRet(call_sew_3347, 0, ret_val_sew_3347); + setArg(call_fp_vector_vector_op_3346, 0, V); + setArg(call_fp_vector_vector_op_3346, 1, 32); + setArg(call_fp_vector_vector_op_3346, 2, 1); + setArg(call_fp_vector_vector_op_3346, 3, fp_vector_vector_op_3346_arg3); + setArg(call_fp_vector_vector_op_3346, 4, fp_vector_vector_op_3346_arg4); + setArg(call_fp_vector_vector_op_3346, 5, fp_vector_vector_op_3346_arg5); + setArg(call_fp_vector_vector_op_3346, 6, vm); + setArg(call_fp_vector_vector_op_3346, 7, vd); + setArg(call_fp_vector_vector_op_3346, 8, vs2); + setArg(call_fp_vector_vector_op_3346, 9, vs1); + setArg(call_fp_vector_vector_op_3346, 10, fp_vector_vector_op_3346_arg10); + setArg(call_fp_vector_vector_op_3346, 11, fp_vector_vector_op_3346_arg11); + InvokeNode* call_fget_flags_3348; + x86::Gp ret_val_fget_flags_3348 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3348, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3348; + setRet(call_fget_flags_3348, 0, ret_val_fget_flags_3348); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3333 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3333, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3333, 64, false) - , traits::vstart); + auto tmp3349 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3349, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3349, traits::vstart); } cc.bind(label_merge); } @@ -79191,30 +78753,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3334; - x86::Gp ret_val_get_sew_pow_3334 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3334, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3335 = get_reg(cc, 8, false); - mov(cc, tmp3335, 1); + InvokeNode* call_get_sew_pow_3350; + x86::Gp ret_val_get_sew_pow_3350 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3350, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3351 = get_reg(cc, 8, false); + mov(cc, tmp3351, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3335, (ret_val_get_sew_pow_3334))), 8, false), ~ 1); - setArg(call_get_sew_pow_3334, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3334, 0, ret_val_get_sew_pow_3334); + (gen_operation(cc, shl, tmp3351, (ret_val_get_sew_pow_3350))), 8, false), ~ 1); + setArg(call_get_sew_pow_3350, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3350, 0, ret_val_get_sew_pow_3350); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3336; - auto illegal_fp_normal_3336_arg2 = SEW; - auto illegal_fp_normal_3336_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3336 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3336, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3336; - setArg(call_illegal_fp_normal_3336, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3336, 1, vd); - setArg(call_illegal_fp_normal_3336, 2, vm); - setArg(call_illegal_fp_normal_3336, 3, illegal_fp_normal_3336_arg2); - setArg(call_illegal_fp_normal_3336, 4, illegal_fp_normal_3336_arg3); - setRet(call_illegal_fp_normal_3336, 0, ret_val_illegal_fp_normal_3336); + InvokeNode* call_illegal_fp_normal_3352; + auto illegal_fp_normal_3352_arg2 = SEW; + auto illegal_fp_normal_3352_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3352 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3352, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3352; + setArg(call_illegal_fp_normal_3352, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3352, 1, vd); + setArg(call_illegal_fp_normal_3352, 2, vm); + setArg(call_illegal_fp_normal_3352, 3, illegal_fp_normal_3352_arg2); + setArg(call_illegal_fp_normal_3352, 4, illegal_fp_normal_3352_arg3); + setRet(call_illegal_fp_normal_3352, 0, ret_val_illegal_fp_normal_3352); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79230,47 +78792,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3338; - x86::Gp ret_val_sew_3338 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3338, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3337; - auto fp_vector_imm_op_3337_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3337_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3337_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3337_arg9 = gen_ext(cc, + InvokeNode* call_sew_3354; + x86::Gp ret_val_sew_3354 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3354, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3353; + auto fp_vector_imm_op_3353_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3353_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3353_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3353_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3337_arg10 = rm; - auto fp_vector_imm_op_3337_arg11 = ret_val_sew_3338; + auto fp_vector_imm_op_3353_arg10 = rm; + auto fp_vector_imm_op_3353_arg11 = ret_val_sew_3354; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3337, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3338, 0, reinterpret_cast(this)); - setRet(call_sew_3338, 0, ret_val_sew_3338); - setArg(call_fp_vector_imm_op_3337, 0, V); - setArg(call_fp_vector_imm_op_3337, 1, 33); - setArg(call_fp_vector_imm_op_3337, 2, 5); - setArg(call_fp_vector_imm_op_3337, 3, fp_vector_imm_op_3337_arg3); - setArg(call_fp_vector_imm_op_3337, 4, fp_vector_imm_op_3337_arg4); - setArg(call_fp_vector_imm_op_3337, 5, fp_vector_imm_op_3337_arg5); - setArg(call_fp_vector_imm_op_3337, 6, vm); - setArg(call_fp_vector_imm_op_3337, 7, vd); - setArg(call_fp_vector_imm_op_3337, 8, vs2); - setArg(call_fp_vector_imm_op_3337, 9, fp_vector_imm_op_3337_arg9); - setArg(call_fp_vector_imm_op_3337, 10, fp_vector_imm_op_3337_arg10); - setArg(call_fp_vector_imm_op_3337, 11, fp_vector_imm_op_3337_arg11); - InvokeNode* call_fget_flags_3339; - x86::Gp ret_val_fget_flags_3339 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3339, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3339; - setRet(call_fget_flags_3339, 0, ret_val_fget_flags_3339); + cc.invoke(&call_fp_vector_imm_op_3353, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3354, 0, reinterpret_cast(this)); + setRet(call_sew_3354, 0, ret_val_sew_3354); + setArg(call_fp_vector_imm_op_3353, 0, V); + setArg(call_fp_vector_imm_op_3353, 1, 33); + setArg(call_fp_vector_imm_op_3353, 2, 5); + setArg(call_fp_vector_imm_op_3353, 3, fp_vector_imm_op_3353_arg3); + setArg(call_fp_vector_imm_op_3353, 4, fp_vector_imm_op_3353_arg4); + setArg(call_fp_vector_imm_op_3353, 5, fp_vector_imm_op_3353_arg5); + setArg(call_fp_vector_imm_op_3353, 6, vm); + setArg(call_fp_vector_imm_op_3353, 7, vd); + setArg(call_fp_vector_imm_op_3353, 8, vs2); + setArg(call_fp_vector_imm_op_3353, 9, fp_vector_imm_op_3353_arg9); + setArg(call_fp_vector_imm_op_3353, 10, fp_vector_imm_op_3353_arg10); + setArg(call_fp_vector_imm_op_3353, 11, fp_vector_imm_op_3353_arg11); + InvokeNode* call_fget_flags_3355; + x86::Gp ret_val_fget_flags_3355 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3355, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3355; + setRet(call_fget_flags_3355, 0, ret_val_fget_flags_3355); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3340 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3340, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3340, 64, false) - , traits::vstart); + auto tmp3356 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3356, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3356, traits::vstart); } cc.bind(label_merge); } @@ -79314,54 +78874,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3341; - x86::Gp ret_val_get_sew_pow_3341 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3341, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3342 = get_reg(cc, 8, false); - mov(cc, tmp3342, 1); + InvokeNode* call_get_sew_pow_3357; + x86::Gp ret_val_get_sew_pow_3357 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3357, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3358 = get_reg(cc, 8, false); + mov(cc, tmp3358, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3342, (ret_val_get_sew_pow_3341))), 8, false), ~ 1); - setArg(call_get_sew_pow_3341, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3341, 0, ret_val_get_sew_pow_3341); - InvokeNode* call_get_lmul_pow_3343; - x86::Gp ret_val_get_lmul_pow_3343 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3343, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3343; - setArg(call_get_lmul_pow_3343, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3343, 0, ret_val_get_lmul_pow_3343); + (gen_operation(cc, shl, tmp3358, (ret_val_get_sew_pow_3357))), 8, false), ~ 1); + setArg(call_get_sew_pow_3357, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3357, 0, ret_val_get_sew_pow_3357); + InvokeNode* call_get_lmul_pow_3359; + x86::Gp ret_val_get_lmul_pow_3359 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3359, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3359; + setArg(call_get_lmul_pow_3359, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3359, 0, ret_val_get_lmul_pow_3359); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3344; - auto illegal_fp_variable_width_3344_arg2 = SEW; - auto illegal_fp_variable_width_3344_arg3 = rm; - auto illegal_fp_variable_width_3344_arg4 = SEW_widen; - auto illegal_fp_variable_width_3344_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3344 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3344, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3345; - auto valid_reg_overlap_3345_arg2 = LMUL_pow; - auto valid_reg_overlap_3345_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3345 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3345, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3344, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3345)); - setArg(call_illegal_fp_variable_width_3344, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3344, 1, vd); - setArg(call_illegal_fp_variable_width_3344, 2, vm); - setArg(call_illegal_fp_variable_width_3344, 3, illegal_fp_variable_width_3344_arg2); - setArg(call_illegal_fp_variable_width_3344, 4, illegal_fp_variable_width_3344_arg3); - setArg(call_illegal_fp_variable_width_3344, 5, illegal_fp_variable_width_3344_arg4); - setArg(call_illegal_fp_variable_width_3344, 6, illegal_fp_variable_width_3344_arg5); - setRet(call_illegal_fp_variable_width_3344, 0, ret_val_illegal_fp_variable_width_3344); - setArg(call_valid_reg_overlap_3345, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3345, 1, vs2); - setArg(call_valid_reg_overlap_3345, 2, vd); - setArg(call_valid_reg_overlap_3345, 3, valid_reg_overlap_3345_arg2); - setArg(call_valid_reg_overlap_3345, 4, valid_reg_overlap_3345_arg3); - setRet(call_valid_reg_overlap_3345, 0, ret_val_valid_reg_overlap_3345); + InvokeNode* call_illegal_fp_variable_width_3360; + auto illegal_fp_variable_width_3360_arg2 = SEW; + auto illegal_fp_variable_width_3360_arg3 = rm; + auto illegal_fp_variable_width_3360_arg4 = SEW_widen; + auto illegal_fp_variable_width_3360_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3360 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3360, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3361; + auto valid_reg_overlap_3361_arg2 = LMUL_pow; + auto valid_reg_overlap_3361_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3361 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3361, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3360, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3361)); + setArg(call_illegal_fp_variable_width_3360, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3360, 1, vd); + setArg(call_illegal_fp_variable_width_3360, 2, vm); + setArg(call_illegal_fp_variable_width_3360, 3, illegal_fp_variable_width_3360_arg2); + setArg(call_illegal_fp_variable_width_3360, 4, illegal_fp_variable_width_3360_arg3); + setArg(call_illegal_fp_variable_width_3360, 5, illegal_fp_variable_width_3360_arg4); + setArg(call_illegal_fp_variable_width_3360, 6, illegal_fp_variable_width_3360_arg5); + setRet(call_illegal_fp_variable_width_3360, 0, ret_val_illegal_fp_variable_width_3360); + setArg(call_valid_reg_overlap_3361, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3361, 1, vs2); + setArg(call_valid_reg_overlap_3361, 2, vd); + setArg(call_valid_reg_overlap_3361, 3, valid_reg_overlap_3361_arg2); + setArg(call_valid_reg_overlap_3361, 4, valid_reg_overlap_3361_arg3); + setRet(call_valid_reg_overlap_3361, 0, ret_val_valid_reg_overlap_3361); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79377,47 +78937,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3347; - x86::Gp ret_val_sew_3347 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3347, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3346; - auto fp_vector_imm_wv_3346_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3346_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3346_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3346_arg9 = gen_ext(cc, + InvokeNode* call_sew_3363; + x86::Gp ret_val_sew_3363 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3363, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3362; + auto fp_vector_imm_wv_3362_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3362_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3362_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3362_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_wv_3346_arg10 = rm; - auto fp_vector_imm_wv_3346_arg11 = ret_val_sew_3347; + auto fp_vector_imm_wv_3362_arg10 = rm; + auto fp_vector_imm_wv_3362_arg11 = ret_val_sew_3363; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3346, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3347, 0, reinterpret_cast(this)); - setRet(call_sew_3347, 0, ret_val_sew_3347); - setArg(call_fp_vector_imm_wv_3346, 0, V); - setArg(call_fp_vector_imm_wv_3346, 1, 56); - setArg(call_fp_vector_imm_wv_3346, 2, 5); - setArg(call_fp_vector_imm_wv_3346, 3, fp_vector_imm_wv_3346_arg3); - setArg(call_fp_vector_imm_wv_3346, 4, fp_vector_imm_wv_3346_arg4); - setArg(call_fp_vector_imm_wv_3346, 5, fp_vector_imm_wv_3346_arg5); - setArg(call_fp_vector_imm_wv_3346, 6, vm); - setArg(call_fp_vector_imm_wv_3346, 7, vd); - setArg(call_fp_vector_imm_wv_3346, 8, vs2); - setArg(call_fp_vector_imm_wv_3346, 9, fp_vector_imm_wv_3346_arg9); - setArg(call_fp_vector_imm_wv_3346, 10, fp_vector_imm_wv_3346_arg10); - setArg(call_fp_vector_imm_wv_3346, 11, fp_vector_imm_wv_3346_arg11); - InvokeNode* call_fget_flags_3348; - x86::Gp ret_val_fget_flags_3348 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3348, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3348; - setRet(call_fget_flags_3348, 0, ret_val_fget_flags_3348); + cc.invoke(&call_fp_vector_imm_wv_3362, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3363, 0, reinterpret_cast(this)); + setRet(call_sew_3363, 0, ret_val_sew_3363); + setArg(call_fp_vector_imm_wv_3362, 0, V); + setArg(call_fp_vector_imm_wv_3362, 1, 56); + setArg(call_fp_vector_imm_wv_3362, 2, 5); + setArg(call_fp_vector_imm_wv_3362, 3, fp_vector_imm_wv_3362_arg3); + setArg(call_fp_vector_imm_wv_3362, 4, fp_vector_imm_wv_3362_arg4); + setArg(call_fp_vector_imm_wv_3362, 5, fp_vector_imm_wv_3362_arg5); + setArg(call_fp_vector_imm_wv_3362, 6, vm); + setArg(call_fp_vector_imm_wv_3362, 7, vd); + setArg(call_fp_vector_imm_wv_3362, 8, vs2); + setArg(call_fp_vector_imm_wv_3362, 9, fp_vector_imm_wv_3362_arg9); + setArg(call_fp_vector_imm_wv_3362, 10, fp_vector_imm_wv_3362_arg10); + setArg(call_fp_vector_imm_wv_3362, 11, fp_vector_imm_wv_3362_arg11); + InvokeNode* call_fget_flags_3364; + x86::Gp ret_val_fget_flags_3364 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3364, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3364; + setRet(call_fget_flags_3364, 0, ret_val_fget_flags_3364); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3349 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3349, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3349, 64, false) - , traits::vstart); + auto tmp3365 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3365, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3365, traits::vstart); } cc.bind(label_merge); } @@ -79461,65 +79019,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3350; - x86::Gp ret_val_get_sew_pow_3350 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3350, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3351 = get_reg(cc, 8, false); - mov(cc, tmp3351, 1); + InvokeNode* call_get_sew_pow_3366; + x86::Gp ret_val_get_sew_pow_3366 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3366, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3367 = get_reg(cc, 8, false); + mov(cc, tmp3367, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3351, (ret_val_get_sew_pow_3350))), 8, false), ~ 1); - setArg(call_get_sew_pow_3350, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3350, 0, ret_val_get_sew_pow_3350); - InvokeNode* call_get_lmul_pow_3352; - x86::Gp ret_val_get_lmul_pow_3352 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3352, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3352; - setArg(call_get_lmul_pow_3352, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3352, 0, ret_val_get_lmul_pow_3352); + (gen_operation(cc, shl, tmp3367, (ret_val_get_sew_pow_3366))), 8, false), ~ 1); + setArg(call_get_sew_pow_3366, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3366, 0, ret_val_get_sew_pow_3366); + InvokeNode* call_get_lmul_pow_3368; + x86::Gp ret_val_get_lmul_pow_3368 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3368, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3368; + setArg(call_get_lmul_pow_3368, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3368, 0, ret_val_get_lmul_pow_3368); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3353; - auto illegal_fp_variable_width_3353_arg2 = SEW; - auto illegal_fp_variable_width_3353_arg3 = rm; - auto illegal_fp_variable_width_3353_arg4 = SEW_widen; - auto illegal_fp_variable_width_3353_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3353 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3353, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3354; - auto valid_reg_overlap_3354_arg2 = LMUL_pow; - auto valid_reg_overlap_3354_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3354 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3354, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3355; - auto valid_reg_overlap_3355_arg2 = LMUL_pow; - auto valid_reg_overlap_3355_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3355 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3355, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3353, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3354)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3355)); - setArg(call_illegal_fp_variable_width_3353, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3353, 1, vd); - setArg(call_illegal_fp_variable_width_3353, 2, vm); - setArg(call_illegal_fp_variable_width_3353, 3, illegal_fp_variable_width_3353_arg2); - setArg(call_illegal_fp_variable_width_3353, 4, illegal_fp_variable_width_3353_arg3); - setArg(call_illegal_fp_variable_width_3353, 5, illegal_fp_variable_width_3353_arg4); - setArg(call_illegal_fp_variable_width_3353, 6, illegal_fp_variable_width_3353_arg5); - setRet(call_illegal_fp_variable_width_3353, 0, ret_val_illegal_fp_variable_width_3353); - setArg(call_valid_reg_overlap_3354, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3354, 1, vs1); - setArg(call_valid_reg_overlap_3354, 2, vd); - setArg(call_valid_reg_overlap_3354, 3, valid_reg_overlap_3354_arg2); - setArg(call_valid_reg_overlap_3354, 4, valid_reg_overlap_3354_arg3); - setRet(call_valid_reg_overlap_3354, 0, ret_val_valid_reg_overlap_3354); - setArg(call_valid_reg_overlap_3355, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3355, 1, vs2); - setArg(call_valid_reg_overlap_3355, 2, vd); - setArg(call_valid_reg_overlap_3355, 3, valid_reg_overlap_3355_arg2); - setArg(call_valid_reg_overlap_3355, 4, valid_reg_overlap_3355_arg3); - setRet(call_valid_reg_overlap_3355, 0, ret_val_valid_reg_overlap_3355); + InvokeNode* call_illegal_fp_variable_width_3369; + auto illegal_fp_variable_width_3369_arg2 = SEW; + auto illegal_fp_variable_width_3369_arg3 = rm; + auto illegal_fp_variable_width_3369_arg4 = SEW_widen; + auto illegal_fp_variable_width_3369_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3369 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3369, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3370; + auto valid_reg_overlap_3370_arg2 = LMUL_pow; + auto valid_reg_overlap_3370_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3370 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3370, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3371; + auto valid_reg_overlap_3371_arg2 = LMUL_pow; + auto valid_reg_overlap_3371_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3371 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3371, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3369, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3370)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3371)); + setArg(call_illegal_fp_variable_width_3369, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3369, 1, vd); + setArg(call_illegal_fp_variable_width_3369, 2, vm); + setArg(call_illegal_fp_variable_width_3369, 3, illegal_fp_variable_width_3369_arg2); + setArg(call_illegal_fp_variable_width_3369, 4, illegal_fp_variable_width_3369_arg3); + setArg(call_illegal_fp_variable_width_3369, 5, illegal_fp_variable_width_3369_arg4); + setArg(call_illegal_fp_variable_width_3369, 6, illegal_fp_variable_width_3369_arg5); + setRet(call_illegal_fp_variable_width_3369, 0, ret_val_illegal_fp_variable_width_3369); + setArg(call_valid_reg_overlap_3370, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3370, 1, vs1); + setArg(call_valid_reg_overlap_3370, 2, vd); + setArg(call_valid_reg_overlap_3370, 3, valid_reg_overlap_3370_arg2); + setArg(call_valid_reg_overlap_3370, 4, valid_reg_overlap_3370_arg3); + setRet(call_valid_reg_overlap_3370, 0, ret_val_valid_reg_overlap_3370); + setArg(call_valid_reg_overlap_3371, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3371, 1, vs2); + setArg(call_valid_reg_overlap_3371, 2, vd); + setArg(call_valid_reg_overlap_3371, 3, valid_reg_overlap_3371_arg2); + setArg(call_valid_reg_overlap_3371, 4, valid_reg_overlap_3371_arg3); + setRet(call_valid_reg_overlap_3371, 0, ret_val_valid_reg_overlap_3371); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79535,45 +79093,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3357; - x86::Gp ret_val_sew_3357 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3357, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3356; - auto fp_vector_vector_wv_3356_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3356_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3356_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3356_arg10 = rm; - auto fp_vector_vector_wv_3356_arg11 = ret_val_sew_3357; + InvokeNode* call_sew_3373; + x86::Gp ret_val_sew_3373 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3373, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3372; + auto fp_vector_vector_wv_3372_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3372_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3372_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3372_arg10 = rm; + auto fp_vector_vector_wv_3372_arg11 = ret_val_sew_3373; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3356, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3357, 0, reinterpret_cast(this)); - setRet(call_sew_3357, 0, ret_val_sew_3357); - setArg(call_fp_vector_vector_wv_3356, 0, V); - setArg(call_fp_vector_vector_wv_3356, 1, 56); - setArg(call_fp_vector_vector_wv_3356, 2, 1); - setArg(call_fp_vector_vector_wv_3356, 3, fp_vector_vector_wv_3356_arg3); - setArg(call_fp_vector_vector_wv_3356, 4, fp_vector_vector_wv_3356_arg4); - setArg(call_fp_vector_vector_wv_3356, 5, fp_vector_vector_wv_3356_arg5); - setArg(call_fp_vector_vector_wv_3356, 6, vm); - setArg(call_fp_vector_vector_wv_3356, 7, vd); - setArg(call_fp_vector_vector_wv_3356, 8, vs2); - setArg(call_fp_vector_vector_wv_3356, 9, vs1); - setArg(call_fp_vector_vector_wv_3356, 10, fp_vector_vector_wv_3356_arg10); - setArg(call_fp_vector_vector_wv_3356, 11, fp_vector_vector_wv_3356_arg11); - InvokeNode* call_fget_flags_3358; - x86::Gp ret_val_fget_flags_3358 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3358, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3358; - setRet(call_fget_flags_3358, 0, ret_val_fget_flags_3358); + cc.invoke(&call_fp_vector_vector_wv_3372, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3373, 0, reinterpret_cast(this)); + setRet(call_sew_3373, 0, ret_val_sew_3373); + setArg(call_fp_vector_vector_wv_3372, 0, V); + setArg(call_fp_vector_vector_wv_3372, 1, 56); + setArg(call_fp_vector_vector_wv_3372, 2, 1); + setArg(call_fp_vector_vector_wv_3372, 3, fp_vector_vector_wv_3372_arg3); + setArg(call_fp_vector_vector_wv_3372, 4, fp_vector_vector_wv_3372_arg4); + setArg(call_fp_vector_vector_wv_3372, 5, fp_vector_vector_wv_3372_arg5); + setArg(call_fp_vector_vector_wv_3372, 6, vm); + setArg(call_fp_vector_vector_wv_3372, 7, vd); + setArg(call_fp_vector_vector_wv_3372, 8, vs2); + setArg(call_fp_vector_vector_wv_3372, 9, vs1); + setArg(call_fp_vector_vector_wv_3372, 10, fp_vector_vector_wv_3372_arg10); + setArg(call_fp_vector_vector_wv_3372, 11, fp_vector_vector_wv_3372_arg11); + InvokeNode* call_fget_flags_3374; + x86::Gp ret_val_fget_flags_3374 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3374, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3374; + setRet(call_fget_flags_3374, 0, ret_val_fget_flags_3374); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3359 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3359, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3359, 64, false) - , traits::vstart); + auto tmp3375 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3375, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3375, traits::vstart); } cc.bind(label_merge); } @@ -79617,30 +79173,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3360; - x86::Gp ret_val_get_sew_pow_3360 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3360, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3361 = get_reg(cc, 8, false); - mov(cc, tmp3361, 1); + InvokeNode* call_get_sew_pow_3376; + x86::Gp ret_val_get_sew_pow_3376 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3376, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3377 = get_reg(cc, 8, false); + mov(cc, tmp3377, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3361, (ret_val_get_sew_pow_3360))), 8, false), ~ 1); - setArg(call_get_sew_pow_3360, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3360, 0, ret_val_get_sew_pow_3360); + (gen_operation(cc, shl, tmp3377, (ret_val_get_sew_pow_3376))), 8, false), ~ 1); + setArg(call_get_sew_pow_3376, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3376, 0, ret_val_get_sew_pow_3376); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3362; - auto illegal_fp_normal_3362_arg2 = SEW; - auto illegal_fp_normal_3362_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3362 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3362, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3362; - setArg(call_illegal_fp_normal_3362, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3362, 1, vd); - setArg(call_illegal_fp_normal_3362, 2, vm); - setArg(call_illegal_fp_normal_3362, 3, illegal_fp_normal_3362_arg2); - setArg(call_illegal_fp_normal_3362, 4, illegal_fp_normal_3362_arg3); - setRet(call_illegal_fp_normal_3362, 0, ret_val_illegal_fp_normal_3362); + InvokeNode* call_illegal_fp_normal_3378; + auto illegal_fp_normal_3378_arg2 = SEW; + auto illegal_fp_normal_3378_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3378 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3378, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3378; + setArg(call_illegal_fp_normal_3378, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3378, 1, vd); + setArg(call_illegal_fp_normal_3378, 2, vm); + setArg(call_illegal_fp_normal_3378, 3, illegal_fp_normal_3378_arg2); + setArg(call_illegal_fp_normal_3378, 4, illegal_fp_normal_3378_arg3); + setRet(call_illegal_fp_normal_3378, 0, ret_val_illegal_fp_normal_3378); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79656,47 +79212,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3364; - x86::Gp ret_val_sew_3364 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3364, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3363; - auto fp_vector_imm_op_3363_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3363_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3363_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3363_arg9 = gen_ext(cc, + InvokeNode* call_sew_3380; + x86::Gp ret_val_sew_3380 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3380, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3379; + auto fp_vector_imm_op_3379_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3379_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3379_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3379_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3363_arg10 = rm; - auto fp_vector_imm_op_3363_arg11 = ret_val_sew_3364; + auto fp_vector_imm_op_3379_arg10 = rm; + auto fp_vector_imm_op_3379_arg11 = ret_val_sew_3380; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3363, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3364, 0, reinterpret_cast(this)); - setRet(call_sew_3364, 0, ret_val_sew_3364); - setArg(call_fp_vector_imm_op_3363, 0, V); - setArg(call_fp_vector_imm_op_3363, 1, 44); - setArg(call_fp_vector_imm_op_3363, 2, 5); - setArg(call_fp_vector_imm_op_3363, 3, fp_vector_imm_op_3363_arg3); - setArg(call_fp_vector_imm_op_3363, 4, fp_vector_imm_op_3363_arg4); - setArg(call_fp_vector_imm_op_3363, 5, fp_vector_imm_op_3363_arg5); - setArg(call_fp_vector_imm_op_3363, 6, vm); - setArg(call_fp_vector_imm_op_3363, 7, vd); - setArg(call_fp_vector_imm_op_3363, 8, vs2); - setArg(call_fp_vector_imm_op_3363, 9, fp_vector_imm_op_3363_arg9); - setArg(call_fp_vector_imm_op_3363, 10, fp_vector_imm_op_3363_arg10); - setArg(call_fp_vector_imm_op_3363, 11, fp_vector_imm_op_3363_arg11); - InvokeNode* call_fget_flags_3365; - x86::Gp ret_val_fget_flags_3365 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3365, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3365; - setRet(call_fget_flags_3365, 0, ret_val_fget_flags_3365); + cc.invoke(&call_fp_vector_imm_op_3379, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3380, 0, reinterpret_cast(this)); + setRet(call_sew_3380, 0, ret_val_sew_3380); + setArg(call_fp_vector_imm_op_3379, 0, V); + setArg(call_fp_vector_imm_op_3379, 1, 44); + setArg(call_fp_vector_imm_op_3379, 2, 5); + setArg(call_fp_vector_imm_op_3379, 3, fp_vector_imm_op_3379_arg3); + setArg(call_fp_vector_imm_op_3379, 4, fp_vector_imm_op_3379_arg4); + setArg(call_fp_vector_imm_op_3379, 5, fp_vector_imm_op_3379_arg5); + setArg(call_fp_vector_imm_op_3379, 6, vm); + setArg(call_fp_vector_imm_op_3379, 7, vd); + setArg(call_fp_vector_imm_op_3379, 8, vs2); + setArg(call_fp_vector_imm_op_3379, 9, fp_vector_imm_op_3379_arg9); + setArg(call_fp_vector_imm_op_3379, 10, fp_vector_imm_op_3379_arg10); + setArg(call_fp_vector_imm_op_3379, 11, fp_vector_imm_op_3379_arg11); + InvokeNode* call_fget_flags_3381; + x86::Gp ret_val_fget_flags_3381 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3381, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3381; + setRet(call_fget_flags_3381, 0, ret_val_fget_flags_3381); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3366 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3366, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3366, 64, false) - , traits::vstart); + auto tmp3382 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3382, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3382, traits::vstart); } cc.bind(label_merge); } @@ -79740,30 +79294,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3367; - x86::Gp ret_val_get_sew_pow_3367 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3367, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3368 = get_reg(cc, 8, false); - mov(cc, tmp3368, 1); + InvokeNode* call_get_sew_pow_3383; + x86::Gp ret_val_get_sew_pow_3383 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3383, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3384 = get_reg(cc, 8, false); + mov(cc, tmp3384, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3368, (ret_val_get_sew_pow_3367))), 8, false), ~ 1); - setArg(call_get_sew_pow_3367, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3367, 0, ret_val_get_sew_pow_3367); + (gen_operation(cc, shl, tmp3384, (ret_val_get_sew_pow_3383))), 8, false), ~ 1); + setArg(call_get_sew_pow_3383, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3383, 0, ret_val_get_sew_pow_3383); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3369; - auto illegal_fp_normal_3369_arg2 = SEW; - auto illegal_fp_normal_3369_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3369 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3369, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3369; - setArg(call_illegal_fp_normal_3369, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3369, 1, vd); - setArg(call_illegal_fp_normal_3369, 2, vm); - setArg(call_illegal_fp_normal_3369, 3, illegal_fp_normal_3369_arg2); - setArg(call_illegal_fp_normal_3369, 4, illegal_fp_normal_3369_arg3); - setRet(call_illegal_fp_normal_3369, 0, ret_val_illegal_fp_normal_3369); + InvokeNode* call_illegal_fp_normal_3385; + auto illegal_fp_normal_3385_arg2 = SEW; + auto illegal_fp_normal_3385_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3385 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3385, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3385; + setArg(call_illegal_fp_normal_3385, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3385, 1, vd); + setArg(call_illegal_fp_normal_3385, 2, vm); + setArg(call_illegal_fp_normal_3385, 3, illegal_fp_normal_3385_arg2); + setArg(call_illegal_fp_normal_3385, 4, illegal_fp_normal_3385_arg3); + setRet(call_illegal_fp_normal_3385, 0, ret_val_illegal_fp_normal_3385); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79779,45 +79333,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3371; - x86::Gp ret_val_sew_3371 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3371, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3370; - auto fp_vector_vector_op_3370_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3370_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3370_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3370_arg10 = rm; - auto fp_vector_vector_op_3370_arg11 = ret_val_sew_3371; + InvokeNode* call_sew_3387; + x86::Gp ret_val_sew_3387 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3387, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3386; + auto fp_vector_vector_op_3386_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3386_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3386_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3386_arg10 = rm; + auto fp_vector_vector_op_3386_arg11 = ret_val_sew_3387; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3370, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3371, 0, reinterpret_cast(this)); - setRet(call_sew_3371, 0, ret_val_sew_3371); - setArg(call_fp_vector_vector_op_3370, 0, V); - setArg(call_fp_vector_vector_op_3370, 1, 44); - setArg(call_fp_vector_vector_op_3370, 2, 1); - setArg(call_fp_vector_vector_op_3370, 3, fp_vector_vector_op_3370_arg3); - setArg(call_fp_vector_vector_op_3370, 4, fp_vector_vector_op_3370_arg4); - setArg(call_fp_vector_vector_op_3370, 5, fp_vector_vector_op_3370_arg5); - setArg(call_fp_vector_vector_op_3370, 6, vm); - setArg(call_fp_vector_vector_op_3370, 7, vd); - setArg(call_fp_vector_vector_op_3370, 8, vs2); - setArg(call_fp_vector_vector_op_3370, 9, vs1); - setArg(call_fp_vector_vector_op_3370, 10, fp_vector_vector_op_3370_arg10); - setArg(call_fp_vector_vector_op_3370, 11, fp_vector_vector_op_3370_arg11); - InvokeNode* call_fget_flags_3372; - x86::Gp ret_val_fget_flags_3372 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3372, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3372; - setRet(call_fget_flags_3372, 0, ret_val_fget_flags_3372); + cc.invoke(&call_fp_vector_vector_op_3386, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3387, 0, reinterpret_cast(this)); + setRet(call_sew_3387, 0, ret_val_sew_3387); + setArg(call_fp_vector_vector_op_3386, 0, V); + setArg(call_fp_vector_vector_op_3386, 1, 44); + setArg(call_fp_vector_vector_op_3386, 2, 1); + setArg(call_fp_vector_vector_op_3386, 3, fp_vector_vector_op_3386_arg3); + setArg(call_fp_vector_vector_op_3386, 4, fp_vector_vector_op_3386_arg4); + setArg(call_fp_vector_vector_op_3386, 5, fp_vector_vector_op_3386_arg5); + setArg(call_fp_vector_vector_op_3386, 6, vm); + setArg(call_fp_vector_vector_op_3386, 7, vd); + setArg(call_fp_vector_vector_op_3386, 8, vs2); + setArg(call_fp_vector_vector_op_3386, 9, vs1); + setArg(call_fp_vector_vector_op_3386, 10, fp_vector_vector_op_3386_arg10); + setArg(call_fp_vector_vector_op_3386, 11, fp_vector_vector_op_3386_arg11); + InvokeNode* call_fget_flags_3388; + x86::Gp ret_val_fget_flags_3388 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3388, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3388; + setRet(call_fget_flags_3388, 0, ret_val_fget_flags_3388); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3373 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3373, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3373, 64, false) - , traits::vstart); + auto tmp3389 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3389, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3389, traits::vstart); } cc.bind(label_merge); } @@ -79861,30 +79413,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3374; - x86::Gp ret_val_get_sew_pow_3374 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3374, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3375 = get_reg(cc, 8, false); - mov(cc, tmp3375, 1); + InvokeNode* call_get_sew_pow_3390; + x86::Gp ret_val_get_sew_pow_3390 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3390, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3391 = get_reg(cc, 8, false); + mov(cc, tmp3391, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3375, (ret_val_get_sew_pow_3374))), 8, false), ~ 1); - setArg(call_get_sew_pow_3374, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3374, 0, ret_val_get_sew_pow_3374); + (gen_operation(cc, shl, tmp3391, (ret_val_get_sew_pow_3390))), 8, false), ~ 1); + setArg(call_get_sew_pow_3390, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3390, 0, ret_val_get_sew_pow_3390); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3376; - auto illegal_fp_normal_3376_arg2 = SEW; - auto illegal_fp_normal_3376_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3376 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3376, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3376; - setArg(call_illegal_fp_normal_3376, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3376, 1, vd); - setArg(call_illegal_fp_normal_3376, 2, vm); - setArg(call_illegal_fp_normal_3376, 3, illegal_fp_normal_3376_arg2); - setArg(call_illegal_fp_normal_3376, 4, illegal_fp_normal_3376_arg3); - setRet(call_illegal_fp_normal_3376, 0, ret_val_illegal_fp_normal_3376); + InvokeNode* call_illegal_fp_normal_3392; + auto illegal_fp_normal_3392_arg2 = SEW; + auto illegal_fp_normal_3392_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3392 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3392, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3392; + setArg(call_illegal_fp_normal_3392, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3392, 1, vd); + setArg(call_illegal_fp_normal_3392, 2, vm); + setArg(call_illegal_fp_normal_3392, 3, illegal_fp_normal_3392_arg2); + setArg(call_illegal_fp_normal_3392, 4, illegal_fp_normal_3392_arg3); + setRet(call_illegal_fp_normal_3392, 0, ret_val_illegal_fp_normal_3392); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -79900,47 +79452,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3378; - x86::Gp ret_val_sew_3378 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3378, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3377; - auto fp_vector_imm_op_3377_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3377_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3377_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3377_arg9 = gen_ext(cc, + InvokeNode* call_sew_3394; + x86::Gp ret_val_sew_3394 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3394, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3393; + auto fp_vector_imm_op_3393_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3393_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3393_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3393_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3377_arg10 = rm; - auto fp_vector_imm_op_3377_arg11 = ret_val_sew_3378; + auto fp_vector_imm_op_3393_arg10 = rm; + auto fp_vector_imm_op_3393_arg11 = ret_val_sew_3394; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3377, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3378, 0, reinterpret_cast(this)); - setRet(call_sew_3378, 0, ret_val_sew_3378); - setArg(call_fp_vector_imm_op_3377, 0, V); - setArg(call_fp_vector_imm_op_3377, 1, 45); - setArg(call_fp_vector_imm_op_3377, 2, 5); - setArg(call_fp_vector_imm_op_3377, 3, fp_vector_imm_op_3377_arg3); - setArg(call_fp_vector_imm_op_3377, 4, fp_vector_imm_op_3377_arg4); - setArg(call_fp_vector_imm_op_3377, 5, fp_vector_imm_op_3377_arg5); - setArg(call_fp_vector_imm_op_3377, 6, vm); - setArg(call_fp_vector_imm_op_3377, 7, vd); - setArg(call_fp_vector_imm_op_3377, 8, vs2); - setArg(call_fp_vector_imm_op_3377, 9, fp_vector_imm_op_3377_arg9); - setArg(call_fp_vector_imm_op_3377, 10, fp_vector_imm_op_3377_arg10); - setArg(call_fp_vector_imm_op_3377, 11, fp_vector_imm_op_3377_arg11); - InvokeNode* call_fget_flags_3379; - x86::Gp ret_val_fget_flags_3379 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3379, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3379; - setRet(call_fget_flags_3379, 0, ret_val_fget_flags_3379); + cc.invoke(&call_fp_vector_imm_op_3393, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3394, 0, reinterpret_cast(this)); + setRet(call_sew_3394, 0, ret_val_sew_3394); + setArg(call_fp_vector_imm_op_3393, 0, V); + setArg(call_fp_vector_imm_op_3393, 1, 45); + setArg(call_fp_vector_imm_op_3393, 2, 5); + setArg(call_fp_vector_imm_op_3393, 3, fp_vector_imm_op_3393_arg3); + setArg(call_fp_vector_imm_op_3393, 4, fp_vector_imm_op_3393_arg4); + setArg(call_fp_vector_imm_op_3393, 5, fp_vector_imm_op_3393_arg5); + setArg(call_fp_vector_imm_op_3393, 6, vm); + setArg(call_fp_vector_imm_op_3393, 7, vd); + setArg(call_fp_vector_imm_op_3393, 8, vs2); + setArg(call_fp_vector_imm_op_3393, 9, fp_vector_imm_op_3393_arg9); + setArg(call_fp_vector_imm_op_3393, 10, fp_vector_imm_op_3393_arg10); + setArg(call_fp_vector_imm_op_3393, 11, fp_vector_imm_op_3393_arg11); + InvokeNode* call_fget_flags_3395; + x86::Gp ret_val_fget_flags_3395 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3395, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3395; + setRet(call_fget_flags_3395, 0, ret_val_fget_flags_3395); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3380 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3380, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3380, 64, false) - , traits::vstart); + auto tmp3396 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3396, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3396, traits::vstart); } cc.bind(label_merge); } @@ -79984,30 +79534,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3381; - x86::Gp ret_val_get_sew_pow_3381 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3381, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3382 = get_reg(cc, 8, false); - mov(cc, tmp3382, 1); + InvokeNode* call_get_sew_pow_3397; + x86::Gp ret_val_get_sew_pow_3397 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3397, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3398 = get_reg(cc, 8, false); + mov(cc, tmp3398, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3382, (ret_val_get_sew_pow_3381))), 8, false), ~ 1); - setArg(call_get_sew_pow_3381, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3381, 0, ret_val_get_sew_pow_3381); + (gen_operation(cc, shl, tmp3398, (ret_val_get_sew_pow_3397))), 8, false), ~ 1); + setArg(call_get_sew_pow_3397, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3397, 0, ret_val_get_sew_pow_3397); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3383; - auto illegal_fp_normal_3383_arg2 = SEW; - auto illegal_fp_normal_3383_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3383 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3383, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3383; - setArg(call_illegal_fp_normal_3383, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3383, 1, vd); - setArg(call_illegal_fp_normal_3383, 2, vm); - setArg(call_illegal_fp_normal_3383, 3, illegal_fp_normal_3383_arg2); - setArg(call_illegal_fp_normal_3383, 4, illegal_fp_normal_3383_arg3); - setRet(call_illegal_fp_normal_3383, 0, ret_val_illegal_fp_normal_3383); + InvokeNode* call_illegal_fp_normal_3399; + auto illegal_fp_normal_3399_arg2 = SEW; + auto illegal_fp_normal_3399_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3399 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3399, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3399; + setArg(call_illegal_fp_normal_3399, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3399, 1, vd); + setArg(call_illegal_fp_normal_3399, 2, vm); + setArg(call_illegal_fp_normal_3399, 3, illegal_fp_normal_3399_arg2); + setArg(call_illegal_fp_normal_3399, 4, illegal_fp_normal_3399_arg3); + setRet(call_illegal_fp_normal_3399, 0, ret_val_illegal_fp_normal_3399); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80023,45 +79573,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3385; - x86::Gp ret_val_sew_3385 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3385, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3384; - auto fp_vector_vector_op_3384_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3384_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3384_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3384_arg10 = rm; - auto fp_vector_vector_op_3384_arg11 = ret_val_sew_3385; + InvokeNode* call_sew_3401; + x86::Gp ret_val_sew_3401 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3401, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3400; + auto fp_vector_vector_op_3400_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3400_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3400_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3400_arg10 = rm; + auto fp_vector_vector_op_3400_arg11 = ret_val_sew_3401; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3384, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3385, 0, reinterpret_cast(this)); - setRet(call_sew_3385, 0, ret_val_sew_3385); - setArg(call_fp_vector_vector_op_3384, 0, V); - setArg(call_fp_vector_vector_op_3384, 1, 45); - setArg(call_fp_vector_vector_op_3384, 2, 1); - setArg(call_fp_vector_vector_op_3384, 3, fp_vector_vector_op_3384_arg3); - setArg(call_fp_vector_vector_op_3384, 4, fp_vector_vector_op_3384_arg4); - setArg(call_fp_vector_vector_op_3384, 5, fp_vector_vector_op_3384_arg5); - setArg(call_fp_vector_vector_op_3384, 6, vm); - setArg(call_fp_vector_vector_op_3384, 7, vd); - setArg(call_fp_vector_vector_op_3384, 8, vs2); - setArg(call_fp_vector_vector_op_3384, 9, vs1); - setArg(call_fp_vector_vector_op_3384, 10, fp_vector_vector_op_3384_arg10); - setArg(call_fp_vector_vector_op_3384, 11, fp_vector_vector_op_3384_arg11); - InvokeNode* call_fget_flags_3386; - x86::Gp ret_val_fget_flags_3386 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3386, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3386; - setRet(call_fget_flags_3386, 0, ret_val_fget_flags_3386); + cc.invoke(&call_fp_vector_vector_op_3400, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3401, 0, reinterpret_cast(this)); + setRet(call_sew_3401, 0, ret_val_sew_3401); + setArg(call_fp_vector_vector_op_3400, 0, V); + setArg(call_fp_vector_vector_op_3400, 1, 45); + setArg(call_fp_vector_vector_op_3400, 2, 1); + setArg(call_fp_vector_vector_op_3400, 3, fp_vector_vector_op_3400_arg3); + setArg(call_fp_vector_vector_op_3400, 4, fp_vector_vector_op_3400_arg4); + setArg(call_fp_vector_vector_op_3400, 5, fp_vector_vector_op_3400_arg5); + setArg(call_fp_vector_vector_op_3400, 6, vm); + setArg(call_fp_vector_vector_op_3400, 7, vd); + setArg(call_fp_vector_vector_op_3400, 8, vs2); + setArg(call_fp_vector_vector_op_3400, 9, vs1); + setArg(call_fp_vector_vector_op_3400, 10, fp_vector_vector_op_3400_arg10); + setArg(call_fp_vector_vector_op_3400, 11, fp_vector_vector_op_3400_arg11); + InvokeNode* call_fget_flags_3402; + x86::Gp ret_val_fget_flags_3402 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3402, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3402; + setRet(call_fget_flags_3402, 0, ret_val_fget_flags_3402); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3387 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3387, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3387, 64, false) - , traits::vstart); + auto tmp3403 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3403, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3403, traits::vstart); } cc.bind(label_merge); } @@ -80105,30 +79653,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3388; - x86::Gp ret_val_get_sew_pow_3388 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3388, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3389 = get_reg(cc, 8, false); - mov(cc, tmp3389, 1); + InvokeNode* call_get_sew_pow_3404; + x86::Gp ret_val_get_sew_pow_3404 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3404, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3405 = get_reg(cc, 8, false); + mov(cc, tmp3405, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3389, (ret_val_get_sew_pow_3388))), 8, false), ~ 1); - setArg(call_get_sew_pow_3388, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3388, 0, ret_val_get_sew_pow_3388); + (gen_operation(cc, shl, tmp3405, (ret_val_get_sew_pow_3404))), 8, false), ~ 1); + setArg(call_get_sew_pow_3404, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3404, 0, ret_val_get_sew_pow_3404); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3390; - auto illegal_fp_normal_3390_arg2 = SEW; - auto illegal_fp_normal_3390_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3390 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3390, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3390; - setArg(call_illegal_fp_normal_3390, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3390, 1, vd); - setArg(call_illegal_fp_normal_3390, 2, vm); - setArg(call_illegal_fp_normal_3390, 3, illegal_fp_normal_3390_arg2); - setArg(call_illegal_fp_normal_3390, 4, illegal_fp_normal_3390_arg3); - setRet(call_illegal_fp_normal_3390, 0, ret_val_illegal_fp_normal_3390); + InvokeNode* call_illegal_fp_normal_3406; + auto illegal_fp_normal_3406_arg2 = SEW; + auto illegal_fp_normal_3406_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3406 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3406, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3406; + setArg(call_illegal_fp_normal_3406, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3406, 1, vd); + setArg(call_illegal_fp_normal_3406, 2, vm); + setArg(call_illegal_fp_normal_3406, 3, illegal_fp_normal_3406_arg2); + setArg(call_illegal_fp_normal_3406, 4, illegal_fp_normal_3406_arg3); + setRet(call_illegal_fp_normal_3406, 0, ret_val_illegal_fp_normal_3406); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80144,47 +79692,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3392; - x86::Gp ret_val_sew_3392 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3392, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3391; - auto fp_vector_imm_op_3391_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3391_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3391_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3391_arg9 = gen_ext(cc, + InvokeNode* call_sew_3408; + x86::Gp ret_val_sew_3408 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3408, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3407; + auto fp_vector_imm_op_3407_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3407_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3407_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3407_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3391_arg10 = rm; - auto fp_vector_imm_op_3391_arg11 = ret_val_sew_3392; + auto fp_vector_imm_op_3407_arg10 = rm; + auto fp_vector_imm_op_3407_arg11 = ret_val_sew_3408; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3391, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3392, 0, reinterpret_cast(this)); - setRet(call_sew_3392, 0, ret_val_sew_3392); - setArg(call_fp_vector_imm_op_3391, 0, V); - setArg(call_fp_vector_imm_op_3391, 1, 46); - setArg(call_fp_vector_imm_op_3391, 2, 5); - setArg(call_fp_vector_imm_op_3391, 3, fp_vector_imm_op_3391_arg3); - setArg(call_fp_vector_imm_op_3391, 4, fp_vector_imm_op_3391_arg4); - setArg(call_fp_vector_imm_op_3391, 5, fp_vector_imm_op_3391_arg5); - setArg(call_fp_vector_imm_op_3391, 6, vm); - setArg(call_fp_vector_imm_op_3391, 7, vd); - setArg(call_fp_vector_imm_op_3391, 8, vs2); - setArg(call_fp_vector_imm_op_3391, 9, fp_vector_imm_op_3391_arg9); - setArg(call_fp_vector_imm_op_3391, 10, fp_vector_imm_op_3391_arg10); - setArg(call_fp_vector_imm_op_3391, 11, fp_vector_imm_op_3391_arg11); - InvokeNode* call_fget_flags_3393; - x86::Gp ret_val_fget_flags_3393 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3393, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3393; - setRet(call_fget_flags_3393, 0, ret_val_fget_flags_3393); + cc.invoke(&call_fp_vector_imm_op_3407, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3408, 0, reinterpret_cast(this)); + setRet(call_sew_3408, 0, ret_val_sew_3408); + setArg(call_fp_vector_imm_op_3407, 0, V); + setArg(call_fp_vector_imm_op_3407, 1, 46); + setArg(call_fp_vector_imm_op_3407, 2, 5); + setArg(call_fp_vector_imm_op_3407, 3, fp_vector_imm_op_3407_arg3); + setArg(call_fp_vector_imm_op_3407, 4, fp_vector_imm_op_3407_arg4); + setArg(call_fp_vector_imm_op_3407, 5, fp_vector_imm_op_3407_arg5); + setArg(call_fp_vector_imm_op_3407, 6, vm); + setArg(call_fp_vector_imm_op_3407, 7, vd); + setArg(call_fp_vector_imm_op_3407, 8, vs2); + setArg(call_fp_vector_imm_op_3407, 9, fp_vector_imm_op_3407_arg9); + setArg(call_fp_vector_imm_op_3407, 10, fp_vector_imm_op_3407_arg10); + setArg(call_fp_vector_imm_op_3407, 11, fp_vector_imm_op_3407_arg11); + InvokeNode* call_fget_flags_3409; + x86::Gp ret_val_fget_flags_3409 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3409, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3409; + setRet(call_fget_flags_3409, 0, ret_val_fget_flags_3409); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3394 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3394, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3394, 64, false) - , traits::vstart); + auto tmp3410 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3410, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3410, traits::vstart); } cc.bind(label_merge); } @@ -80228,30 +79774,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3395; - x86::Gp ret_val_get_sew_pow_3395 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3395, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3396 = get_reg(cc, 8, false); - mov(cc, tmp3396, 1); + InvokeNode* call_get_sew_pow_3411; + x86::Gp ret_val_get_sew_pow_3411 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3411, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3412 = get_reg(cc, 8, false); + mov(cc, tmp3412, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3396, (ret_val_get_sew_pow_3395))), 8, false), ~ 1); - setArg(call_get_sew_pow_3395, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3395, 0, ret_val_get_sew_pow_3395); + (gen_operation(cc, shl, tmp3412, (ret_val_get_sew_pow_3411))), 8, false), ~ 1); + setArg(call_get_sew_pow_3411, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3411, 0, ret_val_get_sew_pow_3411); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3397; - auto illegal_fp_normal_3397_arg2 = SEW; - auto illegal_fp_normal_3397_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3397 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3397, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3397; - setArg(call_illegal_fp_normal_3397, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3397, 1, vd); - setArg(call_illegal_fp_normal_3397, 2, vm); - setArg(call_illegal_fp_normal_3397, 3, illegal_fp_normal_3397_arg2); - setArg(call_illegal_fp_normal_3397, 4, illegal_fp_normal_3397_arg3); - setRet(call_illegal_fp_normal_3397, 0, ret_val_illegal_fp_normal_3397); + InvokeNode* call_illegal_fp_normal_3413; + auto illegal_fp_normal_3413_arg2 = SEW; + auto illegal_fp_normal_3413_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3413 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3413, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3413; + setArg(call_illegal_fp_normal_3413, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3413, 1, vd); + setArg(call_illegal_fp_normal_3413, 2, vm); + setArg(call_illegal_fp_normal_3413, 3, illegal_fp_normal_3413_arg2); + setArg(call_illegal_fp_normal_3413, 4, illegal_fp_normal_3413_arg3); + setRet(call_illegal_fp_normal_3413, 0, ret_val_illegal_fp_normal_3413); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80267,45 +79813,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3399; - x86::Gp ret_val_sew_3399 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3399, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3398; - auto fp_vector_vector_op_3398_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3398_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3398_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3398_arg10 = rm; - auto fp_vector_vector_op_3398_arg11 = ret_val_sew_3399; + InvokeNode* call_sew_3415; + x86::Gp ret_val_sew_3415 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3415, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3414; + auto fp_vector_vector_op_3414_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3414_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3414_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3414_arg10 = rm; + auto fp_vector_vector_op_3414_arg11 = ret_val_sew_3415; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3398, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3399, 0, reinterpret_cast(this)); - setRet(call_sew_3399, 0, ret_val_sew_3399); - setArg(call_fp_vector_vector_op_3398, 0, V); - setArg(call_fp_vector_vector_op_3398, 1, 46); - setArg(call_fp_vector_vector_op_3398, 2, 1); - setArg(call_fp_vector_vector_op_3398, 3, fp_vector_vector_op_3398_arg3); - setArg(call_fp_vector_vector_op_3398, 4, fp_vector_vector_op_3398_arg4); - setArg(call_fp_vector_vector_op_3398, 5, fp_vector_vector_op_3398_arg5); - setArg(call_fp_vector_vector_op_3398, 6, vm); - setArg(call_fp_vector_vector_op_3398, 7, vd); - setArg(call_fp_vector_vector_op_3398, 8, vs2); - setArg(call_fp_vector_vector_op_3398, 9, vs1); - setArg(call_fp_vector_vector_op_3398, 10, fp_vector_vector_op_3398_arg10); - setArg(call_fp_vector_vector_op_3398, 11, fp_vector_vector_op_3398_arg11); - InvokeNode* call_fget_flags_3400; - x86::Gp ret_val_fget_flags_3400 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3400, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3400; - setRet(call_fget_flags_3400, 0, ret_val_fget_flags_3400); + cc.invoke(&call_fp_vector_vector_op_3414, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3415, 0, reinterpret_cast(this)); + setRet(call_sew_3415, 0, ret_val_sew_3415); + setArg(call_fp_vector_vector_op_3414, 0, V); + setArg(call_fp_vector_vector_op_3414, 1, 46); + setArg(call_fp_vector_vector_op_3414, 2, 1); + setArg(call_fp_vector_vector_op_3414, 3, fp_vector_vector_op_3414_arg3); + setArg(call_fp_vector_vector_op_3414, 4, fp_vector_vector_op_3414_arg4); + setArg(call_fp_vector_vector_op_3414, 5, fp_vector_vector_op_3414_arg5); + setArg(call_fp_vector_vector_op_3414, 6, vm); + setArg(call_fp_vector_vector_op_3414, 7, vd); + setArg(call_fp_vector_vector_op_3414, 8, vs2); + setArg(call_fp_vector_vector_op_3414, 9, vs1); + setArg(call_fp_vector_vector_op_3414, 10, fp_vector_vector_op_3414_arg10); + setArg(call_fp_vector_vector_op_3414, 11, fp_vector_vector_op_3414_arg11); + InvokeNode* call_fget_flags_3416; + x86::Gp ret_val_fget_flags_3416 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3416, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3416; + setRet(call_fget_flags_3416, 0, ret_val_fget_flags_3416); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3401 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3401, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3401, 64, false) - , traits::vstart); + auto tmp3417 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3417, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3417, traits::vstart); } cc.bind(label_merge); } @@ -80349,30 +79893,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3402; - x86::Gp ret_val_get_sew_pow_3402 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3402, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3403 = get_reg(cc, 8, false); - mov(cc, tmp3403, 1); + InvokeNode* call_get_sew_pow_3418; + x86::Gp ret_val_get_sew_pow_3418 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3418, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3419 = get_reg(cc, 8, false); + mov(cc, tmp3419, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3403, (ret_val_get_sew_pow_3402))), 8, false), ~ 1); - setArg(call_get_sew_pow_3402, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3402, 0, ret_val_get_sew_pow_3402); + (gen_operation(cc, shl, tmp3419, (ret_val_get_sew_pow_3418))), 8, false), ~ 1); + setArg(call_get_sew_pow_3418, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3418, 0, ret_val_get_sew_pow_3418); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3404; - auto illegal_fp_normal_3404_arg2 = SEW; - auto illegal_fp_normal_3404_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3404 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3404, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3404; - setArg(call_illegal_fp_normal_3404, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3404, 1, vd); - setArg(call_illegal_fp_normal_3404, 2, vm); - setArg(call_illegal_fp_normal_3404, 3, illegal_fp_normal_3404_arg2); - setArg(call_illegal_fp_normal_3404, 4, illegal_fp_normal_3404_arg3); - setRet(call_illegal_fp_normal_3404, 0, ret_val_illegal_fp_normal_3404); + InvokeNode* call_illegal_fp_normal_3420; + auto illegal_fp_normal_3420_arg2 = SEW; + auto illegal_fp_normal_3420_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3420 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3420, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3420; + setArg(call_illegal_fp_normal_3420, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3420, 1, vd); + setArg(call_illegal_fp_normal_3420, 2, vm); + setArg(call_illegal_fp_normal_3420, 3, illegal_fp_normal_3420_arg2); + setArg(call_illegal_fp_normal_3420, 4, illegal_fp_normal_3420_arg3); + setRet(call_illegal_fp_normal_3420, 0, ret_val_illegal_fp_normal_3420); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80388,47 +79932,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3406; - x86::Gp ret_val_sew_3406 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3406, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3405; - auto fp_vector_imm_op_3405_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3405_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3405_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3405_arg9 = gen_ext(cc, + InvokeNode* call_sew_3422; + x86::Gp ret_val_sew_3422 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3422, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3421; + auto fp_vector_imm_op_3421_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3421_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3421_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3421_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3405_arg10 = rm; - auto fp_vector_imm_op_3405_arg11 = ret_val_sew_3406; + auto fp_vector_imm_op_3421_arg10 = rm; + auto fp_vector_imm_op_3421_arg11 = ret_val_sew_3422; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3405, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3406, 0, reinterpret_cast(this)); - setRet(call_sew_3406, 0, ret_val_sew_3406); - setArg(call_fp_vector_imm_op_3405, 0, V); - setArg(call_fp_vector_imm_op_3405, 1, 47); - setArg(call_fp_vector_imm_op_3405, 2, 5); - setArg(call_fp_vector_imm_op_3405, 3, fp_vector_imm_op_3405_arg3); - setArg(call_fp_vector_imm_op_3405, 4, fp_vector_imm_op_3405_arg4); - setArg(call_fp_vector_imm_op_3405, 5, fp_vector_imm_op_3405_arg5); - setArg(call_fp_vector_imm_op_3405, 6, vm); - setArg(call_fp_vector_imm_op_3405, 7, vd); - setArg(call_fp_vector_imm_op_3405, 8, vs2); - setArg(call_fp_vector_imm_op_3405, 9, fp_vector_imm_op_3405_arg9); - setArg(call_fp_vector_imm_op_3405, 10, fp_vector_imm_op_3405_arg10); - setArg(call_fp_vector_imm_op_3405, 11, fp_vector_imm_op_3405_arg11); - InvokeNode* call_fget_flags_3407; - x86::Gp ret_val_fget_flags_3407 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3407, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3407; - setRet(call_fget_flags_3407, 0, ret_val_fget_flags_3407); + cc.invoke(&call_fp_vector_imm_op_3421, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3422, 0, reinterpret_cast(this)); + setRet(call_sew_3422, 0, ret_val_sew_3422); + setArg(call_fp_vector_imm_op_3421, 0, V); + setArg(call_fp_vector_imm_op_3421, 1, 47); + setArg(call_fp_vector_imm_op_3421, 2, 5); + setArg(call_fp_vector_imm_op_3421, 3, fp_vector_imm_op_3421_arg3); + setArg(call_fp_vector_imm_op_3421, 4, fp_vector_imm_op_3421_arg4); + setArg(call_fp_vector_imm_op_3421, 5, fp_vector_imm_op_3421_arg5); + setArg(call_fp_vector_imm_op_3421, 6, vm); + setArg(call_fp_vector_imm_op_3421, 7, vd); + setArg(call_fp_vector_imm_op_3421, 8, vs2); + setArg(call_fp_vector_imm_op_3421, 9, fp_vector_imm_op_3421_arg9); + setArg(call_fp_vector_imm_op_3421, 10, fp_vector_imm_op_3421_arg10); + setArg(call_fp_vector_imm_op_3421, 11, fp_vector_imm_op_3421_arg11); + InvokeNode* call_fget_flags_3423; + x86::Gp ret_val_fget_flags_3423 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3423, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3423; + setRet(call_fget_flags_3423, 0, ret_val_fget_flags_3423); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3408 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3408, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3408, 64, false) - , traits::vstart); + auto tmp3424 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3424, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3424, traits::vstart); } cc.bind(label_merge); } @@ -80472,30 +80014,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3409; - x86::Gp ret_val_get_sew_pow_3409 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3409, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3410 = get_reg(cc, 8, false); - mov(cc, tmp3410, 1); + InvokeNode* call_get_sew_pow_3425; + x86::Gp ret_val_get_sew_pow_3425 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3425, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3426 = get_reg(cc, 8, false); + mov(cc, tmp3426, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3410, (ret_val_get_sew_pow_3409))), 8, false), ~ 1); - setArg(call_get_sew_pow_3409, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3409, 0, ret_val_get_sew_pow_3409); + (gen_operation(cc, shl, tmp3426, (ret_val_get_sew_pow_3425))), 8, false), ~ 1); + setArg(call_get_sew_pow_3425, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3425, 0, ret_val_get_sew_pow_3425); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3411; - auto illegal_fp_normal_3411_arg2 = SEW; - auto illegal_fp_normal_3411_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3411 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3411, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3411; - setArg(call_illegal_fp_normal_3411, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3411, 1, vd); - setArg(call_illegal_fp_normal_3411, 2, vm); - setArg(call_illegal_fp_normal_3411, 3, illegal_fp_normal_3411_arg2); - setArg(call_illegal_fp_normal_3411, 4, illegal_fp_normal_3411_arg3); - setRet(call_illegal_fp_normal_3411, 0, ret_val_illegal_fp_normal_3411); + InvokeNode* call_illegal_fp_normal_3427; + auto illegal_fp_normal_3427_arg2 = SEW; + auto illegal_fp_normal_3427_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3427 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3427, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3427; + setArg(call_illegal_fp_normal_3427, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3427, 1, vd); + setArg(call_illegal_fp_normal_3427, 2, vm); + setArg(call_illegal_fp_normal_3427, 3, illegal_fp_normal_3427_arg2); + setArg(call_illegal_fp_normal_3427, 4, illegal_fp_normal_3427_arg3); + setRet(call_illegal_fp_normal_3427, 0, ret_val_illegal_fp_normal_3427); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80511,45 +80053,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3413; - x86::Gp ret_val_sew_3413 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3413, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3412; - auto fp_vector_vector_op_3412_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3412_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3412_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3412_arg10 = rm; - auto fp_vector_vector_op_3412_arg11 = ret_val_sew_3413; + InvokeNode* call_sew_3429; + x86::Gp ret_val_sew_3429 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3429, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3428; + auto fp_vector_vector_op_3428_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3428_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3428_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3428_arg10 = rm; + auto fp_vector_vector_op_3428_arg11 = ret_val_sew_3429; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3412, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3413, 0, reinterpret_cast(this)); - setRet(call_sew_3413, 0, ret_val_sew_3413); - setArg(call_fp_vector_vector_op_3412, 0, V); - setArg(call_fp_vector_vector_op_3412, 1, 47); - setArg(call_fp_vector_vector_op_3412, 2, 1); - setArg(call_fp_vector_vector_op_3412, 3, fp_vector_vector_op_3412_arg3); - setArg(call_fp_vector_vector_op_3412, 4, fp_vector_vector_op_3412_arg4); - setArg(call_fp_vector_vector_op_3412, 5, fp_vector_vector_op_3412_arg5); - setArg(call_fp_vector_vector_op_3412, 6, vm); - setArg(call_fp_vector_vector_op_3412, 7, vd); - setArg(call_fp_vector_vector_op_3412, 8, vs2); - setArg(call_fp_vector_vector_op_3412, 9, vs1); - setArg(call_fp_vector_vector_op_3412, 10, fp_vector_vector_op_3412_arg10); - setArg(call_fp_vector_vector_op_3412, 11, fp_vector_vector_op_3412_arg11); - InvokeNode* call_fget_flags_3414; - x86::Gp ret_val_fget_flags_3414 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3414, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3414; - setRet(call_fget_flags_3414, 0, ret_val_fget_flags_3414); + cc.invoke(&call_fp_vector_vector_op_3428, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3429, 0, reinterpret_cast(this)); + setRet(call_sew_3429, 0, ret_val_sew_3429); + setArg(call_fp_vector_vector_op_3428, 0, V); + setArg(call_fp_vector_vector_op_3428, 1, 47); + setArg(call_fp_vector_vector_op_3428, 2, 1); + setArg(call_fp_vector_vector_op_3428, 3, fp_vector_vector_op_3428_arg3); + setArg(call_fp_vector_vector_op_3428, 4, fp_vector_vector_op_3428_arg4); + setArg(call_fp_vector_vector_op_3428, 5, fp_vector_vector_op_3428_arg5); + setArg(call_fp_vector_vector_op_3428, 6, vm); + setArg(call_fp_vector_vector_op_3428, 7, vd); + setArg(call_fp_vector_vector_op_3428, 8, vs2); + setArg(call_fp_vector_vector_op_3428, 9, vs1); + setArg(call_fp_vector_vector_op_3428, 10, fp_vector_vector_op_3428_arg10); + setArg(call_fp_vector_vector_op_3428, 11, fp_vector_vector_op_3428_arg11); + InvokeNode* call_fget_flags_3430; + x86::Gp ret_val_fget_flags_3430 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3430, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3430; + setRet(call_fget_flags_3430, 0, ret_val_fget_flags_3430); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3415 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3415, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3415, 64, false) - , traits::vstart); + auto tmp3431 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3431, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3431, traits::vstart); } cc.bind(label_merge); } @@ -80593,30 +80133,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3416; - x86::Gp ret_val_get_sew_pow_3416 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3416, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3417 = get_reg(cc, 8, false); - mov(cc, tmp3417, 1); + InvokeNode* call_get_sew_pow_3432; + x86::Gp ret_val_get_sew_pow_3432 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3432, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3433 = get_reg(cc, 8, false); + mov(cc, tmp3433, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3417, (ret_val_get_sew_pow_3416))), 8, false), ~ 1); - setArg(call_get_sew_pow_3416, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3416, 0, ret_val_get_sew_pow_3416); + (gen_operation(cc, shl, tmp3433, (ret_val_get_sew_pow_3432))), 8, false), ~ 1); + setArg(call_get_sew_pow_3432, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3432, 0, ret_val_get_sew_pow_3432); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3418; - auto illegal_fp_normal_3418_arg2 = SEW; - auto illegal_fp_normal_3418_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3418 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3418, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3418; - setArg(call_illegal_fp_normal_3418, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3418, 1, vd); - setArg(call_illegal_fp_normal_3418, 2, vm); - setArg(call_illegal_fp_normal_3418, 3, illegal_fp_normal_3418_arg2); - setArg(call_illegal_fp_normal_3418, 4, illegal_fp_normal_3418_arg3); - setRet(call_illegal_fp_normal_3418, 0, ret_val_illegal_fp_normal_3418); + InvokeNode* call_illegal_fp_normal_3434; + auto illegal_fp_normal_3434_arg2 = SEW; + auto illegal_fp_normal_3434_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3434 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3434, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3434; + setArg(call_illegal_fp_normal_3434, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3434, 1, vd); + setArg(call_illegal_fp_normal_3434, 2, vm); + setArg(call_illegal_fp_normal_3434, 3, illegal_fp_normal_3434_arg2); + setArg(call_illegal_fp_normal_3434, 4, illegal_fp_normal_3434_arg3); + setRet(call_illegal_fp_normal_3434, 0, ret_val_illegal_fp_normal_3434); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80632,47 +80172,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3420; - x86::Gp ret_val_sew_3420 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3420, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3419; - auto fp_vector_imm_op_3419_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3419_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3419_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3419_arg9 = gen_ext(cc, + InvokeNode* call_sew_3436; + x86::Gp ret_val_sew_3436 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3436, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3435; + auto fp_vector_imm_op_3435_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3435_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3435_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3435_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3419_arg10 = rm; - auto fp_vector_imm_op_3419_arg11 = ret_val_sew_3420; + auto fp_vector_imm_op_3435_arg10 = rm; + auto fp_vector_imm_op_3435_arg11 = ret_val_sew_3436; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3419, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3420, 0, reinterpret_cast(this)); - setRet(call_sew_3420, 0, ret_val_sew_3420); - setArg(call_fp_vector_imm_op_3419, 0, V); - setArg(call_fp_vector_imm_op_3419, 1, 40); - setArg(call_fp_vector_imm_op_3419, 2, 5); - setArg(call_fp_vector_imm_op_3419, 3, fp_vector_imm_op_3419_arg3); - setArg(call_fp_vector_imm_op_3419, 4, fp_vector_imm_op_3419_arg4); - setArg(call_fp_vector_imm_op_3419, 5, fp_vector_imm_op_3419_arg5); - setArg(call_fp_vector_imm_op_3419, 6, vm); - setArg(call_fp_vector_imm_op_3419, 7, vd); - setArg(call_fp_vector_imm_op_3419, 8, vs2); - setArg(call_fp_vector_imm_op_3419, 9, fp_vector_imm_op_3419_arg9); - setArg(call_fp_vector_imm_op_3419, 10, fp_vector_imm_op_3419_arg10); - setArg(call_fp_vector_imm_op_3419, 11, fp_vector_imm_op_3419_arg11); - InvokeNode* call_fget_flags_3421; - x86::Gp ret_val_fget_flags_3421 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3421, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3421; - setRet(call_fget_flags_3421, 0, ret_val_fget_flags_3421); + cc.invoke(&call_fp_vector_imm_op_3435, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3436, 0, reinterpret_cast(this)); + setRet(call_sew_3436, 0, ret_val_sew_3436); + setArg(call_fp_vector_imm_op_3435, 0, V); + setArg(call_fp_vector_imm_op_3435, 1, 40); + setArg(call_fp_vector_imm_op_3435, 2, 5); + setArg(call_fp_vector_imm_op_3435, 3, fp_vector_imm_op_3435_arg3); + setArg(call_fp_vector_imm_op_3435, 4, fp_vector_imm_op_3435_arg4); + setArg(call_fp_vector_imm_op_3435, 5, fp_vector_imm_op_3435_arg5); + setArg(call_fp_vector_imm_op_3435, 6, vm); + setArg(call_fp_vector_imm_op_3435, 7, vd); + setArg(call_fp_vector_imm_op_3435, 8, vs2); + setArg(call_fp_vector_imm_op_3435, 9, fp_vector_imm_op_3435_arg9); + setArg(call_fp_vector_imm_op_3435, 10, fp_vector_imm_op_3435_arg10); + setArg(call_fp_vector_imm_op_3435, 11, fp_vector_imm_op_3435_arg11); + InvokeNode* call_fget_flags_3437; + x86::Gp ret_val_fget_flags_3437 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3437, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3437; + setRet(call_fget_flags_3437, 0, ret_val_fget_flags_3437); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3422 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3422, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3422, 64, false) - , traits::vstart); + auto tmp3438 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3438, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3438, traits::vstart); } cc.bind(label_merge); } @@ -80716,30 +80254,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3423; - x86::Gp ret_val_get_sew_pow_3423 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3423, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3424 = get_reg(cc, 8, false); - mov(cc, tmp3424, 1); + InvokeNode* call_get_sew_pow_3439; + x86::Gp ret_val_get_sew_pow_3439 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3439, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3440 = get_reg(cc, 8, false); + mov(cc, tmp3440, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3424, (ret_val_get_sew_pow_3423))), 8, false), ~ 1); - setArg(call_get_sew_pow_3423, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3423, 0, ret_val_get_sew_pow_3423); + (gen_operation(cc, shl, tmp3440, (ret_val_get_sew_pow_3439))), 8, false), ~ 1); + setArg(call_get_sew_pow_3439, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3439, 0, ret_val_get_sew_pow_3439); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3425; - auto illegal_fp_normal_3425_arg2 = SEW; - auto illegal_fp_normal_3425_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3425 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3425, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3425; - setArg(call_illegal_fp_normal_3425, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3425, 1, vd); - setArg(call_illegal_fp_normal_3425, 2, vm); - setArg(call_illegal_fp_normal_3425, 3, illegal_fp_normal_3425_arg2); - setArg(call_illegal_fp_normal_3425, 4, illegal_fp_normal_3425_arg3); - setRet(call_illegal_fp_normal_3425, 0, ret_val_illegal_fp_normal_3425); + InvokeNode* call_illegal_fp_normal_3441; + auto illegal_fp_normal_3441_arg2 = SEW; + auto illegal_fp_normal_3441_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3441 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3441, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3441; + setArg(call_illegal_fp_normal_3441, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3441, 1, vd); + setArg(call_illegal_fp_normal_3441, 2, vm); + setArg(call_illegal_fp_normal_3441, 3, illegal_fp_normal_3441_arg2); + setArg(call_illegal_fp_normal_3441, 4, illegal_fp_normal_3441_arg3); + setRet(call_illegal_fp_normal_3441, 0, ret_val_illegal_fp_normal_3441); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80755,45 +80293,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3427; - x86::Gp ret_val_sew_3427 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3427, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3426; - auto fp_vector_vector_op_3426_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3426_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3426_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3426_arg10 = rm; - auto fp_vector_vector_op_3426_arg11 = ret_val_sew_3427; + InvokeNode* call_sew_3443; + x86::Gp ret_val_sew_3443 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3443, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3442; + auto fp_vector_vector_op_3442_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3442_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3442_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3442_arg10 = rm; + auto fp_vector_vector_op_3442_arg11 = ret_val_sew_3443; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3426, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3427, 0, reinterpret_cast(this)); - setRet(call_sew_3427, 0, ret_val_sew_3427); - setArg(call_fp_vector_vector_op_3426, 0, V); - setArg(call_fp_vector_vector_op_3426, 1, 40); - setArg(call_fp_vector_vector_op_3426, 2, 1); - setArg(call_fp_vector_vector_op_3426, 3, fp_vector_vector_op_3426_arg3); - setArg(call_fp_vector_vector_op_3426, 4, fp_vector_vector_op_3426_arg4); - setArg(call_fp_vector_vector_op_3426, 5, fp_vector_vector_op_3426_arg5); - setArg(call_fp_vector_vector_op_3426, 6, vm); - setArg(call_fp_vector_vector_op_3426, 7, vd); - setArg(call_fp_vector_vector_op_3426, 8, vs2); - setArg(call_fp_vector_vector_op_3426, 9, vs1); - setArg(call_fp_vector_vector_op_3426, 10, fp_vector_vector_op_3426_arg10); - setArg(call_fp_vector_vector_op_3426, 11, fp_vector_vector_op_3426_arg11); - InvokeNode* call_fget_flags_3428; - x86::Gp ret_val_fget_flags_3428 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3428, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3428; - setRet(call_fget_flags_3428, 0, ret_val_fget_flags_3428); + cc.invoke(&call_fp_vector_vector_op_3442, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3443, 0, reinterpret_cast(this)); + setRet(call_sew_3443, 0, ret_val_sew_3443); + setArg(call_fp_vector_vector_op_3442, 0, V); + setArg(call_fp_vector_vector_op_3442, 1, 40); + setArg(call_fp_vector_vector_op_3442, 2, 1); + setArg(call_fp_vector_vector_op_3442, 3, fp_vector_vector_op_3442_arg3); + setArg(call_fp_vector_vector_op_3442, 4, fp_vector_vector_op_3442_arg4); + setArg(call_fp_vector_vector_op_3442, 5, fp_vector_vector_op_3442_arg5); + setArg(call_fp_vector_vector_op_3442, 6, vm); + setArg(call_fp_vector_vector_op_3442, 7, vd); + setArg(call_fp_vector_vector_op_3442, 8, vs2); + setArg(call_fp_vector_vector_op_3442, 9, vs1); + setArg(call_fp_vector_vector_op_3442, 10, fp_vector_vector_op_3442_arg10); + setArg(call_fp_vector_vector_op_3442, 11, fp_vector_vector_op_3442_arg11); + InvokeNode* call_fget_flags_3444; + x86::Gp ret_val_fget_flags_3444 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3444, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3444; + setRet(call_fget_flags_3444, 0, ret_val_fget_flags_3444); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3429 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3429, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3429, 64, false) - , traits::vstart); + auto tmp3445 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3445, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3445, traits::vstart); } cc.bind(label_merge); } @@ -80837,30 +80373,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3430; - x86::Gp ret_val_get_sew_pow_3430 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3430, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3431 = get_reg(cc, 8, false); - mov(cc, tmp3431, 1); + InvokeNode* call_get_sew_pow_3446; + x86::Gp ret_val_get_sew_pow_3446 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3446, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3447 = get_reg(cc, 8, false); + mov(cc, tmp3447, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3431, (ret_val_get_sew_pow_3430))), 8, false), ~ 1); - setArg(call_get_sew_pow_3430, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3430, 0, ret_val_get_sew_pow_3430); + (gen_operation(cc, shl, tmp3447, (ret_val_get_sew_pow_3446))), 8, false), ~ 1); + setArg(call_get_sew_pow_3446, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3446, 0, ret_val_get_sew_pow_3446); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3432; - auto illegal_fp_normal_3432_arg2 = SEW; - auto illegal_fp_normal_3432_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3432 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3432, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3432; - setArg(call_illegal_fp_normal_3432, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3432, 1, vd); - setArg(call_illegal_fp_normal_3432, 2, vm); - setArg(call_illegal_fp_normal_3432, 3, illegal_fp_normal_3432_arg2); - setArg(call_illegal_fp_normal_3432, 4, illegal_fp_normal_3432_arg3); - setRet(call_illegal_fp_normal_3432, 0, ret_val_illegal_fp_normal_3432); + InvokeNode* call_illegal_fp_normal_3448; + auto illegal_fp_normal_3448_arg2 = SEW; + auto illegal_fp_normal_3448_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3448 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3448, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3448; + setArg(call_illegal_fp_normal_3448, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3448, 1, vd); + setArg(call_illegal_fp_normal_3448, 2, vm); + setArg(call_illegal_fp_normal_3448, 3, illegal_fp_normal_3448_arg2); + setArg(call_illegal_fp_normal_3448, 4, illegal_fp_normal_3448_arg3); + setRet(call_illegal_fp_normal_3448, 0, ret_val_illegal_fp_normal_3448); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80876,47 +80412,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3434; - x86::Gp ret_val_sew_3434 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3434, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3433; - auto fp_vector_imm_op_3433_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3433_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3433_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3433_arg9 = gen_ext(cc, + InvokeNode* call_sew_3450; + x86::Gp ret_val_sew_3450 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3450, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3449; + auto fp_vector_imm_op_3449_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3449_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3449_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3449_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3433_arg10 = rm; - auto fp_vector_imm_op_3433_arg11 = ret_val_sew_3434; + auto fp_vector_imm_op_3449_arg10 = rm; + auto fp_vector_imm_op_3449_arg11 = ret_val_sew_3450; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3433, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3434, 0, reinterpret_cast(this)); - setRet(call_sew_3434, 0, ret_val_sew_3434); - setArg(call_fp_vector_imm_op_3433, 0, V); - setArg(call_fp_vector_imm_op_3433, 1, 41); - setArg(call_fp_vector_imm_op_3433, 2, 5); - setArg(call_fp_vector_imm_op_3433, 3, fp_vector_imm_op_3433_arg3); - setArg(call_fp_vector_imm_op_3433, 4, fp_vector_imm_op_3433_arg4); - setArg(call_fp_vector_imm_op_3433, 5, fp_vector_imm_op_3433_arg5); - setArg(call_fp_vector_imm_op_3433, 6, vm); - setArg(call_fp_vector_imm_op_3433, 7, vd); - setArg(call_fp_vector_imm_op_3433, 8, vs2); - setArg(call_fp_vector_imm_op_3433, 9, fp_vector_imm_op_3433_arg9); - setArg(call_fp_vector_imm_op_3433, 10, fp_vector_imm_op_3433_arg10); - setArg(call_fp_vector_imm_op_3433, 11, fp_vector_imm_op_3433_arg11); - InvokeNode* call_fget_flags_3435; - x86::Gp ret_val_fget_flags_3435 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3435, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3435; - setRet(call_fget_flags_3435, 0, ret_val_fget_flags_3435); + cc.invoke(&call_fp_vector_imm_op_3449, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3450, 0, reinterpret_cast(this)); + setRet(call_sew_3450, 0, ret_val_sew_3450); + setArg(call_fp_vector_imm_op_3449, 0, V); + setArg(call_fp_vector_imm_op_3449, 1, 41); + setArg(call_fp_vector_imm_op_3449, 2, 5); + setArg(call_fp_vector_imm_op_3449, 3, fp_vector_imm_op_3449_arg3); + setArg(call_fp_vector_imm_op_3449, 4, fp_vector_imm_op_3449_arg4); + setArg(call_fp_vector_imm_op_3449, 5, fp_vector_imm_op_3449_arg5); + setArg(call_fp_vector_imm_op_3449, 6, vm); + setArg(call_fp_vector_imm_op_3449, 7, vd); + setArg(call_fp_vector_imm_op_3449, 8, vs2); + setArg(call_fp_vector_imm_op_3449, 9, fp_vector_imm_op_3449_arg9); + setArg(call_fp_vector_imm_op_3449, 10, fp_vector_imm_op_3449_arg10); + setArg(call_fp_vector_imm_op_3449, 11, fp_vector_imm_op_3449_arg11); + InvokeNode* call_fget_flags_3451; + x86::Gp ret_val_fget_flags_3451 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3451, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3451; + setRet(call_fget_flags_3451, 0, ret_val_fget_flags_3451); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3436 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3436, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3436, 64, false) - , traits::vstart); + auto tmp3452 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3452, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3452, traits::vstart); } cc.bind(label_merge); } @@ -80960,30 +80494,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3437; - x86::Gp ret_val_get_sew_pow_3437 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3437, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3438 = get_reg(cc, 8, false); - mov(cc, tmp3438, 1); + InvokeNode* call_get_sew_pow_3453; + x86::Gp ret_val_get_sew_pow_3453 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3453, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3454 = get_reg(cc, 8, false); + mov(cc, tmp3454, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3438, (ret_val_get_sew_pow_3437))), 8, false), ~ 1); - setArg(call_get_sew_pow_3437, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3437, 0, ret_val_get_sew_pow_3437); + (gen_operation(cc, shl, tmp3454, (ret_val_get_sew_pow_3453))), 8, false), ~ 1); + setArg(call_get_sew_pow_3453, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3453, 0, ret_val_get_sew_pow_3453); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3439; - auto illegal_fp_normal_3439_arg2 = SEW; - auto illegal_fp_normal_3439_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3439 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3439, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3439; - setArg(call_illegal_fp_normal_3439, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3439, 1, vd); - setArg(call_illegal_fp_normal_3439, 2, vm); - setArg(call_illegal_fp_normal_3439, 3, illegal_fp_normal_3439_arg2); - setArg(call_illegal_fp_normal_3439, 4, illegal_fp_normal_3439_arg3); - setRet(call_illegal_fp_normal_3439, 0, ret_val_illegal_fp_normal_3439); + InvokeNode* call_illegal_fp_normal_3455; + auto illegal_fp_normal_3455_arg2 = SEW; + auto illegal_fp_normal_3455_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3455 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3455, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3455; + setArg(call_illegal_fp_normal_3455, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3455, 1, vd); + setArg(call_illegal_fp_normal_3455, 2, vm); + setArg(call_illegal_fp_normal_3455, 3, illegal_fp_normal_3455_arg2); + setArg(call_illegal_fp_normal_3455, 4, illegal_fp_normal_3455_arg3); + setRet(call_illegal_fp_normal_3455, 0, ret_val_illegal_fp_normal_3455); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -80999,45 +80533,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3441; - x86::Gp ret_val_sew_3441 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3441, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3440; - auto fp_vector_vector_op_3440_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3440_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3440_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3440_arg10 = rm; - auto fp_vector_vector_op_3440_arg11 = ret_val_sew_3441; + InvokeNode* call_sew_3457; + x86::Gp ret_val_sew_3457 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3457, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3456; + auto fp_vector_vector_op_3456_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3456_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3456_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3456_arg10 = rm; + auto fp_vector_vector_op_3456_arg11 = ret_val_sew_3457; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3440, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3441, 0, reinterpret_cast(this)); - setRet(call_sew_3441, 0, ret_val_sew_3441); - setArg(call_fp_vector_vector_op_3440, 0, V); - setArg(call_fp_vector_vector_op_3440, 1, 41); - setArg(call_fp_vector_vector_op_3440, 2, 1); - setArg(call_fp_vector_vector_op_3440, 3, fp_vector_vector_op_3440_arg3); - setArg(call_fp_vector_vector_op_3440, 4, fp_vector_vector_op_3440_arg4); - setArg(call_fp_vector_vector_op_3440, 5, fp_vector_vector_op_3440_arg5); - setArg(call_fp_vector_vector_op_3440, 6, vm); - setArg(call_fp_vector_vector_op_3440, 7, vd); - setArg(call_fp_vector_vector_op_3440, 8, vs2); - setArg(call_fp_vector_vector_op_3440, 9, vs1); - setArg(call_fp_vector_vector_op_3440, 10, fp_vector_vector_op_3440_arg10); - setArg(call_fp_vector_vector_op_3440, 11, fp_vector_vector_op_3440_arg11); - InvokeNode* call_fget_flags_3442; - x86::Gp ret_val_fget_flags_3442 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3442, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3442; - setRet(call_fget_flags_3442, 0, ret_val_fget_flags_3442); + cc.invoke(&call_fp_vector_vector_op_3456, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3457, 0, reinterpret_cast(this)); + setRet(call_sew_3457, 0, ret_val_sew_3457); + setArg(call_fp_vector_vector_op_3456, 0, V); + setArg(call_fp_vector_vector_op_3456, 1, 41); + setArg(call_fp_vector_vector_op_3456, 2, 1); + setArg(call_fp_vector_vector_op_3456, 3, fp_vector_vector_op_3456_arg3); + setArg(call_fp_vector_vector_op_3456, 4, fp_vector_vector_op_3456_arg4); + setArg(call_fp_vector_vector_op_3456, 5, fp_vector_vector_op_3456_arg5); + setArg(call_fp_vector_vector_op_3456, 6, vm); + setArg(call_fp_vector_vector_op_3456, 7, vd); + setArg(call_fp_vector_vector_op_3456, 8, vs2); + setArg(call_fp_vector_vector_op_3456, 9, vs1); + setArg(call_fp_vector_vector_op_3456, 10, fp_vector_vector_op_3456_arg10); + setArg(call_fp_vector_vector_op_3456, 11, fp_vector_vector_op_3456_arg11); + InvokeNode* call_fget_flags_3458; + x86::Gp ret_val_fget_flags_3458 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3458, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3458; + setRet(call_fget_flags_3458, 0, ret_val_fget_flags_3458); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3443 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3443, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3443, 64, false) - , traits::vstart); + auto tmp3459 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3459, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3459, traits::vstart); } cc.bind(label_merge); } @@ -81081,30 +80613,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3444; - x86::Gp ret_val_get_sew_pow_3444 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3444, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3445 = get_reg(cc, 8, false); - mov(cc, tmp3445, 1); + InvokeNode* call_get_sew_pow_3460; + x86::Gp ret_val_get_sew_pow_3460 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3460, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3461 = get_reg(cc, 8, false); + mov(cc, tmp3461, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3445, (ret_val_get_sew_pow_3444))), 8, false), ~ 1); - setArg(call_get_sew_pow_3444, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3444, 0, ret_val_get_sew_pow_3444); + (gen_operation(cc, shl, tmp3461, (ret_val_get_sew_pow_3460))), 8, false), ~ 1); + setArg(call_get_sew_pow_3460, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3460, 0, ret_val_get_sew_pow_3460); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3446; - auto illegal_fp_normal_3446_arg2 = SEW; - auto illegal_fp_normal_3446_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3446 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3446, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3446; - setArg(call_illegal_fp_normal_3446, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3446, 1, vd); - setArg(call_illegal_fp_normal_3446, 2, vm); - setArg(call_illegal_fp_normal_3446, 3, illegal_fp_normal_3446_arg2); - setArg(call_illegal_fp_normal_3446, 4, illegal_fp_normal_3446_arg3); - setRet(call_illegal_fp_normal_3446, 0, ret_val_illegal_fp_normal_3446); + InvokeNode* call_illegal_fp_normal_3462; + auto illegal_fp_normal_3462_arg2 = SEW; + auto illegal_fp_normal_3462_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3462 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3462, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3462; + setArg(call_illegal_fp_normal_3462, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3462, 1, vd); + setArg(call_illegal_fp_normal_3462, 2, vm); + setArg(call_illegal_fp_normal_3462, 3, illegal_fp_normal_3462_arg2); + setArg(call_illegal_fp_normal_3462, 4, illegal_fp_normal_3462_arg3); + setRet(call_illegal_fp_normal_3462, 0, ret_val_illegal_fp_normal_3462); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81120,47 +80652,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3448; - x86::Gp ret_val_sew_3448 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3448, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3447; - auto fp_vector_imm_op_3447_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3447_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3447_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3447_arg9 = gen_ext(cc, + InvokeNode* call_sew_3464; + x86::Gp ret_val_sew_3464 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3464, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3463; + auto fp_vector_imm_op_3463_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3463_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3463_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3463_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3447_arg10 = rm; - auto fp_vector_imm_op_3447_arg11 = ret_val_sew_3448; + auto fp_vector_imm_op_3463_arg10 = rm; + auto fp_vector_imm_op_3463_arg11 = ret_val_sew_3464; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3447, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3448, 0, reinterpret_cast(this)); - setRet(call_sew_3448, 0, ret_val_sew_3448); - setArg(call_fp_vector_imm_op_3447, 0, V); - setArg(call_fp_vector_imm_op_3447, 1, 42); - setArg(call_fp_vector_imm_op_3447, 2, 5); - setArg(call_fp_vector_imm_op_3447, 3, fp_vector_imm_op_3447_arg3); - setArg(call_fp_vector_imm_op_3447, 4, fp_vector_imm_op_3447_arg4); - setArg(call_fp_vector_imm_op_3447, 5, fp_vector_imm_op_3447_arg5); - setArg(call_fp_vector_imm_op_3447, 6, vm); - setArg(call_fp_vector_imm_op_3447, 7, vd); - setArg(call_fp_vector_imm_op_3447, 8, vs2); - setArg(call_fp_vector_imm_op_3447, 9, fp_vector_imm_op_3447_arg9); - setArg(call_fp_vector_imm_op_3447, 10, fp_vector_imm_op_3447_arg10); - setArg(call_fp_vector_imm_op_3447, 11, fp_vector_imm_op_3447_arg11); - InvokeNode* call_fget_flags_3449; - x86::Gp ret_val_fget_flags_3449 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3449, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3449; - setRet(call_fget_flags_3449, 0, ret_val_fget_flags_3449); + cc.invoke(&call_fp_vector_imm_op_3463, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3464, 0, reinterpret_cast(this)); + setRet(call_sew_3464, 0, ret_val_sew_3464); + setArg(call_fp_vector_imm_op_3463, 0, V); + setArg(call_fp_vector_imm_op_3463, 1, 42); + setArg(call_fp_vector_imm_op_3463, 2, 5); + setArg(call_fp_vector_imm_op_3463, 3, fp_vector_imm_op_3463_arg3); + setArg(call_fp_vector_imm_op_3463, 4, fp_vector_imm_op_3463_arg4); + setArg(call_fp_vector_imm_op_3463, 5, fp_vector_imm_op_3463_arg5); + setArg(call_fp_vector_imm_op_3463, 6, vm); + setArg(call_fp_vector_imm_op_3463, 7, vd); + setArg(call_fp_vector_imm_op_3463, 8, vs2); + setArg(call_fp_vector_imm_op_3463, 9, fp_vector_imm_op_3463_arg9); + setArg(call_fp_vector_imm_op_3463, 10, fp_vector_imm_op_3463_arg10); + setArg(call_fp_vector_imm_op_3463, 11, fp_vector_imm_op_3463_arg11); + InvokeNode* call_fget_flags_3465; + x86::Gp ret_val_fget_flags_3465 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3465, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3465; + setRet(call_fget_flags_3465, 0, ret_val_fget_flags_3465); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3450 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3450, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3450, 64, false) - , traits::vstart); + auto tmp3466 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3466, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3466, traits::vstart); } cc.bind(label_merge); } @@ -81204,30 +80734,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3451; - x86::Gp ret_val_get_sew_pow_3451 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3451, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3452 = get_reg(cc, 8, false); - mov(cc, tmp3452, 1); + InvokeNode* call_get_sew_pow_3467; + x86::Gp ret_val_get_sew_pow_3467 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3467, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3468 = get_reg(cc, 8, false); + mov(cc, tmp3468, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3452, (ret_val_get_sew_pow_3451))), 8, false), ~ 1); - setArg(call_get_sew_pow_3451, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3451, 0, ret_val_get_sew_pow_3451); + (gen_operation(cc, shl, tmp3468, (ret_val_get_sew_pow_3467))), 8, false), ~ 1); + setArg(call_get_sew_pow_3467, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3467, 0, ret_val_get_sew_pow_3467); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3453; - auto illegal_fp_normal_3453_arg2 = SEW; - auto illegal_fp_normal_3453_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3453 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3453, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3453; - setArg(call_illegal_fp_normal_3453, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3453, 1, vd); - setArg(call_illegal_fp_normal_3453, 2, vm); - setArg(call_illegal_fp_normal_3453, 3, illegal_fp_normal_3453_arg2); - setArg(call_illegal_fp_normal_3453, 4, illegal_fp_normal_3453_arg3); - setRet(call_illegal_fp_normal_3453, 0, ret_val_illegal_fp_normal_3453); + InvokeNode* call_illegal_fp_normal_3469; + auto illegal_fp_normal_3469_arg2 = SEW; + auto illegal_fp_normal_3469_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3469 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3469, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3469; + setArg(call_illegal_fp_normal_3469, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3469, 1, vd); + setArg(call_illegal_fp_normal_3469, 2, vm); + setArg(call_illegal_fp_normal_3469, 3, illegal_fp_normal_3469_arg2); + setArg(call_illegal_fp_normal_3469, 4, illegal_fp_normal_3469_arg3); + setRet(call_illegal_fp_normal_3469, 0, ret_val_illegal_fp_normal_3469); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81243,45 +80773,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3455; - x86::Gp ret_val_sew_3455 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3455, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3454; - auto fp_vector_vector_op_3454_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3454_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3454_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3454_arg10 = rm; - auto fp_vector_vector_op_3454_arg11 = ret_val_sew_3455; + InvokeNode* call_sew_3471; + x86::Gp ret_val_sew_3471 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3471, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3470; + auto fp_vector_vector_op_3470_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3470_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3470_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3470_arg10 = rm; + auto fp_vector_vector_op_3470_arg11 = ret_val_sew_3471; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3454, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3455, 0, reinterpret_cast(this)); - setRet(call_sew_3455, 0, ret_val_sew_3455); - setArg(call_fp_vector_vector_op_3454, 0, V); - setArg(call_fp_vector_vector_op_3454, 1, 42); - setArg(call_fp_vector_vector_op_3454, 2, 1); - setArg(call_fp_vector_vector_op_3454, 3, fp_vector_vector_op_3454_arg3); - setArg(call_fp_vector_vector_op_3454, 4, fp_vector_vector_op_3454_arg4); - setArg(call_fp_vector_vector_op_3454, 5, fp_vector_vector_op_3454_arg5); - setArg(call_fp_vector_vector_op_3454, 6, vm); - setArg(call_fp_vector_vector_op_3454, 7, vd); - setArg(call_fp_vector_vector_op_3454, 8, vs2); - setArg(call_fp_vector_vector_op_3454, 9, vs1); - setArg(call_fp_vector_vector_op_3454, 10, fp_vector_vector_op_3454_arg10); - setArg(call_fp_vector_vector_op_3454, 11, fp_vector_vector_op_3454_arg11); - InvokeNode* call_fget_flags_3456; - x86::Gp ret_val_fget_flags_3456 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3456, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3456; - setRet(call_fget_flags_3456, 0, ret_val_fget_flags_3456); + cc.invoke(&call_fp_vector_vector_op_3470, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3471, 0, reinterpret_cast(this)); + setRet(call_sew_3471, 0, ret_val_sew_3471); + setArg(call_fp_vector_vector_op_3470, 0, V); + setArg(call_fp_vector_vector_op_3470, 1, 42); + setArg(call_fp_vector_vector_op_3470, 2, 1); + setArg(call_fp_vector_vector_op_3470, 3, fp_vector_vector_op_3470_arg3); + setArg(call_fp_vector_vector_op_3470, 4, fp_vector_vector_op_3470_arg4); + setArg(call_fp_vector_vector_op_3470, 5, fp_vector_vector_op_3470_arg5); + setArg(call_fp_vector_vector_op_3470, 6, vm); + setArg(call_fp_vector_vector_op_3470, 7, vd); + setArg(call_fp_vector_vector_op_3470, 8, vs2); + setArg(call_fp_vector_vector_op_3470, 9, vs1); + setArg(call_fp_vector_vector_op_3470, 10, fp_vector_vector_op_3470_arg10); + setArg(call_fp_vector_vector_op_3470, 11, fp_vector_vector_op_3470_arg11); + InvokeNode* call_fget_flags_3472; + x86::Gp ret_val_fget_flags_3472 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3472, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3472; + setRet(call_fget_flags_3472, 0, ret_val_fget_flags_3472); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3457 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3457, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3457, 64, false) - , traits::vstart); + auto tmp3473 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3473, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3473, traits::vstart); } cc.bind(label_merge); } @@ -81325,30 +80853,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3458; - x86::Gp ret_val_get_sew_pow_3458 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3458, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3459 = get_reg(cc, 8, false); - mov(cc, tmp3459, 1); + InvokeNode* call_get_sew_pow_3474; + x86::Gp ret_val_get_sew_pow_3474 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3474, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3475 = get_reg(cc, 8, false); + mov(cc, tmp3475, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3459, (ret_val_get_sew_pow_3458))), 8, false), ~ 1); - setArg(call_get_sew_pow_3458, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3458, 0, ret_val_get_sew_pow_3458); + (gen_operation(cc, shl, tmp3475, (ret_val_get_sew_pow_3474))), 8, false), ~ 1); + setArg(call_get_sew_pow_3474, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3474, 0, ret_val_get_sew_pow_3474); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3460; - auto illegal_fp_normal_3460_arg2 = SEW; - auto illegal_fp_normal_3460_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3460 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3460, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3460; - setArg(call_illegal_fp_normal_3460, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3460, 1, vd); - setArg(call_illegal_fp_normal_3460, 2, vm); - setArg(call_illegal_fp_normal_3460, 3, illegal_fp_normal_3460_arg2); - setArg(call_illegal_fp_normal_3460, 4, illegal_fp_normal_3460_arg3); - setRet(call_illegal_fp_normal_3460, 0, ret_val_illegal_fp_normal_3460); + InvokeNode* call_illegal_fp_normal_3476; + auto illegal_fp_normal_3476_arg2 = SEW; + auto illegal_fp_normal_3476_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3476 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3476, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3476; + setArg(call_illegal_fp_normal_3476, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3476, 1, vd); + setArg(call_illegal_fp_normal_3476, 2, vm); + setArg(call_illegal_fp_normal_3476, 3, illegal_fp_normal_3476_arg2); + setArg(call_illegal_fp_normal_3476, 4, illegal_fp_normal_3476_arg3); + setRet(call_illegal_fp_normal_3476, 0, ret_val_illegal_fp_normal_3476); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81364,47 +80892,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3462; - x86::Gp ret_val_sew_3462 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3462, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3461; - auto fp_vector_imm_op_3461_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3461_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3461_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3461_arg9 = gen_ext(cc, + InvokeNode* call_sew_3478; + x86::Gp ret_val_sew_3478 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3478, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3477; + auto fp_vector_imm_op_3477_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3477_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3477_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3477_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3461_arg10 = rm; - auto fp_vector_imm_op_3461_arg11 = ret_val_sew_3462; + auto fp_vector_imm_op_3477_arg10 = rm; + auto fp_vector_imm_op_3477_arg11 = ret_val_sew_3478; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3461, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3462, 0, reinterpret_cast(this)); - setRet(call_sew_3462, 0, ret_val_sew_3462); - setArg(call_fp_vector_imm_op_3461, 0, V); - setArg(call_fp_vector_imm_op_3461, 1, 43); - setArg(call_fp_vector_imm_op_3461, 2, 5); - setArg(call_fp_vector_imm_op_3461, 3, fp_vector_imm_op_3461_arg3); - setArg(call_fp_vector_imm_op_3461, 4, fp_vector_imm_op_3461_arg4); - setArg(call_fp_vector_imm_op_3461, 5, fp_vector_imm_op_3461_arg5); - setArg(call_fp_vector_imm_op_3461, 6, vm); - setArg(call_fp_vector_imm_op_3461, 7, vd); - setArg(call_fp_vector_imm_op_3461, 8, vs2); - setArg(call_fp_vector_imm_op_3461, 9, fp_vector_imm_op_3461_arg9); - setArg(call_fp_vector_imm_op_3461, 10, fp_vector_imm_op_3461_arg10); - setArg(call_fp_vector_imm_op_3461, 11, fp_vector_imm_op_3461_arg11); - InvokeNode* call_fget_flags_3463; - x86::Gp ret_val_fget_flags_3463 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3463, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3463; - setRet(call_fget_flags_3463, 0, ret_val_fget_flags_3463); + cc.invoke(&call_fp_vector_imm_op_3477, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3478, 0, reinterpret_cast(this)); + setRet(call_sew_3478, 0, ret_val_sew_3478); + setArg(call_fp_vector_imm_op_3477, 0, V); + setArg(call_fp_vector_imm_op_3477, 1, 43); + setArg(call_fp_vector_imm_op_3477, 2, 5); + setArg(call_fp_vector_imm_op_3477, 3, fp_vector_imm_op_3477_arg3); + setArg(call_fp_vector_imm_op_3477, 4, fp_vector_imm_op_3477_arg4); + setArg(call_fp_vector_imm_op_3477, 5, fp_vector_imm_op_3477_arg5); + setArg(call_fp_vector_imm_op_3477, 6, vm); + setArg(call_fp_vector_imm_op_3477, 7, vd); + setArg(call_fp_vector_imm_op_3477, 8, vs2); + setArg(call_fp_vector_imm_op_3477, 9, fp_vector_imm_op_3477_arg9); + setArg(call_fp_vector_imm_op_3477, 10, fp_vector_imm_op_3477_arg10); + setArg(call_fp_vector_imm_op_3477, 11, fp_vector_imm_op_3477_arg11); + InvokeNode* call_fget_flags_3479; + x86::Gp ret_val_fget_flags_3479 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3479, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3479; + setRet(call_fget_flags_3479, 0, ret_val_fget_flags_3479); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3464 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3464, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3464, 64, false) - , traits::vstart); + auto tmp3480 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3480, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3480, traits::vstart); } cc.bind(label_merge); } @@ -81448,30 +80974,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3465; - x86::Gp ret_val_get_sew_pow_3465 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3465, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3466 = get_reg(cc, 8, false); - mov(cc, tmp3466, 1); + InvokeNode* call_get_sew_pow_3481; + x86::Gp ret_val_get_sew_pow_3481 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3481, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3482 = get_reg(cc, 8, false); + mov(cc, tmp3482, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3466, (ret_val_get_sew_pow_3465))), 8, false), ~ 1); - setArg(call_get_sew_pow_3465, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3465, 0, ret_val_get_sew_pow_3465); + (gen_operation(cc, shl, tmp3482, (ret_val_get_sew_pow_3481))), 8, false), ~ 1); + setArg(call_get_sew_pow_3481, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3481, 0, ret_val_get_sew_pow_3481); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3467; - auto illegal_fp_normal_3467_arg2 = SEW; - auto illegal_fp_normal_3467_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3467 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3467, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3467; - setArg(call_illegal_fp_normal_3467, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3467, 1, vd); - setArg(call_illegal_fp_normal_3467, 2, vm); - setArg(call_illegal_fp_normal_3467, 3, illegal_fp_normal_3467_arg2); - setArg(call_illegal_fp_normal_3467, 4, illegal_fp_normal_3467_arg3); - setRet(call_illegal_fp_normal_3467, 0, ret_val_illegal_fp_normal_3467); + InvokeNode* call_illegal_fp_normal_3483; + auto illegal_fp_normal_3483_arg2 = SEW; + auto illegal_fp_normal_3483_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3483 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3483, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3483; + setArg(call_illegal_fp_normal_3483, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3483, 1, vd); + setArg(call_illegal_fp_normal_3483, 2, vm); + setArg(call_illegal_fp_normal_3483, 3, illegal_fp_normal_3483_arg2); + setArg(call_illegal_fp_normal_3483, 4, illegal_fp_normal_3483_arg3); + setRet(call_illegal_fp_normal_3483, 0, ret_val_illegal_fp_normal_3483); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81487,45 +81013,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3469; - x86::Gp ret_val_sew_3469 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3469, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3468; - auto fp_vector_vector_op_3468_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3468_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3468_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3468_arg10 = rm; - auto fp_vector_vector_op_3468_arg11 = ret_val_sew_3469; + InvokeNode* call_sew_3485; + x86::Gp ret_val_sew_3485 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3485, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3484; + auto fp_vector_vector_op_3484_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3484_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3484_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3484_arg10 = rm; + auto fp_vector_vector_op_3484_arg11 = ret_val_sew_3485; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3468, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3469, 0, reinterpret_cast(this)); - setRet(call_sew_3469, 0, ret_val_sew_3469); - setArg(call_fp_vector_vector_op_3468, 0, V); - setArg(call_fp_vector_vector_op_3468, 1, 43); - setArg(call_fp_vector_vector_op_3468, 2, 1); - setArg(call_fp_vector_vector_op_3468, 3, fp_vector_vector_op_3468_arg3); - setArg(call_fp_vector_vector_op_3468, 4, fp_vector_vector_op_3468_arg4); - setArg(call_fp_vector_vector_op_3468, 5, fp_vector_vector_op_3468_arg5); - setArg(call_fp_vector_vector_op_3468, 6, vm); - setArg(call_fp_vector_vector_op_3468, 7, vd); - setArg(call_fp_vector_vector_op_3468, 8, vs2); - setArg(call_fp_vector_vector_op_3468, 9, vs1); - setArg(call_fp_vector_vector_op_3468, 10, fp_vector_vector_op_3468_arg10); - setArg(call_fp_vector_vector_op_3468, 11, fp_vector_vector_op_3468_arg11); - InvokeNode* call_fget_flags_3470; - x86::Gp ret_val_fget_flags_3470 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3470, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3470; - setRet(call_fget_flags_3470, 0, ret_val_fget_flags_3470); + cc.invoke(&call_fp_vector_vector_op_3484, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3485, 0, reinterpret_cast(this)); + setRet(call_sew_3485, 0, ret_val_sew_3485); + setArg(call_fp_vector_vector_op_3484, 0, V); + setArg(call_fp_vector_vector_op_3484, 1, 43); + setArg(call_fp_vector_vector_op_3484, 2, 1); + setArg(call_fp_vector_vector_op_3484, 3, fp_vector_vector_op_3484_arg3); + setArg(call_fp_vector_vector_op_3484, 4, fp_vector_vector_op_3484_arg4); + setArg(call_fp_vector_vector_op_3484, 5, fp_vector_vector_op_3484_arg5); + setArg(call_fp_vector_vector_op_3484, 6, vm); + setArg(call_fp_vector_vector_op_3484, 7, vd); + setArg(call_fp_vector_vector_op_3484, 8, vs2); + setArg(call_fp_vector_vector_op_3484, 9, vs1); + setArg(call_fp_vector_vector_op_3484, 10, fp_vector_vector_op_3484_arg10); + setArg(call_fp_vector_vector_op_3484, 11, fp_vector_vector_op_3484_arg11); + InvokeNode* call_fget_flags_3486; + x86::Gp ret_val_fget_flags_3486 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3486, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3486; + setRet(call_fget_flags_3486, 0, ret_val_fget_flags_3486); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3471 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3471, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3471, 64, false) - , traits::vstart); + auto tmp3487 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3487, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3487, traits::vstart); } cc.bind(label_merge); } @@ -81569,54 +81093,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3472; - x86::Gp ret_val_get_sew_pow_3472 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3472, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3473 = get_reg(cc, 8, false); - mov(cc, tmp3473, 1); + InvokeNode* call_get_sew_pow_3488; + x86::Gp ret_val_get_sew_pow_3488 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3488, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3489 = get_reg(cc, 8, false); + mov(cc, tmp3489, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3473, (ret_val_get_sew_pow_3472))), 8, false), ~ 1); - setArg(call_get_sew_pow_3472, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3472, 0, ret_val_get_sew_pow_3472); - InvokeNode* call_get_lmul_pow_3474; - x86::Gp ret_val_get_lmul_pow_3474 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3474, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3474; - setArg(call_get_lmul_pow_3474, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3474, 0, ret_val_get_lmul_pow_3474); + (gen_operation(cc, shl, tmp3489, (ret_val_get_sew_pow_3488))), 8, false), ~ 1); + setArg(call_get_sew_pow_3488, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3488, 0, ret_val_get_sew_pow_3488); + InvokeNode* call_get_lmul_pow_3490; + x86::Gp ret_val_get_lmul_pow_3490 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3490, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3490; + setArg(call_get_lmul_pow_3490, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3490, 0, ret_val_get_lmul_pow_3490); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3475; - auto illegal_fp_variable_width_3475_arg2 = SEW; - auto illegal_fp_variable_width_3475_arg3 = rm; - auto illegal_fp_variable_width_3475_arg4 = SEW_widen; - auto illegal_fp_variable_width_3475_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3475 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3475, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3476; - auto valid_reg_overlap_3476_arg2 = LMUL_pow; - auto valid_reg_overlap_3476_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3476 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3476, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3475, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3476)); - setArg(call_illegal_fp_variable_width_3475, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3475, 1, vd); - setArg(call_illegal_fp_variable_width_3475, 2, vm); - setArg(call_illegal_fp_variable_width_3475, 3, illegal_fp_variable_width_3475_arg2); - setArg(call_illegal_fp_variable_width_3475, 4, illegal_fp_variable_width_3475_arg3); - setArg(call_illegal_fp_variable_width_3475, 5, illegal_fp_variable_width_3475_arg4); - setArg(call_illegal_fp_variable_width_3475, 6, illegal_fp_variable_width_3475_arg5); - setRet(call_illegal_fp_variable_width_3475, 0, ret_val_illegal_fp_variable_width_3475); - setArg(call_valid_reg_overlap_3476, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3476, 1, vs2); - setArg(call_valid_reg_overlap_3476, 2, vd); - setArg(call_valid_reg_overlap_3476, 3, valid_reg_overlap_3476_arg2); - setArg(call_valid_reg_overlap_3476, 4, valid_reg_overlap_3476_arg3); - setRet(call_valid_reg_overlap_3476, 0, ret_val_valid_reg_overlap_3476); + InvokeNode* call_illegal_fp_variable_width_3491; + auto illegal_fp_variable_width_3491_arg2 = SEW; + auto illegal_fp_variable_width_3491_arg3 = rm; + auto illegal_fp_variable_width_3491_arg4 = SEW_widen; + auto illegal_fp_variable_width_3491_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3491 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3491, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3492; + auto valid_reg_overlap_3492_arg2 = LMUL_pow; + auto valid_reg_overlap_3492_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3492 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3492, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3491, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3492)); + setArg(call_illegal_fp_variable_width_3491, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3491, 1, vd); + setArg(call_illegal_fp_variable_width_3491, 2, vm); + setArg(call_illegal_fp_variable_width_3491, 3, illegal_fp_variable_width_3491_arg2); + setArg(call_illegal_fp_variable_width_3491, 4, illegal_fp_variable_width_3491_arg3); + setArg(call_illegal_fp_variable_width_3491, 5, illegal_fp_variable_width_3491_arg4); + setArg(call_illegal_fp_variable_width_3491, 6, illegal_fp_variable_width_3491_arg5); + setRet(call_illegal_fp_variable_width_3491, 0, ret_val_illegal_fp_variable_width_3491); + setArg(call_valid_reg_overlap_3492, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3492, 1, vs2); + setArg(call_valid_reg_overlap_3492, 2, vd); + setArg(call_valid_reg_overlap_3492, 3, valid_reg_overlap_3492_arg2); + setArg(call_valid_reg_overlap_3492, 4, valid_reg_overlap_3492_arg3); + setRet(call_valid_reg_overlap_3492, 0, ret_val_valid_reg_overlap_3492); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81632,47 +81156,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3478; - x86::Gp ret_val_sew_3478 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3478, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3477; - auto fp_vector_imm_wv_3477_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3477_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3477_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3477_arg9 = gen_ext(cc, + InvokeNode* call_sew_3494; + x86::Gp ret_val_sew_3494 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3494, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3493; + auto fp_vector_imm_wv_3493_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3493_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3493_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3493_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_wv_3477_arg10 = rm; - auto fp_vector_imm_wv_3477_arg11 = ret_val_sew_3478; + auto fp_vector_imm_wv_3493_arg10 = rm; + auto fp_vector_imm_wv_3493_arg11 = ret_val_sew_3494; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3477, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3478, 0, reinterpret_cast(this)); - setRet(call_sew_3478, 0, ret_val_sew_3478); - setArg(call_fp_vector_imm_wv_3477, 0, V); - setArg(call_fp_vector_imm_wv_3477, 1, 60); - setArg(call_fp_vector_imm_wv_3477, 2, 5); - setArg(call_fp_vector_imm_wv_3477, 3, fp_vector_imm_wv_3477_arg3); - setArg(call_fp_vector_imm_wv_3477, 4, fp_vector_imm_wv_3477_arg4); - setArg(call_fp_vector_imm_wv_3477, 5, fp_vector_imm_wv_3477_arg5); - setArg(call_fp_vector_imm_wv_3477, 6, vm); - setArg(call_fp_vector_imm_wv_3477, 7, vd); - setArg(call_fp_vector_imm_wv_3477, 8, vs2); - setArg(call_fp_vector_imm_wv_3477, 9, fp_vector_imm_wv_3477_arg9); - setArg(call_fp_vector_imm_wv_3477, 10, fp_vector_imm_wv_3477_arg10); - setArg(call_fp_vector_imm_wv_3477, 11, fp_vector_imm_wv_3477_arg11); - InvokeNode* call_fget_flags_3479; - x86::Gp ret_val_fget_flags_3479 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3479, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3479; - setRet(call_fget_flags_3479, 0, ret_val_fget_flags_3479); + cc.invoke(&call_fp_vector_imm_wv_3493, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3494, 0, reinterpret_cast(this)); + setRet(call_sew_3494, 0, ret_val_sew_3494); + setArg(call_fp_vector_imm_wv_3493, 0, V); + setArg(call_fp_vector_imm_wv_3493, 1, 60); + setArg(call_fp_vector_imm_wv_3493, 2, 5); + setArg(call_fp_vector_imm_wv_3493, 3, fp_vector_imm_wv_3493_arg3); + setArg(call_fp_vector_imm_wv_3493, 4, fp_vector_imm_wv_3493_arg4); + setArg(call_fp_vector_imm_wv_3493, 5, fp_vector_imm_wv_3493_arg5); + setArg(call_fp_vector_imm_wv_3493, 6, vm); + setArg(call_fp_vector_imm_wv_3493, 7, vd); + setArg(call_fp_vector_imm_wv_3493, 8, vs2); + setArg(call_fp_vector_imm_wv_3493, 9, fp_vector_imm_wv_3493_arg9); + setArg(call_fp_vector_imm_wv_3493, 10, fp_vector_imm_wv_3493_arg10); + setArg(call_fp_vector_imm_wv_3493, 11, fp_vector_imm_wv_3493_arg11); + InvokeNode* call_fget_flags_3495; + x86::Gp ret_val_fget_flags_3495 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3495, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3495; + setRet(call_fget_flags_3495, 0, ret_val_fget_flags_3495); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3480 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3480, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3480, 64, false) - , traits::vstart); + auto tmp3496 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3496, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3496, traits::vstart); } cc.bind(label_merge); } @@ -81716,65 +81238,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3481; - x86::Gp ret_val_get_sew_pow_3481 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3481, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3482 = get_reg(cc, 8, false); - mov(cc, tmp3482, 1); + InvokeNode* call_get_sew_pow_3497; + x86::Gp ret_val_get_sew_pow_3497 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3497, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3498 = get_reg(cc, 8, false); + mov(cc, tmp3498, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3482, (ret_val_get_sew_pow_3481))), 8, false), ~ 1); - setArg(call_get_sew_pow_3481, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3481, 0, ret_val_get_sew_pow_3481); - InvokeNode* call_get_lmul_pow_3483; - x86::Gp ret_val_get_lmul_pow_3483 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3483, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3483; - setArg(call_get_lmul_pow_3483, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3483, 0, ret_val_get_lmul_pow_3483); + (gen_operation(cc, shl, tmp3498, (ret_val_get_sew_pow_3497))), 8, false), ~ 1); + setArg(call_get_sew_pow_3497, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3497, 0, ret_val_get_sew_pow_3497); + InvokeNode* call_get_lmul_pow_3499; + x86::Gp ret_val_get_lmul_pow_3499 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3499, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3499; + setArg(call_get_lmul_pow_3499, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3499, 0, ret_val_get_lmul_pow_3499); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3484; - auto illegal_fp_variable_width_3484_arg2 = SEW; - auto illegal_fp_variable_width_3484_arg3 = rm; - auto illegal_fp_variable_width_3484_arg4 = SEW_widen; - auto illegal_fp_variable_width_3484_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3484 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3484, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3485; - auto valid_reg_overlap_3485_arg2 = LMUL_pow; - auto valid_reg_overlap_3485_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3485 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3485, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3486; - auto valid_reg_overlap_3486_arg2 = LMUL_pow; - auto valid_reg_overlap_3486_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3486 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3486, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3484, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3485)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3486)); - setArg(call_illegal_fp_variable_width_3484, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3484, 1, vd); - setArg(call_illegal_fp_variable_width_3484, 2, vm); - setArg(call_illegal_fp_variable_width_3484, 3, illegal_fp_variable_width_3484_arg2); - setArg(call_illegal_fp_variable_width_3484, 4, illegal_fp_variable_width_3484_arg3); - setArg(call_illegal_fp_variable_width_3484, 5, illegal_fp_variable_width_3484_arg4); - setArg(call_illegal_fp_variable_width_3484, 6, illegal_fp_variable_width_3484_arg5); - setRet(call_illegal_fp_variable_width_3484, 0, ret_val_illegal_fp_variable_width_3484); - setArg(call_valid_reg_overlap_3485, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3485, 1, vs1); - setArg(call_valid_reg_overlap_3485, 2, vd); - setArg(call_valid_reg_overlap_3485, 3, valid_reg_overlap_3485_arg2); - setArg(call_valid_reg_overlap_3485, 4, valid_reg_overlap_3485_arg3); - setRet(call_valid_reg_overlap_3485, 0, ret_val_valid_reg_overlap_3485); - setArg(call_valid_reg_overlap_3486, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3486, 1, vs2); - setArg(call_valid_reg_overlap_3486, 2, vd); - setArg(call_valid_reg_overlap_3486, 3, valid_reg_overlap_3486_arg2); - setArg(call_valid_reg_overlap_3486, 4, valid_reg_overlap_3486_arg3); - setRet(call_valid_reg_overlap_3486, 0, ret_val_valid_reg_overlap_3486); + InvokeNode* call_illegal_fp_variable_width_3500; + auto illegal_fp_variable_width_3500_arg2 = SEW; + auto illegal_fp_variable_width_3500_arg3 = rm; + auto illegal_fp_variable_width_3500_arg4 = SEW_widen; + auto illegal_fp_variable_width_3500_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3500 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3500, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3501; + auto valid_reg_overlap_3501_arg2 = LMUL_pow; + auto valid_reg_overlap_3501_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3501 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3501, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3502; + auto valid_reg_overlap_3502_arg2 = LMUL_pow; + auto valid_reg_overlap_3502_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3502 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3502, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3500, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3501)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3502)); + setArg(call_illegal_fp_variable_width_3500, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3500, 1, vd); + setArg(call_illegal_fp_variable_width_3500, 2, vm); + setArg(call_illegal_fp_variable_width_3500, 3, illegal_fp_variable_width_3500_arg2); + setArg(call_illegal_fp_variable_width_3500, 4, illegal_fp_variable_width_3500_arg3); + setArg(call_illegal_fp_variable_width_3500, 5, illegal_fp_variable_width_3500_arg4); + setArg(call_illegal_fp_variable_width_3500, 6, illegal_fp_variable_width_3500_arg5); + setRet(call_illegal_fp_variable_width_3500, 0, ret_val_illegal_fp_variable_width_3500); + setArg(call_valid_reg_overlap_3501, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3501, 1, vs1); + setArg(call_valid_reg_overlap_3501, 2, vd); + setArg(call_valid_reg_overlap_3501, 3, valid_reg_overlap_3501_arg2); + setArg(call_valid_reg_overlap_3501, 4, valid_reg_overlap_3501_arg3); + setRet(call_valid_reg_overlap_3501, 0, ret_val_valid_reg_overlap_3501); + setArg(call_valid_reg_overlap_3502, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3502, 1, vs2); + setArg(call_valid_reg_overlap_3502, 2, vd); + setArg(call_valid_reg_overlap_3502, 3, valid_reg_overlap_3502_arg2); + setArg(call_valid_reg_overlap_3502, 4, valid_reg_overlap_3502_arg3); + setRet(call_valid_reg_overlap_3502, 0, ret_val_valid_reg_overlap_3502); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81790,45 +81312,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3488; - x86::Gp ret_val_sew_3488 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3488, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3487; - auto fp_vector_vector_wv_3487_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3487_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3487_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3487_arg10 = rm; - auto fp_vector_vector_wv_3487_arg11 = ret_val_sew_3488; + InvokeNode* call_sew_3504; + x86::Gp ret_val_sew_3504 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3504, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3503; + auto fp_vector_vector_wv_3503_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3503_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3503_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3503_arg10 = rm; + auto fp_vector_vector_wv_3503_arg11 = ret_val_sew_3504; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3487, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3488, 0, reinterpret_cast(this)); - setRet(call_sew_3488, 0, ret_val_sew_3488); - setArg(call_fp_vector_vector_wv_3487, 0, V); - setArg(call_fp_vector_vector_wv_3487, 1, 60); - setArg(call_fp_vector_vector_wv_3487, 2, 1); - setArg(call_fp_vector_vector_wv_3487, 3, fp_vector_vector_wv_3487_arg3); - setArg(call_fp_vector_vector_wv_3487, 4, fp_vector_vector_wv_3487_arg4); - setArg(call_fp_vector_vector_wv_3487, 5, fp_vector_vector_wv_3487_arg5); - setArg(call_fp_vector_vector_wv_3487, 6, vm); - setArg(call_fp_vector_vector_wv_3487, 7, vd); - setArg(call_fp_vector_vector_wv_3487, 8, vs2); - setArg(call_fp_vector_vector_wv_3487, 9, vs1); - setArg(call_fp_vector_vector_wv_3487, 10, fp_vector_vector_wv_3487_arg10); - setArg(call_fp_vector_vector_wv_3487, 11, fp_vector_vector_wv_3487_arg11); - InvokeNode* call_fget_flags_3489; - x86::Gp ret_val_fget_flags_3489 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3489, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3489; - setRet(call_fget_flags_3489, 0, ret_val_fget_flags_3489); + cc.invoke(&call_fp_vector_vector_wv_3503, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3504, 0, reinterpret_cast(this)); + setRet(call_sew_3504, 0, ret_val_sew_3504); + setArg(call_fp_vector_vector_wv_3503, 0, V); + setArg(call_fp_vector_vector_wv_3503, 1, 60); + setArg(call_fp_vector_vector_wv_3503, 2, 1); + setArg(call_fp_vector_vector_wv_3503, 3, fp_vector_vector_wv_3503_arg3); + setArg(call_fp_vector_vector_wv_3503, 4, fp_vector_vector_wv_3503_arg4); + setArg(call_fp_vector_vector_wv_3503, 5, fp_vector_vector_wv_3503_arg5); + setArg(call_fp_vector_vector_wv_3503, 6, vm); + setArg(call_fp_vector_vector_wv_3503, 7, vd); + setArg(call_fp_vector_vector_wv_3503, 8, vs2); + setArg(call_fp_vector_vector_wv_3503, 9, vs1); + setArg(call_fp_vector_vector_wv_3503, 10, fp_vector_vector_wv_3503_arg10); + setArg(call_fp_vector_vector_wv_3503, 11, fp_vector_vector_wv_3503_arg11); + InvokeNode* call_fget_flags_3505; + x86::Gp ret_val_fget_flags_3505 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3505, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3505; + setRet(call_fget_flags_3505, 0, ret_val_fget_flags_3505); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3490 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3490, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3490, 64, false) - , traits::vstart); + auto tmp3506 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3506, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3506, traits::vstart); } cc.bind(label_merge); } @@ -81872,54 +81392,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3491; - x86::Gp ret_val_get_sew_pow_3491 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3491, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3492 = get_reg(cc, 8, false); - mov(cc, tmp3492, 1); + InvokeNode* call_get_sew_pow_3507; + x86::Gp ret_val_get_sew_pow_3507 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3507, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3508 = get_reg(cc, 8, false); + mov(cc, tmp3508, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3492, (ret_val_get_sew_pow_3491))), 8, false), ~ 1); - setArg(call_get_sew_pow_3491, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3491, 0, ret_val_get_sew_pow_3491); - InvokeNode* call_get_lmul_pow_3493; - x86::Gp ret_val_get_lmul_pow_3493 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3493, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3493; - setArg(call_get_lmul_pow_3493, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3493, 0, ret_val_get_lmul_pow_3493); + (gen_operation(cc, shl, tmp3508, (ret_val_get_sew_pow_3507))), 8, false), ~ 1); + setArg(call_get_sew_pow_3507, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3507, 0, ret_val_get_sew_pow_3507); + InvokeNode* call_get_lmul_pow_3509; + x86::Gp ret_val_get_lmul_pow_3509 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3509, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3509; + setArg(call_get_lmul_pow_3509, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3509, 0, ret_val_get_lmul_pow_3509); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3494; - auto illegal_fp_variable_width_3494_arg2 = SEW; - auto illegal_fp_variable_width_3494_arg3 = rm; - auto illegal_fp_variable_width_3494_arg4 = SEW_widen; - auto illegal_fp_variable_width_3494_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3494 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3494, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3495; - auto valid_reg_overlap_3495_arg2 = LMUL_pow; - auto valid_reg_overlap_3495_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3495 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3495, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3494, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3495)); - setArg(call_illegal_fp_variable_width_3494, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3494, 1, vd); - setArg(call_illegal_fp_variable_width_3494, 2, vm); - setArg(call_illegal_fp_variable_width_3494, 3, illegal_fp_variable_width_3494_arg2); - setArg(call_illegal_fp_variable_width_3494, 4, illegal_fp_variable_width_3494_arg3); - setArg(call_illegal_fp_variable_width_3494, 5, illegal_fp_variable_width_3494_arg4); - setArg(call_illegal_fp_variable_width_3494, 6, illegal_fp_variable_width_3494_arg5); - setRet(call_illegal_fp_variable_width_3494, 0, ret_val_illegal_fp_variable_width_3494); - setArg(call_valid_reg_overlap_3495, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3495, 1, vs2); - setArg(call_valid_reg_overlap_3495, 2, vd); - setArg(call_valid_reg_overlap_3495, 3, valid_reg_overlap_3495_arg2); - setArg(call_valid_reg_overlap_3495, 4, valid_reg_overlap_3495_arg3); - setRet(call_valid_reg_overlap_3495, 0, ret_val_valid_reg_overlap_3495); + InvokeNode* call_illegal_fp_variable_width_3510; + auto illegal_fp_variable_width_3510_arg2 = SEW; + auto illegal_fp_variable_width_3510_arg3 = rm; + auto illegal_fp_variable_width_3510_arg4 = SEW_widen; + auto illegal_fp_variable_width_3510_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3510 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3510, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3511; + auto valid_reg_overlap_3511_arg2 = LMUL_pow; + auto valid_reg_overlap_3511_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3511 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3511, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3510, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3511)); + setArg(call_illegal_fp_variable_width_3510, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3510, 1, vd); + setArg(call_illegal_fp_variable_width_3510, 2, vm); + setArg(call_illegal_fp_variable_width_3510, 3, illegal_fp_variable_width_3510_arg2); + setArg(call_illegal_fp_variable_width_3510, 4, illegal_fp_variable_width_3510_arg3); + setArg(call_illegal_fp_variable_width_3510, 5, illegal_fp_variable_width_3510_arg4); + setArg(call_illegal_fp_variable_width_3510, 6, illegal_fp_variable_width_3510_arg5); + setRet(call_illegal_fp_variable_width_3510, 0, ret_val_illegal_fp_variable_width_3510); + setArg(call_valid_reg_overlap_3511, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3511, 1, vs2); + setArg(call_valid_reg_overlap_3511, 2, vd); + setArg(call_valid_reg_overlap_3511, 3, valid_reg_overlap_3511_arg2); + setArg(call_valid_reg_overlap_3511, 4, valid_reg_overlap_3511_arg3); + setRet(call_valid_reg_overlap_3511, 0, ret_val_valid_reg_overlap_3511); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -81935,47 +81455,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3497; - x86::Gp ret_val_sew_3497 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3497, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3496; - auto fp_vector_imm_wv_3496_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3496_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3496_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3496_arg9 = gen_ext(cc, + InvokeNode* call_sew_3513; + x86::Gp ret_val_sew_3513 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3513, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3512; + auto fp_vector_imm_wv_3512_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3512_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3512_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3512_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_wv_3496_arg10 = rm; - auto fp_vector_imm_wv_3496_arg11 = ret_val_sew_3497; + auto fp_vector_imm_wv_3512_arg10 = rm; + auto fp_vector_imm_wv_3512_arg11 = ret_val_sew_3513; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3496, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3497, 0, reinterpret_cast(this)); - setRet(call_sew_3497, 0, ret_val_sew_3497); - setArg(call_fp_vector_imm_wv_3496, 0, V); - setArg(call_fp_vector_imm_wv_3496, 1, 61); - setArg(call_fp_vector_imm_wv_3496, 2, 5); - setArg(call_fp_vector_imm_wv_3496, 3, fp_vector_imm_wv_3496_arg3); - setArg(call_fp_vector_imm_wv_3496, 4, fp_vector_imm_wv_3496_arg4); - setArg(call_fp_vector_imm_wv_3496, 5, fp_vector_imm_wv_3496_arg5); - setArg(call_fp_vector_imm_wv_3496, 6, vm); - setArg(call_fp_vector_imm_wv_3496, 7, vd); - setArg(call_fp_vector_imm_wv_3496, 8, vs2); - setArg(call_fp_vector_imm_wv_3496, 9, fp_vector_imm_wv_3496_arg9); - setArg(call_fp_vector_imm_wv_3496, 10, fp_vector_imm_wv_3496_arg10); - setArg(call_fp_vector_imm_wv_3496, 11, fp_vector_imm_wv_3496_arg11); - InvokeNode* call_fget_flags_3498; - x86::Gp ret_val_fget_flags_3498 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3498, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3498; - setRet(call_fget_flags_3498, 0, ret_val_fget_flags_3498); + cc.invoke(&call_fp_vector_imm_wv_3512, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3513, 0, reinterpret_cast(this)); + setRet(call_sew_3513, 0, ret_val_sew_3513); + setArg(call_fp_vector_imm_wv_3512, 0, V); + setArg(call_fp_vector_imm_wv_3512, 1, 61); + setArg(call_fp_vector_imm_wv_3512, 2, 5); + setArg(call_fp_vector_imm_wv_3512, 3, fp_vector_imm_wv_3512_arg3); + setArg(call_fp_vector_imm_wv_3512, 4, fp_vector_imm_wv_3512_arg4); + setArg(call_fp_vector_imm_wv_3512, 5, fp_vector_imm_wv_3512_arg5); + setArg(call_fp_vector_imm_wv_3512, 6, vm); + setArg(call_fp_vector_imm_wv_3512, 7, vd); + setArg(call_fp_vector_imm_wv_3512, 8, vs2); + setArg(call_fp_vector_imm_wv_3512, 9, fp_vector_imm_wv_3512_arg9); + setArg(call_fp_vector_imm_wv_3512, 10, fp_vector_imm_wv_3512_arg10); + setArg(call_fp_vector_imm_wv_3512, 11, fp_vector_imm_wv_3512_arg11); + InvokeNode* call_fget_flags_3514; + x86::Gp ret_val_fget_flags_3514 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3514, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3514; + setRet(call_fget_flags_3514, 0, ret_val_fget_flags_3514); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3499 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3499, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3499, 64, false) - , traits::vstart); + auto tmp3515 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3515, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3515, traits::vstart); } cc.bind(label_merge); } @@ -82019,65 +81537,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3500; - x86::Gp ret_val_get_sew_pow_3500 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3500, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3501 = get_reg(cc, 8, false); - mov(cc, tmp3501, 1); + InvokeNode* call_get_sew_pow_3516; + x86::Gp ret_val_get_sew_pow_3516 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3516, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3517 = get_reg(cc, 8, false); + mov(cc, tmp3517, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3501, (ret_val_get_sew_pow_3500))), 8, false), ~ 1); - setArg(call_get_sew_pow_3500, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3500, 0, ret_val_get_sew_pow_3500); - InvokeNode* call_get_lmul_pow_3502; - x86::Gp ret_val_get_lmul_pow_3502 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3502, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3502; - setArg(call_get_lmul_pow_3502, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3502, 0, ret_val_get_lmul_pow_3502); + (gen_operation(cc, shl, tmp3517, (ret_val_get_sew_pow_3516))), 8, false), ~ 1); + setArg(call_get_sew_pow_3516, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3516, 0, ret_val_get_sew_pow_3516); + InvokeNode* call_get_lmul_pow_3518; + x86::Gp ret_val_get_lmul_pow_3518 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3518, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3518; + setArg(call_get_lmul_pow_3518, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3518, 0, ret_val_get_lmul_pow_3518); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3503; - auto illegal_fp_variable_width_3503_arg2 = SEW; - auto illegal_fp_variable_width_3503_arg3 = rm; - auto illegal_fp_variable_width_3503_arg4 = SEW_widen; - auto illegal_fp_variable_width_3503_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3503 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3503, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3504; - auto valid_reg_overlap_3504_arg2 = LMUL_pow; - auto valid_reg_overlap_3504_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3504 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3504, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3505; - auto valid_reg_overlap_3505_arg2 = LMUL_pow; - auto valid_reg_overlap_3505_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3505 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3505, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3503, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3504)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3505)); - setArg(call_illegal_fp_variable_width_3503, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3503, 1, vd); - setArg(call_illegal_fp_variable_width_3503, 2, vm); - setArg(call_illegal_fp_variable_width_3503, 3, illegal_fp_variable_width_3503_arg2); - setArg(call_illegal_fp_variable_width_3503, 4, illegal_fp_variable_width_3503_arg3); - setArg(call_illegal_fp_variable_width_3503, 5, illegal_fp_variable_width_3503_arg4); - setArg(call_illegal_fp_variable_width_3503, 6, illegal_fp_variable_width_3503_arg5); - setRet(call_illegal_fp_variable_width_3503, 0, ret_val_illegal_fp_variable_width_3503); - setArg(call_valid_reg_overlap_3504, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3504, 1, vs1); - setArg(call_valid_reg_overlap_3504, 2, vd); - setArg(call_valid_reg_overlap_3504, 3, valid_reg_overlap_3504_arg2); - setArg(call_valid_reg_overlap_3504, 4, valid_reg_overlap_3504_arg3); - setRet(call_valid_reg_overlap_3504, 0, ret_val_valid_reg_overlap_3504); - setArg(call_valid_reg_overlap_3505, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3505, 1, vs2); - setArg(call_valid_reg_overlap_3505, 2, vd); - setArg(call_valid_reg_overlap_3505, 3, valid_reg_overlap_3505_arg2); - setArg(call_valid_reg_overlap_3505, 4, valid_reg_overlap_3505_arg3); - setRet(call_valid_reg_overlap_3505, 0, ret_val_valid_reg_overlap_3505); + InvokeNode* call_illegal_fp_variable_width_3519; + auto illegal_fp_variable_width_3519_arg2 = SEW; + auto illegal_fp_variable_width_3519_arg3 = rm; + auto illegal_fp_variable_width_3519_arg4 = SEW_widen; + auto illegal_fp_variable_width_3519_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3519 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3519, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3520; + auto valid_reg_overlap_3520_arg2 = LMUL_pow; + auto valid_reg_overlap_3520_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3520 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3520, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3521; + auto valid_reg_overlap_3521_arg2 = LMUL_pow; + auto valid_reg_overlap_3521_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3521 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3521, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3519, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3520)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3521)); + setArg(call_illegal_fp_variable_width_3519, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3519, 1, vd); + setArg(call_illegal_fp_variable_width_3519, 2, vm); + setArg(call_illegal_fp_variable_width_3519, 3, illegal_fp_variable_width_3519_arg2); + setArg(call_illegal_fp_variable_width_3519, 4, illegal_fp_variable_width_3519_arg3); + setArg(call_illegal_fp_variable_width_3519, 5, illegal_fp_variable_width_3519_arg4); + setArg(call_illegal_fp_variable_width_3519, 6, illegal_fp_variable_width_3519_arg5); + setRet(call_illegal_fp_variable_width_3519, 0, ret_val_illegal_fp_variable_width_3519); + setArg(call_valid_reg_overlap_3520, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3520, 1, vs1); + setArg(call_valid_reg_overlap_3520, 2, vd); + setArg(call_valid_reg_overlap_3520, 3, valid_reg_overlap_3520_arg2); + setArg(call_valid_reg_overlap_3520, 4, valid_reg_overlap_3520_arg3); + setRet(call_valid_reg_overlap_3520, 0, ret_val_valid_reg_overlap_3520); + setArg(call_valid_reg_overlap_3521, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3521, 1, vs2); + setArg(call_valid_reg_overlap_3521, 2, vd); + setArg(call_valid_reg_overlap_3521, 3, valid_reg_overlap_3521_arg2); + setArg(call_valid_reg_overlap_3521, 4, valid_reg_overlap_3521_arg3); + setRet(call_valid_reg_overlap_3521, 0, ret_val_valid_reg_overlap_3521); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82093,45 +81611,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3507; - x86::Gp ret_val_sew_3507 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3507, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3506; - auto fp_vector_vector_wv_3506_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3506_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3506_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3506_arg10 = rm; - auto fp_vector_vector_wv_3506_arg11 = ret_val_sew_3507; + InvokeNode* call_sew_3523; + x86::Gp ret_val_sew_3523 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3523, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3522; + auto fp_vector_vector_wv_3522_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3522_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3522_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3522_arg10 = rm; + auto fp_vector_vector_wv_3522_arg11 = ret_val_sew_3523; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3506, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3507, 0, reinterpret_cast(this)); - setRet(call_sew_3507, 0, ret_val_sew_3507); - setArg(call_fp_vector_vector_wv_3506, 0, V); - setArg(call_fp_vector_vector_wv_3506, 1, 61); - setArg(call_fp_vector_vector_wv_3506, 2, 1); - setArg(call_fp_vector_vector_wv_3506, 3, fp_vector_vector_wv_3506_arg3); - setArg(call_fp_vector_vector_wv_3506, 4, fp_vector_vector_wv_3506_arg4); - setArg(call_fp_vector_vector_wv_3506, 5, fp_vector_vector_wv_3506_arg5); - setArg(call_fp_vector_vector_wv_3506, 6, vm); - setArg(call_fp_vector_vector_wv_3506, 7, vd); - setArg(call_fp_vector_vector_wv_3506, 8, vs2); - setArg(call_fp_vector_vector_wv_3506, 9, vs1); - setArg(call_fp_vector_vector_wv_3506, 10, fp_vector_vector_wv_3506_arg10); - setArg(call_fp_vector_vector_wv_3506, 11, fp_vector_vector_wv_3506_arg11); - InvokeNode* call_fget_flags_3508; - x86::Gp ret_val_fget_flags_3508 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3508, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3508; - setRet(call_fget_flags_3508, 0, ret_val_fget_flags_3508); + cc.invoke(&call_fp_vector_vector_wv_3522, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3523, 0, reinterpret_cast(this)); + setRet(call_sew_3523, 0, ret_val_sew_3523); + setArg(call_fp_vector_vector_wv_3522, 0, V); + setArg(call_fp_vector_vector_wv_3522, 1, 61); + setArg(call_fp_vector_vector_wv_3522, 2, 1); + setArg(call_fp_vector_vector_wv_3522, 3, fp_vector_vector_wv_3522_arg3); + setArg(call_fp_vector_vector_wv_3522, 4, fp_vector_vector_wv_3522_arg4); + setArg(call_fp_vector_vector_wv_3522, 5, fp_vector_vector_wv_3522_arg5); + setArg(call_fp_vector_vector_wv_3522, 6, vm); + setArg(call_fp_vector_vector_wv_3522, 7, vd); + setArg(call_fp_vector_vector_wv_3522, 8, vs2); + setArg(call_fp_vector_vector_wv_3522, 9, vs1); + setArg(call_fp_vector_vector_wv_3522, 10, fp_vector_vector_wv_3522_arg10); + setArg(call_fp_vector_vector_wv_3522, 11, fp_vector_vector_wv_3522_arg11); + InvokeNode* call_fget_flags_3524; + x86::Gp ret_val_fget_flags_3524 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3524, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3524; + setRet(call_fget_flags_3524, 0, ret_val_fget_flags_3524); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3509 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3509, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3509, 64, false) - , traits::vstart); + auto tmp3525 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3525, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3525, traits::vstart); } cc.bind(label_merge); } @@ -82175,54 +81691,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3510; - x86::Gp ret_val_get_sew_pow_3510 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3510, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3511 = get_reg(cc, 8, false); - mov(cc, tmp3511, 1); + InvokeNode* call_get_sew_pow_3526; + x86::Gp ret_val_get_sew_pow_3526 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3526, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3527 = get_reg(cc, 8, false); + mov(cc, tmp3527, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3511, (ret_val_get_sew_pow_3510))), 8, false), ~ 1); - setArg(call_get_sew_pow_3510, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3510, 0, ret_val_get_sew_pow_3510); - InvokeNode* call_get_lmul_pow_3512; - x86::Gp ret_val_get_lmul_pow_3512 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3512, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3512; - setArg(call_get_lmul_pow_3512, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3512, 0, ret_val_get_lmul_pow_3512); + (gen_operation(cc, shl, tmp3527, (ret_val_get_sew_pow_3526))), 8, false), ~ 1); + setArg(call_get_sew_pow_3526, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3526, 0, ret_val_get_sew_pow_3526); + InvokeNode* call_get_lmul_pow_3528; + x86::Gp ret_val_get_lmul_pow_3528 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3528, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3528; + setArg(call_get_lmul_pow_3528, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3528, 0, ret_val_get_lmul_pow_3528); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3513; - auto illegal_fp_variable_width_3513_arg2 = SEW; - auto illegal_fp_variable_width_3513_arg3 = rm; - auto illegal_fp_variable_width_3513_arg4 = SEW_widen; - auto illegal_fp_variable_width_3513_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3513 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3513, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3514; - auto valid_reg_overlap_3514_arg2 = LMUL_pow; - auto valid_reg_overlap_3514_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3514 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3514, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3513, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3514)); - setArg(call_illegal_fp_variable_width_3513, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3513, 1, vd); - setArg(call_illegal_fp_variable_width_3513, 2, vm); - setArg(call_illegal_fp_variable_width_3513, 3, illegal_fp_variable_width_3513_arg2); - setArg(call_illegal_fp_variable_width_3513, 4, illegal_fp_variable_width_3513_arg3); - setArg(call_illegal_fp_variable_width_3513, 5, illegal_fp_variable_width_3513_arg4); - setArg(call_illegal_fp_variable_width_3513, 6, illegal_fp_variable_width_3513_arg5); - setRet(call_illegal_fp_variable_width_3513, 0, ret_val_illegal_fp_variable_width_3513); - setArg(call_valid_reg_overlap_3514, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3514, 1, vs2); - setArg(call_valid_reg_overlap_3514, 2, vd); - setArg(call_valid_reg_overlap_3514, 3, valid_reg_overlap_3514_arg2); - setArg(call_valid_reg_overlap_3514, 4, valid_reg_overlap_3514_arg3); - setRet(call_valid_reg_overlap_3514, 0, ret_val_valid_reg_overlap_3514); + InvokeNode* call_illegal_fp_variable_width_3529; + auto illegal_fp_variable_width_3529_arg2 = SEW; + auto illegal_fp_variable_width_3529_arg3 = rm; + auto illegal_fp_variable_width_3529_arg4 = SEW_widen; + auto illegal_fp_variable_width_3529_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3529 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3529, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3530; + auto valid_reg_overlap_3530_arg2 = LMUL_pow; + auto valid_reg_overlap_3530_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3530 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3530, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3529, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3530)); + setArg(call_illegal_fp_variable_width_3529, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3529, 1, vd); + setArg(call_illegal_fp_variable_width_3529, 2, vm); + setArg(call_illegal_fp_variable_width_3529, 3, illegal_fp_variable_width_3529_arg2); + setArg(call_illegal_fp_variable_width_3529, 4, illegal_fp_variable_width_3529_arg3); + setArg(call_illegal_fp_variable_width_3529, 5, illegal_fp_variable_width_3529_arg4); + setArg(call_illegal_fp_variable_width_3529, 6, illegal_fp_variable_width_3529_arg5); + setRet(call_illegal_fp_variable_width_3529, 0, ret_val_illegal_fp_variable_width_3529); + setArg(call_valid_reg_overlap_3530, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3530, 1, vs2); + setArg(call_valid_reg_overlap_3530, 2, vd); + setArg(call_valid_reg_overlap_3530, 3, valid_reg_overlap_3530_arg2); + setArg(call_valid_reg_overlap_3530, 4, valid_reg_overlap_3530_arg3); + setRet(call_valid_reg_overlap_3530, 0, ret_val_valid_reg_overlap_3530); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82238,47 +81754,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3516; - x86::Gp ret_val_sew_3516 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3516, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3515; - auto fp_vector_imm_wv_3515_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3515_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3515_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3515_arg9 = gen_ext(cc, + InvokeNode* call_sew_3532; + x86::Gp ret_val_sew_3532 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3532, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3531; + auto fp_vector_imm_wv_3531_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3531_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3531_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3531_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_wv_3515_arg10 = rm; - auto fp_vector_imm_wv_3515_arg11 = ret_val_sew_3516; + auto fp_vector_imm_wv_3531_arg10 = rm; + auto fp_vector_imm_wv_3531_arg11 = ret_val_sew_3532; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3515, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3516, 0, reinterpret_cast(this)); - setRet(call_sew_3516, 0, ret_val_sew_3516); - setArg(call_fp_vector_imm_wv_3515, 0, V); - setArg(call_fp_vector_imm_wv_3515, 1, 62); - setArg(call_fp_vector_imm_wv_3515, 2, 5); - setArg(call_fp_vector_imm_wv_3515, 3, fp_vector_imm_wv_3515_arg3); - setArg(call_fp_vector_imm_wv_3515, 4, fp_vector_imm_wv_3515_arg4); - setArg(call_fp_vector_imm_wv_3515, 5, fp_vector_imm_wv_3515_arg5); - setArg(call_fp_vector_imm_wv_3515, 6, vm); - setArg(call_fp_vector_imm_wv_3515, 7, vd); - setArg(call_fp_vector_imm_wv_3515, 8, vs2); - setArg(call_fp_vector_imm_wv_3515, 9, fp_vector_imm_wv_3515_arg9); - setArg(call_fp_vector_imm_wv_3515, 10, fp_vector_imm_wv_3515_arg10); - setArg(call_fp_vector_imm_wv_3515, 11, fp_vector_imm_wv_3515_arg11); - InvokeNode* call_fget_flags_3517; - x86::Gp ret_val_fget_flags_3517 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3517, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3517; - setRet(call_fget_flags_3517, 0, ret_val_fget_flags_3517); + cc.invoke(&call_fp_vector_imm_wv_3531, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3532, 0, reinterpret_cast(this)); + setRet(call_sew_3532, 0, ret_val_sew_3532); + setArg(call_fp_vector_imm_wv_3531, 0, V); + setArg(call_fp_vector_imm_wv_3531, 1, 62); + setArg(call_fp_vector_imm_wv_3531, 2, 5); + setArg(call_fp_vector_imm_wv_3531, 3, fp_vector_imm_wv_3531_arg3); + setArg(call_fp_vector_imm_wv_3531, 4, fp_vector_imm_wv_3531_arg4); + setArg(call_fp_vector_imm_wv_3531, 5, fp_vector_imm_wv_3531_arg5); + setArg(call_fp_vector_imm_wv_3531, 6, vm); + setArg(call_fp_vector_imm_wv_3531, 7, vd); + setArg(call_fp_vector_imm_wv_3531, 8, vs2); + setArg(call_fp_vector_imm_wv_3531, 9, fp_vector_imm_wv_3531_arg9); + setArg(call_fp_vector_imm_wv_3531, 10, fp_vector_imm_wv_3531_arg10); + setArg(call_fp_vector_imm_wv_3531, 11, fp_vector_imm_wv_3531_arg11); + InvokeNode* call_fget_flags_3533; + x86::Gp ret_val_fget_flags_3533 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3533, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3533; + setRet(call_fget_flags_3533, 0, ret_val_fget_flags_3533); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3518 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3518, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3518, 64, false) - , traits::vstart); + auto tmp3534 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3534, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3534, traits::vstart); } cc.bind(label_merge); } @@ -82322,65 +81836,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3519; - x86::Gp ret_val_get_sew_pow_3519 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3519, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3520 = get_reg(cc, 8, false); - mov(cc, tmp3520, 1); + InvokeNode* call_get_sew_pow_3535; + x86::Gp ret_val_get_sew_pow_3535 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3535, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3536 = get_reg(cc, 8, false); + mov(cc, tmp3536, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3520, (ret_val_get_sew_pow_3519))), 8, false), ~ 1); - setArg(call_get_sew_pow_3519, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3519, 0, ret_val_get_sew_pow_3519); - InvokeNode* call_get_lmul_pow_3521; - x86::Gp ret_val_get_lmul_pow_3521 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3521, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3521; - setArg(call_get_lmul_pow_3521, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3521, 0, ret_val_get_lmul_pow_3521); + (gen_operation(cc, shl, tmp3536, (ret_val_get_sew_pow_3535))), 8, false), ~ 1); + setArg(call_get_sew_pow_3535, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3535, 0, ret_val_get_sew_pow_3535); + InvokeNode* call_get_lmul_pow_3537; + x86::Gp ret_val_get_lmul_pow_3537 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3537, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3537; + setArg(call_get_lmul_pow_3537, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3537, 0, ret_val_get_lmul_pow_3537); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3522; - auto illegal_fp_variable_width_3522_arg2 = SEW; - auto illegal_fp_variable_width_3522_arg3 = rm; - auto illegal_fp_variable_width_3522_arg4 = SEW_widen; - auto illegal_fp_variable_width_3522_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3522 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3522, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3523; - auto valid_reg_overlap_3523_arg2 = LMUL_pow; - auto valid_reg_overlap_3523_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3523 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3523, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3524; - auto valid_reg_overlap_3524_arg2 = LMUL_pow; - auto valid_reg_overlap_3524_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3524 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3524, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3522, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3523)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3524)); - setArg(call_illegal_fp_variable_width_3522, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3522, 1, vd); - setArg(call_illegal_fp_variable_width_3522, 2, vm); - setArg(call_illegal_fp_variable_width_3522, 3, illegal_fp_variable_width_3522_arg2); - setArg(call_illegal_fp_variable_width_3522, 4, illegal_fp_variable_width_3522_arg3); - setArg(call_illegal_fp_variable_width_3522, 5, illegal_fp_variable_width_3522_arg4); - setArg(call_illegal_fp_variable_width_3522, 6, illegal_fp_variable_width_3522_arg5); - setRet(call_illegal_fp_variable_width_3522, 0, ret_val_illegal_fp_variable_width_3522); - setArg(call_valid_reg_overlap_3523, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3523, 1, vs1); - setArg(call_valid_reg_overlap_3523, 2, vd); - setArg(call_valid_reg_overlap_3523, 3, valid_reg_overlap_3523_arg2); - setArg(call_valid_reg_overlap_3523, 4, valid_reg_overlap_3523_arg3); - setRet(call_valid_reg_overlap_3523, 0, ret_val_valid_reg_overlap_3523); - setArg(call_valid_reg_overlap_3524, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3524, 1, vs2); - setArg(call_valid_reg_overlap_3524, 2, vd); - setArg(call_valid_reg_overlap_3524, 3, valid_reg_overlap_3524_arg2); - setArg(call_valid_reg_overlap_3524, 4, valid_reg_overlap_3524_arg3); - setRet(call_valid_reg_overlap_3524, 0, ret_val_valid_reg_overlap_3524); + InvokeNode* call_illegal_fp_variable_width_3538; + auto illegal_fp_variable_width_3538_arg2 = SEW; + auto illegal_fp_variable_width_3538_arg3 = rm; + auto illegal_fp_variable_width_3538_arg4 = SEW_widen; + auto illegal_fp_variable_width_3538_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3538 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3538, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3539; + auto valid_reg_overlap_3539_arg2 = LMUL_pow; + auto valid_reg_overlap_3539_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3539 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3539, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3540; + auto valid_reg_overlap_3540_arg2 = LMUL_pow; + auto valid_reg_overlap_3540_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3540 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3540, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3538, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3539)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3540)); + setArg(call_illegal_fp_variable_width_3538, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3538, 1, vd); + setArg(call_illegal_fp_variable_width_3538, 2, vm); + setArg(call_illegal_fp_variable_width_3538, 3, illegal_fp_variable_width_3538_arg2); + setArg(call_illegal_fp_variable_width_3538, 4, illegal_fp_variable_width_3538_arg3); + setArg(call_illegal_fp_variable_width_3538, 5, illegal_fp_variable_width_3538_arg4); + setArg(call_illegal_fp_variable_width_3538, 6, illegal_fp_variable_width_3538_arg5); + setRet(call_illegal_fp_variable_width_3538, 0, ret_val_illegal_fp_variable_width_3538); + setArg(call_valid_reg_overlap_3539, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3539, 1, vs1); + setArg(call_valid_reg_overlap_3539, 2, vd); + setArg(call_valid_reg_overlap_3539, 3, valid_reg_overlap_3539_arg2); + setArg(call_valid_reg_overlap_3539, 4, valid_reg_overlap_3539_arg3); + setRet(call_valid_reg_overlap_3539, 0, ret_val_valid_reg_overlap_3539); + setArg(call_valid_reg_overlap_3540, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3540, 1, vs2); + setArg(call_valid_reg_overlap_3540, 2, vd); + setArg(call_valid_reg_overlap_3540, 3, valid_reg_overlap_3540_arg2); + setArg(call_valid_reg_overlap_3540, 4, valid_reg_overlap_3540_arg3); + setRet(call_valid_reg_overlap_3540, 0, ret_val_valid_reg_overlap_3540); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82396,45 +81910,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3526; - x86::Gp ret_val_sew_3526 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3526, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3525; - auto fp_vector_vector_wv_3525_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3525_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3525_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3525_arg10 = rm; - auto fp_vector_vector_wv_3525_arg11 = ret_val_sew_3526; + InvokeNode* call_sew_3542; + x86::Gp ret_val_sew_3542 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3542, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3541; + auto fp_vector_vector_wv_3541_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3541_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3541_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3541_arg10 = rm; + auto fp_vector_vector_wv_3541_arg11 = ret_val_sew_3542; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3525, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3526, 0, reinterpret_cast(this)); - setRet(call_sew_3526, 0, ret_val_sew_3526); - setArg(call_fp_vector_vector_wv_3525, 0, V); - setArg(call_fp_vector_vector_wv_3525, 1, 62); - setArg(call_fp_vector_vector_wv_3525, 2, 1); - setArg(call_fp_vector_vector_wv_3525, 3, fp_vector_vector_wv_3525_arg3); - setArg(call_fp_vector_vector_wv_3525, 4, fp_vector_vector_wv_3525_arg4); - setArg(call_fp_vector_vector_wv_3525, 5, fp_vector_vector_wv_3525_arg5); - setArg(call_fp_vector_vector_wv_3525, 6, vm); - setArg(call_fp_vector_vector_wv_3525, 7, vd); - setArg(call_fp_vector_vector_wv_3525, 8, vs2); - setArg(call_fp_vector_vector_wv_3525, 9, vs1); - setArg(call_fp_vector_vector_wv_3525, 10, fp_vector_vector_wv_3525_arg10); - setArg(call_fp_vector_vector_wv_3525, 11, fp_vector_vector_wv_3525_arg11); - InvokeNode* call_fget_flags_3527; - x86::Gp ret_val_fget_flags_3527 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3527, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3527; - setRet(call_fget_flags_3527, 0, ret_val_fget_flags_3527); + cc.invoke(&call_fp_vector_vector_wv_3541, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3542, 0, reinterpret_cast(this)); + setRet(call_sew_3542, 0, ret_val_sew_3542); + setArg(call_fp_vector_vector_wv_3541, 0, V); + setArg(call_fp_vector_vector_wv_3541, 1, 62); + setArg(call_fp_vector_vector_wv_3541, 2, 1); + setArg(call_fp_vector_vector_wv_3541, 3, fp_vector_vector_wv_3541_arg3); + setArg(call_fp_vector_vector_wv_3541, 4, fp_vector_vector_wv_3541_arg4); + setArg(call_fp_vector_vector_wv_3541, 5, fp_vector_vector_wv_3541_arg5); + setArg(call_fp_vector_vector_wv_3541, 6, vm); + setArg(call_fp_vector_vector_wv_3541, 7, vd); + setArg(call_fp_vector_vector_wv_3541, 8, vs2); + setArg(call_fp_vector_vector_wv_3541, 9, vs1); + setArg(call_fp_vector_vector_wv_3541, 10, fp_vector_vector_wv_3541_arg10); + setArg(call_fp_vector_vector_wv_3541, 11, fp_vector_vector_wv_3541_arg11); + InvokeNode* call_fget_flags_3543; + x86::Gp ret_val_fget_flags_3543 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3543, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3543; + setRet(call_fget_flags_3543, 0, ret_val_fget_flags_3543); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3528 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3528, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3528, 64, false) - , traits::vstart); + auto tmp3544 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3544, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3544, traits::vstart); } cc.bind(label_merge); } @@ -82478,54 +81990,54 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3529; - x86::Gp ret_val_get_sew_pow_3529 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3529, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3530 = get_reg(cc, 8, false); - mov(cc, tmp3530, 1); + InvokeNode* call_get_sew_pow_3545; + x86::Gp ret_val_get_sew_pow_3545 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3545, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3546 = get_reg(cc, 8, false); + mov(cc, tmp3546, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3530, (ret_val_get_sew_pow_3529))), 8, false), ~ 1); - setArg(call_get_sew_pow_3529, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3529, 0, ret_val_get_sew_pow_3529); - InvokeNode* call_get_lmul_pow_3531; - x86::Gp ret_val_get_lmul_pow_3531 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3531, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3531; - setArg(call_get_lmul_pow_3531, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3531, 0, ret_val_get_lmul_pow_3531); + (gen_operation(cc, shl, tmp3546, (ret_val_get_sew_pow_3545))), 8, false), ~ 1); + setArg(call_get_sew_pow_3545, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3545, 0, ret_val_get_sew_pow_3545); + InvokeNode* call_get_lmul_pow_3547; + x86::Gp ret_val_get_lmul_pow_3547 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3547, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3547; + setArg(call_get_lmul_pow_3547, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3547, 0, ret_val_get_lmul_pow_3547); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3532; - auto illegal_fp_variable_width_3532_arg2 = SEW; - auto illegal_fp_variable_width_3532_arg3 = rm; - auto illegal_fp_variable_width_3532_arg4 = SEW_widen; - auto illegal_fp_variable_width_3532_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3532 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3532, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3533; - auto valid_reg_overlap_3533_arg2 = LMUL_pow; - auto valid_reg_overlap_3533_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3533 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3533, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3532, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3533)); - setArg(call_illegal_fp_variable_width_3532, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3532, 1, vd); - setArg(call_illegal_fp_variable_width_3532, 2, vm); - setArg(call_illegal_fp_variable_width_3532, 3, illegal_fp_variable_width_3532_arg2); - setArg(call_illegal_fp_variable_width_3532, 4, illegal_fp_variable_width_3532_arg3); - setArg(call_illegal_fp_variable_width_3532, 5, illegal_fp_variable_width_3532_arg4); - setArg(call_illegal_fp_variable_width_3532, 6, illegal_fp_variable_width_3532_arg5); - setRet(call_illegal_fp_variable_width_3532, 0, ret_val_illegal_fp_variable_width_3532); - setArg(call_valid_reg_overlap_3533, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3533, 1, vs2); - setArg(call_valid_reg_overlap_3533, 2, vd); - setArg(call_valid_reg_overlap_3533, 3, valid_reg_overlap_3533_arg2); - setArg(call_valid_reg_overlap_3533, 4, valid_reg_overlap_3533_arg3); - setRet(call_valid_reg_overlap_3533, 0, ret_val_valid_reg_overlap_3533); + InvokeNode* call_illegal_fp_variable_width_3548; + auto illegal_fp_variable_width_3548_arg2 = SEW; + auto illegal_fp_variable_width_3548_arg3 = rm; + auto illegal_fp_variable_width_3548_arg4 = SEW_widen; + auto illegal_fp_variable_width_3548_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3548 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3548, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3549; + auto valid_reg_overlap_3549_arg2 = LMUL_pow; + auto valid_reg_overlap_3549_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3549 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3549, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3548, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3549)); + setArg(call_illegal_fp_variable_width_3548, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3548, 1, vd); + setArg(call_illegal_fp_variable_width_3548, 2, vm); + setArg(call_illegal_fp_variable_width_3548, 3, illegal_fp_variable_width_3548_arg2); + setArg(call_illegal_fp_variable_width_3548, 4, illegal_fp_variable_width_3548_arg3); + setArg(call_illegal_fp_variable_width_3548, 5, illegal_fp_variable_width_3548_arg4); + setArg(call_illegal_fp_variable_width_3548, 6, illegal_fp_variable_width_3548_arg5); + setRet(call_illegal_fp_variable_width_3548, 0, ret_val_illegal_fp_variable_width_3548); + setArg(call_valid_reg_overlap_3549, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3549, 1, vs2); + setArg(call_valid_reg_overlap_3549, 2, vd); + setArg(call_valid_reg_overlap_3549, 3, valid_reg_overlap_3549_arg2); + setArg(call_valid_reg_overlap_3549, 4, valid_reg_overlap_3549_arg3); + setRet(call_valid_reg_overlap_3549, 0, ret_val_valid_reg_overlap_3549); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82541,47 +82053,45 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3535; - x86::Gp ret_val_sew_3535 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3535, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_wv_3534; - auto fp_vector_imm_wv_3534_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_wv_3534_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_wv_3534_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_wv_3534_arg9 = gen_ext(cc, + InvokeNode* call_sew_3551; + x86::Gp ret_val_sew_3551 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3551, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_wv_3550; + auto fp_vector_imm_wv_3550_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_wv_3550_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_wv_3550_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_wv_3550_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_wv_3534_arg10 = rm; - auto fp_vector_imm_wv_3534_arg11 = ret_val_sew_3535; + auto fp_vector_imm_wv_3550_arg10 = rm; + auto fp_vector_imm_wv_3550_arg11 = ret_val_sew_3551; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_wv_3534, &fp_vector_imm_wv, FuncSignature::build()); - setArg(call_sew_3535, 0, reinterpret_cast(this)); - setRet(call_sew_3535, 0, ret_val_sew_3535); - setArg(call_fp_vector_imm_wv_3534, 0, V); - setArg(call_fp_vector_imm_wv_3534, 1, 63); - setArg(call_fp_vector_imm_wv_3534, 2, 5); - setArg(call_fp_vector_imm_wv_3534, 3, fp_vector_imm_wv_3534_arg3); - setArg(call_fp_vector_imm_wv_3534, 4, fp_vector_imm_wv_3534_arg4); - setArg(call_fp_vector_imm_wv_3534, 5, fp_vector_imm_wv_3534_arg5); - setArg(call_fp_vector_imm_wv_3534, 6, vm); - setArg(call_fp_vector_imm_wv_3534, 7, vd); - setArg(call_fp_vector_imm_wv_3534, 8, vs2); - setArg(call_fp_vector_imm_wv_3534, 9, fp_vector_imm_wv_3534_arg9); - setArg(call_fp_vector_imm_wv_3534, 10, fp_vector_imm_wv_3534_arg10); - setArg(call_fp_vector_imm_wv_3534, 11, fp_vector_imm_wv_3534_arg11); - InvokeNode* call_fget_flags_3536; - x86::Gp ret_val_fget_flags_3536 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3536, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3536; - setRet(call_fget_flags_3536, 0, ret_val_fget_flags_3536); + cc.invoke(&call_fp_vector_imm_wv_3550, &fp_vector_imm_wv, FuncSignature::build()); + setArg(call_sew_3551, 0, reinterpret_cast(this)); + setRet(call_sew_3551, 0, ret_val_sew_3551); + setArg(call_fp_vector_imm_wv_3550, 0, V); + setArg(call_fp_vector_imm_wv_3550, 1, 63); + setArg(call_fp_vector_imm_wv_3550, 2, 5); + setArg(call_fp_vector_imm_wv_3550, 3, fp_vector_imm_wv_3550_arg3); + setArg(call_fp_vector_imm_wv_3550, 4, fp_vector_imm_wv_3550_arg4); + setArg(call_fp_vector_imm_wv_3550, 5, fp_vector_imm_wv_3550_arg5); + setArg(call_fp_vector_imm_wv_3550, 6, vm); + setArg(call_fp_vector_imm_wv_3550, 7, vd); + setArg(call_fp_vector_imm_wv_3550, 8, vs2); + setArg(call_fp_vector_imm_wv_3550, 9, fp_vector_imm_wv_3550_arg9); + setArg(call_fp_vector_imm_wv_3550, 10, fp_vector_imm_wv_3550_arg10); + setArg(call_fp_vector_imm_wv_3550, 11, fp_vector_imm_wv_3550_arg11); + InvokeNode* call_fget_flags_3552; + x86::Gp ret_val_fget_flags_3552 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3552, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3552; + setRet(call_fget_flags_3552, 0, ret_val_fget_flags_3552); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3537 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3537, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3537, 64, false) - , traits::vstart); + auto tmp3553 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3553, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3553, traits::vstart); } cc.bind(label_merge); } @@ -82625,65 +82135,65 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3538; - x86::Gp ret_val_get_sew_pow_3538 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3538, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3539 = get_reg(cc, 8, false); - mov(cc, tmp3539, 1); + InvokeNode* call_get_sew_pow_3554; + x86::Gp ret_val_get_sew_pow_3554 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3554, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3555 = get_reg(cc, 8, false); + mov(cc, tmp3555, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3539, (ret_val_get_sew_pow_3538))), 8, false), ~ 1); - setArg(call_get_sew_pow_3538, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3538, 0, ret_val_get_sew_pow_3538); - InvokeNode* call_get_lmul_pow_3540; - x86::Gp ret_val_get_lmul_pow_3540 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3540, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3540; - setArg(call_get_lmul_pow_3540, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3540, 0, ret_val_get_lmul_pow_3540); + (gen_operation(cc, shl, tmp3555, (ret_val_get_sew_pow_3554))), 8, false), ~ 1); + setArg(call_get_sew_pow_3554, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3554, 0, ret_val_get_sew_pow_3554); + InvokeNode* call_get_lmul_pow_3556; + x86::Gp ret_val_get_lmul_pow_3556 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3556, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3556; + setArg(call_get_lmul_pow_3556, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3556, 0, ret_val_get_lmul_pow_3556); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3541; - auto illegal_fp_variable_width_3541_arg2 = SEW; - auto illegal_fp_variable_width_3541_arg3 = rm; - auto illegal_fp_variable_width_3541_arg4 = SEW_widen; - auto illegal_fp_variable_width_3541_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3541 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3541, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3542; - auto valid_reg_overlap_3542_arg2 = LMUL_pow; - auto valid_reg_overlap_3542_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3542 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3542, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3543; - auto valid_reg_overlap_3543_arg2 = LMUL_pow; - auto valid_reg_overlap_3543_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3543 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3543, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3541, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3542)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3543)); - setArg(call_illegal_fp_variable_width_3541, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3541, 1, vd); - setArg(call_illegal_fp_variable_width_3541, 2, vm); - setArg(call_illegal_fp_variable_width_3541, 3, illegal_fp_variable_width_3541_arg2); - setArg(call_illegal_fp_variable_width_3541, 4, illegal_fp_variable_width_3541_arg3); - setArg(call_illegal_fp_variable_width_3541, 5, illegal_fp_variable_width_3541_arg4); - setArg(call_illegal_fp_variable_width_3541, 6, illegal_fp_variable_width_3541_arg5); - setRet(call_illegal_fp_variable_width_3541, 0, ret_val_illegal_fp_variable_width_3541); - setArg(call_valid_reg_overlap_3542, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3542, 1, vs1); - setArg(call_valid_reg_overlap_3542, 2, vd); - setArg(call_valid_reg_overlap_3542, 3, valid_reg_overlap_3542_arg2); - setArg(call_valid_reg_overlap_3542, 4, valid_reg_overlap_3542_arg3); - setRet(call_valid_reg_overlap_3542, 0, ret_val_valid_reg_overlap_3542); - setArg(call_valid_reg_overlap_3543, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3543, 1, vs2); - setArg(call_valid_reg_overlap_3543, 2, vd); - setArg(call_valid_reg_overlap_3543, 3, valid_reg_overlap_3543_arg2); - setArg(call_valid_reg_overlap_3543, 4, valid_reg_overlap_3543_arg3); - setRet(call_valid_reg_overlap_3543, 0, ret_val_valid_reg_overlap_3543); + InvokeNode* call_illegal_fp_variable_width_3557; + auto illegal_fp_variable_width_3557_arg2 = SEW; + auto illegal_fp_variable_width_3557_arg3 = rm; + auto illegal_fp_variable_width_3557_arg4 = SEW_widen; + auto illegal_fp_variable_width_3557_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3557 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3557, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3558; + auto valid_reg_overlap_3558_arg2 = LMUL_pow; + auto valid_reg_overlap_3558_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3558 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3558, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3559; + auto valid_reg_overlap_3559_arg2 = LMUL_pow; + auto valid_reg_overlap_3559_arg3 = LMUL_pow_widen; + x86::Gp ret_val_valid_reg_overlap_3559 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3559, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3557, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3558)), gen_operation(cc, lnot, ret_val_valid_reg_overlap_3559)); + setArg(call_illegal_fp_variable_width_3557, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3557, 1, vd); + setArg(call_illegal_fp_variable_width_3557, 2, vm); + setArg(call_illegal_fp_variable_width_3557, 3, illegal_fp_variable_width_3557_arg2); + setArg(call_illegal_fp_variable_width_3557, 4, illegal_fp_variable_width_3557_arg3); + setArg(call_illegal_fp_variable_width_3557, 5, illegal_fp_variable_width_3557_arg4); + setArg(call_illegal_fp_variable_width_3557, 6, illegal_fp_variable_width_3557_arg5); + setRet(call_illegal_fp_variable_width_3557, 0, ret_val_illegal_fp_variable_width_3557); + setArg(call_valid_reg_overlap_3558, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3558, 1, vs1); + setArg(call_valid_reg_overlap_3558, 2, vd); + setArg(call_valid_reg_overlap_3558, 3, valid_reg_overlap_3558_arg2); + setArg(call_valid_reg_overlap_3558, 4, valid_reg_overlap_3558_arg3); + setRet(call_valid_reg_overlap_3558, 0, ret_val_valid_reg_overlap_3558); + setArg(call_valid_reg_overlap_3559, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3559, 1, vs2); + setArg(call_valid_reg_overlap_3559, 2, vd); + setArg(call_valid_reg_overlap_3559, 3, valid_reg_overlap_3559_arg2); + setArg(call_valid_reg_overlap_3559, 4, valid_reg_overlap_3559_arg3); + setRet(call_valid_reg_overlap_3559, 0, ret_val_valid_reg_overlap_3559); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82699,45 +82209,43 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3545; - x86::Gp ret_val_sew_3545 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3545, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_wv_3544; - auto fp_vector_vector_wv_3544_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_wv_3544_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_wv_3544_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_wv_3544_arg10 = rm; - auto fp_vector_vector_wv_3544_arg11 = ret_val_sew_3545; + InvokeNode* call_sew_3561; + x86::Gp ret_val_sew_3561 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3561, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_wv_3560; + auto fp_vector_vector_wv_3560_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_wv_3560_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_wv_3560_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_wv_3560_arg10 = rm; + auto fp_vector_vector_wv_3560_arg11 = ret_val_sew_3561; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_wv_3544, &fp_vector_vector_wv, FuncSignature::build()); - setArg(call_sew_3545, 0, reinterpret_cast(this)); - setRet(call_sew_3545, 0, ret_val_sew_3545); - setArg(call_fp_vector_vector_wv_3544, 0, V); - setArg(call_fp_vector_vector_wv_3544, 1, 63); - setArg(call_fp_vector_vector_wv_3544, 2, 1); - setArg(call_fp_vector_vector_wv_3544, 3, fp_vector_vector_wv_3544_arg3); - setArg(call_fp_vector_vector_wv_3544, 4, fp_vector_vector_wv_3544_arg4); - setArg(call_fp_vector_vector_wv_3544, 5, fp_vector_vector_wv_3544_arg5); - setArg(call_fp_vector_vector_wv_3544, 6, vm); - setArg(call_fp_vector_vector_wv_3544, 7, vd); - setArg(call_fp_vector_vector_wv_3544, 8, vs2); - setArg(call_fp_vector_vector_wv_3544, 9, vs1); - setArg(call_fp_vector_vector_wv_3544, 10, fp_vector_vector_wv_3544_arg10); - setArg(call_fp_vector_vector_wv_3544, 11, fp_vector_vector_wv_3544_arg11); - InvokeNode* call_fget_flags_3546; - x86::Gp ret_val_fget_flags_3546 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3546, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3546; - setRet(call_fget_flags_3546, 0, ret_val_fget_flags_3546); + cc.invoke(&call_fp_vector_vector_wv_3560, &fp_vector_vector_wv, FuncSignature::build()); + setArg(call_sew_3561, 0, reinterpret_cast(this)); + setRet(call_sew_3561, 0, ret_val_sew_3561); + setArg(call_fp_vector_vector_wv_3560, 0, V); + setArg(call_fp_vector_vector_wv_3560, 1, 63); + setArg(call_fp_vector_vector_wv_3560, 2, 1); + setArg(call_fp_vector_vector_wv_3560, 3, fp_vector_vector_wv_3560_arg3); + setArg(call_fp_vector_vector_wv_3560, 4, fp_vector_vector_wv_3560_arg4); + setArg(call_fp_vector_vector_wv_3560, 5, fp_vector_vector_wv_3560_arg5); + setArg(call_fp_vector_vector_wv_3560, 6, vm); + setArg(call_fp_vector_vector_wv_3560, 7, vd); + setArg(call_fp_vector_vector_wv_3560, 8, vs2); + setArg(call_fp_vector_vector_wv_3560, 9, vs1); + setArg(call_fp_vector_vector_wv_3560, 10, fp_vector_vector_wv_3560_arg10); + setArg(call_fp_vector_vector_wv_3560, 11, fp_vector_vector_wv_3560_arg11); + InvokeNode* call_fget_flags_3562; + x86::Gp ret_val_fget_flags_3562 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3562, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3562; + setRet(call_fget_flags_3562, 0, ret_val_fget_flags_3562); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3547 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3547, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3547, 64, false) - , traits::vstart); + auto tmp3563 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3563, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3563, traits::vstart); } cc.bind(label_merge); } @@ -82780,30 +82288,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3548; - x86::Gp ret_val_get_sew_pow_3548 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3548, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3549 = get_reg(cc, 8, false); - mov(cc, tmp3549, 1); + InvokeNode* call_get_sew_pow_3564; + x86::Gp ret_val_get_sew_pow_3564 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3564, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3565 = get_reg(cc, 8, false); + mov(cc, tmp3565, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3549, (ret_val_get_sew_pow_3548))), 8, false), ~ 1); - setArg(call_get_sew_pow_3548, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3548, 0, ret_val_get_sew_pow_3548); + (gen_operation(cc, shl, tmp3565, (ret_val_get_sew_pow_3564))), 8, false), ~ 1); + setArg(call_get_sew_pow_3564, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3564, 0, ret_val_get_sew_pow_3564); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3550; - auto illegal_fp_normal_3550_arg2 = SEW; - auto illegal_fp_normal_3550_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3550 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3550, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3550; - setArg(call_illegal_fp_normal_3550, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3550, 1, vd); - setArg(call_illegal_fp_normal_3550, 2, vm); - setArg(call_illegal_fp_normal_3550, 3, illegal_fp_normal_3550_arg2); - setArg(call_illegal_fp_normal_3550, 4, illegal_fp_normal_3550_arg3); - setRet(call_illegal_fp_normal_3550, 0, ret_val_illegal_fp_normal_3550); + InvokeNode* call_illegal_fp_normal_3566; + auto illegal_fp_normal_3566_arg2 = SEW; + auto illegal_fp_normal_3566_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3566 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3566, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3566; + setArg(call_illegal_fp_normal_3566, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3566, 1, vd); + setArg(call_illegal_fp_normal_3566, 2, vm); + setArg(call_illegal_fp_normal_3566, 3, illegal_fp_normal_3566_arg2); + setArg(call_illegal_fp_normal_3566, 4, illegal_fp_normal_3566_arg3); + setRet(call_illegal_fp_normal_3566, 0, ret_val_illegal_fp_normal_3566); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82819,44 +82327,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3552; - x86::Gp ret_val_sew_3552 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3552, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3551; - auto fp_vector_unary_op_3551_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3551_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3551_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3551_arg9 = rm; - auto fp_vector_unary_op_3551_arg10 = ret_val_sew_3552; + InvokeNode* call_sew_3568; + x86::Gp ret_val_sew_3568 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3568, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3567; + auto fp_vector_unary_op_3567_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3567_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3567_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3567_arg9 = rm; + auto fp_vector_unary_op_3567_arg10 = ret_val_sew_3568; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3551, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3552, 0, reinterpret_cast(this)); - setRet(call_sew_3552, 0, ret_val_sew_3552); - setArg(call_fp_vector_unary_op_3551, 0, V); - setArg(call_fp_vector_unary_op_3551, 1, 19); - setArg(call_fp_vector_unary_op_3551, 2, 0); - setArg(call_fp_vector_unary_op_3551, 3, fp_vector_unary_op_3551_arg3); - setArg(call_fp_vector_unary_op_3551, 4, fp_vector_unary_op_3551_arg4); - setArg(call_fp_vector_unary_op_3551, 5, fp_vector_unary_op_3551_arg5); - setArg(call_fp_vector_unary_op_3551, 6, vm); - setArg(call_fp_vector_unary_op_3551, 7, vd); - setArg(call_fp_vector_unary_op_3551, 8, vs2); - setArg(call_fp_vector_unary_op_3551, 9, fp_vector_unary_op_3551_arg9); - setArg(call_fp_vector_unary_op_3551, 10, fp_vector_unary_op_3551_arg10); - InvokeNode* call_fget_flags_3553; - x86::Gp ret_val_fget_flags_3553 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3553, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3553; - setRet(call_fget_flags_3553, 0, ret_val_fget_flags_3553); + cc.invoke(&call_fp_vector_unary_op_3567, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3568, 0, reinterpret_cast(this)); + setRet(call_sew_3568, 0, ret_val_sew_3568); + setArg(call_fp_vector_unary_op_3567, 0, V); + setArg(call_fp_vector_unary_op_3567, 1, 19); + setArg(call_fp_vector_unary_op_3567, 2, 0); + setArg(call_fp_vector_unary_op_3567, 3, fp_vector_unary_op_3567_arg3); + setArg(call_fp_vector_unary_op_3567, 4, fp_vector_unary_op_3567_arg4); + setArg(call_fp_vector_unary_op_3567, 5, fp_vector_unary_op_3567_arg5); + setArg(call_fp_vector_unary_op_3567, 6, vm); + setArg(call_fp_vector_unary_op_3567, 7, vd); + setArg(call_fp_vector_unary_op_3567, 8, vs2); + setArg(call_fp_vector_unary_op_3567, 9, fp_vector_unary_op_3567_arg9); + setArg(call_fp_vector_unary_op_3567, 10, fp_vector_unary_op_3567_arg10); + InvokeNode* call_fget_flags_3569; + x86::Gp ret_val_fget_flags_3569 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3569, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3569; + setRet(call_fget_flags_3569, 0, ret_val_fget_flags_3569); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3554 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3554, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3554, 64, false) - , traits::vstart); + auto tmp3570 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3570, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3570, traits::vstart); } cc.bind(label_merge); } @@ -82899,30 +82405,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3555; - x86::Gp ret_val_get_sew_pow_3555 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3555, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3556 = get_reg(cc, 8, false); - mov(cc, tmp3556, 1); + InvokeNode* call_get_sew_pow_3571; + x86::Gp ret_val_get_sew_pow_3571 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3571, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3572 = get_reg(cc, 8, false); + mov(cc, tmp3572, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3556, (ret_val_get_sew_pow_3555))), 8, false), ~ 1); - setArg(call_get_sew_pow_3555, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3555, 0, ret_val_get_sew_pow_3555); + (gen_operation(cc, shl, tmp3572, (ret_val_get_sew_pow_3571))), 8, false), ~ 1); + setArg(call_get_sew_pow_3571, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3571, 0, ret_val_get_sew_pow_3571); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3557; - auto illegal_fp_normal_3557_arg2 = SEW; - auto illegal_fp_normal_3557_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3557 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3557, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3557; - setArg(call_illegal_fp_normal_3557, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3557, 1, vd); - setArg(call_illegal_fp_normal_3557, 2, vm); - setArg(call_illegal_fp_normal_3557, 3, illegal_fp_normal_3557_arg2); - setArg(call_illegal_fp_normal_3557, 4, illegal_fp_normal_3557_arg3); - setRet(call_illegal_fp_normal_3557, 0, ret_val_illegal_fp_normal_3557); + InvokeNode* call_illegal_fp_normal_3573; + auto illegal_fp_normal_3573_arg2 = SEW; + auto illegal_fp_normal_3573_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3573 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3573, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3573; + setArg(call_illegal_fp_normal_3573, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3573, 1, vd); + setArg(call_illegal_fp_normal_3573, 2, vm); + setArg(call_illegal_fp_normal_3573, 3, illegal_fp_normal_3573_arg2); + setArg(call_illegal_fp_normal_3573, 4, illegal_fp_normal_3573_arg3); + setRet(call_illegal_fp_normal_3573, 0, ret_val_illegal_fp_normal_3573); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -82938,44 +82444,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3559; - x86::Gp ret_val_sew_3559 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3559, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3558; - auto fp_vector_unary_op_3558_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3558_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3558_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3558_arg9 = rm; - auto fp_vector_unary_op_3558_arg10 = ret_val_sew_3559; + InvokeNode* call_sew_3575; + x86::Gp ret_val_sew_3575 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3575, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3574; + auto fp_vector_unary_op_3574_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3574_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3574_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3574_arg9 = rm; + auto fp_vector_unary_op_3574_arg10 = ret_val_sew_3575; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3558, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3559, 0, reinterpret_cast(this)); - setRet(call_sew_3559, 0, ret_val_sew_3559); - setArg(call_fp_vector_unary_op_3558, 0, V); - setArg(call_fp_vector_unary_op_3558, 1, 19); - setArg(call_fp_vector_unary_op_3558, 2, 4); - setArg(call_fp_vector_unary_op_3558, 3, fp_vector_unary_op_3558_arg3); - setArg(call_fp_vector_unary_op_3558, 4, fp_vector_unary_op_3558_arg4); - setArg(call_fp_vector_unary_op_3558, 5, fp_vector_unary_op_3558_arg5); - setArg(call_fp_vector_unary_op_3558, 6, vm); - setArg(call_fp_vector_unary_op_3558, 7, vd); - setArg(call_fp_vector_unary_op_3558, 8, vs2); - setArg(call_fp_vector_unary_op_3558, 9, fp_vector_unary_op_3558_arg9); - setArg(call_fp_vector_unary_op_3558, 10, fp_vector_unary_op_3558_arg10); - InvokeNode* call_fget_flags_3560; - x86::Gp ret_val_fget_flags_3560 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3560, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3560; - setRet(call_fget_flags_3560, 0, ret_val_fget_flags_3560); + cc.invoke(&call_fp_vector_unary_op_3574, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3575, 0, reinterpret_cast(this)); + setRet(call_sew_3575, 0, ret_val_sew_3575); + setArg(call_fp_vector_unary_op_3574, 0, V); + setArg(call_fp_vector_unary_op_3574, 1, 19); + setArg(call_fp_vector_unary_op_3574, 2, 4); + setArg(call_fp_vector_unary_op_3574, 3, fp_vector_unary_op_3574_arg3); + setArg(call_fp_vector_unary_op_3574, 4, fp_vector_unary_op_3574_arg4); + setArg(call_fp_vector_unary_op_3574, 5, fp_vector_unary_op_3574_arg5); + setArg(call_fp_vector_unary_op_3574, 6, vm); + setArg(call_fp_vector_unary_op_3574, 7, vd); + setArg(call_fp_vector_unary_op_3574, 8, vs2); + setArg(call_fp_vector_unary_op_3574, 9, fp_vector_unary_op_3574_arg9); + setArg(call_fp_vector_unary_op_3574, 10, fp_vector_unary_op_3574_arg10); + InvokeNode* call_fget_flags_3576; + x86::Gp ret_val_fget_flags_3576 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3576, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3576; + setRet(call_fget_flags_3576, 0, ret_val_fget_flags_3576); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3561 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3561, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3561, 64, false) - , traits::vstart); + auto tmp3577 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3577, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3577, traits::vstart); } cc.bind(label_merge); } @@ -83018,30 +82522,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3562; - x86::Gp ret_val_get_sew_pow_3562 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3562, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3563 = get_reg(cc, 8, false); - mov(cc, tmp3563, 1); + InvokeNode* call_get_sew_pow_3578; + x86::Gp ret_val_get_sew_pow_3578 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3578, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3579 = get_reg(cc, 8, false); + mov(cc, tmp3579, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3563, (ret_val_get_sew_pow_3562))), 8, false), ~ 1); - setArg(call_get_sew_pow_3562, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3562, 0, ret_val_get_sew_pow_3562); + (gen_operation(cc, shl, tmp3579, (ret_val_get_sew_pow_3578))), 8, false), ~ 1); + setArg(call_get_sew_pow_3578, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3578, 0, ret_val_get_sew_pow_3578); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3564; - auto illegal_fp_normal_3564_arg2 = SEW; - auto illegal_fp_normal_3564_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3564 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3564, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3564; - setArg(call_illegal_fp_normal_3564, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3564, 1, vd); - setArg(call_illegal_fp_normal_3564, 2, vm); - setArg(call_illegal_fp_normal_3564, 3, illegal_fp_normal_3564_arg2); - setArg(call_illegal_fp_normal_3564, 4, illegal_fp_normal_3564_arg3); - setRet(call_illegal_fp_normal_3564, 0, ret_val_illegal_fp_normal_3564); + InvokeNode* call_illegal_fp_normal_3580; + auto illegal_fp_normal_3580_arg2 = SEW; + auto illegal_fp_normal_3580_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3580 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3580, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3580; + setArg(call_illegal_fp_normal_3580, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3580, 1, vd); + setArg(call_illegal_fp_normal_3580, 2, vm); + setArg(call_illegal_fp_normal_3580, 3, illegal_fp_normal_3580_arg2); + setArg(call_illegal_fp_normal_3580, 4, illegal_fp_normal_3580_arg3); + setRet(call_illegal_fp_normal_3580, 0, ret_val_illegal_fp_normal_3580); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83057,44 +82561,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3566; - x86::Gp ret_val_sew_3566 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3566, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3565; - auto fp_vector_unary_op_3565_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3565_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3565_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3565_arg9 = rm; - auto fp_vector_unary_op_3565_arg10 = ret_val_sew_3566; + InvokeNode* call_sew_3582; + x86::Gp ret_val_sew_3582 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3582, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3581; + auto fp_vector_unary_op_3581_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3581_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3581_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3581_arg9 = rm; + auto fp_vector_unary_op_3581_arg10 = ret_val_sew_3582; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3565, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3566, 0, reinterpret_cast(this)); - setRet(call_sew_3566, 0, ret_val_sew_3566); - setArg(call_fp_vector_unary_op_3565, 0, V); - setArg(call_fp_vector_unary_op_3565, 1, 19); - setArg(call_fp_vector_unary_op_3565, 2, 5); - setArg(call_fp_vector_unary_op_3565, 3, fp_vector_unary_op_3565_arg3); - setArg(call_fp_vector_unary_op_3565, 4, fp_vector_unary_op_3565_arg4); - setArg(call_fp_vector_unary_op_3565, 5, fp_vector_unary_op_3565_arg5); - setArg(call_fp_vector_unary_op_3565, 6, vm); - setArg(call_fp_vector_unary_op_3565, 7, vd); - setArg(call_fp_vector_unary_op_3565, 8, vs2); - setArg(call_fp_vector_unary_op_3565, 9, fp_vector_unary_op_3565_arg9); - setArg(call_fp_vector_unary_op_3565, 10, fp_vector_unary_op_3565_arg10); - InvokeNode* call_fget_flags_3567; - x86::Gp ret_val_fget_flags_3567 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3567, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3567; - setRet(call_fget_flags_3567, 0, ret_val_fget_flags_3567); + cc.invoke(&call_fp_vector_unary_op_3581, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3582, 0, reinterpret_cast(this)); + setRet(call_sew_3582, 0, ret_val_sew_3582); + setArg(call_fp_vector_unary_op_3581, 0, V); + setArg(call_fp_vector_unary_op_3581, 1, 19); + setArg(call_fp_vector_unary_op_3581, 2, 5); + setArg(call_fp_vector_unary_op_3581, 3, fp_vector_unary_op_3581_arg3); + setArg(call_fp_vector_unary_op_3581, 4, fp_vector_unary_op_3581_arg4); + setArg(call_fp_vector_unary_op_3581, 5, fp_vector_unary_op_3581_arg5); + setArg(call_fp_vector_unary_op_3581, 6, vm); + setArg(call_fp_vector_unary_op_3581, 7, vd); + setArg(call_fp_vector_unary_op_3581, 8, vs2); + setArg(call_fp_vector_unary_op_3581, 9, fp_vector_unary_op_3581_arg9); + setArg(call_fp_vector_unary_op_3581, 10, fp_vector_unary_op_3581_arg10); + InvokeNode* call_fget_flags_3583; + x86::Gp ret_val_fget_flags_3583 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3583, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3583; + setRet(call_fget_flags_3583, 0, ret_val_fget_flags_3583); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3568 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3568, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3568, 64, false) - , traits::vstart); + auto tmp3584 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3584, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3584, traits::vstart); } cc.bind(label_merge); } @@ -83138,30 +82640,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3569; - x86::Gp ret_val_get_sew_pow_3569 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3569, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3570 = get_reg(cc, 8, false); - mov(cc, tmp3570, 1); + InvokeNode* call_get_sew_pow_3585; + x86::Gp ret_val_get_sew_pow_3585 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3585, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3586 = get_reg(cc, 8, false); + mov(cc, tmp3586, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3570, (ret_val_get_sew_pow_3569))), 8, false), ~ 1); - setArg(call_get_sew_pow_3569, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3569, 0, ret_val_get_sew_pow_3569); + (gen_operation(cc, shl, tmp3586, (ret_val_get_sew_pow_3585))), 8, false), ~ 1); + setArg(call_get_sew_pow_3585, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3585, 0, ret_val_get_sew_pow_3585); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3571; - auto illegal_fp_normal_3571_arg2 = SEW; - auto illegal_fp_normal_3571_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3571 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3571, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3571; - setArg(call_illegal_fp_normal_3571, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3571, 1, vd); - setArg(call_illegal_fp_normal_3571, 2, vm); - setArg(call_illegal_fp_normal_3571, 3, illegal_fp_normal_3571_arg2); - setArg(call_illegal_fp_normal_3571, 4, illegal_fp_normal_3571_arg3); - setRet(call_illegal_fp_normal_3571, 0, ret_val_illegal_fp_normal_3571); + InvokeNode* call_illegal_fp_normal_3587; + auto illegal_fp_normal_3587_arg2 = SEW; + auto illegal_fp_normal_3587_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3587 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3587, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3587; + setArg(call_illegal_fp_normal_3587, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3587, 1, vd); + setArg(call_illegal_fp_normal_3587, 2, vm); + setArg(call_illegal_fp_normal_3587, 3, illegal_fp_normal_3587_arg2); + setArg(call_illegal_fp_normal_3587, 4, illegal_fp_normal_3587_arg3); + setRet(call_illegal_fp_normal_3587, 0, ret_val_illegal_fp_normal_3587); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83177,41 +82679,39 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3573; - x86::Gp ret_val_sew_3573 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3573, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3572; - auto fp_vector_imm_op_3572_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3572_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3572_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3572_arg9 = gen_ext(cc, + InvokeNode* call_sew_3589; + x86::Gp ret_val_sew_3589 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3589, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3588; + auto fp_vector_imm_op_3588_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3588_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3588_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3588_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3572_arg10 = rm; - auto fp_vector_imm_op_3572_arg11 = ret_val_sew_3573; + auto fp_vector_imm_op_3588_arg10 = rm; + auto fp_vector_imm_op_3588_arg11 = ret_val_sew_3589; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3572, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3573, 0, reinterpret_cast(this)); - setRet(call_sew_3573, 0, ret_val_sew_3573); - setArg(call_fp_vector_imm_op_3572, 0, V); - setArg(call_fp_vector_imm_op_3572, 1, 4); - setArg(call_fp_vector_imm_op_3572, 2, 5); - setArg(call_fp_vector_imm_op_3572, 3, fp_vector_imm_op_3572_arg3); - setArg(call_fp_vector_imm_op_3572, 4, fp_vector_imm_op_3572_arg4); - setArg(call_fp_vector_imm_op_3572, 5, fp_vector_imm_op_3572_arg5); - setArg(call_fp_vector_imm_op_3572, 6, vm); - setArg(call_fp_vector_imm_op_3572, 7, vd); - setArg(call_fp_vector_imm_op_3572, 8, vs2); - setArg(call_fp_vector_imm_op_3572, 9, fp_vector_imm_op_3572_arg9); - setArg(call_fp_vector_imm_op_3572, 10, fp_vector_imm_op_3572_arg10); - setArg(call_fp_vector_imm_op_3572, 11, fp_vector_imm_op_3572_arg11); + cc.invoke(&call_fp_vector_imm_op_3588, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3589, 0, reinterpret_cast(this)); + setRet(call_sew_3589, 0, ret_val_sew_3589); + setArg(call_fp_vector_imm_op_3588, 0, V); + setArg(call_fp_vector_imm_op_3588, 1, 4); + setArg(call_fp_vector_imm_op_3588, 2, 5); + setArg(call_fp_vector_imm_op_3588, 3, fp_vector_imm_op_3588_arg3); + setArg(call_fp_vector_imm_op_3588, 4, fp_vector_imm_op_3588_arg4); + setArg(call_fp_vector_imm_op_3588, 5, fp_vector_imm_op_3588_arg5); + setArg(call_fp_vector_imm_op_3588, 6, vm); + setArg(call_fp_vector_imm_op_3588, 7, vd); + setArg(call_fp_vector_imm_op_3588, 8, vs2); + setArg(call_fp_vector_imm_op_3588, 9, fp_vector_imm_op_3588_arg9); + setArg(call_fp_vector_imm_op_3588, 10, fp_vector_imm_op_3588_arg10); + setArg(call_fp_vector_imm_op_3588, 11, fp_vector_imm_op_3588_arg11); } cc.bind(label_merge); } - auto tmp3574 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3574, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3574, 64, false) - , traits::vstart); + auto tmp3590 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3590, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3590, traits::vstart); } cc.bind(label_merge); } @@ -83255,30 +82755,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3575; - x86::Gp ret_val_get_sew_pow_3575 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3575, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3576 = get_reg(cc, 8, false); - mov(cc, tmp3576, 1); + InvokeNode* call_get_sew_pow_3591; + x86::Gp ret_val_get_sew_pow_3591 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3591, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3592 = get_reg(cc, 8, false); + mov(cc, tmp3592, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3576, (ret_val_get_sew_pow_3575))), 8, false), ~ 1); - setArg(call_get_sew_pow_3575, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3575, 0, ret_val_get_sew_pow_3575); + (gen_operation(cc, shl, tmp3592, (ret_val_get_sew_pow_3591))), 8, false), ~ 1); + setArg(call_get_sew_pow_3591, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3591, 0, ret_val_get_sew_pow_3591); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3577; - auto illegal_fp_normal_3577_arg2 = SEW; - auto illegal_fp_normal_3577_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3577 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3577, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3577; - setArg(call_illegal_fp_normal_3577, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3577, 1, vd); - setArg(call_illegal_fp_normal_3577, 2, vm); - setArg(call_illegal_fp_normal_3577, 3, illegal_fp_normal_3577_arg2); - setArg(call_illegal_fp_normal_3577, 4, illegal_fp_normal_3577_arg3); - setRet(call_illegal_fp_normal_3577, 0, ret_val_illegal_fp_normal_3577); + InvokeNode* call_illegal_fp_normal_3593; + auto illegal_fp_normal_3593_arg2 = SEW; + auto illegal_fp_normal_3593_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3593 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3593, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3593; + setArg(call_illegal_fp_normal_3593, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3593, 1, vd); + setArg(call_illegal_fp_normal_3593, 2, vm); + setArg(call_illegal_fp_normal_3593, 3, illegal_fp_normal_3593_arg2); + setArg(call_illegal_fp_normal_3593, 4, illegal_fp_normal_3593_arg3); + setRet(call_illegal_fp_normal_3593, 0, ret_val_illegal_fp_normal_3593); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83294,39 +82794,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3579; - x86::Gp ret_val_sew_3579 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3579, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3578; - auto fp_vector_vector_op_3578_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3578_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3578_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3578_arg10 = rm; - auto fp_vector_vector_op_3578_arg11 = ret_val_sew_3579; + InvokeNode* call_sew_3595; + x86::Gp ret_val_sew_3595 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3595, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3594; + auto fp_vector_vector_op_3594_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3594_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3594_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3594_arg10 = rm; + auto fp_vector_vector_op_3594_arg11 = ret_val_sew_3595; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3578, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3579, 0, reinterpret_cast(this)); - setRet(call_sew_3579, 0, ret_val_sew_3579); - setArg(call_fp_vector_vector_op_3578, 0, V); - setArg(call_fp_vector_vector_op_3578, 1, 4); - setArg(call_fp_vector_vector_op_3578, 2, 1); - setArg(call_fp_vector_vector_op_3578, 3, fp_vector_vector_op_3578_arg3); - setArg(call_fp_vector_vector_op_3578, 4, fp_vector_vector_op_3578_arg4); - setArg(call_fp_vector_vector_op_3578, 5, fp_vector_vector_op_3578_arg5); - setArg(call_fp_vector_vector_op_3578, 6, vm); - setArg(call_fp_vector_vector_op_3578, 7, vd); - setArg(call_fp_vector_vector_op_3578, 8, vs2); - setArg(call_fp_vector_vector_op_3578, 9, vs1); - setArg(call_fp_vector_vector_op_3578, 10, fp_vector_vector_op_3578_arg10); - setArg(call_fp_vector_vector_op_3578, 11, fp_vector_vector_op_3578_arg11); + cc.invoke(&call_fp_vector_vector_op_3594, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3595, 0, reinterpret_cast(this)); + setRet(call_sew_3595, 0, ret_val_sew_3595); + setArg(call_fp_vector_vector_op_3594, 0, V); + setArg(call_fp_vector_vector_op_3594, 1, 4); + setArg(call_fp_vector_vector_op_3594, 2, 1); + setArg(call_fp_vector_vector_op_3594, 3, fp_vector_vector_op_3594_arg3); + setArg(call_fp_vector_vector_op_3594, 4, fp_vector_vector_op_3594_arg4); + setArg(call_fp_vector_vector_op_3594, 5, fp_vector_vector_op_3594_arg5); + setArg(call_fp_vector_vector_op_3594, 6, vm); + setArg(call_fp_vector_vector_op_3594, 7, vd); + setArg(call_fp_vector_vector_op_3594, 8, vs2); + setArg(call_fp_vector_vector_op_3594, 9, vs1); + setArg(call_fp_vector_vector_op_3594, 10, fp_vector_vector_op_3594_arg10); + setArg(call_fp_vector_vector_op_3594, 11, fp_vector_vector_op_3594_arg11); } cc.bind(label_merge); } - auto tmp3580 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3580, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3580, 64, false) - , traits::vstart); + auto tmp3596 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3596, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3596, traits::vstart); } cc.bind(label_merge); } @@ -83370,30 +82868,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3581; - x86::Gp ret_val_get_sew_pow_3581 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3581, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3582 = get_reg(cc, 8, false); - mov(cc, tmp3582, 1); + InvokeNode* call_get_sew_pow_3597; + x86::Gp ret_val_get_sew_pow_3597 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3597, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3598 = get_reg(cc, 8, false); + mov(cc, tmp3598, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3582, (ret_val_get_sew_pow_3581))), 8, false), ~ 1); - setArg(call_get_sew_pow_3581, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3581, 0, ret_val_get_sew_pow_3581); + (gen_operation(cc, shl, tmp3598, (ret_val_get_sew_pow_3597))), 8, false), ~ 1); + setArg(call_get_sew_pow_3597, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3597, 0, ret_val_get_sew_pow_3597); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3583; - auto illegal_fp_normal_3583_arg2 = SEW; - auto illegal_fp_normal_3583_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3583 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3583, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3583; - setArg(call_illegal_fp_normal_3583, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3583, 1, vd); - setArg(call_illegal_fp_normal_3583, 2, vm); - setArg(call_illegal_fp_normal_3583, 3, illegal_fp_normal_3583_arg2); - setArg(call_illegal_fp_normal_3583, 4, illegal_fp_normal_3583_arg3); - setRet(call_illegal_fp_normal_3583, 0, ret_val_illegal_fp_normal_3583); + InvokeNode* call_illegal_fp_normal_3599; + auto illegal_fp_normal_3599_arg2 = SEW; + auto illegal_fp_normal_3599_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3599 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3599, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3599; + setArg(call_illegal_fp_normal_3599, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3599, 1, vd); + setArg(call_illegal_fp_normal_3599, 2, vm); + setArg(call_illegal_fp_normal_3599, 3, illegal_fp_normal_3599_arg2); + setArg(call_illegal_fp_normal_3599, 4, illegal_fp_normal_3599_arg3); + setRet(call_illegal_fp_normal_3599, 0, ret_val_illegal_fp_normal_3599); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83409,41 +82907,39 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3585; - x86::Gp ret_val_sew_3585 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3585, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3584; - auto fp_vector_imm_op_3584_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3584_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3584_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3584_arg9 = gen_ext(cc, + InvokeNode* call_sew_3601; + x86::Gp ret_val_sew_3601 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3601, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3600; + auto fp_vector_imm_op_3600_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3600_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3600_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3600_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3584_arg10 = rm; - auto fp_vector_imm_op_3584_arg11 = ret_val_sew_3585; + auto fp_vector_imm_op_3600_arg10 = rm; + auto fp_vector_imm_op_3600_arg11 = ret_val_sew_3601; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3584, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3585, 0, reinterpret_cast(this)); - setRet(call_sew_3585, 0, ret_val_sew_3585); - setArg(call_fp_vector_imm_op_3584, 0, V); - setArg(call_fp_vector_imm_op_3584, 1, 6); - setArg(call_fp_vector_imm_op_3584, 2, 5); - setArg(call_fp_vector_imm_op_3584, 3, fp_vector_imm_op_3584_arg3); - setArg(call_fp_vector_imm_op_3584, 4, fp_vector_imm_op_3584_arg4); - setArg(call_fp_vector_imm_op_3584, 5, fp_vector_imm_op_3584_arg5); - setArg(call_fp_vector_imm_op_3584, 6, vm); - setArg(call_fp_vector_imm_op_3584, 7, vd); - setArg(call_fp_vector_imm_op_3584, 8, vs2); - setArg(call_fp_vector_imm_op_3584, 9, fp_vector_imm_op_3584_arg9); - setArg(call_fp_vector_imm_op_3584, 10, fp_vector_imm_op_3584_arg10); - setArg(call_fp_vector_imm_op_3584, 11, fp_vector_imm_op_3584_arg11); + cc.invoke(&call_fp_vector_imm_op_3600, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3601, 0, reinterpret_cast(this)); + setRet(call_sew_3601, 0, ret_val_sew_3601); + setArg(call_fp_vector_imm_op_3600, 0, V); + setArg(call_fp_vector_imm_op_3600, 1, 6); + setArg(call_fp_vector_imm_op_3600, 2, 5); + setArg(call_fp_vector_imm_op_3600, 3, fp_vector_imm_op_3600_arg3); + setArg(call_fp_vector_imm_op_3600, 4, fp_vector_imm_op_3600_arg4); + setArg(call_fp_vector_imm_op_3600, 5, fp_vector_imm_op_3600_arg5); + setArg(call_fp_vector_imm_op_3600, 6, vm); + setArg(call_fp_vector_imm_op_3600, 7, vd); + setArg(call_fp_vector_imm_op_3600, 8, vs2); + setArg(call_fp_vector_imm_op_3600, 9, fp_vector_imm_op_3600_arg9); + setArg(call_fp_vector_imm_op_3600, 10, fp_vector_imm_op_3600_arg10); + setArg(call_fp_vector_imm_op_3600, 11, fp_vector_imm_op_3600_arg11); } cc.bind(label_merge); } - auto tmp3586 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3586, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3586, 64, false) - , traits::vstart); + auto tmp3602 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3602, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3602, traits::vstart); } cc.bind(label_merge); } @@ -83487,30 +82983,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3587; - x86::Gp ret_val_get_sew_pow_3587 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3587, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3588 = get_reg(cc, 8, false); - mov(cc, tmp3588, 1); + InvokeNode* call_get_sew_pow_3603; + x86::Gp ret_val_get_sew_pow_3603 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3603, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3604 = get_reg(cc, 8, false); + mov(cc, tmp3604, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3588, (ret_val_get_sew_pow_3587))), 8, false), ~ 1); - setArg(call_get_sew_pow_3587, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3587, 0, ret_val_get_sew_pow_3587); + (gen_operation(cc, shl, tmp3604, (ret_val_get_sew_pow_3603))), 8, false), ~ 1); + setArg(call_get_sew_pow_3603, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3603, 0, ret_val_get_sew_pow_3603); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3589; - auto illegal_fp_normal_3589_arg2 = SEW; - auto illegal_fp_normal_3589_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3589 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3589, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3589; - setArg(call_illegal_fp_normal_3589, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3589, 1, vd); - setArg(call_illegal_fp_normal_3589, 2, vm); - setArg(call_illegal_fp_normal_3589, 3, illegal_fp_normal_3589_arg2); - setArg(call_illegal_fp_normal_3589, 4, illegal_fp_normal_3589_arg3); - setRet(call_illegal_fp_normal_3589, 0, ret_val_illegal_fp_normal_3589); + InvokeNode* call_illegal_fp_normal_3605; + auto illegal_fp_normal_3605_arg2 = SEW; + auto illegal_fp_normal_3605_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3605 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3605, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3605; + setArg(call_illegal_fp_normal_3605, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3605, 1, vd); + setArg(call_illegal_fp_normal_3605, 2, vm); + setArg(call_illegal_fp_normal_3605, 3, illegal_fp_normal_3605_arg2); + setArg(call_illegal_fp_normal_3605, 4, illegal_fp_normal_3605_arg3); + setRet(call_illegal_fp_normal_3605, 0, ret_val_illegal_fp_normal_3605); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83526,39 +83022,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3591; - x86::Gp ret_val_sew_3591 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3591, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3590; - auto fp_vector_vector_op_3590_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3590_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3590_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3590_arg10 = rm; - auto fp_vector_vector_op_3590_arg11 = ret_val_sew_3591; + InvokeNode* call_sew_3607; + x86::Gp ret_val_sew_3607 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3607, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3606; + auto fp_vector_vector_op_3606_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3606_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3606_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3606_arg10 = rm; + auto fp_vector_vector_op_3606_arg11 = ret_val_sew_3607; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3590, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3591, 0, reinterpret_cast(this)); - setRet(call_sew_3591, 0, ret_val_sew_3591); - setArg(call_fp_vector_vector_op_3590, 0, V); - setArg(call_fp_vector_vector_op_3590, 1, 6); - setArg(call_fp_vector_vector_op_3590, 2, 1); - setArg(call_fp_vector_vector_op_3590, 3, fp_vector_vector_op_3590_arg3); - setArg(call_fp_vector_vector_op_3590, 4, fp_vector_vector_op_3590_arg4); - setArg(call_fp_vector_vector_op_3590, 5, fp_vector_vector_op_3590_arg5); - setArg(call_fp_vector_vector_op_3590, 6, vm); - setArg(call_fp_vector_vector_op_3590, 7, vd); - setArg(call_fp_vector_vector_op_3590, 8, vs2); - setArg(call_fp_vector_vector_op_3590, 9, vs1); - setArg(call_fp_vector_vector_op_3590, 10, fp_vector_vector_op_3590_arg10); - setArg(call_fp_vector_vector_op_3590, 11, fp_vector_vector_op_3590_arg11); + cc.invoke(&call_fp_vector_vector_op_3606, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3607, 0, reinterpret_cast(this)); + setRet(call_sew_3607, 0, ret_val_sew_3607); + setArg(call_fp_vector_vector_op_3606, 0, V); + setArg(call_fp_vector_vector_op_3606, 1, 6); + setArg(call_fp_vector_vector_op_3606, 2, 1); + setArg(call_fp_vector_vector_op_3606, 3, fp_vector_vector_op_3606_arg3); + setArg(call_fp_vector_vector_op_3606, 4, fp_vector_vector_op_3606_arg4); + setArg(call_fp_vector_vector_op_3606, 5, fp_vector_vector_op_3606_arg5); + setArg(call_fp_vector_vector_op_3606, 6, vm); + setArg(call_fp_vector_vector_op_3606, 7, vd); + setArg(call_fp_vector_vector_op_3606, 8, vs2); + setArg(call_fp_vector_vector_op_3606, 9, vs1); + setArg(call_fp_vector_vector_op_3606, 10, fp_vector_vector_op_3606_arg10); + setArg(call_fp_vector_vector_op_3606, 11, fp_vector_vector_op_3606_arg11); } cc.bind(label_merge); } - auto tmp3592 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3592, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3592, 64, false) - , traits::vstart); + auto tmp3608 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3608, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3608, traits::vstart); } cc.bind(label_merge); } @@ -83602,30 +83096,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3593; - x86::Gp ret_val_get_sew_pow_3593 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3593, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3594 = get_reg(cc, 8, false); - mov(cc, tmp3594, 1); + InvokeNode* call_get_sew_pow_3609; + x86::Gp ret_val_get_sew_pow_3609 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3609, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3610 = get_reg(cc, 8, false); + mov(cc, tmp3610, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3594, (ret_val_get_sew_pow_3593))), 8, false), ~ 1); - setArg(call_get_sew_pow_3593, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3593, 0, ret_val_get_sew_pow_3593); + (gen_operation(cc, shl, tmp3610, (ret_val_get_sew_pow_3609))), 8, false), ~ 1); + setArg(call_get_sew_pow_3609, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3609, 0, ret_val_get_sew_pow_3609); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3595; - auto illegal_fp_normal_3595_arg2 = SEW; - auto illegal_fp_normal_3595_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3595 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3595, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3595; - setArg(call_illegal_fp_normal_3595, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3595, 1, vd); - setArg(call_illegal_fp_normal_3595, 2, vm); - setArg(call_illegal_fp_normal_3595, 3, illegal_fp_normal_3595_arg2); - setArg(call_illegal_fp_normal_3595, 4, illegal_fp_normal_3595_arg3); - setRet(call_illegal_fp_normal_3595, 0, ret_val_illegal_fp_normal_3595); + InvokeNode* call_illegal_fp_normal_3611; + auto illegal_fp_normal_3611_arg2 = SEW; + auto illegal_fp_normal_3611_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3611 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3611, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3611; + setArg(call_illegal_fp_normal_3611, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3611, 1, vd); + setArg(call_illegal_fp_normal_3611, 2, vm); + setArg(call_illegal_fp_normal_3611, 3, illegal_fp_normal_3611_arg2); + setArg(call_illegal_fp_normal_3611, 4, illegal_fp_normal_3611_arg3); + setRet(call_illegal_fp_normal_3611, 0, ret_val_illegal_fp_normal_3611); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83641,41 +83135,39 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3597; - x86::Gp ret_val_sew_3597 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3597, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3596; - auto fp_vector_imm_op_3596_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3596_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3596_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3596_arg9 = gen_ext(cc, + InvokeNode* call_sew_3613; + x86::Gp ret_val_sew_3613 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3613, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3612; + auto fp_vector_imm_op_3612_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3612_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3612_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3612_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3596_arg10 = rm; - auto fp_vector_imm_op_3596_arg11 = ret_val_sew_3597; + auto fp_vector_imm_op_3612_arg10 = rm; + auto fp_vector_imm_op_3612_arg11 = ret_val_sew_3613; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3596, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3597, 0, reinterpret_cast(this)); - setRet(call_sew_3597, 0, ret_val_sew_3597); - setArg(call_fp_vector_imm_op_3596, 0, V); - setArg(call_fp_vector_imm_op_3596, 1, 8); - setArg(call_fp_vector_imm_op_3596, 2, 5); - setArg(call_fp_vector_imm_op_3596, 3, fp_vector_imm_op_3596_arg3); - setArg(call_fp_vector_imm_op_3596, 4, fp_vector_imm_op_3596_arg4); - setArg(call_fp_vector_imm_op_3596, 5, fp_vector_imm_op_3596_arg5); - setArg(call_fp_vector_imm_op_3596, 6, vm); - setArg(call_fp_vector_imm_op_3596, 7, vd); - setArg(call_fp_vector_imm_op_3596, 8, vs2); - setArg(call_fp_vector_imm_op_3596, 9, fp_vector_imm_op_3596_arg9); - setArg(call_fp_vector_imm_op_3596, 10, fp_vector_imm_op_3596_arg10); - setArg(call_fp_vector_imm_op_3596, 11, fp_vector_imm_op_3596_arg11); + cc.invoke(&call_fp_vector_imm_op_3612, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3613, 0, reinterpret_cast(this)); + setRet(call_sew_3613, 0, ret_val_sew_3613); + setArg(call_fp_vector_imm_op_3612, 0, V); + setArg(call_fp_vector_imm_op_3612, 1, 8); + setArg(call_fp_vector_imm_op_3612, 2, 5); + setArg(call_fp_vector_imm_op_3612, 3, fp_vector_imm_op_3612_arg3); + setArg(call_fp_vector_imm_op_3612, 4, fp_vector_imm_op_3612_arg4); + setArg(call_fp_vector_imm_op_3612, 5, fp_vector_imm_op_3612_arg5); + setArg(call_fp_vector_imm_op_3612, 6, vm); + setArg(call_fp_vector_imm_op_3612, 7, vd); + setArg(call_fp_vector_imm_op_3612, 8, vs2); + setArg(call_fp_vector_imm_op_3612, 9, fp_vector_imm_op_3612_arg9); + setArg(call_fp_vector_imm_op_3612, 10, fp_vector_imm_op_3612_arg10); + setArg(call_fp_vector_imm_op_3612, 11, fp_vector_imm_op_3612_arg11); } cc.bind(label_merge); } - auto tmp3598 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3598, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3598, 64, false) - , traits::vstart); + auto tmp3614 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3614, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3614, traits::vstart); } cc.bind(label_merge); } @@ -83719,30 +83211,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3599; - x86::Gp ret_val_get_sew_pow_3599 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3599, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3600 = get_reg(cc, 8, false); - mov(cc, tmp3600, 1); + InvokeNode* call_get_sew_pow_3615; + x86::Gp ret_val_get_sew_pow_3615 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3615, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3616 = get_reg(cc, 8, false); + mov(cc, tmp3616, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3600, (ret_val_get_sew_pow_3599))), 8, false), ~ 1); - setArg(call_get_sew_pow_3599, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3599, 0, ret_val_get_sew_pow_3599); + (gen_operation(cc, shl, tmp3616, (ret_val_get_sew_pow_3615))), 8, false), ~ 1); + setArg(call_get_sew_pow_3615, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3615, 0, ret_val_get_sew_pow_3615); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3601; - auto illegal_fp_normal_3601_arg2 = SEW; - auto illegal_fp_normal_3601_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3601 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3601, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3601; - setArg(call_illegal_fp_normal_3601, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3601, 1, vd); - setArg(call_illegal_fp_normal_3601, 2, vm); - setArg(call_illegal_fp_normal_3601, 3, illegal_fp_normal_3601_arg2); - setArg(call_illegal_fp_normal_3601, 4, illegal_fp_normal_3601_arg3); - setRet(call_illegal_fp_normal_3601, 0, ret_val_illegal_fp_normal_3601); + InvokeNode* call_illegal_fp_normal_3617; + auto illegal_fp_normal_3617_arg2 = SEW; + auto illegal_fp_normal_3617_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3617 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3617, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3617; + setArg(call_illegal_fp_normal_3617, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3617, 1, vd); + setArg(call_illegal_fp_normal_3617, 2, vm); + setArg(call_illegal_fp_normal_3617, 3, illegal_fp_normal_3617_arg2); + setArg(call_illegal_fp_normal_3617, 4, illegal_fp_normal_3617_arg3); + setRet(call_illegal_fp_normal_3617, 0, ret_val_illegal_fp_normal_3617); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83758,39 +83250,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3603; - x86::Gp ret_val_sew_3603 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3603, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3602; - auto fp_vector_vector_op_3602_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3602_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3602_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3602_arg10 = rm; - auto fp_vector_vector_op_3602_arg11 = ret_val_sew_3603; + InvokeNode* call_sew_3619; + x86::Gp ret_val_sew_3619 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3619, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3618; + auto fp_vector_vector_op_3618_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3618_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3618_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3618_arg10 = rm; + auto fp_vector_vector_op_3618_arg11 = ret_val_sew_3619; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3602, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3603, 0, reinterpret_cast(this)); - setRet(call_sew_3603, 0, ret_val_sew_3603); - setArg(call_fp_vector_vector_op_3602, 0, V); - setArg(call_fp_vector_vector_op_3602, 1, 8); - setArg(call_fp_vector_vector_op_3602, 2, 1); - setArg(call_fp_vector_vector_op_3602, 3, fp_vector_vector_op_3602_arg3); - setArg(call_fp_vector_vector_op_3602, 4, fp_vector_vector_op_3602_arg4); - setArg(call_fp_vector_vector_op_3602, 5, fp_vector_vector_op_3602_arg5); - setArg(call_fp_vector_vector_op_3602, 6, vm); - setArg(call_fp_vector_vector_op_3602, 7, vd); - setArg(call_fp_vector_vector_op_3602, 8, vs2); - setArg(call_fp_vector_vector_op_3602, 9, vs1); - setArg(call_fp_vector_vector_op_3602, 10, fp_vector_vector_op_3602_arg10); - setArg(call_fp_vector_vector_op_3602, 11, fp_vector_vector_op_3602_arg11); + cc.invoke(&call_fp_vector_vector_op_3618, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3619, 0, reinterpret_cast(this)); + setRet(call_sew_3619, 0, ret_val_sew_3619); + setArg(call_fp_vector_vector_op_3618, 0, V); + setArg(call_fp_vector_vector_op_3618, 1, 8); + setArg(call_fp_vector_vector_op_3618, 2, 1); + setArg(call_fp_vector_vector_op_3618, 3, fp_vector_vector_op_3618_arg3); + setArg(call_fp_vector_vector_op_3618, 4, fp_vector_vector_op_3618_arg4); + setArg(call_fp_vector_vector_op_3618, 5, fp_vector_vector_op_3618_arg5); + setArg(call_fp_vector_vector_op_3618, 6, vm); + setArg(call_fp_vector_vector_op_3618, 7, vd); + setArg(call_fp_vector_vector_op_3618, 8, vs2); + setArg(call_fp_vector_vector_op_3618, 9, vs1); + setArg(call_fp_vector_vector_op_3618, 10, fp_vector_vector_op_3618_arg10); + setArg(call_fp_vector_vector_op_3618, 11, fp_vector_vector_op_3618_arg11); } cc.bind(label_merge); } - auto tmp3604 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3604, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3604, 64, false) - , traits::vstart); + auto tmp3620 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3620, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3620, traits::vstart); } cc.bind(label_merge); } @@ -83834,30 +83324,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3605; - x86::Gp ret_val_get_sew_pow_3605 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3605, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3606 = get_reg(cc, 8, false); - mov(cc, tmp3606, 1); + InvokeNode* call_get_sew_pow_3621; + x86::Gp ret_val_get_sew_pow_3621 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3621, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3622 = get_reg(cc, 8, false); + mov(cc, tmp3622, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3606, (ret_val_get_sew_pow_3605))), 8, false), ~ 1); - setArg(call_get_sew_pow_3605, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3605, 0, ret_val_get_sew_pow_3605); + (gen_operation(cc, shl, tmp3622, (ret_val_get_sew_pow_3621))), 8, false), ~ 1); + setArg(call_get_sew_pow_3621, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3621, 0, ret_val_get_sew_pow_3621); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3607; - auto illegal_fp_normal_3607_arg2 = SEW; - auto illegal_fp_normal_3607_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3607 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3607, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3607; - setArg(call_illegal_fp_normal_3607, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3607, 1, vd); - setArg(call_illegal_fp_normal_3607, 2, vm); - setArg(call_illegal_fp_normal_3607, 3, illegal_fp_normal_3607_arg2); - setArg(call_illegal_fp_normal_3607, 4, illegal_fp_normal_3607_arg3); - setRet(call_illegal_fp_normal_3607, 0, ret_val_illegal_fp_normal_3607); + InvokeNode* call_illegal_fp_normal_3623; + auto illegal_fp_normal_3623_arg2 = SEW; + auto illegal_fp_normal_3623_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3623 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3623, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3623; + setArg(call_illegal_fp_normal_3623, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3623, 1, vd); + setArg(call_illegal_fp_normal_3623, 2, vm); + setArg(call_illegal_fp_normal_3623, 3, illegal_fp_normal_3623_arg2); + setArg(call_illegal_fp_normal_3623, 4, illegal_fp_normal_3623_arg3); + setRet(call_illegal_fp_normal_3623, 0, ret_val_illegal_fp_normal_3623); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83873,41 +83363,39 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3609; - x86::Gp ret_val_sew_3609 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3609, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3608; - auto fp_vector_imm_op_3608_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3608_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3608_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3608_arg9 = gen_ext(cc, + InvokeNode* call_sew_3625; + x86::Gp ret_val_sew_3625 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3625, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3624; + auto fp_vector_imm_op_3624_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3624_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3624_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3624_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3608_arg10 = rm; - auto fp_vector_imm_op_3608_arg11 = ret_val_sew_3609; + auto fp_vector_imm_op_3624_arg10 = rm; + auto fp_vector_imm_op_3624_arg11 = ret_val_sew_3625; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3608, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3609, 0, reinterpret_cast(this)); - setRet(call_sew_3609, 0, ret_val_sew_3609); - setArg(call_fp_vector_imm_op_3608, 0, V); - setArg(call_fp_vector_imm_op_3608, 1, 9); - setArg(call_fp_vector_imm_op_3608, 2, 5); - setArg(call_fp_vector_imm_op_3608, 3, fp_vector_imm_op_3608_arg3); - setArg(call_fp_vector_imm_op_3608, 4, fp_vector_imm_op_3608_arg4); - setArg(call_fp_vector_imm_op_3608, 5, fp_vector_imm_op_3608_arg5); - setArg(call_fp_vector_imm_op_3608, 6, vm); - setArg(call_fp_vector_imm_op_3608, 7, vd); - setArg(call_fp_vector_imm_op_3608, 8, vs2); - setArg(call_fp_vector_imm_op_3608, 9, fp_vector_imm_op_3608_arg9); - setArg(call_fp_vector_imm_op_3608, 10, fp_vector_imm_op_3608_arg10); - setArg(call_fp_vector_imm_op_3608, 11, fp_vector_imm_op_3608_arg11); + cc.invoke(&call_fp_vector_imm_op_3624, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3625, 0, reinterpret_cast(this)); + setRet(call_sew_3625, 0, ret_val_sew_3625); + setArg(call_fp_vector_imm_op_3624, 0, V); + setArg(call_fp_vector_imm_op_3624, 1, 9); + setArg(call_fp_vector_imm_op_3624, 2, 5); + setArg(call_fp_vector_imm_op_3624, 3, fp_vector_imm_op_3624_arg3); + setArg(call_fp_vector_imm_op_3624, 4, fp_vector_imm_op_3624_arg4); + setArg(call_fp_vector_imm_op_3624, 5, fp_vector_imm_op_3624_arg5); + setArg(call_fp_vector_imm_op_3624, 6, vm); + setArg(call_fp_vector_imm_op_3624, 7, vd); + setArg(call_fp_vector_imm_op_3624, 8, vs2); + setArg(call_fp_vector_imm_op_3624, 9, fp_vector_imm_op_3624_arg9); + setArg(call_fp_vector_imm_op_3624, 10, fp_vector_imm_op_3624_arg10); + setArg(call_fp_vector_imm_op_3624, 11, fp_vector_imm_op_3624_arg11); } cc.bind(label_merge); } - auto tmp3610 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3610, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3610, 64, false) - , traits::vstart); + auto tmp3626 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3626, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3626, traits::vstart); } cc.bind(label_merge); } @@ -83951,30 +83439,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3611; - x86::Gp ret_val_get_sew_pow_3611 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3611, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3612 = get_reg(cc, 8, false); - mov(cc, tmp3612, 1); + InvokeNode* call_get_sew_pow_3627; + x86::Gp ret_val_get_sew_pow_3627 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3627, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3628 = get_reg(cc, 8, false); + mov(cc, tmp3628, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3612, (ret_val_get_sew_pow_3611))), 8, false), ~ 1); - setArg(call_get_sew_pow_3611, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3611, 0, ret_val_get_sew_pow_3611); + (gen_operation(cc, shl, tmp3628, (ret_val_get_sew_pow_3627))), 8, false), ~ 1); + setArg(call_get_sew_pow_3627, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3627, 0, ret_val_get_sew_pow_3627); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3613; - auto illegal_fp_normal_3613_arg2 = SEW; - auto illegal_fp_normal_3613_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3613 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3613, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3613; - setArg(call_illegal_fp_normal_3613, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3613, 1, vd); - setArg(call_illegal_fp_normal_3613, 2, vm); - setArg(call_illegal_fp_normal_3613, 3, illegal_fp_normal_3613_arg2); - setArg(call_illegal_fp_normal_3613, 4, illegal_fp_normal_3613_arg3); - setRet(call_illegal_fp_normal_3613, 0, ret_val_illegal_fp_normal_3613); + InvokeNode* call_illegal_fp_normal_3629; + auto illegal_fp_normal_3629_arg2 = SEW; + auto illegal_fp_normal_3629_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3629 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3629, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3629; + setArg(call_illegal_fp_normal_3629, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3629, 1, vd); + setArg(call_illegal_fp_normal_3629, 2, vm); + setArg(call_illegal_fp_normal_3629, 3, illegal_fp_normal_3629_arg2); + setArg(call_illegal_fp_normal_3629, 4, illegal_fp_normal_3629_arg3); + setRet(call_illegal_fp_normal_3629, 0, ret_val_illegal_fp_normal_3629); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -83990,39 +83478,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3615; - x86::Gp ret_val_sew_3615 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3615, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3614; - auto fp_vector_vector_op_3614_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3614_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3614_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3614_arg10 = rm; - auto fp_vector_vector_op_3614_arg11 = ret_val_sew_3615; + InvokeNode* call_sew_3631; + x86::Gp ret_val_sew_3631 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3631, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3630; + auto fp_vector_vector_op_3630_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3630_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3630_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3630_arg10 = rm; + auto fp_vector_vector_op_3630_arg11 = ret_val_sew_3631; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3614, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3615, 0, reinterpret_cast(this)); - setRet(call_sew_3615, 0, ret_val_sew_3615); - setArg(call_fp_vector_vector_op_3614, 0, V); - setArg(call_fp_vector_vector_op_3614, 1, 9); - setArg(call_fp_vector_vector_op_3614, 2, 1); - setArg(call_fp_vector_vector_op_3614, 3, fp_vector_vector_op_3614_arg3); - setArg(call_fp_vector_vector_op_3614, 4, fp_vector_vector_op_3614_arg4); - setArg(call_fp_vector_vector_op_3614, 5, fp_vector_vector_op_3614_arg5); - setArg(call_fp_vector_vector_op_3614, 6, vm); - setArg(call_fp_vector_vector_op_3614, 7, vd); - setArg(call_fp_vector_vector_op_3614, 8, vs2); - setArg(call_fp_vector_vector_op_3614, 9, vs1); - setArg(call_fp_vector_vector_op_3614, 10, fp_vector_vector_op_3614_arg10); - setArg(call_fp_vector_vector_op_3614, 11, fp_vector_vector_op_3614_arg11); + cc.invoke(&call_fp_vector_vector_op_3630, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3631, 0, reinterpret_cast(this)); + setRet(call_sew_3631, 0, ret_val_sew_3631); + setArg(call_fp_vector_vector_op_3630, 0, V); + setArg(call_fp_vector_vector_op_3630, 1, 9); + setArg(call_fp_vector_vector_op_3630, 2, 1); + setArg(call_fp_vector_vector_op_3630, 3, fp_vector_vector_op_3630_arg3); + setArg(call_fp_vector_vector_op_3630, 4, fp_vector_vector_op_3630_arg4); + setArg(call_fp_vector_vector_op_3630, 5, fp_vector_vector_op_3630_arg5); + setArg(call_fp_vector_vector_op_3630, 6, vm); + setArg(call_fp_vector_vector_op_3630, 7, vd); + setArg(call_fp_vector_vector_op_3630, 8, vs2); + setArg(call_fp_vector_vector_op_3630, 9, vs1); + setArg(call_fp_vector_vector_op_3630, 10, fp_vector_vector_op_3630_arg10); + setArg(call_fp_vector_vector_op_3630, 11, fp_vector_vector_op_3630_arg11); } cc.bind(label_merge); } - auto tmp3616 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3616, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3616, 64, false) - , traits::vstart); + auto tmp3632 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3632, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3632, traits::vstart); } cc.bind(label_merge); } @@ -84066,30 +83552,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3617; - x86::Gp ret_val_get_sew_pow_3617 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3617, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3618 = get_reg(cc, 8, false); - mov(cc, tmp3618, 1); + InvokeNode* call_get_sew_pow_3633; + x86::Gp ret_val_get_sew_pow_3633 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3633, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3634 = get_reg(cc, 8, false); + mov(cc, tmp3634, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3618, (ret_val_get_sew_pow_3617))), 8, false), ~ 1); - setArg(call_get_sew_pow_3617, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3617, 0, ret_val_get_sew_pow_3617); + (gen_operation(cc, shl, tmp3634, (ret_val_get_sew_pow_3633))), 8, false), ~ 1); + setArg(call_get_sew_pow_3633, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3633, 0, ret_val_get_sew_pow_3633); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3619; - auto illegal_fp_normal_3619_arg2 = SEW; - auto illegal_fp_normal_3619_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3619 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3619, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3619; - setArg(call_illegal_fp_normal_3619, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3619, 1, vd); - setArg(call_illegal_fp_normal_3619, 2, vm); - setArg(call_illegal_fp_normal_3619, 3, illegal_fp_normal_3619_arg2); - setArg(call_illegal_fp_normal_3619, 4, illegal_fp_normal_3619_arg3); - setRet(call_illegal_fp_normal_3619, 0, ret_val_illegal_fp_normal_3619); + InvokeNode* call_illegal_fp_normal_3635; + auto illegal_fp_normal_3635_arg2 = SEW; + auto illegal_fp_normal_3635_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3635 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3635, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3635; + setArg(call_illegal_fp_normal_3635, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3635, 1, vd); + setArg(call_illegal_fp_normal_3635, 2, vm); + setArg(call_illegal_fp_normal_3635, 3, illegal_fp_normal_3635_arg2); + setArg(call_illegal_fp_normal_3635, 4, illegal_fp_normal_3635_arg3); + setRet(call_illegal_fp_normal_3635, 0, ret_val_illegal_fp_normal_3635); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -84105,41 +83591,39 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3621; - x86::Gp ret_val_sew_3621 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3621, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_imm_op_3620; - auto fp_vector_imm_op_3620_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_imm_op_3620_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_imm_op_3620_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_imm_op_3620_arg9 = gen_ext(cc, + InvokeNode* call_sew_3637; + x86::Gp ret_val_sew_3637 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3637, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_imm_op_3636; + auto fp_vector_imm_op_3636_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_imm_op_3636_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_imm_op_3636_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_imm_op_3636_arg9 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto fp_vector_imm_op_3620_arg10 = rm; - auto fp_vector_imm_op_3620_arg11 = ret_val_sew_3621; + auto fp_vector_imm_op_3636_arg10 = rm; + auto fp_vector_imm_op_3636_arg11 = ret_val_sew_3637; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_imm_op_3620, &fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3621, 0, reinterpret_cast(this)); - setRet(call_sew_3621, 0, ret_val_sew_3621); - setArg(call_fp_vector_imm_op_3620, 0, V); - setArg(call_fp_vector_imm_op_3620, 1, 10); - setArg(call_fp_vector_imm_op_3620, 2, 5); - setArg(call_fp_vector_imm_op_3620, 3, fp_vector_imm_op_3620_arg3); - setArg(call_fp_vector_imm_op_3620, 4, fp_vector_imm_op_3620_arg4); - setArg(call_fp_vector_imm_op_3620, 5, fp_vector_imm_op_3620_arg5); - setArg(call_fp_vector_imm_op_3620, 6, vm); - setArg(call_fp_vector_imm_op_3620, 7, vd); - setArg(call_fp_vector_imm_op_3620, 8, vs2); - setArg(call_fp_vector_imm_op_3620, 9, fp_vector_imm_op_3620_arg9); - setArg(call_fp_vector_imm_op_3620, 10, fp_vector_imm_op_3620_arg10); - setArg(call_fp_vector_imm_op_3620, 11, fp_vector_imm_op_3620_arg11); + cc.invoke(&call_fp_vector_imm_op_3636, &fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3637, 0, reinterpret_cast(this)); + setRet(call_sew_3637, 0, ret_val_sew_3637); + setArg(call_fp_vector_imm_op_3636, 0, V); + setArg(call_fp_vector_imm_op_3636, 1, 10); + setArg(call_fp_vector_imm_op_3636, 2, 5); + setArg(call_fp_vector_imm_op_3636, 3, fp_vector_imm_op_3636_arg3); + setArg(call_fp_vector_imm_op_3636, 4, fp_vector_imm_op_3636_arg4); + setArg(call_fp_vector_imm_op_3636, 5, fp_vector_imm_op_3636_arg5); + setArg(call_fp_vector_imm_op_3636, 6, vm); + setArg(call_fp_vector_imm_op_3636, 7, vd); + setArg(call_fp_vector_imm_op_3636, 8, vs2); + setArg(call_fp_vector_imm_op_3636, 9, fp_vector_imm_op_3636_arg9); + setArg(call_fp_vector_imm_op_3636, 10, fp_vector_imm_op_3636_arg10); + setArg(call_fp_vector_imm_op_3636, 11, fp_vector_imm_op_3636_arg11); } cc.bind(label_merge); } - auto tmp3622 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3622, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3622, 64, false) - , traits::vstart); + auto tmp3638 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3638, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3638, traits::vstart); } cc.bind(label_merge); } @@ -84183,30 +83667,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3623; - x86::Gp ret_val_get_sew_pow_3623 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3623, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3624 = get_reg(cc, 8, false); - mov(cc, tmp3624, 1); + InvokeNode* call_get_sew_pow_3639; + x86::Gp ret_val_get_sew_pow_3639 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3639, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3640 = get_reg(cc, 8, false); + mov(cc, tmp3640, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3624, (ret_val_get_sew_pow_3623))), 8, false), ~ 1); - setArg(call_get_sew_pow_3623, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3623, 0, ret_val_get_sew_pow_3623); + (gen_operation(cc, shl, tmp3640, (ret_val_get_sew_pow_3639))), 8, false), ~ 1); + setArg(call_get_sew_pow_3639, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3639, 0, ret_val_get_sew_pow_3639); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3625; - auto illegal_fp_normal_3625_arg2 = SEW; - auto illegal_fp_normal_3625_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3625 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3625, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3625; - setArg(call_illegal_fp_normal_3625, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3625, 1, vd); - setArg(call_illegal_fp_normal_3625, 2, vm); - setArg(call_illegal_fp_normal_3625, 3, illegal_fp_normal_3625_arg2); - setArg(call_illegal_fp_normal_3625, 4, illegal_fp_normal_3625_arg3); - setRet(call_illegal_fp_normal_3625, 0, ret_val_illegal_fp_normal_3625); + InvokeNode* call_illegal_fp_normal_3641; + auto illegal_fp_normal_3641_arg2 = SEW; + auto illegal_fp_normal_3641_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3641 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3641, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3641; + setArg(call_illegal_fp_normal_3641, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3641, 1, vd); + setArg(call_illegal_fp_normal_3641, 2, vm); + setArg(call_illegal_fp_normal_3641, 3, illegal_fp_normal_3641_arg2); + setArg(call_illegal_fp_normal_3641, 4, illegal_fp_normal_3641_arg3); + setRet(call_illegal_fp_normal_3641, 0, ret_val_illegal_fp_normal_3641); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -84222,39 +83706,37 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3627; - x86::Gp ret_val_sew_3627 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3627, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_vector_op_3626; - auto fp_vector_vector_op_3626_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_vector_op_3626_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_vector_op_3626_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_vector_op_3626_arg10 = rm; - auto fp_vector_vector_op_3626_arg11 = ret_val_sew_3627; + InvokeNode* call_sew_3643; + x86::Gp ret_val_sew_3643 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3643, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_vector_op_3642; + auto fp_vector_vector_op_3642_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_vector_op_3642_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_vector_op_3642_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_vector_op_3642_arg10 = rm; + auto fp_vector_vector_op_3642_arg11 = ret_val_sew_3643; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_vector_op_3626, &fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3627, 0, reinterpret_cast(this)); - setRet(call_sew_3627, 0, ret_val_sew_3627); - setArg(call_fp_vector_vector_op_3626, 0, V); - setArg(call_fp_vector_vector_op_3626, 1, 10); - setArg(call_fp_vector_vector_op_3626, 2, 1); - setArg(call_fp_vector_vector_op_3626, 3, fp_vector_vector_op_3626_arg3); - setArg(call_fp_vector_vector_op_3626, 4, fp_vector_vector_op_3626_arg4); - setArg(call_fp_vector_vector_op_3626, 5, fp_vector_vector_op_3626_arg5); - setArg(call_fp_vector_vector_op_3626, 6, vm); - setArg(call_fp_vector_vector_op_3626, 7, vd); - setArg(call_fp_vector_vector_op_3626, 8, vs2); - setArg(call_fp_vector_vector_op_3626, 9, vs1); - setArg(call_fp_vector_vector_op_3626, 10, fp_vector_vector_op_3626_arg10); - setArg(call_fp_vector_vector_op_3626, 11, fp_vector_vector_op_3626_arg11); + cc.invoke(&call_fp_vector_vector_op_3642, &fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3643, 0, reinterpret_cast(this)); + setRet(call_sew_3643, 0, ret_val_sew_3643); + setArg(call_fp_vector_vector_op_3642, 0, V); + setArg(call_fp_vector_vector_op_3642, 1, 10); + setArg(call_fp_vector_vector_op_3642, 2, 1); + setArg(call_fp_vector_vector_op_3642, 3, fp_vector_vector_op_3642_arg3); + setArg(call_fp_vector_vector_op_3642, 4, fp_vector_vector_op_3642_arg4); + setArg(call_fp_vector_vector_op_3642, 5, fp_vector_vector_op_3642_arg5); + setArg(call_fp_vector_vector_op_3642, 6, vm); + setArg(call_fp_vector_vector_op_3642, 7, vd); + setArg(call_fp_vector_vector_op_3642, 8, vs2); + setArg(call_fp_vector_vector_op_3642, 9, vs1); + setArg(call_fp_vector_vector_op_3642, 10, fp_vector_vector_op_3642_arg10); + setArg(call_fp_vector_vector_op_3642, 11, fp_vector_vector_op_3642_arg11); } cc.bind(label_merge); } - auto tmp3628 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3628, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3628, 64, false) - , traits::vstart); + auto tmp3644 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3644, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3644, traits::vstart); } cc.bind(label_merge); } @@ -84298,28 +83780,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3629; - x86::Gp ret_val_get_sew_pow_3629 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3629, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3630 = get_reg(cc, 8, false); - mov(cc, tmp3630, 1); + InvokeNode* call_get_sew_pow_3645; + x86::Gp ret_val_get_sew_pow_3645 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3645, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3646 = get_reg(cc, 8, false); + mov(cc, tmp3646, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3630, (ret_val_get_sew_pow_3629))), 8, false), ~ 1); - setArg(call_get_sew_pow_3629, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3629, 0, ret_val_get_sew_pow_3629); + (gen_operation(cc, shl, tmp3646, (ret_val_get_sew_pow_3645))), 8, false), ~ 1); + setArg(call_get_sew_pow_3645, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3645, 0, ret_val_get_sew_pow_3645); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3631; - auto illegal_fp_vd_unmasked_3631_arg0 = SEW; - auto illegal_fp_vd_unmasked_3631_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3631 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3631, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3631; - setArg(call_illegal_fp_vd_unmasked_3631, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3631, 1, illegal_fp_vd_unmasked_3631_arg0); - setArg(call_illegal_fp_vd_unmasked_3631, 2, illegal_fp_vd_unmasked_3631_arg1); - setRet(call_illegal_fp_vd_unmasked_3631, 0, ret_val_illegal_fp_vd_unmasked_3631); + InvokeNode* call_illegal_fp_vd_unmasked_3647; + auto illegal_fp_vd_unmasked_3647_arg0 = SEW; + auto illegal_fp_vd_unmasked_3647_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3647 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3647, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3647; + setArg(call_illegal_fp_vd_unmasked_3647, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3647, 1, illegal_fp_vd_unmasked_3647_arg0); + setArg(call_illegal_fp_vd_unmasked_3647, 2, illegal_fp_vd_unmasked_3647_arg1); + setRet(call_illegal_fp_vd_unmasked_3647, 0, ret_val_illegal_fp_vd_unmasked_3647); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -84335,46 +83817,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3633; - x86::Gp ret_val_sew_3633 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3633, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3632; - auto mask_fp_vector_imm_op_3632_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3632_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3632_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3632_arg8 = gen_ext(cc, + InvokeNode* call_sew_3649; + x86::Gp ret_val_sew_3649 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3649, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3648; + auto mask_fp_vector_imm_op_3648_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3648_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3648_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3648_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto mask_fp_vector_imm_op_3632_arg9 = rm; - auto mask_fp_vector_imm_op_3632_arg10 = ret_val_sew_3633; + auto mask_fp_vector_imm_op_3648_arg9 = rm; + auto mask_fp_vector_imm_op_3648_arg10 = ret_val_sew_3649; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3632, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3633, 0, reinterpret_cast(this)); - setRet(call_sew_3633, 0, ret_val_sew_3633); - setArg(call_mask_fp_vector_imm_op_3632, 0, V); - setArg(call_mask_fp_vector_imm_op_3632, 1, 24); - setArg(call_mask_fp_vector_imm_op_3632, 2, mask_fp_vector_imm_op_3632_arg2); - setArg(call_mask_fp_vector_imm_op_3632, 3, mask_fp_vector_imm_op_3632_arg3); - setArg(call_mask_fp_vector_imm_op_3632, 4, mask_fp_vector_imm_op_3632_arg4); - setArg(call_mask_fp_vector_imm_op_3632, 5, vm); - setArg(call_mask_fp_vector_imm_op_3632, 6, vd); - setArg(call_mask_fp_vector_imm_op_3632, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3632, 8, mask_fp_vector_imm_op_3632_arg8); - setArg(call_mask_fp_vector_imm_op_3632, 9, mask_fp_vector_imm_op_3632_arg9); - setArg(call_mask_fp_vector_imm_op_3632, 10, mask_fp_vector_imm_op_3632_arg10); - InvokeNode* call_fget_flags_3634; - x86::Gp ret_val_fget_flags_3634 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3634, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3634; - setRet(call_fget_flags_3634, 0, ret_val_fget_flags_3634); + cc.invoke(&call_mask_fp_vector_imm_op_3648, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3649, 0, reinterpret_cast(this)); + setRet(call_sew_3649, 0, ret_val_sew_3649); + setArg(call_mask_fp_vector_imm_op_3648, 0, V); + setArg(call_mask_fp_vector_imm_op_3648, 1, 24); + setArg(call_mask_fp_vector_imm_op_3648, 2, mask_fp_vector_imm_op_3648_arg2); + setArg(call_mask_fp_vector_imm_op_3648, 3, mask_fp_vector_imm_op_3648_arg3); + setArg(call_mask_fp_vector_imm_op_3648, 4, mask_fp_vector_imm_op_3648_arg4); + setArg(call_mask_fp_vector_imm_op_3648, 5, vm); + setArg(call_mask_fp_vector_imm_op_3648, 6, vd); + setArg(call_mask_fp_vector_imm_op_3648, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3648, 8, mask_fp_vector_imm_op_3648_arg8); + setArg(call_mask_fp_vector_imm_op_3648, 9, mask_fp_vector_imm_op_3648_arg9); + setArg(call_mask_fp_vector_imm_op_3648, 10, mask_fp_vector_imm_op_3648_arg10); + InvokeNode* call_fget_flags_3650; + x86::Gp ret_val_fget_flags_3650 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3650, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3650; + setRet(call_fget_flags_3650, 0, ret_val_fget_flags_3650); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3635 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3635, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3635, 64, false) - , traits::vstart); + auto tmp3651 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3651, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3651, traits::vstart); } cc.bind(label_merge); } @@ -84418,28 +83898,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3636; - x86::Gp ret_val_get_sew_pow_3636 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3636, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3637 = get_reg(cc, 8, false); - mov(cc, tmp3637, 1); + InvokeNode* call_get_sew_pow_3652; + x86::Gp ret_val_get_sew_pow_3652 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3652, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3653 = get_reg(cc, 8, false); + mov(cc, tmp3653, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3637, (ret_val_get_sew_pow_3636))), 8, false), ~ 1); - setArg(call_get_sew_pow_3636, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3636, 0, ret_val_get_sew_pow_3636); + (gen_operation(cc, shl, tmp3653, (ret_val_get_sew_pow_3652))), 8, false), ~ 1); + setArg(call_get_sew_pow_3652, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3652, 0, ret_val_get_sew_pow_3652); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3638; - auto illegal_fp_vd_unmasked_3638_arg0 = SEW; - auto illegal_fp_vd_unmasked_3638_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3638 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3638, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3638; - setArg(call_illegal_fp_vd_unmasked_3638, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3638, 1, illegal_fp_vd_unmasked_3638_arg0); - setArg(call_illegal_fp_vd_unmasked_3638, 2, illegal_fp_vd_unmasked_3638_arg1); - setRet(call_illegal_fp_vd_unmasked_3638, 0, ret_val_illegal_fp_vd_unmasked_3638); + InvokeNode* call_illegal_fp_vd_unmasked_3654; + auto illegal_fp_vd_unmasked_3654_arg0 = SEW; + auto illegal_fp_vd_unmasked_3654_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3654 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3654, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3654; + setArg(call_illegal_fp_vd_unmasked_3654, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3654, 1, illegal_fp_vd_unmasked_3654_arg0); + setArg(call_illegal_fp_vd_unmasked_3654, 2, illegal_fp_vd_unmasked_3654_arg1); + setRet(call_illegal_fp_vd_unmasked_3654, 0, ret_val_illegal_fp_vd_unmasked_3654); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -84455,44 +83935,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3640; - x86::Gp ret_val_sew_3640 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3640, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_vector_op_3639; - auto mask_fp_vector_vector_op_3639_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_vector_op_3639_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_vector_op_3639_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_vector_op_3639_arg9 = rm; - auto mask_fp_vector_vector_op_3639_arg10 = ret_val_sew_3640; + InvokeNode* call_sew_3656; + x86::Gp ret_val_sew_3656 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3656, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3655; + auto mask_fp_vector_vector_op_3655_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3655_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3655_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3655_arg9 = rm; + auto mask_fp_vector_vector_op_3655_arg10 = ret_val_sew_3656; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_vector_op_3639, &mask_fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3640, 0, reinterpret_cast(this)); - setRet(call_sew_3640, 0, ret_val_sew_3640); - setArg(call_mask_fp_vector_vector_op_3639, 0, V); - setArg(call_mask_fp_vector_vector_op_3639, 1, 24); - setArg(call_mask_fp_vector_vector_op_3639, 2, mask_fp_vector_vector_op_3639_arg2); - setArg(call_mask_fp_vector_vector_op_3639, 3, mask_fp_vector_vector_op_3639_arg3); - setArg(call_mask_fp_vector_vector_op_3639, 4, mask_fp_vector_vector_op_3639_arg4); - setArg(call_mask_fp_vector_vector_op_3639, 5, vm); - setArg(call_mask_fp_vector_vector_op_3639, 6, vd); - setArg(call_mask_fp_vector_vector_op_3639, 7, vs2); - setArg(call_mask_fp_vector_vector_op_3639, 8, vs1); - setArg(call_mask_fp_vector_vector_op_3639, 9, mask_fp_vector_vector_op_3639_arg9); - setArg(call_mask_fp_vector_vector_op_3639, 10, mask_fp_vector_vector_op_3639_arg10); - InvokeNode* call_fget_flags_3641; - x86::Gp ret_val_fget_flags_3641 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3641, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3641; - setRet(call_fget_flags_3641, 0, ret_val_fget_flags_3641); + cc.invoke(&call_mask_fp_vector_vector_op_3655, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3656, 0, reinterpret_cast(this)); + setRet(call_sew_3656, 0, ret_val_sew_3656); + setArg(call_mask_fp_vector_vector_op_3655, 0, V); + setArg(call_mask_fp_vector_vector_op_3655, 1, 24); + setArg(call_mask_fp_vector_vector_op_3655, 2, mask_fp_vector_vector_op_3655_arg2); + setArg(call_mask_fp_vector_vector_op_3655, 3, mask_fp_vector_vector_op_3655_arg3); + setArg(call_mask_fp_vector_vector_op_3655, 4, mask_fp_vector_vector_op_3655_arg4); + setArg(call_mask_fp_vector_vector_op_3655, 5, vm); + setArg(call_mask_fp_vector_vector_op_3655, 6, vd); + setArg(call_mask_fp_vector_vector_op_3655, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3655, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3655, 9, mask_fp_vector_vector_op_3655_arg9); + setArg(call_mask_fp_vector_vector_op_3655, 10, mask_fp_vector_vector_op_3655_arg10); + InvokeNode* call_fget_flags_3657; + x86::Gp ret_val_fget_flags_3657 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3657, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3657; + setRet(call_fget_flags_3657, 0, ret_val_fget_flags_3657); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3642 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3642, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3642, 64, false) - , traits::vstart); + auto tmp3658 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3658, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3658, traits::vstart); } cc.bind(label_merge); } @@ -84536,28 +84014,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3643; - x86::Gp ret_val_get_sew_pow_3643 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3643, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3644 = get_reg(cc, 8, false); - mov(cc, tmp3644, 1); + InvokeNode* call_get_sew_pow_3659; + x86::Gp ret_val_get_sew_pow_3659 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3659, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3660 = get_reg(cc, 8, false); + mov(cc, tmp3660, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3644, (ret_val_get_sew_pow_3643))), 8, false), ~ 1); - setArg(call_get_sew_pow_3643, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3643, 0, ret_val_get_sew_pow_3643); + (gen_operation(cc, shl, tmp3660, (ret_val_get_sew_pow_3659))), 8, false), ~ 1); + setArg(call_get_sew_pow_3659, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3659, 0, ret_val_get_sew_pow_3659); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3645; - auto illegal_fp_vd_unmasked_3645_arg0 = SEW; - auto illegal_fp_vd_unmasked_3645_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3645 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3645, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3645; - setArg(call_illegal_fp_vd_unmasked_3645, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3645, 1, illegal_fp_vd_unmasked_3645_arg0); - setArg(call_illegal_fp_vd_unmasked_3645, 2, illegal_fp_vd_unmasked_3645_arg1); - setRet(call_illegal_fp_vd_unmasked_3645, 0, ret_val_illegal_fp_vd_unmasked_3645); + InvokeNode* call_illegal_fp_vd_unmasked_3661; + auto illegal_fp_vd_unmasked_3661_arg0 = SEW; + auto illegal_fp_vd_unmasked_3661_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3661 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3661, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3661; + setArg(call_illegal_fp_vd_unmasked_3661, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3661, 1, illegal_fp_vd_unmasked_3661_arg0); + setArg(call_illegal_fp_vd_unmasked_3661, 2, illegal_fp_vd_unmasked_3661_arg1); + setRet(call_illegal_fp_vd_unmasked_3661, 0, ret_val_illegal_fp_vd_unmasked_3661); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -84573,46 +84051,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3647; - x86::Gp ret_val_sew_3647 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3647, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3646; - auto mask_fp_vector_imm_op_3646_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3646_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3646_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3646_arg8 = gen_ext(cc, + InvokeNode* call_sew_3663; + x86::Gp ret_val_sew_3663 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3663, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3662; + auto mask_fp_vector_imm_op_3662_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3662_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3662_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3662_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto mask_fp_vector_imm_op_3646_arg9 = rm; - auto mask_fp_vector_imm_op_3646_arg10 = ret_val_sew_3647; + auto mask_fp_vector_imm_op_3662_arg9 = rm; + auto mask_fp_vector_imm_op_3662_arg10 = ret_val_sew_3663; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3646, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3647, 0, reinterpret_cast(this)); - setRet(call_sew_3647, 0, ret_val_sew_3647); - setArg(call_mask_fp_vector_imm_op_3646, 0, V); - setArg(call_mask_fp_vector_imm_op_3646, 1, 28); - setArg(call_mask_fp_vector_imm_op_3646, 2, mask_fp_vector_imm_op_3646_arg2); - setArg(call_mask_fp_vector_imm_op_3646, 3, mask_fp_vector_imm_op_3646_arg3); - setArg(call_mask_fp_vector_imm_op_3646, 4, mask_fp_vector_imm_op_3646_arg4); - setArg(call_mask_fp_vector_imm_op_3646, 5, vm); - setArg(call_mask_fp_vector_imm_op_3646, 6, vd); - setArg(call_mask_fp_vector_imm_op_3646, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3646, 8, mask_fp_vector_imm_op_3646_arg8); - setArg(call_mask_fp_vector_imm_op_3646, 9, mask_fp_vector_imm_op_3646_arg9); - setArg(call_mask_fp_vector_imm_op_3646, 10, mask_fp_vector_imm_op_3646_arg10); - InvokeNode* call_fget_flags_3648; - x86::Gp ret_val_fget_flags_3648 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3648, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3648; - setRet(call_fget_flags_3648, 0, ret_val_fget_flags_3648); + cc.invoke(&call_mask_fp_vector_imm_op_3662, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3663, 0, reinterpret_cast(this)); + setRet(call_sew_3663, 0, ret_val_sew_3663); + setArg(call_mask_fp_vector_imm_op_3662, 0, V); + setArg(call_mask_fp_vector_imm_op_3662, 1, 28); + setArg(call_mask_fp_vector_imm_op_3662, 2, mask_fp_vector_imm_op_3662_arg2); + setArg(call_mask_fp_vector_imm_op_3662, 3, mask_fp_vector_imm_op_3662_arg3); + setArg(call_mask_fp_vector_imm_op_3662, 4, mask_fp_vector_imm_op_3662_arg4); + setArg(call_mask_fp_vector_imm_op_3662, 5, vm); + setArg(call_mask_fp_vector_imm_op_3662, 6, vd); + setArg(call_mask_fp_vector_imm_op_3662, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3662, 8, mask_fp_vector_imm_op_3662_arg8); + setArg(call_mask_fp_vector_imm_op_3662, 9, mask_fp_vector_imm_op_3662_arg9); + setArg(call_mask_fp_vector_imm_op_3662, 10, mask_fp_vector_imm_op_3662_arg10); + InvokeNode* call_fget_flags_3664; + x86::Gp ret_val_fget_flags_3664 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3664, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3664; + setRet(call_fget_flags_3664, 0, ret_val_fget_flags_3664); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3649 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3649, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3649, 64, false) - , traits::vstart); + auto tmp3665 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3665, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3665, traits::vstart); } cc.bind(label_merge); } @@ -84656,28 +84132,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3650; - x86::Gp ret_val_get_sew_pow_3650 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3650, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3651 = get_reg(cc, 8, false); - mov(cc, tmp3651, 1); + InvokeNode* call_get_sew_pow_3666; + x86::Gp ret_val_get_sew_pow_3666 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3666, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3667 = get_reg(cc, 8, false); + mov(cc, tmp3667, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3651, (ret_val_get_sew_pow_3650))), 8, false), ~ 1); - setArg(call_get_sew_pow_3650, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3650, 0, ret_val_get_sew_pow_3650); + (gen_operation(cc, shl, tmp3667, (ret_val_get_sew_pow_3666))), 8, false), ~ 1); + setArg(call_get_sew_pow_3666, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3666, 0, ret_val_get_sew_pow_3666); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3652; - auto illegal_fp_vd_unmasked_3652_arg0 = SEW; - auto illegal_fp_vd_unmasked_3652_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3652 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3652, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3652; - setArg(call_illegal_fp_vd_unmasked_3652, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3652, 1, illegal_fp_vd_unmasked_3652_arg0); - setArg(call_illegal_fp_vd_unmasked_3652, 2, illegal_fp_vd_unmasked_3652_arg1); - setRet(call_illegal_fp_vd_unmasked_3652, 0, ret_val_illegal_fp_vd_unmasked_3652); + InvokeNode* call_illegal_fp_vd_unmasked_3668; + auto illegal_fp_vd_unmasked_3668_arg0 = SEW; + auto illegal_fp_vd_unmasked_3668_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3668 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3668, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3668; + setArg(call_illegal_fp_vd_unmasked_3668, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3668, 1, illegal_fp_vd_unmasked_3668_arg0); + setArg(call_illegal_fp_vd_unmasked_3668, 2, illegal_fp_vd_unmasked_3668_arg1); + setRet(call_illegal_fp_vd_unmasked_3668, 0, ret_val_illegal_fp_vd_unmasked_3668); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -84693,44 +84169,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3654; - x86::Gp ret_val_sew_3654 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3654, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_vector_op_3653; - auto mask_fp_vector_vector_op_3653_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_vector_op_3653_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_vector_op_3653_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_vector_op_3653_arg9 = rm; - auto mask_fp_vector_vector_op_3653_arg10 = ret_val_sew_3654; + InvokeNode* call_sew_3670; + x86::Gp ret_val_sew_3670 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3670, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3669; + auto mask_fp_vector_vector_op_3669_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3669_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3669_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3669_arg9 = rm; + auto mask_fp_vector_vector_op_3669_arg10 = ret_val_sew_3670; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_vector_op_3653, &mask_fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3654, 0, reinterpret_cast(this)); - setRet(call_sew_3654, 0, ret_val_sew_3654); - setArg(call_mask_fp_vector_vector_op_3653, 0, V); - setArg(call_mask_fp_vector_vector_op_3653, 1, 28); - setArg(call_mask_fp_vector_vector_op_3653, 2, mask_fp_vector_vector_op_3653_arg2); - setArg(call_mask_fp_vector_vector_op_3653, 3, mask_fp_vector_vector_op_3653_arg3); - setArg(call_mask_fp_vector_vector_op_3653, 4, mask_fp_vector_vector_op_3653_arg4); - setArg(call_mask_fp_vector_vector_op_3653, 5, vm); - setArg(call_mask_fp_vector_vector_op_3653, 6, vd); - setArg(call_mask_fp_vector_vector_op_3653, 7, vs2); - setArg(call_mask_fp_vector_vector_op_3653, 8, vs1); - setArg(call_mask_fp_vector_vector_op_3653, 9, mask_fp_vector_vector_op_3653_arg9); - setArg(call_mask_fp_vector_vector_op_3653, 10, mask_fp_vector_vector_op_3653_arg10); - InvokeNode* call_fget_flags_3655; - x86::Gp ret_val_fget_flags_3655 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3655, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3655; - setRet(call_fget_flags_3655, 0, ret_val_fget_flags_3655); + cc.invoke(&call_mask_fp_vector_vector_op_3669, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3670, 0, reinterpret_cast(this)); + setRet(call_sew_3670, 0, ret_val_sew_3670); + setArg(call_mask_fp_vector_vector_op_3669, 0, V); + setArg(call_mask_fp_vector_vector_op_3669, 1, 28); + setArg(call_mask_fp_vector_vector_op_3669, 2, mask_fp_vector_vector_op_3669_arg2); + setArg(call_mask_fp_vector_vector_op_3669, 3, mask_fp_vector_vector_op_3669_arg3); + setArg(call_mask_fp_vector_vector_op_3669, 4, mask_fp_vector_vector_op_3669_arg4); + setArg(call_mask_fp_vector_vector_op_3669, 5, vm); + setArg(call_mask_fp_vector_vector_op_3669, 6, vd); + setArg(call_mask_fp_vector_vector_op_3669, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3669, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3669, 9, mask_fp_vector_vector_op_3669_arg9); + setArg(call_mask_fp_vector_vector_op_3669, 10, mask_fp_vector_vector_op_3669_arg10); + InvokeNode* call_fget_flags_3671; + x86::Gp ret_val_fget_flags_3671 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3671, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3671; + setRet(call_fget_flags_3671, 0, ret_val_fget_flags_3671); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3656 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3656, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3656, 64, false) - , traits::vstart); + auto tmp3672 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3672, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3672, traits::vstart); } cc.bind(label_merge); } @@ -84774,28 +84248,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3657; - x86::Gp ret_val_get_sew_pow_3657 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3657, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3658 = get_reg(cc, 8, false); - mov(cc, tmp3658, 1); + InvokeNode* call_get_sew_pow_3673; + x86::Gp ret_val_get_sew_pow_3673 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3673, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3674 = get_reg(cc, 8, false); + mov(cc, tmp3674, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3658, (ret_val_get_sew_pow_3657))), 8, false), ~ 1); - setArg(call_get_sew_pow_3657, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3657, 0, ret_val_get_sew_pow_3657); + (gen_operation(cc, shl, tmp3674, (ret_val_get_sew_pow_3673))), 8, false), ~ 1); + setArg(call_get_sew_pow_3673, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3673, 0, ret_val_get_sew_pow_3673); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3659; - auto illegal_fp_vd_unmasked_3659_arg0 = SEW; - auto illegal_fp_vd_unmasked_3659_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3659 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3659, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3659; - setArg(call_illegal_fp_vd_unmasked_3659, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3659, 1, illegal_fp_vd_unmasked_3659_arg0); - setArg(call_illegal_fp_vd_unmasked_3659, 2, illegal_fp_vd_unmasked_3659_arg1); - setRet(call_illegal_fp_vd_unmasked_3659, 0, ret_val_illegal_fp_vd_unmasked_3659); + InvokeNode* call_illegal_fp_vd_unmasked_3675; + auto illegal_fp_vd_unmasked_3675_arg0 = SEW; + auto illegal_fp_vd_unmasked_3675_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3675 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3675, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3675; + setArg(call_illegal_fp_vd_unmasked_3675, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3675, 1, illegal_fp_vd_unmasked_3675_arg0); + setArg(call_illegal_fp_vd_unmasked_3675, 2, illegal_fp_vd_unmasked_3675_arg1); + setRet(call_illegal_fp_vd_unmasked_3675, 0, ret_val_illegal_fp_vd_unmasked_3675); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -84811,46 +84285,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3661; - x86::Gp ret_val_sew_3661 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3661, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3660; - auto mask_fp_vector_imm_op_3660_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3660_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3660_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3660_arg8 = gen_ext(cc, + InvokeNode* call_sew_3677; + x86::Gp ret_val_sew_3677 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3677, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3676; + auto mask_fp_vector_imm_op_3676_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3676_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3676_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3676_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto mask_fp_vector_imm_op_3660_arg9 = rm; - auto mask_fp_vector_imm_op_3660_arg10 = ret_val_sew_3661; + auto mask_fp_vector_imm_op_3676_arg9 = rm; + auto mask_fp_vector_imm_op_3676_arg10 = ret_val_sew_3677; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3660, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3661, 0, reinterpret_cast(this)); - setRet(call_sew_3661, 0, ret_val_sew_3661); - setArg(call_mask_fp_vector_imm_op_3660, 0, V); - setArg(call_mask_fp_vector_imm_op_3660, 1, 27); - setArg(call_mask_fp_vector_imm_op_3660, 2, mask_fp_vector_imm_op_3660_arg2); - setArg(call_mask_fp_vector_imm_op_3660, 3, mask_fp_vector_imm_op_3660_arg3); - setArg(call_mask_fp_vector_imm_op_3660, 4, mask_fp_vector_imm_op_3660_arg4); - setArg(call_mask_fp_vector_imm_op_3660, 5, vm); - setArg(call_mask_fp_vector_imm_op_3660, 6, vd); - setArg(call_mask_fp_vector_imm_op_3660, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3660, 8, mask_fp_vector_imm_op_3660_arg8); - setArg(call_mask_fp_vector_imm_op_3660, 9, mask_fp_vector_imm_op_3660_arg9); - setArg(call_mask_fp_vector_imm_op_3660, 10, mask_fp_vector_imm_op_3660_arg10); - InvokeNode* call_fget_flags_3662; - x86::Gp ret_val_fget_flags_3662 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3662, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3662; - setRet(call_fget_flags_3662, 0, ret_val_fget_flags_3662); + cc.invoke(&call_mask_fp_vector_imm_op_3676, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3677, 0, reinterpret_cast(this)); + setRet(call_sew_3677, 0, ret_val_sew_3677); + setArg(call_mask_fp_vector_imm_op_3676, 0, V); + setArg(call_mask_fp_vector_imm_op_3676, 1, 27); + setArg(call_mask_fp_vector_imm_op_3676, 2, mask_fp_vector_imm_op_3676_arg2); + setArg(call_mask_fp_vector_imm_op_3676, 3, mask_fp_vector_imm_op_3676_arg3); + setArg(call_mask_fp_vector_imm_op_3676, 4, mask_fp_vector_imm_op_3676_arg4); + setArg(call_mask_fp_vector_imm_op_3676, 5, vm); + setArg(call_mask_fp_vector_imm_op_3676, 6, vd); + setArg(call_mask_fp_vector_imm_op_3676, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3676, 8, mask_fp_vector_imm_op_3676_arg8); + setArg(call_mask_fp_vector_imm_op_3676, 9, mask_fp_vector_imm_op_3676_arg9); + setArg(call_mask_fp_vector_imm_op_3676, 10, mask_fp_vector_imm_op_3676_arg10); + InvokeNode* call_fget_flags_3678; + x86::Gp ret_val_fget_flags_3678 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3678, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3678; + setRet(call_fget_flags_3678, 0, ret_val_fget_flags_3678); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3663 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3663, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3663, 64, false) - , traits::vstart); + auto tmp3679 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3679, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3679, traits::vstart); } cc.bind(label_merge); } @@ -84894,28 +84366,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3664; - x86::Gp ret_val_get_sew_pow_3664 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3664, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3665 = get_reg(cc, 8, false); - mov(cc, tmp3665, 1); + InvokeNode* call_get_sew_pow_3680; + x86::Gp ret_val_get_sew_pow_3680 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3680, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3681 = get_reg(cc, 8, false); + mov(cc, tmp3681, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3665, (ret_val_get_sew_pow_3664))), 8, false), ~ 1); - setArg(call_get_sew_pow_3664, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3664, 0, ret_val_get_sew_pow_3664); + (gen_operation(cc, shl, tmp3681, (ret_val_get_sew_pow_3680))), 8, false), ~ 1); + setArg(call_get_sew_pow_3680, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3680, 0, ret_val_get_sew_pow_3680); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3666; - auto illegal_fp_vd_unmasked_3666_arg0 = SEW; - auto illegal_fp_vd_unmasked_3666_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3666 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3666, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3666; - setArg(call_illegal_fp_vd_unmasked_3666, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3666, 1, illegal_fp_vd_unmasked_3666_arg0); - setArg(call_illegal_fp_vd_unmasked_3666, 2, illegal_fp_vd_unmasked_3666_arg1); - setRet(call_illegal_fp_vd_unmasked_3666, 0, ret_val_illegal_fp_vd_unmasked_3666); + InvokeNode* call_illegal_fp_vd_unmasked_3682; + auto illegal_fp_vd_unmasked_3682_arg0 = SEW; + auto illegal_fp_vd_unmasked_3682_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3682 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3682, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3682; + setArg(call_illegal_fp_vd_unmasked_3682, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3682, 1, illegal_fp_vd_unmasked_3682_arg0); + setArg(call_illegal_fp_vd_unmasked_3682, 2, illegal_fp_vd_unmasked_3682_arg1); + setRet(call_illegal_fp_vd_unmasked_3682, 0, ret_val_illegal_fp_vd_unmasked_3682); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -84931,44 +84403,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3668; - x86::Gp ret_val_sew_3668 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3668, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_vector_op_3667; - auto mask_fp_vector_vector_op_3667_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_vector_op_3667_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_vector_op_3667_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_vector_op_3667_arg9 = rm; - auto mask_fp_vector_vector_op_3667_arg10 = ret_val_sew_3668; + InvokeNode* call_sew_3684; + x86::Gp ret_val_sew_3684 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3684, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3683; + auto mask_fp_vector_vector_op_3683_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3683_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3683_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3683_arg9 = rm; + auto mask_fp_vector_vector_op_3683_arg10 = ret_val_sew_3684; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_vector_op_3667, &mask_fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3668, 0, reinterpret_cast(this)); - setRet(call_sew_3668, 0, ret_val_sew_3668); - setArg(call_mask_fp_vector_vector_op_3667, 0, V); - setArg(call_mask_fp_vector_vector_op_3667, 1, 27); - setArg(call_mask_fp_vector_vector_op_3667, 2, mask_fp_vector_vector_op_3667_arg2); - setArg(call_mask_fp_vector_vector_op_3667, 3, mask_fp_vector_vector_op_3667_arg3); - setArg(call_mask_fp_vector_vector_op_3667, 4, mask_fp_vector_vector_op_3667_arg4); - setArg(call_mask_fp_vector_vector_op_3667, 5, vm); - setArg(call_mask_fp_vector_vector_op_3667, 6, vd); - setArg(call_mask_fp_vector_vector_op_3667, 7, vs2); - setArg(call_mask_fp_vector_vector_op_3667, 8, vs1); - setArg(call_mask_fp_vector_vector_op_3667, 9, mask_fp_vector_vector_op_3667_arg9); - setArg(call_mask_fp_vector_vector_op_3667, 10, mask_fp_vector_vector_op_3667_arg10); - InvokeNode* call_fget_flags_3669; - x86::Gp ret_val_fget_flags_3669 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3669, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3669; - setRet(call_fget_flags_3669, 0, ret_val_fget_flags_3669); + cc.invoke(&call_mask_fp_vector_vector_op_3683, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3684, 0, reinterpret_cast(this)); + setRet(call_sew_3684, 0, ret_val_sew_3684); + setArg(call_mask_fp_vector_vector_op_3683, 0, V); + setArg(call_mask_fp_vector_vector_op_3683, 1, 27); + setArg(call_mask_fp_vector_vector_op_3683, 2, mask_fp_vector_vector_op_3683_arg2); + setArg(call_mask_fp_vector_vector_op_3683, 3, mask_fp_vector_vector_op_3683_arg3); + setArg(call_mask_fp_vector_vector_op_3683, 4, mask_fp_vector_vector_op_3683_arg4); + setArg(call_mask_fp_vector_vector_op_3683, 5, vm); + setArg(call_mask_fp_vector_vector_op_3683, 6, vd); + setArg(call_mask_fp_vector_vector_op_3683, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3683, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3683, 9, mask_fp_vector_vector_op_3683_arg9); + setArg(call_mask_fp_vector_vector_op_3683, 10, mask_fp_vector_vector_op_3683_arg10); + InvokeNode* call_fget_flags_3685; + x86::Gp ret_val_fget_flags_3685 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3685, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3685; + setRet(call_fget_flags_3685, 0, ret_val_fget_flags_3685); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3670 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3670, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3670, 64, false) - , traits::vstart); + auto tmp3686 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3686, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3686, traits::vstart); } cc.bind(label_merge); } @@ -85012,28 +84482,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3671; - x86::Gp ret_val_get_sew_pow_3671 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3671, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3672 = get_reg(cc, 8, false); - mov(cc, tmp3672, 1); + InvokeNode* call_get_sew_pow_3687; + x86::Gp ret_val_get_sew_pow_3687 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3687, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3688 = get_reg(cc, 8, false); + mov(cc, tmp3688, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3672, (ret_val_get_sew_pow_3671))), 8, false), ~ 1); - setArg(call_get_sew_pow_3671, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3671, 0, ret_val_get_sew_pow_3671); + (gen_operation(cc, shl, tmp3688, (ret_val_get_sew_pow_3687))), 8, false), ~ 1); + setArg(call_get_sew_pow_3687, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3687, 0, ret_val_get_sew_pow_3687); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3673; - auto illegal_fp_vd_unmasked_3673_arg0 = SEW; - auto illegal_fp_vd_unmasked_3673_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3673 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3673, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3673; - setArg(call_illegal_fp_vd_unmasked_3673, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3673, 1, illegal_fp_vd_unmasked_3673_arg0); - setArg(call_illegal_fp_vd_unmasked_3673, 2, illegal_fp_vd_unmasked_3673_arg1); - setRet(call_illegal_fp_vd_unmasked_3673, 0, ret_val_illegal_fp_vd_unmasked_3673); + InvokeNode* call_illegal_fp_vd_unmasked_3689; + auto illegal_fp_vd_unmasked_3689_arg0 = SEW; + auto illegal_fp_vd_unmasked_3689_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3689 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3689, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3689; + setArg(call_illegal_fp_vd_unmasked_3689, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3689, 1, illegal_fp_vd_unmasked_3689_arg0); + setArg(call_illegal_fp_vd_unmasked_3689, 2, illegal_fp_vd_unmasked_3689_arg1); + setRet(call_illegal_fp_vd_unmasked_3689, 0, ret_val_illegal_fp_vd_unmasked_3689); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -85049,46 +84519,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3675; - x86::Gp ret_val_sew_3675 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3675, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3674; - auto mask_fp_vector_imm_op_3674_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3674_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3674_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3674_arg8 = gen_ext(cc, + InvokeNode* call_sew_3691; + x86::Gp ret_val_sew_3691 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3691, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3690; + auto mask_fp_vector_imm_op_3690_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3690_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3690_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3690_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto mask_fp_vector_imm_op_3674_arg9 = rm; - auto mask_fp_vector_imm_op_3674_arg10 = ret_val_sew_3675; + auto mask_fp_vector_imm_op_3690_arg9 = rm; + auto mask_fp_vector_imm_op_3690_arg10 = ret_val_sew_3691; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3674, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3675, 0, reinterpret_cast(this)); - setRet(call_sew_3675, 0, ret_val_sew_3675); - setArg(call_mask_fp_vector_imm_op_3674, 0, V); - setArg(call_mask_fp_vector_imm_op_3674, 1, 25); - setArg(call_mask_fp_vector_imm_op_3674, 2, mask_fp_vector_imm_op_3674_arg2); - setArg(call_mask_fp_vector_imm_op_3674, 3, mask_fp_vector_imm_op_3674_arg3); - setArg(call_mask_fp_vector_imm_op_3674, 4, mask_fp_vector_imm_op_3674_arg4); - setArg(call_mask_fp_vector_imm_op_3674, 5, vm); - setArg(call_mask_fp_vector_imm_op_3674, 6, vd); - setArg(call_mask_fp_vector_imm_op_3674, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3674, 8, mask_fp_vector_imm_op_3674_arg8); - setArg(call_mask_fp_vector_imm_op_3674, 9, mask_fp_vector_imm_op_3674_arg9); - setArg(call_mask_fp_vector_imm_op_3674, 10, mask_fp_vector_imm_op_3674_arg10); - InvokeNode* call_fget_flags_3676; - x86::Gp ret_val_fget_flags_3676 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3676, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3676; - setRet(call_fget_flags_3676, 0, ret_val_fget_flags_3676); + cc.invoke(&call_mask_fp_vector_imm_op_3690, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3691, 0, reinterpret_cast(this)); + setRet(call_sew_3691, 0, ret_val_sew_3691); + setArg(call_mask_fp_vector_imm_op_3690, 0, V); + setArg(call_mask_fp_vector_imm_op_3690, 1, 25); + setArg(call_mask_fp_vector_imm_op_3690, 2, mask_fp_vector_imm_op_3690_arg2); + setArg(call_mask_fp_vector_imm_op_3690, 3, mask_fp_vector_imm_op_3690_arg3); + setArg(call_mask_fp_vector_imm_op_3690, 4, mask_fp_vector_imm_op_3690_arg4); + setArg(call_mask_fp_vector_imm_op_3690, 5, vm); + setArg(call_mask_fp_vector_imm_op_3690, 6, vd); + setArg(call_mask_fp_vector_imm_op_3690, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3690, 8, mask_fp_vector_imm_op_3690_arg8); + setArg(call_mask_fp_vector_imm_op_3690, 9, mask_fp_vector_imm_op_3690_arg9); + setArg(call_mask_fp_vector_imm_op_3690, 10, mask_fp_vector_imm_op_3690_arg10); + InvokeNode* call_fget_flags_3692; + x86::Gp ret_val_fget_flags_3692 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3692, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3692; + setRet(call_fget_flags_3692, 0, ret_val_fget_flags_3692); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3677 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3677, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3677, 64, false) - , traits::vstart); + auto tmp3693 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3693, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3693, traits::vstart); } cc.bind(label_merge); } @@ -85132,28 +84600,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3678; - x86::Gp ret_val_get_sew_pow_3678 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3678, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3679 = get_reg(cc, 8, false); - mov(cc, tmp3679, 1); + InvokeNode* call_get_sew_pow_3694; + x86::Gp ret_val_get_sew_pow_3694 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3694, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3695 = get_reg(cc, 8, false); + mov(cc, tmp3695, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3679, (ret_val_get_sew_pow_3678))), 8, false), ~ 1); - setArg(call_get_sew_pow_3678, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3678, 0, ret_val_get_sew_pow_3678); + (gen_operation(cc, shl, tmp3695, (ret_val_get_sew_pow_3694))), 8, false), ~ 1); + setArg(call_get_sew_pow_3694, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3694, 0, ret_val_get_sew_pow_3694); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3680; - auto illegal_fp_vd_unmasked_3680_arg0 = SEW; - auto illegal_fp_vd_unmasked_3680_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3680 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3680, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3680; - setArg(call_illegal_fp_vd_unmasked_3680, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3680, 1, illegal_fp_vd_unmasked_3680_arg0); - setArg(call_illegal_fp_vd_unmasked_3680, 2, illegal_fp_vd_unmasked_3680_arg1); - setRet(call_illegal_fp_vd_unmasked_3680, 0, ret_val_illegal_fp_vd_unmasked_3680); + InvokeNode* call_illegal_fp_vd_unmasked_3696; + auto illegal_fp_vd_unmasked_3696_arg0 = SEW; + auto illegal_fp_vd_unmasked_3696_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3696 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3696, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3696; + setArg(call_illegal_fp_vd_unmasked_3696, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3696, 1, illegal_fp_vd_unmasked_3696_arg0); + setArg(call_illegal_fp_vd_unmasked_3696, 2, illegal_fp_vd_unmasked_3696_arg1); + setRet(call_illegal_fp_vd_unmasked_3696, 0, ret_val_illegal_fp_vd_unmasked_3696); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -85169,44 +84637,42 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3682; - x86::Gp ret_val_sew_3682 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3682, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_vector_op_3681; - auto mask_fp_vector_vector_op_3681_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_vector_op_3681_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_vector_op_3681_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_vector_op_3681_arg9 = rm; - auto mask_fp_vector_vector_op_3681_arg10 = ret_val_sew_3682; + InvokeNode* call_sew_3698; + x86::Gp ret_val_sew_3698 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3698, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_vector_op_3697; + auto mask_fp_vector_vector_op_3697_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_vector_op_3697_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_vector_op_3697_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_vector_op_3697_arg9 = rm; + auto mask_fp_vector_vector_op_3697_arg10 = ret_val_sew_3698; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_vector_op_3681, &mask_fp_vector_vector_op, FuncSignature::build()); - setArg(call_sew_3682, 0, reinterpret_cast(this)); - setRet(call_sew_3682, 0, ret_val_sew_3682); - setArg(call_mask_fp_vector_vector_op_3681, 0, V); - setArg(call_mask_fp_vector_vector_op_3681, 1, 25); - setArg(call_mask_fp_vector_vector_op_3681, 2, mask_fp_vector_vector_op_3681_arg2); - setArg(call_mask_fp_vector_vector_op_3681, 3, mask_fp_vector_vector_op_3681_arg3); - setArg(call_mask_fp_vector_vector_op_3681, 4, mask_fp_vector_vector_op_3681_arg4); - setArg(call_mask_fp_vector_vector_op_3681, 5, vm); - setArg(call_mask_fp_vector_vector_op_3681, 6, vd); - setArg(call_mask_fp_vector_vector_op_3681, 7, vs2); - setArg(call_mask_fp_vector_vector_op_3681, 8, vs1); - setArg(call_mask_fp_vector_vector_op_3681, 9, mask_fp_vector_vector_op_3681_arg9); - setArg(call_mask_fp_vector_vector_op_3681, 10, mask_fp_vector_vector_op_3681_arg10); - InvokeNode* call_fget_flags_3683; - x86::Gp ret_val_fget_flags_3683 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3683, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3683; - setRet(call_fget_flags_3683, 0, ret_val_fget_flags_3683); + cc.invoke(&call_mask_fp_vector_vector_op_3697, &mask_fp_vector_vector_op, FuncSignature::build()); + setArg(call_sew_3698, 0, reinterpret_cast(this)); + setRet(call_sew_3698, 0, ret_val_sew_3698); + setArg(call_mask_fp_vector_vector_op_3697, 0, V); + setArg(call_mask_fp_vector_vector_op_3697, 1, 25); + setArg(call_mask_fp_vector_vector_op_3697, 2, mask_fp_vector_vector_op_3697_arg2); + setArg(call_mask_fp_vector_vector_op_3697, 3, mask_fp_vector_vector_op_3697_arg3); + setArg(call_mask_fp_vector_vector_op_3697, 4, mask_fp_vector_vector_op_3697_arg4); + setArg(call_mask_fp_vector_vector_op_3697, 5, vm); + setArg(call_mask_fp_vector_vector_op_3697, 6, vd); + setArg(call_mask_fp_vector_vector_op_3697, 7, vs2); + setArg(call_mask_fp_vector_vector_op_3697, 8, vs1); + setArg(call_mask_fp_vector_vector_op_3697, 9, mask_fp_vector_vector_op_3697_arg9); + setArg(call_mask_fp_vector_vector_op_3697, 10, mask_fp_vector_vector_op_3697_arg10); + InvokeNode* call_fget_flags_3699; + x86::Gp ret_val_fget_flags_3699 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3699, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3699; + setRet(call_fget_flags_3699, 0, ret_val_fget_flags_3699); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3684 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3684, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3684, 64, false) - , traits::vstart); + auto tmp3700 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3700, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3700, traits::vstart); } cc.bind(label_merge); } @@ -85250,28 +84716,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3685; - x86::Gp ret_val_get_sew_pow_3685 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3685, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3686 = get_reg(cc, 8, false); - mov(cc, tmp3686, 1); + InvokeNode* call_get_sew_pow_3701; + x86::Gp ret_val_get_sew_pow_3701 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3701, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3702 = get_reg(cc, 8, false); + mov(cc, tmp3702, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3686, (ret_val_get_sew_pow_3685))), 8, false), ~ 1); - setArg(call_get_sew_pow_3685, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3685, 0, ret_val_get_sew_pow_3685); + (gen_operation(cc, shl, tmp3702, (ret_val_get_sew_pow_3701))), 8, false), ~ 1); + setArg(call_get_sew_pow_3701, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3701, 0, ret_val_get_sew_pow_3701); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3687; - auto illegal_fp_vd_unmasked_3687_arg0 = SEW; - auto illegal_fp_vd_unmasked_3687_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3687 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3687, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3687; - setArg(call_illegal_fp_vd_unmasked_3687, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3687, 1, illegal_fp_vd_unmasked_3687_arg0); - setArg(call_illegal_fp_vd_unmasked_3687, 2, illegal_fp_vd_unmasked_3687_arg1); - setRet(call_illegal_fp_vd_unmasked_3687, 0, ret_val_illegal_fp_vd_unmasked_3687); + InvokeNode* call_illegal_fp_vd_unmasked_3703; + auto illegal_fp_vd_unmasked_3703_arg0 = SEW; + auto illegal_fp_vd_unmasked_3703_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3703 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3703, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3703; + setArg(call_illegal_fp_vd_unmasked_3703, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3703, 1, illegal_fp_vd_unmasked_3703_arg0); + setArg(call_illegal_fp_vd_unmasked_3703, 2, illegal_fp_vd_unmasked_3703_arg1); + setRet(call_illegal_fp_vd_unmasked_3703, 0, ret_val_illegal_fp_vd_unmasked_3703); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -85287,46 +84753,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3689; - x86::Gp ret_val_sew_3689 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3689, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3688; - auto mask_fp_vector_imm_op_3688_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3688_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3688_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3688_arg8 = gen_ext(cc, + InvokeNode* call_sew_3705; + x86::Gp ret_val_sew_3705 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3705, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3704; + auto mask_fp_vector_imm_op_3704_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3704_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3704_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3704_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto mask_fp_vector_imm_op_3688_arg9 = rm; - auto mask_fp_vector_imm_op_3688_arg10 = ret_val_sew_3689; + auto mask_fp_vector_imm_op_3704_arg9 = rm; + auto mask_fp_vector_imm_op_3704_arg10 = ret_val_sew_3705; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3688, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3689, 0, reinterpret_cast(this)); - setRet(call_sew_3689, 0, ret_val_sew_3689); - setArg(call_mask_fp_vector_imm_op_3688, 0, V); - setArg(call_mask_fp_vector_imm_op_3688, 1, 29); - setArg(call_mask_fp_vector_imm_op_3688, 2, mask_fp_vector_imm_op_3688_arg2); - setArg(call_mask_fp_vector_imm_op_3688, 3, mask_fp_vector_imm_op_3688_arg3); - setArg(call_mask_fp_vector_imm_op_3688, 4, mask_fp_vector_imm_op_3688_arg4); - setArg(call_mask_fp_vector_imm_op_3688, 5, vm); - setArg(call_mask_fp_vector_imm_op_3688, 6, vd); - setArg(call_mask_fp_vector_imm_op_3688, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3688, 8, mask_fp_vector_imm_op_3688_arg8); - setArg(call_mask_fp_vector_imm_op_3688, 9, mask_fp_vector_imm_op_3688_arg9); - setArg(call_mask_fp_vector_imm_op_3688, 10, mask_fp_vector_imm_op_3688_arg10); - InvokeNode* call_fget_flags_3690; - x86::Gp ret_val_fget_flags_3690 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3690, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3690; - setRet(call_fget_flags_3690, 0, ret_val_fget_flags_3690); + cc.invoke(&call_mask_fp_vector_imm_op_3704, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3705, 0, reinterpret_cast(this)); + setRet(call_sew_3705, 0, ret_val_sew_3705); + setArg(call_mask_fp_vector_imm_op_3704, 0, V); + setArg(call_mask_fp_vector_imm_op_3704, 1, 29); + setArg(call_mask_fp_vector_imm_op_3704, 2, mask_fp_vector_imm_op_3704_arg2); + setArg(call_mask_fp_vector_imm_op_3704, 3, mask_fp_vector_imm_op_3704_arg3); + setArg(call_mask_fp_vector_imm_op_3704, 4, mask_fp_vector_imm_op_3704_arg4); + setArg(call_mask_fp_vector_imm_op_3704, 5, vm); + setArg(call_mask_fp_vector_imm_op_3704, 6, vd); + setArg(call_mask_fp_vector_imm_op_3704, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3704, 8, mask_fp_vector_imm_op_3704_arg8); + setArg(call_mask_fp_vector_imm_op_3704, 9, mask_fp_vector_imm_op_3704_arg9); + setArg(call_mask_fp_vector_imm_op_3704, 10, mask_fp_vector_imm_op_3704_arg10); + InvokeNode* call_fget_flags_3706; + x86::Gp ret_val_fget_flags_3706 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3706, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3706; + setRet(call_fget_flags_3706, 0, ret_val_fget_flags_3706); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3691 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3691, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3691, 64, false) - , traits::vstart); + auto tmp3707 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3707, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3707, traits::vstart); } cc.bind(label_merge); } @@ -85370,28 +84834,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3692; - x86::Gp ret_val_get_sew_pow_3692 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3692, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3693 = get_reg(cc, 8, false); - mov(cc, tmp3693, 1); + InvokeNode* call_get_sew_pow_3708; + x86::Gp ret_val_get_sew_pow_3708 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3708, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3709 = get_reg(cc, 8, false); + mov(cc, tmp3709, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3693, (ret_val_get_sew_pow_3692))), 8, false), ~ 1); - setArg(call_get_sew_pow_3692, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3692, 0, ret_val_get_sew_pow_3692); + (gen_operation(cc, shl, tmp3709, (ret_val_get_sew_pow_3708))), 8, false), ~ 1); + setArg(call_get_sew_pow_3708, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3708, 0, ret_val_get_sew_pow_3708); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3694; - auto illegal_fp_vd_unmasked_3694_arg0 = SEW; - auto illegal_fp_vd_unmasked_3694_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3694 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3694, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3694; - setArg(call_illegal_fp_vd_unmasked_3694, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3694, 1, illegal_fp_vd_unmasked_3694_arg0); - setArg(call_illegal_fp_vd_unmasked_3694, 2, illegal_fp_vd_unmasked_3694_arg1); - setRet(call_illegal_fp_vd_unmasked_3694, 0, ret_val_illegal_fp_vd_unmasked_3694); + InvokeNode* call_illegal_fp_vd_unmasked_3710; + auto illegal_fp_vd_unmasked_3710_arg0 = SEW; + auto illegal_fp_vd_unmasked_3710_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3710 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3710, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3710; + setArg(call_illegal_fp_vd_unmasked_3710, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3710, 1, illegal_fp_vd_unmasked_3710_arg0); + setArg(call_illegal_fp_vd_unmasked_3710, 2, illegal_fp_vd_unmasked_3710_arg1); + setRet(call_illegal_fp_vd_unmasked_3710, 0, ret_val_illegal_fp_vd_unmasked_3710); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -85407,46 +84871,44 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3696; - x86::Gp ret_val_sew_3696 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3696, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_mask_fp_vector_imm_op_3695; - auto mask_fp_vector_imm_op_3695_arg2 = load_reg_from_mem(jh, traits::vl); - auto mask_fp_vector_imm_op_3695_arg3 = load_reg_from_mem(jh, traits::vstart); - auto mask_fp_vector_imm_op_3695_arg4 = load_reg_from_mem(jh, traits::vtype); - auto mask_fp_vector_imm_op_3695_arg8 = gen_ext(cc, + InvokeNode* call_sew_3712; + x86::Gp ret_val_sew_3712 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3712, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_mask_fp_vector_imm_op_3711; + auto mask_fp_vector_imm_op_3711_arg2 = load_reg_from_mem(jh, traits::vl); + auto mask_fp_vector_imm_op_3711_arg3 = load_reg_from_mem(jh, traits::vstart); + auto mask_fp_vector_imm_op_3711_arg4 = load_reg_from_mem(jh, traits::vtype); + auto mask_fp_vector_imm_op_3711_arg8 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto mask_fp_vector_imm_op_3695_arg9 = rm; - auto mask_fp_vector_imm_op_3695_arg10 = ret_val_sew_3696; + auto mask_fp_vector_imm_op_3711_arg9 = rm; + auto mask_fp_vector_imm_op_3711_arg10 = ret_val_sew_3712; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_mask_fp_vector_imm_op_3695, &mask_fp_vector_imm_op, FuncSignature::build()); - setArg(call_sew_3696, 0, reinterpret_cast(this)); - setRet(call_sew_3696, 0, ret_val_sew_3696); - setArg(call_mask_fp_vector_imm_op_3695, 0, V); - setArg(call_mask_fp_vector_imm_op_3695, 1, 31); - setArg(call_mask_fp_vector_imm_op_3695, 2, mask_fp_vector_imm_op_3695_arg2); - setArg(call_mask_fp_vector_imm_op_3695, 3, mask_fp_vector_imm_op_3695_arg3); - setArg(call_mask_fp_vector_imm_op_3695, 4, mask_fp_vector_imm_op_3695_arg4); - setArg(call_mask_fp_vector_imm_op_3695, 5, vm); - setArg(call_mask_fp_vector_imm_op_3695, 6, vd); - setArg(call_mask_fp_vector_imm_op_3695, 7, vs2); - setArg(call_mask_fp_vector_imm_op_3695, 8, mask_fp_vector_imm_op_3695_arg8); - setArg(call_mask_fp_vector_imm_op_3695, 9, mask_fp_vector_imm_op_3695_arg9); - setArg(call_mask_fp_vector_imm_op_3695, 10, mask_fp_vector_imm_op_3695_arg10); - InvokeNode* call_fget_flags_3697; - x86::Gp ret_val_fget_flags_3697 = get_reg_Gp(cc, 32, false); - cc.invoke(&call_fget_flags_3697, &fget_flags, FuncSignature::build()); - auto flags = ret_val_fget_flags_3697; - setRet(call_fget_flags_3697, 0, ret_val_fget_flags_3697); + cc.invoke(&call_mask_fp_vector_imm_op_3711, &mask_fp_vector_imm_op, FuncSignature::build()); + setArg(call_sew_3712, 0, reinterpret_cast(this)); + setRet(call_sew_3712, 0, ret_val_sew_3712); + setArg(call_mask_fp_vector_imm_op_3711, 0, V); + setArg(call_mask_fp_vector_imm_op_3711, 1, 31); + setArg(call_mask_fp_vector_imm_op_3711, 2, mask_fp_vector_imm_op_3711_arg2); + setArg(call_mask_fp_vector_imm_op_3711, 3, mask_fp_vector_imm_op_3711_arg3); + setArg(call_mask_fp_vector_imm_op_3711, 4, mask_fp_vector_imm_op_3711_arg4); + setArg(call_mask_fp_vector_imm_op_3711, 5, vm); + setArg(call_mask_fp_vector_imm_op_3711, 6, vd); + setArg(call_mask_fp_vector_imm_op_3711, 7, vs2); + setArg(call_mask_fp_vector_imm_op_3711, 8, mask_fp_vector_imm_op_3711_arg8); + setArg(call_mask_fp_vector_imm_op_3711, 9, mask_fp_vector_imm_op_3711_arg9); + setArg(call_mask_fp_vector_imm_op_3711, 10, mask_fp_vector_imm_op_3711_arg10); + InvokeNode* call_fget_flags_3713; + x86::Gp ret_val_fget_flags_3713 = get_reg_Gp(cc, 32, false); + cc.invoke(&call_fget_flags_3713, &fget_flags, FuncSignature::build()); + auto flags = ret_val_fget_flags_3713; + setRet(call_fget_flags_3713, 0, ret_val_fget_flags_3713); mov(cc, load_reg_from_mem(jh, traits::FCSR), gen_operation(cc, bor, (gen_operation(cc, band, load_reg_from_mem(jh, traits::FCSR), ~ static_cast(traits::FFLAG_MASK))), (gen_operation(cc, band, flags, static_cast(traits::FFLAG_MASK))))); } cc.bind(label_merge); } - auto tmp3698 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3698, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3698, 64, false) - , traits::vstart); + auto tmp3714 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3714, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3714, traits::vstart); } cc.bind(label_merge); } @@ -85489,30 +84951,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3699; - x86::Gp ret_val_get_sew_pow_3699 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3699, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3700 = get_reg(cc, 8, false); - mov(cc, tmp3700, 1); + InvokeNode* call_get_sew_pow_3715; + x86::Gp ret_val_get_sew_pow_3715 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3715, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3716 = get_reg(cc, 8, false); + mov(cc, tmp3716, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3700, (ret_val_get_sew_pow_3699))), 8, false), ~ 1); - setArg(call_get_sew_pow_3699, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3699, 0, ret_val_get_sew_pow_3699); + (gen_operation(cc, shl, tmp3716, (ret_val_get_sew_pow_3715))), 8, false), ~ 1); + setArg(call_get_sew_pow_3715, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3715, 0, ret_val_get_sew_pow_3715); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3701; - auto illegal_fp_normal_3701_arg2 = SEW; - auto illegal_fp_normal_3701_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3701 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3701, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3701; - setArg(call_illegal_fp_normal_3701, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3701, 1, vd); - setArg(call_illegal_fp_normal_3701, 2, vm); - setArg(call_illegal_fp_normal_3701, 3, illegal_fp_normal_3701_arg2); - setArg(call_illegal_fp_normal_3701, 4, illegal_fp_normal_3701_arg3); - setRet(call_illegal_fp_normal_3701, 0, ret_val_illegal_fp_normal_3701); + InvokeNode* call_illegal_fp_normal_3717; + auto illegal_fp_normal_3717_arg2 = SEW; + auto illegal_fp_normal_3717_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3717 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3717, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3717; + setArg(call_illegal_fp_normal_3717, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3717, 1, vd); + setArg(call_illegal_fp_normal_3717, 2, vm); + setArg(call_illegal_fp_normal_3717, 3, illegal_fp_normal_3717_arg2); + setArg(call_illegal_fp_normal_3717, 4, illegal_fp_normal_3717_arg3); + setRet(call_illegal_fp_normal_3717, 0, ret_val_illegal_fp_normal_3717); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -85528,38 +84990,36 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3703; - x86::Gp ret_val_sew_3703 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3703, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3702; - auto fp_vector_unary_op_3702_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3702_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3702_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3702_arg9 = rm; - auto fp_vector_unary_op_3702_arg10 = ret_val_sew_3703; + InvokeNode* call_sew_3719; + x86::Gp ret_val_sew_3719 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3719, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3718; + auto fp_vector_unary_op_3718_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3718_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3718_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3718_arg9 = rm; + auto fp_vector_unary_op_3718_arg10 = ret_val_sew_3719; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3702, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3703, 0, reinterpret_cast(this)); - setRet(call_sew_3703, 0, ret_val_sew_3703); - setArg(call_fp_vector_unary_op_3702, 0, V); - setArg(call_fp_vector_unary_op_3702, 1, 19); - setArg(call_fp_vector_unary_op_3702, 2, 16); - setArg(call_fp_vector_unary_op_3702, 3, fp_vector_unary_op_3702_arg3); - setArg(call_fp_vector_unary_op_3702, 4, fp_vector_unary_op_3702_arg4); - setArg(call_fp_vector_unary_op_3702, 5, fp_vector_unary_op_3702_arg5); - setArg(call_fp_vector_unary_op_3702, 6, vm); - setArg(call_fp_vector_unary_op_3702, 7, vd); - setArg(call_fp_vector_unary_op_3702, 8, vs2); - setArg(call_fp_vector_unary_op_3702, 9, fp_vector_unary_op_3702_arg9); - setArg(call_fp_vector_unary_op_3702, 10, fp_vector_unary_op_3702_arg10); + cc.invoke(&call_fp_vector_unary_op_3718, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3719, 0, reinterpret_cast(this)); + setRet(call_sew_3719, 0, ret_val_sew_3719); + setArg(call_fp_vector_unary_op_3718, 0, V); + setArg(call_fp_vector_unary_op_3718, 1, 19); + setArg(call_fp_vector_unary_op_3718, 2, 16); + setArg(call_fp_vector_unary_op_3718, 3, fp_vector_unary_op_3718_arg3); + setArg(call_fp_vector_unary_op_3718, 4, fp_vector_unary_op_3718_arg4); + setArg(call_fp_vector_unary_op_3718, 5, fp_vector_unary_op_3718_arg5); + setArg(call_fp_vector_unary_op_3718, 6, vm); + setArg(call_fp_vector_unary_op_3718, 7, vd); + setArg(call_fp_vector_unary_op_3718, 8, vs2); + setArg(call_fp_vector_unary_op_3718, 9, fp_vector_unary_op_3718_arg9); + setArg(call_fp_vector_unary_op_3718, 10, fp_vector_unary_op_3718_arg10); } cc.bind(label_merge); } - auto tmp3704 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3704, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3704, 64, false) - , traits::vstart); + auto tmp3720 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3720, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3720, traits::vstart); } cc.bind(label_merge); } @@ -85602,29 +85062,29 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3705; - x86::Gp ret_val_get_sew_pow_3705 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3705, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3706 = get_reg(cc, 8, false); - mov(cc, tmp3706, 1); + InvokeNode* call_get_sew_pow_3721; + x86::Gp ret_val_get_sew_pow_3721 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3721, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3722 = get_reg(cc, 8, false); + mov(cc, tmp3722, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3706, (ret_val_get_sew_pow_3705))), 8, false), ~ 1); - setArg(call_get_sew_pow_3705, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3705, 0, ret_val_get_sew_pow_3705); + (gen_operation(cc, shl, tmp3722, (ret_val_get_sew_pow_3721))), 8, false), ~ 1); + setArg(call_get_sew_pow_3721, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3721, 0, ret_val_get_sew_pow_3721); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_masked_3707; - auto illegal_fp_vd_masked_3707_arg1 = SEW; - auto illegal_fp_vd_masked_3707_arg2 = rm; - x86::Gp ret_val_illegal_fp_vd_masked_3707 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_masked_3707, (uintptr_t)&vm_impl::_illegal_fp_vd_masked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_masked_3707; - setArg(call_illegal_fp_vd_masked_3707, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_masked_3707, 1, vd); - setArg(call_illegal_fp_vd_masked_3707, 2, illegal_fp_vd_masked_3707_arg1); - setArg(call_illegal_fp_vd_masked_3707, 3, illegal_fp_vd_masked_3707_arg2); - setRet(call_illegal_fp_vd_masked_3707, 0, ret_val_illegal_fp_vd_masked_3707); + InvokeNode* call_illegal_fp_vd_masked_3723; + auto illegal_fp_vd_masked_3723_arg1 = SEW; + auto illegal_fp_vd_masked_3723_arg2 = rm; + x86::Gp ret_val_illegal_fp_vd_masked_3723 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_masked_3723, (uintptr_t)&vm_impl::_illegal_fp_vd_masked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_masked_3723; + setArg(call_illegal_fp_vd_masked_3723, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_masked_3723, 1, vd); + setArg(call_illegal_fp_vd_masked_3723, 2, illegal_fp_vd_masked_3723_arg1); + setArg(call_illegal_fp_vd_masked_3723, 3, illegal_fp_vd_masked_3723_arg2); + setRet(call_illegal_fp_vd_masked_3723, 0, ret_val_illegal_fp_vd_masked_3723); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -85640,37 +85100,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3709; - x86::Gp ret_val_sew_3709 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3709, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_imm_merge_3708; - auto vector_imm_merge_3708_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_imm_merge_3708_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_imm_merge_3708_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_imm_merge_3708_arg7 = gen_ext(cc, + InvokeNode* call_sew_3725; + x86::Gp ret_val_sew_3725 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3725, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_3724; + auto vector_imm_merge_3724_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_3724_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_3724_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_3724_arg7 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto vector_imm_merge_3708_arg8 = ret_val_sew_3709; + auto vector_imm_merge_3724_arg8 = ret_val_sew_3725; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_merge_3708, &vector_imm_merge, FuncSignature::build()); - setArg(call_sew_3709, 0, reinterpret_cast(this)); - setRet(call_sew_3709, 0, ret_val_sew_3709); - setArg(call_vector_imm_merge_3708, 0, V); - setArg(call_vector_imm_merge_3708, 1, vector_imm_merge_3708_arg1); - setArg(call_vector_imm_merge_3708, 2, vector_imm_merge_3708_arg2); - setArg(call_vector_imm_merge_3708, 3, vector_imm_merge_3708_arg3); - setArg(call_vector_imm_merge_3708, 4, 0); - setArg(call_vector_imm_merge_3708, 5, vd); - setArg(call_vector_imm_merge_3708, 6, vs2); - setArg(call_vector_imm_merge_3708, 7, vector_imm_merge_3708_arg7); - setArg(call_vector_imm_merge_3708, 8, vector_imm_merge_3708_arg8); + cc.invoke(&call_vector_imm_merge_3724, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_3725, 0, reinterpret_cast(this)); + setRet(call_sew_3725, 0, ret_val_sew_3725); + setArg(call_vector_imm_merge_3724, 0, V); + setArg(call_vector_imm_merge_3724, 1, vector_imm_merge_3724_arg1); + setArg(call_vector_imm_merge_3724, 2, vector_imm_merge_3724_arg2); + setArg(call_vector_imm_merge_3724, 3, vector_imm_merge_3724_arg3); + setArg(call_vector_imm_merge_3724, 4, 0); + setArg(call_vector_imm_merge_3724, 5, vd); + setArg(call_vector_imm_merge_3724, 6, vs2); + setArg(call_vector_imm_merge_3724, 7, vector_imm_merge_3724_arg7); + setArg(call_vector_imm_merge_3724, 8, vector_imm_merge_3724_arg8); } cc.bind(label_merge); } - auto tmp3710 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3710, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3710, 64, false) - , traits::vstart); + auto tmp3726 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3726, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3726, traits::vstart); } cc.bind(label_merge); } @@ -85712,28 +85170,28 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3711; - x86::Gp ret_val_get_sew_pow_3711 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3711, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3712 = get_reg(cc, 8, false); - mov(cc, tmp3712, 1); + InvokeNode* call_get_sew_pow_3727; + x86::Gp ret_val_get_sew_pow_3727 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3727, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3728 = get_reg(cc, 8, false); + mov(cc, tmp3728, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3712, (ret_val_get_sew_pow_3711))), 8, false), ~ 1); - setArg(call_get_sew_pow_3711, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3711, 0, ret_val_get_sew_pow_3711); + (gen_operation(cc, shl, tmp3728, (ret_val_get_sew_pow_3727))), 8, false), ~ 1); + setArg(call_get_sew_pow_3727, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3727, 0, ret_val_get_sew_pow_3727); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_vd_unmasked_3713; - auto illegal_fp_vd_unmasked_3713_arg0 = SEW; - auto illegal_fp_vd_unmasked_3713_arg1 = rm; - x86::Gp ret_val_illegal_fp_vd_unmasked_3713 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_vd_unmasked_3713, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); - auto cond = ret_val_illegal_fp_vd_unmasked_3713; - setArg(call_illegal_fp_vd_unmasked_3713, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_vd_unmasked_3713, 1, illegal_fp_vd_unmasked_3713_arg0); - setArg(call_illegal_fp_vd_unmasked_3713, 2, illegal_fp_vd_unmasked_3713_arg1); - setRet(call_illegal_fp_vd_unmasked_3713, 0, ret_val_illegal_fp_vd_unmasked_3713); + InvokeNode* call_illegal_fp_vd_unmasked_3729; + auto illegal_fp_vd_unmasked_3729_arg0 = SEW; + auto illegal_fp_vd_unmasked_3729_arg1 = rm; + x86::Gp ret_val_illegal_fp_vd_unmasked_3729 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_vd_unmasked_3729, (uintptr_t)&vm_impl::_illegal_fp_vd_unmasked, FuncSignature::build()); + auto cond = ret_val_illegal_fp_vd_unmasked_3729; + setArg(call_illegal_fp_vd_unmasked_3729, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_vd_unmasked_3729, 1, illegal_fp_vd_unmasked_3729_arg0); + setArg(call_illegal_fp_vd_unmasked_3729, 2, illegal_fp_vd_unmasked_3729_arg1); + setRet(call_illegal_fp_vd_unmasked_3729, 0, ret_val_illegal_fp_vd_unmasked_3729); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -85749,37 +85207,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3715; - x86::Gp ret_val_sew_3715 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3715, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_vector_imm_merge_3714; - auto vector_imm_merge_3714_arg1 = load_reg_from_mem(jh, traits::vl); - auto vector_imm_merge_3714_arg2 = load_reg_from_mem(jh, traits::vstart); - auto vector_imm_merge_3714_arg3 = load_reg_from_mem(jh, traits::vtype); - auto vector_imm_merge_3714_arg7 = gen_ext(cc, + InvokeNode* call_sew_3731; + x86::Gp ret_val_sew_3731 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3731, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_vector_imm_merge_3730; + auto vector_imm_merge_3730_arg1 = load_reg_from_mem(jh, traits::vl); + auto vector_imm_merge_3730_arg2 = load_reg_from_mem(jh, traits::vstart); + auto vector_imm_merge_3730_arg3 = load_reg_from_mem(jh, traits::vtype); + auto vector_imm_merge_3730_arg7 = gen_ext(cc, load_reg_from_mem_Gp(jh, traits::F0 + rs1), 64, false); - auto vector_imm_merge_3714_arg8 = ret_val_sew_3715; + auto vector_imm_merge_3730_arg8 = ret_val_sew_3731; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_vector_imm_merge_3714, &vector_imm_merge, FuncSignature::build()); - setArg(call_sew_3715, 0, reinterpret_cast(this)); - setRet(call_sew_3715, 0, ret_val_sew_3715); - setArg(call_vector_imm_merge_3714, 0, V); - setArg(call_vector_imm_merge_3714, 1, vector_imm_merge_3714_arg1); - setArg(call_vector_imm_merge_3714, 2, vector_imm_merge_3714_arg2); - setArg(call_vector_imm_merge_3714, 3, vector_imm_merge_3714_arg3); - setArg(call_vector_imm_merge_3714, 4, 1); - setArg(call_vector_imm_merge_3714, 5, vd); - setArg(call_vector_imm_merge_3714, 6, 0); - setArg(call_vector_imm_merge_3714, 7, vector_imm_merge_3714_arg7); - setArg(call_vector_imm_merge_3714, 8, vector_imm_merge_3714_arg8); + cc.invoke(&call_vector_imm_merge_3730, &vector_imm_merge, FuncSignature::build()); + setArg(call_sew_3731, 0, reinterpret_cast(this)); + setRet(call_sew_3731, 0, ret_val_sew_3731); + setArg(call_vector_imm_merge_3730, 0, V); + setArg(call_vector_imm_merge_3730, 1, vector_imm_merge_3730_arg1); + setArg(call_vector_imm_merge_3730, 2, vector_imm_merge_3730_arg2); + setArg(call_vector_imm_merge_3730, 3, vector_imm_merge_3730_arg3); + setArg(call_vector_imm_merge_3730, 4, 1); + setArg(call_vector_imm_merge_3730, 5, vd); + setArg(call_vector_imm_merge_3730, 6, 0); + setArg(call_vector_imm_merge_3730, 7, vector_imm_merge_3730_arg7); + setArg(call_vector_imm_merge_3730, 8, vector_imm_merge_3730_arg8); } cc.bind(label_merge); } - auto tmp3716 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3716, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3716, 64, false) - , traits::vstart); + auto tmp3732 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3732, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3732, traits::vstart); } cc.bind(label_merge); } @@ -85822,30 +85278,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3717; - x86::Gp ret_val_get_sew_pow_3717 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3717, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3718 = get_reg(cc, 8, false); - mov(cc, tmp3718, 1); + InvokeNode* call_get_sew_pow_3733; + x86::Gp ret_val_get_sew_pow_3733 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3733, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3734 = get_reg(cc, 8, false); + mov(cc, tmp3734, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3718, (ret_val_get_sew_pow_3717))), 8, false), ~ 1); - setArg(call_get_sew_pow_3717, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3717, 0, ret_val_get_sew_pow_3717); + (gen_operation(cc, shl, tmp3734, (ret_val_get_sew_pow_3733))), 8, false), ~ 1); + setArg(call_get_sew_pow_3733, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3733, 0, ret_val_get_sew_pow_3733); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3719; - auto illegal_fp_normal_3719_arg2 = SEW; - auto illegal_fp_normal_3719_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3719 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3719, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3719; - setArg(call_illegal_fp_normal_3719, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3719, 1, vd); - setArg(call_illegal_fp_normal_3719, 2, vm); - setArg(call_illegal_fp_normal_3719, 3, illegal_fp_normal_3719_arg2); - setArg(call_illegal_fp_normal_3719, 4, illegal_fp_normal_3719_arg3); - setRet(call_illegal_fp_normal_3719, 0, ret_val_illegal_fp_normal_3719); + InvokeNode* call_illegal_fp_normal_3735; + auto illegal_fp_normal_3735_arg2 = SEW; + auto illegal_fp_normal_3735_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3735 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3735, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3735; + setArg(call_illegal_fp_normal_3735, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3735, 1, vd); + setArg(call_illegal_fp_normal_3735, 2, vm); + setArg(call_illegal_fp_normal_3735, 3, illegal_fp_normal_3735_arg2); + setArg(call_illegal_fp_normal_3735, 4, illegal_fp_normal_3735_arg3); + setRet(call_illegal_fp_normal_3735, 0, ret_val_illegal_fp_normal_3735); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -85861,38 +85317,36 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3721; - x86::Gp ret_val_sew_3721 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3721, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3720; - auto fp_vector_unary_op_3720_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3720_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3720_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3720_arg9 = rm; - auto fp_vector_unary_op_3720_arg10 = ret_val_sew_3721; + InvokeNode* call_sew_3737; + x86::Gp ret_val_sew_3737 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3737, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3736; + auto fp_vector_unary_op_3736_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3736_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3736_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3736_arg9 = rm; + auto fp_vector_unary_op_3736_arg10 = ret_val_sew_3737; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3720, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3721, 0, reinterpret_cast(this)); - setRet(call_sew_3721, 0, ret_val_sew_3721); - setArg(call_fp_vector_unary_op_3720, 0, V); - setArg(call_fp_vector_unary_op_3720, 1, 18); - setArg(call_fp_vector_unary_op_3720, 2, 0); - setArg(call_fp_vector_unary_op_3720, 3, fp_vector_unary_op_3720_arg3); - setArg(call_fp_vector_unary_op_3720, 4, fp_vector_unary_op_3720_arg4); - setArg(call_fp_vector_unary_op_3720, 5, fp_vector_unary_op_3720_arg5); - setArg(call_fp_vector_unary_op_3720, 6, vm); - setArg(call_fp_vector_unary_op_3720, 7, vd); - setArg(call_fp_vector_unary_op_3720, 8, vs2); - setArg(call_fp_vector_unary_op_3720, 9, fp_vector_unary_op_3720_arg9); - setArg(call_fp_vector_unary_op_3720, 10, fp_vector_unary_op_3720_arg10); + cc.invoke(&call_fp_vector_unary_op_3736, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3737, 0, reinterpret_cast(this)); + setRet(call_sew_3737, 0, ret_val_sew_3737); + setArg(call_fp_vector_unary_op_3736, 0, V); + setArg(call_fp_vector_unary_op_3736, 1, 18); + setArg(call_fp_vector_unary_op_3736, 2, 0); + setArg(call_fp_vector_unary_op_3736, 3, fp_vector_unary_op_3736_arg3); + setArg(call_fp_vector_unary_op_3736, 4, fp_vector_unary_op_3736_arg4); + setArg(call_fp_vector_unary_op_3736, 5, fp_vector_unary_op_3736_arg5); + setArg(call_fp_vector_unary_op_3736, 6, vm); + setArg(call_fp_vector_unary_op_3736, 7, vd); + setArg(call_fp_vector_unary_op_3736, 8, vs2); + setArg(call_fp_vector_unary_op_3736, 9, fp_vector_unary_op_3736_arg9); + setArg(call_fp_vector_unary_op_3736, 10, fp_vector_unary_op_3736_arg10); } cc.bind(label_merge); } - auto tmp3722 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3722, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3722, 64, false) - , traits::vstart); + auto tmp3738 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3738, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3738, traits::vstart); } cc.bind(label_merge); } @@ -85935,30 +85389,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3723; - x86::Gp ret_val_get_sew_pow_3723 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3723, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3724 = get_reg(cc, 8, false); - mov(cc, tmp3724, 1); + InvokeNode* call_get_sew_pow_3739; + x86::Gp ret_val_get_sew_pow_3739 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3739, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3740 = get_reg(cc, 8, false); + mov(cc, tmp3740, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3724, (ret_val_get_sew_pow_3723))), 8, false), ~ 1); - setArg(call_get_sew_pow_3723, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3723, 0, ret_val_get_sew_pow_3723); + (gen_operation(cc, shl, tmp3740, (ret_val_get_sew_pow_3739))), 8, false), ~ 1); + setArg(call_get_sew_pow_3739, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3739, 0, ret_val_get_sew_pow_3739); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3725; - auto illegal_fp_normal_3725_arg2 = SEW; - auto illegal_fp_normal_3725_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3725 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3725, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3725; - setArg(call_illegal_fp_normal_3725, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3725, 1, vd); - setArg(call_illegal_fp_normal_3725, 2, vm); - setArg(call_illegal_fp_normal_3725, 3, illegal_fp_normal_3725_arg2); - setArg(call_illegal_fp_normal_3725, 4, illegal_fp_normal_3725_arg3); - setRet(call_illegal_fp_normal_3725, 0, ret_val_illegal_fp_normal_3725); + InvokeNode* call_illegal_fp_normal_3741; + auto illegal_fp_normal_3741_arg2 = SEW; + auto illegal_fp_normal_3741_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3741 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3741, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3741; + setArg(call_illegal_fp_normal_3741, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3741, 1, vd); + setArg(call_illegal_fp_normal_3741, 2, vm); + setArg(call_illegal_fp_normal_3741, 3, illegal_fp_normal_3741_arg2); + setArg(call_illegal_fp_normal_3741, 4, illegal_fp_normal_3741_arg3); + setRet(call_illegal_fp_normal_3741, 0, ret_val_illegal_fp_normal_3741); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -85974,38 +85428,36 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3727; - x86::Gp ret_val_sew_3727 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3727, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3726; - auto fp_vector_unary_op_3726_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3726_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3726_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3726_arg9 = rm; - auto fp_vector_unary_op_3726_arg10 = ret_val_sew_3727; + InvokeNode* call_sew_3743; + x86::Gp ret_val_sew_3743 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3743, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3742; + auto fp_vector_unary_op_3742_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3742_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3742_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3742_arg9 = rm; + auto fp_vector_unary_op_3742_arg10 = ret_val_sew_3743; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3726, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3727, 0, reinterpret_cast(this)); - setRet(call_sew_3727, 0, ret_val_sew_3727); - setArg(call_fp_vector_unary_op_3726, 0, V); - setArg(call_fp_vector_unary_op_3726, 1, 18); - setArg(call_fp_vector_unary_op_3726, 2, 1); - setArg(call_fp_vector_unary_op_3726, 3, fp_vector_unary_op_3726_arg3); - setArg(call_fp_vector_unary_op_3726, 4, fp_vector_unary_op_3726_arg4); - setArg(call_fp_vector_unary_op_3726, 5, fp_vector_unary_op_3726_arg5); - setArg(call_fp_vector_unary_op_3726, 6, vm); - setArg(call_fp_vector_unary_op_3726, 7, vd); - setArg(call_fp_vector_unary_op_3726, 8, vs2); - setArg(call_fp_vector_unary_op_3726, 9, fp_vector_unary_op_3726_arg9); - setArg(call_fp_vector_unary_op_3726, 10, fp_vector_unary_op_3726_arg10); + cc.invoke(&call_fp_vector_unary_op_3742, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3743, 0, reinterpret_cast(this)); + setRet(call_sew_3743, 0, ret_val_sew_3743); + setArg(call_fp_vector_unary_op_3742, 0, V); + setArg(call_fp_vector_unary_op_3742, 1, 18); + setArg(call_fp_vector_unary_op_3742, 2, 1); + setArg(call_fp_vector_unary_op_3742, 3, fp_vector_unary_op_3742_arg3); + setArg(call_fp_vector_unary_op_3742, 4, fp_vector_unary_op_3742_arg4); + setArg(call_fp_vector_unary_op_3742, 5, fp_vector_unary_op_3742_arg5); + setArg(call_fp_vector_unary_op_3742, 6, vm); + setArg(call_fp_vector_unary_op_3742, 7, vd); + setArg(call_fp_vector_unary_op_3742, 8, vs2); + setArg(call_fp_vector_unary_op_3742, 9, fp_vector_unary_op_3742_arg9); + setArg(call_fp_vector_unary_op_3742, 10, fp_vector_unary_op_3742_arg10); } cc.bind(label_merge); } - auto tmp3728 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3728, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3728, 64, false) - , traits::vstart); + auto tmp3744 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3744, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3744, traits::vstart); } cc.bind(label_merge); } @@ -86048,29 +85500,29 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3729; - x86::Gp ret_val_get_sew_pow_3729 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3729, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3730 = get_reg(cc, 8, false); - mov(cc, tmp3730, 1); + InvokeNode* call_get_sew_pow_3745; + x86::Gp ret_val_get_sew_pow_3745 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3745, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3746 = get_reg(cc, 8, false); + mov(cc, tmp3746, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3730, (ret_val_get_sew_pow_3729))), 8, false), ~ 1); - setArg(call_get_sew_pow_3729, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3729, 0, ret_val_get_sew_pow_3729); + (gen_operation(cc, shl, tmp3746, (ret_val_get_sew_pow_3745))), 8, false), ~ 1); + setArg(call_get_sew_pow_3745, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3745, 0, ret_val_get_sew_pow_3745); auto rm = 1; { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3731; - auto illegal_fp_normal_3731_arg2 = SEW; - x86::Gp ret_val_illegal_fp_normal_3731 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3731, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3731; - setArg(call_illegal_fp_normal_3731, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3731, 1, vd); - setArg(call_illegal_fp_normal_3731, 2, vm); - setArg(call_illegal_fp_normal_3731, 3, illegal_fp_normal_3731_arg2); - setArg(call_illegal_fp_normal_3731, 4, rm); - setRet(call_illegal_fp_normal_3731, 0, ret_val_illegal_fp_normal_3731); + InvokeNode* call_illegal_fp_normal_3747; + auto illegal_fp_normal_3747_arg2 = SEW; + x86::Gp ret_val_illegal_fp_normal_3747 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3747, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3747; + setArg(call_illegal_fp_normal_3747, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3747, 1, vd); + setArg(call_illegal_fp_normal_3747, 2, vm); + setArg(call_illegal_fp_normal_3747, 3, illegal_fp_normal_3747_arg2); + setArg(call_illegal_fp_normal_3747, 4, rm); + setRet(call_illegal_fp_normal_3747, 0, ret_val_illegal_fp_normal_3747); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -86086,37 +85538,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3733; - x86::Gp ret_val_sew_3733 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3733, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3732; - auto fp_vector_unary_op_3732_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3732_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3732_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3732_arg10 = ret_val_sew_3733; + InvokeNode* call_sew_3749; + x86::Gp ret_val_sew_3749 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3749, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3748; + auto fp_vector_unary_op_3748_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3748_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3748_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3748_arg10 = ret_val_sew_3749; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3732, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3733, 0, reinterpret_cast(this)); - setRet(call_sew_3733, 0, ret_val_sew_3733); - setArg(call_fp_vector_unary_op_3732, 0, V); - setArg(call_fp_vector_unary_op_3732, 1, 18); - setArg(call_fp_vector_unary_op_3732, 2, 6); - setArg(call_fp_vector_unary_op_3732, 3, fp_vector_unary_op_3732_arg3); - setArg(call_fp_vector_unary_op_3732, 4, fp_vector_unary_op_3732_arg4); - setArg(call_fp_vector_unary_op_3732, 5, fp_vector_unary_op_3732_arg5); - setArg(call_fp_vector_unary_op_3732, 6, vm); - setArg(call_fp_vector_unary_op_3732, 7, vd); - setArg(call_fp_vector_unary_op_3732, 8, vs2); - setArg(call_fp_vector_unary_op_3732, 9, rm); - setArg(call_fp_vector_unary_op_3732, 10, fp_vector_unary_op_3732_arg10); + cc.invoke(&call_fp_vector_unary_op_3748, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3749, 0, reinterpret_cast(this)); + setRet(call_sew_3749, 0, ret_val_sew_3749); + setArg(call_fp_vector_unary_op_3748, 0, V); + setArg(call_fp_vector_unary_op_3748, 1, 18); + setArg(call_fp_vector_unary_op_3748, 2, 6); + setArg(call_fp_vector_unary_op_3748, 3, fp_vector_unary_op_3748_arg3); + setArg(call_fp_vector_unary_op_3748, 4, fp_vector_unary_op_3748_arg4); + setArg(call_fp_vector_unary_op_3748, 5, fp_vector_unary_op_3748_arg5); + setArg(call_fp_vector_unary_op_3748, 6, vm); + setArg(call_fp_vector_unary_op_3748, 7, vd); + setArg(call_fp_vector_unary_op_3748, 8, vs2); + setArg(call_fp_vector_unary_op_3748, 9, rm); + setArg(call_fp_vector_unary_op_3748, 10, fp_vector_unary_op_3748_arg10); } cc.bind(label_merge); } - auto tmp3734 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3734, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3734, 64, false) - , traits::vstart); + auto tmp3750 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3750, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3750, traits::vstart); } cc.bind(label_merge); } @@ -86159,29 +85609,29 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3735; - x86::Gp ret_val_get_sew_pow_3735 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3735, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3736 = get_reg(cc, 8, false); - mov(cc, tmp3736, 1); + InvokeNode* call_get_sew_pow_3751; + x86::Gp ret_val_get_sew_pow_3751 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3751, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3752 = get_reg(cc, 8, false); + mov(cc, tmp3752, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3736, (ret_val_get_sew_pow_3735))), 8, false), ~ 1); - setArg(call_get_sew_pow_3735, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3735, 0, ret_val_get_sew_pow_3735); + (gen_operation(cc, shl, tmp3752, (ret_val_get_sew_pow_3751))), 8, false), ~ 1); + setArg(call_get_sew_pow_3751, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3751, 0, ret_val_get_sew_pow_3751); auto rm = 1; { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3737; - auto illegal_fp_normal_3737_arg2 = SEW; - x86::Gp ret_val_illegal_fp_normal_3737 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3737, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3737; - setArg(call_illegal_fp_normal_3737, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3737, 1, vd); - setArg(call_illegal_fp_normal_3737, 2, vm); - setArg(call_illegal_fp_normal_3737, 3, illegal_fp_normal_3737_arg2); - setArg(call_illegal_fp_normal_3737, 4, rm); - setRet(call_illegal_fp_normal_3737, 0, ret_val_illegal_fp_normal_3737); + InvokeNode* call_illegal_fp_normal_3753; + auto illegal_fp_normal_3753_arg2 = SEW; + x86::Gp ret_val_illegal_fp_normal_3753 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3753, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3753; + setArg(call_illegal_fp_normal_3753, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3753, 1, vd); + setArg(call_illegal_fp_normal_3753, 2, vm); + setArg(call_illegal_fp_normal_3753, 3, illegal_fp_normal_3753_arg2); + setArg(call_illegal_fp_normal_3753, 4, rm); + setRet(call_illegal_fp_normal_3753, 0, ret_val_illegal_fp_normal_3753); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -86197,37 +85647,35 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3739; - x86::Gp ret_val_sew_3739 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3739, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3738; - auto fp_vector_unary_op_3738_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3738_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3738_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3738_arg10 = ret_val_sew_3739; + InvokeNode* call_sew_3755; + x86::Gp ret_val_sew_3755 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3755, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3754; + auto fp_vector_unary_op_3754_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3754_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3754_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3754_arg10 = ret_val_sew_3755; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3738, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3739, 0, reinterpret_cast(this)); - setRet(call_sew_3739, 0, ret_val_sew_3739); - setArg(call_fp_vector_unary_op_3738, 0, V); - setArg(call_fp_vector_unary_op_3738, 1, 18); - setArg(call_fp_vector_unary_op_3738, 2, 7); - setArg(call_fp_vector_unary_op_3738, 3, fp_vector_unary_op_3738_arg3); - setArg(call_fp_vector_unary_op_3738, 4, fp_vector_unary_op_3738_arg4); - setArg(call_fp_vector_unary_op_3738, 5, fp_vector_unary_op_3738_arg5); - setArg(call_fp_vector_unary_op_3738, 6, vm); - setArg(call_fp_vector_unary_op_3738, 7, vd); - setArg(call_fp_vector_unary_op_3738, 8, vs2); - setArg(call_fp_vector_unary_op_3738, 9, rm); - setArg(call_fp_vector_unary_op_3738, 10, fp_vector_unary_op_3738_arg10); + cc.invoke(&call_fp_vector_unary_op_3754, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3755, 0, reinterpret_cast(this)); + setRet(call_sew_3755, 0, ret_val_sew_3755); + setArg(call_fp_vector_unary_op_3754, 0, V); + setArg(call_fp_vector_unary_op_3754, 1, 18); + setArg(call_fp_vector_unary_op_3754, 2, 7); + setArg(call_fp_vector_unary_op_3754, 3, fp_vector_unary_op_3754_arg3); + setArg(call_fp_vector_unary_op_3754, 4, fp_vector_unary_op_3754_arg4); + setArg(call_fp_vector_unary_op_3754, 5, fp_vector_unary_op_3754_arg5); + setArg(call_fp_vector_unary_op_3754, 6, vm); + setArg(call_fp_vector_unary_op_3754, 7, vd); + setArg(call_fp_vector_unary_op_3754, 8, vs2); + setArg(call_fp_vector_unary_op_3754, 9, rm); + setArg(call_fp_vector_unary_op_3754, 10, fp_vector_unary_op_3754_arg10); } cc.bind(label_merge); } - auto tmp3740 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3740, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3740, 64, false) - , traits::vstart); + auto tmp3756 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3756, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3756, traits::vstart); } cc.bind(label_merge); } @@ -86270,30 +85718,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3741; - x86::Gp ret_val_get_sew_pow_3741 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3741, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3742 = get_reg(cc, 8, false); - mov(cc, tmp3742, 1); + InvokeNode* call_get_sew_pow_3757; + x86::Gp ret_val_get_sew_pow_3757 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3757, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3758 = get_reg(cc, 8, false); + mov(cc, tmp3758, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3742, (ret_val_get_sew_pow_3741))), 8, false), ~ 1); - setArg(call_get_sew_pow_3741, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3741, 0, ret_val_get_sew_pow_3741); + (gen_operation(cc, shl, tmp3758, (ret_val_get_sew_pow_3757))), 8, false), ~ 1); + setArg(call_get_sew_pow_3757, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3757, 0, ret_val_get_sew_pow_3757); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3743; - auto illegal_fp_normal_3743_arg2 = SEW; - auto illegal_fp_normal_3743_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3743 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3743, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3743; - setArg(call_illegal_fp_normal_3743, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3743, 1, vd); - setArg(call_illegal_fp_normal_3743, 2, vm); - setArg(call_illegal_fp_normal_3743, 3, illegal_fp_normal_3743_arg2); - setArg(call_illegal_fp_normal_3743, 4, illegal_fp_normal_3743_arg3); - setRet(call_illegal_fp_normal_3743, 0, ret_val_illegal_fp_normal_3743); + InvokeNode* call_illegal_fp_normal_3759; + auto illegal_fp_normal_3759_arg2 = SEW; + auto illegal_fp_normal_3759_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3759 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3759, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3759; + setArg(call_illegal_fp_normal_3759, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3759, 1, vd); + setArg(call_illegal_fp_normal_3759, 2, vm); + setArg(call_illegal_fp_normal_3759, 3, illegal_fp_normal_3759_arg2); + setArg(call_illegal_fp_normal_3759, 4, illegal_fp_normal_3759_arg3); + setRet(call_illegal_fp_normal_3759, 0, ret_val_illegal_fp_normal_3759); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -86309,38 +85757,36 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3745; - x86::Gp ret_val_sew_3745 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3745, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3744; - auto fp_vector_unary_op_3744_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3744_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3744_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3744_arg9 = rm; - auto fp_vector_unary_op_3744_arg10 = ret_val_sew_3745; + InvokeNode* call_sew_3761; + x86::Gp ret_val_sew_3761 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3761, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3760; + auto fp_vector_unary_op_3760_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3760_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3760_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3760_arg9 = rm; + auto fp_vector_unary_op_3760_arg10 = ret_val_sew_3761; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3744, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3745, 0, reinterpret_cast(this)); - setRet(call_sew_3745, 0, ret_val_sew_3745); - setArg(call_fp_vector_unary_op_3744, 0, V); - setArg(call_fp_vector_unary_op_3744, 1, 18); - setArg(call_fp_vector_unary_op_3744, 2, 2); - setArg(call_fp_vector_unary_op_3744, 3, fp_vector_unary_op_3744_arg3); - setArg(call_fp_vector_unary_op_3744, 4, fp_vector_unary_op_3744_arg4); - setArg(call_fp_vector_unary_op_3744, 5, fp_vector_unary_op_3744_arg5); - setArg(call_fp_vector_unary_op_3744, 6, vm); - setArg(call_fp_vector_unary_op_3744, 7, vd); - setArg(call_fp_vector_unary_op_3744, 8, vs2); - setArg(call_fp_vector_unary_op_3744, 9, fp_vector_unary_op_3744_arg9); - setArg(call_fp_vector_unary_op_3744, 10, fp_vector_unary_op_3744_arg10); + cc.invoke(&call_fp_vector_unary_op_3760, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3761, 0, reinterpret_cast(this)); + setRet(call_sew_3761, 0, ret_val_sew_3761); + setArg(call_fp_vector_unary_op_3760, 0, V); + setArg(call_fp_vector_unary_op_3760, 1, 18); + setArg(call_fp_vector_unary_op_3760, 2, 2); + setArg(call_fp_vector_unary_op_3760, 3, fp_vector_unary_op_3760_arg3); + setArg(call_fp_vector_unary_op_3760, 4, fp_vector_unary_op_3760_arg4); + setArg(call_fp_vector_unary_op_3760, 5, fp_vector_unary_op_3760_arg5); + setArg(call_fp_vector_unary_op_3760, 6, vm); + setArg(call_fp_vector_unary_op_3760, 7, vd); + setArg(call_fp_vector_unary_op_3760, 8, vs2); + setArg(call_fp_vector_unary_op_3760, 9, fp_vector_unary_op_3760_arg9); + setArg(call_fp_vector_unary_op_3760, 10, fp_vector_unary_op_3760_arg10); } cc.bind(label_merge); } - auto tmp3746 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3746, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3746, 64, false) - , traits::vstart); + auto tmp3762 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3762, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3762, traits::vstart); } cc.bind(label_merge); } @@ -86383,30 +85829,30 @@ template class vm_impl : public iss::asmjit::vm_base { gen_instr_prologue(jh); /*generate behavior*/ - InvokeNode* call_get_sew_pow_3747; - x86::Gp ret_val_get_sew_pow_3747 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3747, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3748 = get_reg(cc, 8, false); - mov(cc, tmp3748, 1); + InvokeNode* call_get_sew_pow_3763; + x86::Gp ret_val_get_sew_pow_3763 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3763, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3764 = get_reg(cc, 8, false); + mov(cc, tmp3764, 1); auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3748, (ret_val_get_sew_pow_3747))), 8, false), ~ 1); - setArg(call_get_sew_pow_3747, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3747, 0, ret_val_get_sew_pow_3747); + (gen_operation(cc, shl, tmp3764, (ret_val_get_sew_pow_3763))), 8, false), ~ 1); + setArg(call_get_sew_pow_3763, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3763, 0, ret_val_get_sew_pow_3763); auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_normal_3749; - auto illegal_fp_normal_3749_arg2 = SEW; - auto illegal_fp_normal_3749_arg3 = rm; - x86::Gp ret_val_illegal_fp_normal_3749 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_normal_3749, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); - auto cond = ret_val_illegal_fp_normal_3749; - setArg(call_illegal_fp_normal_3749, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_normal_3749, 1, vd); - setArg(call_illegal_fp_normal_3749, 2, vm); - setArg(call_illegal_fp_normal_3749, 3, illegal_fp_normal_3749_arg2); - setArg(call_illegal_fp_normal_3749, 4, illegal_fp_normal_3749_arg3); - setRet(call_illegal_fp_normal_3749, 0, ret_val_illegal_fp_normal_3749); + InvokeNode* call_illegal_fp_normal_3765; + auto illegal_fp_normal_3765_arg2 = SEW; + auto illegal_fp_normal_3765_arg3 = rm; + x86::Gp ret_val_illegal_fp_normal_3765 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_normal_3765, (uintptr_t)&vm_impl::_illegal_fp_normal, FuncSignature::build()); + auto cond = ret_val_illegal_fp_normal_3765; + setArg(call_illegal_fp_normal_3765, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_normal_3765, 1, vd); + setArg(call_illegal_fp_normal_3765, 2, vm); + setArg(call_illegal_fp_normal_3765, 3, illegal_fp_normal_3765_arg2); + setArg(call_illegal_fp_normal_3765, 4, illegal_fp_normal_3765_arg3); + setRet(call_illegal_fp_normal_3765, 0, ret_val_illegal_fp_normal_3765); cmp(cc, cond, 0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -86422,38 +85868,36 @@ template class vm_impl : public iss::asmjit::vm_base { cmp(cc, cond, 0); cc.je(label_merge); { - InvokeNode* call_sew_3751; - x86::Gp ret_val_sew_3751 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3751, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_op_3750; - auto fp_vector_unary_op_3750_arg3 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_op_3750_arg4 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_op_3750_arg5 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_op_3750_arg9 = rm; - auto fp_vector_unary_op_3750_arg10 = ret_val_sew_3751; + InvokeNode* call_sew_3767; + x86::Gp ret_val_sew_3767 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3767, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_op_3766; + auto fp_vector_unary_op_3766_arg3 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_op_3766_arg4 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_op_3766_arg5 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_op_3766_arg9 = rm; + auto fp_vector_unary_op_3766_arg10 = ret_val_sew_3767; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_op_3750, &fp_vector_unary_op, FuncSignature::build()); - setArg(call_sew_3751, 0, reinterpret_cast(this)); - setRet(call_sew_3751, 0, ret_val_sew_3751); - setArg(call_fp_vector_unary_op_3750, 0, V); - setArg(call_fp_vector_unary_op_3750, 1, 18); - setArg(call_fp_vector_unary_op_3750, 2, 3); - setArg(call_fp_vector_unary_op_3750, 3, fp_vector_unary_op_3750_arg3); - setArg(call_fp_vector_unary_op_3750, 4, fp_vector_unary_op_3750_arg4); - setArg(call_fp_vector_unary_op_3750, 5, fp_vector_unary_op_3750_arg5); - setArg(call_fp_vector_unary_op_3750, 6, vm); - setArg(call_fp_vector_unary_op_3750, 7, vd); - setArg(call_fp_vector_unary_op_3750, 8, vs2); - setArg(call_fp_vector_unary_op_3750, 9, fp_vector_unary_op_3750_arg9); - setArg(call_fp_vector_unary_op_3750, 10, fp_vector_unary_op_3750_arg10); + cc.invoke(&call_fp_vector_unary_op_3766, &fp_vector_unary_op, FuncSignature::build()); + setArg(call_sew_3767, 0, reinterpret_cast(this)); + setRet(call_sew_3767, 0, ret_val_sew_3767); + setArg(call_fp_vector_unary_op_3766, 0, V); + setArg(call_fp_vector_unary_op_3766, 1, 18); + setArg(call_fp_vector_unary_op_3766, 2, 3); + setArg(call_fp_vector_unary_op_3766, 3, fp_vector_unary_op_3766_arg3); + setArg(call_fp_vector_unary_op_3766, 4, fp_vector_unary_op_3766_arg4); + setArg(call_fp_vector_unary_op_3766, 5, fp_vector_unary_op_3766_arg5); + setArg(call_fp_vector_unary_op_3766, 6, vm); + setArg(call_fp_vector_unary_op_3766, 7, vd); + setArg(call_fp_vector_unary_op_3766, 8, vs2); + setArg(call_fp_vector_unary_op_3766, 9, fp_vector_unary_op_3766_arg9); + setArg(call_fp_vector_unary_op_3766, 10, fp_vector_unary_op_3766_arg10); } cc.bind(label_merge); } - auto tmp3752 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3752, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3752, 64, false) - , traits::vstart); + auto tmp3768 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3768, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3768, traits::vstart); } cc.bind(label_merge); } @@ -86494,278 +85938,6 @@ template class vm_impl : public iss::asmjit::vm_base { mov(cc, jh.next_pc, pc.val); cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); - gen_instr_prologue(jh); - /*generate behavior*/ - InvokeNode* call_get_sew_pow_3753; - x86::Gp ret_val_get_sew_pow_3753 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3753, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3754 = get_reg(cc, 8, false); - mov(cc, tmp3754, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3754, (ret_val_get_sew_pow_3753))), 8, false), ~ 1); - setArg(call_get_sew_pow_3753, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3753, 0, ret_val_get_sew_pow_3753); - InvokeNode* call_get_lmul_pow_3755; - x86::Gp ret_val_get_lmul_pow_3755 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3755, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3755; - setArg(call_get_lmul_pow_3755, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3755, 0, ret_val_get_lmul_pow_3755); - auto SEW_widen = gen_ext(cc, - (gen_operation(cc, umul, SEW, 2)), 8, false); - auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); - { - auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3756; - auto illegal_fp_variable_width_3756_arg2 = SEW; - auto illegal_fp_variable_width_3756_arg3 = rm; - auto illegal_fp_variable_width_3756_arg4 = SEW_widen; - auto illegal_fp_variable_width_3756_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3756 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3756, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3757; - auto valid_reg_overlap_3757_arg2 = LMUL_pow; - auto valid_reg_overlap_3757_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3757 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3757, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3756, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3757)); - setArg(call_illegal_fp_variable_width_3756, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3756, 1, vd); - setArg(call_illegal_fp_variable_width_3756, 2, vm); - setArg(call_illegal_fp_variable_width_3756, 3, illegal_fp_variable_width_3756_arg2); - setArg(call_illegal_fp_variable_width_3756, 4, illegal_fp_variable_width_3756_arg3); - setArg(call_illegal_fp_variable_width_3756, 5, illegal_fp_variable_width_3756_arg4); - setArg(call_illegal_fp_variable_width_3756, 6, illegal_fp_variable_width_3756_arg5); - setRet(call_illegal_fp_variable_width_3756, 0, ret_val_illegal_fp_variable_width_3756); - setArg(call_valid_reg_overlap_3757, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3757, 1, vs2); - setArg(call_valid_reg_overlap_3757, 2, vd); - setArg(call_valid_reg_overlap_3757, 3, valid_reg_overlap_3757_arg2); - setArg(call_valid_reg_overlap_3757, 4, valid_reg_overlap_3757_arg3); - setRet(call_valid_reg_overlap_3757, 0, ret_val_valid_reg_overlap_3757); - cmp(cc, cond, 0); - auto label_else = cc.newLabel(); - cc.je(label_else); - { - gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); - } - cc.jmp(label_merge); - cc.bind(label_else); - { - { - auto label_merge = cc.newLabel(); - auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); - cmp(cc, cond, 0); - cc.je(label_merge); - { - InvokeNode* call_sew_3759; - x86::Gp ret_val_sew_3759 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3759, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_w_3758; - auto fp_vector_unary_w_3758_arg2 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_w_3758_arg3 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_w_3758_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_w_3758_arg8 = rm; - auto fp_vector_unary_w_3758_arg9 = ret_val_sew_3759; - auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_w_3758, &fp_vector_unary_w, FuncSignature::build()); - setArg(call_sew_3759, 0, reinterpret_cast(this)); - setRet(call_sew_3759, 0, ret_val_sew_3759); - setArg(call_fp_vector_unary_w_3758, 0, V); - setArg(call_fp_vector_unary_w_3758, 1, 8); - setArg(call_fp_vector_unary_w_3758, 2, fp_vector_unary_w_3758_arg2); - setArg(call_fp_vector_unary_w_3758, 3, fp_vector_unary_w_3758_arg3); - setArg(call_fp_vector_unary_w_3758, 4, fp_vector_unary_w_3758_arg4); - setArg(call_fp_vector_unary_w_3758, 5, vm); - setArg(call_fp_vector_unary_w_3758, 6, vd); - setArg(call_fp_vector_unary_w_3758, 7, vs2); - setArg(call_fp_vector_unary_w_3758, 8, fp_vector_unary_w_3758_arg8); - setArg(call_fp_vector_unary_w_3758, 9, fp_vector_unary_w_3758_arg9); - } - cc.bind(label_merge); - } - auto tmp3760 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3760, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3760, 64, false) - , traits::vstart); - } - cc.bind(label_merge); - } - auto returnValue = CONT; - - gen_sync(jh, POST_SYNC, 812); - gen_instr_epilogue(jh); - return returnValue; - } - - /* instruction 813: VFWCVT__X__F__V */ - continuation_e __vfwcvt__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ - uint64_t PC = pc.val; - uint8_t vd = ((bit_sub<7,5>(instr))); - uint8_t vs2 = ((bit_sub<20,5>(instr))); - uint8_t vm = ((bit_sub<25,1>(instr))); - if(this->disass_enabled){ - /* generate disass */ - - auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.x.f.v"), - fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); - InvokeNode* call_print_disass; - char* mnemonic_ptr = strdup(mnemonic.c_str()); - jh.disass_collection.push_back(mnemonic_ptr); - jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); - call_print_disass->setArg(0, jh.arch_if_ptr); - call_print_disass->setArg(1, pc.val); - call_print_disass->setArg(2, mnemonic_ptr); - - } - x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__X__F__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 813); - mov(cc, jh.pc, pc.val); - gen_set_tval(jh, instr); - pc = pc+4; - mov(cc, jh.next_pc, pc.val); - cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); - - gen_instr_prologue(jh); - /*generate behavior*/ - InvokeNode* call_get_sew_pow_3761; - x86::Gp ret_val_get_sew_pow_3761 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_get_sew_pow_3761, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); - auto tmp3762 = get_reg(cc, 8, false); - mov(cc, tmp3762, 1); - auto SEW = gen_operation(cc, band, gen_ext(cc, - (gen_operation(cc, shl, tmp3762, (ret_val_get_sew_pow_3761))), 8, false), ~ 1); - setArg(call_get_sew_pow_3761, 0, reinterpret_cast(this)); - setRet(call_get_sew_pow_3761, 0, ret_val_get_sew_pow_3761); - InvokeNode* call_get_lmul_pow_3763; - x86::Gp ret_val_get_lmul_pow_3763 = get_reg_Gp(cc, 8, true); - cc.invoke(&call_get_lmul_pow_3763, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); - auto LMUL_pow = ret_val_get_lmul_pow_3763; - setArg(call_get_lmul_pow_3763, 0, reinterpret_cast(this)); - setRet(call_get_lmul_pow_3763, 0, ret_val_get_lmul_pow_3763); - auto SEW_widen = gen_ext(cc, - (gen_operation(cc, umul, SEW, 2)), 8, false); - auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); - { - auto label_merge = cc.newLabel(); - InvokeNode* call_illegal_fp_variable_width_3764; - auto illegal_fp_variable_width_3764_arg2 = SEW; - auto illegal_fp_variable_width_3764_arg3 = rm; - auto illegal_fp_variable_width_3764_arg4 = SEW_widen; - auto illegal_fp_variable_width_3764_arg5 = LMUL_pow_widen; - x86::Gp ret_val_illegal_fp_variable_width_3764 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_illegal_fp_variable_width_3764, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); - InvokeNode* call_valid_reg_overlap_3765; - auto valid_reg_overlap_3765_arg2 = LMUL_pow; - auto valid_reg_overlap_3765_arg3 = LMUL_pow_widen; - x86::Gp ret_val_valid_reg_overlap_3765 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_valid_reg_overlap_3765, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); - auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3764, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3765)); - setArg(call_illegal_fp_variable_width_3764, 0, reinterpret_cast(this)); - setArg(call_illegal_fp_variable_width_3764, 1, vd); - setArg(call_illegal_fp_variable_width_3764, 2, vm); - setArg(call_illegal_fp_variable_width_3764, 3, illegal_fp_variable_width_3764_arg2); - setArg(call_illegal_fp_variable_width_3764, 4, illegal_fp_variable_width_3764_arg3); - setArg(call_illegal_fp_variable_width_3764, 5, illegal_fp_variable_width_3764_arg4); - setArg(call_illegal_fp_variable_width_3764, 6, illegal_fp_variable_width_3764_arg5); - setRet(call_illegal_fp_variable_width_3764, 0, ret_val_illegal_fp_variable_width_3764); - setArg(call_valid_reg_overlap_3765, 0, reinterpret_cast(this)); - setArg(call_valid_reg_overlap_3765, 1, vs2); - setArg(call_valid_reg_overlap_3765, 2, vd); - setArg(call_valid_reg_overlap_3765, 3, valid_reg_overlap_3765_arg2); - setArg(call_valid_reg_overlap_3765, 4, valid_reg_overlap_3765_arg3); - setRet(call_valid_reg_overlap_3765, 0, ret_val_valid_reg_overlap_3765); - cmp(cc, cond, 0); - auto label_else = cc.newLabel(); - cc.je(label_else); - { - gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); - } - cc.jmp(label_merge); - cc.bind(label_else); - { - { - auto label_merge = cc.newLabel(); - auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); - cmp(cc, cond, 0); - cc.je(label_merge); - { - InvokeNode* call_sew_3767; - x86::Gp ret_val_sew_3767 = get_reg_Gp(cc, 8, false); - cc.invoke(&call_sew_3767, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_w_3766; - auto fp_vector_unary_w_3766_arg2 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_w_3766_arg3 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_w_3766_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_w_3766_arg8 = rm; - auto fp_vector_unary_w_3766_arg9 = ret_val_sew_3767; - auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_w_3766, &fp_vector_unary_w, FuncSignature::build()); - setArg(call_sew_3767, 0, reinterpret_cast(this)); - setRet(call_sew_3767, 0, ret_val_sew_3767); - setArg(call_fp_vector_unary_w_3766, 0, V); - setArg(call_fp_vector_unary_w_3766, 1, 9); - setArg(call_fp_vector_unary_w_3766, 2, fp_vector_unary_w_3766_arg2); - setArg(call_fp_vector_unary_w_3766, 3, fp_vector_unary_w_3766_arg3); - setArg(call_fp_vector_unary_w_3766, 4, fp_vector_unary_w_3766_arg4); - setArg(call_fp_vector_unary_w_3766, 5, vm); - setArg(call_fp_vector_unary_w_3766, 6, vd); - setArg(call_fp_vector_unary_w_3766, 7, vs2); - setArg(call_fp_vector_unary_w_3766, 8, fp_vector_unary_w_3766_arg8); - setArg(call_fp_vector_unary_w_3766, 9, fp_vector_unary_w_3766_arg9); - } - cc.bind(label_merge); - } - auto tmp3768 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3768, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3768, 64, false) - , traits::vstart); - } - cc.bind(label_merge); - } - auto returnValue = CONT; - - gen_sync(jh, POST_SYNC, 813); - gen_instr_epilogue(jh); - return returnValue; - } - - /* instruction 814: VFWCVT__RTZ__XU__F__V */ - continuation_e __vfwcvt__rtz__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ - uint64_t PC = pc.val; - uint8_t vd = ((bit_sub<7,5>(instr))); - uint8_t vs2 = ((bit_sub<20,5>(instr))); - uint8_t vm = ((bit_sub<25,1>(instr))); - if(this->disass_enabled){ - /* generate disass */ - - auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.xu.f.v"), - fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); - InvokeNode* call_print_disass; - char* mnemonic_ptr = strdup(mnemonic.c_str()); - jh.disass_collection.push_back(mnemonic_ptr); - jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); - call_print_disass->setArg(0, jh.arch_if_ptr); - call_print_disass->setArg(1, pc.val); - call_print_disass->setArg(2, mnemonic_ptr); - - } - x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__RTZ__XU__F__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 814); - mov(cc, jh.pc, pc.val); - gen_set_tval(jh, instr); - pc = pc+4; - mov(cc, jh.next_pc, pc.val); - cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); - gen_instr_prologue(jh); /*generate behavior*/ InvokeNode* call_get_sew_pow_3769; @@ -86786,11 +85958,12 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = 1; + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3772; auto illegal_fp_variable_width_3772_arg2 = SEW; + auto illegal_fp_variable_width_3772_arg3 = rm; auto illegal_fp_variable_width_3772_arg4 = SEW_widen; auto illegal_fp_variable_width_3772_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3772 = get_reg_Gp(cc, 8, false); @@ -86805,7 +85978,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3772, 1, vd); setArg(call_illegal_fp_variable_width_3772, 2, vm); setArg(call_illegal_fp_variable_width_3772, 3, illegal_fp_variable_width_3772_arg2); - setArg(call_illegal_fp_variable_width_3772, 4, rm); + setArg(call_illegal_fp_variable_width_3772, 4, illegal_fp_variable_width_3772_arg3); setArg(call_illegal_fp_variable_width_3772, 5, illegal_fp_variable_width_3772_arg4); setArg(call_illegal_fp_variable_width_3772, 6, illegal_fp_variable_width_3772_arg5); setRet(call_illegal_fp_variable_width_3772, 0, ret_val_illegal_fp_variable_width_3772); @@ -86837,41 +86010,40 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_w_3774_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_w_3774_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_w_3774_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3774_arg8 = rm; auto fp_vector_unary_w_3774_arg9 = ret_val_sew_3775; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); cc.invoke(&call_fp_vector_unary_w_3774, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3775, 0, reinterpret_cast(this)); setRet(call_sew_3775, 0, ret_val_sew_3775); setArg(call_fp_vector_unary_w_3774, 0, V); - setArg(call_fp_vector_unary_w_3774, 1, 14); + setArg(call_fp_vector_unary_w_3774, 1, 8); setArg(call_fp_vector_unary_w_3774, 2, fp_vector_unary_w_3774_arg2); setArg(call_fp_vector_unary_w_3774, 3, fp_vector_unary_w_3774_arg3); setArg(call_fp_vector_unary_w_3774, 4, fp_vector_unary_w_3774_arg4); setArg(call_fp_vector_unary_w_3774, 5, vm); setArg(call_fp_vector_unary_w_3774, 6, vd); setArg(call_fp_vector_unary_w_3774, 7, vs2); - setArg(call_fp_vector_unary_w_3774, 8, rm); + setArg(call_fp_vector_unary_w_3774, 8, fp_vector_unary_w_3774_arg8); setArg(call_fp_vector_unary_w_3774, 9, fp_vector_unary_w_3774_arg9); } cc.bind(label_merge); } - auto tmp3776 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3776, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3776, 64, false) - , traits::vstart); + auto tmp3776 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3776, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3776, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 814); + gen_sync(jh, POST_SYNC, 812); gen_instr_epilogue(jh); return returnValue; } - /* instruction 815: VFWCVT__RTZ__X__F__V */ - continuation_e __vfwcvt__rtz__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 813: VFWCVT__X__F__V */ + continuation_e __vfwcvt__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -86880,7 +86052,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.x.f.v"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.x.f.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -86892,8 +86064,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__RTZ__X__F__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 815); + cc.comment(fmt::format("VFWCVT__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 813); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -86920,11 +86092,12 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = 1; + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3780; auto illegal_fp_variable_width_3780_arg2 = SEW; + auto illegal_fp_variable_width_3780_arg3 = rm; auto illegal_fp_variable_width_3780_arg4 = SEW_widen; auto illegal_fp_variable_width_3780_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3780 = get_reg_Gp(cc, 8, false); @@ -86939,7 +86112,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3780, 1, vd); setArg(call_illegal_fp_variable_width_3780, 2, vm); setArg(call_illegal_fp_variable_width_3780, 3, illegal_fp_variable_width_3780_arg2); - setArg(call_illegal_fp_variable_width_3780, 4, rm); + setArg(call_illegal_fp_variable_width_3780, 4, illegal_fp_variable_width_3780_arg3); setArg(call_illegal_fp_variable_width_3780, 5, illegal_fp_variable_width_3780_arg4); setArg(call_illegal_fp_variable_width_3780, 6, illegal_fp_variable_width_3780_arg5); setRet(call_illegal_fp_variable_width_3780, 0, ret_val_illegal_fp_variable_width_3780); @@ -86971,41 +86144,40 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_w_3782_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_w_3782_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_w_3782_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3782_arg8 = rm; auto fp_vector_unary_w_3782_arg9 = ret_val_sew_3783; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); cc.invoke(&call_fp_vector_unary_w_3782, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3783, 0, reinterpret_cast(this)); setRet(call_sew_3783, 0, ret_val_sew_3783); setArg(call_fp_vector_unary_w_3782, 0, V); - setArg(call_fp_vector_unary_w_3782, 1, 15); + setArg(call_fp_vector_unary_w_3782, 1, 9); setArg(call_fp_vector_unary_w_3782, 2, fp_vector_unary_w_3782_arg2); setArg(call_fp_vector_unary_w_3782, 3, fp_vector_unary_w_3782_arg3); setArg(call_fp_vector_unary_w_3782, 4, fp_vector_unary_w_3782_arg4); setArg(call_fp_vector_unary_w_3782, 5, vm); setArg(call_fp_vector_unary_w_3782, 6, vd); setArg(call_fp_vector_unary_w_3782, 7, vs2); - setArg(call_fp_vector_unary_w_3782, 8, rm); + setArg(call_fp_vector_unary_w_3782, 8, fp_vector_unary_w_3782_arg8); setArg(call_fp_vector_unary_w_3782, 9, fp_vector_unary_w_3782_arg9); } cc.bind(label_merge); } - auto tmp3784 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3784, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3784, 64, false) - , traits::vstart); + auto tmp3784 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3784, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3784, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 815); + gen_sync(jh, POST_SYNC, 813); gen_instr_epilogue(jh); return returnValue; } - /* instruction 816: VFWCVT__F__XU__V */ - continuation_e __vfwcvt__f__xu__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 814: VFWCVT__RTZ__XU__F__V */ + continuation_e __vfwcvt__rtz__xu__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -87014,7 +86186,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.xu.v"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.xu.f.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -87026,8 +86198,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__F__XU__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 816); + cc.comment(fmt::format("VFWCVT__RTZ__XU__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 814); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -87054,12 +86226,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = 1; { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3788; auto illegal_fp_variable_width_3788_arg2 = SEW; - auto illegal_fp_variable_width_3788_arg3 = rm; auto illegal_fp_variable_width_3788_arg4 = SEW_widen; auto illegal_fp_variable_width_3788_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3788 = get_reg_Gp(cc, 8, false); @@ -87074,7 +86245,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3788, 1, vd); setArg(call_illegal_fp_variable_width_3788, 2, vm); setArg(call_illegal_fp_variable_width_3788, 3, illegal_fp_variable_width_3788_arg2); - setArg(call_illegal_fp_variable_width_3788, 4, illegal_fp_variable_width_3788_arg3); + setArg(call_illegal_fp_variable_width_3788, 4, rm); setArg(call_illegal_fp_variable_width_3788, 5, illegal_fp_variable_width_3788_arg4); setArg(call_illegal_fp_variable_width_3788, 6, illegal_fp_variable_width_3788_arg5); setRet(call_illegal_fp_variable_width_3788, 0, ret_val_illegal_fp_variable_width_3788); @@ -87106,42 +86277,39 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_w_3790_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_w_3790_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_w_3790_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_w_3790_arg8 = rm; auto fp_vector_unary_w_3790_arg9 = ret_val_sew_3791; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); cc.invoke(&call_fp_vector_unary_w_3790, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3791, 0, reinterpret_cast(this)); setRet(call_sew_3791, 0, ret_val_sew_3791); setArg(call_fp_vector_unary_w_3790, 0, V); - setArg(call_fp_vector_unary_w_3790, 1, 10); + setArg(call_fp_vector_unary_w_3790, 1, 14); setArg(call_fp_vector_unary_w_3790, 2, fp_vector_unary_w_3790_arg2); setArg(call_fp_vector_unary_w_3790, 3, fp_vector_unary_w_3790_arg3); setArg(call_fp_vector_unary_w_3790, 4, fp_vector_unary_w_3790_arg4); setArg(call_fp_vector_unary_w_3790, 5, vm); setArg(call_fp_vector_unary_w_3790, 6, vd); setArg(call_fp_vector_unary_w_3790, 7, vs2); - setArg(call_fp_vector_unary_w_3790, 8, fp_vector_unary_w_3790_arg8); + setArg(call_fp_vector_unary_w_3790, 8, rm); setArg(call_fp_vector_unary_w_3790, 9, fp_vector_unary_w_3790_arg9); } cc.bind(label_merge); } - auto tmp3792 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3792, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3792, 64, false) - , traits::vstart); + auto tmp3792 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3792, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3792, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 816); + gen_sync(jh, POST_SYNC, 814); gen_instr_epilogue(jh); return returnValue; } - /* instruction 817: VFWCVT__F__X__V */ - continuation_e __vfwcvt__f__x__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 815: VFWCVT__RTZ__X__F__V */ + continuation_e __vfwcvt__rtz__x__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -87150,7 +86318,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.x.v"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.rtz.x.f.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -87162,8 +86330,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__F__X__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 817); + cc.comment(fmt::format("VFWCVT__RTZ__X__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 815); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -87190,12 +86358,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = 1; { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3796; auto illegal_fp_variable_width_3796_arg2 = SEW; - auto illegal_fp_variable_width_3796_arg3 = rm; auto illegal_fp_variable_width_3796_arg4 = SEW_widen; auto illegal_fp_variable_width_3796_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3796 = get_reg_Gp(cc, 8, false); @@ -87210,7 +86377,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3796, 1, vd); setArg(call_illegal_fp_variable_width_3796, 2, vm); setArg(call_illegal_fp_variable_width_3796, 3, illegal_fp_variable_width_3796_arg2); - setArg(call_illegal_fp_variable_width_3796, 4, illegal_fp_variable_width_3796_arg3); + setArg(call_illegal_fp_variable_width_3796, 4, rm); setArg(call_illegal_fp_variable_width_3796, 5, illegal_fp_variable_width_3796_arg4); setArg(call_illegal_fp_variable_width_3796, 6, illegal_fp_variable_width_3796_arg5); setRet(call_illegal_fp_variable_width_3796, 0, ret_val_illegal_fp_variable_width_3796); @@ -87242,42 +86409,39 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_w_3798_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_w_3798_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_w_3798_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_w_3798_arg8 = rm; auto fp_vector_unary_w_3798_arg9 = ret_val_sew_3799; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); cc.invoke(&call_fp_vector_unary_w_3798, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3799, 0, reinterpret_cast(this)); setRet(call_sew_3799, 0, ret_val_sew_3799); setArg(call_fp_vector_unary_w_3798, 0, V); - setArg(call_fp_vector_unary_w_3798, 1, 11); + setArg(call_fp_vector_unary_w_3798, 1, 15); setArg(call_fp_vector_unary_w_3798, 2, fp_vector_unary_w_3798_arg2); setArg(call_fp_vector_unary_w_3798, 3, fp_vector_unary_w_3798_arg3); setArg(call_fp_vector_unary_w_3798, 4, fp_vector_unary_w_3798_arg4); setArg(call_fp_vector_unary_w_3798, 5, vm); setArg(call_fp_vector_unary_w_3798, 6, vd); setArg(call_fp_vector_unary_w_3798, 7, vs2); - setArg(call_fp_vector_unary_w_3798, 8, fp_vector_unary_w_3798_arg8); + setArg(call_fp_vector_unary_w_3798, 8, rm); setArg(call_fp_vector_unary_w_3798, 9, fp_vector_unary_w_3798_arg9); } cc.bind(label_merge); } - auto tmp3800 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3800, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3800, 64, false) - , traits::vstart); + auto tmp3800 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3800, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3800, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 817); + gen_sync(jh, POST_SYNC, 815); gen_instr_epilogue(jh); return returnValue; } - /* instruction 818: VFWCVT__F__F__V */ - continuation_e __vfwcvt__f__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 816: VFWCVT__F__XU__V */ + continuation_e __vfwcvt__f__xu__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -87286,7 +86450,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.f.v"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.xu.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -87298,8 +86462,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFWCVT__F__F__V_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 818); + cc.comment(fmt::format("VFWCVT__F__XU__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 816); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -87385,7 +86549,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_sew_3807, 0, reinterpret_cast(this)); setRet(call_sew_3807, 0, ret_val_sew_3807); setArg(call_fp_vector_unary_w_3806, 0, V); - setArg(call_fp_vector_unary_w_3806, 1, 12); + setArg(call_fp_vector_unary_w_3806, 1, 10); setArg(call_fp_vector_unary_w_3806, 2, fp_vector_unary_w_3806_arg2); setArg(call_fp_vector_unary_w_3806, 3, fp_vector_unary_w_3806_arg3); setArg(call_fp_vector_unary_w_3806, 4, fp_vector_unary_w_3806_arg4); @@ -87397,23 +86561,21 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp3808 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3808, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3808, 64, false) - , traits::vstart); + auto tmp3808 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3808, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3808, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 818); + gen_sync(jh, POST_SYNC, 816); gen_instr_epilogue(jh); return returnValue; } - /* instruction 819: VFNCVT__X__F__W */ - continuation_e __vfncvt__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 817: VFWCVT__F__X__V */ + continuation_e __vfwcvt__f__x__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -87422,7 +86584,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.x.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.x.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -87434,8 +86596,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__X__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 819); + cc.comment(fmt::format("VFWCVT__F__X__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 817); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -87473,8 +86635,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_illegal_fp_variable_width_3812 = get_reg_Gp(cc, 8, false); cc.invoke(&call_illegal_fp_variable_width_3812, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); InvokeNode* call_valid_reg_overlap_3813; - auto valid_reg_overlap_3813_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_3813_arg3 = LMUL_pow; + auto valid_reg_overlap_3813_arg2 = LMUL_pow; + auto valid_reg_overlap_3813_arg3 = LMUL_pow_widen; x86::Gp ret_val_valid_reg_overlap_3813 = get_reg_Gp(cc, 8, false); cc.invoke(&call_valid_reg_overlap_3813, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3812, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3813)); @@ -87510,46 +86672,44 @@ template class vm_impl : public iss::asmjit::vm_base { InvokeNode* call_sew_3815; x86::Gp ret_val_sew_3815 = get_reg_Gp(cc, 8, false); cc.invoke(&call_sew_3815, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_n_3814; - auto fp_vector_unary_n_3814_arg2 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_n_3814_arg3 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_n_3814_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_n_3814_arg8 = rm; - auto fp_vector_unary_n_3814_arg9 = ret_val_sew_3815; + InvokeNode* call_fp_vector_unary_w_3814; + auto fp_vector_unary_w_3814_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3814_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3814_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3814_arg8 = rm; + auto fp_vector_unary_w_3814_arg9 = ret_val_sew_3815; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_n_3814, &fp_vector_unary_n, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_w_3814, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3815, 0, reinterpret_cast(this)); setRet(call_sew_3815, 0, ret_val_sew_3815); - setArg(call_fp_vector_unary_n_3814, 0, V); - setArg(call_fp_vector_unary_n_3814, 1, 17); - setArg(call_fp_vector_unary_n_3814, 2, fp_vector_unary_n_3814_arg2); - setArg(call_fp_vector_unary_n_3814, 3, fp_vector_unary_n_3814_arg3); - setArg(call_fp_vector_unary_n_3814, 4, fp_vector_unary_n_3814_arg4); - setArg(call_fp_vector_unary_n_3814, 5, vm); - setArg(call_fp_vector_unary_n_3814, 6, vd); - setArg(call_fp_vector_unary_n_3814, 7, vs2); - setArg(call_fp_vector_unary_n_3814, 8, fp_vector_unary_n_3814_arg8); - setArg(call_fp_vector_unary_n_3814, 9, fp_vector_unary_n_3814_arg9); + setArg(call_fp_vector_unary_w_3814, 0, V); + setArg(call_fp_vector_unary_w_3814, 1, 11); + setArg(call_fp_vector_unary_w_3814, 2, fp_vector_unary_w_3814_arg2); + setArg(call_fp_vector_unary_w_3814, 3, fp_vector_unary_w_3814_arg3); + setArg(call_fp_vector_unary_w_3814, 4, fp_vector_unary_w_3814_arg4); + setArg(call_fp_vector_unary_w_3814, 5, vm); + setArg(call_fp_vector_unary_w_3814, 6, vd); + setArg(call_fp_vector_unary_w_3814, 7, vs2); + setArg(call_fp_vector_unary_w_3814, 8, fp_vector_unary_w_3814_arg8); + setArg(call_fp_vector_unary_w_3814, 9, fp_vector_unary_w_3814_arg9); } cc.bind(label_merge); } - auto tmp3816 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3816, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3816, 64, false) - , traits::vstart); + auto tmp3816 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3816, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3816, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 819); + gen_sync(jh, POST_SYNC, 817); gen_instr_epilogue(jh); return returnValue; } - /* instruction 820: VFNCVT__XU__F__W */ - continuation_e __vfncvt__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 818: VFWCVT__F__F__V */ + continuation_e __vfwcvt__f__f__v(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -87558,7 +86718,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.xu.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfwcvt.f.f.v"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -87570,8 +86730,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__XU__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 820); + cc.comment(fmt::format("VFWCVT__F__F__V_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 818); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -87609,8 +86769,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_illegal_fp_variable_width_3820 = get_reg_Gp(cc, 8, false); cc.invoke(&call_illegal_fp_variable_width_3820, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); InvokeNode* call_valid_reg_overlap_3821; - auto valid_reg_overlap_3821_arg2 = LMUL_pow_widen; - auto valid_reg_overlap_3821_arg3 = LMUL_pow; + auto valid_reg_overlap_3821_arg2 = LMUL_pow; + auto valid_reg_overlap_3821_arg3 = LMUL_pow_widen; x86::Gp ret_val_valid_reg_overlap_3821 = get_reg_Gp(cc, 8, false); cc.invoke(&call_valid_reg_overlap_3821, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3820, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3821)); @@ -87646,46 +86806,44 @@ template class vm_impl : public iss::asmjit::vm_base { InvokeNode* call_sew_3823; x86::Gp ret_val_sew_3823 = get_reg_Gp(cc, 8, false); cc.invoke(&call_sew_3823, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); - InvokeNode* call_fp_vector_unary_n_3822; - auto fp_vector_unary_n_3822_arg2 = load_reg_from_mem(jh, traits::vl); - auto fp_vector_unary_n_3822_arg3 = load_reg_from_mem(jh, traits::vstart); - auto fp_vector_unary_n_3822_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_n_3822_arg8 = rm; - auto fp_vector_unary_n_3822_arg9 = ret_val_sew_3823; + InvokeNode* call_fp_vector_unary_w_3822; + auto fp_vector_unary_w_3822_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_w_3822_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_w_3822_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_w_3822_arg8 = rm; + auto fp_vector_unary_w_3822_arg9 = ret_val_sew_3823; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); - cc.invoke(&call_fp_vector_unary_n_3822, &fp_vector_unary_n, FuncSignature::build()); + cc.invoke(&call_fp_vector_unary_w_3822, &fp_vector_unary_w, FuncSignature::build()); setArg(call_sew_3823, 0, reinterpret_cast(this)); setRet(call_sew_3823, 0, ret_val_sew_3823); - setArg(call_fp_vector_unary_n_3822, 0, V); - setArg(call_fp_vector_unary_n_3822, 1, 16); - setArg(call_fp_vector_unary_n_3822, 2, fp_vector_unary_n_3822_arg2); - setArg(call_fp_vector_unary_n_3822, 3, fp_vector_unary_n_3822_arg3); - setArg(call_fp_vector_unary_n_3822, 4, fp_vector_unary_n_3822_arg4); - setArg(call_fp_vector_unary_n_3822, 5, vm); - setArg(call_fp_vector_unary_n_3822, 6, vd); - setArg(call_fp_vector_unary_n_3822, 7, vs2); - setArg(call_fp_vector_unary_n_3822, 8, fp_vector_unary_n_3822_arg8); - setArg(call_fp_vector_unary_n_3822, 9, fp_vector_unary_n_3822_arg9); + setArg(call_fp_vector_unary_w_3822, 0, V); + setArg(call_fp_vector_unary_w_3822, 1, 12); + setArg(call_fp_vector_unary_w_3822, 2, fp_vector_unary_w_3822_arg2); + setArg(call_fp_vector_unary_w_3822, 3, fp_vector_unary_w_3822_arg3); + setArg(call_fp_vector_unary_w_3822, 4, fp_vector_unary_w_3822_arg4); + setArg(call_fp_vector_unary_w_3822, 5, vm); + setArg(call_fp_vector_unary_w_3822, 6, vd); + setArg(call_fp_vector_unary_w_3822, 7, vs2); + setArg(call_fp_vector_unary_w_3822, 8, fp_vector_unary_w_3822_arg8); + setArg(call_fp_vector_unary_w_3822, 9, fp_vector_unary_w_3822_arg9); } cc.bind(label_merge); } - auto tmp3824 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3824, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3824, 64, false) - , traits::vstart); + auto tmp3824 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3824, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3824, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 820); + gen_sync(jh, POST_SYNC, 818); gen_instr_epilogue(jh); return returnValue; } - /* instruction 821: VFNCVT__RTZ__XU__F__W */ - continuation_e __vfncvt__rtz__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 819: VFNCVT__X__F__W */ + continuation_e __vfncvt__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -87694,7 +86852,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.xu.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.x.f.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -87706,8 +86864,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__RTZ__XU__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 821); + cc.comment(fmt::format("VFNCVT__X__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 819); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -87734,11 +86892,12 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = 1; + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3828; auto illegal_fp_variable_width_3828_arg2 = SEW; + auto illegal_fp_variable_width_3828_arg3 = rm; auto illegal_fp_variable_width_3828_arg4 = SEW_widen; auto illegal_fp_variable_width_3828_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3828 = get_reg_Gp(cc, 8, false); @@ -87753,7 +86912,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3828, 1, vd); setArg(call_illegal_fp_variable_width_3828, 2, vm); setArg(call_illegal_fp_variable_width_3828, 3, illegal_fp_variable_width_3828_arg2); - setArg(call_illegal_fp_variable_width_3828, 4, rm); + setArg(call_illegal_fp_variable_width_3828, 4, illegal_fp_variable_width_3828_arg3); setArg(call_illegal_fp_variable_width_3828, 5, illegal_fp_variable_width_3828_arg4); setArg(call_illegal_fp_variable_width_3828, 6, illegal_fp_variable_width_3828_arg5); setRet(call_illegal_fp_variable_width_3828, 0, ret_val_illegal_fp_variable_width_3828); @@ -87785,41 +86944,40 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3830_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_n_3830_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_n_3830_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3830_arg8 = rm; auto fp_vector_unary_n_3830_arg9 = ret_val_sew_3831; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); cc.invoke(&call_fp_vector_unary_n_3830, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3831, 0, reinterpret_cast(this)); setRet(call_sew_3831, 0, ret_val_sew_3831); setArg(call_fp_vector_unary_n_3830, 0, V); - setArg(call_fp_vector_unary_n_3830, 1, 22); + setArg(call_fp_vector_unary_n_3830, 1, 17); setArg(call_fp_vector_unary_n_3830, 2, fp_vector_unary_n_3830_arg2); setArg(call_fp_vector_unary_n_3830, 3, fp_vector_unary_n_3830_arg3); setArg(call_fp_vector_unary_n_3830, 4, fp_vector_unary_n_3830_arg4); setArg(call_fp_vector_unary_n_3830, 5, vm); setArg(call_fp_vector_unary_n_3830, 6, vd); setArg(call_fp_vector_unary_n_3830, 7, vs2); - setArg(call_fp_vector_unary_n_3830, 8, rm); + setArg(call_fp_vector_unary_n_3830, 8, fp_vector_unary_n_3830_arg8); setArg(call_fp_vector_unary_n_3830, 9, fp_vector_unary_n_3830_arg9); } cc.bind(label_merge); } - auto tmp3832 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3832, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3832, 64, false) - , traits::vstart); + auto tmp3832 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3832, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3832, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 821); + gen_sync(jh, POST_SYNC, 819); gen_instr_epilogue(jh); return returnValue; } - /* instruction 822: VFNCVT__RTZ__X__F__W */ - continuation_e __vfncvt__rtz__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 820: VFNCVT__XU__F__W */ + continuation_e __vfncvt__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -87828,7 +86986,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.x.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.xu.f.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -87840,8 +86998,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__RTZ__X__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 822); + cc.comment(fmt::format("VFNCVT__XU__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 820); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -87868,11 +87026,12 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = 1; + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3836; auto illegal_fp_variable_width_3836_arg2 = SEW; + auto illegal_fp_variable_width_3836_arg3 = rm; auto illegal_fp_variable_width_3836_arg4 = SEW_widen; auto illegal_fp_variable_width_3836_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3836 = get_reg_Gp(cc, 8, false); @@ -87887,7 +87046,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3836, 1, vd); setArg(call_illegal_fp_variable_width_3836, 2, vm); setArg(call_illegal_fp_variable_width_3836, 3, illegal_fp_variable_width_3836_arg2); - setArg(call_illegal_fp_variable_width_3836, 4, rm); + setArg(call_illegal_fp_variable_width_3836, 4, illegal_fp_variable_width_3836_arg3); setArg(call_illegal_fp_variable_width_3836, 5, illegal_fp_variable_width_3836_arg4); setArg(call_illegal_fp_variable_width_3836, 6, illegal_fp_variable_width_3836_arg5); setRet(call_illegal_fp_variable_width_3836, 0, ret_val_illegal_fp_variable_width_3836); @@ -87919,41 +87078,40 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3838_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_n_3838_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_n_3838_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3838_arg8 = rm; auto fp_vector_unary_n_3838_arg9 = ret_val_sew_3839; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); cc.invoke(&call_fp_vector_unary_n_3838, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3839, 0, reinterpret_cast(this)); setRet(call_sew_3839, 0, ret_val_sew_3839); setArg(call_fp_vector_unary_n_3838, 0, V); - setArg(call_fp_vector_unary_n_3838, 1, 23); + setArg(call_fp_vector_unary_n_3838, 1, 16); setArg(call_fp_vector_unary_n_3838, 2, fp_vector_unary_n_3838_arg2); setArg(call_fp_vector_unary_n_3838, 3, fp_vector_unary_n_3838_arg3); setArg(call_fp_vector_unary_n_3838, 4, fp_vector_unary_n_3838_arg4); setArg(call_fp_vector_unary_n_3838, 5, vm); setArg(call_fp_vector_unary_n_3838, 6, vd); setArg(call_fp_vector_unary_n_3838, 7, vs2); - setArg(call_fp_vector_unary_n_3838, 8, rm); + setArg(call_fp_vector_unary_n_3838, 8, fp_vector_unary_n_3838_arg8); setArg(call_fp_vector_unary_n_3838, 9, fp_vector_unary_n_3838_arg9); } cc.bind(label_merge); } - auto tmp3840 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3840, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3840, 64, false) - , traits::vstart); + auto tmp3840 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3840, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3840, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 822); + gen_sync(jh, POST_SYNC, 820); gen_instr_epilogue(jh); return returnValue; } - /* instruction 823: VFNCVT__F__XU__W */ - continuation_e __vfncvt__f__xu__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 821: VFNCVT__RTZ__XU__F__W */ + continuation_e __vfncvt__rtz__xu__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -87962,7 +87120,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.xu.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.xu.f.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -87974,8 +87132,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__F__XU__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 823); + cc.comment(fmt::format("VFNCVT__RTZ__XU__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 821); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -88002,12 +87160,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = 1; { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3844; auto illegal_fp_variable_width_3844_arg2 = SEW; - auto illegal_fp_variable_width_3844_arg3 = rm; auto illegal_fp_variable_width_3844_arg4 = SEW_widen; auto illegal_fp_variable_width_3844_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3844 = get_reg_Gp(cc, 8, false); @@ -88022,7 +87179,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3844, 1, vd); setArg(call_illegal_fp_variable_width_3844, 2, vm); setArg(call_illegal_fp_variable_width_3844, 3, illegal_fp_variable_width_3844_arg2); - setArg(call_illegal_fp_variable_width_3844, 4, illegal_fp_variable_width_3844_arg3); + setArg(call_illegal_fp_variable_width_3844, 4, rm); setArg(call_illegal_fp_variable_width_3844, 5, illegal_fp_variable_width_3844_arg4); setArg(call_illegal_fp_variable_width_3844, 6, illegal_fp_variable_width_3844_arg5); setRet(call_illegal_fp_variable_width_3844, 0, ret_val_illegal_fp_variable_width_3844); @@ -88054,42 +87211,39 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3846_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_n_3846_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_n_3846_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_n_3846_arg8 = rm; auto fp_vector_unary_n_3846_arg9 = ret_val_sew_3847; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); cc.invoke(&call_fp_vector_unary_n_3846, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3847, 0, reinterpret_cast(this)); setRet(call_sew_3847, 0, ret_val_sew_3847); setArg(call_fp_vector_unary_n_3846, 0, V); - setArg(call_fp_vector_unary_n_3846, 1, 18); + setArg(call_fp_vector_unary_n_3846, 1, 22); setArg(call_fp_vector_unary_n_3846, 2, fp_vector_unary_n_3846_arg2); setArg(call_fp_vector_unary_n_3846, 3, fp_vector_unary_n_3846_arg3); setArg(call_fp_vector_unary_n_3846, 4, fp_vector_unary_n_3846_arg4); setArg(call_fp_vector_unary_n_3846, 5, vm); setArg(call_fp_vector_unary_n_3846, 6, vd); setArg(call_fp_vector_unary_n_3846, 7, vs2); - setArg(call_fp_vector_unary_n_3846, 8, fp_vector_unary_n_3846_arg8); + setArg(call_fp_vector_unary_n_3846, 8, rm); setArg(call_fp_vector_unary_n_3846, 9, fp_vector_unary_n_3846_arg9); } cc.bind(label_merge); } - auto tmp3848 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3848, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3848, 64, false) - , traits::vstart); + auto tmp3848 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3848, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3848, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 823); + gen_sync(jh, POST_SYNC, 821); gen_instr_epilogue(jh); return returnValue; } - /* instruction 824: VFNCVT__F__X__W */ - continuation_e __vfncvt__f__x__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 822: VFNCVT__RTZ__X__F__W */ + continuation_e __vfncvt__rtz__x__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -88098,7 +87252,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.x.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rtz.x.f.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -88110,8 +87264,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__F__X__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 824); + cc.comment(fmt::format("VFNCVT__RTZ__X__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 822); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -88138,12 +87292,11 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = 1; { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3852; auto illegal_fp_variable_width_3852_arg2 = SEW; - auto illegal_fp_variable_width_3852_arg3 = rm; auto illegal_fp_variable_width_3852_arg4 = SEW_widen; auto illegal_fp_variable_width_3852_arg5 = LMUL_pow_widen; x86::Gp ret_val_illegal_fp_variable_width_3852 = get_reg_Gp(cc, 8, false); @@ -88158,7 +87311,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_illegal_fp_variable_width_3852, 1, vd); setArg(call_illegal_fp_variable_width_3852, 2, vm); setArg(call_illegal_fp_variable_width_3852, 3, illegal_fp_variable_width_3852_arg2); - setArg(call_illegal_fp_variable_width_3852, 4, illegal_fp_variable_width_3852_arg3); + setArg(call_illegal_fp_variable_width_3852, 4, rm); setArg(call_illegal_fp_variable_width_3852, 5, illegal_fp_variable_width_3852_arg4); setArg(call_illegal_fp_variable_width_3852, 6, illegal_fp_variable_width_3852_arg5); setRet(call_illegal_fp_variable_width_3852, 0, ret_val_illegal_fp_variable_width_3852); @@ -88190,42 +87343,39 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3854_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_n_3854_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_n_3854_arg4 = load_reg_from_mem(jh, traits::vtype); - auto fp_vector_unary_n_3854_arg8 = rm; auto fp_vector_unary_n_3854_arg9 = ret_val_sew_3855; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); cc.invoke(&call_fp_vector_unary_n_3854, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3855, 0, reinterpret_cast(this)); setRet(call_sew_3855, 0, ret_val_sew_3855); setArg(call_fp_vector_unary_n_3854, 0, V); - setArg(call_fp_vector_unary_n_3854, 1, 19); + setArg(call_fp_vector_unary_n_3854, 1, 23); setArg(call_fp_vector_unary_n_3854, 2, fp_vector_unary_n_3854_arg2); setArg(call_fp_vector_unary_n_3854, 3, fp_vector_unary_n_3854_arg3); setArg(call_fp_vector_unary_n_3854, 4, fp_vector_unary_n_3854_arg4); setArg(call_fp_vector_unary_n_3854, 5, vm); setArg(call_fp_vector_unary_n_3854, 6, vd); setArg(call_fp_vector_unary_n_3854, 7, vs2); - setArg(call_fp_vector_unary_n_3854, 8, fp_vector_unary_n_3854_arg8); + setArg(call_fp_vector_unary_n_3854, 8, rm); setArg(call_fp_vector_unary_n_3854, 9, fp_vector_unary_n_3854_arg9); } cc.bind(label_merge); } - auto tmp3856 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3856, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3856, 64, false) - , traits::vstart); + auto tmp3856 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3856, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3856, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 824); + gen_sync(jh, POST_SYNC, 822); gen_instr_epilogue(jh); return returnValue; } - /* instruction 825: VFNCVT__F__F__W */ - continuation_e __vfncvt__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 823: VFNCVT__F__XU__W */ + continuation_e __vfncvt__f__xu__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -88234,7 +87384,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.xu.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -88246,8 +87396,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__F__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 825); + cc.comment(fmt::format("VFNCVT__F__XU__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 823); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -88333,7 +87483,7 @@ template class vm_impl : public iss::asmjit::vm_base { setArg(call_sew_3863, 0, reinterpret_cast(this)); setRet(call_sew_3863, 0, ret_val_sew_3863); setArg(call_fp_vector_unary_n_3862, 0, V); - setArg(call_fp_vector_unary_n_3862, 1, 20); + setArg(call_fp_vector_unary_n_3862, 1, 18); setArg(call_fp_vector_unary_n_3862, 2, fp_vector_unary_n_3862_arg2); setArg(call_fp_vector_unary_n_3862, 3, fp_vector_unary_n_3862_arg3); setArg(call_fp_vector_unary_n_3862, 4, fp_vector_unary_n_3862_arg4); @@ -88345,23 +87495,21 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto tmp3864 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3864, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3864, 64, false) - , traits::vstart); + auto tmp3864 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3864, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3864, traits::vstart); } cc.bind(label_merge); } auto returnValue = CONT; - gen_sync(jh, POST_SYNC, 825); + gen_sync(jh, POST_SYNC, 823); gen_instr_epilogue(jh); return returnValue; } - /* instruction 826: VFNCVT__ROD__F__F__W */ - continuation_e __vfncvt__rod__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + /* instruction 824: VFNCVT__F__X__W */ + continuation_e __vfncvt__f__x__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ uint64_t PC = pc.val; uint8_t vd = ((bit_sub<7,5>(instr))); uint8_t vs2 = ((bit_sub<20,5>(instr))); @@ -88370,7 +87518,7 @@ template class vm_impl : public iss::asmjit::vm_base { /* generate disass */ auto mnemonic = fmt::format( - "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rod.f.f.w"), + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.x.w"), fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); InvokeNode* call_print_disass; char* mnemonic_ptr = strdup(mnemonic.c_str()); @@ -88382,8 +87530,8 @@ template class vm_impl : public iss::asmjit::vm_base { } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("VFNCVT__ROD__F__F__W_{:#x}:",pc.val).c_str()); - gen_sync(jh, PRE_SYNC, 826); + cc.comment(fmt::format("VFNCVT__F__X__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 824); mov(cc, jh.pc, pc.val); gen_set_tval(jh, instr); pc = pc+4; @@ -88462,29 +87610,295 @@ template class vm_impl : public iss::asmjit::vm_base { auto fp_vector_unary_n_3870_arg2 = load_reg_from_mem(jh, traits::vl); auto fp_vector_unary_n_3870_arg3 = load_reg_from_mem(jh, traits::vstart); auto fp_vector_unary_n_3870_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3870_arg8 = rm; auto fp_vector_unary_n_3870_arg9 = ret_val_sew_3871; auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); cc.invoke(&call_fp_vector_unary_n_3870, &fp_vector_unary_n, FuncSignature::build()); setArg(call_sew_3871, 0, reinterpret_cast(this)); setRet(call_sew_3871, 0, ret_val_sew_3871); setArg(call_fp_vector_unary_n_3870, 0, V); - setArg(call_fp_vector_unary_n_3870, 1, 21); + setArg(call_fp_vector_unary_n_3870, 1, 19); setArg(call_fp_vector_unary_n_3870, 2, fp_vector_unary_n_3870_arg2); setArg(call_fp_vector_unary_n_3870, 3, fp_vector_unary_n_3870_arg3); setArg(call_fp_vector_unary_n_3870, 4, fp_vector_unary_n_3870_arg4); setArg(call_fp_vector_unary_n_3870, 5, vm); setArg(call_fp_vector_unary_n_3870, 6, vd); setArg(call_fp_vector_unary_n_3870, 7, vs2); - setArg(call_fp_vector_unary_n_3870, 8, 6); + setArg(call_fp_vector_unary_n_3870, 8, fp_vector_unary_n_3870_arg8); setArg(call_fp_vector_unary_n_3870, 9, fp_vector_unary_n_3870_arg9); } cc.bind(label_merge); } - auto tmp3872 = get_reg_Gp(cc, 8, false); - mov(cc, tmp3872, 0); - write_reg_to_mem(jh, - gen_ext(cc, tmp3872, 64, false) - , traits::vstart); + auto tmp3872 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3872, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3872, traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 824); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 825: VFNCVT__F__F__W */ + continuation_e __vfncvt__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__F__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 825); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3873; + x86::Gp ret_val_get_sew_pow_3873 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3873, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3874 = get_reg(cc, 8, false); + mov(cc, tmp3874, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3874, (ret_val_get_sew_pow_3873))), 8, false), ~ 1); + setArg(call_get_sew_pow_3873, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3873, 0, ret_val_get_sew_pow_3873); + InvokeNode* call_get_lmul_pow_3875; + x86::Gp ret_val_get_lmul_pow_3875 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3875, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3875; + setArg(call_get_lmul_pow_3875, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3875, 0, ret_val_get_lmul_pow_3875); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3876; + auto illegal_fp_variable_width_3876_arg2 = SEW; + auto illegal_fp_variable_width_3876_arg3 = rm; + auto illegal_fp_variable_width_3876_arg4 = SEW_widen; + auto illegal_fp_variable_width_3876_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3876 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3876, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3877; + auto valid_reg_overlap_3877_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3877_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3877 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3877, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3876, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3877)); + setArg(call_illegal_fp_variable_width_3876, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3876, 1, vd); + setArg(call_illegal_fp_variable_width_3876, 2, vm); + setArg(call_illegal_fp_variable_width_3876, 3, illegal_fp_variable_width_3876_arg2); + setArg(call_illegal_fp_variable_width_3876, 4, illegal_fp_variable_width_3876_arg3); + setArg(call_illegal_fp_variable_width_3876, 5, illegal_fp_variable_width_3876_arg4); + setArg(call_illegal_fp_variable_width_3876, 6, illegal_fp_variable_width_3876_arg5); + setRet(call_illegal_fp_variable_width_3876, 0, ret_val_illegal_fp_variable_width_3876); + setArg(call_valid_reg_overlap_3877, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3877, 1, vs2); + setArg(call_valid_reg_overlap_3877, 2, vd); + setArg(call_valid_reg_overlap_3877, 3, valid_reg_overlap_3877_arg2); + setArg(call_valid_reg_overlap_3877, 4, valid_reg_overlap_3877_arg3); + setRet(call_valid_reg_overlap_3877, 0, ret_val_valid_reg_overlap_3877); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3879; + x86::Gp ret_val_sew_3879 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3879, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3878; + auto fp_vector_unary_n_3878_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3878_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3878_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3878_arg8 = rm; + auto fp_vector_unary_n_3878_arg9 = ret_val_sew_3879; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3878, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3879, 0, reinterpret_cast(this)); + setRet(call_sew_3879, 0, ret_val_sew_3879); + setArg(call_fp_vector_unary_n_3878, 0, V); + setArg(call_fp_vector_unary_n_3878, 1, 20); + setArg(call_fp_vector_unary_n_3878, 2, fp_vector_unary_n_3878_arg2); + setArg(call_fp_vector_unary_n_3878, 3, fp_vector_unary_n_3878_arg3); + setArg(call_fp_vector_unary_n_3878, 4, fp_vector_unary_n_3878_arg4); + setArg(call_fp_vector_unary_n_3878, 5, vm); + setArg(call_fp_vector_unary_n_3878, 6, vd); + setArg(call_fp_vector_unary_n_3878, 7, vs2); + setArg(call_fp_vector_unary_n_3878, 8, fp_vector_unary_n_3878_arg8); + setArg(call_fp_vector_unary_n_3878, 9, fp_vector_unary_n_3878_arg9); + } + cc.bind(label_merge); + } + auto tmp3880 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3880, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3880, traits::vstart); + } + cc.bind(label_merge); + } + auto returnValue = CONT; + + gen_sync(jh, POST_SYNC, 825); + gen_instr_epilogue(jh); + return returnValue; + } + + /* instruction 826: VFNCVT__ROD__F__F__W */ + continuation_e __vfncvt__rod__f__f__w(virt_addr_t& pc, code_word_t instr, jit_holder& jh){ + uint64_t PC = pc.val; + uint8_t vd = ((bit_sub<7,5>(instr))); + uint8_t vs2 = ((bit_sub<20,5>(instr))); + uint8_t vm = ((bit_sub<25,1>(instr))); + if(this->disass_enabled){ + /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {vd}, {vs2}, {vm}", fmt::arg("mnemonic", "vfncvt.rod.f.f.w"), + fmt::arg("vd", vname(vd)), fmt::arg("vs2", vname(vs2)), fmt::arg("vm", vm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + + } + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("VFNCVT__ROD__F__F__W_{:#x}:",pc.val).c_str()); + gen_sync(jh, PRE_SYNC, 826); + mov(cc, jh.pc, pc.val); + gen_set_tval(jh, instr); + pc = pc+4; + mov(cc, jh.next_pc, pc.val); + cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr); + + gen_instr_prologue(jh); + /*generate behavior*/ + InvokeNode* call_get_sew_pow_3881; + x86::Gp ret_val_get_sew_pow_3881 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_get_sew_pow_3881, (uintptr_t)&vm_impl::_get_sew_pow, FuncSignature::build()); + auto tmp3882 = get_reg(cc, 8, false); + mov(cc, tmp3882, 1); + auto SEW = gen_operation(cc, band, gen_ext(cc, + (gen_operation(cc, shl, tmp3882, (ret_val_get_sew_pow_3881))), 8, false), ~ 1); + setArg(call_get_sew_pow_3881, 0, reinterpret_cast(this)); + setRet(call_get_sew_pow_3881, 0, ret_val_get_sew_pow_3881); + InvokeNode* call_get_lmul_pow_3883; + x86::Gp ret_val_get_lmul_pow_3883 = get_reg_Gp(cc, 8, true); + cc.invoke(&call_get_lmul_pow_3883, (uintptr_t)&vm_impl::_get_lmul_pow, FuncSignature::build()); + auto LMUL_pow = ret_val_get_lmul_pow_3883; + setArg(call_get_lmul_pow_3883, 0, reinterpret_cast(this)); + setRet(call_get_lmul_pow_3883, 0, ret_val_get_lmul_pow_3883); + auto SEW_widen = gen_ext(cc, + (gen_operation(cc, umul, SEW, 2)), 8, false); + auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + { + auto label_merge = cc.newLabel(); + InvokeNode* call_illegal_fp_variable_width_3884; + auto illegal_fp_variable_width_3884_arg2 = SEW; + auto illegal_fp_variable_width_3884_arg3 = rm; + auto illegal_fp_variable_width_3884_arg4 = SEW_widen; + auto illegal_fp_variable_width_3884_arg5 = LMUL_pow_widen; + x86::Gp ret_val_illegal_fp_variable_width_3884 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_illegal_fp_variable_width_3884, (uintptr_t)&vm_impl::_illegal_fp_variable_width, FuncSignature::build()); + InvokeNode* call_valid_reg_overlap_3885; + auto valid_reg_overlap_3885_arg2 = LMUL_pow_widen; + auto valid_reg_overlap_3885_arg3 = LMUL_pow; + x86::Gp ret_val_valid_reg_overlap_3885 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_valid_reg_overlap_3885, (uintptr_t)&vm_impl::_valid_reg_overlap, FuncSignature::build()); + auto cond = gen_operation(cc, lor, ret_val_illegal_fp_variable_width_3884, gen_operation(cc, lnot, ret_val_valid_reg_overlap_3885)); + setArg(call_illegal_fp_variable_width_3884, 0, reinterpret_cast(this)); + setArg(call_illegal_fp_variable_width_3884, 1, vd); + setArg(call_illegal_fp_variable_width_3884, 2, vm); + setArg(call_illegal_fp_variable_width_3884, 3, illegal_fp_variable_width_3884_arg2); + setArg(call_illegal_fp_variable_width_3884, 4, illegal_fp_variable_width_3884_arg3); + setArg(call_illegal_fp_variable_width_3884, 5, illegal_fp_variable_width_3884_arg4); + setArg(call_illegal_fp_variable_width_3884, 6, illegal_fp_variable_width_3884_arg5); + setRet(call_illegal_fp_variable_width_3884, 0, ret_val_illegal_fp_variable_width_3884); + setArg(call_valid_reg_overlap_3885, 0, reinterpret_cast(this)); + setArg(call_valid_reg_overlap_3885, 1, vs2); + setArg(call_valid_reg_overlap_3885, 2, vd); + setArg(call_valid_reg_overlap_3885, 3, valid_reg_overlap_3885_arg2); + setArg(call_valid_reg_overlap_3885, 4, valid_reg_overlap_3885_arg3); + setRet(call_valid_reg_overlap_3885, 0, ret_val_valid_reg_overlap_3885); + cmp(cc, cond, 0); + auto label_else = cc.newLabel(); + cc.je(label_else); + { + gen_raise(jh, 0, static_cast(traits::RV_CAUSE_ILLEGAL_INSTRUCTION)); + } + cc.jmp(label_merge); + cc.bind(label_else); + { + { + auto label_merge = cc.newLabel(); + auto cond = gen_operation(cc, gtu, load_reg_from_mem(jh, traits::vl), load_reg_from_mem(jh, traits::vstart)); + cmp(cc, cond, 0); + cc.je(label_merge); + { + InvokeNode* call_sew_3887; + x86::Gp ret_val_sew_3887 = get_reg_Gp(cc, 8, false); + cc.invoke(&call_sew_3887, (uintptr_t)&vm_impl::_sew, FuncSignature::build()); + InvokeNode* call_fp_vector_unary_n_3886; + auto fp_vector_unary_n_3886_arg2 = load_reg_from_mem(jh, traits::vl); + auto fp_vector_unary_n_3886_arg3 = load_reg_from_mem(jh, traits::vstart); + auto fp_vector_unary_n_3886_arg4 = load_reg_from_mem(jh, traits::vtype); + auto fp_vector_unary_n_3886_arg9 = ret_val_sew_3887; + auto V = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::V0]); + cc.invoke(&call_fp_vector_unary_n_3886, &fp_vector_unary_n, FuncSignature::build()); + setArg(call_sew_3887, 0, reinterpret_cast(this)); + setRet(call_sew_3887, 0, ret_val_sew_3887); + setArg(call_fp_vector_unary_n_3886, 0, V); + setArg(call_fp_vector_unary_n_3886, 1, 21); + setArg(call_fp_vector_unary_n_3886, 2, fp_vector_unary_n_3886_arg2); + setArg(call_fp_vector_unary_n_3886, 3, fp_vector_unary_n_3886_arg3); + setArg(call_fp_vector_unary_n_3886, 4, fp_vector_unary_n_3886_arg4); + setArg(call_fp_vector_unary_n_3886, 5, vm); + setArg(call_fp_vector_unary_n_3886, 6, vd); + setArg(call_fp_vector_unary_n_3886, 7, vs2); + setArg(call_fp_vector_unary_n_3886, 8, 6); + setArg(call_fp_vector_unary_n_3886, 9, fp_vector_unary_n_3886_arg9); + } + cc.bind(label_merge); + } + auto tmp3888 = get_reg_Gp(cc, 64, false); + mov(cc, tmp3888, gen_ext(cc, 0, 64, false)); + write_reg_to_mem(jh, tmp3888, traits::vstart); } cc.bind(label_merge); } @@ -88633,7 +88047,6 @@ inline void vm_impl::gen_lower(jit_holder& jh) { auto tmp1 = get_reg_for(cc, traits::TRAP_STATE); mov(cc, tmp1, 0); mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1); - cc.jmp(jh.trap_entry); } template template diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp index 3e6fbaa..660fa8a 100644 --- a/src/vm/interp/vm_rv32gcv.cpp +++ b/src/vm/interp/vm_rv32gcv.cpp @@ -40,9 +40,6 @@ #include -#define CUR_VLEN 256 -#define CUR_XLEN 32 -#include #include #include @@ -65,6 +62,7 @@ namespace iss { namespace interp { namespace rv32gcv { + using namespace iss::arch; using namespace iss::debugger; using namespace std::placeholders; @@ -84,7 +82,73 @@ template class vm_impl : public iss::interp::vm_base { using reg_t = typename traits::reg_t; using mem_type_e = typename traits::mem_type_e; using opcode_e = typename traits::opcode_e; - + + + static constexpr auto& vlseg = trampoline::vlseg; + static constexpr auto& vsseg = trampoline::vsseg; + static constexpr auto& vlsseg = trampoline::vlsseg; + static constexpr auto& vssseg = trampoline::vssseg; + static constexpr auto& vlxseg = trampoline::vlxseg; + static constexpr auto& vsxseg = trampoline::vsxseg; + static constexpr auto& vector_vector_op = trampoline::vector_vector_op; + static constexpr auto& vector_imm_op = trampoline::vector_imm_op; + static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; + static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; + static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; + static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; + static constexpr auto& vector_extend = trampoline::vector_extend; + static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; + static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; + static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; + static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; + static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; + static constexpr auto& vector_red_op = trampoline::vector_red_op; + static constexpr auto& vector_red_wv = trampoline::vector_red_wv; + static constexpr auto& mask_mask_op = trampoline::mask_mask_op; + static constexpr auto& vcpop = trampoline::vcpop; + static constexpr auto& vfirst = trampoline::vfirst; + static constexpr auto& mask_set_op = trampoline::mask_set_op; + static constexpr auto& viota = trampoline::viota; + static constexpr auto& vid = trampoline::vid; + static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; + static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; + static constexpr auto& vector_slideup = trampoline::vector_slideup; + static constexpr auto& vector_slidedown = trampoline::vector_slidedown; + static constexpr auto& vector_slide1up = trampoline::vector_slide1up; + static constexpr auto& vector_slide1down = trampoline::vector_slide1down; + static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; + static constexpr auto& vector_compress = trampoline::vector_compress; + static constexpr auto& vector_whole_move = trampoline::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; + static constexpr auto& vector_unary_op = trampoline::vector_unary_op; + vm_impl(); vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); @@ -336,8 +400,8 @@ template class vm_impl : public iss::interp::vm_base { } uint8_t valid_reg_overlap(uint8_t rs, uint8_t rd, int8_t EMUL_pow_rs, int8_t EMUL_pow_rd){ - uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& (1ULL << 4) : 1; - uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& (1ULL << 4) : 1; + uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& ((1ULL << 5)-1) : 1; + uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& ((1ULL << 5)-1) : 1; if(EMUL_pow_rs < EMUL_pow_rd) { return (rs + rs_group <= rd) || (rs >= rd + rd_group) || ((rs + rs_group == rd + rd_group) & (EMUL_pow_rs >= 0)); } @@ -433,8 +497,8 @@ template class vm_impl : public iss::interp::vm_base { return ! valid_vtype() || *vstart != 0; } - uint8_t illegal_reduction_widen(uint8_t EEW, int8_t EMUL_pow){ - return illegal_reduction() || ! valid_eew_emul(EEW, EMUL_pow); + uint8_t illegal_reduction_widen(uint8_t EEW){ + return illegal_reduction() || ! (EEW >= 8 && EEW <= traits::ELEN); } uint8_t illegal_fp_reduction(uint8_t SEW, uint8_t rm){ @@ -442,6 +506,10 @@ template class vm_impl : public iss::interp::vm_base { return ! valid_vtype() || *vstart != 0 || ! valid_fp_op(SEW, rm); } + uint8_t illegal_fp_reduction_widen(uint8_t SEW, uint8_t rm, uint8_t EEW){ + return illegal_fp_reduction(SEW, rm) || ! (EEW >= 8 && EEW <= traits::ELEN); + } + uint8_t illegal_fp_variable_width(uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm, uint8_t SEW_new, int8_t LMUL_pow_new){ return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_fp_op(SEW, rm)) || ! (valid_eew_emul(SEW_new, LMUL_pow_new)); } @@ -4636,7 +4704,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 4; // execute instruction { - *(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& (1ULL << 0)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1)))); + *(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1)))); } break; }// @suppress("No break at end of case") @@ -5486,7 +5554,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 4; // execute instruction { - *(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& (1ULL << 0)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1)))); + *(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1)))); } break; }// @suppress("No break at end of case") @@ -19389,9 +19457,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 2; + uint8_t SEW_target = (uint8_t)(SEW / 2); int8_t LMUL_pow_target = LMUL_pow - 1; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -19426,9 +19494,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 2; + uint8_t SEW_target = (uint8_t)(SEW / 2); int8_t LMUL_pow_target = LMUL_pow - 1; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -19463,9 +19531,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 4; + uint8_t SEW_target = (uint8_t)(SEW / 4); int8_t LMUL_pow_target = LMUL_pow - 2; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -19500,9 +19568,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 4; + uint8_t SEW_target = (uint8_t)(SEW / 4); int8_t LMUL_pow_target = LMUL_pow - 2; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -19537,9 +19605,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 8; + uint8_t SEW_target = (uint8_t)(SEW / 8); int8_t LMUL_pow_target = LMUL_pow - 3; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -19574,9 +19642,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 8; + uint8_t SEW_target = (uint8_t)(SEW / 8); int8_t LMUL_pow_target = LMUL_pow - 3; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -23156,9 +23224,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_widen = (uint8_t)(SEW * 2); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); int8_t LMUL_pow_widen = LMUL_pow + 1; if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -24803,10 +24871,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; - int8_t LMUL_pow = get_lmul_pow(); uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); - int8_t LMUL_pow_widen = LMUL_pow + 1; - if(illegal_reduction_widen(SEW_widen, LMUL_pow_widen)) { + if(illegal_reduction_widen(SEW_widen)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { @@ -24840,10 +24906,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; - int8_t LMUL_pow = get_lmul_pow(); uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); - int8_t LMUL_pow_widen = LMUL_pow + 1; - if(illegal_reduction_widen(SEW_widen, LMUL_pow_widen)) { + if(illegal_reduction_widen(SEW_widen)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { @@ -25027,7 +25091,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); - if(illegal_fp_reduction(SEW, rm)) { + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + if(illegal_fp_reduction_widen(SEW, rm, SEW_widen)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { @@ -25065,7 +25130,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); - if(illegal_fp_reduction(SEW, rm)) { + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + if(illegal_fp_reduction_widen(SEW, rm, SEW_widen)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp index 7157a7b..0d069e1 100644 --- a/src/vm/interp/vm_rv64gcv.cpp +++ b/src/vm/interp/vm_rv64gcv.cpp @@ -40,9 +40,6 @@ #include -#define CUR_VLEN 512 -#define CUR_XLEN 64 -#include #include #include @@ -65,6 +62,7 @@ namespace iss { namespace interp { namespace rv64gcv { + using namespace iss::arch; using namespace iss::debugger; using namespace std::placeholders; @@ -84,7 +82,73 @@ template class vm_impl : public iss::interp::vm_base { using reg_t = typename traits::reg_t; using mem_type_e = typename traits::mem_type_e; using opcode_e = typename traits::opcode_e; - + + + static constexpr auto& vlseg = trampoline::vlseg; + static constexpr auto& vsseg = trampoline::vsseg; + static constexpr auto& vlsseg = trampoline::vlsseg; + static constexpr auto& vssseg = trampoline::vssseg; + static constexpr auto& vlxseg = trampoline::vlxseg; + static constexpr auto& vsxseg = trampoline::vsxseg; + static constexpr auto& vector_vector_op = trampoline::vector_vector_op; + static constexpr auto& vector_imm_op = trampoline::vector_imm_op; + static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; + static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; + static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; + static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; + static constexpr auto& vector_extend = trampoline::vector_extend; + static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; + static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; + static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; + static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; + static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; + static constexpr auto& vector_red_op = trampoline::vector_red_op; + static constexpr auto& vector_red_wv = trampoline::vector_red_wv; + static constexpr auto& mask_mask_op = trampoline::mask_mask_op; + static constexpr auto& vcpop = trampoline::vcpop; + static constexpr auto& vfirst = trampoline::vfirst; + static constexpr auto& mask_set_op = trampoline::mask_set_op; + static constexpr auto& viota = trampoline::viota; + static constexpr auto& vid = trampoline::vid; + static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; + static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; + static constexpr auto& vector_slideup = trampoline::vector_slideup; + static constexpr auto& vector_slidedown = trampoline::vector_slidedown; + static constexpr auto& vector_slide1up = trampoline::vector_slide1up; + static constexpr auto& vector_slide1down = trampoline::vector_slide1down; + static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; + static constexpr auto& vector_compress = trampoline::vector_compress; + static constexpr auto& vector_whole_move = trampoline::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; + static constexpr auto& vector_unary_op = trampoline::vector_unary_op; + vm_impl(); vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); @@ -336,8 +400,8 @@ template class vm_impl : public iss::interp::vm_base { } uint8_t valid_reg_overlap(uint8_t rs, uint8_t rd, int8_t EMUL_pow_rs, int8_t EMUL_pow_rd){ - uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& (1ULL << 4) : 1; - uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& (1ULL << 4) : 1; + uint8_t rs_group = EMUL_pow_rs > 0? (uint8_t)(1 << EMUL_pow_rs) & (~1)& ((1ULL << 5)-1) : 1; + uint8_t rd_group = EMUL_pow_rd > 0? (uint8_t)(1 << EMUL_pow_rd) & (~1)& ((1ULL << 5)-1) : 1; if(EMUL_pow_rs < EMUL_pow_rd) { return (rs + rs_group <= rd) || (rs >= rd + rd_group) || ((rs + rs_group == rd + rd_group) & (EMUL_pow_rs >= 0)); } @@ -433,8 +497,8 @@ template class vm_impl : public iss::interp::vm_base { return ! valid_vtype() || *vstart != 0; } - uint8_t illegal_reduction_widen(uint8_t EEW, int8_t EMUL_pow){ - return illegal_reduction() || ! valid_eew_emul(EEW, EMUL_pow); + uint8_t illegal_reduction_widen(uint8_t EEW){ + return illegal_reduction() || ! (EEW >= 8 && EEW <= traits::ELEN); } uint8_t illegal_fp_reduction(uint8_t SEW, uint8_t rm){ @@ -442,6 +506,10 @@ template class vm_impl : public iss::interp::vm_base { return ! valid_vtype() || *vstart != 0 || ! valid_fp_op(SEW, rm); } + uint8_t illegal_fp_reduction_widen(uint8_t SEW, uint8_t rm, uint8_t EEW){ + return illegal_fp_reduction(SEW, rm) || ! (EEW >= 8 && EEW <= traits::ELEN); + } + uint8_t illegal_fp_variable_width(uint8_t vd, uint8_t vm, uint8_t SEW, uint8_t rm, uint8_t SEW_new, int8_t LMUL_pow_new){ return ! (valid_vtype()) || ! (valid_rd_mask(vd, vm)) || ! (valid_fp_op(SEW, rm)) || ! (valid_eew_emul(SEW_new, LMUL_pow_new)); } @@ -5897,7 +5965,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 4; // execute instruction { - *(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& (1ULL << 0)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1)))); + *(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1)))); } break; }// @suppress("No break at end of case") @@ -6775,7 +6843,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 4; // execute instruction { - *(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& (1ULL << 0)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1)))); + *(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1)))); } break; }// @suppress("No break at end of case") @@ -20732,9 +20800,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 2; + uint8_t SEW_target = (uint8_t)(SEW / 2); int8_t LMUL_pow_target = LMUL_pow - 1; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -20769,9 +20837,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 2; + uint8_t SEW_target = (uint8_t)(SEW / 2); int8_t LMUL_pow_target = LMUL_pow - 1; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -20806,9 +20874,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 4; + uint8_t SEW_target = (uint8_t)(SEW / 4); int8_t LMUL_pow_target = LMUL_pow - 2; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -20843,9 +20911,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 4; + uint8_t SEW_target = (uint8_t)(SEW / 4); int8_t LMUL_pow_target = LMUL_pow - 2; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -20880,9 +20948,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 8; + uint8_t SEW_target = (uint8_t)(SEW / 8); int8_t LMUL_pow_target = LMUL_pow - 3; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -20917,9 +20985,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW_pow = get_sew_pow(); - uint8_t SEW = (uint8_t)(1 << SEW_pow) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << SEW_pow); int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_target = SEW / 8; + uint8_t SEW_target = (uint8_t)(SEW / 8); int8_t LMUL_pow_target = LMUL_pow - 3; if(illegal_variable_width(vd, vm, SEW_target, LMUL_pow_target) || ! valid_reg_overlap(vs2, vd, LMUL_pow_target, LMUL_pow)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -24499,9 +24567,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { - uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & (~1)& (1ULL << 4); + uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; int8_t LMUL_pow = get_lmul_pow(); - uint8_t SEW_widen = (uint8_t)(SEW * 2); + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); int8_t LMUL_pow_widen = LMUL_pow + 1; if(illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) || ! valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); @@ -26146,10 +26214,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; - int8_t LMUL_pow = get_lmul_pow(); uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); - int8_t LMUL_pow_widen = LMUL_pow + 1; - if(illegal_reduction_widen(SEW_widen, LMUL_pow_widen)) { + if(illegal_reduction_widen(SEW_widen)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { @@ -26183,10 +26249,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint8_t SEW = (uint8_t)(1 << get_sew_pow()) & ~1; - int8_t LMUL_pow = get_lmul_pow(); uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); - int8_t LMUL_pow_widen = LMUL_pow + 1; - if(illegal_reduction_widen(SEW_widen, LMUL_pow_widen)) { + if(illegal_reduction_widen(SEW_widen)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { @@ -26370,7 +26434,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); - if(illegal_fp_reduction(SEW, rm)) { + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + if(illegal_fp_reduction_widen(SEW, rm, SEW_widen)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { @@ -26408,7 +26473,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co { uint8_t SEW = (uint8_t)(1 << (get_sew_pow())) & ~1; uint8_t rm = bit_sub<5, 7-5+1>(*FCSR); - if(illegal_fp_reduction(SEW, rm)) { + uint8_t SEW_widen = (uint8_t)((uint16_t)(SEW) * (uint16_t)(2)); + if(illegal_fp_reduction_widen(SEW, rm, SEW_widen)) { raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION); } else { diff --git a/src/vm/new_vector_functions.cpp b/src/vm/new_vector_functions.cpp deleted file mode 100644 index 1bd7fdb..0000000 --- a/src/vm/new_vector_functions.cpp +++ /dev/null @@ -1,934 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2025, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -// Contributors: -// alex@minres.com - initial API and implementation -//////////////////////////////////////////////////////////////////////////////// - -#include -#include - -#include "iss/arch_if.h" -#include "iss/vm_types.h" -#include -#include - -using indexed_load_store_t = std::function, uint8_t*, uint64_t, - uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; -template indexed_load_store_t getFunction() { - return [](void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, - uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, uint8_t segment_size) { - return softvector::vector_load_store_index(core, load_store_fn, V, vl, vstart, vtype, vm, vd, rs1, vs2, - segment_size); - }; -} - -const std::array, 4> functionTable = { - {{getFunction(), getFunction(), getFunction(), - getFunction()}, - {getFunction(), getFunction(), getFunction(), - getFunction()}, - {getFunction(), getFunction(), getFunction(), - getFunction()}, - {getFunction(), getFunction(), getFunction(), - getFunction()}}}; -constexpr size_t map_index_size[9] = {0, - std::numeric_limits::max(), - 1, - std::numeric_limits::max(), - 2, - std::numeric_limits::max(), - std::numeric_limits::max(), - std::numeric_limits::max(), - 3}; - -bool softvec_read(void* core, uint64_t addr, uint64_t length, uint8_t* data) { - // Read length bytes from addr into *data - iss::status status = static_cast(core)->read(iss::address_type::PHYSICAL, iss::access_type::READ, - 0 /*traits::MEM*/, addr, length, data); - return status == iss::Ok; -} -bool softvec_write(void* core, uint64_t addr, uint64_t length, uint8_t* data) { - // Write length bytes from addr into *data - iss::status status = static_cast(core)->write(iss::address_type::PHYSICAL, iss::access_type::READ, - 0 /*traits::MEM*/, addr, length, data); - return status == iss::Ok; -} -extern "C" { -uint64_t vlseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size) { - switch(width_val) { - case 0b000: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b101: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b110: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b111: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - default: - throw new std::runtime_error("Unsupported width bit value"); - } -} -uint64_t vsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size) { - switch(width_val) { - case 0b000: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b101: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b110: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b111: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - default: - throw new std::runtime_error("Unsupported width bit value"); - } -} -uint64_t vlsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size, int64_t stride) { - switch(width_val) { - case 0b000: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b101: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b110: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b111: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - default: - throw new std::runtime_error("Unsupported width bit value"); - } -} -uint64_t vssseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size, int64_t stride) { - switch(width_val) { - case 0b000: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b101: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b110: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b111: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - default: - throw new std::runtime_error("Unsupported width bit value"); - } -} -uint64_t vlxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered) { - return functionTable[map_index_size[index_byte_size]][data_byte_size](core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, vs2, - segment_size); -} -uint64_t vsxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, - uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered) { - return functionTable[map_index_size[index_byte_size]][data_byte_size](core, softvec_write, V, vl, vstart, vtype, vm, vs3, rs1_val, vs2, - segment_size); -} -void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint8_t target_sew_pow, uint8_t frac_pow) { - switch(target_sew_pow) { - case 4: // uint16_t target - if(frac_pow != 1) - throw new std::runtime_error("Unsupported frac_pow"); - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 5: // uint32_t target - switch(frac_pow) { - case 1: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 2: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported frac_pow"); - } - case 6: // uint64_t target - switch(frac_pow) { - case 1: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 2: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 3: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported frac_pow"); - } - default: - throw new std::runtime_error("Unsupported target_sew_pow"); - } -} -void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b001: - return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b010: - return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b011: - return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b001: - return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b010: - return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b011: - return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, - uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b001: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b010: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b011: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, - bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b001: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b010: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b011: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, - uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b001: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b010: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, - bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b001: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b010: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1) { - return softvector::mask_mask_op(V, funct6, funct3, vl, vstart, vd, vs2, vs1); -} -uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { - return softvector::vcpop(V, vl, vstart, vm, vs2); -} -int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { - return softvector::vfirst(V, vl, vstart, vm, vs2); -} -void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2) { - return softvector::mask_set_op(V, enc, vl, vstart, vm, vd, vs2); -} -void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); - case 0b001: - return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); - case 0b010: - return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); - case 0b011: - return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vid(V, vl, vstart, vtype, vm, vd); - case 0b001: - return softvector::vid(V, vl, vstart, vtype, vm, vd); - case 0b010: - return softvector::vid(V, vl, vstart, vtype, vm, vd); - case 0b011: - return softvector::vid(V, vl, vstart, vtype, vm, vd); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - softvector::scalar_move(V, vtype, vd, val, true); - break; - case 0b001: - softvector::scalar_move(V, vtype, vd, val, true); - break; - case 0b010: - softvector::scalar_move(V, vtype, vd, val, true); - break; - case 0b011: - softvector::scalar_move(V, vtype, vd, val, true); - break; - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::scalar_move(V, vtype, vd, 0, false); - case 0b001: - return softvector::scalar_move(V, vtype, vd, 0, false); - case 0b010: - return softvector::scalar_move(V, vtype, vd, 0, false); - case 0b011: - return softvector::scalar_move(V, vtype, vd, 0, false); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b001: - return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b010: - return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b011: - return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count) { - return softvector::vector_whole_move(V, vd, vs2, count); -} -uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val) { - return scalar_from_vector(V, vtype, vd, sew_val); -} -void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint64_t imm, uint8_t sew_val) { - return vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); -} -void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint64_t imm, uint8_t sew_val) { - return vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); -} -void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b001: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, - rm); - case 0b010: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, - rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, - vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, - vs1, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, - rm); - case 0b010: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, - rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, - bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: - return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: - return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint64_t imm, uint8_t sew_val) { - vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); -} -void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b001: - return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b001: - return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: // would require 128 bit value to narrow - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b001: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b010: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b011: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported sew_val"); - } -} -} \ No newline at end of file diff --git a/src/vm/new_vector_functions.h b/src/vm/new_vector_functions.h index 8710ee3..33a7055 100644 --- a/src/vm/new_vector_functions.h +++ b/src/vm/new_vector_functions.h @@ -34,134 +34,956 @@ #ifndef RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ #define RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ +#include #include +#include + +#include "iss/arch_if.h" +#include "iss/vm_types.h" #include -// To make the language server happy -#ifndef CUR_VLEN -#define CUR_VLEN 0 -#endif -#ifndef CUR_XLEN -#define CUR_XLEN 0 -#endif -extern "C" { +namespace trampoline { +using indexed_load_store_t = std::function, uint8_t*, uint64_t, + uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; +template indexed_load_store_t getFunction() { + return [](void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, + uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, uint8_t segment_size) { + return softvector::vector_load_store_index(core, load_store_fn, V, vl, vstart, vtype, vm, vd, rs1, vs2, + segment_size); + }; +} +template +const std::array, 4> functionTable = { + {{getFunction(), getFunction(), + getFunction(), getFunction()}, + {getFunction(), getFunction(), + getFunction(), getFunction()}, + {getFunction(), getFunction(), + getFunction(), getFunction()}, + {getFunction(), getFunction(), + getFunction(), getFunction()}}}; +constexpr size_t map_index_size[9] = {std::numeric_limits::max(), + 0, + 1, + std::numeric_limits::max(), + 2, + std::numeric_limits::max(), + std::numeric_limits::max(), + std::numeric_limits::max(), + 3}; + +inline bool softvec_read(void* core, uint64_t addr, uint64_t length, uint8_t* data) { + // Read length bytes from addr into *data + iss::status status = static_cast(core)->read(iss::address_type::PHYSICAL, iss::access_type::READ, + 0 /*traits::MEM*/, addr, length, data); + return status == iss::Ok; +} +inline bool softvec_write(void* core, uint64_t addr, uint64_t length, uint8_t* data) { + // Write length bytes from addr into *data + iss::status status = static_cast(core)->write(iss::address_type::PHYSICAL, iss::access_type::READ, + 0 /*traits::MEM*/, addr, length, data); + return status == iss::Ok; +} +template uint64_t vlseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size); + uint8_t width_val, uint8_t segment_size) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b101: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b110: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b111: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +template uint64_t vsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size); + uint8_t width_val, uint8_t segment_size) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b101: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b110: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b111: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +template uint64_t vlsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size, int64_t stride); + uint8_t width_val, uint8_t segment_size, int64_t stride) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, + true); + case 0b101: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b110: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b111: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +template uint64_t vssseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size, int64_t stride); + uint8_t width_val, uint8_t segment_size, int64_t stride) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b101: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b110: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b111: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +template uint64_t vlxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered); + uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered) { + return functionTable[map_index_size[index_byte_size]][data_byte_size](core, softvec_read, V, vl, vstart, vtype, vm, vd, + rs1_val, vs2, segment_size); +} +template uint64_t vsxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, - uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered); + uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered) { + return functionTable[map_index_size[index_byte_size]][data_byte_size](core, softvec_write, V, vl, vstart, vtype, vm, vs3, + rs1_val, vs2, segment_size); +} +template void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val); + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val); + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val); + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint8_t target_sew_pow, uint8_t frac_pow); + uint8_t target_sew_pow, uint8_t frac_pow) { + switch(target_sew_pow) { + case 4: // uint16_t target + if(frac_pow != 1) + throw new std::runtime_error("Unsupported frac_pow"); + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 5: // uint32_t target + switch(frac_pow) { + case 1: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 2: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported frac_pow"); + } + case 6: // uint64_t target + switch(frac_pow) { + case 1: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 2: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 3: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported frac_pow"); + } + default: + throw new std::runtime_error("Unsupported target_sew_pow"); + } +} +template void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry); + uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b001: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b010: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b011: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry); + uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b001: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b010: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b011: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1, uint8_t sew_val); + unsigned vs2, unsigned vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, int64_t imm, uint8_t sew_val); + unsigned vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val); + unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val); + unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val); + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, - uint8_t sew_val); + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, - uint8_t sew_val); + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, - uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); + uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b001: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b010: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b011: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, - bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val); + bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b001: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b010: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b011: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, - uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val); + uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b001: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b010: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, - bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val); + bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b001: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b010: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t sew_val); + uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t sew_val); -void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1); -uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2); -int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2); -void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2); -void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val); -void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val); -void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val); -uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val); + uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1) { + return softvector::mask_mask_op(V, funct6, funct3, vl, vstart, vd, vs2, vs1); +} +template uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { + return softvector::vcpop(V, vl, vstart, vm, vs2); +} +template int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { + return softvector::vfirst(V, vl, vstart, vm, vs2); +} +template void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2) { + return softvector::mask_set_op(V, enc, vl, vstart, vm, vd, vs2); +} +template +void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + case 0b001: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + case 0b010: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + case 0b011: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + case 0b001: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + case 0b010: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + case 0b011: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + softvector::scalar_move(V, vtype, vd, val, true); + break; + case 0b001: + softvector::scalar_move(V, vtype, vd, val, true); + break; + case 0b010: + softvector::scalar_move(V, vtype, vd, val, true); + break; + case 0b011: + softvector::scalar_move(V, vtype, vd, val, true); + break; + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::scalar_move(V, vtype, vd, 0, false); + case 0b001: + return softvector::scalar_move(V, vtype, vd, 0, false); + case 0b010: + return softvector::scalar_move(V, vtype, vd, 0, false); + case 0b011: + return softvector::scalar_move(V, vtype, vd, 0, false); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, - uint8_t sew_val); + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, - uint8_t sew_val); + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, - uint8_t sew_val); + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint64_t imm, uint8_t sew_val); + uint64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint8_t vs1, uint8_t sew_val); + uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint8_t vs1, uint8_t sew_val); + uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, - uint8_t sew_val); + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, - uint8_t sew_val); -void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count); -uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val); + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b001: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b010: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b011: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count) { + return softvector::vector_whole_move(V, vd, vs2, count); +} +template uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val) { + return scalar_from_vector(V, vtype, vd, sew_val); +} +template void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint64_t imm, uint8_t sew_val); + uint64_t imm, uint8_t sew_val) { + return vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); +} +template void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint64_t imm, uint8_t sew_val); + uint64_t imm, uint8_t sew_val) { + return vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); +} +template void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b001: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, + rm); + case 0b010: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, + rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val); + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, - bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val); + bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: + return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val); + uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val); + uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: + return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint64_t imm, uint8_t sew_val); + uint64_t imm, uint8_t sew_val) { + vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); +} +template void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t rm, uint8_t sew_val); + uint8_t vs2, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b001: + return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t rm, uint8_t sew_val); + uint8_t vs2, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b001: + return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: // would require 128 bit value to narrow + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t sew_val); + uint8_t vs2, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b001: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b010: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b011: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported sew_val"); + } } +} // namespace trampoline #endif /* RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ */ From 3cbaa1c3a2887a5669a841e725d7dc95fc0f6e99 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Wed, 24 Sep 2025 20:20:31 +0200 Subject: [PATCH 016/230] corrects htif / tohost functionality --- src/iss/arch/riscv_hart_common.h | 9 +++++---- src/iss/mem/memory_with_htif.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h index 8abd089..f61713b 100644 --- a/src/iss/arch/riscv_hart_common.h +++ b/src/iss/arch/riscv_hart_common.h @@ -293,7 +293,7 @@ template struct priv_if { std::function read_csr; std::function write_csr; - std::function exec_htif; + std::function exec_htif; std::function raise_trap; // trap_id, cause, fault_data std::unordered_map& csr_rd_cb; std::unordered_map& csr_wr_cb; @@ -861,7 +861,7 @@ template struct riscv_hart_co priv_if get_priv_if() { return priv_if{.read_csr = [this](unsigned addr, reg_t& val) -> iss::status { return read_csr(addr, val); }, .write_csr = [this](unsigned addr, reg_t val) -> iss::status { return write_csr(addr, val); }, - .exec_htif = [this](uint8_t const* data) -> iss::status { return execute_htif(data); }, + .exec_htif = [this](uint8_t const* data, unsigned length) -> iss::status { return execute_htif(data, length); }, .raise_trap = [this](uint16_t trap_id, uint16_t cause, reg_t fault_data) { this->reg.trap_state = 0x80ULL << 24 | (cause << 16) | trap_id; @@ -877,8 +877,9 @@ template struct riscv_hart_co .max_irq{mcause_max_irq}}; } - iss::status execute_htif(uint8_t const* data) { - reg_t cur_data = *reinterpret_cast(data); + iss::status execute_htif(uint8_t const* data, unsigned length) { + reg_t cur_data{0}; + memcpy(&cur_data, data, length); // Extract Device (bits 63:56) uint8_t device = traits::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF; // Extract Command (bits 55:48) diff --git a/src/iss/mem/memory_with_htif.h b/src/iss/mem/memory_with_htif.h index db92c9a..47b021f 100644 --- a/src/iss/mem/memory_with_htif.h +++ b/src/iss/mem/memory_with_htif.h @@ -100,7 +100,7 @@ template struct memory_with_htif : public memory_elem { // this->tohost handling in case of riscv-test // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754: if(access && iss::access_type::FUNC && addr == hart_if.tohost) { - return hart_if.exec_htif(data); + return hart_if.exec_htif(data, length); } return iss::Ok; } From 093daa77309e9f8db55ee37d907f0af20e333e48 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Wed, 24 Sep 2025 20:23:12 +0200 Subject: [PATCH 017/230] updates dbt-rise-core --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 083cdbc..829ccc1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -20,7 +20,7 @@ if(NOT TARGET dbt-rise-core) dbt_rise_core_git GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git" #GIT_TAG "origin/develop" - GIT_TAG 718f877 + GIT_TAG d2bafe GIT_SHALLOW OFF UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped. ) From 40207521760f06f50eb91b2e39ed2f726d237a22 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Wed, 24 Sep 2025 20:23:37 +0200 Subject: [PATCH 018/230] updates ISA submodule --- gen_input/ISA | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gen_input/ISA b/gen_input/ISA index dafcab1..34eef99 160000 --- a/gen_input/ISA +++ b/gen_input/ISA @@ -1 +1 @@ -Subproject commit dafcab1b8b6b84e2b333cf791a2c33b005011835 +Subproject commit 34eef9992295d9fbe2bdf9a5abdf8747e18dd54a From 1b9e3ba27b9af4735ba967abde789c1494ba894c Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 25 Sep 2025 08:16:56 +0200 Subject: [PATCH 019/230] corrects name for vector interface functions --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 128 +++++++++---------- gen_input/templates/interp/CORENAME.cpp.gtl | 128 +++++++++---------- src/vm/asmjit/vm_rv32gcv.cpp | 128 +++++++++---------- src/vm/asmjit/vm_rv64gcv.cpp | 132 ++++++++++---------- src/vm/interp/vm_rv32gcv.cpp | 130 +++++++++---------- src/vm/interp/vm_rv64gcv.cpp | 130 +++++++++---------- src/vm/new_vector_functions.h | 4 +- 7 files changed, 390 insertions(+), 390 deletions(-) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 4aae8d1..7b56d9e 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -99,70 +99,70 @@ public: using addr_t = typename super::addr_t; <%if(vector) {%> - static constexpr auto& vlseg = trampoline::vlseg; - static constexpr auto& vsseg = trampoline::vsseg; - static constexpr auto& vlsseg = trampoline::vlsseg; - static constexpr auto& vssseg = trampoline::vssseg; - static constexpr auto& vlxseg = trampoline::vlxseg; - static constexpr auto& vsxseg = trampoline::vsxseg; - static constexpr auto& vector_vector_op = trampoline::vector_vector_op; - static constexpr auto& vector_imm_op = trampoline::vector_imm_op; - static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; - static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; - static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; - static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; - static constexpr auto& vector_extend = trampoline::vector_extend; - static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; - static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; - static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; - static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; - static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; - static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; - static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; - static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; - static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; - static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; - static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; - static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; - static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; - static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; - static constexpr auto& vector_red_op = trampoline::vector_red_op; - static constexpr auto& vector_red_wv = trampoline::vector_red_wv; - static constexpr auto& mask_mask_op = trampoline::mask_mask_op; - static constexpr auto& vcpop = trampoline::vcpop; - static constexpr auto& vfirst = trampoline::vfirst; - static constexpr auto& mask_set_op = trampoline::mask_set_op; - static constexpr auto& viota = trampoline::viota; - static constexpr auto& vid = trampoline::vid; - static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; - static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; - static constexpr auto& vector_slideup = trampoline::vector_slideup; - static constexpr auto& vector_slidedown = trampoline::vector_slidedown; - static constexpr auto& vector_slide1up = trampoline::vector_slide1up; - static constexpr auto& vector_slide1down = trampoline::vector_slide1down; - static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; - static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; - static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; - static constexpr auto& vector_compress = trampoline::vector_compress; - static constexpr auto& vector_whole_move = trampoline::vector_whole_move; - static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; - static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; - static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; - static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; - static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; - static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; - static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; - static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; - static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; - static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; - static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; - static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; - static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; - static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; - static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; - static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; - static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; - static constexpr auto& vector_unary_op = trampoline::vector_unary_op; + static constexpr auto& vlseg = softvec_if::vlseg; + static constexpr auto& vsseg = softvec_if::vsseg; + static constexpr auto& vlsseg = softvec_if::vlsseg; + static constexpr auto& vssseg = softvec_if::vssseg; + static constexpr auto& vlxseg = softvec_if::vlxseg; + static constexpr auto& vsxseg = softvec_if::vsxseg; + static constexpr auto& vector_vector_op = softvec_if::vector_vector_op; + static constexpr auto& vector_imm_op = softvec_if::vector_imm_op; + static constexpr auto& vector_vector_wv = softvec_if::vector_vector_wv; + static constexpr auto& vector_imm_wv = softvec_if::vector_imm_wv; + static constexpr auto& vector_vector_ww = softvec_if::vector_vector_ww; + static constexpr auto& vector_imm_ww = softvec_if::vector_imm_ww; + static constexpr auto& vector_extend = softvec_if::vector_extend; + static constexpr auto& vector_vector_carry = softvec_if::vector_vector_carry; + static constexpr auto& vector_imm_carry = softvec_if::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = softvec_if::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = softvec_if::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = softvec_if::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = softvec_if::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = softvec_if::vector_vector_vw; + static constexpr auto& vector_imm_vw = softvec_if::vector_imm_vw; + static constexpr auto& vector_vector_merge = softvec_if::vector_vector_merge; + static constexpr auto& vector_imm_merge = softvec_if::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = softvec_if::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = softvec_if::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = softvec_if::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = softvec_if::sat_vector_imm_vw; + static constexpr auto& vector_red_op = softvec_if::vector_red_op; + static constexpr auto& vector_red_wv = softvec_if::vector_red_wv; + static constexpr auto& mask_mask_op = softvec_if::mask_mask_op; + static constexpr auto& vcpop = softvec_if::vcpop; + static constexpr auto& vfirst = softvec_if::vfirst; + static constexpr auto& mask_set_op = softvec_if::mask_set_op; + static constexpr auto& viota = softvec_if::viota; + static constexpr auto& vid = softvec_if::vid; + static constexpr auto& scalar_to_vector = softvec_if::scalar_to_vector; + static constexpr auto& scalar_from_vector = softvec_if::scalar_from_vector; + static constexpr auto& vector_slideup = softvec_if::vector_slideup; + static constexpr auto& vector_slidedown = softvec_if::vector_slidedown; + static constexpr auto& vector_slide1up = softvec_if::vector_slide1up; + static constexpr auto& vector_slide1down = softvec_if::vector_slide1down; + static constexpr auto& vector_vector_gather = softvec_if::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = softvec_if::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = softvec_if::vector_imm_gather; + static constexpr auto& vector_compress = softvec_if::vector_compress; + static constexpr auto& vector_whole_move = softvec_if::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = softvec_if::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = softvec_if::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = softvec_if::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = softvec_if::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = softvec_if::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = softvec_if::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = softvec_if::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = softvec_if::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = softvec_if::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = softvec_if::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = softvec_if::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = softvec_if::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = softvec_if::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = softvec_if::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = softvec_if::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = softvec_if::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = softvec_if::fp_vector_unary_n; + static constexpr auto& vector_unary_op = softvec_if::vector_unary_op; <%}%> vm_impl(); diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 187768f..784f8b7 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -96,70 +96,70 @@ public: using opcode_e = typename traits::opcode_e; <%if(vector) {%> - static constexpr auto& vlseg = trampoline::vlseg; - static constexpr auto& vsseg = trampoline::vsseg; - static constexpr auto& vlsseg = trampoline::vlsseg; - static constexpr auto& vssseg = trampoline::vssseg; - static constexpr auto& vlxseg = trampoline::vlxseg; - static constexpr auto& vsxseg = trampoline::vsxseg; - static constexpr auto& vector_vector_op = trampoline::vector_vector_op; - static constexpr auto& vector_imm_op = trampoline::vector_imm_op; - static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; - static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; - static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; - static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; - static constexpr auto& vector_extend = trampoline::vector_extend; - static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; - static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; - static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; - static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; - static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; - static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; - static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; - static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; - static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; - static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; - static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; - static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; - static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; - static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; - static constexpr auto& vector_red_op = trampoline::vector_red_op; - static constexpr auto& vector_red_wv = trampoline::vector_red_wv; - static constexpr auto& mask_mask_op = trampoline::mask_mask_op; - static constexpr auto& vcpop = trampoline::vcpop; - static constexpr auto& vfirst = trampoline::vfirst; - static constexpr auto& mask_set_op = trampoline::mask_set_op; - static constexpr auto& viota = trampoline::viota; - static constexpr auto& vid = trampoline::vid; - static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; - static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; - static constexpr auto& vector_slideup = trampoline::vector_slideup; - static constexpr auto& vector_slidedown = trampoline::vector_slidedown; - static constexpr auto& vector_slide1up = trampoline::vector_slide1up; - static constexpr auto& vector_slide1down = trampoline::vector_slide1down; - static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; - static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; - static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; - static constexpr auto& vector_compress = trampoline::vector_compress; - static constexpr auto& vector_whole_move = trampoline::vector_whole_move; - static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; - static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; - static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; - static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; - static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; - static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; - static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; - static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; - static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; - static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; - static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; - static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; - static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; - static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; - static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; - static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; - static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; - static constexpr auto& vector_unary_op = trampoline::vector_unary_op; + static constexpr auto& vlseg = softvec_if::vlseg; + static constexpr auto& vsseg = softvec_if::vsseg; + static constexpr auto& vlsseg = softvec_if::vlsseg; + static constexpr auto& vssseg = softvec_if::vssseg; + static constexpr auto& vlxseg = softvec_if::vlxseg; + static constexpr auto& vsxseg = softvec_if::vsxseg; + static constexpr auto& vector_vector_op = softvec_if::vector_vector_op; + static constexpr auto& vector_imm_op = softvec_if::vector_imm_op; + static constexpr auto& vector_vector_wv = softvec_if::vector_vector_wv; + static constexpr auto& vector_imm_wv = softvec_if::vector_imm_wv; + static constexpr auto& vector_vector_ww = softvec_if::vector_vector_ww; + static constexpr auto& vector_imm_ww = softvec_if::vector_imm_ww; + static constexpr auto& vector_extend = softvec_if::vector_extend; + static constexpr auto& vector_vector_carry = softvec_if::vector_vector_carry; + static constexpr auto& vector_imm_carry = softvec_if::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = softvec_if::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = softvec_if::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = softvec_if::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = softvec_if::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = softvec_if::vector_vector_vw; + static constexpr auto& vector_imm_vw = softvec_if::vector_imm_vw; + static constexpr auto& vector_vector_merge = softvec_if::vector_vector_merge; + static constexpr auto& vector_imm_merge = softvec_if::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = softvec_if::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = softvec_if::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = softvec_if::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = softvec_if::sat_vector_imm_vw; + static constexpr auto& vector_red_op = softvec_if::vector_red_op; + static constexpr auto& vector_red_wv = softvec_if::vector_red_wv; + static constexpr auto& mask_mask_op = softvec_if::mask_mask_op; + static constexpr auto& vcpop = softvec_if::vcpop; + static constexpr auto& vfirst = softvec_if::vfirst; + static constexpr auto& mask_set_op = softvec_if::mask_set_op; + static constexpr auto& viota = softvec_if::viota; + static constexpr auto& vid = softvec_if::vid; + static constexpr auto& scalar_to_vector = softvec_if::scalar_to_vector; + static constexpr auto& scalar_from_vector = softvec_if::scalar_from_vector; + static constexpr auto& vector_slideup = softvec_if::vector_slideup; + static constexpr auto& vector_slidedown = softvec_if::vector_slidedown; + static constexpr auto& vector_slide1up = softvec_if::vector_slide1up; + static constexpr auto& vector_slide1down = softvec_if::vector_slide1down; + static constexpr auto& vector_vector_gather = softvec_if::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = softvec_if::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = softvec_if::vector_imm_gather; + static constexpr auto& vector_compress = softvec_if::vector_compress; + static constexpr auto& vector_whole_move = softvec_if::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = softvec_if::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = softvec_if::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = softvec_if::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = softvec_if::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = softvec_if::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = softvec_if::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = softvec_if::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = softvec_if::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = softvec_if::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = softvec_if::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = softvec_if::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = softvec_if::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = softvec_if::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = softvec_if::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = softvec_if::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = softvec_if::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = softvec_if::fp_vector_unary_n; + static constexpr auto& vector_unary_op = softvec_if::vector_unary_op; <%}%> vm_impl(); diff --git a/src/vm/asmjit/vm_rv32gcv.cpp b/src/vm/asmjit/vm_rv32gcv.cpp index 0f04046..3638d04 100644 --- a/src/vm/asmjit/vm_rv32gcv.cpp +++ b/src/vm/asmjit/vm_rv32gcv.cpp @@ -87,70 +87,70 @@ template class vm_impl : public iss::asmjit::vm_base { using addr_t = typename super::addr_t; - static constexpr auto& vlseg = trampoline::vlseg; - static constexpr auto& vsseg = trampoline::vsseg; - static constexpr auto& vlsseg = trampoline::vlsseg; - static constexpr auto& vssseg = trampoline::vssseg; - static constexpr auto& vlxseg = trampoline::vlxseg; - static constexpr auto& vsxseg = trampoline::vsxseg; - static constexpr auto& vector_vector_op = trampoline::vector_vector_op; - static constexpr auto& vector_imm_op = trampoline::vector_imm_op; - static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; - static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; - static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; - static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; - static constexpr auto& vector_extend = trampoline::vector_extend; - static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; - static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; - static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; - static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; - static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; - static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; - static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; - static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; - static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; - static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; - static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; - static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; - static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; - static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; - static constexpr auto& vector_red_op = trampoline::vector_red_op; - static constexpr auto& vector_red_wv = trampoline::vector_red_wv; - static constexpr auto& mask_mask_op = trampoline::mask_mask_op; - static constexpr auto& vcpop = trampoline::vcpop; - static constexpr auto& vfirst = trampoline::vfirst; - static constexpr auto& mask_set_op = trampoline::mask_set_op; - static constexpr auto& viota = trampoline::viota; - static constexpr auto& vid = trampoline::vid; - static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; - static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; - static constexpr auto& vector_slideup = trampoline::vector_slideup; - static constexpr auto& vector_slidedown = trampoline::vector_slidedown; - static constexpr auto& vector_slide1up = trampoline::vector_slide1up; - static constexpr auto& vector_slide1down = trampoline::vector_slide1down; - static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; - static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; - static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; - static constexpr auto& vector_compress = trampoline::vector_compress; - static constexpr auto& vector_whole_move = trampoline::vector_whole_move; - static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; - static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; - static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; - static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; - static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; - static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; - static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; - static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; - static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; - static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; - static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; - static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; - static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; - static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; - static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; - static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; - static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; - static constexpr auto& vector_unary_op = trampoline::vector_unary_op; + static constexpr auto& vlseg = softvec_if::vlseg; + static constexpr auto& vsseg = softvec_if::vsseg; + static constexpr auto& vlsseg = softvec_if::vlsseg; + static constexpr auto& vssseg = softvec_if::vssseg; + static constexpr auto& vlxseg = softvec_if::vlxseg; + static constexpr auto& vsxseg = softvec_if::vsxseg; + static constexpr auto& vector_vector_op = softvec_if::vector_vector_op; + static constexpr auto& vector_imm_op = softvec_if::vector_imm_op; + static constexpr auto& vector_vector_wv = softvec_if::vector_vector_wv; + static constexpr auto& vector_imm_wv = softvec_if::vector_imm_wv; + static constexpr auto& vector_vector_ww = softvec_if::vector_vector_ww; + static constexpr auto& vector_imm_ww = softvec_if::vector_imm_ww; + static constexpr auto& vector_extend = softvec_if::vector_extend; + static constexpr auto& vector_vector_carry = softvec_if::vector_vector_carry; + static constexpr auto& vector_imm_carry = softvec_if::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = softvec_if::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = softvec_if::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = softvec_if::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = softvec_if::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = softvec_if::vector_vector_vw; + static constexpr auto& vector_imm_vw = softvec_if::vector_imm_vw; + static constexpr auto& vector_vector_merge = softvec_if::vector_vector_merge; + static constexpr auto& vector_imm_merge = softvec_if::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = softvec_if::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = softvec_if::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = softvec_if::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = softvec_if::sat_vector_imm_vw; + static constexpr auto& vector_red_op = softvec_if::vector_red_op; + static constexpr auto& vector_red_wv = softvec_if::vector_red_wv; + static constexpr auto& mask_mask_op = softvec_if::mask_mask_op; + static constexpr auto& vcpop = softvec_if::vcpop; + static constexpr auto& vfirst = softvec_if::vfirst; + static constexpr auto& mask_set_op = softvec_if::mask_set_op; + static constexpr auto& viota = softvec_if::viota; + static constexpr auto& vid = softvec_if::vid; + static constexpr auto& scalar_to_vector = softvec_if::scalar_to_vector; + static constexpr auto& scalar_from_vector = softvec_if::scalar_from_vector; + static constexpr auto& vector_slideup = softvec_if::vector_slideup; + static constexpr auto& vector_slidedown = softvec_if::vector_slidedown; + static constexpr auto& vector_slide1up = softvec_if::vector_slide1up; + static constexpr auto& vector_slide1down = softvec_if::vector_slide1down; + static constexpr auto& vector_vector_gather = softvec_if::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = softvec_if::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = softvec_if::vector_imm_gather; + static constexpr auto& vector_compress = softvec_if::vector_compress; + static constexpr auto& vector_whole_move = softvec_if::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = softvec_if::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = softvec_if::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = softvec_if::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = softvec_if::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = softvec_if::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = softvec_if::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = softvec_if::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = softvec_if::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = softvec_if::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = softvec_if::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = softvec_if::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = softvec_if::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = softvec_if::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = softvec_if::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = softvec_if::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = softvec_if::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = softvec_if::fp_vector_unary_n; + static constexpr auto& vector_unary_op = softvec_if::vector_unary_op; vm_impl(); diff --git a/src/vm/asmjit/vm_rv64gcv.cpp b/src/vm/asmjit/vm_rv64gcv.cpp index 8ccda13..2250e88 100644 --- a/src/vm/asmjit/vm_rv64gcv.cpp +++ b/src/vm/asmjit/vm_rv64gcv.cpp @@ -29,7 +29,7 @@ * POSSIBILITY OF SUCH DAMAGE. * *******************************************************************************/ - + // clang-format off #include #include @@ -87,70 +87,70 @@ template class vm_impl : public iss::asmjit::vm_base { using addr_t = typename super::addr_t; - static constexpr auto& vlseg = trampoline::vlseg; - static constexpr auto& vsseg = trampoline::vsseg; - static constexpr auto& vlsseg = trampoline::vlsseg; - static constexpr auto& vssseg = trampoline::vssseg; - static constexpr auto& vlxseg = trampoline::vlxseg; - static constexpr auto& vsxseg = trampoline::vsxseg; - static constexpr auto& vector_vector_op = trampoline::vector_vector_op; - static constexpr auto& vector_imm_op = trampoline::vector_imm_op; - static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; - static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; - static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; - static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; - static constexpr auto& vector_extend = trampoline::vector_extend; - static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; - static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; - static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; - static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; - static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; - static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; - static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; - static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; - static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; - static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; - static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; - static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; - static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; - static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; - static constexpr auto& vector_red_op = trampoline::vector_red_op; - static constexpr auto& vector_red_wv = trampoline::vector_red_wv; - static constexpr auto& mask_mask_op = trampoline::mask_mask_op; - static constexpr auto& vcpop = trampoline::vcpop; - static constexpr auto& vfirst = trampoline::vfirst; - static constexpr auto& mask_set_op = trampoline::mask_set_op; - static constexpr auto& viota = trampoline::viota; - static constexpr auto& vid = trampoline::vid; - static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; - static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; - static constexpr auto& vector_slideup = trampoline::vector_slideup; - static constexpr auto& vector_slidedown = trampoline::vector_slidedown; - static constexpr auto& vector_slide1up = trampoline::vector_slide1up; - static constexpr auto& vector_slide1down = trampoline::vector_slide1down; - static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; - static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; - static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; - static constexpr auto& vector_compress = trampoline::vector_compress; - static constexpr auto& vector_whole_move = trampoline::vector_whole_move; - static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; - static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; - static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; - static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; - static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; - static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; - static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; - static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; - static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; - static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; - static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; - static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; - static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; - static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; - static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; - static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; - static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; - static constexpr auto& vector_unary_op = trampoline::vector_unary_op; + static constexpr auto& vlseg = softvec_if::vlseg; + static constexpr auto& vsseg = softvec_if::vsseg; + static constexpr auto& vlsseg = softvec_if::vlsseg; + static constexpr auto& vssseg = softvec_if::vssseg; + static constexpr auto& vlxseg = softvec_if::vlxseg; + static constexpr auto& vsxseg = softvec_if::vsxseg; + static constexpr auto& vector_vector_op = softvec_if::vector_vector_op; + static constexpr auto& vector_imm_op = softvec_if::vector_imm_op; + static constexpr auto& vector_vector_wv = softvec_if::vector_vector_wv; + static constexpr auto& vector_imm_wv = softvec_if::vector_imm_wv; + static constexpr auto& vector_vector_ww = softvec_if::vector_vector_ww; + static constexpr auto& vector_imm_ww = softvec_if::vector_imm_ww; + static constexpr auto& vector_extend = softvec_if::vector_extend; + static constexpr auto& vector_vector_carry = softvec_if::vector_vector_carry; + static constexpr auto& vector_imm_carry = softvec_if::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = softvec_if::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = softvec_if::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = softvec_if::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = softvec_if::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = softvec_if::vector_vector_vw; + static constexpr auto& vector_imm_vw = softvec_if::vector_imm_vw; + static constexpr auto& vector_vector_merge = softvec_if::vector_vector_merge; + static constexpr auto& vector_imm_merge = softvec_if::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = softvec_if::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = softvec_if::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = softvec_if::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = softvec_if::sat_vector_imm_vw; + static constexpr auto& vector_red_op = softvec_if::vector_red_op; + static constexpr auto& vector_red_wv = softvec_if::vector_red_wv; + static constexpr auto& mask_mask_op = softvec_if::mask_mask_op; + static constexpr auto& vcpop = softvec_if::vcpop; + static constexpr auto& vfirst = softvec_if::vfirst; + static constexpr auto& mask_set_op = softvec_if::mask_set_op; + static constexpr auto& viota = softvec_if::viota; + static constexpr auto& vid = softvec_if::vid; + static constexpr auto& scalar_to_vector = softvec_if::scalar_to_vector; + static constexpr auto& scalar_from_vector = softvec_if::scalar_from_vector; + static constexpr auto& vector_slideup = softvec_if::vector_slideup; + static constexpr auto& vector_slidedown = softvec_if::vector_slidedown; + static constexpr auto& vector_slide1up = softvec_if::vector_slide1up; + static constexpr auto& vector_slide1down = softvec_if::vector_slide1down; + static constexpr auto& vector_vector_gather = softvec_if::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = softvec_if::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = softvec_if::vector_imm_gather; + static constexpr auto& vector_compress = softvec_if::vector_compress; + static constexpr auto& vector_whole_move = softvec_if::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = softvec_if::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = softvec_if::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = softvec_if::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = softvec_if::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = softvec_if::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = softvec_if::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = softvec_if::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = softvec_if::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = softvec_if::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = softvec_if::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = softvec_if::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = softvec_if::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = softvec_if::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = softvec_if::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = softvec_if::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = softvec_if::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = softvec_if::fp_vector_unary_n; + static constexpr auto& vector_unary_op = softvec_if::vector_unary_op; vm_impl(); @@ -88077,8 +88077,8 @@ std::unique_ptr create(arch::rv64gcv *core, unsigned short } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp index 660fa8a..63b6bfb 100644 --- a/src/vm/interp/vm_rv32gcv.cpp +++ b/src/vm/interp/vm_rv32gcv.cpp @@ -84,70 +84,70 @@ template class vm_impl : public iss::interp::vm_base { using opcode_e = typename traits::opcode_e; - static constexpr auto& vlseg = trampoline::vlseg; - static constexpr auto& vsseg = trampoline::vsseg; - static constexpr auto& vlsseg = trampoline::vlsseg; - static constexpr auto& vssseg = trampoline::vssseg; - static constexpr auto& vlxseg = trampoline::vlxseg; - static constexpr auto& vsxseg = trampoline::vsxseg; - static constexpr auto& vector_vector_op = trampoline::vector_vector_op; - static constexpr auto& vector_imm_op = trampoline::vector_imm_op; - static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; - static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; - static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; - static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; - static constexpr auto& vector_extend = trampoline::vector_extend; - static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; - static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; - static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; - static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; - static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; - static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; - static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; - static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; - static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; - static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; - static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; - static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; - static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; - static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; - static constexpr auto& vector_red_op = trampoline::vector_red_op; - static constexpr auto& vector_red_wv = trampoline::vector_red_wv; - static constexpr auto& mask_mask_op = trampoline::mask_mask_op; - static constexpr auto& vcpop = trampoline::vcpop; - static constexpr auto& vfirst = trampoline::vfirst; - static constexpr auto& mask_set_op = trampoline::mask_set_op; - static constexpr auto& viota = trampoline::viota; - static constexpr auto& vid = trampoline::vid; - static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; - static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; - static constexpr auto& vector_slideup = trampoline::vector_slideup; - static constexpr auto& vector_slidedown = trampoline::vector_slidedown; - static constexpr auto& vector_slide1up = trampoline::vector_slide1up; - static constexpr auto& vector_slide1down = trampoline::vector_slide1down; - static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; - static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; - static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; - static constexpr auto& vector_compress = trampoline::vector_compress; - static constexpr auto& vector_whole_move = trampoline::vector_whole_move; - static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; - static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; - static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; - static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; - static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; - static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; - static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; - static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; - static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; - static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; - static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; - static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; - static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; - static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; - static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; - static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; - static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; - static constexpr auto& vector_unary_op = trampoline::vector_unary_op; + static constexpr auto& vlseg = softvec_if::vlseg; + static constexpr auto& vsseg = softvec_if::vsseg; + static constexpr auto& vlsseg = softvec_if::vlsseg; + static constexpr auto& vssseg = softvec_if::vssseg; + static constexpr auto& vlxseg = softvec_if::vlxseg; + static constexpr auto& vsxseg = softvec_if::vsxseg; + static constexpr auto& vector_vector_op = softvec_if::vector_vector_op; + static constexpr auto& vector_imm_op = softvec_if::vector_imm_op; + static constexpr auto& vector_vector_wv = softvec_if::vector_vector_wv; + static constexpr auto& vector_imm_wv = softvec_if::vector_imm_wv; + static constexpr auto& vector_vector_ww = softvec_if::vector_vector_ww; + static constexpr auto& vector_imm_ww = softvec_if::vector_imm_ww; + static constexpr auto& vector_extend = softvec_if::vector_extend; + static constexpr auto& vector_vector_carry = softvec_if::vector_vector_carry; + static constexpr auto& vector_imm_carry = softvec_if::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = softvec_if::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = softvec_if::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = softvec_if::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = softvec_if::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = softvec_if::vector_vector_vw; + static constexpr auto& vector_imm_vw = softvec_if::vector_imm_vw; + static constexpr auto& vector_vector_merge = softvec_if::vector_vector_merge; + static constexpr auto& vector_imm_merge = softvec_if::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = softvec_if::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = softvec_if::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = softvec_if::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = softvec_if::sat_vector_imm_vw; + static constexpr auto& vector_red_op = softvec_if::vector_red_op; + static constexpr auto& vector_red_wv = softvec_if::vector_red_wv; + static constexpr auto& mask_mask_op = softvec_if::mask_mask_op; + static constexpr auto& vcpop = softvec_if::vcpop; + static constexpr auto& vfirst = softvec_if::vfirst; + static constexpr auto& mask_set_op = softvec_if::mask_set_op; + static constexpr auto& viota = softvec_if::viota; + static constexpr auto& vid = softvec_if::vid; + static constexpr auto& scalar_to_vector = softvec_if::scalar_to_vector; + static constexpr auto& scalar_from_vector = softvec_if::scalar_from_vector; + static constexpr auto& vector_slideup = softvec_if::vector_slideup; + static constexpr auto& vector_slidedown = softvec_if::vector_slidedown; + static constexpr auto& vector_slide1up = softvec_if::vector_slide1up; + static constexpr auto& vector_slide1down = softvec_if::vector_slide1down; + static constexpr auto& vector_vector_gather = softvec_if::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = softvec_if::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = softvec_if::vector_imm_gather; + static constexpr auto& vector_compress = softvec_if::vector_compress; + static constexpr auto& vector_whole_move = softvec_if::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = softvec_if::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = softvec_if::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = softvec_if::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = softvec_if::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = softvec_if::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = softvec_if::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = softvec_if::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = softvec_if::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = softvec_if::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = softvec_if::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = softvec_if::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = softvec_if::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = softvec_if::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = softvec_if::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = softvec_if::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = softvec_if::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = softvec_if::fp_vector_unary_n; + static constexpr auto& vector_unary_op = softvec_if::vector_unary_op; vm_impl(); @@ -29797,8 +29797,8 @@ std::unique_ptr create(arch::rv32gcv *core, unsigned short } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp index 0d069e1..b35699b 100644 --- a/src/vm/interp/vm_rv64gcv.cpp +++ b/src/vm/interp/vm_rv64gcv.cpp @@ -84,70 +84,70 @@ template class vm_impl : public iss::interp::vm_base { using opcode_e = typename traits::opcode_e; - static constexpr auto& vlseg = trampoline::vlseg; - static constexpr auto& vsseg = trampoline::vsseg; - static constexpr auto& vlsseg = trampoline::vlsseg; - static constexpr auto& vssseg = trampoline::vssseg; - static constexpr auto& vlxseg = trampoline::vlxseg; - static constexpr auto& vsxseg = trampoline::vsxseg; - static constexpr auto& vector_vector_op = trampoline::vector_vector_op; - static constexpr auto& vector_imm_op = trampoline::vector_imm_op; - static constexpr auto& vector_vector_wv = trampoline::vector_vector_wv; - static constexpr auto& vector_imm_wv = trampoline::vector_imm_wv; - static constexpr auto& vector_vector_ww = trampoline::vector_vector_ww; - static constexpr auto& vector_imm_ww = trampoline::vector_imm_ww; - static constexpr auto& vector_extend = trampoline::vector_extend; - static constexpr auto& vector_vector_carry = trampoline::vector_vector_carry; - static constexpr auto& vector_imm_carry = trampoline::vector_imm_carry; - static constexpr auto& carry_vector_vector_op = trampoline::carry_vector_vector_op; - static constexpr auto& carry_vector_imm_op = trampoline::carry_vector_imm_op; - static constexpr auto& mask_vector_vector_op = trampoline::mask_vector_vector_op; - static constexpr auto& mask_vector_imm_op = trampoline::mask_vector_imm_op; - static constexpr auto& vector_vector_vw = trampoline::vector_vector_vw; - static constexpr auto& vector_imm_vw = trampoline::vector_imm_vw; - static constexpr auto& vector_vector_merge = trampoline::vector_vector_merge; - static constexpr auto& vector_imm_merge = trampoline::vector_imm_merge; - static constexpr auto& sat_vector_vector_op = trampoline::sat_vector_vector_op; - static constexpr auto& sat_vector_imm_op = trampoline::sat_vector_imm_op; - static constexpr auto& sat_vector_vector_vw = trampoline::sat_vector_vector_vw; - static constexpr auto& sat_vector_imm_vw = trampoline::sat_vector_imm_vw; - static constexpr auto& vector_red_op = trampoline::vector_red_op; - static constexpr auto& vector_red_wv = trampoline::vector_red_wv; - static constexpr auto& mask_mask_op = trampoline::mask_mask_op; - static constexpr auto& vcpop = trampoline::vcpop; - static constexpr auto& vfirst = trampoline::vfirst; - static constexpr auto& mask_set_op = trampoline::mask_set_op; - static constexpr auto& viota = trampoline::viota; - static constexpr auto& vid = trampoline::vid; - static constexpr auto& scalar_to_vector = trampoline::scalar_to_vector; - static constexpr auto& scalar_from_vector = trampoline::scalar_from_vector; - static constexpr auto& vector_slideup = trampoline::vector_slideup; - static constexpr auto& vector_slidedown = trampoline::vector_slidedown; - static constexpr auto& vector_slide1up = trampoline::vector_slide1up; - static constexpr auto& vector_slide1down = trampoline::vector_slide1down; - static constexpr auto& vector_vector_gather = trampoline::vector_vector_gather; - static constexpr auto& vector_vector_gatherei16 = trampoline::vector_vector_gatherei16; - static constexpr auto& vector_imm_gather = trampoline::vector_imm_gather; - static constexpr auto& vector_compress = trampoline::vector_compress; - static constexpr auto& vector_whole_move = trampoline::vector_whole_move; - static constexpr auto& fp_scalar_from_vector = trampoline::fp_scalar_from_vector; - static constexpr auto& fp_vector_slide1up = trampoline::fp_vector_slide1up; - static constexpr auto& fp_vector_slide1down = trampoline::fp_vector_slide1down; - static constexpr auto& fp_vector_red_op = trampoline::fp_vector_red_op; - static constexpr auto& fp_vector_red_wv = trampoline::fp_vector_red_wv; - static constexpr auto& fp_vector_vector_op = trampoline::fp_vector_vector_op; - static constexpr auto& fp_vector_imm_op = trampoline::fp_vector_imm_op; - static constexpr auto& fp_vector_vector_wv = trampoline::fp_vector_vector_wv; - static constexpr auto& fp_vector_imm_wv = trampoline::fp_vector_imm_wv; - static constexpr auto& fp_vector_vector_ww = trampoline::fp_vector_vector_ww; - static constexpr auto& fp_vector_imm_ww = trampoline::fp_vector_imm_ww; - static constexpr auto& fp_vector_unary_op = trampoline::fp_vector_unary_op; - static constexpr auto& mask_fp_vector_vector_op = trampoline::mask_fp_vector_vector_op; - static constexpr auto& mask_fp_vector_imm_op = trampoline::mask_fp_vector_imm_op; - static constexpr auto& fp_vector_imm_merge = trampoline::fp_vector_imm_merge; - static constexpr auto& fp_vector_unary_w = trampoline::fp_vector_unary_w; - static constexpr auto& fp_vector_unary_n = trampoline::fp_vector_unary_n; - static constexpr auto& vector_unary_op = trampoline::vector_unary_op; + static constexpr auto& vlseg = softvec_if::vlseg; + static constexpr auto& vsseg = softvec_if::vsseg; + static constexpr auto& vlsseg = softvec_if::vlsseg; + static constexpr auto& vssseg = softvec_if::vssseg; + static constexpr auto& vlxseg = softvec_if::vlxseg; + static constexpr auto& vsxseg = softvec_if::vsxseg; + static constexpr auto& vector_vector_op = softvec_if::vector_vector_op; + static constexpr auto& vector_imm_op = softvec_if::vector_imm_op; + static constexpr auto& vector_vector_wv = softvec_if::vector_vector_wv; + static constexpr auto& vector_imm_wv = softvec_if::vector_imm_wv; + static constexpr auto& vector_vector_ww = softvec_if::vector_vector_ww; + static constexpr auto& vector_imm_ww = softvec_if::vector_imm_ww; + static constexpr auto& vector_extend = softvec_if::vector_extend; + static constexpr auto& vector_vector_carry = softvec_if::vector_vector_carry; + static constexpr auto& vector_imm_carry = softvec_if::vector_imm_carry; + static constexpr auto& carry_vector_vector_op = softvec_if::carry_vector_vector_op; + static constexpr auto& carry_vector_imm_op = softvec_if::carry_vector_imm_op; + static constexpr auto& mask_vector_vector_op = softvec_if::mask_vector_vector_op; + static constexpr auto& mask_vector_imm_op = softvec_if::mask_vector_imm_op; + static constexpr auto& vector_vector_vw = softvec_if::vector_vector_vw; + static constexpr auto& vector_imm_vw = softvec_if::vector_imm_vw; + static constexpr auto& vector_vector_merge = softvec_if::vector_vector_merge; + static constexpr auto& vector_imm_merge = softvec_if::vector_imm_merge; + static constexpr auto& sat_vector_vector_op = softvec_if::sat_vector_vector_op; + static constexpr auto& sat_vector_imm_op = softvec_if::sat_vector_imm_op; + static constexpr auto& sat_vector_vector_vw = softvec_if::sat_vector_vector_vw; + static constexpr auto& sat_vector_imm_vw = softvec_if::sat_vector_imm_vw; + static constexpr auto& vector_red_op = softvec_if::vector_red_op; + static constexpr auto& vector_red_wv = softvec_if::vector_red_wv; + static constexpr auto& mask_mask_op = softvec_if::mask_mask_op; + static constexpr auto& vcpop = softvec_if::vcpop; + static constexpr auto& vfirst = softvec_if::vfirst; + static constexpr auto& mask_set_op = softvec_if::mask_set_op; + static constexpr auto& viota = softvec_if::viota; + static constexpr auto& vid = softvec_if::vid; + static constexpr auto& scalar_to_vector = softvec_if::scalar_to_vector; + static constexpr auto& scalar_from_vector = softvec_if::scalar_from_vector; + static constexpr auto& vector_slideup = softvec_if::vector_slideup; + static constexpr auto& vector_slidedown = softvec_if::vector_slidedown; + static constexpr auto& vector_slide1up = softvec_if::vector_slide1up; + static constexpr auto& vector_slide1down = softvec_if::vector_slide1down; + static constexpr auto& vector_vector_gather = softvec_if::vector_vector_gather; + static constexpr auto& vector_vector_gatherei16 = softvec_if::vector_vector_gatherei16; + static constexpr auto& vector_imm_gather = softvec_if::vector_imm_gather; + static constexpr auto& vector_compress = softvec_if::vector_compress; + static constexpr auto& vector_whole_move = softvec_if::vector_whole_move; + static constexpr auto& fp_scalar_from_vector = softvec_if::fp_scalar_from_vector; + static constexpr auto& fp_vector_slide1up = softvec_if::fp_vector_slide1up; + static constexpr auto& fp_vector_slide1down = softvec_if::fp_vector_slide1down; + static constexpr auto& fp_vector_red_op = softvec_if::fp_vector_red_op; + static constexpr auto& fp_vector_red_wv = softvec_if::fp_vector_red_wv; + static constexpr auto& fp_vector_vector_op = softvec_if::fp_vector_vector_op; + static constexpr auto& fp_vector_imm_op = softvec_if::fp_vector_imm_op; + static constexpr auto& fp_vector_vector_wv = softvec_if::fp_vector_vector_wv; + static constexpr auto& fp_vector_imm_wv = softvec_if::fp_vector_imm_wv; + static constexpr auto& fp_vector_vector_ww = softvec_if::fp_vector_vector_ww; + static constexpr auto& fp_vector_imm_ww = softvec_if::fp_vector_imm_ww; + static constexpr auto& fp_vector_unary_op = softvec_if::fp_vector_unary_op; + static constexpr auto& mask_fp_vector_vector_op = softvec_if::mask_fp_vector_vector_op; + static constexpr auto& mask_fp_vector_imm_op = softvec_if::mask_fp_vector_imm_op; + static constexpr auto& fp_vector_imm_merge = softvec_if::fp_vector_imm_merge; + static constexpr auto& fp_vector_unary_w = softvec_if::fp_vector_unary_w; + static constexpr auto& fp_vector_unary_n = softvec_if::fp_vector_unary_n; + static constexpr auto& vector_unary_op = softvec_if::vector_unary_op; vm_impl(); @@ -31140,8 +31140,8 @@ std::unique_ptr create(arch::rv64gcv *core, unsigned short } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/new_vector_functions.h b/src/vm/new_vector_functions.h index 33a7055..7f35a90 100644 --- a/src/vm/new_vector_functions.h +++ b/src/vm/new_vector_functions.h @@ -42,7 +42,7 @@ #include "iss/vm_types.h" #include -namespace trampoline { +namespace softvec_if { using indexed_load_store_t = std::function, uint8_t*, uint64_t, uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; template indexed_load_store_t getFunction() { @@ -985,5 +985,5 @@ void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, throw new std::runtime_error("Unsupported sew_val"); } } -} // namespace trampoline +} // namespace softvec_if #endif /* RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ */ From 2499b1117f85d0958db2bb72f9a3d7b511d01952 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 25 Sep 2025 08:48:10 +0200 Subject: [PATCH 020/230] moves functionality into softvector, adjust names --- .gitmodules | 3 + gen_input/templates/asmjit/CORENAME.cpp.gtl | 4 +- gen_input/templates/interp/CORENAME.cpp.gtl | 4 +- gen_input/templates/llvm/CORENAME.cpp.gtl | 2 +- softvector | 1 + src/vm/asmjit/vm_rv32gc.cpp | 4 +- src/vm/asmjit/vm_rv32gcv.cpp | 4 +- src/vm/asmjit/vm_rv64gc.cpp | 4 +- src/vm/asmjit/vm_rv64gcv.cpp | 4 +- src/vm/fp_functions.cpp | 948 -------- src/vm/fp_functions.h | 125 - src/vm/interp/vm_rv32gc.cpp | 4 +- src/vm/interp/vm_rv32gcv.cpp | 4 +- src/vm/interp/vm_rv64gc.cpp | 4 +- src/vm/interp/vm_rv64gcv.cpp | 4 +- src/vm/llvm/vm_rv32gc.cpp | 4 +- src/vm/llvm/vm_rv64gc.cpp | 4 +- src/vm/new_vector_functions.h | 989 -------- src/vm/vector_functions.cpp | 394 ---- src/vm/vector_functions.h | 1099 +++++++-- src/vm/vector_functions.hpp | 2281 ------------------- 21 files changed, 980 insertions(+), 4910 deletions(-) create mode 160000 softvector delete mode 100644 src/vm/fp_functions.cpp delete mode 100644 src/vm/fp_functions.h delete mode 100644 src/vm/new_vector_functions.h delete mode 100644 src/vm/vector_functions.cpp delete mode 100644 src/vm/vector_functions.hpp diff --git a/.gitmodules b/.gitmodules index e55fe4f..57198f4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "gen_input/ISA"] path = gen_input/ISA url = https://github.com/Minres/RISCV_ISA_CoreDSL.git +[submodule "softvector"] + path = softvector + url = https://github.com/Minres/softvector.git diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 7b56d9e..e558bb8 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -48,10 +48,10 @@ def nativeTypeSize(int size){ #include <% if(floating_point) {%> -#include +#include <%} if(vector){%> -#include +#include <%} if(aes) {%> #include diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 784f8b7..00d5f0c 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -46,10 +46,10 @@ def nativeTypeSize(int size){ #include <% if(floating_point) {%> -#include +#include <%} if(vector) {%> -#include +#include <%} if(aes) {%> #include diff --git a/gen_input/templates/llvm/CORENAME.cpp.gtl b/gen_input/templates/llvm/CORENAME.cpp.gtl index fff12b6..3b63455 100644 --- a/gen_input/templates/llvm/CORENAME.cpp.gtl +++ b/gen_input/templates/llvm/CORENAME.cpp.gtl @@ -41,7 +41,7 @@ #include <%def fcsr = registers.find {it.name=='FCSR'} if(fcsr != null) {%> -#include <%}%> +#include <%}%> #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif diff --git a/softvector b/softvector new file mode 160000 index 0000000..f0f7cfb --- /dev/null +++ b/softvector @@ -0,0 +1 @@ +Subproject commit f0f7cfbb20adf67bbe5e3688051dab1cd7320be1 diff --git a/src/vm/asmjit/vm_rv32gc.cpp b/src/vm/asmjit/vm_rv32gc.cpp index 533bfaa..1b97374 100644 --- a/src/vm/asmjit/vm_rv32gc.cpp +++ b/src/vm/asmjit/vm_rv32gc.cpp @@ -39,7 +39,7 @@ #include #include -#include +#include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif @@ -10091,8 +10091,8 @@ std::unique_ptr create(arch::rv32gc *core, unsigned short p } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/asmjit/vm_rv32gcv.cpp b/src/vm/asmjit/vm_rv32gcv.cpp index 3638d04..9470b31 100644 --- a/src/vm/asmjit/vm_rv32gcv.cpp +++ b/src/vm/asmjit/vm_rv32gcv.cpp @@ -40,9 +40,9 @@ #include #include -#include +#include -#include +#include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY diff --git a/src/vm/asmjit/vm_rv64gc.cpp b/src/vm/asmjit/vm_rv64gc.cpp index 1b6da5a..3e9da7b 100644 --- a/src/vm/asmjit/vm_rv64gc.cpp +++ b/src/vm/asmjit/vm_rv64gc.cpp @@ -39,7 +39,7 @@ #include #include -#include +#include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif @@ -12672,8 +12672,8 @@ std::unique_ptr create(arch::rv64gc *core, unsigned short p } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/asmjit/vm_rv64gcv.cpp b/src/vm/asmjit/vm_rv64gcv.cpp index 2250e88..80ebf7c 100644 --- a/src/vm/asmjit/vm_rv64gcv.cpp +++ b/src/vm/asmjit/vm_rv64gcv.cpp @@ -40,9 +40,9 @@ #include #include -#include +#include -#include +#include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY diff --git a/src/vm/fp_functions.cpp b/src/vm/fp_functions.cpp deleted file mode 100644 index c16b175..0000000 --- a/src/vm/fp_functions.cpp +++ /dev/null @@ -1,948 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2017, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -// Contributors: -// eyck@minres.com - initial API and implementation -//////////////////////////////////////////////////////////////////////////////// - -#include "fp_functions.h" -#include "softfloat_types.h" -#include -#include - -extern "C" { -#include "internals.h" -#include "specialize.h" -#include -} - -#include - -using this_t = uint8_t*; -template T constexpr defaultNaN(); -template <> uint16_t constexpr defaultNaN() { return defaultNaNF16UI; } -template <> uint32_t constexpr defaultNaN() { return defaultNaNF32UI; } -template <> uint64_t constexpr defaultNaN() { return defaultNaNF64UI; } -template T constexpr posInf(); -template <> uint16_t constexpr posInf() { return 0x7C00; } -template <> uint32_t constexpr posInf() { return 0x7F800000; } -template <> uint64_t constexpr posInf() { return 0x7FF0000000000000; } -template T constexpr negInf(); -template <> uint16_t constexpr negInf() { return 0xFC00; } -template <> uint32_t constexpr negInf() { return 0xFF800000; } -template <> uint64_t constexpr negInf() { return 0xFFF0000000000000; } -template T constexpr negZero(); -template <> uint16_t constexpr negZero() { return 0x8000; } -template <> uint32_t constexpr negZero() { return 0x80000000; } -template <> uint64_t constexpr negZero() { return 0x8000000000000000; } -// this does not inlcude any reserved rm or the DYN rm, as DYN rm should be taken care of in the vm_impl -template bool rsqrt_check(T fclass_val, bool& subnormal, T& ret_val) { - softfloat_exceptionFlags = 0; - switch(fclass_val) { - case 0x0001: { - softfloat_exceptionFlags |= softfloat_flag_invalid; - ret_val = defaultNaN(); - return true; - } - case 0x0002: { - softfloat_exceptionFlags |= softfloat_flag_invalid; - ret_val = defaultNaN(); - return true; - } - case 0x0004: { - softfloat_exceptionFlags |= softfloat_flag_invalid; - ret_val = defaultNaN(); - return true; - } - case 0x0100: { - softfloat_exceptionFlags |= softfloat_flag_invalid; - ret_val = defaultNaN(); - return true; - } - case 0x0200: { - ret_val = defaultNaN(); - return true; - } - case 0x0008: { - softfloat_exceptionFlags |= softfloat_flag_infinite; - ret_val = negInf(); - return true; - } - case 0x0010: { - softfloat_exceptionFlags |= softfloat_flag_infinite; - ret_val = posInf(); - return true; - } - case 0x0080: { - ret_val = 0; - return true; - } - case 0x0020: { - subnormal = true; - } - default: - return false; - } -} -static constexpr std::array, 2> rsqrt_table{ - {{ - 52, 51, 50, 48, 47, 46, 44, 43, 42, 41, 40, 39, 38, 36, 35, 34, 33, 32, 31, 30, 30, 29, 28, 27, 26, 25, 24, 23, 23, 22, 21, 20, - 19, 19, 18, 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 9, 9, 8, 7, 7, 6, 6, 5, 4, 4, 3, 3, 2, 2, 1, 1, 0, - }, - {127, 125, 123, 121, 119, 118, 116, 114, 113, 111, 109, 108, 106, 105, 103, 102, 100, 99, 97, 96, 95, 93, - 92, 91, 90, 88, 87, 86, 85, 84, 83, 82, 80, 79, 78, 77, 76, 75, 74, 73, 72, 71, 70, 70, - 69, 68, 67, 66, 65, 64, 63, 63, 62, 61, 60, 59, 59, 58, 57, 56, 56, 55, 54, 53}}}; - -uint64_t constexpr frsqrt7_general(const unsigned s, const unsigned e, const uint64_t sign, const int64_t exp, const uint64_t sig, - const bool subnormal) { - int64_t normalized_exp = exp; - uint64_t normalized_sig = sig; - if(subnormal) { - signed nr_leadingzeros = __builtin_clzll(sig) - (64 - s); - normalized_exp = -nr_leadingzeros; - normalized_sig = (sig << (1 + nr_leadingzeros)) & ((1ULL << s) - 1); - } - unsigned exp_idx = normalized_exp & 1; - unsigned sig_idx = (normalized_sig >> (s - 6)) & 0x3f; - // The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the - // result significand is zero. - uint64_t out_sig = rsqrt_table[exp_idx][sig_idx] << (s - 7); - // The output exponent equals floor((3*B - 1 - the normalized input exponent) / 2), where B is the exponent bias. - unsigned bias = (1UL << (e - 1)) - 1; - uint64_t out_exp = (3 * bias - 1 - normalized_exp) / 2; - // The output sign equals the input sign. - return (sign << (s + e)) | (out_exp << s) | out_sig; -} -template bool recip_check(T fclass_val, bool& subnormal, uint64_t& ret_val) { - softfloat_exceptionFlags = 0; - switch(fclass_val) { - case 0x0001: { - ret_val = negZero(); - return true; - } - case 0x0080: { - ret_val = 0; - return true; - } - case 0x0008: { - softfloat_exceptionFlags |= softfloat_flag_infinite; - ret_val = negInf(); - return true; - } - case 0x0010: { - softfloat_exceptionFlags |= softfloat_flag_infinite; - ret_val = posInf(); - return true; - } - case 0x0100: { - softfloat_exceptionFlags |= softfloat_flag_invalid; - ret_val = defaultNaN(); - return true; - } - case 0x0200: { - ret_val = defaultNaN(); - return true; - } - case 0x0004: { - subnormal = true; - return false; - } - case 0x0020: { - subnormal = true; - return false; - } - default: { - subnormal = false; - return false; - } - } -} -static constexpr std::array rec_table{ - {127, 125, 123, 121, 119, 117, 116, 114, 112, 110, 109, 107, 105, 104, 102, 100, 99, 97, 96, 94, 93, 91, 90, 88, 87, 85, - 84, 83, 81, 80, 79, 77, 76, 75, 74, 72, 71, 70, 69, 68, 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, - 54, 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 40, 39, 38, 37, 36, 35, 35, 34, 33, 32, 31, - 31, 30, 29, 28, 28, 27, 26, 25, 25, 24, 23, 23, 22, 21, 21, 20, 19, 19, 18, 17, 17, 16, 15, 15, 14, 14, - 13, 12, 12, 11, 11, 10, 9, 9, 8, 8, 7, 7, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1, 0}}; -bool frec_general(uint64_t& res, const unsigned s, const unsigned e, const uint64_t sign, const int64_t exp, const uint64_t sig, - const bool subnormal, uint8_t mode) { - int nr_leadingzeros = __builtin_clzll(sig) - (64 - s); - int64_t normalized_exp = subnormal ? -nr_leadingzeros : exp; - uint64_t normalized_sig = subnormal ? ((sig << (1 + nr_leadingzeros)) & ((1ULL << s) - 1)) : sig; - unsigned idx = (normalized_sig >> (s - 7)) & 0x7f; - unsigned bias = (1UL << (e - 1)) - 1; - uint64_t mid_exp = 2 * (bias)-1 - normalized_exp; - uint64_t mid_sig = rec_table[idx] << (s - 7); - - uint64_t out_exp = mid_exp; - uint64_t out_sig = mid_sig; - if(mid_exp == 0) { - out_exp = mid_exp; - out_sig = (mid_sig >> 1) | (1ULL << (s - 1)); - } else if(mid_exp == (1ULL << e) - 1) { - out_exp = 0; - out_sig = (mid_sig >> 2) | (1ULL << (s - 2)); - } - if(subnormal && nr_leadingzeros > 1) { - if((mode == 0b001) || (mode == 0b010 && sign == 0b0) || (mode == 0b011 && sign == 0b1)) { - res = (sign << (s + e)) | ((1ULL << (e - 1)) - 1) << s | ((1ULL << s) - 1); - return true; - } else { - res = (sign << (s + e)) | ((1ULL << e) - 1) << s; - return true; - } - } - res = (sign << (s + e)) | (out_exp << s) | out_sig; - return false; -} - -extern "C" { - -uint32_t fget_flags() { return softfloat_exceptionFlags & 0x1f; } -uint16_t fadd_h(uint16_t v1, uint16_t v2, uint8_t mode) { - float16_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float16_t r = f16_add(v1f, v2f); - return r.v; -} - -uint16_t fsub_h(uint16_t v1, uint16_t v2, uint8_t mode) { - float16_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float16_t r = f16_sub(v1f, v2f); - return r.v; -} - -uint16_t fmul_h(uint16_t v1, uint16_t v2, uint8_t mode) { - float16_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float16_t r = f16_mul(v1f, v2f); - return r.v; -} - -uint16_t fdiv_h(uint16_t v1, uint16_t v2, uint8_t mode) { - float16_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float16_t r = f16_div(v1f, v2f); - return r.v; -} - -uint16_t fsqrt_h(uint16_t v1, uint8_t mode) { - float16_t v1f{v1}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float16_t r = f16_sqrt(v1f); - return r.v; -} - -uint16_t fcmp_h(uint16_t v1, uint16_t v2, uint16_t op) { - float16_t v1f{v1}, v2f{v2}; - softfloat_exceptionFlags = 0; - bool nan = v1 == defaultNaNF16UI || v2 & defaultNaNF16UI; - bool snan = softfloat_isSigNaNF16UI(v1) || softfloat_isSigNaNF16UI(v2); - switch(op) { - case 0: - if(nan | snan) { - if(snan) - softfloat_raiseFlags(softfloat_flag_invalid); - return 0; - } else - return f16_eq(v1f, v2f) ? 1 : 0; - case 1: - if(nan | snan) { - softfloat_raiseFlags(softfloat_flag_invalid); - return 0; - } else - return f16_le(v1f, v2f) ? 1 : 0; - case 2: - if(nan | snan) { - softfloat_raiseFlags(softfloat_flag_invalid); - return 0; - } else - return f16_lt(v1f, v2f) ? 1 : 0; - default: - break; - } - return -1; -} - -uint16_t fmadd_h(uint16_t v1, uint16_t v2, uint16_t v3, uint16_t op, uint8_t mode) { - uint16_t F16_SIGN = 1UL << 15; - switch(op) { - case 0: // FMADD_S - break; - case 1: // FMSUB_S - v3 ^= F16_SIGN; - break; - case 2: // FNMADD_S - v1 ^= F16_SIGN; - v3 ^= F16_SIGN; - break; - case 3: // FNMSUB_S - v1 ^= F16_SIGN; - break; - } - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float16_t res = softfloat_mulAddF16(v1, v2, v3, 0); - return res.v; -} - -uint16_t fsel_h(uint16_t v1, uint16_t v2, uint16_t op) { - softfloat_exceptionFlags = 0; - bool v1_nan = (v1 & defaultNaNF16UI) == defaultNaNF16UI; - bool v2_nan = (v2 & defaultNaNF16UI) == defaultNaNF16UI; - bool v1_snan = softfloat_isSigNaNF16UI(v1); - bool v2_snan = softfloat_isSigNaNF16UI(v2); - if(v1_snan || v2_snan) - softfloat_raiseFlags(softfloat_flag_invalid); - if(v1_nan || v1_snan) - return (v2_nan || v2_snan) ? defaultNaNF16UI : v2; - else if(v2_nan || v2_snan) - return v1; - else { - if((v1 & 0x7fff) == 0 && (v2 & 0x7fff) == 0) { - return op == 0 ? ((v1 & 0x8000) ? v1 : v2) : ((v1 & 0x8000) ? v2 : v1); - } else { - float16_t v1f{v1}, v2f{v2}; - return op == 0 ? (f16_lt(v1f, v2f) ? v1 : v2) : (f16_lt(v1f, v2f) ? v2 : v1); - } - } -} - -uint16_t fclass_h(uint16_t v1) { - - float16_t a{v1}; - union ui16_f16 uA; - uint_fast16_t uiA; - - uA.f = a; - uiA = uA.ui; - - bool infOrNaN = expF16UI(uiA) == 0x1F; - bool subnormalOrZero = expF16UI(uiA) == 0; - bool sign = signF16UI(uiA); - bool fracZero = fracF16UI(uiA) == 0; - bool isNaN = isNaNF16UI(uiA); - bool isSNaN = softfloat_isSigNaNF16UI(uiA); - - return (sign && infOrNaN && fracZero) << 0 | (sign && !infOrNaN && !subnormalOrZero) << 1 | - (sign && subnormalOrZero && !fracZero) << 2 | (sign && subnormalOrZero && fracZero) << 3 | (!sign && infOrNaN && fracZero) << 7 | - (!sign && !infOrNaN && !subnormalOrZero) << 6 | (!sign && subnormalOrZero && !fracZero) << 5 | - (!sign && subnormalOrZero && fracZero) << 4 | (isNaN && isSNaN) << 8 | (isNaN && !isSNaN) << 9; -} - -uint16_t frsqrt7_h(uint16_t v) { - bool subnormal = false; - uint16_t ret_val = 0; - if(rsqrt_check(fclass_h(v), subnormal, ret_val)) { - return ret_val; - } - uint16_t sig = fracF64UI(v); - int16_t exp = expF64UI(v); - uint16_t sign = signF64UI(v); - unsigned constexpr e = 5; - unsigned constexpr s = 10; - return frsqrt7_general(s, e, sign, exp, sig, subnormal); -} - -uint16_t frec7_h(uint16_t v, uint8_t mode) { - bool subnormal = false; - uint64_t ret_val = 0; - if(recip_check(fclass_h(v), subnormal, ret_val)) { - return ret_val; - } - uint16_t sig = fracF16UI(v); - int exp = expF16UI(v); - uint16_t sign = signF16UI(v); - unsigned constexpr e = 5; - unsigned constexpr s = 10; - if(frec_general(ret_val, s, e, sign, exp, sig, subnormal, mode)) - softfloat_exceptionFlags |= (softfloat_flag_inexact | softfloat_flag_overflow); - return ret_val; -} - -uint16_t unbox_h(uint8_t FLEN, uint64_t v) { - uint64_t mask = 0; - switch(FLEN) { - case 32: { - mask = std::numeric_limits::max() & ~((uint64_t)std::numeric_limits::max()); - break; - } - case 64: { - mask = std::numeric_limits::max() & ~((uint64_t)std::numeric_limits::max()); - break; - } - default: - break; - } - if((v & mask) != mask) - return defaultNaNF16UI; - else - return v & std::numeric_limits::max(); -} - -uint32_t fadd_s(uint32_t v1, uint32_t v2, uint8_t mode) { - float32_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float32_t r = f32_add(v1f, v2f); - return r.v; -} - -uint32_t fsub_s(uint32_t v1, uint32_t v2, uint8_t mode) { - float32_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float32_t r = f32_sub(v1f, v2f); - return r.v; -} - -uint32_t fmul_s(uint32_t v1, uint32_t v2, uint8_t mode) { - float32_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float32_t r = f32_mul(v1f, v2f); - return r.v; -} - -uint32_t fdiv_s(uint32_t v1, uint32_t v2, uint8_t mode) { - float32_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float32_t r = f32_div(v1f, v2f); - return r.v; -} - -uint32_t fsqrt_s(uint32_t v1, uint8_t mode) { - float32_t v1f{v1}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float32_t r = f32_sqrt(v1f); - return r.v; -} - -uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) { - float32_t v1f{v1}, v2f{v2}; - softfloat_exceptionFlags = 0; - bool nan = v1 == defaultNaNF32UI || v2 == defaultNaNF32UI; - bool snan = softfloat_isSigNaNF32UI(v1) || softfloat_isSigNaNF32UI(v2); - switch(op) { - case 0: - if(nan | snan) { - if(snan) - softfloat_raiseFlags(softfloat_flag_invalid); - return 0; - } else - return f32_eq(v1f, v2f) ? 1 : 0; - case 1: - if(nan | snan) { - softfloat_raiseFlags(softfloat_flag_invalid); - return 0; - } else - return f32_le(v1f, v2f) ? 1 : 0; - case 2: - if(nan | snan) { - softfloat_raiseFlags(softfloat_flag_invalid); - return 0; - } else - return f32_lt(v1f, v2f) ? 1 : 0; - default: - break; - } - return -1; -} - -uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode) { - uint32_t F32_SIGN = 1UL << 31; - switch(op) { - case 0: // FMADD_S - break; - case 1: // FMSUB_S - v3 ^= F32_SIGN; - break; - case 2: // FNMADD_S - v1 ^= F32_SIGN; - v3 ^= F32_SIGN; - break; - case 3: // FNMSUB_S - v1 ^= F32_SIGN; - break; - } - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float32_t res = softfloat_mulAddF32(v1, v2, v3, 0); - return res.v; -} - -uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op) { - softfloat_exceptionFlags = 0; - bool v1_nan = (v1 & defaultNaNF32UI) == defaultNaNF32UI; - bool v2_nan = (v2 & defaultNaNF32UI) == defaultNaNF32UI; - bool v1_snan = softfloat_isSigNaNF32UI(v1); - bool v2_snan = softfloat_isSigNaNF32UI(v2); - if(v1_snan || v2_snan) - softfloat_raiseFlags(softfloat_flag_invalid); - if(v1_nan || v1_snan) - return (v2_nan || v2_snan) ? defaultNaNF32UI : v2; - else if(v2_nan || v2_snan) - return v1; - else { - if((v1 & 0x7fffffff) == 0 && (v2 & 0x7fffffff) == 0) { - return op == 0 ? ((v1 & 0x80000000) ? v1 : v2) : ((v1 & 0x80000000) ? v2 : v1); - } else { - float32_t v1f{v1}, v2f{v2}; - return op == 0 ? (f32_lt(v1f, v2f) ? v1 : v2) : (f32_lt(v1f, v2f) ? v2 : v1); - } - } -} - -uint32_t fclass_s(uint32_t v1) { - - float32_t a{v1}; - union ui32_f32 uA; - uint_fast32_t uiA; - - uA.f = a; - uiA = uA.ui; - - bool infOrNaN = expF32UI(uiA) == 0xFF; - bool subnormalOrZero = expF32UI(uiA) == 0; - bool sign = signF32UI(uiA); - bool fracZero = fracF32UI(uiA) == 0; - bool isNaN = isNaNF32UI(uiA); - bool isSNaN = softfloat_isSigNaNF32UI(uiA); - - return (sign && infOrNaN && fracZero) << 0 | (sign && !infOrNaN && !subnormalOrZero) << 1 | - (sign && subnormalOrZero && !fracZero) << 2 | (sign && subnormalOrZero && fracZero) << 3 | (!sign && infOrNaN && fracZero) << 7 | - (!sign && !infOrNaN && !subnormalOrZero) << 6 | (!sign && subnormalOrZero && !fracZero) << 5 | - (!sign && subnormalOrZero && fracZero) << 4 | (isNaN && isSNaN) << 8 | (isNaN && !isSNaN) << 9; -} - -uint32_t frsqrt7_s(uint32_t v) { - bool subnormal = false; - uint32_t ret_val = 0; - if(rsqrt_check(fclass_s(v), subnormal, ret_val)) { - return ret_val; - } - uint32_t sig = fracF32UI(v); - int exp = expF32UI(v); - uint32_t sign = signF32UI(v); - unsigned constexpr e = 8; - unsigned constexpr s = 23; - return frsqrt7_general(s, e, sign, exp, sig, subnormal); -} - -uint32_t frec7_s(uint32_t v, uint8_t mode) { - bool subnormal = false; - uint64_t ret_val = 0; - if(recip_check(fclass_s(v), subnormal, ret_val)) { - return ret_val; - } - uint32_t sig = fracF32UI(v); - int exp = expF32UI(v); - uint32_t sign = signF32UI(v); - unsigned constexpr e = 8; - unsigned constexpr s = 23; - if(frec_general(ret_val, s, e, sign, exp, sig, subnormal, mode)) - softfloat_exceptionFlags |= (softfloat_flag_inexact | softfloat_flag_overflow); - return ret_val; -} - -uint32_t unbox_s(uint8_t FLEN, uint64_t v) { - uint64_t mask = 0; - switch(FLEN) { - case 32: { - return v; - } - case 64: { - mask = std::numeric_limits::max() & ~((uint64_t)std::numeric_limits::max()); - break; - } - default: - break; - } - if((v & mask) != mask) - return defaultNaNF32UI; - else - return v & std::numeric_limits::max(); -} - -uint64_t fadd_d(uint64_t v1, uint64_t v2, uint8_t mode) { - bool nan = v1 == defaultNaNF32UI; - bool snan = softfloat_isSigNaNF32UI(v1); - float64_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float64_t r = f64_add(v1f, v2f); - return r.v; -} - -uint64_t fsub_d(uint64_t v1, uint64_t v2, uint8_t mode) { - float64_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float64_t r = f64_sub(v1f, v2f); - return r.v; -} - -uint64_t fmul_d(uint64_t v1, uint64_t v2, uint8_t mode) { - float64_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float64_t r = f64_mul(v1f, v2f); - return r.v; -} - -uint64_t fdiv_d(uint64_t v1, uint64_t v2, uint8_t mode) { - float64_t v1f{v1}, v2f{v2}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float64_t r = f64_div(v1f, v2f); - return r.v; -} - -uint64_t fsqrt_d(uint64_t v1, uint8_t mode) { - float64_t v1f{v1}; - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float64_t r = f64_sqrt(v1f); - return r.v; -} - -uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) { - float64_t v1f{v1}, v2f{v2}; - softfloat_exceptionFlags = 0; - bool nan = v1 == defaultNaNF64UI || v2 == defaultNaNF64UI; - bool snan = softfloat_isSigNaNF64UI(v1) || softfloat_isSigNaNF64UI(v2); - switch(op) { - case 0: - if(nan | snan) { - if(snan) - softfloat_raiseFlags(softfloat_flag_invalid); - return 0; - } else - return f64_eq(v1f, v2f) ? 1 : 0; - case 1: - if(nan | snan) { - softfloat_raiseFlags(softfloat_flag_invalid); - return 0; - } else - return f64_le(v1f, v2f) ? 1 : 0; - case 2: - if(nan | snan) { - softfloat_raiseFlags(softfloat_flag_invalid); - return 0; - } else - return f64_lt(v1f, v2f) ? 1 : 0; - default: - break; - } - return -1; -} - -uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode) { - uint64_t F64_SIGN = 1ULL << 63; - switch(op) { - case 0: // FMADD_D - break; - case 1: // FMSUB_D - v3 ^= F64_SIGN; - break; - case 2: // FNMADD_D - v1 ^= F64_SIGN; - v3 ^= F64_SIGN; - break; - case 3: // FNMSUB_D - v1 ^= F64_SIGN; - break; - } - softfloat_roundingMode = mode; - softfloat_exceptionFlags = 0; - float64_t res = softfloat_mulAddF64(v1, v2, v3, 0); - return res.v; -} - -uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op) { - softfloat_exceptionFlags = 0; - bool v1_nan = (v1 & defaultNaNF64UI) == defaultNaNF64UI; - bool v2_nan = (v2 & defaultNaNF64UI) == defaultNaNF64UI; - bool v1_snan = softfloat_isSigNaNF64UI(v1); - bool v2_snan = softfloat_isSigNaNF64UI(v2); - if(v1_snan || v2_snan) - softfloat_raiseFlags(softfloat_flag_invalid); - if(v1_nan || v1_snan) - return (v2_nan || v2_snan) ? defaultNaNF64UI : v2; - else if(v2_nan || v2_snan) - return v1; - else { - if((v1 & std::numeric_limits::max()) == 0 && (v2 & std::numeric_limits::max()) == 0) { - return op == 0 ? ((v1 & std::numeric_limits::min()) ? v1 : v2) - : ((v1 & std::numeric_limits::min()) ? v2 : v1); - } else { - float64_t v1f{v1}, v2f{v2}; - return op == 0 ? (f64_lt(v1f, v2f) ? v1 : v2) : (f64_lt(v1f, v2f) ? v2 : v1); - } - } -} - -uint64_t fclass_d(uint64_t v1) { - - float64_t a{v1}; - union ui64_f64 uA; - uint_fast64_t uiA; - - uA.f = a; - uiA = uA.ui; - - bool infOrNaN = expF64UI(uiA) == 0x7FF; - bool subnormalOrZero = expF64UI(uiA) == 0; - bool sign = signF64UI(uiA); - bool fracZero = fracF64UI(uiA) == 0; - bool isNaN = isNaNF64UI(uiA); - bool isSNaN = softfloat_isSigNaNF64UI(uiA); - - return (sign && infOrNaN && fracZero) << 0 | (sign && !infOrNaN && !subnormalOrZero) << 1 | - (sign && subnormalOrZero && !fracZero) << 2 | (sign && subnormalOrZero && fracZero) << 3 | (!sign && infOrNaN && fracZero) << 7 | - (!sign && !infOrNaN && !subnormalOrZero) << 6 | (!sign && subnormalOrZero && !fracZero) << 5 | - (!sign && subnormalOrZero && fracZero) << 4 | (isNaN && isSNaN) << 8 | (isNaN && !isSNaN) << 9; -} - -uint64_t frsqrt7_d(uint64_t v) { - bool subnormal = false; - uint64_t ret_val = 0; - if(rsqrt_check(fclass_d(v), subnormal, ret_val)) { - return ret_val; - } - uint64_t sig = fracF64UI(v); - int exp = expF64UI(v); - uint64_t sign = signF64UI(v); - unsigned constexpr e = 11; - unsigned constexpr s = 52; - return frsqrt7_general(s, e, sign, exp, sig, subnormal); -} - -uint64_t frec7_d(uint64_t v, uint8_t mode) { - bool subnormal = false; - uint64_t ret_val = 0; - if(recip_check(fclass_d(v), subnormal, ret_val)) { - return ret_val; - } - uint64_t sig = fracF64UI(v); - int exp = expF64UI(v); - uint64_t sign = signF64UI(v); - unsigned constexpr e = 11; - unsigned constexpr s = 52; - if(frec_general(ret_val, s, e, sign, exp, sig, subnormal, mode)) - softfloat_exceptionFlags |= (softfloat_flag_inexact | softfloat_flag_overflow); - return ret_val; -} - -uint64_t unbox_d(uint8_t FLEN, uint64_t v) { - uint64_t mask = 0; - switch(FLEN) { - case 64: { - return v; - break; - } - default: - break; - } - if((v & mask) != mask) - return defaultNaNF64UI; - else - return v & std::numeric_limits::max(); -} - -// conversion: float to float -uint32_t f16tof32(uint16_t val, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f16_to_f32(float16_t{val}).v; - } -uint64_t f16tof64(uint16_t val, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f16_to_f64(float16_t{val}).v; -} - -uint16_t f32tof16(uint32_t val, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f32_to_f16(float32_t{val}).v; - } -uint64_t f32tof64(uint32_t val, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f32_to_f64(float32_t{val}).v; - } - -uint16_t f64tof16(uint64_t val, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f64_to_f16(float64_t{val}).v; - } -uint32_t f64tof32(uint64_t val, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f64_to_f32(float64_t{val}).v; -} - -// conversions: float to unsigned -uint32_t f16toui32(uint16_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f16_to_ui32(float16_t{v}, rm, true); -} -uint64_t f16toui64(uint16_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f16_to_ui64(float16_t{v}, rm, true); -} -uint32_t f32toui32(uint32_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f32_to_ui32(float32_t{v}, rm, true); -} -uint64_t f32toui64(uint32_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f32_to_ui64(float32_t{v}, rm, true); -} -uint32_t f64toui32(uint64_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f64_to_ui32(float64_t{v}, rm, true); -} -uint64_t f64toui64(uint64_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f64_to_ui64(float64_t{v}, rm, true); -} - -// conversions: float to signed -uint32_t f16toi32(uint16_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f16_to_i32(float16_t{v}, rm, true); -} -uint64_t f16toi64(uint16_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f16_to_i64(float16_t{v}, rm, true); -} -uint32_t f32toi32(uint32_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f32_to_i32(float32_t{v}, rm, true); -} -uint64_t f32toi64(uint32_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f32_to_i64(float32_t{v}, rm, true); -} -uint32_t f64toi32(uint64_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f64_to_i32(float64_t{v}, rm, true); -} -uint64_t f64toi64(uint64_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return f64_to_i64(float64_t{v}, rm, true); -} - -// conversions: unsigned to float -uint16_t ui32tof16(uint32_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return ui32_to_f16(v).v; -} -uint16_t ui64tof16(uint64_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return ui64_to_f16(v).v; -} -uint32_t ui32tof32(uint32_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return ui32_to_f32(v).v; -} -uint32_t ui64tof32(uint64_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return ui64_to_f32(v).v; -} -uint64_t ui32tof64(uint32_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return ui32_to_f64(v).v; -} -uint64_t ui64tof64(uint64_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return ui64_to_f64(v).v; -} - -// conversions: signed to float -uint16_t i32tof16(uint32_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return i32_to_f16(v).v; -} -uint16_t i64tof16(uint64_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return i64_to_f16(v).v; -} -uint32_t i32tof32(uint32_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return i32_to_f32(v).v; -} -uint32_t i64tof32(uint64_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return i64_to_f32(v).v; -} -uint64_t i32tof64(uint32_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return i32_to_f64(v).v; -} -uint64_t i64tof64(uint64_t v, uint8_t rm) { - softfloat_exceptionFlags = 0; - softfloat_roundingMode = rm; - return i64_to_f64(v).v; -} -} diff --git a/src/vm/fp_functions.h b/src/vm/fp_functions.h deleted file mode 100644 index 50a108b..0000000 --- a/src/vm/fp_functions.h +++ /dev/null @@ -1,125 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2020, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -// Contributors: -// eyck@minres.com - initial API and implementation -//////////////////////////////////////////////////////////////////////////////// - -#ifndef RISCV_SRC_VM_FP_FUNCTIONS_H_ -#define RISCV_SRC_VM_FP_FUNCTIONS_H_ - -#include - -extern "C" { -uint32_t fget_flags(); - -// half precision -uint16_t fadd_h(uint16_t v1, uint16_t v2, uint8_t mode); -uint16_t fsub_h(uint16_t v1, uint16_t v2, uint8_t mode); -uint16_t fmul_h(uint16_t v1, uint16_t v2, uint8_t mode); -uint16_t fdiv_h(uint16_t v1, uint16_t v2, uint8_t mode); -uint16_t fsqrt_h(uint16_t v1, uint8_t mode); -uint16_t fcmp_h(uint16_t v1, uint16_t v2, uint16_t op); -uint16_t fmadd_h(uint16_t v1, uint16_t v2, uint16_t v3, uint16_t op, uint8_t mode); -uint16_t fsel_h(uint16_t v1, uint16_t v2, uint16_t op); -uint16_t fclass_h(uint16_t v1); -uint16_t frsqrt7_h(uint16_t v); -uint16_t frec7_h(uint16_t v, uint8_t mode); -uint16_t unbox_h(uint8_t FLEN, uint64_t v); - -// single precision -uint32_t fadd_s(uint32_t v1, uint32_t v2, uint8_t mode); -uint32_t fsub_s(uint32_t v1, uint32_t v2, uint8_t mode); -uint32_t fmul_s(uint32_t v1, uint32_t v2, uint8_t mode); -uint32_t fdiv_s(uint32_t v1, uint32_t v2, uint8_t mode); -uint32_t fsqrt_s(uint32_t v1, uint8_t mode); -uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op); -uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode); -uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op); -uint32_t fclass_s(uint32_t v1); -uint32_t frsqrt7_s(uint32_t v); -uint32_t frec7_s(uint32_t v, uint8_t mode); -uint32_t unbox_s(uint8_t FLEN, uint64_t v); - -// double precision -uint64_t fadd_d(uint64_t v1, uint64_t v2, uint8_t mode); -uint64_t fsub_d(uint64_t v1, uint64_t v2, uint8_t mode); -uint64_t fmul_d(uint64_t v1, uint64_t v2, uint8_t mode); -uint64_t fdiv_d(uint64_t v1, uint64_t v2, uint8_t mode); -uint64_t fsqrt_d(uint64_t v1, uint8_t mode); -uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op); -uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode); -uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op); -uint64_t fclass_d(uint64_t v1); -uint64_t frsqrt7_d(uint64_t v); -uint64_t frec7_d(uint64_t v, uint8_t mode); -uint64_t unbox_d(uint8_t FLEN, uint64_t v); - -// conversion: float to float -uint32_t f16tof32(uint16_t val, uint8_t rm); -uint64_t f16tof64(uint16_t val, uint8_t rm); -uint16_t f32tof16(uint32_t val, uint8_t rm); -uint64_t f32tof64(uint32_t val, uint8_t rm); -uint16_t f64tof16(uint64_t val, uint8_t rm); -uint32_t f64tof32(uint64_t val, uint8_t rm); - -// conversions: float to unsigned -uint32_t f16toui32(uint16_t v, uint8_t rm); -uint64_t f16toui64(uint16_t v, uint8_t rm); -uint32_t f32toui32(uint32_t v, uint8_t rm); -uint64_t f32toui64(uint32_t v, uint8_t rm); -uint32_t f64toui32(uint64_t v, uint8_t rm); -uint64_t f64toui64(uint64_t v, uint8_t rm); - -// conversions: float to signed -uint32_t f16toi32(uint16_t v, uint8_t rm); -uint64_t f16toi64(uint16_t v, uint8_t rm); -uint32_t f32toi32(uint32_t v, uint8_t rm); -uint64_t f32toi64(uint32_t v, uint8_t rm); -uint32_t f64toi32(uint64_t v, uint8_t rm); -uint64_t f64toi64(uint64_t v, uint8_t rm); - -// conversions: unsigned to float -uint16_t ui32tof16(uint32_t v, uint8_t rm); -uint16_t ui64tof16(uint64_t v, uint8_t rm); -uint32_t ui32tof32(uint32_t v, uint8_t rm); -uint32_t ui64tof32(uint64_t v, uint8_t rm); -uint64_t ui32tof64(uint32_t v, uint8_t rm); -uint64_t ui64tof64(uint64_t v, uint8_t rm); - -// conversions: signed to float -uint16_t i32tof16(uint32_t v, uint8_t rm); -uint16_t i64tof16(uint64_t v, uint8_t rm); -uint32_t i32tof32(uint32_t v, uint8_t rm); -uint32_t i64tof32(uint64_t v, uint8_t rm); -uint64_t i32tof64(uint32_t v, uint8_t rm); -uint64_t i64tof64(uint64_t v, uint8_t rm); -} -#endif /* RISCV_SRC_VM_FP_FUNCTIONS_H_ */ diff --git a/src/vm/interp/vm_rv32gc.cpp b/src/vm/interp/vm_rv32gc.cpp index efe26bf..02421cd 100644 --- a/src/vm/interp/vm_rv32gc.cpp +++ b/src/vm/interp/vm_rv32gc.cpp @@ -38,7 +38,7 @@ #include #include -#include +#include #include #include @@ -4918,8 +4918,8 @@ std::unique_ptr create(arch::rv32gc *core, unsigned short p } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp index 63b6bfb..d080c20 100644 --- a/src/vm/interp/vm_rv32gcv.cpp +++ b/src/vm/interp/vm_rv32gcv.cpp @@ -38,9 +38,9 @@ #include #include -#include +#include -#include +#include #include #include diff --git a/src/vm/interp/vm_rv64gc.cpp b/src/vm/interp/vm_rv64gc.cpp index 7781643..c4a51a7 100644 --- a/src/vm/interp/vm_rv64gc.cpp +++ b/src/vm/interp/vm_rv64gc.cpp @@ -38,7 +38,7 @@ #include #include -#include +#include #include #include @@ -6261,8 +6261,8 @@ std::unique_ptr create(arch::rv64gc *core, unsigned short p } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp index b35699b..a580509 100644 --- a/src/vm/interp/vm_rv64gcv.cpp +++ b/src/vm/interp/vm_rv64gcv.cpp @@ -38,9 +38,9 @@ #include #include -#include +#include -#include +#include #include #include diff --git a/src/vm/llvm/vm_rv32gc.cpp b/src/vm/llvm/vm_rv32gc.cpp index 41927d9..0f20537 100644 --- a/src/vm/llvm/vm_rv32gc.cpp +++ b/src/vm/llvm/vm_rv32gc.cpp @@ -40,7 +40,7 @@ #include #include -#include +#include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif @@ -9771,8 +9771,8 @@ std::unique_ptr create(arch::rv32gc *core, unsigned short p } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/llvm/vm_rv64gc.cpp b/src/vm/llvm/vm_rv64gc.cpp index e83dce5..bc2285b 100644 --- a/src/vm/llvm/vm_rv64gc.cpp +++ b/src/vm/llvm/vm_rv64gc.cpp @@ -40,7 +40,7 @@ #include #include -#include +#include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif @@ -12449,8 +12449,8 @@ std::unique_ptr create(arch::rv64gc *core, unsigned short p } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/new_vector_functions.h b/src/vm/new_vector_functions.h deleted file mode 100644 index 7f35a90..0000000 --- a/src/vm/new_vector_functions.h +++ /dev/null @@ -1,989 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2025, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -// Contributors: -// alex@minres.com - initial API and implementation -//////////////////////////////////////////////////////////////////////////////// - -#ifndef RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ -#define RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ -#include -#include -#include - -#include "iss/arch_if.h" -#include "iss/vm_types.h" -#include - -namespace softvec_if { -using indexed_load_store_t = std::function, uint8_t*, uint64_t, - uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; -template indexed_load_store_t getFunction() { - return [](void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, - uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, uint8_t segment_size) { - return softvector::vector_load_store_index(core, load_store_fn, V, vl, vstart, vtype, vm, vd, rs1, vs2, - segment_size); - }; -} -template -const std::array, 4> functionTable = { - {{getFunction(), getFunction(), - getFunction(), getFunction()}, - {getFunction(), getFunction(), - getFunction(), getFunction()}, - {getFunction(), getFunction(), - getFunction(), getFunction()}, - {getFunction(), getFunction(), - getFunction(), getFunction()}}}; -constexpr size_t map_index_size[9] = {std::numeric_limits::max(), - 0, - 1, - std::numeric_limits::max(), - 2, - std::numeric_limits::max(), - std::numeric_limits::max(), - std::numeric_limits::max(), - 3}; - -inline bool softvec_read(void* core, uint64_t addr, uint64_t length, uint8_t* data) { - // Read length bytes from addr into *data - iss::status status = static_cast(core)->read(iss::address_type::PHYSICAL, iss::access_type::READ, - 0 /*traits::MEM*/, addr, length, data); - return status == iss::Ok; -} -inline bool softvec_write(void* core, uint64_t addr, uint64_t length, uint8_t* data) { - // Write length bytes from addr into *data - iss::status status = static_cast(core)->write(iss::address_type::PHYSICAL, iss::access_type::READ, - 0 /*traits::MEM*/, addr, length, data); - return status == iss::Ok; -} -template -uint64_t vlseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size) { - switch(width_val) { - case 0b000: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b101: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b110: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b111: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - default: - throw new std::runtime_error("Unsupported width bit value"); - } -} -template -uint64_t vsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size) { - switch(width_val) { - case 0b000: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b101: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b110: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - case 0b111: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); - default: - throw new std::runtime_error("Unsupported width bit value"); - } -} -template -uint64_t vlsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size, int64_t stride) { - switch(width_val) { - case 0b000: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, - true); - case 0b101: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b110: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b111: - return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - default: - throw new std::runtime_error("Unsupported width bit value"); - } -} -template -uint64_t vssseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t width_val, uint8_t segment_size, int64_t stride) { - switch(width_val) { - case 0b000: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b101: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b110: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - case 0b111: - return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, - stride, true); - default: - throw new std::runtime_error("Unsupported width bit value"); - } -} -template -uint64_t vlxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, - uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered) { - return functionTable[map_index_size[index_byte_size]][data_byte_size](core, softvec_read, V, vl, vstart, vtype, vm, vd, - rs1_val, vs2, segment_size); -} -template -uint64_t vsxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, - uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered) { - return functionTable[map_index_size[index_byte_size]][data_byte_size](core, softvec_write, V, vl, vstart, vtype, vm, vs3, - rs1_val, vs2, segment_size); -} -template -void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint8_t target_sew_pow, uint8_t frac_pow) { - switch(target_sew_pow) { - case 4: // uint16_t target - if(frac_pow != 1) - throw new std::runtime_error("Unsupported frac_pow"); - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 5: // uint32_t target - switch(frac_pow) { - case 1: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 2: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported frac_pow"); - } - case 6: // uint64_t target - switch(frac_pow) { - case 1: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 2: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 3: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported frac_pow"); - } - default: - throw new std::runtime_error("Unsupported target_sew_pow"); - } -} -template -void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b001: - return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b010: - return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - case 0b011: - return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b001: - return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b010: - return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - case 0b011: - return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, - uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b001: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b010: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b011: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, - bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b001: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b010: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b011: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, - uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b001: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b010: - return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, - bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b001: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b010: - return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1) { - return softvector::mask_mask_op(V, funct6, funct3, vl, vstart, vd, vs2, vs1); -} -template uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { - return softvector::vcpop(V, vl, vstart, vm, vs2); -} -template int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { - return softvector::vfirst(V, vl, vstart, vm, vs2); -} -template void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2) { - return softvector::mask_set_op(V, enc, vl, vstart, vm, vd, vs2); -} -template -void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); - case 0b001: - return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); - case 0b010: - return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); - case 0b011: - return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vid(V, vl, vstart, vtype, vm, vd); - case 0b001: - return softvector::vid(V, vl, vstart, vtype, vm, vd); - case 0b010: - return softvector::vid(V, vl, vstart, vtype, vm, vd); - case 0b011: - return softvector::vid(V, vl, vstart, vtype, vm, vd); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - softvector::scalar_move(V, vtype, vd, val, true); - break; - case 0b001: - softvector::scalar_move(V, vtype, vd, val, true); - break; - case 0b010: - softvector::scalar_move(V, vtype, vd, val, true); - break; - case 0b011: - softvector::scalar_move(V, vtype, vd, val, true); - break; - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::scalar_move(V, vtype, vd, 0, false); - case 0b001: - return softvector::scalar_move(V, vtype, vd, 0, false); - case 0b010: - return softvector::scalar_move(V, vtype, vd, 0, false); - case 0b011: - return softvector::scalar_move(V, vtype, vd, 0, false); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint64_t imm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint8_t vs1, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b001: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b010: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - case 0b011: - return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b001: - return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b010: - return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); - case 0b011: - return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, - uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b001: - return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b010: - return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); - case 0b011: - return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count) { - return softvector::vector_whole_move(V, vd, vs2, count); -} -template uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val) { - return scalar_from_vector(V, vtype, vd, sew_val); -} -template -void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint64_t imm, uint8_t sew_val) { - return vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); -} -template -void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint64_t imm, uint8_t sew_val) { - return vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); -} -template -void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b001: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would require 128 bits vs2 value - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, - rm); - case 0b010: - return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, - rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, - uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, - bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: - return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b010: - return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - case 0b011: - return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - throw new std::runtime_error("Unsupported sew bit value"); - case 0b001: - return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b010: - return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - case 0b011: - return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, - uint64_t imm, uint8_t sew_val) { - vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); -} -template -void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b001: - return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: // would widen to 128 bits - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t rm, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b001: - return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b010: - return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); - case 0b011: // would require 128 bit value to narrow - default: - throw new std::runtime_error("Unsupported sew bit value"); - } -} -template -void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, - uint8_t vs2, uint8_t sew_val) { - switch(sew_val) { - case 0b000: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b001: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b010: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - case 0b011: - return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); - default: - throw new std::runtime_error("Unsupported sew_val"); - } -} -} // namespace softvec_if -#endif /* RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ */ diff --git a/src/vm/vector_functions.cpp b/src/vm/vector_functions.cpp deleted file mode 100644 index 9e008d0..0000000 --- a/src/vm/vector_functions.cpp +++ /dev/null @@ -1,394 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2025, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -// Contributors: -// alex@minres.com - initial API and implementation -//////////////////////////////////////////////////////////////////////////////// - -#include "vector_functions.h" -#include "vm/aes_sbox.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -namespace softvector { - -vtype_t::vtype_t(uint32_t vtype_val) { underlying = (vtype_val & 0x8000) << 32 | (vtype_val & ~0x8000); } -vtype_t::vtype_t(uint64_t vtype_val) { underlying = vtype_val; } -bool vtype_t::vill() { return underlying >> 63; } -bool vtype_t::vma() { return (underlying >> 7) & 1; } -bool vtype_t::vta() { return (underlying >> 6) & 1; } -unsigned vtype_t::sew() { - uint8_t vsew = (underlying >> 3) & 0b111; - // pow(2, 3 + vsew); - return 1 << (3 + vsew); -} -double vtype_t::lmul() { - uint8_t vlmul = underlying & 0b111; - assert(vlmul != 0b100); // reserved encoding - int8_t signed_vlmul = (vlmul >> 2) ? 0b11111000 | vlmul : vlmul; - return pow(2, signed_vlmul); -} - -mask_bit_reference& mask_bit_reference::operator=(const bool new_value) { - *start = *start & ~(1U << pos) | static_cast(new_value) << pos; - return *this; -} - -mask_bit_reference::mask_bit_reference(uint8_t* start, uint8_t pos) -: start(start) -, pos(pos) { - assert(pos < 8 && "Bit reference can only be initialized for bytes"); -}; -mask_bit_reference::operator bool() const { return *(start) & (1U << (pos)); } - -mask_bit_reference vmask_view::operator[](size_t idx) const { - assert(idx < elem_count); - return {start + idx / 8, static_cast(idx % 8)}; -} - -vmask_view read_vmask(uint8_t* V, uint16_t VLEN, uint16_t elem_count, uint8_t reg_idx) { - uint8_t* mask_start = V + VLEN / 8 * reg_idx; - assert(mask_start + elem_count / 8 <= V + VLEN * RFS / 8); - return {mask_start, elem_count}; -} -uint8_t xt2(uint8_t x) { return (x << 1) ^ (bit_sub<7, 1>(x) ? 27 : 0); } - -uint8_t xt3(uint8_t x) { return x ^ xt2(x); } - -uint8_t gfmul(uint8_t x, uint8_t y) { - return (bit_sub<0, 1>(y) ? x : 0) ^ (bit_sub<1, 1>(y) ? xt2(x) : 0) ^ (bit_sub<2, 1>(y) ? xt2(xt2(x)) : 0) ^ - (bit_sub<3, 1>(y) ? xt2(xt2(xt2(x))) : 0); -} - -uint32_t aes_mixcolumn_byte_fwd(uint8_t so) { - return ((uint32_t)gfmul(so, 3) << 24) | ((uint32_t)so << 16) | ((uint32_t)so << 8) | gfmul(so, 2); -} - -uint32_t aes_mixcolumn_byte_inv(uint8_t so) { - return ((uint32_t)gfmul(so, 11) << 24) | ((uint32_t)gfmul(so, 13) << 16) | ((uint32_t)gfmul(so, 9) << 8) | gfmul(so, 14); -} - -uint32_t aes_mixcolumn_fwd(uint32_t x) { - uint8_t s0 = bit_sub<0, 7 - 0 + 1>(x); - uint8_t s1 = bit_sub<8, 15 - 8 + 1>(x); - uint8_t s2 = bit_sub<16, 23 - 16 + 1>(x); - uint8_t s3 = bit_sub<24, 31 - 24 + 1>(x); - uint8_t b0 = xt2(s0) ^ xt3(s1) ^ (s2) ^ (s3); - uint8_t b1 = (s0) ^ xt2(s1) ^ xt3(s2) ^ (s3); - uint8_t b2 = (s0) ^ (s1) ^ xt2(s2) ^ xt3(s3); - uint8_t b3 = xt3(s0) ^ (s1) ^ (s2) ^ xt2(s3); - return ((uint32_t)b3 << 24) | ((uint32_t)b2 << 16) | ((uint32_t)b1 << 8) | b0; -} - -uint32_t aes_mixcolumn_inv(uint32_t x) { - uint8_t s0 = bit_sub<0, 7 - 0 + 1>(x); - uint8_t s1 = bit_sub<8, 15 - 8 + 1>(x); - uint8_t s2 = bit_sub<16, 23 - 16 + 1>(x); - uint8_t s3 = bit_sub<24, 31 - 24 + 1>(x); - uint8_t b0 = gfmul(s0, 14) ^ gfmul(s1, 11) ^ gfmul(s2, 13) ^ gfmul(s3, 9); - uint8_t b1 = gfmul(s0, 9) ^ gfmul(s1, 14) ^ gfmul(s2, 11) ^ gfmul(s3, 13); - uint8_t b2 = gfmul(s0, 13) ^ gfmul(s1, 9) ^ gfmul(s2, 14) ^ gfmul(s3, 11); - uint8_t b3 = gfmul(s0, 11) ^ gfmul(s1, 13) ^ gfmul(s2, 9) ^ gfmul(s3, 14); - return ((uint32_t)b3 << 24) | ((uint32_t)b2 << 16) | ((uint32_t)b1 << 8) | b0; -} - -uint32_t aes_decode_rcon(uint8_t r) { - switch(r) { - case 0: - return 1; - case 1: - return 2; - case 2: - return 4; - case 3: - return 8; - case 4: - return 16; - case 5: - return 32; - case 6: - return 64; - case 7: - return 128; - case 8: - return 27; - case 9: - return 54; - } - return 0; -} - -uint32_t aes_subword_fwd(uint32_t x) { - return ((uint32_t)aes_sbox_fwd(bit_sub<24, 31 - 24 + 1>(x)) << 24) | ((uint32_t)aes_sbox_fwd(bit_sub<16, 23 - 16 + 1>(x)) << 16) | - ((uint32_t)aes_sbox_fwd(bit_sub<8, 15 - 8 + 1>(x)) << 8) | aes_sbox_fwd(bit_sub<0, 7 - 0 + 1>(x)); -} - -uint32_t aes_subword_inv(uint32_t x) { - return ((uint32_t)aes_sbox_inv(bit_sub<24, 31 - 24 + 1>(x)) << 24) | ((uint32_t)aes_sbox_inv(bit_sub<16, 23 - 16 + 1>(x)) << 16) | - ((uint32_t)aes_sbox_inv(bit_sub<8, 15 - 8 + 1>(x)) << 8) | aes_sbox_inv(bit_sub<0, 7 - 0 + 1>(x)); -} - -uint32_t aes_get_column(__uint128_t state, unsigned c) { - assert(c < 4); - return static_cast(state >> (32 * c)); -}; - -uint64_t aes_apply_fwd_sbox_to_each_byte(uint64_t x) { - return ((uint64_t)aes_sbox_fwd(bit_sub<56, 63 - 56 + 1>(x)) << 56) | ((uint64_t)aes_sbox_fwd(bit_sub<48, 55 - 48 + 1>(x)) << 48) | - ((uint64_t)aes_sbox_fwd(bit_sub<40, 47 - 40 + 1>(x)) << 40) | ((uint64_t)aes_sbox_fwd(bit_sub<32, 39 - 32 + 1>(x)) << 32) | - ((uint64_t)aes_sbox_fwd(bit_sub<24, 31 - 24 + 1>(x)) << 24) | ((uint64_t)aes_sbox_fwd(bit_sub<16, 23 - 16 + 1>(x)) << 16) | - ((uint64_t)aes_sbox_fwd(bit_sub<8, 15 - 8 + 1>(x)) << 8) | aes_sbox_fwd(bit_sub<0, 7 - 0 + 1>(x)); -} - -uint64_t aes_apply_inv_sbox_to_each_byte(uint64_t x) { - return ((uint64_t)aes_sbox_inv(bit_sub<56, 63 - 56 + 1>(x)) << 56) | ((uint64_t)aes_sbox_inv(bit_sub<48, 55 - 48 + 1>(x)) << 48) | - ((uint64_t)aes_sbox_inv(bit_sub<40, 47 - 40 + 1>(x)) << 40) | ((uint64_t)aes_sbox_inv(bit_sub<32, 39 - 32 + 1>(x)) << 32) | - ((uint64_t)aes_sbox_inv(bit_sub<24, 31 - 24 + 1>(x)) << 24) | ((uint64_t)aes_sbox_inv(bit_sub<16, 23 - 16 + 1>(x)) << 16) | - ((uint64_t)aes_sbox_inv(bit_sub<8, 15 - 8 + 1>(x)) << 8) | aes_sbox_inv(bit_sub<0, 7 - 0 + 1>(x)); -} - -uint64_t aes_rv64_shiftrows_fwd(uint64_t rs2, uint64_t rs1) { - return ((uint64_t)bit_sub<24, 31 - 24 + 1>(rs1) << 56) | ((uint64_t)bit_sub<48, 55 - 48 + 1>(rs2) << 48) | - ((uint64_t)bit_sub<8, 15 - 8 + 1>(rs2) << 40) | ((uint64_t)bit_sub<32, 39 - 32 + 1>(rs1) << 32) | - ((uint64_t)bit_sub<56, 63 - 56 + 1>(rs2) << 24) | ((uint64_t)bit_sub<16, 23 - 16 + 1>(rs2) << 16) | - ((uint64_t)bit_sub<40, 47 - 40 + 1>(rs1) << 8) | bit_sub<0, 7 - 0 + 1>(rs1); -} - -uint64_t aes_rv64_shiftrows_inv(uint64_t rs2, uint64_t rs1) { - return ((uint64_t)bit_sub<24, 31 - 24 + 1>(rs2) << 56) | ((uint64_t)bit_sub<48, 55 - 48 + 1>(rs2) << 48) | - ((uint64_t)bit_sub<8, 15 - 8 + 1>(rs1) << 40) | ((uint64_t)bit_sub<32, 39 - 32 + 1>(rs1) << 32) | - ((uint64_t)bit_sub<56, 63 - 56 + 1>(rs1) << 24) | ((uint64_t)bit_sub<16, 23 - 16 + 1>(rs2) << 16) | - ((uint64_t)bit_sub<40, 47 - 40 + 1>(rs2) << 8) | bit_sub<0, 7 - 0 + 1>(rs1); -} - -uint128_t aes_shift_rows_fwd(uint128_t x) { - uint32_t ic3 = aes_get_column(x, 3); - uint32_t ic2 = aes_get_column(x, 2); - uint32_t ic1 = aes_get_column(x, 1); - uint32_t ic0 = aes_get_column(x, 0); - uint32_t oc0 = ((uint32_t)bit_sub<24, 31 - 24 + 1>(ic3) << 24) | ((uint32_t)bit_sub<16, 23 - 16 + 1>(ic2) << 16) | - ((uint32_t)bit_sub<8, 15 - 8 + 1>(ic1) << 8) | bit_sub<0, 7 - 0 + 1>(ic0); - uint32_t oc1 = ((uint32_t)bit_sub<24, 31 - 24 + 1>(ic0) << 24) | ((uint32_t)bit_sub<16, 23 - 16 + 1>(ic3) << 16) | - ((uint32_t)bit_sub<8, 15 - 8 + 1>(ic2) << 8) | bit_sub<0, 7 - 0 + 1>(ic1); - uint32_t oc2 = ((uint32_t)bit_sub<24, 31 - 24 + 1>(ic1) << 24) | ((uint32_t)bit_sub<16, 23 - 16 + 1>(ic0) << 16) | - ((uint32_t)bit_sub<8, 15 - 8 + 1>(ic3) << 8) | bit_sub<0, 7 - 0 + 1>(ic2); - uint32_t oc3 = ((uint32_t)bit_sub<24, 31 - 24 + 1>(ic2) << 24) | ((uint32_t)bit_sub<16, 23 - 16 + 1>(ic1) << 16) | - ((uint32_t)bit_sub<8, 15 - 8 + 1>(ic0) << 8) | bit_sub<0, 7 - 0 + 1>(ic3); - return ((uint128_t)oc3 << 96) | ((uint128_t)oc2 << 64) | ((uint128_t)oc1 << 32) | oc0; -} - -uint128_t aes_shift_rows_inv(uint128_t x) { - uint32_t ic3 = aes_get_column(x, 3); - uint32_t ic2 = aes_get_column(x, 2); - uint32_t ic1 = aes_get_column(x, 1); - uint32_t ic0 = aes_get_column(x, 0); - uint32_t oc0 = ((uint32_t)bit_sub<24, 31 - 24 + 1>(ic1) << 24) | ((uint32_t)bit_sub<16, 23 - 16 + 1>(ic2) << 16) | - ((uint32_t)bit_sub<8, 15 - 8 + 1>(ic3) << 8) | bit_sub<0, 7 - 0 + 1>(ic0); - uint32_t oc1 = ((uint32_t)bit_sub<24, 31 - 24 + 1>(ic2) << 24) | ((uint32_t)bit_sub<16, 23 - 16 + 1>(ic3) << 16) | - ((uint32_t)bit_sub<8, 15 - 8 + 1>(ic0) << 8) | bit_sub<0, 7 - 0 + 1>(ic1); - uint32_t oc2 = ((uint32_t)bit_sub<24, 31 - 24 + 1>(ic3) << 24) | ((uint32_t)bit_sub<16, 23 - 16 + 1>(ic0) << 16) | - ((uint32_t)bit_sub<8, 15 - 8 + 1>(ic1) << 8) | bit_sub<0, 7 - 0 + 1>(ic2); - uint32_t oc3 = ((uint32_t)bit_sub<24, 31 - 24 + 1>(ic0) << 24) | ((uint32_t)bit_sub<16, 23 - 16 + 1>(ic1) << 16) | - ((uint32_t)bit_sub<8, 15 - 8 + 1>(ic2) << 8) | bit_sub<0, 7 - 0 + 1>(ic3); - return ((uint128_t)oc3 << 96) | ((uint128_t)oc2 << 64) | ((uint128_t)oc1 << 32) | oc0; -} - -uint128_t aes_subbytes_fwd(uint128_t x) { - uint32_t oc0 = aes_subword_fwd(aes_get_column(x, 0)); - uint32_t oc1 = aes_subword_fwd(aes_get_column(x, 1)); - uint32_t oc2 = aes_subword_fwd(aes_get_column(x, 2)); - uint32_t oc3 = aes_subword_fwd(aes_get_column(x, 3)); - return ((uint128_t)oc3 << 96) | ((uint128_t)oc2 << 64) | ((uint128_t)oc1 << 32) | oc0; -} - -uint128_t aes_subbytes_inv(uint128_t x) { - uint32_t oc0 = aes_subword_inv(aes_get_column(x, 0)); - uint32_t oc1 = aes_subword_inv(aes_get_column(x, 1)); - uint32_t oc2 = aes_subword_inv(aes_get_column(x, 2)); - uint32_t oc3 = aes_subword_inv(aes_get_column(x, 3)); - return ((uint128_t)oc3 << 96) | ((uint128_t)oc2 << 64) | ((uint128_t)oc1 << 32) | oc0; -} - -uint128_t aes_mixcolumns_fwd(uint128_t x) { - uint32_t oc0 = aes_mixcolumn_fwd(aes_get_column(x, 0)); - uint32_t oc1 = aes_mixcolumn_fwd(aes_get_column(x, 1)); - uint32_t oc2 = aes_mixcolumn_fwd(aes_get_column(x, 2)); - uint32_t oc3 = aes_mixcolumn_fwd(aes_get_column(x, 3)); - return ((uint128_t)oc3 << 96) | ((uint128_t)oc2 << 64) | ((uint128_t)oc1 << 32) | oc0; -} - -uint128_t aes_mixcolumns_inv(uint128_t x) { - uint32_t oc0 = aes_mixcolumn_inv(aes_get_column(x, 0)); - uint32_t oc1 = aes_mixcolumn_inv(aes_get_column(x, 1)); - uint32_t oc2 = aes_mixcolumn_inv(aes_get_column(x, 2)); - uint32_t oc3 = aes_mixcolumn_inv(aes_get_column(x, 3)); - return ((uint128_t)oc3 << 96) | ((uint128_t)oc2 << 64) | ((uint128_t)oc1 << 32) | oc0; -} - -uint32_t aes_rotword(uint32_t x) { - uint8_t a0 = bit_sub<0, 7 - 0 + 1>(x); - uint8_t a1 = bit_sub<8, 15 - 8 + 1>(x); - uint8_t a2 = bit_sub<16, 23 - 16 + 1>(x); - uint8_t a3 = bit_sub<24, 31 - 24 + 1>(x); - return ((uint32_t)a0 << 24) | ((uint32_t)a3 << 16) | ((uint32_t)a2 << 8) | a1; -} - -std::function get_crypto_funct(unsigned funct6, unsigned vs1) { - switch(funct6) { - case 0b101000: // VAES.VV - case 0b101001: // VAES.VS - switch(vs1) { - case 0b00000: // VAESDM - return [](uint128_t state, uint128_t rkey, uint128_t) { - uint128_t sr = aes_shift_rows_inv(state); - uint128_t sb = aes_subbytes_inv(sr); - uint128_t ark = sb ^ rkey; - uint128_t mix = aes_mixcolumns_inv(ark); - return mix; - }; - case 0b00001: // VAESDF - return [](uint128_t state, uint128_t rkey, uint128_t) { - uint128_t sr = aes_shift_rows_inv(state); - uint128_t sb = aes_subbytes_inv(sr); - uint128_t ark = sb ^ rkey; - return ark; - }; - case 0b00010: // VAESEM - return [](uint128_t state, uint128_t rkey, uint128_t) { - uint128_t sb = aes_subbytes_fwd(state); - uint128_t sr = aes_shift_rows_fwd(sb); - uint128_t mix = aes_mixcolumns_fwd(sr); - uint128_t ark = mix ^ rkey; - return ark; - }; - case 0b00011: // VAESEF - return [](uint128_t state, uint128_t rkey, uint128_t) { - uint128_t sb = aes_subbytes_fwd(state); - uint128_t sr = aes_shift_rows_fwd(sb); - uint128_t ark = sr ^ rkey; - return ark; - }; - case 0b00111: // VAESZ - return [](uint128_t state, uint128_t rkey, uint128_t) { - uint128_t ark = state ^ rkey; - return ark; - }; - case 0b10000: // VSM4R - throw new std::runtime_error("Unsupported operation in get_crypto_funct"); - case 0b10001: // VGMUL - return [](uint128_t vd, uint128_t vs2, uint128_t) { - uint128_t Y = brev8(vd); - uint128_t H = brev8(vs2); - uint128_t Z = 0; - for(size_t bit = 0; bit < 128; bit++) { - if((Y >> bit) & 1) - Z ^= H; - bool reduce = (H >> 127) & 1; - H = H << 1; - if(reduce) - H ^= 0x87; - } - uint128_t result = brev8(Z); - return result; - }; - default: - throw new std::runtime_error("Unsupported operation in get_crypto_funct"); - } - case 0b100000: // VSM3ME - case 0b100001: // VSM4K - throw new std::runtime_error("Unsupported operation in get_crypto_funct"); - case 0b100010: // VAESKF1 - return [](uint128_t vd, uint128_t vs2, uint128_t r) { - auto extract_word = [](const uint128_t& value, int index) -> uint32_t { - return static_cast((value >> (32 * index)) & std::numeric_limits::max()); - }; - - uint32_t k0 = (vs2 >> 32 * 0) & std::numeric_limits::max(); - uint32_t k1 = (vs2 >> 32 * 1) & std::numeric_limits::max(); - uint32_t k2 = (vs2 >> 32 * 2) & std::numeric_limits::max(); - uint32_t k3 = (vs2 >> 32 * 3) & std::numeric_limits::max(); - uint32_t w0 = aes_subword_fwd(aes_rotword(k3)) ^ aes_decode_rcon(r) ^ k0; - uint32_t w1 = w0 ^ k1; - uint32_t w2 = w1 ^ k2; - uint32_t w3 = w2 ^ k3; - uint128_t result = (uint128_t(w3) << 96) | (uint128_t(w2) << 64) | (uint128_t(w1) << 32) | (uint128_t(w0)); - return result; - }; - case 0b101010: // VAESKF2 - return [](uint128_t vd, uint128_t vs2, uint128_t r) { - uint32_t k0 = (vs2 >> 32 * 0) & std::numeric_limits::max(); - uint32_t k1 = (vs2 >> 32 * 1) & std::numeric_limits::max(); - uint32_t k2 = (vs2 >> 32 * 2) & std::numeric_limits::max(); - uint32_t k3 = (vs2 >> 32 * 3) & std::numeric_limits::max(); - uint32_t rkb0 = (vd >> 32 * 0) & std::numeric_limits::max(); - uint32_t rkb1 = (vd >> 32 * 1) & std::numeric_limits::max(); - uint32_t rkb2 = (vd >> 32 * 2) & std::numeric_limits::max(); - uint32_t rkb3 = (vd >> 32 * 3) & std::numeric_limits::max(); - uint32_t w0 = r & 1 ? aes_subword_fwd(k3) ^ rkb0 : aes_subword_fwd(aes_rotword(k3)) ^ aes_decode_rcon((r >> 1) - 1) ^ rkb0; - uint32_t w1 = w0 ^ rkb1; - uint32_t w2 = w1 ^ rkb2; - uint32_t w3 = w2 ^ rkb3; - uint128_t result = (uint128_t(w3) << 96) | (uint128_t(w2) << 64) | (uint128_t(w1) << 32) | (uint128_t(w0)); - return result; - }; - case 0b101011: // VSM3C - throw new std::runtime_error("Unsupported operation in get_crypto_funct"); - case 0b101100: // VGHSH - return [](uint128_t Y, uint128_t vs2, uint128_t X) { - auto H = brev8(vs2); - uint128_t Z = 0; - uint128_t S = brev8(Y ^ X); - for(size_t bit = 0; bit < 128; bit++) { - if((S >> bit) & 1) - Z ^= H; - bool reduce = (H >> 127) & 1; - H = H << 1; - if(reduce) - H ^= 0x87; - } - uint128_t result = brev8(Z); - return result; - }; - case 0b101101: // VSHA2MS - case 0b101110: // VSHA2CH - case 0b101111: // VSHA2CL - default: - throw new std::runtime_error("Unknown funct6 in get_crypto_funct"); - } -} -} // namespace softvector \ No newline at end of file diff --git a/src/vm/vector_functions.h b/src/vm/vector_functions.h index 38e3be5..db04488 100644 --- a/src/vm/vector_functions.h +++ b/src/vm/vector_functions.h @@ -32,155 +32,958 @@ // alex@minres.com - initial API and implementation //////////////////////////////////////////////////////////////////////////////// -#ifndef _VM_VECTOR_FUNCTIONS_H_ -#define _VM_VECTOR_FUNCTIONS_H_ +#ifndef RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ +#define RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ +#include #include -#include -#include -namespace softvector { -#ifndef _MSC_VER -using int128_t = __int128; -using uint128_t = unsigned __int128; -#endif -const unsigned RFS = 32; +#include -struct vtype_t { - uint64_t underlying; - vtype_t(uint32_t vtype_val); - vtype_t(uint64_t vtype_val); - unsigned sew(); - double lmul(); - bool vill(); - bool vma(); - bool vta(); -}; -class mask_bit_reference { - uint8_t* start; - uint8_t pos; +#include "iss/arch_if.h" +#include "iss/vm_types.h" +#include -public: - mask_bit_reference& operator=(const bool new_value); - mask_bit_reference(uint8_t* start, uint8_t pos); - operator bool() const; -}; +namespace softvec_if { +using indexed_load_store_t = std::function, uint8_t*, uint64_t, + uint64_t, softvector::vtype_t, bool, uint8_t, uint64_t, uint8_t, uint8_t)>; +template indexed_load_store_t getFunction() { + return [](void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, + uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, uint8_t segment_size) { + return softvector::vector_load_store_index(core, load_store_fn, V, vl, vstart, vtype, vm, vd, rs1, vs2, + segment_size); + }; +} +template +const std::array, 4> functionTable = { + {{getFunction(), getFunction(), + getFunction(), getFunction()}, + {getFunction(), getFunction(), + getFunction(), getFunction()}, + {getFunction(), getFunction(), + getFunction(), getFunction()}, + {getFunction(), getFunction(), + getFunction(), getFunction()}}}; +constexpr size_t map_index_size[9] = {std::numeric_limits::max(), + 0, + 1, + std::numeric_limits::max(), + 2, + std::numeric_limits::max(), + std::numeric_limits::max(), + std::numeric_limits::max(), + 3}; -struct vmask_view { - uint8_t* start; - size_t elem_count; - mask_bit_reference operator[](size_t) const; -}; -vmask_view read_vmask(uint8_t* V, uint16_t VLEN, uint16_t elem_count, uint8_t reg_idx = 0); -template vmask_view read_vmask(uint8_t* V, uint16_t elem_count, uint8_t reg_idx = 0); -std::function get_crypto_funct(unsigned funct6, unsigned vs1); - -template dest_elem_t brev(src_elem_t vs2); -template dest_elem_t brev8(src_elem_t vs2); - -template -uint64_t vector_load_store(void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, - uint64_t vstart, vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t segment_size, int64_t stride = 0, - bool use_stride = false); -template -uint64_t vector_load_store_index(void* core, std::function load_store_fn, uint8_t* V, - uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, - uint8_t segment_size); -template -void vector_vector_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1); -template -void vector_imm_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, typename std::make_signed::type imm); -template -void vector_vector_carry(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, unsigned vd, - unsigned vs2, unsigned vs1, signed carry); -template -void vector_imm_carry(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, unsigned vd, unsigned vs2, - typename std::make_signed::type imm, signed carry); -template -void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1); -template -void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm); -template -void vector_unary_op(uint8_t* V, unsigned unary_op, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2); -template -void mask_vector_vector_op(uint8_t* V, unsigned funct, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1); -template -void mask_vector_imm_op(uint8_t* V, unsigned funct, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, typename std::make_signed::type imm); -void carry_vector_vector_op(uint8_t* V, unsigned funct, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - unsigned vs1); -template -void carry_vector_imm_op(uint8_t* V, unsigned funct, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - typename std::make_signed::type imm); -template -bool sat_vector_vector_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, int64_t vxrm, bool vm, - unsigned vd, unsigned vs2, unsigned vs1); -template -bool sat_vector_imm_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, int64_t vxrm, bool vm, - unsigned vd, unsigned vs2, typename std::make_signed::type imm); -template -void vector_red_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1); -template -void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1); -template uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2); -template uint64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2); -template void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2); -template -void viota(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2); -template void vid(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd); -template uint64_t scalar_move(uint8_t* V, vtype_t vtype, unsigned vd, uint64_t val, bool to_vector); -template -void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm); -template -void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm); -template -void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm); -template -void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm); -template -void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1); -template -void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm); -template -void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, unsigned vd, unsigned vs2, unsigned vs1); -template void vector_whole_move(uint8_t* V, unsigned vd, unsigned vs2, unsigned count); -template -void fp_vector_red_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1, uint8_t rm); -template -void fp_vector_vector_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1, uint8_t rm); -template -void fp_vector_imm_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, src1_elem_t imm, uint8_t rm); -template -void fp_vector_unary_op(uint8_t* V, unsigned encoding_space, unsigned unary_op, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, - unsigned vd, unsigned vs2, uint8_t rm); -template -void fp_vector_unary_w(uint8_t* V, unsigned unary_op, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint8_t rm); -template -void fp_vector_unary_n(uint8_t* V, unsigned unary_op, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint8_t rm); -template -void mask_fp_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - unsigned vs1, uint8_t rm); -template -void mask_fp_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - elem_t imm, uint8_t rm); -template -void vector_vector_crypto(uint8_t* V, unsigned funct6, uint64_t eg_len, uint64_t eg_start, vtype_t vtype, unsigned vd, unsigned vs2, - unsigned vs1); -template -void vector_scalar_crypto(uint8_t* V, unsigned funct6, uint64_t eg_len, uint64_t eg_start, vtype_t vtype, unsigned vd, unsigned vs2, - unsigned vs1); -template -void vector_imm_crypto(uint8_t* V, unsigned funct6, uint64_t eg_len, uint64_t eg_start, vtype_t vtype, unsigned vd, unsigned vs2, - uint8_t imm); -template -void vector_crypto(uint8_t* V, unsigned funct6, uint64_t eg_len, uint64_t eg_start, vtype_t vtype, unsigned vd, unsigned vs2, unsigned vs1); -} // namespace softvector -#include "vm/vector_functions.hpp" -#endif /* _VM_VECTOR_FUNCTIONS_H_ */ +inline bool softvec_read(void* core, uint64_t addr, uint64_t length, uint8_t* data) { + // Read length bytes from addr into *data + iss::status status = static_cast(core)->read(iss::address_type::PHYSICAL, iss::access_type::READ, + 0 /*traits::MEM*/, addr, length, data); + return status == iss::Ok; +} +inline bool softvec_write(void* core, uint64_t addr, uint64_t length, uint8_t* data) { + // Write length bytes from addr into *data + iss::status status = static_cast(core)->write(iss::address_type::PHYSICAL, iss::access_type::READ, + 0 /*traits::MEM*/, addr, length, data); + return status == iss::Ok; +} +template +uint64_t vlseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b101: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b110: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b111: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +template +uint64_t vsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b101: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b110: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + case 0b111: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +template +uint64_t vlsseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size, int64_t stride) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, stride, + true); + case 0b101: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b110: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b111: + return softvector::vector_load_store(core, softvec_read, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +template +uint64_t vssseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t width_val, uint8_t segment_size, int64_t stride) { + switch(width_val) { + case 0b000: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b101: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b110: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + case 0b111: + return softvector::vector_load_store(core, softvec_write, V, vl, vstart, vtype, vm, vd, rs1_val, segment_size, + stride, true); + default: + throw new std::runtime_error("Unsupported width bit value"); + } +} +template +uint64_t vlxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1_val, + uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered) { + return functionTable[map_index_size[index_byte_size]][data_byte_size](core, softvec_read, V, vl, vstart, vtype, vm, vd, + rs1_val, vs2, segment_size); +} +template +uint64_t vsxseg(void* core, uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vs3, uint64_t rs1_val, + uint8_t vs2, uint8_t segment_size, uint8_t index_byte_size, uint8_t data_byte_size, bool ordered) { + return functionTable[map_index_size[index_byte_size]][data_byte_size](core, softvec_write, V, vl, vstart, vtype, vm, vs3, + rs1_val, vs2, segment_size); +} +template +void vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_extend(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint8_t target_sew_pow, uint8_t frac_pow) { + switch(target_sew_pow) { + case 4: // uint16_t target + if(frac_pow != 1) + throw new std::runtime_error("Unsupported frac_pow"); + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 5: // uint32_t target + switch(frac_pow) { + case 1: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 2: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported frac_pow"); + } + case 6: // uint64_t target + switch(frac_pow) { + case 1: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 2: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 3: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported frac_pow"); + } + default: + throw new std::runtime_error("Unsupported target_sew_pow"); + } +} +template +void vector_vector_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t sew_val, int8_t carry) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b001: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b010: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + case 0b011: + return softvector::vector_vector_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, vs1, carry); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_imm_carry(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val, int8_t carry) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b001: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b010: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + case 0b011: + return softvector::vector_imm_carry(V, funct6, funct3, vl, vstart, vtype, vd, vs2, imm, carry); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void carry_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, + unsigned vs2, unsigned vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::carry_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void carry_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, + unsigned vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::carry_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void mask_vector_vector_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + unsigned vd, unsigned vs2, unsigned vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::mask_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void mask_vector_imm_op(uint8_t* V, unsigned funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + unsigned vd, unsigned vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::mask_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_merge(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +bool sat_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, + uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b001: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b010: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b011: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +bool sat_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, + bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b001: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b010: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b011: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +bool sat_vector_vector_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, + uint64_t vxrm, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b001: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b010: + return softvector::sat_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +bool sat_vector_imm_vw(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint64_t vxrm, + bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b001: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b010: + return softvector::sat_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vxrm, vm, vd, vs2, imm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1) { + return softvector::mask_mask_op(V, funct6, funct3, vl, vstart, vd, vs2, vs1); +} +template uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { + return softvector::vcpop(V, vl, vstart, vm, vs2); +} +template int64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { + return softvector::vfirst(V, vl, vstart, vm, vs2); +} +template void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2) { + return softvector::mask_set_op(V, enc, vl, vstart, vm, vd, vs2); +} +template +void viota(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + case 0b001: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + case 0b010: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + case 0b011: + return softvector::viota(V, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vid(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + case 0b001: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + case 0b010: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + case 0b011: + return softvector::vid(V, vl, vstart, vtype, vm, vd); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void scalar_to_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint64_t val, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + softvector::scalar_move(V, vtype, vd, val, true); + break; + case 0b001: + softvector::scalar_move(V, vtype, vd, val, true); + break; + case 0b010: + softvector::scalar_move(V, vtype, vd, val, true); + break; + case 0b011: + softvector::scalar_move(V, vtype, vd, val, true); + break; + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template uint64_t scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::scalar_move(V, vtype, vd, 0, false); + case 0b001: + return softvector::scalar_move(V, vtype, vd, 0, false); + case 0b010: + return softvector::scalar_move(V, vtype, vd, 0, false); + case 0b011: + return softvector::scalar_move(V, vtype, vd, 0, false); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, + uint64_t imm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_vector_gatherei16(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint8_t vs1, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b001: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b010: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + case 0b011: + return softvector::vector_vector_gather(V, vl, vstart, vtype, vm, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint64_t imm, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b001: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b010: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + case 0b011: + return softvector::vector_imm_gather(V, vl, vstart, vtype, vm, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, uint8_t vs1, + uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b001: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b010: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + case 0b011: + return softvector::vector_compress(V, vl, vstart, vtype, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template void vector_whole_move(uint8_t* V, uint8_t vd, uint8_t vs2, uint8_t count) { + return softvector::vector_whole_move(V, vd, vs2, count); +} +template uint64_t fp_scalar_from_vector(uint8_t* V, softvector::vtype_t vtype, unsigned vd, uint8_t sew_val) { + return scalar_from_vector(V, vtype, vd, sew_val); +} +template +void fp_vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, + uint64_t imm, uint8_t sew_val) { + return vector_slide1up(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); +} +template +void fp_vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, unsigned vd, unsigned vs2, + uint64_t imm, uint8_t sew_val) { + return vector_slide1down(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); +} +template +void fp_vector_red_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void fp_vector_red_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b001: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_red_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would require 128 bits vs2 value + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void fp_vector_vector_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void fp_vector_imm_wv(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void fp_vector_vector_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, + rm); + case 0b010: + return softvector::fp_vector_vector_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, vs1, + rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void fp_vector_imm_ww(uint8_t* V, uint8_t funct6, uint8_t funct3, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, + uint8_t vd, uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::fp_vector_imm_op(V, funct6, funct3, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void fp_vector_unary_op(uint8_t* V, uint8_t encoding_space, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, + bool vm, uint8_t vd, uint8_t vs2, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: + return softvector::fp_vector_unary_op(V, encoding_space, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void mask_fp_vector_vector_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b010: + return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + case 0b011: + return softvector::mask_fp_vector_vector_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, vs1, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void mask_fp_vector_imm_op(uint8_t* V, uint8_t funct6, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint64_t imm, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + throw new std::runtime_error("Unsupported sew bit value"); + case 0b001: + return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b010: + return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + case 0b011: + return softvector::mask_fp_vector_imm_op(V, funct6, vl, vstart, vtype, vm, vd, vs2, imm, rm); + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void fp_vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, + uint64_t imm, uint8_t sew_val) { + vector_imm_merge(V, vl, vstart, vtype, vm, vd, vs2, imm, sew_val); +} +template +void fp_vector_unary_w(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b001: + return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_w(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: // would widen to 128 bits + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void fp_vector_unary_n(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t rm, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b001: + return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b010: + return softvector::fp_vector_unary_n(V, unary_op, vl, vstart, vtype, vm, vd, vs2, rm); + case 0b011: // would require 128 bit value to narrow + default: + throw new std::runtime_error("Unsupported sew bit value"); + } +} +template +void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, + uint8_t vs2, uint8_t sew_val) { + switch(sew_val) { + case 0b000: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b001: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b010: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + case 0b011: + return softvector::vector_unary_op(V, unary_op, vl, vstart, vtype, vm, vd, vs2); + default: + throw new std::runtime_error("Unsupported sew_val"); + } +} +} // namespace softvec_if +#endif /* RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ */ diff --git a/src/vm/vector_functions.hpp b/src/vm/vector_functions.hpp deleted file mode 100644 index e9df5aa..0000000 --- a/src/vm/vector_functions.hpp +++ /dev/null @@ -1,2281 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2025, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -// Contributors: -// alex@minres.com - initial API and implementation -//////////////////////////////////////////////////////////////////////////////// -#pragma once -extern "C" { -#include -} -#include "softfloat_types.h" -#include "specialize.h" -#include "vm/fp_functions.h" -#include "vm/vector_functions.h" -#include -#include -#include -#include -#include -#include -#include -#include -#ifndef _VM_VECTOR_FUNCTIONS_H_ -#error __FILE__ should only be included from vector_functions.h -#endif -#include - -#ifdef __SIZEOF_INT128__ -template <> struct std::make_signed<__uint128_t> { using type = __int128_t; }; -template <> struct std::make_signed<__int128_t> { using type = __int128_t; }; -// helper struct to make calling twice on 128-bit datatypes legal at compile time -struct poison128_t { - poison128_t() { throw std::runtime_error("Attempt to use twice<__uint128_t>::type at runtime"); } - poison128_t(const poison128_t&) { throw std::runtime_error("Copy of poison128_t is not allowed"); } - template poison128_t(U) { throw std::runtime_error("Conversion to poison128_t is not allowed"); } - operator __uint128_t() const { throw std::runtime_error("Use of poison128_t as __uint128_t is not allowed"); } -}; -template <> struct std::make_signed { using type = poison128_t; }; -#endif - -namespace softvector { - -template struct vreg_view { - uint8_t* start; - size_t vlmax; - elem_t& operator[](size_t idx) { - assert(idx < vlmax); - return *(reinterpret_cast(start) + idx); - } -}; -template vreg_view get_vreg(uint8_t* V, uint8_t reg_idx, uint16_t vlmax) { - assert(V + vlmax * sizeof(elem_t) <= V + VLEN * RFS / 8); - return {V + VLEN / 8 * reg_idx, vlmax}; -} -template vmask_view read_vmask(uint8_t* V, uint16_t vlmax, uint8_t reg_idx) { - uint8_t* mask_start = V + VLEN / 8 * reg_idx; - assert(mask_start + vlmax / 8 <= V + VLEN * RFS / 8); - return {mask_start, vlmax}; -} - -template constexpr elem_t shift_mask() { - static_assert(std::numeric_limits::is_integer, "shift_mask only supports integer types"); - return std::numeric_limits::digits - 1; -} -template constexpr T agnostic_behavior(T val) { -#ifdef AGNOSTIC_ONES - return std::numeric_limits::max(); -#else - return val; -#endif -} - -enum FUNCT3 { - OPIVV = 0b000, - OPFVV = 0b001, - OPMVV = 0b010, - OPIVI = 0b011, - OPIVX = 0b100, - OPFVF = 0b101, - OPMVX = 0b110, -}; -template struct twice; -template <> struct twice { using type = int16_t; }; -template <> struct twice { using type = uint16_t; }; -template <> struct twice { using type = int32_t; }; -template <> struct twice { using type = uint32_t; }; -template <> struct twice { using type = int64_t; }; -template <> struct twice { using type = uint64_t; }; -#ifdef __SIZEOF_INT128__ -template <> struct twice { using type = __int128_t; }; -template <> struct twice { using type = __uint128_t; }; - -template <> struct twice<__uint128_t> { using type = poison128_t; }; -template <> struct twice<__int128_t> { using type = poison128_t; }; - -#endif -template using twice_t = typename twice::type; // for convenience -template constexpr TO sext(FROM val) { - return static_cast>(static_cast>(val)); -}; - -template -uint64_t vector_load_store(void* core, std::function load_store_fn, uint8_t* V, uint64_t vl, - uint64_t vstart, vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t segment_size, int64_t stride, - bool use_stride) { - unsigned vlmax = VLEN * vtype.lmul() / vtype.sew(); - auto emul_stride = std::max(vlmax, VLEN / (sizeof(eew_t) * 8)); - auto vd_view = get_vreg(V, vd, emul_stride * segment_size); - vmask_view mask_reg = read_vmask(V, VLEN, vlmax); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) { - signed stride_offset = stride * idx; - auto seg_offset = use_stride ? 0 : segment_size * sizeof(eew_t) * idx; - for(size_t s_idx = 0; s_idx < segment_size; s_idx++) { - eew_t* addressed_elem = &vd_view[idx + emul_stride * s_idx]; - uint64_t addr = rs1 + stride_offset + seg_offset + s_idx * sizeof(eew_t); - if(!load_store_fn(core, addr, sizeof(eew_t), reinterpret_cast(addressed_elem))) - return idx; - } - } else if(vtype.vma()) - for(size_t s_idx = 0; s_idx < segment_size; s_idx++) - vd_view[idx + emul_stride * s_idx] = agnostic_behavior(vd_view[idx + emul_stride * s_idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - for(size_t s_idx = 0; s_idx < segment_size; s_idx++) - vd_view[idx + emul_stride * s_idx] = agnostic_behavior(vd_view[idx + emul_stride * s_idx]); - return 0; -} -// eew for index registers, sew for data register -template -uint64_t vector_load_store_index(void* core, std::function load_store_fn, uint8_t* V, - uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, uint8_t vd, uint64_t rs1, uint8_t vs2, - uint8_t segment_size) { - // All load stores are ordered in this implementation - unsigned vlmax = VLEN * vtype.lmul() / vtype.sew(); - auto emul_stride = std::max(vlmax, VLEN / (sizeof(sew_t) * 8)); - auto vd_view = get_vreg(V, vd, emul_stride * segment_size); - auto vs2_view = get_vreg(V, vs2, vlmax); - vmask_view mask_reg = read_vmask(V, VLEN, vlmax); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) { - uint64_t index_offset = vs2_view[idx] & std::numeric_limits>::max(); - for(size_t s_idx = 0; s_idx < segment_size; s_idx++) { - sew_t* addressed_elem = &vd_view[idx + emul_stride * s_idx]; - uint64_t addr = rs1 + index_offset + s_idx * sizeof(sew_t); - if(!load_store_fn(core, addr, sizeof(sew_t), reinterpret_cast(addressed_elem))) - return idx; - } - } else if(vtype.vma()) - for(size_t s_idx = 0; s_idx < segment_size; s_idx++) - vd_view[idx + emul_stride * s_idx] = agnostic_behavior(vd_view[idx + emul_stride * s_idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - for(size_t s_idx = 0; s_idx < segment_size; s_idx++) - vd_view[idx + emul_stride * s_idx] = agnostic_behavior(vd_view[idx + emul_stride * s_idx]); - return 0; -} -template -std::function get_funct(unsigned funct6, unsigned funct3) { - if(funct3 == OPIVV || funct3 == OPIVX || funct3 == OPIVI) - switch(funct6) { - case 0b000000: // VADD - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs2 + vs1; }; - case 0b000001: // VANDN - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs2 & ~vs1; }; - case 0b000010: // VSUB - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs2 - vs1; }; - case 0b000011: // VRSUB - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs1 - vs2; }; - case 0b000100: // VMINU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return std::min(vs2, vs1); }; - case 0b000101: // VMIN - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return std::min>(vs2, vs1); }; - case 0b000110: // VMAXU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return std::max(vs2, vs1); }; - case 0b000111: // VMAX - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return std::max>(vs2, vs1); }; - case 0b001001: // VAND - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs1 & vs2; }; - case 0b001010: // VOR - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs1 | vs2; }; - case 0b001011: // VXOR - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs1 ^ vs2; }; - case 0b010000: // VADC - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs2 + vs1; }; - case 0b010010: // VSBC - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast>(static_cast>(vs2) - - static_cast>(vs1)); - }; - case 0b010100: // VROR - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - constexpr dest_elem_t bits = sizeof(src2_elem_t) * 8; - auto shamt = vs1 & shift_mask(); - return (vs2 >> shamt) | (vs2 << (bits - shamt)); - }; - case 0b010101: { // VROL - if(funct3 == OPIVI) - return get_funct(0b010100, funct3); - else - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - constexpr dest_elem_t bits = sizeof(src2_elem_t) * 8; - auto shamt = vs1 & shift_mask(); - return (vs2 << shamt) | (vs2 >> (bits - shamt)); - }; - } - case 0b100101: // VSLL - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs2 << (vs1 & shift_mask()); }; - case 0b101000: // VSRL - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs2 >> (vs1 & shift_mask()); }; - case 0b101001: // VSRA - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast>(vs2) >> (vs1 & shift_mask()); - }; - case 0b101100: // VNSRL - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs2 >> (vs1 & shift_mask()); }; - case 0b101101: // VNSRA - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast>(vs2) >> (vs1 & shift_mask()); - }; - case 0b110101: // VWSLL - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast(vs2) << (vs1 & (shift_mask())); - }; - default: - throw new std::runtime_error("Unknown funct6 in get_funct"); - } - else if(funct3 == OPMVV || funct3 == OPMVX) - switch(funct6) { - case 0b100000: // VDIVU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) -> dest_elem_t { - if(vs1 == 0) - return -1; - else - return vs2 / vs1; - }; - case 0b100001: // VDIV - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) -> dest_elem_t { - if(vs1 == 0) - return -1; - else if(vs2 == std::numeric_limits>::min() && - static_cast>(vs1) == -1) - return vs2; - else - return static_cast>(vs2) / static_cast>(vs1); - }; - case 0b100010: // VREMU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) -> dest_elem_t { - if(vs1 == 0) - return vs2; - else - return vs2 % vs1; - }; - case 0b100011: // VREM - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) -> dest_elem_t { - if(vs1 == 0) - return vs2; - else if(vs2 == std::numeric_limits>::min() && - static_cast>(vs1) == -1) - return 0; - else - return static_cast>(vs2) % static_cast>(vs1); - }; - case 0b100100: // VMULHU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return (static_cast>(vs2) * static_cast>(vs1)) >> sizeof(dest_elem_t) * 8; - }; - case 0b100101: // VMUL - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast>(vs2) * static_cast>(vs1); - }; - case 0b100110: // VMULHSU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return (sext>(vs2) * static_cast>(vs1)) >> sizeof(dest_elem_t) * 8; - }; - case 0b100111: // VMULH - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return (sext>(vs2) * sext>(vs1)) >> sizeof(dest_elem_t) * 8; - }; - case 0b101001: // VMADD - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs1 * vd + vs2; }; - case 0b101011: // VNMSUB - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return -1 * (vs1 * vd) + vs2; }; - case 0b101101: // VMACC - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return vs1 * vs2 + vd; }; - case 0b101111: // VNMSAC - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return -1 * (vs1 * vs2) + vd; }; - case 0b110000: // VWADDU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast(vs2) + static_cast(vs1); - }; - case 0b110001: // VWADD - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return sext(vs2) + sext(vs1); }; - case 0b110010: // VWSUBU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast(vs2) - static_cast(vs1); - }; - case 0b110011: // VWSUB - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return sext(vs2) - sext(vs1); }; - case 0b110100: // VWADDU.W - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast(vs2) + static_cast(vs1); - }; - case 0b110101: // VWADD.W - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return sext(vs2) + sext(vs1); }; - case 0b110110: // VWSUBU.W - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast(vs2) - static_cast(vs1); - }; - case 0b110111: // VWSUB.W - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return sext(vs2) - sext(vs1); }; - case 0b111000: // VWMULU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return (static_cast(vs2) * static_cast(vs1)); - }; - case 0b111010: // VWMULSU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return sext(vs2) * static_cast(vs1); }; - case 0b111011: // VWMUL - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return sext(vs2) * sext(vs1); }; - case 0b111100: // VWMACCU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast(vs1) * static_cast(vs2) + vd; - }; - case 0b111101: // VWMACC - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { return sext(vs1) * sext(vs2) + vd; }; - case 0b111110: // VWMACCUS - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return static_cast(vs1) * sext(vs2) + vd; - }; - case 0b111111: // VWMACCSU - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return sext(vs1) * static_cast(vs2) + vd; - }; - case 0b001100: // VCLMUL - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t output = 0; - for(size_t i = 0; i <= sizeof(dest_elem_t) * 8 - 1; i++) { - if((vs2 >> i) & 1) - output = output ^ (vs1 << i); - } - return output; - }; - case 0b001101: // VCLMULH - return [](dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t output = 0; - for(size_t i = 1; i < sizeof(dest_elem_t) * 8; i++) { - if((vs2 >> i) & 1) - output = output ^ (vs1 >> (sizeof(dest_elem_t) * 8 - i)); - } - return output; - }; - default: - throw new std::runtime_error("Unknown funct6 in get_funct"); - } - else - throw new std::runtime_error("Unknown funct3 in get_funct"); -} -template -void vector_vector_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_view = get_vreg(V, vs1, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_funct(funct6, funct3); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = fn(vd_view[idx], vs2_view[idx], vs1_view[idx]); - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -void vector_imm_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, typename std::make_signed::type imm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_funct(funct6, funct3); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = fn(vd_view[idx], vs2_view[idx], imm); - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -void vector_vector_carry(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, unsigned vd, - unsigned vs2, unsigned vs1, signed carry) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_view = get_vreg(V, vs1, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_funct(funct6, funct3); - for(size_t idx = vstart; idx < vl; idx++) - vd_view[idx] = fn(vd_view[idx], vs2_view[idx], vs1_view[idx]) + carry * mask_reg[idx]; - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -void vector_imm_carry(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, unsigned vd, unsigned vs2, - typename std::make_signed::type imm, signed carry) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_funct(funct6, funct3); - for(size_t idx = vstart; idx < vl; idx++) - vd_view[idx] = fn(vd_view[idx], vs2_view[idx], imm) + carry * mask_reg[idx]; - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -void vector_vector_merge(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_view = get_vreg(V, vs1, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = vs1_view[idx]; - else - vd_view[idx] = vs2_view[idx]; - } -} -template -void vector_imm_merge(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = imm; - else - vd_view[idx] = vs2_view[idx]; - } -} -template std::function get_mask_funct(unsigned funct6, unsigned funct3) { - if(funct3 == OPIVV || funct3 == OPIVX || funct3 == OPIVI) - switch(funct6) { - case 0b011000: // VMSEQ - return [](elem_t vs2, elem_t vs1) { return vs2 == vs1; }; - case 0b011001: // VMSNE - return [](elem_t vs2, elem_t vs1) { return vs2 != vs1; }; - case 0b011010: // VMSLTU - return [](elem_t vs2, elem_t vs1) { return vs2 < vs1; }; - case 0b011011: // VMSLT - return [](elem_t vs2, elem_t vs1) { - return static_cast>(vs2) < static_cast>(vs1); - }; - case 0b011100: // VMSLEU - return [](elem_t vs2, elem_t vs1) { return vs2 <= vs1; }; - case 0b011101: // VMSLE - return [](elem_t vs2, elem_t vs1) { - return static_cast>(vs2) <= static_cast>(vs1); - }; - case 0b011110: // VMSGTU - return [](elem_t vs2, elem_t vs1) { return vs2 > vs1; }; - case 0b011111: // VMSGT - return [](elem_t vs2, elem_t vs1) { - return static_cast>(vs2) > static_cast>(vs1); - }; - - default: - throw new std::runtime_error("Unknown funct6 in get_mask_funct"); - } - else if(funct3 == OPMVV || funct3 == OPMVX) - switch(funct6) { - case 0b011000: // VMANDN - return [](elem_t vs2, elem_t vs1) { return vs2 & !vs1; }; - case 0b011001: // VMAND - return [](elem_t vs2, elem_t vs1) { return vs2 & vs1; }; - case 0b011010: // VMOR - return [](elem_t vs2, elem_t vs1) { return vs2 | vs1; }; - case 0b011011: // VMXOR - return [](elem_t vs2, elem_t vs1) { return vs2 ^ vs1; }; - case 0b011100: // VMORN - return [](elem_t vs2, elem_t vs1) { return vs2 | !vs1; }; - case 0b011101: // VMNAND - return [](elem_t vs2, elem_t vs1) { return !(vs2 & vs1); }; - case 0b011110: // VMNOR - return [](elem_t vs2, elem_t vs1) { return !(vs2 | vs1); }; - case 0b011111: // VMXNOR - return [](elem_t vs2, elem_t vs1) { return !(vs2 ^ vs1); }; - default: - throw new std::runtime_error("Unknown funct6 in get_mask_funct"); - } - else - throw new std::runtime_error("Unknown funct3 in get_mask_funct"); -} -template -void mask_vector_vector_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_view = get_vreg(V, vs1, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - vmask_view vd_mask_view = read_vmask(V, VLEN, vd); - auto fn = get_mask_funct(funct6, funct3); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_mask_view[idx] = fn(vs2_view[idx], vs1_view[idx]); - else if(vtype.vma()) - vd_mask_view[idx] = agnostic_behavior(vd_mask_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < VLEN; idx++) - vd_mask_view[idx] = agnostic_behavior(vd_mask_view[idx]); -} -template -void mask_vector_imm_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, typename std::make_signed::type imm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - vmask_view vd_mask_view = read_vmask(V, VLEN, vd); - auto fn = get_mask_funct(funct6, funct3); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_mask_view[idx] = fn(vs2_view[idx], imm); - else if(vtype.vma()) - vd_mask_view[idx] = agnostic_behavior(vd_mask_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < VLEN; idx++) - vd_mask_view[idx] = agnostic_behavior(vd_mask_view[idx]); -} -template -std::function get_unary_fn(unsigned unary_op) { - switch(unary_op) { - case 0b00111: // VSEXT.VF2 - case 0b00101: // VSEXT.VF4 - case 0b00011: // VSEXT.VF8 - return [](src2_elem_t vs2) { return static_cast>(vs2); }; - case 0b00110: // VZEXT.VF2 - case 0b00100: // VZEXT.VF4 - case 0b00010: // VZEXT.VF8 - return [](src2_elem_t vs2) { return vs2; }; - case 0b01000: // VBREV8 - return [](src2_elem_t vs2) { return brev8(vs2); }; - case 0b01001: // VREV8 - return [](src2_elem_t vs2) { - constexpr unsigned byte_count = sizeof(src2_elem_t); - dest_elem_t result = 0; - for(size_t i = 0; i < byte_count; ++i) { - result <<= 8; - result |= (vs2 & 0xFF); - vs2 >>= 8; - } - return result; - }; - case 0b01010: // VBREV - return [](src2_elem_t vs2) { return brev(vs2); }; - case 0b01100: // VCLZ - return [](src2_elem_t vs2) { - if(std::is_same_v) - return static_cast(__builtin_clz(vs2)); - else if(std::is_same_v) - return static_cast(__builtin_clzl(vs2)); - else if(std::is_same_v) - return static_cast(__builtin_clzll(vs2)); - else { - constexpr dest_elem_t bits = sizeof(src2_elem_t) * 8; - if(vs2 == 0) - return bits; - dest_elem_t count = 0; - for(size_t i = bits - 1; i >= 0; --i) { - if((vs2 >> i) & 1) - break; - ++count; - } - return count; - } - }; - case 0b01101: // VCTZ - return [](src2_elem_t vs2) { - if(std::is_same_v) - return static_cast(__builtin_ctz(vs2)); - else if(std::is_same_v) - return static_cast(__builtin_ctzl(vs2)); - else if(std::is_same_v) - return static_cast(__builtin_ctzll(vs2)); - else { - constexpr dest_elem_t bits = sizeof(src2_elem_t) * 8; - if(vs2 == 0) - return bits; - dest_elem_t count = 0; - while((vs2 & 1) == 0) { - ++count; - vs2 >>= 1; - } - return count; - } - }; - case 0b01110: // VCPOP - return [](src2_elem_t vs2) { - if(std::is_same_v) - return static_cast(__builtin_popcount(vs2)); - else if(std::is_same_v) - return static_cast(__builtin_popcountl(vs2)); - else if(std::is_same_v) - return static_cast(__builtin_popcountll(vs2)); - else { - dest_elem_t count = 0; - while(vs2) { - count += vs2 & 1; - vs2 >>= 1; - } - return count; - } - }; - default: - throw new std::runtime_error("Unknown funct in get_unary_fn"); - } -} -template -void vector_unary_op(uint8_t* V, unsigned unary_op, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_unary_fn(unary_op); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = fn(vs2_view[idx]); - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template std::function get_carry_funct(unsigned funct) { - switch(funct) { - case 0b010001: // VMADC - return [](elem_t vs2, elem_t vs1, elem_t carry) { - return static_cast(vs2 + vs1 + carry) < std::max(vs1, vs2) || static_cast(vs2 + vs1) < std::max(vs1, vs2); - }; - case 0b010011: // VMSBC - return [](elem_t vs2, elem_t vs1, elem_t carry) { - return vs2 < static_cast(vs1 + carry) || (vs1 == std::numeric_limits::max() && carry); - }; - default: - throw new std::runtime_error("Unknown funct in get_carry_funct"); - } -} -template -void carry_vector_vector_op(uint8_t* V, unsigned funct, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - unsigned vs1) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_view = get_vreg(V, vs1, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - vmask_view vd_mask_view = read_vmask(V, vlmax, vd); - auto fn = get_carry_funct(funct); - for(size_t idx = vstart; idx < vl; idx++) { - elem_t carry = vm ? 0 : mask_reg[idx]; - vd_mask_view[idx] = fn(vs2_view[idx], vs1_view[idx], carry); - } - for(size_t idx = vl; idx < vlmax; idx++) - vd_mask_view[idx] = agnostic_behavior(vd_mask_view[idx]); -} -template -void carry_vector_imm_op(uint8_t* V, unsigned funct, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - typename std::make_signed::type imm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - vmask_view vd_mask_view = read_vmask(V, vlmax, vd); - auto fn = get_carry_funct(funct); - for(size_t idx = vstart; idx < vl; idx++) { - elem_t carry = vm ? 0 : mask_reg[idx]; - vd_mask_view[idx] = fn(vs2_view[idx], imm, carry); - } - for(size_t idx = vl; idx < vlmax; idx++) - vd_mask_view[idx] = agnostic_behavior(vd_mask_view[idx]); -} -template bool get_rounding_increment(T v, uint64_t d, int64_t vxrm) { - if(d == 0) - return 0; - switch(vxrm & 0b11) { - case 0b00: - return (v >> (d - 1)) & 1; - case 0b01: - return ((v >> (d - 1)) & 1) && (((v & ((1 << (d - 1)) - 1)) != 0) || ((v >> d) & 1)); - case 0b10: - return false; - case 0b11: - return (!(v & (static_cast(1) << d)) && ((v & ((static_cast(1) << d) - 1)) != 0)); - } - return false; -} -template T roundoff(T v, uint64_t d, int64_t vxrm) { - unsigned r = get_rounding_increment(v, d, vxrm); - return (v >> d) + r; -} -template -std::function get_sat_funct(unsigned funct6, unsigned funct3) { - if(funct3 == OPIVV || funct3 == OPIVX || funct3 == OPIVI) - switch(funct6) { - case 0b100000: // VSADDU - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - auto res = static_cast>(vs2) + static_cast>(vs1); - if(res > std::numeric_limits::max()) { - vd = std::numeric_limits::max(); - return 1; - } else { - vd = res; - return 0; - } - }; - case 0b100001: // VSADD - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - auto res = static_cast>>(static_cast>(vs2)) + - static_cast>>(static_cast>(vs1)); - if(res < std::numeric_limits>::min()) { - vd = std::numeric_limits>::min(); - return 1; - } else if(res > std::numeric_limits>::max()) { - vd = std::numeric_limits>::max(); - return 1; - } else { - vd = res; - return 0; - } - }; - case 0b100010: // VSSUBU - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - if(vs2 < vs1) { - vd = 0; - return 1; - } else { - vd = vs2 - vs1; - return 0; - } - }; - case 0b100011: // VSSUB - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - auto res = static_cast>>(static_cast>(vs2)) - - static_cast>>(static_cast>(vs1)); - if(res < std::numeric_limits>::min()) { - vd = std::numeric_limits>::min(); - return 1; - } else if(res > std::numeric_limits>::max()) { - vd = std::numeric_limits>::max(); - return 1; - } else { - vd = res; - return 0; - } - }; - case 0b100111: // VSMUL - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - auto big_val = static_cast>>(static_cast>(vs2)) * - static_cast>>(static_cast>(vs1)); - auto res = roundoff(big_val, vtype.sew() - 1, vxrm); - if(res < std::numeric_limits>::min()) { - vd = std::numeric_limits>::min(); - return 1; - } else if(res > std::numeric_limits>::max()) { - vd = std::numeric_limits>::max(); - return 1; - } else { - vd = res; - return 0; - } - }; - case 0b101010: // VSSRL - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - vd = roundoff(vs2, vs1 & shift_mask(), vxrm); - return 0; - }; - case 0b101011: // VSSRA - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - vd = roundoff(static_cast>(vs2), vs1 & shift_mask(), vxrm); - return 0; - }; - case 0b101110: // VNCLIPU - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - auto res = roundoff(vs2, vs1 & shift_mask(), vxrm); - if(res > std::numeric_limits::max()) { - vd = std::numeric_limits::max(); - return 1; - } else { - vd = res; - return 0; - } - }; - case 0b101111: // VNCLIP - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - auto res = roundoff(static_cast>(vs2), vs1 & shift_mask(), vxrm); - if(res < std::numeric_limits>::min()) { - vd = std::numeric_limits>::min(); - return 1; - } else if(res > std::numeric_limits>::max()) { - vd = std::numeric_limits>::max(); - return 1; - } else { - vd = res; - return 0; - } - }; - default: - throw new std::runtime_error("Unknown funct6 in get_sat_funct"); - } - else if(funct3 == OPMVV || funct3 == OPMVX) - switch(funct6) { - case 0b001000: // VAADDU - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - auto res = static_cast(vs2) + static_cast>(vs1); - vd = roundoff(res, 1, vxrm); - return 0; - }; - case 0b001001: // VAADD - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - auto res = sext>(vs2) + sext>(vs1); - vd = roundoff(res, 1, vxrm); - return 0; - }; - case 0b001010: // VASUBU - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - auto res = static_cast(vs2) - static_cast>(vs1); - vd = roundoff(res, 1, vxrm); - return 0; - }; - case 0b001011: // VASUB - return [](uint64_t vxrm, vtype_t vtype, dest_elem_t& vd, src2_elem_t vs2, src1_elem_t vs1) { - auto res = sext>(vs2) - sext>(vs1); - vd = roundoff(res, 1, vxrm); - return 0; - }; - default: - throw new std::runtime_error("Unknown funct6 in get_sat_funct"); - } - else - throw new std::runtime_error("Unknown funct3 in get_sat_funct"); -} -template -bool sat_vector_vector_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, int64_t vxrm, bool vm, - unsigned vd, unsigned vs2, unsigned vs1) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - bool saturated = false; - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_view = get_vreg(V, vs1, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_sat_funct(funct6, funct3); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - saturated |= fn(vxrm, vtype, vd_view[idx], vs2_view[idx], vs1_view[idx]); - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) { - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - return saturated; -} -template -bool sat_vector_imm_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, int64_t vxrm, bool vm, - unsigned vd, unsigned vs2, typename std::make_signed::type imm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - bool saturated = false; - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_sat_funct(funct6, funct3); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - saturated |= fn(vxrm, vtype, vd_view[idx], vs2_view[idx], imm); - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) { - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - return saturated; -} -template -std::function get_red_funct(unsigned funct6, unsigned funct3) { - if(funct3 == OPIVV || funct3 == OPIVX || funct3 == OPIVI) - switch(funct6) { - case 0b110000: // VWREDSUMU - return [](dest_elem_t& running_total, src_elem_t vs2) { return running_total += static_cast(vs2); }; - case 0b110001: // VWREDSUM - return [](dest_elem_t& running_total, src_elem_t vs2) { - // cast the signed vs2 elem to unsigned to enable wrap around on overflow - return running_total += static_cast(sext(vs2)); - }; - default: - throw new std::runtime_error("Unknown funct6 in get_red_funct"); - } - else if(funct3 == OPMVV || funct3 == OPMVX) - switch(funct6) { - case 0b000000: // VREDSUM - return [](dest_elem_t& running_total, src_elem_t vs2) { return running_total += vs2; }; - case 0b000001: // VREDAND - return [](dest_elem_t& running_total, src_elem_t vs2) { return running_total &= vs2; }; - case 0b000010: // VREDOR - return [](dest_elem_t& running_total, src_elem_t vs2) { return running_total |= vs2; }; - case 0b000011: // VREDXOR - return [](dest_elem_t& running_total, src_elem_t vs2) { running_total ^= vs2; }; - case 0b000100: // VREDMINU - return [](dest_elem_t& running_total, src_elem_t vs2) { running_total = std::min(running_total, vs2); }; - case 0b000101: // VREDMIN - return [](dest_elem_t& running_total, src_elem_t vs2) { - running_total = std::min(static_cast>(running_total), - static_cast>(static_cast>(vs2))); - }; - case 0b000110: // VREDMAXU - return - [](dest_elem_t& running_total, src_elem_t vs2) { running_total = std::max(running_total, static_cast(vs2)); }; - case 0b000111: // VREDMAX - return [](dest_elem_t& running_total, src_elem_t vs2) { - running_total = std::max(static_cast>(running_total), - static_cast>(static_cast>(vs2))); - }; - default: - throw new std::runtime_error("Unknown funct6 in get_red_funct"); - } - else - throw new std::runtime_error("Unknown funct3 in get_red_funct"); -} -template -void vector_red_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_elem = get_vreg(V, vs1, vlmax)[0]; - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_red_funct(funct6, funct3); - dest_elem_t& running_total = vd_view[0] = vs1_elem; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) { - fn(running_total, vs2_view[idx]); - } - } - // the tail is all elements of the destination register beyond the first one - if(vtype.vta()) - for(size_t idx = 1; idx < VLEN / vtype.sew(); idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} - -// might be that these exist somewhere in softfloat -template constexpr bool isNaN(src_elem_t x); -template <> constexpr bool isNaN(uint16_t x) { return ((x & 0x7C00) == 0x7C00) && ((x & 0x03FF) != 0); } -template <> constexpr bool isNaN(uint32_t x) { return ((x & 0x7F800000) == 0x7F800000) && ((x & 0x007FFFFF) != 0); } -template <> constexpr bool isNaN(uint64_t x) { - return ((x & 0x7FF0000000000000) == 0x7FF0000000000000) && ((x & 0x000FFFFFFFFFFFFF) != 0); -} -template constexpr bool isNegZero(src_elem_t x); -template <> constexpr bool isNegZero(uint16_t x) { return x == 0x8000; } -template <> constexpr bool isNegZero(uint32_t x) { return x == 0x80000000; } -template <> constexpr bool isNegZero(uint64_t x) { return x == 0x8000000000000000; } -template constexpr bool isPosZero(src_elem_t x); -template <> constexpr bool isPosZero(uint16_t x) { return x == 0x0000; } -template <> constexpr bool isPosZero(uint32_t x) { return x == 0x00000000; } -template <> constexpr bool isPosZero(uint64_t x) { return x == 0x0000000000000000; } - -template dest_elem_t widen_float(src_elem_t val) { - throw new std::runtime_error("Trying to widen a weird 'float'"); -} -template <> inline uint64_t widen_float(uint32_t val) { return f32_to_f64(float32_t{val}).v; } - -template elem_size_t fp_add(uint8_t, elem_size_t, elem_size_t); -template <> inline uint16_t fp_add(uint8_t mode, uint16_t v2, uint16_t v1) { return fadd_h(v2, v1, mode); } -template <> inline uint32_t fp_add(uint8_t mode, uint32_t v2, uint32_t v1) { return fadd_s(v2, v1, mode); } -template <> inline uint64_t fp_add(uint8_t mode, uint64_t v2, uint64_t v1) { return fadd_d(v2, v1, mode); } -template elem_size_t fp_sub(uint8_t, elem_size_t, elem_size_t); -template <> inline uint16_t fp_sub(uint8_t mode, uint16_t v2, uint16_t v1) { return fsub_h(v2, v1, mode); } -template <> inline uint32_t fp_sub(uint8_t mode, uint32_t v2, uint32_t v1) { return fsub_s(v2, v1, mode); } -template <> inline uint64_t fp_sub(uint8_t mode, uint64_t v2, uint64_t v1) { return fsub_d(v2, v1, mode); } -template elem_size_t fp_mul(uint8_t, elem_size_t, elem_size_t); -template <> inline uint16_t fp_mul(uint8_t mode, uint16_t v2, uint16_t v1) { return fmul_h(v2, v1, mode); } -template <> inline uint32_t fp_mul(uint8_t mode, uint32_t v2, uint32_t v1) { return fmul_s(v2, v1, mode); } -template <> inline uint64_t fp_mul(uint8_t mode, uint64_t v2, uint64_t v1) { return fmul_d(v2, v1, mode); } -template elem_size_t fp_div(uint8_t, elem_size_t, elem_size_t); -template <> inline uint16_t fp_div(uint8_t mode, uint16_t v2, uint16_t v1) { return fdiv_h(v2, v1, mode); } -template <> inline uint32_t fp_div(uint8_t mode, uint32_t v2, uint32_t v1) { return fdiv_s(v2, v1, mode); } -template <> inline uint64_t fp_div(uint8_t mode, uint64_t v2, uint64_t v1) { return fdiv_d(v2, v1, mode); } -template elem_size_t fp_madd(uint8_t, elem_size_t, elem_size_t, elem_size_t); -template <> inline uint16_t fp_madd(uint8_t mode, uint16_t v2, uint16_t v1, uint16_t v3) { return fmadd_h(v1, v2, v3, 0, mode); } -template <> inline uint32_t fp_madd(uint8_t mode, uint32_t v2, uint32_t v1, uint32_t v3) { return fmadd_s(v1, v2, v3, 0, mode); } -template <> inline uint64_t fp_madd(uint8_t mode, uint64_t v2, uint64_t v1, uint64_t v3) { return fmadd_d(v1, v2, v3, 0, mode); } -template elem_size_t fp_nmadd(uint8_t, elem_size_t, elem_size_t, elem_size_t); -template <> inline uint16_t fp_nmadd(uint8_t mode, uint16_t v2, uint16_t v1, uint16_t v3) { return fmadd_h(v1, v2, v3, 2, mode); } -template <> inline uint32_t fp_nmadd(uint8_t mode, uint32_t v2, uint32_t v1, uint32_t v3) { return fmadd_s(v1, v2, v3, 2, mode); } -template <> inline uint64_t fp_nmadd(uint8_t mode, uint64_t v2, uint64_t v1, uint64_t v3) { return fmadd_d(v1, v2, v3, 2, mode); } -template elem_size_t fp_msub(uint8_t, elem_size_t, elem_size_t, elem_size_t); -template <> inline uint16_t fp_msub(uint8_t mode, uint16_t v2, uint16_t v1, uint16_t v3) { return fmadd_h(v1, v2, v3, 1, mode); } -template <> inline uint32_t fp_msub(uint8_t mode, uint32_t v2, uint32_t v1, uint32_t v3) { return fmadd_s(v1, v2, v3, 1, mode); } -template <> inline uint64_t fp_msub(uint8_t mode, uint64_t v2, uint64_t v1, uint64_t v3) { return fmadd_d(v1, v2, v3, 1, mode); } -template elem_size_t fp_nmsub(uint8_t, elem_size_t, elem_size_t, elem_size_t); -template <> inline uint16_t fp_nmsub(uint8_t mode, uint16_t v2, uint16_t v1, uint16_t v3) { return fmadd_h(v1, v2, v3, 3, mode); } -template <> inline uint32_t fp_nmsub(uint8_t mode, uint32_t v2, uint32_t v1, uint32_t v3) { return fmadd_s(v1, v2, v3, 3, mode); } -template <> inline uint64_t fp_nmsub(uint8_t mode, uint64_t v2, uint64_t v1, uint64_t v3) { return fmadd_d(v1, v2, v3, 3, mode); } -template elem_size_t fp_min(elem_size_t, elem_size_t); -template <> inline uint16_t fp_min(uint16_t v2, uint16_t v1) { - if(isNaN(v1) && isNaN(v2)) - return defaultNaNF16UI; - else if(isNaN(v1)) - return v2; - else if(isNaN(v2)) - return v1; - else if(isNegZero(v1) && isNegZero(v2)) - return v1; - else if(isNegZero(v2) && isNegZero(v1)) - return v2; - else if(fcmp_h(v1, v2, 2)) - return v1; - else - return v2; -} -template <> inline uint32_t fp_min(uint32_t v2, uint32_t v1) { - if(isNaN(v1) && isNaN(v2)) - return defaultNaNF32UI; - else if(isNaN(v1)) - return v2; - else if(isNaN(v2)) - return v1; - else if(isNegZero(v1) && isNegZero(v2)) - return v1; - else if(isNegZero(v2) && isNegZero(v1)) - return v2; - else if(fcmp_s(v1, v2, 2)) - return v1; - else - return v2; -} -template <> inline uint64_t fp_min(uint64_t v2, uint64_t v1) { - if(isNaN(v1) && isNaN(v2)) - return defaultNaNF64UI; - else if(isNaN(v1)) - return v2; - else if(isNaN(v2)) - return v1; - else if(isNegZero(v1) && isNegZero(v2)) - return v1; - else if(isNegZero(v2) && isNegZero(v1)) - return v2; - else if(fcmp_d(v1, v2, 2)) - return v1; - else - return v2; -} -template elem_size_t fp_max(elem_size_t, elem_size_t); -template <> inline uint16_t fp_max(uint16_t v2, uint16_t v1) { - if(isNaN(v1) && isNaN(v2)) - return defaultNaNF16UI; - else if(isNaN(v1)) - return v2; - else if(isNaN(v2)) - return v1; - else if(isNegZero(v1) && isNegZero(v2)) - return v2; - else if(isNegZero(v2) && isNegZero(v1)) - return v1; - else if(fcmp_h(v1, v2, 2)) - return v2; - else - return v1; -} -template <> inline uint32_t fp_max(uint32_t v2, uint32_t v1) { - if(isNaN(v1) && isNaN(v2)) - return defaultNaNF32UI; - else if(isNaN(v1)) - return v2; - else if(isNaN(v2)) - return v1; - else if(isNegZero(v1) && isNegZero(v2)) - return v2; - else if(isNegZero(v2) && isNegZero(v1)) - return v1; - else if(fcmp_s(v1, v2, 2)) - return v2; - else - return v1; -} -template <> inline uint64_t fp_max(uint64_t v2, uint64_t v1) { - if(isNaN(v1) && isNaN(v2)) - return defaultNaNF64UI; - else if(isNaN(v1)) - return v2; - else if(isNaN(v2)) - return v1; - else if(isNegZero(v1) && isNegZero(v2)) - return v2; - else if(isNegZero(v2) && isNegZero(v1)) - return v1; - else if(fcmp_d(v1, v2, 2)) - return v2; - else - return v1; -} - -template -std::function get_fp_funct(unsigned funct6, unsigned funct3) { - if(funct3 == OPFVV || funct3 == OPFVF) - switch(funct6) { - case 0b000000: // VFADD - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_add(rm, vs2, vs1); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b000010: // VFSUB - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_sub(rm, vs2, vs1); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b000100: // VFMIN - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return fp_min(vs2, vs1); - }; - case 0b000110: // VFMAX - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - return fp_max(vs2, vs1); - }; - case 0b100000: // VFDIV - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_div(rm, vs2, vs1); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b100001: // VFRDIV - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_div(rm, vs1, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b100100: // VFMUL - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_mul(rm, vs2, vs1); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b100111: // VFRSUB - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_sub(rm, vs1, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b101000: // VFMADD - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_madd(rm, vs1, vd, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b101001: // VFNMADD - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_nmadd(rm, vs1, vd, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b101010: // VFMSUB - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_msub(rm, vs1, vd, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b101011: // VFNMSUB - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_nmsub(rm, vs1, vd, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b101100: // VFMACC - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_madd(rm, vs1, vs2, vd); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b101101: // VFNMAC - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_nmadd(rm, vs1, vs2, vd); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b101110: // VFMSAC - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_msub(rm, vs1, vs2, vd); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b101111: // VFNMSAC - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_nmsub(rm, vs1, vs2, vd); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b110000: // VFWADD - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_add(rm, widen_float(vs2), widen_float(vs1)); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b110010: // VFWSUB - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_sub(rm, widen_float(vs2), widen_float(vs1)); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b110100: // VFWADD.W - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_add(rm, vs2, widen_float(vs1)); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b110110: // VFWSUB.W - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_sub(rm, vs2, widen_float(vs1)); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b111000: // VFWMUL - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_mul(rm, widen_float(vs2), widen_float(vs1)); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b111100: // VFWMACC - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_madd(rm, widen_float(vs1), widen_float(vs2), vd); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b111101: // VFWNMACC - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_nmadd(rm, widen_float(vs1), widen_float(vs2), vd); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b111110: // VFWMSAC - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_msub(rm, widen_float(vs1), widen_float(vs2), vd); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b111111: // VFWNMSAC - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t val = fp_nmsub(rm, widen_float(vs1), widen_float(vs2), vd); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b001000: // VFSGNJ - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t mask = std::numeric_limits::max() >> 1; - dest_elem_t sign_mask = std::numeric_limits>::min(); - return (vs2 & mask) | (vs1 & sign_mask); - }; - case 0b001001: // VFSGNJN - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t mask = std::numeric_limits::max() >> 1; - dest_elem_t sign_mask = std::numeric_limits>::min(); - return (vs2 & mask) | (~vs1 & sign_mask); - }; - case 0b001010: // VFSGNJX - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t vd, src2_elem_t vs2, src1_elem_t vs1) { - dest_elem_t mask = std::numeric_limits::max() >> 1; - dest_elem_t sign_mask = std::numeric_limits>::min(); - return vs2 ^ (vs1 & sign_mask); - }; - default: - throw new std::runtime_error("Unknown funct6 in get_fp_funct"); - } - else - throw new std::runtime_error("Unknown funct3 in get_fp_funct"); -} -template -void fp_vector_vector_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1, uint8_t rm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_view = get_vreg(V, vs1, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_fp_funct(funct6, funct3); - uint8_t accrued_flags = 0; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = fn(rm, accrued_flags, vd_view[idx], vs2_view[idx], vs1_view[idx]); - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - softfloat_exceptionFlags = accrued_flags; - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) { - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } -} -template -void fp_vector_imm_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, src1_elem_t imm, uint8_t rm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_fp_funct(funct6, funct3); - uint8_t accrued_flags = 0; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = fn(rm, accrued_flags, vd_view[idx], vs2_view[idx], imm); - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - softfloat_exceptionFlags = accrued_flags; - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -std::function get_fp_red_funct(unsigned funct6, unsigned funct3) { - if(funct3 == OPFVV || funct3 == OPFVF) - switch(funct6) { - case 0b000001: // VFREDUSUM - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t& running_total, src_elem_t vs2) { - running_total = fp_add(rm, running_total, vs2); - accrued_flags |= softfloat_exceptionFlags; - }; - case 0b000011: // VFREDOSUM - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t& running_total, src_elem_t vs2) { - running_total = fp_add(rm, running_total, vs2); - accrued_flags |= softfloat_exceptionFlags; - }; - case 0b000101: // VFREDMIN - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t& running_total, src_elem_t vs2) { - running_total = fp_min(running_total, vs2); - }; - case 0b000111: // VFREDMAX - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t& running_total, src_elem_t vs2) { - running_total = fp_max(running_total, vs2); - }; - case 0b110001: // VFWREDUSUM - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t& running_total, src_elem_t vs2) { - running_total = fp_add(rm, running_total, widen_float(vs2)); - accrued_flags |= softfloat_exceptionFlags; - }; - case 0b110011: // VFWREDOSUM - return [](uint8_t rm, uint8_t& accrued_flags, dest_elem_t& running_total, src_elem_t vs2) { - running_total = fp_add(rm, running_total, widen_float(vs2)); - accrued_flags |= softfloat_exceptionFlags; - }; - default: - throw new std::runtime_error("Unknown funct6 in get_fp_red_funct"); - } - else - throw new std::runtime_error("Unknown funct3 in get_fp_red_funct"); -} -template -void fp_vector_red_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, - unsigned vs2, unsigned vs1, uint8_t rm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_elem = get_vreg(V, vs1, vlmax)[0]; - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_fp_red_funct(funct6, funct3); - dest_elem_t& running_total = vd_view[0] = vs1_elem; - uint8_t accrued_flags = 0; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - fn(rm, accrued_flags, running_total, vs2_view[idx]); - } - softfloat_exceptionFlags = accrued_flags; - // the tail is all elements of the destination register beyond the first one - if(vtype.vta()) - for(size_t idx = 1; idx < VLEN / vtype.sew(); idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template elem_size_t fp_sqrt(uint8_t, elem_size_t); -template <> inline uint16_t fp_sqrt(uint8_t mode, uint16_t v2) { return fsqrt_h(v2, mode); } -template <> inline uint32_t fp_sqrt(uint8_t mode, uint32_t v2) { return fsqrt_s(v2, mode); } -template <> inline uint64_t fp_sqrt(uint8_t mode, uint64_t v2) { return fsqrt_d(v2, mode); } -template elem_size_t fp_rsqrt7(elem_size_t); -template <> inline uint16_t fp_rsqrt7(uint16_t v2) { return frsqrt7_h(v2); } -template <> inline uint32_t fp_rsqrt7(uint32_t v2) { return frsqrt7_s(v2); } -template <> inline uint64_t fp_rsqrt7(uint64_t v2) { return frsqrt7_d(v2); } -template elem_size_t fp_rec7(uint8_t, elem_size_t); -template <> inline uint16_t fp_rec7(uint8_t mode, uint16_t v2) { return frec7_h(v2, mode); } -template <> inline uint32_t fp_rec7(uint8_t mode, uint32_t v2) { return frec7_s(v2, mode); } -template <> inline uint64_t fp_rec7(uint8_t mode, uint64_t v2) { return frec7_d(v2, mode); } -template elem_size_t fp_fclass(elem_size_t); -template <> inline uint16_t fp_fclass(uint16_t v2) { return fclass_h(v2); } -template <> inline uint32_t fp_fclass(uint32_t v2) { return fclass_s(v2); } -template <> inline uint64_t fp_fclass(uint64_t v2) { return fclass_d(v2); } - -template dest_elem_size_t fp_f_to_ui(uint8_t, src_elem_size_t); -template dest_elem_size_t fp_f_to_i(uint8_t, src_elem_size_t); -template dest_elem_size_t fp_ui_to_f(uint8_t, src_elem_size_t); -template dest_elem_size_t fp_i_to_f(uint8_t, src_elem_size_t); -template dest_elem_t fp_f_to_f(uint8_t rm, src_elem_t val); - -template <> inline uint16_t fp_f_to_ui(uint8_t rm, uint16_t v2) { return f16toui32(v2, rm); } -template <> inline uint32_t fp_f_to_ui(uint8_t rm, uint32_t v2) { return f32toui32(v2, rm); } -template <> inline uint64_t fp_f_to_ui(uint8_t rm, uint64_t v2) { return f64toui64(v2, rm); } - -template <> inline uint16_t fp_f_to_i(uint8_t rm, uint16_t v2) { return f16toi32(v2, rm); } -template <> inline uint32_t fp_f_to_i(uint8_t rm, uint32_t v2) { return f32toi32(v2, rm); } -template <> inline uint64_t fp_f_to_i(uint8_t rm, uint64_t v2) { return f64toi64(v2, rm); } - -template <> inline uint16_t fp_ui_to_f(uint8_t rm, uint16_t v2) { return ui32tof16(v2, rm); } -template <> inline uint32_t fp_ui_to_f(uint8_t rm, uint32_t v2) { return ui32tof32(v2, rm); } -template <> inline uint64_t fp_ui_to_f(uint8_t rm, uint64_t v2) { return ui64tof64(v2, rm); } - -template <> inline uint16_t fp_i_to_f(uint8_t rm, uint16_t v2) { return i32tof16(v2, rm); } -template <> inline uint32_t fp_i_to_f(uint8_t rm, uint32_t v2) { return i32tof32(v2, rm); } -template <> inline uint64_t fp_i_to_f(uint8_t rm, uint64_t v2) { return i64tof64(v2, rm); } - -template std::function get_fp_unary_fn(unsigned encoding_space, unsigned unary_op) { - if(encoding_space == 0b010011) // VFUNARY1 - switch(unary_op) { - case 0b00000: // VFSQRT - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2) { - elem_t val = fp_sqrt(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b00100: // VFRSQRT7 - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2) { - elem_t val = fp_rsqrt7(vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b00101: // VFREC7 - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2) { - elem_t val = fp_rec7(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b10000: // VFCLASS - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2) { - elem_t val = fp_fclass(vs2); - return val; - }; - default: - throw new std::runtime_error("Unknown funct in get_fp_unary_fn"); - } - else if(encoding_space == 0b010010) // VFUNARY0 - switch(unary_op) { - case 0b00000: // VFCVT.XU.F.V - case 0b00110: // VFCVT.RTZ.XU.F.V - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2) { - elem_t val = fp_f_to_ui(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b00001: // VFCVT.X.F.V - case 0b00111: // VFCVT.RTZ.X.F.V - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2) { - elem_t val = fp_f_to_i(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b00010: // VFCVT.F.XU.V - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2) { - elem_t val = fp_ui_to_f(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b00011: // VFCVT.F.X.V - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2) { - elem_t val = fp_i_to_f(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - default: - throw new std::runtime_error("Unknown funct in get_fp_unary_fn"); - } - else - throw new std::runtime_error("Unknown funct in get_fp_unary_fn"); -} -template -void fp_vector_unary_op(uint8_t* V, unsigned encoding_space, unsigned unary_op, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, - unsigned vd, unsigned vs2, uint8_t rm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_fp_unary_fn(encoding_space, unary_op); - uint8_t accrued_flags = 0; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = fn(rm, accrued_flags, vs2_view[idx]); - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - softfloat_exceptionFlags = accrued_flags; - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} - -template <> inline uint16_t fp_f_to_ui(uint8_t rm, uint8_t v2) { - throw new std::runtime_error("Attempting illegal widening conversion"); -} -template <> inline uint32_t fp_f_to_ui(uint8_t rm, uint16_t v2) { return f16toui32(v2, rm); } -template <> inline uint64_t fp_f_to_ui(uint8_t rm, uint32_t v2) { return f32toui64(v2, rm); } - -template <> inline uint16_t fp_f_to_i(uint8_t rm, uint8_t v2) { - throw new std::runtime_error("Attempting illegal widening conversion"); -} -template <> inline uint32_t fp_f_to_i(uint8_t rm, uint16_t v2) { return f16toi32(v2, rm); } -template <> inline uint64_t fp_f_to_i(uint8_t rm, uint32_t v2) { return f32toi64(v2, rm); } - -template <> inline uint16_t fp_ui_to_f(uint8_t rm, uint8_t v2) { return ui32tof16(v2, rm); } -template <> inline uint32_t fp_ui_to_f(uint8_t rm, uint16_t v2) { return ui32tof32(v2, rm); } -template <> inline uint64_t fp_ui_to_f(uint8_t rm, uint32_t v2) { return ui32tof64(v2, rm); } - -template <> inline uint16_t fp_i_to_f(uint8_t rm, uint8_t v2) { return i32tof16(v2, rm); } -template <> inline uint32_t fp_i_to_f(uint8_t rm, uint16_t v2) { return i32tof32(v2, rm); } -template <> inline uint64_t fp_i_to_f(uint8_t rm, uint32_t v2) { return i32tof64(v2, rm); } - -template <> inline uint16_t fp_f_to_f(uint8_t rm, uint8_t val) { - throw new std::runtime_error("Attempting illegal widening conversion"); -} -template <> inline uint32_t fp_f_to_f(uint8_t rm, uint16_t val) { return f16tof32(val, rm); } -template <> inline uint64_t fp_f_to_f(uint8_t rm, uint32_t val) { return f32tof64(val, rm); } - -template -std::function get_fp_widening_fn(unsigned unary_op) { - switch(unary_op) { - case 0b01000: // VFWCVT.XU.F.V - case 0b01110: // VFWCVT.RTZ.XU.F.V - return [](uint8_t rm, uint8_t& accrued_flags, src_elem_t vs2) { - dest_elem_t val = fp_f_to_ui(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b01001: // VFWCVT.X.F.V - case 0b01111: // VFWCVT.RTZ.X.F.V - return [](uint8_t rm, uint8_t& accrued_flags, src_elem_t vs2) { - dest_elem_t val = fp_f_to_i(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b01010: // VFWCVT.F.XU.V - return [](uint8_t rm, uint8_t& accrued_flags, src_elem_t vs2) { - dest_elem_t val = fp_ui_to_f(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b01011: // VFWCVT.F.X.V - return [](uint8_t rm, uint8_t& accrued_flags, src_elem_t vs2) { - dest_elem_t val = fp_i_to_f(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b01100: // VFWCVT.F.F.V - return [](uint8_t rm, uint8_t& accrued_flags, src_elem_t vs2) { - dest_elem_t val = fp_f_to_f(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - default: - throw new std::runtime_error("Unknown funct in get_fp_unary_fn"); - } -} -template -void fp_vector_unary_w(uint8_t* V, unsigned unary_op, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint8_t rm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_fp_widening_fn(unary_op); - uint8_t accrued_flags = 0; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = fn(rm, accrued_flags, vs2_view[idx]); - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - softfloat_exceptionFlags = accrued_flags; - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} - -template <> inline uint8_t fp_f_to_ui(uint8_t rm, uint16_t v2) { return f16toui32(v2, rm); } -template <> inline uint16_t fp_f_to_ui(uint8_t rm, uint32_t v2) { return f32toui32(v2, rm); } -template <> inline uint32_t fp_f_to_ui(uint8_t rm, uint64_t v2) { return f64toui32(v2, rm); } - -template <> inline uint8_t fp_f_to_i(uint8_t rm, uint16_t v2) { return f16toi32(v2, rm); } -template <> inline uint16_t fp_f_to_i(uint8_t rm, uint32_t v2) { return f32toi32(v2, rm); } -template <> inline uint32_t fp_f_to_i(uint8_t rm, uint64_t v2) { return f64toi32(v2, rm); } - -template <> inline uint8_t fp_ui_to_f(uint8_t rm, uint16_t v2) { - throw new std::runtime_error("Attempting illegal narrowing conversion"); -} -template <> inline uint16_t fp_ui_to_f(uint8_t rm, uint32_t v2) { return ui32tof16(v2, rm); } -template <> inline uint32_t fp_ui_to_f(uint8_t rm, uint64_t v2) { return ui64tof32(v2, rm); } - -template <> inline uint8_t fp_i_to_f(uint8_t rm, uint16_t v2) { - throw new std::runtime_error("Attempting illegal narrowing conversion"); -} -template <> inline uint16_t fp_i_to_f(uint8_t rm, uint32_t v2) { return i32tof16(v2, rm); } -template <> inline uint32_t fp_i_to_f(uint8_t rm, uint64_t v2) { return i64tof32(v2, rm); } - -template <> inline uint8_t fp_f_to_f(uint8_t rm, uint16_t val) { - throw new std::runtime_error("Attempting illegal narrowing conversion"); -} -template <> inline uint16_t fp_f_to_f(uint8_t rm, uint32_t val) { return f32tof16(val, rm); } -template <> inline uint32_t fp_f_to_f(uint8_t rm, uint64_t val) { return f64tof32(val, rm); } -template -std::function get_fp_narrowing_fn(unsigned unary_op) { - switch(unary_op) { - case 0b10000: // VFNCVT.XU.F.W - case 0b10110: // VFNCVT.RTZ.XU.F.W - return [](uint8_t rm, uint8_t& accrued_flags, src_elem_t vs2) { - dest_elem_t val = fp_f_to_ui(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b10001: // VFNCVT.X.F.W - case 0b10111: // VFNCVT.RTZ.X.F.W - return [](uint8_t rm, uint8_t& accrued_flags, src_elem_t vs2) { - dest_elem_t val = fp_f_to_i(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b10010: // VFNCVT.F.XU.W - return [](uint8_t rm, uint8_t& accrued_flags, src_elem_t vs2) { - dest_elem_t val = fp_ui_to_f(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b10011: // VFNCVT.F.X.W - return [](uint8_t rm, uint8_t& accrued_flags, src_elem_t vs2) { - dest_elem_t val = fp_i_to_f(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b10100: // VFNCVT.F.F.W - case 0b10101: // VFNCVT.ROD.F.F.W - return [](uint8_t rm, uint8_t& accrued_flags, src_elem_t vs2) { - dest_elem_t val = fp_f_to_f(rm, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - default: - throw new std::runtime_error("Unknown funct in get_fp_narrowing_fn"); - } -} -template -void fp_vector_unary_n(uint8_t* V, unsigned unary_op, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - uint8_t rm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_fp_narrowing_fn(unary_op); - uint8_t accrued_flags = 0; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = fn(rm, accrued_flags, vs2_view[idx]); - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - softfloat_exceptionFlags = accrued_flags; - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template bool fp_eq(elem_size_t, elem_size_t); -template <> inline bool fp_eq(uint16_t v2, uint16_t v1) { return fcmp_h(v2, v1, 0); } -template <> inline bool fp_eq(uint32_t v2, uint32_t v1) { return fcmp_s(v2, v1, 0); } -template <> inline bool fp_eq(uint64_t v2, uint64_t v1) { return fcmp_d(v2, v1, 0); } -template bool fp_le(elem_size_t, elem_size_t); -template <> inline bool fp_le(uint16_t v2, uint16_t v1) { return fcmp_h(v2, v1, 1); } -template <> inline bool fp_le(uint32_t v2, uint32_t v1) { return fcmp_s(v2, v1, 1); } -template <> inline bool fp_le(uint64_t v2, uint64_t v1) { return fcmp_d(v2, v1, 1); } -template bool fp_lt(elem_size_t, elem_size_t); -template <> inline bool fp_lt(uint16_t v2, uint16_t v1) { return fcmp_h(v2, v1, 2); } -template <> inline bool fp_lt(uint32_t v2, uint32_t v1) { return fcmp_s(v2, v1, 2); } -template <> inline bool fp_lt(uint64_t v2, uint64_t v1) { return fcmp_d(v2, v1, 2); } -template std::function get_fp_mask_funct(unsigned funct6) { - switch(funct6) { - case 0b011000: // VMFEQ - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2, elem_t vs1) { - elem_t val = fp_eq(vs2, vs1); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b011001: // VMFLE - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2, elem_t vs1) { - elem_t val = fp_le(vs2, vs1); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b011011: // VMFLT - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2, elem_t vs1) { - elem_t val = fp_lt(vs2, vs1); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b011100: // VMFNE - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2, elem_t vs1) { - elem_t val = !fp_eq(vs2, vs1); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b011101: // VMFGT - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2, elem_t vs1) { - elem_t val = fp_lt(vs1, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - case 0b011111: // VMFGE - return [](uint8_t rm, uint8_t& accrued_flags, elem_t vs2, elem_t vs1) { - elem_t val = fp_le(vs1, vs2); - accrued_flags |= softfloat_exceptionFlags; - return val; - }; - default: - throw new std::runtime_error("Unknown funct6 in get_fp_mask_funct"); - } -} -template -void mask_fp_vector_vector_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - unsigned vs1, uint8_t rm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_view = get_vreg(V, vs1, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - vmask_view vd_mask_view = read_vmask(V, VLEN, vd); - auto fn = get_fp_mask_funct(funct6); - uint8_t accrued_flags = 0; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_mask_view[idx] = fn(rm, accrued_flags, vs2_view[idx], vs1_view[idx]); - else if(vtype.vma()) - vd_mask_view[idx] = agnostic_behavior(vd_mask_view[idx]); - } - softfloat_exceptionFlags = accrued_flags; - if(vtype.vta()) - for(size_t idx = vl; idx < VLEN; idx++) - vd_mask_view[idx] = agnostic_behavior(vd_mask_view[idx]); -} -template -void mask_fp_vector_imm_op(uint8_t* V, unsigned funct6, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, - elem_t imm, uint8_t rm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - vmask_view vd_mask_view = read_vmask(V, VLEN, vd); - auto fn = get_fp_mask_funct(funct6); - uint8_t accrued_flags = 0; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_mask_view[idx] = fn(rm, accrued_flags, vs2_view[idx], imm); - else if(vtype.vma()) - vd_mask_view[idx] = agnostic_behavior(vd_mask_view[idx]); - } - softfloat_exceptionFlags = accrued_flags; - if(vtype.vta()) - for(size_t idx = vl; idx < VLEN; idx++) - vd_mask_view[idx] = agnostic_behavior(vd_mask_view[idx]); -} -template -void mask_mask_op(uint8_t* V, unsigned funct6, unsigned funct3, uint64_t vl, uint64_t vstart, unsigned vd, unsigned vs2, unsigned vs1) { - uint64_t vlmax = VLEN; - auto vs1_view = read_vmask(V, vlmax, vs1); - auto vs2_view = read_vmask(V, vlmax, vs2); - auto vd_view = read_vmask(V, vlmax, vd); - auto fn = get_mask_funct(funct6, funct3); // could be bool, but would break the make_signed_t in get_mask_funct - for(size_t idx = vstart; idx < vl; idx++) - vd_view[idx] = fn(vs2_view[idx], vs1_view[idx]); - - // the tail is all elements of the destination register beyond the first one - for(size_t idx = 1; idx < VLEN; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template uint64_t vcpop(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { - uint64_t vlmax = VLEN; - auto vs2_view = read_vmask(V, vlmax, vs2); - vmask_view mask_reg = read_vmask(V, vlmax); - unsigned running_total = 0; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active && vs2_view[idx]) - running_total += 1; - } - return running_total; -} -template uint64_t vfirst(uint8_t* V, uint64_t vl, uint64_t vstart, bool vm, unsigned vs2) { - uint64_t vlmax = VLEN; - auto vs2_view = read_vmask(V, vlmax, vs2); - vmask_view mask_reg = read_vmask(V, vlmax); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active && vs2_view[idx]) - return idx; - } - return -1; -} -inline std::function get_mask_set_funct(unsigned enc) { - switch(enc) { - case 0b00001: // VMSBF - return [](bool& marker, bool vs2) { - if(marker) - return 0; - if(vs2) { - marker = true; - return 0; - } else - return 1; - }; - case 0b00010: // VMSOF - return [](bool& marker, bool vs2) { - if(marker) - return 0; - if(vs2) { - marker = true; - return 1; - } else - return 0; - }; - case 0b00011: // VMSIF - return [](bool& marker, bool vs2) { - if(marker) - return 0; - if(vs2) { - marker = true; - return 1; - } else - return 1; - }; - default: - throw new std::runtime_error("Unknown enc in get_mask_set_funct"); - } -} -template void mask_set_op(uint8_t* V, unsigned enc, uint64_t vl, uint64_t vstart, bool vm, unsigned vd, unsigned vs2) { - uint64_t vlmax = VLEN; - auto vs2_view = read_vmask(V, vlmax, vs2); - auto vd_view = read_vmask(V, vlmax, vd); - vmask_view mask_reg = read_vmask(V, vlmax); - auto fn = get_mask_set_funct(enc); - bool marker = false; - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = fn(marker, vs2_view[idx]); - } - // the tail is all elements of the destination register beyond the first one - for(size_t idx = 1; idx < VLEN; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -void viota(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - auto vs2_view = read_vmask(V, vlmax, vs2); - auto vd_view = get_vreg(V, vd, vlmax); - vmask_view mask_reg = read_vmask(V, vlmax); - unsigned current = 0; - for(size_t idx = vstart; idx < std::min(vl, vlmax); idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) { - vd_view[idx] = current; - if(vs2_view[idx]) - current += 1; - } - } -} -template void vid(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - auto vd_view = get_vreg(V, vd, vlmax); - vmask_view mask_reg = read_vmask(V, vlmax); - for(size_t idx = vstart; idx < std::min(vl, vlmax); idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = idx; - } -} -template uint64_t scalar_move(uint8_t* V, vtype_t vtype, unsigned vd, uint64_t val, bool to_vector) { - unsigned vlmax = VLEN * vtype.lmul() / vtype.sew(); - auto vd_view = get_vreg(V, vd, vlmax); - if(to_vector) { - vd_view[0] = val; - if(vtype.vta()) - for(size_t idx = 1; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - return static_cast(static_cast>(vd_view[0])); -} -template -void vector_slideup(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm) { - uint64_t vlmax = VLEN * vtype.lmul() / (sizeof(src_elem_t) * 8); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - for(size_t idx = std::max(vstart, imm); idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = idx - imm < vlmax ? vs2_view[idx - imm] : 0; - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -void vector_slidedown(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm) { - uint64_t vlmax = VLEN * vtype.lmul() / (sizeof(src_elem_t) * 8); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = std::numeric_limits::max() - idx > imm && idx + imm < vlmax ? vs2_view[idx + imm] : 0; - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -void vector_slide1up(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm) { - vector_slideup(V, vl, vstart, vtype, vm, vd, vs2, 1); - vmask_view mask_reg = read_vmask(V, 1); - auto vd_view = get_vreg(V, vd, 1); - if(vm || mask_reg[0]) - vd_view[0] = imm; - else if(vtype.vma()) - vd_view[0] = agnostic_behavior(vd_view[0]); -} -template -void vector_slide1down(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm) { - vector_slidedown(V, vl, vstart, vtype, vm, vd, vs2, 1); - - vmask_view mask_reg = read_vmask(V, vl); - auto vd_view = get_vreg(V, vd, vl); - if(vm || mask_reg[vl - 1]) - vd_view[vl - 1] = imm; - else if(vtype.vma()) - vd_view[0] = agnostic_behavior(vd_view[0]); -} -template -void vector_vector_gather(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, unsigned vs1) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs1_view = get_vreg(V, vs1, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = (vs1_view[idx] >= vlmax) ? 0 : vs2_view[vs1_view[idx]]; - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -void vector_imm_gather(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, bool vm, unsigned vd, unsigned vs2, uint64_t imm) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - for(size_t idx = vstart; idx < vl; idx++) { - bool mask_active = vm ? 1 : mask_reg[idx]; - if(mask_active) - vd_view[idx] = (imm >= vlmax) ? 0 : vs2_view[imm]; - else if(vtype.vma()) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -void vector_compress(uint8_t* V, uint64_t vl, uint64_t vstart, vtype_t vtype, unsigned vd, unsigned vs2, unsigned vs1) { - uint64_t vlmax = VLEN * vtype.lmul() / vtype.sew(); - vmask_view mask_reg = read_vmask(V, vlmax, vs1); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - unsigned current_pos = 0; - for(size_t idx = vstart; idx < vl; idx++) - if(mask_reg[idx]) { - vd_view[current_pos] = vs2_view[idx]; - current_pos += 1; - } - - if(vtype.vta()) - for(size_t idx = vl; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template void vector_whole_move(uint8_t* V, unsigned vd, unsigned vs2, unsigned count) { - auto vd_view = get_vreg(V, vd, 1); - auto vs2_view = get_vreg(V, vs2, 1); - memcpy(vd_view.start, vs2_view.start, VLEN / 8 * count); -} - -template -void vector_vector_crypto(uint8_t* V, unsigned funct6, uint64_t eg_len, uint64_t eg_start, vtype_t vtype, unsigned vd, unsigned vs2, - unsigned vs1) { - uint64_t vlmax = VLEN * vtype.lmul() / (vtype.sew() * EGS); - auto vs1_view = get_vreg(V, vs1, vlmax); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_crypto_funct(funct6, vs1); - for(size_t idx = eg_start; idx < eg_len; idx++) { - vd_view[idx] = fn(vd_view[idx], vs2_view[idx], vs1_view[idx]); - } - if(vtype.vta()) - for(size_t idx = eg_len; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template -void vector_scalar_crypto(uint8_t* V, unsigned funct6, uint64_t eg_len, uint64_t eg_start, vtype_t vtype, unsigned vd, unsigned vs2, - unsigned vs1) { - uint64_t vlmax = VLEN * vtype.lmul() / (vtype.sew() * EGS); - auto vs2_val = get_vreg(V, vs2, vlmax)[0]; - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_crypto_funct(funct6, vs1); - for(size_t idx = eg_start; idx < eg_len; idx++) { - vd_view[idx] = fn(vd_view[idx], vs2_val, -1); - } - if(vtype.vta()) - for(size_t idx = eg_len; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} - -template -void vector_imm_crypto(uint8_t* V, unsigned funct6, uint64_t eg_len, uint64_t eg_start, vtype_t vtype, unsigned vd, unsigned vs2, - uint8_t imm) { - uint64_t vlmax = VLEN * vtype.lmul() / (vtype.sew() * EGS); - auto vs2_view = get_vreg(V, vs2, vlmax); - auto vd_view = get_vreg(V, vd, vlmax); - auto fn = get_crypto_funct(funct6, -1); - for(size_t idx = eg_start; idx < eg_len; idx++) { - vd_view[idx] = fn(vd_view[idx], vs2_view[idx], imm); - } - if(vtype.vta()) - for(size_t idx = eg_len; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); -} -template T rotr(T x, unsigned n) { - assert(n < sizeof(T) * 8); - return (x >> n) | (x << (sizeof(T) * 8 - n)); -} -template T shr(T x, unsigned n) { - assert(n < sizeof(T) * 8); - return (x >> n); -} -template T sum0(T); -template <> inline uint32_t sum0(uint32_t x) { return rotr(x, 2) ^ rotr(x, 13) ^ rotr(x, 22); } -template <> inline uint64_t sum0(uint64_t x) { return rotr(x, 28) ^ rotr(x, 34) ^ rotr(x, 39); } -template T sum1(T); -template <> inline uint32_t sum1(uint32_t x) { return rotr(x, 6) ^ rotr(x, 11) ^ rotr(x, 25); } -template <> inline uint64_t sum1(uint64_t x) { return rotr(x, 14) ^ rotr(x, 18) ^ rotr(x, 41); } -template T ch(T x, T y, T z) { return ((x & y) ^ ((~x) & z)); } -template T maj(T x, T y, T z) { return ((x & y) ^ (x & z) ^ (y & z)); } -template T sig0(T); -template <> inline uint32_t sig0(uint32_t x) { return rotr(x, 7) ^ rotr(x, 18) ^ shr(x, 3); } -template <> inline uint64_t sig0(uint64_t x) { return rotr(x, 1) ^ rotr(x, 8) ^ shr(x, 7); } -template T sig1(T); -template <> inline uint32_t sig1(uint32_t x) { return rotr(x, 17) ^ rotr(x, 19) ^ shr(x, 10); } -template <> inline uint64_t sig1(uint64_t x) { return rotr(x, 19) ^ rotr(x, 61) ^ shr(x, 6); } -template std::function&, vreg_view&, vreg_view&)> get_crypto_funct(unsigned int funct6) { - switch(funct6) { - case 0b101110: // VSHA2CH - return [](vreg_view& vd_view, vreg_view& vs2_view, vreg_view& vs1_view) { - T a = vs2_view[3]; - T b = vs2_view[2]; - T c = vd_view[3]; - T d = vd_view[2]; - T e = vs2_view[1]; - T f = vs2_view[0]; - T g = vd_view[1]; - T h = vd_view[0]; - T W0 = vs1_view[2]; - T W1 = vs1_view[3]; - T T1 = h + sum1(e) + ch(e, f, g) + W0; - T T2 = sum0(a) + maj(a, b, c); - h = g; - g = f; - f = e; - e = d + T1; - d = c; - c = b; - b = a; - a = T1 + T2; - T1 = h + sum1(e) + ch(e, f, g) + W1; - T2 = sum0(a) + maj(a, b, c); - h = g; - g = f; - f = e; - e = d + T1; - d = c; - c = b; - b = a; - a = T1 + T2; - vd_view[0] = f; - vd_view[1] = e; - vd_view[2] = b; - vd_view[3] = a; - }; - case 0b101111: // VSHA2CL - return [](vreg_view& vd_view, vreg_view& vs2_view, vreg_view& vs1_view) { - T a = vs2_view[3]; - T b = vs2_view[2]; - T c = vd_view[3]; - T d = vd_view[2]; - T e = vs2_view[1]; - T f = vs2_view[0]; - T g = vd_view[1]; - T h = vd_view[0]; - T W0 = vs1_view[0]; - T W1 = vs1_view[1]; - T T1 = h + sum1(e) + ch(e, f, g) + W0; - T T2 = sum0(a) + maj(a, b, c); - h = g; - g = f; - f = e; - e = d + T1; - d = c; - c = b; - b = a; - a = T1 + T2; - T1 = h + sum1(e) + ch(e, f, g) + W1; - T2 = sum0(a) + maj(a, b, c); - h = g; - g = f; - f = e; - e = d + T1; - d = c; - c = b; - b = a; - a = T1 + T2; - vd_view[0] = f; - vd_view[1] = e; - vd_view[2] = b; - vd_view[3] = a; - }; - case 0b101101: // VSHA2MS - return [](vreg_view& vd_view, vreg_view& vs2_view, vreg_view& vs1_view) { - T W0 = vd_view[0]; - T W1 = vd_view[1]; - T W2 = vd_view[2]; - T W3 = vd_view[3]; - - T W4 = vs2_view[0]; - T W9 = vs2_view[1]; - T W10 = vs2_view[2]; - T W11 = vs2_view[3]; - - T W12 = vs1_view[0]; - T W13 = vs1_view[1]; - T W14 = vs1_view[2]; - T W15 = vs1_view[3]; - - T W16 = sig1(W14) + W9 + sig0(W1) + W0; - T W17 = sig1(W15) + W10 + sig0(W2) + W1; - T W18 = sig1(W16) + W11 + sig0(W3) + W2; - T W19 = sig1(W17) + W12 + sig0(W4) + W3; - - vd_view[0] = W16; - vd_view[1] = W17; - vd_view[2] = W18; - vd_view[3] = W19; - }; - default: - throw new std::runtime_error("Unsupported operation in get_crypto_funct"); - } -} -template -void vector_crypto(uint8_t* V, unsigned funct6, uint64_t eg_len, uint64_t eg_start, vtype_t vtype, unsigned vd, unsigned vs2, - unsigned vs1) { - auto fn = get_crypto_funct(funct6); - auto vd_view = get_vreg(V, vd, EGS); - auto vs2_view = get_vreg(V, vs2, EGS); - auto vs1_view = get_vreg(V, vs1, EGS); - for(size_t idx = eg_start; idx < eg_len; idx++) { - fn(vd_view, vs2_view, vs1_view); - // We cannot use views in case EGW < VLEN, as views can only address the start of a register - vd_view.start += EGS * sizeof(elem_type_t); - vs2_view.start += EGS * sizeof(elem_type_t); - vs1_view.start += EGS * sizeof(elem_type_t); - } - if(vtype.vta()) { - uint64_t vlmax = VLEN * vtype.lmul() / (vtype.sew()); - auto vd_view = get_vreg(V, vd, vlmax); - for(size_t idx = eg_len * EGS; idx < vlmax; idx++) - vd_view[idx] = agnostic_behavior(vd_view[idx]); - } -} - -template dest_elem_t brev(src_elem_t vs2) { - constexpr dest_elem_t bits = sizeof(src_elem_t) * 8; - dest_elem_t result = 0; - for(size_t i = 0; i < bits; ++i) { - result <<= 1; - result |= (vs2 & 1); - vs2 >>= 1; - } - return result; -}; -template dest_elem_t brev8(src_elem_t vs2) { - constexpr unsigned byte_count = sizeof(src_elem_t); - dest_elem_t result = 0; - for(size_t i = 0; i < byte_count; ++i) { - dest_elem_t byte = (vs2 >> (i * 8)) & 0xFF; - byte = ((byte & 0xF0) >> 4) | ((byte & 0x0F) << 4); - byte = ((byte & 0xCC) >> 2) | ((byte & 0x33) << 2); - byte = ((byte & 0xAA) >> 1) | ((byte & 0x55) << 1); - result |= byte << (i * 8); - } - return result; -}; -} // namespace softvector \ No newline at end of file From 0e917de78327cb701d55ac5908d7d747ccbdc98a Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 25 Sep 2025 10:05:07 +0200 Subject: [PATCH 021/230] moves softfloat into softvector --- CMakeLists.txt | 49 +- softfloat/CMakeLists.txt | 354 ---- softfloat/COPYING.txt | 37 - softfloat/README.html | 49 - softfloat/README.md | 24 - softfloat/README.txt | 21 - softfloat/build/Linux-386-GCC/Makefile | 325 ---- softfloat/build/Linux-386-GCC/platform.h | 53 - softfloat/build/Linux-386-SSE2-GCC/Makefile | 325 ---- softfloat/build/Linux-386-SSE2-GCC/platform.h | 53 - softfloat/build/Linux-ARM-VFPv2-GCC/Makefile | 323 ---- .../build/Linux-ARM-VFPv2-GCC/platform.h | 53 - softfloat/build/Linux-RISCV64-GCC/Makefile | 399 ----- softfloat/build/Linux-RISCV64-GCC/platform.h | 54 - softfloat/build/Linux-x86_64-GCC/Makefile | 397 ----- softfloat/build/Linux-x86_64-GCC/platform.h | 56 - softfloat/build/Win32-MinGW/Makefile | 325 ---- softfloat/build/Win32-MinGW/platform.h | 53 - softfloat/build/Win32-SSE2-MinGW/Makefile | 325 ---- softfloat/build/Win32-SSE2-MinGW/platform.h | 53 - softfloat/build/Win64-MinGW-w64/Makefile | 390 ----- softfloat/build/Win64-MinGW-w64/platform.h | 54 - softfloat/build/template-FAST_INT64/Makefile | 396 ----- .../build/template-FAST_INT64/platform.h | 50 - .../build/template-not-FAST_INT64/Makefile | 325 ---- .../build/template-not-FAST_INT64/platform.h | 50 - softfloat/doc/SoftFloat-history.html | 258 --- softfloat/doc/SoftFloat-source.html | 686 -------- softfloat/doc/SoftFloat.html | 1527 ----------------- .../source/8086-SSE/extF80M_isSignalingNaN.c | 57 - .../source/8086-SSE/f128M_isSignalingNaN.c | 60 - .../source/8086-SSE/s_bf16UIToCommonNaN.c | 59 - .../source/8086-SSE/s_commonNaNToBF16UI.c | 51 - .../source/8086-SSE/s_commonNaNToExtF80M.c | 56 - .../source/8086-SSE/s_commonNaNToExtF80UI.c | 56 - .../source/8086-SSE/s_commonNaNToF128M.c | 56 - .../source/8086-SSE/s_commonNaNToF128UI.c | 55 - .../source/8086-SSE/s_commonNaNToF16UI.c | 51 - .../source/8086-SSE/s_commonNaNToF32UI.c | 51 - .../source/8086-SSE/s_commonNaNToF64UI.c | 53 - .../source/8086-SSE/s_extF80MToCommonNaN.c | 62 - .../source/8086-SSE/s_extF80UIToCommonNaN.c | 62 - .../source/8086-SSE/s_f128MToCommonNaN.c | 62 - .../source/8086-SSE/s_f128UIToCommonNaN.c | 65 - .../source/8086-SSE/s_f16UIToCommonNaN.c | 59 - .../source/8086-SSE/s_f32UIToCommonNaN.c | 59 - .../source/8086-SSE/s_f64UIToCommonNaN.c | 59 - .../source/8086-SSE/s_propagateNaNExtF80M.c | 107 -- .../source/8086-SSE/s_propagateNaNExtF80UI.c | 106 -- .../source/8086-SSE/s_propagateNaNF128M.c | 76 - .../source/8086-SSE/s_propagateNaNF128UI.c | 81 - .../source/8086-SSE/s_propagateNaNF16UI.c | 63 - .../source/8086-SSE/s_propagateNaNF32UI.c | 63 - .../source/8086-SSE/s_propagateNaNF64UI.c | 63 - .../source/8086-SSE/softfloat_raiseFlags.c | 52 - softfloat/source/8086-SSE/specialize.h | 367 ---- .../source/8086/extF80M_isSignalingNaN.c | 57 - softfloat/source/8086/f128M_isSignalingNaN.c | 60 - softfloat/source/8086/s_commonNaNToExtF80M.c | 56 - softfloat/source/8086/s_commonNaNToExtF80UI.c | 56 - softfloat/source/8086/s_commonNaNToF128M.c | 56 - softfloat/source/8086/s_commonNaNToF128UI.c | 55 - softfloat/source/8086/s_commonNaNToF16UI.c | 51 - softfloat/source/8086/s_commonNaNToF32UI.c | 51 - softfloat/source/8086/s_commonNaNToF64UI.c | 53 - softfloat/source/8086/s_extF80MToCommonNaN.c | 62 - softfloat/source/8086/s_extF80UIToCommonNaN.c | 62 - softfloat/source/8086/s_f128MToCommonNaN.c | 62 - softfloat/source/8086/s_f128UIToCommonNaN.c | 65 - softfloat/source/8086/s_f16UIToCommonNaN.c | 59 - softfloat/source/8086/s_f32UIToCommonNaN.c | 59 - softfloat/source/8086/s_f64UIToCommonNaN.c | 59 - softfloat/source/8086/s_propagateNaNExtF80M.c | 107 -- .../source/8086/s_propagateNaNExtF80UI.c | 106 -- softfloat/source/8086/s_propagateNaNF128M.c | 108 -- softfloat/source/8086/s_propagateNaNF128UI.c | 105 -- softfloat/source/8086/s_propagateNaNF16UI.c | 84 - softfloat/source/8086/s_propagateNaNF32UI.c | 84 - softfloat/source/8086/s_propagateNaNF64UI.c | 84 - softfloat/source/8086/softfloat_raiseFlags.c | 52 - softfloat/source/8086/specialize.h | 346 ---- .../extF80M_isSignalingNaN.c | 57 - .../f128M_isSignalingNaN.c | 60 - .../s_commonNaNToExtF80M.c | 57 - .../s_commonNaNToExtF80UI.c | 57 - .../ARM-VFPv2-defaultNaN/s_commonNaNToF128M.c | 60 - .../s_commonNaNToF128UI.c | 56 - .../ARM-VFPv2-defaultNaN/s_commonNaNToF16UI.c | 5 - .../ARM-VFPv2-defaultNaN/s_commonNaNToF32UI.c | 5 - .../ARM-VFPv2-defaultNaN/s_commonNaNToF64UI.c | 5 - .../s_extF80MToCommonNaN.c | 5 - .../s_extF80UIToCommonNaN.c | 5 - .../ARM-VFPv2-defaultNaN/s_f128MToCommonNaN.c | 5 - .../s_f128UIToCommonNaN.c | 5 - .../ARM-VFPv2-defaultNaN/s_f16UIToCommonNaN.c | 5 - .../ARM-VFPv2-defaultNaN/s_f32UIToCommonNaN.c | 5 - .../ARM-VFPv2-defaultNaN/s_f64UIToCommonNaN.c | 5 - .../s_propagateNaNExtF80M.c | 74 - .../s_propagateNaNExtF80UI.c | 73 - .../s_propagateNaNF128M.c | 68 - .../s_propagateNaNF128UI.c | 73 - .../s_propagateNaNF16UI.c | 58 - .../s_propagateNaNF32UI.c | 58 - .../s_propagateNaNF64UI.c | 58 - .../softfloat_raiseFlags.c | 52 - .../source/ARM-VFPv2-defaultNaN/specialize.h | 393 ----- .../source/ARM-VFPv2/extF80M_isSignalingNaN.c | 57 - .../source/ARM-VFPv2/f128M_isSignalingNaN.c | 60 - .../source/ARM-VFPv2/s_commonNaNToExtF80M.c | 56 - .../source/ARM-VFPv2/s_commonNaNToExtF80UI.c | 56 - .../source/ARM-VFPv2/s_commonNaNToF128M.c | 56 - .../source/ARM-VFPv2/s_commonNaNToF128UI.c | 55 - .../source/ARM-VFPv2/s_commonNaNToF16UI.c | 51 - .../source/ARM-VFPv2/s_commonNaNToF32UI.c | 51 - .../source/ARM-VFPv2/s_commonNaNToF64UI.c | 53 - .../source/ARM-VFPv2/s_extF80MToCommonNaN.c | 62 - .../source/ARM-VFPv2/s_extF80UIToCommonNaN.c | 62 - .../source/ARM-VFPv2/s_f128MToCommonNaN.c | 62 - .../source/ARM-VFPv2/s_f128UIToCommonNaN.c | 65 - .../source/ARM-VFPv2/s_f16UIToCommonNaN.c | 59 - .../source/ARM-VFPv2/s_f32UIToCommonNaN.c | 59 - .../source/ARM-VFPv2/s_f64UIToCommonNaN.c | 59 - .../source/ARM-VFPv2/s_propagateNaNExtF80M.c | 86 - .../source/ARM-VFPv2/s_propagateNaNExtF80UI.c | 83 - .../source/ARM-VFPv2/s_propagateNaNF128M.c | 77 - .../source/ARM-VFPv2/s_propagateNaNF128UI.c | 83 - .../source/ARM-VFPv2/s_propagateNaNF16UI.c | 63 - .../source/ARM-VFPv2/s_propagateNaNF32UI.c | 63 - .../source/ARM-VFPv2/s_propagateNaNF64UI.c | 63 - .../source/ARM-VFPv2/softfloat_raiseFlags.c | 52 - softfloat/source/ARM-VFPv2/specialize.h | 346 ---- .../source/RISCV/extF80M_isSignalingNaN.c | 57 - softfloat/source/RISCV/f128M_isSignalingNaN.c | 60 - softfloat/source/RISCV/s_bf16UIToCommonNaN.c | 5 - softfloat/source/RISCV/s_commonNaNToBF16UI.c | 5 - softfloat/source/RISCV/s_commonNaNToExtF80M.c | 57 - .../source/RISCV/s_commonNaNToExtF80UI.c | 57 - softfloat/source/RISCV/s_commonNaNToF128M.c | 60 - softfloat/source/RISCV/s_commonNaNToF128UI.c | 56 - softfloat/source/RISCV/s_commonNaNToF16UI.c | 5 - softfloat/source/RISCV/s_commonNaNToF32UI.c | 5 - softfloat/source/RISCV/s_commonNaNToF64UI.c | 5 - softfloat/source/RISCV/s_extF80MToCommonNaN.c | 5 - .../source/RISCV/s_extF80UIToCommonNaN.c | 5 - softfloat/source/RISCV/s_f128MToCommonNaN.c | 5 - softfloat/source/RISCV/s_f128UIToCommonNaN.c | 5 - softfloat/source/RISCV/s_f16UIToCommonNaN.c | 5 - softfloat/source/RISCV/s_f32UIToCommonNaN.c | 5 - softfloat/source/RISCV/s_f64UIToCommonNaN.c | 5 - .../source/RISCV/s_propagateNaNExtF80M.c | 74 - .../source/RISCV/s_propagateNaNExtF80UI.c | 73 - softfloat/source/RISCV/s_propagateNaNF128M.c | 68 - softfloat/source/RISCV/s_propagateNaNF128UI.c | 73 - softfloat/source/RISCV/s_propagateNaNF16UI.c | 58 - softfloat/source/RISCV/s_propagateNaNF32UI.c | 58 - softfloat/source/RISCV/s_propagateNaNF64UI.c | 58 - softfloat/source/RISCV/softfloat_raiseFlags.c | 52 - softfloat/source/RISCV/specialize.h | 421 ----- softfloat/source/bf16_isSignalingNaN.c | 51 - softfloat/source/bf16_to_f32.c | 90 - softfloat/source/extF80M_add.c | 100 -- softfloat/source/extF80M_div.c | 194 --- softfloat/source/extF80M_eq.c | 98 -- softfloat/source/extF80M_eq_signaling.c | 92 - softfloat/source/extF80M_le.c | 106 -- softfloat/source/extF80M_le_quiet.c | 112 -- softfloat/source/extF80M_lt.c | 106 -- softfloat/source/extF80M_lt_quiet.c | 112 -- softfloat/source/extF80M_mul.c | 139 -- softfloat/source/extF80M_rem.c | 204 --- softfloat/source/extF80M_roundToInt.c | 176 -- softfloat/source/extF80M_sqrt.c | 180 -- softfloat/source/extF80M_sub.c | 100 -- softfloat/source/extF80M_to_f128M.c | 125 -- softfloat/source/extF80M_to_f16.c | 112 -- softfloat/source/extF80M_to_f32.c | 112 -- softfloat/source/extF80M_to_f64.c | 112 -- softfloat/source/extF80M_to_i32.c | 100 -- softfloat/source/extF80M_to_i32_r_minMag.c | 120 -- softfloat/source/extF80M_to_i64.c | 97 -- softfloat/source/extF80M_to_i64_r_minMag.c | 115 -- softfloat/source/extF80M_to_ui32.c | 101 -- softfloat/source/extF80M_to_ui32_r_minMag.c | 111 -- softfloat/source/extF80M_to_ui64.c | 97 -- softfloat/source/extF80M_to_ui64_r_minMag.c | 108 -- softfloat/source/extF80_add.c | 80 - softfloat/source/extF80_div.c | 203 --- softfloat/source/extF80_eq.c | 73 - softfloat/source/extF80_eq_signaling.c | 67 - softfloat/source/extF80_isSignalingNaN.c | 51 - softfloat/source/extF80_le.c | 73 - softfloat/source/extF80_le_quiet.c | 78 - softfloat/source/extF80_lt.c | 73 - softfloat/source/extF80_lt_quiet.c | 78 - softfloat/source/extF80_mul.c | 158 -- softfloat/source/extF80_rem.c | 225 --- softfloat/source/extF80_roundToInt.c | 154 -- softfloat/source/extF80_sqrt.c | 176 -- softfloat/source/extF80_sub.c | 80 - softfloat/source/extF80_to_f128.c | 75 - softfloat/source/extF80_to_f16.c | 96 -- softfloat/source/extF80_to_f32.c | 96 -- softfloat/source/extF80_to_f64.c | 96 -- softfloat/source/extF80_to_i32.c | 83 - softfloat/source/extF80_to_i32_r_minMag.c | 97 -- softfloat/source/extF80_to_i64.c | 89 - softfloat/source/extF80_to_i64_r_minMag.c | 94 - softfloat/source/extF80_to_ui32.c | 83 - softfloat/source/extF80_to_ui32_r_minMag.c | 88 - softfloat/source/extF80_to_ui64.c | 84 - softfloat/source/extF80_to_ui64_r_minMag.c | 88 - softfloat/source/f128M_add.c | 97 -- softfloat/source/f128M_div.c | 187 -- softfloat/source/f128M_eq.c | 100 -- softfloat/source/f128M_eq_signaling.c | 92 - softfloat/source/f128M_le.c | 93 - softfloat/source/f128M_le_quiet.c | 96 -- softfloat/source/f128M_lt.c | 93 - softfloat/source/f128M_lt_quiet.c | 96 -- softfloat/source/f128M_mul.c | 158 -- softfloat/source/f128M_mulAdd.c | 92 - softfloat/source/f128M_rem.c | 182 -- softfloat/source/f128M_roundToInt.c | 223 --- softfloat/source/f128M_sqrt.c | 228 --- softfloat/source/f128M_sub.c | 97 -- softfloat/source/f128M_to_extF80M.c | 101 -- softfloat/source/f128M_to_f16.c | 113 -- softfloat/source/f128M_to_f32.c | 109 -- softfloat/source/f128M_to_f64.c | 112 -- softfloat/source/f128M_to_i32.c | 98 -- softfloat/source/f128M_to_i32_r_minMag.c | 106 -- softfloat/source/f128M_to_i64.c | 102 -- softfloat/source/f128M_to_i64_r_minMag.c | 124 -- softfloat/source/f128M_to_ui32.c | 98 -- softfloat/source/f128M_to_ui32_r_minMag.c | 102 -- softfloat/source/f128M_to_ui64.c | 102 -- softfloat/source/f128M_to_ui64_r_minMag.c | 114 -- softfloat/source/f128_add.c | 78 - softfloat/source/f128_div.c | 199 --- softfloat/source/f128_eq.c | 73 - softfloat/source/f128_eq_signaling.c | 67 - softfloat/source/f128_isSignalingNaN.c | 51 - softfloat/source/f128_le.c | 72 - softfloat/source/f128_le_quiet.c | 78 - softfloat/source/f128_lt.c | 72 - softfloat/source/f128_lt_quiet.c | 78 - softfloat/source/f128_mul.c | 163 -- softfloat/source/f128_mulAdd.c | 63 - softfloat/source/f128_rem.c | 190 -- softfloat/source/f128_roundToInt.c | 172 -- softfloat/source/f128_sqrt.c | 201 --- softfloat/source/f128_sub.c | 78 - softfloat/source/f128_to_extF80.c | 109 -- softfloat/source/f128_to_f16.c | 95 - softfloat/source/f128_to_f32.c | 95 - softfloat/source/f128_to_f64.c | 100 -- softfloat/source/f128_to_i32.c | 85 - softfloat/source/f128_to_i32_r_minMag.c | 100 -- softfloat/source/f128_to_i64.c | 95 - softfloat/source/f128_to_i64_r_minMag.c | 113 -- softfloat/source/f128_to_ui32.c | 86 - softfloat/source/f128_to_ui32_r_minMag.c | 89 - softfloat/source/f128_to_ui64.c | 96 -- softfloat/source/f128_to_ui64_r_minMag.c | 105 -- softfloat/source/f16_add.c | 70 - softfloat/source/f16_div.c | 186 -- softfloat/source/f16_eq.c | 66 - softfloat/source/f16_eq_signaling.c | 61 - softfloat/source/f16_isSignalingNaN.c | 51 - softfloat/source/f16_le.c | 66 - softfloat/source/f16_le_quiet.c | 71 - softfloat/source/f16_lt.c | 66 - softfloat/source/f16_lt_quiet.c | 71 - softfloat/source/f16_mul.c | 140 -- softfloat/source/f16_mulAdd.c | 60 - softfloat/source/f16_rem.c | 171 -- softfloat/source/f16_roundToInt.c | 120 -- softfloat/source/f16_sqrt.c | 136 -- softfloat/source/f16_sub.c | 70 - softfloat/source/f16_to_extF80.c | 101 -- softfloat/source/f16_to_extF80M.c | 111 -- softfloat/source/f16_to_f128.c | 96 -- softfloat/source/f16_to_f128M.c | 111 -- softfloat/source/f16_to_f32.c | 93 - softfloat/source/f16_to_f64.c | 93 - softfloat/source/f16_to_i32.c | 87 - softfloat/source/f16_to_i32_r_minMag.c | 88 - softfloat/source/f16_to_i64.c | 87 - softfloat/source/f16_to_i64_r_minMag.c | 88 - softfloat/source/f16_to_ui32.c | 84 - softfloat/source/f16_to_ui32_r_minMag.c | 87 - softfloat/source/f16_to_ui64.c | 96 -- softfloat/source/f16_to_ui64_r_minMag.c | 87 - softfloat/source/f32_add.c | 70 - softfloat/source/f32_div.c | 180 -- softfloat/source/f32_eq.c | 66 - softfloat/source/f32_eq_signaling.c | 61 - softfloat/source/f32_isSignalingNaN.c | 51 - softfloat/source/f32_le.c | 66 - softfloat/source/f32_le_quiet.c | 71 - softfloat/source/f32_lt.c | 66 - softfloat/source/f32_lt_quiet.c | 71 - softfloat/source/f32_mul.c | 137 -- softfloat/source/f32_mulAdd.c | 60 - softfloat/source/f32_rem.c | 168 -- softfloat/source/f32_roundToInt.c | 120 -- softfloat/source/f32_sqrt.c | 121 -- softfloat/source/f32_sub.c | 70 - softfloat/source/f32_to_bf16.c | 105 -- softfloat/source/f32_to_extF80.c | 101 -- softfloat/source/f32_to_extF80M.c | 111 -- softfloat/source/f32_to_f128.c | 96 -- softfloat/source/f32_to_f128M.c | 115 -- softfloat/source/f32_to_f16.c | 91 - softfloat/source/f32_to_f64.c | 93 - softfloat/source/f32_to_i32.c | 84 - softfloat/source/f32_to_i32_r_minMag.c | 89 - softfloat/source/f32_to_i64.c | 96 -- softfloat/source/f32_to_i64_r_minMag.c | 94 - softfloat/source/f32_to_ui32.c | 84 - softfloat/source/f32_to_ui32_r_minMag.c | 88 - softfloat/source/f32_to_ui64.c | 96 -- softfloat/source/f32_to_ui64_r_minMag.c | 90 - softfloat/source/f64_add.c | 74 - softfloat/source/f64_div.c | 172 -- softfloat/source/f64_eq.c | 66 - softfloat/source/f64_eq_signaling.c | 61 - softfloat/source/f64_isSignalingNaN.c | 51 - softfloat/source/f64_le.c | 67 - softfloat/source/f64_le_quiet.c | 72 - softfloat/source/f64_lt.c | 67 - softfloat/source/f64_lt_quiet.c | 72 - softfloat/source/f64_mul.c | 150 -- softfloat/source/f64_mulAdd.c | 60 - softfloat/source/f64_rem.c | 189 -- softfloat/source/f64_roundToInt.c | 120 -- softfloat/source/f64_sqrt.c | 133 -- softfloat/source/f64_sub.c | 74 - softfloat/source/f64_to_extF80.c | 101 -- softfloat/source/f64_to_extF80M.c | 111 -- softfloat/source/f64_to_f128.c | 98 -- softfloat/source/f64_to_f128M.c | 117 -- softfloat/source/f64_to_f16.c | 88 - softfloat/source/f64_to_f32.c | 88 - softfloat/source/f64_to_i32.c | 82 - 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mode 100644 softfloat/source/softfloat_state.c delete mode 100644 softfloat/source/ui32_to_extF80.c delete mode 100644 softfloat/source/ui32_to_extF80M.c delete mode 100644 softfloat/source/ui32_to_f128.c delete mode 100644 softfloat/source/ui32_to_f128M.c delete mode 100644 softfloat/source/ui32_to_f16.c delete mode 100644 softfloat/source/ui32_to_f32.c delete mode 100644 softfloat/source/ui32_to_f64.c delete mode 100644 softfloat/source/ui64_to_extF80.c delete mode 100644 softfloat/source/ui64_to_extF80M.c delete mode 100644 softfloat/source/ui64_to_f128.c delete mode 100644 softfloat/source/ui64_to_f128M.c delete mode 100644 softfloat/source/ui64_to_f16.c delete mode 100644 softfloat/source/ui64_to_f32.c delete mode 100644 softfloat/source/ui64_to_f64.c delete mode 100644 src/vm/aes_sbox.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 829ccc1..dd994dc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -16,19 +16,19 @@ set(CMAKE_CXX_STANDARD_REQUIRED ON) include(FetchContent) if(NOT TARGET dbt-rise-core) - FetchContent_Declare( - dbt_rise_core_git - GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git" - #GIT_TAG "origin/develop" - GIT_TAG d2bafe - GIT_SHALLOW OFF - UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped. - ) - FetchContent_GetProperties(dbt_rise_core_git) - if(NOT dbt_rise_core_git_POPULATED) - FetchContent_Populate(dbt_rise_core_git) - endif() - add_subdirectory(${dbt_rise_core_git_SOURCE_DIR} ${dbt_rise_core_git_BINARY_DIR}) + FetchContent_Declare( + dbt_rise_core_git + GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git" + #GIT_TAG "origin/develop" + GIT_TAG d2bafe + GIT_SHALLOW OFF + UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped. + ) + FetchContent_GetProperties(dbt_rise_core_git) + if(NOT dbt_rise_core_git_POPULATED) + FetchContent_Populate(dbt_rise_core_git) + endif() + add_subdirectory(${dbt_rise_core_git_SOURCE_DIR} ${dbt_rise_core_git_BINARY_DIR}) endif() FetchContent_GetProperties(scc_git) list(APPEND CMAKE_MODULE_PATH ${scc_git_SOURCE_DIR}/cmake) @@ -39,22 +39,21 @@ find_package(yaml-cpp) find_package(Boost COMPONENTS coroutine REQUIRED) if(CMAKE_PROJECT_NAME STREQUAL "dbt-rise-riscv") - set(CLANG_FORMAT_EXCLUDE_PATTERNS /build/ /.direnv/ softfloat/) - find_package(ClangFormat) + set(CLANG_FORMAT_EXCLUDE_PATTERNS /build/ /.direnv/ softfloat/) + find_package(ClangFormat) else() - set(CLANG_FORMAT_EXCLUDE_PATTERNS ${CLANG_FORMAT_EXCLUDE_PATTERNS} /build/ /.direnv/ softfloat/ PARENT_SCOPE) + set(CLANG_FORMAT_EXCLUDE_PATTERNS ${CLANG_FORMAT_EXCLUDE_PATTERNS} /build/ /.direnv/ softfloat/ PARENT_SCOPE) endif() -add_subdirectory(softfloat) - +add_subdirectory(softvector) set(LIB_SOURCES src/iss/plugin/instruction_count.cpp - src/iss/arch/rv32i.cpp + src/iss/arch/rv32i.cpp src/iss/arch/rv32imc.cpp src/iss/arch/rv32imac.cpp src/iss/arch/rv32gc.cpp src/iss/arch/rv32gcv.cpp - src/iss/arch/rv64i.cpp + src/iss/arch/rv64i.cpp src/iss/arch/rv64gc.cpp src/iss/arch/rv64gcv.cpp src/iss/arch/tgc5c.cpp @@ -67,8 +66,6 @@ set(LIB_SOURCES src/vm/interp/vm_rv64i.cpp src/vm/interp/vm_rv64gc.cpp src/vm/interp/vm_rv64gcv.cpp - src/vm/fp_functions.cpp - src/vm/vector_functions.cpp src/iss/debugger/csr_names.cpp src/iss/semihosting/semihosting.cpp ) @@ -163,11 +160,11 @@ get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES) target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL}) get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS) -if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND)) +if(NOT (DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND)) target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS}) endif() -target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine) +target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat softvector scc-util Boost::coroutine) if(TARGET yaml-cpp::yaml-cpp) target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS) @@ -216,9 +213,9 @@ endforeach() target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-riscv yaml-cpp::yaml-cpp Boost::program_options) if(TARGET fmt::fmt-header-only) - target_link_libraries(${PROJECT_NAME} PUBLIC fmt::fmt-header-only) + target_link_libraries(${PROJECT_NAME} PUBLIC fmt::fmt-header-only) else() - target_link_libraries(${PROJECT_NAME} PUBLIC fmt::fmt) + target_link_libraries(${PROJECT_NAME} PUBLIC fmt::fmt) endif() target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS}) diff --git a/softfloat/CMakeLists.txt b/softfloat/CMakeLists.txt deleted file mode 100644 index 8369f6c..0000000 --- a/softfloat/CMakeLists.txt +++ /dev/null @@ -1,354 +0,0 @@ -cmake_minimum_required(VERSION 3.12) -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake) # main (top) cmake dir -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake) # project specific cmake dir - -# Set the name of your project here -project("sotfloat" VERSION 3.0.0) - -# Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0) -set(VERSION "3e") - -include(GNUInstallDirs) - -set(SPECIALIZATION RISCV) - -set(LIB_HEADERS source/include/softfloat.h source/include/softfloat_types.h) -set(PRIMITIVES - source/s_eq128.c - source/s_le128.c - source/s_lt128.c - source/s_shortShiftLeft128.c - source/s_shortShiftRight128.c - source/s_shortShiftRightJam64.c - source/s_shortShiftRightJam64Extra.c - source/s_shortShiftRightJam128.c - source/s_shortShiftRightJam128Extra.c - source/s_shiftRightJam32.c - source/s_shiftRightJam64.c - source/s_shiftRightJam64Extra.c - source/s_shiftRightJam128.c - source/s_shiftRightJam128Extra.c - source/s_shiftRightJam256M.c - source/s_countLeadingZeros8.c - source/s_countLeadingZeros16.c - source/s_countLeadingZeros32.c - source/s_countLeadingZeros64.c - source/s_add128.c - source/s_add256M.c - source/s_sub128.c - source/s_sub256M.c - source/s_mul64ByShifted32To128.c - source/s_mul64To128.c - source/s_mul128By32.c - source/s_mul128To256M.c - source/s_approxRecip_1Ks.c - source/s_approxRecip32_1.c - source/s_approxRecipSqrt_1Ks.c - source/s_approxRecipSqrt32_1.c -) - -set(SPECIALIZE - source/${SPECIALIZATION}/softfloat_raiseFlags.c - source/${SPECIALIZATION}/s_f16UIToCommonNaN.c - source/${SPECIALIZATION}/s_commonNaNToF16UI.c - source/${SPECIALIZATION}/s_propagateNaNF16UI.c - source/${SPECIALIZATION}/s_f32UIToCommonNaN.c - source/${SPECIALIZATION}/s_commonNaNToF32UI.c - source/${SPECIALIZATION}/s_propagateNaNF32UI.c - source/${SPECIALIZATION}/s_f64UIToCommonNaN.c - source/${SPECIALIZATION}/s_commonNaNToF64UI.c - source/${SPECIALIZATION}/s_propagateNaNF64UI.c - source/${SPECIALIZATION}/extF80M_isSignalingNaN.c - source/${SPECIALIZATION}/s_extF80UIToCommonNaN.c - source/${SPECIALIZATION}/s_commonNaNToExtF80UI.c - source/${SPECIALIZATION}/s_propagateNaNExtF80UI.c - source/${SPECIALIZATION}/f128M_isSignalingNaN.c - source/${SPECIALIZATION}/s_f128UIToCommonNaN.c - source/${SPECIALIZATION}/s_commonNaNToF128UI.c - source/${SPECIALIZATION}/s_propagateNaNF128UI.c -) - -set(OTHERS - source/s_roundToUI32.c - source/s_roundToUI64.c - source/s_roundToI32.c - source/s_roundToI64.c - source/s_normSubnormalF16Sig.c - source/s_roundPackToF16.c - source/s_normRoundPackToF16.c - source/s_addMagsF16.c - source/s_subMagsF16.c - source/s_mulAddF16.c - source/s_normSubnormalF32Sig.c - source/s_roundPackToF32.c - source/s_normRoundPackToF32.c - source/s_addMagsF32.c - source/s_subMagsF32.c - source/s_mulAddF32.c - source/s_normSubnormalF64Sig.c - source/s_roundPackToF64.c - source/s_normRoundPackToF64.c - source/s_addMagsF64.c - source/s_subMagsF64.c - source/s_mulAddF64.c - source/s_normSubnormalExtF80Sig.c - source/s_roundPackToExtF80.c - source/s_normRoundPackToExtF80.c - source/s_addMagsExtF80.c - source/s_subMagsExtF80.c - source/s_normSubnormalF128Sig.c - source/s_roundPackToF128.c - source/s_normRoundPackToF128.c - source/s_addMagsF128.c - source/s_subMagsF128.c - source/s_mulAddF128.c - source/softfloat_state.c - source/ui32_to_f16.c - source/ui32_to_f32.c - source/ui32_to_f64.c - source/ui32_to_extF80.c - source/ui32_to_extF80M.c - source/ui32_to_f128.c - source/ui32_to_f128M.c - source/ui64_to_f16.c - source/ui64_to_f32.c - source/ui64_to_f64.c - source/ui64_to_extF80.c - source/ui64_to_extF80M.c - source/ui64_to_f128.c - source/ui64_to_f128M.c - source/i32_to_f16.c - source/i32_to_f32.c - source/i32_to_f64.c - source/i32_to_extF80.c - source/i32_to_extF80M.c - source/i32_to_f128.c - source/i32_to_f128M.c - source/i64_to_f16.c - source/i64_to_f32.c - source/i64_to_f64.c - source/i64_to_extF80.c - source/i64_to_extF80M.c - source/i64_to_f128.c - source/i64_to_f128M.c - source/f16_to_ui32.c - source/f16_to_ui64.c - source/f16_to_i32.c - source/f16_to_i64.c - source/f16_to_ui32_r_minMag.c - source/f16_to_ui64_r_minMag.c - source/f16_to_i32_r_minMag.c - source/f16_to_i64_r_minMag.c - source/f16_to_f32.c - source/f16_to_f64.c - source/f16_to_extF80.c - source/f16_to_extF80M.c - source/f16_to_f128.c - source/f16_to_f128M.c - source/f16_roundToInt.c - source/f16_add.c - source/f16_sub.c - source/f16_mul.c - source/f16_mulAdd.c - source/f16_div.c - source/f16_rem.c - source/f16_sqrt.c - source/f16_eq.c - source/f16_le.c - source/f16_lt.c - source/f16_eq_signaling.c - source/f16_le_quiet.c - source/f16_lt_quiet.c - source/f16_isSignalingNaN.c - source/f32_to_ui32.c - source/f32_to_ui64.c - source/f32_to_i32.c - source/f32_to_i64.c - source/f32_to_ui32_r_minMag.c - source/f32_to_ui64_r_minMag.c - source/f32_to_i32_r_minMag.c - source/f32_to_i64_r_minMag.c - source/f32_to_f16.c - source/f32_to_f64.c - source/f32_to_extF80.c - source/f32_to_extF80M.c - source/f32_to_f128.c - source/f32_to_f128M.c - source/f32_roundToInt.c - source/f32_add.c - source/f32_sub.c - source/f32_mul.c - source/f32_mulAdd.c - source/f32_div.c - source/f32_rem.c - source/f32_sqrt.c - source/f32_eq.c - source/f32_le.c - source/f32_lt.c - source/f32_eq_signaling.c - source/f32_le_quiet.c - source/f32_lt_quiet.c - source/f32_isSignalingNaN.c - source/f64_to_ui32.c - source/f64_to_ui64.c - source/f64_to_i32.c - source/f64_to_i64.c - source/f64_to_ui32_r_minMag.c - source/f64_to_ui64_r_minMag.c - source/f64_to_i32_r_minMag.c - source/f64_to_i64_r_minMag.c - source/f64_to_f16.c - source/f64_to_f32.c - source/f64_to_extF80.c - source/f64_to_extF80M.c - source/f64_to_f128.c - source/f64_to_f128M.c - source/f64_roundToInt.c - source/f64_add.c - source/f64_sub.c - source/f64_mul.c - source/f64_mulAdd.c - source/f64_div.c - source/f64_rem.c - source/f64_sqrt.c - source/f64_eq.c - source/f64_le.c - source/f64_lt.c - source/f64_eq_signaling.c - source/f64_le_quiet.c - source/f64_lt_quiet.c - source/f64_isSignalingNaN.c - source/extF80_to_ui32.c - source/extF80_to_ui64.c - source/extF80_to_i32.c - source/extF80_to_i64.c - source/extF80_to_ui32_r_minMag.c - source/extF80_to_ui64_r_minMag.c - source/extF80_to_i32_r_minMag.c - source/extF80_to_i64_r_minMag.c - source/extF80_to_f16.c - source/extF80_to_f32.c - source/extF80_to_f64.c - source/extF80_to_f128.c - source/extF80_roundToInt.c - source/extF80_add.c - source/extF80_sub.c - source/extF80_mul.c - source/extF80_div.c - source/extF80_rem.c - source/extF80_sqrt.c - source/extF80_eq.c - source/extF80_le.c - source/extF80_lt.c - source/extF80_eq_signaling.c - source/extF80_le_quiet.c - source/extF80_lt_quiet.c - source/extF80_isSignalingNaN.c - source/extF80M_to_ui32.c - source/extF80M_to_ui64.c - source/extF80M_to_i32.c - source/extF80M_to_i64.c - source/extF80M_to_ui32_r_minMag.c - source/extF80M_to_ui64_r_minMag.c - source/extF80M_to_i32_r_minMag.c - source/extF80M_to_i64_r_minMag.c - source/extF80M_to_f16.c - source/extF80M_to_f32.c - source/extF80M_to_f64.c - source/extF80M_to_f128M.c - source/extF80M_roundToInt.c - source/extF80M_add.c - source/extF80M_sub.c - source/extF80M_mul.c - source/extF80M_div.c - source/extF80M_rem.c - source/extF80M_sqrt.c - source/extF80M_eq.c - source/extF80M_le.c - source/extF80M_lt.c - source/extF80M_eq_signaling.c - source/extF80M_le_quiet.c - source/extF80M_lt_quiet.c - source/f128_to_ui32.c - source/f128_to_ui64.c - source/f128_to_i32.c - source/f128_to_i64.c - source/f128_to_ui32_r_minMag.c - source/f128_to_ui64_r_minMag.c - source/f128_to_i32_r_minMag.c - source/f128_to_i64_r_minMag.c - source/f128_to_f16.c - source/f128_to_f32.c - source/f128_to_extF80.c - source/f128_to_f64.c - source/f128_roundToInt.c - source/f128_add.c - source/f128_sub.c - source/f128_mul.c - source/f128_mulAdd.c - source/f128_div.c - source/f128_rem.c - source/f128_sqrt.c - source/f128_eq.c - source/f128_le.c - source/f128_lt.c - source/f128_eq_signaling.c - source/f128_le_quiet.c - source/f128_lt_quiet.c - source/f128_isSignalingNaN.c - source/f128M_to_ui32.c - source/f128M_to_ui64.c - source/f128M_to_i32.c - source/f128M_to_i64.c - source/f128M_to_ui32_r_minMag.c - source/f128M_to_ui64_r_minMag.c - source/f128M_to_i32_r_minMag.c - source/f128M_to_i64_r_minMag.c - source/f128M_to_f16.c - source/f128M_to_f32.c - source/f128M_to_extF80M.c - source/f128M_to_f64.c - source/f128M_roundToInt.c - source/f128M_add.c - source/f128M_sub.c - source/f128M_mul.c - source/f128M_mulAdd.c - source/f128M_div.c - source/f128M_rem.c - source/f128M_sqrt.c - source/f128M_eq.c - source/f128M_le.c - source/f128M_lt.c - source/f128M_eq_signaling.c - source/f128M_le_quiet.c - source/f128M_lt_quiet.c -) - -set(LIB_SOURCES ${PRIMITIVES} ${SPECIALIZE} ${OTHERS}) - -add_library(softfloat STATIC ${LIB_SOURCES}) -set_property(TARGET softfloat PROPERTY C_STANDARD 99) -target_compile_definitions(softfloat PRIVATE - SOFTFLOAT_ROUND_ODD - INLINE_LEVEL=5 - SOFTFLOAT_FAST_DIV32TO16 - SOFTFLOAT_FAST_DIV64TO32 - SOFTFLOAT_FAST_INT64 -# THREAD_LOCAL=__thread -) -target_include_directories(softfloat PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/build/Linux-x86_64-GCC) -target_include_directories(softfloat PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/source/include ${CMAKE_CURRENT_SOURCE_DIR}/source/${SPECIALIZATION}) -set_target_properties(softfloat PROPERTIES - VERSION ${VERSION} - FRAMEWORK FALSE - PUBLIC_HEADER "${LIB_HEADERS}" -) - -install(TARGETS softfloat - EXPORT ${PROJECT_NAME}Targets # for downstream dependencies - ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}/static COMPONENT libs # static lib - LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # shared lib - FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac - PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} COMPONENT devel # headers for mac (note the different component -> different package) - INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers -) diff --git a/softfloat/COPYING.txt b/softfloat/COPYING.txt deleted file mode 100644 index 9c05d49..0000000 --- a/softfloat/COPYING.txt +++ /dev/null @@ -1,37 +0,0 @@ - -License for Berkeley SoftFloat Release 3e - -John R. Hauser -2018 January 20 - -The following applies to the whole of SoftFloat Release 3e as well as to -each source file individually. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions, and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors - may be used to endorse or promote products derived from this software - without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - diff --git a/softfloat/README.html b/softfloat/README.html deleted file mode 100644 index 7989e0c..0000000 --- a/softfloat/README.html +++ /dev/null @@ -1,49 +0,0 @@ - - - - -Berkeley SoftFloat Package Overview - - - - -

Package Overview for Berkeley SoftFloat Release 3e

- -

-John R. Hauser
-2018 January 20
-

- -

-Berkeley SoftFloat is a software implementation of binary floating-point that -conforms to the IEEE Standard for Floating-Point Arithmetic. -SoftFloat is distributed in the form of C source code. -Building the SoftFloat sources generates a library file (typically -softfloat.a or libsoftfloat.a) containing the -floating-point subroutines. -

- -

-The SoftFloat package is documented in the following files in the -doc subdirectory: -

- - - - - - - - - - - - - -
SoftFloat.htmlDocumentation for using the SoftFloat functions.
SoftFloat-source.htmlDocumentation for building SoftFloat.
SoftFloat-history.html   History of the major changes to SoftFloat.
-
-Other files in the package comprise the source code for SoftFloat. -

- - - diff --git a/softfloat/README.md b/softfloat/README.md deleted file mode 100644 index d468020..0000000 --- a/softfloat/README.md +++ /dev/null @@ -1,24 +0,0 @@ - -Package Overview for Berkeley SoftFloat Release 3e -================================================== - -John R. Hauser
-2018 January 20 - - -Berkeley SoftFloat is a software implementation of binary floating-point -that conforms to the IEEE Standard for Floating-Point Arithmetic. SoftFloat -is distributed in the form of C source code. Building the SoftFloat sources -generates a library file (typically `softfloat.a` or `libsoftfloat.a`) -containing the floating-point subroutines. - - -The SoftFloat package is documented in the following files in the `doc` -subdirectory: - -* [SoftFloat.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat.html) Documentation for using the SoftFloat functions. -* [SoftFloat-source.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-source.html) Documentation for building SoftFloat. -* [SoftFloat-history.html](http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-history.html) History of the major changes to SoftFloat. - -Other files in the package comprise the source code for SoftFloat. - diff --git a/softfloat/README.txt b/softfloat/README.txt deleted file mode 100644 index f819baa..0000000 --- a/softfloat/README.txt +++ /dev/null @@ -1,21 +0,0 @@ - -Package Overview for Berkeley SoftFloat Release 3e - -John R. Hauser -2018 January 20 - -Berkeley SoftFloat is a software implementation of binary floating-point -that conforms to the IEEE Standard for Floating-Point Arithmetic. SoftFloat -is distributed in the form of C source code. Building the SoftFloat sources -generates a library file (typically "softfloat.a" or "libsoftfloat.a") -containing the floating-point subroutines. - -The SoftFloat package is documented in the following files in the "doc" -subdirectory: - - SoftFloat.html Documentation for using the SoftFloat functions. - SoftFloat-source.html Documentation for building SoftFloat. - SoftFloat-history.html History of the major changes to SoftFloat. - -Other files in the package comprise the source code for SoftFloat. - diff --git a/softfloat/build/Linux-386-GCC/Makefile b/softfloat/build/Linux-386-GCC/Makefile deleted file mode 100644 index 4181600..0000000 --- a/softfloat/build/Linux-386-GCC/Makefile +++ /dev/null @@ -1,325 +0,0 @@ - -#============================================================================= -# -# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic -# Package, Release 3e, by John R. Hauser. -# -# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -# University of California. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions, and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions, and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the University nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#============================================================================= - -SOURCE_DIR ?= ../../source -SPECIALIZE_TYPE ?= 8086 - -SOFTFLOAT_OPTS ?= \ - -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \ - -DSOFTFLOAT_FAST_DIV64TO32 - -DELETE = rm -f -C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include -COMPILE_C = \ - gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \ - $(C_INCLUDES) -O2 -o $@ -MAKELIB = ar crs $@ - -OBJ = .o -LIB = .a - -OTHER_HEADERS = - -.PHONY: all -all: softfloat$(LIB) - -OBJS_PRIMITIVES = \ - s_compare96M$(OBJ) \ - s_compare128M$(OBJ) \ - s_shortShiftLeft64To96M$(OBJ) \ - s_shortShiftLeftM$(OBJ) \ - s_shiftLeftM$(OBJ) \ - s_shortShiftRightM$(OBJ) \ - s_shortShiftRightJam64$(OBJ) \ - s_shortShiftRightJamM$(OBJ) \ - s_shiftRightJam32$(OBJ) \ - s_shiftRightJam64$(OBJ) \ - s_shiftRightJamM$(OBJ) \ - s_shiftRightM$(OBJ) \ - s_countLeadingZeros8$(OBJ) \ - s_countLeadingZeros16$(OBJ) \ - s_countLeadingZeros32$(OBJ) \ - s_countLeadingZeros64$(OBJ) \ - s_addM$(OBJ) \ - s_addCarryM$(OBJ) \ - s_addComplCarryM$(OBJ) \ - s_negXM$(OBJ) \ - s_sub1XM$(OBJ) \ - s_subM$(OBJ) \ - s_mul64To128M$(OBJ) \ - s_mul128MTo256M$(OBJ) \ - s_approxRecip_1Ks$(OBJ) \ - s_approxRecip32_1$(OBJ) \ - s_approxRecipSqrt_1Ks$(OBJ) \ - s_approxRecipSqrt32_1$(OBJ) \ - s_remStepMBy32$(OBJ) \ - -OBJS_SPECIALIZE = \ - softfloat_raiseFlags$(OBJ) \ - s_f16UIToCommonNaN$(OBJ) \ - s_commonNaNToF16UI$(OBJ) \ - s_propagateNaNF16UI$(OBJ) \ - s_f32UIToCommonNaN$(OBJ) \ - s_commonNaNToF32UI$(OBJ) \ - s_propagateNaNF32UI$(OBJ) \ - s_f64UIToCommonNaN$(OBJ) \ - s_commonNaNToF64UI$(OBJ) \ - s_propagateNaNF64UI$(OBJ) \ - extF80M_isSignalingNaN$(OBJ) \ - s_extF80MToCommonNaN$(OBJ) \ - s_commonNaNToExtF80M$(OBJ) \ - s_propagateNaNExtF80M$(OBJ) \ - f128M_isSignalingNaN$(OBJ) \ - s_f128MToCommonNaN$(OBJ) \ - s_commonNaNToF128M$(OBJ) \ - s_propagateNaNF128M$(OBJ) \ - -OBJS_OTHERS = \ - s_roundToUI32$(OBJ) \ - s_roundMToUI64$(OBJ) \ - s_roundToI32$(OBJ) \ - s_roundMToI64$(OBJ) \ - s_normSubnormalF16Sig$(OBJ) \ - s_roundPackToF16$(OBJ) \ - s_normRoundPackToF16$(OBJ) \ - s_addMagsF16$(OBJ) \ - s_subMagsF16$(OBJ) \ - s_mulAddF16$(OBJ) \ - s_normSubnormalF32Sig$(OBJ) \ - s_roundPackToF32$(OBJ) \ - s_normRoundPackToF32$(OBJ) \ - s_addMagsF32$(OBJ) \ - s_subMagsF32$(OBJ) \ - s_mulAddF32$(OBJ) \ - s_normSubnormalF64Sig$(OBJ) \ - s_roundPackToF64$(OBJ) \ - s_normRoundPackToF64$(OBJ) \ - s_addMagsF64$(OBJ) \ - s_subMagsF64$(OBJ) \ - s_mulAddF64$(OBJ) \ - s_tryPropagateNaNExtF80M$(OBJ) \ - s_invalidExtF80M$(OBJ) \ - s_normExtF80SigM$(OBJ) \ - s_roundPackMToExtF80M$(OBJ) \ - s_normRoundPackMToExtF80M$(OBJ) \ - s_addExtF80M$(OBJ) \ - s_compareNonnormExtF80M$(OBJ) \ - s_isNaNF128M$(OBJ) \ - s_tryPropagateNaNF128M$(OBJ) \ - s_invalidF128M$(OBJ) \ - s_shiftNormSigF128M$(OBJ) \ - s_roundPackMToF128M$(OBJ) \ - s_normRoundPackMToF128M$(OBJ) \ - s_addF128M$(OBJ) \ - s_mulAddF128M$(OBJ) \ - softfloat_state$(OBJ) \ - ui32_to_f16$(OBJ) \ - ui32_to_f32$(OBJ) \ - ui32_to_f64$(OBJ) \ - ui32_to_extF80M$(OBJ) \ - ui32_to_f128M$(OBJ) \ - ui64_to_f16$(OBJ) \ - ui64_to_f32$(OBJ) \ - ui64_to_f64$(OBJ) \ - ui64_to_extF80M$(OBJ) \ - ui64_to_f128M$(OBJ) \ - i32_to_f16$(OBJ) \ - i32_to_f32$(OBJ) \ - i32_to_f64$(OBJ) \ - i32_to_extF80M$(OBJ) \ - i32_to_f128M$(OBJ) \ - i64_to_f16$(OBJ) \ - i64_to_f32$(OBJ) \ - i64_to_f64$(OBJ) \ - i64_to_extF80M$(OBJ) \ - i64_to_f128M$(OBJ) \ - f16_to_ui32$(OBJ) \ - f16_to_ui64$(OBJ) \ - f16_to_i32$(OBJ) \ - f16_to_i64$(OBJ) \ - f16_to_ui32_r_minMag$(OBJ) \ - f16_to_ui64_r_minMag$(OBJ) \ - f16_to_i32_r_minMag$(OBJ) \ - f16_to_i64_r_minMag$(OBJ) \ - f16_to_f32$(OBJ) \ - f16_to_f64$(OBJ) \ - f16_to_extF80M$(OBJ) \ - f16_to_f128M$(OBJ) \ - f16_roundToInt$(OBJ) \ - f16_add$(OBJ) \ - f16_sub$(OBJ) \ - f16_mul$(OBJ) \ - f16_mulAdd$(OBJ) \ - f16_div$(OBJ) \ - f16_rem$(OBJ) \ - f16_sqrt$(OBJ) \ - f16_eq$(OBJ) \ - f16_le$(OBJ) \ - f16_lt$(OBJ) \ - f16_eq_signaling$(OBJ) \ - f16_le_quiet$(OBJ) \ - f16_lt_quiet$(OBJ) \ - f16_isSignalingNaN$(OBJ) \ - f32_to_ui32$(OBJ) \ - f32_to_ui64$(OBJ) \ - f32_to_i32$(OBJ) \ - f32_to_i64$(OBJ) \ - f32_to_ui32_r_minMag$(OBJ) \ - f32_to_ui64_r_minMag$(OBJ) \ - f32_to_i32_r_minMag$(OBJ) \ - f32_to_i64_r_minMag$(OBJ) \ - f32_to_f16$(OBJ) \ - f32_to_f64$(OBJ) \ - f32_to_extF80M$(OBJ) \ - f32_to_f128M$(OBJ) \ - f32_roundToInt$(OBJ) \ - f32_add$(OBJ) \ - f32_sub$(OBJ) \ - f32_mul$(OBJ) \ - f32_mulAdd$(OBJ) \ - f32_div$(OBJ) \ - f32_rem$(OBJ) \ - f32_sqrt$(OBJ) \ - f32_eq$(OBJ) \ - f32_le$(OBJ) \ - f32_lt$(OBJ) \ - f32_eq_signaling$(OBJ) \ - f32_le_quiet$(OBJ) \ - f32_lt_quiet$(OBJ) \ - f32_isSignalingNaN$(OBJ) \ - f64_to_ui32$(OBJ) \ - f64_to_ui64$(OBJ) \ - f64_to_i32$(OBJ) \ - f64_to_i64$(OBJ) \ - f64_to_ui32_r_minMag$(OBJ) \ - f64_to_ui64_r_minMag$(OBJ) \ - f64_to_i32_r_minMag$(OBJ) \ - f64_to_i64_r_minMag$(OBJ) \ - f64_to_f16$(OBJ) \ - f64_to_f32$(OBJ) \ - f64_to_extF80M$(OBJ) \ - f64_to_f128M$(OBJ) \ - f64_roundToInt$(OBJ) \ - f64_add$(OBJ) \ - f64_sub$(OBJ) \ - f64_mul$(OBJ) \ - f64_mulAdd$(OBJ) \ - f64_div$(OBJ) \ - f64_rem$(OBJ) \ - f64_sqrt$(OBJ) \ - f64_eq$(OBJ) \ - f64_le$(OBJ) \ - f64_lt$(OBJ) \ - f64_eq_signaling$(OBJ) \ - f64_le_quiet$(OBJ) \ - f64_lt_quiet$(OBJ) \ - f64_isSignalingNaN$(OBJ) \ - extF80M_to_ui32$(OBJ) \ - extF80M_to_ui64$(OBJ) \ - extF80M_to_i32$(OBJ) \ - extF80M_to_i64$(OBJ) \ - extF80M_to_ui32_r_minMag$(OBJ) \ - extF80M_to_ui64_r_minMag$(OBJ) \ - extF80M_to_i32_r_minMag$(OBJ) \ - extF80M_to_i64_r_minMag$(OBJ) \ - extF80M_to_f16$(OBJ) \ - extF80M_to_f32$(OBJ) \ - extF80M_to_f64$(OBJ) \ - extF80M_to_f128M$(OBJ) \ - extF80M_roundToInt$(OBJ) \ - extF80M_add$(OBJ) \ - extF80M_sub$(OBJ) \ - extF80M_mul$(OBJ) \ - extF80M_div$(OBJ) \ - extF80M_rem$(OBJ) \ - extF80M_sqrt$(OBJ) \ - extF80M_eq$(OBJ) \ - extF80M_le$(OBJ) \ - extF80M_lt$(OBJ) \ - extF80M_eq_signaling$(OBJ) \ - extF80M_le_quiet$(OBJ) \ - extF80M_lt_quiet$(OBJ) \ - f128M_to_ui32$(OBJ) \ - f128M_to_ui64$(OBJ) \ - f128M_to_i32$(OBJ) \ - f128M_to_i64$(OBJ) \ - f128M_to_ui32_r_minMag$(OBJ) \ - f128M_to_ui64_r_minMag$(OBJ) \ - f128M_to_i32_r_minMag$(OBJ) \ - f128M_to_i64_r_minMag$(OBJ) \ - f128M_to_f16$(OBJ) \ - f128M_to_f32$(OBJ) \ - f128M_to_f64$(OBJ) \ - f128M_to_extF80M$(OBJ) \ - f128M_roundToInt$(OBJ) \ - f128M_add$(OBJ) \ - f128M_sub$(OBJ) \ - f128M_mul$(OBJ) \ - f128M_mulAdd$(OBJ) \ - f128M_div$(OBJ) \ - f128M_rem$(OBJ) \ - f128M_sqrt$(OBJ) \ - f128M_eq$(OBJ) \ - f128M_le$(OBJ) \ - f128M_lt$(OBJ) \ - f128M_eq_signaling$(OBJ) \ - f128M_le_quiet$(OBJ) \ - f128M_lt_quiet$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) - -$(OBJS_ALL): \ - $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ - $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ - $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ - $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ - $(SOURCE_DIR)/include/softfloat.h - -$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$*.c - -$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c - -softfloat$(LIB): $(OBJS_ALL) - $(DELETE) $@ - $(MAKELIB) $^ - -.PHONY: clean -clean: - $(DELETE) $(OBJS_ALL) softfloat$(LIB) - diff --git a/softfloat/build/Linux-386-GCC/platform.h b/softfloat/build/Linux-386-GCC/platform.h deleted file mode 100644 index 420aa4e..0000000 --- a/softfloat/build/Linux-386-GCC/platform.h +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define LITTLEENDIAN 1 - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#ifdef __GNUC_STDC_INLINE__ -#define INLINE inline -#else -#define INLINE extern inline -#endif - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define SOFTFLOAT_BUILTIN_CLZ 1 -#include "opts-GCC.h" - diff --git a/softfloat/build/Linux-386-SSE2-GCC/Makefile b/softfloat/build/Linux-386-SSE2-GCC/Makefile deleted file mode 100644 index 1cf6f5e..0000000 --- a/softfloat/build/Linux-386-SSE2-GCC/Makefile +++ /dev/null @@ -1,325 +0,0 @@ - -#============================================================================= -# -# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic -# Package, Release 3e, by John R. Hauser. -# -# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -# University of California. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions, and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions, and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the University nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#============================================================================= - -SOURCE_DIR ?= ../../source -SPECIALIZE_TYPE ?= 8086-SSE - -SOFTFLOAT_OPTS ?= \ - -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \ - -DSOFTFLOAT_FAST_DIV64TO32 - -DELETE = rm -f -C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include -COMPILE_C = \ - gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \ - $(C_INCLUDES) -O2 -o $@ -MAKELIB = ar crs $@ - -OBJ = .o -LIB = .a - -OTHER_HEADERS = - -.PHONY: all -all: softfloat$(LIB) - -OBJS_PRIMITIVES = \ - s_compare96M$(OBJ) \ - s_compare128M$(OBJ) \ - s_shortShiftLeft64To96M$(OBJ) \ - s_shortShiftLeftM$(OBJ) \ - s_shiftLeftM$(OBJ) \ - s_shortShiftRightM$(OBJ) \ - s_shortShiftRightJam64$(OBJ) \ - s_shortShiftRightJamM$(OBJ) \ - s_shiftRightJam32$(OBJ) \ - s_shiftRightJam64$(OBJ) \ - s_shiftRightJamM$(OBJ) \ - s_shiftRightM$(OBJ) \ - s_countLeadingZeros8$(OBJ) \ - s_countLeadingZeros16$(OBJ) \ - s_countLeadingZeros32$(OBJ) \ - s_countLeadingZeros64$(OBJ) \ - s_addM$(OBJ) \ - s_addCarryM$(OBJ) \ - s_addComplCarryM$(OBJ) \ - s_negXM$(OBJ) \ - s_sub1XM$(OBJ) \ - s_subM$(OBJ) \ - s_mul64To128M$(OBJ) \ - s_mul128MTo256M$(OBJ) \ - s_approxRecip_1Ks$(OBJ) \ - s_approxRecip32_1$(OBJ) \ - s_approxRecipSqrt_1Ks$(OBJ) \ - s_approxRecipSqrt32_1$(OBJ) \ - s_remStepMBy32$(OBJ) \ - -OBJS_SPECIALIZE = \ - softfloat_raiseFlags$(OBJ) \ - s_f16UIToCommonNaN$(OBJ) \ - s_commonNaNToF16UI$(OBJ) \ - s_propagateNaNF16UI$(OBJ) \ - s_f32UIToCommonNaN$(OBJ) \ - s_commonNaNToF32UI$(OBJ) \ - s_propagateNaNF32UI$(OBJ) \ - s_f64UIToCommonNaN$(OBJ) \ - s_commonNaNToF64UI$(OBJ) \ - s_propagateNaNF64UI$(OBJ) \ - extF80M_isSignalingNaN$(OBJ) \ - s_extF80MToCommonNaN$(OBJ) \ - s_commonNaNToExtF80M$(OBJ) \ - s_propagateNaNExtF80M$(OBJ) \ - f128M_isSignalingNaN$(OBJ) \ - s_f128MToCommonNaN$(OBJ) \ - s_commonNaNToF128M$(OBJ) \ - s_propagateNaNF128M$(OBJ) \ - -OBJS_OTHERS = \ - s_roundToUI32$(OBJ) \ - s_roundMToUI64$(OBJ) \ - s_roundToI32$(OBJ) \ - s_roundMToI64$(OBJ) \ - s_normSubnormalF16Sig$(OBJ) \ - s_roundPackToF16$(OBJ) \ - s_normRoundPackToF16$(OBJ) \ - s_addMagsF16$(OBJ) \ - s_subMagsF16$(OBJ) \ - s_mulAddF16$(OBJ) \ - s_normSubnormalF32Sig$(OBJ) \ - s_roundPackToF32$(OBJ) \ - s_normRoundPackToF32$(OBJ) \ - s_addMagsF32$(OBJ) \ - s_subMagsF32$(OBJ) \ - s_mulAddF32$(OBJ) \ - s_normSubnormalF64Sig$(OBJ) \ - s_roundPackToF64$(OBJ) \ - s_normRoundPackToF64$(OBJ) \ - s_addMagsF64$(OBJ) \ - s_subMagsF64$(OBJ) \ - s_mulAddF64$(OBJ) \ - s_tryPropagateNaNExtF80M$(OBJ) \ - s_invalidExtF80M$(OBJ) \ - s_normExtF80SigM$(OBJ) \ - s_roundPackMToExtF80M$(OBJ) \ - s_normRoundPackMToExtF80M$(OBJ) \ - s_addExtF80M$(OBJ) \ - s_compareNonnormExtF80M$(OBJ) \ - s_isNaNF128M$(OBJ) \ - s_tryPropagateNaNF128M$(OBJ) \ - s_invalidF128M$(OBJ) \ - s_shiftNormSigF128M$(OBJ) \ - s_roundPackMToF128M$(OBJ) \ - s_normRoundPackMToF128M$(OBJ) \ - s_addF128M$(OBJ) \ - s_mulAddF128M$(OBJ) \ - softfloat_state$(OBJ) \ - ui32_to_f16$(OBJ) \ - ui32_to_f32$(OBJ) \ - ui32_to_f64$(OBJ) \ - ui32_to_extF80M$(OBJ) \ - ui32_to_f128M$(OBJ) \ - ui64_to_f16$(OBJ) \ - ui64_to_f32$(OBJ) \ - ui64_to_f64$(OBJ) \ - ui64_to_extF80M$(OBJ) \ - ui64_to_f128M$(OBJ) \ - i32_to_f16$(OBJ) \ - i32_to_f32$(OBJ) \ - i32_to_f64$(OBJ) \ - i32_to_extF80M$(OBJ) \ - i32_to_f128M$(OBJ) \ - i64_to_f16$(OBJ) \ - i64_to_f32$(OBJ) \ - i64_to_f64$(OBJ) \ - i64_to_extF80M$(OBJ) \ - i64_to_f128M$(OBJ) \ - f16_to_ui32$(OBJ) \ - f16_to_ui64$(OBJ) \ - f16_to_i32$(OBJ) \ - f16_to_i64$(OBJ) \ - f16_to_ui32_r_minMag$(OBJ) \ - f16_to_ui64_r_minMag$(OBJ) \ - f16_to_i32_r_minMag$(OBJ) \ - f16_to_i64_r_minMag$(OBJ) \ - f16_to_f32$(OBJ) \ - f16_to_f64$(OBJ) \ - f16_to_extF80M$(OBJ) \ - f16_to_f128M$(OBJ) \ - f16_roundToInt$(OBJ) \ - f16_add$(OBJ) \ - f16_sub$(OBJ) \ - f16_mul$(OBJ) \ - f16_mulAdd$(OBJ) \ - f16_div$(OBJ) \ - f16_rem$(OBJ) \ - f16_sqrt$(OBJ) \ - f16_eq$(OBJ) \ - f16_le$(OBJ) \ - f16_lt$(OBJ) \ - f16_eq_signaling$(OBJ) \ - f16_le_quiet$(OBJ) \ - f16_lt_quiet$(OBJ) \ - f16_isSignalingNaN$(OBJ) \ - f32_to_ui32$(OBJ) \ - f32_to_ui64$(OBJ) \ - f32_to_i32$(OBJ) \ - f32_to_i64$(OBJ) \ - f32_to_ui32_r_minMag$(OBJ) \ - f32_to_ui64_r_minMag$(OBJ) \ - f32_to_i32_r_minMag$(OBJ) \ - f32_to_i64_r_minMag$(OBJ) \ - f32_to_f16$(OBJ) \ - f32_to_f64$(OBJ) \ - f32_to_extF80M$(OBJ) \ - f32_to_f128M$(OBJ) \ - f32_roundToInt$(OBJ) \ - f32_add$(OBJ) \ - f32_sub$(OBJ) \ - f32_mul$(OBJ) \ - f32_mulAdd$(OBJ) \ - f32_div$(OBJ) \ - f32_rem$(OBJ) \ - f32_sqrt$(OBJ) \ - f32_eq$(OBJ) \ - f32_le$(OBJ) \ - f32_lt$(OBJ) \ - f32_eq_signaling$(OBJ) \ - f32_le_quiet$(OBJ) \ - f32_lt_quiet$(OBJ) \ - f32_isSignalingNaN$(OBJ) \ - f64_to_ui32$(OBJ) \ - f64_to_ui64$(OBJ) \ - f64_to_i32$(OBJ) \ - f64_to_i64$(OBJ) \ - f64_to_ui32_r_minMag$(OBJ) \ - f64_to_ui64_r_minMag$(OBJ) \ - f64_to_i32_r_minMag$(OBJ) \ - f64_to_i64_r_minMag$(OBJ) \ - f64_to_f16$(OBJ) \ - f64_to_f32$(OBJ) \ - f64_to_extF80M$(OBJ) \ - f64_to_f128M$(OBJ) \ - f64_roundToInt$(OBJ) \ - f64_add$(OBJ) \ - f64_sub$(OBJ) \ - f64_mul$(OBJ) \ - f64_mulAdd$(OBJ) \ - f64_div$(OBJ) \ - f64_rem$(OBJ) \ - f64_sqrt$(OBJ) \ - f64_eq$(OBJ) \ - f64_le$(OBJ) \ - f64_lt$(OBJ) \ - f64_eq_signaling$(OBJ) \ - f64_le_quiet$(OBJ) \ - f64_lt_quiet$(OBJ) \ - f64_isSignalingNaN$(OBJ) \ - extF80M_to_ui32$(OBJ) \ - extF80M_to_ui64$(OBJ) \ - extF80M_to_i32$(OBJ) \ - extF80M_to_i64$(OBJ) \ - extF80M_to_ui32_r_minMag$(OBJ) \ - extF80M_to_ui64_r_minMag$(OBJ) \ - extF80M_to_i32_r_minMag$(OBJ) \ - extF80M_to_i64_r_minMag$(OBJ) \ - extF80M_to_f16$(OBJ) \ - extF80M_to_f32$(OBJ) \ - extF80M_to_f64$(OBJ) \ - extF80M_to_f128M$(OBJ) \ - extF80M_roundToInt$(OBJ) \ - extF80M_add$(OBJ) \ - extF80M_sub$(OBJ) \ - extF80M_mul$(OBJ) \ - extF80M_div$(OBJ) \ - extF80M_rem$(OBJ) \ - extF80M_sqrt$(OBJ) \ - extF80M_eq$(OBJ) \ - extF80M_le$(OBJ) \ - extF80M_lt$(OBJ) \ - extF80M_eq_signaling$(OBJ) \ - extF80M_le_quiet$(OBJ) \ - extF80M_lt_quiet$(OBJ) \ - f128M_to_ui32$(OBJ) \ - f128M_to_ui64$(OBJ) \ - f128M_to_i32$(OBJ) \ - f128M_to_i64$(OBJ) \ - f128M_to_ui32_r_minMag$(OBJ) \ - f128M_to_ui64_r_minMag$(OBJ) \ - f128M_to_i32_r_minMag$(OBJ) \ - f128M_to_i64_r_minMag$(OBJ) \ - f128M_to_f16$(OBJ) \ - f128M_to_f32$(OBJ) \ - f128M_to_f64$(OBJ) \ - f128M_to_extF80M$(OBJ) \ - f128M_roundToInt$(OBJ) \ - f128M_add$(OBJ) \ - f128M_sub$(OBJ) \ - f128M_mul$(OBJ) \ - f128M_mulAdd$(OBJ) \ - f128M_div$(OBJ) \ - f128M_rem$(OBJ) \ - f128M_sqrt$(OBJ) \ - f128M_eq$(OBJ) \ - f128M_le$(OBJ) \ - f128M_lt$(OBJ) \ - f128M_eq_signaling$(OBJ) \ - f128M_le_quiet$(OBJ) \ - f128M_lt_quiet$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) - -$(OBJS_ALL): \ - $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ - $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ - $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ - $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ - $(SOURCE_DIR)/include/softfloat.h - -$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$*.c - -$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c - -softfloat$(LIB): $(OBJS_ALL) - $(DELETE) $@ - $(MAKELIB) $^ - -.PHONY: clean -clean: - $(DELETE) $(OBJS_ALL) softfloat$(LIB) - diff --git a/softfloat/build/Linux-386-SSE2-GCC/platform.h b/softfloat/build/Linux-386-SSE2-GCC/platform.h deleted file mode 100644 index 420aa4e..0000000 --- a/softfloat/build/Linux-386-SSE2-GCC/platform.h +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define LITTLEENDIAN 1 - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#ifdef __GNUC_STDC_INLINE__ -#define INLINE inline -#else -#define INLINE extern inline -#endif - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define SOFTFLOAT_BUILTIN_CLZ 1 -#include "opts-GCC.h" - diff --git a/softfloat/build/Linux-ARM-VFPv2-GCC/Makefile b/softfloat/build/Linux-ARM-VFPv2-GCC/Makefile deleted file mode 100644 index 2565fe5..0000000 --- a/softfloat/build/Linux-ARM-VFPv2-GCC/Makefile +++ /dev/null @@ -1,323 +0,0 @@ - -#============================================================================= -# -# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic -# Package, Release 3e, by John R. Hauser. -# -# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -# University of California. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions, and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions, and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the University nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#============================================================================= - -SOURCE_DIR ?= ../../source -SPECIALIZE_TYPE ?= ARM-VFPv2 - -SOFTFLOAT_OPTS ?= -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 - -DELETE = rm -f -C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include -COMPILE_C = \ - gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \ - $(C_INCLUDES) -O2 -o $@ -MAKELIB = ar crs $@ - -OBJ = .o -LIB = .a - -OTHER_HEADERS = - -.PHONY: all -all: softfloat$(LIB) - -OBJS_PRIMITIVES = \ - s_compare96M$(OBJ) \ - s_compare128M$(OBJ) \ - s_shortShiftLeft64To96M$(OBJ) \ - s_shortShiftLeftM$(OBJ) \ - s_shiftLeftM$(OBJ) \ - s_shortShiftRightM$(OBJ) \ - s_shortShiftRightJam64$(OBJ) \ - s_shortShiftRightJamM$(OBJ) \ - s_shiftRightJam32$(OBJ) \ - s_shiftRightJam64$(OBJ) \ - s_shiftRightJamM$(OBJ) \ - s_shiftRightM$(OBJ) \ - s_countLeadingZeros8$(OBJ) \ - s_countLeadingZeros16$(OBJ) \ - s_countLeadingZeros32$(OBJ) \ - s_countLeadingZeros64$(OBJ) \ - s_addM$(OBJ) \ - s_addCarryM$(OBJ) \ - s_addComplCarryM$(OBJ) \ - s_negXM$(OBJ) \ - s_sub1XM$(OBJ) \ - s_subM$(OBJ) \ - s_mul64To128M$(OBJ) \ - s_mul128MTo256M$(OBJ) \ - s_approxRecip_1Ks$(OBJ) \ - s_approxRecip32_1$(OBJ) \ - s_approxRecipSqrt_1Ks$(OBJ) \ - s_approxRecipSqrt32_1$(OBJ) \ - s_remStepMBy32$(OBJ) \ - -OBJS_SPECIALIZE = \ - softfloat_raiseFlags$(OBJ) \ - s_f16UIToCommonNaN$(OBJ) \ - s_commonNaNToF16UI$(OBJ) \ - s_propagateNaNF16UI$(OBJ) \ - s_f32UIToCommonNaN$(OBJ) \ - s_commonNaNToF32UI$(OBJ) \ - s_propagateNaNF32UI$(OBJ) \ - s_f64UIToCommonNaN$(OBJ) \ - s_commonNaNToF64UI$(OBJ) \ - s_propagateNaNF64UI$(OBJ) \ - extF80M_isSignalingNaN$(OBJ) \ - s_extF80MToCommonNaN$(OBJ) \ - s_commonNaNToExtF80M$(OBJ) \ - s_propagateNaNExtF80M$(OBJ) \ - f128M_isSignalingNaN$(OBJ) \ - s_f128MToCommonNaN$(OBJ) \ - s_commonNaNToF128M$(OBJ) \ - s_propagateNaNF128M$(OBJ) \ - -OBJS_OTHERS = \ - s_roundToUI32$(OBJ) \ - s_roundMToUI64$(OBJ) \ - s_roundToI32$(OBJ) \ - s_roundMToI64$(OBJ) \ - s_normSubnormalF16Sig$(OBJ) \ - s_roundPackToF16$(OBJ) \ - s_normRoundPackToF16$(OBJ) \ - s_addMagsF16$(OBJ) \ - s_subMagsF16$(OBJ) \ - s_mulAddF16$(OBJ) \ - s_normSubnormalF32Sig$(OBJ) \ - s_roundPackToF32$(OBJ) \ - s_normRoundPackToF32$(OBJ) \ - s_addMagsF32$(OBJ) \ - s_subMagsF32$(OBJ) \ - s_mulAddF32$(OBJ) \ - s_normSubnormalF64Sig$(OBJ) \ - s_roundPackToF64$(OBJ) \ - s_normRoundPackToF64$(OBJ) \ - s_addMagsF64$(OBJ) \ - s_subMagsF64$(OBJ) \ - s_mulAddF64$(OBJ) \ - s_tryPropagateNaNExtF80M$(OBJ) \ - s_invalidExtF80M$(OBJ) \ - s_normExtF80SigM$(OBJ) \ - s_roundPackMToExtF80M$(OBJ) \ - s_normRoundPackMToExtF80M$(OBJ) \ - s_addExtF80M$(OBJ) \ - s_compareNonnormExtF80M$(OBJ) \ - s_isNaNF128M$(OBJ) \ - s_tryPropagateNaNF128M$(OBJ) \ - s_invalidF128M$(OBJ) \ - s_shiftNormSigF128M$(OBJ) \ - s_roundPackMToF128M$(OBJ) \ - s_normRoundPackMToF128M$(OBJ) \ - s_addF128M$(OBJ) \ - s_mulAddF128M$(OBJ) \ - softfloat_state$(OBJ) \ - ui32_to_f16$(OBJ) \ - ui32_to_f32$(OBJ) \ - ui32_to_f64$(OBJ) \ - ui32_to_extF80M$(OBJ) \ - ui32_to_f128M$(OBJ) \ - ui64_to_f16$(OBJ) \ - ui64_to_f32$(OBJ) \ - ui64_to_f64$(OBJ) \ - ui64_to_extF80M$(OBJ) \ - ui64_to_f128M$(OBJ) \ - i32_to_f16$(OBJ) \ - i32_to_f32$(OBJ) \ - i32_to_f64$(OBJ) \ - i32_to_extF80M$(OBJ) \ - i32_to_f128M$(OBJ) \ - i64_to_f16$(OBJ) \ - i64_to_f32$(OBJ) \ - i64_to_f64$(OBJ) \ - i64_to_extF80M$(OBJ) \ - i64_to_f128M$(OBJ) \ - f16_to_ui32$(OBJ) \ - f16_to_ui64$(OBJ) \ - f16_to_i32$(OBJ) \ - f16_to_i64$(OBJ) \ - f16_to_ui32_r_minMag$(OBJ) \ - f16_to_ui64_r_minMag$(OBJ) \ - f16_to_i32_r_minMag$(OBJ) \ - f16_to_i64_r_minMag$(OBJ) \ - f16_to_f32$(OBJ) \ - f16_to_f64$(OBJ) \ - f16_to_extF80M$(OBJ) \ - f16_to_f128M$(OBJ) \ - f16_roundToInt$(OBJ) \ - f16_add$(OBJ) \ - f16_sub$(OBJ) \ - f16_mul$(OBJ) \ - f16_mulAdd$(OBJ) \ - f16_div$(OBJ) \ - f16_rem$(OBJ) \ - f16_sqrt$(OBJ) \ - f16_eq$(OBJ) \ - f16_le$(OBJ) \ - f16_lt$(OBJ) \ - f16_eq_signaling$(OBJ) \ - f16_le_quiet$(OBJ) \ - f16_lt_quiet$(OBJ) \ - f16_isSignalingNaN$(OBJ) \ - f32_to_ui32$(OBJ) \ - f32_to_ui64$(OBJ) \ - f32_to_i32$(OBJ) \ - f32_to_i64$(OBJ) \ - f32_to_ui32_r_minMag$(OBJ) \ - f32_to_ui64_r_minMag$(OBJ) \ - f32_to_i32_r_minMag$(OBJ) \ - f32_to_i64_r_minMag$(OBJ) \ - f32_to_f16$(OBJ) \ - f32_to_f64$(OBJ) \ - f32_to_extF80M$(OBJ) \ - f32_to_f128M$(OBJ) \ - f32_roundToInt$(OBJ) \ - f32_add$(OBJ) \ - f32_sub$(OBJ) \ - f32_mul$(OBJ) \ - f32_mulAdd$(OBJ) \ - f32_div$(OBJ) \ - f32_rem$(OBJ) \ - f32_sqrt$(OBJ) \ - f32_eq$(OBJ) \ - f32_le$(OBJ) \ - f32_lt$(OBJ) \ - f32_eq_signaling$(OBJ) \ - f32_le_quiet$(OBJ) \ - f32_lt_quiet$(OBJ) \ - f32_isSignalingNaN$(OBJ) \ - f64_to_ui32$(OBJ) \ - f64_to_ui64$(OBJ) \ - f64_to_i32$(OBJ) \ - f64_to_i64$(OBJ) \ - f64_to_ui32_r_minMag$(OBJ) \ - f64_to_ui64_r_minMag$(OBJ) \ - f64_to_i32_r_minMag$(OBJ) \ - f64_to_i64_r_minMag$(OBJ) \ - f64_to_f16$(OBJ) \ - f64_to_f32$(OBJ) \ - f64_to_extF80M$(OBJ) \ - f64_to_f128M$(OBJ) \ - f64_roundToInt$(OBJ) \ - f64_add$(OBJ) \ - f64_sub$(OBJ) \ - f64_mul$(OBJ) \ - f64_mulAdd$(OBJ) \ - f64_div$(OBJ) \ - f64_rem$(OBJ) \ - f64_sqrt$(OBJ) \ - f64_eq$(OBJ) \ - f64_le$(OBJ) \ - f64_lt$(OBJ) \ - f64_eq_signaling$(OBJ) \ - f64_le_quiet$(OBJ) \ - f64_lt_quiet$(OBJ) \ - f64_isSignalingNaN$(OBJ) \ - extF80M_to_ui32$(OBJ) \ - extF80M_to_ui64$(OBJ) \ - extF80M_to_i32$(OBJ) \ - extF80M_to_i64$(OBJ) \ - extF80M_to_ui32_r_minMag$(OBJ) \ - extF80M_to_ui64_r_minMag$(OBJ) \ - extF80M_to_i32_r_minMag$(OBJ) \ - extF80M_to_i64_r_minMag$(OBJ) \ - extF80M_to_f16$(OBJ) \ - extF80M_to_f32$(OBJ) \ - extF80M_to_f64$(OBJ) \ - extF80M_to_f128M$(OBJ) \ - extF80M_roundToInt$(OBJ) \ - extF80M_add$(OBJ) \ - extF80M_sub$(OBJ) \ - extF80M_mul$(OBJ) \ - extF80M_div$(OBJ) \ - extF80M_rem$(OBJ) \ - extF80M_sqrt$(OBJ) \ - extF80M_eq$(OBJ) \ - extF80M_le$(OBJ) \ - extF80M_lt$(OBJ) \ - extF80M_eq_signaling$(OBJ) \ - extF80M_le_quiet$(OBJ) \ - extF80M_lt_quiet$(OBJ) \ - f128M_to_ui32$(OBJ) \ - f128M_to_ui64$(OBJ) \ - f128M_to_i32$(OBJ) \ - f128M_to_i64$(OBJ) \ - f128M_to_ui32_r_minMag$(OBJ) \ - f128M_to_ui64_r_minMag$(OBJ) \ - f128M_to_i32_r_minMag$(OBJ) \ - f128M_to_i64_r_minMag$(OBJ) \ - f128M_to_f16$(OBJ) \ - f128M_to_f32$(OBJ) \ - f128M_to_f64$(OBJ) \ - f128M_to_extF80M$(OBJ) \ - f128M_roundToInt$(OBJ) \ - f128M_add$(OBJ) \ - f128M_sub$(OBJ) \ - f128M_mul$(OBJ) \ - f128M_mulAdd$(OBJ) \ - f128M_div$(OBJ) \ - f128M_rem$(OBJ) \ - f128M_sqrt$(OBJ) \ - f128M_eq$(OBJ) \ - f128M_le$(OBJ) \ - f128M_lt$(OBJ) \ - f128M_eq_signaling$(OBJ) \ - f128M_le_quiet$(OBJ) \ - f128M_lt_quiet$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) - -$(OBJS_ALL): \ - $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ - $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ - $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ - $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ - $(SOURCE_DIR)/include/softfloat.h - -$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$*.c - -$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c - -softfloat$(LIB): $(OBJS_ALL) - $(DELETE) $@ - $(MAKELIB) $^ - -.PHONY: clean -clean: - $(DELETE) $(OBJS_ALL) softfloat$(LIB) - diff --git a/softfloat/build/Linux-ARM-VFPv2-GCC/platform.h b/softfloat/build/Linux-ARM-VFPv2-GCC/platform.h deleted file mode 100644 index 420aa4e..0000000 --- a/softfloat/build/Linux-ARM-VFPv2-GCC/platform.h +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define LITTLEENDIAN 1 - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#ifdef __GNUC_STDC_INLINE__ -#define INLINE inline -#else -#define INLINE extern inline -#endif - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define SOFTFLOAT_BUILTIN_CLZ 1 -#include "opts-GCC.h" - diff --git a/softfloat/build/Linux-RISCV64-GCC/Makefile b/softfloat/build/Linux-RISCV64-GCC/Makefile deleted file mode 100644 index b9408c6..0000000 --- a/softfloat/build/Linux-RISCV64-GCC/Makefile +++ /dev/null @@ -1,399 +0,0 @@ - -#============================================================================= -# -# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic -# Package, Release 3e, by John R. Hauser. -# -# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -# University of California. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions, and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions, and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the University nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#============================================================================= - -SOURCE_DIR ?= ../../source -SPECIALIZE_TYPE ?= RISCV -MARCH ?= rv64gcv_zfh_zfhmin -MABI ?= lp64d - -SOFTFLOAT_OPTS ?= \ - -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \ - -DSOFTFLOAT_FAST_DIV64TO32 - -DELETE = rm -f -C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include -COMPILE_C = \ - riscv64-unknown-linux-gnu-gcc -c -march=$(MARCH) -mabi=$(MABI) -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \ - $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@ -MAKELIB = ar crs $@ - -OBJ = .o -LIB = .a - -OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h - -.PHONY: all -all: softfloat$(LIB) - -OBJS_PRIMITIVES = \ - s_eq128$(OBJ) \ - s_le128$(OBJ) \ - s_lt128$(OBJ) \ - s_shortShiftLeft128$(OBJ) \ - s_shortShiftRight128$(OBJ) \ - s_shortShiftRightJam64$(OBJ) \ - s_shortShiftRightJam64Extra$(OBJ) \ - s_shortShiftRightJam128$(OBJ) \ - s_shortShiftRightJam128Extra$(OBJ) \ - s_shiftRightJam32$(OBJ) \ - s_shiftRightJam64$(OBJ) \ - s_shiftRightJam64Extra$(OBJ) \ - s_shiftRightJam128$(OBJ) \ - s_shiftRightJam128Extra$(OBJ) \ - s_shiftRightJam256M$(OBJ) \ - s_countLeadingZeros8$(OBJ) \ - s_countLeadingZeros16$(OBJ) \ - s_countLeadingZeros32$(OBJ) \ - s_countLeadingZeros64$(OBJ) \ - s_add128$(OBJ) \ - s_add256M$(OBJ) \ - s_sub128$(OBJ) \ - s_sub256M$(OBJ) \ - s_mul64ByShifted32To128$(OBJ) \ - s_mul64To128$(OBJ) \ - s_mul128By32$(OBJ) \ - s_mul128To256M$(OBJ) \ - s_approxRecip_1Ks$(OBJ) \ - s_approxRecip32_1$(OBJ) \ - s_approxRecipSqrt_1Ks$(OBJ) \ - s_approxRecipSqrt32_1$(OBJ) \ - -OBJS_SPECIALIZE = \ - softfloat_raiseFlags$(OBJ) \ - s_f16UIToCommonNaN$(OBJ) \ - s_commonNaNToF16UI$(OBJ) \ - s_propagateNaNF16UI$(OBJ) \ - s_bf16UIToCommonNaN$(OBJ) \ - s_commonNaNToBF16UI$(OBJ) \ - s_f32UIToCommonNaN$(OBJ) \ - s_commonNaNToF32UI$(OBJ) \ - s_propagateNaNF32UI$(OBJ) \ - s_f64UIToCommonNaN$(OBJ) \ - s_commonNaNToF64UI$(OBJ) \ - s_propagateNaNF64UI$(OBJ) \ - extF80M_isSignalingNaN$(OBJ) \ - s_extF80UIToCommonNaN$(OBJ) \ - s_commonNaNToExtF80UI$(OBJ) \ - s_propagateNaNExtF80UI$(OBJ) \ - f128M_isSignalingNaN$(OBJ) \ - s_f128UIToCommonNaN$(OBJ) \ - s_commonNaNToF128UI$(OBJ) \ - s_propagateNaNF128UI$(OBJ) \ - -OBJS_OTHERS = \ - s_roundToUI32$(OBJ) \ - s_roundToUI64$(OBJ) \ - s_roundToI32$(OBJ) \ - s_roundToI64$(OBJ) \ - s_normSubnormalBF16Sig$(OBJ) \ - s_roundPackToBF16$(OBJ) \ - s_normSubnormalF16Sig$(OBJ) \ - s_roundPackToF16$(OBJ) \ - s_normRoundPackToF16$(OBJ) \ - s_addMagsF16$(OBJ) \ - s_subMagsF16$(OBJ) \ - s_mulAddF16$(OBJ) \ - s_normSubnormalF32Sig$(OBJ) \ - s_roundPackToF32$(OBJ) \ - s_normRoundPackToF32$(OBJ) \ - s_addMagsF32$(OBJ) \ - s_subMagsF32$(OBJ) \ - s_mulAddF32$(OBJ) \ - s_normSubnormalF64Sig$(OBJ) \ - s_roundPackToF64$(OBJ) \ - s_normRoundPackToF64$(OBJ) \ - s_addMagsF64$(OBJ) \ - s_subMagsF64$(OBJ) \ - s_mulAddF64$(OBJ) \ - s_normSubnormalExtF80Sig$(OBJ) \ - s_roundPackToExtF80$(OBJ) \ - s_normRoundPackToExtF80$(OBJ) \ - s_addMagsExtF80$(OBJ) \ - s_subMagsExtF80$(OBJ) \ - s_normSubnormalF128Sig$(OBJ) \ - s_roundPackToF128$(OBJ) \ - s_normRoundPackToF128$(OBJ) \ - s_addMagsF128$(OBJ) \ - s_subMagsF128$(OBJ) \ - s_mulAddF128$(OBJ) \ - softfloat_state$(OBJ) \ - ui32_to_f16$(OBJ) \ - ui32_to_f32$(OBJ) \ - ui32_to_f64$(OBJ) \ - ui32_to_extF80$(OBJ) \ - ui32_to_extF80M$(OBJ) \ - ui32_to_f128$(OBJ) \ - ui32_to_f128M$(OBJ) \ - ui64_to_f16$(OBJ) \ - ui64_to_f32$(OBJ) \ - ui64_to_f64$(OBJ) \ - ui64_to_extF80$(OBJ) \ - ui64_to_extF80M$(OBJ) \ - ui64_to_f128$(OBJ) \ - ui64_to_f128M$(OBJ) \ - i32_to_f16$(OBJ) \ - i32_to_f32$(OBJ) \ - i32_to_f64$(OBJ) \ - i32_to_extF80$(OBJ) \ - i32_to_extF80M$(OBJ) \ - i32_to_f128$(OBJ) \ - i32_to_f128M$(OBJ) \ - i64_to_f16$(OBJ) \ - i64_to_f32$(OBJ) \ - i64_to_f64$(OBJ) \ - i64_to_extF80$(OBJ) \ - i64_to_extF80M$(OBJ) \ - i64_to_f128$(OBJ) \ - i64_to_f128M$(OBJ) \ - bf16_isSignalingNaN$(OBJ) \ - bf16_to_f32$(OBJ) \ - f16_to_ui32$(OBJ) \ - f16_to_ui64$(OBJ) \ - f16_to_i32$(OBJ) \ - f16_to_i64$(OBJ) \ - f16_to_ui32_r_minMag$(OBJ) \ - f16_to_ui64_r_minMag$(OBJ) \ - f16_to_i32_r_minMag$(OBJ) \ - f16_to_i64_r_minMag$(OBJ) \ - f16_to_f32$(OBJ) \ - f16_to_f64$(OBJ) \ - f16_to_extF80$(OBJ) \ - f16_to_extF80M$(OBJ) \ - f16_to_f128$(OBJ) \ - f16_to_f128M$(OBJ) \ - f16_roundToInt$(OBJ) \ - f16_add$(OBJ) \ - f16_sub$(OBJ) \ - f16_mul$(OBJ) \ - f16_mulAdd$(OBJ) \ - f16_div$(OBJ) \ - f16_rem$(OBJ) \ - f16_sqrt$(OBJ) \ - f16_eq$(OBJ) \ - f16_le$(OBJ) \ - f16_lt$(OBJ) \ - f16_eq_signaling$(OBJ) \ - f16_le_quiet$(OBJ) \ - f16_lt_quiet$(OBJ) \ - f16_isSignalingNaN$(OBJ) \ - f32_to_ui32$(OBJ) \ - f32_to_ui64$(OBJ) \ - f32_to_i32$(OBJ) \ - f32_to_i64$(OBJ) \ - f32_to_ui32_r_minMag$(OBJ) \ - f32_to_ui64_r_minMag$(OBJ) \ - f32_to_i32_r_minMag$(OBJ) \ - f32_to_i64_r_minMag$(OBJ) \ - f32_to_bf16$(OBJ) \ - f32_to_f16$(OBJ) \ - f32_to_f64$(OBJ) \ - f32_to_extF80$(OBJ) \ - f32_to_extF80M$(OBJ) \ - f32_to_f128$(OBJ) \ - f32_to_f128M$(OBJ) \ - f32_roundToInt$(OBJ) \ - f32_add$(OBJ) \ - f32_sub$(OBJ) \ - f32_mul$(OBJ) \ - f32_mulAdd$(OBJ) \ - f32_div$(OBJ) \ - f32_rem$(OBJ) \ - f32_sqrt$(OBJ) \ - f32_eq$(OBJ) \ - f32_le$(OBJ) \ - f32_lt$(OBJ) \ - f32_eq_signaling$(OBJ) \ - f32_le_quiet$(OBJ) \ - f32_lt_quiet$(OBJ) \ - f32_isSignalingNaN$(OBJ) \ - f64_to_ui32$(OBJ) \ - f64_to_ui64$(OBJ) \ - f64_to_i32$(OBJ) \ - f64_to_i64$(OBJ) \ - f64_to_ui32_r_minMag$(OBJ) \ - f64_to_ui64_r_minMag$(OBJ) \ - f64_to_i32_r_minMag$(OBJ) \ - f64_to_i64_r_minMag$(OBJ) \ - f64_to_f16$(OBJ) \ - f64_to_f32$(OBJ) \ - f64_to_extF80$(OBJ) \ - f64_to_extF80M$(OBJ) \ - f64_to_f128$(OBJ) \ - f64_to_f128M$(OBJ) \ - f64_roundToInt$(OBJ) \ - f64_add$(OBJ) \ - f64_sub$(OBJ) \ - f64_mul$(OBJ) \ - f64_mulAdd$(OBJ) \ - f64_div$(OBJ) \ - f64_rem$(OBJ) \ - f64_sqrt$(OBJ) \ - f64_eq$(OBJ) \ - f64_le$(OBJ) \ - f64_lt$(OBJ) \ - f64_eq_signaling$(OBJ) \ - f64_le_quiet$(OBJ) \ - f64_lt_quiet$(OBJ) \ - f64_isSignalingNaN$(OBJ) \ - extF80_to_ui32$(OBJ) \ - extF80_to_ui64$(OBJ) \ - extF80_to_i32$(OBJ) \ - extF80_to_i64$(OBJ) \ - extF80_to_ui32_r_minMag$(OBJ) \ - extF80_to_ui64_r_minMag$(OBJ) \ - extF80_to_i32_r_minMag$(OBJ) \ - extF80_to_i64_r_minMag$(OBJ) \ - extF80_to_f16$(OBJ) \ - extF80_to_f32$(OBJ) \ - extF80_to_f64$(OBJ) \ - extF80_to_f128$(OBJ) \ - extF80_roundToInt$(OBJ) \ - extF80_add$(OBJ) \ - extF80_sub$(OBJ) \ - extF80_mul$(OBJ) \ - extF80_div$(OBJ) \ - extF80_rem$(OBJ) \ - extF80_sqrt$(OBJ) \ - extF80_eq$(OBJ) \ - extF80_le$(OBJ) \ - extF80_lt$(OBJ) \ - extF80_eq_signaling$(OBJ) \ - extF80_le_quiet$(OBJ) \ - extF80_lt_quiet$(OBJ) \ - extF80_isSignalingNaN$(OBJ) \ - extF80M_to_ui32$(OBJ) \ - extF80M_to_ui64$(OBJ) \ - extF80M_to_i32$(OBJ) \ - extF80M_to_i64$(OBJ) \ - extF80M_to_ui32_r_minMag$(OBJ) \ - extF80M_to_ui64_r_minMag$(OBJ) \ - extF80M_to_i32_r_minMag$(OBJ) \ - extF80M_to_i64_r_minMag$(OBJ) \ - extF80M_to_f16$(OBJ) \ - extF80M_to_f32$(OBJ) \ - extF80M_to_f64$(OBJ) \ - extF80M_to_f128M$(OBJ) \ - extF80M_roundToInt$(OBJ) \ - extF80M_add$(OBJ) \ - extF80M_sub$(OBJ) \ - extF80M_mul$(OBJ) \ - extF80M_div$(OBJ) \ - extF80M_rem$(OBJ) \ - extF80M_sqrt$(OBJ) \ - extF80M_eq$(OBJ) \ - extF80M_le$(OBJ) \ - extF80M_lt$(OBJ) \ - extF80M_eq_signaling$(OBJ) \ - extF80M_le_quiet$(OBJ) \ - extF80M_lt_quiet$(OBJ) \ - f128_to_ui32$(OBJ) \ - f128_to_ui64$(OBJ) \ - f128_to_i32$(OBJ) \ - f128_to_i64$(OBJ) \ - f128_to_ui32_r_minMag$(OBJ) \ - f128_to_ui64_r_minMag$(OBJ) \ - f128_to_i32_r_minMag$(OBJ) \ - f128_to_i64_r_minMag$(OBJ) \ - f128_to_f16$(OBJ) \ - f128_to_f32$(OBJ) \ - f128_to_extF80$(OBJ) \ - f128_to_f64$(OBJ) \ - f128_roundToInt$(OBJ) \ - f128_add$(OBJ) \ - f128_sub$(OBJ) \ - f128_mul$(OBJ) \ - f128_mulAdd$(OBJ) \ - f128_div$(OBJ) \ - f128_rem$(OBJ) \ - f128_sqrt$(OBJ) \ - f128_eq$(OBJ) \ - f128_le$(OBJ) \ - f128_lt$(OBJ) \ - f128_eq_signaling$(OBJ) \ - f128_le_quiet$(OBJ) \ - f128_lt_quiet$(OBJ) \ - f128_isSignalingNaN$(OBJ) \ - f128M_to_ui32$(OBJ) \ - f128M_to_ui64$(OBJ) \ - f128M_to_i32$(OBJ) \ - f128M_to_i64$(OBJ) \ - f128M_to_ui32_r_minMag$(OBJ) \ - f128M_to_ui64_r_minMag$(OBJ) \ - f128M_to_i32_r_minMag$(OBJ) \ - f128M_to_i64_r_minMag$(OBJ) \ - f128M_to_f16$(OBJ) \ - f128M_to_f32$(OBJ) \ - f128M_to_extF80M$(OBJ) \ - f128M_to_f64$(OBJ) \ - f128M_roundToInt$(OBJ) \ - f128M_add$(OBJ) \ - f128M_sub$(OBJ) \ - f128M_mul$(OBJ) \ - f128M_mulAdd$(OBJ) \ - f128M_div$(OBJ) \ - f128M_rem$(OBJ) \ - f128M_sqrt$(OBJ) \ - f128M_eq$(OBJ) \ - f128M_le$(OBJ) \ - f128M_lt$(OBJ) \ - f128M_eq_signaling$(OBJ) \ - f128M_le_quiet$(OBJ) \ - f128M_lt_quiet$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) - -$(OBJS_ALL): \ - $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ - $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ - $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ - $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ - $(SOURCE_DIR)/include/softfloat.h - -$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$*.c - -$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c - -softfloat$(LIB): $(OBJS_ALL) - $(DELETE) $@ - $(MAKELIB) $^ - -.PHONY: clean -clean: - $(DELETE) $(OBJS_ALL) softfloat$(LIB) - diff --git a/softfloat/build/Linux-RISCV64-GCC/platform.h b/softfloat/build/Linux-RISCV64-GCC/platform.h deleted file mode 100644 index c5e06f8..0000000 --- a/softfloat/build/Linux-RISCV64-GCC/platform.h +++ /dev/null @@ -1,54 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define LITTLEENDIAN 1 - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#ifdef __GNUC_STDC_INLINE__ -#define INLINE inline -#else -#define INLINE extern inline -#endif - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define SOFTFLOAT_BUILTIN_CLZ 1 -#define SOFTFLOAT_INTRINSIC_INT128 1 -#include "opts-GCC.h" - diff --git a/softfloat/build/Linux-x86_64-GCC/Makefile b/softfloat/build/Linux-x86_64-GCC/Makefile deleted file mode 100644 index 72f251a..0000000 --- a/softfloat/build/Linux-x86_64-GCC/Makefile +++ /dev/null @@ -1,397 +0,0 @@ - -#============================================================================= -# -# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic -# Package, Release 3e, by John R. Hauser. -# -# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -# University of California. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions, and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions, and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the University nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#============================================================================= - -SOURCE_DIR ?= ../../source -SPECIALIZE_TYPE ?= 8086-SSE - -SOFTFLOAT_OPTS ?= \ - -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \ - -DSOFTFLOAT_FAST_DIV64TO32 - -DELETE = rm -f -C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include -COMPILE_C = \ - gcc -c -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \ - $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@ -MAKELIB = ar crs $@ - -OBJ = .o -LIB = .a - -OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h - -.PHONY: all -all: softfloat$(LIB) - -OBJS_PRIMITIVES = \ - s_eq128$(OBJ) \ - s_le128$(OBJ) \ - s_lt128$(OBJ) \ - s_shortShiftLeft128$(OBJ) \ - s_shortShiftRight128$(OBJ) \ - s_shortShiftRightJam64$(OBJ) \ - s_shortShiftRightJam64Extra$(OBJ) \ - s_shortShiftRightJam128$(OBJ) \ - s_shortShiftRightJam128Extra$(OBJ) \ - s_shiftRightJam32$(OBJ) \ - s_shiftRightJam64$(OBJ) \ - s_shiftRightJam64Extra$(OBJ) \ - s_shiftRightJam128$(OBJ) \ - s_shiftRightJam128Extra$(OBJ) \ - s_shiftRightJam256M$(OBJ) \ - s_countLeadingZeros8$(OBJ) \ - s_countLeadingZeros16$(OBJ) \ - s_countLeadingZeros32$(OBJ) \ - s_countLeadingZeros64$(OBJ) \ - s_add128$(OBJ) \ - s_add256M$(OBJ) \ - s_sub128$(OBJ) \ - s_sub256M$(OBJ) \ - s_mul64ByShifted32To128$(OBJ) \ - s_mul64To128$(OBJ) \ - s_mul128By32$(OBJ) \ - s_mul128To256M$(OBJ) \ - s_approxRecip_1Ks$(OBJ) \ - s_approxRecip32_1$(OBJ) \ - s_approxRecipSqrt_1Ks$(OBJ) \ - s_approxRecipSqrt32_1$(OBJ) \ - -OBJS_SPECIALIZE = \ - softfloat_raiseFlags$(OBJ) \ - s_f16UIToCommonNaN$(OBJ) \ - s_commonNaNToF16UI$(OBJ) \ - s_propagateNaNF16UI$(OBJ) \ - s_bf16UIToCommonNaN$(OBJ) \ - s_commonNaNToBF16UI$(OBJ) \ - s_f32UIToCommonNaN$(OBJ) \ - s_commonNaNToF32UI$(OBJ) \ - s_propagateNaNF32UI$(OBJ) \ - s_f64UIToCommonNaN$(OBJ) \ - s_commonNaNToF64UI$(OBJ) \ - s_propagateNaNF64UI$(OBJ) \ - extF80M_isSignalingNaN$(OBJ) \ - s_extF80UIToCommonNaN$(OBJ) \ - s_commonNaNToExtF80UI$(OBJ) \ - s_propagateNaNExtF80UI$(OBJ) \ - f128M_isSignalingNaN$(OBJ) \ - s_f128UIToCommonNaN$(OBJ) \ - s_commonNaNToF128UI$(OBJ) \ - s_propagateNaNF128UI$(OBJ) \ - -OBJS_OTHERS = \ - s_roundToUI32$(OBJ) \ - s_roundToUI64$(OBJ) \ - s_roundToI32$(OBJ) \ - s_roundToI64$(OBJ) \ - s_normSubnormalBF16Sig$(OBJ) \ - s_roundPackToBF16$(OBJ) \ - s_normSubnormalF16Sig$(OBJ) \ - s_roundPackToF16$(OBJ) \ - s_normRoundPackToF16$(OBJ) \ - s_addMagsF16$(OBJ) \ - s_subMagsF16$(OBJ) \ - s_mulAddF16$(OBJ) \ - s_normSubnormalF32Sig$(OBJ) \ - s_roundPackToF32$(OBJ) \ - s_normRoundPackToF32$(OBJ) \ - s_addMagsF32$(OBJ) \ - s_subMagsF32$(OBJ) \ - s_mulAddF32$(OBJ) \ - s_normSubnormalF64Sig$(OBJ) \ - s_roundPackToF64$(OBJ) \ - s_normRoundPackToF64$(OBJ) \ - s_addMagsF64$(OBJ) \ - s_subMagsF64$(OBJ) \ - s_mulAddF64$(OBJ) \ - s_normSubnormalExtF80Sig$(OBJ) \ - s_roundPackToExtF80$(OBJ) \ - s_normRoundPackToExtF80$(OBJ) \ - s_addMagsExtF80$(OBJ) \ - s_subMagsExtF80$(OBJ) \ - s_normSubnormalF128Sig$(OBJ) \ - s_roundPackToF128$(OBJ) \ - s_normRoundPackToF128$(OBJ) \ - s_addMagsF128$(OBJ) \ - s_subMagsF128$(OBJ) \ - s_mulAddF128$(OBJ) \ - softfloat_state$(OBJ) \ - ui32_to_f16$(OBJ) \ - ui32_to_f32$(OBJ) \ - ui32_to_f64$(OBJ) \ - ui32_to_extF80$(OBJ) \ - ui32_to_extF80M$(OBJ) \ - ui32_to_f128$(OBJ) \ - ui32_to_f128M$(OBJ) \ - ui64_to_f16$(OBJ) \ - ui64_to_f32$(OBJ) \ - ui64_to_f64$(OBJ) \ - ui64_to_extF80$(OBJ) \ - ui64_to_extF80M$(OBJ) \ - ui64_to_f128$(OBJ) \ - ui64_to_f128M$(OBJ) \ - i32_to_f16$(OBJ) \ - i32_to_f32$(OBJ) \ - i32_to_f64$(OBJ) \ - i32_to_extF80$(OBJ) \ - i32_to_extF80M$(OBJ) \ - i32_to_f128$(OBJ) \ - i32_to_f128M$(OBJ) \ - i64_to_f16$(OBJ) \ - i64_to_f32$(OBJ) \ - i64_to_f64$(OBJ) \ - i64_to_extF80$(OBJ) \ - i64_to_extF80M$(OBJ) \ - i64_to_f128$(OBJ) \ - i64_to_f128M$(OBJ) \ - bf16_isSignalingNaN$(OBJ) \ - bf16_to_f32$(OBJ) \ - f16_to_ui32$(OBJ) \ - f16_to_ui64$(OBJ) \ - f16_to_i32$(OBJ) \ - f16_to_i64$(OBJ) \ - f16_to_ui32_r_minMag$(OBJ) \ - f16_to_ui64_r_minMag$(OBJ) \ - f16_to_i32_r_minMag$(OBJ) \ - f16_to_i64_r_minMag$(OBJ) \ - f16_to_f32$(OBJ) \ - f16_to_f64$(OBJ) \ - f16_to_extF80$(OBJ) \ - f16_to_extF80M$(OBJ) \ - f16_to_f128$(OBJ) \ - f16_to_f128M$(OBJ) \ - f16_roundToInt$(OBJ) \ - f16_add$(OBJ) \ - f16_sub$(OBJ) \ - f16_mul$(OBJ) \ - f16_mulAdd$(OBJ) \ - f16_div$(OBJ) \ - f16_rem$(OBJ) \ - f16_sqrt$(OBJ) \ - f16_eq$(OBJ) \ - f16_le$(OBJ) \ - f16_lt$(OBJ) \ - f16_eq_signaling$(OBJ) \ - f16_le_quiet$(OBJ) \ - f16_lt_quiet$(OBJ) \ - f16_isSignalingNaN$(OBJ) \ - f32_to_ui32$(OBJ) \ - f32_to_ui64$(OBJ) \ - f32_to_i32$(OBJ) \ - f32_to_i64$(OBJ) \ - f32_to_ui32_r_minMag$(OBJ) \ - f32_to_ui64_r_minMag$(OBJ) \ - f32_to_i32_r_minMag$(OBJ) \ - f32_to_i64_r_minMag$(OBJ) \ - f32_to_bf16$(OBJ) \ - f32_to_f16$(OBJ) \ - f32_to_f64$(OBJ) \ - f32_to_extF80$(OBJ) \ - f32_to_extF80M$(OBJ) \ - f32_to_f128$(OBJ) \ - f32_to_f128M$(OBJ) \ - f32_roundToInt$(OBJ) \ - f32_add$(OBJ) \ - f32_sub$(OBJ) \ - f32_mul$(OBJ) \ - f32_mulAdd$(OBJ) \ - f32_div$(OBJ) \ - f32_rem$(OBJ) \ - f32_sqrt$(OBJ) \ - f32_eq$(OBJ) \ - f32_le$(OBJ) \ - f32_lt$(OBJ) \ - f32_eq_signaling$(OBJ) \ - f32_le_quiet$(OBJ) \ - f32_lt_quiet$(OBJ) \ - f32_isSignalingNaN$(OBJ) \ - f64_to_ui32$(OBJ) \ - f64_to_ui64$(OBJ) \ - f64_to_i32$(OBJ) \ - f64_to_i64$(OBJ) \ - f64_to_ui32_r_minMag$(OBJ) \ - f64_to_ui64_r_minMag$(OBJ) \ - f64_to_i32_r_minMag$(OBJ) \ - f64_to_i64_r_minMag$(OBJ) \ - f64_to_f16$(OBJ) \ - f64_to_f32$(OBJ) \ - f64_to_extF80$(OBJ) \ - f64_to_extF80M$(OBJ) \ - f64_to_f128$(OBJ) \ - f64_to_f128M$(OBJ) \ - f64_roundToInt$(OBJ) \ - f64_add$(OBJ) \ - f64_sub$(OBJ) \ - f64_mul$(OBJ) \ - f64_mulAdd$(OBJ) \ - f64_div$(OBJ) \ - f64_rem$(OBJ) \ - f64_sqrt$(OBJ) \ - f64_eq$(OBJ) \ - f64_le$(OBJ) \ - f64_lt$(OBJ) \ - f64_eq_signaling$(OBJ) \ - f64_le_quiet$(OBJ) \ - f64_lt_quiet$(OBJ) \ - f64_isSignalingNaN$(OBJ) \ - extF80_to_ui32$(OBJ) \ - extF80_to_ui64$(OBJ) \ - extF80_to_i32$(OBJ) \ - extF80_to_i64$(OBJ) \ - extF80_to_ui32_r_minMag$(OBJ) \ - extF80_to_ui64_r_minMag$(OBJ) \ - extF80_to_i32_r_minMag$(OBJ) \ - extF80_to_i64_r_minMag$(OBJ) \ - extF80_to_f16$(OBJ) \ - extF80_to_f32$(OBJ) \ - extF80_to_f64$(OBJ) \ - extF80_to_f128$(OBJ) \ - extF80_roundToInt$(OBJ) \ - extF80_add$(OBJ) \ - extF80_sub$(OBJ) \ - extF80_mul$(OBJ) \ - extF80_div$(OBJ) \ - extF80_rem$(OBJ) \ - extF80_sqrt$(OBJ) \ - extF80_eq$(OBJ) \ - extF80_le$(OBJ) \ - extF80_lt$(OBJ) \ - extF80_eq_signaling$(OBJ) \ - extF80_le_quiet$(OBJ) \ - extF80_lt_quiet$(OBJ) \ - extF80_isSignalingNaN$(OBJ) \ - extF80M_to_ui32$(OBJ) \ - extF80M_to_ui64$(OBJ) \ - extF80M_to_i32$(OBJ) \ - extF80M_to_i64$(OBJ) \ - extF80M_to_ui32_r_minMag$(OBJ) \ - extF80M_to_ui64_r_minMag$(OBJ) \ - extF80M_to_i32_r_minMag$(OBJ) \ - extF80M_to_i64_r_minMag$(OBJ) \ - extF80M_to_f16$(OBJ) \ - extF80M_to_f32$(OBJ) \ - extF80M_to_f64$(OBJ) \ - extF80M_to_f128M$(OBJ) \ - extF80M_roundToInt$(OBJ) \ - extF80M_add$(OBJ) \ - extF80M_sub$(OBJ) \ - extF80M_mul$(OBJ) \ - extF80M_div$(OBJ) \ - extF80M_rem$(OBJ) \ - extF80M_sqrt$(OBJ) \ - extF80M_eq$(OBJ) \ - extF80M_le$(OBJ) \ - extF80M_lt$(OBJ) \ - extF80M_eq_signaling$(OBJ) \ - extF80M_le_quiet$(OBJ) \ - extF80M_lt_quiet$(OBJ) \ - f128_to_ui32$(OBJ) \ - f128_to_ui64$(OBJ) \ - f128_to_i32$(OBJ) \ - f128_to_i64$(OBJ) \ - f128_to_ui32_r_minMag$(OBJ) \ - f128_to_ui64_r_minMag$(OBJ) \ - f128_to_i32_r_minMag$(OBJ) \ - f128_to_i64_r_minMag$(OBJ) \ - f128_to_f16$(OBJ) \ - f128_to_f32$(OBJ) \ - f128_to_extF80$(OBJ) \ - f128_to_f64$(OBJ) \ - f128_roundToInt$(OBJ) \ - f128_add$(OBJ) \ - f128_sub$(OBJ) \ - f128_mul$(OBJ) \ - f128_mulAdd$(OBJ) \ - f128_div$(OBJ) \ - f128_rem$(OBJ) \ - f128_sqrt$(OBJ) \ - f128_eq$(OBJ) \ - f128_le$(OBJ) \ - f128_lt$(OBJ) \ - f128_eq_signaling$(OBJ) \ - f128_le_quiet$(OBJ) \ - f128_lt_quiet$(OBJ) \ - f128_isSignalingNaN$(OBJ) \ - f128M_to_ui32$(OBJ) \ - f128M_to_ui64$(OBJ) \ - f128M_to_i32$(OBJ) \ - f128M_to_i64$(OBJ) \ - f128M_to_ui32_r_minMag$(OBJ) \ - f128M_to_ui64_r_minMag$(OBJ) \ - f128M_to_i32_r_minMag$(OBJ) \ - f128M_to_i64_r_minMag$(OBJ) \ - f128M_to_f16$(OBJ) \ - f128M_to_f32$(OBJ) \ - f128M_to_extF80M$(OBJ) \ - f128M_to_f64$(OBJ) \ - f128M_roundToInt$(OBJ) \ - f128M_add$(OBJ) \ - f128M_sub$(OBJ) \ - f128M_mul$(OBJ) \ - f128M_mulAdd$(OBJ) \ - f128M_div$(OBJ) \ - f128M_rem$(OBJ) \ - f128M_sqrt$(OBJ) \ - f128M_eq$(OBJ) \ - f128M_le$(OBJ) \ - f128M_lt$(OBJ) \ - f128M_eq_signaling$(OBJ) \ - f128M_le_quiet$(OBJ) \ - f128M_lt_quiet$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) - -$(OBJS_ALL): \ - $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ - $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ - $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ - $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ - $(SOURCE_DIR)/include/softfloat.h - -$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$*.c - -$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c - -softfloat$(LIB): $(OBJS_ALL) - $(DELETE) $@ - $(MAKELIB) $^ - -.PHONY: clean -clean: - $(DELETE) $(OBJS_ALL) softfloat$(LIB) - diff --git a/softfloat/build/Linux-x86_64-GCC/platform.h b/softfloat/build/Linux-x86_64-GCC/platform.h deleted file mode 100644 index cd1b5b4..0000000 --- a/softfloat/build/Linux-x86_64-GCC/platform.h +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -#define LITTLEENDIAN 1 - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -#ifdef __GNUC_STDC_INLINE__ -//#define INLINE inline -#define INLINE static -#else -#define INLINE extern inline -#endif - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -#ifdef __GNUC__ -#define SOFTFLOAT_BUILTIN_CLZ 1 -#define SOFTFLOAT_INTRINSIC_INT128 1 -#endif -#include "opts-GCC.h" diff --git a/softfloat/build/Win32-MinGW/Makefile b/softfloat/build/Win32-MinGW/Makefile deleted file mode 100644 index 4181600..0000000 --- a/softfloat/build/Win32-MinGW/Makefile +++ /dev/null @@ -1,325 +0,0 @@ - -#============================================================================= -# -# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic -# Package, Release 3e, by John R. Hauser. -# -# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -# University of California. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions, and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions, and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the University nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#============================================================================= - -SOURCE_DIR ?= ../../source -SPECIALIZE_TYPE ?= 8086 - -SOFTFLOAT_OPTS ?= \ - -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \ - -DSOFTFLOAT_FAST_DIV64TO32 - -DELETE = rm -f -C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include -COMPILE_C = \ - gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \ - $(C_INCLUDES) -O2 -o $@ -MAKELIB = ar crs $@ - -OBJ = .o -LIB = .a - -OTHER_HEADERS = - -.PHONY: all -all: softfloat$(LIB) - -OBJS_PRIMITIVES = \ - s_compare96M$(OBJ) \ - s_compare128M$(OBJ) \ - s_shortShiftLeft64To96M$(OBJ) \ - s_shortShiftLeftM$(OBJ) \ - s_shiftLeftM$(OBJ) \ - s_shortShiftRightM$(OBJ) \ - s_shortShiftRightJam64$(OBJ) \ - s_shortShiftRightJamM$(OBJ) \ - s_shiftRightJam32$(OBJ) \ - s_shiftRightJam64$(OBJ) \ - s_shiftRightJamM$(OBJ) \ - s_shiftRightM$(OBJ) \ - s_countLeadingZeros8$(OBJ) \ - s_countLeadingZeros16$(OBJ) \ - s_countLeadingZeros32$(OBJ) \ - s_countLeadingZeros64$(OBJ) \ - s_addM$(OBJ) \ - s_addCarryM$(OBJ) \ - s_addComplCarryM$(OBJ) \ - s_negXM$(OBJ) \ - s_sub1XM$(OBJ) \ - s_subM$(OBJ) \ - s_mul64To128M$(OBJ) \ - s_mul128MTo256M$(OBJ) \ - s_approxRecip_1Ks$(OBJ) \ - s_approxRecip32_1$(OBJ) \ - s_approxRecipSqrt_1Ks$(OBJ) \ - s_approxRecipSqrt32_1$(OBJ) \ - s_remStepMBy32$(OBJ) \ - -OBJS_SPECIALIZE = \ - softfloat_raiseFlags$(OBJ) \ - s_f16UIToCommonNaN$(OBJ) \ - s_commonNaNToF16UI$(OBJ) \ - s_propagateNaNF16UI$(OBJ) \ - s_f32UIToCommonNaN$(OBJ) \ - s_commonNaNToF32UI$(OBJ) \ - s_propagateNaNF32UI$(OBJ) \ - s_f64UIToCommonNaN$(OBJ) \ - s_commonNaNToF64UI$(OBJ) \ - s_propagateNaNF64UI$(OBJ) \ - extF80M_isSignalingNaN$(OBJ) \ - s_extF80MToCommonNaN$(OBJ) \ - s_commonNaNToExtF80M$(OBJ) \ - s_propagateNaNExtF80M$(OBJ) \ - f128M_isSignalingNaN$(OBJ) \ - s_f128MToCommonNaN$(OBJ) \ - s_commonNaNToF128M$(OBJ) \ - s_propagateNaNF128M$(OBJ) \ - -OBJS_OTHERS = \ - s_roundToUI32$(OBJ) \ - s_roundMToUI64$(OBJ) \ - s_roundToI32$(OBJ) \ - s_roundMToI64$(OBJ) \ - s_normSubnormalF16Sig$(OBJ) \ - s_roundPackToF16$(OBJ) \ - s_normRoundPackToF16$(OBJ) \ - s_addMagsF16$(OBJ) \ - s_subMagsF16$(OBJ) \ - s_mulAddF16$(OBJ) \ - s_normSubnormalF32Sig$(OBJ) \ - s_roundPackToF32$(OBJ) \ - s_normRoundPackToF32$(OBJ) \ - s_addMagsF32$(OBJ) \ - s_subMagsF32$(OBJ) \ - s_mulAddF32$(OBJ) \ - s_normSubnormalF64Sig$(OBJ) \ - s_roundPackToF64$(OBJ) \ - s_normRoundPackToF64$(OBJ) \ - s_addMagsF64$(OBJ) \ - s_subMagsF64$(OBJ) \ - s_mulAddF64$(OBJ) \ - s_tryPropagateNaNExtF80M$(OBJ) \ - s_invalidExtF80M$(OBJ) \ - s_normExtF80SigM$(OBJ) \ - s_roundPackMToExtF80M$(OBJ) \ - s_normRoundPackMToExtF80M$(OBJ) \ - s_addExtF80M$(OBJ) \ - s_compareNonnormExtF80M$(OBJ) \ - s_isNaNF128M$(OBJ) \ - s_tryPropagateNaNF128M$(OBJ) \ - s_invalidF128M$(OBJ) \ - s_shiftNormSigF128M$(OBJ) \ - s_roundPackMToF128M$(OBJ) \ - s_normRoundPackMToF128M$(OBJ) \ - s_addF128M$(OBJ) \ - s_mulAddF128M$(OBJ) \ - softfloat_state$(OBJ) \ - ui32_to_f16$(OBJ) \ - ui32_to_f32$(OBJ) \ - ui32_to_f64$(OBJ) \ - ui32_to_extF80M$(OBJ) \ - ui32_to_f128M$(OBJ) \ - ui64_to_f16$(OBJ) \ - ui64_to_f32$(OBJ) \ - ui64_to_f64$(OBJ) \ - ui64_to_extF80M$(OBJ) \ - ui64_to_f128M$(OBJ) \ - i32_to_f16$(OBJ) \ - i32_to_f32$(OBJ) \ - i32_to_f64$(OBJ) \ - i32_to_extF80M$(OBJ) \ - i32_to_f128M$(OBJ) \ - i64_to_f16$(OBJ) \ - i64_to_f32$(OBJ) \ - i64_to_f64$(OBJ) \ - i64_to_extF80M$(OBJ) \ - i64_to_f128M$(OBJ) \ - f16_to_ui32$(OBJ) \ - f16_to_ui64$(OBJ) \ - f16_to_i32$(OBJ) \ - f16_to_i64$(OBJ) \ - f16_to_ui32_r_minMag$(OBJ) \ - f16_to_ui64_r_minMag$(OBJ) \ - f16_to_i32_r_minMag$(OBJ) \ - f16_to_i64_r_minMag$(OBJ) \ - f16_to_f32$(OBJ) \ - f16_to_f64$(OBJ) \ - f16_to_extF80M$(OBJ) \ - f16_to_f128M$(OBJ) \ - f16_roundToInt$(OBJ) \ - f16_add$(OBJ) \ - f16_sub$(OBJ) \ - f16_mul$(OBJ) \ - f16_mulAdd$(OBJ) \ - f16_div$(OBJ) \ - f16_rem$(OBJ) \ - f16_sqrt$(OBJ) \ - f16_eq$(OBJ) \ - f16_le$(OBJ) \ - f16_lt$(OBJ) \ - f16_eq_signaling$(OBJ) \ - f16_le_quiet$(OBJ) \ - f16_lt_quiet$(OBJ) \ - f16_isSignalingNaN$(OBJ) \ - f32_to_ui32$(OBJ) \ - f32_to_ui64$(OBJ) \ - f32_to_i32$(OBJ) \ - f32_to_i64$(OBJ) \ - f32_to_ui32_r_minMag$(OBJ) \ - f32_to_ui64_r_minMag$(OBJ) \ - f32_to_i32_r_minMag$(OBJ) \ - f32_to_i64_r_minMag$(OBJ) \ - f32_to_f16$(OBJ) \ - f32_to_f64$(OBJ) \ - f32_to_extF80M$(OBJ) \ - f32_to_f128M$(OBJ) \ - f32_roundToInt$(OBJ) \ - f32_add$(OBJ) \ - f32_sub$(OBJ) \ - f32_mul$(OBJ) \ - f32_mulAdd$(OBJ) \ - f32_div$(OBJ) \ - f32_rem$(OBJ) \ - f32_sqrt$(OBJ) \ - f32_eq$(OBJ) \ - f32_le$(OBJ) \ - f32_lt$(OBJ) \ - f32_eq_signaling$(OBJ) \ - f32_le_quiet$(OBJ) \ - f32_lt_quiet$(OBJ) \ - f32_isSignalingNaN$(OBJ) \ - f64_to_ui32$(OBJ) \ - f64_to_ui64$(OBJ) \ - f64_to_i32$(OBJ) \ - f64_to_i64$(OBJ) \ - f64_to_ui32_r_minMag$(OBJ) \ - f64_to_ui64_r_minMag$(OBJ) \ - f64_to_i32_r_minMag$(OBJ) \ - f64_to_i64_r_minMag$(OBJ) \ - f64_to_f16$(OBJ) \ - f64_to_f32$(OBJ) \ - f64_to_extF80M$(OBJ) \ - f64_to_f128M$(OBJ) \ - f64_roundToInt$(OBJ) \ - f64_add$(OBJ) \ - f64_sub$(OBJ) \ - f64_mul$(OBJ) \ - f64_mulAdd$(OBJ) \ - f64_div$(OBJ) \ - f64_rem$(OBJ) \ - f64_sqrt$(OBJ) \ - f64_eq$(OBJ) \ - f64_le$(OBJ) \ - f64_lt$(OBJ) \ - f64_eq_signaling$(OBJ) \ - f64_le_quiet$(OBJ) \ - f64_lt_quiet$(OBJ) \ - f64_isSignalingNaN$(OBJ) \ - extF80M_to_ui32$(OBJ) \ - extF80M_to_ui64$(OBJ) \ - extF80M_to_i32$(OBJ) \ - extF80M_to_i64$(OBJ) \ - extF80M_to_ui32_r_minMag$(OBJ) \ - extF80M_to_ui64_r_minMag$(OBJ) \ - extF80M_to_i32_r_minMag$(OBJ) \ - extF80M_to_i64_r_minMag$(OBJ) \ - extF80M_to_f16$(OBJ) \ - extF80M_to_f32$(OBJ) \ - extF80M_to_f64$(OBJ) \ - extF80M_to_f128M$(OBJ) \ - extF80M_roundToInt$(OBJ) \ - extF80M_add$(OBJ) \ - extF80M_sub$(OBJ) \ - extF80M_mul$(OBJ) \ - extF80M_div$(OBJ) \ - extF80M_rem$(OBJ) \ - extF80M_sqrt$(OBJ) \ - extF80M_eq$(OBJ) \ - extF80M_le$(OBJ) \ - extF80M_lt$(OBJ) \ - extF80M_eq_signaling$(OBJ) \ - extF80M_le_quiet$(OBJ) \ - extF80M_lt_quiet$(OBJ) \ - f128M_to_ui32$(OBJ) \ - f128M_to_ui64$(OBJ) \ - f128M_to_i32$(OBJ) \ - f128M_to_i64$(OBJ) \ - f128M_to_ui32_r_minMag$(OBJ) \ - f128M_to_ui64_r_minMag$(OBJ) \ - f128M_to_i32_r_minMag$(OBJ) \ - f128M_to_i64_r_minMag$(OBJ) \ - f128M_to_f16$(OBJ) \ - f128M_to_f32$(OBJ) \ - f128M_to_f64$(OBJ) \ - f128M_to_extF80M$(OBJ) \ - f128M_roundToInt$(OBJ) \ - f128M_add$(OBJ) \ - f128M_sub$(OBJ) \ - f128M_mul$(OBJ) \ - f128M_mulAdd$(OBJ) \ - f128M_div$(OBJ) \ - f128M_rem$(OBJ) \ - f128M_sqrt$(OBJ) \ - f128M_eq$(OBJ) \ - f128M_le$(OBJ) \ - f128M_lt$(OBJ) \ - f128M_eq_signaling$(OBJ) \ - f128M_le_quiet$(OBJ) \ - f128M_lt_quiet$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) - -$(OBJS_ALL): \ - $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ - $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ - $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ - $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ - $(SOURCE_DIR)/include/softfloat.h - -$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$*.c - -$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c - -softfloat$(LIB): $(OBJS_ALL) - $(DELETE) $@ - $(MAKELIB) $^ - -.PHONY: clean -clean: - $(DELETE) $(OBJS_ALL) softfloat$(LIB) - diff --git a/softfloat/build/Win32-MinGW/platform.h b/softfloat/build/Win32-MinGW/platform.h deleted file mode 100644 index 420aa4e..0000000 --- a/softfloat/build/Win32-MinGW/platform.h +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define LITTLEENDIAN 1 - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#ifdef __GNUC_STDC_INLINE__ -#define INLINE inline -#else -#define INLINE extern inline -#endif - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define SOFTFLOAT_BUILTIN_CLZ 1 -#include "opts-GCC.h" - diff --git a/softfloat/build/Win32-SSE2-MinGW/Makefile b/softfloat/build/Win32-SSE2-MinGW/Makefile deleted file mode 100644 index 1cf6f5e..0000000 --- a/softfloat/build/Win32-SSE2-MinGW/Makefile +++ /dev/null @@ -1,325 +0,0 @@ - -#============================================================================= -# -# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic -# Package, Release 3e, by John R. Hauser. -# -# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -# University of California. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions, and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions, and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the University nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#============================================================================= - -SOURCE_DIR ?= ../../source -SPECIALIZE_TYPE ?= 8086-SSE - -SOFTFLOAT_OPTS ?= \ - -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \ - -DSOFTFLOAT_FAST_DIV64TO32 - -DELETE = rm -f -C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include -COMPILE_C = \ - gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \ - $(C_INCLUDES) -O2 -o $@ -MAKELIB = ar crs $@ - -OBJ = .o -LIB = .a - -OTHER_HEADERS = - -.PHONY: all -all: softfloat$(LIB) - -OBJS_PRIMITIVES = \ - s_compare96M$(OBJ) \ - s_compare128M$(OBJ) \ - s_shortShiftLeft64To96M$(OBJ) \ - s_shortShiftLeftM$(OBJ) \ - s_shiftLeftM$(OBJ) \ - s_shortShiftRightM$(OBJ) \ - s_shortShiftRightJam64$(OBJ) \ - s_shortShiftRightJamM$(OBJ) \ - s_shiftRightJam32$(OBJ) \ - s_shiftRightJam64$(OBJ) \ - s_shiftRightJamM$(OBJ) \ - s_shiftRightM$(OBJ) \ - s_countLeadingZeros8$(OBJ) \ - s_countLeadingZeros16$(OBJ) \ - s_countLeadingZeros32$(OBJ) \ - s_countLeadingZeros64$(OBJ) \ - s_addM$(OBJ) \ - s_addCarryM$(OBJ) \ - s_addComplCarryM$(OBJ) \ - s_negXM$(OBJ) \ - s_sub1XM$(OBJ) \ - s_subM$(OBJ) \ - s_mul64To128M$(OBJ) \ - s_mul128MTo256M$(OBJ) \ - s_approxRecip_1Ks$(OBJ) \ - s_approxRecip32_1$(OBJ) \ - s_approxRecipSqrt_1Ks$(OBJ) \ - s_approxRecipSqrt32_1$(OBJ) \ - s_remStepMBy32$(OBJ) \ - -OBJS_SPECIALIZE = \ - softfloat_raiseFlags$(OBJ) \ - s_f16UIToCommonNaN$(OBJ) \ - s_commonNaNToF16UI$(OBJ) \ - s_propagateNaNF16UI$(OBJ) \ - s_f32UIToCommonNaN$(OBJ) \ - s_commonNaNToF32UI$(OBJ) \ - s_propagateNaNF32UI$(OBJ) \ - s_f64UIToCommonNaN$(OBJ) \ - s_commonNaNToF64UI$(OBJ) \ - s_propagateNaNF64UI$(OBJ) \ - extF80M_isSignalingNaN$(OBJ) \ - s_extF80MToCommonNaN$(OBJ) \ - s_commonNaNToExtF80M$(OBJ) \ - s_propagateNaNExtF80M$(OBJ) \ - f128M_isSignalingNaN$(OBJ) \ - s_f128MToCommonNaN$(OBJ) \ - s_commonNaNToF128M$(OBJ) \ - s_propagateNaNF128M$(OBJ) \ - -OBJS_OTHERS = \ - s_roundToUI32$(OBJ) \ - s_roundMToUI64$(OBJ) \ - s_roundToI32$(OBJ) \ - s_roundMToI64$(OBJ) \ - s_normSubnormalF16Sig$(OBJ) \ - s_roundPackToF16$(OBJ) \ - s_normRoundPackToF16$(OBJ) \ - s_addMagsF16$(OBJ) \ - s_subMagsF16$(OBJ) \ - s_mulAddF16$(OBJ) \ - s_normSubnormalF32Sig$(OBJ) \ - s_roundPackToF32$(OBJ) \ - s_normRoundPackToF32$(OBJ) \ - s_addMagsF32$(OBJ) \ - s_subMagsF32$(OBJ) \ - s_mulAddF32$(OBJ) \ - s_normSubnormalF64Sig$(OBJ) \ - s_roundPackToF64$(OBJ) \ - s_normRoundPackToF64$(OBJ) \ - s_addMagsF64$(OBJ) \ - s_subMagsF64$(OBJ) \ - s_mulAddF64$(OBJ) \ - s_tryPropagateNaNExtF80M$(OBJ) \ - s_invalidExtF80M$(OBJ) \ - s_normExtF80SigM$(OBJ) \ - s_roundPackMToExtF80M$(OBJ) \ - s_normRoundPackMToExtF80M$(OBJ) \ - s_addExtF80M$(OBJ) \ - s_compareNonnormExtF80M$(OBJ) \ - s_isNaNF128M$(OBJ) \ - s_tryPropagateNaNF128M$(OBJ) \ - s_invalidF128M$(OBJ) \ - s_shiftNormSigF128M$(OBJ) \ - s_roundPackMToF128M$(OBJ) \ - s_normRoundPackMToF128M$(OBJ) \ - s_addF128M$(OBJ) \ - s_mulAddF128M$(OBJ) \ - softfloat_state$(OBJ) \ - ui32_to_f16$(OBJ) \ - ui32_to_f32$(OBJ) \ - ui32_to_f64$(OBJ) \ - ui32_to_extF80M$(OBJ) \ - ui32_to_f128M$(OBJ) \ - ui64_to_f16$(OBJ) \ - ui64_to_f32$(OBJ) \ - ui64_to_f64$(OBJ) \ - ui64_to_extF80M$(OBJ) \ - ui64_to_f128M$(OBJ) \ - i32_to_f16$(OBJ) \ - i32_to_f32$(OBJ) \ - i32_to_f64$(OBJ) \ - i32_to_extF80M$(OBJ) \ - i32_to_f128M$(OBJ) \ - i64_to_f16$(OBJ) \ - i64_to_f32$(OBJ) \ - i64_to_f64$(OBJ) \ - i64_to_extF80M$(OBJ) \ - i64_to_f128M$(OBJ) \ - f16_to_ui32$(OBJ) \ - f16_to_ui64$(OBJ) \ - f16_to_i32$(OBJ) \ - f16_to_i64$(OBJ) \ - f16_to_ui32_r_minMag$(OBJ) \ - f16_to_ui64_r_minMag$(OBJ) \ - f16_to_i32_r_minMag$(OBJ) \ - f16_to_i64_r_minMag$(OBJ) \ - f16_to_f32$(OBJ) \ - f16_to_f64$(OBJ) \ - f16_to_extF80M$(OBJ) \ - f16_to_f128M$(OBJ) \ - f16_roundToInt$(OBJ) \ - f16_add$(OBJ) \ - f16_sub$(OBJ) \ - f16_mul$(OBJ) \ - f16_mulAdd$(OBJ) \ - f16_div$(OBJ) \ - f16_rem$(OBJ) \ - f16_sqrt$(OBJ) \ - f16_eq$(OBJ) \ - f16_le$(OBJ) \ - f16_lt$(OBJ) \ - f16_eq_signaling$(OBJ) \ - f16_le_quiet$(OBJ) \ - f16_lt_quiet$(OBJ) \ - f16_isSignalingNaN$(OBJ) \ - f32_to_ui32$(OBJ) \ - f32_to_ui64$(OBJ) \ - f32_to_i32$(OBJ) \ - f32_to_i64$(OBJ) \ - f32_to_ui32_r_minMag$(OBJ) \ - f32_to_ui64_r_minMag$(OBJ) \ - f32_to_i32_r_minMag$(OBJ) \ - f32_to_i64_r_minMag$(OBJ) \ - f32_to_f16$(OBJ) \ - f32_to_f64$(OBJ) \ - f32_to_extF80M$(OBJ) \ - f32_to_f128M$(OBJ) \ - f32_roundToInt$(OBJ) \ - f32_add$(OBJ) \ - f32_sub$(OBJ) \ - f32_mul$(OBJ) \ - f32_mulAdd$(OBJ) \ - f32_div$(OBJ) \ - f32_rem$(OBJ) \ - f32_sqrt$(OBJ) \ - f32_eq$(OBJ) \ - f32_le$(OBJ) \ - f32_lt$(OBJ) \ - f32_eq_signaling$(OBJ) \ - f32_le_quiet$(OBJ) \ - f32_lt_quiet$(OBJ) \ - f32_isSignalingNaN$(OBJ) \ - f64_to_ui32$(OBJ) \ - f64_to_ui64$(OBJ) \ - f64_to_i32$(OBJ) \ - f64_to_i64$(OBJ) \ - f64_to_ui32_r_minMag$(OBJ) \ - f64_to_ui64_r_minMag$(OBJ) \ - f64_to_i32_r_minMag$(OBJ) \ - f64_to_i64_r_minMag$(OBJ) \ - f64_to_f16$(OBJ) \ - f64_to_f32$(OBJ) \ - f64_to_extF80M$(OBJ) \ - f64_to_f128M$(OBJ) \ - f64_roundToInt$(OBJ) \ - f64_add$(OBJ) \ - f64_sub$(OBJ) \ - f64_mul$(OBJ) \ - f64_mulAdd$(OBJ) \ - f64_div$(OBJ) \ - f64_rem$(OBJ) \ - f64_sqrt$(OBJ) \ - f64_eq$(OBJ) \ - f64_le$(OBJ) \ - f64_lt$(OBJ) \ - f64_eq_signaling$(OBJ) \ - f64_le_quiet$(OBJ) \ - f64_lt_quiet$(OBJ) \ - f64_isSignalingNaN$(OBJ) \ - extF80M_to_ui32$(OBJ) \ - extF80M_to_ui64$(OBJ) \ - extF80M_to_i32$(OBJ) \ - extF80M_to_i64$(OBJ) \ - extF80M_to_ui32_r_minMag$(OBJ) \ - extF80M_to_ui64_r_minMag$(OBJ) \ - extF80M_to_i32_r_minMag$(OBJ) \ - extF80M_to_i64_r_minMag$(OBJ) \ - extF80M_to_f16$(OBJ) \ - extF80M_to_f32$(OBJ) \ - extF80M_to_f64$(OBJ) \ - extF80M_to_f128M$(OBJ) \ - extF80M_roundToInt$(OBJ) \ - extF80M_add$(OBJ) \ - extF80M_sub$(OBJ) \ - extF80M_mul$(OBJ) \ - extF80M_div$(OBJ) \ - extF80M_rem$(OBJ) \ - extF80M_sqrt$(OBJ) \ - extF80M_eq$(OBJ) \ - extF80M_le$(OBJ) \ - extF80M_lt$(OBJ) \ - extF80M_eq_signaling$(OBJ) \ - extF80M_le_quiet$(OBJ) \ - extF80M_lt_quiet$(OBJ) \ - f128M_to_ui32$(OBJ) \ - f128M_to_ui64$(OBJ) \ - f128M_to_i32$(OBJ) \ - f128M_to_i64$(OBJ) \ - f128M_to_ui32_r_minMag$(OBJ) \ - f128M_to_ui64_r_minMag$(OBJ) \ - f128M_to_i32_r_minMag$(OBJ) \ - f128M_to_i64_r_minMag$(OBJ) \ - f128M_to_f16$(OBJ) \ - f128M_to_f32$(OBJ) \ - f128M_to_f64$(OBJ) \ - f128M_to_extF80M$(OBJ) \ - f128M_roundToInt$(OBJ) \ - f128M_add$(OBJ) \ - f128M_sub$(OBJ) \ - f128M_mul$(OBJ) \ - f128M_mulAdd$(OBJ) \ - f128M_div$(OBJ) \ - f128M_rem$(OBJ) \ - f128M_sqrt$(OBJ) \ - f128M_eq$(OBJ) \ - f128M_le$(OBJ) \ - f128M_lt$(OBJ) \ - f128M_eq_signaling$(OBJ) \ - f128M_le_quiet$(OBJ) \ - f128M_lt_quiet$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) - -$(OBJS_ALL): \ - $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ - $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ - $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ - $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ - $(SOURCE_DIR)/include/softfloat.h - -$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$*.c - -$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c - -softfloat$(LIB): $(OBJS_ALL) - $(DELETE) $@ - $(MAKELIB) $^ - -.PHONY: clean -clean: - $(DELETE) $(OBJS_ALL) softfloat$(LIB) - diff --git a/softfloat/build/Win32-SSE2-MinGW/platform.h b/softfloat/build/Win32-SSE2-MinGW/platform.h deleted file mode 100644 index 420aa4e..0000000 --- a/softfloat/build/Win32-SSE2-MinGW/platform.h +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define LITTLEENDIAN 1 - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#ifdef __GNUC_STDC_INLINE__ -#define INLINE inline -#else -#define INLINE extern inline -#endif - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define SOFTFLOAT_BUILTIN_CLZ 1 -#include "opts-GCC.h" - diff --git a/softfloat/build/Win64-MinGW-w64/Makefile b/softfloat/build/Win64-MinGW-w64/Makefile deleted file mode 100644 index 05bbf5b..0000000 --- a/softfloat/build/Win64-MinGW-w64/Makefile +++ /dev/null @@ -1,390 +0,0 @@ - -#============================================================================= -# -# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic -# Package, Release 3e, by John R. Hauser. -# -# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -# University of California. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions, and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions, and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the University nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#============================================================================= - -SOURCE_DIR ?= ../../source -SPECIALIZE_TYPE ?= 8086-SSE - -SOFTFLOAT_OPTS ?= \ - -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \ - -DSOFTFLOAT_FAST_DIV64TO32 - -DELETE = rm -f -C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include -COMPILE_C = \ - x86_64-w64-mingw32-gcc -c -Werror-implicit-function-declaration \ - -DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@ -MAKELIB = x86_64-w64-mingw32-ar crs $@ - -OBJ = .o -LIB = .a - -OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h - -.PHONY: all -all: softfloat$(LIB) - -OBJS_PRIMITIVES = \ - s_eq128$(OBJ) \ - s_le128$(OBJ) \ - s_lt128$(OBJ) \ - s_shortShiftLeft128$(OBJ) \ - s_shortShiftRight128$(OBJ) \ - s_shortShiftRightJam64$(OBJ) \ - s_shortShiftRightJam64Extra$(OBJ) \ - s_shortShiftRightJam128$(OBJ) \ - s_shortShiftRightJam128Extra$(OBJ) \ - s_shiftRightJam32$(OBJ) \ - s_shiftRightJam64$(OBJ) \ - s_shiftRightJam64Extra$(OBJ) \ - s_shiftRightJam128$(OBJ) \ - s_shiftRightJam128Extra$(OBJ) \ - s_shiftRightJam256M$(OBJ) \ - s_countLeadingZeros8$(OBJ) \ - s_countLeadingZeros16$(OBJ) \ - s_countLeadingZeros32$(OBJ) \ - s_countLeadingZeros64$(OBJ) \ - s_add128$(OBJ) \ - s_add256M$(OBJ) \ - s_sub128$(OBJ) \ - s_sub256M$(OBJ) \ - s_mul64ByShifted32To128$(OBJ) \ - s_mul64To128$(OBJ) \ - s_mul128By32$(OBJ) \ - s_mul128To256M$(OBJ) \ - s_approxRecip_1Ks$(OBJ) \ - s_approxRecip32_1$(OBJ) \ - s_approxRecipSqrt_1Ks$(OBJ) \ - s_approxRecipSqrt32_1$(OBJ) \ - -OBJS_SPECIALIZE = \ - softfloat_raiseFlags$(OBJ) \ - s_f16UIToCommonNaN$(OBJ) \ - s_commonNaNToF16UI$(OBJ) \ - s_propagateNaNF16UI$(OBJ) \ - s_f32UIToCommonNaN$(OBJ) \ - s_commonNaNToF32UI$(OBJ) \ - s_propagateNaNF32UI$(OBJ) \ - s_f64UIToCommonNaN$(OBJ) \ - s_commonNaNToF64UI$(OBJ) \ - s_propagateNaNF64UI$(OBJ) \ - extF80M_isSignalingNaN$(OBJ) \ - s_extF80UIToCommonNaN$(OBJ) \ - s_commonNaNToExtF80UI$(OBJ) \ - s_propagateNaNExtF80UI$(OBJ) \ - f128M_isSignalingNaN$(OBJ) \ - s_f128UIToCommonNaN$(OBJ) \ - s_commonNaNToF128UI$(OBJ) \ - s_propagateNaNF128UI$(OBJ) \ - -OBJS_OTHERS = \ - s_roundToUI32$(OBJ) \ - s_roundToUI64$(OBJ) \ - s_roundToI32$(OBJ) \ - s_roundToI64$(OBJ) \ - s_normSubnormalF16Sig$(OBJ) \ - s_roundPackToF16$(OBJ) \ - s_normRoundPackToF16$(OBJ) \ - s_addMagsF16$(OBJ) \ - s_subMagsF16$(OBJ) \ - s_mulAddF16$(OBJ) \ - s_normSubnormalF32Sig$(OBJ) \ - s_roundPackToF32$(OBJ) \ - s_normRoundPackToF32$(OBJ) \ - s_addMagsF32$(OBJ) \ - s_subMagsF32$(OBJ) \ - s_mulAddF32$(OBJ) \ - s_normSubnormalF64Sig$(OBJ) \ - s_roundPackToF64$(OBJ) \ - s_normRoundPackToF64$(OBJ) \ - s_addMagsF64$(OBJ) \ - s_subMagsF64$(OBJ) \ - s_mulAddF64$(OBJ) \ - s_normSubnormalExtF80Sig$(OBJ) \ - s_roundPackToExtF80$(OBJ) \ - s_normRoundPackToExtF80$(OBJ) \ - s_addMagsExtF80$(OBJ) \ - s_subMagsExtF80$(OBJ) \ - s_normSubnormalF128Sig$(OBJ) \ - s_roundPackToF128$(OBJ) \ - s_normRoundPackToF128$(OBJ) \ - s_addMagsF128$(OBJ) \ - s_subMagsF128$(OBJ) \ - s_mulAddF128$(OBJ) \ - softfloat_state$(OBJ) \ - ui32_to_f16$(OBJ) \ - ui32_to_f32$(OBJ) \ - ui32_to_f64$(OBJ) \ - ui32_to_extF80$(OBJ) \ - ui32_to_extF80M$(OBJ) \ - ui32_to_f128$(OBJ) \ - ui32_to_f128M$(OBJ) \ - ui64_to_f16$(OBJ) \ - ui64_to_f32$(OBJ) \ - ui64_to_f64$(OBJ) \ - ui64_to_extF80$(OBJ) \ - ui64_to_extF80M$(OBJ) \ - ui64_to_f128$(OBJ) \ - ui64_to_f128M$(OBJ) \ - i32_to_f16$(OBJ) \ - i32_to_f32$(OBJ) \ - i32_to_f64$(OBJ) \ - i32_to_extF80$(OBJ) \ - i32_to_extF80M$(OBJ) \ - i32_to_f128$(OBJ) \ - i32_to_f128M$(OBJ) \ - i64_to_f16$(OBJ) \ - i64_to_f32$(OBJ) \ - i64_to_f64$(OBJ) \ - i64_to_extF80$(OBJ) \ - i64_to_extF80M$(OBJ) \ - i64_to_f128$(OBJ) \ - i64_to_f128M$(OBJ) \ - f16_to_ui32$(OBJ) \ - f16_to_ui64$(OBJ) \ - f16_to_i32$(OBJ) \ - f16_to_i64$(OBJ) \ - f16_to_ui32_r_minMag$(OBJ) \ - f16_to_ui64_r_minMag$(OBJ) \ - f16_to_i32_r_minMag$(OBJ) \ - f16_to_i64_r_minMag$(OBJ) \ - f16_to_f32$(OBJ) \ - f16_to_f64$(OBJ) \ - f16_to_extF80$(OBJ) \ - f16_to_extF80M$(OBJ) \ - f16_to_f128$(OBJ) \ - f16_to_f128M$(OBJ) \ - f16_roundToInt$(OBJ) \ - f16_add$(OBJ) \ - f16_sub$(OBJ) \ - f16_mul$(OBJ) \ - f16_mulAdd$(OBJ) \ - f16_div$(OBJ) \ - f16_rem$(OBJ) \ - f16_sqrt$(OBJ) \ - f16_eq$(OBJ) \ - f16_le$(OBJ) \ - f16_lt$(OBJ) \ - f16_eq_signaling$(OBJ) \ - f16_le_quiet$(OBJ) \ - f16_lt_quiet$(OBJ) \ - f16_isSignalingNaN$(OBJ) \ - f32_to_ui32$(OBJ) \ - f32_to_ui64$(OBJ) \ - f32_to_i32$(OBJ) \ - f32_to_i64$(OBJ) \ - f32_to_ui32_r_minMag$(OBJ) \ - f32_to_ui64_r_minMag$(OBJ) \ - f32_to_i32_r_minMag$(OBJ) \ - f32_to_i64_r_minMag$(OBJ) \ - f32_to_f16$(OBJ) \ - f32_to_f64$(OBJ) \ - f32_to_extF80$(OBJ) \ - f32_to_extF80M$(OBJ) \ - f32_to_f128$(OBJ) \ - f32_to_f128M$(OBJ) \ - f32_roundToInt$(OBJ) \ - f32_add$(OBJ) \ - f32_sub$(OBJ) \ - f32_mul$(OBJ) \ - f32_mulAdd$(OBJ) \ - f32_div$(OBJ) \ - f32_rem$(OBJ) \ - f32_sqrt$(OBJ) \ - f32_eq$(OBJ) \ - f32_le$(OBJ) \ - f32_lt$(OBJ) \ - f32_eq_signaling$(OBJ) \ - f32_le_quiet$(OBJ) \ - f32_lt_quiet$(OBJ) \ - f32_isSignalingNaN$(OBJ) \ - f64_to_ui32$(OBJ) \ - f64_to_ui64$(OBJ) \ - f64_to_i32$(OBJ) \ - f64_to_i64$(OBJ) \ - f64_to_ui32_r_minMag$(OBJ) \ - f64_to_ui64_r_minMag$(OBJ) \ - f64_to_i32_r_minMag$(OBJ) \ - f64_to_i64_r_minMag$(OBJ) \ - f64_to_f16$(OBJ) \ - f64_to_f32$(OBJ) \ - f64_to_extF80$(OBJ) \ - f64_to_extF80M$(OBJ) \ - f64_to_f128$(OBJ) \ - f64_to_f128M$(OBJ) \ - f64_roundToInt$(OBJ) \ - f64_add$(OBJ) \ - f64_sub$(OBJ) \ - f64_mul$(OBJ) \ - f64_mulAdd$(OBJ) \ - f64_div$(OBJ) \ - f64_rem$(OBJ) \ - f64_sqrt$(OBJ) \ - f64_eq$(OBJ) \ - f64_le$(OBJ) \ - f64_lt$(OBJ) \ - f64_eq_signaling$(OBJ) \ - f64_le_quiet$(OBJ) \ - f64_lt_quiet$(OBJ) \ - f64_isSignalingNaN$(OBJ) \ - extF80_to_ui32$(OBJ) \ - extF80_to_ui64$(OBJ) \ - extF80_to_i32$(OBJ) \ - extF80_to_i64$(OBJ) \ - extF80_to_ui32_r_minMag$(OBJ) \ - extF80_to_ui64_r_minMag$(OBJ) \ - extF80_to_i32_r_minMag$(OBJ) \ - extF80_to_i64_r_minMag$(OBJ) \ - extF80_to_f16$(OBJ) \ - extF80_to_f32$(OBJ) \ - extF80_to_f64$(OBJ) \ - extF80_to_f128$(OBJ) \ - extF80_roundToInt$(OBJ) \ - extF80_add$(OBJ) \ - extF80_sub$(OBJ) \ - extF80_mul$(OBJ) \ - extF80_div$(OBJ) \ - extF80_rem$(OBJ) \ - extF80_sqrt$(OBJ) \ - extF80_eq$(OBJ) \ - extF80_le$(OBJ) \ - extF80_lt$(OBJ) \ - extF80_eq_signaling$(OBJ) \ - extF80_le_quiet$(OBJ) \ - extF80_lt_quiet$(OBJ) \ - extF80_isSignalingNaN$(OBJ) \ - extF80M_to_ui32$(OBJ) \ - extF80M_to_ui64$(OBJ) \ - extF80M_to_i32$(OBJ) \ - extF80M_to_i64$(OBJ) \ - extF80M_to_ui32_r_minMag$(OBJ) \ - extF80M_to_ui64_r_minMag$(OBJ) \ - extF80M_to_i32_r_minMag$(OBJ) \ - extF80M_to_i64_r_minMag$(OBJ) \ - extF80M_to_f16$(OBJ) \ - extF80M_to_f32$(OBJ) \ - extF80M_to_f64$(OBJ) \ - extF80M_to_f128M$(OBJ) \ - extF80M_roundToInt$(OBJ) \ - extF80M_add$(OBJ) \ - extF80M_sub$(OBJ) \ - extF80M_mul$(OBJ) \ - extF80M_div$(OBJ) \ - extF80M_rem$(OBJ) \ - extF80M_sqrt$(OBJ) \ - extF80M_eq$(OBJ) \ - extF80M_le$(OBJ) \ - extF80M_lt$(OBJ) \ - extF80M_eq_signaling$(OBJ) \ - extF80M_le_quiet$(OBJ) \ - extF80M_lt_quiet$(OBJ) \ - f128_to_ui32$(OBJ) \ - f128_to_ui64$(OBJ) \ - f128_to_i32$(OBJ) \ - f128_to_i64$(OBJ) \ - f128_to_ui32_r_minMag$(OBJ) \ - f128_to_ui64_r_minMag$(OBJ) \ - f128_to_i32_r_minMag$(OBJ) \ - f128_to_i64_r_minMag$(OBJ) \ - f128_to_f16$(OBJ) \ - f128_to_f32$(OBJ) \ - f128_to_extF80$(OBJ) \ - f128_to_f64$(OBJ) \ - f128_roundToInt$(OBJ) \ - f128_add$(OBJ) \ - f128_sub$(OBJ) \ - f128_mul$(OBJ) \ - f128_mulAdd$(OBJ) \ - f128_div$(OBJ) \ - f128_rem$(OBJ) \ - f128_sqrt$(OBJ) \ - f128_eq$(OBJ) \ - f128_le$(OBJ) \ - f128_lt$(OBJ) \ - f128_eq_signaling$(OBJ) \ - f128_le_quiet$(OBJ) \ - f128_lt_quiet$(OBJ) \ - f128_isSignalingNaN$(OBJ) \ - f128M_to_ui32$(OBJ) \ - f128M_to_ui64$(OBJ) \ - f128M_to_i32$(OBJ) \ - f128M_to_i64$(OBJ) \ - f128M_to_ui32_r_minMag$(OBJ) \ - f128M_to_ui64_r_minMag$(OBJ) \ - f128M_to_i32_r_minMag$(OBJ) \ - f128M_to_i64_r_minMag$(OBJ) \ - f128M_to_f16$(OBJ) \ - f128M_to_f32$(OBJ) \ - f128M_to_extF80M$(OBJ) \ - f128M_to_f64$(OBJ) \ - f128M_roundToInt$(OBJ) \ - f128M_add$(OBJ) \ - f128M_sub$(OBJ) \ - f128M_mul$(OBJ) \ - f128M_mulAdd$(OBJ) \ - f128M_div$(OBJ) \ - f128M_rem$(OBJ) \ - f128M_sqrt$(OBJ) \ - f128M_eq$(OBJ) \ - f128M_le$(OBJ) \ - f128M_lt$(OBJ) \ - f128M_eq_signaling$(OBJ) \ - f128M_le_quiet$(OBJ) \ - f128M_lt_quiet$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) - -$(OBJS_ALL): \ - $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ - $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ - $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ - $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ - $(SOURCE_DIR)/include/softfloat.h - -$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$*.c - -$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c - -softfloat$(LIB): $(OBJS_ALL) - $(DELETE) $@ - $(MAKELIB) $^ - -.PHONY: clean -clean: - $(DELETE) $(OBJS_ALL) softfloat$(LIB) - diff --git a/softfloat/build/Win64-MinGW-w64/platform.h b/softfloat/build/Win64-MinGW-w64/platform.h deleted file mode 100644 index 2fccb6c..0000000 --- a/softfloat/build/Win64-MinGW-w64/platform.h +++ /dev/null @@ -1,54 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define LITTLEENDIAN 1 - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#ifdef __GNUC_STDC_INLINE__ -#define INLINE inline -#else -#define INLINE extern inline -#endif - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define SOFTFLOAT_BUILTIN_CLZ 1 -#define SOFTFLOAT_INTRINSIC_INT128 1 -#include "opts-GCC.h" - diff --git a/softfloat/build/template-FAST_INT64/Makefile b/softfloat/build/template-FAST_INT64/Makefile deleted file mode 100644 index e04c216..0000000 --- a/softfloat/build/template-FAST_INT64/Makefile +++ /dev/null @@ -1,396 +0,0 @@ - -#============================================================================= -# -# This Makefile template is part of the SoftFloat IEEE Floating-Point -# Arithmetic Package, Release 3e, by John R. Hauser. -# -# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -# University of California. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions, and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions, and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the University nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#============================================================================= - -# Edit lines marked with `==>'. See "SoftFloat-source.html". - -==> SOURCE_DIR ?= ../../source -==> SPECIALIZE_TYPE ?= 8086 - -==> SOFTFLOAT_OPTS ?= \ -==> -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \ -==> -DSOFTFLOAT_FAST_DIV64TO32 - -==> DELETE = rm -f -==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include -==> COMPILE_C = \ -==> cc -c -DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@ -==> MAKELIB = ar crs $@ - -==> OBJ = .o -==> LIB = .a - -==> OTHER_HEADERS = - -.PHONY: all -all: softfloat$(LIB) - -OBJS_PRIMITIVES = \ - s_eq128$(OBJ) \ - s_le128$(OBJ) \ - s_lt128$(OBJ) \ - s_shortShiftLeft128$(OBJ) \ - s_shortShiftRight128$(OBJ) \ - s_shortShiftRightJam64$(OBJ) \ - s_shortShiftRightJam64Extra$(OBJ) \ - s_shortShiftRightJam128$(OBJ) \ - s_shortShiftRightJam128Extra$(OBJ) \ - s_shiftRightJam32$(OBJ) \ - s_shiftRightJam64$(OBJ) \ - s_shiftRightJam64Extra$(OBJ) \ - s_shiftRightJam128$(OBJ) \ - s_shiftRightJam128Extra$(OBJ) \ - s_shiftRightJam256M$(OBJ) \ - s_countLeadingZeros8$(OBJ) \ - s_countLeadingZeros16$(OBJ) \ - s_countLeadingZeros32$(OBJ) \ - s_countLeadingZeros64$(OBJ) \ - s_add128$(OBJ) \ - s_add256M$(OBJ) \ - s_sub128$(OBJ) \ - s_sub256M$(OBJ) \ - s_mul64ByShifted32To128$(OBJ) \ - s_mul64To128$(OBJ) \ - s_mul128By32$(OBJ) \ - s_mul128To256M$(OBJ) \ - s_approxRecip_1Ks$(OBJ) \ - s_approxRecip32_1$(OBJ) \ - s_approxRecipSqrt_1Ks$(OBJ) \ - s_approxRecipSqrt32_1$(OBJ) \ - -OBJS_SPECIALIZE = \ - softfloat_raiseFlags$(OBJ) \ - s_f16UIToCommonNaN$(OBJ) \ - s_commonNaNToF16UI$(OBJ) \ - s_propagateNaNF16UI$(OBJ) \ - s_f32UIToCommonNaN$(OBJ) \ - s_commonNaNToF32UI$(OBJ) \ - s_propagateNaNF32UI$(OBJ) \ - s_f64UIToCommonNaN$(OBJ) \ - s_commonNaNToF64UI$(OBJ) \ - s_propagateNaNF64UI$(OBJ) \ - extF80M_isSignalingNaN$(OBJ) \ - s_extF80UIToCommonNaN$(OBJ) \ - s_commonNaNToExtF80UI$(OBJ) \ - s_propagateNaNExtF80UI$(OBJ) \ - f128M_isSignalingNaN$(OBJ) \ - s_f128UIToCommonNaN$(OBJ) \ - s_commonNaNToF128UI$(OBJ) \ - s_propagateNaNF128UI$(OBJ) \ - -OBJS_OTHERS = \ - s_roundToUI32$(OBJ) \ - s_roundToUI64$(OBJ) \ - s_roundToI32$(OBJ) \ - s_roundToI64$(OBJ) \ - s_normSubnormalBF16Sig$(OBJ) \ - s_roundPackToBF16$(OBJ) \ - s_normSubnormalF16Sig$(OBJ) \ - s_roundPackToF16$(OBJ) \ - s_normRoundPackToF16$(OBJ) \ - s_addMagsF16$(OBJ) \ - s_subMagsF16$(OBJ) \ - s_mulAddF16$(OBJ) \ - s_normSubnormalF32Sig$(OBJ) \ - s_roundPackToF32$(OBJ) \ - s_normRoundPackToF32$(OBJ) \ - s_addMagsF32$(OBJ) \ - s_subMagsF32$(OBJ) \ - s_mulAddF32$(OBJ) \ - s_normSubnormalF64Sig$(OBJ) \ - s_roundPackToF64$(OBJ) \ - s_normRoundPackToF64$(OBJ) \ - s_addMagsF64$(OBJ) \ - s_subMagsF64$(OBJ) \ - s_mulAddF64$(OBJ) \ - s_normSubnormalExtF80Sig$(OBJ) \ - s_roundPackToExtF80$(OBJ) \ - s_normRoundPackToExtF80$(OBJ) \ - s_addMagsExtF80$(OBJ) \ - s_subMagsExtF80$(OBJ) \ - s_normSubnormalF128Sig$(OBJ) \ - s_roundPackToF128$(OBJ) \ - s_normRoundPackToF128$(OBJ) \ - s_addMagsF128$(OBJ) \ - s_subMagsF128$(OBJ) \ - s_mulAddF128$(OBJ) \ - softfloat_state$(OBJ) \ - ui32_to_f16$(OBJ) \ - ui32_to_f32$(OBJ) \ - ui32_to_f64$(OBJ) \ - ui32_to_extF80$(OBJ) \ - ui32_to_extF80M$(OBJ) \ - ui32_to_f128$(OBJ) \ - ui32_to_f128M$(OBJ) \ - ui64_to_f16$(OBJ) \ - ui64_to_f32$(OBJ) \ - ui64_to_f64$(OBJ) \ - ui64_to_extF80$(OBJ) \ - ui64_to_extF80M$(OBJ) \ - ui64_to_f128$(OBJ) \ - ui64_to_f128M$(OBJ) \ - i32_to_f16$(OBJ) \ - i32_to_f32$(OBJ) \ - i32_to_f64$(OBJ) \ - i32_to_extF80$(OBJ) \ - i32_to_extF80M$(OBJ) \ - i32_to_f128$(OBJ) \ - i32_to_f128M$(OBJ) \ - i64_to_f16$(OBJ) \ - i64_to_f32$(OBJ) \ - i64_to_f64$(OBJ) \ - i64_to_extF80$(OBJ) \ - i64_to_extF80M$(OBJ) \ - i64_to_f128$(OBJ) \ - i64_to_f128M$(OBJ) \ - bf16_isSignalingNaN$(OBJ) \ - bf16_to_f32$(OBJ) \ - f16_to_ui32$(OBJ) \ - f16_to_ui64$(OBJ) \ - f16_to_i32$(OBJ) \ - f16_to_i64$(OBJ) \ - f16_to_ui32_r_minMag$(OBJ) \ - f16_to_ui64_r_minMag$(OBJ) \ - f16_to_i32_r_minMag$(OBJ) \ - f16_to_i64_r_minMag$(OBJ) \ - f16_to_f32$(OBJ) \ - f16_to_f64$(OBJ) \ - f16_to_extF80$(OBJ) \ - f16_to_extF80M$(OBJ) \ - f16_to_f128$(OBJ) \ - f16_to_f128M$(OBJ) \ - f16_roundToInt$(OBJ) \ - f16_add$(OBJ) \ - f16_sub$(OBJ) \ - f16_mul$(OBJ) \ - f16_mulAdd$(OBJ) \ - f16_div$(OBJ) \ - f16_rem$(OBJ) \ - f16_sqrt$(OBJ) \ - f16_eq$(OBJ) \ - f16_le$(OBJ) \ - f16_lt$(OBJ) \ - f16_eq_signaling$(OBJ) \ - f16_le_quiet$(OBJ) \ - f16_lt_quiet$(OBJ) \ - f16_isSignalingNaN$(OBJ) \ - f32_to_ui32$(OBJ) \ - f32_to_ui64$(OBJ) \ - f32_to_i32$(OBJ) \ - f32_to_i64$(OBJ) \ - f32_to_ui32_r_minMag$(OBJ) \ - f32_to_ui64_r_minMag$(OBJ) \ - f32_to_i32_r_minMag$(OBJ) \ - f32_to_i64_r_minMag$(OBJ) \ - f32_to_bf16$(OBJ) \ - f32_to_f16$(OBJ) \ - f32_to_f64$(OBJ) \ - f32_to_extF80$(OBJ) \ - f32_to_extF80M$(OBJ) \ - f32_to_f128$(OBJ) \ - f32_to_f128M$(OBJ) \ - f32_roundToInt$(OBJ) \ - f32_add$(OBJ) \ - f32_sub$(OBJ) \ - f32_mul$(OBJ) \ - f32_mulAdd$(OBJ) \ - f32_div$(OBJ) \ - f32_rem$(OBJ) \ - f32_sqrt$(OBJ) \ - f32_eq$(OBJ) \ - f32_le$(OBJ) \ - f32_lt$(OBJ) \ - f32_eq_signaling$(OBJ) \ - f32_le_quiet$(OBJ) \ - f32_lt_quiet$(OBJ) \ - f32_isSignalingNaN$(OBJ) \ - f64_to_ui32$(OBJ) \ - f64_to_ui64$(OBJ) \ - f64_to_i32$(OBJ) \ - f64_to_i64$(OBJ) \ - f64_to_ui32_r_minMag$(OBJ) \ - f64_to_ui64_r_minMag$(OBJ) \ - f64_to_i32_r_minMag$(OBJ) \ - f64_to_i64_r_minMag$(OBJ) \ - f64_to_f16$(OBJ) \ - f64_to_f32$(OBJ) \ - f64_to_extF80$(OBJ) \ - f64_to_extF80M$(OBJ) \ - f64_to_f128$(OBJ) \ - f64_to_f128M$(OBJ) \ - f64_roundToInt$(OBJ) \ - f64_add$(OBJ) \ - f64_sub$(OBJ) \ - f64_mul$(OBJ) \ - f64_mulAdd$(OBJ) \ - f64_div$(OBJ) \ - f64_rem$(OBJ) \ - f64_sqrt$(OBJ) \ - f64_eq$(OBJ) \ - f64_le$(OBJ) \ - f64_lt$(OBJ) \ - f64_eq_signaling$(OBJ) \ - f64_le_quiet$(OBJ) \ - f64_lt_quiet$(OBJ) \ - f64_isSignalingNaN$(OBJ) \ - extF80_to_ui32$(OBJ) \ - extF80_to_ui64$(OBJ) \ - extF80_to_i32$(OBJ) \ - extF80_to_i64$(OBJ) \ - extF80_to_ui32_r_minMag$(OBJ) \ - extF80_to_ui64_r_minMag$(OBJ) \ - extF80_to_i32_r_minMag$(OBJ) \ - extF80_to_i64_r_minMag$(OBJ) \ - extF80_to_f16$(OBJ) \ - extF80_to_f32$(OBJ) \ - extF80_to_f64$(OBJ) \ - extF80_to_f128$(OBJ) \ - extF80_roundToInt$(OBJ) \ - extF80_add$(OBJ) \ - extF80_sub$(OBJ) \ - extF80_mul$(OBJ) \ - extF80_div$(OBJ) \ - extF80_rem$(OBJ) \ - extF80_sqrt$(OBJ) \ - extF80_eq$(OBJ) \ - extF80_le$(OBJ) \ - extF80_lt$(OBJ) \ - extF80_eq_signaling$(OBJ) \ - extF80_le_quiet$(OBJ) \ - extF80_lt_quiet$(OBJ) \ - extF80_isSignalingNaN$(OBJ) \ - extF80M_to_ui32$(OBJ) \ - extF80M_to_ui64$(OBJ) \ - extF80M_to_i32$(OBJ) \ - extF80M_to_i64$(OBJ) \ - extF80M_to_ui32_r_minMag$(OBJ) \ - extF80M_to_ui64_r_minMag$(OBJ) \ - extF80M_to_i32_r_minMag$(OBJ) \ - extF80M_to_i64_r_minMag$(OBJ) \ - extF80M_to_f16$(OBJ) \ - extF80M_to_f32$(OBJ) \ - extF80M_to_f64$(OBJ) \ - extF80M_to_f128M$(OBJ) \ - extF80M_roundToInt$(OBJ) \ - extF80M_add$(OBJ) \ - extF80M_sub$(OBJ) \ - extF80M_mul$(OBJ) \ - extF80M_div$(OBJ) \ - extF80M_rem$(OBJ) \ - extF80M_sqrt$(OBJ) \ - extF80M_eq$(OBJ) \ - extF80M_le$(OBJ) \ - extF80M_lt$(OBJ) \ - extF80M_eq_signaling$(OBJ) \ - extF80M_le_quiet$(OBJ) \ - extF80M_lt_quiet$(OBJ) \ - f128_to_ui32$(OBJ) \ - f128_to_ui64$(OBJ) \ - f128_to_i32$(OBJ) \ - f128_to_i64$(OBJ) \ - f128_to_ui32_r_minMag$(OBJ) \ - f128_to_ui64_r_minMag$(OBJ) \ - f128_to_i32_r_minMag$(OBJ) \ - f128_to_i64_r_minMag$(OBJ) \ - f128_to_f16$(OBJ) \ - f128_to_f32$(OBJ) \ - f128_to_extF80$(OBJ) \ - f128_to_f64$(OBJ) \ - f128_roundToInt$(OBJ) \ - f128_add$(OBJ) \ - f128_sub$(OBJ) \ - f128_mul$(OBJ) \ - f128_mulAdd$(OBJ) \ - f128_div$(OBJ) \ - f128_rem$(OBJ) \ - f128_sqrt$(OBJ) \ - f128_eq$(OBJ) \ - f128_le$(OBJ) \ - f128_lt$(OBJ) \ - f128_eq_signaling$(OBJ) \ - f128_le_quiet$(OBJ) \ - f128_lt_quiet$(OBJ) \ - f128_isSignalingNaN$(OBJ) \ - f128M_to_ui32$(OBJ) \ - f128M_to_ui64$(OBJ) \ - f128M_to_i32$(OBJ) \ - f128M_to_i64$(OBJ) \ - f128M_to_ui32_r_minMag$(OBJ) \ - f128M_to_ui64_r_minMag$(OBJ) \ - f128M_to_i32_r_minMag$(OBJ) \ - f128M_to_i64_r_minMag$(OBJ) \ - f128M_to_f16$(OBJ) \ - f128M_to_f32$(OBJ) \ - f128M_to_extF80M$(OBJ) \ - f128M_to_f64$(OBJ) \ - f128M_roundToInt$(OBJ) \ - f128M_add$(OBJ) \ - f128M_sub$(OBJ) \ - f128M_mul$(OBJ) \ - f128M_mulAdd$(OBJ) \ - f128M_div$(OBJ) \ - f128M_rem$(OBJ) \ - f128M_sqrt$(OBJ) \ - f128M_eq$(OBJ) \ - f128M_le$(OBJ) \ - f128M_lt$(OBJ) \ - f128M_eq_signaling$(OBJ) \ - f128M_le_quiet$(OBJ) \ - f128M_lt_quiet$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) - -$(OBJS_ALL): \ - $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ - $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ - $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ - $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ - $(SOURCE_DIR)/include/softfloat.h - -$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$*.c - -$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c - -softfloat$(LIB): $(OBJS_ALL) - $(DELETE) $@ - $(MAKELIB) $^ - -.PHONY: clean -clean: - $(DELETE) $(OBJS_ALL) softfloat$(LIB) - diff --git a/softfloat/build/template-FAST_INT64/platform.h b/softfloat/build/template-FAST_INT64/platform.h deleted file mode 100644 index 2094658..0000000 --- a/softfloat/build/template-FAST_INT64/platform.h +++ /dev/null @@ -1,50 +0,0 @@ - -/*============================================================================ - -This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -// Edit lines marked with `==>'. See "SoftFloat-source.html". - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define LITTLEENDIAN 1 - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define INLINE inline - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define THREAD_LOCAL _Thread_local - diff --git a/softfloat/build/template-not-FAST_INT64/Makefile b/softfloat/build/template-not-FAST_INT64/Makefile deleted file mode 100644 index 49fddfd..0000000 --- a/softfloat/build/template-not-FAST_INT64/Makefile +++ /dev/null @@ -1,325 +0,0 @@ - -#============================================================================= -# -# This Makefile template is part of the SoftFloat IEEE Floating-Point -# Arithmetic Package, Release 3e, by John R. Hauser. -# -# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -# University of California. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions, and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions, and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the University nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#============================================================================= - -# Edit lines marked with `==>'. See "SoftFloat-source.html". - -==> SOURCE_DIR ?= ../../source -==> SPECIALIZE_TYPE ?= 8086 - -==> SOFTFLOAT_OPTS ?= \ -==> -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \ -==> -DSOFTFLOAT_FAST_DIV64TO32 - -==> DELETE = rm -f -==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include -==> COMPILE_C = cc -c $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@ -==> MAKELIB = ar crs $@ - -==> OBJ = .o -==> LIB = .a - -==> OTHER_HEADERS = - -.PHONY: all -all: softfloat$(LIB) - -OBJS_PRIMITIVES = \ - s_compare96M$(OBJ) \ - s_compare128M$(OBJ) \ - s_shortShiftLeft64To96M$(OBJ) \ - s_shortShiftLeftM$(OBJ) \ - s_shiftLeftM$(OBJ) \ - s_shortShiftRightM$(OBJ) \ - s_shortShiftRightJam64$(OBJ) \ - s_shortShiftRightJamM$(OBJ) \ - s_shiftRightJam32$(OBJ) \ - s_shiftRightJam64$(OBJ) \ - s_shiftRightJamM$(OBJ) \ - s_shiftRightM$(OBJ) \ - s_countLeadingZeros8$(OBJ) \ - s_countLeadingZeros16$(OBJ) \ - s_countLeadingZeros32$(OBJ) \ - s_countLeadingZeros64$(OBJ) \ - s_addM$(OBJ) \ - s_addCarryM$(OBJ) \ - s_addComplCarryM$(OBJ) \ - s_negXM$(OBJ) \ - s_sub1XM$(OBJ) \ - s_subM$(OBJ) \ - s_mul64To128M$(OBJ) \ - s_mul128MTo256M$(OBJ) \ - s_approxRecip_1Ks$(OBJ) \ - s_approxRecip32_1$(OBJ) \ - s_approxRecipSqrt_1Ks$(OBJ) \ - s_approxRecipSqrt32_1$(OBJ) \ - s_remStepMBy32$(OBJ) \ - -OBJS_SPECIALIZE = \ - softfloat_raiseFlags$(OBJ) \ - s_f16UIToCommonNaN$(OBJ) \ - s_commonNaNToF16UI$(OBJ) \ - s_propagateNaNF16UI$(OBJ) \ - s_f32UIToCommonNaN$(OBJ) \ - s_commonNaNToF32UI$(OBJ) \ - s_propagateNaNF32UI$(OBJ) \ - s_f64UIToCommonNaN$(OBJ) \ - s_commonNaNToF64UI$(OBJ) \ - s_propagateNaNF64UI$(OBJ) \ - extF80M_isSignalingNaN$(OBJ) \ - s_extF80MToCommonNaN$(OBJ) \ - s_commonNaNToExtF80M$(OBJ) \ - s_propagateNaNExtF80M$(OBJ) \ - f128M_isSignalingNaN$(OBJ) \ - s_f128MToCommonNaN$(OBJ) \ - s_commonNaNToF128M$(OBJ) \ - s_propagateNaNF128M$(OBJ) \ - -OBJS_OTHERS = \ - s_roundToUI32$(OBJ) \ - s_roundMToUI64$(OBJ) \ - s_roundToI32$(OBJ) \ - s_roundMToI64$(OBJ) \ - s_normSubnormalF16Sig$(OBJ) \ - s_roundPackToF16$(OBJ) \ - s_normRoundPackToF16$(OBJ) \ - s_addMagsF16$(OBJ) \ - s_subMagsF16$(OBJ) \ - s_mulAddF16$(OBJ) \ - s_normSubnormalF32Sig$(OBJ) \ - s_roundPackToF32$(OBJ) \ - s_normRoundPackToF32$(OBJ) \ - s_addMagsF32$(OBJ) \ - s_subMagsF32$(OBJ) \ - s_mulAddF32$(OBJ) \ - s_normSubnormalF64Sig$(OBJ) \ - s_roundPackToF64$(OBJ) \ - s_normRoundPackToF64$(OBJ) \ - s_addMagsF64$(OBJ) \ - s_subMagsF64$(OBJ) \ - s_mulAddF64$(OBJ) \ - s_tryPropagateNaNExtF80M$(OBJ) \ - s_invalidExtF80M$(OBJ) \ - s_normExtF80SigM$(OBJ) \ - s_roundPackMToExtF80M$(OBJ) \ - s_normRoundPackMToExtF80M$(OBJ) \ - s_addExtF80M$(OBJ) \ - s_compareNonnormExtF80M$(OBJ) \ - s_isNaNF128M$(OBJ) \ - s_tryPropagateNaNF128M$(OBJ) \ - s_invalidF128M$(OBJ) \ - s_shiftNormSigF128M$(OBJ) \ - s_roundPackMToF128M$(OBJ) \ - s_normRoundPackMToF128M$(OBJ) \ - s_addF128M$(OBJ) \ - s_mulAddF128M$(OBJ) \ - softfloat_state$(OBJ) \ - ui32_to_f16$(OBJ) \ - ui32_to_f32$(OBJ) \ - ui32_to_f64$(OBJ) \ - ui32_to_extF80M$(OBJ) \ - ui32_to_f128M$(OBJ) \ - ui64_to_f16$(OBJ) \ - ui64_to_f32$(OBJ) \ - ui64_to_f64$(OBJ) \ - ui64_to_extF80M$(OBJ) \ - ui64_to_f128M$(OBJ) \ - i32_to_f16$(OBJ) \ - i32_to_f32$(OBJ) \ - i32_to_f64$(OBJ) \ - i32_to_extF80M$(OBJ) \ - i32_to_f128M$(OBJ) \ - i64_to_f16$(OBJ) \ - i64_to_f32$(OBJ) \ - i64_to_f64$(OBJ) \ - i64_to_extF80M$(OBJ) \ - i64_to_f128M$(OBJ) \ - f16_to_ui32$(OBJ) \ - f16_to_ui64$(OBJ) \ - f16_to_i32$(OBJ) \ - f16_to_i64$(OBJ) \ - f16_to_ui32_r_minMag$(OBJ) \ - f16_to_ui64_r_minMag$(OBJ) \ - f16_to_i32_r_minMag$(OBJ) \ - f16_to_i64_r_minMag$(OBJ) \ - f16_to_f32$(OBJ) \ - f16_to_f64$(OBJ) \ - f16_to_extF80M$(OBJ) \ - f16_to_f128M$(OBJ) \ - f16_roundToInt$(OBJ) \ - f16_add$(OBJ) \ - f16_sub$(OBJ) \ - f16_mul$(OBJ) \ - f16_mulAdd$(OBJ) \ - f16_div$(OBJ) \ - f16_rem$(OBJ) \ - f16_sqrt$(OBJ) \ - f16_eq$(OBJ) \ - f16_le$(OBJ) \ - f16_lt$(OBJ) \ - f16_eq_signaling$(OBJ) \ - f16_le_quiet$(OBJ) \ - f16_lt_quiet$(OBJ) \ - f16_isSignalingNaN$(OBJ) \ - f32_to_ui32$(OBJ) \ - f32_to_ui64$(OBJ) \ - f32_to_i32$(OBJ) \ - f32_to_i64$(OBJ) \ - f32_to_ui32_r_minMag$(OBJ) \ - f32_to_ui64_r_minMag$(OBJ) \ - f32_to_i32_r_minMag$(OBJ) \ - f32_to_i64_r_minMag$(OBJ) \ - f32_to_f16$(OBJ) \ - f32_to_f64$(OBJ) \ - f32_to_extF80M$(OBJ) \ - f32_to_f128M$(OBJ) \ - f32_roundToInt$(OBJ) \ - f32_add$(OBJ) \ - f32_sub$(OBJ) \ - f32_mul$(OBJ) \ - f32_mulAdd$(OBJ) \ - f32_div$(OBJ) \ - f32_rem$(OBJ) \ - f32_sqrt$(OBJ) \ - f32_eq$(OBJ) \ - f32_le$(OBJ) \ - f32_lt$(OBJ) \ - f32_eq_signaling$(OBJ) \ - f32_le_quiet$(OBJ) \ - f32_lt_quiet$(OBJ) \ - f32_isSignalingNaN$(OBJ) \ - f64_to_ui32$(OBJ) \ - f64_to_ui64$(OBJ) \ - f64_to_i32$(OBJ) \ - f64_to_i64$(OBJ) \ - f64_to_ui32_r_minMag$(OBJ) \ - f64_to_ui64_r_minMag$(OBJ) \ - f64_to_i32_r_minMag$(OBJ) \ - f64_to_i64_r_minMag$(OBJ) \ - f64_to_f16$(OBJ) \ - f64_to_f32$(OBJ) \ - f64_to_extF80M$(OBJ) \ - f64_to_f128M$(OBJ) \ - f64_roundToInt$(OBJ) \ - f64_add$(OBJ) \ - f64_sub$(OBJ) \ - f64_mul$(OBJ) \ - f64_mulAdd$(OBJ) \ - f64_div$(OBJ) \ - f64_rem$(OBJ) \ - f64_sqrt$(OBJ) \ - f64_eq$(OBJ) \ - f64_le$(OBJ) \ - f64_lt$(OBJ) \ - f64_eq_signaling$(OBJ) \ - f64_le_quiet$(OBJ) \ - f64_lt_quiet$(OBJ) \ - f64_isSignalingNaN$(OBJ) \ - extF80M_to_ui32$(OBJ) \ - extF80M_to_ui64$(OBJ) \ - extF80M_to_i32$(OBJ) \ - extF80M_to_i64$(OBJ) \ - extF80M_to_ui32_r_minMag$(OBJ) \ - extF80M_to_ui64_r_minMag$(OBJ) \ - extF80M_to_i32_r_minMag$(OBJ) \ - extF80M_to_i64_r_minMag$(OBJ) \ - extF80M_to_f16$(OBJ) \ - extF80M_to_f32$(OBJ) \ - extF80M_to_f64$(OBJ) \ - extF80M_to_f128M$(OBJ) \ - extF80M_roundToInt$(OBJ) \ - extF80M_add$(OBJ) \ - extF80M_sub$(OBJ) \ - extF80M_mul$(OBJ) \ - extF80M_div$(OBJ) \ - extF80M_rem$(OBJ) \ - extF80M_sqrt$(OBJ) \ - extF80M_eq$(OBJ) \ - extF80M_le$(OBJ) \ - extF80M_lt$(OBJ) \ - extF80M_eq_signaling$(OBJ) \ - extF80M_le_quiet$(OBJ) \ - extF80M_lt_quiet$(OBJ) \ - f128M_to_ui32$(OBJ) \ - f128M_to_ui64$(OBJ) \ - f128M_to_i32$(OBJ) \ - f128M_to_i64$(OBJ) \ - f128M_to_ui32_r_minMag$(OBJ) \ - f128M_to_ui64_r_minMag$(OBJ) \ - f128M_to_i32_r_minMag$(OBJ) \ - f128M_to_i64_r_minMag$(OBJ) \ - f128M_to_f16$(OBJ) \ - f128M_to_f32$(OBJ) \ - f128M_to_f64$(OBJ) \ - f128M_to_extF80M$(OBJ) \ - f128M_roundToInt$(OBJ) \ - f128M_add$(OBJ) \ - f128M_sub$(OBJ) \ - f128M_mul$(OBJ) \ - f128M_mulAdd$(OBJ) \ - f128M_div$(OBJ) \ - f128M_rem$(OBJ) \ - f128M_sqrt$(OBJ) \ - f128M_eq$(OBJ) \ - f128M_le$(OBJ) \ - f128M_lt$(OBJ) \ - f128M_eq_signaling$(OBJ) \ - f128M_le_quiet$(OBJ) \ - f128M_lt_quiet$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) - -$(OBJS_ALL): \ - $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ - $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ - $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ - $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ - $(SOURCE_DIR)/include/softfloat.h - -$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$*.c - -$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c - $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c - -softfloat$(LIB): $(OBJS_ALL) - $(DELETE) $@ - $(MAKELIB) $^ - -.PHONY: clean -clean: - $(DELETE) $(OBJS_ALL) softfloat$(LIB) - diff --git a/softfloat/build/template-not-FAST_INT64/platform.h b/softfloat/build/template-not-FAST_INT64/platform.h deleted file mode 100644 index b63e2a7..0000000 --- a/softfloat/build/template-not-FAST_INT64/platform.h +++ /dev/null @@ -1,50 +0,0 @@ - -/*============================================================================ - -This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -// Edit lines marked with `==>'. See "SoftFloat-source.html". - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define LITTLEENDIAN 1 - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define INLINE inline - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define THREAD_LOCAL _Thread_local - diff --git a/softfloat/doc/SoftFloat-history.html b/softfloat/doc/SoftFloat-history.html deleted file mode 100644 index d81c6bc..0000000 --- a/softfloat/doc/SoftFloat-history.html +++ /dev/null @@ -1,258 +0,0 @@ - - - - -Berkeley SoftFloat History - - - - -

History of Berkeley SoftFloat, to Release 3e

- -

-John R. Hauser
-2018 January 20
-

- - -

Release 3e (2018 January)

- -
    - -
  • -Changed the default numeric code for optional rounding mode odd -(round to odd, also known as jamming) from 5 to 6. - -
  • -Modified the behavior of rounding mode odd when rounding to an -integer value (either conversion to an integer format or a -‘roundToInt’ function). -Previously, for those cases only, rounding mode odd acted the same -as rounding to minimum magnitude. -Now all operations are rounded consistently. - -
  • -Fixed some errors in the specialization code modeling Intel x86 floating-point, -specifically the integers returned on invalid operations and the propagation of -NaN payloads in a few rare cases. - -
  • -Added specialization code modeling ARM floating-point, conforming to VFPv2 or -later. - -
  • -Added an example target for ARM processors. - -
  • -Fixed a minor bug whereby function f16_to_ui64 might return a -different integer than expected in the case that the floating-point operand is -negative. - -
  • -Added example target-specific optimization for GCC, employing GCC instrinsics -and support for 128-bit integer arithmetic. - -
  • -Made other minor improvements. - -
- - -

Release 3d (2017 August)

- -
    - -
  • -Fixed bugs in the square root functions for 64-bit -double-precision, 80-bit double-extended-precision, and -128-bit quadruple-precision. -For 64-bit double-precision (f64_sqrt), the result -could sometimes be off by 1 unit in the last place -(1 ulp) from what it should be. -For the larger formats, the square root could be wrong in a large portion of -the less-significant bits. -(A bug in f128_sqrt was first reported by Alexei Sibidanov.) - -
- - -

Release 3c (2017 February)

- -
    - -
  • -Added optional rounding mode odd (round to odd, also known as -jamming). - -
  • -Corrected the documentation concerning non-canonical representations in -80-bit double-extended-precision. - -
- - -

Release 3b (2016 July)

- -
    - -
  • -Implemented the common 16-bit “half-precision” -floating-point format (float16_t). - -
  • -Made the integer values returned on invalid conversions to integer formats -be determined by the port-specific specialization instead of being the same for -all ports. - -
  • -Added preprocessor macro THREAD_LOCAL to allow the floating-point -state (modes and exception flags) to be made per-thread. - -
  • -Modified the provided Makefiles to allow some options to be overridden from the -make command. - -
  • -Made other minor improvements. - -
- - -

Release 3a (2015 October)

- -
    - -
  • -Replaced the license text supplied by the University of California, Berkeley. - -
- - -

Release 3 (2015 February)

- -
    - -
  • -Complete rewrite, funded by the University of California, Berkeley, and -consequently having a different use license than earlier releases. -Major changes included renaming most types and functions, upgrading some -algorithms, restructuring the source files, and making SoftFloat into a true -library. - -
  • -Added functions to convert between floating-point and unsigned integers, both -32-bit and 64-bit (uint32_t and -uint64_t). - -
  • -Added functions for fused multiply-add, for all supported floating-point -formats except 80-bit double-extended-precision. - -
  • -Added support for a fifth rounding mode, near_maxMag (round to -nearest, with ties to maximum magnitude, away from zero). - -
  • -Dropped the timesoftfloat program (now part of the Berkeley -TestFloat package). - -
- - -

Release 2c (2015 January)

- -
    - -
  • -Fixed mistakes affecting some 64-bit processors. - -
  • -Further improved the documentation and the wording for the legal restrictions -on using SoftFloat releases through 2c (not applicable to -Release 3 or later). - -
- - -

Release 2b (2002 May)

- -
    - -
  • -Made minor updates to the documentation, including improved wording for the -legal restrictions on using SoftFloat. - -
- - -

Release 2a (1998 December)

- -
    - -
  • -Added functions to convert between 64-bit integers -(int64) and all supported floating-point formats. - -
  • -Fixed a bug in all 64-bit-version square root functions except -float32_sqrt that caused the result sometimes to be off by -1 unit in the last place (1 ulp) from what it should -be. -(Bug discovered by Paul Donahue.) - -
  • -Improved the Makefiles. -
- - -

Release 2 (1997 June)

- -
    - -
  • -Created the 64-bit (bits64) version, adding the -floatx80 and float128 formats. - -
  • -Changed the source directory structure, splitting the sources into a -bits32 and a bits64 version. -Renamed environment.h to milieu.h to avoid confusion -with environment variables. - -
  • -Fixed a small error that caused float64_round_to_int often to -round the wrong way in nearest/even mode when the operand was between -220 and 221 and halfway between two integers. - -
- - -

Release 1a (1996 July)

- -
    - -
  • -Corrected a mistake that caused borderline underflow cases not to raise the -underflow flag when they should have. -(Problem reported by Doug Priest.) - -
  • -Added the float_detect_tininess variable to control whether -tininess is detected before or after rounding. - -
- - -

Release 1 (1996 July)

- -
    - -
  • -Original release, based on work done for the International Computer Science -Institute (ICSI) in Berkeley, California. - -
- - - - diff --git a/softfloat/doc/SoftFloat-source.html b/softfloat/doc/SoftFloat-source.html deleted file mode 100644 index 4ff9d4c..0000000 --- a/softfloat/doc/SoftFloat-source.html +++ /dev/null @@ -1,686 +0,0 @@ - - - - -Berkeley SoftFloat Source Documentation - - - - -

Berkeley SoftFloat Release 3e: Source Documentation

- -

-John R. Hauser
-2018 January 20
-

- - -

Contents

- -
- --- - - - - - - - - - - - - - - - - - - - -
1. Introduction
2. Limitations
3. Acknowledgments and License
4. SoftFloat Package Directory Structure
5. Issues for Porting SoftFloat to a New Target
5.1. Standard Headers <stdbool.h> and - <stdint.h>
5.2. Specializing Floating-Point Behavior
5.3. Macros for Build Options
5.4. Adapting a Template Target Directory
5.5. Target-Specific Optimization of Primitive Functions
6. Testing SoftFloat
7. Providing SoftFloat as a Common Library for Applications
8. Contact Information
-
- - -

1. Introduction

- -

-This document gives information needed for compiling and/or porting Berkeley -SoftFloat, a library of C functions implementing binary floating-point -conforming to the IEEE Standard for Floating-Point Arithmetic. -For basic documentation about SoftFloat refer to -SoftFloat.html. -

- -

-The source code for SoftFloat is intended to be relatively machine-independent -and should be compilable with any ISO-Standard C compiler that also supports -64-bit integers. -SoftFloat has been successfully compiled with the GNU C Compiler -(gcc) for several platforms. -

- -

-Release 3 of SoftFloat was a complete rewrite relative to -Release 2 or earlier. -Changes to the interface of SoftFloat functions are documented in -SoftFloat.html. -The current version of SoftFloat is Release 3e. -

- - -

2. Limitations

- -

-SoftFloat assumes the computer has an addressable byte size of either 8 or -16 bits. -(Nearly all computers in use today have 8-bit bytes.) -

- -

-SoftFloat is written in C and is designed to work with other C code. -The C compiler used must conform at a minimum to the 1989 ANSI standard for the -C language (same as the 1990 ISO standard) and must in addition support basic -arithmetic on 64-bit integers. -Earlier releases of SoftFloat included implementations of 32-bit -single-precision and 64-bit double-precision floating-point that -did not require 64-bit integers, but this option is not supported -starting with Release 3. -Since 1999, ISO standards for C have mandated compiler support for -64-bit integers. -A compiler conforming to the 1999 C Standard or later is recommended but not -strictly required. -

- -

-C Standard header files <stdbool.h> and -<stdint.h> are required for defining standard Boolean and -integer types. -If these headers are not supplied with the C compiler, minimal substitutes must -be provided. -SoftFloat’s dependence on these headers is detailed later in -section 5.1, Standard Headers <stdbool.h> -and <stdint.h>. -

- - -

3. Acknowledgments and License

- -

-The SoftFloat package was written by me, John R. Hauser. -Release 3 of SoftFloat was a completely new implementation -supplanting earlier releases. -The project to create Release 3 (now through 3e) was -done in the employ of the University of California, Berkeley, within the -Department of Electrical Engineering and Computer Sciences, first for the -Parallel Computing Laboratory (Par Lab) and then for the ASPIRE Lab. -The work was officially overseen by Prof. Krste Asanovic, with funding provided -by these sources: -

- ---- - - - - - - - - - -
Par Lab: -Microsoft (Award #024263), Intel (Award #024894), and U.C. Discovery -(Award #DIG07-10227), with additional support from Par Lab affiliates Nokia, -NVIDIA, Oracle, and Samsung. -
ASPIRE Lab: -DARPA PERFECT program (Award #HR0011-12-2-0016), with additional support from -ASPIRE industrial sponsor Intel and ASPIRE affiliates Google, Nokia, NVIDIA, -Oracle, and Samsung. -
-
-

- -

-The following applies to the whole of SoftFloat Release 3e as well -as to each source file individually. -

- -

-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the -University of California. -All rights reserved. -

- -

-Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: -

    - -
  1. -

    -Redistributions of source code must retain the above copyright notice, this -list of conditions, and the following disclaimer. -

    - -
  2. -

    -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions, and the following disclaimer in the documentation and/or -other materials provided with the distribution. -

    - -
  3. -

    -Neither the name of the University nor the names of its contributors may be -used to endorse or promote products derived from this software without specific -prior written permission. -

    - -
-

- -

-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS “AS IS”, -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. -IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -

- - -

4. SoftFloat Package Directory Structure

- -

-Because SoftFloat is targeted to multiple platforms, its source code is -slightly scattered between target-specific and target-independent directories -and files. -The supplied directory structure is as follows: -

-
-doc
-source
-    include
-    8086
-    8086-SSE
-    ARM-VFPv2
-    ARM-VFPv2-defaultNaN
-build
-    template-FAST_INT64
-    template-not-FAST_INT64
-    Linux-386-GCC
-    Linux-386-SSE2-GCC
-    Linux-x86_64-GCC
-    Linux-ARM-VFPv2-GCC
-    Win32-MinGW
-    Win32-SSE2-MinGW
-    Win64-MinGW-w64
-
-
-The majority of the SoftFloat sources are provided in the source -directory. -The include subdirectory contains several header files -(unsurprisingly), while the other subdirectories of source contain -source files that specialize the floating-point behavior to match particular -processor families: -
-
-
8086
-
-Intel’s older, 8087-derived floating-point, extended to all supported -floating-point types -
-
8086-SSE
-
-Intel’s x86 processors with Streaming SIMD Extensions (SSE) and later -compatible extensions, having 8087 behavior for 80-bit -double-extended-precision (extFloat80_t) and SSE behavior for -other floating-point types -
-
ARM-VFPv2
-
-ARM’s VFPv2 or later floating-point, with NaN payload propagation -
-
ARM-VFPv2-defaultNaN
-
-ARM’s VFPv2 or later floating-point, with the “default NaN” -option -
-
-
-If other specializations are attempted, these would be expected to be other -subdirectories of source alongside the ones listed above. -Specialization is covered later, in section 5.2, Specializing -Floating-Point Behavior. -

- -

-The build directory is intended to contain a subdirectory for each -target platform for which a build of the SoftFloat library may be created. -For each build target, the target’s subdirectory is where all derived -object files and the completed SoftFloat library (typically -softfloat.a or libsoftfloat.a) are created. -The two template subdirectories are not actual build targets but -contain sample files for creating new target directories. -(The meaning of FAST_INT64 will be explained later.) -

- -

-Ignoring the template directories, the supplied target directories -are intended to follow a naming system of -<execution-environment>-<compiler>. -For the example targets, -<execution-environment> is -Linux-386, Linux-386-SSE2, -Linux-x86_64, -Linux-ARM-VFPv2, Win32, -Win32-SSE2, or Win64, and -<compiler> is GCC, -MinGW, or MinGW-w64. -

- -

-All of the supplied target directories are merely examples that may or may not -be correct for compiling on any particular system. -Despite requests, there are currently no plans to include and maintain in the -SoftFloat package the build files needed for a great many users’ -compilation environments, which can span a huge range of operating systems, -compilers, and other tools. -

- -

-As supplied, each target directory contains two files: -

-
-Makefile
-platform.h
-
-
-The provided Makefile is written for GNU make. -A build of SoftFloat for the specific target is begun by executing the -make command with the target directory as the current directory. -A completely different build tool can be used if an appropriate -Makefile equivalent is created. -

- -

-The platform.h header file exists to provide a location for -additional C declarations specific to the build target. -Every C source file of SoftFloat contains a #include for -platform.h. -In many cases, the contents of platform.h can be as simple as one -or two lines of code. -At the other extreme, to get maximal performance from SoftFloat, it may be -desirable to include in header platform.h (directly or via -#include) declarations for numerous target-specific optimizations. -Such possibilities are discussed in the next section, Issues for Porting -SoftFloat to a New Target. -If the target’s compiler or library has bugs or other shortcomings, -workarounds for these issues may also be possible with target-specific -declarations in platform.h, avoiding the need to modify the main -SoftFloat sources. -

- - -

5. Issues for Porting SoftFloat to a New Target

- -

5.1. Standard Headers <stdbool.h> and <stdint.h>

- -

-The SoftFloat sources make use of standard headers -<stdbool.h> and <stdint.h>, which have -been part of the ISO C Standard Library since 1999. -With any recent compiler, these standard headers are likely to be supported, -even if the compiler does not claim complete conformance to the latest ISO C -Standard. -For older or nonstandard compilers, substitutes for -<stdbool.h> and <stdint.h> may need to be -created. -SoftFloat depends on these names from <stdbool.h>: -

-
-bool
-true
-false
-
-
-and on these names from <stdint.h>: -
-
-uint16_t
-uint32_t
-uint64_t
-int32_t
-int64_t
-UINT64_C
-INT64_C
-uint_least8_t
-uint_fast8_t
-uint_fast16_t
-uint_fast32_t
-uint_fast64_t
-int_fast8_t
-int_fast16_t
-int_fast32_t
-int_fast64_t
-
-
-

- - -

5.2. Specializing Floating-Point Behavior

- -

-The IEEE Floating-Point Standard allows for some flexibility in a conforming -implementation, particularly concerning NaNs. -The SoftFloat source directory is supplied with some -specialization subdirectories containing possible definitions for this -implementation-specific behavior. -For example, the 8086 and 8086-SSE -subdirectories have source files that specialize SoftFloat’s behavior to -match that of Intel’s x86 line of processors. -The files in a specialization subdirectory must determine: -

    -
  • -whether tininess for underflow is detected before or after rounding by default; -
  • -how signaling NaNs are distinguished from quiet NaNs; -
  • -what (if anything) special happens when exceptions are raised; -
  • -the default generated quiet NaNs; -
  • -how NaNs are propagated from function inputs to output; and -
  • -the integer results returned when conversions to integer type raise the -invalid exception. -
-

- -

-As provided, the build process for a target expects to involve exactly -one specialization directory that defines all of these -implementation-specific details for the target. -A specialization directory such as 8086 is expected to contain a -header file called specialize.h, together with whatever other -source files are needed to complete the specialization. -

- -

-A new build target may use an existing specialization, such as the ones -provided by the 8086 and 8086-SSE -subdirectories. -If a build target needs a new specialization, different from any existing ones, -it is recommended that a new specialization directory be created for this -purpose. -The specialize.h header file from any of the provided -specialization subdirectories can be used as a model for what definitions are -needed. -

- - -

5.3. Macros for Build Options

- -

-The SoftFloat source files adapt the floating-point implementation according to -several C preprocessor macros: -

-
-
LITTLEENDIAN -
-Must be defined for little-endian machines; must not be defined for big-endian -machines. -
INLINE -
-Specifies the sequence of tokens used to indicate that a C function should be -inlined. -If macro INLINE_LEVEL is defined with a value of 1 or higher, this -macro must be defined; otherwise, this macro is ignored and need not be -defined. -For compilers that conform to the C Standard’s rules for inline -functions, this macro can be defined as the single keyword inline. -For other compilers that follow a convention pre-dating the standardization of -inline, this macro may need to be defined to extern -inline. -
THREAD_LOCAL -
-Can be defined to a sequence of tokens that, when appearing at the start of a -variable declaration, indicates to the C compiler that the variable is -per-thread, meaning that each execution thread gets its own separate -instance of the variable. -This macro is used in header softfloat.h in the declarations of -variables softfloat_roundingMode, -softfloat_detectTininess, extF80_roundingPrecision, -and softfloat_exceptionFlags. -If macro THREAD_LOCAL is left undefined, these variables will -default to being ordinary global variables. -Depending on the compiler, possible valid definitions of this macro include -_Thread_local and __thread. -
-
-
SOFTFLOAT_ROUND_ODD -
-Can be defined to enable support for optional rounding mode -softfloat_round_odd. -
-
-
INLINE_LEVEL -
-Can be defined to an integer to determine the degree of inlining requested of -the compiler. -Larger numbers request that more inlining be done. -If this macro is not defined or is defined to a value less than 1 -(zero or negative), no inlining is requested. -The maximum effective value is no higher than 5. -Defining this macro to a value greater than 5 is the same as defining it -to 5. -
SOFTFLOAT_FAST_INT64 -
-Can be defined to indicate that the build target’s implementation of -64-bit arithmetic is efficient. -For newer 64-bit processors, this macro should usually be defined. -For very small microprocessors whose buses and registers are 8-bit -or 16-bit in size, this macro should usually not be defined. -Whether this macro should be defined for a 32-bit processor may -depend on the target machine and the applications that will use SoftFloat. -
SOFTFLOAT_FAST_DIV32TO16 -
-Can be defined to indicate that the target’s division operator -in C (written as /) is reasonably efficient for -dividing a 32-bit unsigned integer by a 16-bit -unsigned integer. -Setting this macro may affect the performance of function f16_div. -
SOFTFLOAT_FAST_DIV64TO32 -
-Can be defined to indicate that the target’s division operator -in C (written as /) is reasonably efficient for -dividing a 64-bit unsigned integer by a 32-bit -unsigned integer. -Setting this macro may affect the performance of division, remainder, and -square root operations other than f16_div. -
-
-

- -

-Following the usual custom for C, for most of these macros (all -except INLINE, THREAD_LOCAL, and -INLINE_LEVEL), the content of any definition is irrelevant; -what matters is a macro’s effect on #ifdef directives. -

- -

-It is recommended that any definitions of macros LITTLEENDIAN, -INLINE, and THREAD_LOCAL be made in a build -target’s platform.h header file, because these macros are -expected to be determined inflexibly by the target machine and compiler. -The other five macros select options and control optimization, and thus might -be better located in the target’s Makefile (or its equivalent). -

- - -

5.4. Adapting a Template Target Directory

- -

-In the build directory, two template subdirectories -provide models for new target directories. -Two different templates exist because different functions are needed in the -SoftFloat library depending on whether macro SOFTFLOAT_FAST_INT64 -is defined. -If macro SOFTFLOAT_FAST_INT64 will be defined, -template-FAST_INT64 is the template to use; -otherwise, template-not-FAST_INT64 is the appropriate -template. -A new target directory can be created by copying the correct template directory -and editing the files inside. -To avoid confusion, it would be wise to refrain from editing the files within a -template directory directly. -

- - -

5.5. Target-Specific Optimization of Primitive Functions

- -

-Header file primitives.h (in directory -source/include) declares macros and functions for numerous -underlying arithmetic operations upon which many of SoftFloat’s -floating-point functions are ultimately built. -The SoftFloat sources include implementations of all of these functions/macros, -written as standard C code, so a complete and correct SoftFloat library can be -created using only the supplied code for all functions. -However, for many targets, SoftFloat’s performance can be improved by -substituting target-specific implementations of some of the functions/macros -declared in primitives.h. -

- -

-For example, primitives.h declares a function called -softfloat_countLeadingZeros32 that takes an unsigned -32-bit integer as an argument and returns the number of the -integer’s most-significant bits that are zeros. -While the SoftFloat sources include an implementation of this function written -in standard C, many processors can perform this same function -directly in only one or two machine instructions. -An alternative, target-specific implementation that maps to those instructions -is likely to be more efficient than the generic C code from the SoftFloat -package. -

- -

-A build target can replace the supplied version of any function or macro of -primitives.h by defining a macro with the same name in the -target’s platform.h header file. -For this purpose, it may be helpful for platform.h to -#include header file primitiveTypes.h, which defines -types used for arguments and results of functions declared in -primitives.h. -When a desired replacement implementation is a function, not a macro, it is -sufficient for platform.h to include the line -

-
-#define <function-name> <function-name>
-
-
-where <function-name> is the name of the -function. -This technically defines <function-name> -as a macro, but one that resolves to the same name, which may then be a -function. -(A preprocessor that conforms to the C Standard is required to limit recursive -macro expansion from being applied more than once.) -

- -

-The supplied header file opts-GCC.h (in directory -source/include) provides an example of target-specific -optimization for the GCC compiler. -Each GCC target example in the build directory has -

-#include "opts-GCC.h" -
-in its platform.h header file. -Before opts-GCC.h is included, the following macros must be -defined (or not) to control which features are invoked: -
-
-
SOFTFLOAT_BUILTIN_CLZ
-
-If defined, SoftFloat’s internal -‘countLeadingZeros’ functions use intrinsics -__builtin_clz and __builtin_clzll. -
-
SOFTFLOAT_INTRINSIC_INT128
-
-If defined, SoftFloat makes use of GCC’s nonstandard 128-bit -integer type __int128. -
-
-
-On some machines, these improvements are observed to increase the speeds of -f64_mul and f128_mul by around 20 to 25%, although -other functions receive less dramatic boosts, or none at all. -Results can vary greatly across different platforms. -

- - -

6. Testing SoftFloat

- -

-SoftFloat can be tested using the testsoftfloat program by the -same author. -This program is part of the Berkeley TestFloat package available at the Web -page -http://www.jhauser.us/arithmetic/TestFloat.html. -The TestFloat package also has a program called timesoftfloat that -measures the speed of SoftFloat’s floating-point functions. -

- - -

7. Providing SoftFloat as a Common Library for Applications

- -

-Header file softfloat.h defines the SoftFloat interface as seen by -clients. -If the SoftFloat library will be made a common library for programs on a -system, the supplied softfloat.h has a couple of deficiencies for -this purpose: -

    -
  • -As supplied, softfloat.h depends on another header, -softfloat_types.h, that is not intended for public use but which -must also be visible to the programmer’s compiler. -
  • -More troubling, at the time softfloat.h is included in a C source -file, macros SOFTFLOAT_FAST_INT64 and THREAD_LOCAL -must be defined, or not defined, consistent with how these macro were defined -when the SoftFloat library was built. -
-In the situation that new programs may regularly #include header -file softfloat.h, it is recommended that a custom, self-contained -version of this header file be created that eliminates these issues. -

- - -

8. Contact Information

- -

-At the time of this writing, the most up-to-date information about SoftFloat -and the latest release can be found at the Web page -http://www.jhauser.us/arithmetic/SoftFloat.html. -

- - - - diff --git a/softfloat/doc/SoftFloat.html b/softfloat/doc/SoftFloat.html deleted file mode 100644 index 8367d6f..0000000 --- a/softfloat/doc/SoftFloat.html +++ /dev/null @@ -1,1527 +0,0 @@ - - - - -Berkeley SoftFloat Library Interface - - - - -

Berkeley SoftFloat Release 3e: Library Interface

- -

-John R. Hauser
-2018 January 20
-

- - -

Contents

- -
- --- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1. Introduction
2. Limitations
3. Acknowledgments and License
4. Types and Functions
4.1. Boolean and Integer Types
4.2. Floating-Point Types
4.3. Supported Floating-Point Functions
4.4. Non-canonical Representations in extFloat80_t
4.5. Conventions for Passing Arguments and Results
5. Reserved Names
6. Mode Variables
6.1. Rounding Mode
6.2. Underflow Detection
6.3. Rounding Precision for the 80-Bit Extended Format
7. Exceptions and Exception Flags
8. Function Details
8.1. Conversions from Integer to Floating-Point
8.2. Conversions from Floating-Point to Integer
8.3. Conversions Among Floating-Point Types
8.4. Basic Arithmetic Functions
8.5. Fused Multiply-Add Functions
8.6. Remainder Functions
8.7. Round-to-Integer Functions
8.8. Comparison Functions
8.9. Signaling NaN Test Functions
8.10. Raise-Exception Function
9. Changes from SoftFloat Release 2
9.1. Name Changes
9.2. Changes to Function Arguments
9.3. Added Capabilities
9.4. Better Compatibility with the C Language
9.5. New Organization as a Library
9.6. Optimization Gains (and Losses)
10. Future Directions
11. Contact Information
-
- - -

1. Introduction

- -

-Berkeley SoftFloat is a software implementation of binary floating-point that -conforms to the IEEE Standard for Floating-Point Arithmetic. -The current release supports five binary formats: 16-bit -half-precision, 32-bit single-precision, 64-bit -double-precision, 80-bit double-extended-precision, and -128-bit quadruple-precision. -The following functions are supported for each format: -

    -
  • -addition, subtraction, multiplication, division, and square root; -
  • -fused multiply-add as defined by the IEEE Standard, except for -80-bit double-extended-precision; -
  • -remainder as defined by the IEEE Standard; -
  • -round to integral value; -
  • -comparisons; -
  • -conversions to/from other supported formats; and -
  • -conversions to/from 32-bit and 64-bit integers, -signed and unsigned. -
-All operations required by the original 1985 version of the IEEE Floating-Point -Standard are implemented, except for conversions to and from decimal. -

- -

-This document gives information about the types defined and the routines -implemented by SoftFloat. -It does not attempt to define or explain the IEEE Floating-Point Standard. -Information about the standard is available elsewhere. -

- -

-The current version of SoftFloat is Release 3e. -This release modifies the behavior of the rarely used odd rounding mode -(round to odd, also known as jamming), and also adds some new -specialization and optimization examples for those compiling SoftFloat. -

- -

-The previous Release 3d fixed bugs that were found in the square -root functions for the 64-bit, 80-bit, and -128-bit floating-point formats. -(Thanks to Alexei Sibidanov at the University of Victoria for reporting an -incorrect result.) -The bugs affected all prior Release-3 versions of SoftFloat -through 3c. -The flaw in the 64-bit floating-point square root function was of -very minor impact, causing a 1-ulp error (1 unit in -the last place) a few times out of a billion. -The bugs in the 80-bit and 128-bit square root -functions were more serious. -Although incorrect results again occurred only a few times out of a billion, -when they did occur a large portion of the less-significant bits could be -wrong. -

- -

-Among earlier releases, 3b was notable for adding support for the -16-bit half-precision format. -For more about the evolution of SoftFloat releases, see -SoftFloat-history.html. -

- -

-The functional interface of SoftFloat Release 3 and later differs -in many details from the releases that came before. -For specifics of these differences, see section 9 below, -Changes from SoftFloat Release 2. -

- - -

2. Limitations

- -

-SoftFloat assumes the computer has an addressable byte size of 8 or -16 bits. -(Nearly all computers in use today have 8-bit bytes.) -

- -

-SoftFloat is written in C and is designed to work with other C code. -The C compiler used must conform at a minimum to the 1989 ANSI standard for the -C language (same as the 1990 ISO standard) and must in addition support basic -arithmetic on 64-bit integers. -Earlier releases of SoftFloat included implementations of 32-bit -single-precision and 64-bit double-precision floating-point that -did not require 64-bit integers, but this option is not supported -starting with Release 3. -Since 1999, ISO standards for C have mandated compiler support for -64-bit integers. -A compiler conforming to the 1999 C Standard or later is recommended but not -strictly required. -

- -

-Most operations not required by the original 1985 version of the IEEE -Floating-Point Standard but added in the 2008 version are not yet supported in -SoftFloat Release 3e. -

- - -

3. Acknowledgments and License

- -

-The SoftFloat package was written by me, John R. Hauser. -Release 3 of SoftFloat was a completely new implementation -supplanting earlier releases. -The project to create Release 3 (now through 3e) was -done in the employ of the University of California, Berkeley, within the -Department of Electrical Engineering and Computer Sciences, first for the -Parallel Computing Laboratory (Par Lab) and then for the ASPIRE Lab. -The work was officially overseen by Prof. Krste Asanovic, with funding provided -by these sources: -

- ---- - - - - - - - - - -
Par Lab: -Microsoft (Award #024263), Intel (Award #024894), and U.C. Discovery -(Award #DIG07-10227), with additional support from Par Lab affiliates Nokia, -NVIDIA, Oracle, and Samsung. -
ASPIRE Lab: -DARPA PERFECT program (Award #HR0011-12-2-0016), with additional support from -ASPIRE industrial sponsor Intel and ASPIRE affiliates Google, Nokia, NVIDIA, -Oracle, and Samsung. -
-
-

- -

-The following applies to the whole of SoftFloat Release 3e as well -as to each source file individually. -

- -

-Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the -University of California. -All rights reserved. -

- -

-Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: -

    - -
  1. -

    -Redistributions of source code must retain the above copyright notice, this -list of conditions, and the following disclaimer. -

    - -
  2. -

    -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions, and the following disclaimer in the documentation and/or -other materials provided with the distribution. -

    - -
  3. -

    -Neither the name of the University nor the names of its contributors may be -used to endorse or promote products derived from this software without specific -prior written permission. -

    - -
-

- -

-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS “AS IS”, -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. -IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -

- - -

4. Types and Functions

- -

-The types and functions of SoftFloat are declared in header file -softfloat.h. -

- -

4.1. Boolean and Integer Types

- -

-Header file softfloat.h depends on standard headers -<stdbool.h> and <stdint.h> to define type -bool and several integer types. -These standard headers have been part of the ISO C Standard Library since 1999. -With any recent compiler, they are likely to be supported, even if the compiler -does not claim complete conformance to the latest ISO C Standard. -For older or nonstandard compilers, a port of SoftFloat may have substitutes -for these headers. -Header softfloat.h depends only on the name bool from -<stdbool.h> and on these type names from -<stdint.h>: -

-
-uint16_t
-uint32_t
-uint64_t
-int32_t
-int64_t
-uint_fast8_t
-uint_fast32_t
-uint_fast64_t
-int_fast32_t
-int_fast64_t
-
-
-

- - -

4.2. Floating-Point Types

- -

-The softfloat.h header defines five floating-point types: -

- - - - - - - - - - - - - - - - - - - - - -
float16_t16-bit half-precision binary format
float32_t32-bit single-precision binary format
float64_t64-bit double-precision binary format
extFloat80_t   80-bit double-extended-precision binary format (old Intel or -Motorola format)
float128_t128-bit quadruple-precision binary format
-
-The non-extended types are each exactly the size specified: -16 bits for float16_t, 32 bits for -float32_t, 64 bits for float64_t, and -128 bits for float128_t. -Aside from these size requirements, the definitions of all these types may -differ for different ports of SoftFloat to specific systems. -A given port of SoftFloat may or may not define some of the floating-point -types as aliases for the C standard types float, -double, and long double. -

- -

-Header file softfloat.h also defines a structure, -struct extFloat80M, for the representation of -80-bit double-extended-precision floating-point values in memory. -This structure is the same size as type extFloat80_t and contains -at least these two fields (not necessarily in this order): -

-
-uint16_t signExp;
-uint64_t signif;
-
-
-Field signExp contains the sign and exponent of the floating-point -value, with the sign in the most significant bit (bit 15) and the -encoded exponent in the other 15 bits. -Field signif is the complete 64-bit significand of -the floating-point value. -(In the usual encoding for 80-bit extended floating-point, the -leading 1 bit of normalized numbers is not implicit but is stored -in the most significant bit of the significand.) -

- -

4.3. Supported Floating-Point Functions

- -

-SoftFloat implements these arithmetic operations for its floating-point types: -

    -
  • -conversions between any two floating-point formats; -
  • -for each floating-point format, conversions to and from signed and unsigned -32-bit and 64-bit integers; -
  • -for each format, the usual addition, subtraction, multiplication, division, and -square root operations; -
  • -for each format except extFloat80_t, the fused multiply-add -operation defined by the IEEE Standard; -
  • -for each format, the floating-point remainder operation defined by the IEEE -Standard; -
  • -for each format, a “round to integer” operation that rounds to the -nearest integer value in the same format; and -
  • -comparisons between two values in the same floating-point format. -
-

- -

-The following operations required by the 2008 IEEE Floating-Point Standard are -not supported in SoftFloat Release 3e: -

    -
  • -nextUp, nextDown, minNum, maxNum, minNumMag, -maxNumMag, scaleB, and logB; -
  • -conversions between floating-point formats and decimal or hexadecimal character -sequences; -
  • -all “quiet-computation” operations (copy, negate, -abs, and copySign, which all involve only simple copying and/or -manipulation of the floating-point sign bit); and -
  • -all “non-computational” operations other than isSignaling -(which is supported). -
-

- -

4.4. Non-canonical Representations in extFloat80_t

- -

-Because the 80-bit double-extended-precision format, -extFloat80_t, stores an explicit leading significand bit, many -finite floating-point numbers are encodable in this type in multiple equivalent -forms. -Of these multiple encodings, there is always a unique one with the least -encoded exponent value, and this encoding is considered the canonical -representation of the floating-point number. -Any other equivalent representations (having a higher encoded exponent value) -are non-canonical. -For a value in the subnormal range (including zero), the canonical -representation always has an encoded exponent of zero and a leading significand -bit of 0. -For finite values outside the subnormal range, the canonical representation -always has an encoded exponent that is nonzero and a leading significand bit -of 1. -

- -

-For an infinity or NaN, the leading significand bit is similarly expected to -be 1. -An infinity or NaN with a leading significand bit of 0 is again -considered non-canonical. -Hence, altogether, to be canonical, a value of type extFloat80_t -must have a leading significand bit of 1, unless the value is -subnormal or zero, in which case the leading significand bit and the encoded -exponent must both be zero. -

- -

-SoftFloat’s functions are not guaranteed to operate as expected when -inputs of type extFloat80_t are non-canonical. -Assuming all of a function’s extFloat80_t inputs (if any) -are canonical, function outputs of type extFloat80_t will always -be canonical. -

- -

4.5. Conventions for Passing Arguments and Results

- -

-Values that are at most 64 bits in size (i.e., not the -80-bit or 128-bit floating-point formats) are in all -cases passed as function arguments by value. -Likewise, when an output of a function is no more than 64 bits, it -is always returned directly as the function result. -Thus, for example, the SoftFloat function for adding two 64-bit -floating-point values has this simple signature: -

-float64_t f64_add( float64_t, float64_t ); -
-

- -

-The story is more complex when function inputs and outputs are -80-bit and 128-bit floating-point. -For these types, SoftFloat always provides a function that passes these larger -values into or out of the function indirectly, via pointers. -For example, for adding two 128-bit floating-point values, -SoftFloat supplies this function: -

-void f128M_add( const float128_t *, const float128_t *, float128_t * ); -
-The first two arguments point to the values to be added, and the last argument -points to the location where the sum will be stored. -The M in the name f128M_add is mnemonic for the fact -that the 128-bit inputs and outputs are “in memory”, -pointed to by pointer arguments. -

- -

-All ports of SoftFloat implement these pass-by-pointer functions for -types extFloat80_t and float128_t. -At the same time, SoftFloat ports may also implement alternate versions of -these same functions that pass extFloat80_t and -float128_t by value, like the smaller formats. -Thus, besides the function with name f128M_add shown above, a -SoftFloat port may also supply an equivalent function with this signature: -

-float128_t f128_add( float128_t, float128_t ); -
-

- -

-As a general rule, on computers where the machine word size is -32 bits or smaller, only the pass-by-pointer versions of functions -(e.g., f128M_add) are provided for types extFloat80_t -and float128_t, because passing such large types directly can have -significant extra cost. -On computers where the word size is 64 bits or larger, both -function versions (f128M_add and f128_add) are -provided, because the cost of passing by value is then more reasonable. -Applications that must be portable across both classes of computers must use -the pointer-based functions, as these are always implemented. -However, if it is known that SoftFloat includes the by-value functions for all -platforms of interest, programmers can use whichever version they prefer. -

- - -

5. Reserved Names

- -

-In addition to the variables and functions documented here, SoftFloat defines -some symbol names for its own private use. -These private names always begin with the prefix -‘softfloat_’. -When a program includes header softfloat.h or links with the -SoftFloat library, all names with prefix ‘softfloat_’ -are reserved for possible use by SoftFloat. -Applications that use SoftFloat should not define their own names with this -prefix, and should reference only such names as are documented. -

- - -

6. Mode Variables

- -

-The following global variables control rounding mode, underflow detection, and -the 80-bit extended format’s rounding precision: -

-softfloat_roundingMode
-softfloat_detectTininess
-extF80_roundingPrecision -
-These mode variables are covered in the next several subsections. -For some SoftFloat ports, these variables may be per-thread (declared -thread_local), meaning that different execution threads have their -own separate copies of the variables. -

- -

6.1. Rounding Mode

- -

-All five rounding modes defined by the 2008 IEEE Floating-Point Standard are -implemented for all operations that require rounding. -Some ports of SoftFloat may also implement the round-to-odd mode. -

- -

-The rounding mode is selected by the global variable -

-uint_fast8_t softfloat_roundingMode; -
-This variable may be set to one of the values -
- - - - - - - - - - - - - - - - - - - - - - - - - -
softfloat_round_near_evenround to nearest, with ties to even
softfloat_round_near_maxMag  round to nearest, with ties to maximum magnitude (away from zero)
softfloat_round_minMaground to minimum magnitude (toward zero)
softfloat_round_minround to minimum (down)
softfloat_round_maxround to maximum (up)
softfloat_round_oddround to odd (jamming), if supported by the SoftFloat port
-
-Variable softfloat_roundingMode is initialized to -softfloat_round_near_even. -

- -

-When softfloat_round_odd is the rounding mode for a function that -rounds to an integer value (either conversion to an integer format or a -‘roundToInt’ function), if the input is not already an -integer, the rounded result is the closest odd integer. -For other operations, this rounding mode acts as though the floating-point -result is first rounded to minimum magnitude, the same as -softfloat_round_minMag, and then, if the result is inexact, the -least-significant bit of the result is set to 1. -Rounding to odd is also known as jamming. -

- -

6.2. Underflow Detection

- -

-In the terminology of the IEEE Standard, SoftFloat can detect tininess for -underflow either before or after rounding. -The choice is made by the global variable -

-uint_fast8_t softfloat_detectTininess; -
-which can be set to either -
-softfloat_tininess_beforeRounding
-softfloat_tininess_afterRounding -
-Detecting tininess after rounding is usually better because it results in fewer -spurious underflow signals. -The other option is provided for compatibility with some systems. -Like most systems (and as required by the newer 2008 IEEE Standard), SoftFloat -always detects loss of accuracy for underflow as an inexact result. -

- -

6.3. Rounding Precision for the 80-Bit Extended Format

- -

-For extFloat80_t only, the rounding precision of the basic -arithmetic operations is controlled by the global variable -

-uint_fast8_t extF80_roundingPrecision; -
-The operations affected are: -
-extF80_add
-extF80_sub
-extF80_mul
-extF80_div
-extF80_sqrt -
-When extF80_roundingPrecision is set to its default value of 80, -these operations are rounded to the full precision of the 80-bit -double-extended-precision format, like occurs for other formats. -Setting extF80_roundingPrecision to 32 or to 64 causes the -operations listed to be rounded to 32-bit precision (equivalent to -float32_t) or to 64-bit precision (equivalent to -float64_t), respectively. -When rounding to reduced precision, additional bits in the result significand -beyond the rounding point are set to zero. -The consequences of setting extF80_roundingPrecision to a value -other than 32, 64, or 80 is not specified. -Operations other than the ones listed above are not affected by -extF80_roundingPrecision. -

- - -

7. Exceptions and Exception Flags

- -

-All five exception flags required by the IEEE Floating-Point Standard are -implemented. -Each flag is stored as a separate bit in the global variable -

-uint_fast8_t softfloat_exceptionFlags; -
-The positions of the exception flag bits within this variable are determined by -the bit masks -
-softfloat_flag_inexact
-softfloat_flag_underflow
-softfloat_flag_overflow
-softfloat_flag_infinite
-softfloat_flag_invalid -
-Variable softfloat_exceptionFlags is initialized to all zeros, -meaning no exceptions. -

- -

-For some SoftFloat ports, softfloat_exceptionFlags may be -per-thread (declared thread_local), meaning that different -execution threads have their own separate instances of it. -

- -

-An individual exception flag can be cleared with the statement -

-softfloat_exceptionFlags &= ~softfloat_flag_<exception>; -
-where <exception> is the appropriate name. -To raise a floating-point exception, function softfloat_raiseFlags -should normally be used. -

- -

-When SoftFloat detects an exception other than inexact, it calls -softfloat_raiseFlags. -The default version of this function simply raises the corresponding exception -flags. -Particular ports of SoftFloat may support alternate behavior, such as exception -traps, by modifying the default softfloat_raiseFlags. -A program may also supply its own softfloat_raiseFlags function to -override the one from the SoftFloat library. -

- -

-Because inexact results occur frequently under most circumstances (and thus are -hardly exceptional), SoftFloat does not ordinarily call -softfloat_raiseFlags for inexact exceptions. -It does always raise the inexact exception flag as required. -

- - -

8. Function Details

- -

-In this section, <float> appears in function names as -a substitute for one of these abbreviations: -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
f16indicates float16_t, passed by value
f32indicates float32_t, passed by value
f64indicates float64_t, passed by value
extF80M   indicates extFloat80_t, passed indirectly via pointers
extF80indicates extFloat80_t, passed by value
f128Mindicates float128_t, passed indirectly via pointers
f128indicates float128_t, passed by value
-
-The circumstances under which values of floating-point types -extFloat80_t and float128_t may be passed either by -value or indirectly via pointers was discussed earlier in -section 4.5, Conventions for Passing Arguments and Results. -

- -

8.1. Conversions from Integer to Floating-Point

- -

-All conversions from a 32-bit or 64-bit integer, -signed or unsigned, to a floating-point format are supported. -Functions performing these conversions have these names: -

-ui32_to_<float>
-ui64_to_<float>
-i32_to_<float>
-i64_to_<float> -
-Conversions from 32-bit integers to 64-bit -double-precision and larger formats are always exact, and likewise conversions -from 64-bit integers to 80-bit -double-extended-precision and 128-bit quadruple-precision are also -always exact. -

- -

-Each conversion function takes one input of the appropriate type and generates -one output. -The following illustrates the signatures of these functions in cases when the -floating-point result is passed either by value or via pointers: -

-
-float64_t i32_to_f64( int32_t a );
-
-
-void i32_to_f128M( int32_t a, float128_t *destPtr );
-
-
-

- -

8.2. Conversions from Floating-Point to Integer

- -

-Conversions from a floating-point format to a 32-bit or -64-bit integer, signed or unsigned, are supported with these -functions: -

-<float>_to_ui32
-<float>_to_ui64
-<float>_to_i32
-<float>_to_i64 -
-The functions have signatures as follows, depending on whether the -floating-point input is passed by value or via pointers: -
-
-int_fast32_t f64_to_i32( float64_t a, uint_fast8_t roundingMode, bool exact );
-
-
-int_fast32_t
- f128M_to_i32( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact );
-
-
-

- -

-The roundingMode argument specifies the rounding mode for -the conversion. -The variable that usually indicates rounding mode, -softfloat_roundingMode, is ignored. -Argument exact determines whether the inexact -exception flag is raised if the conversion is not exact. -If exact is true, the inexact flag may -be raised; -otherwise, it will not be, even if the conversion is inexact. -

- -

-A conversion from floating-point to integer format raises the invalid -exception if the source value cannot be rounded to a representable integer of -the desired size (32 or 64 bits). -In such circumstances, the integer result returned is determined by the -particular port of SoftFloat, although typically this value will be either the -maximum or minimum value of the integer format. -The functions that convert to integer types never raise the floating-point -overflow exception. -

- -

-Because languages such as C require that conversions to integers -be rounded toward zero, the following functions are provided for improved speed -and convenience: -

-<float>_to_ui32_r_minMag
-<float>_to_ui64_r_minMag
-<float>_to_i32_r_minMag
-<float>_to_i64_r_minMag -
-These functions round only toward zero (to minimum magnitude). -The signatures for these functions are the same as above without the redundant -roundingMode argument: -
-
-int_fast32_t f64_to_i32_r_minMag( float64_t a, bool exact );
-
-
-int_fast32_t f128M_to_i32_r_minMag( const float128_t *aPtr, bool exact );
-
-
-

- -

8.3. Conversions Among Floating-Point Types

- -

-Conversions between floating-point formats are done by functions with these -names: -

-<float>_to_<float> -
-All combinations of source and result type are supported where the source and -result are different formats. -There are four different styles of signature for these functions, depending on -whether the input and the output floating-point values are passed by value or -via pointers: -
-
-float32_t f64_to_f32( float64_t a );
-
-
-float32_t f128M_to_f32( const float128_t *aPtr );
-
-
-void f32_to_f128M( float32_t a, float128_t *destPtr );
-
-
-void extF80M_to_f128M( const extFloat80_t *aPtr, float128_t *destPtr );
-
-
-

- -

-Conversions from a smaller to a larger floating-point format are always exact -and so require no rounding. -

- -

8.4. Basic Arithmetic Functions

- -

-The following basic arithmetic functions are provided: -

-<float>_add
-<float>_sub
-<float>_mul
-<float>_div
-<float>_sqrt -
-Each floating-point operation takes two operands, except for sqrt -(square root) which takes only one. -The operands and result are all of the same floating-point format. -Signatures for these functions take the following forms: -
-
-float64_t f64_add( float64_t a, float64_t b );
-
-
-void
- f128M_add(
-     const float128_t *aPtr, const float128_t *bPtr, float128_t *destPtr );
-
-
-float64_t f64_sqrt( float64_t a );
-
-
-void f128M_sqrt( const float128_t *aPtr, float128_t *destPtr );
-
-
-When floating-point values are passed indirectly through pointers, arguments -aPtr and bPtr point to the input -operands, and the last argument, destPtr, points to the -location where the result is stored. -

- -

-Rounding of the 80-bit double-extended-precision -(extFloat80_t) functions is affected by variable -extF80_roundingPrecision, as explained earlier in -section 6.3, -Rounding Precision for the 80-Bit Extended Format. -

- -

8.5. Fused Multiply-Add Functions

- -

-The 2008 version of the IEEE Floating-Point Standard defines a fused -multiply-add operation that does a combined multiplication and addition -with only a single rounding. -SoftFloat implements fused multiply-add with functions -

-<float>_mulAdd -
-Unlike other operations, fused multiple-add is not supported for the -80-bit double-extended-precision format, -extFloat80_t. -

- -

-Depending on whether floating-point values are passed by value or via pointers, -the fused multiply-add functions have signatures of these forms: -

-
-float64_t f64_mulAdd( float64_t a, float64_t b, float64_t c );
-
-
-void
- f128M_mulAdd(
-     const float128_t *aPtr,
-     const float128_t *bPtr,
-     const float128_t *cPtr,
-     float128_t *destPtr
- );
-
-
-The functions compute -(a × b) - + c -with a single rounding. -When floating-point values are passed indirectly through pointers, arguments -aPtr, bPtr, and -cPtr point to operands a, -b, and c respectively, and -destPtr points to the location where the result is stored. -

- -

-If one of the multiplication operands a and -b is infinite and the other is zero, these functions raise -the invalid exception even if operand c is a quiet NaN. -

- -

8.6. Remainder Functions

- -

-For each format, SoftFloat implements the remainder operation defined by the -IEEE Floating-Point Standard. -The remainder functions have names -

-<float>_rem -
-Each remainder operation takes two floating-point operands of the same format -and returns a result in the same format. -Depending on whether floating-point values are passed by value or via pointers, -the remainder functions have signatures of these forms: -
-
-float64_t f64_rem( float64_t a, float64_t b );
-
-
-void
- f128M_rem(
-     const float128_t *aPtr, const float128_t *bPtr, float128_t *destPtr );
-
-
-When floating-point values are passed indirectly through pointers, arguments -aPtr and bPtr point to operands -a and b respectively, and -destPtr points to the location where the result is stored. -

- -

-The IEEE Standard remainder operation computes the value -a - − n × b, -where n is the integer closest to -a ÷ b. -If a ÷ b is exactly -halfway between two integers, n is the even integer closest to -a ÷ b. -The IEEE Standard’s remainder operation is always exact and so requires -no rounding. -

- -

-Depending on the relative magnitudes of the operands, the remainder -functions can take considerably longer to execute than the other SoftFloat -functions. -This is an inherent characteristic of the remainder operation itself and is not -a flaw in the SoftFloat implementation. -

- -

8.7. Round-to-Integer Functions

- -

-For each format, SoftFloat implements the round-to-integer operation specified -by the IEEE Floating-Point Standard. -These functions are named -

-<float>_roundToInt -
-Each round-to-integer operation takes a single floating-point operand. -This operand is rounded to an integer according to a specified rounding mode, -and the resulting integer value is returned in the same floating-point format. -(Note that the result is not an integer type.) -

- -

-The signatures of the round-to-integer functions are similar to those for -conversions to an integer type: -

-
-float64_t f64_roundToInt( float64_t a, uint_fast8_t roundingMode, bool exact );
-
-
-void
- f128M_roundToInt(
-     const float128_t *aPtr,
-     uint_fast8_t roundingMode,
-     bool exact,
-     float128_t *destPtr
- );
-
-
-When floating-point values are passed indirectly through pointers, -aPtr points to the input operand and -destPtr points to the location where the result is stored. -

- -

-The roundingMode argument specifies the rounding mode to -apply. -The variable that usually indicates rounding mode, -softfloat_roundingMode, is ignored. -Argument exact determines whether the inexact -exception flag is raised if the conversion is not exact. -If exact is true, the inexact flag may -be raised; -otherwise, it will not be, even if the conversion is inexact. -

- -

8.8. Comparison Functions

- -

-For each format, the following floating-point comparison functions are -provided: -

-<float>_eq
-<float>_le
-<float>_lt -
-Each comparison takes two operands of the same type and returns a Boolean. -The abbreviation eq stands for “equal” (=); -le stands for “less than or equal” (≤); -and lt stands for “less than” (<). -Depending on whether the floating-point operands are passed by value or via -pointers, the comparison functions have signatures of these forms: -
-
-bool f64_eq( float64_t a, float64_t b );
-
-
-bool f128M_eq( const float128_t *aPtr, const float128_t *bPtr );
-
-
-

- -

-The usual greater-than (>), greater-than-or-equal (≥), and not-equal -(≠) comparisons are easily obtained from the functions provided. -The not-equal function is just the logical complement of the equal function. -The greater-than-or-equal function is identical to the less-than-or-equal -function with the arguments in reverse order, and likewise the greater-than -function is identical to the less-than function with the arguments reversed. -

- -

-The IEEE Floating-Point Standard specifies that the less-than-or-equal and -less-than comparisons by default raise the invalid exception if either -operand is any kind of NaN. -Equality comparisons, on the other hand, are defined by default to raise the -invalid exception only for signaling NaNs, not quiet NaNs. -For completeness, SoftFloat provides these complementary functions: -

-<float>_eq_signaling
-<float>_le_quiet
-<float>_lt_quiet -
-The signaling equality comparisons are identical to the default -equality comparisons except that the invalid exception is raised for any -NaN input, not just for signaling NaNs. -Similarly, the quiet comparison functions are identical to their -default counterparts except that the invalid exception is not raised for -quiet NaNs. -

- -

8.9. Signaling NaN Test Functions

- -

-Functions for testing whether a floating-point value is a signaling NaN are -provided with these names: -

-<float>_isSignalingNaN -
-The functions take one floating-point operand and return a Boolean indicating -whether the operand is a signaling NaN. -Accordingly, the functions have the forms -
-
-bool f64_isSignalingNaN( float64_t a );
-
-
-bool f128M_isSignalingNaN( const float128_t *aPtr );
-
-
-

- -

8.10. Raise-Exception Function

- -

-SoftFloat provides a single function for raising floating-point exceptions: -

-
-void softfloat_raiseFlags( uint_fast8_t exceptions );
-
-
-The exceptions argument is a mask indicating the set of -exceptions to raise. -(See earlier section 7, Exceptions and Exception Flags.) -In addition to setting the specified exception flags in variable -softfloat_exceptionFlags, the softfloat_raiseFlags -function may cause a trap or abort appropriate for the current system. -

- - -

9. Changes from SoftFloat Release 2

- -

-Apart from a change in the legal use license, Release 3 of -SoftFloat introduced numerous technical differences compared to earlier -releases. -

- -

9.1. Name Changes

- -

-The most obvious and pervasive difference compared to Release 2 -is that the names of most functions and variables have changed, even when the -behavior has not. -First, the floating-point types, the mode variables, the exception flags -variable, the function to raise exceptions, and various associated constants -have been renamed as follows: -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
old name, Release 2:new name, Release 3:
float32float32_t
float64float64_t
floatx80extFloat80_t
float128float128_t
float_rounding_modesoftfloat_roundingMode
float_round_nearest_evensoftfloat_round_near_even
float_round_to_zerosoftfloat_round_minMag
float_round_downsoftfloat_round_min
float_round_upsoftfloat_round_max
float_detect_tininesssoftfloat_detectTininess
float_tininess_before_rounding    softfloat_tininess_beforeRounding
float_tininess_after_roundingsoftfloat_tininess_afterRounding
floatx80_rounding_precisionextF80_roundingPrecision
float_exception_flagssoftfloat_exceptionFlags
float_flag_inexactsoftfloat_flag_inexact
float_flag_underflowsoftfloat_flag_underflow
float_flag_overflowsoftfloat_flag_overflow
float_flag_divbyzerosoftfloat_flag_infinite
float_flag_invalidsoftfloat_flag_invalid
float_raisesoftfloat_raiseFlags
-
-

- -

-Furthermore, Release 3 adopted the following new abbreviations for -function names: -

- - - - - - - - - - - -
used in names in Release 2:    used in names in Release 3:
int32 i32
int64 i64
float32 f32
float64 f64
floatx80 extF80
float128 f128
-
-Thus, for example, the function to add two 32-bit floating-point -numbers, previously called float32_add in Release 2, -is now f32_add. -Lastly, there have been a few other changes to function names: -
- - - - - - - - - - - - - - - - - - - - - -
used in names in Release 2:   used in names in Release 3:   relevant functions:
_round_to_zero_r_minMagconversions from floating-point to integer (section 8.2)
round_to_introundToIntround-to-integer functions (section 8.7)
is_signaling_nan    isSignalingNaNsignaling NaN test functions (section 8.9)
-
-

- -

9.2. Changes to Function Arguments

- -

-Besides simple name changes, some operations were given a different interface -in Release 3 than they had in Release 2: -

    - -
  • -

    -Since Release 3, integer arguments and results of functions have -standard types from header <stdint.h>, such as -uint32_t, whereas previously their types could be defined -differently for each port of SoftFloat, usually using traditional C types such -as unsigned int. -Likewise, functions in Release 3 and later pass Booleans as -standard type bool from <stdbool.h>, whereas -previously these were again passed as a port-specific type (usually -int). -

    - -
  • -

    -As explained earlier in section 4.5, Conventions for Passing -Arguments and Results, SoftFloat functions in Release 3 and -later may pass 80-bit and 128-bit floating-point -values through pointers, meaning that functions take pointer arguments and then -read or write floating-point values at the locations indicated by the pointers. -In Release 2, floating-point arguments and results were always -passed by value, regardless of their size. -

    - -
  • -

    -Functions that round to an integer have additional -roundingMode and exact arguments that -they did not have in Release 2. -Refer to sections 8.2 and 8.7 for descriptions of these functions -since Release 3. -For Release 2, the rounding mode, when needed, was taken from the -same global variable that affects the basic arithmetic operations (now called -softfloat_roundingMode but previously known as -float_rounding_mode). -Also, for Release 2, if the original floating-point input was not -an exact integer value, and if the invalid exception was not raised by -the function, the inexact exception was always raised. -Release 2 had no option to suppress raising inexact in this -case. -Applications using SoftFloat Release 3 or later can get the same -effect as Release 2 by passing variable -softfloat_roundingMode for argument -roundingMode and true for argument -exact. -

    - -
-

- -

9.3. Added Capabilities

- -

-With Release 3, some new features have been added that were not -present in Release 2: -

    - -
  • -

    -A port of SoftFloat can now define any of the floating-point types -float32_t, float64_t, extFloat80_t, and -float128_t as aliases for C’s standard floating-point types -float, double, and long -double, using either #define or typedef. -This potential convenience was not supported under Release 2. -

    - -

    -(Note, however, that there may be a performance cost to defining -SoftFloat’s floating-point types this way, depending on the platform and -the applications using SoftFloat. -Ports of SoftFloat may choose to forgo the convenience in favor of better -speed.) -

    - -

    -

  • -As of Release 3b, 16-bit half-precision, -float16_t, is supported. -

    - -

    -

  • -Functions have been added for converting between the floating-point types and -unsigned integers. -Release 2 supported only signed integers, not unsigned. -

    - -

    -

  • -Fused multiply-add functions have been added for all floating-point formats -except 80-bit double-extended-precision, -extFloat80_t. -

    - -

    -

  • -New rounding modes are supported: -softfloat_round_near_maxMag (round to nearest, with ties to -maximum magnitude, away from zero), and, as of Release 3c, -optional softfloat_round_odd (round to odd, also known as -jamming). -

    - -
-

- -

9.4. Better Compatibility with the C Language

- -

-Release 3 of SoftFloat was written to conform better to the ISO C -Standard’s rules for portability. -For example, older releases of SoftFloat employed type conversions in ways -that, while commonly practiced, are not fully defined by the C Standard. -Such problematic type conversions have generally been replaced by the use of -unions, the behavior around which is more strictly regulated these days. -

- -

9.5. New Organization as a Library

- -

-Starting with Release 3, SoftFloat now builds as a library. -Previously, SoftFloat compiled into a single, monolithic object file containing -all the SoftFloat functions, with the consequence that a program linking with -SoftFloat would get every SoftFloat function in its binary file even if only a -few functions were actually used. -With SoftFloat in the form of a library, a program that is linked by a standard -linker will include only those functions of SoftFloat that it needs and no -others. -

- -

9.6. Optimization Gains (and Losses)

- -

-Individual SoftFloat functions have been variously improved in -Release 3 compared to earlier releases. -In particular, better, faster algorithms have been deployed for the operations -of division, square root, and remainder. -For functions operating on the larger 80-bit and -128-bit formats, extFloat80_t and -float128_t, code size has also generally been reduced. -

- -

-However, because Release 2 compiled all of SoftFloat together as a -single object file, compilers could make optimizations across function calls -when one SoftFloat function calls another. -Now that the functions of SoftFloat are compiled separately and only afterward -linked together into a program, there is not usually the same opportunity to -optimize across function calls. -Some loss of speed has been observed due to this change. -

- - -

10. Future Directions

- -

-The following improvements are anticipated for future releases of SoftFloat: -

    -
  • -more functions from the 2008 version of the IEEE Floating-Point Standard; -
  • -consistent, defined behavior for non-canonical representations of extended -format extFloat80_t (discussed in section 4.4, -Non-canonical Representations in extFloat80_t). - -
-

- - -

11. Contact Information

- -

-At the time of this writing, the most up-to-date information about SoftFloat -and the latest release can be found at the Web page -http://www.jhauser.us/arithmetic/SoftFloat.html. -

- - - - diff --git a/softfloat/source/8086-SSE/extF80M_isSignalingNaN.c b/softfloat/source/8086-SSE/extF80M_isSignalingNaN.c deleted file mode 100644 index 85ee211..0000000 --- a/softfloat/source/8086-SSE/extF80M_isSignalingNaN.c +++ /dev/null @@ -1,57 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool extF80M_isSignalingNaN( const extFloat80_t *aPtr ) -{ - const struct extFloat80M *aSPtr; - uint64_t uiA0; - - aSPtr = (const struct extFloat80M *) aPtr; - if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false; - uiA0 = aSPtr->signif; - return - ! (uiA0 & UINT64_C( 0x4000000000000000 )) - && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF)); - -} - diff --git a/softfloat/source/8086-SSE/f128M_isSignalingNaN.c b/softfloat/source/8086-SSE/f128M_isSignalingNaN.c deleted file mode 100644 index 79a7077..0000000 --- a/softfloat/source/8086-SSE/f128M_isSignalingNaN.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "primitives.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool f128M_isSignalingNaN( const float128_t *aPtr ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false; - return - ((uiA96 & 0x00007FFF) != 0) - || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )]) - != 0); - -} - diff --git a/softfloat/source/8086-SSE/s_bf16UIToCommonNaN.c b/softfloat/source/8086-SSE/s_bf16UIToCommonNaN.c deleted file mode 100644 index c1c774d..0000000 --- a/softfloat/source/8086-SSE/s_bf16UIToCommonNaN.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming `uiA' has the bit pattern of a BF16 NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_bf16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNBF16UI( uiA ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA>>15; - zPtr->v64 = (uint_fast64_t) uiA<<56; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086-SSE/s_commonNaNToBF16UI.c b/softfloat/source/8086-SSE/s_commonNaNToBF16UI.c deleted file mode 100644 index d81cf51..0000000 --- a/softfloat/source/8086-SSE/s_commonNaNToBF16UI.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a BF16 NaN, and -| returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToBF16UI( const struct commonNaN *aPtr ) -{ - - return (uint_fast16_t) aPtr->sign<<15 | 0x7FC0 | aPtr->v64>>56; - -} - diff --git a/softfloat/source/8086-SSE/s_commonNaNToExtF80M.c b/softfloat/source/8086-SSE/s_commonNaNToExtF80M.c deleted file mode 100644 index 3405b3b..0000000 --- a/softfloat/source/8086-SSE/s_commonNaNToExtF80M.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into an 80-bit extended -| floating-point NaN, and stores this NaN at the location pointed to by -| `zSPtr'. -*----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ) -{ - - zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF ); - zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1; - -} - diff --git a/softfloat/source/8086-SSE/s_commonNaNToExtF80UI.c b/softfloat/source/8086-SSE/s_commonNaNToExtF80UI.c deleted file mode 100644 index cb7424f..0000000 --- a/softfloat/source/8086-SSE/s_commonNaNToExtF80UI.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into an 80-bit extended -| floating-point NaN, and returns the bit pattern of this value as an unsigned -| integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ) -{ - struct uint128 uiZ; - - uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF; - uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1; - return uiZ; - -} - diff --git a/softfloat/source/8086-SSE/s_commonNaNToF128M.c b/softfloat/source/8086-SSE/s_commonNaNToF128M.c deleted file mode 100644 index e7ea802..0000000 --- a/softfloat/source/8086-SSE/s_commonNaNToF128M.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point -| NaN, and stores this NaN at the location pointed to by `zWPtr'. Argument -| `zWPtr' points to an array of four 32-bit elements that concatenate in the -| platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ) -{ - - softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr ); - zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000; - -} - diff --git a/softfloat/source/8086-SSE/s_commonNaNToF128UI.c b/softfloat/source/8086-SSE/s_commonNaNToF128UI.c deleted file mode 100644 index 7a9423b..0000000 --- a/softfloat/source/8086-SSE/s_commonNaNToF128UI.c +++ /dev/null @@ -1,55 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr ) -{ - struct uint128 uiZ; - - uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 ); - uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 ); - return uiZ; - -} - diff --git a/softfloat/source/8086-SSE/s_commonNaNToF16UI.c b/softfloat/source/8086-SSE/s_commonNaNToF16UI.c deleted file mode 100644 index d4e458a..0000000 --- a/softfloat/source/8086-SSE/s_commonNaNToF16UI.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 16-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ) -{ - - return (uint_fast16_t) aPtr->sign<<15 | 0x7E00 | aPtr->v64>>54; - -} - diff --git a/softfloat/source/8086-SSE/s_commonNaNToF32UI.c b/softfloat/source/8086-SSE/s_commonNaNToF32UI.c deleted file mode 100644 index ed6c226..0000000 --- a/softfloat/source/8086-SSE/s_commonNaNToF32UI.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ) -{ - - return (uint_fast32_t) aPtr->sign<<31 | 0x7FC00000 | aPtr->v64>>41; - -} - diff --git a/softfloat/source/8086-SSE/s_commonNaNToF64UI.c b/softfloat/source/8086-SSE/s_commonNaNToF64UI.c deleted file mode 100644 index 1182be3..0000000 --- a/softfloat/source/8086-SSE/s_commonNaNToF64UI.c +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ) -{ - - return - (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FF8000000000000 ) - | aPtr->v64>>12; - -} - diff --git a/softfloat/source/8086-SSE/s_extF80MToCommonNaN.c b/softfloat/source/8086-SSE/s_extF80MToCommonNaN.c deleted file mode 100644 index 00baf35..0000000 --- a/softfloat/source/8086-SSE/s_extF80MToCommonNaN.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the 80-bit extended floating-point value pointed to by `aSPtr' is -| a NaN, converts this NaN to the common NaN form, and stores the resulting -| common NaN at the location pointed to by `zPtr'. If the NaN is a signaling -| NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_extF80MToCommonNaN( - const struct extFloat80M *aSPtr, struct commonNaN *zPtr ) -{ - - if ( extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = signExtF80UI64( aSPtr->signExp ); - zPtr->v64 = aSPtr->signif<<1; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086-SSE/s_extF80UIToCommonNaN.c b/softfloat/source/8086-SSE/s_extF80UIToCommonNaN.c deleted file mode 100644 index ab6311e..0000000 --- a/softfloat/source/8086-SSE/s_extF80UIToCommonNaN.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0' -| has the bit pattern of an 80-bit extended floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_extF80UIToCommonNaN( - uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA64>>15; - zPtr->v64 = uiA0<<1; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086-SSE/s_f128MToCommonNaN.c b/softfloat/source/8086-SSE/s_f128MToCommonNaN.c deleted file mode 100644 index 55ec25b..0000000 --- a/softfloat/source/8086-SSE/s_f128MToCommonNaN.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the 128-bit floating-point value pointed to by `aWPtr' is a NaN, -| converts this NaN to the common NaN form, and stores the resulting common -| NaN at the location pointed to by `zPtr'. If the NaN is a signaling NaN, -| the invalid exception is raised. Argument `aWPtr' points to an array of -| four 32-bit elements that concatenate in the platform's normal endian order -| to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr ) -{ - - if ( f128M_isSignalingNaN( (const float128_t *) aWPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = aWPtr[indexWordHi( 4 )]>>31; - softfloat_shortShiftLeft128M( aWPtr, 16, (uint32_t *) &zPtr->v0 ); - -} - diff --git a/softfloat/source/8086-SSE/s_f128UIToCommonNaN.c b/softfloat/source/8086-SSE/s_f128UIToCommonNaN.c deleted file mode 100644 index f838f02..0000000 --- a/softfloat/source/8086-SSE/s_f128UIToCommonNaN.c +++ /dev/null @@ -1,65 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0' -| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to -| the common NaN form, and stores the resulting common NaN at the location -| pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid exception -| is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_f128UIToCommonNaN( - uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ) -{ - struct uint128 NaNSig; - - if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 ); - zPtr->sign = uiA64>>63; - zPtr->v64 = NaNSig.v64; - zPtr->v0 = NaNSig.v0; - -} - diff --git a/softfloat/source/8086-SSE/s_f16UIToCommonNaN.c b/softfloat/source/8086-SSE/s_f16UIToCommonNaN.c deleted file mode 100644 index c1e242d..0000000 --- a/softfloat/source/8086-SSE/s_f16UIToCommonNaN.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming `uiA' has the bit pattern of a 16-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNF16UI( uiA ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA>>15; - zPtr->v64 = (uint_fast64_t) uiA<<54; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086-SSE/s_f32UIToCommonNaN.c b/softfloat/source/8086-SSE/s_f32UIToCommonNaN.c deleted file mode 100644 index b21ba66..0000000 --- a/softfloat/source/8086-SSE/s_f32UIToCommonNaN.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming `uiA' has the bit pattern of a 32-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNF32UI( uiA ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA>>31; - zPtr->v64 = (uint_fast64_t) uiA<<41; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086-SSE/s_f64UIToCommonNaN.c b/softfloat/source/8086-SSE/s_f64UIToCommonNaN.c deleted file mode 100644 index 6529d2e..0000000 --- a/softfloat/source/8086-SSE/s_f64UIToCommonNaN.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming `uiA' has the bit pattern of a 64-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNF64UI( uiA ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA>>63; - zPtr->v64 = uiA<<12; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086-SSE/s_propagateNaNExtF80M.c b/softfloat/source/8086-SSE/s_propagateNaNExtF80M.c deleted file mode 100644 index ea1d57a..0000000 --- a/softfloat/source/8086-SSE/s_propagateNaNExtF80M.c +++ /dev/null @@ -1,107 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 80-bit extended floating-point values -| pointed to by `aSPtr' and `bSPtr' is a NaN, stores the combined NaN result -| at the location pointed to by `zSPtr'. If either original floating-point -| value is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ) -{ - bool isSigNaNA; - const struct extFloat80M *sPtr; - bool isSigNaNB; - uint_fast16_t uiB64; - uint64_t uiB0; - uint_fast16_t uiA64; - uint64_t uiA0; - uint_fast16_t uiMagA64, uiMagB64; - - isSigNaNA = extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ); - sPtr = aSPtr; - if ( ! bSPtr ) { - if ( isSigNaNA ) softfloat_raiseFlags( softfloat_flag_invalid ); - goto copy; - } - isSigNaNB = extF80M_isSignalingNaN( (const extFloat80_t *) bSPtr ); - if ( isSigNaNA | isSigNaNB ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) { - uiB64 = bSPtr->signExp; - if ( isSigNaNB ) goto returnLargerUIMag; - uiB0 = bSPtr->signif; - if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto copyB; - goto copy; - } else { - uiA64 = aSPtr->signExp; - uiA0 = aSPtr->signif; - if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto copy; - goto copyB; - } - } - uiB64 = bSPtr->signExp; - returnLargerUIMag: - uiA64 = aSPtr->signExp; - uiMagA64 = uiA64 & 0x7FFF; - uiMagB64 = uiB64 & 0x7FFF; - if ( uiMagA64 < uiMagB64 ) goto copyB; - if ( uiMagB64 < uiMagA64 ) goto copy; - uiA0 = aSPtr->signif; - uiB0 = bSPtr->signif; - if ( uiA0 < uiB0 ) goto copyB; - if ( uiB0 < uiA0 ) goto copy; - if ( uiA64 < uiB64 ) goto copy; - copyB: - sPtr = bSPtr; - copy: - zSPtr->signExp = sPtr->signExp; - zSPtr->signif = sPtr->signif | UINT64_C( 0xC000000000000000 ); - -} - diff --git a/softfloat/source/8086-SSE/s_propagateNaNExtF80UI.c b/softfloat/source/8086-SSE/s_propagateNaNExtF80UI.c deleted file mode 100644 index cc3f0f4..0000000 --- a/softfloat/source/8086-SSE/s_propagateNaNExtF80UI.c +++ /dev/null @@ -1,106 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting -| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 80-bit extended floating-point value, and assuming at least on of these -| floating-point values is a NaN, returns the bit pattern of the combined NaN -| result. If either original floating-point value is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNExtF80UI( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0 - ) -{ - bool isSigNaNA, isSigNaNB; - uint_fast64_t uiNonsigA0, uiNonsigB0; - uint_fast16_t uiMagA64, uiMagB64; - struct uint128 uiZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - isSigNaNA = softfloat_isSigNaNExtF80UI( uiA64, uiA0 ); - isSigNaNB = softfloat_isSigNaNExtF80UI( uiB64, uiB0 ); - /*------------------------------------------------------------------------ - | Make NaNs non-signaling. - *------------------------------------------------------------------------*/ - uiNonsigA0 = uiA0 | UINT64_C( 0xC000000000000000 ); - uiNonsigB0 = uiB0 | UINT64_C( 0xC000000000000000 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isSigNaNA | isSigNaNB ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) { - if ( isSigNaNB ) goto returnLargerMag; - if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto returnB; - goto returnA; - } else { - if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto returnA; - goto returnB; - } - } - returnLargerMag: - uiMagA64 = uiA64 & 0x7FFF; - uiMagB64 = uiB64 & 0x7FFF; - if ( uiMagA64 < uiMagB64 ) goto returnB; - if ( uiMagB64 < uiMagA64 ) goto returnA; - if ( uiA0 < uiB0 ) goto returnB; - if ( uiB0 < uiA0 ) goto returnA; - if ( uiA64 < uiB64 ) goto returnA; - returnB: - uiZ.v64 = uiB64; - uiZ.v0 = uiNonsigB0; - return uiZ; - returnA: - uiZ.v64 = uiA64; - uiZ.v0 = uiNonsigA0; - return uiZ; - -} - diff --git a/softfloat/source/8086-SSE/s_propagateNaNF128M.c b/softfloat/source/8086-SSE/s_propagateNaNF128M.c deleted file mode 100644 index aa903bf..0000000 --- a/softfloat/source/8086-SSE/s_propagateNaNF128M.c +++ /dev/null @@ -1,76 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 128-bit floating-point values pointed to by -| `aWPtr' and `bWPtr' is a NaN, stores the combined NaN result at the location -| pointed to by `zWPtr'. If either original floating-point value is a -| signaling NaN, the invalid exception is raised. Each of `aWPtr', `bWPtr', -| and `zWPtr' points to an array of four 32-bit elements that concatenate in -| the platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ) -{ - bool isSigNaNA; - const uint32_t *ptr; - - ptr = aWPtr; - isSigNaNA = f128M_isSignalingNaN( (const float128_t *) aWPtr ); - if ( - isSigNaNA - || (bWPtr && f128M_isSignalingNaN( (const float128_t *) bWPtr )) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) goto copy; - } - if ( ! softfloat_isNaNF128M( aWPtr ) ) ptr = bWPtr; - copy: - zWPtr[indexWordHi( 4 )] = ptr[indexWordHi( 4 )] | 0x00008000; - zWPtr[indexWord( 4, 2 )] = ptr[indexWord( 4, 2 )]; - zWPtr[indexWord( 4, 1 )] = ptr[indexWord( 4, 1 )]; - zWPtr[indexWord( 4, 0 )] = ptr[indexWord( 4, 0 )]; - -} - diff --git a/softfloat/source/8086-SSE/s_propagateNaNF128UI.c b/softfloat/source/8086-SSE/s_propagateNaNF128UI.c deleted file mode 100644 index 1c1c2f4..0000000 --- a/softfloat/source/8086-SSE/s_propagateNaNF128UI.c +++ /dev/null @@ -1,81 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating `uiA64' and -| `uiA0' as a 128-bit floating-point value, and likewise interpreting the -| unsigned integer formed from concatenating `uiB64' and `uiB0' as another -| 128-bit floating-point value, and assuming at least on of these floating- -| point values is a NaN, returns the bit pattern of the combined NaN result. -| If either original floating-point value is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNF128UI( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0 - ) -{ - bool isSigNaNA; - struct uint128 uiZ; - - isSigNaNA = softfloat_isSigNaNF128UI( uiA64, uiA0 ); - if ( isSigNaNA || softfloat_isSigNaNF128UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) goto returnNonsigA; - } - if ( isNaNF128UI( uiA64, uiA0 ) ) { - returnNonsigA: - uiZ.v64 = uiA64; - uiZ.v0 = uiA0; - } else { - uiZ.v64 = uiB64; - uiZ.v0 = uiB0; - } - uiZ.v64 |= UINT64_C( 0x0000800000000000 ); - return uiZ; - -} - diff --git a/softfloat/source/8086-SSE/s_propagateNaNF16UI.c b/softfloat/source/8086-SSE/s_propagateNaNF16UI.c deleted file mode 100644 index 4e87ff4..0000000 --- a/softfloat/source/8086-SSE/s_propagateNaNF16UI.c +++ /dev/null @@ -1,63 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting `uiA' and `uiB' as the bit patterns of two 16-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either `uiA' or `uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast16_t - softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ) -{ - bool isSigNaNA; - - isSigNaNA = softfloat_isSigNaNF16UI( uiA ); - if ( isSigNaNA || softfloat_isSigNaNF16UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) return uiA | 0x0200; - } - return (isNaNF16UI( uiA ) ? uiA : uiB) | 0x0200; - -} - diff --git a/softfloat/source/8086-SSE/s_propagateNaNF32UI.c b/softfloat/source/8086-SSE/s_propagateNaNF32UI.c deleted file mode 100644 index e1a8755..0000000 --- a/softfloat/source/8086-SSE/s_propagateNaNF32UI.c +++ /dev/null @@ -1,63 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting `uiA' and `uiB' as the bit patterns of two 32-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either `uiA' or `uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast32_t - softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ) -{ - bool isSigNaNA; - - isSigNaNA = softfloat_isSigNaNF32UI( uiA ); - if ( isSigNaNA || softfloat_isSigNaNF32UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) return uiA | 0x00400000; - } - return (isNaNF32UI( uiA ) ? uiA : uiB) | 0x00400000; - -} - diff --git a/softfloat/source/8086-SSE/s_propagateNaNF64UI.c b/softfloat/source/8086-SSE/s_propagateNaNF64UI.c deleted file mode 100644 index 1af349f..0000000 --- a/softfloat/source/8086-SSE/s_propagateNaNF64UI.c +++ /dev/null @@ -1,63 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting `uiA' and `uiB' as the bit patterns of two 64-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either `uiA' or `uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ) -{ - bool isSigNaNA; - - isSigNaNA = softfloat_isSigNaNF64UI( uiA ); - if ( isSigNaNA || softfloat_isSigNaNF64UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) return uiA | UINT64_C( 0x0008000000000000 ); - } - return (isNaNF64UI( uiA ) ? uiA : uiB) | UINT64_C( 0x0008000000000000 ); - -} - diff --git a/softfloat/source/8086-SSE/softfloat_raiseFlags.c b/softfloat/source/8086-SSE/softfloat_raiseFlags.c deleted file mode 100644 index 3115306..0000000 --- a/softfloat/source/8086-SSE/softfloat_raiseFlags.c +++ /dev/null @@ -1,52 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Raises the exceptions specified by `flags'. Floating-point traps can be -| defined here if desired. It is currently not possible for such a trap -| to substitute a result value. If traps are not implemented, this routine -| should be simply `softfloat_exceptionFlags |= flags;'. -*----------------------------------------------------------------------------*/ -void softfloat_raiseFlags( uint_fast8_t flags ) -{ - - softfloat_exceptionFlags |= flags; - -} - diff --git a/softfloat/source/8086-SSE/specialize.h b/softfloat/source/8086-SSE/specialize.h deleted file mode 100644 index 6dd8fd3..0000000 --- a/softfloat/source/8086-SSE/specialize.h +++ /dev/null @@ -1,367 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2018 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#ifndef specialize_h -#define specialize_h 1 - -#include "primitiveTypes.h" -#include "softfloat.h" -#include -#include - -/*---------------------------------------------------------------------------- -| Default value for 'softfloat_detectTininess'. -*----------------------------------------------------------------------------*/ -#define init_detectTininess softfloat_tininess_afterRounding - -/*---------------------------------------------------------------------------- -| The values to return on conversions to 32-bit integer formats that raise an -| invalid exception. -*----------------------------------------------------------------------------*/ -#define ui32_fromPosOverflow 0xFFFFFFFF -#define ui32_fromNegOverflow 0xFFFFFFFF -#define ui32_fromNaN 0xFFFFFFFF -#define i32_fromPosOverflow (-0x7FFFFFFF - 1) -#define i32_fromNegOverflow (-0x7FFFFFFF - 1) -#define i32_fromNaN (-0x7FFFFFFF - 1) - -/*---------------------------------------------------------------------------- -| The values to return on conversions to 64-bit integer formats that raise an -| invalid exception. -*----------------------------------------------------------------------------*/ -#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define ui64_fromNegOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define ui64_fromNaN UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define i64_fromPosOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) -#define i64_fromNegOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) -#define i64_fromNaN (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) - -/*---------------------------------------------------------------------------- -| "Common NaN" structure, used to transfer NaN representations from one format -| to another. -*----------------------------------------------------------------------------*/ -struct commonNaN { - bool sign; -#ifdef LITTLEENDIAN - uint64_t v0, v64; -#else - uint64_t v64, v0; -#endif -}; - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 16-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF16UI 0xFE00 - -/*---------------------------------------------------------------------------- -| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a -| 16-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ); - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB); - -/*---------------------------------------------------------------------------- -| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a -| 16-bit brain floating-point (BF16) signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNBF16UI( uiA ) ((((uiA) & 0x7FC0) == 0x7F80) && ((uiA) & 0x003F)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 16-bit BF16 floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_bf16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToBF16UI( const struct commonNaN *aPtr ); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 32-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF32UI 0xFFC00000 - -/*---------------------------------------------------------------------------- -| Returns true when 32-bit unsigned integer 'uiA' has the bit pattern of a -| 32-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 64-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF64UI UINT64_C( 0xFFF8000000000000 ) - -/*---------------------------------------------------------------------------- -| Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a -| 64-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF64UI(uiA) \ - ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF))) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 80-bit extended floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNExtF80UI64 0xFFFF -#define defaultNaNExtF80UI0 UINT64_C( 0xC000000000000000 ) - -/*---------------------------------------------------------------------------- -| Returns true when the 80-bit unsigned integer formed from concatenating -| 16-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of an 80-bit extended -| floating-point signaling NaN. -| Note: This macro evaluates its arguments more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNExtF80UI(uiA64, uiA0) \ - ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF))) - -#ifdef SOFTFLOAT_FAST_INT64 - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is -| defined. -*----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of an 80-bit extended floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and returns the bit pattern of this value as an unsigned -| integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting -| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 80-bit extended floating-point value, and assuming at least on of these -| floating-point values is a NaN, returns the bit pattern of the combined NaN -| result. If either original floating-point value is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 128-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 ) -#define defaultNaNF128UI0 UINT64_C( 0 ) - -/*---------------------------------------------------------------------------- -| Returns true when the 128-bit unsigned integer formed from concatenating -| 64-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of a 128-bit floating- -| point signaling NaN. -| Note: This macro evaluates its arguments more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF128UI(uiA64, uiA0) \ - ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF)))) - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to -| the common NaN form, and stores the resulting common NaN at the location -| pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception -| is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the -| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 128-bit floating-point value, and assuming at least on of these floating- -| point values is a NaN, returns the bit pattern of the combined NaN result. -| If either original floating-point value is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0); - -#else - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not -| defined. -*----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- -| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is -| a NaN, converts this NaN to the common NaN form, and stores the resulting -| common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling -| NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and stores this NaN at the location pointed to by -| 'zSPtr'. -*----------------------------------------------------------------------------*/ -void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr); - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 80-bit extended floating-point values -| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result -| at the location pointed to by 'zSPtr'. If either original floating-point -| value is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 128-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF128UI96 0xFFFF8000 -#define defaultNaNF128UI64 0 -#define defaultNaNF128UI32 0 -#define defaultNaNF128UI0 0 - -/*---------------------------------------------------------------------------- -| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, -| converts this NaN to the common NaN form, and stores the resulting common -| NaN at the location pointed to by 'zPtr'. If the NaN is a signaling NaN, -| the invalid exception is raised. Argument 'aWPtr' points to an array of -| four 32-bit elements that concatenate in the platform's normal endian order -| to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and stores this NaN at the location pointed to by 'zWPtr'. Argument -| 'zWPtr' points to an array of four 32-bit elements that concatenate in the -| platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr); - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 128-bit floating-point values pointed to by -| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location -| pointed to by 'zWPtr'. If either original floating-point value is a -| signaling NaN, the invalid exception is raised. Each of 'aWPtr', 'bWPtr', -| and 'zWPtr' points to an array of four 32-bit elements that concatenate in -| the platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr); - -#endif - -#endif diff --git a/softfloat/source/8086/extF80M_isSignalingNaN.c b/softfloat/source/8086/extF80M_isSignalingNaN.c deleted file mode 100644 index 85ee211..0000000 --- a/softfloat/source/8086/extF80M_isSignalingNaN.c +++ /dev/null @@ -1,57 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool extF80M_isSignalingNaN( const extFloat80_t *aPtr ) -{ - const struct extFloat80M *aSPtr; - uint64_t uiA0; - - aSPtr = (const struct extFloat80M *) aPtr; - if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false; - uiA0 = aSPtr->signif; - return - ! (uiA0 & UINT64_C( 0x4000000000000000 )) - && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF)); - -} - diff --git a/softfloat/source/8086/f128M_isSignalingNaN.c b/softfloat/source/8086/f128M_isSignalingNaN.c deleted file mode 100644 index 79a7077..0000000 --- a/softfloat/source/8086/f128M_isSignalingNaN.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "primitives.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool f128M_isSignalingNaN( const float128_t *aPtr ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false; - return - ((uiA96 & 0x00007FFF) != 0) - || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )]) - != 0); - -} - diff --git a/softfloat/source/8086/s_commonNaNToExtF80M.c b/softfloat/source/8086/s_commonNaNToExtF80M.c deleted file mode 100644 index 3405b3b..0000000 --- a/softfloat/source/8086/s_commonNaNToExtF80M.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into an 80-bit extended -| floating-point NaN, and stores this NaN at the location pointed to by -| `zSPtr'. -*----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ) -{ - - zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF ); - zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1; - -} - diff --git a/softfloat/source/8086/s_commonNaNToExtF80UI.c b/softfloat/source/8086/s_commonNaNToExtF80UI.c deleted file mode 100644 index cb7424f..0000000 --- a/softfloat/source/8086/s_commonNaNToExtF80UI.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into an 80-bit extended -| floating-point NaN, and returns the bit pattern of this value as an unsigned -| integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ) -{ - struct uint128 uiZ; - - uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF; - uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1; - return uiZ; - -} - diff --git a/softfloat/source/8086/s_commonNaNToF128M.c b/softfloat/source/8086/s_commonNaNToF128M.c deleted file mode 100644 index e7ea802..0000000 --- a/softfloat/source/8086/s_commonNaNToF128M.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point -| NaN, and stores this NaN at the location pointed to by `zWPtr'. Argument -| `zWPtr' points to an array of four 32-bit elements that concatenate in the -| platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ) -{ - - softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr ); - zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000; - -} - diff --git a/softfloat/source/8086/s_commonNaNToF128UI.c b/softfloat/source/8086/s_commonNaNToF128UI.c deleted file mode 100644 index 7a9423b..0000000 --- a/softfloat/source/8086/s_commonNaNToF128UI.c +++ /dev/null @@ -1,55 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr ) -{ - struct uint128 uiZ; - - uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 ); - uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 ); - return uiZ; - -} - diff --git a/softfloat/source/8086/s_commonNaNToF16UI.c b/softfloat/source/8086/s_commonNaNToF16UI.c deleted file mode 100644 index d4e458a..0000000 --- a/softfloat/source/8086/s_commonNaNToF16UI.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 16-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ) -{ - - return (uint_fast16_t) aPtr->sign<<15 | 0x7E00 | aPtr->v64>>54; - -} - diff --git a/softfloat/source/8086/s_commonNaNToF32UI.c b/softfloat/source/8086/s_commonNaNToF32UI.c deleted file mode 100644 index ed6c226..0000000 --- a/softfloat/source/8086/s_commonNaNToF32UI.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ) -{ - - return (uint_fast32_t) aPtr->sign<<31 | 0x7FC00000 | aPtr->v64>>41; - -} - diff --git a/softfloat/source/8086/s_commonNaNToF64UI.c b/softfloat/source/8086/s_commonNaNToF64UI.c deleted file mode 100644 index 1182be3..0000000 --- a/softfloat/source/8086/s_commonNaNToF64UI.c +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ) -{ - - return - (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FF8000000000000 ) - | aPtr->v64>>12; - -} - diff --git a/softfloat/source/8086/s_extF80MToCommonNaN.c b/softfloat/source/8086/s_extF80MToCommonNaN.c deleted file mode 100644 index 00baf35..0000000 --- a/softfloat/source/8086/s_extF80MToCommonNaN.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the 80-bit extended floating-point value pointed to by `aSPtr' is -| a NaN, converts this NaN to the common NaN form, and stores the resulting -| common NaN at the location pointed to by `zPtr'. If the NaN is a signaling -| NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_extF80MToCommonNaN( - const struct extFloat80M *aSPtr, struct commonNaN *zPtr ) -{ - - if ( extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = signExtF80UI64( aSPtr->signExp ); - zPtr->v64 = aSPtr->signif<<1; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086/s_extF80UIToCommonNaN.c b/softfloat/source/8086/s_extF80UIToCommonNaN.c deleted file mode 100644 index ab6311e..0000000 --- a/softfloat/source/8086/s_extF80UIToCommonNaN.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0' -| has the bit pattern of an 80-bit extended floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_extF80UIToCommonNaN( - uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA64>>15; - zPtr->v64 = uiA0<<1; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086/s_f128MToCommonNaN.c b/softfloat/source/8086/s_f128MToCommonNaN.c deleted file mode 100644 index 55ec25b..0000000 --- a/softfloat/source/8086/s_f128MToCommonNaN.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the 128-bit floating-point value pointed to by `aWPtr' is a NaN, -| converts this NaN to the common NaN form, and stores the resulting common -| NaN at the location pointed to by `zPtr'. If the NaN is a signaling NaN, -| the invalid exception is raised. Argument `aWPtr' points to an array of -| four 32-bit elements that concatenate in the platform's normal endian order -| to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr ) -{ - - if ( f128M_isSignalingNaN( (const float128_t *) aWPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = aWPtr[indexWordHi( 4 )]>>31; - softfloat_shortShiftLeft128M( aWPtr, 16, (uint32_t *) &zPtr->v0 ); - -} - diff --git a/softfloat/source/8086/s_f128UIToCommonNaN.c b/softfloat/source/8086/s_f128UIToCommonNaN.c deleted file mode 100644 index f838f02..0000000 --- a/softfloat/source/8086/s_f128UIToCommonNaN.c +++ /dev/null @@ -1,65 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0' -| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to -| the common NaN form, and stores the resulting common NaN at the location -| pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid exception -| is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_f128UIToCommonNaN( - uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ) -{ - struct uint128 NaNSig; - - if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 ); - zPtr->sign = uiA64>>63; - zPtr->v64 = NaNSig.v64; - zPtr->v0 = NaNSig.v0; - -} - diff --git a/softfloat/source/8086/s_f16UIToCommonNaN.c b/softfloat/source/8086/s_f16UIToCommonNaN.c deleted file mode 100644 index c1e242d..0000000 --- a/softfloat/source/8086/s_f16UIToCommonNaN.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming `uiA' has the bit pattern of a 16-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNF16UI( uiA ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA>>15; - zPtr->v64 = (uint_fast64_t) uiA<<54; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086/s_f32UIToCommonNaN.c b/softfloat/source/8086/s_f32UIToCommonNaN.c deleted file mode 100644 index b21ba66..0000000 --- a/softfloat/source/8086/s_f32UIToCommonNaN.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming `uiA' has the bit pattern of a 32-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNF32UI( uiA ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA>>31; - zPtr->v64 = (uint_fast64_t) uiA<<41; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086/s_f64UIToCommonNaN.c b/softfloat/source/8086/s_f64UIToCommonNaN.c deleted file mode 100644 index 6529d2e..0000000 --- a/softfloat/source/8086/s_f64UIToCommonNaN.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming `uiA' has the bit pattern of a 64-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNF64UI( uiA ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA>>63; - zPtr->v64 = uiA<<12; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/8086/s_propagateNaNExtF80M.c b/softfloat/source/8086/s_propagateNaNExtF80M.c deleted file mode 100644 index ea1d57a..0000000 --- a/softfloat/source/8086/s_propagateNaNExtF80M.c +++ /dev/null @@ -1,107 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 80-bit extended floating-point values -| pointed to by `aSPtr' and `bSPtr' is a NaN, stores the combined NaN result -| at the location pointed to by `zSPtr'. If either original floating-point -| value is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ) -{ - bool isSigNaNA; - const struct extFloat80M *sPtr; - bool isSigNaNB; - uint_fast16_t uiB64; - uint64_t uiB0; - uint_fast16_t uiA64; - uint64_t uiA0; - uint_fast16_t uiMagA64, uiMagB64; - - isSigNaNA = extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ); - sPtr = aSPtr; - if ( ! bSPtr ) { - if ( isSigNaNA ) softfloat_raiseFlags( softfloat_flag_invalid ); - goto copy; - } - isSigNaNB = extF80M_isSignalingNaN( (const extFloat80_t *) bSPtr ); - if ( isSigNaNA | isSigNaNB ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) { - uiB64 = bSPtr->signExp; - if ( isSigNaNB ) goto returnLargerUIMag; - uiB0 = bSPtr->signif; - if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto copyB; - goto copy; - } else { - uiA64 = aSPtr->signExp; - uiA0 = aSPtr->signif; - if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto copy; - goto copyB; - } - } - uiB64 = bSPtr->signExp; - returnLargerUIMag: - uiA64 = aSPtr->signExp; - uiMagA64 = uiA64 & 0x7FFF; - uiMagB64 = uiB64 & 0x7FFF; - if ( uiMagA64 < uiMagB64 ) goto copyB; - if ( uiMagB64 < uiMagA64 ) goto copy; - uiA0 = aSPtr->signif; - uiB0 = bSPtr->signif; - if ( uiA0 < uiB0 ) goto copyB; - if ( uiB0 < uiA0 ) goto copy; - if ( uiA64 < uiB64 ) goto copy; - copyB: - sPtr = bSPtr; - copy: - zSPtr->signExp = sPtr->signExp; - zSPtr->signif = sPtr->signif | UINT64_C( 0xC000000000000000 ); - -} - diff --git a/softfloat/source/8086/s_propagateNaNExtF80UI.c b/softfloat/source/8086/s_propagateNaNExtF80UI.c deleted file mode 100644 index cc3f0f4..0000000 --- a/softfloat/source/8086/s_propagateNaNExtF80UI.c +++ /dev/null @@ -1,106 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting -| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 80-bit extended floating-point value, and assuming at least on of these -| floating-point values is a NaN, returns the bit pattern of the combined NaN -| result. If either original floating-point value is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNExtF80UI( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0 - ) -{ - bool isSigNaNA, isSigNaNB; - uint_fast64_t uiNonsigA0, uiNonsigB0; - uint_fast16_t uiMagA64, uiMagB64; - struct uint128 uiZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - isSigNaNA = softfloat_isSigNaNExtF80UI( uiA64, uiA0 ); - isSigNaNB = softfloat_isSigNaNExtF80UI( uiB64, uiB0 ); - /*------------------------------------------------------------------------ - | Make NaNs non-signaling. - *------------------------------------------------------------------------*/ - uiNonsigA0 = uiA0 | UINT64_C( 0xC000000000000000 ); - uiNonsigB0 = uiB0 | UINT64_C( 0xC000000000000000 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isSigNaNA | isSigNaNB ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) { - if ( isSigNaNB ) goto returnLargerMag; - if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto returnB; - goto returnA; - } else { - if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto returnA; - goto returnB; - } - } - returnLargerMag: - uiMagA64 = uiA64 & 0x7FFF; - uiMagB64 = uiB64 & 0x7FFF; - if ( uiMagA64 < uiMagB64 ) goto returnB; - if ( uiMagB64 < uiMagA64 ) goto returnA; - if ( uiA0 < uiB0 ) goto returnB; - if ( uiB0 < uiA0 ) goto returnA; - if ( uiA64 < uiB64 ) goto returnA; - returnB: - uiZ.v64 = uiB64; - uiZ.v0 = uiNonsigB0; - return uiZ; - returnA: - uiZ.v64 = uiA64; - uiZ.v0 = uiNonsigA0; - return uiZ; - -} - diff --git a/softfloat/source/8086/s_propagateNaNF128M.c b/softfloat/source/8086/s_propagateNaNF128M.c deleted file mode 100644 index 06554fb..0000000 --- a/softfloat/source/8086/s_propagateNaNF128M.c +++ /dev/null @@ -1,108 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 128-bit floating-point values pointed to by -| `aWPtr' and `bWPtr' is a NaN, stores the combined NaN result at the location -| pointed to by `zWPtr'. If either original floating-point value is a -| signaling NaN, the invalid exception is raised. Each of `aWPtr', `bWPtr', -| and `zWPtr' points to an array of four 32-bit elements that concatenate in -| the platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ) -{ - bool isSigNaNA; - const uint32_t *ptr; - bool isSigNaNB; - uint32_t uiA96, uiB96, wordMagA, wordMagB; - - isSigNaNA = f128M_isSignalingNaN( (const float128_t *) aWPtr ); - ptr = aWPtr; - if ( ! bWPtr ) { - if ( isSigNaNA ) softfloat_raiseFlags( softfloat_flag_invalid ); - goto copy; - } - isSigNaNB = f128M_isSignalingNaN( (const float128_t *) bWPtr ); - if ( isSigNaNA | isSigNaNB ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) { - if ( isSigNaNB ) goto returnLargerUIMag; - if ( softfloat_isNaNF128M( bWPtr ) ) goto copyB; - goto copy; - } else { - if ( softfloat_isNaNF128M( aWPtr ) ) goto copy; - goto copyB; - } - } - returnLargerUIMag: - uiA96 = aWPtr[indexWordHi( 4 )]; - uiB96 = bWPtr[indexWordHi( 4 )]; - wordMagA = uiA96 & 0x7FFFFFFF; - wordMagB = uiB96 & 0x7FFFFFFF; - if ( wordMagA < wordMagB ) goto copyB; - if ( wordMagB < wordMagA ) goto copy; - wordMagA = aWPtr[indexWord( 4, 2 )]; - wordMagB = bWPtr[indexWord( 4, 2 )]; - if ( wordMagA < wordMagB ) goto copyB; - if ( wordMagB < wordMagA ) goto copy; - wordMagA = aWPtr[indexWord( 4, 1 )]; - wordMagB = bWPtr[indexWord( 4, 1 )]; - if ( wordMagA < wordMagB ) goto copyB; - if ( wordMagB < wordMagA ) goto copy; - wordMagA = aWPtr[indexWord( 4, 0 )]; - wordMagB = bWPtr[indexWord( 4, 0 )]; - if ( wordMagA < wordMagB ) goto copyB; - if ( wordMagB < wordMagA ) goto copy; - if ( uiA96 < uiB96 ) goto copy; - copyB: - ptr = bWPtr; - copy: - zWPtr[indexWordHi( 4 )] = ptr[indexWordHi( 4 )] | 0x00008000; - zWPtr[indexWord( 4, 2 )] = ptr[indexWord( 4, 2 )]; - zWPtr[indexWord( 4, 1 )] = ptr[indexWord( 4, 1 )]; - zWPtr[indexWord( 4, 0 )] = ptr[indexWord( 4, 0 )]; - -} - diff --git a/softfloat/source/8086/s_propagateNaNF128UI.c b/softfloat/source/8086/s_propagateNaNF128UI.c deleted file mode 100644 index 46b9f5f..0000000 --- a/softfloat/source/8086/s_propagateNaNF128UI.c +++ /dev/null @@ -1,105 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the -| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 128-bit floating-point value, and assuming at least on of these floating- -| point values is a NaN, returns the bit pattern of the combined NaN result. -| If either original floating-point value is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNF128UI( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0 - ) -{ - bool isSigNaNA, isSigNaNB; - uint_fast64_t uiNonsigA64, uiNonsigB64, uiMagA64, uiMagB64; - struct uint128 uiZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - isSigNaNA = softfloat_isSigNaNF128UI( uiA64, uiA0 ); - isSigNaNB = softfloat_isSigNaNF128UI( uiB64, uiB0 ); - /*------------------------------------------------------------------------ - | Make NaNs non-signaling. - *------------------------------------------------------------------------*/ - uiNonsigA64 = uiA64 | UINT64_C( 0x0000800000000000 ); - uiNonsigB64 = uiB64 | UINT64_C( 0x0000800000000000 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isSigNaNA | isSigNaNB ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) { - if ( isSigNaNB ) goto returnLargerMag; - if ( isNaNF128UI( uiB64, uiB0 ) ) goto returnB; - goto returnA; - } else { - if ( isNaNF128UI( uiA64, uiA0 ) ) goto returnA; - goto returnB; - } - } - returnLargerMag: - uiMagA64 = uiA64 & UINT64_C( 0x7FFFFFFFFFFFFFFF ); - uiMagB64 = uiB64 & UINT64_C( 0x7FFFFFFFFFFFFFFF ); - if ( uiMagA64 < uiMagB64 ) goto returnB; - if ( uiMagB64 < uiMagA64 ) goto returnA; - if ( uiA0 < uiB0 ) goto returnB; - if ( uiB0 < uiA0 ) goto returnA; - if ( uiNonsigA64 < uiNonsigB64 ) goto returnA; - returnB: - uiZ.v64 = uiNonsigB64; - uiZ.v0 = uiB0; - return uiZ; - returnA: - uiZ.v64 = uiNonsigA64; - uiZ.v0 = uiA0; - return uiZ; - -} - diff --git a/softfloat/source/8086/s_propagateNaNF16UI.c b/softfloat/source/8086/s_propagateNaNF16UI.c deleted file mode 100644 index 89cc0fe..0000000 --- a/softfloat/source/8086/s_propagateNaNF16UI.c +++ /dev/null @@ -1,84 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2018 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast16_t - softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ) -{ - bool isSigNaNA, isSigNaNB; - uint_fast16_t uiNonsigA, uiNonsigB, uiMagA, uiMagB; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - isSigNaNA = softfloat_isSigNaNF16UI( uiA ); - isSigNaNB = softfloat_isSigNaNF16UI( uiB ); - /*------------------------------------------------------------------------ - | Make NaNs non-signaling. - *------------------------------------------------------------------------*/ - uiNonsigA = uiA | 0x0200; - uiNonsigB = uiB | 0x0200; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isSigNaNA | isSigNaNB ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) { - if ( isSigNaNB ) goto returnLargerMag; - return isNaNF16UI( uiB ) ? uiNonsigB : uiNonsigA; - } else { - return isNaNF16UI( uiA ) ? uiNonsigA : uiNonsigB; - } - } - returnLargerMag: - uiMagA = uiA & 0x7FFF; - uiMagB = uiB & 0x7FFF; - if ( uiMagA < uiMagB ) return uiNonsigB; - if ( uiMagB < uiMagA ) return uiNonsigA; - return (uiNonsigA < uiNonsigB) ? uiNonsigA : uiNonsigB; - -} - diff --git a/softfloat/source/8086/s_propagateNaNF32UI.c b/softfloat/source/8086/s_propagateNaNF32UI.c deleted file mode 100644 index aeb6024..0000000 --- a/softfloat/source/8086/s_propagateNaNF32UI.c +++ /dev/null @@ -1,84 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast32_t - softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ) -{ - bool isSigNaNA, isSigNaNB; - uint_fast32_t uiNonsigA, uiNonsigB, uiMagA, uiMagB; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - isSigNaNA = softfloat_isSigNaNF32UI( uiA ); - isSigNaNB = softfloat_isSigNaNF32UI( uiB ); - /*------------------------------------------------------------------------ - | Make NaNs non-signaling. - *------------------------------------------------------------------------*/ - uiNonsigA = uiA | 0x00400000; - uiNonsigB = uiB | 0x00400000; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isSigNaNA | isSigNaNB ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) { - if ( isSigNaNB ) goto returnLargerMag; - return isNaNF32UI( uiB ) ? uiNonsigB : uiNonsigA; - } else { - return isNaNF32UI( uiA ) ? uiNonsigA : uiNonsigB; - } - } - returnLargerMag: - uiMagA = uiA & 0x7FFFFFFF; - uiMagB = uiB & 0x7FFFFFFF; - if ( uiMagA < uiMagB ) return uiNonsigB; - if ( uiMagB < uiMagA ) return uiNonsigA; - return (uiNonsigA < uiNonsigB) ? uiNonsigA : uiNonsigB; - -} - diff --git a/softfloat/source/8086/s_propagateNaNF64UI.c b/softfloat/source/8086/s_propagateNaNF64UI.c deleted file mode 100644 index dabad40..0000000 --- a/softfloat/source/8086/s_propagateNaNF64UI.c +++ /dev/null @@ -1,84 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ) -{ - bool isSigNaNA, isSigNaNB; - uint_fast64_t uiNonsigA, uiNonsigB, uiMagA, uiMagB; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - isSigNaNA = softfloat_isSigNaNF64UI( uiA ); - isSigNaNB = softfloat_isSigNaNF64UI( uiB ); - /*------------------------------------------------------------------------ - | Make NaNs non-signaling. - *------------------------------------------------------------------------*/ - uiNonsigA = uiA | UINT64_C( 0x0008000000000000 ); - uiNonsigB = uiB | UINT64_C( 0x0008000000000000 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isSigNaNA | isSigNaNB ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) { - if ( isSigNaNB ) goto returnLargerMag; - return isNaNF64UI( uiB ) ? uiNonsigB : uiNonsigA; - } else { - return isNaNF64UI( uiA ) ? uiNonsigA : uiNonsigB; - } - } - returnLargerMag: - uiMagA = uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF ); - uiMagB = uiB & UINT64_C( 0x7FFFFFFFFFFFFFFF ); - if ( uiMagA < uiMagB ) return uiNonsigB; - if ( uiMagB < uiMagA ) return uiNonsigA; - return (uiNonsigA < uiNonsigB) ? uiNonsigA : uiNonsigB; - -} - diff --git a/softfloat/source/8086/softfloat_raiseFlags.c b/softfloat/source/8086/softfloat_raiseFlags.c deleted file mode 100644 index 3115306..0000000 --- a/softfloat/source/8086/softfloat_raiseFlags.c +++ /dev/null @@ -1,52 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Raises the exceptions specified by `flags'. Floating-point traps can be -| defined here if desired. It is currently not possible for such a trap -| to substitute a result value. If traps are not implemented, this routine -| should be simply `softfloat_exceptionFlags |= flags;'. -*----------------------------------------------------------------------------*/ -void softfloat_raiseFlags( uint_fast8_t flags ) -{ - - softfloat_exceptionFlags |= flags; - -} - diff --git a/softfloat/source/8086/specialize.h b/softfloat/source/8086/specialize.h deleted file mode 100644 index f2a2c81..0000000 --- a/softfloat/source/8086/specialize.h +++ /dev/null @@ -1,346 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2018 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#ifndef specialize_h -#define specialize_h 1 - -#include "primitiveTypes.h" -#include "softfloat.h" -#include -#include - -/*---------------------------------------------------------------------------- -| Default value for 'softfloat_detectTininess'. -*----------------------------------------------------------------------------*/ -#define init_detectTininess softfloat_tininess_afterRounding - -/*---------------------------------------------------------------------------- -| The values to return on conversions to 32-bit integer formats that raise an -| invalid exception. -*----------------------------------------------------------------------------*/ -#define ui32_fromPosOverflow 0xFFFFFFFF -#define ui32_fromNegOverflow 0xFFFFFFFF -#define ui32_fromNaN 0xFFFFFFFF -#define i32_fromPosOverflow (-0x7FFFFFFF - 1) -#define i32_fromNegOverflow (-0x7FFFFFFF - 1) -#define i32_fromNaN (-0x7FFFFFFF - 1) - -/*---------------------------------------------------------------------------- -| The values to return on conversions to 64-bit integer formats that raise an -| invalid exception. -*----------------------------------------------------------------------------*/ -#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define ui64_fromNegOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define ui64_fromNaN UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define i64_fromPosOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) -#define i64_fromNegOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) -#define i64_fromNaN (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) - -/*---------------------------------------------------------------------------- -| "Common NaN" structure, used to transfer NaN representations from one format -| to another. -*----------------------------------------------------------------------------*/ -struct commonNaN { - bool sign; -#ifdef LITTLEENDIAN - uint64_t v0, v64; -#else - uint64_t v64, v0; -#endif -}; - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 16-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF16UI 0xFE00 - -/*---------------------------------------------------------------------------- -| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a -| 16-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ); - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 32-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF32UI 0xFFC00000 - -/*---------------------------------------------------------------------------- -| Returns true when 32-bit unsigned integer 'uiA' has the bit pattern of a -| 32-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 64-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF64UI UINT64_C( 0xFFF8000000000000 ) - -/*---------------------------------------------------------------------------- -| Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a -| 64-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF ))) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 80-bit extended floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNExtF80UI64 0xFFFF -#define defaultNaNExtF80UI0 UINT64_C( 0xC000000000000000 ) - -/*---------------------------------------------------------------------------- -| Returns true when the 80-bit unsigned integer formed from concatenating -| 16-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of an 80-bit extended -| floating-point signaling NaN. -| Note: This macro evaluates its arguments more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNExtF80UI(uiA64, uiA0) \ - ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF))) - -#ifdef SOFTFLOAT_FAST_INT64 - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is -| defined. -*----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of an 80-bit extended floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and returns the bit pattern of this value as an unsigned -| integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting -| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 80-bit extended floating-point value, and assuming at least on of these -| floating-point values is a NaN, returns the bit pattern of the combined NaN -| result. If either original floating-point value is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 128-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 ) -#define defaultNaNF128UI0 UINT64_C( 0 ) - -/*---------------------------------------------------------------------------- -| Returns true when the 128-bit unsigned integer formed from concatenating -| 64-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of a 128-bit floating- -| point signaling NaN. -| Note: This macro evaluates its arguments more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF128UI(uiA64, uiA0) \ - ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF)))) - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to -| the common NaN form, and stores the resulting common NaN at the location -| pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception -| is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the -| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 128-bit floating-point value, and assuming at least on of these floating- -| point values is a NaN, returns the bit pattern of the combined NaN result. -| If either original floating-point value is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0); - -#else - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not -| defined. -*----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- -| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is -| a NaN, converts this NaN to the common NaN form, and stores the resulting -| common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling -| NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and stores this NaN at the location pointed to by -| 'zSPtr'. -*----------------------------------------------------------------------------*/ -void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr); - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 80-bit extended floating-point values -| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result -| at the location pointed to by 'zSPtr'. If either original floating-point -| value is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 128-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF128UI96 0xFFFF8000 -#define defaultNaNF128UI64 0 -#define defaultNaNF128UI32 0 -#define defaultNaNF128UI0 0 - -/*---------------------------------------------------------------------------- -| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, -| converts this NaN to the common NaN form, and stores the resulting common -| NaN at the location pointed to by 'zPtr'. If the NaN is a signaling NaN, -| the invalid exception is raised. Argument 'aWPtr' points to an array of -| four 32-bit elements that concatenate in the platform's normal endian order -| to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and stores this NaN at the location pointed to by 'zWPtr'. Argument -| 'zWPtr' points to an array of four 32-bit elements that concatenate in the -| platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr); - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 128-bit floating-point values pointed to by -| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location -| pointed to by 'zWPtr'. If either original floating-point value is a -| signaling NaN, the invalid exception is raised. Each of 'aWPtr', 'bWPtr', -| and 'zWPtr' points to an array of four 32-bit elements that concatenate in -| the platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr); - -#endif - -#endif diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/extF80M_isSignalingNaN.c b/softfloat/source/ARM-VFPv2-defaultNaN/extF80M_isSignalingNaN.c deleted file mode 100644 index 85ee211..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/extF80M_isSignalingNaN.c +++ /dev/null @@ -1,57 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool extF80M_isSignalingNaN( const extFloat80_t *aPtr ) -{ - const struct extFloat80M *aSPtr; - uint64_t uiA0; - - aSPtr = (const struct extFloat80M *) aPtr; - if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false; - uiA0 = aSPtr->signif; - return - ! (uiA0 & UINT64_C( 0x4000000000000000 )) - && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF)); - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/f128M_isSignalingNaN.c b/softfloat/source/ARM-VFPv2-defaultNaN/f128M_isSignalingNaN.c deleted file mode 100644 index 79a7077..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/f128M_isSignalingNaN.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "primitives.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool f128M_isSignalingNaN( const float128_t *aPtr ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false; - return - ((uiA96 & 0x00007FFF) != 0) - || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )]) - != 0); - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80M.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80M.c deleted file mode 100644 index 54a50dc..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80M.c +++ /dev/null @@ -1,57 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "softfloat_types.h" - -#define softfloat_commonNaNToExtF80M softfloat_commonNaNToExtF80M -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and stores this NaN at the location pointed to by -| 'zSPtr'. -*----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ) -{ - - zSPtr->signExp = defaultNaNExtF80UI64; - zSPtr->signif = defaultNaNExtF80UI0; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80UI.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80UI.c deleted file mode 100644 index 5b698f6..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80UI.c +++ /dev/null @@ -1,57 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "primitiveTypes.h" - -#define softfloat_commonNaNToExtF80UI softfloat_commonNaNToExtF80UI -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and returns the bit pattern of this value as an unsigned -| integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ) -{ - struct uint128 uiZ; - - uiZ.v64 = defaultNaNExtF80UI64; - uiZ.v0 = defaultNaNExtF80UI0; - return uiZ; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128M.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128M.c deleted file mode 100644 index b22baa8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128M.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#define softfloat_commonNaNToF128M softfloat_commonNaNToF128M -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and stores this NaN at the location pointed to by 'zWPtr'. Argument -| 'zWPtr' points to an array of four 32-bit elements that concatenate in the -| platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ) -{ - - zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96; - zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64; - zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32; - zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128UI.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128UI.c deleted file mode 100644 index 70f0cf1..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128UI.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "primitiveTypes.h" - -#define softfloat_commonNaNToF128UI softfloat_commonNaNToF128UI -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr ) -{ - struct uint128 uiZ; - - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - return uiZ; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF16UI.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF16UI.c deleted file mode 100644 index 7c7d5c8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF16UI.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF32UI.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF32UI.c deleted file mode 100644 index 7c7d5c8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF32UI.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF64UI.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF64UI.c deleted file mode 100644 index 7c7d5c8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_commonNaNToF64UI.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_extF80MToCommonNaN.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_extF80MToCommonNaN.c deleted file mode 100644 index 7c7d5c8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_extF80MToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_extF80UIToCommonNaN.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_extF80UIToCommonNaN.c deleted file mode 100644 index 7c7d5c8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_extF80UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_f128MToCommonNaN.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_f128MToCommonNaN.c deleted file mode 100644 index 7c7d5c8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_f128MToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_f128UIToCommonNaN.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_f128UIToCommonNaN.c deleted file mode 100644 index 7c7d5c8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_f128UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_f16UIToCommonNaN.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_f16UIToCommonNaN.c deleted file mode 100644 index 7c7d5c8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_f16UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_f32UIToCommonNaN.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_f32UIToCommonNaN.c deleted file mode 100644 index 7c7d5c8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_f32UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_f64UIToCommonNaN.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_f64UIToCommonNaN.c deleted file mode 100644 index 7c7d5c8..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_f64UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80M.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80M.c deleted file mode 100644 index 1c6510c..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80M.c +++ /dev/null @@ -1,74 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 80-bit extended floating-point values -| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result -| at the location pointed to by 'zSPtr'. If either original floating-point -| value is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ) -{ - uint_fast16_t ui64; - uint_fast64_t ui0; - - ui64 = aSPtr->signExp; - ui0 = aSPtr->signif; - if ( - softfloat_isSigNaNExtF80UI( ui64, ui0 ) - || (bSPtr - && (ui64 = bSPtr->signExp, - ui0 = bSPtr->signif, - softfloat_isSigNaNExtF80UI( ui64, ui0 ))) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zSPtr->signExp = defaultNaNExtF80UI64; - zSPtr->signif = defaultNaNExtF80UI0; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80UI.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80UI.c deleted file mode 100644 index e1bb155..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80UI.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting -| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 80-bit extended floating-point value, and assuming at least on of these -| floating-point values is a NaN, returns the bit pattern of the combined NaN -| result. If either original floating-point value is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNExtF80UI( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0 - ) -{ - struct uint128 uiZ; - - if ( - softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) - || softfloat_isSigNaNExtF80UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - uiZ.v64 = defaultNaNExtF80UI64; - uiZ.v0 = defaultNaNExtF80UI0; - return uiZ; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128M.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128M.c deleted file mode 100644 index 9bddee9..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128M.c +++ /dev/null @@ -1,68 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 128-bit floating-point values pointed to by -| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location -| pointed to by 'zWPtr'. If either original floating-point value is a -| signaling NaN, the invalid exception is raised. Each of 'aWPtr', 'bWPtr', -| and 'zWPtr' points to an array of four 32-bit elements that concatenate in -| the platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ) -{ - - if ( - f128M_isSignalingNaN( (const float128_t *) aWPtr ); - || (bWPtr && f128M_isSignalingNaN( (const float128_t *) bWPtr )) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96; - zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64; - zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32; - zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128UI.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128UI.c deleted file mode 100644 index 57fddd1..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128UI.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the -| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 128-bit floating-point value, and assuming at least on of these floating- -| point values is a NaN, returns the bit pattern of the combined NaN result. -| If either original floating-point value is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNF128UI( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0 - ) -{ - struct uint128 uiZ; - - if ( - softfloat_isSigNaNF128UI( uiA64, uiA0 ) - || softfloat_isSigNaNF128UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - return uiZ; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF16UI.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF16UI.c deleted file mode 100644 index 0b08e00..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF16UI.c +++ /dev/null @@ -1,58 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast16_t - softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ) -{ - - if ( softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return defaultNaNF16UI; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF32UI.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF32UI.c deleted file mode 100644 index cab7403..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF32UI.c +++ /dev/null @@ -1,58 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast32_t - softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ) -{ - - if ( softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return defaultNaNF32UI; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF64UI.c b/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF64UI.c deleted file mode 100644 index 83b91d3..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/s_propagateNaNF64UI.c +++ /dev/null @@ -1,58 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ) -{ - - if ( softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return defaultNaNF64UI; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/softfloat_raiseFlags.c b/softfloat/source/ARM-VFPv2-defaultNaN/softfloat_raiseFlags.c deleted file mode 100644 index 61046da..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/softfloat_raiseFlags.c +++ /dev/null @@ -1,52 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Raises the exceptions specified by 'flags'. Floating-point traps can be -| defined here if desired. It is currently not possible for such a trap -| to substitute a result value. If traps are not implemented, this routine -| should be simply 'softfloat_exceptionFlags |= flags;'. -*----------------------------------------------------------------------------*/ -void softfloat_raiseFlags( uint_fast8_t flags ) -{ - - softfloat_exceptionFlags |= flags; - -} - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/specialize.h b/softfloat/source/ARM-VFPv2-defaultNaN/specialize.h deleted file mode 100644 index 7143282..0000000 --- a/softfloat/source/ARM-VFPv2-defaultNaN/specialize.h +++ /dev/null @@ -1,393 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#ifndef specialize_h -#define specialize_h 1 - -#include "primitiveTypes.h" -#include "softfloat.h" -#include -#include - -/*---------------------------------------------------------------------------- -| Default value for 'softfloat_detectTininess'. -*----------------------------------------------------------------------------*/ -#define init_detectTininess softfloat_tininess_beforeRounding - -/*---------------------------------------------------------------------------- -| The values to return on conversions to 32-bit integer formats that raise an -| invalid exception. -*----------------------------------------------------------------------------*/ -#define ui32_fromPosOverflow 0xFFFFFFFF -#define ui32_fromNegOverflow 0 -#define ui32_fromNaN 0 -#define i32_fromPosOverflow 0x7FFFFFFF -#define i32_fromNegOverflow (-0x7FFFFFFF - 1) -#define i32_fromNaN 0 - -/*---------------------------------------------------------------------------- -| The values to return on conversions to 64-bit integer formats that raise an -| invalid exception. -*----------------------------------------------------------------------------*/ -#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF) -#define ui64_fromNegOverflow 0 -#define ui64_fromNaN 0 -#define i64_fromPosOverflow INT64_C(0x7FFFFFFFFFFFFFFF) -#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) -#define i64_fromNaN 0 - -/*---------------------------------------------------------------------------- -| "Common NaN" structure, used to transfer NaN representations from one format -| to another. -*----------------------------------------------------------------------------*/ -struct commonNaN { - char _unused; -}; - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 16-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF16UI 0x7E00 - -/*---------------------------------------------------------------------------- -| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a -| 16-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_f16UIToCommonNaN(uiA, zPtr) \ - if(!((uiA)&0x0200)) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -#define softfloat_commonNaNToF16UI(aPtr) ((uint_fast16_t)defaultNaNF16UI) - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 32-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF32UI 0x7FC00000 - -/*---------------------------------------------------------------------------- -| Returns true when 32-bit unsigned integer 'uiA' has the bit pattern of a -| 32-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_f32UIToCommonNaN(uiA, zPtr) \ - if(!((uiA)&0x00400000)) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -#define softfloat_commonNaNToF32UI(aPtr) ((uint_fast32_t)defaultNaNF32UI) - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 64-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF64UI UINT64_C(0x7FF8000000000000) - -/*---------------------------------------------------------------------------- -| Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a -| 64-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF64UI(uiA) \ - ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF))) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_f64UIToCommonNaN(uiA, zPtr) \ - if(!((uiA)&UINT64_C(0x0008000000000000))) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -#define softfloat_commonNaNToF64UI(aPtr) ((uint_fast64_t)defaultNaNF64UI) - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 80-bit extended floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNExtF80UI64 0x7FFF -#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000) - -/*---------------------------------------------------------------------------- -| Returns true when the 80-bit unsigned integer formed from concatenating -| 16-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of an 80-bit extended -| floating-point signaling NaN. -| Note: This macro evaluates its arguments more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNExtF80UI(uiA64, uiA0) \ - ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF))) - -#ifdef SOFTFLOAT_FAST_INT64 - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is -| defined. -*----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of an 80-bit extended floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_extF80UIToCommonNaN(uiA64, uiA0, zPtr) \ - if(!((uiA0)&UINT64_C(0x4000000000000000))) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and returns the bit pattern of this value as an unsigned -| integer. -*----------------------------------------------------------------------------*/ -#if defined INLINE && !defined softfloat_commonNaNToExtF80UI -INLINE -struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr) { - struct uint128 uiZ; - uiZ.v64 = defaultNaNExtF80UI64; - uiZ.v0 = defaultNaNExtF80UI0; - return uiZ; -} -#else -struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr); -#endif - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting -| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 80-bit extended floating-point value, and assuming at least on of these -| floating-point values is a NaN, returns the bit pattern of the combined NaN -| result. If either original floating-point value is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 128-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF128UI64 UINT64_C(0x7FFF800000000000) -#define defaultNaNF128UI0 UINT64_C(0) - -/*---------------------------------------------------------------------------- -| Returns true when the 128-bit unsigned integer formed from concatenating -| 64-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of a 128-bit floating- -| point signaling NaN. -| Note: This macro evaluates its arguments more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF128UI(uiA64, uiA0) \ - ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF)))) - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to -| the common NaN form, and stores the resulting common NaN at the location -| pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception -| is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_f128UIToCommonNaN(uiA64, uiA0, zPtr) \ - if(!((uiA64)&UINT64_C(0x0000800000000000))) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -#if defined INLINE && !defined softfloat_commonNaNToF128UI -INLINE -struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN* aPtr) { - struct uint128 uiZ; - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - return uiZ; -} -#else -struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*); -#endif - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the -| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 128-bit floating-point value, and assuming at least on of these floating- -| point values is a NaN, returns the bit pattern of the combined NaN result. -| If either original floating-point value is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0); - -#else - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not -| defined. -*----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- -| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is -| a NaN, converts this NaN to the common NaN form, and stores the resulting -| common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling -| NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_extF80MToCommonNaN(aSPtr, zPtr) \ - if(!((aSPtr)->signif & UINT64_C(0x4000000000000000))) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and stores this NaN at the location pointed to by -| 'zSPtr'. -*----------------------------------------------------------------------------*/ -#if defined INLINE && !defined softfloat_commonNaNToExtF80M -INLINE -void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr) { - zSPtr->signExp = defaultNaNExtF80UI64; - zSPtr->signif = defaultNaNExtF80UI0; -} -#else -void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr); -#endif - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 80-bit extended floating-point values -| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result -| at the location pointed to by 'zSPtr'. If either original floating-point -| value is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 128-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF128UI96 0x7FFF8000 -#define defaultNaNF128UI64 0 -#define defaultNaNF128UI32 0 -#define defaultNaNF128UI0 0 - -/*---------------------------------------------------------------------------- -| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, -| converts this NaN to the common NaN form, and stores the resulting common -| NaN at the location pointed to by 'zPtr'. If the NaN is a signaling NaN, -| the invalid exception is raised. Argument 'aWPtr' points to an array of -| four 32-bit elements that concatenate in the platform's normal endian order -| to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -#define softfloat_f128MToCommonNaN(aWPtr, zPtr) \ - if(!((aWPtr)[indexWordHi(4)] & UINT64_C(0x0000800000000000))) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and stores this NaN at the location pointed to by 'zWPtr'. Argument -| 'zWPtr' points to an array of four 32-bit elements that concatenate in the -| platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -#if defined INLINE && !defined softfloat_commonNaNToF128M -INLINE -void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr) { - zWPtr[indexWord(4, 3)] = defaultNaNF128UI96; - zWPtr[indexWord(4, 2)] = defaultNaNF128UI64; - zWPtr[indexWord(4, 1)] = defaultNaNF128UI32; - zWPtr[indexWord(4, 0)] = defaultNaNF128UI0; -} -#else -void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr); -#endif - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 128-bit floating-point values pointed to by -| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location -| pointed to by 'zWPtr'. If either original floating-point value is a -| signaling NaN, the invalid exception is raised. Each of 'aWPtr', 'bWPtr', -| and 'zWPtr' points to an array of four 32-bit elements that concatenate in -| the platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr); - -#endif - -#endif diff --git a/softfloat/source/ARM-VFPv2/extF80M_isSignalingNaN.c b/softfloat/source/ARM-VFPv2/extF80M_isSignalingNaN.c deleted file mode 100644 index 85ee211..0000000 --- a/softfloat/source/ARM-VFPv2/extF80M_isSignalingNaN.c +++ /dev/null @@ -1,57 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool extF80M_isSignalingNaN( const extFloat80_t *aPtr ) -{ - const struct extFloat80M *aSPtr; - uint64_t uiA0; - - aSPtr = (const struct extFloat80M *) aPtr; - if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false; - uiA0 = aSPtr->signif; - return - ! (uiA0 & UINT64_C( 0x4000000000000000 )) - && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF)); - -} - diff --git a/softfloat/source/ARM-VFPv2/f128M_isSignalingNaN.c b/softfloat/source/ARM-VFPv2/f128M_isSignalingNaN.c deleted file mode 100644 index 79a7077..0000000 --- a/softfloat/source/ARM-VFPv2/f128M_isSignalingNaN.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "primitives.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool f128M_isSignalingNaN( const float128_t *aPtr ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false; - return - ((uiA96 & 0x00007FFF) != 0) - || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )]) - != 0); - -} - diff --git a/softfloat/source/ARM-VFPv2/s_commonNaNToExtF80M.c b/softfloat/source/ARM-VFPv2/s_commonNaNToExtF80M.c deleted file mode 100644 index 543400b..0000000 --- a/softfloat/source/ARM-VFPv2/s_commonNaNToExtF80M.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and stores this NaN at the location pointed to by -| 'zSPtr'. -*----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ) -{ - - zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF ); - zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_commonNaNToExtF80UI.c b/softfloat/source/ARM-VFPv2/s_commonNaNToExtF80UI.c deleted file mode 100644 index 6cf1d11..0000000 --- a/softfloat/source/ARM-VFPv2/s_commonNaNToExtF80UI.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and returns the bit pattern of this value as an unsigned -| integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ) -{ - struct uint128 uiZ; - - uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF; - uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1; - return uiZ; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_commonNaNToF128M.c b/softfloat/source/ARM-VFPv2/s_commonNaNToF128M.c deleted file mode 100644 index 4e8ede0..0000000 --- a/softfloat/source/ARM-VFPv2/s_commonNaNToF128M.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and stores this NaN at the location pointed to by 'zWPtr'. Argument -| 'zWPtr' points to an array of four 32-bit elements that concatenate in the -| platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ) -{ - - softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr ); - zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_commonNaNToF128UI.c b/softfloat/source/ARM-VFPv2/s_commonNaNToF128UI.c deleted file mode 100644 index f938c3f..0000000 --- a/softfloat/source/ARM-VFPv2/s_commonNaNToF128UI.c +++ /dev/null @@ -1,55 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr ) -{ - struct uint128 uiZ; - - uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 ); - uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 ); - return uiZ; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_commonNaNToF16UI.c b/softfloat/source/ARM-VFPv2/s_commonNaNToF16UI.c deleted file mode 100644 index 6cd4fc1..0000000 --- a/softfloat/source/ARM-VFPv2/s_commonNaNToF16UI.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ) -{ - - return (uint_fast16_t) aPtr->sign<<15 | 0x7E00 | aPtr->v64>>54; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_commonNaNToF32UI.c b/softfloat/source/ARM-VFPv2/s_commonNaNToF32UI.c deleted file mode 100644 index 7b38167..0000000 --- a/softfloat/source/ARM-VFPv2/s_commonNaNToF32UI.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ) -{ - - return (uint_fast32_t) aPtr->sign<<31 | 0x7FC00000 | aPtr->v64>>41; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_commonNaNToF64UI.c b/softfloat/source/ARM-VFPv2/s_commonNaNToF64UI.c deleted file mode 100644 index 1484702..0000000 --- a/softfloat/source/ARM-VFPv2/s_commonNaNToF64UI.c +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ) -{ - - return - (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FF8000000000000 ) - | aPtr->v64>>12; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_extF80MToCommonNaN.c b/softfloat/source/ARM-VFPv2/s_extF80MToCommonNaN.c deleted file mode 100644 index 82216cf..0000000 --- a/softfloat/source/ARM-VFPv2/s_extF80MToCommonNaN.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is -| a NaN, converts this NaN to the common NaN form, and stores the resulting -| common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling -| NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_extF80MToCommonNaN( - const struct extFloat80M *aSPtr, struct commonNaN *zPtr ) -{ - - if ( extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = signExtF80UI64( aSPtr->signExp ); - zPtr->v64 = aSPtr->signif<<1; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_extF80UIToCommonNaN.c b/softfloat/source/ARM-VFPv2/s_extF80UIToCommonNaN.c deleted file mode 100644 index 2559fb6..0000000 --- a/softfloat/source/ARM-VFPv2/s_extF80UIToCommonNaN.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of an 80-bit extended floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_extF80UIToCommonNaN( - uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA64>>15; - zPtr->v64 = uiA0<<1; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_f128MToCommonNaN.c b/softfloat/source/ARM-VFPv2/s_f128MToCommonNaN.c deleted file mode 100644 index 322d25a..0000000 --- a/softfloat/source/ARM-VFPv2/s_f128MToCommonNaN.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, -| converts this NaN to the common NaN form, and stores the resulting common -| NaN at the location pointed to by 'zPtr'. If the NaN is a signaling NaN, -| the invalid exception is raised. Argument 'aWPtr' points to an array of -| four 32-bit elements that concatenate in the platform's normal endian order -| to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr ) -{ - - if ( f128M_isSignalingNaN( (const float128_t *) aWPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = aWPtr[indexWordHi( 4 )]>>31; - softfloat_shortShiftLeft128M( aWPtr, 16, (uint32_t *) &zPtr->v0 ); - -} - diff --git a/softfloat/source/ARM-VFPv2/s_f128UIToCommonNaN.c b/softfloat/source/ARM-VFPv2/s_f128UIToCommonNaN.c deleted file mode 100644 index 843c187..0000000 --- a/softfloat/source/ARM-VFPv2/s_f128UIToCommonNaN.c +++ /dev/null @@ -1,65 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to -| the common NaN form, and stores the resulting common NaN at the location -| pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception -| is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_f128UIToCommonNaN( - uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ) -{ - struct uint128 NaNSig; - - if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 ); - zPtr->sign = uiA64>>63; - zPtr->v64 = NaNSig.v64; - zPtr->v0 = NaNSig.v0; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_f16UIToCommonNaN.c b/softfloat/source/ARM-VFPv2/s_f16UIToCommonNaN.c deleted file mode 100644 index f5fe587..0000000 --- a/softfloat/source/ARM-VFPv2/s_f16UIToCommonNaN.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNF16UI( uiA ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA>>15; - zPtr->v64 = (uint_fast64_t) uiA<<54; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_f32UIToCommonNaN.c b/softfloat/source/ARM-VFPv2/s_f32UIToCommonNaN.c deleted file mode 100644 index 58726a3..0000000 --- a/softfloat/source/ARM-VFPv2/s_f32UIToCommonNaN.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNF32UI( uiA ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA>>31; - zPtr->v64 = (uint_fast64_t) uiA<<41; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_f64UIToCommonNaN.c b/softfloat/source/ARM-VFPv2/s_f64UIToCommonNaN.c deleted file mode 100644 index 03761e4..0000000 --- a/softfloat/source/ARM-VFPv2/s_f64UIToCommonNaN.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ) -{ - - if ( softfloat_isSigNaNF64UI( uiA ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zPtr->sign = uiA>>63; - zPtr->v64 = uiA<<12; - zPtr->v0 = 0; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_propagateNaNExtF80M.c b/softfloat/source/ARM-VFPv2/s_propagateNaNExtF80M.c deleted file mode 100644 index f10ed0b..0000000 --- a/softfloat/source/ARM-VFPv2/s_propagateNaNExtF80M.c +++ /dev/null @@ -1,86 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 80-bit extended floating-point values -| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result -| at the location pointed to by 'zSPtr'. If either original floating-point -| value is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ) -{ - const struct extFloat80M *sPtr; - bool isSigNaNA; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0; - - sPtr = aSPtr; - isSigNaNA = extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ); - if ( - isSigNaNA - || (bSPtr - && extF80M_isSignalingNaN( (const extFloat80_t *) bSPtr )) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) goto copyNonsig; - goto copyNonsigB; - } - uiZ64 = sPtr->signExp; - uiZ0 = sPtr->signif; - if ( isNaNExtF80UI( uiZ64, uiZ0 ) ) goto returnNonsig; - copyNonsigB: - sPtr = bSPtr; - copyNonsig: - uiZ64 = sPtr->signExp; - uiZ0 = sPtr->signif; - returnNonsig: - zSPtr->signExp = uiZ64; - zSPtr->signif = uiZ0 | UINT64_C( 0xC000000000000000 ); - -} - diff --git a/softfloat/source/ARM-VFPv2/s_propagateNaNExtF80UI.c b/softfloat/source/ARM-VFPv2/s_propagateNaNExtF80UI.c deleted file mode 100644 index bd23c24..0000000 --- a/softfloat/source/ARM-VFPv2/s_propagateNaNExtF80UI.c +++ /dev/null @@ -1,83 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting -| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 80-bit extended floating-point value, and assuming at least on of these -| floating-point values is a NaN, returns the bit pattern of the combined NaN -| result. If either original floating-point value is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNExtF80UI( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0 - ) -{ - bool isSigNaNA; - struct uint128 uiZ; - - isSigNaNA = softfloat_isSigNaNExtF80UI( uiA64, uiA0 ); - if ( isSigNaNA || softfloat_isSigNaNExtF80UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) goto returnNonsigA; - goto returnNonsigB; - } - if ( isNaNExtF80UI( uiA64, uiA0 ) ) { - returnNonsigA: - uiZ.v64 = uiA64; - uiZ.v0 = uiA0; - } else { - returnNonsigB: - uiZ.v64 = uiB64; - uiZ.v0 = uiB0; - } - uiZ.v0 | UINT64_C( 0xC000000000000000 ); - return uiZ; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_propagateNaNF128M.c b/softfloat/source/ARM-VFPv2/s_propagateNaNF128M.c deleted file mode 100644 index 23e766a..0000000 --- a/softfloat/source/ARM-VFPv2/s_propagateNaNF128M.c +++ /dev/null @@ -1,77 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 128-bit floating-point values pointed to by -| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location -| pointed to by 'zWPtr'. If either original floating-point value is a -| signaling NaN, the invalid exception is raised. Each of 'aWPtr', 'bWPtr', -| and 'zWPtr' points to an array of four 32-bit elements that concatenate in -| the platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ) -{ - const uint32_t *ptr; - bool isSigNaNA; - - ptr = aWPtr; - isSigNaNA = f128M_isSignalingNaN( (const float128_t *) aWPtr ); - if ( - isSigNaNA - || (bWPtr && f128M_isSignalingNaN( (const float128_t *) bWPtr )) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( ! isSigNaNA ) ptr = bWPtr; - goto copyNonsig; - } - if ( ! softfloat_isNaNF128M( aWPtr ) ) ptr = bWPtr; - copyNonsig: - zWPtr[indexWordHi( 4 )] = ptr[indexWordHi( 4 )] | 0x00008000; - zWPtr[indexWord( 4, 2 )] = ptr[indexWord( 4, 2 )]; - zWPtr[indexWord( 4, 1 )] = ptr[indexWord( 4, 1 )]; - zWPtr[indexWord( 4, 0 )] = ptr[indexWord( 4, 0 )]; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_propagateNaNF128UI.c b/softfloat/source/ARM-VFPv2/s_propagateNaNF128UI.c deleted file mode 100644 index b8882d7..0000000 --- a/softfloat/source/ARM-VFPv2/s_propagateNaNF128UI.c +++ /dev/null @@ -1,83 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the -| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 128-bit floating-point value, and assuming at least on of these floating- -| point values is a NaN, returns the bit pattern of the combined NaN result. -| If either original floating-point value is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNF128UI( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0 - ) -{ - bool isSigNaNA; - struct uint128 uiZ; - - isSigNaNA = softfloat_isSigNaNF128UI( uiA64, uiA0 ); - if ( isSigNaNA || softfloat_isSigNaNF128UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - if ( isSigNaNA ) goto returnNonsigA; - goto returnNonsigB; - } - if ( isNaNF128UI( uiA64, uiA0 ) ) { - returnNonsigA: - uiZ.v64 = uiA64; - uiZ.v0 = uiA0; - } else { - returnNonsigB: - uiZ.v64 = uiB64; - uiZ.v0 = uiB0; - } - uiZ.v64 |= UINT64_C( 0x0000800000000000 ); - return uiZ; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_propagateNaNF16UI.c b/softfloat/source/ARM-VFPv2/s_propagateNaNF16UI.c deleted file mode 100644 index e333328..0000000 --- a/softfloat/source/ARM-VFPv2/s_propagateNaNF16UI.c +++ /dev/null @@ -1,63 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast16_t - softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ) -{ - bool isSigNaNA; - - isSigNaNA = softfloat_isSigNaNF16UI( uiA ); - if ( isSigNaNA || softfloat_isSigNaNF16UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return (isSigNaNA ? uiA : uiB) | 0x0200; - } - return isNaNF16UI( uiA ) ? uiA : uiB; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_propagateNaNF32UI.c b/softfloat/source/ARM-VFPv2/s_propagateNaNF32UI.c deleted file mode 100644 index c7508ae..0000000 --- a/softfloat/source/ARM-VFPv2/s_propagateNaNF32UI.c +++ /dev/null @@ -1,63 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast32_t - softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ) -{ - bool isSigNaNA; - - isSigNaNA = softfloat_isSigNaNF32UI( uiA ); - if ( isSigNaNA || softfloat_isSigNaNF32UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return (isSigNaNA ? uiA : uiB) | 0x00400000; - } - return isNaNF32UI( uiA ) ? uiA : uiB; - -} - diff --git a/softfloat/source/ARM-VFPv2/s_propagateNaNF64UI.c b/softfloat/source/ARM-VFPv2/s_propagateNaNF64UI.c deleted file mode 100644 index 8c67763..0000000 --- a/softfloat/source/ARM-VFPv2/s_propagateNaNF64UI.c +++ /dev/null @@ -1,63 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ) -{ - bool isSigNaNA; - - isSigNaNA = softfloat_isSigNaNF64UI( uiA ); - if ( isSigNaNA || softfloat_isSigNaNF64UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return (isSigNaNA ? uiA : uiB) | UINT64_C( 0x0008000000000000 ); - } - return isNaNF64UI( uiA ) ? uiA : uiB; - -} - diff --git a/softfloat/source/ARM-VFPv2/softfloat_raiseFlags.c b/softfloat/source/ARM-VFPv2/softfloat_raiseFlags.c deleted file mode 100644 index 61046da..0000000 --- a/softfloat/source/ARM-VFPv2/softfloat_raiseFlags.c +++ /dev/null @@ -1,52 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Raises the exceptions specified by 'flags'. Floating-point traps can be -| defined here if desired. It is currently not possible for such a trap -| to substitute a result value. If traps are not implemented, this routine -| should be simply 'softfloat_exceptionFlags |= flags;'. -*----------------------------------------------------------------------------*/ -void softfloat_raiseFlags( uint_fast8_t flags ) -{ - - softfloat_exceptionFlags |= flags; - -} - diff --git a/softfloat/source/ARM-VFPv2/specialize.h b/softfloat/source/ARM-VFPv2/specialize.h deleted file mode 100644 index a75c585..0000000 --- a/softfloat/source/ARM-VFPv2/specialize.h +++ /dev/null @@ -1,346 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#ifndef specialize_h -#define specialize_h 1 - -#include "primitiveTypes.h" -#include "softfloat.h" -#include -#include - -/*---------------------------------------------------------------------------- -| Default value for 'softfloat_detectTininess'. -*----------------------------------------------------------------------------*/ -#define init_detectTininess softfloat_tininess_beforeRounding - -/*---------------------------------------------------------------------------- -| The values to return on conversions to 32-bit integer formats that raise an -| invalid exception. -*----------------------------------------------------------------------------*/ -#define ui32_fromPosOverflow 0xFFFFFFFF -#define ui32_fromNegOverflow 0 -#define ui32_fromNaN 0 -#define i32_fromPosOverflow 0x7FFFFFFF -#define i32_fromNegOverflow (-0x7FFFFFFF - 1) -#define i32_fromNaN 0 - -/*---------------------------------------------------------------------------- -| The values to return on conversions to 64-bit integer formats that raise an -| invalid exception. -*----------------------------------------------------------------------------*/ -#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF) -#define ui64_fromNegOverflow 0 -#define ui64_fromNaN 0 -#define i64_fromPosOverflow INT64_C(0x7FFFFFFFFFFFFFFF) -#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) -#define i64_fromNaN 0 - -/*---------------------------------------------------------------------------- -| "Common NaN" structure, used to transfer NaN representations from one format -| to another. -*----------------------------------------------------------------------------*/ -struct commonNaN { - bool sign; -#ifdef LITTLEENDIAN - uint64_t v0, v64; -#else - uint64_t v64, v0; -#endif -}; - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 16-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF16UI 0x7E00 - -/*---------------------------------------------------------------------------- -| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a -| 16-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f16UIToCommonNaN(uint_fast16_t uiA, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr); - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 32-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF32UI 0x7FC00000 - -/*---------------------------------------------------------------------------- -| Returns true when 32-bit unsigned integer 'uiA' has the bit pattern of a -| 32-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f32UIToCommonNaN(uint_fast32_t uiA, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr); - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 64-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF64UI UINT64_C(0x7FF8000000000000) - -/*---------------------------------------------------------------------------- -| Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a -| 64-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF64UI(uiA) \ - ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF))) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f64UIToCommonNaN(uint_fast64_t uiA, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr); - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 80-bit extended floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNExtF80UI64 0x7FFF -#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000) - -/*---------------------------------------------------------------------------- -| Returns true when the 80-bit unsigned integer formed from concatenating -| 16-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of an 80-bit extended -| floating-point signaling NaN. -| Note: This macro evaluates its arguments more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNExtF80UI(uiA64, uiA0) \ - ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF))) - -#ifdef SOFTFLOAT_FAST_INT64 - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is -| defined. -*----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of an 80-bit extended floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and returns the bit pattern of this value as an unsigned -| integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr); - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting -| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 80-bit extended floating-point value, and assuming at least on of these -| floating-point values is a NaN, returns the bit pattern of the combined NaN -| result. If either original floating-point value is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 128-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF128UI64 UINT64_C(0x7FFF800000000000) -#define defaultNaNF128UI0 UINT64_C(0) - -/*---------------------------------------------------------------------------- -| Returns true when the 128-bit unsigned integer formed from concatenating -| 64-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of a 128-bit floating- -| point signaling NaN. -| Note: This macro evaluates its arguments more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF128UI(uiA64, uiA0) \ - ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF)))) - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to -| the common NaN form, and stores the resulting common NaN at the location -| pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception -| is raised. -*----------------------------------------------------------------------------*/ -void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*); - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the -| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 128-bit floating-point value, and assuming at least on of these floating- -| point values is a NaN, returns the bit pattern of the combined NaN result. -| If either original floating-point value is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0); - -#else - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not -| defined. -*----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- -| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is -| a NaN, converts this NaN to the common NaN form, and stores the resulting -| common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling -| NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and stores this NaN at the location pointed to by -| 'zSPtr'. -*----------------------------------------------------------------------------*/ -void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr); - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 80-bit extended floating-point values -| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result -| at the location pointed to by 'zSPtr'. If either original floating-point -| value is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 128-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF128UI96 0x7FFF8000 -#define defaultNaNF128UI64 0 -#define defaultNaNF128UI32 0 -#define defaultNaNF128UI0 0 - -/*---------------------------------------------------------------------------- -| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, -| converts this NaN to the common NaN form, and stores the resulting common -| NaN at the location pointed to by 'zPtr'. If the NaN is a signaling NaN, -| the invalid exception is raised. Argument 'aWPtr' points to an array of -| four 32-bit elements that concatenate in the platform's normal endian order -| to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr); - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and stores this NaN at the location pointed to by 'zWPtr'. Argument -| 'zWPtr' points to an array of four 32-bit elements that concatenate in the -| platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr); - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 128-bit floating-point values pointed to by -| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location -| pointed to by 'zWPtr'. If either original floating-point value is a -| signaling NaN, the invalid exception is raised. Each of 'aWPtr', 'bWPtr', -| and 'zWPtr' points to an array of four 32-bit elements that concatenate in -| the platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr); - -#endif - -#endif diff --git a/softfloat/source/RISCV/extF80M_isSignalingNaN.c b/softfloat/source/RISCV/extF80M_isSignalingNaN.c deleted file mode 100644 index 85ee211..0000000 --- a/softfloat/source/RISCV/extF80M_isSignalingNaN.c +++ /dev/null @@ -1,57 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool extF80M_isSignalingNaN( const extFloat80_t *aPtr ) -{ - const struct extFloat80M *aSPtr; - uint64_t uiA0; - - aSPtr = (const struct extFloat80M *) aPtr; - if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false; - uiA0 = aSPtr->signif; - return - ! (uiA0 & UINT64_C( 0x4000000000000000 )) - && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF)); - -} - diff --git a/softfloat/source/RISCV/f128M_isSignalingNaN.c b/softfloat/source/RISCV/f128M_isSignalingNaN.c deleted file mode 100644 index 79a7077..0000000 --- a/softfloat/source/RISCV/f128M_isSignalingNaN.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "primitives.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool f128M_isSignalingNaN( const float128_t *aPtr ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false; - return - ((uiA96 & 0x00007FFF) != 0) - || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )]) - != 0); - -} - diff --git a/softfloat/source/RISCV/s_bf16UIToCommonNaN.c b/softfloat/source/RISCV/s_bf16UIToCommonNaN.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_bf16UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_commonNaNToBF16UI.c b/softfloat/source/RISCV/s_commonNaNToBF16UI.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_commonNaNToBF16UI.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_commonNaNToExtF80M.c b/softfloat/source/RISCV/s_commonNaNToExtF80M.c deleted file mode 100644 index 6d1e67e..0000000 --- a/softfloat/source/RISCV/s_commonNaNToExtF80M.c +++ /dev/null @@ -1,57 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "softfloat_types.h" - -#define softfloat_commonNaNToExtF80M softfloat_commonNaNToExtF80M -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into an 80-bit extended -| floating-point NaN, and stores this NaN at the location pointed to by -| `zSPtr'. -*----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ) -{ - - zSPtr->signExp = defaultNaNExtF80UI64; - zSPtr->signif = defaultNaNExtF80UI0; - -} - diff --git a/softfloat/source/RISCV/s_commonNaNToExtF80UI.c b/softfloat/source/RISCV/s_commonNaNToExtF80UI.c deleted file mode 100644 index 953b97a..0000000 --- a/softfloat/source/RISCV/s_commonNaNToExtF80UI.c +++ /dev/null @@ -1,57 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "primitiveTypes.h" - -#define softfloat_commonNaNToExtF80UI softfloat_commonNaNToExtF80UI -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into an 80-bit extended -| floating-point NaN, and returns the bit pattern of this value as an unsigned -| integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ) -{ - struct uint128 uiZ; - - uiZ.v64 = defaultNaNExtF80UI64; - uiZ.v0 = defaultNaNExtF80UI0; - return uiZ; - -} - diff --git a/softfloat/source/RISCV/s_commonNaNToF128M.c b/softfloat/source/RISCV/s_commonNaNToF128M.c deleted file mode 100644 index d91b62e..0000000 --- a/softfloat/source/RISCV/s_commonNaNToF128M.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#define softfloat_commonNaNToF128M softfloat_commonNaNToF128M -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point -| NaN, and stores this NaN at the location pointed to by `zWPtr'. Argument -| `zWPtr' points to an array of four 32-bit elements that concatenate in the -| platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ) -{ - - zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96; - zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64; - zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32; - zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0; - -} - diff --git a/softfloat/source/RISCV/s_commonNaNToF128UI.c b/softfloat/source/RISCV/s_commonNaNToF128UI.c deleted file mode 100644 index b4c578d..0000000 --- a/softfloat/source/RISCV/s_commonNaNToF128UI.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "primitiveTypes.h" - -#define softfloat_commonNaNToF128UI softfloat_commonNaNToF128UI -#include "specialize.h" - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr ) -{ - struct uint128 uiZ; - - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - return uiZ; - -} - diff --git a/softfloat/source/RISCV/s_commonNaNToF16UI.c b/softfloat/source/RISCV/s_commonNaNToF16UI.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_commonNaNToF16UI.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_commonNaNToF32UI.c b/softfloat/source/RISCV/s_commonNaNToF32UI.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_commonNaNToF32UI.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_commonNaNToF64UI.c b/softfloat/source/RISCV/s_commonNaNToF64UI.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_commonNaNToF64UI.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_extF80MToCommonNaN.c b/softfloat/source/RISCV/s_extF80MToCommonNaN.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_extF80MToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_extF80UIToCommonNaN.c b/softfloat/source/RISCV/s_extF80UIToCommonNaN.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_extF80UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_f128MToCommonNaN.c b/softfloat/source/RISCV/s_f128MToCommonNaN.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_f128MToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_f128UIToCommonNaN.c b/softfloat/source/RISCV/s_f128UIToCommonNaN.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_f128UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_f16UIToCommonNaN.c b/softfloat/source/RISCV/s_f16UIToCommonNaN.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_f16UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_f32UIToCommonNaN.c b/softfloat/source/RISCV/s_f32UIToCommonNaN.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_f32UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_f64UIToCommonNaN.c b/softfloat/source/RISCV/s_f64UIToCommonNaN.c deleted file mode 100644 index 861b269..0000000 --- a/softfloat/source/RISCV/s_f64UIToCommonNaN.c +++ /dev/null @@ -1,5 +0,0 @@ - -/*---------------------------------------------------------------------------- -| This file intentionally contains no code. -*----------------------------------------------------------------------------*/ - diff --git a/softfloat/source/RISCV/s_propagateNaNExtF80M.c b/softfloat/source/RISCV/s_propagateNaNExtF80M.c deleted file mode 100644 index 8adc62e..0000000 --- a/softfloat/source/RISCV/s_propagateNaNExtF80M.c +++ /dev/null @@ -1,74 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 80-bit extended floating-point values -| pointed to by `aSPtr' and `bSPtr' is a NaN, stores the combined NaN result -| at the location pointed to by `zSPtr'. If either original floating-point -| value is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ) -{ - uint_fast16_t ui64; - uint_fast64_t ui0; - - ui64 = aSPtr->signExp; - ui0 = aSPtr->signif; - if ( - softfloat_isSigNaNExtF80UI( ui64, ui0 ) - || (bSPtr - && (ui64 = bSPtr->signExp, - ui0 = bSPtr->signif, - softfloat_isSigNaNExtF80UI( ui64, ui0 ))) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zSPtr->signExp = defaultNaNExtF80UI64; - zSPtr->signif = defaultNaNExtF80UI0; - -} - diff --git a/softfloat/source/RISCV/s_propagateNaNExtF80UI.c b/softfloat/source/RISCV/s_propagateNaNExtF80UI.c deleted file mode 100644 index 88bfee5..0000000 --- a/softfloat/source/RISCV/s_propagateNaNExtF80UI.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating `uiA64' and -| `uiA0' as an 80-bit extended floating-point value, and likewise interpreting -| the unsigned integer formed from concatenating `uiB64' and `uiB0' as another -| 80-bit extended floating-point value, and assuming at least on of these -| floating-point values is a NaN, returns the bit pattern of the combined NaN -| result. If either original floating-point value is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNExtF80UI( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0 - ) -{ - struct uint128 uiZ; - - if ( - softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) - || softfloat_isSigNaNExtF80UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - uiZ.v64 = defaultNaNExtF80UI64; - uiZ.v0 = defaultNaNExtF80UI0; - return uiZ; - -} - diff --git a/softfloat/source/RISCV/s_propagateNaNF128M.c b/softfloat/source/RISCV/s_propagateNaNF128M.c deleted file mode 100644 index df76ab2..0000000 --- a/softfloat/source/RISCV/s_propagateNaNF128M.c +++ /dev/null @@ -1,68 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2018 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 128-bit floating-point values pointed to by -| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location -| pointed to by 'zWPtr'. If either original floating-point value is a -| signaling NaN, the invalid exception is raised. Each of 'aWPtr', 'bWPtr', -| and 'zWPtr' points to an array of four 32-bit elements that concatenate in -| the platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ) -{ - - if ( - f128M_isSignalingNaN( (const float128_t *) aWPtr ) - || (bWPtr && f128M_isSignalingNaN( (const float128_t *) bWPtr )) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96; - zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64; - zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32; - zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0; - -} - diff --git a/softfloat/source/RISCV/s_propagateNaNF128UI.c b/softfloat/source/RISCV/s_propagateNaNF128UI.c deleted file mode 100644 index 49e2535..0000000 --- a/softfloat/source/RISCV/s_propagateNaNF128UI.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating `uiA64' and -| `uiA0' as a 128-bit floating-point value, and likewise interpreting the -| unsigned integer formed from concatenating `uiB64' and `uiB0' as another -| 128-bit floating-point value, and assuming at least on of these floating- -| point values is a NaN, returns the bit pattern of the combined NaN result. -| If either original floating-point value is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNF128UI( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0 - ) -{ - struct uint128 uiZ; - - if ( - softfloat_isSigNaNF128UI( uiA64, uiA0 ) - || softfloat_isSigNaNF128UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - return uiZ; - -} - diff --git a/softfloat/source/RISCV/s_propagateNaNF16UI.c b/softfloat/source/RISCV/s_propagateNaNF16UI.c deleted file mode 100644 index 228dcd8..0000000 --- a/softfloat/source/RISCV/s_propagateNaNF16UI.c +++ /dev/null @@ -1,58 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting `uiA' and `uiB' as the bit patterns of two 16-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either `uiA' or `uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast16_t - softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ) -{ - - if ( softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return defaultNaNF16UI; - -} - diff --git a/softfloat/source/RISCV/s_propagateNaNF32UI.c b/softfloat/source/RISCV/s_propagateNaNF32UI.c deleted file mode 100644 index c6308cc..0000000 --- a/softfloat/source/RISCV/s_propagateNaNF32UI.c +++ /dev/null @@ -1,58 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting `uiA' and `uiB' as the bit patterns of two 32-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either `uiA' or `uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast32_t - softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ) -{ - - if ( softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return defaultNaNF32UI; - -} - diff --git a/softfloat/source/RISCV/s_propagateNaNF64UI.c b/softfloat/source/RISCV/s_propagateNaNF64UI.c deleted file mode 100644 index 2203665..0000000 --- a/softfloat/source/RISCV/s_propagateNaNF64UI.c +++ /dev/null @@ -1,58 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Interpreting `uiA' and `uiB' as the bit patterns of two 64-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either `uiA' or `uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ) -{ - - if ( softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return defaultNaNF64UI; - -} - diff --git a/softfloat/source/RISCV/softfloat_raiseFlags.c b/softfloat/source/RISCV/softfloat_raiseFlags.c deleted file mode 100644 index 3115306..0000000 --- a/softfloat/source/RISCV/softfloat_raiseFlags.c +++ /dev/null @@ -1,52 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "softfloat.h" - -/*---------------------------------------------------------------------------- -| Raises the exceptions specified by `flags'. Floating-point traps can be -| defined here if desired. It is currently not possible for such a trap -| to substitute a result value. If traps are not implemented, this routine -| should be simply `softfloat_exceptionFlags |= flags;'. -*----------------------------------------------------------------------------*/ -void softfloat_raiseFlags( uint_fast8_t flags ) -{ - - softfloat_exceptionFlags |= flags; - -} - diff --git a/softfloat/source/RISCV/specialize.h b/softfloat/source/RISCV/specialize.h deleted file mode 100644 index fe19494..0000000 --- a/softfloat/source/RISCV/specialize.h +++ /dev/null @@ -1,421 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2018 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#ifndef specialize_h -#define specialize_h 1 - -#include "primitiveTypes.h" -#include "softfloat.h" -#include -#include - -/*---------------------------------------------------------------------------- -| Default value for 'softfloat_detectTininess'. -*----------------------------------------------------------------------------*/ -#define init_detectTininess softfloat_tininess_afterRounding - -/*---------------------------------------------------------------------------- -| The values to return on conversions to 32-bit integer formats that raise an -| invalid exception. -*----------------------------------------------------------------------------*/ -#define ui32_fromPosOverflow 0xFFFFFFFF -#define ui32_fromNegOverflow 0 -#define ui32_fromNaN 0xFFFFFFFF -#define i32_fromPosOverflow 0x7FFFFFFF -#define i32_fromNegOverflow (-0x7FFFFFFF - 1) -#define i32_fromNaN 0x7FFFFFFF - -/*---------------------------------------------------------------------------- -| The values to return on conversions to 64-bit integer formats that raise an -| invalid exception. -*----------------------------------------------------------------------------*/ -#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF) -#define ui64_fromNegOverflow 0 -#define ui64_fromNaN UINT64_C(0xFFFFFFFFFFFFFFFF) -#define i64_fromPosOverflow INT64_C(0x7FFFFFFFFFFFFFFF) -#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) -#define i64_fromNaN INT64_C(0x7FFFFFFFFFFFFFFF) - -/*---------------------------------------------------------------------------- -| "Common NaN" structure, used to transfer NaN representations from one format -| to another. -*----------------------------------------------------------------------------*/ -struct commonNaN { - char _unused; -}; - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 16-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF16UI 0x7E00 - -/*---------------------------------------------------------------------------- -| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a -| 16-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF)) - -/*---------------------------------------------------------------------------- -| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a -| 16-bit brain floating-point (BF16) signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNBF16UI(uiA) ((((uiA)&0x7FC0) == 0x7F80) && ((uiA)&0x003F)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_f16UIToCommonNaN(uiA, zPtr) \ - if(!((uiA)&0x0200)) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 16-bit BF16 floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_bf16UIToCommonNaN(uiA, zPtr) \ - if(!((uiA)&0x0040)) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -#define softfloat_commonNaNToF16UI(aPtr) ((uint_fast16_t)defaultNaNF16UI) - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 16-bit BF16 floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNBF16UI 0x7FC0 - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -#define softfloat_commonNaNToBF16UI(aPtr) ((uint_fast16_t)defaultNaNBF16UI) - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 32-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF32UI 0x7FC00000 - -/*---------------------------------------------------------------------------- -| Returns true when 32-bit unsigned integer 'uiA' has the bit pattern of a -| 32-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF)) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_f32UIToCommonNaN(uiA, zPtr) \ - if(!((uiA)&0x00400000)) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -#define softfloat_commonNaNToF32UI(aPtr) ((uint_fast32_t)defaultNaNF32UI) - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 64-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF64UI UINT64_C(0x7FF8000000000000) - -/*---------------------------------------------------------------------------- -| Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a -| 64-bit floating-point signaling NaN. -| Note: This macro evaluates its argument more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF64UI(uiA) \ - ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF))) - -/*---------------------------------------------------------------------------- -| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_f64UIToCommonNaN(uiA, zPtr) \ - if(!((uiA)&UINT64_C(0x0008000000000000))) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -#define softfloat_commonNaNToF64UI(aPtr) ((uint_fast64_t)defaultNaNF64UI) - -/*---------------------------------------------------------------------------- -| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- -| point values, at least one of which is a NaN, returns the bit pattern of -| the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 80-bit extended floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNExtF80UI64 0x7FFF -#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000) - -/*---------------------------------------------------------------------------- -| Returns true when the 80-bit unsigned integer formed from concatenating -| 16-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of an 80-bit extended -| floating-point signaling NaN. -| Note: This macro evaluates its arguments more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNExtF80UI(uiA64, uiA0) \ - ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF))) - -#ifdef SOFTFLOAT_FAST_INT64 - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is -| defined. -*----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of an 80-bit extended floating-point NaN, converts -| this NaN to the common NaN form, and stores the resulting common NaN at the -| location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_extF80UIToCommonNaN(uiA64, uiA0, zPtr) \ - if(!((uiA0)&UINT64_C(0x4000000000000000))) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and returns the bit pattern of this value as an unsigned -| integer. -*----------------------------------------------------------------------------*/ -#if defined INLINE && !defined softfloat_commonNaNToExtF80UI -INLINE -struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr) { - struct uint128 uiZ; - uiZ.v64 = defaultNaNExtF80UI64; - uiZ.v0 = defaultNaNExtF80UI0; - return uiZ; -} -#else -struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr); -#endif - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting -| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 80-bit extended floating-point value, and assuming at least on of these -| floating-point values is a NaN, returns the bit pattern of the combined NaN -| result. If either original floating-point value is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 128-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF128UI64 UINT64_C(0x7FFF800000000000) -#define defaultNaNF128UI0 UINT64_C(0) - -/*---------------------------------------------------------------------------- -| Returns true when the 128-bit unsigned integer formed from concatenating -| 64-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of a 128-bit floating- -| point signaling NaN. -| Note: This macro evaluates its arguments more than once. -*----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF128UI(uiA64, uiA0) \ - ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF)))) - -/*---------------------------------------------------------------------------- -| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' -| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to -| the common NaN form, and stores the resulting common NaN at the location -| pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception -| is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_f128UIToCommonNaN(uiA64, uiA0, zPtr) \ - if(!((uiA64)&UINT64_C(0x0000800000000000))) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and returns the bit pattern of this value as an unsigned integer. -*----------------------------------------------------------------------------*/ -#if defined INLINE && !defined softfloat_commonNaNToF128UI -INLINE -struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN* aPtr) { - struct uint128 uiZ; - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - return uiZ; -} -#else -struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*); -#endif - -/*---------------------------------------------------------------------------- -| Interpreting the unsigned integer formed from concatenating 'uiA64' and -| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the -| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another -| 128-bit floating-point value, and assuming at least on of these floating- -| point values is a NaN, returns the bit pattern of the combined NaN result. -| If either original floating-point value is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0); - -#else - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not -| defined. -*----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- -| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is -| a NaN, converts this NaN to the common NaN form, and stores the resulting -| common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling -| NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -#define softfloat_extF80MToCommonNaN(aSPtr, zPtr) \ - if(!((aSPtr)->signif & UINT64_C(0x4000000000000000))) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended -| floating-point NaN, and stores this NaN at the location pointed to by -| 'zSPtr'. -*----------------------------------------------------------------------------*/ -#if defined INLINE && !defined softfloat_commonNaNToExtF80M -INLINE -void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr) { - zSPtr->signExp = defaultNaNExtF80UI64; - zSPtr->signif = defaultNaNExtF80UI0; -} -#else -void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr); -#endif - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 80-bit extended floating-point values -| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result -| at the location pointed to by 'zSPtr'. If either original floating-point -| value is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ -void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr); - -/*---------------------------------------------------------------------------- -| The bit pattern for a default generated 128-bit floating-point NaN. -*----------------------------------------------------------------------------*/ -#define defaultNaNF128UI96 0x7FFF8000 -#define defaultNaNF128UI64 0 -#define defaultNaNF128UI32 0 -#define defaultNaNF128UI0 0 - -/*---------------------------------------------------------------------------- -| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, -| converts this NaN to the common NaN form, and stores the resulting common -| NaN at the location pointed to by 'zPtr'. If the NaN is a signaling NaN, -| the invalid exception is raised. Argument 'aWPtr' points to an array of -| four 32-bit elements that concatenate in the platform's normal endian order -| to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -#define softfloat_f128MToCommonNaN(aWPtr, zPtr) \ - if(!((aWPtr)[indexWordHi(4)] & UINT64_C(0x0000800000000000))) \ - softfloat_raiseFlags(softfloat_flag_invalid) - -/*---------------------------------------------------------------------------- -| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point -| NaN, and stores this NaN at the location pointed to by 'zWPtr'. Argument -| 'zWPtr' points to an array of four 32-bit elements that concatenate in the -| platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -#if defined INLINE && !defined softfloat_commonNaNToF128M -INLINE -void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr) { - zWPtr[indexWord(4, 3)] = defaultNaNF128UI96; - zWPtr[indexWord(4, 2)] = defaultNaNF128UI64; - zWPtr[indexWord(4, 1)] = defaultNaNF128UI32; - zWPtr[indexWord(4, 0)] = defaultNaNF128UI0; -} -#else -void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr); -#endif - -/*---------------------------------------------------------------------------- -| Assuming at least one of the two 128-bit floating-point values pointed to by -| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location -| pointed to by 'zWPtr'. If either original floating-point value is a -| signaling NaN, the invalid exception is raised. Each of 'aWPtr', 'bWPtr', -| and 'zWPtr' points to an array of four 32-bit elements that concatenate in -| the platform's normal endian order to form a 128-bit floating-point value. -*----------------------------------------------------------------------------*/ -void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr); - -#endif - -#endif diff --git a/softfloat/source/bf16_isSignalingNaN.c b/softfloat/source/bf16_isSignalingNaN.c deleted file mode 100644 index 79ca87f..0000000 --- a/softfloat/source/bf16_isSignalingNaN.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool bf16_isSignalingNaN( bfloat16_t a ) -{ - union ui16_bf16 uA; - - uA.f = a; - return softfloat_isSigNaNBF16UI( uA.ui ); - -} - diff --git a/softfloat/source/bf16_to_f32.c b/softfloat/source/bf16_to_f32.c deleted file mode 100644 index b86482c..0000000 --- a/softfloat/source/bf16_to_f32.c +++ /dev/null @@ -1,90 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t bf16_to_f32( bfloat16_t a ) -{ - union ui16_bf16 uA; - uint_fast16_t uiA; - bool sign; - int_fast16_t exp; - uint_fast16_t frac; - struct commonNaN commonNaN; - uint_fast32_t uiZ; - struct exp8_sig16 normExpSig; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signBF16UI( uiA ); - exp = expBF16UI( uiA ); - frac = fracBF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - // NaN or Inf - if ( exp == 0xFF ) { - if ( frac ) { - softfloat_bf16UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToF32UI( &commonNaN ); - } else { - uiZ = packToF32UI( sign, 0xFF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - // packToF32UI simply packs bitfields without any numerical change - // which means it can be used directly for any BF16 to f32 conversions which - // does not require bits manipulation - // (that is everything where the 16-bit are just padded right with 16 zeros, including - // subnormal numbers) - uiZ = packToF32UI( sign, exp, ((uint_fast32_t) frac) <<16 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - - - diff --git a/softfloat/source/extF80M_add.c b/softfloat/source/extF80M_add.c deleted file mode 100644 index 02e415f..0000000 --- a/softfloat/source/extF80M_add.c +++ /dev/null @@ -1,100 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - extF80M_add( - const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool signA; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - bool signB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) - extFloat80_t - (*magsFuncPtr)( - uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool ); -#endif - - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - uiA64 = aSPtr->signExp; - uiA0 = aSPtr->signif; - signA = signExtF80UI64( uiA64 ); - uiB64 = bSPtr->signExp; - uiB0 = bSPtr->signif; - signB = signExtF80UI64( uiB64 ); -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) - if ( signA == signB ) { - *zPtr = softfloat_addMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA ); - } else { - *zPtr = softfloat_subMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA ); - } -#else - magsFuncPtr = - (signA == signB) ? softfloat_addMagsExtF80 : softfloat_subMagsExtF80; - *zPtr = (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA ); -#endif - -} - -#else - -void - extF80M_add( - const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr ) -{ - - softfloat_addExtF80M( - (const struct extFloat80M *) aPtr, - (const struct extFloat80M *) bPtr, - (struct extFloat80M *) zPtr, - false - ); - -} - -#endif - diff --git a/softfloat/source/extF80M_div.c b/softfloat/source/extF80M_div.c deleted file mode 100644 index 4d543ce..0000000 --- a/softfloat/source/extF80M_div.c +++ /dev/null @@ -1,194 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - extF80M_div( - const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr ) -{ - - *zPtr = extF80_div( *aPtr, *bPtr ); - -} - -#else - -void - extF80M_div( - const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - struct extFloat80M *zSPtr; - uint_fast16_t uiA64; - int32_t expA; - uint_fast16_t uiB64; - int32_t expB; - bool signZ; - uint64_t sigA, x64; - int32_t expZ; - int shiftDist; - uint32_t y[3], recip32, sigB[3]; - int ix; - uint32_t q, qs[2]; - uint_fast16_t uiZ64; - uint64_t uiZ0; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - zSPtr = (struct extFloat80M *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - expA = expExtF80UI64( uiA64 ); - uiB64 = bSPtr->signExp; - expB = expExtF80UI64( uiB64 ); - signZ = signExtF80UI64( uiA64 ) ^ signExtF80UI64( uiB64 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) { - if ( softfloat_tryPropagateNaNExtF80M( aSPtr, bSPtr, zSPtr ) ) return; - if ( expA == 0x7FFF ) { - if ( expB == 0x7FFF ) goto invalid; - goto infinity; - } - goto zero; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sigA = aSPtr->signif; - x64 = bSPtr->signif; - if ( ! expB ) expB = 1; - if ( ! (x64 & UINT64_C( 0x8000000000000000 )) ) { - if ( ! x64 ) { - if ( ! sigA ) goto invalid; - softfloat_raiseFlags( softfloat_flag_infinite ); - goto infinity; - } - expB += softfloat_normExtF80SigM( &x64 ); - } - if ( ! expA ) expA = 1; - if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigA ) goto zero; - expA += softfloat_normExtF80SigM( &sigA ); - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA - expB + 0x3FFF; - shiftDist = 29; - if ( sigA < x64 ) { - --expZ; - shiftDist = 30; - } - softfloat_shortShiftLeft64To96M( sigA, shiftDist, y ); - recip32 = softfloat_approxRecip32_1( x64>>32 ); - sigB[indexWord( 3, 0 )] = (uint32_t) x64<<30; - x64 >>= 2; - sigB[indexWord( 3, 2 )] = x64>>32; - sigB[indexWord( 3, 1 )] = x64; - ix = 2; - for (;;) { - x64 = (uint64_t) y[indexWordHi( 3 )] * recip32; - q = (x64 + 0x80000000)>>32; - --ix; - if ( ix < 0 ) break; - softfloat_remStep96MBy32( y, 29, sigB, q, y ); - if ( y[indexWordHi( 3 )] & 0x80000000 ) { - --q; - softfloat_add96M( y, sigB, y ); - } - qs[ix] = q; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ((q + 1) & 0x3FFFFF) < 2 ) { - softfloat_remStep96MBy32( y, 29, sigB, q, y ); - if ( y[indexWordHi( 3 )] & 0x80000000 ) { - --q; - softfloat_add96M( y, sigB, y ); - } else if ( softfloat_compare96M( sigB, y ) <= 0 ) { - ++q; - softfloat_sub96M( y, sigB, y ); - } - if ( - y[indexWordLo( 3 )] || y[indexWord( 3, 1 )] || y[indexWord( 3, 2 )] - ) { - q |= 1; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - x64 = (uint64_t) q<<9; - y[indexWord( 3, 0 )] = x64; - x64 = ((uint64_t) qs[0]<<6) + (x64>>32); - y[indexWord( 3, 1 )] = x64; - y[indexWord( 3, 2 )] = (qs[1]<<3) + (x64>>32); - softfloat_roundPackMToExtF80M( - signZ, expZ, y, extF80_roundingPrecision, zSPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_invalidExtF80M( zSPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infinity: - uiZ64 = packToExtF80UI64( signZ, 0x7FFF ); - uiZ0 = UINT64_C( 0x8000000000000000 ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ64 = packToExtF80UI64( signZ, 0 ); - uiZ0 = 0; - uiZ: - zSPtr->signExp = uiZ64; - zSPtr->signif = uiZ0; - -} - -#endif - diff --git a/softfloat/source/extF80M_eq.c b/softfloat/source/extF80M_eq.c deleted file mode 100644 index e17aa24..0000000 --- a/softfloat/source/extF80M_eq.c +++ /dev/null @@ -1,98 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool extF80M_eq( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - - return extF80_eq( *aPtr, *bPtr ); - -} - -#else - -bool extF80M_eq( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - uint_fast16_t uiA64; - uint64_t uiA0; - uint_fast16_t uiB64; - uint64_t uiB0; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - uiA0 = aSPtr->signif; - uiB64 = bSPtr->signExp; - uiB0 = bSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - if ( - softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) - || softfloat_isSigNaNExtF80UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( uiA0 == uiB0 ) { - return (uiA64 == uiB64) || ! uiA0; - } else { - if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) { - return ! softfloat_compareNonnormExtF80M( aSPtr, bSPtr ); - } - return false; - } - -} - -#endif - diff --git a/softfloat/source/extF80M_eq_signaling.c b/softfloat/source/extF80M_eq_signaling.c deleted file mode 100644 index c4a7322..0000000 --- a/softfloat/source/extF80M_eq_signaling.c +++ /dev/null @@ -1,92 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool extF80M_eq_signaling( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - - return extF80_eq_signaling( *aPtr, *bPtr ); - -} - -#else - -bool extF80M_eq_signaling( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - uint_fast16_t uiA64; - uint64_t uiA0; - uint_fast16_t uiB64; - uint64_t uiB0; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - uiA0 = aSPtr->signif; - uiB64 = bSPtr->signExp; - uiB0 = bSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( uiA0 == uiB0 ) { - return (uiA64 == uiB64) || ! uiA0; - } else { - if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) { - return ! softfloat_compareNonnormExtF80M( aSPtr, bSPtr ); - } - return false; - } - -} - -#endif - diff --git a/softfloat/source/extF80M_le.c b/softfloat/source/extF80M_le.c deleted file mode 100644 index e54eb9e..0000000 --- a/softfloat/source/extF80M_le.c +++ /dev/null @@ -1,106 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool extF80M_le( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - - return extF80_le( *aPtr, *bPtr ); - -} - -#else - -bool extF80M_le( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - uint_fast16_t uiA64; - uint64_t uiA0; - uint_fast16_t uiB64; - uint64_t uiB0; - bool signA, ltMags; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - uiA0 = aSPtr->signif; - uiB64 = bSPtr->signExp; - uiB0 = bSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signA = signExtF80UI64( uiA64 ); - if ( (uiA64 ^ uiB64) & 0x8000 ) { - /*-------------------------------------------------------------------- - | Signs are different. - *--------------------------------------------------------------------*/ - return signA || ! (uiA0 | uiB0); - } else { - /*-------------------------------------------------------------------- - | Signs are the same. - *--------------------------------------------------------------------*/ - if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) { - return (softfloat_compareNonnormExtF80M( aSPtr, bSPtr ) <= 0); - } - if ( uiA64 == uiB64 ) { - if ( uiA0 == uiB0 ) return true; - ltMags = (uiA0 < uiB0); - } else { - ltMags = (uiA64 < uiB64); - } - return signA ^ ltMags; - } - -} - -#endif - diff --git a/softfloat/source/extF80M_le_quiet.c b/softfloat/source/extF80M_le_quiet.c deleted file mode 100644 index 943f262..0000000 --- a/softfloat/source/extF80M_le_quiet.c +++ /dev/null @@ -1,112 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool extF80M_le_quiet( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - - return extF80_le_quiet( *aPtr, *bPtr ); - -} - -#else - -bool extF80M_le_quiet( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - uint_fast16_t uiA64; - uint64_t uiA0; - uint_fast16_t uiB64; - uint64_t uiB0; - bool signA, ltMags; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - uiA0 = aSPtr->signif; - uiB64 = bSPtr->signExp; - uiB0 = bSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - if ( - softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) - || softfloat_isSigNaNExtF80UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signA = signExtF80UI64( uiA64 ); - if ( (uiA64 ^ uiB64) & 0x8000 ) { - /*-------------------------------------------------------------------- - | Signs are different. - *--------------------------------------------------------------------*/ - return signA || ! (uiA0 | uiB0); - } else { - /*-------------------------------------------------------------------- - | Signs are the same. - *--------------------------------------------------------------------*/ - if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) { - return (softfloat_compareNonnormExtF80M( aSPtr, bSPtr ) <= 0); - } - if ( uiA64 == uiB64 ) { - if ( uiA0 == uiB0 ) return true; - ltMags = (uiA0 < uiB0); - } else { - ltMags = (uiA64 < uiB64); - } - return signA ^ ltMags; - } - -} - -#endif - diff --git a/softfloat/source/extF80M_lt.c b/softfloat/source/extF80M_lt.c deleted file mode 100644 index cbc562f..0000000 --- a/softfloat/source/extF80M_lt.c +++ /dev/null @@ -1,106 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool extF80M_lt( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - - return extF80_lt( *aPtr, *bPtr ); - -} - -#else - -bool extF80M_lt( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - uint_fast16_t uiA64; - uint64_t uiA0; - uint_fast16_t uiB64; - uint64_t uiB0; - bool signA, ltMags; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - uiA0 = aSPtr->signif; - uiB64 = bSPtr->signExp; - uiB0 = bSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signA = signExtF80UI64( uiA64 ); - if ( (uiA64 ^ uiB64) & 0x8000 ) { - /*-------------------------------------------------------------------- - | Signs are different. - *--------------------------------------------------------------------*/ - return signA && ((uiA0 | uiB0) != 0); - } else { - /*-------------------------------------------------------------------- - | Signs are the same. - *--------------------------------------------------------------------*/ - if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) { - return (softfloat_compareNonnormExtF80M( aSPtr, bSPtr ) < 0); - } - if ( uiA64 == uiB64 ) { - if ( uiA0 == uiB0 ) return false; - ltMags = (uiA0 < uiB0); - } else { - ltMags = (uiA64 < uiB64); - } - return signA ^ ltMags; - } - -} - -#endif - diff --git a/softfloat/source/extF80M_lt_quiet.c b/softfloat/source/extF80M_lt_quiet.c deleted file mode 100644 index 650586d..0000000 --- a/softfloat/source/extF80M_lt_quiet.c +++ /dev/null @@ -1,112 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool extF80M_lt_quiet( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - - return extF80_lt_quiet( *aPtr, *bPtr ); - -} - -#else - -bool extF80M_lt_quiet( const extFloat80_t *aPtr, const extFloat80_t *bPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - uint_fast16_t uiA64; - uint64_t uiA0; - uint_fast16_t uiB64; - uint64_t uiB0; - bool signA, ltMags; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - uiA0 = aSPtr->signif; - uiB64 = bSPtr->signExp; - uiB0 = bSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - if ( - softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) - || softfloat_isSigNaNExtF80UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signA = signExtF80UI64( uiA64 ); - if ( (uiA64 ^ uiB64) & 0x8000 ) { - /*-------------------------------------------------------------------- - | Signs are different. - *--------------------------------------------------------------------*/ - return signA && ((uiA0 | uiB0) != 0); - } else { - /*-------------------------------------------------------------------- - | Signs are the same. - *--------------------------------------------------------------------*/ - if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) { - return (softfloat_compareNonnormExtF80M( aSPtr, bSPtr ) < 0); - } - if ( uiA64 == uiB64 ) { - if ( uiA0 == uiB0 ) return false; - ltMags = (uiA0 < uiB0); - } else { - ltMags = (uiA64 < uiB64); - } - return signA ^ ltMags; - } - -} - -#endif - diff --git a/softfloat/source/extF80M_mul.c b/softfloat/source/extF80M_mul.c deleted file mode 100644 index 281394f..0000000 --- a/softfloat/source/extF80M_mul.c +++ /dev/null @@ -1,139 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - extF80M_mul( - const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr ) -{ - - *zPtr = extF80_mul( *aPtr, *bPtr ); - -} - -#else - -void - extF80M_mul( - const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - struct extFloat80M *zSPtr; - uint_fast16_t uiA64; - int32_t expA; - uint_fast16_t uiB64; - int32_t expB; - bool signZ; - uint_fast16_t exp, uiZ64; - uint64_t uiZ0, sigA, sigB; - int32_t expZ; - uint32_t sigProd[4], *extSigZPtr; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - zSPtr = (struct extFloat80M *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - expA = expExtF80UI64( uiA64 ); - uiB64 = bSPtr->signExp; - expB = expExtF80UI64( uiB64 ); - signZ = signExtF80UI64( uiA64 ) ^ signExtF80UI64( uiB64 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) { - if ( softfloat_tryPropagateNaNExtF80M( aSPtr, bSPtr, zSPtr ) ) return; - if ( - (! aSPtr->signif && (expA != 0x7FFF)) - || (! bSPtr->signif && (expB != 0x7FFF)) - ) { - softfloat_invalidExtF80M( zSPtr ); - return; - } - uiZ64 = packToExtF80UI64( signZ, 0x7FFF ); - uiZ0 = UINT64_C( 0x8000000000000000 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) expA = 1; - sigA = aSPtr->signif; - if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigA ) goto zero; - expA += softfloat_normExtF80SigM( &sigA ); - } - if ( ! expB ) expB = 1; - sigB = bSPtr->signif; - if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigB ) goto zero; - expB += softfloat_normExtF80SigM( &sigB ); - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA + expB - 0x3FFE; - softfloat_mul64To128M( sigA, sigB, sigProd ); - if ( sigProd[indexWordLo( 4 )] ) sigProd[indexWord( 4, 1 )] |= 1; - extSigZPtr = &sigProd[indexMultiwordHi( 4, 3 )]; - if ( sigProd[indexWordHi( 4 )] < 0x80000000 ) { - --expZ; - softfloat_add96M( extSigZPtr, extSigZPtr, extSigZPtr ); - } - softfloat_roundPackMToExtF80M( - signZ, expZ, extSigZPtr, extF80_roundingPrecision, zSPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ64 = packToExtF80UI64( signZ, 0 ); - uiZ0 = 0; - uiZ: - zSPtr->signExp = uiZ64; - zSPtr->signif = uiZ0; - -} - -#endif - diff --git a/softfloat/source/extF80M_rem.c b/softfloat/source/extF80M_rem.c deleted file mode 100644 index 4aff18a..0000000 --- a/softfloat/source/extF80M_rem.c +++ /dev/null @@ -1,204 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - extF80M_rem( - const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr ) -{ - - *zPtr = extF80_rem( *aPtr, *bPtr ); - -} - -#else - -void - extF80M_rem( - const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - struct extFloat80M *zSPtr; - uint_fast16_t uiA64; - int32_t expA, expB; - uint64_t x64; - bool signRem; - uint64_t sigA; - int32_t expDiff; - uint32_t rem[3], x[3], sig32B, q, recip32, rem2[3], *remPtr, *altRemPtr; - uint32_t *newRemPtr, wordMeanRem; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - zSPtr = (struct extFloat80M *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - expA = expExtF80UI64( uiA64 ); - expB = expExtF80UI64( bSPtr->signExp ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) { - if ( softfloat_tryPropagateNaNExtF80M( aSPtr, bSPtr, zSPtr ) ) return; - if ( expA == 0x7FFF ) goto invalid; - /*-------------------------------------------------------------------- - | If we get here, then argument b is an infinity and `expB' is 0x7FFF; - | Doubling `expB' is an easy way to ensure that `expDiff' later is - | less than -1, which will result in returning a canonicalized version - | of argument a. - *--------------------------------------------------------------------*/ - expB += expB; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) expB = 1; - x64 = bSPtr->signif; - if ( ! (x64 & UINT64_C( 0x8000000000000000 )) ) { - if ( ! x64 ) goto invalid; - expB += softfloat_normExtF80SigM( &x64 ); - } - signRem = signExtF80UI64( uiA64 ); - if ( ! expA ) expA = 1; - sigA = aSPtr->signif; - if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigA ) { - expA = 0; - goto copyA; - } - expA += softfloat_normExtF80SigM( &sigA ); - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( expDiff < -1 ) goto copyA; - rem[indexWord( 3, 2 )] = sigA>>34; - rem[indexWord( 3, 1 )] = sigA>>2; - rem[indexWord( 3, 0 )] = (uint32_t) sigA<<30; - x[indexWord( 3, 0 )] = (uint32_t) x64<<30; - sig32B = x64>>32; - x64 >>= 2; - x[indexWord( 3, 2 )] = x64>>32; - x[indexWord( 3, 1 )] = x64; - if ( expDiff < 1 ) { - if ( expDiff ) { - --expB; - softfloat_add96M( x, x, x ); - q = 0; - } else { - q = (softfloat_compare96M( x, rem ) <= 0); - if ( q ) softfloat_sub96M( rem, x, rem ); - } - } else { - recip32 = softfloat_approxRecip32_1( sig32B ); - expDiff -= 30; - for (;;) { - x64 = (uint64_t) rem[indexWordHi( 3 )] * recip32; - if ( expDiff < 0 ) break; - q = (x64 + 0x80000000)>>32; - softfloat_remStep96MBy32( rem, 29, x, q, rem ); - if ( rem[indexWordHi( 3 )] & 0x80000000 ) { - softfloat_add96M( rem, x, rem ); - } - expDiff -= 29; - } - /*-------------------------------------------------------------------- - | (`expDiff' cannot be less than -29 here.) - *--------------------------------------------------------------------*/ - q = (uint32_t) (x64>>32)>>(~expDiff & 31); - softfloat_remStep96MBy32( rem, expDiff + 30, x, q, rem ); - if ( rem[indexWordHi( 3 )] & 0x80000000 ) { - remPtr = rem; - altRemPtr = rem2; - softfloat_add96M( remPtr, x, altRemPtr ); - goto selectRem; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - remPtr = rem; - altRemPtr = rem2; - do { - ++q; - newRemPtr = altRemPtr; - softfloat_sub96M( remPtr, x, newRemPtr ); - altRemPtr = remPtr; - remPtr = newRemPtr; - } while ( ! (remPtr[indexWordHi( 3 )] & 0x80000000) ); - selectRem: - softfloat_add96M( remPtr, altRemPtr, x ); - wordMeanRem = x[indexWordHi( 3 )]; - if ( - (wordMeanRem & 0x80000000) - || (! wordMeanRem && (q & 1) && ! x[indexWord( 3, 0 )] - && ! x[indexWord( 3, 1 )]) - ) { - remPtr = altRemPtr; - } - if ( remPtr[indexWordHi( 3 )] & 0x80000000 ) { - signRem = ! signRem; - softfloat_negX96M( remPtr ); - } - softfloat_normRoundPackMToExtF80M( signRem, expB + 2, remPtr, 80, zSPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_invalidExtF80M( zSPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - copyA: - if ( expA < 1 ) { - sigA >>= 1 - expA; - expA = 0; - } - zSPtr->signExp = packToExtF80UI64( signRem, expA ); - zSPtr->signif = sigA; - -} - -#endif - diff --git a/softfloat/source/extF80M_roundToInt.c b/softfloat/source/extF80M_roundToInt.c deleted file mode 100644 index 2e85729..0000000 --- a/softfloat/source/extF80M_roundToInt.c +++ /dev/null @@ -1,176 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - extF80M_roundToInt( - const extFloat80_t *aPtr, - uint_fast8_t roundingMode, - bool exact, - extFloat80_t *zPtr - ) -{ - - *zPtr = extF80_roundToInt( *aPtr, roundingMode, exact ); - -} - -#else - -void - extF80M_roundToInt( - const extFloat80_t *aPtr, - uint_fast8_t roundingMode, - bool exact, - extFloat80_t *zPtr - ) -{ - const struct extFloat80M *aSPtr; - struct extFloat80M *zSPtr; - uint_fast16_t uiA64, signUI64; - int32_t exp; - uint64_t sigA; - uint_fast16_t uiZ64; - uint64_t sigZ, lastBitMask, roundBitsMask; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - zSPtr = (struct extFloat80M *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - signUI64 = uiA64 & packToExtF80UI64( 1, 0 ); - exp = expExtF80UI64( uiA64 ); - sigA = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( !(sigA & UINT64_C( 0x8000000000000000 )) && (exp != 0x7FFF) ) { - if ( !sigA ) { - uiZ64 = signUI64; - sigZ = 0; - goto uiZ; - } - exp += softfloat_normExtF80SigM( &sigA ); - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp <= 0x3FFE ) { - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - switch ( roundingMode ) { - case softfloat_round_near_even: - if ( !(sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) break; - case softfloat_round_near_maxMag: - if ( exp == 0x3FFE ) goto mag1; - break; - case softfloat_round_min: - if ( signUI64 ) goto mag1; - break; - case softfloat_round_max: - if ( !signUI64 ) goto mag1; - break; -#ifdef SOFTFLOAT_ROUND_ODD - case softfloat_round_odd: - goto mag1; -#endif - } - uiZ64 = signUI64; - sigZ = 0; - goto uiZ; - mag1: - uiZ64 = signUI64 | 0x3FFF; - sigZ = UINT64_C( 0x8000000000000000 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x403E <= exp ) { - if ( exp == 0x7FFF ) { - if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - softfloat_propagateNaNExtF80M( aSPtr, 0, zSPtr ); - return; - } - sigZ = UINT64_C( 0x8000000000000000 ); - } else { - sigZ = sigA; - } - uiZ64 = signUI64 | exp; - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ64 = signUI64 | exp; - lastBitMask = (uint64_t) 1<<(0x403E - exp); - roundBitsMask = lastBitMask - 1; - sigZ = sigA; - if ( roundingMode == softfloat_round_near_maxMag ) { - sigZ += lastBitMask>>1; - } else if ( roundingMode == softfloat_round_near_even ) { - sigZ += lastBitMask>>1; - if ( !(sigZ & roundBitsMask) ) sigZ &= ~lastBitMask; - } else if ( - roundingMode == (signUI64 ? softfloat_round_min : softfloat_round_max) - ) { - sigZ += roundBitsMask; - } - sigZ &= ~roundBitsMask; - if ( !sigZ ) { - ++uiZ64; - sigZ = UINT64_C( 0x8000000000000000 ); - } - if ( sigZ != sigA ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) sigZ |= lastBitMask; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - uiZ: - zSPtr->signExp = uiZ64; - zSPtr->signif = sigZ; - return; - -} - -#endif - diff --git a/softfloat/source/extF80M_sqrt.c b/softfloat/source/extF80M_sqrt.c deleted file mode 100644 index 7ee91e0..0000000 --- a/softfloat/source/extF80M_sqrt.c +++ /dev/null @@ -1,180 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void extF80M_sqrt( const extFloat80_t *aPtr, extFloat80_t *zPtr ) -{ - - *zPtr = extF80_sqrt( *aPtr ); - -} - -#else - -void extF80M_sqrt( const extFloat80_t *aPtr, extFloat80_t *zPtr ) -{ - const struct extFloat80M *aSPtr; - struct extFloat80M *zSPtr; - uint_fast16_t uiA64, signUI64; - int32_t expA; - uint64_t rem64; - int32_t expZ; - uint32_t rem96[3], sig32A, recipSqrt32, sig32Z, q; - uint64_t sig64Z, x64; - uint32_t rem32, term[4], rem[4], extSigZ[3]; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - zSPtr = (struct extFloat80M *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - signUI64 = uiA64 & packToExtF80UI64( 1, 0 ); - expA = expExtF80UI64( uiA64 ); - rem64 = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FFF ) { - if ( rem64 & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - softfloat_propagateNaNExtF80M( aSPtr, 0, zSPtr ); - return; - } - if ( signUI64 ) goto invalid; - rem64 = UINT64_C( 0x8000000000000000 ); - goto copyA; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) expA = 1; - if ( ! (rem64 & UINT64_C( 0x8000000000000000 )) ) { - if ( ! rem64 ) { - uiA64 = signUI64; - goto copyA; - } - expA += softfloat_normExtF80SigM( &rem64 ); - } - if ( signUI64 ) goto invalid; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = ((expA - 0x3FFF)>>1) + 0x3FFF; - expA &= 1; - softfloat_shortShiftLeft64To96M( rem64, 30 - expA, rem96 ); - sig32A = rem64>>32; - recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A ); - sig32Z = ((uint64_t) sig32A * recipSqrt32)>>32; - if ( expA ) sig32Z >>= 1; - rem64 = - ((uint64_t) rem96[indexWord( 3, 2 )]<<32 | rem96[indexWord( 3, 1 )]) - - (uint64_t) sig32Z * sig32Z; - rem96[indexWord( 3, 2 )] = rem64>>32; - rem96[indexWord( 3, 1 )] = rem64; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q = ((uint32_t) (rem64>>2) * (uint64_t) recipSqrt32)>>32; - sig64Z = ((uint64_t) sig32Z<<32) + ((uint64_t) q<<3); - term[indexWord( 3, 2 )] = 0; - /*------------------------------------------------------------------------ - | (Repeating this loop is a rare occurrence.) - *------------------------------------------------------------------------*/ - for (;;) { - x64 = ((uint64_t) sig32Z<<32) + sig64Z; - term[indexWord( 3, 1 )] = x64>>32; - term[indexWord( 3, 0 )] = x64; - softfloat_remStep96MBy32( - rem96, 29, term, q, &rem[indexMultiwordHi( 4, 3 )] ); - rem32 = rem[indexWord( 4, 3 )]; - if ( ! (rem32 & 0x80000000) ) break; - --q; - sig64Z -= 1<<3; - } - rem64 = (uint64_t) rem32<<32 | rem[indexWord( 4, 2 )]; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q = (((uint32_t) (rem64>>2) * (uint64_t) recipSqrt32)>>32) + 2; - if ( rem64>>34 ) q += recipSqrt32; - x64 = (uint64_t) q<<7; - extSigZ[indexWord( 3, 0 )] = x64; - x64 = (sig64Z<<1) + (x64>>32); - extSigZ[indexWord( 3, 2 )] = x64>>32; - extSigZ[indexWord( 3, 1 )] = x64; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (q & 0xFFFFFF) <= 2 ) { - q &= ~(uint32_t) 0xFFFF; - extSigZ[indexWordLo( 3 )] = q<<7; - x64 = sig64Z + (q>>27); - term[indexWord( 4, 3 )] = 0; - term[indexWord( 4, 2 )] = x64>>32; - term[indexWord( 4, 1 )] = x64; - term[indexWord( 4, 0 )] = q<<5; - rem[indexWord( 4, 0 )] = 0; - softfloat_remStep128MBy32( rem, 28, term, q, rem ); - q = rem[indexWordHi( 4 )]; - if ( q & 0x80000000 ) { - softfloat_sub1X96M( extSigZ ); - } else { - if ( q || rem[indexWord( 4, 1 )] || rem[indexWord( 4, 2 )] ) { - extSigZ[indexWordLo( 3 )] |= 1; - } - } - } - softfloat_roundPackMToExtF80M( - 0, expZ, extSigZ, extF80_roundingPrecision, zSPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_invalidExtF80M( zSPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - copyA: - zSPtr->signExp = uiA64; - zSPtr->signif = rem64; - -} - -#endif - diff --git a/softfloat/source/extF80M_sub.c b/softfloat/source/extF80M_sub.c deleted file mode 100644 index 5d1895c..0000000 --- a/softfloat/source/extF80M_sub.c +++ /dev/null @@ -1,100 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - extF80M_sub( - const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr ) -{ - const struct extFloat80M *aSPtr, *bSPtr; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool signA; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - bool signB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) - extFloat80_t - (*magsFuncPtr)( - uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool ); -#endif - - aSPtr = (const struct extFloat80M *) aPtr; - bSPtr = (const struct extFloat80M *) bPtr; - uiA64 = aSPtr->signExp; - uiA0 = aSPtr->signif; - signA = signExtF80UI64( uiA64 ); - uiB64 = bSPtr->signExp; - uiB0 = bSPtr->signif; - signB = signExtF80UI64( uiB64 ); -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) - if ( signA == signB ) { - *zPtr = softfloat_subMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA ); - } else { - *zPtr = softfloat_addMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA ); - } -#else - magsFuncPtr = - (signA == signB) ? softfloat_subMagsExtF80 : softfloat_addMagsExtF80; - *zPtr = (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA ); -#endif - -} - -#else - -void - extF80M_sub( - const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr ) -{ - - softfloat_addExtF80M( - (const struct extFloat80M *) aPtr, - (const struct extFloat80M *) bPtr, - (struct extFloat80M *) zPtr, - true - ); - -} - -#endif - diff --git a/softfloat/source/extF80M_to_f128M.c b/softfloat/source/extF80M_to_f128M.c deleted file mode 100644 index da81e8d..0000000 --- a/softfloat/source/extF80M_to_f128M.c +++ /dev/null @@ -1,125 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void extF80M_to_f128M( const extFloat80_t *aPtr, float128_t *zPtr ) -{ - - *zPtr = extF80_to_f128( *aPtr ); - -} - -#else - -void extF80M_to_f128M( const extFloat80_t *aPtr, float128_t *zPtr ) -{ - const struct extFloat80M *aSPtr; - uint32_t *zWPtr; - uint_fast16_t uiA64; - bool sign; - int32_t exp; - uint64_t sig; - struct commonNaN commonNaN; - uint32_t uiZ96; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - zWPtr = (uint32_t *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zWPtr[indexWord( 4, 0 )] = 0; - if ( exp == 0x7FFF ) { - if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - softfloat_extF80MToCommonNaN( aSPtr, &commonNaN ); - softfloat_commonNaNToF128M( &commonNaN, zWPtr ); - return; - } - uiZ96 = packToF128UI96( sign, 0x7FFF, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) --exp; - if ( ! (sig & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sig ) { - uiZ96 = packToF128UI96( sign, 0, 0 ); - goto uiZ; - } - exp += softfloat_normExtF80SigM( &sig ); - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zWPtr[indexWord( 4, 1 )] = (uint32_t) sig<<17; - sig >>= 15; - zWPtr[indexWord( 4, 2 )] = sig; - if ( exp < 0 ) { - zWPtr[indexWordHi( 4 )] = sig>>32; - softfloat_shiftRight96M( - &zWPtr[indexMultiwordHi( 4, 3 )], - -exp, - &zWPtr[indexMultiwordHi( 4, 3 )] - ); - exp = 0; - sig = (uint64_t) zWPtr[indexWordHi( 4 )]<<32; - } - zWPtr[indexWordHi( 4 )] = packToF128UI96( sign, exp, sig>>32 ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - zWPtr[indexWord( 4, 3 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = 0; - zWPtr[indexWord( 4, 1 )] = 0; - -} - -#endif - diff --git a/softfloat/source/extF80M_to_f16.c b/softfloat/source/extF80M_to_f16.c deleted file mode 100644 index 5ae38d0..0000000 --- a/softfloat/source/extF80M_to_f16.c +++ /dev/null @@ -1,112 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -float16_t extF80M_to_f16( const extFloat80_t *aPtr ) -{ - - return extF80_to_f16( *aPtr ); - -} - -#else - -float16_t extF80M_to_f16( const extFloat80_t *aPtr ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - bool sign; - int32_t exp; - uint64_t sig; - struct commonNaN commonNaN; - uint16_t uiZ, sig16; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - softfloat_extF80MToCommonNaN( aSPtr, &commonNaN ); - uiZ = softfloat_commonNaNToF16UI( &commonNaN ); - } else { - uiZ = packToF16UI( sign, 0x1F, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! (sig & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sig ) { - uiZ = packToF16UI( sign, 0, 0 ); - goto uiZ; - } - exp += softfloat_normExtF80SigM( &sig ); - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig16 = softfloat_shortShiftRightJam64( sig, 49 ); - exp -= 0x3FF1; - if ( sizeof (int_fast16_t) < sizeof (int32_t) ) { - if ( exp < -0x40 ) exp = -0x40; - } - return softfloat_roundPackToF16( sign, exp, sig16 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - -#endif - diff --git a/softfloat/source/extF80M_to_f32.c b/softfloat/source/extF80M_to_f32.c deleted file mode 100644 index 47cf224..0000000 --- a/softfloat/source/extF80M_to_f32.c +++ /dev/null @@ -1,112 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -float32_t extF80M_to_f32( const extFloat80_t *aPtr ) -{ - - return extF80_to_f32( *aPtr ); - -} - -#else - -float32_t extF80M_to_f32( const extFloat80_t *aPtr ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - bool sign; - int32_t exp; - uint64_t sig; - struct commonNaN commonNaN; - uint32_t uiZ, sig32; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - softfloat_extF80MToCommonNaN( aSPtr, &commonNaN ); - uiZ = softfloat_commonNaNToF32UI( &commonNaN ); - } else { - uiZ = packToF32UI( sign, 0xFF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! (sig & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sig ) { - uiZ = packToF32UI( sign, 0, 0 ); - goto uiZ; - } - exp += softfloat_normExtF80SigM( &sig ); - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig32 = softfloat_shortShiftRightJam64( sig, 33 ); - exp -= 0x3F81; - if ( sizeof (int_fast16_t) < sizeof (int32_t) ) { - if ( exp < -0x1000 ) exp = -0x1000; - } - return softfloat_roundPackToF32( sign, exp, sig32 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - -#endif - diff --git a/softfloat/source/extF80M_to_f64.c b/softfloat/source/extF80M_to_f64.c deleted file mode 100644 index 5f8f4aa..0000000 --- a/softfloat/source/extF80M_to_f64.c +++ /dev/null @@ -1,112 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -float64_t extF80M_to_f64( const extFloat80_t *aPtr ) -{ - - return extF80_to_f64( *aPtr ); - -} - -#else - -float64_t extF80M_to_f64( const extFloat80_t *aPtr ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - bool sign; - int32_t exp; - uint64_t sig; - struct commonNaN commonNaN; - uint64_t uiZ; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - softfloat_extF80MToCommonNaN( aSPtr, &commonNaN ); - uiZ = softfloat_commonNaNToF64UI( &commonNaN ); - } else { - uiZ = packToF64UI( sign, 0x7FF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! (sig & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sig ) { - uiZ = packToF64UI( sign, 0, 0 ); - goto uiZ; - } - exp += softfloat_normExtF80SigM( &sig ); - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig = softfloat_shortShiftRightJam64( sig, 1 ); - exp -= 0x3C01; - if ( sizeof (int_fast16_t) < sizeof (int32_t) ) { - if ( exp < -0x1000 ) exp = -0x1000; - } - return softfloat_roundPackToF64( sign, exp, sig ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - -#endif - diff --git a/softfloat/source/extF80M_to_i32.c b/softfloat/source/extF80M_to_i32.c deleted file mode 100644 index 06394e3..0000000 --- a/softfloat/source/extF80M_to_i32.c +++ /dev/null @@ -1,100 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -int_fast32_t - extF80M_to_i32( - const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - - return extF80_to_i32( *aPtr, roundingMode, exact ); - -} - -#else - -int_fast32_t - extF80M_to_i32( - const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - bool sign; - int32_t exp; - uint64_t sig; - int32_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - uiA64 = aSPtr->signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x4032 - exp; - if ( shiftDist <= 0 ) { - if ( sig>>32 ) goto invalid; - if ( -32 < shiftDist ) { - sig <<= -shiftDist; - } else { - if ( (uint32_t) sig ) goto invalid; - } - } else { - sig = softfloat_shiftRightJam64( sig, shiftDist ); - } - return softfloat_roundToI32( sign, sig, roundingMode, exact ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ? i32_fromNaN - : sign ? i32_fromNegOverflow : i32_fromPosOverflow; - -} - -#endif - diff --git a/softfloat/source/extF80M_to_i32_r_minMag.c b/softfloat/source/extF80M_to_i32_r_minMag.c deleted file mode 100644 index 5f5cf59..0000000 --- a/softfloat/source/extF80M_to_i32_r_minMag.c +++ /dev/null @@ -1,120 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -int_fast32_t extF80M_to_i32_r_minMag( const extFloat80_t *aPtr, bool exact ) -{ - - return extF80_to_i32_r_minMag( *aPtr, exact ); - -} - -#else - -int_fast32_t extF80M_to_i32_r_minMag( const extFloat80_t *aPtr, bool exact ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - int32_t exp; - uint64_t sig; - int32_t shiftDist; - bool sign, raiseInexact; - int32_t z; - uint64_t shiftedSig; - uint32_t absZ; - union { uint32_t ui; int32_t i; } u; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - uiA64 = aSPtr->signExp; - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! sig && (exp != 0x7FFF) ) return 0; - shiftDist = 0x403E - exp; - if ( 64 <= shiftDist ) { - raiseInexact = exact; - z = 0; - } else { - sign = signExtF80UI64( uiA64 ); - raiseInexact = false; - if ( shiftDist < 0 ) { - if ( sig>>32 || (shiftDist <= -31) ) goto invalid; - shiftedSig = (uint64_t) (uint32_t) sig<<-shiftDist; - if ( shiftedSig>>32 ) goto invalid; - absZ = shiftedSig; - } else { - shiftedSig = sig; - if ( shiftDist ) shiftedSig >>= shiftDist; - if ( shiftedSig>>32 ) goto invalid; - absZ = shiftedSig; - if ( exact && shiftDist ) { - raiseInexact = ((uint64_t) absZ< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -int_fast64_t - extF80M_to_i64( - const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - - return extF80_to_i64( *aPtr, roundingMode, exact ); - -} - -#else - -int_fast64_t - extF80M_to_i64( - const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - bool sign; - int32_t exp; - uint64_t sig; - int32_t shiftDist; - uint32_t extSig[3]; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - uiA64 = aSPtr->signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x403E - exp; - if ( shiftDist < 0 ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - extSig[indexWord( 3, 2 )] = sig>>32; - extSig[indexWord( 3, 1 )] = sig; - extSig[indexWord( 3, 0 )] = 0; - if ( shiftDist ) softfloat_shiftRightJam96M( extSig, shiftDist, extSig ); - return softfloat_roundMToI64( sign, extSig, roundingMode, exact ); - -} - -#endif - diff --git a/softfloat/source/extF80M_to_i64_r_minMag.c b/softfloat/source/extF80M_to_i64_r_minMag.c deleted file mode 100644 index ec9b928..0000000 --- a/softfloat/source/extF80M_to_i64_r_minMag.c +++ /dev/null @@ -1,115 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -int_fast64_t extF80M_to_i64_r_minMag( const extFloat80_t *aPtr, bool exact ) -{ - - return extF80_to_i64_r_minMag( *aPtr, exact ); - -} - -#else - -int_fast64_t extF80M_to_i64_r_minMag( const extFloat80_t *aPtr, bool exact ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - int32_t exp; - uint64_t sig; - int32_t shiftDist; - bool sign, raiseInexact; - int64_t z; - uint64_t absZ; - union { uint64_t ui; int64_t i; } u; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - uiA64 = aSPtr->signExp; - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! sig && (exp != 0x7FFF) ) return 0; - shiftDist = 0x403E - exp; - if ( 64 <= shiftDist ) { - raiseInexact = exact; - z = 0; - } else { - sign = signExtF80UI64( uiA64 ); - raiseInexact = false; - if ( shiftDist < 0 ) { - if ( shiftDist <= -63 ) goto invalid; - shiftDist = -shiftDist; - absZ = sig<>shiftDist != sig ) goto invalid; - } else { - absZ = sig; - if ( shiftDist ) absZ >>= shiftDist; - if ( exact && shiftDist ) raiseInexact = (absZ< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -uint_fast32_t - extF80M_to_ui32( - const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - - return extF80_to_ui32( *aPtr, roundingMode, exact ); - -} - -#else - -uint_fast32_t - extF80M_to_ui32( - const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - bool sign; - int32_t exp; - uint64_t sig; - int32_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - uiA64 = aSPtr->signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x4032 - exp; - if ( shiftDist <= 0 ) { - if ( sig>>32 ) goto invalid; - if ( -32 < shiftDist ) { - sig <<= -shiftDist; - } else { - if ( (uint32_t) sig ) goto invalid; - } - } else { - sig = softfloat_shiftRightJam64( sig, shiftDist ); - } - return softfloat_roundToUI32( sign, sig, roundingMode, exact ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - ? ui32_fromNaN - : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; - -} - -#endif - diff --git a/softfloat/source/extF80M_to_ui32_r_minMag.c b/softfloat/source/extF80M_to_ui32_r_minMag.c deleted file mode 100644 index e28b08d..0000000 --- a/softfloat/source/extF80M_to_ui32_r_minMag.c +++ /dev/null @@ -1,111 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -uint_fast32_t extF80M_to_ui32_r_minMag( const extFloat80_t *aPtr, bool exact ) -{ - - return extF80_to_ui32_r_minMag( *aPtr, exact ); - -} - -#else - -uint_fast32_t extF80M_to_ui32_r_minMag( const extFloat80_t *aPtr, bool exact ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - int32_t exp; - uint64_t sig; - int32_t shiftDist; - bool sign; - uint64_t shiftedSig; - uint32_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - uiA64 = aSPtr->signExp; - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! sig && (exp != 0x7FFF) ) return 0; - shiftDist = 0x403E - exp; - if ( 64 <= shiftDist ) { - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signExtF80UI64( uiA64 ); - if ( shiftDist < 0 ) { - if ( sign || sig>>32 || (shiftDist <= -31) ) goto invalid; - shiftedSig = (uint64_t) (uint32_t) sig<<-shiftDist; - if ( shiftedSig>>32 ) goto invalid; - z = shiftedSig; - } else { - shiftedSig = sig; - if ( shiftDist ) shiftedSig >>= shiftDist; - if ( shiftedSig>>32 ) goto invalid; - z = shiftedSig; - if ( sign && z ) goto invalid; - if ( exact && shiftDist && ((uint64_t) z< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -uint_fast64_t - extF80M_to_ui64( - const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - - return extF80_to_ui64( *aPtr, roundingMode, exact ); - -} - -#else - -uint_fast64_t - extF80M_to_ui64( - const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - bool sign; - int32_t exp; - uint64_t sig; - int32_t shiftDist; - uint32_t extSig[3]; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - uiA64 = aSPtr->signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x403E - exp; - if ( shiftDist < 0 ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - extSig[indexWord( 3, 2 )] = sig>>32; - extSig[indexWord( 3, 1 )] = sig; - extSig[indexWord( 3, 0 )] = 0; - if ( shiftDist ) softfloat_shiftRightJam96M( extSig, shiftDist, extSig ); - return softfloat_roundMToUI64( sign, extSig, roundingMode, exact ); - -} - -#endif - diff --git a/softfloat/source/extF80M_to_ui64_r_minMag.c b/softfloat/source/extF80M_to_ui64_r_minMag.c deleted file mode 100644 index 87d8089..0000000 --- a/softfloat/source/extF80M_to_ui64_r_minMag.c +++ /dev/null @@ -1,108 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -uint_fast64_t extF80M_to_ui64_r_minMag( const extFloat80_t *aPtr, bool exact ) -{ - - return extF80_to_ui64_r_minMag( *aPtr, exact ); - -} - -#else - -uint_fast64_t extF80M_to_ui64_r_minMag( const extFloat80_t *aPtr, bool exact ) -{ - const struct extFloat80M *aSPtr; - uint_fast16_t uiA64; - int32_t exp; - uint64_t sig; - int32_t shiftDist; - bool sign; - uint64_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aSPtr = (const struct extFloat80M *) aPtr; - uiA64 = aSPtr->signExp; - exp = expExtF80UI64( uiA64 ); - sig = aSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! sig && (exp != 0x7FFF) ) return 0; - shiftDist = 0x403E - exp; - if ( 64 <= shiftDist ) { - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signExtF80UI64( uiA64 ); - if ( shiftDist < 0 ) { - if ( sign || (shiftDist <= -63) ) goto invalid; - shiftDist = -shiftDist; - z = sig<>shiftDist != sig ) goto invalid; - } else { - z = sig; - if ( shiftDist ) z >>= shiftDist; - if ( sign && z ) goto invalid; - if ( exact && shiftDist && (z< -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool signA; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - bool signB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) - extFloat80_t - (*magsFuncPtr)( - uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool ); -#endif - - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - signA = signExtF80UI64( uiA64 ); - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - signB = signExtF80UI64( uiB64 ); -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) - if ( signA == signB ) { - return softfloat_addMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA ); - } else { - return softfloat_subMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA ); - } -#else - magsFuncPtr = - (signA == signB) ? softfloat_addMagsExtF80 : softfloat_subMagsExtF80; - return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA ); -#endif - -} - diff --git a/softfloat/source/extF80_div.c b/softfloat/source/extF80_div.c deleted file mode 100644 index 28dfb13..0000000 --- a/softfloat/source/extF80_div.c +++ /dev/null @@ -1,203 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool signA; - int_fast32_t expA; - uint_fast64_t sigA; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - bool signB; - int_fast32_t expB; - uint_fast64_t sigB; - bool signZ; - struct exp32_sig64 normExpSig; - int_fast32_t expZ; - struct uint128 rem; - uint_fast32_t recip32; - uint_fast64_t sigZ; - int ix; - uint_fast64_t q64; - uint_fast32_t q; - struct uint128 term; - uint_fast64_t sigZExtra; - struct uint128 uiZ; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - signA = signExtF80UI64( uiA64 ); - expA = expExtF80UI64( uiA64 ); - sigA = uiA0; - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - signB = signExtF80UI64( uiB64 ); - expB = expExtF80UI64( uiB64 ); - sigB = uiB0; - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FFF ) { - if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN; - if ( expB == 0x7FFF ) { - if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN; - goto invalid; - } - goto infinity; - } - if ( expB == 0x7FFF ) { - if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN; - goto zero; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) expB = 1; - if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigB ) { - if ( ! sigA ) goto invalid; - softfloat_raiseFlags( softfloat_flag_infinite ); - goto infinity; - } - normExpSig = softfloat_normSubnormalExtF80Sig( sigB ); - expB += normExpSig.exp; - sigB = normExpSig.sig; - } - if ( ! expA ) expA = 1; - if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigA ) goto zero; - normExpSig = softfloat_normSubnormalExtF80Sig( sigA ); - expA += normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA - expB + 0x3FFF; - if ( sigA < sigB ) { - --expZ; - rem = softfloat_shortShiftLeft128( 0, sigA, 32 ); - } else { - rem = softfloat_shortShiftLeft128( 0, sigA, 31 ); - } - recip32 = softfloat_approxRecip32_1( sigB>>32 ); - sigZ = 0; - ix = 2; - for (;;) { - q64 = (uint_fast64_t) (uint32_t) (rem.v64>>2) * recip32; - q = (q64 + 0x80000000)>>32; - --ix; - if ( ix < 0 ) break; - rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); - term = softfloat_mul64ByShifted32To128( sigB, q ); - rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - --q; - rem = softfloat_add128( rem.v64, rem.v0, sigB>>32, sigB<<32 ); - } - sigZ = (sigZ<<29) + q; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ((q + 1) & 0x3FFFFF) < 2 ) { - rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); - term = softfloat_mul64ByShifted32To128( sigB, q ); - rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); - term = softfloat_shortShiftLeft128( 0, sigB, 32 ); - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - --q; - rem = softfloat_add128( rem.v64, rem.v0, term.v64, term.v0 ); - } else if ( softfloat_le128( term.v64, term.v0, rem.v64, rem.v0 ) ) { - ++q; - rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); - } - if ( rem.v64 | rem.v0 ) q |= 1; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sigZ = (sigZ<<6) + (q>>23); - sigZExtra = (uint64_t) ((uint_fast64_t) q<<41); - return - softfloat_roundPackToExtF80( - signZ, expZ, sigZ, sigZExtra, extF80_roundingPrecision ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 ); - uiZ64 = uiZ.v64; - uiZ0 = uiZ.v0; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ64 = defaultNaNExtF80UI64; - uiZ0 = defaultNaNExtF80UI0; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infinity: - uiZ64 = packToExtF80UI64( signZ, 0x7FFF ); - uiZ0 = UINT64_C( 0x8000000000000000 ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ64 = packToExtF80UI64( signZ, 0 ); - uiZ0 = 0; - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/extF80_eq.c b/softfloat/source/extF80_eq.c deleted file mode 100644 index efcbc37..0000000 --- a/softfloat/source/extF80_eq.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool extF80_eq( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - if ( - softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) - || softfloat_isSigNaNExtF80UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - return - (uiA0 == uiB0) - && ((uiA64 == uiB64) || (! uiA0 && ! ((uiA64 | uiB64) & 0x7FFF))); - -} - diff --git a/softfloat/source/extF80_eq_signaling.c b/softfloat/source/extF80_eq_signaling.c deleted file mode 100644 index 193b191..0000000 --- a/softfloat/source/extF80_eq_signaling.c +++ /dev/null @@ -1,67 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool extF80_eq_signaling( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - return - (uiA0 == uiB0) - && ((uiA64 == uiB64) || (! uiA0 && ! ((uiA64 | uiB64) & 0x7FFF))); - -} - diff --git a/softfloat/source/extF80_isSignalingNaN.c b/softfloat/source/extF80_isSignalingNaN.c deleted file mode 100644 index 33d2abd..0000000 --- a/softfloat/source/extF80_isSignalingNaN.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool extF80_isSignalingNaN( extFloat80_t a ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - - uA.f = a; - return softfloat_isSigNaNExtF80UI( uA.s.signExp, uA.s.signif ); - -} - diff --git a/softfloat/source/extF80_le.c b/softfloat/source/extF80_le.c deleted file mode 100644 index 4e23c51..0000000 --- a/softfloat/source/extF80_le.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool extF80_le( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - bool signA, signB; - - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - signA = signExtF80UI64( uiA64 ); - signB = signExtF80UI64( uiB64 ); - return - (signA != signB) - ? signA || ! (((uiA64 | uiB64) & 0x7FFF) | uiA0 | uiB0) - : ((uiA64 == uiB64) && (uiA0 == uiB0)) - || (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); - -} - diff --git a/softfloat/source/extF80_le_quiet.c b/softfloat/source/extF80_le_quiet.c deleted file mode 100644 index 9839e47..0000000 --- a/softfloat/source/extF80_le_quiet.c +++ /dev/null @@ -1,78 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool extF80_le_quiet( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - bool signA, signB; - - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - if ( - softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) - || softfloat_isSigNaNExtF80UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - signA = signExtF80UI64( uiA64 ); - signB = signExtF80UI64( uiB64 ); - return - (signA != signB) - ? signA || ! (((uiA64 | uiB64) & 0x7FFF) | uiA0 | uiB0) - : ((uiA64 == uiB64) && (uiA0 == uiB0)) - || (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); - -} - diff --git a/softfloat/source/extF80_lt.c b/softfloat/source/extF80_lt.c deleted file mode 100644 index a4ac69f..0000000 --- a/softfloat/source/extF80_lt.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool extF80_lt( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - bool signA, signB; - - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - signA = signExtF80UI64( uiA64 ); - signB = signExtF80UI64( uiB64 ); - return - (signA != signB) - ? signA && (((uiA64 | uiB64) & 0x7FFF) | uiA0 | uiB0) - : ((uiA64 != uiB64) || (uiA0 != uiB0)) - && (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); - -} - diff --git a/softfloat/source/extF80_lt_quiet.c b/softfloat/source/extF80_lt_quiet.c deleted file mode 100644 index 00f4d47..0000000 --- a/softfloat/source/extF80_lt_quiet.c +++ /dev/null @@ -1,78 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool extF80_lt_quiet( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - bool signA, signB; - - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) { - if ( - softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) - || softfloat_isSigNaNExtF80UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - signA = signExtF80UI64( uiA64 ); - signB = signExtF80UI64( uiB64 ); - return - (signA != signB) - ? signA && (((uiA64 | uiB64) & 0x7FFF) | uiA0 | uiB0) - : ((uiA64 != uiB64) || (uiA0 != uiB0)) - && (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); - -} - diff --git a/softfloat/source/extF80_mul.c b/softfloat/source/extF80_mul.c deleted file mode 100644 index 39ce401..0000000 --- a/softfloat/source/extF80_mul.c +++ /dev/null @@ -1,158 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool signA; - int_fast32_t expA; - uint_fast64_t sigA; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - bool signB; - int_fast32_t expB; - uint_fast64_t sigB; - bool signZ; - uint_fast64_t magBits; - struct exp32_sig64 normExpSig; - int_fast32_t expZ; - struct uint128 sig128Z, uiZ; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - signA = signExtF80UI64( uiA64 ); - expA = expExtF80UI64( uiA64 ); - sigA = uiA0; - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - signB = signExtF80UI64( uiB64 ); - expB = expExtF80UI64( uiB64 ); - sigB = uiB0; - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FFF ) { - if ( - (sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - || ((expB == 0x7FFF) && (sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ))) - ) { - goto propagateNaN; - } - magBits = expB | sigB; - goto infArg; - } - if ( expB == 0x7FFF ) { - if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN; - magBits = expA | sigA; - goto infArg; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) expA = 1; - if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigA ) goto zero; - normExpSig = softfloat_normSubnormalExtF80Sig( sigA ); - expA += normExpSig.exp; - sigA = normExpSig.sig; - } - if ( ! expB ) expB = 1; - if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigB ) goto zero; - normExpSig = softfloat_normSubnormalExtF80Sig( sigB ); - expB += normExpSig.exp; - sigB = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA + expB - 0x3FFE; - sig128Z = softfloat_mul64To128( sigA, sigB ); - if ( sig128Z.v64 < UINT64_C( 0x8000000000000000 ) ) { - --expZ; - sig128Z = - softfloat_add128( - sig128Z.v64, sig128Z.v0, sig128Z.v64, sig128Z.v0 ); - } - return - softfloat_roundPackToExtF80( - signZ, expZ, sig128Z.v64, sig128Z.v0, extF80_roundingPrecision ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 ); - uiZ64 = uiZ.v64; - uiZ0 = uiZ.v0; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infArg: - if ( ! magBits ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ64 = defaultNaNExtF80UI64; - uiZ0 = defaultNaNExtF80UI0; - } else { - uiZ64 = packToExtF80UI64( signZ, 0x7FFF ); - uiZ0 = UINT64_C( 0x8000000000000000 ); - } - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ64 = packToExtF80UI64( signZ, 0 ); - uiZ0 = 0; - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/extF80_rem.c b/softfloat/source/extF80_rem.c deleted file mode 100644 index 5ad9775..0000000 --- a/softfloat/source/extF80_rem.c +++ /dev/null @@ -1,225 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t extF80_rem( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool signA; - int_fast32_t expA; - uint_fast64_t sigA; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - int_fast32_t expB; - uint_fast64_t sigB; - struct exp32_sig64 normExpSig; - int_fast32_t expDiff; - struct uint128 rem, shiftedSigB; - uint_fast32_t q, recip32; - uint_fast64_t q64; - struct uint128 term, altRem, meanRem; - bool signRem; - struct uint128 uiZ; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - signA = signExtF80UI64( uiA64 ); - expA = expExtF80UI64( uiA64 ); - sigA = uiA0; - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - expB = expExtF80UI64( uiB64 ); - sigB = uiB0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FFF ) { - if ( - (sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - || ((expB == 0x7FFF) && (sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ))) - ) { - goto propagateNaN; - } - goto invalid; - } - if ( expB == 0x7FFF ) { - if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN; - /*-------------------------------------------------------------------- - | Argument b is an infinity. Doubling `expB' is an easy way to ensure - | that `expDiff' later is less than -1, which will result in returning - | a canonicalized version of argument a. - *--------------------------------------------------------------------*/ - expB += expB; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) expB = 1; - if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigB ) goto invalid; - normExpSig = softfloat_normSubnormalExtF80Sig( sigB ); - expB += normExpSig.exp; - sigB = normExpSig.sig; - } - if ( ! expA ) expA = 1; - if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigA ) { - expA = 0; - goto copyA; - } - normExpSig = softfloat_normSubnormalExtF80Sig( sigA ); - expA += normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( expDiff < -1 ) goto copyA; - rem = softfloat_shortShiftLeft128( 0, sigA, 32 ); - shiftedSigB = softfloat_shortShiftLeft128( 0, sigB, 32 ); - if ( expDiff < 1 ) { - if ( expDiff ) { - --expB; - shiftedSigB = softfloat_shortShiftLeft128( 0, sigB, 33 ); - q = 0; - } else { - q = (sigB <= sigA); - if ( q ) { - rem = - softfloat_sub128( - rem.v64, rem.v0, shiftedSigB.v64, shiftedSigB.v0 ); - } - } - } else { - recip32 = softfloat_approxRecip32_1( sigB>>32 ); - expDiff -= 30; - for (;;) { - q64 = (uint_fast64_t) (uint32_t) (rem.v64>>2) * recip32; - if ( expDiff < 0 ) break; - q = (q64 + 0x80000000)>>32; - rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); - term = softfloat_mul64ByShifted32To128( sigB, q ); - rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - rem = - softfloat_add128( - rem.v64, rem.v0, shiftedSigB.v64, shiftedSigB.v0 ); - } - expDiff -= 29; - } - /*-------------------------------------------------------------------- - | (`expDiff' cannot be less than -29 here.) - *--------------------------------------------------------------------*/ - q = (uint32_t) (q64>>32)>>(~expDiff & 31); - rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, expDiff + 30 ); - term = softfloat_mul64ByShifted32To128( sigB, q ); - rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - altRem = - softfloat_add128( - rem.v64, rem.v0, shiftedSigB.v64, shiftedSigB.v0 ); - goto selectRem; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - do { - altRem = rem; - ++q; - rem = - softfloat_sub128( - rem.v64, rem.v0, shiftedSigB.v64, shiftedSigB.v0 ); - } while ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ); - selectRem: - meanRem = softfloat_add128( rem.v64, rem.v0, altRem.v64, altRem.v0 ); - if ( - (meanRem.v64 & UINT64_C( 0x8000000000000000 )) - || (! (meanRem.v64 | meanRem.v0) && (q & 1)) - ) { - rem = altRem; - } - signRem = signA; - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - signRem = ! signRem; - rem = softfloat_sub128( 0, 0, rem.v64, rem.v0 ); - } - return - softfloat_normRoundPackToExtF80( - signRem, rem.v64 | rem.v0 ? expB + 32 : 0, rem.v64, rem.v0, 80 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 ); - uiZ64 = uiZ.v64; - uiZ0 = uiZ.v0; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ64 = defaultNaNExtF80UI64; - uiZ0 = defaultNaNExtF80UI0; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - copyA: - if ( expA < 1 ) { - sigA >>= 1 - expA; - expA = 0; - } - uiZ64 = packToExtF80UI64( signA, expA ); - uiZ0 = sigA; - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/extF80_roundToInt.c b/softfloat/source/extF80_roundToInt.c deleted file mode 100644 index 6c12d84..0000000 --- a/softfloat/source/extF80_roundToInt.c +++ /dev/null @@ -1,154 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t - extF80_roundToInt( extFloat80_t a, uint_fast8_t roundingMode, bool exact ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64, signUI64; - int_fast32_t exp; - uint_fast64_t sigA; - uint_fast16_t uiZ64; - uint_fast64_t sigZ; - struct exp32_sig64 normExpSig; - struct uint128 uiZ; - uint_fast64_t lastBitMask, roundBitsMask; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - signUI64 = uiA64 & packToExtF80UI64( 1, 0 ); - exp = expExtF80UI64( uiA64 ); - sigA = uA.s.signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( !(sigA & UINT64_C( 0x8000000000000000 )) && (exp != 0x7FFF) ) { - if ( !sigA ) { - uiZ64 = signUI64; - sigZ = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalExtF80Sig( sigA ); - exp += normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x403E <= exp ) { - if ( exp == 0x7FFF ) { - if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - uiZ = softfloat_propagateNaNExtF80UI( uiA64, sigA, 0, 0 ); - uiZ64 = uiZ.v64; - sigZ = uiZ.v0; - goto uiZ; - } - sigZ = UINT64_C( 0x8000000000000000 ); - } else { - sigZ = sigA; - } - uiZ64 = signUI64 | exp; - goto uiZ; - } - if ( exp <= 0x3FFE ) { - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - switch ( roundingMode ) { - case softfloat_round_near_even: - if ( !(sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) break; - case softfloat_round_near_maxMag: - if ( exp == 0x3FFE ) goto mag1; - break; - case softfloat_round_min: - if ( signUI64 ) goto mag1; - break; - case softfloat_round_max: - if ( !signUI64 ) goto mag1; - break; -#ifdef SOFTFLOAT_ROUND_ODD - case softfloat_round_odd: - goto mag1; -#endif - } - uiZ64 = signUI64; - sigZ = 0; - goto uiZ; - mag1: - uiZ64 = signUI64 | 0x3FFF; - sigZ = UINT64_C( 0x8000000000000000 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ64 = signUI64 | exp; - lastBitMask = (uint_fast64_t) 1<<(0x403E - exp); - roundBitsMask = lastBitMask - 1; - sigZ = sigA; - if ( roundingMode == softfloat_round_near_maxMag ) { - sigZ += lastBitMask>>1; - } else if ( roundingMode == softfloat_round_near_even ) { - sigZ += lastBitMask>>1; - if ( !(sigZ & roundBitsMask) ) sigZ &= ~lastBitMask; - } else if ( - roundingMode == (signUI64 ? softfloat_round_min : softfloat_round_max) - ) { - sigZ += roundBitsMask; - } - sigZ &= ~roundBitsMask; - if ( !sigZ ) { - ++uiZ64; - sigZ = UINT64_C( 0x8000000000000000 ); - } - if ( sigZ != sigA ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) sigZ |= lastBitMask; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = sigZ; - return uZ.f; - -} - diff --git a/softfloat/source/extF80_sqrt.c b/softfloat/source/extF80_sqrt.c deleted file mode 100644 index af8c496..0000000 --- a/softfloat/source/extF80_sqrt.c +++ /dev/null @@ -1,176 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t extF80_sqrt( extFloat80_t a ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool signA; - int_fast32_t expA; - uint_fast64_t sigA; - struct uint128 uiZ; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0; - struct exp32_sig64 normExpSig; - int_fast32_t expZ; - uint_fast32_t sig32A, recipSqrt32, sig32Z; - struct uint128 rem; - uint_fast64_t q, x64, sigZ; - struct uint128 y, term; - uint_fast64_t sigZExtra; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - signA = signExtF80UI64( uiA64 ); - expA = expExtF80UI64( uiA64 ); - sigA = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FFF ) { - if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, 0, 0 ); - uiZ64 = uiZ.v64; - uiZ0 = uiZ.v0; - goto uiZ; - } - if ( ! signA ) return a; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( signA ) { - if ( ! sigA ) goto zero; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) expA = 1; - if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) { - if ( ! sigA ) goto zero; - normExpSig = softfloat_normSubnormalExtF80Sig( sigA ); - expA += normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - | (`sig32Z' is guaranteed to be a lower bound on the square root of - | `sig32A', which makes `sig32Z' also a lower bound on the square root of - | `sigA'.) - *------------------------------------------------------------------------*/ - expZ = ((expA - 0x3FFF)>>1) + 0x3FFF; - expA &= 1; - sig32A = sigA>>32; - recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A ); - sig32Z = ((uint_fast64_t) sig32A * recipSqrt32)>>32; - if ( expA ) { - sig32Z >>= 1; - rem = softfloat_shortShiftLeft128( 0, sigA, 61 ); - } else { - rem = softfloat_shortShiftLeft128( 0, sigA, 62 ); - } - rem.v64 -= (uint_fast64_t) sig32Z * sig32Z; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q = ((uint32_t) (rem.v64>>2) * (uint_fast64_t) recipSqrt32)>>32; - x64 = (uint_fast64_t) sig32Z<<32; - sigZ = x64 + (q<<3); - y = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); - /*------------------------------------------------------------------------ - | (Repeating this loop is a rare occurrence.) - *------------------------------------------------------------------------*/ - for (;;) { - term = softfloat_mul64ByShifted32To128( x64 + sigZ, q ); - rem = softfloat_sub128( y.v64, y.v0, term.v64, term.v0 ); - if ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ) break; - --q; - sigZ -= 1<<3; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q = (((rem.v64>>2) * recipSqrt32)>>32) + 2; - x64 = sigZ; - sigZ = (sigZ<<1) + (q>>25); - sigZExtra = (uint64_t) (q<<39); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (q & 0xFFFFFF) <= 2 ) { - q &= ~(uint_fast64_t) 0xFFFF; - sigZExtra = (uint64_t) (q<<39); - term = softfloat_mul64ByShifted32To128( x64 + (q>>27), q ); - x64 = (uint32_t) (q<<5) * (uint_fast64_t) (uint32_t) q; - term = softfloat_add128( term.v64, term.v0, 0, x64 ); - rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 28 ); - rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - if ( ! sigZExtra ) --sigZ; - --sigZExtra; - } else { - if ( rem.v64 | rem.v0 ) sigZExtra |= 1; - } - } - return - softfloat_roundPackToExtF80( - 0, expZ, sigZ, sigZExtra, extF80_roundingPrecision ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ64 = defaultNaNExtF80UI64; - uiZ0 = defaultNaNExtF80UI0; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ64 = packToExtF80UI64( signA, 0 ); - uiZ0 = 0; - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/extF80_sub.c b/softfloat/source/extF80_sub.c deleted file mode 100644 index 770c756..0000000 --- a/softfloat/source/extF80_sub.c +++ /dev/null @@ -1,80 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool signA; - union { struct extFloat80M s; extFloat80_t f; } uB; - uint_fast16_t uiB64; - uint_fast64_t uiB0; - bool signB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) - extFloat80_t - (*magsFuncPtr)( - uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool ); -#endif - - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - signA = signExtF80UI64( uiA64 ); - uB.f = b; - uiB64 = uB.s.signExp; - uiB0 = uB.s.signif; - signB = signExtF80UI64( uiB64 ); -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) - if ( signA == signB ) { - return softfloat_subMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA ); - } else { - return softfloat_addMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA ); - } -#else - magsFuncPtr = - (signA == signB) ? softfloat_subMagsExtF80 : softfloat_addMagsExtF80; - return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA ); -#endif - -} - diff --git a/softfloat/source/extF80_to_f128.c b/softfloat/source/extF80_to_f128.c deleted file mode 100644 index 4de90ae..0000000 --- a/softfloat/source/extF80_to_f128.c +++ /dev/null @@ -1,75 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t extF80_to_f128( extFloat80_t a ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - uint_fast16_t exp; - uint_fast64_t frac; - struct commonNaN commonNaN; - struct uint128 uiZ; - bool sign; - struct uint128 frac128; - union ui128_f128 uZ; - - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - exp = expExtF80UI64( uiA64 ); - frac = uiA0 & UINT64_C( 0x7FFFFFFFFFFFFFFF ); - if ( (exp == 0x7FFF) && frac ) { - softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN ); - uiZ = softfloat_commonNaNToF128UI( &commonNaN ); - } else { - sign = signExtF80UI64( uiA64 ); - frac128 = softfloat_shortShiftLeft128( 0, frac, 49 ); - uiZ.v64 = packToF128UI64( sign, exp, frac128.v64 ); - uiZ.v0 = frac128.v0; - } - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/extF80_to_f16.c b/softfloat/source/extF80_to_f16.c deleted file mode 100644 index 5919403..0000000 --- a/softfloat/source/extF80_to_f16.c +++ /dev/null @@ -1,96 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float16_t extF80_to_f16( extFloat80_t a ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t sig; - struct commonNaN commonNaN; - uint_fast16_t uiZ, sig16; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN ); - uiZ = softfloat_commonNaNToF16UI( &commonNaN ); - } else { - uiZ = packToF16UI( sign, 0x1F, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig16 = softfloat_shortShiftRightJam64( sig, 49 ); - if ( ! (exp | sig16) ) { - uiZ = packToF16UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - exp -= 0x3FF1; - if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) { - if ( exp < -0x40 ) exp = -0x40; - } - return softfloat_roundPackToF16( sign, exp, sig16 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/extF80_to_f32.c b/softfloat/source/extF80_to_f32.c deleted file mode 100644 index 77fcfdc..0000000 --- a/softfloat/source/extF80_to_f32.c +++ /dev/null @@ -1,96 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t extF80_to_f32( extFloat80_t a ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t sig; - struct commonNaN commonNaN; - uint_fast32_t uiZ, sig32; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN ); - uiZ = softfloat_commonNaNToF32UI( &commonNaN ); - } else { - uiZ = packToF32UI( sign, 0xFF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig32 = softfloat_shortShiftRightJam64( sig, 33 ); - if ( ! (exp | sig32) ) { - uiZ = packToF32UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - exp -= 0x3F81; - if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) { - if ( exp < -0x1000 ) exp = -0x1000; - } - return softfloat_roundPackToF32( sign, exp, sig32 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/extF80_to_f64.c b/softfloat/source/extF80_to_f64.c deleted file mode 100644 index 410d662..0000000 --- a/softfloat/source/extF80_to_f64.c +++ /dev/null @@ -1,96 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float64_t extF80_to_f64( extFloat80_t a ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - uint_fast64_t uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t sig; - struct commonNaN commonNaN; - uint_fast64_t uiZ; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - uiA0 = uA.s.signif; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! (exp | sig) ) { - uiZ = packToF64UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN ); - uiZ = softfloat_commonNaNToF64UI( &commonNaN ); - } else { - uiZ = packToF64UI( sign, 0x7FF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig = softfloat_shortShiftRightJam64( sig, 1 ); - exp -= 0x3C01; - if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) { - if ( exp < -0x1000 ) exp = -0x1000; - } - return softfloat_roundPackToF64( sign, exp, sig ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/extF80_to_i32.c b/softfloat/source/extF80_to_i32.c deleted file mode 100644 index 9acdc3c..0000000 --- a/softfloat/source/extF80_to_i32.c +++ /dev/null @@ -1,83 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t - extF80_to_i32( extFloat80_t a, uint_fast8_t roundingMode, bool exact ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - bool sign; - int_fast32_t exp; - uint_fast64_t sig; - int_fast32_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = uA.s.signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ -#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow) - if ( (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) { -#if (i32_fromNaN == i32_fromPosOverflow) - sign = 0; -#elif (i32_fromNaN == i32_fromNegOverflow) - sign = 1; -#else - softfloat_raiseFlags( softfloat_flag_invalid ); - return i32_fromNaN; -#endif - } -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x4032 - exp; - if ( shiftDist <= 0 ) shiftDist = 1; - sig = softfloat_shiftRightJam64( sig, shiftDist ); - return softfloat_roundToI32( sign, sig, roundingMode, exact ); - -} - diff --git a/softfloat/source/extF80_to_i32_r_minMag.c b/softfloat/source/extF80_to_i32_r_minMag.c deleted file mode 100644 index 0322467..0000000 --- a/softfloat/source/extF80_to_i32_r_minMag.c +++ /dev/null @@ -1,97 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t extF80_to_i32_r_minMag( extFloat80_t a, bool exact ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - int_fast32_t exp; - uint_fast64_t sig; - int_fast32_t shiftDist; - bool sign; - int_fast32_t absZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - exp = expExtF80UI64( uiA64 ); - sig = uA.s.signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x403E - exp; - if ( 64 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signExtF80UI64( uiA64 ); - if ( shiftDist < 33 ) { - if ( - (uiA64 == packToExtF80UI64( 1, 0x401E )) - && (sig < UINT64_C( 0x8000000100000000 )) - ) { - if ( exact && (sig & UINT64_C( 0x00000000FFFFFFFF )) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return -0x7FFFFFFF - 1; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - ? i32_fromNaN - : sign ? i32_fromNegOverflow : i32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - absZ = sig>>shiftDist; - if ( exact && ((uint_fast64_t) (uint_fast32_t) absZ< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t - extF80_to_i64( extFloat80_t a, uint_fast8_t roundingMode, bool exact ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - bool sign; - int_fast32_t exp; - uint_fast64_t sig; - int_fast32_t shiftDist; - uint_fast64_t sigExtra; - struct uint64_extra sig64Extra; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = uA.s.signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x403E - exp; - if ( shiftDist <= 0 ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( shiftDist ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sigExtra = 0; - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sig64Extra = softfloat_shiftRightJam64Extra( sig, 0, shiftDist ); - sig = sig64Extra.v; - sigExtra = sig64Extra.extra; - } - return softfloat_roundToI64( sign, sig, sigExtra, roundingMode, exact ); - -} - diff --git a/softfloat/source/extF80_to_i64_r_minMag.c b/softfloat/source/extF80_to_i64_r_minMag.c deleted file mode 100644 index 8871d01..0000000 --- a/softfloat/source/extF80_to_i64_r_minMag.c +++ /dev/null @@ -1,94 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t extF80_to_i64_r_minMag( extFloat80_t a, bool exact ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - int_fast32_t exp; - uint_fast64_t sig; - int_fast32_t shiftDist; - bool sign; - int_fast64_t absZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - exp = expExtF80UI64( uiA64 ); - sig = uA.s.signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x403E - exp; - if ( 64 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signExtF80UI64( uiA64 ); - if ( shiftDist <= 0 ) { - if ( - (uiA64 == packToExtF80UI64( 1, 0x403E )) - && (sig == UINT64_C( 0x8000000000000000 )) - ) { - return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - absZ = sig>>shiftDist; - if ( exact && (uint64_t) (sig<<(-shiftDist & 63)) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return sign ? -absZ : absZ; - -} - diff --git a/softfloat/source/extF80_to_ui32.c b/softfloat/source/extF80_to_ui32.c deleted file mode 100644 index 5812977..0000000 --- a/softfloat/source/extF80_to_ui32.c +++ /dev/null @@ -1,83 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t - extF80_to_ui32( extFloat80_t a, uint_fast8_t roundingMode, bool exact ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - bool sign; - int_fast32_t exp; - uint_fast64_t sig; - int_fast32_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = uA.s.signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ -#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow) - if ( (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) { -#if (ui32_fromNaN == ui32_fromPosOverflow) - sign = 0; -#elif (ui32_fromNaN == ui32_fromNegOverflow) - sign = 1; -#else - softfloat_raiseFlags( softfloat_flag_invalid ); - return ui32_fromNaN; -#endif - } -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x4032 - exp; - if ( shiftDist <= 0 ) shiftDist = 1; - sig = softfloat_shiftRightJam64( sig, shiftDist ); - return softfloat_roundToUI32( sign, sig, roundingMode, exact ); - -} - diff --git a/softfloat/source/extF80_to_ui32_r_minMag.c b/softfloat/source/extF80_to_ui32_r_minMag.c deleted file mode 100644 index be2c53b..0000000 --- a/softfloat/source/extF80_to_ui32_r_minMag.c +++ /dev/null @@ -1,88 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t extF80_to_ui32_r_minMag( extFloat80_t a, bool exact ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - int_fast32_t exp; - uint_fast64_t sig; - int_fast32_t shiftDist; - bool sign; - uint_fast32_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - exp = expExtF80UI64( uiA64 ); - sig = uA.s.signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x403E - exp; - if ( 64 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signExtF80UI64( uiA64 ); - if ( sign || (shiftDist < 32) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - ? ui32_fromNaN - : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - z = sig>>shiftDist; - if ( exact && ((uint_fast64_t) z< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t - extF80_to_ui64( extFloat80_t a, uint_fast8_t roundingMode, bool exact ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - bool sign; - int_fast32_t exp; - uint_fast64_t sig; - int_fast32_t shiftDist; - uint_fast64_t sigExtra; - struct uint64_extra sig64Extra; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - sign = signExtF80UI64( uiA64 ); - exp = expExtF80UI64( uiA64 ); - sig = uA.s.signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x403E - exp; - if ( shiftDist < 0 ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sigExtra = 0; - if ( shiftDist ) { - sig64Extra = softfloat_shiftRightJam64Extra( sig, 0, shiftDist ); - sig = sig64Extra.v; - sigExtra = sig64Extra.extra; - } - return softfloat_roundToUI64( sign, sig, sigExtra, roundingMode, exact ); - -} - diff --git a/softfloat/source/extF80_to_ui64_r_minMag.c b/softfloat/source/extF80_to_ui64_r_minMag.c deleted file mode 100644 index eca688c..0000000 --- a/softfloat/source/extF80_to_ui64_r_minMag.c +++ /dev/null @@ -1,88 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t extF80_to_ui64_r_minMag( extFloat80_t a, bool exact ) -{ - union { struct extFloat80M s; extFloat80_t f; } uA; - uint_fast16_t uiA64; - int_fast32_t exp; - uint_fast64_t sig; - int_fast32_t shiftDist; - bool sign; - uint_fast64_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.s.signExp; - exp = expExtF80UI64( uiA64 ); - sig = uA.s.signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x403E - exp; - if ( 64 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signExtF80UI64( uiA64 ); - if ( sign || (shiftDist < 0) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - z = sig>>shiftDist; - if ( exact && (z< -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - f128M_add( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr ) -{ - const uint64_t *aWPtr, *bWPtr; - uint_fast64_t uiA64, uiA0; - bool signA; - uint_fast64_t uiB64, uiB0; - bool signB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) - float128_t - (*magsFuncPtr)( - uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool ); -#endif - - aWPtr = (const uint64_t *) aPtr; - bWPtr = (const uint64_t *) bPtr; - uiA64 = aWPtr[indexWord( 2, 1 )]; - uiA0 = aWPtr[indexWord( 2, 0 )]; - signA = signF128UI64( uiA64 ); - uiB64 = bWPtr[indexWord( 2, 1 )]; - uiB0 = bWPtr[indexWord( 2, 0 )]; - signB = signF128UI64( uiB64 ); -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) - if ( signA == signB ) { - *zPtr = softfloat_addMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); - } else { - *zPtr = softfloat_subMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); - } -#else - magsFuncPtr = - (signA == signB) ? softfloat_addMagsF128 : softfloat_subMagsF128; - *zPtr = (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA ); -#endif - -} - -#else - -void - f128M_add( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr ) -{ - - softfloat_addF128M( - (const uint32_t *) aPtr, - (const uint32_t *) bPtr, - (uint32_t *) zPtr, - false - ); - -} - -#endif - diff --git a/softfloat/source/f128M_div.c b/softfloat/source/f128M_div.c deleted file mode 100644 index b443548..0000000 --- a/softfloat/source/f128M_div.c +++ /dev/null @@ -1,187 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - f128M_div( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr ) -{ - - *zPtr = f128_div( *aPtr, *bPtr ); - -} - -#else - -void - f128M_div( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr ) -{ - const uint32_t *aWPtr, *bWPtr; - uint32_t *zWPtr, uiA96; - bool signA; - int32_t expA; - uint32_t uiB96; - bool signB; - int32_t expB; - bool signZ; - uint32_t y[5], sigB[4]; - int32_t expZ; - uint32_t recip32; - int ix; - uint64_t q64; - uint32_t q, qs[3], uiZ96; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - bWPtr = (const uint32_t *) bPtr; - zWPtr = (uint32_t *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA96 = aWPtr[indexWordHi( 4 )]; - signA = signF128UI96( uiA96 ); - expA = expF128UI96( uiA96 ); - uiB96 = bWPtr[indexWordHi( 4 )]; - signB = signF128UI96( uiB96 ); - expB = expF128UI96( uiB96 ); - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) { - if ( softfloat_tryPropagateNaNF128M( aWPtr, bWPtr, zWPtr ) ) return; - if ( expA == 0x7FFF ) { - if ( expB == 0x7FFF ) goto invalid; - goto infinity; - } - goto zero; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = softfloat_shiftNormSigF128M( aWPtr, 13, y ); - expB = softfloat_shiftNormSigF128M( bWPtr, 13, sigB ); - if ( expA == -128 ) { - if ( expB == -128 ) goto invalid; - goto zero; - } - if ( expB == -128 ) { - softfloat_raiseFlags( softfloat_flag_infinite ); - goto infinity; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA - expB + 0x3FFE; - if ( softfloat_compare128M( y, sigB ) < 0 ) { - --expZ; - softfloat_add128M( y, y, y ); - } - recip32 = - softfloat_approxRecip32_1( - ((uint64_t) sigB[indexWord( 4, 3 )]<<32 | sigB[indexWord( 4, 2 )]) - >>30 - ); - ix = 3; - for (;;) { - q64 = (uint64_t) y[indexWordHi( 4 )] * recip32; - q = (q64 + 0x80000000)>>32; - --ix; - if ( ix < 0 ) break; - softfloat_remStep128MBy32( y, 29, sigB, q, y ); - if ( y[indexWordHi( 4 )] & 0x80000000 ) { - --q; - softfloat_add128M( y, sigB, y ); - } - qs[ix] = q; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ((q + 1) & 7) < 2 ) { - softfloat_remStep128MBy32( y, 29, sigB, q, y ); - if ( y[indexWordHi( 4 )] & 0x80000000 ) { - --q; - softfloat_add128M( y, sigB, y ); - } else if ( softfloat_compare128M( sigB, y ) <= 0 ) { - ++q; - softfloat_sub128M( y, sigB, y ); - } - if ( - y[indexWordLo( 4 )] || y[indexWord( 4, 1 )] - || (y[indexWord( 4, 2 )] | y[indexWord( 4, 3 )]) - ) { - q |= 1; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q64 = (uint64_t) q<<28; - y[indexWord( 5, 0 )] = q64; - q64 = ((uint64_t) qs[0]<<25) + (q64>>32); - y[indexWord( 5, 1 )] = q64; - q64 = ((uint64_t) qs[1]<<22) + (q64>>32); - y[indexWord( 5, 2 )] = q64; - q64 = ((uint64_t) qs[2]<<19) + (q64>>32); - y[indexWord( 5, 3 )] = q64; - y[indexWord( 5, 4 )] = q64>>32; - softfloat_roundPackMToF128M( signZ, expZ, y, zWPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_invalidF128M( zWPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infinity: - uiZ96 = packToF128UI96( signZ, 0x7FFF, 0 ); - goto uiZ96; - zero: - uiZ96 = packToF128UI96( signZ, 0, 0 ); - uiZ96: - zWPtr[indexWordHi( 4 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = 0; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - -} - -#endif - diff --git a/softfloat/source/f128M_eq.c b/softfloat/source/f128M_eq.c deleted file mode 100644 index 497fdbf..0000000 --- a/softfloat/source/f128M_eq.c +++ /dev/null @@ -1,100 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool f128M_eq( const float128_t *aPtr, const float128_t *bPtr ) -{ - - return f128_eq( *aPtr, *bPtr ); - -} - -#else - -bool f128M_eq( const float128_t *aPtr, const float128_t *bPtr ) -{ - const uint32_t *aWPtr, *bWPtr; - uint32_t wordA, wordB, uiA96, uiB96; - bool possibleOppositeZeros; - uint32_t mashWord; - - aWPtr = (const uint32_t *) aPtr; - bWPtr = (const uint32_t *) bPtr; - wordA = aWPtr[indexWord( 4, 2 )]; - wordB = bWPtr[indexWord( 4, 2 )]; - if ( wordA != wordB ) goto false_checkSigNaNs; - uiA96 = aWPtr[indexWordHi( 4 )]; - uiB96 = bWPtr[indexWordHi( 4 )]; - possibleOppositeZeros = false; - if ( uiA96 != uiB96 ) { - possibleOppositeZeros = (((uiA96 | uiB96) & 0x7FFFFFFF) == 0); - if ( ! possibleOppositeZeros ) goto false_checkSigNaNs; - } - mashWord = wordA | wordB; - wordA = aWPtr[indexWord( 4, 1 )]; - wordB = bWPtr[indexWord( 4, 1 )]; - if ( wordA != wordB ) goto false_checkSigNaNs; - mashWord |= wordA | wordB; - wordA = aWPtr[indexWord( 4, 0 )]; - wordB = bWPtr[indexWord( 4, 0 )]; - if ( wordA != wordB ) goto false_checkSigNaNs; - if ( possibleOppositeZeros && ((mashWord | wordA | wordB) != 0) ) { - goto false_checkSigNaNs; - } - if ( ! softfloat_isNaNF128M( aWPtr ) && ! softfloat_isNaNF128M( bWPtr ) ) { - return true; - } - false_checkSigNaNs: - if ( - f128M_isSignalingNaN( (const float128_t *) aWPtr ) - || f128M_isSignalingNaN( (const float128_t *) bWPtr ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - -} - -#endif - diff --git a/softfloat/source/f128M_eq_signaling.c b/softfloat/source/f128M_eq_signaling.c deleted file mode 100644 index a9fa4d5..0000000 --- a/softfloat/source/f128M_eq_signaling.c +++ /dev/null @@ -1,92 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool f128M_eq_signaling( const float128_t *aPtr, const float128_t *bPtr ) -{ - - return f128_eq_signaling( *aPtr, *bPtr ); - -} - -#else - -bool f128M_eq_signaling( const float128_t *aPtr, const float128_t *bPtr ) -{ - const uint32_t *aWPtr, *bWPtr; - uint32_t wordA, wordB, uiA96, uiB96; - bool possibleOppositeZeros; - uint32_t mashWord; - - aWPtr = (const uint32_t *) aPtr; - bWPtr = (const uint32_t *) bPtr; - if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - wordA = aWPtr[indexWord( 4, 2 )]; - wordB = bWPtr[indexWord( 4, 2 )]; - if ( wordA != wordB ) return false; - uiA96 = aWPtr[indexWordHi( 4 )]; - uiB96 = bWPtr[indexWordHi( 4 )]; - possibleOppositeZeros = false; - if ( uiA96 != uiB96 ) { - possibleOppositeZeros = (((uiA96 | uiB96) & 0x7FFFFFFF) == 0); - if ( ! possibleOppositeZeros ) return false; - } - mashWord = wordA | wordB; - wordA = aWPtr[indexWord( 4, 1 )]; - wordB = bWPtr[indexWord( 4, 1 )]; - if ( wordA != wordB ) return false; - mashWord |= wordA | wordB; - wordA = aWPtr[indexWord( 4, 0 )]; - wordB = bWPtr[indexWord( 4, 0 )]; - return - (wordA == wordB) - && (! possibleOppositeZeros || ((mashWord | wordA | wordB) == 0)); - -} - -#endif - diff --git a/softfloat/source/f128M_le.c b/softfloat/source/f128M_le.c deleted file mode 100644 index 7306e45..0000000 --- a/softfloat/source/f128M_le.c +++ /dev/null @@ -1,93 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool f128M_le( const float128_t *aPtr, const float128_t *bPtr ) -{ - - return f128_le( *aPtr, *bPtr ); - -} - -#else - -bool f128M_le( const float128_t *aPtr, const float128_t *bPtr ) -{ - const uint32_t *aWPtr, *bWPtr; - uint32_t uiA96, uiB96; - bool signA, signB; - uint32_t wordA, wordB; - - aWPtr = (const uint32_t *) aPtr; - bWPtr = (const uint32_t *) bPtr; - if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - uiA96 = aWPtr[indexWordHi( 4 )]; - uiB96 = bWPtr[indexWordHi( 4 )]; - signA = signF128UI96( uiA96 ); - signB = signF128UI96( uiB96 ); - if ( signA != signB ) { - if ( signA ) return true; - if ( (uiA96 | uiB96) & 0x7FFFFFFF ) return false; - wordA = aWPtr[indexWord( 4, 2 )]; - wordB = bWPtr[indexWord( 4, 2 )]; - if ( wordA | wordB ) return false; - wordA = aWPtr[indexWord( 4, 1 )]; - wordB = bWPtr[indexWord( 4, 1 )]; - if ( wordA | wordB ) return false; - wordA = aWPtr[indexWord( 4, 0 )]; - wordB = bWPtr[indexWord( 4, 0 )]; - return ((wordA | wordB) == 0); - } - if ( signA ) { - aWPtr = (const uint32_t *) bPtr; - bWPtr = (const uint32_t *) aPtr; - } - return (softfloat_compare128M( aWPtr, bWPtr ) <= 0); - -} - -#endif - diff --git a/softfloat/source/f128M_le_quiet.c b/softfloat/source/f128M_le_quiet.c deleted file mode 100644 index d9e4429..0000000 --- a/softfloat/source/f128M_le_quiet.c +++ /dev/null @@ -1,96 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool f128M_le_quiet( const float128_t *aPtr, const float128_t *bPtr ) -{ - - return f128_le_quiet( *aPtr, *bPtr ); - -} - -#else - -bool f128M_le_quiet( const float128_t *aPtr, const float128_t *bPtr ) -{ - const uint32_t *aWPtr, *bWPtr; - uint32_t uiA96, uiB96; - bool signA, signB; - uint32_t wordA, wordB; - - aWPtr = (const uint32_t *) aPtr; - bWPtr = (const uint32_t *) bPtr; - if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) { - if ( f128M_isSignalingNaN( aPtr ) || f128M_isSignalingNaN( bPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - uiA96 = aWPtr[indexWordHi( 4 )]; - uiB96 = bWPtr[indexWordHi( 4 )]; - signA = signF128UI96( uiA96 ); - signB = signF128UI96( uiB96 ); - if ( signA != signB ) { - if ( signA ) return true; - if ( (uiA96 | uiB96) & 0x7FFFFFFF ) return false; - wordA = aWPtr[indexWord( 4, 2 )]; - wordB = bWPtr[indexWord( 4, 2 )]; - if ( wordA | wordB ) return false; - wordA = aWPtr[indexWord( 4, 1 )]; - wordB = bWPtr[indexWord( 4, 1 )]; - if ( wordA | wordB ) return false; - wordA = aWPtr[indexWord( 4, 0 )]; - wordB = bWPtr[indexWord( 4, 0 )]; - return ((wordA | wordB) == 0); - } - if ( signA ) { - aWPtr = (const uint32_t *) bPtr; - bWPtr = (const uint32_t *) aPtr; - } - return (softfloat_compare128M( aWPtr, bWPtr ) <= 0); - -} - -#endif - diff --git a/softfloat/source/f128M_lt.c b/softfloat/source/f128M_lt.c deleted file mode 100644 index d2f797f..0000000 --- a/softfloat/source/f128M_lt.c +++ /dev/null @@ -1,93 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool f128M_lt( const float128_t *aPtr, const float128_t *bPtr ) -{ - - return f128_lt( *aPtr, *bPtr ); - -} - -#else - -bool f128M_lt( const float128_t *aPtr, const float128_t *bPtr ) -{ - const uint32_t *aWPtr, *bWPtr; - uint32_t uiA96, uiB96; - bool signA, signB; - uint32_t wordA, wordB; - - aWPtr = (const uint32_t *) aPtr; - bWPtr = (const uint32_t *) bPtr; - if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - uiA96 = aWPtr[indexWordHi( 4 )]; - uiB96 = bWPtr[indexWordHi( 4 )]; - signA = signF128UI96( uiA96 ); - signB = signF128UI96( uiB96 ); - if ( signA != signB ) { - if ( signB ) return false; - if ( (uiA96 | uiB96) & 0x7FFFFFFF ) return true; - wordA = aWPtr[indexWord( 4, 2 )]; - wordB = bWPtr[indexWord( 4, 2 )]; - if ( wordA | wordB ) return true; - wordA = aWPtr[indexWord( 4, 1 )]; - wordB = bWPtr[indexWord( 4, 1 )]; - if ( wordA | wordB ) return true; - wordA = aWPtr[indexWord( 4, 0 )]; - wordB = bWPtr[indexWord( 4, 0 )]; - return ((wordA | wordB) != 0); - } - if ( signA ) { - aWPtr = (const uint32_t *) bPtr; - bWPtr = (const uint32_t *) aPtr; - } - return (softfloat_compare128M( aWPtr, bWPtr ) < 0); - -} - -#endif - diff --git a/softfloat/source/f128M_lt_quiet.c b/softfloat/source/f128M_lt_quiet.c deleted file mode 100644 index adbddea..0000000 --- a/softfloat/source/f128M_lt_quiet.c +++ /dev/null @@ -1,96 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -bool f128M_lt_quiet( const float128_t *aPtr, const float128_t *bPtr ) -{ - - return f128_lt_quiet( *aPtr, *bPtr ); - -} - -#else - -bool f128M_lt_quiet( const float128_t *aPtr, const float128_t *bPtr ) -{ - const uint32_t *aWPtr, *bWPtr; - uint32_t uiA96, uiB96; - bool signA, signB; - uint32_t wordA, wordB; - - aWPtr = (const uint32_t *) aPtr; - bWPtr = (const uint32_t *) bPtr; - if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) { - if ( f128M_isSignalingNaN( aPtr ) || f128M_isSignalingNaN( bPtr ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - uiA96 = aWPtr[indexWordHi( 4 )]; - uiB96 = bWPtr[indexWordHi( 4 )]; - signA = signF128UI96( uiA96 ); - signB = signF128UI96( uiB96 ); - if ( signA != signB ) { - if ( signB ) return false; - if ( (uiA96 | uiB96) & 0x7FFFFFFF ) return true; - wordA = aWPtr[indexWord( 4, 2 )]; - wordB = bWPtr[indexWord( 4, 2 )]; - if ( wordA | wordB ) return true; - wordA = aWPtr[indexWord( 4, 1 )]; - wordB = bWPtr[indexWord( 4, 1 )]; - if ( wordA | wordB ) return true; - wordA = aWPtr[indexWord( 4, 0 )]; - wordB = bWPtr[indexWord( 4, 0 )]; - return ((wordA | wordB) != 0); - } - if ( signA ) { - aWPtr = (const uint32_t *) bPtr; - bWPtr = (const uint32_t *) aPtr; - } - return (softfloat_compare128M( aWPtr, bWPtr ) < 0); - -} - -#endif - diff --git a/softfloat/source/f128M_mul.c b/softfloat/source/f128M_mul.c deleted file mode 100644 index 4b8292a..0000000 --- a/softfloat/source/f128M_mul.c +++ /dev/null @@ -1,158 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - f128M_mul( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr ) -{ - - *zPtr = f128_mul( *aPtr, *bPtr ); - -} - -#else - -void - f128M_mul( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr ) -{ - const uint32_t *aWPtr, *bWPtr; - uint32_t *zWPtr; - uint32_t uiA96; - int32_t expA; - uint32_t uiB96; - int32_t expB; - bool signZ; - const uint32_t *ptr; - uint32_t uiZ96, sigA[4]; - uint_fast8_t shiftDist; - uint32_t sigB[4]; - int32_t expZ; - uint32_t sigProd[8], *extSigZPtr; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - bWPtr = (const uint32_t *) bPtr; - zWPtr = (uint32_t *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA96 = aWPtr[indexWordHi( 4 )]; - expA = expF128UI96( uiA96 ); - uiB96 = bWPtr[indexWordHi( 4 )]; - expB = expF128UI96( uiB96 ); - signZ = signF128UI96( uiA96 ) ^ signF128UI96( uiB96 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) { - if ( softfloat_tryPropagateNaNF128M( aWPtr, bWPtr, zWPtr ) ) return; - ptr = aWPtr; - if ( ! expA ) goto possiblyInvalid; - if ( ! expB ) { - ptr = bWPtr; - possiblyInvalid: - if ( - ! fracF128UI96( ptr[indexWordHi( 4 )] ) - && ! (ptr[indexWord( 4, 2 )] | ptr[indexWord( 4, 1 )] - | ptr[indexWord( 4, 0 )]) - ) { - softfloat_invalidF128M( zWPtr ); - return; - } - } - uiZ96 = packToF128UI96( signZ, 0x7FFF, 0 ); - goto uiZ96; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA ) { - sigA[indexWordHi( 4 )] = fracF128UI96( uiA96 ) | 0x00010000; - sigA[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )]; - sigA[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )]; - sigA[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )]; - } else { - expA = softfloat_shiftNormSigF128M( aWPtr, 0, sigA ); - if ( expA == -128 ) goto zero; - } - if ( expB ) { - sigB[indexWordHi( 4 )] = fracF128UI96( uiB96 ) | 0x00010000; - sigB[indexWord( 4, 2 )] = bWPtr[indexWord( 4, 2 )]; - sigB[indexWord( 4, 1 )] = bWPtr[indexWord( 4, 1 )]; - sigB[indexWord( 4, 0 )] = bWPtr[indexWord( 4, 0 )]; - } else { - expB = softfloat_shiftNormSigF128M( bWPtr, 0, sigB ); - if ( expB == -128 ) goto zero; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA + expB - 0x4000; - softfloat_mul128MTo256M( sigA, sigB, sigProd ); - if ( - sigProd[indexWord( 8, 2 )] - || (sigProd[indexWord( 8, 1 )] | sigProd[indexWord( 8, 0 )]) - ) { - sigProd[indexWord( 8, 3 )] |= 1; - } - extSigZPtr = &sigProd[indexMultiwordHi( 8, 5 )]; - shiftDist = 16; - if ( extSigZPtr[indexWordHi( 5 )] & 2 ) { - ++expZ; - shiftDist = 15; - } - softfloat_shortShiftLeft160M( extSigZPtr, shiftDist, extSigZPtr ); - softfloat_roundPackMToF128M( signZ, expZ, extSigZPtr, zWPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ96 = packToF128UI96( signZ, 0, 0 ); - uiZ96: - zWPtr[indexWordHi( 4 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = 0; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - -} - -#endif - diff --git a/softfloat/source/f128M_mulAdd.c b/softfloat/source/f128M_mulAdd.c deleted file mode 100644 index 2b0b7fe..0000000 --- a/softfloat/source/f128M_mulAdd.c +++ /dev/null @@ -1,92 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - f128M_mulAdd( - const float128_t *aPtr, - const float128_t *bPtr, - const float128_t *cPtr, - float128_t *zPtr - ) -{ - const uint64_t *aWPtr, *bWPtr, *cWPtr; - uint_fast64_t uiA64, uiA0; - uint_fast64_t uiB64, uiB0; - uint_fast64_t uiC64, uiC0; - - aWPtr = (const uint64_t *) aPtr; - bWPtr = (const uint64_t *) bPtr; - cWPtr = (const uint64_t *) cPtr; - uiA64 = aWPtr[indexWord( 2, 1 )]; - uiA0 = aWPtr[indexWord( 2, 0 )]; - uiB64 = bWPtr[indexWord( 2, 1 )]; - uiB0 = bWPtr[indexWord( 2, 0 )]; - uiC64 = cWPtr[indexWord( 2, 1 )]; - uiC0 = cWPtr[indexWord( 2, 0 )]; - *zPtr = softfloat_mulAddF128( uiA64, uiA0, uiB64, uiB0, uiC64, uiC0, 0 ); - -} - -#else - -void - f128M_mulAdd( - const float128_t *aPtr, - const float128_t *bPtr, - const float128_t *cPtr, - float128_t *zPtr - ) -{ - - softfloat_mulAddF128M( - (const uint32_t *) aPtr, - (const uint32_t *) bPtr, - (const uint32_t *) cPtr, - (uint32_t *) zPtr, - 0 - ); - -} - -#endif - diff --git a/softfloat/source/f128M_rem.c b/softfloat/source/f128M_rem.c deleted file mode 100644 index 39aafdd..0000000 --- a/softfloat/source/f128M_rem.c +++ /dev/null @@ -1,182 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - f128M_rem( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr ) -{ - - *zPtr = f128_rem( *aPtr, *bPtr ); - -} - -#else - -void - f128M_rem( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr ) -{ - const uint32_t *aWPtr, *bWPtr; - uint32_t *zWPtr, uiA96; - int32_t expA, expB; - uint32_t x[4], rem1[5], *remPtr; - bool signRem; - int32_t expDiff; - uint32_t q, recip32; - uint64_t q64; - uint32_t rem2[5], *altRemPtr, *newRemPtr, wordMeanRem; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - bWPtr = (const uint32_t *) bPtr; - zWPtr = (uint32_t *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA96 = aWPtr[indexWordHi( 4 )]; - expA = expF128UI96( uiA96 ); - expB = expF128UI96( bWPtr[indexWordHi( 4 )] ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) { - if ( softfloat_tryPropagateNaNF128M( aWPtr, bWPtr, zWPtr ) ) return; - if ( expA == 0x7FFF ) goto invalid; - goto copyA; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA < expB - 1 ) goto copyA; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expB = softfloat_shiftNormSigF128M( bWPtr, 13, x ); - if ( expB == -128 ) goto invalid; - remPtr = &rem1[indexMultiwordLo( 5, 4 )]; - expA = softfloat_shiftNormSigF128M( aWPtr, 13, remPtr ); - if ( expA == -128 ) goto copyA; - signRem = signF128UI96( uiA96 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( expDiff < 1 ) { - if ( expDiff < -1 ) goto copyA; - if ( expDiff ) { - --expB; - softfloat_add128M( x, x, x ); - q = 0; - } else { - q = (softfloat_compare128M( x, remPtr ) <= 0); - if ( q ) softfloat_sub128M( remPtr, x, remPtr ); - } - } else { - recip32 = - softfloat_approxRecip32_1( - ((uint64_t) x[indexWord( 4, 3 )]<<32 | x[indexWord( 4, 2 )]) - >>30 - ); - expDiff -= 30; - for (;;) { - q64 = (uint64_t) remPtr[indexWordHi( 4 )] * recip32; - if ( expDiff < 0 ) break; - q = (q64 + 0x80000000)>>32; - softfloat_remStep128MBy32( remPtr, 29, x, q, remPtr ); - if ( remPtr[indexWordHi( 4 )] & 0x80000000 ) { - softfloat_add128M( remPtr, x, remPtr ); - } - expDiff -= 29; - } - /*-------------------------------------------------------------------- - | (`expDiff' cannot be less than -29 here.) - *--------------------------------------------------------------------*/ - q = (uint32_t) (q64>>32)>>(~expDiff & 31); - softfloat_remStep128MBy32( remPtr, expDiff + 30, x, q, remPtr ); - if ( remPtr[indexWordHi( 4 )] & 0x80000000 ) { - altRemPtr = &rem2[indexMultiwordLo( 5, 4 )]; - softfloat_add128M( remPtr, x, altRemPtr ); - goto selectRem; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - altRemPtr = &rem2[indexMultiwordLo( 5, 4 )]; - do { - ++q; - newRemPtr = altRemPtr; - softfloat_sub128M( remPtr, x, newRemPtr ); - altRemPtr = remPtr; - remPtr = newRemPtr; - } while ( ! (remPtr[indexWordHi( 4 )] & 0x80000000) ); - selectRem: - softfloat_add128M( remPtr, altRemPtr, x ); - wordMeanRem = x[indexWordHi( 4 )]; - if ( - (wordMeanRem & 0x80000000) - || (! wordMeanRem && (q & 1) && ! x[indexWord( 4, 0 )] - && ! (x[indexWord( 4, 2 )] | x[indexWord( 4, 1 )])) - ) { - remPtr = altRemPtr; - } - if ( remPtr[indexWordHi( 4 )] & 0x80000000 ) { - signRem = ! signRem; - softfloat_negX128M( remPtr ); - } - remPtr -= indexMultiwordLo( 5, 4 ); - remPtr[indexWordHi( 5 )] = 0; - softfloat_normRoundPackMToF128M( signRem, expB + 18, remPtr, zWPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_invalidF128M( zWPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - copyA: - zWPtr[indexWordHi( 4 )] = uiA96; - zWPtr[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )]; - zWPtr[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )]; - zWPtr[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )]; - -} - -#endif - diff --git a/softfloat/source/f128M_roundToInt.c b/softfloat/source/f128M_roundToInt.c deleted file mode 100644 index b96d742..0000000 --- a/softfloat/source/f128M_roundToInt.c +++ /dev/null @@ -1,223 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - f128M_roundToInt( - const float128_t *aPtr, - uint_fast8_t roundingMode, - bool exact, - float128_t *zPtr - ) -{ - - *zPtr = f128_roundToInt( *aPtr, roundingMode, exact ); - -} - -#else - -void - f128M_roundToInt( - const float128_t *aPtr, - uint_fast8_t roundingMode, - bool exact, - float128_t *zPtr - ) -{ - const uint32_t *aWPtr; - uint32_t *zWPtr; - uint32_t ui96; - int32_t exp; - uint32_t sigExtra; - bool sign; - uint_fast8_t bitPos; - bool roundNear; - unsigned int index, lastIndex; - bool extra; - uint32_t wordA, bit, wordZ; - uint_fast8_t carry; - uint32_t extrasMask; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - zWPtr = (uint32_t *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - ui96 = aWPtr[indexWordHi( 4 )]; - exp = expF128UI96( ui96 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp < 0x3FFF ) { - zWPtr[indexWord( 4, 2 )] = 0; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - sigExtra = aWPtr[indexWord( 4, 2 )]; - if ( !sigExtra ) { - sigExtra = aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )]; - } - if ( !sigExtra && !(ui96 & 0x7FFFFFFF) ) goto ui96; - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - sign = signF128UI96( ui96 ); - switch ( roundingMode ) { - case softfloat_round_near_even: - if ( !fracF128UI96( ui96 ) && !sigExtra ) break; - case softfloat_round_near_maxMag: - if ( exp == 0x3FFE ) goto mag1; - break; - case softfloat_round_min: - if ( sign ) goto mag1; - break; - case softfloat_round_max: - if ( !sign ) goto mag1; - break; -#ifdef SOFTFLOAT_ROUND_ODD - case softfloat_round_odd: - goto mag1; -#endif - } - ui96 = packToF128UI96( sign, 0, 0 ); - goto ui96; - mag1: - ui96 = packToF128UI96( sign, 0x3FFF, 0 ); - goto ui96; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x406F <= exp ) { - if ( - (exp == 0x7FFF) - && (fracF128UI96( ui96 ) - || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )])) - ) { - softfloat_propagateNaNF128M( aWPtr, 0, zWPtr ); - return; - } - zWPtr[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )]; - zWPtr[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )]; - zWPtr[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )]; - goto ui96; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - bitPos = 0x406F - exp; - roundNear = - (roundingMode == softfloat_round_near_maxMag) - || (roundingMode == softfloat_round_near_even); - bitPos -= roundNear; - index = indexWordLo( 4 ); - lastIndex = indexWordHi( 4 ); - extra = 0; - for (;;) { - wordA = aWPtr[index]; - if ( bitPos < 32 ) break; - if ( wordA ) extra = 1; - zWPtr[index] = 0; - index += wordIncr; - bitPos -= 32; - } - bit = (uint32_t) 1< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void f128M_sqrt( const float128_t *aPtr, float128_t *zPtr ) -{ - - *zPtr = f128_sqrt( *aPtr ); - -} - -#else - -void f128M_sqrt( const float128_t *aPtr, float128_t *zPtr ) -{ - const uint32_t *aWPtr; - uint32_t *zWPtr; - uint32_t uiA96; - bool signA; - int32_t rawExpA; - uint32_t rem[6]; - int32_t expA, expZ; - uint64_t rem64; - uint32_t sig32A, recipSqrt32, sig32Z, qs[3], q; - uint64_t sig64Z; - uint32_t term[5]; - uint64_t x64; - uint32_t y[5], rem32; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - zWPtr = (uint32_t *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA96 = aWPtr[indexWordHi( 4 )]; - signA = signF128UI96( uiA96 ); - rawExpA = expF128UI96( uiA96 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( rawExpA == 0x7FFF ) { - if ( - fracF128UI96( uiA96 ) - || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )]) - ) { - softfloat_propagateNaNF128M( aWPtr, 0, zWPtr ); - return; - } - if ( ! signA ) goto copyA; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = softfloat_shiftNormSigF128M( aWPtr, 13 - (rawExpA & 1), rem ); - if ( expA == -128 ) goto copyA; - if ( signA ) goto invalid; - /*------------------------------------------------------------------------ - | (`sig32Z' is guaranteed to be a lower bound on the square root of - | `sig32A', which makes `sig32Z' also a lower bound on the square root of - | `sigA'.) - *------------------------------------------------------------------------*/ - expZ = ((expA - 0x3FFF)>>1) + 0x3FFE; - expA &= 1; - rem64 = (uint64_t) rem[indexWord( 4, 3 )]<<32 | rem[indexWord( 4, 2 )]; - if ( expA ) { - if ( ! rawExpA ) { - softfloat_shortShiftRight128M( rem, 1, rem ); - rem64 >>= 1; - } - sig32A = rem64>>29; - } else { - sig32A = rem64>>30; - } - recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A ); - sig32Z = ((uint64_t) sig32A * recipSqrt32)>>32; - if ( expA ) sig32Z >>= 1; - qs[2] = sig32Z; - rem64 -= (uint64_t) sig32Z * sig32Z; - rem[indexWord( 4, 3 )] = rem64>>32; - rem[indexWord( 4, 2 )] = rem64; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q = ((uint32_t) (rem64>>2) * (uint64_t) recipSqrt32)>>32; - sig64Z = ((uint64_t) sig32Z<<32) + ((uint64_t) q<<3); - term[indexWord( 4, 3 )] = 0; - term[indexWord( 4, 0 )] = 0; - /*------------------------------------------------------------------------ - | (Repeating this loop is a rare occurrence.) - *------------------------------------------------------------------------*/ - for (;;) { - x64 = ((uint64_t) sig32Z<<32) + sig64Z; - term[indexWord( 4, 2 )] = x64>>32; - term[indexWord( 4, 1 )] = x64; - softfloat_remStep128MBy32( rem, 29, term, q, y ); - rem32 = y[indexWord( 4, 3 )]; - if ( ! (rem32 & 0x80000000) ) break; - --q; - sig64Z -= 1<<3; - } - qs[1] = q; - rem64 = (uint64_t) rem32<<32 | y[indexWord( 4, 2 )]; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q = ((uint32_t) (rem64>>2) * (uint64_t) recipSqrt32)>>32; - if ( rem64>>34 ) q += recipSqrt32; - sig64Z <<= 1; - /*------------------------------------------------------------------------ - | (Repeating this loop is a rare occurrence.) - *------------------------------------------------------------------------*/ - for (;;) { - x64 = sig64Z + (q>>26); - term[indexWord( 4, 2 )] = x64>>32; - term[indexWord( 4, 1 )] = x64; - term[indexWord( 4, 0 )] = q<<6; - softfloat_remStep128MBy32( - y, 29, term, q, &rem[indexMultiwordHi( 6, 4 )] ); - rem32 = rem[indexWordHi( 6 )]; - if ( ! (rem32 & 0x80000000) ) break; - --q; - } - qs[0] = q; - rem64 = (uint64_t) rem32<<32 | rem[indexWord( 6, 4 )]; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q = (((uint32_t) (rem64>>2) * (uint64_t) recipSqrt32)>>32) + 2; - if ( rem64>>34 ) q += recipSqrt32; - x64 = (uint64_t) q<<27; - y[indexWord( 5, 0 )] = x64; - x64 = ((uint64_t) qs[0]<<24) + (x64>>32); - y[indexWord( 5, 1 )] = x64; - x64 = ((uint64_t) qs[1]<<21) + (x64>>32); - y[indexWord( 5, 2 )] = x64; - x64 = ((uint64_t) qs[2]<<18) + (x64>>32); - y[indexWord( 5, 3 )] = x64; - y[indexWord( 5, 4 )] = x64>>32; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (q & 0xF) <= 2 ) { - q &= ~3; - y[indexWordLo( 5 )] = q<<27; - term[indexWord( 5, 4 )] = 0; - term[indexWord( 5, 3 )] = 0; - term[indexWord( 5, 2 )] = 0; - term[indexWord( 5, 1 )] = q>>6; - term[indexWord( 5, 0 )] = q<<26; - softfloat_sub160M( y, term, term ); - rem[indexWord( 6, 1 )] = 0; - rem[indexWord( 6, 0 )] = 0; - softfloat_remStep160MBy32( - &rem[indexMultiwordLo( 6, 5 )], - 14, - term, - q, - &rem[indexMultiwordLo( 6, 5 )] - ); - rem32 = rem[indexWord( 6, 4 )]; - if ( rem32 & 0x80000000 ) { - softfloat_sub1X160M( y ); - } else { - if ( - rem32 || rem[indexWord( 6, 0 )] || rem[indexWord( 6, 1 )] - || (rem[indexWord( 6, 3 )] | rem[indexWord( 6, 2 )]) - ) { - y[indexWordLo( 5 )] |= 1; - } - } - } - softfloat_roundPackMToF128M( 0, expZ, y, zWPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_invalidF128M( zWPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - copyA: - zWPtr[indexWordHi( 4 )] = uiA96; - zWPtr[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )]; - zWPtr[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )]; - zWPtr[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )]; - -} - -#endif - diff --git a/softfloat/source/f128M_sub.c b/softfloat/source/f128M_sub.c deleted file mode 100644 index 5d65c79..0000000 --- a/softfloat/source/f128M_sub.c +++ /dev/null @@ -1,97 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void - f128M_sub( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr ) -{ - const uint64_t *aWPtr, *bWPtr; - uint_fast64_t uiA64, uiA0; - bool signA; - uint_fast64_t uiB64, uiB0; - bool signB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) - float128_t - (*magsFuncPtr)( - uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool ); -#endif - - aWPtr = (const uint64_t *) aPtr; - bWPtr = (const uint64_t *) bPtr; - uiA64 = aWPtr[indexWord( 2, 1 )]; - uiA0 = aWPtr[indexWord( 2, 0 )]; - signA = signF128UI64( uiA64 ); - uiB64 = bWPtr[indexWord( 2, 1 )]; - uiB0 = bWPtr[indexWord( 2, 0 )]; - signB = signF128UI64( uiB64 ); -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) - if ( signA == signB ) { - *zPtr = softfloat_subMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); - } else { - *zPtr = softfloat_addMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); - } -#else - magsFuncPtr = - (signA == signB) ? softfloat_subMagsF128 : softfloat_addMagsF128; - *zPtr = (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA ); -#endif - -} - -#else - -void - f128M_sub( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr ) -{ - - softfloat_addF128M( - (const uint32_t *) aPtr, - (const uint32_t *) bPtr, - (uint32_t *) zPtr, - true - ); - -} - -#endif - diff --git a/softfloat/source/f128M_to_extF80M.c b/softfloat/source/f128M_to_extF80M.c deleted file mode 100644 index b0340c7..0000000 --- a/softfloat/source/f128M_to_extF80M.c +++ /dev/null @@ -1,101 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void f128M_to_extF80M( const float128_t *aPtr, extFloat80_t *zPtr ) -{ - - *zPtr = f128_to_extF80( *aPtr ); - -} - -#else - -void f128M_to_extF80M( const float128_t *aPtr, extFloat80_t *zPtr ) -{ - const uint32_t *aWPtr; - struct extFloat80M *zSPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - struct commonNaN commonNaN; - uint32_t sig[4]; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - zSPtr = (struct extFloat80M *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( softfloat_isNaNF128M( aWPtr ) ) { - softfloat_f128MToCommonNaN( aWPtr, &commonNaN ); - softfloat_commonNaNToExtF80M( &commonNaN, zSPtr ); - return; - } - zSPtr->signExp = packToExtF80UI64( sign, 0x7FFF ); - zSPtr->signif = UINT64_C( 0x8000000000000000 ); - return; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - exp = softfloat_shiftNormSigF128M( aWPtr, 15, sig ); - if ( exp == -128 ) { - zSPtr->signExp = packToExtF80UI64( sign, 0 ); - zSPtr->signif = 0; - return; - } - if ( sig[indexWord( 4, 0 )] ) sig[indexWord( 4, 1 )] |= 1; - softfloat_roundPackMToExtF80M( - sign, exp, &sig[indexMultiwordHi( 4, 3 )], 80, zSPtr ); - -} - -#endif - diff --git a/softfloat/source/f128M_to_f16.c b/softfloat/source/f128M_to_f16.c deleted file mode 100644 index 95109a7..0000000 --- a/softfloat/source/f128M_to_f16.c +++ /dev/null @@ -1,113 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -float16_t f128M_to_f16( const float128_t *aPtr ) -{ - - return f128_to_f16( *aPtr ); - -} - -#else - -float16_t f128M_to_f16( const float128_t *aPtr ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - uint32_t frac32; - struct commonNaN commonNaN; - uint16_t uiZ, frac16; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - frac32 = - fracF128UI96( uiA96 ) - | ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )]) - != 0); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( frac32 ) { - softfloat_f128MToCommonNaN( aWPtr, &commonNaN ); - uiZ = softfloat_commonNaNToF16UI( &commonNaN ); - } else { - uiZ = packToF16UI( sign, 0x1F, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - frac16 = frac32>>2 | (frac32 & 3); - if ( ! (exp | frac16) ) { - uiZ = packToF16UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - exp -= 0x3FF1; - if ( sizeof (int_fast16_t) < sizeof (int32_t) ) { - if ( exp < -0x40 ) exp = -0x40; - } - return softfloat_roundPackToF16( sign, exp, frac16 | 0x4000 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - -#endif - diff --git a/softfloat/source/f128M_to_f32.c b/softfloat/source/f128M_to_f32.c deleted file mode 100644 index 4542deb..0000000 --- a/softfloat/source/f128M_to_f32.c +++ /dev/null @@ -1,109 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -float32_t f128M_to_f32( const float128_t *aPtr ) -{ - - return f128_to_f32( *aPtr ); - -} - -#else - -float32_t f128M_to_f32( const float128_t *aPtr ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - uint64_t frac64; - struct commonNaN commonNaN; - uint32_t uiZ, frac32; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - frac64 = - (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )] - | ((aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )]) != 0); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( frac64 ) { - softfloat_f128MToCommonNaN( aWPtr, &commonNaN ); - uiZ = softfloat_commonNaNToF32UI( &commonNaN ); - } else { - uiZ = packToF32UI( sign, 0xFF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - frac32 = softfloat_shortShiftRightJam64( frac64, 18 ); - if ( ! (exp | frac32) ) { - uiZ = packToF32UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - exp -= 0x3F81; - if ( sizeof (int_fast16_t) < sizeof (int32_t) ) { - if ( exp < -0x1000 ) exp = -0x1000; - } - return softfloat_roundPackToF32( sign, exp, frac32 | 0x40000000 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - -#endif - diff --git a/softfloat/source/f128M_to_f64.c b/softfloat/source/f128M_to_f64.c deleted file mode 100644 index 6213bb7..0000000 --- a/softfloat/source/f128M_to_f64.c +++ /dev/null @@ -1,112 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -float64_t f128M_to_f64( const float128_t *aPtr ) -{ - - return f128_to_f64( *aPtr ); - -} - -#else - -float64_t f128M_to_f64( const float128_t *aPtr ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - uint64_t frac64; - struct commonNaN commonNaN; - uint64_t uiZ; - uint32_t frac32; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - frac64 = (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )]; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( frac64 || aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )] ) { - softfloat_f128MToCommonNaN( aWPtr, &commonNaN ); - uiZ = softfloat_commonNaNToF64UI( &commonNaN ); - } else { - uiZ = packToF64UI( sign, 0x7FF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - frac32 = aWPtr[indexWord( 4, 1 )]; - frac64 = frac64<<14 | frac32>>18; - if ( (frac32 & 0x0003FFFF) || aWPtr[indexWord( 4, 0 )] ) frac64 |= 1; - if ( ! (exp | frac64) ) { - uiZ = packToF64UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - exp -= 0x3C01; - if ( sizeof (int_fast16_t) < sizeof (int32_t) ) { - if ( exp < -0x1000 ) exp = -0x1000; - } - return - softfloat_roundPackToF64( - sign, exp, frac64 | UINT64_C( 0x4000000000000000 ) ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - -#endif - diff --git a/softfloat/source/f128M_to_i32.c b/softfloat/source/f128M_to_i32.c deleted file mode 100644 index 54cc6f6..0000000 --- a/softfloat/source/f128M_to_i32.c +++ /dev/null @@ -1,98 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -int_fast32_t - f128M_to_i32( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - - return f128_to_i32( *aPtr, roundingMode, exact ); - -} - -#else - -int_fast32_t - f128M_to_i32( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - uint64_t sig64; - int32_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - sig64 = (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )]; - if ( aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )] ) sig64 |= 1; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ -#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow) - if ( (exp == 0x7FFF) && sig64 ) { -#if (i32_fromNaN == i32_fromPosOverflow) - sign = 0; -#elif (i32_fromNaN == i32_fromNegOverflow) - sign = 1; -#else - softfloat_raiseFlags( softfloat_flag_invalid ); - return i32_fromNaN; -#endif - } -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 ); - shiftDist = 0x4023 - exp; - if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist ); - return softfloat_roundToI32( sign, sig64, roundingMode, exact ); - -} - -#endif - diff --git a/softfloat/source/f128M_to_i32_r_minMag.c b/softfloat/source/f128M_to_i32_r_minMag.c deleted file mode 100644 index 1f22039..0000000 --- a/softfloat/source/f128M_to_i32_r_minMag.c +++ /dev/null @@ -1,106 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -int_fast32_t f128M_to_i32_r_minMag( const float128_t *aPtr, bool exact ) -{ - - return f128_to_i32_r_minMag( *aPtr, exact ); - -} - -#else - -int_fast32_t f128M_to_i32_r_minMag( const float128_t *aPtr, bool exact ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - uint64_t sig64; - int32_t shiftDist; - uint32_t absZ, uiZ; - union { uint32_t ui; int32_t i; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - sig64 = (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )]; - if ( aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )] ) sig64 |= 1; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp < 0x3FFF ) { - if ( exact && (exp | sig64) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x401F <= exp ) goto invalid; - shiftDist = 0x402F - exp; - sig64 |= UINT64_C( 0x0001000000000000 ); - absZ = sig64>>shiftDist; - uiZ = sign ? -absZ : absZ; - if ( uiZ>>31 != sign ) goto invalid; - if ( exact && ((uint64_t) absZ< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -int_fast64_t - f128M_to_i64( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - - return f128_to_i64( *aPtr, roundingMode, exact ); - -} - -#else - -int_fast64_t - f128M_to_i64( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - uint32_t sig96; - int32_t shiftDist; - uint32_t sig[4]; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - sig96 = fracF128UI96( uiA96 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x404F - exp; - if ( shiftDist < 17 ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) - && (sig96 - || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )])) - ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig96 |= 0x00010000; - sig[indexWord( 4, 3 )] = sig96; - sig[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )]; - sig[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )]; - sig[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )]; - softfloat_shiftRightJam128M( sig, shiftDist, sig ); - return - softfloat_roundMToI64( - sign, sig + indexMultiwordLo( 4, 3 ), roundingMode, exact ); - -} - -#endif - diff --git a/softfloat/source/f128M_to_i64_r_minMag.c b/softfloat/source/f128M_to_i64_r_minMag.c deleted file mode 100644 index da3d28a..0000000 --- a/softfloat/source/f128M_to_i64_r_minMag.c +++ /dev/null @@ -1,124 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -int_fast64_t f128M_to_i64_r_minMag( const float128_t *aPtr, bool exact ) -{ - - return f128_to_i64_r_minMag( *aPtr, exact ); - -} - -#else - -int_fast64_t f128M_to_i64_r_minMag( const float128_t *aPtr, bool exact ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - uint32_t sig96; - int32_t shiftDist; - uint32_t sig[4]; - uint64_t uiZ; - union { uint64_t ui; int64_t i; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - sig96 = fracF128UI96( uiA96 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x403E - exp; - if ( shiftDist < 0 ) goto invalid; - if ( exact ) { - if ( exp ) sig96 |= 0x00010000; - sig[indexWord( 4, 3 )] = sig96; - sig[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )]; - sig[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )]; - sig[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )]; - softfloat_shiftRightJam128M( sig, shiftDist + 17, sig ); - uiZ = (uint64_t) sig[indexWord( 4, 2 )]<<32 | sig[indexWord( 4, 1 )]; - if ( uiZ>>63 && (! sign || (uiZ != UINT64_C( 0x8000000000000000 ))) ) { - goto invalid; - } - if ( sig[indexWordLo( 4 )] ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - } else { - if ( 64 <= shiftDist ) return 0; - uiZ = - (uint64_t) sig96<<47 - | (uint64_t) aWPtr[indexWord( 4, 2 )]<<15 - | aWPtr[indexWord( 4, 1 )]>>17; - if ( shiftDist ) { - uiZ |= UINT64_C( 0x8000000000000000 ); - uiZ >>= shiftDist; - } else { - if ( uiZ || ! sign ) goto invalid; - uiZ |= UINT64_C( 0x8000000000000000 ); - } - } - if ( sign ) uiZ = -uiZ; - uZ.ui = uiZ; - return uZ.i; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) - && (sig96 - || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )])) - ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - -} - -#endif - diff --git a/softfloat/source/f128M_to_ui32.c b/softfloat/source/f128M_to_ui32.c deleted file mode 100644 index c1baa06..0000000 --- a/softfloat/source/f128M_to_ui32.c +++ /dev/null @@ -1,98 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -uint_fast32_t - f128M_to_ui32( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - - return f128_to_ui32( *aPtr, roundingMode, exact ); - -} - -#else - -uint_fast32_t - f128M_to_ui32( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - uint64_t sig64; - int32_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - sig64 = (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )]; - if ( aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )] ) sig64 |= 1; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ -#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow) - if ( (exp == 0x7FFF) && sig64 ) { -#if (ui32_fromNaN == ui32_fromPosOverflow) - sign = 0; -#elif (ui32_fromNaN == ui32_fromNegOverflow) - sign = 1; -#else - softfloat_raiseFlags( softfloat_flag_invalid ); - return ui32_fromNaN; -#endif - } -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 ); - shiftDist = 0x4023 - exp; - if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist ); - return softfloat_roundToUI32( sign, sig64, roundingMode, exact ); - -} - -#endif - diff --git a/softfloat/source/f128M_to_ui32_r_minMag.c b/softfloat/source/f128M_to_ui32_r_minMag.c deleted file mode 100644 index a1aca62..0000000 --- a/softfloat/source/f128M_to_ui32_r_minMag.c +++ /dev/null @@ -1,102 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -uint_fast32_t f128M_to_ui32_r_minMag( const float128_t *aPtr, bool exact ) -{ - - return f128_to_ui32_r_minMag( *aPtr, exact ); - -} - -#else - -uint_fast32_t f128M_to_ui32_r_minMag( const float128_t *aPtr, bool exact ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - int32_t exp; - uint64_t sig64; - int32_t shiftDist; - bool sign; - uint32_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - exp = expF128UI96( uiA96 ); - sig64 = (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )]; - if ( aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )] ) sig64 |= 1; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x402F - exp; - if ( 49 <= shiftDist ) { - if ( exact && (exp | sig64) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF128UI96( uiA96 ); - if ( sign || (shiftDist < 17) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && sig64 ? ui32_fromNaN - : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig64 |= UINT64_C( 0x0001000000000000 ); - z = sig64>>shiftDist; - if ( exact && ((uint64_t) z< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -uint_fast64_t - f128M_to_ui64( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - - return f128_to_ui64( *aPtr, roundingMode, exact ); - -} - -#else - -uint_fast64_t - f128M_to_ui64( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - uint32_t sig96; - int32_t shiftDist; - uint32_t sig[4]; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - sig96 = fracF128UI96( uiA96 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x404F - exp; - if ( shiftDist < 17 ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) - && (sig96 - || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )])) - ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig96 |= 0x00010000; - sig[indexWord( 4, 3 )] = sig96; - sig[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )]; - sig[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )]; - sig[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )]; - softfloat_shiftRightJam128M( sig, shiftDist, sig ); - return - softfloat_roundMToUI64( - sign, sig + indexMultiwordLo( 4, 3 ), roundingMode, exact ); - -} - -#endif - diff --git a/softfloat/source/f128M_to_ui64_r_minMag.c b/softfloat/source/f128M_to_ui64_r_minMag.c deleted file mode 100644 index 7a1b602..0000000 --- a/softfloat/source/f128M_to_ui64_r_minMag.c +++ /dev/null @@ -1,114 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -uint_fast64_t f128M_to_ui64_r_minMag( const float128_t *aPtr, bool exact ) -{ - - return f128_to_ui64_r_minMag( *aPtr, exact ); - -} - -#else - -uint_fast64_t f128M_to_ui64_r_minMag( const float128_t *aPtr, bool exact ) -{ - const uint32_t *aWPtr; - uint32_t uiA96; - bool sign; - int32_t exp; - uint32_t sig96; - int32_t shiftDist; - uint32_t sig[4]; - uint64_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - aWPtr = (const uint32_t *) aPtr; - uiA96 = aWPtr[indexWordHi( 4 )]; - sign = signF128UI96( uiA96 ); - exp = expF128UI96( uiA96 ); - sig96 = fracF128UI96( uiA96 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x403E - exp; - if ( shiftDist < 0 ) goto invalid; - if ( exact ) { - if ( exp ) sig96 |= 0x00010000; - sig[indexWord( 4, 3 )] = sig96; - sig[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )]; - sig[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )]; - sig[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )]; - softfloat_shiftRightJam128M( sig, shiftDist + 17, sig ); - z = (uint64_t) sig[indexWord( 4, 2 )]<<32 | sig[indexWord( 4, 1 )]; - if ( sign && z ) goto invalid; - if ( sig[indexWordLo( 4 )] ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - } else { - if ( 64 <= shiftDist ) return 0; - if ( sign ) goto invalid; - z = UINT64_C( 0x8000000000000000 ) - | (uint64_t) sig96<<47 - | (uint64_t) aWPtr[indexWord( 4, 2 )]<<15 - | aWPtr[indexWord( 4, 1 )]>>17; - z >>= shiftDist; - } - return z; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) - && (sig96 - || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )])) - ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - -} - -#endif - diff --git a/softfloat/source/f128_add.c b/softfloat/source/f128_add.c deleted file mode 100644 index e9caba6..0000000 --- a/softfloat/source/f128_add.c +++ /dev/null @@ -1,78 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float128_t f128_add( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool signA; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - bool signB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) - float128_t - (*magsFuncPtr)( - uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool ); -#endif - - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - signA = signF128UI64( uiA64 ); - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - signB = signF128UI64( uiB64 ); -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) - if ( signA == signB ) { - return softfloat_addMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); - } else { - return softfloat_subMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); - } -#else - magsFuncPtr = - (signA == signB) ? softfloat_addMagsF128 : softfloat_subMagsF128; - return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA ); -#endif - -} - diff --git a/softfloat/source/f128_div.c b/softfloat/source/f128_div.c deleted file mode 100644 index 0693db7..0000000 --- a/softfloat/source/f128_div.c +++ /dev/null @@ -1,199 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t f128_div( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool signA; - int_fast32_t expA; - struct uint128 sigA; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - bool signB; - int_fast32_t expB; - struct uint128 sigB; - bool signZ; - struct exp32_sig128 normExpSig; - int_fast32_t expZ; - struct uint128 rem; - uint_fast32_t recip32; - int ix; - uint_fast64_t q64; - uint_fast32_t q; - struct uint128 term; - uint_fast32_t qs[3]; - uint_fast64_t sigZExtra; - struct uint128 sigZ, uiZ; - union ui128_f128 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - signA = signF128UI64( uiA64 ); - expA = expF128UI64( uiA64 ); - sigA.v64 = fracF128UI64( uiA64 ); - sigA.v0 = uiA0; - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - signB = signF128UI64( uiB64 ); - expB = expF128UI64( uiB64 ); - sigB.v64 = fracF128UI64( uiB64 ); - sigB.v0 = uiB0; - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FFF ) { - if ( sigA.v64 | sigA.v0 ) goto propagateNaN; - if ( expB == 0x7FFF ) { - if ( sigB.v64 | sigB.v0 ) goto propagateNaN; - goto invalid; - } - goto infinity; - } - if ( expB == 0x7FFF ) { - if ( sigB.v64 | sigB.v0 ) goto propagateNaN; - goto zero; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) { - if ( ! (sigB.v64 | sigB.v0) ) { - if ( ! (expA | sigA.v64 | sigA.v0) ) goto invalid; - softfloat_raiseFlags( softfloat_flag_infinite ); - goto infinity; - } - normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - if ( ! expA ) { - if ( ! (sigA.v64 | sigA.v0) ) goto zero; - normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA - expB + 0x3FFE; - sigA.v64 |= UINT64_C( 0x0001000000000000 ); - sigB.v64 |= UINT64_C( 0x0001000000000000 ); - rem = sigA; - if ( softfloat_lt128( sigA.v64, sigA.v0, sigB.v64, sigB.v0 ) ) { - --expZ; - rem = softfloat_add128( sigA.v64, sigA.v0, sigA.v64, sigA.v0 ); - } - recip32 = softfloat_approxRecip32_1( sigB.v64>>17 ); - ix = 3; - for (;;) { - q64 = (uint_fast64_t) (uint32_t) (rem.v64>>19) * recip32; - q = (q64 + 0x80000000)>>32; - --ix; - if ( ix < 0 ) break; - rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); - term = softfloat_mul128By32( sigB.v64, sigB.v0, q ); - rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - --q; - rem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); - } - qs[ix] = q; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ((q + 1) & 7) < 2 ) { - rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); - term = softfloat_mul128By32( sigB.v64, sigB.v0, q ); - rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - --q; - rem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); - } else if ( softfloat_le128( sigB.v64, sigB.v0, rem.v64, rem.v0 ) ) { - ++q; - rem = softfloat_sub128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); - } - if ( rem.v64 | rem.v0 ) q |= 1; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sigZExtra = (uint64_t) ((uint_fast64_t) q<<60); - term = softfloat_shortShiftLeft128( 0, qs[1], 54 ); - sigZ = - softfloat_add128( - (uint_fast64_t) qs[2]<<19, ((uint_fast64_t) qs[0]<<25) + (q>>4), - term.v64, term.v0 - ); - return - softfloat_roundPackToF128( signZ, expZ, sigZ.v64, sigZ.v0, sigZExtra ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infinity: - uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 ); - goto uiZ0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ.v64 = packToF128UI64( signZ, 0, 0 ); - uiZ0: - uiZ.v0 = 0; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f128_eq.c b/softfloat/source/f128_eq.c deleted file mode 100644 index 9462fc2..0000000 --- a/softfloat/source/f128_eq.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f128_eq( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { - if ( - softfloat_isSigNaNF128UI( uiA64, uiA0 ) - || softfloat_isSigNaNF128UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - return - (uiA0 == uiB0) - && ( (uiA64 == uiB64) - || (! uiA0 && ! ((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))) - ); - -} - diff --git a/softfloat/source/f128_eq_signaling.c b/softfloat/source/f128_eq_signaling.c deleted file mode 100644 index 5d0819d..0000000 --- a/softfloat/source/f128_eq_signaling.c +++ /dev/null @@ -1,67 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f128_eq_signaling( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - return - (uiA0 == uiB0) - && ( (uiA64 == uiB64) - || (! uiA0 && ! ((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))) - ); - -} - diff --git a/softfloat/source/f128_isSignalingNaN.c b/softfloat/source/f128_isSignalingNaN.c deleted file mode 100644 index a764ff6..0000000 --- a/softfloat/source/f128_isSignalingNaN.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f128_isSignalingNaN( float128_t a ) -{ - union ui128_f128 uA; - - uA.f = a; - return softfloat_isSigNaNF128UI( uA.ui.v64, uA.ui.v0 ); - -} - diff --git a/softfloat/source/f128_le.c b/softfloat/source/f128_le.c deleted file mode 100644 index 521a1cb..0000000 --- a/softfloat/source/f128_le.c +++ /dev/null @@ -1,72 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f128_le( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - bool signA, signB; - - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - signA = signF128UI64( uiA64 ); - signB = signF128UI64( uiB64 ); - return - (signA != signB) - ? signA - || ! (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - | uiA0 | uiB0) - : ((uiA64 == uiB64) && (uiA0 == uiB0)) - || (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); - -} - diff --git a/softfloat/source/f128_le_quiet.c b/softfloat/source/f128_le_quiet.c deleted file mode 100644 index 820b28b..0000000 --- a/softfloat/source/f128_le_quiet.c +++ /dev/null @@ -1,78 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f128_le_quiet( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - bool signA, signB; - - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { - if ( - softfloat_isSigNaNF128UI( uiA64, uiA0 ) - || softfloat_isSigNaNF128UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - signA = signF128UI64( uiA64 ); - signB = signF128UI64( uiB64 ); - return - (signA != signB) - ? signA - || ! (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - | uiA0 | uiB0) - : ((uiA64 == uiB64) && (uiA0 == uiB0)) - || (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); - -} - diff --git a/softfloat/source/f128_lt.c b/softfloat/source/f128_lt.c deleted file mode 100644 index fa46ae2..0000000 --- a/softfloat/source/f128_lt.c +++ /dev/null @@ -1,72 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f128_lt( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - bool signA, signB; - - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - signA = signF128UI64( uiA64 ); - signB = signF128UI64( uiB64 ); - return - (signA != signB) - ? signA - && (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - | uiA0 | uiB0) - : ((uiA64 != uiB64) || (uiA0 != uiB0)) - && (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); - -} - diff --git a/softfloat/source/f128_lt_quiet.c b/softfloat/source/f128_lt_quiet.c deleted file mode 100644 index d491de2..0000000 --- a/softfloat/source/f128_lt_quiet.c +++ /dev/null @@ -1,78 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f128_lt_quiet( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - bool signA, signB; - - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { - if ( - softfloat_isSigNaNF128UI( uiA64, uiA0 ) - || softfloat_isSigNaNF128UI( uiB64, uiB0 ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - signA = signF128UI64( uiA64 ); - signB = signF128UI64( uiB64 ); - return - (signA != signB) - ? signA - && (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - | uiA0 | uiB0) - : ((uiA64 != uiB64) || (uiA0 != uiB0)) - && (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); - -} - diff --git a/softfloat/source/f128_mul.c b/softfloat/source/f128_mul.c deleted file mode 100644 index 24af86a..0000000 --- a/softfloat/source/f128_mul.c +++ /dev/null @@ -1,163 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t f128_mul( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool signA; - int_fast32_t expA; - struct uint128 sigA; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - bool signB; - int_fast32_t expB; - struct uint128 sigB; - bool signZ; - uint_fast64_t magBits; - struct exp32_sig128 normExpSig; - int_fast32_t expZ; - uint64_t sig256Z[4]; - uint_fast64_t sigZExtra; - struct uint128 sigZ; - struct uint128_extra sig128Extra; - struct uint128 uiZ; - union ui128_f128 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - signA = signF128UI64( uiA64 ); - expA = expF128UI64( uiA64 ); - sigA.v64 = fracF128UI64( uiA64 ); - sigA.v0 = uiA0; - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - signB = signF128UI64( uiB64 ); - expB = expF128UI64( uiB64 ); - sigB.v64 = fracF128UI64( uiB64 ); - sigB.v0 = uiB0; - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FFF ) { - if ( - (sigA.v64 | sigA.v0) || ((expB == 0x7FFF) && (sigB.v64 | sigB.v0)) - ) { - goto propagateNaN; - } - magBits = expB | sigB.v64 | sigB.v0; - goto infArg; - } - if ( expB == 0x7FFF ) { - if ( sigB.v64 | sigB.v0 ) goto propagateNaN; - magBits = expA | sigA.v64 | sigA.v0; - goto infArg; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! (sigA.v64 | sigA.v0) ) goto zero; - normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - if ( ! expB ) { - if ( ! (sigB.v64 | sigB.v0) ) goto zero; - normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA + expB - 0x4000; - sigA.v64 |= UINT64_C( 0x0001000000000000 ); - sigB = softfloat_shortShiftLeft128( sigB.v64, sigB.v0, 16 ); - softfloat_mul128To256M( sigA.v64, sigA.v0, sigB.v64, sigB.v0, sig256Z ); - sigZExtra = sig256Z[indexWord( 4, 1 )] | (sig256Z[indexWord( 4, 0 )] != 0); - sigZ = - softfloat_add128( - sig256Z[indexWord( 4, 3 )], sig256Z[indexWord( 4, 2 )], - sigA.v64, sigA.v0 - ); - if ( UINT64_C( 0x0002000000000000 ) <= sigZ.v64 ) { - ++expZ; - sig128Extra = - softfloat_shortShiftRightJam128Extra( - sigZ.v64, sigZ.v0, sigZExtra, 1 ); - sigZ = sig128Extra.v; - sigZExtra = sig128Extra.extra; - } - return - softfloat_roundPackToF128( signZ, expZ, sigZ.v64, sigZ.v0, sigZExtra ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infArg: - if ( ! magBits ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - goto uiZ; - } - uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 ); - goto uiZ0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ.v64 = packToF128UI64( signZ, 0, 0 ); - uiZ0: - uiZ.v0 = 0; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f128_mulAdd.c b/softfloat/source/f128_mulAdd.c deleted file mode 100644 index c7272d4..0000000 --- a/softfloat/source/f128_mulAdd.c +++ /dev/null @@ -1,63 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float128_t f128_mulAdd( float128_t a, float128_t b, float128_t c ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - union ui128_f128 uC; - uint_fast64_t uiC64, uiC0; - - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - uC.f = c; - uiC64 = uC.ui.v64; - uiC0 = uC.ui.v0; - return softfloat_mulAddF128( uiA64, uiA0, uiB64, uiB0, uiC64, uiC0, 0 ); - -} - diff --git a/softfloat/source/f128_rem.c b/softfloat/source/f128_rem.c deleted file mode 100644 index f525f69..0000000 --- a/softfloat/source/f128_rem.c +++ /dev/null @@ -1,190 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t f128_rem( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool signA; - int_fast32_t expA; - struct uint128 sigA; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - int_fast32_t expB; - struct uint128 sigB; - struct exp32_sig128 normExpSig; - struct uint128 rem; - int_fast32_t expDiff; - uint_fast32_t q, recip32; - uint_fast64_t q64; - struct uint128 term, altRem, meanRem; - bool signRem; - struct uint128 uiZ; - union ui128_f128 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - signA = signF128UI64( uiA64 ); - expA = expF128UI64( uiA64 ); - sigA.v64 = fracF128UI64( uiA64 ); - sigA.v0 = uiA0; - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - expB = expF128UI64( uiB64 ); - sigB.v64 = fracF128UI64( uiB64 ); - sigB.v0 = uiB0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FFF ) { - if ( - (sigA.v64 | sigA.v0) || ((expB == 0x7FFF) && (sigB.v64 | sigB.v0)) - ) { - goto propagateNaN; - } - goto invalid; - } - if ( expB == 0x7FFF ) { - if ( sigB.v64 | sigB.v0 ) goto propagateNaN; - return a; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) { - if ( ! (sigB.v64 | sigB.v0) ) goto invalid; - normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - if ( ! expA ) { - if ( ! (sigA.v64 | sigA.v0) ) return a; - normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sigA.v64 |= UINT64_C( 0x0001000000000000 ); - sigB.v64 |= UINT64_C( 0x0001000000000000 ); - rem = sigA; - expDiff = expA - expB; - if ( expDiff < 1 ) { - if ( expDiff < -1 ) return a; - if ( expDiff ) { - --expB; - sigB = softfloat_add128( sigB.v64, sigB.v0, sigB.v64, sigB.v0 ); - q = 0; - } else { - q = softfloat_le128( sigB.v64, sigB.v0, rem.v64, rem.v0 ); - if ( q ) { - rem = softfloat_sub128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); - } - } - } else { - recip32 = softfloat_approxRecip32_1( sigB.v64>>17 ); - expDiff -= 30; - for (;;) { - q64 = (uint_fast64_t) (uint32_t) (rem.v64>>19) * recip32; - if ( expDiff < 0 ) break; - q = (q64 + 0x80000000)>>32; - rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); - term = softfloat_mul128By32( sigB.v64, sigB.v0, q ); - rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - rem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); - } - expDiff -= 29; - } - /*-------------------------------------------------------------------- - | (`expDiff' cannot be less than -29 here.) - *--------------------------------------------------------------------*/ - q = (uint32_t) (q64>>32)>>(~expDiff & 31); - rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, expDiff + 30 ); - term = softfloat_mul128By32( sigB.v64, sigB.v0, q ); - rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - altRem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); - goto selectRem; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - do { - altRem = rem; - ++q; - rem = softfloat_sub128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); - } while ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ); - selectRem: - meanRem = softfloat_add128( rem.v64, rem.v0, altRem.v64, altRem.v0 ); - if ( - (meanRem.v64 & UINT64_C( 0x8000000000000000 )) - || (! (meanRem.v64 | meanRem.v0) && (q & 1)) - ) { - rem = altRem; - } - signRem = signA; - if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { - signRem = ! signRem; - rem = softfloat_sub128( 0, 0, rem.v64, rem.v0 ); - } - return softfloat_normRoundPackToF128( signRem, expB - 1, rem.v64, rem.v0 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f128_roundToInt.c b/softfloat/source/f128_roundToInt.c deleted file mode 100644 index 69185d6..0000000 --- a/softfloat/source/f128_roundToInt.c +++ /dev/null @@ -1,172 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t - f128_roundToInt( float128_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - int_fast32_t exp; - struct uint128 uiZ; - uint_fast64_t lastBitMask0, roundBitsMask; - bool roundNearEven; - uint_fast64_t lastBitMask64; - union ui128_f128 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - exp = expF128UI64( uiA64 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x402F <= exp ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( 0x406F <= exp ) { - if ( (exp == 0x7FFF) && (fracF128UI64( uiA64 ) | uiA0) ) { - uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, 0, 0 ); - goto uiZ; - } - return a; - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - lastBitMask0 = (uint_fast64_t) 2<<(0x406E - exp); - roundBitsMask = lastBitMask0 - 1; - uiZ.v64 = uiA64; - uiZ.v0 = uiA0; - roundNearEven = (roundingMode == softfloat_round_near_even); - if ( roundNearEven || (roundingMode == softfloat_round_near_maxMag) ) { - if ( exp == 0x402F ) { - if ( UINT64_C( 0x8000000000000000 ) <= uiZ.v0 ) { - ++uiZ.v64; - if ( - roundNearEven - && (uiZ.v0 == UINT64_C( 0x8000000000000000 )) - ) { - uiZ.v64 &= ~1; - } - } - } else { - uiZ = softfloat_add128( uiZ.v64, uiZ.v0, 0, lastBitMask0>>1 ); - if ( roundNearEven && !(uiZ.v0 & roundBitsMask) ) { - uiZ.v0 &= ~lastBitMask0; - } - } - } else if ( - roundingMode - == (signF128UI64( uiZ.v64 ) ? softfloat_round_min - : softfloat_round_max) - ) { - uiZ = softfloat_add128( uiZ.v64, uiZ.v0, 0, roundBitsMask ); - } - uiZ.v0 &= ~roundBitsMask; - lastBitMask64 = !lastBitMask0; - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( exp < 0x3FFF ) { - if ( !((uiA64 & UINT64_C( 0x7FFFFFFFFFFFFFFF )) | uiA0) ) return a; - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - uiZ.v64 = uiA64 & packToF128UI64( 1, 0, 0 ); - uiZ.v0 = 0; - switch ( roundingMode ) { - case softfloat_round_near_even: - if ( !(fracF128UI64( uiA64 ) | uiA0) ) break; - case softfloat_round_near_maxMag: - if ( exp == 0x3FFE ) uiZ.v64 |= packToF128UI64( 0, 0x3FFF, 0 ); - break; - case softfloat_round_min: - if ( uiZ.v64 ) uiZ.v64 = packToF128UI64( 1, 0x3FFF, 0 ); - break; - case softfloat_round_max: - if ( !uiZ.v64 ) uiZ.v64 = packToF128UI64( 0, 0x3FFF, 0 ); - break; -#ifdef SOFTFLOAT_ROUND_ODD - case softfloat_round_odd: - uiZ.v64 |= packToF128UI64( 0, 0x3FFF, 0 ); - break; -#endif - } - goto uiZ; - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - uiZ.v64 = uiA64; - uiZ.v0 = 0; - lastBitMask64 = (uint_fast64_t) 1<<(0x402F - exp); - roundBitsMask = lastBitMask64 - 1; - if ( roundingMode == softfloat_round_near_maxMag ) { - uiZ.v64 += lastBitMask64>>1; - } else if ( roundingMode == softfloat_round_near_even ) { - uiZ.v64 += lastBitMask64>>1; - if ( !((uiZ.v64 & roundBitsMask) | uiA0) ) { - uiZ.v64 &= ~lastBitMask64; - } - } else if ( - roundingMode - == (signF128UI64( uiZ.v64 ) ? softfloat_round_min - : softfloat_round_max) - ) { - uiZ.v64 = (uiZ.v64 | (uiA0 != 0)) + roundBitsMask; - } - uiZ.v64 &= ~roundBitsMask; - lastBitMask0 = 0; - } - if ( (uiZ.v64 != uiA64) || (uiZ.v0 != uiA0) ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - uiZ.v64 |= lastBitMask64; - uiZ.v0 |= lastBitMask0; - } -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f128_sqrt.c b/softfloat/source/f128_sqrt.c deleted file mode 100644 index f1d9bac..0000000 --- a/softfloat/source/f128_sqrt.c +++ /dev/null @@ -1,201 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t f128_sqrt( float128_t a ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool signA; - int_fast32_t expA; - struct uint128 sigA, uiZ; - struct exp32_sig128 normExpSig; - int_fast32_t expZ; - uint_fast32_t sig32A, recipSqrt32, sig32Z; - struct uint128 rem; - uint32_t qs[3]; - uint_fast32_t q; - uint_fast64_t x64, sig64Z; - struct uint128 y, term; - uint_fast64_t sigZExtra; - struct uint128 sigZ; - union ui128_f128 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - signA = signF128UI64( uiA64 ); - expA = expF128UI64( uiA64 ); - sigA.v64 = fracF128UI64( uiA64 ); - sigA.v0 = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FFF ) { - if ( sigA.v64 | sigA.v0 ) { - uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, 0, 0 ); - goto uiZ; - } - if ( ! signA ) return a; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( signA ) { - if ( ! (expA | sigA.v64 | sigA.v0) ) return a; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! (sigA.v64 | sigA.v0) ) return a; - normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - | (`sig32Z' is guaranteed to be a lower bound on the square root of - | `sig32A', which makes `sig32Z' also a lower bound on the square root of - | `sigA'.) - *------------------------------------------------------------------------*/ - expZ = ((expA - 0x3FFF)>>1) + 0x3FFE; - expA &= 1; - sigA.v64 |= UINT64_C( 0x0001000000000000 ); - sig32A = sigA.v64>>17; - recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A ); - sig32Z = ((uint_fast64_t) sig32A * recipSqrt32)>>32; - if ( expA ) { - sig32Z >>= 1; - rem = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 12 ); - } else { - rem = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 13 ); - } - qs[2] = sig32Z; - rem.v64 -= (uint_fast64_t) sig32Z * sig32Z; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q = ((uint32_t) (rem.v64>>2) * (uint_fast64_t) recipSqrt32)>>32; - x64 = (uint_fast64_t) sig32Z<<32; - sig64Z = x64 + ((uint_fast64_t) q<<3); - y = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); - /*------------------------------------------------------------------------ - | (Repeating this loop is a rare occurrence.) - *------------------------------------------------------------------------*/ - for (;;) { - term = softfloat_mul64ByShifted32To128( x64 + sig64Z, q ); - rem = softfloat_sub128( y.v64, y.v0, term.v64, term.v0 ); - if ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ) break; - --q; - sig64Z -= 1<<3; - } - qs[1] = q; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q = ((rem.v64>>2) * recipSqrt32)>>32; - y = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); - sig64Z <<= 1; - /*------------------------------------------------------------------------ - | (Repeating this loop is a rare occurrence.) - *------------------------------------------------------------------------*/ - for (;;) { - term = softfloat_shortShiftLeft128( 0, sig64Z, 32 ); - term = softfloat_add128( term.v64, term.v0, 0, (uint_fast64_t) q<<6 ); - term = softfloat_mul128By32( term.v64, term.v0, q ); - rem = softfloat_sub128( y.v64, y.v0, term.v64, term.v0 ); - if ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ) break; - --q; - } - qs[0] = q; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - q = (((rem.v64>>2) * recipSqrt32)>>32) + 2; - sigZExtra = (uint64_t) ((uint_fast64_t) q<<59); - term = softfloat_shortShiftLeft128( 0, qs[1], 53 ); - sigZ = - softfloat_add128( - (uint_fast64_t) qs[2]<<18, ((uint_fast64_t) qs[0]<<24) + (q>>5), - term.v64, term.v0 - ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (q & 0xF) <= 2 ) { - q &= ~3; - sigZExtra = (uint64_t) ((uint_fast64_t) q<<59); - y = softfloat_shortShiftLeft128( sigZ.v64, sigZ.v0, 6 ); - y.v0 |= sigZExtra>>58; - term = softfloat_sub128( y.v64, y.v0, 0, q ); - y = softfloat_mul64ByShifted32To128( term.v0, q ); - term = softfloat_mul64ByShifted32To128( term.v64, q ); - term = softfloat_add128( term.v64, term.v0, 0, y.v64 ); - rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 20 ); - term = softfloat_sub128( term.v64, term.v0, rem.v64, rem.v0 ); - /*-------------------------------------------------------------------- - | The concatenation of `term' and `y.v0' is now the negative remainder - | (3 words altogether). - *--------------------------------------------------------------------*/ - if ( term.v64 & UINT64_C( 0x8000000000000000 ) ) { - sigZExtra |= 1; - } else { - if ( term.v64 | term.v0 | y.v0 ) { - if ( sigZExtra ) { - --sigZExtra; - } else { - sigZ = softfloat_sub128( sigZ.v64, sigZ.v0, 0, 1 ); - sigZExtra = ~0; - } - } - } - } - return softfloat_roundPackToF128( 0, expZ, sigZ.v64, sigZ.v0, sigZExtra ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f128_sub.c b/softfloat/source/f128_sub.c deleted file mode 100644 index 5181cc5..0000000 --- a/softfloat/source/f128_sub.c +++ /dev/null @@ -1,78 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float128_t f128_sub( float128_t a, float128_t b ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool signA; - union ui128_f128 uB; - uint_fast64_t uiB64, uiB0; - bool signB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) - float128_t - (*magsFuncPtr)( - uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool ); -#endif - - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - signA = signF128UI64( uiA64 ); - uB.f = b; - uiB64 = uB.ui.v64; - uiB0 = uB.ui.v0; - signB = signF128UI64( uiB64 ); -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) - if ( signA == signB ) { - return softfloat_subMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); - } else { - return softfloat_addMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); - } -#else - magsFuncPtr = - (signA == signB) ? softfloat_subMagsF128 : softfloat_addMagsF128; - return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA ); -#endif - -} - diff --git a/softfloat/source/f128_to_extF80.c b/softfloat/source/f128_to_extF80.c deleted file mode 100644 index ec169c0..0000000 --- a/softfloat/source/f128_to_extF80.c +++ /dev/null @@ -1,109 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t f128_to_extF80( float128_t a ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t frac64, frac0; - struct commonNaN commonNaN; - struct uint128 uiZ; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0; - struct exp32_sig128 normExpSig; - struct uint128 sig128; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - sign = signF128UI64( uiA64 ); - exp = expF128UI64( uiA64 ); - frac64 = fracF128UI64( uiA64 ); - frac0 = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( frac64 | frac0 ) { - softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN ); - uiZ = softfloat_commonNaNToExtF80UI( &commonNaN ); - uiZ64 = uiZ.v64; - uiZ0 = uiZ.v0; - } else { - uiZ64 = packToExtF80UI64( sign, 0x7FFF ); - uiZ0 = UINT64_C( 0x8000000000000000 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! (frac64 | frac0) ) { - uiZ64 = packToExtF80UI64( sign, 0 ); - uiZ0 = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalF128Sig( frac64, frac0 ); - exp = normExpSig.exp; - frac64 = normExpSig.sig.v64; - frac0 = normExpSig.sig.v0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig128 = - softfloat_shortShiftLeft128( - frac64 | UINT64_C( 0x0001000000000000 ), frac0, 15 ); - return softfloat_roundPackToExtF80( sign, exp, sig128.v64, sig128.v0, 80 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/f128_to_f16.c b/softfloat/source/f128_to_f16.c deleted file mode 100644 index 5a8ee72..0000000 --- a/softfloat/source/f128_to_f16.c +++ /dev/null @@ -1,95 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float16_t f128_to_f16( float128_t a ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t frac64; - struct commonNaN commonNaN; - uint_fast16_t uiZ, frac16; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - sign = signF128UI64( uiA64 ); - exp = expF128UI64( uiA64 ); - frac64 = fracF128UI64( uiA64 ) | (uiA0 != 0); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( frac64 ) { - softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN ); - uiZ = softfloat_commonNaNToF16UI( &commonNaN ); - } else { - uiZ = packToF16UI( sign, 0x1F, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - frac16 = softfloat_shortShiftRightJam64( frac64, 34 ); - if ( ! (exp | frac16) ) { - uiZ = packToF16UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - exp -= 0x3FF1; - if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) { - if ( exp < -0x40 ) exp = -0x40; - } - return softfloat_roundPackToF16( sign, exp, frac16 | 0x4000 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f128_to_f32.c b/softfloat/source/f128_to_f32.c deleted file mode 100644 index 07e4a80..0000000 --- a/softfloat/source/f128_to_f32.c +++ /dev/null @@ -1,95 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t f128_to_f32( float128_t a ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t frac64; - struct commonNaN commonNaN; - uint_fast32_t uiZ, frac32; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - sign = signF128UI64( uiA64 ); - exp = expF128UI64( uiA64 ); - frac64 = fracF128UI64( uiA64 ) | (uiA0 != 0); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( frac64 ) { - softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN ); - uiZ = softfloat_commonNaNToF32UI( &commonNaN ); - } else { - uiZ = packToF32UI( sign, 0xFF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - frac32 = softfloat_shortShiftRightJam64( frac64, 18 ); - if ( ! (exp | frac32) ) { - uiZ = packToF32UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - exp -= 0x3F81; - if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) { - if ( exp < -0x1000 ) exp = -0x1000; - } - return softfloat_roundPackToF32( sign, exp, frac32 | 0x40000000 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f128_to_f64.c b/softfloat/source/f128_to_f64.c deleted file mode 100644 index f791938..0000000 --- a/softfloat/source/f128_to_f64.c +++ /dev/null @@ -1,100 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float64_t f128_to_f64( float128_t a ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t frac64, frac0; - struct commonNaN commonNaN; - uint_fast64_t uiZ; - struct uint128 frac128; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - sign = signF128UI64( uiA64 ); - exp = expF128UI64( uiA64 ); - frac64 = fracF128UI64( uiA64 ); - frac0 = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FFF ) { - if ( frac64 | frac0 ) { - softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN ); - uiZ = softfloat_commonNaNToF64UI( &commonNaN ); - } else { - uiZ = packToF64UI( sign, 0x7FF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - frac128 = softfloat_shortShiftLeft128( frac64, frac0, 14 ); - frac64 = frac128.v64 | (frac128.v0 != 0); - if ( ! (exp | frac64) ) { - uiZ = packToF64UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - exp -= 0x3C01; - if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) { - if ( exp < -0x1000 ) exp = -0x1000; - } - return - softfloat_roundPackToF64( - sign, exp, frac64 | UINT64_C( 0x4000000000000000 ) ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f128_to_i32.c b/softfloat/source/f128_to_i32.c deleted file mode 100644 index 16c4a3c..0000000 --- a/softfloat/source/f128_to_i32.c +++ /dev/null @@ -1,85 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t f128_to_i32( float128_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t sig64, sig0; - int_fast32_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - sign = signF128UI64( uiA64 ); - exp = expF128UI64( uiA64 ); - sig64 = fracF128UI64( uiA64 ); - sig0 = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ -#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow) - if ( (exp == 0x7FFF) && (sig64 | sig0) ) { -#if (i32_fromNaN == i32_fromPosOverflow) - sign = 0; -#elif (i32_fromNaN == i32_fromNegOverflow) - sign = 1; -#else - softfloat_raiseFlags( softfloat_flag_invalid ); - return i32_fromNaN; -#endif - } -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 ); - sig64 |= (sig0 != 0); - shiftDist = 0x4023 - exp; - if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist ); - return softfloat_roundToI32( sign, sig64, roundingMode, exact ); - -} - diff --git a/softfloat/source/f128_to_i32_r_minMag.c b/softfloat/source/f128_to_i32_r_minMag.c deleted file mode 100644 index 18cfeae..0000000 --- a/softfloat/source/f128_to_i32_r_minMag.c +++ /dev/null @@ -1,100 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t f128_to_i32_r_minMag( float128_t a, bool exact ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - int_fast32_t exp; - uint_fast64_t sig64; - int_fast32_t shiftDist; - bool sign; - int_fast32_t absZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - exp = expF128UI64( uiA64 ); - sig64 = fracF128UI64( uiA64 ) | (uiA0 != 0); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x402F - exp; - if ( 49 <= shiftDist ) { - if ( exact && (exp | sig64) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF128UI64( uiA64 ); - if ( shiftDist < 18 ) { - if ( - sign && (shiftDist == 17) - && (sig64 < UINT64_C( 0x0000000000020000 )) - ) { - if ( exact && sig64 ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return -0x7FFFFFFF - 1; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && sig64 ? i32_fromNaN - : sign ? i32_fromNegOverflow : i32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig64 |= UINT64_C( 0x0001000000000000 ); - absZ = sig64>>shiftDist; - if ( - exact && ((uint_fast64_t) (uint_fast32_t) absZ< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t f128_to_i64( float128_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t sig64, sig0; - int_fast32_t shiftDist; - struct uint128 sig128; - struct uint64_extra sigExtra; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - sign = signF128UI64( uiA64 ); - exp = expF128UI64( uiA64 ); - sig64 = fracF128UI64( uiA64 ); - sig0 = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x402F - exp; - if ( shiftDist <= 0 ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( shiftDist < -15 ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig64 | sig0) ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sig64 |= UINT64_C( 0x0001000000000000 ); - if ( shiftDist ) { - sig128 = softfloat_shortShiftLeft128( sig64, sig0, -shiftDist ); - sig64 = sig128.v64; - sig0 = sig128.v0; - } - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 ); - sigExtra = softfloat_shiftRightJam64Extra( sig64, sig0, shiftDist ); - sig64 = sigExtra.v; - sig0 = sigExtra.extra; - } - return softfloat_roundToI64( sign, sig64, sig0, roundingMode, exact ); - -} - diff --git a/softfloat/source/f128_to_i64_r_minMag.c b/softfloat/source/f128_to_i64_r_minMag.c deleted file mode 100644 index e2cc62e..0000000 --- a/softfloat/source/f128_to_i64_r_minMag.c +++ /dev/null @@ -1,113 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t f128_to_i64_r_minMag( float128_t a, bool exact ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t sig64, sig0; - int_fast32_t shiftDist; - int_fast8_t negShiftDist; - int_fast64_t absZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - sign = signF128UI64( uiA64 ); - exp = expF128UI64( uiA64 ); - sig64 = fracF128UI64( uiA64 ); - sig0 = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x402F - exp; - if ( shiftDist < 0 ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( shiftDist < -14 ) { - if ( - (uiA64 == UINT64_C( 0xC03E000000000000 )) - && (sig0 < UINT64_C( 0x0002000000000000 )) - ) { - if ( exact && sig0 ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig64 | sig0) ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sig64 |= UINT64_C( 0x0001000000000000 ); - negShiftDist = -shiftDist; - absZ = sig64<>(shiftDist & 63); - if ( exact && (uint64_t) (sig0<>shiftDist; - if ( exact && (sig0 || (absZ< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t - f128_to_ui32( float128_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t sig64; - int_fast32_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - sign = signF128UI64( uiA64 ); - exp = expF128UI64( uiA64 ); - sig64 = fracF128UI64( uiA64 ) | (uiA0 != 0); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ -#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow) - if ( (exp == 0x7FFF) && sig64 ) { -#if (ui32_fromNaN == ui32_fromPosOverflow) - sign = 0; -#elif (ui32_fromNaN == ui32_fromNegOverflow) - sign = 1; -#else - softfloat_raiseFlags( softfloat_flag_invalid ); - return ui32_fromNaN; -#endif - } -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 ); - shiftDist = 0x4023 - exp; - if ( 0 < shiftDist ) { - sig64 = softfloat_shiftRightJam64( sig64, shiftDist ); - } - return softfloat_roundToUI32( sign, sig64, roundingMode, exact ); - -} - diff --git a/softfloat/source/f128_to_ui32_r_minMag.c b/softfloat/source/f128_to_ui32_r_minMag.c deleted file mode 100644 index 92facd5..0000000 --- a/softfloat/source/f128_to_ui32_r_minMag.c +++ /dev/null @@ -1,89 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t f128_to_ui32_r_minMag( float128_t a, bool exact ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - int_fast32_t exp; - uint_fast64_t sig64; - int_fast32_t shiftDist; - bool sign; - uint_fast32_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - exp = expF128UI64( uiA64 ); - sig64 = fracF128UI64( uiA64 ) | (uiA0 != 0); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x402F - exp; - if ( 49 <= shiftDist ) { - if ( exact && (exp | sig64) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF128UI64( uiA64 ); - if ( sign || (shiftDist < 17) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && sig64 ? ui32_fromNaN - : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig64 |= UINT64_C( 0x0001000000000000 ); - z = sig64>>shiftDist; - if ( exact && ((uint_fast64_t) z< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t - f128_to_ui64( float128_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t sig64, sig0; - int_fast32_t shiftDist; - struct uint128 sig128; - struct uint64_extra sigExtra; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - sign = signF128UI64( uiA64 ); - exp = expF128UI64( uiA64 ); - sig64 = fracF128UI64( uiA64 ); - sig0 = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x402F - exp; - if ( shiftDist <= 0 ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( shiftDist < -15 ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FFF) && (sig64 | sig0) ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sig64 |= UINT64_C( 0x0001000000000000 ); - if ( shiftDist ) { - sig128 = softfloat_shortShiftLeft128( sig64, sig0, -shiftDist ); - sig64 = sig128.v64; - sig0 = sig128.v0; - } - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 ); - sigExtra = softfloat_shiftRightJam64Extra( sig64, sig0, shiftDist ); - sig64 = sigExtra.v; - sig0 = sigExtra.extra; - } - return softfloat_roundToUI64( sign, sig64, sig0, roundingMode, exact ); - -} - diff --git a/softfloat/source/f128_to_ui64_r_minMag.c b/softfloat/source/f128_to_ui64_r_minMag.c deleted file mode 100644 index edeafd3..0000000 --- a/softfloat/source/f128_to_ui64_r_minMag.c +++ /dev/null @@ -1,105 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t f128_to_ui64_r_minMag( float128_t a, bool exact ) -{ - union ui128_f128 uA; - uint_fast64_t uiA64, uiA0; - bool sign; - int_fast32_t exp; - uint_fast64_t sig64, sig0; - int_fast32_t shiftDist; - int_fast8_t negShiftDist; - uint_fast64_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA64 = uA.ui.v64; - uiA0 = uA.ui.v0; - sign = signF128UI64( uiA64 ); - exp = expF128UI64( uiA64 ); - sig64 = fracF128UI64( uiA64 ); - sig0 = uiA0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x402F - exp; - if ( shiftDist < 0 ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( sign || (shiftDist < -15) ) goto invalid; - sig64 |= UINT64_C( 0x0001000000000000 ); - negShiftDist = -shiftDist; - z = sig64<>(shiftDist & 63); - if ( exact && (uint64_t) (sig0<>shiftDist; - if ( exact && (sig0 || (z< -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float16_t f16_add( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - union ui16_f16 uB; - uint_fast16_t uiB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1) - float16_t (*magsFuncPtr)( uint_fast16_t, uint_fast16_t ); -#endif - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; -#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) - if ( signF16UI( uiA ^ uiB ) ) { - return softfloat_subMagsF16( uiA, uiB ); - } else { - return softfloat_addMagsF16( uiA, uiB ); - } -#else - magsFuncPtr = - signF16UI( uiA ^ uiB ) ? softfloat_subMagsF16 : softfloat_addMagsF16; - return (*magsFuncPtr)( uiA, uiB ); -#endif - -} - diff --git a/softfloat/source/f16_div.c b/softfloat/source/f16_div.c deleted file mode 100644 index 77f9a2c..0000000 --- a/softfloat/source/f16_div.c +++ /dev/null @@ -1,186 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extern const uint16_t softfloat_approxRecip_1k0s[]; -extern const uint16_t softfloat_approxRecip_1k1s[]; - -float16_t f16_div( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool signA; - int_fast8_t expA; - uint_fast16_t sigA; - union ui16_f16 uB; - uint_fast16_t uiB; - bool signB; - int_fast8_t expB; - uint_fast16_t sigB; - bool signZ; - struct exp8_sig16 normExpSig; - int_fast8_t expZ; -#ifdef SOFTFLOAT_FAST_DIV32TO16 - uint_fast32_t sig32A; - uint_fast16_t sigZ; -#else - int index; - uint16_t r0; - uint_fast16_t sigZ, rem; -#endif - uint_fast16_t uiZ; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF16UI( uiA ); - expA = expF16UI( uiA ); - sigA = fracF16UI( uiA ); - uB.f = b; - uiB = uB.ui; - signB = signF16UI( uiB ); - expB = expF16UI( uiB ); - sigB = fracF16UI( uiB ); - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x1F ) { - if ( sigA ) goto propagateNaN; - if ( expB == 0x1F ) { - if ( sigB ) goto propagateNaN; - goto invalid; - } - goto infinity; - } - if ( expB == 0x1F ) { - if ( sigB ) goto propagateNaN; - goto zero; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) { - if ( ! sigB ) { - if ( ! (expA | sigA) ) goto invalid; - softfloat_raiseFlags( softfloat_flag_infinite ); - goto infinity; - } - normExpSig = softfloat_normSubnormalF16Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - if ( ! expA ) { - if ( ! sigA ) goto zero; - normExpSig = softfloat_normSubnormalF16Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA - expB + 0xE; - sigA |= 0x0400; - sigB |= 0x0400; -#ifdef SOFTFLOAT_FAST_DIV32TO16 - if ( sigA < sigB ) { - --expZ; - sig32A = (uint_fast32_t) sigA<<15; - } else { - sig32A = (uint_fast32_t) sigA<<14; - } - sigZ = sig32A / sigB; - if ( ! (sigZ & 7) ) sigZ |= ((uint_fast32_t) sigB * sigZ != sig32A); -#else - if ( sigA < sigB ) { - --expZ; - sigA <<= 5; - } else { - sigA <<= 4; - } - index = sigB>>6 & 0xF; - r0 = softfloat_approxRecip_1k0s[index] - - (((uint_fast32_t) softfloat_approxRecip_1k1s[index] - * (sigB & 0x3F)) - >>10); - sigZ = ((uint_fast32_t) sigA * r0)>>16; - rem = (sigA<<10) - sigZ * sigB; - sigZ += (rem * (uint_fast32_t) r0)>>26; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - ++sigZ; - if ( ! (sigZ & 7) ) { - sigZ &= ~1; - rem = (sigA<<10) - sigZ * sigB; - if ( rem & 0x8000 ) { - sigZ -= 2; - } else { - if ( rem ) sigZ |= 1; - } - } -#endif - return softfloat_roundPackToF16( signZ, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF16UI; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infinity: - uiZ = packToF16UI( signZ, 0x1F, 0 ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ = packToF16UI( signZ, 0, 0 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f16_eq.c b/softfloat/source/f16_eq.c deleted file mode 100644 index 692fa03..0000000 --- a/softfloat/source/f16_eq.c +++ /dev/null @@ -1,66 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f16_eq( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - union ui16_f16 uB; - uint_fast16_t uiB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { - if ( - softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - return (uiA == uiB) || ! (uint16_t) ((uiA | uiB)<<1); - -} - diff --git a/softfloat/source/f16_eq_signaling.c b/softfloat/source/f16_eq_signaling.c deleted file mode 100644 index c1e7a50..0000000 --- a/softfloat/source/f16_eq_signaling.c +++ /dev/null @@ -1,61 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f16_eq_signaling( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - union ui16_f16 uB; - uint_fast16_t uiB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - return (uiA == uiB) || ! (uint16_t) ((uiA | uiB)<<1); - -} - diff --git a/softfloat/source/f16_isSignalingNaN.c b/softfloat/source/f16_isSignalingNaN.c deleted file mode 100644 index 3eb3d4c..0000000 --- a/softfloat/source/f16_isSignalingNaN.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f16_isSignalingNaN( float16_t a ) -{ - union ui16_f16 uA; - - uA.f = a; - return softfloat_isSigNaNF16UI( uA.ui ); - -} - diff --git a/softfloat/source/f16_le.c b/softfloat/source/f16_le.c deleted file mode 100644 index d7313de..0000000 --- a/softfloat/source/f16_le.c +++ /dev/null @@ -1,66 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f16_le( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - union ui16_f16 uB; - uint_fast16_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - signA = signF16UI( uiA ); - signB = signF16UI( uiB ); - return - (signA != signB) ? signA || ! (uint16_t) ((uiA | uiB)<<1) - : (uiA == uiB) || (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f16_le_quiet.c b/softfloat/source/f16_le_quiet.c deleted file mode 100644 index 15181c2..0000000 --- a/softfloat/source/f16_le_quiet.c +++ /dev/null @@ -1,71 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f16_le_quiet( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - union ui16_f16 uB; - uint_fast16_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { - if ( - softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - signA = signF16UI( uiA ); - signB = signF16UI( uiB ); - return - (signA != signB) ? signA || ! (uint16_t) ((uiA | uiB)<<1) - : (uiA == uiB) || (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f16_lt.c b/softfloat/source/f16_lt.c deleted file mode 100644 index 7745699..0000000 --- a/softfloat/source/f16_lt.c +++ /dev/null @@ -1,66 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f16_lt( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - union ui16_f16 uB; - uint_fast16_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - signA = signF16UI( uiA ); - signB = signF16UI( uiB ); - return - (signA != signB) ? signA && ((uint16_t) ((uiA | uiB)<<1) != 0) - : (uiA != uiB) && (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f16_lt_quiet.c b/softfloat/source/f16_lt_quiet.c deleted file mode 100644 index a31e4a1..0000000 --- a/softfloat/source/f16_lt_quiet.c +++ /dev/null @@ -1,71 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f16_lt_quiet( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - union ui16_f16 uB; - uint_fast16_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { - if ( - softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - signA = signF16UI( uiA ); - signB = signF16UI( uiB ); - return - (signA != signB) ? signA && ((uint16_t) ((uiA | uiB)<<1) != 0) - : (uiA != uiB) && (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f16_mul.c b/softfloat/source/f16_mul.c deleted file mode 100644 index a47cab8..0000000 --- a/softfloat/source/f16_mul.c +++ /dev/null @@ -1,140 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float16_t f16_mul( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool signA; - int_fast8_t expA; - uint_fast16_t sigA; - union ui16_f16 uB; - uint_fast16_t uiB; - bool signB; - int_fast8_t expB; - uint_fast16_t sigB; - bool signZ; - uint_fast16_t magBits; - struct exp8_sig16 normExpSig; - int_fast8_t expZ; - uint_fast32_t sig32Z; - uint_fast16_t sigZ, uiZ; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF16UI( uiA ); - expA = expF16UI( uiA ); - sigA = fracF16UI( uiA ); - uB.f = b; - uiB = uB.ui; - signB = signF16UI( uiB ); - expB = expF16UI( uiB ); - sigB = fracF16UI( uiB ); - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x1F ) { - if ( sigA || ((expB == 0x1F) && sigB) ) goto propagateNaN; - magBits = expB | sigB; - goto infArg; - } - if ( expB == 0x1F ) { - if ( sigB ) goto propagateNaN; - magBits = expA | sigA; - goto infArg; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! sigA ) goto zero; - normExpSig = softfloat_normSubnormalF16Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - if ( ! expB ) { - if ( ! sigB ) goto zero; - normExpSig = softfloat_normSubnormalF16Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA + expB - 0xF; - sigA = (sigA | 0x0400)<<4; - sigB = (sigB | 0x0400)<<5; - sig32Z = (uint_fast32_t) sigA * sigB; - sigZ = sig32Z>>16; - if ( sig32Z & 0xFFFF ) sigZ |= 1; - if ( sigZ < 0x4000 ) { - --expZ; - sigZ <<= 1; - } - return softfloat_roundPackToF16( signZ, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infArg: - if ( ! magBits ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF16UI; - } else { - uiZ = packToF16UI( signZ, 0x1F, 0 ); - } - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ = packToF16UI( signZ, 0, 0 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f16_mulAdd.c b/softfloat/source/f16_mulAdd.c deleted file mode 100644 index e97571a..0000000 --- a/softfloat/source/f16_mulAdd.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float16_t f16_mulAdd( float16_t a, float16_t b, float16_t c ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - union ui16_f16 uB; - uint_fast16_t uiB; - union ui16_f16 uC; - uint_fast16_t uiC; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - uC.f = c; - uiC = uC.ui; - return softfloat_mulAddF16( uiA, uiB, uiC, 0 ); - -} - diff --git a/softfloat/source/f16_rem.c b/softfloat/source/f16_rem.c deleted file mode 100644 index 0ffa498..0000000 --- a/softfloat/source/f16_rem.c +++ /dev/null @@ -1,171 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float16_t f16_rem( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool signA; - int_fast8_t expA; - uint_fast16_t sigA; - union ui16_f16 uB; - uint_fast16_t uiB; - int_fast8_t expB; - uint_fast16_t sigB; - struct exp8_sig16 normExpSig; - uint16_t rem; - int_fast8_t expDiff; - uint_fast16_t q; - uint32_t recip32, q32; - uint16_t altRem, meanRem; - bool signRem; - uint_fast16_t uiZ; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF16UI( uiA ); - expA = expF16UI( uiA ); - sigA = fracF16UI( uiA ); - uB.f = b; - uiB = uB.ui; - expB = expF16UI( uiB ); - sigB = fracF16UI( uiB ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x1F ) { - if ( sigA || ((expB == 0x1F) && sigB) ) goto propagateNaN; - goto invalid; - } - if ( expB == 0x1F ) { - if ( sigB ) goto propagateNaN; - return a; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) { - if ( ! sigB ) goto invalid; - normExpSig = softfloat_normSubnormalF16Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - if ( ! expA ) { - if ( ! sigA ) return a; - normExpSig = softfloat_normSubnormalF16Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - rem = sigA | 0x0400; - sigB |= 0x0400; - expDiff = expA - expB; - if ( expDiff < 1 ) { - if ( expDiff < -1 ) return a; - sigB <<= 3; - if ( expDiff ) { - rem <<= 2; - q = 0; - } else { - rem <<= 3; - q = (sigB <= rem); - if ( q ) rem -= sigB; - } - } else { - recip32 = softfloat_approxRecip32_1( (uint_fast32_t) sigB<<21 ); - /*-------------------------------------------------------------------- - | Changing the shift of `rem' here requires also changing the initial - | subtraction from `expDiff'. - *--------------------------------------------------------------------*/ - rem <<= 4; - expDiff -= 31; - /*-------------------------------------------------------------------- - | The scale of `sigB' affects how many bits are obtained during each - | cycle of the loop. Currently this is 29 bits per loop iteration, - | which is believed to be the maximum possible. - *--------------------------------------------------------------------*/ - sigB <<= 3; - for (;;) { - q32 = (rem * (uint_fast64_t) recip32)>>16; - if ( expDiff < 0 ) break; - rem = -((uint_fast16_t) q32 * sigB); - expDiff -= 29; - } - /*-------------------------------------------------------------------- - | (`expDiff' cannot be less than -30 here.) - *--------------------------------------------------------------------*/ - q32 >>= ~expDiff & 31; - q = q32; - rem = (rem<<(expDiff + 30)) - q * sigB; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - do { - altRem = rem; - ++q; - rem -= sigB; - } while ( ! (rem & 0x8000) ); - meanRem = rem + altRem; - if ( (meanRem & 0x8000) || (! meanRem && (q & 1)) ) rem = altRem; - signRem = signA; - if ( 0x8000 <= rem ) { - signRem = ! signRem; - rem = -rem; - } - return softfloat_normRoundPackToF16( signRem, expB, rem ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); - goto uiZ; - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF16UI; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f16_roundToInt.c b/softfloat/source/f16_roundToInt.c deleted file mode 100644 index a567d51..0000000 --- a/softfloat/source/f16_roundToInt.c +++ /dev/null @@ -1,120 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float16_t f16_roundToInt( float16_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - int_fast8_t exp; - uint_fast16_t uiZ, lastBitMask, roundBitsMask; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp <= 0xE ) { - if ( !(uint16_t) (uiA<<1) ) return a; - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - uiZ = uiA & packToF16UI( 1, 0, 0 ); - switch ( roundingMode ) { - case softfloat_round_near_even: - if ( !fracF16UI( uiA ) ) break; - case softfloat_round_near_maxMag: - if ( exp == 0xE ) uiZ |= packToF16UI( 0, 0xF, 0 ); - break; - case softfloat_round_min: - if ( uiZ ) uiZ = packToF16UI( 1, 0xF, 0 ); - break; - case softfloat_round_max: - if ( !uiZ ) uiZ = packToF16UI( 0, 0xF, 0 ); - break; -#ifdef SOFTFLOAT_ROUND_ODD - case softfloat_round_odd: - uiZ |= packToF16UI( 0, 0xF, 0 ); - break; -#endif - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x19 <= exp ) { - if ( (exp == 0x1F) && fracF16UI( uiA ) ) { - uiZ = softfloat_propagateNaNF16UI( uiA, 0 ); - goto uiZ; - } - return a; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ = uiA; - lastBitMask = (uint_fast16_t) 1<<(0x19 - exp); - roundBitsMask = lastBitMask - 1; - if ( roundingMode == softfloat_round_near_maxMag ) { - uiZ += lastBitMask>>1; - } else if ( roundingMode == softfloat_round_near_even ) { - uiZ += lastBitMask>>1; - if ( !(uiZ & roundBitsMask) ) uiZ &= ~lastBitMask; - } else if ( - roundingMode - == (signF16UI( uiZ ) ? softfloat_round_min : softfloat_round_max) - ) { - uiZ += roundBitsMask; - } - uiZ &= ~roundBitsMask; - if ( uiZ != uiA ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) uiZ |= lastBitMask; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f16_sqrt.c b/softfloat/source/f16_sqrt.c deleted file mode 100644 index 47a3bbf..0000000 --- a/softfloat/source/f16_sqrt.c +++ /dev/null @@ -1,136 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extern const uint16_t softfloat_approxRecipSqrt_1k0s[]; -extern const uint16_t softfloat_approxRecipSqrt_1k1s[]; - -float16_t f16_sqrt( float16_t a ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool signA; - int_fast8_t expA; - uint_fast16_t sigA, uiZ; - struct exp8_sig16 normExpSig; - int_fast8_t expZ; - int index; - uint_fast16_t r0; - uint_fast32_t ESqrR0; - uint16_t sigma0; - uint_fast16_t recipSqrt16, sigZ, shiftedSigZ; - uint16_t negRem; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF16UI( uiA ); - expA = expF16UI( uiA ); - sigA = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x1F ) { - if ( sigA ) { - uiZ = softfloat_propagateNaNF16UI( uiA, 0 ); - goto uiZ; - } - if ( ! signA ) return a; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( signA ) { - if ( ! (expA | sigA) ) return a; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! sigA ) return a; - normExpSig = softfloat_normSubnormalF16Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = ((expA - 0xF)>>1) + 0xE; - expA &= 1; - sigA |= 0x0400; - index = (sigA>>6 & 0xE) + expA; - r0 = softfloat_approxRecipSqrt_1k0s[index] - - (((uint_fast32_t) softfloat_approxRecipSqrt_1k1s[index] - * (sigA & 0x7F)) - >>11); - ESqrR0 = ((uint_fast32_t) r0 * r0)>>1; - if ( expA ) ESqrR0 >>= 1; - sigma0 = ~(uint_fast16_t) ((ESqrR0 * sigA)>>16); - recipSqrt16 = r0 + (((uint_fast32_t) r0 * sigma0)>>25); - if ( ! (recipSqrt16 & 0x8000) ) recipSqrt16 = 0x8000; - sigZ = ((uint_fast32_t) (sigA<<5) * recipSqrt16)>>16; - if ( expA ) sigZ >>= 1; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - ++sigZ; - if ( ! (sigZ & 7) ) { - shiftedSigZ = sigZ>>1; - negRem = shiftedSigZ * shiftedSigZ; - sigZ &= ~1; - if ( negRem & 0x8000 ) { - sigZ |= 1; - } else { - if ( negRem ) --sigZ; - } - } - return softfloat_roundPackToF16( 0, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF16UI; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f16_sub.c b/softfloat/source/f16_sub.c deleted file mode 100644 index 03a87cf..0000000 --- a/softfloat/source/f16_sub.c +++ /dev/null @@ -1,70 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float16_t f16_sub( float16_t a, float16_t b ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - union ui16_f16 uB; - uint_fast16_t uiB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1) - float16_t (*magsFuncPtr)( uint_fast16_t, uint_fast16_t ); -#endif - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; -#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) - if ( signF16UI( uiA ^ uiB ) ) { - return softfloat_addMagsF16( uiA, uiB ); - } else { - return softfloat_subMagsF16( uiA, uiB ); - } -#else - magsFuncPtr = - signF16UI( uiA ^ uiB ) ? softfloat_addMagsF16 : softfloat_subMagsF16; - return (*magsFuncPtr)( uiA, uiB ); -#endif - -} - diff --git a/softfloat/source/f16_to_extF80.c b/softfloat/source/f16_to_extF80.c deleted file mode 100644 index 99c2dfc..0000000 --- a/softfloat/source/f16_to_extF80.c +++ /dev/null @@ -1,101 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t f16_to_extF80( float16_t a ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool sign; - int_fast8_t exp; - uint_fast16_t frac; - struct commonNaN commonNaN; - struct uint128 uiZ; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0; - struct exp8_sig16 normExpSig; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF16UI( uiA ); - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x1F ) { - if ( frac ) { - softfloat_f16UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToExtF80UI( &commonNaN ); - uiZ64 = uiZ.v64; - uiZ0 = uiZ.v0; - } else { - uiZ64 = packToExtF80UI64( sign, 0x7FFF ); - uiZ0 = UINT64_C( 0x8000000000000000 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ64 = packToExtF80UI64( sign, 0 ); - uiZ0 = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalF16Sig( frac ); - exp = normExpSig.exp; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ64 = packToExtF80UI64( sign, exp + 0x3FF0 ); - uiZ0 = (uint_fast64_t) (frac | 0x0400)<<53; - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/f16_to_extF80M.c b/softfloat/source/f16_to_extF80M.c deleted file mode 100644 index 7f2d534..0000000 --- a/softfloat/source/f16_to_extF80M.c +++ /dev/null @@ -1,111 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void f16_to_extF80M( float16_t a, extFloat80_t *zPtr ) -{ - - *zPtr = f16_to_extF80( a ); - -} - -#else - -void f16_to_extF80M( float16_t a, extFloat80_t *zPtr ) -{ - struct extFloat80M *zSPtr; - union ui16_f16 uA; - uint16_t uiA; - bool sign; - int_fast8_t exp; - uint16_t frac; - struct commonNaN commonNaN; - uint_fast16_t uiZ64; - uint32_t uiZ32; - struct exp8_sig16 normExpSig; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zSPtr = (struct extFloat80M *) zPtr; - uA.f = a; - uiA = uA.ui; - sign = signF16UI( uiA ); - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x1F ) { - if ( frac ) { - softfloat_f16UIToCommonNaN( uiA, &commonNaN ); - softfloat_commonNaNToExtF80M( &commonNaN, zSPtr ); - return; - } - uiZ64 = packToExtF80UI64( sign, 0x7FFF ); - uiZ32 = 0x80000000; - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ64 = packToExtF80UI64( sign, 0 ); - uiZ32 = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalF16Sig( frac ); - exp = normExpSig.exp; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ64 = packToExtF80UI64( sign, exp + 0x3FF0 ); - uiZ32 = 0x80000000 | (uint32_t) frac<<21; - uiZ: - zSPtr->signExp = uiZ64; - zSPtr->signif = (uint64_t) uiZ32<<32; - -} - -#endif - diff --git a/softfloat/source/f16_to_f128.c b/softfloat/source/f16_to_f128.c deleted file mode 100644 index c4b81dc..0000000 --- a/softfloat/source/f16_to_f128.c +++ /dev/null @@ -1,96 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t f16_to_f128( float16_t a ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool sign; - int_fast8_t exp; - uint_fast16_t frac; - struct commonNaN commonNaN; - struct uint128 uiZ; - struct exp8_sig16 normExpSig; - union ui128_f128 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF16UI( uiA ); - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x1F ) { - if ( frac ) { - softfloat_f16UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToF128UI( &commonNaN ); - } else { - uiZ.v64 = packToF128UI64( sign, 0x7FFF, 0 ); - uiZ.v0 = 0; - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ.v64 = packToF128UI64( sign, 0, 0 ); - uiZ.v0 = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalF16Sig( frac ); - exp = normExpSig.exp - 1; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ.v64 = packToF128UI64( sign, exp + 0x3FF0, (uint_fast64_t) frac<<38 ); - uiZ.v0 = 0; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f16_to_f128M.c b/softfloat/source/f16_to_f128M.c deleted file mode 100644 index b4fc873..0000000 --- a/softfloat/source/f16_to_f128M.c +++ /dev/null @@ -1,111 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void f16_to_f128M( float16_t a, float128_t *zPtr ) -{ - - *zPtr = f16_to_f128( a ); - -} - -#else - -void f16_to_f128M( float16_t a, float128_t *zPtr ) -{ - uint32_t *zWPtr; - union ui16_f16 uA; - uint16_t uiA; - bool sign; - int_fast8_t exp; - uint16_t frac; - struct commonNaN commonNaN; - uint32_t uiZ96; - struct exp8_sig16 normExpSig; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zWPtr = (uint32_t *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF16UI( uiA ); - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x1F ) { - if ( frac ) { - softfloat_f16UIToCommonNaN( uiA, &commonNaN ); - softfloat_commonNaNToF128M( &commonNaN, zWPtr ); - return; - } - uiZ96 = packToF128UI96( sign, 0x7FFF, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ96 = packToF128UI96( sign, 0, 0 ); - goto uiZ; - } - normExpSig = softfloat_normSubnormalF16Sig( frac ); - exp = normExpSig.exp - 1; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ96 = packToF128UI96( sign, exp + 0x3FF0, (uint32_t) frac<<6 ); - uiZ: - zWPtr[indexWord( 4, 3 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = 0; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - -} - -#endif - diff --git a/softfloat/source/f16_to_f32.c b/softfloat/source/f16_to_f32.c deleted file mode 100644 index a219454..0000000 --- a/softfloat/source/f16_to_f32.c +++ /dev/null @@ -1,93 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t f16_to_f32( float16_t a ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool sign; - int_fast8_t exp; - uint_fast16_t frac; - struct commonNaN commonNaN; - uint_fast32_t uiZ; - struct exp8_sig16 normExpSig; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF16UI( uiA ); - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x1F ) { - if ( frac ) { - softfloat_f16UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToF32UI( &commonNaN ); - } else { - uiZ = packToF32UI( sign, 0xFF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ = packToF32UI( sign, 0, 0 ); - goto uiZ; - } - normExpSig = softfloat_normSubnormalF16Sig( frac ); - exp = normExpSig.exp - 1; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ = packToF32UI( sign, exp + 0x70, (uint_fast32_t) frac<<13 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f16_to_f64.c b/softfloat/source/f16_to_f64.c deleted file mode 100644 index 7e87c25..0000000 --- a/softfloat/source/f16_to_f64.c +++ /dev/null @@ -1,93 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float64_t f16_to_f64( float16_t a ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool sign; - int_fast8_t exp; - uint_fast16_t frac; - struct commonNaN commonNaN; - uint_fast64_t uiZ; - struct exp8_sig16 normExpSig; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF16UI( uiA ); - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x1F ) { - if ( frac ) { - softfloat_f16UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToF64UI( &commonNaN ); - } else { - uiZ = packToF64UI( sign, 0x7FF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ = packToF64UI( sign, 0, 0 ); - goto uiZ; - } - normExpSig = softfloat_normSubnormalF16Sig( frac ); - exp = normExpSig.exp - 1; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ = packToF64UI( sign, exp + 0x3F0, (uint_fast64_t) frac<<42 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f16_to_i32.c b/softfloat/source/f16_to_i32.c deleted file mode 100644 index 805c4e5..0000000 --- a/softfloat/source/f16_to_i32.c +++ /dev/null @@ -1,87 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t f16_to_i32( float16_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool sign; - int_fast8_t exp; - uint_fast16_t frac; - int_fast32_t sig32; - int_fast8_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF16UI( uiA ); - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x1F ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - frac ? i32_fromNaN - : sign ? i32_fromNegOverflow : i32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig32 = frac; - if ( exp ) { - sig32 |= 0x0400; - shiftDist = exp - 0x19; - if ( 0 <= shiftDist ) { - sig32 <<= shiftDist; - return sign ? -sig32 : sig32; - } - shiftDist = exp - 0x0D; - if ( 0 < shiftDist ) sig32 <<= shiftDist; - } - return - softfloat_roundToI32( - sign, (uint_fast32_t) sig32, roundingMode, exact ); - -} - diff --git a/softfloat/source/f16_to_i32_r_minMag.c b/softfloat/source/f16_to_i32_r_minMag.c deleted file mode 100644 index b1f9963..0000000 --- a/softfloat/source/f16_to_i32_r_minMag.c +++ /dev/null @@ -1,88 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t f16_to_i32_r_minMag( float16_t a, bool exact ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - int_fast8_t exp; - uint_fast16_t frac; - int_fast8_t shiftDist; - bool sign; - int_fast32_t alignedSig; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = exp - 0x0F; - if ( shiftDist < 0 ) { - if ( exact && (exp | frac) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF16UI( uiA ); - if ( exp == 0x1F ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x1F) && frac ? i32_fromNaN - : sign ? i32_fromNegOverflow : i32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - alignedSig = (int_fast32_t) (frac | 0x0400)<>= 10; - return sign ? -alignedSig : alignedSig; - -} - diff --git a/softfloat/source/f16_to_i64.c b/softfloat/source/f16_to_i64.c deleted file mode 100644 index e3c0065..0000000 --- a/softfloat/source/f16_to_i64.c +++ /dev/null @@ -1,87 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t f16_to_i64( float16_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool sign; - int_fast8_t exp; - uint_fast16_t frac; - int_fast32_t sig32; - int_fast8_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF16UI( uiA ); - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x1F ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - frac ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig32 = frac; - if ( exp ) { - sig32 |= 0x0400; - shiftDist = exp - 0x19; - if ( 0 <= shiftDist ) { - sig32 <<= shiftDist; - return sign ? -sig32 : sig32; - } - shiftDist = exp - 0x0D; - if ( 0 < shiftDist ) sig32 <<= shiftDist; - } - return - softfloat_roundToI32( - sign, (uint_fast32_t) sig32, roundingMode, exact ); - -} - diff --git a/softfloat/source/f16_to_i64_r_minMag.c b/softfloat/source/f16_to_i64_r_minMag.c deleted file mode 100644 index a5a6a07..0000000 --- a/softfloat/source/f16_to_i64_r_minMag.c +++ /dev/null @@ -1,88 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t f16_to_i64_r_minMag( float16_t a, bool exact ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - int_fast8_t exp; - uint_fast16_t frac; - int_fast8_t shiftDist; - bool sign; - int_fast32_t alignedSig; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = exp - 0x0F; - if ( shiftDist < 0 ) { - if ( exact && (exp | frac) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF16UI( uiA ); - if ( exp == 0x1F ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x1F) && frac ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - alignedSig = (int_fast32_t) (frac | 0x0400)<>= 10; - return sign ? -alignedSig : alignedSig; - -} - diff --git a/softfloat/source/f16_to_ui32.c b/softfloat/source/f16_to_ui32.c deleted file mode 100644 index 5371ca3..0000000 --- a/softfloat/source/f16_to_ui32.c +++ /dev/null @@ -1,84 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t f16_to_ui32( float16_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool sign; - int_fast8_t exp; - uint_fast16_t frac; - uint_fast32_t sig32; - int_fast8_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF16UI( uiA ); - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x1F ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - frac ? ui32_fromNaN - : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig32 = frac; - if ( exp ) { - sig32 |= 0x0400; - shiftDist = exp - 0x19; - if ( (0 <= shiftDist) && ! sign ) { - return sig32< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t f16_to_ui32_r_minMag( float16_t a, bool exact ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - int_fast8_t exp; - uint_fast16_t frac; - int_fast8_t shiftDist; - bool sign; - uint_fast32_t alignedSig; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = exp - 0x0F; - if ( shiftDist < 0 ) { - if ( exact && (exp | frac) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF16UI( uiA ); - if ( sign || (exp == 0x1F) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x1F) && frac ? ui32_fromNaN - : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - alignedSig = (uint_fast32_t) (frac | 0x0400)<>10; - -} - diff --git a/softfloat/source/f16_to_ui64.c b/softfloat/source/f16_to_ui64.c deleted file mode 100644 index e6cb000..0000000 --- a/softfloat/source/f16_to_ui64.c +++ /dev/null @@ -1,96 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t f16_to_ui64( float16_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - bool sign; - int_fast8_t exp; - uint_fast16_t frac; - uint_fast32_t sig32; - int_fast8_t shiftDist; -#ifndef SOFTFLOAT_FAST_INT64 - uint32_t extSig[3]; -#endif - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF16UI( uiA ); - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x1F ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - frac ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig32 = frac; - if ( exp ) { - sig32 |= 0x0400; - shiftDist = exp - 0x19; - if ( (0 <= shiftDist) && ! sign ) { - return sig32<>12, (uint_fast64_t) sig32<<52, roundingMode, exact ); -#else - extSig[indexWord( 3, 2 )] = 0; - extSig[indexWord( 3, 1 )] = sig32>>12; - extSig[indexWord( 3, 0 )] = sig32<<20; - return softfloat_roundMToUI64( sign, extSig, roundingMode, exact ); -#endif - -} - diff --git a/softfloat/source/f16_to_ui64_r_minMag.c b/softfloat/source/f16_to_ui64_r_minMag.c deleted file mode 100644 index b4f975f..0000000 --- a/softfloat/source/f16_to_ui64_r_minMag.c +++ /dev/null @@ -1,87 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t f16_to_ui64_r_minMag( float16_t a, bool exact ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - int_fast8_t exp; - uint_fast16_t frac; - int_fast8_t shiftDist; - bool sign; - uint_fast32_t alignedSig; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF16UI( uiA ); - frac = fracF16UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = exp - 0x0F; - if ( shiftDist < 0 ) { - if ( exact && (exp | frac) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF16UI( uiA ); - if ( sign || (exp == 0x1F) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x1F) && frac ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - alignedSig = (uint_fast32_t) (frac | 0x0400)<>10; - -} - diff --git a/softfloat/source/f32_add.c b/softfloat/source/f32_add.c deleted file mode 100644 index 70e03e7..0000000 --- a/softfloat/source/f32_add.c +++ /dev/null @@ -1,70 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float32_t f32_add( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - union ui32_f32 uB; - uint_fast32_t uiB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1) - float32_t (*magsFuncPtr)( uint_fast32_t, uint_fast32_t ); -#endif - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; -#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) - if ( signF32UI( uiA ^ uiB ) ) { - return softfloat_subMagsF32( uiA, uiB ); - } else { - return softfloat_addMagsF32( uiA, uiB ); - } -#else - magsFuncPtr = - signF32UI( uiA ^ uiB ) ? softfloat_subMagsF32 : softfloat_addMagsF32; - return (*magsFuncPtr)( uiA, uiB ); -#endif - -} - diff --git a/softfloat/source/f32_div.c b/softfloat/source/f32_div.c deleted file mode 100644 index 05ec701..0000000 --- a/softfloat/source/f32_div.c +++ /dev/null @@ -1,180 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t f32_div( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool signA; - int_fast16_t expA; - uint_fast32_t sigA; - union ui32_f32 uB; - uint_fast32_t uiB; - bool signB; - int_fast16_t expB; - uint_fast32_t sigB; - bool signZ; - struct exp16_sig32 normExpSig; - int_fast16_t expZ; -#ifdef SOFTFLOAT_FAST_DIV64TO32 - uint_fast64_t sig64A; - uint_fast32_t sigZ; -#else - uint_fast32_t sigZ; - uint_fast64_t rem; -#endif - uint_fast32_t uiZ; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF32UI( uiA ); - expA = expF32UI( uiA ); - sigA = fracF32UI( uiA ); - uB.f = b; - uiB = uB.ui; - signB = signF32UI( uiB ); - expB = expF32UI( uiB ); - sigB = fracF32UI( uiB ); - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0xFF ) { - if ( sigA ) goto propagateNaN; - if ( expB == 0xFF ) { - if ( sigB ) goto propagateNaN; - goto invalid; - } - goto infinity; - } - if ( expB == 0xFF ) { - if ( sigB ) goto propagateNaN; - goto zero; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) { - if ( ! sigB ) { - if ( ! (expA | sigA) ) goto invalid; - softfloat_raiseFlags( softfloat_flag_infinite ); - goto infinity; - } - normExpSig = softfloat_normSubnormalF32Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - if ( ! expA ) { - if ( ! sigA ) goto zero; - normExpSig = softfloat_normSubnormalF32Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA - expB + 0x7E; - sigA |= 0x00800000; - sigB |= 0x00800000; -#ifdef SOFTFLOAT_FAST_DIV64TO32 - if ( sigA < sigB ) { - --expZ; - sig64A = (uint_fast64_t) sigA<<31; - } else { - sig64A = (uint_fast64_t) sigA<<30; - } - sigZ = sig64A / sigB; - if ( ! (sigZ & 0x3F) ) sigZ |= ((uint_fast64_t) sigB * sigZ != sig64A); -#else - if ( sigA < sigB ) { - --expZ; - sigA <<= 8; - } else { - sigA <<= 7; - } - sigB <<= 8; - sigZ = ((uint_fast64_t) sigA * softfloat_approxRecip32_1( sigB ))>>32; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sigZ += 2; - if ( (sigZ & 0x3F) < 2 ) { - sigZ &= ~3; -#ifdef SOFTFLOAT_FAST_INT64 - rem = ((uint_fast64_t) sigA<<31) - (uint_fast64_t) sigZ * sigB; -#else - rem = ((uint_fast64_t) sigA<<32) - (uint_fast64_t) (sigZ<<1) * sigB; -#endif - if ( rem & UINT64_C( 0x8000000000000000 ) ) { - sigZ -= 4; - } else { - if ( rem ) sigZ |= 1; - } - } -#endif - return softfloat_roundPackToF32( signZ, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF32UI( uiA, uiB ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF32UI; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infinity: - uiZ = packToF32UI( signZ, 0xFF, 0 ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ = packToF32UI( signZ, 0, 0 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f32_eq.c b/softfloat/source/f32_eq.c deleted file mode 100644 index 801bbfd..0000000 --- a/softfloat/source/f32_eq.c +++ /dev/null @@ -1,66 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f32_eq( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - union ui32_f32 uB; - uint_fast32_t uiB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { - if ( - softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - return (uiA == uiB) || ! (uint32_t) ((uiA | uiB)<<1); - -} - diff --git a/softfloat/source/f32_eq_signaling.c b/softfloat/source/f32_eq_signaling.c deleted file mode 100644 index 4c610ff..0000000 --- a/softfloat/source/f32_eq_signaling.c +++ /dev/null @@ -1,61 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f32_eq_signaling( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - union ui32_f32 uB; - uint_fast32_t uiB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - return (uiA == uiB) || ! (uint32_t) ((uiA | uiB)<<1); - -} - diff --git a/softfloat/source/f32_isSignalingNaN.c b/softfloat/source/f32_isSignalingNaN.c deleted file mode 100644 index f5954cb..0000000 --- a/softfloat/source/f32_isSignalingNaN.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f32_isSignalingNaN( float32_t a ) -{ - union ui32_f32 uA; - - uA.f = a; - return softfloat_isSigNaNF32UI( uA.ui ); - -} - diff --git a/softfloat/source/f32_le.c b/softfloat/source/f32_le.c deleted file mode 100644 index d89d1e8..0000000 --- a/softfloat/source/f32_le.c +++ /dev/null @@ -1,66 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f32_le( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - union ui32_f32 uB; - uint_fast32_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - signA = signF32UI( uiA ); - signB = signF32UI( uiB ); - return - (signA != signB) ? signA || ! (uint32_t) ((uiA | uiB)<<1) - : (uiA == uiB) || (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f32_le_quiet.c b/softfloat/source/f32_le_quiet.c deleted file mode 100644 index c2d4297..0000000 --- a/softfloat/source/f32_le_quiet.c +++ /dev/null @@ -1,71 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f32_le_quiet( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - union ui32_f32 uB; - uint_fast32_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { - if ( - softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - signA = signF32UI( uiA ); - signB = signF32UI( uiB ); - return - (signA != signB) ? signA || ! (uint32_t) ((uiA | uiB)<<1) - : (uiA == uiB) || (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f32_lt.c b/softfloat/source/f32_lt.c deleted file mode 100644 index 5b5fd22..0000000 --- a/softfloat/source/f32_lt.c +++ /dev/null @@ -1,66 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f32_lt( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - union ui32_f32 uB; - uint_fast32_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - signA = signF32UI( uiA ); - signB = signF32UI( uiB ); - return - (signA != signB) ? signA && ((uint32_t) ((uiA | uiB)<<1) != 0) - : (uiA != uiB) && (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f32_lt_quiet.c b/softfloat/source/f32_lt_quiet.c deleted file mode 100644 index 0153881..0000000 --- a/softfloat/source/f32_lt_quiet.c +++ /dev/null @@ -1,71 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f32_lt_quiet( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - union ui32_f32 uB; - uint_fast32_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { - if ( - softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - signA = signF32UI( uiA ); - signB = signF32UI( uiB ); - return - (signA != signB) ? signA && ((uint32_t) ((uiA | uiB)<<1) != 0) - : (uiA != uiB) && (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f32_mul.c b/softfloat/source/f32_mul.c deleted file mode 100644 index f5c8560..0000000 --- a/softfloat/source/f32_mul.c +++ /dev/null @@ -1,137 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t f32_mul( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool signA; - int_fast16_t expA; - uint_fast32_t sigA; - union ui32_f32 uB; - uint_fast32_t uiB; - bool signB; - int_fast16_t expB; - uint_fast32_t sigB; - bool signZ; - uint_fast32_t magBits; - struct exp16_sig32 normExpSig; - int_fast16_t expZ; - uint_fast32_t sigZ, uiZ; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF32UI( uiA ); - expA = expF32UI( uiA ); - sigA = fracF32UI( uiA ); - uB.f = b; - uiB = uB.ui; - signB = signF32UI( uiB ); - expB = expF32UI( uiB ); - sigB = fracF32UI( uiB ); - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0xFF ) { - if ( sigA || ((expB == 0xFF) && sigB) ) goto propagateNaN; - magBits = expB | sigB; - goto infArg; - } - if ( expB == 0xFF ) { - if ( sigB ) goto propagateNaN; - magBits = expA | sigA; - goto infArg; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! sigA ) goto zero; - normExpSig = softfloat_normSubnormalF32Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - if ( ! expB ) { - if ( ! sigB ) goto zero; - normExpSig = softfloat_normSubnormalF32Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA + expB - 0x7F; - sigA = (sigA | 0x00800000)<<7; - sigB = (sigB | 0x00800000)<<8; - sigZ = softfloat_shortShiftRightJam64( (uint_fast64_t) sigA * sigB, 32 ); - if ( sigZ < 0x40000000 ) { - --expZ; - sigZ <<= 1; - } - return softfloat_roundPackToF32( signZ, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF32UI( uiA, uiB ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infArg: - if ( ! magBits ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF32UI; - } else { - uiZ = packToF32UI( signZ, 0xFF, 0 ); - } - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ = packToF32UI( signZ, 0, 0 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f32_mulAdd.c b/softfloat/source/f32_mulAdd.c deleted file mode 100644 index 9a28e21..0000000 --- a/softfloat/source/f32_mulAdd.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float32_t f32_mulAdd( float32_t a, float32_t b, float32_t c ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - union ui32_f32 uB; - uint_fast32_t uiB; - union ui32_f32 uC; - uint_fast32_t uiC; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - uC.f = c; - uiC = uC.ui; - return softfloat_mulAddF32( uiA, uiB, uiC, 0 ); - -} - diff --git a/softfloat/source/f32_rem.c b/softfloat/source/f32_rem.c deleted file mode 100644 index b29bf41..0000000 --- a/softfloat/source/f32_rem.c +++ /dev/null @@ -1,168 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t f32_rem( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool signA; - int_fast16_t expA; - uint_fast32_t sigA; - union ui32_f32 uB; - uint_fast32_t uiB; - int_fast16_t expB; - uint_fast32_t sigB; - struct exp16_sig32 normExpSig; - uint32_t rem; - int_fast16_t expDiff; - uint32_t q, recip32, altRem, meanRem; - bool signRem; - uint_fast32_t uiZ; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF32UI( uiA ); - expA = expF32UI( uiA ); - sigA = fracF32UI( uiA ); - uB.f = b; - uiB = uB.ui; - expB = expF32UI( uiB ); - sigB = fracF32UI( uiB ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0xFF ) { - if ( sigA || ((expB == 0xFF) && sigB) ) goto propagateNaN; - goto invalid; - } - if ( expB == 0xFF ) { - if ( sigB ) goto propagateNaN; - return a; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) { - if ( ! sigB ) goto invalid; - normExpSig = softfloat_normSubnormalF32Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - if ( ! expA ) { - if ( ! sigA ) return a; - normExpSig = softfloat_normSubnormalF32Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - rem = sigA | 0x00800000; - sigB |= 0x00800000; - expDiff = expA - expB; - if ( expDiff < 1 ) { - if ( expDiff < -1 ) return a; - sigB <<= 6; - if ( expDiff ) { - rem <<= 5; - q = 0; - } else { - rem <<= 6; - q = (sigB <= rem); - if ( q ) rem -= sigB; - } - } else { - recip32 = softfloat_approxRecip32_1( sigB<<8 ); - /*-------------------------------------------------------------------- - | Changing the shift of `rem' here requires also changing the initial - | subtraction from `expDiff'. - *--------------------------------------------------------------------*/ - rem <<= 7; - expDiff -= 31; - /*-------------------------------------------------------------------- - | The scale of `sigB' affects how many bits are obtained during each - | cycle of the loop. Currently this is 29 bits per loop iteration, - | which is believed to be the maximum possible. - *--------------------------------------------------------------------*/ - sigB <<= 6; - for (;;) { - q = (rem * (uint_fast64_t) recip32)>>32; - if ( expDiff < 0 ) break; - rem = -(q * (uint32_t) sigB); - expDiff -= 29; - } - /*-------------------------------------------------------------------- - | (`expDiff' cannot be less than -30 here.) - *--------------------------------------------------------------------*/ - q >>= ~expDiff & 31; - rem = (rem<<(expDiff + 30)) - q * (uint32_t) sigB; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - do { - altRem = rem; - ++q; - rem -= sigB; - } while ( ! (rem & 0x80000000) ); - meanRem = rem + altRem; - if ( (meanRem & 0x80000000) || (! meanRem && (q & 1)) ) rem = altRem; - signRem = signA; - if ( 0x80000000 <= rem ) { - signRem = ! signRem; - rem = -rem; - } - return softfloat_normRoundPackToF32( signRem, expB, rem ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF32UI( uiA, uiB ); - goto uiZ; - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF32UI; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f32_roundToInt.c b/softfloat/source/f32_roundToInt.c deleted file mode 100644 index 305af79..0000000 --- a/softfloat/source/f32_roundToInt.c +++ /dev/null @@ -1,120 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t f32_roundToInt( float32_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - int_fast16_t exp; - uint_fast32_t uiZ, lastBitMask, roundBitsMask; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp <= 0x7E ) { - if ( !(uint32_t) (uiA<<1) ) return a; - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - uiZ = uiA & packToF32UI( 1, 0, 0 ); - switch ( roundingMode ) { - case softfloat_round_near_even: - if ( !fracF32UI( uiA ) ) break; - case softfloat_round_near_maxMag: - if ( exp == 0x7E ) uiZ |= packToF32UI( 0, 0x7F, 0 ); - break; - case softfloat_round_min: - if ( uiZ ) uiZ = packToF32UI( 1, 0x7F, 0 ); - break; - case softfloat_round_max: - if ( !uiZ ) uiZ = packToF32UI( 0, 0x7F, 0 ); - break; -#ifdef SOFTFLOAT_ROUND_ODD - case softfloat_round_odd: - uiZ |= packToF32UI( 0, 0x7F, 0 ); - break; -#endif - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x96 <= exp ) { - if ( (exp == 0xFF) && fracF32UI( uiA ) ) { - uiZ = softfloat_propagateNaNF32UI( uiA, 0 ); - goto uiZ; - } - return a; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ = uiA; - lastBitMask = (uint_fast32_t) 1<<(0x96 - exp); - roundBitsMask = lastBitMask - 1; - if ( roundingMode == softfloat_round_near_maxMag ) { - uiZ += lastBitMask>>1; - } else if ( roundingMode == softfloat_round_near_even ) { - uiZ += lastBitMask>>1; - if ( !(uiZ & roundBitsMask) ) uiZ &= ~lastBitMask; - } else if ( - roundingMode - == (signF32UI( uiZ ) ? softfloat_round_min : softfloat_round_max) - ) { - uiZ += roundBitsMask; - } - uiZ &= ~roundBitsMask; - if ( uiZ != uiA ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) uiZ |= lastBitMask; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f32_sqrt.c b/softfloat/source/f32_sqrt.c deleted file mode 100644 index 9263bde..0000000 --- a/softfloat/source/f32_sqrt.c +++ /dev/null @@ -1,121 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t f32_sqrt( float32_t a ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool signA; - int_fast16_t expA; - uint_fast32_t sigA, uiZ; - struct exp16_sig32 normExpSig; - int_fast16_t expZ; - uint_fast32_t sigZ, shiftedSigZ; - uint32_t negRem; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF32UI( uiA ); - expA = expF32UI( uiA ); - sigA = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0xFF ) { - if ( sigA ) { - uiZ = softfloat_propagateNaNF32UI( uiA, 0 ); - goto uiZ; - } - if ( ! signA ) return a; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( signA ) { - if ( ! (expA | sigA) ) return a; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! sigA ) return a; - normExpSig = softfloat_normSubnormalF32Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = ((expA - 0x7F)>>1) + 0x7E; - expA &= 1; - sigA = (sigA | 0x00800000)<<8; - sigZ = - ((uint_fast64_t) sigA * softfloat_approxRecipSqrt32_1( expA, sigA )) - >>32; - if ( expA ) sigZ >>= 1; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sigZ += 2; - if ( (sigZ & 0x3F) < 2 ) { - shiftedSigZ = sigZ>>2; - negRem = shiftedSigZ * shiftedSigZ; - sigZ &= ~3; - if ( negRem & 0x80000000 ) { - sigZ |= 1; - } else { - if ( negRem ) --sigZ; - } - } - return softfloat_roundPackToF32( 0, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF32UI; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f32_sub.c b/softfloat/source/f32_sub.c deleted file mode 100644 index 383484d..0000000 --- a/softfloat/source/f32_sub.c +++ /dev/null @@ -1,70 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float32_t f32_sub( float32_t a, float32_t b ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - union ui32_f32 uB; - uint_fast32_t uiB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1) - float32_t (*magsFuncPtr)( uint_fast32_t, uint_fast32_t ); -#endif - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; -#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) - if ( signF32UI( uiA ^ uiB ) ) { - return softfloat_addMagsF32( uiA, uiB ); - } else { - return softfloat_subMagsF32( uiA, uiB ); - } -#else - magsFuncPtr = - signF32UI( uiA ^ uiB ) ? softfloat_addMagsF32 : softfloat_subMagsF32; - return (*magsFuncPtr)( uiA, uiB ); -#endif - -} - diff --git a/softfloat/source/f32_to_bf16.c b/softfloat/source/f32_to_bf16.c deleted file mode 100644 index 6f81493..0000000 --- a/softfloat/source/f32_to_bf16.c +++ /dev/null @@ -1,105 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#include -#include - -bfloat16_t f32_to_bf16( float32_t a ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool sign; - int_fast16_t exp; - uint_fast32_t frac; - struct commonNaN commonNaN; - uint_fast16_t uiZ, frac16; - union ui16_bf16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - frac = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - // infinity or NaN cases - if ( exp == 0xFF ) { - if ( frac ) { - // NaN case - softfloat_f32UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToBF16UI( &commonNaN ); - } else { - // infinity case - uiZ = packToBF16UI( sign, 0xFF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - // frac is a 24-bit mantissa, right shifted by 9 - // In the normal case, (24-9) = 15 are set - frac16 = frac>>9 | ((frac & 0x1FF) != 0); - if ( ! (exp | frac16) ) { - uiZ = packToBF16UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - // softfloat_roundPackToBF16 exponent argument (2nd argument) - // must correspond to the exponent of fracIn[13] bits - // (fracIn is the 3rd and last argument) - uint_fast32_t mask = exp ? 0x4000 : 0x0; // implicit one mask added if input is a normal number - // exponent for the lowest normal and largest subnormal should be equal - // but is not in IEEE encoding so mantissa must be partially normalized - // (by one bit) for subnormal numbers. Such that (exp - 1) corresponds - // to the exponent of frac16[13] - frac16 = frac16 << (exp ? 0 : 1); - return softfloat_roundPackToBF16( sign, exp - 1, frac16 | mask ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f32_to_extF80.c b/softfloat/source/f32_to_extF80.c deleted file mode 100644 index 742ed64..0000000 --- a/softfloat/source/f32_to_extF80.c +++ /dev/null @@ -1,101 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t f32_to_extF80( float32_t a ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool sign; - int_fast16_t exp; - uint_fast32_t frac; - struct commonNaN commonNaN; - struct uint128 uiZ; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0; - struct exp16_sig32 normExpSig; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - frac = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0xFF ) { - if ( frac ) { - softfloat_f32UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToExtF80UI( &commonNaN ); - uiZ64 = uiZ.v64; - uiZ0 = uiZ.v0; - } else { - uiZ64 = packToExtF80UI64( sign, 0x7FFF ); - uiZ0 = UINT64_C( 0x8000000000000000 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ64 = packToExtF80UI64( sign, 0 ); - uiZ0 = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalF32Sig( frac ); - exp = normExpSig.exp; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ64 = packToExtF80UI64( sign, exp + 0x3F80 ); - uiZ0 = (uint_fast64_t) (frac | 0x00800000)<<40; - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/f32_to_extF80M.c b/softfloat/source/f32_to_extF80M.c deleted file mode 100644 index af7e32a..0000000 --- a/softfloat/source/f32_to_extF80M.c +++ /dev/null @@ -1,111 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void f32_to_extF80M( float32_t a, extFloat80_t *zPtr ) -{ - - *zPtr = f32_to_extF80( a ); - -} - -#else - -void f32_to_extF80M( float32_t a, extFloat80_t *zPtr ) -{ - struct extFloat80M *zSPtr; - union ui32_f32 uA; - uint32_t uiA; - bool sign; - int_fast16_t exp; - uint32_t frac; - struct commonNaN commonNaN; - uint_fast16_t uiZ64; - uint32_t uiZ32; - struct exp16_sig32 normExpSig; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zSPtr = (struct extFloat80M *) zPtr; - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - frac = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0xFF ) { - if ( frac ) { - softfloat_f32UIToCommonNaN( uiA, &commonNaN ); - softfloat_commonNaNToExtF80M( &commonNaN, zSPtr ); - return; - } - uiZ64 = packToExtF80UI64( sign, 0x7FFF ); - uiZ32 = 0x80000000; - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ64 = packToExtF80UI64( sign, 0 ); - uiZ32 = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalF32Sig( frac ); - exp = normExpSig.exp; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ64 = packToExtF80UI64( sign, exp + 0x3F80 ); - uiZ32 = 0x80000000 | (uint32_t) frac<<8; - uiZ: - zSPtr->signExp = uiZ64; - zSPtr->signif = (uint64_t) uiZ32<<32; - -} - -#endif - diff --git a/softfloat/source/f32_to_f128.c b/softfloat/source/f32_to_f128.c deleted file mode 100644 index 6a765a4..0000000 --- a/softfloat/source/f32_to_f128.c +++ /dev/null @@ -1,96 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t f32_to_f128( float32_t a ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool sign; - int_fast16_t exp; - uint_fast32_t frac; - struct commonNaN commonNaN; - struct uint128 uiZ; - struct exp16_sig32 normExpSig; - union ui128_f128 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - frac = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0xFF ) { - if ( frac ) { - softfloat_f32UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToF128UI( &commonNaN ); - } else { - uiZ.v64 = packToF128UI64( sign, 0x7FFF, 0 ); - uiZ.v0 = 0; - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ.v64 = packToF128UI64( sign, 0, 0 ); - uiZ.v0 = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalF32Sig( frac ); - exp = normExpSig.exp - 1; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ.v64 = packToF128UI64( sign, exp + 0x3F80, (uint_fast64_t) frac<<25 ); - uiZ.v0 = 0; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f32_to_f128M.c b/softfloat/source/f32_to_f128M.c deleted file mode 100644 index ee7e6b3..0000000 --- a/softfloat/source/f32_to_f128M.c +++ /dev/null @@ -1,115 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void f32_to_f128M( float32_t a, float128_t *zPtr ) -{ - - *zPtr = f32_to_f128( a ); - -} - -#else - -void f32_to_f128M( float32_t a, float128_t *zPtr ) -{ - uint32_t *zWPtr; - union ui32_f32 uA; - uint32_t uiA; - bool sign; - int_fast16_t exp; - uint32_t frac, uiZ64; - struct commonNaN commonNaN; - uint32_t uiZ96; - struct exp16_sig32 normExpSig; - uint64_t frac64; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zWPtr = (uint32_t *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - frac = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ64 = 0; - if ( exp == 0xFF ) { - if ( frac ) { - softfloat_f32UIToCommonNaN( uiA, &commonNaN ); - softfloat_commonNaNToF128M( &commonNaN, zWPtr ); - return; - } - uiZ96 = packToF128UI96( sign, 0x7FFF, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ96 = packToF128UI96( sign, 0, 0 ); - goto uiZ; - } - normExpSig = softfloat_normSubnormalF32Sig( frac ); - exp = normExpSig.exp - 1; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - frac64 = (uint64_t) frac<<25; - uiZ96 = packToF128UI96( sign, exp + 0x3F80, frac64>>32 ); - uiZ64 = frac64; - uiZ: - zWPtr[indexWord( 4, 3 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = uiZ64; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - -} - -#endif - diff --git a/softfloat/source/f32_to_f16.c b/softfloat/source/f32_to_f16.c deleted file mode 100644 index 45005fe..0000000 --- a/softfloat/source/f32_to_f16.c +++ /dev/null @@ -1,91 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float16_t f32_to_f16( float32_t a ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool sign; - int_fast16_t exp; - uint_fast32_t frac; - struct commonNaN commonNaN; - uint_fast16_t uiZ, frac16; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - frac = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0xFF ) { - if ( frac ) { - softfloat_f32UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToF16UI( &commonNaN ); - } else { - uiZ = packToF16UI( sign, 0x1F, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - // frac is a 24-bit significand, the bottom 9 bits LSB are extracted and OR-red - // into a sticky flag, the top 15 MSBs are extracted, the LSB of this top slice - // is OR-red with the sticky - frac16 = frac>>9 | ((frac & 0x1FF) != 0); - if ( ! (exp | frac16) ) { - uiZ = packToF16UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - return softfloat_roundPackToF16( sign, exp - 0x71, frac16 | 0x4000 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f32_to_f64.c b/softfloat/source/f32_to_f64.c deleted file mode 100644 index 4f97519..0000000 --- a/softfloat/source/f32_to_f64.c +++ /dev/null @@ -1,93 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float64_t f32_to_f64( float32_t a ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool sign; - int_fast16_t exp; - uint_fast32_t frac; - struct commonNaN commonNaN; - uint_fast64_t uiZ; - struct exp16_sig32 normExpSig; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - frac = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0xFF ) { - if ( frac ) { - softfloat_f32UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToF64UI( &commonNaN ); - } else { - uiZ = packToF64UI( sign, 0x7FF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ = packToF64UI( sign, 0, 0 ); - goto uiZ; - } - normExpSig = softfloat_normSubnormalF32Sig( frac ); - exp = normExpSig.exp - 1; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ = packToF64UI( sign, exp + 0x380, (uint_fast64_t) frac<<29 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f32_to_i32.c b/softfloat/source/f32_to_i32.c deleted file mode 100644 index 7d0356f..0000000 --- a/softfloat/source/f32_to_i32.c +++ /dev/null @@ -1,84 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t f32_to_i32( float32_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool sign; - int_fast16_t exp; - uint_fast32_t sig; - uint_fast64_t sig64; - int_fast16_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - sig = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ -#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow) - if ( (exp == 0xFF) && sig ) { -#if (i32_fromNaN == i32_fromPosOverflow) - sign = 0; -#elif (i32_fromNaN == i32_fromNegOverflow) - sign = 1; -#else - softfloat_raiseFlags( softfloat_flag_invalid ); - return i32_fromNaN; -#endif - } -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig |= 0x00800000; - sig64 = (uint_fast64_t) sig<<32; - shiftDist = 0xAA - exp; - if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist ); - return softfloat_roundToI32( sign, sig64, roundingMode, exact ); - -} - diff --git a/softfloat/source/f32_to_i32_r_minMag.c b/softfloat/source/f32_to_i32_r_minMag.c deleted file mode 100644 index 7652f2e..0000000 --- a/softfloat/source/f32_to_i32_r_minMag.c +++ /dev/null @@ -1,89 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t f32_to_i32_r_minMag( float32_t a, bool exact ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - int_fast16_t exp; - uint_fast32_t sig; - int_fast16_t shiftDist; - bool sign; - int_fast32_t absZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF32UI( uiA ); - sig = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x9E - exp; - if ( 32 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF32UI( uiA ); - if ( shiftDist <= 0 ) { - if ( uiA == packToF32UI( 1, 0x9E, 0 ) ) return -0x7FFFFFFF - 1; - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0xFF) && sig ? i32_fromNaN - : sign ? i32_fromNegOverflow : i32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig = (sig | 0x00800000)<<8; - absZ = sig>>shiftDist; - if ( exact && ((uint_fast32_t) absZ< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t f32_to_i64( float32_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool sign; - int_fast16_t exp; - uint_fast32_t sig; - int_fast16_t shiftDist; -#ifdef SOFTFLOAT_FAST_INT64 - uint_fast64_t sig64, extra; - struct uint64_extra sig64Extra; -#else - uint32_t extSig[3]; -#endif - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - sig = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0xBE - exp; - if ( shiftDist < 0 ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0xFF) && sig ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig |= 0x00800000; -#ifdef SOFTFLOAT_FAST_INT64 - sig64 = (uint_fast64_t) sig<<40; - extra = 0; - if ( shiftDist ) { - sig64Extra = softfloat_shiftRightJam64Extra( sig64, 0, shiftDist ); - sig64 = sig64Extra.v; - extra = sig64Extra.extra; - } - return softfloat_roundToI64( sign, sig64, extra, roundingMode, exact ); -#else - extSig[indexWord( 3, 2 )] = sig<<8; - extSig[indexWord( 3, 1 )] = 0; - extSig[indexWord( 3, 0 )] = 0; - if ( shiftDist ) softfloat_shiftRightJam96M( extSig, shiftDist, extSig ); - return softfloat_roundMToI64( sign, extSig, roundingMode, exact ); -#endif - -} - diff --git a/softfloat/source/f32_to_i64_r_minMag.c b/softfloat/source/f32_to_i64_r_minMag.c deleted file mode 100644 index 397ddf6..0000000 --- a/softfloat/source/f32_to_i64_r_minMag.c +++ /dev/null @@ -1,94 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t f32_to_i64_r_minMag( float32_t a, bool exact ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - int_fast16_t exp; - uint_fast32_t sig; - int_fast16_t shiftDist; - bool sign; - uint_fast64_t sig64; - int_fast64_t absZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF32UI( uiA ); - sig = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0xBE - exp; - if ( 64 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF32UI( uiA ); - if ( shiftDist <= 0 ) { - if ( uiA == packToF32UI( 1, 0xBE, 0 ) ) { - return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0xFF) && sig ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig |= 0x00800000; - sig64 = (uint_fast64_t) sig<<40; - absZ = sig64>>shiftDist; - shiftDist = 40 - shiftDist; - if ( exact && (shiftDist < 0) && (uint32_t) (sig<<(shiftDist & 31)) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return sign ? -absZ : absZ; - -} - diff --git a/softfloat/source/f32_to_ui32.c b/softfloat/source/f32_to_ui32.c deleted file mode 100644 index cb47d94..0000000 --- a/softfloat/source/f32_to_ui32.c +++ /dev/null @@ -1,84 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t f32_to_ui32( float32_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool sign; - int_fast16_t exp; - uint_fast32_t sig; - uint_fast64_t sig64; - int_fast16_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - sig = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ -#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow) - if ( (exp == 0xFF) && sig ) { -#if (ui32_fromNaN == ui32_fromPosOverflow) - sign = 0; -#elif (ui32_fromNaN == ui32_fromNegOverflow) - sign = 1; -#else - softfloat_raiseFlags( softfloat_flag_invalid ); - return ui32_fromNaN; -#endif - } -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig |= 0x00800000; - sig64 = (uint_fast64_t) sig<<32; - shiftDist = 0xAA - exp; - if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist ); - return softfloat_roundToUI32( sign, sig64, roundingMode, exact ); - -} - diff --git a/softfloat/source/f32_to_ui32_r_minMag.c b/softfloat/source/f32_to_ui32_r_minMag.c deleted file mode 100644 index cdeb75f..0000000 --- a/softfloat/source/f32_to_ui32_r_minMag.c +++ /dev/null @@ -1,88 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t f32_to_ui32_r_minMag( float32_t a, bool exact ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - int_fast16_t exp; - uint_fast32_t sig; - int_fast16_t shiftDist; - bool sign; - uint_fast32_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF32UI( uiA ); - sig = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x9E - exp; - if ( 32 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF32UI( uiA ); - if ( sign || (shiftDist < 0) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0xFF) && sig ? ui32_fromNaN - : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig = (sig | 0x00800000)<<8; - z = sig>>shiftDist; - if ( exact && (z< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t f32_to_ui64( float32_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - bool sign; - int_fast16_t exp; - uint_fast32_t sig; - int_fast16_t shiftDist; -#ifdef SOFTFLOAT_FAST_INT64 - uint_fast64_t sig64, extra; - struct uint64_extra sig64Extra; -#else - uint32_t extSig[3]; -#endif - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF32UI( uiA ); - exp = expF32UI( uiA ); - sig = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0xBE - exp; - if ( shiftDist < 0 ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0xFF) && sig ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig |= 0x00800000; -#ifdef SOFTFLOAT_FAST_INT64 - sig64 = (uint_fast64_t) sig<<40; - extra = 0; - if ( shiftDist ) { - sig64Extra = softfloat_shiftRightJam64Extra( sig64, 0, shiftDist ); - sig64 = sig64Extra.v; - extra = sig64Extra.extra; - } - return softfloat_roundToUI64( sign, sig64, extra, roundingMode, exact ); -#else - extSig[indexWord( 3, 2 )] = sig<<8; - extSig[indexWord( 3, 1 )] = 0; - extSig[indexWord( 3, 0 )] = 0; - if ( shiftDist ) softfloat_shiftRightJam96M( extSig, shiftDist, extSig ); - return softfloat_roundMToUI64( sign, extSig, roundingMode, exact ); -#endif - -} - diff --git a/softfloat/source/f32_to_ui64_r_minMag.c b/softfloat/source/f32_to_ui64_r_minMag.c deleted file mode 100644 index c0fe54f..0000000 --- a/softfloat/source/f32_to_ui64_r_minMag.c +++ /dev/null @@ -1,90 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t f32_to_ui64_r_minMag( float32_t a, bool exact ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - int_fast16_t exp; - uint_fast32_t sig; - int_fast16_t shiftDist; - bool sign; - uint_fast64_t sig64, z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF32UI( uiA ); - sig = fracF32UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0xBE - exp; - if ( 64 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF32UI( uiA ); - if ( sign || (shiftDist < 0) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0xFF) && sig ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig |= 0x00800000; - sig64 = (uint_fast64_t) sig<<40; - z = sig64>>shiftDist; - shiftDist = 40 - shiftDist; - if ( exact && (shiftDist < 0) && (uint32_t) (sig<<(shiftDist & 31)) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return z; - -} - diff --git a/softfloat/source/f64_add.c b/softfloat/source/f64_add.c deleted file mode 100644 index 42f840d..0000000 --- a/softfloat/source/f64_add.c +++ /dev/null @@ -1,74 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float64_t f64_add( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool signA; - union ui64_f64 uB; - uint_fast64_t uiB; - bool signB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) - float64_t (*magsFuncPtr)( uint_fast64_t, uint_fast64_t, bool ); -#endif - - uA.f = a; - uiA = uA.ui; - signA = signF64UI( uiA ); - uB.f = b; - uiB = uB.ui; - signB = signF64UI( uiB ); -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) - if ( signA == signB ) { - return softfloat_addMagsF64( uiA, uiB, signA ); - } else { - return softfloat_subMagsF64( uiA, uiB, signA ); - } -#else - magsFuncPtr = - (signA == signB) ? softfloat_addMagsF64 : softfloat_subMagsF64; - return (*magsFuncPtr)( uiA, uiB, signA ); -#endif - -} - diff --git a/softfloat/source/f64_div.c b/softfloat/source/f64_div.c deleted file mode 100644 index 9c967bb..0000000 --- a/softfloat/source/f64_div.c +++ /dev/null @@ -1,172 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float64_t f64_div( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool signA; - int_fast16_t expA; - uint_fast64_t sigA; - union ui64_f64 uB; - uint_fast64_t uiB; - bool signB; - int_fast16_t expB; - uint_fast64_t sigB; - bool signZ; - struct exp16_sig64 normExpSig; - int_fast16_t expZ; - uint32_t recip32, sig32Z, doubleTerm; - uint_fast64_t rem; - uint32_t q; - uint_fast64_t sigZ; - uint_fast64_t uiZ; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF64UI( uiA ); - expA = expF64UI( uiA ); - sigA = fracF64UI( uiA ); - uB.f = b; - uiB = uB.ui; - signB = signF64UI( uiB ); - expB = expF64UI( uiB ); - sigB = fracF64UI( uiB ); - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FF ) { - if ( sigA ) goto propagateNaN; - if ( expB == 0x7FF ) { - if ( sigB ) goto propagateNaN; - goto invalid; - } - goto infinity; - } - if ( expB == 0x7FF ) { - if ( sigB ) goto propagateNaN; - goto zero; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) { - if ( ! sigB ) { - if ( ! (expA | sigA) ) goto invalid; - softfloat_raiseFlags( softfloat_flag_infinite ); - goto infinity; - } - normExpSig = softfloat_normSubnormalF64Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - if ( ! expA ) { - if ( ! sigA ) goto zero; - normExpSig = softfloat_normSubnormalF64Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA - expB + 0x3FE; - sigA |= UINT64_C( 0x0010000000000000 ); - sigB |= UINT64_C( 0x0010000000000000 ); - if ( sigA < sigB ) { - --expZ; - sigA <<= 11; - } else { - sigA <<= 10; - } - sigB <<= 11; - recip32 = softfloat_approxRecip32_1( sigB>>32 ) - 2; - sig32Z = ((uint32_t) (sigA>>32) * (uint_fast64_t) recip32)>>32; - doubleTerm = sig32Z<<1; - rem = - ((sigA - (uint_fast64_t) doubleTerm * (uint32_t) (sigB>>32))<<28) - - (uint_fast64_t) doubleTerm * ((uint32_t) sigB>>4); - q = (((uint32_t) (rem>>32) * (uint_fast64_t) recip32)>>32) + 4; - sigZ = ((uint_fast64_t) sig32Z<<32) + ((uint_fast64_t) q<<4); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (sigZ & 0x1FF) < 4<<4 ) { - q &= ~7; - sigZ &= ~(uint_fast64_t) 0x7F; - doubleTerm = q<<1; - rem = - ((rem - (uint_fast64_t) doubleTerm * (uint32_t) (sigB>>32))<<28) - - (uint_fast64_t) doubleTerm * ((uint32_t) sigB>>4); - if ( rem & UINT64_C( 0x8000000000000000 ) ) { - sigZ -= 1<<7; - } else { - if ( rem ) sigZ |= 1; - } - } - return softfloat_roundPackToF64( signZ, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF64UI; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infinity: - uiZ = packToF64UI( signZ, 0x7FF, 0 ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ = packToF64UI( signZ, 0, 0 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f64_eq.c b/softfloat/source/f64_eq.c deleted file mode 100644 index 3602003..0000000 --- a/softfloat/source/f64_eq.c +++ /dev/null @@ -1,66 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f64_eq( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - union ui64_f64 uB; - uint_fast64_t uiB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { - if ( - softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - return (uiA == uiB) || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )); - -} - diff --git a/softfloat/source/f64_eq_signaling.c b/softfloat/source/f64_eq_signaling.c deleted file mode 100644 index 5daa179..0000000 --- a/softfloat/source/f64_eq_signaling.c +++ /dev/null @@ -1,61 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f64_eq_signaling( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - union ui64_f64 uB; - uint_fast64_t uiB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - return (uiA == uiB) || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )); - -} - diff --git a/softfloat/source/f64_isSignalingNaN.c b/softfloat/source/f64_isSignalingNaN.c deleted file mode 100644 index e5d3832..0000000 --- a/softfloat/source/f64_isSignalingNaN.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f64_isSignalingNaN( float64_t a ) -{ - union ui64_f64 uA; - - uA.f = a; - return softfloat_isSigNaNF64UI( uA.ui ); - -} - diff --git a/softfloat/source/f64_le.c b/softfloat/source/f64_le.c deleted file mode 100644 index 0b43d04..0000000 --- a/softfloat/source/f64_le.c +++ /dev/null @@ -1,67 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f64_le( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - union ui64_f64 uB; - uint_fast64_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - signA = signF64UI( uiA ); - signB = signF64UI( uiB ); - return - (signA != signB) - ? signA || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - : (uiA == uiB) || (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f64_le_quiet.c b/softfloat/source/f64_le_quiet.c deleted file mode 100644 index 832eee7..0000000 --- a/softfloat/source/f64_le_quiet.c +++ /dev/null @@ -1,72 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f64_le_quiet( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - union ui64_f64 uB; - uint_fast64_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { - if ( - softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - signA = signF64UI( uiA ); - signB = signF64UI( uiB ); - return - (signA != signB) - ? signA || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - : (uiA == uiB) || (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f64_lt.c b/softfloat/source/f64_lt.c deleted file mode 100644 index 49ee05b..0000000 --- a/softfloat/source/f64_lt.c +++ /dev/null @@ -1,67 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -bool f64_lt( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - union ui64_f64 uB; - uint_fast64_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return false; - } - signA = signF64UI( uiA ); - signB = signF64UI( uiB ); - return - (signA != signB) - ? signA && ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - : (uiA != uiB) && (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f64_lt_quiet.c b/softfloat/source/f64_lt_quiet.c deleted file mode 100644 index d640880..0000000 --- a/softfloat/source/f64_lt_quiet.c +++ /dev/null @@ -1,72 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -bool f64_lt_quiet( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - union ui64_f64 uB; - uint_fast64_t uiB; - bool signA, signB; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { - if ( - softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) - ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - } - return false; - } - signA = signF64UI( uiA ); - signB = signF64UI( uiB ); - return - (signA != signB) - ? signA && ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - : (uiA != uiB) && (signA ^ (uiA < uiB)); - -} - diff --git a/softfloat/source/f64_mul.c b/softfloat/source/f64_mul.c deleted file mode 100644 index 222e91d..0000000 --- a/softfloat/source/f64_mul.c +++ /dev/null @@ -1,150 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float64_t f64_mul( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool signA; - int_fast16_t expA; - uint_fast64_t sigA; - union ui64_f64 uB; - uint_fast64_t uiB; - bool signB; - int_fast16_t expB; - uint_fast64_t sigB; - bool signZ; - uint_fast64_t magBits; - struct exp16_sig64 normExpSig; - int_fast16_t expZ; -#ifdef SOFTFLOAT_FAST_INT64 - struct uint128 sig128Z; -#else - uint32_t sig128Z[4]; -#endif - uint_fast64_t sigZ, uiZ; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF64UI( uiA ); - expA = expF64UI( uiA ); - sigA = fracF64UI( uiA ); - uB.f = b; - uiB = uB.ui; - signB = signF64UI( uiB ); - expB = expF64UI( uiB ); - sigB = fracF64UI( uiB ); - signZ = signA ^ signB; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FF ) { - if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN; - magBits = expB | sigB; - goto infArg; - } - if ( expB == 0x7FF ) { - if ( sigB ) goto propagateNaN; - magBits = expA | sigA; - goto infArg; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! sigA ) goto zero; - normExpSig = softfloat_normSubnormalF64Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - if ( ! expB ) { - if ( ! sigB ) goto zero; - normExpSig = softfloat_normSubnormalF64Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA + expB - 0x3FF; - sigA = (sigA | UINT64_C( 0x0010000000000000 ))<<10; - sigB = (sigB | UINT64_C( 0x0010000000000000 ))<<11; -#ifdef SOFTFLOAT_FAST_INT64 - sig128Z = softfloat_mul64To128( sigA, sigB ); - sigZ = sig128Z.v64 | (sig128Z.v0 != 0); -#else - softfloat_mul64To128M( sigA, sigB, sig128Z ); - sigZ = - (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 | sig128Z[indexWord( 4, 2 )]; - if ( sig128Z[indexWord( 4, 1 )] || sig128Z[indexWord( 4, 0 )] ) sigZ |= 1; -#endif - if ( sigZ < UINT64_C( 0x4000000000000000 ) ) { - --expZ; - sigZ <<= 1; - } - return softfloat_roundPackToF64( signZ, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infArg: - if ( ! magBits ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF64UI; - } else { - uiZ = packToF64UI( signZ, 0x7FF, 0 ); - } - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zero: - uiZ = packToF64UI( signZ, 0, 0 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f64_mulAdd.c b/softfloat/source/f64_mulAdd.c deleted file mode 100644 index fea3d96..0000000 --- a/softfloat/source/f64_mulAdd.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float64_t f64_mulAdd( float64_t a, float64_t b, float64_t c ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - union ui64_f64 uB; - uint_fast64_t uiB; - union ui64_f64 uC; - uint_fast64_t uiC; - - uA.f = a; - uiA = uA.ui; - uB.f = b; - uiB = uB.ui; - uC.f = c; - uiC = uC.ui; - return softfloat_mulAddF64( uiA, uiB, uiC, 0 ); - -} - diff --git a/softfloat/source/f64_rem.c b/softfloat/source/f64_rem.c deleted file mode 100644 index ffce679..0000000 --- a/softfloat/source/f64_rem.c +++ /dev/null @@ -1,189 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float64_t f64_rem( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool signA; - int_fast16_t expA; - uint_fast64_t sigA; - union ui64_f64 uB; - uint_fast64_t uiB; - int_fast16_t expB; - uint_fast64_t sigB; - struct exp16_sig64 normExpSig; - uint64_t rem; - int_fast16_t expDiff; - uint32_t q, recip32; - uint_fast64_t q64; - uint64_t altRem, meanRem; - bool signRem; - uint_fast64_t uiZ; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF64UI( uiA ); - expA = expF64UI( uiA ); - sigA = fracF64UI( uiA ); - uB.f = b; - uiB = uB.ui; - expB = expF64UI( uiB ); - sigB = fracF64UI( uiB ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FF ) { - if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN; - goto invalid; - } - if ( expB == 0x7FF ) { - if ( sigB ) goto propagateNaN; - return a; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA < expB - 1 ) return a; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expB ) { - if ( ! sigB ) goto invalid; - normExpSig = softfloat_normSubnormalF64Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - if ( ! expA ) { - if ( ! sigA ) return a; - normExpSig = softfloat_normSubnormalF64Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - rem = sigA | UINT64_C( 0x0010000000000000 ); - sigB |= UINT64_C( 0x0010000000000000 ); - expDiff = expA - expB; - if ( expDiff < 1 ) { - if ( expDiff < -1 ) return a; - sigB <<= 9; - if ( expDiff ) { - rem <<= 8; - q = 0; - } else { - rem <<= 9; - q = (sigB <= rem); - if ( q ) rem -= sigB; - } - } else { - recip32 = softfloat_approxRecip32_1( sigB>>21 ); - /*-------------------------------------------------------------------- - | Changing the shift of `rem' here requires also changing the initial - | subtraction from `expDiff'. - *--------------------------------------------------------------------*/ - rem <<= 9; - expDiff -= 30; - /*-------------------------------------------------------------------- - | The scale of `sigB' affects how many bits are obtained during each - | cycle of the loop. Currently this is 29 bits per loop iteration, - | the maximum possible. - *--------------------------------------------------------------------*/ - sigB <<= 9; - for (;;) { - q64 = (uint32_t) (rem>>32) * (uint_fast64_t) recip32; - if ( expDiff < 0 ) break; - q = (q64 + 0x80000000)>>32; -#ifdef SOFTFLOAT_FAST_INT64 - rem <<= 29; -#else - rem = (uint_fast64_t) (uint32_t) (rem>>3)<<32; -#endif - rem -= q * (uint64_t) sigB; - if ( rem & UINT64_C( 0x8000000000000000 ) ) rem += sigB; - expDiff -= 29; - } - /*-------------------------------------------------------------------- - | (`expDiff' cannot be less than -29 here.) - *--------------------------------------------------------------------*/ - q = (uint32_t) (q64>>32)>>(~expDiff & 31); - rem = (rem<<(expDiff + 30)) - q * (uint64_t) sigB; - if ( rem & UINT64_C( 0x8000000000000000 ) ) { - altRem = rem + sigB; - goto selectRem; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - do { - altRem = rem; - ++q; - rem -= sigB; - } while ( ! (rem & UINT64_C( 0x8000000000000000 )) ); - selectRem: - meanRem = rem + altRem; - if ( - (meanRem & UINT64_C( 0x8000000000000000 )) || (! meanRem && (q & 1)) - ) { - rem = altRem; - } - signRem = signA; - if ( rem & UINT64_C( 0x8000000000000000 ) ) { - signRem = ! signRem; - rem = -rem; - } - return softfloat_normRoundPackToF64( signRem, expB, rem ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); - goto uiZ; - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF64UI; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f64_roundToInt.c b/softfloat/source/f64_roundToInt.c deleted file mode 100644 index 54e7b05..0000000 --- a/softfloat/source/f64_roundToInt.c +++ /dev/null @@ -1,120 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float64_t f64_roundToInt( float64_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - int_fast16_t exp; - uint_fast64_t uiZ, lastBitMask, roundBitsMask; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp <= 0x3FE ) { - if ( !(uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) return a; - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - uiZ = uiA & packToF64UI( 1, 0, 0 ); - switch ( roundingMode ) { - case softfloat_round_near_even: - if ( !fracF64UI( uiA ) ) break; - case softfloat_round_near_maxMag: - if ( exp == 0x3FE ) uiZ |= packToF64UI( 0, 0x3FF, 0 ); - break; - case softfloat_round_min: - if ( uiZ ) uiZ = packToF64UI( 1, 0x3FF, 0 ); - break; - case softfloat_round_max: - if ( !uiZ ) uiZ = packToF64UI( 0, 0x3FF, 0 ); - break; -#ifdef SOFTFLOAT_ROUND_ODD - case softfloat_round_odd: - uiZ |= packToF64UI( 0, 0x3FF, 0 ); - break; -#endif - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x433 <= exp ) { - if ( (exp == 0x7FF) && fracF64UI( uiA ) ) { - uiZ = softfloat_propagateNaNF64UI( uiA, 0 ); - goto uiZ; - } - return a; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ = uiA; - lastBitMask = (uint_fast64_t) 1<<(0x433 - exp); - roundBitsMask = lastBitMask - 1; - if ( roundingMode == softfloat_round_near_maxMag ) { - uiZ += lastBitMask>>1; - } else if ( roundingMode == softfloat_round_near_even ) { - uiZ += lastBitMask>>1; - if ( !(uiZ & roundBitsMask) ) uiZ &= ~lastBitMask; - } else if ( - roundingMode - == (signF64UI( uiZ ) ? softfloat_round_min : softfloat_round_max) - ) { - uiZ += roundBitsMask; - } - uiZ &= ~roundBitsMask; - if ( uiZ != uiA ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) uiZ |= lastBitMask; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f64_sqrt.c b/softfloat/source/f64_sqrt.c deleted file mode 100644 index f9f226b..0000000 --- a/softfloat/source/f64_sqrt.c +++ /dev/null @@ -1,133 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float64_t f64_sqrt( float64_t a ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool signA; - int_fast16_t expA; - uint_fast64_t sigA, uiZ; - struct exp16_sig64 normExpSig; - int_fast16_t expZ; - uint32_t sig32A, recipSqrt32, sig32Z; - uint_fast64_t rem; - uint32_t q; - uint_fast64_t sigZ, shiftedSigZ; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - signA = signF64UI( uiA ); - expA = expF64UI( uiA ); - sigA = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FF ) { - if ( sigA ) { - uiZ = softfloat_propagateNaNF64UI( uiA, 0 ); - goto uiZ; - } - if ( ! signA ) return a; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( signA ) { - if ( ! (expA | sigA) ) return a; - goto invalid; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! sigA ) return a; - normExpSig = softfloat_normSubnormalF64Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - /*------------------------------------------------------------------------ - | (`sig32Z' is guaranteed to be a lower bound on the square root of - | `sig32A', which makes `sig32Z' also a lower bound on the square root of - | `sigA'.) - *------------------------------------------------------------------------*/ - expZ = ((expA - 0x3FF)>>1) + 0x3FE; - expA &= 1; - sigA |= UINT64_C( 0x0010000000000000 ); - sig32A = sigA>>21; - recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A ); - sig32Z = ((uint_fast64_t) sig32A * recipSqrt32)>>32; - if ( expA ) { - sigA <<= 8; - sig32Z >>= 1; - } else { - sigA <<= 9; - } - rem = sigA - (uint_fast64_t) sig32Z * sig32Z; - q = ((uint32_t) (rem>>2) * (uint_fast64_t) recipSqrt32)>>32; - sigZ = ((uint_fast64_t) sig32Z<<32 | 1<<5) + ((uint_fast64_t) q<<3); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (sigZ & 0x1FF) < 0x22 ) { - sigZ &= ~(uint_fast64_t) 0x3F; - shiftedSigZ = sigZ>>6; - rem = (sigA<<52) - shiftedSigZ * shiftedSigZ; - if ( rem & UINT64_C( 0x8000000000000000 ) ) { - --sigZ; - } else { - if ( rem ) sigZ |= 1; - } - } - return softfloat_roundPackToF64( 0, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF64UI; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f64_sub.c b/softfloat/source/f64_sub.c deleted file mode 100644 index b5ccb88..0000000 --- a/softfloat/source/f64_sub.c +++ /dev/null @@ -1,74 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float64_t f64_sub( float64_t a, float64_t b ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool signA; - union ui64_f64 uB; - uint_fast64_t uiB; - bool signB; -#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) - float64_t (*magsFuncPtr)( uint_fast64_t, uint_fast64_t, bool ); -#endif - - uA.f = a; - uiA = uA.ui; - signA = signF64UI( uiA ); - uB.f = b; - uiB = uB.ui; - signB = signF64UI( uiB ); -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) - if ( signA == signB ) { - return softfloat_subMagsF64( uiA, uiB, signA ); - } else { - return softfloat_addMagsF64( uiA, uiB, signA ); - } -#else - magsFuncPtr = - (signA == signB) ? softfloat_subMagsF64 : softfloat_addMagsF64; - return (*magsFuncPtr)( uiA, uiB, signA ); -#endif - -} - diff --git a/softfloat/source/f64_to_extF80.c b/softfloat/source/f64_to_extF80.c deleted file mode 100644 index 2799d9b..0000000 --- a/softfloat/source/f64_to_extF80.c +++ /dev/null @@ -1,101 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t f64_to_extF80( float64_t a ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool sign; - int_fast16_t exp; - uint_fast64_t frac; - struct commonNaN commonNaN; - struct uint128 uiZ; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0; - struct exp16_sig64 normExpSig; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - frac = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FF ) { - if ( frac ) { - softfloat_f64UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToExtF80UI( &commonNaN ); - uiZ64 = uiZ.v64; - uiZ0 = uiZ.v0; - } else { - uiZ64 = packToExtF80UI64( sign, 0x7FFF ); - uiZ0 = UINT64_C( 0x8000000000000000 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ64 = packToExtF80UI64( sign, 0 ); - uiZ0 = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalF64Sig( frac ); - exp = normExpSig.exp; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ64 = packToExtF80UI64( sign, exp + 0x3C00 ); - uiZ0 = (frac | UINT64_C( 0x0010000000000000 ))<<11; - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/f64_to_extF80M.c b/softfloat/source/f64_to_extF80M.c deleted file mode 100644 index a2e67e4..0000000 --- a/softfloat/source/f64_to_extF80M.c +++ /dev/null @@ -1,111 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void f64_to_extF80M( float64_t a, extFloat80_t *zPtr ) -{ - - *zPtr = f64_to_extF80( a ); - -} - -#else - -void f64_to_extF80M( float64_t a, extFloat80_t *zPtr ) -{ - struct extFloat80M *zSPtr; - union ui64_f64 uA; - uint64_t uiA; - bool sign; - int_fast16_t exp; - uint64_t frac; - struct commonNaN commonNaN; - uint_fast16_t uiZ64; - uint64_t uiZ0; - struct exp16_sig64 normExpSig; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zSPtr = (struct extFloat80M *) zPtr; - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - frac = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FF ) { - if ( frac ) { - softfloat_f64UIToCommonNaN( uiA, &commonNaN ); - softfloat_commonNaNToExtF80M( &commonNaN, zSPtr ); - return; - } - uiZ64 = packToExtF80UI64( sign, 0x7FFF ); - uiZ0 = UINT64_C( 0x8000000000000000 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ64 = packToExtF80UI64( sign, 0 ); - uiZ0 = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalF64Sig( frac ); - exp = normExpSig.exp; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ64 = packToExtF80UI64( sign, exp + 0x3C00 ); - uiZ0 = UINT64_C( 0x8000000000000000 ) | frac<<11; - uiZ: - zSPtr->signExp = uiZ64; - zSPtr->signif = uiZ0; - -} - -#endif - diff --git a/softfloat/source/f64_to_f128.c b/softfloat/source/f64_to_f128.c deleted file mode 100644 index 60af3b0..0000000 --- a/softfloat/source/f64_to_f128.c +++ /dev/null @@ -1,98 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t f64_to_f128( float64_t a ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool sign; - int_fast16_t exp; - uint_fast64_t frac; - struct commonNaN commonNaN; - struct uint128 uiZ; - struct exp16_sig64 normExpSig; - struct uint128 frac128; - union ui128_f128 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - frac = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FF ) { - if ( frac ) { - softfloat_f64UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToF128UI( &commonNaN ); - } else { - uiZ.v64 = packToF128UI64( sign, 0x7FFF, 0 ); - uiZ.v0 = 0; - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ.v64 = packToF128UI64( sign, 0, 0 ); - uiZ.v0 = 0; - goto uiZ; - } - normExpSig = softfloat_normSubnormalF64Sig( frac ); - exp = normExpSig.exp - 1; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - frac128 = softfloat_shortShiftLeft128( 0, frac, 60 ); - uiZ.v64 = packToF128UI64( sign, exp + 0x3C00, frac128.v64 ); - uiZ.v0 = frac128.v0; - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f64_to_f128M.c b/softfloat/source/f64_to_f128M.c deleted file mode 100644 index fbc4515..0000000 --- a/softfloat/source/f64_to_f128M.c +++ /dev/null @@ -1,117 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void f64_to_f128M( float64_t a, float128_t *zPtr ) -{ - - *zPtr = f64_to_f128( a ); - -} - -#else - -void f64_to_f128M( float64_t a, float128_t *zPtr ) -{ - uint32_t *zWPtr; - union ui64_f64 uA; - uint64_t uiA; - bool sign; - int_fast16_t exp; - uint64_t frac; - struct commonNaN commonNaN; - uint32_t uiZ96; - struct exp16_sig64 normExpSig; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zWPtr = (uint32_t *) zPtr; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - frac = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zWPtr[indexWord( 4, 0 )] = 0; - if ( exp == 0x7FF ) { - if ( frac ) { - softfloat_f64UIToCommonNaN( uiA, &commonNaN ); - softfloat_commonNaNToF128M( &commonNaN, zWPtr ); - return; - } - uiZ96 = packToF128UI96( sign, 0x7FFF, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! exp ) { - if ( ! frac ) { - uiZ96 = packToF128UI96( sign, 0, 0 ); - goto uiZ; - } - normExpSig = softfloat_normSubnormalF64Sig( frac ); - exp = normExpSig.exp - 1; - frac = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zWPtr[indexWord( 4, 1 )] = (uint32_t) frac<<28; - frac >>= 4; - zWPtr[indexWordHi( 4 )] = packToF128UI96( sign, exp + 0x3C00, frac>>32 ); - zWPtr[indexWord( 4, 2 )] = frac; - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiZ: - zWPtr[indexWord( 4, 3 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = 0; - zWPtr[indexWord( 4, 1 )] = 0; - -} - -#endif - diff --git a/softfloat/source/f64_to_f16.c b/softfloat/source/f64_to_f16.c deleted file mode 100644 index 121e306..0000000 --- a/softfloat/source/f64_to_f16.c +++ /dev/null @@ -1,88 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float16_t f64_to_f16( float64_t a ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool sign; - int_fast16_t exp; - uint_fast64_t frac; - struct commonNaN commonNaN; - uint_fast16_t uiZ, frac16; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - frac = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FF ) { - if ( frac ) { - softfloat_f64UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToF16UI( &commonNaN ); - } else { - uiZ = packToF16UI( sign, 0x1F, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - frac16 = softfloat_shortShiftRightJam64( frac, 38 ); - if ( ! (exp | frac16) ) { - uiZ = packToF16UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - return softfloat_roundPackToF16( sign, exp - 0x3F1, frac16 | 0x4000 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f64_to_f32.c b/softfloat/source/f64_to_f32.c deleted file mode 100644 index a181065..0000000 --- a/softfloat/source/f64_to_f32.c +++ /dev/null @@ -1,88 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t f64_to_f32( float64_t a ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool sign; - int_fast16_t exp; - uint_fast64_t frac; - struct commonNaN commonNaN; - uint_fast32_t uiZ, frac32; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - frac = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp == 0x7FF ) { - if ( frac ) { - softfloat_f64UIToCommonNaN( uiA, &commonNaN ); - uiZ = softfloat_commonNaNToF32UI( &commonNaN ); - } else { - uiZ = packToF32UI( sign, 0xFF, 0 ); - } - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - frac32 = softfloat_shortShiftRightJam64( frac, 22 ); - if ( ! (exp | frac32) ) { - uiZ = packToF32UI( sign, 0, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - return softfloat_roundPackToF32( sign, exp - 0x381, frac32 | 0x40000000 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/f64_to_i32.c b/softfloat/source/f64_to_i32.c deleted file mode 100644 index 8d9785b..0000000 --- a/softfloat/source/f64_to_i32.c +++ /dev/null @@ -1,82 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t f64_to_i32( float64_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool sign; - int_fast16_t exp; - uint_fast64_t sig; - int_fast16_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - sig = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ -#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow) - if ( (exp == 0x7FF) && sig ) { -#if (i32_fromNaN == i32_fromPosOverflow) - sign = 0; -#elif (i32_fromNaN == i32_fromNegOverflow) - sign = 1; -#else - softfloat_raiseFlags( softfloat_flag_invalid ); - return i32_fromNaN; -#endif - } -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig |= UINT64_C( 0x0010000000000000 ); - shiftDist = 0x427 - exp; - if ( 0 < shiftDist ) sig = softfloat_shiftRightJam64( sig, shiftDist ); - return softfloat_roundToI32( sign, sig, roundingMode, exact ); - -} - diff --git a/softfloat/source/f64_to_i32_r_minMag.c b/softfloat/source/f64_to_i32_r_minMag.c deleted file mode 100644 index 8b7a91f..0000000 --- a/softfloat/source/f64_to_i32_r_minMag.c +++ /dev/null @@ -1,96 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t f64_to_i32_r_minMag( float64_t a, bool exact ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - int_fast16_t exp; - uint_fast64_t sig; - int_fast16_t shiftDist; - bool sign; - int_fast32_t absZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF64UI( uiA ); - sig = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x433 - exp; - if ( 53 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF64UI( uiA ); - if ( shiftDist < 22 ) { - if ( - sign && (exp == 0x41E) && (sig < UINT64_C( 0x0000000000200000 )) - ) { - if ( exact && sig ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return -0x7FFFFFFF - 1; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FF) && sig ? i32_fromNaN - : sign ? i32_fromNegOverflow : i32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig |= UINT64_C( 0x0010000000000000 ); - absZ = sig>>shiftDist; - if ( exact && ((uint_fast64_t) (uint_fast32_t) absZ< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t f64_to_i64( float64_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool sign; - int_fast16_t exp; - uint_fast64_t sig; - int_fast16_t shiftDist; -#ifdef SOFTFLOAT_FAST_INT64 - struct uint64_extra sigExtra; -#else - uint32_t extSig[3]; -#endif - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - sig = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig |= UINT64_C( 0x0010000000000000 ); - shiftDist = 0x433 - exp; -#ifdef SOFTFLOAT_FAST_INT64 - if ( shiftDist <= 0 ) { - if ( shiftDist < -11 ) goto invalid; - sigExtra.v = sig<<-shiftDist; - sigExtra.extra = 0; - } else { - sigExtra = softfloat_shiftRightJam64Extra( sig, 0, shiftDist ); - } - return - softfloat_roundToI64( - sign, sigExtra.v, sigExtra.extra, roundingMode, exact ); -#else - extSig[indexWord( 3, 0 )] = 0; - if ( shiftDist <= 0 ) { - if ( shiftDist < -11 ) goto invalid; - sig <<= -shiftDist; - extSig[indexWord( 3, 2 )] = sig>>32; - extSig[indexWord( 3, 1 )] = sig; - } else { - extSig[indexWord( 3, 2 )] = sig>>32; - extSig[indexWord( 3, 1 )] = sig; - softfloat_shiftRightJam96M( extSig, shiftDist, extSig ); - } - return softfloat_roundMToI64( sign, extSig, roundingMode, exact ); -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FF) && fracF64UI( uiA ) ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - -} - diff --git a/softfloat/source/f64_to_i64_r_minMag.c b/softfloat/source/f64_to_i64_r_minMag.c deleted file mode 100644 index 56c6a10..0000000 --- a/softfloat/source/f64_to_i64_r_minMag.c +++ /dev/null @@ -1,100 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t f64_to_i64_r_minMag( float64_t a, bool exact ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool sign; - int_fast16_t exp; - uint_fast64_t sig; - int_fast16_t shiftDist; - int_fast64_t absZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - sig = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x433 - exp; - if ( shiftDist <= 0 ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( shiftDist < -10 ) { - if ( uiA == packToF64UI( 1, 0x43E, 0 ) ) { - return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FF) && sig ? i64_fromNaN - : sign ? i64_fromNegOverflow : i64_fromPosOverflow; - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sig |= UINT64_C( 0x0010000000000000 ); - absZ = sig<<-shiftDist; - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( 53 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sig |= UINT64_C( 0x0010000000000000 ); - absZ = sig>>shiftDist; - if ( exact && (absZ< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t f64_to_ui32( float64_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool sign; - int_fast16_t exp; - uint_fast64_t sig; - int_fast16_t shiftDist; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - sig = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ -#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow) - if ( (exp == 0x7FF) && sig ) { -#if (ui32_fromNaN == ui32_fromPosOverflow) - sign = 0; -#elif (ui32_fromNaN == ui32_fromNegOverflow) - sign = 1; -#else - softfloat_raiseFlags( softfloat_flag_invalid ); - return ui32_fromNaN; -#endif - } -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig |= UINT64_C( 0x0010000000000000 ); - shiftDist = 0x427 - exp; - if ( 0 < shiftDist ) sig = softfloat_shiftRightJam64( sig, shiftDist ); - return softfloat_roundToUI32( sign, sig, roundingMode, exact ); - -} - diff --git a/softfloat/source/f64_to_ui32_r_minMag.c b/softfloat/source/f64_to_ui32_r_minMag.c deleted file mode 100644 index 6e3d14e..0000000 --- a/softfloat/source/f64_to_ui32_r_minMag.c +++ /dev/null @@ -1,88 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t f64_to_ui32_r_minMag( float64_t a, bool exact ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - int_fast16_t exp; - uint_fast64_t sig; - int_fast16_t shiftDist; - bool sign; - uint_fast32_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF64UI( uiA ); - sig = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x433 - exp; - if ( 53 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF64UI( uiA ); - if ( sign || (shiftDist < 21) ) { - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FF) && sig ? ui32_fromNaN - : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig |= UINT64_C( 0x0010000000000000 ); - z = sig>>shiftDist; - if ( exact && ((uint_fast64_t) z< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t f64_to_ui64( float64_t a, uint_fast8_t roundingMode, bool exact ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - bool sign; - int_fast16_t exp; - uint_fast64_t sig; - int_fast16_t shiftDist; -#ifdef SOFTFLOAT_FAST_INT64 - struct uint64_extra sigExtra; -#else - uint32_t extSig[3]; -#endif - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - sign = signF64UI( uiA ); - exp = expF64UI( uiA ); - sig = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( exp ) sig |= UINT64_C( 0x0010000000000000 ); - shiftDist = 0x433 - exp; -#ifdef SOFTFLOAT_FAST_INT64 - if ( shiftDist <= 0 ) { - if ( shiftDist < -11 ) goto invalid; - sigExtra.v = sig<<-shiftDist; - sigExtra.extra = 0; - } else { - sigExtra = softfloat_shiftRightJam64Extra( sig, 0, shiftDist ); - } - return - softfloat_roundToUI64( - sign, sigExtra.v, sigExtra.extra, roundingMode, exact ); -#else - extSig[indexWord( 3, 0 )] = 0; - if ( shiftDist <= 0 ) { - if ( shiftDist < -11 ) goto invalid; - sig <<= -shiftDist; - extSig[indexWord( 3, 2 )] = sig>>32; - extSig[indexWord( 3, 1 )] = sig; - } else { - extSig[indexWord( 3, 2 )] = sig>>32; - extSig[indexWord( 3, 1 )] = sig; - softfloat_shiftRightJam96M( extSig, shiftDist, extSig ); - } - return softfloat_roundMToUI64( sign, extSig, roundingMode, exact ); -#endif - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FF) && fracF64UI( uiA ) ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - -} - diff --git a/softfloat/source/f64_to_ui64_r_minMag.c b/softfloat/source/f64_to_ui64_r_minMag.c deleted file mode 100644 index 87eb0d0..0000000 --- a/softfloat/source/f64_to_ui64_r_minMag.c +++ /dev/null @@ -1,93 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t f64_to_ui64_r_minMag( float64_t a, bool exact ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - int_fast16_t exp; - uint_fast64_t sig; - int_fast16_t shiftDist; - bool sign; - uint_fast64_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uA.f = a; - uiA = uA.ui; - exp = expF64UI( uiA ); - sig = fracF64UI( uiA ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 0x433 - exp; - if ( 53 <= shiftDist ) { - if ( exact && (exp | sig) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sign = signF64UI( uiA ); - if ( sign ) goto invalid; - if ( shiftDist <= 0 ) { - if ( shiftDist < -11 ) goto invalid; - z = (sig | UINT64_C( 0x0010000000000000 ))<<-shiftDist; - } else { - sig |= UINT64_C( 0x0010000000000000 ); - z = sig>>shiftDist; - if ( exact && (uint64_t) (sig<<(-shiftDist & 63)) ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; - } - } - return z; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return - (exp == 0x7FF) && sig ? ui64_fromNaN - : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - -} - diff --git a/softfloat/source/i32_to_extF80.c b/softfloat/source/i32_to_extF80.c deleted file mode 100644 index 8036fa9..0000000 --- a/softfloat/source/i32_to_extF80.c +++ /dev/null @@ -1,65 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -extFloat80_t i32_to_extF80( int32_t a ) -{ - uint_fast16_t uiZ64; - uint_fast32_t absA; - bool sign; - int_fast8_t shiftDist; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - uiZ64 = 0; - absA = 0; - if ( a ) { - sign = (a < 0); - absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a; - shiftDist = softfloat_countLeadingZeros32( absA ); - uiZ64 = packToExtF80UI64( sign, 0x401E - shiftDist ); - absA <<= shiftDist; - } - uZ.s.signExp = uiZ64; - uZ.s.signif = (uint_fast64_t) absA<<32; - return uZ.f; - -} - diff --git a/softfloat/source/i32_to_extF80M.c b/softfloat/source/i32_to_extF80M.c deleted file mode 100644 index 6d5431c..0000000 --- a/softfloat/source/i32_to_extF80M.c +++ /dev/null @@ -1,78 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void i32_to_extF80M( int32_t a, extFloat80_t *zPtr ) -{ - - *zPtr = i32_to_extF80( a ); - -} - -#else - -void i32_to_extF80M( int32_t a, extFloat80_t *zPtr ) -{ - struct extFloat80M *zSPtr; - uint_fast16_t uiZ64; - uint64_t sigZ; - bool sign; - uint32_t absA; - int_fast8_t shiftDist; - - zSPtr = (struct extFloat80M *) zPtr; - uiZ64 = 0; - sigZ = 0; - if ( a ) { - sign = (a < 0); - absA = sign ? -(uint32_t) a : (uint32_t) a; - shiftDist = softfloat_countLeadingZeros32( absA ); - uiZ64 = packToExtF80UI64( sign, 0x401E - shiftDist ); - sigZ = (uint64_t) (absA<signExp = uiZ64; - zSPtr->signif = sigZ; - -} - -#endif - diff --git a/softfloat/source/i32_to_f128.c b/softfloat/source/i32_to_f128.c deleted file mode 100644 index a7d55cb..0000000 --- a/softfloat/source/i32_to_f128.c +++ /dev/null @@ -1,64 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float128_t i32_to_f128( int32_t a ) -{ - uint_fast64_t uiZ64; - bool sign; - uint_fast32_t absA; - int_fast8_t shiftDist; - union ui128_f128 uZ; - - uiZ64 = 0; - if ( a ) { - sign = (a < 0); - absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a; - shiftDist = softfloat_countLeadingZeros32( absA ) + 17; - uiZ64 = - packToF128UI64( - sign, 0x402E - shiftDist, (uint_fast64_t) absA< -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void i32_to_f128M( int32_t a, float128_t *zPtr ) -{ - - *zPtr = i32_to_f128( a ); - -} - -#else - -void i32_to_f128M( int32_t a, float128_t *zPtr ) -{ - uint32_t *zWPtr; - uint32_t uiZ96, uiZ64; - bool sign; - uint32_t absA; - int_fast8_t shiftDist; - uint64_t normAbsA; - - zWPtr = (uint32_t *) zPtr; - uiZ96 = 0; - uiZ64 = 0; - if ( a ) { - sign = (a < 0); - absA = sign ? -(uint32_t) a : (uint32_t) a; - shiftDist = softfloat_countLeadingZeros32( absA ) + 17; - normAbsA = (uint64_t) absA<>32 ); - uiZ64 = normAbsA; - } - zWPtr[indexWord( 4, 3 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = uiZ64; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - -} - -#endif - diff --git a/softfloat/source/i32_to_f16.c b/softfloat/source/i32_to_f16.c deleted file mode 100644 index d311724..0000000 --- a/softfloat/source/i32_to_f16.c +++ /dev/null @@ -1,71 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float16_t i32_to_f16( int32_t a ) -{ - bool sign; - uint_fast32_t absA; - int_fast8_t shiftDist; - union ui16_f16 u; - uint_fast16_t sig; - - sign = (a < 0); - absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a; - shiftDist = softfloat_countLeadingZeros32( absA ) - 21; - if ( 0 <= shiftDist ) { - u.ui = - a ? packToF16UI( - sign, 0x18 - shiftDist, (uint_fast16_t) absA<>(-shiftDist) - | ((uint32_t) (absA<<(shiftDist & 31)) != 0) - : (uint_fast16_t) absA< -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float32_t i32_to_f32( int32_t a ) -{ - bool sign; - union ui32_f32 uZ; - uint_fast32_t absA; - - sign = (a < 0); - if ( ! (a & 0x7FFFFFFF) ) { - uZ.ui = sign ? packToF32UI( 1, 0x9E, 0 ) : 0; - return uZ.f; - } - absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a; - return softfloat_normRoundPackToF32( sign, 0x9C, absA ); - -} - diff --git a/softfloat/source/i32_to_f64.c b/softfloat/source/i32_to_f64.c deleted file mode 100644 index 24feda5..0000000 --- a/softfloat/source/i32_to_f64.c +++ /dev/null @@ -1,65 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float64_t i32_to_f64( int32_t a ) -{ - uint_fast64_t uiZ; - bool sign; - uint_fast32_t absA; - int_fast8_t shiftDist; - union ui64_f64 uZ; - - if ( ! a ) { - uiZ = 0; - } else { - sign = (a < 0); - absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a; - shiftDist = softfloat_countLeadingZeros32( absA ) + 21; - uiZ = - packToF64UI( - sign, 0x432 - shiftDist, (uint_fast64_t) absA< -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -extFloat80_t i64_to_extF80( int64_t a ) -{ - uint_fast16_t uiZ64; - uint_fast64_t absA; - bool sign; - int_fast8_t shiftDist; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - uiZ64 = 0; - absA = 0; - if ( a ) { - sign = (a < 0); - absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a; - shiftDist = softfloat_countLeadingZeros64( absA ); - uiZ64 = packToExtF80UI64( sign, 0x403E - shiftDist ); - absA <<= shiftDist; - } - uZ.s.signExp = uiZ64; - uZ.s.signif = absA; - return uZ.f; - -} - diff --git a/softfloat/source/i64_to_extF80M.c b/softfloat/source/i64_to_extF80M.c deleted file mode 100644 index 4838dde..0000000 --- a/softfloat/source/i64_to_extF80M.c +++ /dev/null @@ -1,78 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void i64_to_extF80M( int64_t a, extFloat80_t *zPtr ) -{ - - *zPtr = i64_to_extF80( a ); - -} - -#else - -void i64_to_extF80M( int64_t a, extFloat80_t *zPtr ) -{ - struct extFloat80M *zSPtr; - uint_fast16_t uiZ64; - uint64_t sigZ; - bool sign; - uint64_t absA; - int_fast8_t shiftDist; - - zSPtr = (struct extFloat80M *) zPtr; - uiZ64 = 0; - sigZ = 0; - if ( a ) { - sign = (a < 0); - absA = sign ? -(uint64_t) a : (uint64_t) a; - shiftDist = softfloat_countLeadingZeros64( absA ); - uiZ64 = packToExtF80UI64( sign, 0x403E - shiftDist ); - sigZ = absA<signExp = uiZ64; - zSPtr->signif = sigZ; - -} - -#endif - diff --git a/softfloat/source/i64_to_f128.c b/softfloat/source/i64_to_f128.c deleted file mode 100644 index fcb0179..0000000 --- a/softfloat/source/i64_to_f128.c +++ /dev/null @@ -1,72 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float128_t i64_to_f128( int64_t a ) -{ - uint_fast64_t uiZ64, uiZ0; - bool sign; - uint_fast64_t absA; - int_fast8_t shiftDist; - struct uint128 zSig; - union ui128_f128 uZ; - - if ( ! a ) { - uiZ64 = 0; - uiZ0 = 0; - } else { - sign = (a < 0); - absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a; - shiftDist = softfloat_countLeadingZeros64( absA ) + 49; - if ( 64 <= shiftDist ) { - zSig.v64 = absA<<(shiftDist - 64); - zSig.v0 = 0; - } else { - zSig = softfloat_shortShiftLeft128( 0, absA, shiftDist ); - } - uiZ64 = packToF128UI64( sign, 0x406E - shiftDist, zSig.v64 ); - uiZ0 = zSig.v0; - } - uZ.ui.v64 = uiZ64; - uZ.ui.v0 = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/i64_to_f128M.c b/softfloat/source/i64_to_f128M.c deleted file mode 100644 index 0a04eb8..0000000 --- a/softfloat/source/i64_to_f128M.c +++ /dev/null @@ -1,92 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void i64_to_f128M( int64_t a, float128_t *zPtr ) -{ - - *zPtr = i64_to_f128( a ); - -} - -#else - -void i64_to_f128M( int64_t a, float128_t *zPtr ) -{ - uint32_t *zWPtr; - uint32_t uiZ96, uiZ64; - bool sign; - uint64_t absA; - uint_fast8_t shiftDist; - uint32_t *ptr; - - zWPtr = (uint32_t *) zPtr; - uiZ96 = 0; - uiZ64 = 0; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - if ( a ) { - sign = (a < 0); - absA = sign ? -(uint64_t) a : (uint64_t) a; - shiftDist = softfloat_countLeadingZeros64( absA ) + 17; - if ( shiftDist < 32 ) { - ptr = zWPtr + indexMultiwordHi( 4, 3 ); - ptr[indexWord( 3, 2 )] = 0; - ptr[indexWord( 3, 1 )] = absA>>32; - ptr[indexWord( 3, 0 )] = absA; - softfloat_shortShiftLeft96M( ptr, shiftDist, ptr ); - ptr[indexWordHi( 3 )] = - packToF128UI96( - sign, 0x404E - shiftDist, ptr[indexWordHi( 3 )] ); - return; - } - absA <<= shiftDist - 32; - uiZ96 = packToF128UI96( sign, 0x404E - shiftDist, absA>>32 ); - uiZ64 = absA; - } - zWPtr[indexWord( 4, 3 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = uiZ64; - -} - -#endif - diff --git a/softfloat/source/i64_to_f16.c b/softfloat/source/i64_to_f16.c deleted file mode 100644 index cef7b61..0000000 --- a/softfloat/source/i64_to_f16.c +++ /dev/null @@ -1,70 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float16_t i64_to_f16( int64_t a ) -{ - bool sign; - uint_fast64_t absA; - int_fast8_t shiftDist; - union ui16_f16 u; - uint_fast16_t sig; - - sign = (a < 0); - absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a; - shiftDist = softfloat_countLeadingZeros64( absA ) - 53; - if ( 0 <= shiftDist ) { - u.ui = - a ? packToF16UI( - sign, 0x18 - shiftDist, (uint_fast16_t) absA< -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float32_t i64_to_f32( int64_t a ) -{ - bool sign; - uint_fast64_t absA; - int_fast8_t shiftDist; - union ui32_f32 u; - uint_fast32_t sig; - - sign = (a < 0); - absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a; - shiftDist = softfloat_countLeadingZeros64( absA ) - 40; - if ( 0 <= shiftDist ) { - u.ui = - a ? packToF32UI( - sign, 0x95 - shiftDist, (uint_fast32_t) absA< -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float64_t i64_to_f64( int64_t a ) -{ - bool sign; - union ui64_f64 uZ; - uint_fast64_t absA; - - sign = (a < 0); - if ( ! (a & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) { - uZ.ui = sign ? packToF64UI( 1, 0x43E, 0 ) : 0; - return uZ.f; - } - absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a; - return softfloat_normRoundPackToF64( sign, 0x43C, absA ); - -} - diff --git a/softfloat/source/include/internals.h b/softfloat/source/include/internals.h deleted file mode 100644 index be7c875..0000000 --- a/softfloat/source/include/internals.h +++ /dev/null @@ -1,257 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#ifndef internals_h -#define internals_h 1 - -#include "primitives.h" -#include "softfloat_types.h" -#include -#include - -union ui16_f16 { - uint16_t ui; - float16_t f; -}; -union ui16_bf16 { - uint16_t ui; - bfloat16_t f; -}; -union ui32_f32 { - uint32_t ui; - float32_t f; -}; -union ui64_f64 { - uint64_t ui; - float64_t f; -}; - -#ifdef SOFTFLOAT_FAST_INT64 -union extF80M_extF80 { - struct extFloat80M fM; - extFloat80_t f; -}; -union ui128_f128 { - struct uint128 ui; - float128_t f; -}; -#endif - -enum { softfloat_mulAdd_subC = 1, softfloat_mulAdd_subProd = 2 }; - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_roundToUI32(bool, uint_fast64_t, uint_fast8_t, bool); - -#ifdef SOFTFLOAT_FAST_INT64 -uint_fast64_t softfloat_roundToUI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool); -#else -uint_fast64_t softfloat_roundMToUI64(bool, uint32_t*, uint_fast8_t, bool); -#endif - -int_fast32_t softfloat_roundToI32(bool, uint_fast64_t, uint_fast8_t, bool); - -#ifdef SOFTFLOAT_FAST_INT64 -int_fast64_t softfloat_roundToI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool); -#else -int_fast64_t softfloat_roundMToI64(bool, uint32_t*, uint_fast8_t, bool); -#endif - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -#define signF16UI(a) ((bool)((uint16_t)(a) >> 15)) -#define expF16UI(a) ((int_fast8_t)((a) >> 10) & 0x1F) -#define fracF16UI(a) ((a)&0x03FF) -#define packToF16UI(sign, exp, sig) (((uint16_t)(sign) << 15) + ((uint16_t)(exp) << 10) + (sig)) - -#define isNaNF16UI(a) (((~(a)&0x7C00) == 0) && ((a)&0x03FF)) - -struct exp8_sig16 { - int_fast8_t exp; - uint_fast16_t sig; -}; -struct exp8_sig16 softfloat_normSubnormalF16Sig(uint_fast16_t); - -float16_t softfloat_roundPackToF16(bool, int_fast16_t, uint_fast16_t); -float16_t softfloat_normRoundPackToF16(bool, int_fast16_t, uint_fast16_t); - -float16_t softfloat_addMagsF16(uint_fast16_t, uint_fast16_t); -float16_t softfloat_subMagsF16(uint_fast16_t, uint_fast16_t); -float16_t softfloat_mulAddF16(uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t); - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -#define signBF16UI(a) ((bool)((uint16_t)(a) >> 15)) -#define expBF16UI(a) ((int_fast16_t)((a) >> 7) & 0xFF) -#define fracBF16UI(a) ((a)&0x07F) -#define packToBF16UI(sign, exp, sig) (((uint16_t)(sign) << 15) + ((uint16_t)(exp) << 7) + (sig)) - -#define isNaNBF16UI(a) (((~(a)&0x7FC0) == 0) && ((a)&0x07F)) - -bfloat16_t softfloat_roundPackToBF16(bool, int_fast16_t, uint_fast16_t); -struct exp8_sig16 softfloat_normSubnormalBF16Sig(uint_fast16_t); - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -#define signF32UI(a) ((bool)((uint32_t)(a) >> 31)) -#define expF32UI(a) ((int_fast16_t)((a) >> 23) & 0xFF) -#define fracF32UI(a) ((a)&0x007FFFFF) -#define packToF32UI(sign, exp, sig) (((uint32_t)(sign) << 31) + ((uint32_t)(exp) << 23) + (sig)) - -#define isNaNF32UI(a) (((~(a)&0x7F800000) == 0) && ((a)&0x007FFFFF)) - -struct exp16_sig32 { - int_fast16_t exp; - uint_fast32_t sig; -}; -struct exp16_sig32 softfloat_normSubnormalF32Sig(uint_fast32_t); - -float32_t softfloat_roundPackToF32(bool, int_fast16_t, uint_fast32_t); -float32_t softfloat_normRoundPackToF32(bool, int_fast16_t, uint_fast32_t); - -float32_t softfloat_addMagsF32(uint_fast32_t, uint_fast32_t); -float32_t softfloat_subMagsF32(uint_fast32_t, uint_fast32_t); -float32_t softfloat_mulAddF32(uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t); - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -#define signF64UI(a) ((bool)((uint64_t)(a) >> 63)) -#define expF64UI(a) ((int_fast16_t)((a) >> 52) & 0x7FF) -#define fracF64UI(a) ((a)&UINT64_C(0x000FFFFFFFFFFFFF)) -#define packToF64UI(sign, exp, sig) ((uint64_t)(((uint_fast64_t)(sign) << 63) + ((uint_fast64_t)(exp) << 52) + (sig))) - -#define isNaNF64UI(a) (((~(a)&UINT64_C(0x7FF0000000000000)) == 0) && ((a)&UINT64_C(0x000FFFFFFFFFFFFF))) - -struct exp16_sig64 { - int_fast16_t exp; - uint_fast64_t sig; -}; -struct exp16_sig64 softfloat_normSubnormalF64Sig(uint_fast64_t); - -float64_t softfloat_roundPackToF64(bool, int_fast16_t, uint_fast64_t); -float64_t softfloat_normRoundPackToF64(bool, int_fast16_t, uint_fast64_t); - -float64_t softfloat_addMagsF64(uint_fast64_t, uint_fast64_t, bool); -float64_t softfloat_subMagsF64(uint_fast64_t, uint_fast64_t, bool); -float64_t softfloat_mulAddF64(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t); - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -#define signExtF80UI64(a64) ((bool)((uint16_t)(a64) >> 15)) -#define expExtF80UI64(a64) ((a64)&0x7FFF) -#define packToExtF80UI64(sign, exp) ((uint_fast16_t)(sign) << 15 | (exp)) - -#define isNaNExtF80UI(a64, a0) ((((a64)&0x7FFF) == 0x7FFF) && ((a0)&UINT64_C(0x7FFFFFFFFFFFFFFF))) - -#ifdef SOFTFLOAT_FAST_INT64 - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ - -struct exp32_sig64 { - int_fast32_t exp; - uint64_t sig; -}; -struct exp32_sig64 softfloat_normSubnormalExtF80Sig(uint_fast64_t); - -extFloat80_t softfloat_roundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t); -extFloat80_t softfloat_normRoundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t); - -extFloat80_t softfloat_addMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool); -extFloat80_t softfloat_subMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool); - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -#define signF128UI64(a64) ((bool)((uint64_t)(a64) >> 63)) -#define expF128UI64(a64) ((int_fast32_t)((a64) >> 48) & 0x7FFF) -#define fracF128UI64(a64) ((a64)&UINT64_C(0x0000FFFFFFFFFFFF)) -#define packToF128UI64(sign, exp, sig64) (((uint_fast64_t)(sign) << 63) + ((uint_fast64_t)(exp) << 48) + (sig64)) - -#define isNaNF128UI(a64, a0) (((~(a64)&UINT64_C(0x7FFF000000000000)) == 0) && (a0 || ((a64)&UINT64_C(0x0000FFFFFFFFFFFF)))) - -struct exp32_sig128 { - int_fast32_t exp; - struct uint128 sig; -}; -struct exp32_sig128 softfloat_normSubnormalF128Sig(uint_fast64_t, uint_fast64_t); - -float128_t softfloat_roundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t); -float128_t softfloat_normRoundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t); - -float128_t softfloat_addMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool); -float128_t softfloat_subMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool); -float128_t softfloat_mulAddF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t); - -#else - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ - -bool softfloat_tryPropagateNaNExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*); -void softfloat_invalidExtF80M(struct extFloat80M*); - -int softfloat_normExtF80SigM(uint64_t*); - -void softfloat_roundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*); -void softfloat_normRoundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*); - -void softfloat_addExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*, bool); - -int softfloat_compareNonnormExtF80M(const struct extFloat80M*, const struct extFloat80M*); - -/*---------------------------------------------------------------------------- - *----------------------------------------------------------------------------*/ -#define signF128UI96(a96) ((bool)((uint32_t)(a96) >> 31)) -#define expF128UI96(a96) ((int32_t)((a96) >> 16) & 0x7FFF) -#define fracF128UI96(a96) ((a96)&0x0000FFFF) -#define packToF128UI96(sign, exp, sig96) (((uint32_t)(sign) << 31) + ((uint32_t)(exp) << 16) + (sig96)) - -bool softfloat_isNaNF128M(const uint32_t*); - -bool softfloat_tryPropagateNaNF128M(const uint32_t*, const uint32_t*, uint32_t*); -void softfloat_invalidF128M(uint32_t*); - -int softfloat_shiftNormSigF128M(const uint32_t*, uint_fast8_t, uint32_t*); - -void softfloat_roundPackMToF128M(bool, int32_t, uint32_t*, uint32_t*); -void softfloat_normRoundPackMToF128M(bool, int32_t, uint32_t*, uint32_t*); - -void softfloat_addF128M(const uint32_t*, const uint32_t*, uint32_t*, bool); -void softfloat_mulAddF128M(const uint32_t*, const uint32_t*, const uint32_t*, uint32_t*, uint_fast8_t); - -#endif - -#endif diff --git a/softfloat/source/include/opts-GCC.h b/softfloat/source/include/opts-GCC.h deleted file mode 100644 index 99a4127..0000000 --- a/softfloat/source/include/opts-GCC.h +++ /dev/null @@ -1,113 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2017 The Regents of the University of California. All rights -reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#ifndef opts_GCC_h -#define opts_GCC_h 1 - -#ifdef INLINE - -#include "primitiveTypes.h" -#include - -#ifdef SOFTFLOAT_BUILTIN_CLZ - -INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) { return a ? __builtin_clz(a) - 16 : 16; } -#define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16 - -INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) { return a ? __builtin_clz(a) : 32; } -#define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32 - -INLINE uint_fast8_t softfloat_countLeadingZeros64(uint64_t a) { return a ? __builtin_clzll(a) : 64; } -#define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64 - -#endif - -#ifdef SOFTFLOAT_INTRINSIC_INT128 - -INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) { - union { - unsigned __int128 ui; - struct uint128 s; - } uZ; - uZ.ui = (unsigned __int128)a * ((uint_fast64_t)b << 32); - return uZ.s; -} -#define softfloat_mul64ByShifted32To128 softfloat_mul64ByShifted32To128 - -INLINE struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b) { - union { - unsigned __int128 ui; - struct uint128 s; - } uZ; - uZ.ui = (unsigned __int128)a * b; - return uZ.s; -} -#define softfloat_mul64To128 softfloat_mul64To128 - -INLINE -struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) { - union { - unsigned __int128 ui; - struct uint128 s; - } uZ; - uZ.ui = ((unsigned __int128)a64 << 64 | a0) * b; - return uZ.s; -} -#define softfloat_mul128By32 softfloat_mul128By32 - -INLINE -void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr) { - unsigned __int128 z0, mid1, mid, z128; - z0 = (unsigned __int128)a0 * b0; - mid1 = (unsigned __int128)a64 * b0; - mid = mid1 + (unsigned __int128)a0 * b64; - z128 = (unsigned __int128)a64 * b64; - z128 += (unsigned __int128)(mid < mid1) << 64 | mid >> 64; - mid <<= 64; - z0 += mid; - z128 += (z0 < mid); - zPtr[indexWord(4, 0)] = z0; - zPtr[indexWord(4, 1)] = z0 >> 64; - zPtr[indexWord(4, 2)] = z128; - zPtr[indexWord(4, 3)] = z128 >> 64; -} -#define softfloat_mul128To256M softfloat_mul128To256M - -#endif - -#endif - -#endif diff --git a/softfloat/source/include/primitiveTypes.h b/softfloat/source/include/primitiveTypes.h deleted file mode 100644 index b8348e3..0000000 --- a/softfloat/source/include/primitiveTypes.h +++ /dev/null @@ -1,100 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#ifndef primitiveTypes_h -#define primitiveTypes_h 1 - -#include - -#ifdef SOFTFLOAT_FAST_INT64 - -#ifdef LITTLEENDIAN -struct uint128 { - uint64_t v0, v64; -}; -struct uint64_extra { - uint64_t extra, v; -}; -struct uint128_extra { - uint64_t extra; - struct uint128 v; -}; -#else -struct uint128 { - uint64_t v64, v0; -}; -struct uint64_extra { - uint64_t v, extra; -}; -struct uint128_extra { - struct uint128 v; - uint64_t extra; -}; -#endif - -#endif - -/*---------------------------------------------------------------------------- -| These macros are used to isolate the differences in word order between big- -| endian and little-endian platforms. -*----------------------------------------------------------------------------*/ -#ifdef LITTLEENDIAN -#define wordIncr 1 -#define indexWord(total, n) (n) -#define indexWordHi(total) ((total)-1) -#define indexWordLo(total) 0 -#define indexMultiword(total, m, n) (n) -#define indexMultiwordHi(total, n) ((total) - (n)) -#define indexMultiwordLo(total, n) 0 -#define indexMultiwordHiBut(total, n) (n) -#define indexMultiwordLoBut(total, n) 0 -#define INIT_UINTM4(v3, v2, v1, v0) \ - { v0, v1, v2, v3 } -#else -#define wordIncr -1 -#define indexWord(total, n) ((total)-1 - (n)) -#define indexWordHi(total) 0 -#define indexWordLo(total) ((total)-1) -#define indexMultiword(total, m, n) ((total)-1 - (m)) -#define indexMultiwordHi(total, n) 0 -#define indexMultiwordLo(total, n) ((total) - (n)) -#define indexMultiwordHiBut(total, n) 0 -#define indexMultiwordLoBut(total, n) (n) -#define INIT_UINTM4(v3, v2, v1, v0) \ - { v3, v2, v1, v0 } -#endif - -#endif diff --git a/softfloat/source/include/primitives.h b/softfloat/source/include/primitives.h deleted file mode 100644 index 48c2596..0000000 --- a/softfloat/source/include/primitives.h +++ /dev/null @@ -1,1030 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#ifndef primitives_h -#define primitives_h 1 - -#include "primitiveTypes.h" -#include -#include - -#ifndef softfloat_shortShiftRightJam64 -/*---------------------------------------------------------------------------- -| Shifts 'a' right by the number of bits given in 'dist', which must be in -| the range 1 to 63. If any nonzero bits are shifted off, they are "jammed" -| into the least-significant bit of the shifted value by setting the least- -| significant bit to 1. This shifted-and-jammed value is returned. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE -uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist) { return a >> dist | ((a & (((uint_fast64_t)1 << dist) - 1)) != 0); } -#else -uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist); -#endif -#endif - -#ifndef softfloat_shiftRightJam32 -/*---------------------------------------------------------------------------- -| Shifts 'a' right by the number of bits given in 'dist', which must not -| be zero. If any nonzero bits are shifted off, they are "jammed" into the -| least-significant bit of the shifted value by setting the least-significant -| bit to 1. This shifted-and-jammed value is returned. -| The value of 'dist' can be arbitrarily large. In particular, if 'dist' is -| greater than 32, the result will be either 0 or 1, depending on whether 'a' -| is zero or nonzero. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist) { - return (dist < 31) ? a >> dist | ((uint32_t)(a << (-dist & 31)) != 0) : (a != 0); -} -#else -uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist); -#endif -#endif - -#ifndef softfloat_shiftRightJam64 -/*---------------------------------------------------------------------------- -| Shifts 'a' right by the number of bits given in 'dist', which must not -| be zero. If any nonzero bits are shifted off, they are "jammed" into the -| least-significant bit of the shifted value by setting the least-significant -| bit to 1. This shifted-and-jammed value is returned. -| The value of 'dist' can be arbitrarily large. In particular, if 'dist' is -| greater than 64, the result will be either 0 or 1, depending on whether 'a' -| is zero or nonzero. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) -INLINE uint64_t softfloat_shiftRightJam64(uint64_t a, uint_fast32_t dist) { - return (dist < 63) ? a >> dist | ((uint64_t)(a << (-dist & 63)) != 0) : (a != 0); -} -#else -uint64_t softfloat_shiftRightJam64(uint64_t a, uint_fast32_t dist); -#endif -#endif - -/*---------------------------------------------------------------------------- -| A constant table that translates an 8-bit unsigned integer (the array index) -| into the number of leading 0 bits before the most-significant 1 of that -| integer. For integer zero (index 0), the corresponding table element is 8. -*----------------------------------------------------------------------------*/ -extern const uint_least8_t softfloat_countLeadingZeros8[256]; - -#ifndef softfloat_countLeadingZeros16 -/*---------------------------------------------------------------------------- -| Returns the number of leading 0 bits before the most-significant 1 bit of -| 'a'. If 'a' is zero, 16 is returned. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) { - uint_fast8_t count = 8; - if(0x100 <= a) { - count = 0; - a >>= 8; - } - count += softfloat_countLeadingZeros8[a]; - return count; -} -#else -uint_fast8_t softfloat_countLeadingZeros16(uint16_t a); -#endif -#endif - -#ifndef softfloat_countLeadingZeros32 -/*---------------------------------------------------------------------------- -| Returns the number of leading 0 bits before the most-significant 1 bit of -| 'a'. If 'a' is zero, 32 is returned. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) -INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) { - uint_fast8_t count = 0; - if(a < 0x10000) { - count = 16; - a <<= 16; - } - if(a < 0x1000000) { - count += 8; - a <<= 8; - } - count += softfloat_countLeadingZeros8[a >> 24]; - return count; -} -#else -uint_fast8_t softfloat_countLeadingZeros32(uint32_t a); -#endif -#endif - -#ifndef softfloat_countLeadingZeros64 -/*---------------------------------------------------------------------------- -| Returns the number of leading 0 bits before the most-significant 1 bit of -| 'a'. If 'a' is zero, 64 is returned. -*----------------------------------------------------------------------------*/ -uint_fast8_t softfloat_countLeadingZeros64(uint64_t a); -#endif - -extern const uint16_t softfloat_approxRecip_1k0s[16]; -extern const uint16_t softfloat_approxRecip_1k1s[16]; - -#ifndef softfloat_approxRecip32_1 -/*---------------------------------------------------------------------------- -| Returns an approximation to the reciprocal of the number represented by 'a', -| where 'a' is interpreted as an unsigned fixed-point number with one integer -| bit and 31 fraction bits. The 'a' input must be "normalized", meaning that -| its most-significant bit (bit 31) must be 1. Thus, if A is the value of -| the fixed-point interpretation of 'a', then 1 <= A < 2. The returned value -| is interpreted as a pure unsigned fraction, having no integer bits and 32 -| fraction bits. The approximation returned is never greater than the true -| reciprocal 1/A, and it differs from the true reciprocal by at most 2.006 ulp -| (units in the last place). -*----------------------------------------------------------------------------*/ -#ifdef SOFTFLOAT_FAST_DIV64TO32 -#define softfloat_approxRecip32_1(a) ((uint32_t)(UINT64_C(0x7FFFFFFFFFFFFFFF) / (uint32_t)(a))) -#else -uint32_t softfloat_approxRecip32_1(uint32_t a); -#endif -#endif - -extern const uint16_t softfloat_approxRecipSqrt_1k0s[16]; -extern const uint16_t softfloat_approxRecipSqrt_1k1s[16]; - -#ifndef softfloat_approxRecipSqrt32_1 -/*---------------------------------------------------------------------------- -| Returns an approximation to the reciprocal of the square root of the number -| represented by 'a', where 'a' is interpreted as an unsigned fixed-point -| number either with one integer bit and 31 fraction bits or with two integer -| bits and 30 fraction bits. The format of 'a' is determined by 'oddExpA', -| which must be either 0 or 1. If 'oddExpA' is 1, 'a' is interpreted as -| having one integer bit, and if 'oddExpA' is 0, 'a' is interpreted as having -| two integer bits. The 'a' input must be "normalized", meaning that its -| most-significant bit (bit 31) must be 1. Thus, if A is the value of the -| fixed-point interpretation of 'a', it follows that 1 <= A < 2 when 'oddExpA' -| is 1, and 2 <= A < 4 when 'oddExpA' is 0. -| The returned value is interpreted as a pure unsigned fraction, having -| no integer bits and 32 fraction bits. The approximation returned is never -| greater than the true reciprocal 1/sqrt(A), and it differs from the true -| reciprocal by at most 2.06 ulp (units in the last place). The approximation -| returned is also always within the range 0.5 to 1; thus, the most- -| significant bit of the result is always set. -*----------------------------------------------------------------------------*/ -uint32_t softfloat_approxRecipSqrt32_1(unsigned int oddExpA, uint32_t a); -#endif - -#ifdef SOFTFLOAT_FAST_INT64 - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is -| defined. -*----------------------------------------------------------------------------*/ - -#ifndef softfloat_eq128 -/*---------------------------------------------------------------------------- -| Returns true if the 128-bit unsigned integer formed by concatenating 'a64' -| and 'a0' is equal to the 128-bit unsigned integer formed by concatenating -| 'b64' and 'b0'. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) -INLINE -bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 == b64) && (a0 == b0); } -#else -bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0); -#endif -#endif - -#ifndef softfloat_le128 -/*---------------------------------------------------------------------------- -| Returns true if the 128-bit unsigned integer formed by concatenating 'a64' -| and 'a0' is less than or equal to the 128-bit unsigned integer formed by -| concatenating 'b64' and 'b0'. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE -bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); } -#else -bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0); -#endif -#endif - -#ifndef softfloat_lt128 -/*---------------------------------------------------------------------------- -| Returns true if the 128-bit unsigned integer formed by concatenating 'a64' -| and 'a0' is less than the 128-bit unsigned integer formed by concatenating -| 'b64' and 'b0'. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE -bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); } -#else -bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0); -#endif -#endif - -#ifndef softfloat_shortShiftLeft128 -/*---------------------------------------------------------------------------- -| Shifts the 128 bits formed by concatenating 'a64' and 'a0' left by the -| number of bits given in 'dist', which must be in the range 1 to 63. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE -struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist) { - struct uint128 z; - z.v64 = a64 << dist | a0 >> (-dist & 63); - z.v0 = a0 << dist; - return z; -} -#else -struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist); -#endif -#endif - -#ifndef softfloat_shortShiftRight128 -/*---------------------------------------------------------------------------- -| Shifts the 128 bits formed by concatenating 'a64' and 'a0' right by the -| number of bits given in 'dist', which must be in the range 1 to 63. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE -struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist) { - struct uint128 z; - z.v64 = a64 >> dist; - z.v0 = a64 << (-dist & 63) | a0 >> dist; - return z; -} -#else -struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist); -#endif -#endif - -#ifndef softfloat_shortShiftRightJam64Extra -/*---------------------------------------------------------------------------- -| This function is the same as 'softfloat_shiftRightJam64Extra' (below), -| except that 'dist' must be in the range 1 to 63. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE -struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist) { - struct uint64_extra z; - z.v = a >> dist; - z.extra = a << (-dist & 63) | (extra != 0); - return z; -} -#else -struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist); -#endif -#endif - -#ifndef softfloat_shortShiftRightJam128 -/*---------------------------------------------------------------------------- -| Shifts the 128 bits formed by concatenating 'a64' and 'a0' right by the -| number of bits given in 'dist', which must be in the range 1 to 63. If any -| nonzero bits are shifted off, they are "jammed" into the least-significant -| bit of the shifted value by setting the least-significant bit to 1. This -| shifted-and-jammed value is returned. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) -INLINE -struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist) { - uint_fast8_t negDist = -dist; - struct uint128 z; - z.v64 = a64 >> dist; - z.v0 = a64 << (negDist & 63) | a0 >> dist | ((uint64_t)(a0 << (negDist & 63)) != 0); - return z; -} -#else -struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist); -#endif -#endif - -#ifndef softfloat_shortShiftRightJam128Extra -/*---------------------------------------------------------------------------- -| This function is the same as 'softfloat_shiftRightJam128Extra' (below), -| except that 'dist' must be in the range 1 to 63. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) -INLINE -struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist) { - uint_fast8_t negDist = -dist; - struct uint128_extra z; - z.v.v64 = a64 >> dist; - z.v.v0 = a64 << (negDist & 63) | a0 >> dist; - z.extra = a0 << (negDist & 63) | (extra != 0); - return z; -} -#else -struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist); -#endif -#endif - -#ifndef softfloat_shiftRightJam64Extra -/*---------------------------------------------------------------------------- -| Shifts the 128 bits formed by concatenating 'a' and 'extra' right by 64 -| _plus_ the number of bits given in 'dist', which must not be zero. This -| shifted value is at most 64 nonzero bits and is returned in the 'v' field -| of the 'struct uint64_extra' result. The 64-bit 'extra' field of the result -| contains a value formed as follows from the bits that were shifted off: The -| _last_ bit shifted off is the most-significant bit of the 'extra' field, and -| the other 63 bits of the 'extra' field are all zero if and only if _all_but_ -| _the_last_ bits shifted off were all zero. -| (This function makes more sense if 'a' and 'extra' are considered to form -| an unsigned fixed-point number with binary point between 'a' and 'extra'. -| This fixed-point value is shifted right by the number of bits given in -| 'dist', and the integer part of this shifted value is returned in the 'v' -| field of the result. The fractional part of the shifted value is modified -| as described above and returned in the 'extra' field of the result.) -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (4 <= INLINE_LEVEL) -INLINE -struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist) { - struct uint64_extra z; - if(dist < 64) { - z.v = a >> dist; - z.extra = a << (-dist & 63); - } else { - z.v = 0; - z.extra = (dist == 64) ? a : (a != 0); - } - z.extra |= (extra != 0); - return z; -} -#else -struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist); -#endif -#endif - -#ifndef softfloat_shiftRightJam128 -/*---------------------------------------------------------------------------- -| Shifts the 128 bits formed by concatenating 'a64' and 'a0' right by the -| number of bits given in 'dist', which must not be zero. If any nonzero bits -| are shifted off, they are "jammed" into the least-significant bit of the -| shifted value by setting the least-significant bit to 1. This shifted-and- -| jammed value is returned. -| The value of 'dist' can be arbitrarily large. In particular, if 'dist' is -| greater than 128, the result will be either 0 or 1, depending on whether the -| original 128 bits are all zeros. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_shiftRightJam128(uint64_t a64, uint64_t a0, uint_fast32_t dist); -#endif - -#ifndef softfloat_shiftRightJam128Extra -/*---------------------------------------------------------------------------- -| Shifts the 192 bits formed by concatenating 'a64', 'a0', and 'extra' right -| by 64 _plus_ the number of bits given in 'dist', which must not be zero. -| This shifted value is at most 128 nonzero bits and is returned in the 'v' -| field of the 'struct uint128_extra' result. The 64-bit 'extra' field of the -| result contains a value formed as follows from the bits that were shifted -| off: The _last_ bit shifted off is the most-significant bit of the 'extra' -| field, and the other 63 bits of the 'extra' field are all zero if and only -| if _all_but_the_last_ bits shifted off were all zero. -| (This function makes more sense if 'a64', 'a0', and 'extra' are considered -| to form an unsigned fixed-point number with binary point between 'a0' and -| 'extra'. This fixed-point value is shifted right by the number of bits -| given in 'dist', and the integer part of this shifted value is returned -| in the 'v' field of the result. The fractional part of the shifted value -| is modified as described above and returned in the 'extra' field of the -| result.) -*----------------------------------------------------------------------------*/ -struct uint128_extra softfloat_shiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist); -#endif - -#ifndef softfloat_shiftRightJam256M -/*---------------------------------------------------------------------------- -| Shifts the 256-bit unsigned integer pointed to by 'aPtr' right by the number -| of bits given in 'dist', which must not be zero. If any nonzero bits are -| shifted off, they are "jammed" into the least-significant bit of the shifted -| value by setting the least-significant bit to 1. This shifted-and-jammed -| value is stored at the location pointed to by 'zPtr'. Each of 'aPtr' and -| 'zPtr' points to an array of four 64-bit elements that concatenate in the -| platform's normal endian order to form a 256-bit integer. -| The value of 'dist' can be arbitrarily large. In particular, if 'dist' -| is greater than 256, the stored result will be either 0 or 1, depending on -| whether the original 256 bits are all zeros. -*----------------------------------------------------------------------------*/ -void softfloat_shiftRightJam256M(const uint64_t* aPtr, uint_fast32_t dist, uint64_t* zPtr); -#endif - -#ifndef softfloat_add128 -/*---------------------------------------------------------------------------- -| Returns the sum of the 128-bit integer formed by concatenating 'a64' and -| 'a0' and the 128-bit integer formed by concatenating 'b64' and 'b0'. The -| addition is modulo 2^128, so any carry out is lost. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE -struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { - struct uint128 z; - z.v0 = a0 + b0; - z.v64 = a64 + b64 + (z.v0 < a0); - return z; -} -#else -struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0); -#endif -#endif - -#ifndef softfloat_add256M -/*---------------------------------------------------------------------------- -| Adds the two 256-bit integers pointed to by 'aPtr' and 'bPtr'. The addition -| is modulo 2^256, so any carry out is lost. The sum is stored at the -| location pointed to by 'zPtr'. Each of 'aPtr', 'bPtr', and 'zPtr' points to -| an array of four 64-bit elements that concatenate in the platform's normal -| endian order to form a 256-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_add256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr); -#endif - -#ifndef softfloat_sub128 -/*---------------------------------------------------------------------------- -| Returns the difference of the 128-bit integer formed by concatenating 'a64' -| and 'a0' and the 128-bit integer formed by concatenating 'b64' and 'b0'. -| The subtraction is modulo 2^128, so any borrow out (carry out) is lost. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE -struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { - struct uint128 z; - z.v0 = a0 - b0; - z.v64 = a64 - b64; - z.v64 -= (a0 < b0); - return z; -} -#else -struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0); -#endif -#endif - -#ifndef softfloat_sub256M -/*---------------------------------------------------------------------------- -| Subtracts the 256-bit integer pointed to by 'bPtr' from the 256-bit integer -| pointed to by 'aPtr'. The addition is modulo 2^256, so any borrow out -| (carry out) is lost. The difference is stored at the location pointed to -| by 'zPtr'. Each of 'aPtr', 'bPtr', and 'zPtr' points to an array of four -| 64-bit elements that concatenate in the platform's normal endian order to -| form a 256-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_sub256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr); -#endif - -#ifndef softfloat_mul64ByShifted32To128 -/*---------------------------------------------------------------------------- -| Returns the 128-bit product of 'a', 'b', and 2^32. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) -INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) { - uint_fast64_t mid; - struct uint128 z; - mid = (uint_fast64_t)(uint32_t)a * b; - z.v0 = mid << 32; - z.v64 = (uint_fast64_t)(uint32_t)(a >> 32) * b + (mid >> 32); - return z; -} -#else -struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b); -#endif -#endif - -#ifndef softfloat_mul64To128 -/*---------------------------------------------------------------------------- -| Returns the 128-bit product of 'a' and 'b'. -*----------------------------------------------------------------------------*/ -struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b); -#endif - -#ifndef softfloat_mul128By32 -/*---------------------------------------------------------------------------- -| Returns the product of the 128-bit integer formed by concatenating 'a64' and -| 'a0', multiplied by 'b'. The multiplication is modulo 2^128; any overflow -| bits are discarded. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (4 <= INLINE_LEVEL) -INLINE -struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) { - struct uint128 z; - uint_fast64_t mid; - uint_fast32_t carry; - z.v0 = a0 * b; - mid = (uint_fast64_t)(uint32_t)(a0 >> 32) * b; - carry = (uint32_t)((uint_fast32_t)(z.v0 >> 32) - (uint_fast32_t)mid); - z.v64 = a64 * b + (uint_fast32_t)((mid + carry) >> 32); - return z; -} -#else -struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b); -#endif -#endif - -#ifndef softfloat_mul128To256M -/*---------------------------------------------------------------------------- -| Multiplies the 128-bit unsigned integer formed by concatenating 'a64' and -| 'a0' by the 128-bit unsigned integer formed by concatenating 'b64' and -| 'b0'. The 256-bit product is stored at the location pointed to by 'zPtr'. -| Argument 'zPtr' points to an array of four 64-bit elements that concatenate -| in the platform's normal endian order to form a 256-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr); -#endif - -#else - -/*---------------------------------------------------------------------------- -| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not -| defined. -*----------------------------------------------------------------------------*/ - -#ifndef softfloat_compare96M -/*---------------------------------------------------------------------------- -| Compares the two 96-bit unsigned integers pointed to by 'aPtr' and 'bPtr'. -| Returns -1 if the first integer (A) is less than the second (B); returns 0 -| if the two integers are equal; and returns +1 if the first integer (A) -| is greater than the second (B). (The result is thus the signum of A - B.) -| Each of 'aPtr' and 'bPtr' points to an array of three 32-bit elements that -| concatenate in the platform's normal endian order to form a 96-bit integer. -*----------------------------------------------------------------------------*/ -int_fast8_t softfloat_compare96M(const uint32_t* aPtr, const uint32_t* bPtr); -#endif - -#ifndef softfloat_compare128M -/*---------------------------------------------------------------------------- -| Compares the two 128-bit unsigned integers pointed to by 'aPtr' and 'bPtr'. -| Returns -1 if the first integer (A) is less than the second (B); returns 0 -| if the two integers are equal; and returns +1 if the first integer (A) -| is greater than the second (B). (The result is thus the signum of A - B.) -| Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that -| concatenate in the platform's normal endian order to form a 128-bit integer. -*----------------------------------------------------------------------------*/ -int_fast8_t softfloat_compare128M(const uint32_t* aPtr, const uint32_t* bPtr); -#endif - -#ifndef softfloat_shortShiftLeft64To96M -/*---------------------------------------------------------------------------- -| Extends 'a' to 96 bits and shifts the value left by the number of bits given -| in 'dist', which must be in the range 1 to 31. The result is stored at the -| location pointed to by 'zPtr'. Argument 'zPtr' points to an array of three -| 32-bit elements that concatenate in the platform's normal endian order to -| form a 96-bit integer. -*----------------------------------------------------------------------------*/ -#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE -void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr) { - zPtr[indexWord(3, 0)] = (uint32_t)a << dist; - a >>= 32 - dist; - zPtr[indexWord(3, 2)] = a >> 32; - zPtr[indexWord(3, 1)] = a; -} -#else -void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr); -#endif -#endif - -#ifndef softfloat_shortShiftLeftM -/*---------------------------------------------------------------------------- -| Shifts the N-bit unsigned integer pointed to by 'aPtr' left by the number -| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' -| must be in the range 1 to 31. Any nonzero bits shifted off are lost. The -| shifted N-bit result is stored at the location pointed to by 'zPtr'. Each -| of 'aPtr' and 'zPtr' points to a 'size_words'-long array of 32-bit elements -| that concatenate in the platform's normal endian order to form an N-bit -| integer. -*----------------------------------------------------------------------------*/ -void softfloat_shortShiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr); -#endif - -#ifndef softfloat_shortShiftLeft96M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shortShiftLeftM' with -| 'size_words' = 3 (N = 96). -*----------------------------------------------------------------------------*/ -#define softfloat_shortShiftLeft96M(aPtr, dist, zPtr) softfloat_shortShiftLeftM(3, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shortShiftLeft128M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shortShiftLeftM' with -| 'size_words' = 4 (N = 128). -*----------------------------------------------------------------------------*/ -#define softfloat_shortShiftLeft128M(aPtr, dist, zPtr) softfloat_shortShiftLeftM(4, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shortShiftLeft160M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shortShiftLeftM' with -| 'size_words' = 5 (N = 160). -*----------------------------------------------------------------------------*/ -#define softfloat_shortShiftLeft160M(aPtr, dist, zPtr) softfloat_shortShiftLeftM(5, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shiftLeftM -/*---------------------------------------------------------------------------- -| Shifts the N-bit unsigned integer pointed to by 'aPtr' left by the number -| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' -| must not be zero. Any nonzero bits shifted off are lost. The shifted -| N-bit result is stored at the location pointed to by 'zPtr'. Each of 'aPtr' -| and 'zPtr' points to a 'size_words'-long array of 32-bit elements that -| concatenate in the platform's normal endian order to form an N-bit integer. -| The value of 'dist' can be arbitrarily large. In particular, if 'dist' is -| greater than N, the stored result will be 0. -*----------------------------------------------------------------------------*/ -void softfloat_shiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr); -#endif - -#ifndef softfloat_shiftLeft96M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shiftLeftM' with -| 'size_words' = 3 (N = 96). -*----------------------------------------------------------------------------*/ -#define softfloat_shiftLeft96M(aPtr, dist, zPtr) softfloat_shiftLeftM(3, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shiftLeft128M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shiftLeftM' with -| 'size_words' = 4 (N = 128). -*----------------------------------------------------------------------------*/ -#define softfloat_shiftLeft128M(aPtr, dist, zPtr) softfloat_shiftLeftM(4, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shiftLeft160M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shiftLeftM' with -| 'size_words' = 5 (N = 160). -*----------------------------------------------------------------------------*/ -#define softfloat_shiftLeft160M(aPtr, dist, zPtr) softfloat_shiftLeftM(5, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shortShiftRightM -/*---------------------------------------------------------------------------- -| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number -| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' -| must be in the range 1 to 31. Any nonzero bits shifted off are lost. The -| shifted N-bit result is stored at the location pointed to by 'zPtr'. Each -| of 'aPtr' and 'zPtr' points to a 'size_words'-long array of 32-bit elements -| that concatenate in the platform's normal endian order to form an N-bit -| integer. -*----------------------------------------------------------------------------*/ -void softfloat_shortShiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr); -#endif - -#ifndef softfloat_shortShiftRight128M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shortShiftRightM' with -| 'size_words' = 4 (N = 128). -*----------------------------------------------------------------------------*/ -#define softfloat_shortShiftRight128M(aPtr, dist, zPtr) softfloat_shortShiftRightM(4, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shortShiftRight160M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shortShiftRightM' with -| 'size_words' = 5 (N = 160). -*----------------------------------------------------------------------------*/ -#define softfloat_shortShiftRight160M(aPtr, dist, zPtr) softfloat_shortShiftRightM(5, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shortShiftRightJamM -/*---------------------------------------------------------------------------- -| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number -| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' -| must be in the range 1 to 31. If any nonzero bits are shifted off, they are -| "jammed" into the least-significant bit of the shifted value by setting the -| least-significant bit to 1. This shifted-and-jammed N-bit result is stored -| at the location pointed to by 'zPtr'. Each of 'aPtr' and 'zPtr' points -| to a 'size_words'-long array of 32-bit elements that concatenate in the -| platform's normal endian order to form an N-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_shortShiftRightJamM(uint_fast8_t, const uint32_t*, uint_fast8_t, uint32_t*); -#endif - -#ifndef softfloat_shortShiftRightJam160M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shortShiftRightJamM' with -| 'size_words' = 5 (N = 160). -*----------------------------------------------------------------------------*/ -#define softfloat_shortShiftRightJam160M(aPtr, dist, zPtr) softfloat_shortShiftRightJamM(5, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shiftRightM -/*---------------------------------------------------------------------------- -| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number -| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' -| must not be zero. Any nonzero bits shifted off are lost. The shifted -| N-bit result is stored at the location pointed to by 'zPtr'. Each of 'aPtr' -| and 'zPtr' points to a 'size_words'-long array of 32-bit elements that -| concatenate in the platform's normal endian order to form an N-bit integer. -| The value of 'dist' can be arbitrarily large. In particular, if 'dist' is -| greater than N, the stored result will be 0. -*----------------------------------------------------------------------------*/ -void softfloat_shiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr); -#endif - -#ifndef softfloat_shiftRight96M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shiftRightM' with -| 'size_words' = 3 (N = 96). -*----------------------------------------------------------------------------*/ -#define softfloat_shiftRight96M(aPtr, dist, zPtr) softfloat_shiftRightM(3, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shiftRightJamM -/*---------------------------------------------------------------------------- -| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number -| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' -| must not be zero. If any nonzero bits are shifted off, they are "jammed" -| into the least-significant bit of the shifted value by setting the least- -| significant bit to 1. This shifted-and-jammed N-bit result is stored -| at the location pointed to by 'zPtr'. Each of 'aPtr' and 'zPtr' points -| to a 'size_words'-long array of 32-bit elements that concatenate in the -| platform's normal endian order to form an N-bit integer. -| The value of 'dist' can be arbitrarily large. In particular, if 'dist' -| is greater than N, the stored result will be either 0 or 1, depending on -| whether the original N bits are all zeros. -*----------------------------------------------------------------------------*/ -void softfloat_shiftRightJamM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr); -#endif - -#ifndef softfloat_shiftRightJam96M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shiftRightJamM' with -| 'size_words' = 3 (N = 96). -*----------------------------------------------------------------------------*/ -#define softfloat_shiftRightJam96M(aPtr, dist, zPtr) softfloat_shiftRightJamM(3, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shiftRightJam128M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shiftRightJamM' with -| 'size_words' = 4 (N = 128). -*----------------------------------------------------------------------------*/ -#define softfloat_shiftRightJam128M(aPtr, dist, zPtr) softfloat_shiftRightJamM(4, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_shiftRightJam160M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_shiftRightJamM' with -| 'size_words' = 5 (N = 160). -*----------------------------------------------------------------------------*/ -#define softfloat_shiftRightJam160M(aPtr, dist, zPtr) softfloat_shiftRightJamM(5, aPtr, dist, zPtr) -#endif - -#ifndef softfloat_addM -/*---------------------------------------------------------------------------- -| Adds the two N-bit integers pointed to by 'aPtr' and 'bPtr', where N = -| 'size_words' * 32. The addition is modulo 2^N, so any carry out is lost. -| The N-bit sum is stored at the location pointed to by 'zPtr'. Each of -| 'aPtr', 'bPtr', and 'zPtr' points to a 'size_words'-long array of 32-bit -| elements that concatenate in the platform's normal endian order to form an -| N-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_addM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr); -#endif - -#ifndef softfloat_add96M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_addM' with 'size_words' -| = 3 (N = 96). -*----------------------------------------------------------------------------*/ -#define softfloat_add96M(aPtr, bPtr, zPtr) softfloat_addM(3, aPtr, bPtr, zPtr) -#endif - -#ifndef softfloat_add128M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_addM' with 'size_words' -| = 4 (N = 128). -*----------------------------------------------------------------------------*/ -#define softfloat_add128M(aPtr, bPtr, zPtr) softfloat_addM(4, aPtr, bPtr, zPtr) -#endif - -#ifndef softfloat_add160M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_addM' with 'size_words' -| = 5 (N = 160). -*----------------------------------------------------------------------------*/ -#define softfloat_add160M(aPtr, bPtr, zPtr) softfloat_addM(5, aPtr, bPtr, zPtr) -#endif - -#ifndef softfloat_addCarryM -/*---------------------------------------------------------------------------- -| Adds the two N-bit unsigned integers pointed to by 'aPtr' and 'bPtr', where -| N = 'size_words' * 32, plus 'carry', which must be either 0 or 1. The N-bit -| sum (modulo 2^N) is stored at the location pointed to by 'zPtr', and any -| carry out is returned as the result. Each of 'aPtr', 'bPtr', and 'zPtr' -| points to a 'size_words'-long array of 32-bit elements that concatenate in -| the platform's normal endian order to form an N-bit integer. -*----------------------------------------------------------------------------*/ -uint_fast8_t softfloat_addCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry, uint32_t* zPtr); -#endif - -#ifndef softfloat_addComplCarryM -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_addCarryM', except that -| the value of the unsigned integer pointed to by 'bPtr' is bit-wise completed -| before the addition. -*----------------------------------------------------------------------------*/ -uint_fast8_t softfloat_addComplCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry, - uint32_t* zPtr); -#endif - -#ifndef softfloat_addComplCarry96M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_addComplCarryM' with -| 'size_words' = 3 (N = 96). -*----------------------------------------------------------------------------*/ -#define softfloat_addComplCarry96M(aPtr, bPtr, carry, zPtr) softfloat_addComplCarryM(3, aPtr, bPtr, carry, zPtr) -#endif - -#ifndef softfloat_negXM -/*---------------------------------------------------------------------------- -| Replaces the N-bit unsigned integer pointed to by 'zPtr' by the -| 2s-complement of itself, where N = 'size_words' * 32. Argument 'zPtr' -| points to a 'size_words'-long array of 32-bit elements that concatenate in -| the platform's normal endian order to form an N-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_negXM(uint_fast8_t size_words, uint32_t* zPtr); -#endif - -#ifndef softfloat_negX96M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_negXM' with 'size_words' -| = 3 (N = 96). -*----------------------------------------------------------------------------*/ -#define softfloat_negX96M(zPtr) softfloat_negXM(3, zPtr) -#endif - -#ifndef softfloat_negX128M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_negXM' with 'size_words' -| = 4 (N = 128). -*----------------------------------------------------------------------------*/ -#define softfloat_negX128M(zPtr) softfloat_negXM(4, zPtr) -#endif - -#ifndef softfloat_negX160M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_negXM' with 'size_words' -| = 5 (N = 160). -*----------------------------------------------------------------------------*/ -#define softfloat_negX160M(zPtr) softfloat_negXM(5, zPtr) -#endif - -#ifndef softfloat_negX256M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_negXM' with 'size_words' -| = 8 (N = 256). -*----------------------------------------------------------------------------*/ -#define softfloat_negX256M(zPtr) softfloat_negXM(8, zPtr) -#endif - -#ifndef softfloat_sub1XM -/*---------------------------------------------------------------------------- -| Subtracts 1 from the N-bit integer pointed to by 'zPtr', where N = -| 'size_words' * 32. The subtraction is modulo 2^N, so any borrow out (carry -| out) is lost. Argument 'zPtr' points to a 'size_words'-long array of 32-bit -| elements that concatenate in the platform's normal endian order to form an -| N-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_sub1XM(uint_fast8_t size_words, uint32_t* zPtr); -#endif - -#ifndef softfloat_sub1X96M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_sub1XM' with 'size_words' -| = 3 (N = 96). -*----------------------------------------------------------------------------*/ -#define softfloat_sub1X96M(zPtr) softfloat_sub1XM(3, zPtr) -#endif - -#ifndef softfloat_sub1X160M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_sub1XM' with 'size_words' -| = 5 (N = 160). -*----------------------------------------------------------------------------*/ -#define softfloat_sub1X160M(zPtr) softfloat_sub1XM(5, zPtr) -#endif - -#ifndef softfloat_subM -/*---------------------------------------------------------------------------- -| Subtracts the two N-bit integers pointed to by 'aPtr' and 'bPtr', where N = -| 'size_words' * 32. The subtraction is modulo 2^N, so any borrow out (carry -| out) is lost. The N-bit difference is stored at the location pointed to by -| 'zPtr'. Each of 'aPtr', 'bPtr', and 'zPtr' points to a 'size_words'-long -| array of 32-bit elements that concatenate in the platform's normal endian -| order to form an N-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_subM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr); -#endif - -#ifndef softfloat_sub96M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_subM' with 'size_words' -| = 3 (N = 96). -*----------------------------------------------------------------------------*/ -#define softfloat_sub96M(aPtr, bPtr, zPtr) softfloat_subM(3, aPtr, bPtr, zPtr) -#endif - -#ifndef softfloat_sub128M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_subM' with 'size_words' -| = 4 (N = 128). -*----------------------------------------------------------------------------*/ -#define softfloat_sub128M(aPtr, bPtr, zPtr) softfloat_subM(4, aPtr, bPtr, zPtr) -#endif - -#ifndef softfloat_sub160M -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_subM' with 'size_words' -| = 5 (N = 160). -*----------------------------------------------------------------------------*/ -#define softfloat_sub160M(aPtr, bPtr, zPtr) softfloat_subM(5, aPtr, bPtr, zPtr) -#endif - -#ifndef softfloat_mul64To128M -/*---------------------------------------------------------------------------- -| Multiplies 'a' and 'b' and stores the 128-bit product at the location -| pointed to by 'zPtr'. Argument 'zPtr' points to an array of four 32-bit -| elements that concatenate in the platform's normal endian order to form a -| 128-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_mul64To128M(uint64_t a, uint64_t b, uint32_t* zPtr); -#endif - -#ifndef softfloat_mul128MTo256M -/*---------------------------------------------------------------------------- -| Multiplies the two 128-bit unsigned integers pointed to by 'aPtr' and -| 'bPtr', and stores the 256-bit product at the location pointed to by 'zPtr'. -| Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that -| concatenate in the platform's normal endian order to form a 128-bit integer. -| Argument 'zPtr' points to an array of eight 32-bit elements that concatenate -| to form a 256-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_mul128MTo256M(const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr); -#endif - -#ifndef softfloat_remStepMBy32 -/*---------------------------------------------------------------------------- -| Performs a "remainder reduction step" as follows: Arguments 'remPtr' and -| 'bPtr' both point to N-bit unsigned integers, where N = 'size_words' * 32. -| Defining R and B as the values of those integers, the expression (R<<'dist') -| - B * q is computed modulo 2^N, and the N-bit result is stored at the -| location pointed to by 'zPtr'. Each of 'remPtr', 'bPtr', and 'zPtr' points -| to a 'size_words'-long array of 32-bit elements that concatenate in the -| platform's normal endian order to form an N-bit integer. -*----------------------------------------------------------------------------*/ -void softfloat_remStepMBy32(uint_fast8_t size_words, const uint32_t* remPtr, uint_fast8_t dist, const uint32_t* bPtr, uint32_t q, - uint32_t* zPtr); -#endif - -#ifndef softfloat_remStep96MBy32 -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_remStepMBy32' with -| 'size_words' = 3 (N = 96). -*----------------------------------------------------------------------------*/ -#define softfloat_remStep96MBy32(remPtr, dist, bPtr, q, zPtr) softfloat_remStepMBy32(3, remPtr, dist, bPtr, q, zPtr) -#endif - -#ifndef softfloat_remStep128MBy32 -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_remStepMBy32' with -| 'size_words' = 4 (N = 128). -*----------------------------------------------------------------------------*/ -#define softfloat_remStep128MBy32(remPtr, dist, bPtr, q, zPtr) softfloat_remStepMBy32(4, remPtr, dist, bPtr, q, zPtr) -#endif - -#ifndef softfloat_remStep160MBy32 -/*---------------------------------------------------------------------------- -| This function or macro is the same as 'softfloat_remStepMBy32' with -| 'size_words' = 5 (N = 160). -*----------------------------------------------------------------------------*/ -#define softfloat_remStep160MBy32(remPtr, dist, bPtr, q, zPtr) softfloat_remStepMBy32(5, remPtr, dist, bPtr, q, zPtr) -#endif - -#endif - -#endif diff --git a/softfloat/source/include/softfloat.h b/softfloat/source/include/softfloat.h deleted file mode 100644 index f3bed57..0000000 --- a/softfloat/source/include/softfloat.h +++ /dev/null @@ -1,368 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -/*============================================================================ -| Note: If SoftFloat is made available as a general library for programs to -| use, it is strongly recommended that a platform-specific version of this -| header, "softfloat.h", be created that folds in "softfloat_types.h" and that -| eliminates all dependencies on compile-time macros. -*============================================================================*/ - -#ifndef softfloat_h -#define softfloat_h 1 - -#include "softfloat_types.h" -#include -#include - -#ifndef THREAD_LOCAL -#define THREAD_LOCAL -#endif - -/*---------------------------------------------------------------------------- -| Software floating-point underflow tininess-detection mode. -*----------------------------------------------------------------------------*/ -extern THREAD_LOCAL uint_fast8_t softfloat_detectTininess; -enum { softfloat_tininess_beforeRounding = 0, softfloat_tininess_afterRounding = 1 }; - -/*---------------------------------------------------------------------------- -| Software floating-point rounding mode. (Mode "odd" is supported only if -| SoftFloat is compiled with macro 'SOFTFLOAT_ROUND_ODD' defined.) -*----------------------------------------------------------------------------*/ -extern THREAD_LOCAL uint_fast8_t softfloat_roundingMode; -enum { - softfloat_round_near_even = 0, - softfloat_round_minMag = 1, - softfloat_round_min = 2, - softfloat_round_max = 3, - softfloat_round_near_maxMag = 4, - softfloat_round_odd = 6 -}; - -/*---------------------------------------------------------------------------- -| Software floating-point exception flags. -*----------------------------------------------------------------------------*/ -extern THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags; -typedef enum { - softfloat_flag_inexact = 1, - softfloat_flag_underflow = 2, - softfloat_flag_overflow = 4, - softfloat_flag_infinite = 8, - softfloat_flag_invalid = 16 -} exceptionFlag_t; - -/*---------------------------------------------------------------------------- -| Routine to raise any or all of the software floating-point exception flags. -*----------------------------------------------------------------------------*/ -void softfloat_raiseFlags(uint_fast8_t); - -/*---------------------------------------------------------------------------- -| Integer-to-floating-point conversion routines. -*----------------------------------------------------------------------------*/ -float16_t ui32_to_f16(uint32_t); -float32_t ui32_to_f32(uint32_t); -float64_t ui32_to_f64(uint32_t); -#ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t ui32_to_extF80(uint32_t); -float128_t ui32_to_f128(uint32_t); -#endif -void ui32_to_extF80M(uint32_t, extFloat80_t*); -void ui32_to_f128M(uint32_t, float128_t*); -float16_t ui64_to_f16(uint64_t); -float32_t ui64_to_f32(uint64_t); -float64_t ui64_to_f64(uint64_t); -#ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t ui64_to_extF80(uint64_t); -float128_t ui64_to_f128(uint64_t); -#endif -void ui64_to_extF80M(uint64_t, extFloat80_t*); -void ui64_to_f128M(uint64_t, float128_t*); -float16_t i32_to_f16(int32_t); -float32_t i32_to_f32(int32_t); -float64_t i32_to_f64(int32_t); -#ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t i32_to_extF80(int32_t); -float128_t i32_to_f128(int32_t); -#endif -void i32_to_extF80M(int32_t, extFloat80_t*); -void i32_to_f128M(int32_t, float128_t*); -float16_t i64_to_f16(int64_t); -float32_t i64_to_f32(int64_t); -float64_t i64_to_f64(int64_t); -#ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t i64_to_extF80(int64_t); -float128_t i64_to_f128(int64_t); -#endif -void i64_to_extF80M(int64_t, extFloat80_t*); -void i64_to_f128M(int64_t, float128_t*); - -/*---------------------------------------------------------------------------- -| 16-bit (half-precision) floating-point operations. -*----------------------------------------------------------------------------*/ -uint_fast32_t f16_to_ui32(float16_t, uint_fast8_t, bool); -uint_fast64_t f16_to_ui64(float16_t, uint_fast8_t, bool); -int_fast32_t f16_to_i32(float16_t, uint_fast8_t, bool); -int_fast64_t f16_to_i64(float16_t, uint_fast8_t, bool); -uint_fast32_t f16_to_ui32_r_minMag(float16_t, bool); -uint_fast64_t f16_to_ui64_r_minMag(float16_t, bool); -int_fast32_t f16_to_i32_r_minMag(float16_t, bool); -int_fast64_t f16_to_i64_r_minMag(float16_t, bool); -float32_t f16_to_f32(float16_t); -float64_t f16_to_f64(float16_t); -#ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t f16_to_extF80(float16_t); -float128_t f16_to_f128(float16_t); -#endif -void f16_to_extF80M(float16_t, extFloat80_t*); -void f16_to_f128M(float16_t, float128_t*); -float16_t f16_roundToInt(float16_t, uint_fast8_t, bool); -float16_t f16_add(float16_t, float16_t); -float16_t f16_sub(float16_t, float16_t); -float16_t f16_mul(float16_t, float16_t); -float16_t f16_mulAdd(float16_t, float16_t, float16_t); -float16_t f16_div(float16_t, float16_t); -float16_t f16_rem(float16_t, float16_t); -float16_t f16_sqrt(float16_t); -bool f16_eq(float16_t, float16_t); -bool f16_le(float16_t, float16_t); -bool f16_lt(float16_t, float16_t); -bool f16_eq_signaling(float16_t, float16_t); -bool f16_le_quiet(float16_t, float16_t); -bool f16_lt_quiet(float16_t, float16_t); -bool f16_isSignalingNaN(float16_t); - -/*---------------------------------------------------------------------------- -| 16-bit (brain float 16) floating-point operations. -*----------------------------------------------------------------------------*/ -float32_t bf16_to_f32(bfloat16_t); -bfloat16_t f32_to_bf16(float32_t); -bool bf16_isSignalingNaN(bfloat16_t); - -/*---------------------------------------------------------------------------- -| 32-bit (single-precision) floating-point operations. -*----------------------------------------------------------------------------*/ -uint_fast32_t f32_to_ui32(float32_t, uint_fast8_t, bool); -uint_fast64_t f32_to_ui64(float32_t, uint_fast8_t, bool); -int_fast32_t f32_to_i32(float32_t, uint_fast8_t, bool); -int_fast64_t f32_to_i64(float32_t, uint_fast8_t, bool); -uint_fast32_t f32_to_ui32_r_minMag(float32_t, bool); -uint_fast64_t f32_to_ui64_r_minMag(float32_t, bool); -int_fast32_t f32_to_i32_r_minMag(float32_t, bool); -int_fast64_t f32_to_i64_r_minMag(float32_t, bool); -float16_t f32_to_f16(float32_t); -float64_t f32_to_f64(float32_t); -#ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t f32_to_extF80(float32_t); -float128_t f32_to_f128(float32_t); -#endif -void f32_to_extF80M(float32_t, extFloat80_t*); -void f32_to_f128M(float32_t, float128_t*); -float32_t f32_roundToInt(float32_t, uint_fast8_t, bool); -float32_t f32_add(float32_t, float32_t); -float32_t f32_sub(float32_t, float32_t); -float32_t f32_mul(float32_t, float32_t); -float32_t f32_mulAdd(float32_t, float32_t, float32_t); -float32_t f32_div(float32_t, float32_t); -float32_t f32_rem(float32_t, float32_t); -float32_t f32_sqrt(float32_t); -bool f32_eq(float32_t, float32_t); -bool f32_le(float32_t, float32_t); -bool f32_lt(float32_t, float32_t); -bool f32_eq_signaling(float32_t, float32_t); -bool f32_le_quiet(float32_t, float32_t); -bool f32_lt_quiet(float32_t, float32_t); -bool f32_isSignalingNaN(float32_t); - -/*---------------------------------------------------------------------------- -| 64-bit (double-precision) floating-point operations. -*----------------------------------------------------------------------------*/ -uint_fast32_t f64_to_ui32(float64_t, uint_fast8_t, bool); -uint_fast64_t f64_to_ui64(float64_t, uint_fast8_t, bool); -int_fast32_t f64_to_i32(float64_t, uint_fast8_t, bool); -int_fast64_t f64_to_i64(float64_t, uint_fast8_t, bool); -uint_fast32_t f64_to_ui32_r_minMag(float64_t, bool); -uint_fast64_t f64_to_ui64_r_minMag(float64_t, bool); -int_fast32_t f64_to_i32_r_minMag(float64_t, bool); -int_fast64_t f64_to_i64_r_minMag(float64_t, bool); -float16_t f64_to_f16(float64_t); -float32_t f64_to_f32(float64_t); -#ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t f64_to_extF80(float64_t); -float128_t f64_to_f128(float64_t); -#endif -void f64_to_extF80M(float64_t, extFloat80_t*); -void f64_to_f128M(float64_t, float128_t*); -float64_t f64_roundToInt(float64_t, uint_fast8_t, bool); -float64_t f64_add(float64_t, float64_t); -float64_t f64_sub(float64_t, float64_t); -float64_t f64_mul(float64_t, float64_t); -float64_t f64_mulAdd(float64_t, float64_t, float64_t); -float64_t f64_div(float64_t, float64_t); -float64_t f64_rem(float64_t, float64_t); -float64_t f64_sqrt(float64_t); -bool f64_eq(float64_t, float64_t); -bool f64_le(float64_t, float64_t); -bool f64_lt(float64_t, float64_t); -bool f64_eq_signaling(float64_t, float64_t); -bool f64_le_quiet(float64_t, float64_t); -bool f64_lt_quiet(float64_t, float64_t); -bool f64_isSignalingNaN(float64_t); - -/*---------------------------------------------------------------------------- -| Rounding precision for 80-bit extended double-precision floating-point. -| Valid values are 32, 64, and 80. -*----------------------------------------------------------------------------*/ -extern THREAD_LOCAL uint_fast8_t extF80_roundingPrecision; - -/*---------------------------------------------------------------------------- -| 80-bit extended double-precision floating-point operations. -*----------------------------------------------------------------------------*/ -#ifdef SOFTFLOAT_FAST_INT64 -uint_fast32_t extF80_to_ui32(extFloat80_t, uint_fast8_t, bool); -uint_fast64_t extF80_to_ui64(extFloat80_t, uint_fast8_t, bool); -int_fast32_t extF80_to_i32(extFloat80_t, uint_fast8_t, bool); -int_fast64_t extF80_to_i64(extFloat80_t, uint_fast8_t, bool); -uint_fast32_t extF80_to_ui32_r_minMag(extFloat80_t, bool); -uint_fast64_t extF80_to_ui64_r_minMag(extFloat80_t, bool); -int_fast32_t extF80_to_i32_r_minMag(extFloat80_t, bool); -int_fast64_t extF80_to_i64_r_minMag(extFloat80_t, bool); -float16_t extF80_to_f16(extFloat80_t); -float32_t extF80_to_f32(extFloat80_t); -float64_t extF80_to_f64(extFloat80_t); -float128_t extF80_to_f128(extFloat80_t); -extFloat80_t extF80_roundToInt(extFloat80_t, uint_fast8_t, bool); -extFloat80_t extF80_add(extFloat80_t, extFloat80_t); -extFloat80_t extF80_sub(extFloat80_t, extFloat80_t); -extFloat80_t extF80_mul(extFloat80_t, extFloat80_t); -extFloat80_t extF80_div(extFloat80_t, extFloat80_t); -extFloat80_t extF80_rem(extFloat80_t, extFloat80_t); -extFloat80_t extF80_sqrt(extFloat80_t); -bool extF80_eq(extFloat80_t, extFloat80_t); -bool extF80_le(extFloat80_t, extFloat80_t); -bool extF80_lt(extFloat80_t, extFloat80_t); -bool extF80_eq_signaling(extFloat80_t, extFloat80_t); -bool extF80_le_quiet(extFloat80_t, extFloat80_t); -bool extF80_lt_quiet(extFloat80_t, extFloat80_t); -bool extF80_isSignalingNaN(extFloat80_t); -#endif -uint_fast32_t extF80M_to_ui32(const extFloat80_t*, uint_fast8_t, bool); -uint_fast64_t extF80M_to_ui64(const extFloat80_t*, uint_fast8_t, bool); -int_fast32_t extF80M_to_i32(const extFloat80_t*, uint_fast8_t, bool); -int_fast64_t extF80M_to_i64(const extFloat80_t*, uint_fast8_t, bool); -uint_fast32_t extF80M_to_ui32_r_minMag(const extFloat80_t*, bool); -uint_fast64_t extF80M_to_ui64_r_minMag(const extFloat80_t*, bool); -int_fast32_t extF80M_to_i32_r_minMag(const extFloat80_t*, bool); -int_fast64_t extF80M_to_i64_r_minMag(const extFloat80_t*, bool); -float16_t extF80M_to_f16(const extFloat80_t*); -float32_t extF80M_to_f32(const extFloat80_t*); -float64_t extF80M_to_f64(const extFloat80_t*); -void extF80M_to_f128M(const extFloat80_t*, float128_t*); -void extF80M_roundToInt(const extFloat80_t*, uint_fast8_t, bool, extFloat80_t*); -void extF80M_add(const extFloat80_t*, const extFloat80_t*, extFloat80_t*); -void extF80M_sub(const extFloat80_t*, const extFloat80_t*, extFloat80_t*); -void extF80M_mul(const extFloat80_t*, const extFloat80_t*, extFloat80_t*); -void extF80M_div(const extFloat80_t*, const extFloat80_t*, extFloat80_t*); -void extF80M_rem(const extFloat80_t*, const extFloat80_t*, extFloat80_t*); -void extF80M_sqrt(const extFloat80_t*, extFloat80_t*); -bool extF80M_eq(const extFloat80_t*, const extFloat80_t*); -bool extF80M_le(const extFloat80_t*, const extFloat80_t*); -bool extF80M_lt(const extFloat80_t*, const extFloat80_t*); -bool extF80M_eq_signaling(const extFloat80_t*, const extFloat80_t*); -bool extF80M_le_quiet(const extFloat80_t*, const extFloat80_t*); -bool extF80M_lt_quiet(const extFloat80_t*, const extFloat80_t*); -bool extF80M_isSignalingNaN(const extFloat80_t*); - -/*---------------------------------------------------------------------------- -| 128-bit (quadruple-precision) floating-point operations. -*----------------------------------------------------------------------------*/ -#ifdef SOFTFLOAT_FAST_INT64 -uint_fast32_t f128_to_ui32(float128_t, uint_fast8_t, bool); -uint_fast64_t f128_to_ui64(float128_t, uint_fast8_t, bool); -int_fast32_t f128_to_i32(float128_t, uint_fast8_t, bool); -int_fast64_t f128_to_i64(float128_t, uint_fast8_t, bool); -uint_fast32_t f128_to_ui32_r_minMag(float128_t, bool); -uint_fast64_t f128_to_ui64_r_minMag(float128_t, bool); -int_fast32_t f128_to_i32_r_minMag(float128_t, bool); -int_fast64_t f128_to_i64_r_minMag(float128_t, bool); -float16_t f128_to_f16(float128_t); -float32_t f128_to_f32(float128_t); -float64_t f128_to_f64(float128_t); -extFloat80_t f128_to_extF80(float128_t); -float128_t f128_roundToInt(float128_t, uint_fast8_t, bool); -float128_t f128_add(float128_t, float128_t); -float128_t f128_sub(float128_t, float128_t); -float128_t f128_mul(float128_t, float128_t); -float128_t f128_mulAdd(float128_t, float128_t, float128_t); -float128_t f128_div(float128_t, float128_t); -float128_t f128_rem(float128_t, float128_t); -float128_t f128_sqrt(float128_t); -bool f128_eq(float128_t, float128_t); -bool f128_le(float128_t, float128_t); -bool f128_lt(float128_t, float128_t); -bool f128_eq_signaling(float128_t, float128_t); -bool f128_le_quiet(float128_t, float128_t); -bool f128_lt_quiet(float128_t, float128_t); -bool f128_isSignalingNaN(float128_t); -#endif -uint_fast32_t f128M_to_ui32(const float128_t*, uint_fast8_t, bool); -uint_fast64_t f128M_to_ui64(const float128_t*, uint_fast8_t, bool); -int_fast32_t f128M_to_i32(const float128_t*, uint_fast8_t, bool); -int_fast64_t f128M_to_i64(const float128_t*, uint_fast8_t, bool); -uint_fast32_t f128M_to_ui32_r_minMag(const float128_t*, bool); -uint_fast64_t f128M_to_ui64_r_minMag(const float128_t*, bool); -int_fast32_t f128M_to_i32_r_minMag(const float128_t*, bool); -int_fast64_t f128M_to_i64_r_minMag(const float128_t*, bool); -float16_t f128M_to_f16(const float128_t*); -float32_t f128M_to_f32(const float128_t*); -float64_t f128M_to_f64(const float128_t*); -void f128M_to_extF80M(const float128_t*, extFloat80_t*); -void f128M_roundToInt(const float128_t*, uint_fast8_t, bool, float128_t*); -void f128M_add(const float128_t*, const float128_t*, float128_t*); -void f128M_sub(const float128_t*, const float128_t*, float128_t*); -void f128M_mul(const float128_t*, const float128_t*, float128_t*); -void f128M_mulAdd(const float128_t*, const float128_t*, const float128_t*, float128_t*); -void f128M_div(const float128_t*, const float128_t*, float128_t*); -void f128M_rem(const float128_t*, const float128_t*, float128_t*); -void f128M_sqrt(const float128_t*, float128_t*); -bool f128M_eq(const float128_t*, const float128_t*); -bool f128M_le(const float128_t*, const float128_t*); -bool f128M_lt(const float128_t*, const float128_t*); -bool f128M_eq_signaling(const float128_t*, const float128_t*); -bool f128M_le_quiet(const float128_t*, const float128_t*); -bool f128M_lt_quiet(const float128_t*, const float128_t*); -bool f128M_isSignalingNaN(const float128_t*); - -#endif diff --git a/softfloat/source/include/softfloat_types.h b/softfloat/source/include/softfloat_types.h deleted file mode 100644 index 9ed5809..0000000 --- a/softfloat/source/include/softfloat_types.h +++ /dev/null @@ -1,97 +0,0 @@ - -/*============================================================================ - -This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#ifndef softfloat_types_h -#define softfloat_types_h 1 - -#include - -/*---------------------------------------------------------------------------- -| Types used to pass 16-bit, 32-bit, 64-bit, and 128-bit floating-point -| arguments and results to/from functions. These types must be exactly -| 16 bits, 32 bits, 64 bits, and 128 bits in size, respectively. Where a -| platform has "native" support for IEEE-Standard floating-point formats, -| the types below may, if desired, be defined as aliases for the native types -| (typically 'float' and 'double', and possibly 'long double'). -*----------------------------------------------------------------------------*/ -typedef struct { - uint16_t v; -} float16_t; -typedef struct { - uint16_t v; -} bfloat16_t; -typedef struct { - uint32_t v; -} float32_t; -typedef struct { - uint64_t v; -} float64_t; -typedef struct { - uint64_t v[2]; -} float128_t; - -/*---------------------------------------------------------------------------- -| The format of an 80-bit extended floating-point number in memory. This -| structure must contain a 16-bit field named 'signExp' and a 64-bit field -| named 'signif'. -*----------------------------------------------------------------------------*/ -#ifdef LITTLEENDIAN -struct extFloat80M { - uint64_t signif; - uint16_t signExp; -}; -#else -struct extFloat80M { - uint16_t signExp; - uint64_t signif; -}; -#endif - -/*---------------------------------------------------------------------------- -| The type used to pass 80-bit extended floating-point arguments and -| results to/from functions. This type must have size identical to -| 'struct extFloat80M'. Type 'extFloat80_t' can be defined as an alias for -| 'struct extFloat80M'. Alternatively, if a platform has "native" support -| for IEEE-Standard 80-bit extended floating-point, it may be possible, -| if desired, to define 'extFloat80_t' as an alias for the native type -| (presumably either 'long double' or a nonstandard compiler-intrinsic type). -| In that case, the 'signif' and 'signExp' fields of 'struct extFloat80M' -| must align exactly with the locations in memory of the sign, exponent, and -| significand of the native type. -*----------------------------------------------------------------------------*/ -typedef struct extFloat80M extFloat80_t; - -#endif diff --git a/softfloat/source/s_add128.c b/softfloat/source/s_add128.c deleted file mode 100644 index 5a9d508..0000000 --- a/softfloat/source/s_add128.c +++ /dev/null @@ -1,55 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_add128 - -struct uint128 - softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) -{ - struct uint128 z; - - z.v0 = a0 + b0; - z.v64 = a64 + b64 + (z.v0 < a0); - return z; - -} - -#endif - diff --git a/softfloat/source/s_add256M.c b/softfloat/source/s_add256M.c deleted file mode 100644 index 4fb46a1..0000000 --- a/softfloat/source/s_add256M.c +++ /dev/null @@ -1,65 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_add256M - -void - softfloat_add256M( - const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr ) -{ - unsigned int index; - uint_fast8_t carry; - uint64_t wordA, wordZ; - - index = indexWordLo( 4 ); - carry = 0; - for (;;) { - wordA = aPtr[index]; - wordZ = wordA + bPtr[index] + carry; - zPtr[index] = wordZ; - if ( index == indexWordHi( 4 ) ) break; - if ( wordZ != wordA ) carry = (wordZ < wordA); - index += wordIncr; - } - -} - -#endif - diff --git a/softfloat/source/s_addCarryM.c b/softfloat/source/s_addCarryM.c deleted file mode 100644 index f0ccf67..0000000 --- a/softfloat/source/s_addCarryM.c +++ /dev/null @@ -1,70 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_addCarryM - -uint_fast8_t - softfloat_addCarryM( - uint_fast8_t size_words, - const uint32_t *aPtr, - const uint32_t *bPtr, - uint_fast8_t carry, - uint32_t *zPtr - ) -{ - unsigned int index, lastIndex; - uint32_t wordA, wordZ; - - index = indexWordLo( size_words ); - lastIndex = indexWordHi( size_words ); - for (;;) { - wordA = aPtr[index]; - wordZ = wordA + bPtr[index] + carry; - zPtr[index] = wordZ; - if ( wordZ != wordA ) carry = (wordZ < wordA); - if ( index == lastIndex ) break; - index += wordIncr; - } - return carry; - -} - -#endif - diff --git a/softfloat/source/s_addComplCarryM.c b/softfloat/source/s_addComplCarryM.c deleted file mode 100644 index e1584c6..0000000 --- a/softfloat/source/s_addComplCarryM.c +++ /dev/null @@ -1,70 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_addComplCarryM - -uint_fast8_t - softfloat_addComplCarryM( - uint_fast8_t size_words, - const uint32_t *aPtr, - const uint32_t *bPtr, - uint_fast8_t carry, - uint32_t *zPtr - ) -{ - unsigned int index, lastIndex; - uint32_t wordA, wordZ; - - index = indexWordLo( size_words ); - lastIndex = indexWordHi( size_words ); - for (;;) { - wordA = aPtr[index]; - wordZ = wordA + ~bPtr[index] + carry; - zPtr[index] = wordZ; - if ( wordZ != wordA ) carry = (wordZ < wordA); - if ( index == lastIndex ) break; - index += wordIncr; - } - return carry; - -} - -#endif - diff --git a/softfloat/source/s_addExtF80M.c b/softfloat/source/s_addExtF80M.c deleted file mode 100644 index febfb65..0000000 --- a/softfloat/source/s_addExtF80M.c +++ /dev/null @@ -1,186 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -void - softfloat_addExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr, - bool negateB - ) -{ - uint32_t uiA64; - int32_t expA; - uint32_t uiB64; - int32_t expB; - uint32_t uiZ64; - bool signZ, signB; - const struct extFloat80M *tempSPtr; - uint64_t sigZ, sigB; - void - (*roundPackRoutinePtr)( - bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * ); - int32_t expDiff; - uint32_t extSigX[3], sigZExtra; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - expA = expExtF80UI64( uiA64 ); - uiB64 = bSPtr->signExp; - expB = expExtF80UI64( uiB64 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) { - if ( softfloat_tryPropagateNaNExtF80M( aSPtr, bSPtr, zSPtr ) ) return; - uiZ64 = uiA64; - if ( expB == 0x7FFF ) { - uiZ64 = uiB64 ^ packToExtF80UI64( negateB, 0 ); - if ( (expA == 0x7FFF) && (uiZ64 != uiA64) ) { - softfloat_invalidExtF80M( zSPtr ); - return; - } - } - zSPtr->signExp = uiZ64; - zSPtr->signif = UINT64_C( 0x8000000000000000 ); - return; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signZ = signExtF80UI64( uiA64 ); - signB = signExtF80UI64( uiB64 ) ^ negateB; - negateB = (signZ != signB); - if ( expA < expB ) { - signZ = signB; - expA = expB; - expB = expExtF80UI64( uiA64 ); - tempSPtr = aSPtr; - aSPtr = bSPtr; - bSPtr = tempSPtr; - } - if ( ! expB ) { - expB = 1; - if ( ! expA ) expA = 1; - } - sigZ = aSPtr->signif; - sigB = bSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundPackRoutinePtr = softfloat_roundPackMToExtF80M; - expDiff = expA - expB; - if ( expDiff ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - extSigX[indexWord( 3, 2 )] = sigB>>32; - extSigX[indexWord( 3, 1 )] = sigB; - extSigX[indexWord( 3, 0 )] = 0; - softfloat_shiftRightJam96M( extSigX, expDiff, extSigX ); - sigB = - (uint64_t) extSigX[indexWord( 3, 2 )]<<32 - | extSigX[indexWord( 3, 1 )]; - if ( negateB ) { - sigZ -= sigB; - sigZExtra = extSigX[indexWordLo( 3 )]; - if ( sigZExtra ) { - --sigZ; - sigZExtra = -sigZExtra; - } - if ( ! (sigZ & UINT64_C( 0x8000000000000000 )) ) { - if ( sigZ & UINT64_C( 0x4000000000000000 ) ) { - --expA; - sigZ = sigZ<<1 | sigZExtra>>31; - sigZExtra <<= 1; - } else { - roundPackRoutinePtr = softfloat_normRoundPackMToExtF80M; - } - } - } else { - sigZ += sigB; - if ( sigZ & UINT64_C( 0x8000000000000000 ) ) goto sigZ; - sigZExtra = (uint32_t) sigZ<<31 | (extSigX[indexWordLo( 3 )] != 0); - goto completeNormAfterAdd; - } - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sigZExtra = 0; - if ( negateB ) { - if ( sigZ < sigB ) { - signZ = ! signZ; - sigZ = sigB - sigZ; - } else { - sigZ -= sigB; - if ( ! sigZ ) { - signZ = (softfloat_roundingMode == softfloat_round_min); - zSPtr->signExp = packToExtF80UI64( signZ, 0 ); - zSPtr->signif = 0; - return; - } - } - roundPackRoutinePtr = softfloat_normRoundPackMToExtF80M; - } else { - sigZ += sigB; - if ( sigZ < sigB ) { - sigZExtra = (uint32_t) sigZ<<31; - completeNormAfterAdd: - ++expA; - sigZ = UINT64_C( 0x8000000000000000 ) | sigZ>>1; - } else { - if ( ! (sigZ & UINT64_C( 0x8000000000000000 )) ) { - roundPackRoutinePtr = softfloat_normRoundPackMToExtF80M; - } - } - } - } - extSigX[indexWord( 3, 0 )] = sigZExtra; - sigZ: - extSigX[indexWord( 3, 2 )] = sigZ>>32; - extSigX[indexWord( 3, 1 )] = sigZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundPack: - (*roundPackRoutinePtr)( - signZ, expA, extSigX, extF80_roundingPrecision, zSPtr ); - -} - diff --git a/softfloat/source/s_addF128M.c b/softfloat/source/s_addF128M.c deleted file mode 100644 index 8ed9d27..0000000 --- a/softfloat/source/s_addF128M.c +++ /dev/null @@ -1,211 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -void - softfloat_addF128M( - const uint32_t *aWPtr, - const uint32_t *bWPtr, - uint32_t *zWPtr, - bool negateB - ) -{ - uint32_t uiA96; - int32_t expA; - uint32_t uiB96; - int32_t expB; - uint32_t uiZ96; - bool signZ, signB; - const uint32_t *tempPtr; - uint32_t sig96A, sig96B; - int32_t expDiff; - uint_fast8_t - (*addCarryMRoutinePtr)( - uint_fast8_t, - const uint32_t *, - const uint32_t *, - uint_fast8_t, - uint32_t * - ); - uint32_t extSigZ[5], wordSigZ; - uint_fast8_t carry; - void (*roundPackRoutinePtr)( bool, int32_t, uint32_t *, uint32_t * ); - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA96 = aWPtr[indexWordHi( 4 )]; - expA = expF128UI96( uiA96 ); - uiB96 = bWPtr[indexWordHi( 4 )]; - expB = expF128UI96( uiB96 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) { - if ( softfloat_tryPropagateNaNF128M( aWPtr, bWPtr, zWPtr ) ) return; - uiZ96 = uiA96; - if ( expB == 0x7FFF ) { - uiZ96 = uiB96 ^ packToF128UI96( negateB, 0, 0 ); - if ( (expA == 0x7FFF) && (uiZ96 != uiA96) ) { - softfloat_invalidF128M( zWPtr ); - return; - } - } - zWPtr[indexWordHi( 4 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = 0; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - return; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signZ = signF128UI96( uiA96 ); - signB = signF128UI96( uiB96 ) ^ negateB; - negateB = (signZ != signB); - if ( (uint32_t) (uiA96<<1) < (uint32_t) (uiB96<<1) ) { - signZ = signB; - expA = expB; - expB = expF128UI96( uiA96 ); - tempPtr = aWPtr; - aWPtr = bWPtr; - bWPtr = tempPtr; - uiA96 = uiB96; - uiB96 = bWPtr[indexWordHi( 4 )]; - } - sig96A = fracF128UI96( uiA96 ); - sig96B = fracF128UI96( uiB96 ); - if ( expA ) { - --expA; - sig96A |= 0x00010000; - if ( expB ) { - --expB; - sig96B |= 0x00010000; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - addCarryMRoutinePtr = - negateB ? softfloat_addComplCarryM : softfloat_addCarryM; - expDiff = expA - expB; - if ( expDiff ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - extSigZ[indexWordHi( 5 )] = sig96B; - extSigZ[indexWord( 5, 3 )] = bWPtr[indexWord( 4, 2 )]; - extSigZ[indexWord( 5, 2 )] = bWPtr[indexWord( 4, 1 )]; - extSigZ[indexWord( 5, 1 )] = bWPtr[indexWord( 4, 0 )]; - extSigZ[indexWord( 5, 0 )] = 0; - softfloat_shiftRightJam160M( extSigZ, expDiff, extSigZ ); - sig96B = extSigZ[indexWordHi( 5 )]; - carry = 0; - if ( negateB ) { - sig96B = ~sig96B; - wordSigZ = extSigZ[indexWordLo( 5 )]; - extSigZ[indexWordLo( 5 )] = -wordSigZ; - carry = ! wordSigZ; - } - carry = - (*addCarryMRoutinePtr)( - 3, - &aWPtr[indexMultiwordLo( 4, 3 )], - &extSigZ[indexMultiword( 5, 3, 1 )], - carry, - &extSigZ[indexMultiword( 5, 3, 1 )] - ); - wordSigZ = sig96A + sig96B + carry; - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - extSigZ[indexWordLo( 5 )] = 0; - carry = - (*addCarryMRoutinePtr)( - 3, - &aWPtr[indexMultiwordLo( 4, 3 )], - &bWPtr[indexMultiwordLo( 4, 3 )], - negateB, - &extSigZ[indexMultiword( 5, 3, 1 )] - ); - if ( negateB ) { - wordSigZ = sig96A + ~sig96B + carry; - if ( wordSigZ & 0x80000000 ) { - signZ = ! signZ; - carry = - softfloat_addComplCarry96M( - &bWPtr[indexMultiwordLo( 4, 3 )], - &aWPtr[indexMultiwordLo( 4, 3 )], - 1, - &extSigZ[indexMultiword( 5, 3, 1 )] - ); - wordSigZ = sig96B + ~sig96A + carry; - } else { - if ( - ! wordSigZ && ! extSigZ[indexWord( 5, 3 )] - && ! ( extSigZ[indexWord( 5, 2 )] - | extSigZ[indexWord( 5, 1 )] - | extSigZ[indexWord( 5, 0 )] - ) - ) { - signZ = (softfloat_roundingMode == softfloat_round_min); - zWPtr[indexWordHi( 4 )] = packToF128UI96( signZ, 0, 0 ); - zWPtr[indexWord( 4, 2 )] = 0; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - return; - } - } - } else { - wordSigZ = sig96A + sig96B + carry; - } - } - extSigZ[indexWordHi( 5 )] = wordSigZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundPackRoutinePtr = softfloat_normRoundPackMToF128M; - if ( 0x00010000 <= wordSigZ ) { - if ( 0x00020000 <= wordSigZ ) { - ++expA; - softfloat_shortShiftRightJam160M( extSigZ, 1, extSigZ ); - } - roundPackRoutinePtr = softfloat_roundPackMToF128M; - } - (*roundPackRoutinePtr)( signZ, expA, extSigZ, zWPtr ); - -} - diff --git a/softfloat/source/s_addM.c b/softfloat/source/s_addM.c deleted file mode 100644 index c935baa..0000000 --- a/softfloat/source/s_addM.c +++ /dev/null @@ -1,70 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_addM - -void - softfloat_addM( - uint_fast8_t size_words, - const uint32_t *aPtr, - const uint32_t *bPtr, - uint32_t *zPtr - ) -{ - unsigned int index, lastIndex; - uint_fast8_t carry; - uint32_t wordA, wordZ; - - index = indexWordLo( size_words ); - lastIndex = indexWordHi( size_words ); - carry = 0; - for (;;) { - wordA = aPtr[index]; - wordZ = wordA + bPtr[index] + carry; - zPtr[index] = wordZ; - if ( index == lastIndex ) break; - if ( wordZ != wordA ) carry = (wordZ < wordA); - index += wordIncr; - } - -} - -#endif - diff --git a/softfloat/source/s_addMagsExtF80.c b/softfloat/source/s_addMagsExtF80.c deleted file mode 100644 index b1bb5db..0000000 --- a/softfloat/source/s_addMagsExtF80.c +++ /dev/null @@ -1,156 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t - softfloat_addMagsExtF80( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0, - bool signZ - ) -{ - int_fast32_t expA; - uint_fast64_t sigA; - int_fast32_t expB; - uint_fast64_t sigB; - int_fast32_t expDiff; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0, sigZ, sigZExtra; - struct exp32_sig64 normExpSig; - int_fast32_t expZ; - struct uint64_extra sig64Extra; - struct uint128 uiZ; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = expExtF80UI64( uiA64 ); - sigA = uiA0; - expB = expExtF80UI64( uiB64 ); - sigB = uiB0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( ! expDiff ) { - if ( expA == 0x7FFF ) { - if ( (sigA | sigB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - goto propagateNaN; - } - uiZ64 = uiA64; - uiZ0 = uiA0; - goto uiZ; - } - sigZ = sigA + sigB; - sigZExtra = 0; - if ( ! expA ) { - normExpSig = softfloat_normSubnormalExtF80Sig( sigZ ); - expZ = normExpSig.exp + 1; - sigZ = normExpSig.sig; - goto roundAndPack; - } - expZ = expA; - goto shiftRight1; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expDiff < 0 ) { - if ( expB == 0x7FFF ) { - if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN; - uiZ64 = packToExtF80UI64( signZ, 0x7FFF ); - uiZ0 = uiB0; - goto uiZ; - } - expZ = expB; - if ( ! expA ) { - ++expDiff; - sigZExtra = 0; - if ( ! expDiff ) goto newlyAligned; - } - sig64Extra = softfloat_shiftRightJam64Extra( sigA, 0, -expDiff ); - sigA = sig64Extra.v; - sigZExtra = sig64Extra.extra; - } else { - if ( expA == 0x7FFF ) { - if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN; - uiZ64 = uiA64; - uiZ0 = uiA0; - goto uiZ; - } - expZ = expA; - if ( ! expB ) { - --expDiff; - sigZExtra = 0; - if ( ! expDiff ) goto newlyAligned; - } - sig64Extra = softfloat_shiftRightJam64Extra( sigB, 0, expDiff ); - sigB = sig64Extra.v; - sigZExtra = sig64Extra.extra; - } - newlyAligned: - sigZ = sigA + sigB; - if ( sigZ & UINT64_C( 0x8000000000000000 ) ) goto roundAndPack; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftRight1: - sig64Extra = softfloat_shortShiftRightJam64Extra( sigZ, sigZExtra, 1 ); - sigZ = sig64Extra.v | UINT64_C( 0x8000000000000000 ); - sigZExtra = sig64Extra.extra; - ++expZ; - roundAndPack: - return - softfloat_roundPackToExtF80( - signZ, expZ, sigZ, sigZExtra, extF80_roundingPrecision ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 ); - uiZ64 = uiZ.v64; - uiZ0 = uiZ.v0; - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/s_addMagsF128.c b/softfloat/source/s_addMagsF128.c deleted file mode 100644 index 8e5ce5b..0000000 --- a/softfloat/source/s_addMagsF128.c +++ /dev/null @@ -1,154 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" - -float128_t - softfloat_addMagsF128( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0, - bool signZ - ) -{ - int_fast32_t expA; - struct uint128 sigA; - int_fast32_t expB; - struct uint128 sigB; - int_fast32_t expDiff; - struct uint128 uiZ, sigZ; - int_fast32_t expZ; - uint_fast64_t sigZExtra; - struct uint128_extra sig128Extra; - union ui128_f128 uZ; - - expA = expF128UI64( uiA64 ); - sigA.v64 = fracF128UI64( uiA64 ); - sigA.v0 = uiA0; - expB = expF128UI64( uiB64 ); - sigB.v64 = fracF128UI64( uiB64 ); - sigB.v0 = uiB0; - expDiff = expA - expB; - if ( ! expDiff ) { - if ( expA == 0x7FFF ) { - if ( sigA.v64 | sigA.v0 | sigB.v64 | sigB.v0 ) goto propagateNaN; - uiZ.v64 = uiA64; - uiZ.v0 = uiA0; - goto uiZ; - } - sigZ = softfloat_add128( sigA.v64, sigA.v0, sigB.v64, sigB.v0 ); - if ( ! expA ) { - uiZ.v64 = packToF128UI64( signZ, 0, sigZ.v64 ); - uiZ.v0 = sigZ.v0; - goto uiZ; - } - expZ = expA; - sigZ.v64 |= UINT64_C( 0x0002000000000000 ); - sigZExtra = 0; - goto shiftRight1; - } - if ( expDiff < 0 ) { - if ( expB == 0x7FFF ) { - if ( sigB.v64 | sigB.v0 ) goto propagateNaN; - uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 ); - uiZ.v0 = 0; - goto uiZ; - } - expZ = expB; - if ( expA ) { - sigA.v64 |= UINT64_C( 0x0001000000000000 ); - } else { - ++expDiff; - sigZExtra = 0; - if ( ! expDiff ) goto newlyAligned; - } - sig128Extra = - softfloat_shiftRightJam128Extra( sigA.v64, sigA.v0, 0, -expDiff ); - sigA = sig128Extra.v; - sigZExtra = sig128Extra.extra; - } else { - if ( expA == 0x7FFF ) { - if ( sigA.v64 | sigA.v0 ) goto propagateNaN; - uiZ.v64 = uiA64; - uiZ.v0 = uiA0; - goto uiZ; - } - expZ = expA; - if ( expB ) { - sigB.v64 |= UINT64_C( 0x0001000000000000 ); - } else { - --expDiff; - sigZExtra = 0; - if ( ! expDiff ) goto newlyAligned; - } - sig128Extra = - softfloat_shiftRightJam128Extra( sigB.v64, sigB.v0, 0, expDiff ); - sigB = sig128Extra.v; - sigZExtra = sig128Extra.extra; - } - newlyAligned: - sigZ = - softfloat_add128( - sigA.v64 | UINT64_C( 0x0001000000000000 ), - sigA.v0, - sigB.v64, - sigB.v0 - ); - --expZ; - if ( sigZ.v64 < UINT64_C( 0x0002000000000000 ) ) goto roundAndPack; - ++expZ; - shiftRight1: - sig128Extra = - softfloat_shortShiftRightJam128Extra( - sigZ.v64, sigZ.v0, sigZExtra, 1 ); - sigZ = sig128Extra.v; - sigZExtra = sig128Extra.extra; - roundAndPack: - return - softfloat_roundPackToF128( signZ, expZ, sigZ.v64, sigZ.v0, sigZExtra ); - propagateNaN: - uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_addMagsF16.c b/softfloat/source/s_addMagsF16.c deleted file mode 100644 index b7fba09..0000000 --- a/softfloat/source/s_addMagsF16.c +++ /dev/null @@ -1,183 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float16_t softfloat_addMagsF16( uint_fast16_t uiA, uint_fast16_t uiB ) -{ - int_fast8_t expA; - uint_fast16_t sigA; - int_fast8_t expB; - uint_fast16_t sigB; - int_fast8_t expDiff; - uint_fast16_t uiZ; - bool signZ; - int_fast8_t expZ; - uint_fast16_t sigZ; - uint_fast16_t sigX, sigY; - int_fast8_t shiftDist; - uint_fast32_t sig32Z; - int_fast8_t roundingMode; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = expF16UI( uiA ); - sigA = fracF16UI( uiA ); - expB = expF16UI( uiB ); - sigB = fracF16UI( uiB ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( ! expDiff ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( ! expA ) { - uiZ = uiA + sigB; - goto uiZ; - } - if ( expA == 0x1F ) { - if ( sigA | sigB ) goto propagateNaN; - uiZ = uiA; - goto uiZ; - } - signZ = signF16UI( uiA ); - expZ = expA; - sigZ = 0x0800 + sigA + sigB; - if ( ! (sigZ & 1) && (expZ < 0x1E) ) { - sigZ >>= 1; - goto pack; - } - sigZ <<= 3; - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - signZ = signF16UI( uiA ); - if ( expDiff < 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - if ( expB == 0x1F ) { - if ( sigB ) goto propagateNaN; - uiZ = packToF16UI( signZ, 0x1F, 0 ); - goto uiZ; - } - if ( expDiff <= -13 ) { - uiZ = packToF16UI( signZ, expB, sigB ); - if ( expA | sigA ) goto addEpsilon; - goto uiZ; - } - expZ = expB; - sigX = sigB | 0x0400; - sigY = sigA + (expA ? 0x0400 : sigA); - shiftDist = 19 + expDiff; - } else { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - uiZ = uiA; - if ( expA == 0x1F ) { - if ( sigA ) goto propagateNaN; - goto uiZ; - } - if ( 13 <= expDiff ) { - if ( expB | sigB ) goto addEpsilon; - goto uiZ; - } - expZ = expA; - sigX = sigA | 0x0400; - sigY = sigB + (expB ? 0x0400 : sigB); - shiftDist = 19 - expDiff; - } - sig32Z = - ((uint_fast32_t) sigX<<19) + ((uint_fast32_t) sigY<>16; - if ( sig32Z & 0xFFFF ) { - sigZ |= 1; - } else { - if ( ! (sigZ & 0xF) && (expZ < 0x1E) ) { - sigZ >>= 4; - goto pack; - } - } - } - return softfloat_roundPackToF16( signZ, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - addEpsilon: - roundingMode = softfloat_roundingMode; - if ( roundingMode != softfloat_round_near_even ) { - if ( - roundingMode - == (signF16UI( uiZ ) ? softfloat_round_min - : softfloat_round_max) - ) { - ++uiZ; - if ( (uint16_t) (uiZ<<1) == 0xF800 ) { - softfloat_raiseFlags( - softfloat_flag_overflow | softfloat_flag_inexact ); - } - } -#ifdef SOFTFLOAT_ROUND_ODD - else if ( roundingMode == softfloat_round_odd ) { - uiZ |= 1; - } -#endif - } - softfloat_exceptionFlags |= softfloat_flag_inexact; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - pack: - uiZ = packToF16UI( signZ, expZ, sigZ ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_addMagsF32.c b/softfloat/source/s_addMagsF32.c deleted file mode 100644 index b74489d..0000000 --- a/softfloat/source/s_addMagsF32.c +++ /dev/null @@ -1,126 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" - -float32_t softfloat_addMagsF32( uint_fast32_t uiA, uint_fast32_t uiB ) -{ - int_fast16_t expA; - uint_fast32_t sigA; - int_fast16_t expB; - uint_fast32_t sigB; - int_fast16_t expDiff; - uint_fast32_t uiZ; - bool signZ; - int_fast16_t expZ; - uint_fast32_t sigZ; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = expF32UI( uiA ); - sigA = fracF32UI( uiA ); - expB = expF32UI( uiB ); - sigB = fracF32UI( uiB ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( ! expDiff ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( ! expA ) { - uiZ = uiA + sigB; - goto uiZ; - } - if ( expA == 0xFF ) { - if ( sigA | sigB ) goto propagateNaN; - uiZ = uiA; - goto uiZ; - } - signZ = signF32UI( uiA ); - expZ = expA; - sigZ = 0x01000000 + sigA + sigB; - if ( ! (sigZ & 1) && (expZ < 0xFE) ) { - uiZ = packToF32UI( signZ, expZ, sigZ>>1 ); - goto uiZ; - } - sigZ <<= 6; - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - signZ = signF32UI( uiA ); - sigA <<= 6; - sigB <<= 6; - if ( expDiff < 0 ) { - if ( expB == 0xFF ) { - if ( sigB ) goto propagateNaN; - uiZ = packToF32UI( signZ, 0xFF, 0 ); - goto uiZ; - } - expZ = expB; - sigA += expA ? 0x20000000 : sigA; - sigA = softfloat_shiftRightJam32( sigA, -expDiff ); - } else { - if ( expA == 0xFF ) { - if ( sigA ) goto propagateNaN; - uiZ = uiA; - goto uiZ; - } - expZ = expA; - sigB += expB ? 0x20000000 : sigB; - sigB = softfloat_shiftRightJam32( sigB, expDiff ); - } - sigZ = 0x20000000 + sigA + sigB; - if ( sigZ < 0x40000000 ) { - --expZ; - sigZ <<= 1; - } - } - return softfloat_roundPackToF32( signZ, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF32UI( uiA, uiB ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_addMagsF64.c b/softfloat/source/s_addMagsF64.c deleted file mode 100644 index e8a4898..0000000 --- a/softfloat/source/s_addMagsF64.c +++ /dev/null @@ -1,128 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" - -float64_t - softfloat_addMagsF64( uint_fast64_t uiA, uint_fast64_t uiB, bool signZ ) -{ - int_fast16_t expA; - uint_fast64_t sigA; - int_fast16_t expB; - uint_fast64_t sigB; - int_fast16_t expDiff; - uint_fast64_t uiZ; - int_fast16_t expZ; - uint_fast64_t sigZ; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = expF64UI( uiA ); - sigA = fracF64UI( uiA ); - expB = expF64UI( uiB ); - sigB = fracF64UI( uiB ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( ! expDiff ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( ! expA ) { - uiZ = uiA + sigB; - goto uiZ; - } - if ( expA == 0x7FF ) { - if ( sigA | sigB ) goto propagateNaN; - uiZ = uiA; - goto uiZ; - } - expZ = expA; - sigZ = UINT64_C( 0x0020000000000000 ) + sigA + sigB; - sigZ <<= 9; - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sigA <<= 9; - sigB <<= 9; - if ( expDiff < 0 ) { - if ( expB == 0x7FF ) { - if ( sigB ) goto propagateNaN; - uiZ = packToF64UI( signZ, 0x7FF, 0 ); - goto uiZ; - } - expZ = expB; - if ( expA ) { - sigA += UINT64_C( 0x2000000000000000 ); - } else { - sigA <<= 1; - } - sigA = softfloat_shiftRightJam64( sigA, -expDiff ); - } else { - if ( expA == 0x7FF ) { - if ( sigA ) goto propagateNaN; - uiZ = uiA; - goto uiZ; - } - expZ = expA; - if ( expB ) { - sigB += UINT64_C( 0x2000000000000000 ); - } else { - sigB <<= 1; - } - sigB = softfloat_shiftRightJam64( sigB, expDiff ); - } - sigZ = UINT64_C( 0x2000000000000000 ) + sigA + sigB; - if ( sigZ < UINT64_C( 0x4000000000000000 ) ) { - --expZ; - sigZ <<= 1; - } - } - return softfloat_roundPackToF64( signZ, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_approxRecip32_1.c b/softfloat/source/s_approxRecip32_1.c deleted file mode 100644 index 4a326a4..0000000 --- a/softfloat/source/s_approxRecip32_1.c +++ /dev/null @@ -1,66 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_approxRecip32_1 - -extern const uint16_t softfloat_approxRecip_1k0s[16]; -extern const uint16_t softfloat_approxRecip_1k1s[16]; - -uint32_t softfloat_approxRecip32_1( uint32_t a ) -{ - int index; - uint16_t eps, r0; - uint32_t sigma0; - uint_fast32_t r; - uint32_t sqrSigma0; - - index = a>>27 & 0xF; - eps = (uint16_t) (a>>11); - r0 = softfloat_approxRecip_1k0s[index] - - ((softfloat_approxRecip_1k1s[index] * (uint_fast32_t) eps)>>20); - sigma0 = ~(uint_fast32_t) ((r0 * (uint_fast64_t) a)>>7); - r = ((uint_fast32_t) r0<<16) + ((r0 * (uint_fast64_t) sigma0)>>24); - sqrSigma0 = ((uint_fast64_t) sigma0 * sigma0)>>32; - r += ((uint32_t) r * (uint_fast64_t) sqrSigma0)>>48; - return r; - -} - -#endif - diff --git a/softfloat/source/s_approxRecipSqrt32_1.c b/softfloat/source/s_approxRecipSqrt32_1.c deleted file mode 100644 index b3fdeba..0000000 --- a/softfloat/source/s_approxRecipSqrt32_1.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_approxRecipSqrt32_1 - -extern const uint16_t softfloat_approxRecipSqrt_1k0s[]; -extern const uint16_t softfloat_approxRecipSqrt_1k1s[]; - -uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a ) -{ - int index; - uint16_t eps, r0; - uint_fast32_t ESqrR0; - uint32_t sigma0; - uint_fast32_t r; - uint32_t sqrSigma0; - - index = (a>>27 & 0xE) + oddExpA; - eps = (uint16_t) (a>>12); - r0 = softfloat_approxRecipSqrt_1k0s[index] - - ((softfloat_approxRecipSqrt_1k1s[index] * (uint_fast32_t) eps) - >>20); - ESqrR0 = (uint_fast32_t) r0 * r0; - if ( ! oddExpA ) ESqrR0 <<= 1; - sigma0 = ~(uint_fast32_t) (((uint32_t) ESqrR0 * (uint_fast64_t) a)>>23); - r = ((uint_fast32_t) r0<<16) + ((r0 * (uint_fast64_t) sigma0)>>25); - sqrSigma0 = ((uint_fast64_t) sigma0 * sigma0)>>32; - r += ((uint32_t) ((r>>1) + (r>>3) - ((uint_fast32_t) r0<<14)) - * (uint_fast64_t) sqrSigma0) - >>48; - if ( ! (r & 0x80000000) ) r = 0x80000000; - return r; - -} - -#endif - diff --git a/softfloat/source/s_approxRecipSqrt_1Ks.c b/softfloat/source/s_approxRecipSqrt_1Ks.c deleted file mode 100644 index 38a2798..0000000 --- a/softfloat/source/s_approxRecipSqrt_1Ks.c +++ /dev/null @@ -1,49 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" - -const uint16_t softfloat_approxRecipSqrt_1k0s[16] = { - 0xB4C9, 0xFFAB, 0xAA7D, 0xF11C, 0xA1C5, 0xE4C7, 0x9A43, 0xDA29, - 0x93B5, 0xD0E5, 0x8DED, 0xC8B7, 0x88C6, 0xC16D, 0x8424, 0xBAE1 -}; -const uint16_t softfloat_approxRecipSqrt_1k1s[16] = { - 0xA5A5, 0xEA42, 0x8C21, 0xC62D, 0x788F, 0xAA7F, 0x6928, 0x94B6, - 0x5CC7, 0x8335, 0x52A6, 0x74E2, 0x4A3E, 0x68FE, 0x432B, 0x5EFD -}; - diff --git a/softfloat/source/s_approxRecip_1Ks.c b/softfloat/source/s_approxRecip_1Ks.c deleted file mode 100644 index f1fca74..0000000 --- a/softfloat/source/s_approxRecip_1Ks.c +++ /dev/null @@ -1,49 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" - -const uint16_t softfloat_approxRecip_1k0s[16] = { - 0xFFC4, 0xF0BE, 0xE363, 0xD76F, 0xCCAD, 0xC2F0, 0xBA16, 0xB201, - 0xAA97, 0xA3C6, 0x9D7A, 0x97A6, 0x923C, 0x8D32, 0x887E, 0x8417 -}; -const uint16_t softfloat_approxRecip_1k1s[16] = { - 0xF0F1, 0xD62C, 0xBFA1, 0xAC77, 0x9C0A, 0x8DDB, 0x8185, 0x76BA, - 0x6D3B, 0x64D4, 0x5D5C, 0x56B1, 0x50B6, 0x4B55, 0x4679, 0x4211 -}; - diff --git a/softfloat/source/s_compare128M.c b/softfloat/source/s_compare128M.c deleted file mode 100644 index dc97ce9..0000000 --- a/softfloat/source/s_compare128M.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_compare128M - -int_fast8_t softfloat_compare128M( const uint32_t *aPtr, const uint32_t *bPtr ) -{ - unsigned int index, lastIndex; - uint32_t wordA, wordB; - - index = indexWordHi( 4 ); - lastIndex = indexWordLo( 4 ); - for (;;) { - wordA = aPtr[index]; - wordB = bPtr[index]; - if ( wordA != wordB ) return (wordA < wordB) ? -1 : 1; - if ( index == lastIndex ) break; - index -= wordIncr; - } - return 0; - -} - -#endif - diff --git a/softfloat/source/s_compare96M.c b/softfloat/source/s_compare96M.c deleted file mode 100644 index 2681c46..0000000 --- a/softfloat/source/s_compare96M.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_compare96M - -int_fast8_t softfloat_compare96M( const uint32_t *aPtr, const uint32_t *bPtr ) -{ - unsigned int index, lastIndex; - uint32_t wordA, wordB; - - index = indexWordHi( 3 ); - lastIndex = indexWordLo( 3 ); - for (;;) { - wordA = aPtr[index]; - wordB = bPtr[index]; - if ( wordA != wordB ) return (wordA < wordB) ? -1 : 1; - if ( index == lastIndex ) break; - index -= wordIncr; - } - return 0; - -} - -#endif - diff --git a/softfloat/source/s_compareNonnormExtF80M.c b/softfloat/source/s_compareNonnormExtF80M.c deleted file mode 100644 index 2673153..0000000 --- a/softfloat/source/s_compareNonnormExtF80M.c +++ /dev/null @@ -1,111 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat_types.h" - -int - softfloat_compareNonnormExtF80M( - const struct extFloat80M *aSPtr, const struct extFloat80M *bSPtr ) -{ - uint_fast16_t uiA64, uiB64; - uint64_t sigA; - bool signB; - uint64_t sigB; - int32_t expA, expB; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA64 = aSPtr->signExp; - uiB64 = bSPtr->signExp; - sigA = aSPtr->signif; - signB = signExtF80UI64( uiB64 ); - sigB = bSPtr->signif; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( (uiA64 ^ uiB64) & 0x8000 ) { - if ( ! (sigA | sigB) ) return 0; - goto resultFromSignB; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = expExtF80UI64( uiA64 ); - expB = expExtF80UI64( uiB64 ); - if ( expA == 0x7FFF ) { - if (expB == 0x7FFF) return 0; - signB = ! signB; - goto resultFromSignB; - } - if ( expB == 0x7FFF ) { - goto resultFromSignB; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) expA = 1; - if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) { - if ( sigA ) { - expA += softfloat_normExtF80SigM( &sigA ); - } else { - expA = -128; - } - } - if ( ! expB ) expB = 1; - if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) { - if ( sigB ) { - expB += softfloat_normExtF80SigM( &sigB ); - } else { - expB = -128; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( signB ) { - if ( expA < expB ) return 1; - if ( (expB < expA) || (sigB < sigA) ) return -1; - } else { - if ( expB < expA ) return 1; - if ( (expA < expB) || (sigA < sigB) ) return -1; - } - return (sigA != sigB); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - resultFromSignB: - return signB ? 1 : -1; - -} - diff --git a/softfloat/source/s_countLeadingZeros16.c b/softfloat/source/s_countLeadingZeros16.c deleted file mode 100644 index 7a68da5..0000000 --- a/softfloat/source/s_countLeadingZeros16.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_countLeadingZeros16 - -#define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16 -#include "primitives.h" - -uint_fast8_t softfloat_countLeadingZeros16( uint16_t a ) -{ - uint_fast8_t count; - - count = 8; - if ( 0x100 <= a ) { - count = 0; - a >>= 8; - } - count += softfloat_countLeadingZeros8[a]; - return count; - -} - -#endif - diff --git a/softfloat/source/s_countLeadingZeros32.c b/softfloat/source/s_countLeadingZeros32.c deleted file mode 100644 index 53ab228..0000000 --- a/softfloat/source/s_countLeadingZeros32.c +++ /dev/null @@ -1,64 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_countLeadingZeros32 - -#define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32 -#include "primitives.h" - -uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ) -{ - uint_fast8_t count; - - count = 0; - if ( a < 0x10000 ) { - count = 16; - a <<= 16; - } - if ( a < 0x1000000 ) { - count += 8; - a <<= 8; - } - count += softfloat_countLeadingZeros8[a>>24]; - return count; - -} - -#endif - diff --git a/softfloat/source/s_countLeadingZeros64.c b/softfloat/source/s_countLeadingZeros64.c deleted file mode 100644 index 13a2224..0000000 --- a/softfloat/source/s_countLeadingZeros64.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_countLeadingZeros64 - -#define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64 -#include "primitives.h" - -uint_fast8_t softfloat_countLeadingZeros64( uint64_t a ) -{ - uint_fast8_t count; - uint32_t a32; - - count = 0; - a32 = a>>32; - if ( ! a32 ) { - count = 32; - a32 = a; - } - /*------------------------------------------------------------------------ - | From here, result is current count + count leading zeros of `a32'. - *------------------------------------------------------------------------*/ - if ( a32 < 0x10000 ) { - count += 16; - a32 <<= 16; - } - if ( a32 < 0x1000000 ) { - count += 8; - a32 <<= 8; - } - count += softfloat_countLeadingZeros8[a32>>24]; - return count; - -} - -#endif - diff --git a/softfloat/source/s_countLeadingZeros8.c b/softfloat/source/s_countLeadingZeros8.c deleted file mode 100644 index a56f5a4..0000000 --- a/softfloat/source/s_countLeadingZeros8.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" - -const uint_least8_t softfloat_countLeadingZeros8[256] = { - 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - diff --git a/softfloat/source/s_eq128.c b/softfloat/source/s_eq128.c deleted file mode 100644 index 275b8ae..0000000 --- a/softfloat/source/s_eq128.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" - -#ifndef softfloat_eq128 - -bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) -{ - - return (a64 == b64) && (a0 == b0); - -} - -#endif - diff --git a/softfloat/source/s_invalidExtF80M.c b/softfloat/source/s_invalidExtF80M.c deleted file mode 100644 index 237d217..0000000 --- a/softfloat/source/s_invalidExtF80M.c +++ /dev/null @@ -1,49 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include "platform.h" -#include "specialize.h" -#include "softfloat.h" - -void softfloat_invalidExtF80M( struct extFloat80M *zSPtr ) -{ - - softfloat_raiseFlags( softfloat_flag_invalid ); - zSPtr->signExp = defaultNaNExtF80UI64; - zSPtr->signif = defaultNaNExtF80UI0; - -} - diff --git a/softfloat/source/s_invalidF128M.c b/softfloat/source/s_invalidF128M.c deleted file mode 100644 index a20840e..0000000 --- a/softfloat/source/s_invalidF128M.c +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitives.h" -#include "specialize.h" -#include "softfloat.h" - -void softfloat_invalidF128M( uint32_t *zWPtr ) -{ - - softfloat_raiseFlags( softfloat_flag_invalid ); - zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96; - zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64; - zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32; - zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0; - -} - diff --git a/softfloat/source/s_isNaNF128M.c b/softfloat/source/s_isNaNF128M.c deleted file mode 100644 index 6008cf3..0000000 --- a/softfloat/source/s_isNaNF128M.c +++ /dev/null @@ -1,57 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "primitives.h" - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -bool softfloat_isNaNF128M( const uint32_t *aWPtr ) -{ - uint32_t uiA96; - - uiA96 = aWPtr[indexWordHi( 4 )]; - if ( (~uiA96 & 0x7FFF0000) != 0 ) return false; - return - ((uiA96 & 0x0000FFFF) != 0) - || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )] - | aWPtr[indexWord( 4, 0 )]) - != 0); - -} - diff --git a/softfloat/source/s_le128.c b/softfloat/source/s_le128.c deleted file mode 100644 index 1fce7af..0000000 --- a/softfloat/source/s_le128.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" - -#ifndef softfloat_le128 - -bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) -{ - - return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); - -} - -#endif - diff --git a/softfloat/source/s_lt128.c b/softfloat/source/s_lt128.c deleted file mode 100644 index d7ce3b9..0000000 --- a/softfloat/source/s_lt128.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" - -#ifndef softfloat_lt128 - -bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) -{ - - return (a64 < b64) || ((a64 == b64) && (a0 < b0)); - -} - -#endif - diff --git a/softfloat/source/s_mul128By32.c b/softfloat/source/s_mul128By32.c deleted file mode 100644 index 7c0fdc8..0000000 --- a/softfloat/source/s_mul128By32.c +++ /dev/null @@ -1,58 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_mul128By32 - -struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b ) -{ - struct uint128 z; - uint_fast64_t mid; - uint_fast32_t carry; - - z.v0 = a0 * b; - mid = (uint_fast64_t) (uint32_t) (a0>>32) * b; - carry = (uint32_t) ((uint_fast32_t) (z.v0>>32) - (uint_fast32_t) mid); - z.v64 = a64 * b + (uint_fast32_t) ((mid + carry)>>32); - return z; - -} - -#endif - diff --git a/softfloat/source/s_mul128MTo256M.c b/softfloat/source/s_mul128MTo256M.c deleted file mode 100644 index ea8865e..0000000 --- a/softfloat/source/s_mul128MTo256M.c +++ /dev/null @@ -1,100 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_mul128MTo256M - -void - softfloat_mul128MTo256M( - const uint32_t *aPtr, const uint32_t *bPtr, uint32_t *zPtr ) -{ - uint32_t *lastZPtr, wordB; - uint64_t dwordProd; - uint32_t wordZ; - uint_fast8_t carry; - - bPtr += indexWordLo( 4 ); - lastZPtr = zPtr + indexMultiwordHi( 8, 5 ); - zPtr += indexMultiwordLo( 8, 5 ); - wordB = *bPtr; - dwordProd = (uint64_t) aPtr[indexWord( 4, 0 )] * wordB; - zPtr[indexWord( 5, 0 )] = dwordProd; - dwordProd = (uint64_t) aPtr[indexWord( 4, 1 )] * wordB + (dwordProd>>32); - zPtr[indexWord( 5, 1 )] = dwordProd; - dwordProd = (uint64_t) aPtr[indexWord( 4, 2 )] * wordB + (dwordProd>>32); - zPtr[indexWord( 5, 2 )] = dwordProd; - dwordProd = (uint64_t) aPtr[indexWord( 4, 3 )] * wordB + (dwordProd>>32); - zPtr[indexWord( 5, 3 )] = dwordProd; - zPtr[indexWord( 5, 4 )] = dwordProd>>32; - do { - bPtr += wordIncr; - zPtr += wordIncr; - wordB = *bPtr; - dwordProd = (uint64_t) aPtr[indexWord( 4, 0 )] * wordB; - wordZ = zPtr[indexWord( 5, 0 )] + (uint32_t) dwordProd; - zPtr[indexWord( 5, 0 )] = wordZ; - carry = (wordZ < (uint32_t) dwordProd); - dwordProd = - (uint64_t) aPtr[indexWord( 4, 1 )] * wordB + (dwordProd>>32); - wordZ = zPtr[indexWord( 5, 1 )] + (uint32_t) dwordProd + carry; - zPtr[indexWord( 5, 1 )] = wordZ; - if ( wordZ != (uint32_t) dwordProd ) { - carry = (wordZ < (uint32_t) dwordProd); - } - dwordProd = - (uint64_t) aPtr[indexWord( 4, 2 )] * wordB + (dwordProd>>32); - wordZ = zPtr[indexWord( 5, 2 )] + (uint32_t) dwordProd + carry; - zPtr[indexWord( 5, 2 )] = wordZ; - if ( wordZ != (uint32_t) dwordProd ) { - carry = (wordZ < (uint32_t) dwordProd); - } - dwordProd = - (uint64_t) aPtr[indexWord( 4, 3 )] * wordB + (dwordProd>>32); - wordZ = zPtr[indexWord( 5, 3 )] + (uint32_t) dwordProd + carry; - zPtr[indexWord( 5, 3 )] = wordZ; - if ( wordZ != (uint32_t) dwordProd ) { - carry = (wordZ < (uint32_t) dwordProd); - } - zPtr[indexWord( 5, 4 )] = (dwordProd>>32) + carry; - } while ( zPtr != lastZPtr ); - -} - -#endif - diff --git a/softfloat/source/s_mul128To256M.c b/softfloat/source/s_mul128To256M.c deleted file mode 100644 index 7c9d9b5..0000000 --- a/softfloat/source/s_mul128To256M.c +++ /dev/null @@ -1,71 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_mul128To256M - -#define softfloat_mul128To256M softfloat_mul128To256M -#include "primitives.h" - -void - softfloat_mul128To256M( - uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr ) -{ - struct uint128 p0, p64, p128; - uint_fast64_t z64, z128, z192; - - p0 = softfloat_mul64To128( a0, b0 ); - zPtr[indexWord( 4, 0 )] = p0.v0; - p64 = softfloat_mul64To128( a64, b0 ); - z64 = p64.v0 + p0.v64; - z128 = p64.v64 + (z64 < p64.v0); - p128 = softfloat_mul64To128( a64, b64 ); - z128 += p128.v0; - z192 = p128.v64 + (z128 < p128.v0); - p64 = softfloat_mul64To128( a0, b64 ); - z64 += p64.v0; - zPtr[indexWord( 4, 1 )] = z64; - p64.v64 += (z64 < p64.v0); - z128 += p64.v64; - zPtr[indexWord( 4, 2 )] = z128; - zPtr[indexWord( 4, 3 )] = z192 + (z128 < p64.v64); - -} - -#endif - diff --git a/softfloat/source/s_mul64ByShifted32To128.c b/softfloat/source/s_mul64ByShifted32To128.c deleted file mode 100644 index 57e5288..0000000 --- a/softfloat/source/s_mul64ByShifted32To128.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_mul64ByShifted32To128 - -struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ) -{ - uint_fast64_t mid; - struct uint128 z; - - mid = (uint_fast64_t) (uint32_t) a * b; - z.v0 = mid<<32; - z.v64 = (uint_fast64_t) (uint32_t) (a>>32) * b + (mid>>32); - return z; - -} - -#endif - diff --git a/softfloat/source/s_mul64To128.c b/softfloat/source/s_mul64To128.c deleted file mode 100644 index 5d360aa..0000000 --- a/softfloat/source/s_mul64To128.c +++ /dev/null @@ -1,66 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_mul64To128 - -struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b ) -{ - uint32_t a32, a0, b32, b0; - struct uint128 z; - uint64_t mid1, mid; - - a32 = a>>32; - a0 = a; - b32 = b>>32; - b0 = b; - z.v0 = (uint_fast64_t) a0 * b0; - mid1 = (uint_fast64_t) a32 * b0; - mid = mid1 + (uint_fast64_t) a0 * b32; - z.v64 = (uint_fast64_t) a32 * b32; - z.v64 += (uint_fast64_t) (mid < mid1)<<32 | mid>>32; - mid <<= 32; - z.v0 += mid; - z.v64 += (z.v0 < mid); - return z; - -} - -#endif - diff --git a/softfloat/source/s_mul64To128M.c b/softfloat/source/s_mul64To128M.c deleted file mode 100644 index ed10be3..0000000 --- a/softfloat/source/s_mul64To128M.c +++ /dev/null @@ -1,68 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_mul64To128M - -void softfloat_mul64To128M( uint64_t a, uint64_t b, uint32_t *zPtr ) -{ - uint32_t a32, a0, b32, b0; - uint64_t z0, mid1, z64, mid; - - a32 = a>>32; - a0 = a; - b32 = b>>32; - b0 = b; - z0 = (uint64_t) a0 * b0; - mid1 = (uint64_t) a32 * b0; - mid = mid1 + (uint64_t) a0 * b32; - z64 = (uint64_t) a32 * b32; - z64 += (uint64_t) (mid < mid1)<<32 | mid>>32; - mid <<= 32; - z0 += mid; - zPtr[indexWord( 4, 1 )] = z0>>32; - zPtr[indexWord( 4, 0 )] = z0; - z64 += (z0 < mid); - zPtr[indexWord( 4, 3 )] = z64>>32; - zPtr[indexWord( 4, 2 )] = z64; - -} - -#endif - diff --git a/softfloat/source/s_mulAddF128.c b/softfloat/source/s_mulAddF128.c deleted file mode 100644 index f6b2b45..0000000 --- a/softfloat/source/s_mulAddF128.c +++ /dev/null @@ -1,350 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t - softfloat_mulAddF128( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0, - uint_fast64_t uiC64, - uint_fast64_t uiC0, - uint_fast8_t op - ) -{ - bool signA; - int_fast32_t expA; - struct uint128 sigA; - bool signB; - int_fast32_t expB; - struct uint128 sigB; - bool signC; - int_fast32_t expC; - struct uint128 sigC; - bool signZ; - uint_fast64_t magBits; - struct uint128 uiZ; - struct exp32_sig128 normExpSig; - int_fast32_t expZ; - uint64_t sig256Z[4]; - struct uint128 sigZ; - int_fast32_t shiftDist, expDiff; - struct uint128 x128; - uint64_t sig256C[4]; - static uint64_t zero256[4] = INIT_UINTM4( 0, 0, 0, 0 ); - uint_fast64_t sigZExtra, sig256Z0; - union ui128_f128 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signA = signF128UI64( uiA64 ); - expA = expF128UI64( uiA64 ); - sigA.v64 = fracF128UI64( uiA64 ); - sigA.v0 = uiA0; - signB = signF128UI64( uiB64 ); - expB = expF128UI64( uiB64 ); - sigB.v64 = fracF128UI64( uiB64 ); - sigB.v0 = uiB0; - signC = signF128UI64( uiC64 ) ^ (op == softfloat_mulAdd_subC); - expC = expF128UI64( uiC64 ); - sigC.v64 = fracF128UI64( uiC64 ); - sigC.v0 = uiC0; - signZ = signA ^ signB ^ (op == softfloat_mulAdd_subProd); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FFF ) { - if ( - (sigA.v64 | sigA.v0) || ((expB == 0x7FFF) && (sigB.v64 | sigB.v0)) - ) { - goto propagateNaN_ABC; - } - magBits = expB | sigB.v64 | sigB.v0; - goto infProdArg; - } - if ( expB == 0x7FFF ) { - if ( sigB.v64 | sigB.v0 ) goto propagateNaN_ABC; - magBits = expA | sigA.v64 | sigA.v0; - goto infProdArg; - } - if ( expC == 0x7FFF ) { - if ( sigC.v64 | sigC.v0 ) { - uiZ.v64 = 0; - uiZ.v0 = 0; - goto propagateNaN_ZC; - } - uiZ.v64 = uiC64; - uiZ.v0 = uiC0; - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! (sigA.v64 | sigA.v0) ) goto zeroProd; - normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - if ( ! expB ) { - if ( ! (sigB.v64 | sigB.v0) ) goto zeroProd; - normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA + expB - 0x3FFE; - sigA.v64 |= UINT64_C( 0x0001000000000000 ); - sigB.v64 |= UINT64_C( 0x0001000000000000 ); - sigA = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 8 ); - sigB = softfloat_shortShiftLeft128( sigB.v64, sigB.v0, 15 ); - softfloat_mul128To256M( sigA.v64, sigA.v0, sigB.v64, sigB.v0, sig256Z ); - sigZ.v64 = sig256Z[indexWord( 4, 3 )]; - sigZ.v0 = sig256Z[indexWord( 4, 2 )]; - shiftDist = 0; - if ( ! (sigZ.v64 & UINT64_C( 0x0100000000000000 )) ) { - --expZ; - shiftDist = -1; - } - if ( ! expC ) { - if ( ! (sigC.v64 | sigC.v0) ) { - shiftDist += 8; - goto sigZ; - } - normExpSig = softfloat_normSubnormalF128Sig( sigC.v64, sigC.v0 ); - expC = normExpSig.exp; - sigC = normExpSig.sig; - } - sigC.v64 |= UINT64_C( 0x0001000000000000 ); - sigC = softfloat_shortShiftLeft128( sigC.v64, sigC.v0, 8 ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expZ - expC; - if ( expDiff < 0 ) { - expZ = expC; - if ( (signZ == signC) || (expDiff < -1) ) { - shiftDist -= expDiff; - if ( shiftDist ) { - sigZ = - softfloat_shiftRightJam128( sigZ.v64, sigZ.v0, shiftDist ); - } - } else { - if ( ! shiftDist ) { - x128 = - softfloat_shortShiftRight128( - sig256Z[indexWord( 4, 1 )], sig256Z[indexWord( 4, 0 )], - 1 - ); - sig256Z[indexWord( 4, 1 )] = (sigZ.v0<<63) | x128.v64; - sig256Z[indexWord( 4, 0 )] = x128.v0; - sigZ = softfloat_shortShiftRight128( sigZ.v64, sigZ.v0, 1 ); - sig256Z[indexWord( 4, 3 )] = sigZ.v64; - sig256Z[indexWord( 4, 2 )] = sigZ.v0; - } - } - } else { - if ( shiftDist ) softfloat_add256M( sig256Z, sig256Z, sig256Z ); - if ( ! expDiff ) { - sigZ.v64 = sig256Z[indexWord( 4, 3 )]; - sigZ.v0 = sig256Z[indexWord( 4, 2 )]; - } else { - sig256C[indexWord( 4, 3 )] = sigC.v64; - sig256C[indexWord( 4, 2 )] = sigC.v0; - sig256C[indexWord( 4, 1 )] = 0; - sig256C[indexWord( 4, 0 )] = 0; - softfloat_shiftRightJam256M( sig256C, expDiff, sig256C ); - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - shiftDist = 8; - if ( signZ == signC ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expDiff <= 0 ) { - sigZ = softfloat_add128( sigC.v64, sigC.v0, sigZ.v64, sigZ.v0 ); - } else { - softfloat_add256M( sig256Z, sig256C, sig256Z ); - sigZ.v64 = sig256Z[indexWord( 4, 3 )]; - sigZ.v0 = sig256Z[indexWord( 4, 2 )]; - } - if ( sigZ.v64 & UINT64_C( 0x0200000000000000 ) ) { - ++expZ; - shiftDist = 9; - } - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expDiff < 0 ) { - signZ = signC; - if ( expDiff < -1 ) { - sigZ = - softfloat_sub128( sigC.v64, sigC.v0, sigZ.v64, sigZ.v0 ); - sigZExtra = - sig256Z[indexWord( 4, 1 )] | sig256Z[indexWord( 4, 0 )]; - if ( sigZExtra ) { - sigZ = softfloat_sub128( sigZ.v64, sigZ.v0, 0, 1 ); - } - if ( ! (sigZ.v64 & UINT64_C( 0x0100000000000000 )) ) { - --expZ; - shiftDist = 7; - } - goto shiftRightRoundPack; - } else { - sig256C[indexWord( 4, 3 )] = sigC.v64; - sig256C[indexWord( 4, 2 )] = sigC.v0; - sig256C[indexWord( 4, 1 )] = 0; - sig256C[indexWord( 4, 0 )] = 0; - softfloat_sub256M( sig256C, sig256Z, sig256Z ); - } - } else if ( ! expDiff ) { - sigZ = softfloat_sub128( sigZ.v64, sigZ.v0, sigC.v64, sigC.v0 ); - if ( - ! (sigZ.v64 | sigZ.v0) && ! sig256Z[indexWord( 4, 1 )] - && ! sig256Z[indexWord( 4, 0 )] - ) { - goto completeCancellation; - } - sig256Z[indexWord( 4, 3 )] = sigZ.v64; - sig256Z[indexWord( 4, 2 )] = sigZ.v0; - if ( sigZ.v64 & UINT64_C( 0x8000000000000000 ) ) { - signZ = ! signZ; - softfloat_sub256M( zero256, sig256Z, sig256Z ); - } - } else { - softfloat_sub256M( sig256Z, sig256C, sig256Z ); - if ( 1 < expDiff ) { - sigZ.v64 = sig256Z[indexWord( 4, 3 )]; - sigZ.v0 = sig256Z[indexWord( 4, 2 )]; - if ( ! (sigZ.v64 & UINT64_C( 0x0100000000000000 )) ) { - --expZ; - shiftDist = 7; - } - goto sigZ; - } - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sigZ.v64 = sig256Z[indexWord( 4, 3 )]; - sigZ.v0 = sig256Z[indexWord( 4, 2 )]; - sigZExtra = sig256Z[indexWord( 4, 1 )]; - sig256Z0 = sig256Z[indexWord( 4, 0 )]; - if ( sigZ.v64 ) { - if ( sig256Z0 ) sigZExtra |= 1; - } else { - expZ -= 64; - sigZ.v64 = sigZ.v0; - sigZ.v0 = sigZExtra; - sigZExtra = sig256Z0; - if ( ! sigZ.v64 ) { - expZ -= 64; - sigZ.v64 = sigZ.v0; - sigZ.v0 = sigZExtra; - sigZExtra = 0; - if ( ! sigZ.v64 ) { - expZ -= 64; - sigZ.v64 = sigZ.v0; - sigZ.v0 = 0; - } - } - } - shiftDist = softfloat_countLeadingZeros64( sigZ.v64 ); - expZ += 7 - shiftDist; - shiftDist = 15 - shiftDist; - if ( 0 < shiftDist ) goto shiftRightRoundPack; - if ( shiftDist ) { - shiftDist = -shiftDist; - sigZ = softfloat_shortShiftLeft128( sigZ.v64, sigZ.v0, shiftDist ); - x128 = softfloat_shortShiftLeft128( 0, sigZExtra, shiftDist ); - sigZ.v0 |= x128.v64; - sigZExtra = x128.v0; - } - goto roundPack; - } - sigZ: - sigZExtra = sig256Z[indexWord( 4, 1 )] | sig256Z[indexWord( 4, 0 )]; - shiftRightRoundPack: - sigZExtra = (uint64_t) (sigZ.v0<<(64 - shiftDist)) | (sigZExtra != 0); - sigZ = softfloat_shortShiftRight128( sigZ.v64, sigZ.v0, shiftDist ); - roundPack: - return - softfloat_roundPackToF128( - signZ, expZ - 1, sigZ.v64, sigZ.v0, sigZExtra ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN_ABC: - uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); - goto propagateNaN_ZC; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infProdArg: - if ( magBits ) { - uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 ); - uiZ.v0 = 0; - if ( expC != 0x7FFF ) goto uiZ; - if ( sigC.v64 | sigC.v0 ) goto propagateNaN_ZC; - if ( signZ == signC ) goto uiZ; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - propagateNaN_ZC: - uiZ = softfloat_propagateNaNF128UI( uiZ.v64, uiZ.v0, uiC64, uiC0 ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zeroProd: - uiZ.v64 = uiC64; - uiZ.v0 = uiC0; - if ( ! (expC | sigC.v64 | sigC.v0) && (signZ != signC) ) { - completeCancellation: - uiZ.v64 = - packToF128UI64( - (softfloat_roundingMode == softfloat_round_min), 0, 0 ); - uiZ.v0 = 0; - } - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_mulAddF128M.c b/softfloat/source/s_mulAddF128M.c deleted file mode 100644 index f51fc71..0000000 --- a/softfloat/source/s_mulAddF128M.c +++ /dev/null @@ -1,382 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -void - softfloat_mulAddF128M( - const uint32_t *aWPtr, - const uint32_t *bWPtr, - const uint32_t *cWPtr, - uint32_t *zWPtr, - uint_fast8_t op - ) -{ - uint32_t uiA96; - int32_t expA; - uint32_t uiB96; - int32_t expB; - uint32_t uiC96; - bool signC; - int32_t expC; - bool signProd, prodIsInfinite; - uint32_t *ptr, uiZ96, sigA[4]; - uint_fast8_t shiftDist; - uint32_t sigX[5]; - int32_t expProd; - uint32_t sigProd[8], wordSig; - bool doSub; - uint_fast8_t - (*addCarryMRoutinePtr)( - uint_fast8_t, - const uint32_t *, - const uint32_t *, - uint_fast8_t, - uint32_t * - ); - int32_t expDiff; - bool signZ; - int32_t expZ; - uint32_t *extSigPtr; - uint_fast8_t carry; - void (*roundPackRoutinePtr)( bool, int32_t, uint32_t *, uint32_t * ); - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uiA96 = aWPtr[indexWordHi( 4 )]; - expA = expF128UI96( uiA96 ); - uiB96 = bWPtr[indexWordHi( 4 )]; - expB = expF128UI96( uiB96 ); - uiC96 = cWPtr[indexWordHi( 4 )]; - signC = signF128UI96( uiC96 ) ^ (op == softfloat_mulAdd_subC); - expC = expF128UI96( uiC96 ); - signProd = - signF128UI96( uiA96 ) ^ signF128UI96( uiB96 ) - ^ (op == softfloat_mulAdd_subProd); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - prodIsInfinite = false; - if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) { - if ( softfloat_tryPropagateNaNF128M( aWPtr, bWPtr, zWPtr ) ) { - goto propagateNaN_ZC; - } - ptr = (uint32_t *) aWPtr; - if ( ! (uint32_t) (uiA96<<1) ) goto possibleInvalidProd; - if ( ! (uint32_t) (uiB96<<1) ) { - ptr = (uint32_t *) bWPtr; - possibleInvalidProd: - if ( - ! (ptr[indexWord( 4, 2 )] | ptr[indexWord( 4, 1 )] - | ptr[indexWord( 4, 0 )]) - ) { - goto invalid; - } - } - prodIsInfinite = true; - } - if ( expC == 0x7FFF ) { - if ( - fracF128UI96( uiC96 ) - || (cWPtr[indexWord( 4, 2 )] | cWPtr[indexWord( 4, 1 )] - | cWPtr[indexWord( 4, 0 )]) - ) { - zWPtr[indexWordHi( 4 )] = 0; - goto propagateNaN_ZC; - } - if ( prodIsInfinite && (signProd != signC) ) goto invalid; - goto copyC; - } - if ( prodIsInfinite ) { - uiZ96 = packToF128UI96( signProd, 0x7FFF, 0 ); - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA ) { - sigA[indexWordHi( 4 )] = fracF128UI96( uiA96 ) | 0x00010000; - sigA[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )]; - sigA[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )]; - sigA[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )]; - } else { - expA = softfloat_shiftNormSigF128M( aWPtr, 0, sigA ); - if ( expA == -128 ) goto zeroProd; - } - if ( expB ) { - sigX[indexWordHi( 4 )] = fracF128UI96( uiB96 ) | 0x00010000; - sigX[indexWord( 4, 2 )] = bWPtr[indexWord( 4, 2 )]; - sigX[indexWord( 4, 1 )] = bWPtr[indexWord( 4, 1 )]; - sigX[indexWord( 4, 0 )] = bWPtr[indexWord( 4, 0 )]; - } else { - expB = softfloat_shiftNormSigF128M( bWPtr, 0, sigX ); - if ( expB == -128 ) goto zeroProd; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expProd = expA + expB - 0x3FF0; - softfloat_mul128MTo256M( sigA, sigX, sigProd ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - wordSig = fracF128UI96( uiC96 ); - if ( expC ) { - --expC; - wordSig |= 0x00010000; - } - sigX[indexWordHi( 5 )] = wordSig; - sigX[indexWord( 5, 3 )] = cWPtr[indexWord( 4, 2 )]; - sigX[indexWord( 5, 2 )] = cWPtr[indexWord( 4, 1 )]; - sigX[indexWord( 5, 1 )] = cWPtr[indexWord( 4, 0 )]; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - doSub = (signProd != signC); - addCarryMRoutinePtr = - doSub ? softfloat_addComplCarryM : softfloat_addCarryM; - expDiff = expProd - expC; - if ( expDiff <= 0 ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - signZ = signC; - expZ = expC; - if ( - sigProd[indexWord( 8, 2 )] - || (sigProd[indexWord( 8, 1 )] | sigProd[indexWord( 8, 0 )]) - ) { - sigProd[indexWord( 8, 3 )] |= 1; - } - extSigPtr = &sigProd[indexMultiwordHi( 8, 5 )]; - if ( expDiff ) { - softfloat_shiftRightJam160M( extSigPtr, -expDiff, extSigPtr ); - } - carry = 0; - if ( doSub ) { - wordSig = extSigPtr[indexWordLo( 5 )]; - extSigPtr[indexWordLo( 5 )] = -wordSig; - carry = ! wordSig; - } - (*addCarryMRoutinePtr)( - 4, - &sigX[indexMultiwordHi( 5, 4 )], - extSigPtr + indexMultiwordHi( 5, 4 ), - carry, - extSigPtr + indexMultiwordHi( 5, 4 ) - ); - wordSig = extSigPtr[indexWordHi( 5 )]; - if ( ! expZ ) { - if ( wordSig & 0x80000000 ) { - signZ = ! signZ; - softfloat_negX160M( extSigPtr ); - wordSig = extSigPtr[indexWordHi( 5 )]; - } - goto checkCancellation; - } - if ( wordSig < 0x00010000 ) { - --expZ; - softfloat_add160M( extSigPtr, extSigPtr, extSigPtr ); - goto roundPack; - } - goto extSigReady_noCancellation; - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - signZ = signProd; - expZ = expProd; - sigX[indexWordLo( 5 )] = 0; - expDiff -= 128; - if ( 0 <= expDiff ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - if ( expDiff ) softfloat_shiftRightJam160M( sigX, expDiff, sigX ); - wordSig = sigX[indexWordLo( 5 )]; - carry = 0; - if ( doSub ) { - carry = ! wordSig; - wordSig = -wordSig; - } - carry = - (*addCarryMRoutinePtr)( - 4, - &sigProd[indexMultiwordLo( 8, 4 )], - &sigX[indexMultiwordHi( 5, 4 )], - carry, - &sigProd[indexMultiwordLo( 8, 4 )] - ); - sigProd[indexWord( 8, 2 )] |= wordSig; - ptr = &sigProd[indexWord( 8, 4 )]; - } else { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - shiftDist = expDiff & 31; - if ( shiftDist ) { - softfloat_shortShiftRight160M( sigX, shiftDist, sigX ); - } - expDiff >>= 5; - extSigPtr = - &sigProd[indexMultiwordLo( 8, 5 )] - wordIncr - + expDiff * -wordIncr; - carry = - (*addCarryMRoutinePtr)( 5, extSigPtr, sigX, doSub, extSigPtr ); - if ( expDiff == -4 ) { - /*------------------------------------------------------------ - *------------------------------------------------------------*/ - wordSig = sigProd[indexWordHi( 8 )]; - if ( wordSig & 0x80000000 ) { - signZ = ! signZ; - softfloat_negX256M( sigProd ); - wordSig = sigProd[indexWordHi( 8 )]; - } - /*------------------------------------------------------------ - *------------------------------------------------------------*/ - if ( wordSig ) goto expProdBigger_noWordShift; - wordSig = sigProd[indexWord( 8, 6 )]; - if ( 0x00040000 <= wordSig ) goto expProdBigger_noWordShift; - expZ -= 32; - extSigPtr = &sigProd[indexMultiwordHi( 8, 5 )] - wordIncr; - for (;;) { - if ( wordSig ) break; - wordSig = extSigPtr[indexWord( 5, 3 )]; - if ( 0x00040000 <= wordSig ) break; - expZ -= 32; - extSigPtr -= wordIncr; - if ( extSigPtr == &sigProd[indexMultiwordLo( 8, 5 )] ) { - goto checkCancellation; - } - } - /*------------------------------------------------------------ - *------------------------------------------------------------*/ - ptr = extSigPtr + indexWordLo( 5 ); - do { - ptr -= wordIncr; - if ( *ptr ) { - extSigPtr[indexWordLo( 5 )] |= 1; - break; - } - } while ( ptr != &sigProd[indexWordLo( 8 )] ); - wordSig = extSigPtr[indexWordHi( 5 )]; - goto extSigReady; - } - ptr = extSigPtr + indexWordHi( 5 ) + wordIncr; - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( carry != doSub ) { - if ( doSub ) { - do { - wordSig = *ptr; - *ptr = wordSig - 1; - ptr += wordIncr; - } while ( ! wordSig ); - } else { - do { - wordSig = *ptr + 1; - *ptr = wordSig; - ptr += wordIncr; - } while ( ! wordSig ); - } - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - expProdBigger_noWordShift: - if ( - sigProd[indexWord( 8, 2 )] - || (sigProd[indexWord( 8, 1 )] | sigProd[indexWord( 8, 0 )]) - ) { - sigProd[indexWord( 8, 3 )] |= 1; - } - extSigPtr = &sigProd[indexMultiwordHi( 8, 5 )]; - wordSig = extSigPtr[indexWordHi( 5 )]; - } - extSigReady: - roundPackRoutinePtr = softfloat_normRoundPackMToF128M; - if ( wordSig < 0x00010000 ) goto doRoundPack; - extSigReady_noCancellation: - if ( 0x00020000 <= wordSig ) { - ++expZ; - softfloat_shortShiftRightJam160M( extSigPtr, 1, extSigPtr ); - } - roundPack: - roundPackRoutinePtr = softfloat_roundPackMToF128M; - doRoundPack: - (*roundPackRoutinePtr)( signZ, expZ, extSigPtr, zWPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_invalidF128M( zWPtr ); - propagateNaN_ZC: - softfloat_propagateNaNF128M( zWPtr, cWPtr, zWPtr ); - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zeroProd: - if ( - ! (uint32_t) (uiC96<<1) && (signProd != signC) - && ! cWPtr[indexWord( 4, 2 )] - && ! (cWPtr[indexWord( 4, 1 )] | cWPtr[indexWord( 4, 0 )]) - ) { - goto completeCancellation; - } - copyC: - zWPtr[indexWordHi( 4 )] = uiC96; - zWPtr[indexWord( 4, 2 )] = cWPtr[indexWord( 4, 2 )]; - zWPtr[indexWord( 4, 1 )] = cWPtr[indexWord( 4, 1 )]; - zWPtr[indexWord( 4, 0 )] = cWPtr[indexWord( 4, 0 )]; - return; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - checkCancellation: - if ( - wordSig - || (extSigPtr[indexWord( 5, 3 )] | extSigPtr[indexWord( 5, 2 )]) - || (extSigPtr[indexWord( 5, 1 )] | extSigPtr[indexWord( 5, 0 )]) - ) { - goto extSigReady; - } - completeCancellation: - uiZ96 = - packToF128UI96( - (softfloat_roundingMode == softfloat_round_min), 0, 0 ); - uiZ: - zWPtr[indexWordHi( 4 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = 0; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - -} - diff --git a/softfloat/source/s_mulAddF16.c b/softfloat/source/s_mulAddF16.c deleted file mode 100644 index 3a684ac..0000000 --- a/softfloat/source/s_mulAddF16.c +++ /dev/null @@ -1,226 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float16_t - softfloat_mulAddF16( - uint_fast16_t uiA, uint_fast16_t uiB, uint_fast16_t uiC, uint_fast8_t op ) -{ - bool signA; - int_fast8_t expA; - uint_fast16_t sigA; - bool signB; - int_fast8_t expB; - uint_fast16_t sigB; - bool signC; - int_fast8_t expC; - uint_fast16_t sigC; - bool signProd; - uint_fast16_t magBits, uiZ; - struct exp8_sig16 normExpSig; - int_fast8_t expProd; - uint_fast32_t sigProd; - bool signZ; - int_fast8_t expZ; - uint_fast16_t sigZ; - int_fast8_t expDiff; - uint_fast32_t sig32Z, sig32C; - int_fast8_t shiftDist; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signA = signF16UI( uiA ); - expA = expF16UI( uiA ); - sigA = fracF16UI( uiA ); - signB = signF16UI( uiB ); - expB = expF16UI( uiB ); - sigB = fracF16UI( uiB ); - signC = signF16UI( uiC ) ^ (op == softfloat_mulAdd_subC); - expC = expF16UI( uiC ); - sigC = fracF16UI( uiC ); - signProd = signA ^ signB ^ (op == softfloat_mulAdd_subProd); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x1F ) { - if ( sigA || ((expB == 0x1F) && sigB) ) goto propagateNaN_ABC; - magBits = expB | sigB; - goto infProdArg; - } - if ( expB == 0x1F ) { - if ( sigB ) goto propagateNaN_ABC; - magBits = expA | sigA; - goto infProdArg; - } - if ( expC == 0x1F ) { - if ( sigC ) { - uiZ = 0; - goto propagateNaN_ZC; - } - uiZ = uiC; - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! sigA ) goto zeroProd; - normExpSig = softfloat_normSubnormalF16Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - if ( ! expB ) { - if ( ! sigB ) goto zeroProd; - normExpSig = softfloat_normSubnormalF16Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expProd = expA + expB - 0xE; - sigA = (sigA | 0x0400)<<4; - sigB = (sigB | 0x0400)<<4; - sigProd = (uint_fast32_t) sigA * sigB; - if ( sigProd < 0x20000000 ) { - --expProd; - sigProd <<= 1; - } - signZ = signProd; - if ( ! expC ) { - if ( ! sigC ) { - expZ = expProd - 1; - sigZ = sigProd>>15 | ((sigProd & 0x7FFF) != 0); - goto roundPack; - } - normExpSig = softfloat_normSubnormalF16Sig( sigC ); - expC = normExpSig.exp; - sigC = normExpSig.sig; - } - sigC = (sigC | 0x0400)<<3; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expProd - expC; - if ( signProd == signC ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expDiff <= 0 ) { - expZ = expC; - sigZ = sigC + softfloat_shiftRightJam32( sigProd, 16 - expDiff ); - } else { - expZ = expProd; - sig32Z = - sigProd - + softfloat_shiftRightJam32( - (uint_fast32_t) sigC<<16, expDiff ); - sigZ = sig32Z>>16 | ((sig32Z & 0xFFFF) != 0 ); - } - if ( sigZ < 0x4000 ) { - --expZ; - sigZ <<= 1; - } - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sig32C = (uint_fast32_t) sigC<<16; - if ( expDiff < 0 ) { - signZ = signC; - expZ = expC; - sig32Z = sig32C - softfloat_shiftRightJam32( sigProd, -expDiff ); - } else if ( ! expDiff ) { - expZ = expProd; - sig32Z = sigProd - sig32C; - if ( ! sig32Z ) goto completeCancellation; - if ( sig32Z & 0x80000000 ) { - signZ = ! signZ; - sig32Z = -sig32Z; - } - } else { - expZ = expProd; - sig32Z = sigProd - softfloat_shiftRightJam32( sig32C, expDiff ); - } - shiftDist = softfloat_countLeadingZeros32( sig32Z ) - 1; - expZ -= shiftDist; - shiftDist -= 16; - if ( shiftDist < 0 ) { - sigZ = - sig32Z>>(-shiftDist) - | ((uint32_t) (sig32Z<<(shiftDist & 31)) != 0); - } else { - sigZ = (uint_fast16_t) sig32Z< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t - softfloat_mulAddF32( - uint_fast32_t uiA, uint_fast32_t uiB, uint_fast32_t uiC, uint_fast8_t op ) -{ - bool signA; - int_fast16_t expA; - uint_fast32_t sigA; - bool signB; - int_fast16_t expB; - uint_fast32_t sigB; - bool signC; - int_fast16_t expC; - uint_fast32_t sigC; - bool signProd; - uint_fast32_t magBits, uiZ; - struct exp16_sig32 normExpSig; - int_fast16_t expProd; - uint_fast64_t sigProd; - bool signZ; - int_fast16_t expZ; - uint_fast32_t sigZ; - int_fast16_t expDiff; - uint_fast64_t sig64Z, sig64C; - int_fast8_t shiftDist; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signA = signF32UI( uiA ); - expA = expF32UI( uiA ); - sigA = fracF32UI( uiA ); - signB = signF32UI( uiB ); - expB = expF32UI( uiB ); - sigB = fracF32UI( uiB ); - signC = signF32UI( uiC ) ^ (op == softfloat_mulAdd_subC); - expC = expF32UI( uiC ); - sigC = fracF32UI( uiC ); - signProd = signA ^ signB ^ (op == softfloat_mulAdd_subProd); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0xFF ) { - if ( sigA || ((expB == 0xFF) && sigB) ) goto propagateNaN_ABC; - magBits = expB | sigB; - goto infProdArg; - } - if ( expB == 0xFF ) { - if ( sigB ) goto propagateNaN_ABC; - magBits = expA | sigA; - goto infProdArg; - } - if ( expC == 0xFF ) { - if ( sigC ) { - uiZ = 0; - goto propagateNaN_ZC; - } - uiZ = uiC; - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! sigA ) goto zeroProd; - normExpSig = softfloat_normSubnormalF32Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - if ( ! expB ) { - if ( ! sigB ) goto zeroProd; - normExpSig = softfloat_normSubnormalF32Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expProd = expA + expB - 0x7E; - sigA = (sigA | 0x00800000)<<7; - sigB = (sigB | 0x00800000)<<7; - sigProd = (uint_fast64_t) sigA * sigB; - if ( sigProd < UINT64_C( 0x2000000000000000 ) ) { - --expProd; - sigProd <<= 1; - } - signZ = signProd; - if ( ! expC ) { - if ( ! sigC ) { - expZ = expProd - 1; - sigZ = softfloat_shortShiftRightJam64( sigProd, 31 ); - goto roundPack; - } - normExpSig = softfloat_normSubnormalF32Sig( sigC ); - expC = normExpSig.exp; - sigC = normExpSig.sig; - } - sigC = (sigC | 0x00800000)<<6; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expProd - expC; - if ( signProd == signC ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expDiff <= 0 ) { - expZ = expC; - sigZ = sigC + softfloat_shiftRightJam64( sigProd, 32 - expDiff ); - } else { - expZ = expProd; - sig64Z = - sigProd - + softfloat_shiftRightJam64( - (uint_fast64_t) sigC<<32, expDiff ); - sigZ = softfloat_shortShiftRightJam64( sig64Z, 32 ); - } - if ( sigZ < 0x40000000 ) { - --expZ; - sigZ <<= 1; - } - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - sig64C = (uint_fast64_t) sigC<<32; - if ( expDiff < 0 ) { - signZ = signC; - expZ = expC; - sig64Z = sig64C - softfloat_shiftRightJam64( sigProd, -expDiff ); - } else if ( ! expDiff ) { - expZ = expProd; - sig64Z = sigProd - sig64C; - if ( ! sig64Z ) goto completeCancellation; - if ( sig64Z & UINT64_C( 0x8000000000000000 ) ) { - signZ = ! signZ; - sig64Z = -sig64Z; - } - } else { - expZ = expProd; - sig64Z = sigProd - softfloat_shiftRightJam64( sig64C, expDiff ); - } - shiftDist = softfloat_countLeadingZeros64( sig64Z ) - 1; - expZ -= shiftDist; - shiftDist -= 32; - if ( shiftDist < 0 ) { - sigZ = softfloat_shortShiftRightJam64( sig64Z, -shiftDist ); - } else { - sigZ = (uint_fast32_t) sig64Z< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -float64_t - softfloat_mulAddF64( - uint_fast64_t uiA, uint_fast64_t uiB, uint_fast64_t uiC, uint_fast8_t op ) -{ - bool signA; - int_fast16_t expA; - uint_fast64_t sigA; - bool signB; - int_fast16_t expB; - uint_fast64_t sigB; - bool signC; - int_fast16_t expC; - uint_fast64_t sigC; - bool signZ; - uint_fast64_t magBits, uiZ; - struct exp16_sig64 normExpSig; - int_fast16_t expZ; - struct uint128 sig128Z; - uint_fast64_t sigZ; - int_fast16_t expDiff; - struct uint128 sig128C; - int_fast8_t shiftDist; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signA = signF64UI( uiA ); - expA = expF64UI( uiA ); - sigA = fracF64UI( uiA ); - signB = signF64UI( uiB ); - expB = expF64UI( uiB ); - sigB = fracF64UI( uiB ); - signC = signF64UI( uiC ) ^ (op == softfloat_mulAdd_subC); - expC = expF64UI( uiC ); - sigC = fracF64UI( uiC ); - signZ = signA ^ signB ^ (op == softfloat_mulAdd_subProd); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FF ) { - if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN_ABC; - magBits = expB | sigB; - goto infProdArg; - } - if ( expB == 0x7FF ) { - if ( sigB ) goto propagateNaN_ABC; - magBits = expA | sigA; - goto infProdArg; - } - if ( expC == 0x7FF ) { - if ( sigC ) { - uiZ = 0; - goto propagateNaN_ZC; - } - uiZ = uiC; - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! sigA ) goto zeroProd; - normExpSig = softfloat_normSubnormalF64Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - if ( ! expB ) { - if ( ! sigB ) goto zeroProd; - normExpSig = softfloat_normSubnormalF64Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA + expB - 0x3FE; - sigA = (sigA | UINT64_C( 0x0010000000000000 ))<<10; - sigB = (sigB | UINT64_C( 0x0010000000000000 ))<<10; - sig128Z = softfloat_mul64To128( sigA, sigB ); - if ( sig128Z.v64 < UINT64_C( 0x2000000000000000 ) ) { - --expZ; - sig128Z = - softfloat_add128( - sig128Z.v64, sig128Z.v0, sig128Z.v64, sig128Z.v0 ); - } - if ( ! expC ) { - if ( ! sigC ) { - --expZ; - sigZ = sig128Z.v64<<1 | (sig128Z.v0 != 0); - goto roundPack; - } - normExpSig = softfloat_normSubnormalF64Sig( sigC ); - expC = normExpSig.exp; - sigC = normExpSig.sig; - } - sigC = (sigC | UINT64_C( 0x0010000000000000 ))<<9; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expZ - expC; - if ( expDiff < 0 ) { - expZ = expC; - if ( (signZ == signC) || (expDiff < -1) ) { - sig128Z.v64 = softfloat_shiftRightJam64( sig128Z.v64, -expDiff ); - } else { - sig128Z = - softfloat_shortShiftRightJam128( sig128Z.v64, sig128Z.v0, 1 ); - } - } else if ( expDiff ) { - sig128C = softfloat_shiftRightJam128( sigC, 0, expDiff ); - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( signZ == signC ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expDiff <= 0 ) { - sigZ = (sigC + sig128Z.v64) | (sig128Z.v0 != 0); - } else { - sig128Z = - softfloat_add128( - sig128Z.v64, sig128Z.v0, sig128C.v64, sig128C.v0 ); - sigZ = sig128Z.v64 | (sig128Z.v0 != 0); - } - if ( sigZ < UINT64_C( 0x4000000000000000 ) ) { - --expZ; - sigZ <<= 1; - } - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expDiff < 0 ) { - signZ = signC; - sig128Z = softfloat_sub128( sigC, 0, sig128Z.v64, sig128Z.v0 ); - } else if ( ! expDiff ) { - sig128Z.v64 = sig128Z.v64 - sigC; - if ( ! (sig128Z.v64 | sig128Z.v0) ) goto completeCancellation; - if ( sig128Z.v64 & UINT64_C( 0x8000000000000000 ) ) { - signZ = ! signZ; - sig128Z = softfloat_sub128( 0, 0, sig128Z.v64, sig128Z.v0 ); - } - } else { - sig128Z = - softfloat_sub128( - sig128Z.v64, sig128Z.v0, sig128C.v64, sig128C.v0 ); - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( ! sig128Z.v64 ) { - expZ -= 64; - sig128Z.v64 = sig128Z.v0; - sig128Z.v0 = 0; - } - shiftDist = softfloat_countLeadingZeros64( sig128Z.v64 ) - 1; - expZ -= shiftDist; - if ( shiftDist < 0 ) { - sigZ = softfloat_shortShiftRightJam64( sig128Z.v64, -shiftDist ); - } else { - sig128Z = - softfloat_shortShiftLeft128( - sig128Z.v64, sig128Z.v0, shiftDist ); - sigZ = sig128Z.v64; - } - sigZ |= (sig128Z.v0 != 0); - } - roundPack: - return softfloat_roundPackToF64( signZ, expZ, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN_ABC: - uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); - goto propagateNaN_ZC; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infProdArg: - if ( magBits ) { - uiZ = packToF64UI( signZ, 0x7FF, 0 ); - if ( expC != 0x7FF ) goto uiZ; - if ( sigC ) goto propagateNaN_ZC; - if ( signZ == signC ) goto uiZ; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF64UI; - propagateNaN_ZC: - uiZ = softfloat_propagateNaNF64UI( uiZ, uiC ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zeroProd: - uiZ = uiC; - if ( ! (expC | sigC) && (signZ != signC) ) { - completeCancellation: - uiZ = - packToF64UI( - (softfloat_roundingMode == softfloat_round_min), 0, 0 ); - } - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - -#else - -float64_t - softfloat_mulAddF64( - uint_fast64_t uiA, uint_fast64_t uiB, uint_fast64_t uiC, uint_fast8_t op ) -{ - bool signA; - int_fast16_t expA; - uint64_t sigA; - bool signB; - int_fast16_t expB; - uint64_t sigB; - bool signC; - int_fast16_t expC; - uint64_t sigC; - bool signZ; - uint64_t magBits, uiZ; - struct exp16_sig64 normExpSig; - int_fast16_t expZ; - uint32_t sig128Z[4]; - uint64_t sigZ; - int_fast16_t shiftDist, expDiff; - uint32_t sig128C[4]; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - signA = signF64UI( uiA ); - expA = expF64UI( uiA ); - sigA = fracF64UI( uiA ); - signB = signF64UI( uiB ); - expB = expF64UI( uiB ); - sigB = fracF64UI( uiB ); - signC = signF64UI( uiC ) ^ (op == softfloat_mulAdd_subC); - expC = expF64UI( uiC ); - sigC = fracF64UI( uiC ); - signZ = signA ^ signB ^ (op == softfloat_mulAdd_subProd); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( expA == 0x7FF ) { - if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN_ABC; - magBits = expB | sigB; - goto infProdArg; - } - if ( expB == 0x7FF ) { - if ( sigB ) goto propagateNaN_ABC; - magBits = expA | sigA; - goto infProdArg; - } - if ( expC == 0x7FF ) { - if ( sigC ) { - uiZ = 0; - goto propagateNaN_ZC; - } - uiZ = uiC; - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( ! expA ) { - if ( ! sigA ) goto zeroProd; - normExpSig = softfloat_normSubnormalF64Sig( sigA ); - expA = normExpSig.exp; - sigA = normExpSig.sig; - } - if ( ! expB ) { - if ( ! sigB ) goto zeroProd; - normExpSig = softfloat_normSubnormalF64Sig( sigB ); - expB = normExpSig.exp; - sigB = normExpSig.sig; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA + expB - 0x3FE; - sigA = (sigA | UINT64_C( 0x0010000000000000 ))<<10; - sigB = (sigB | UINT64_C( 0x0010000000000000 ))<<11; - softfloat_mul64To128M( sigA, sigB, sig128Z ); - sigZ = - (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 | sig128Z[indexWord( 4, 2 )]; - shiftDist = 0; - if ( ! (sigZ & UINT64_C( 0x4000000000000000 )) ) { - --expZ; - shiftDist = -1; - } - if ( ! expC ) { - if ( ! sigC ) { - if ( shiftDist ) sigZ <<= 1; - goto sigZ; - } - normExpSig = softfloat_normSubnormalF64Sig( sigC ); - expC = normExpSig.exp; - sigC = normExpSig.sig; - } - sigC = (sigC | UINT64_C( 0x0010000000000000 ))<<10; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expZ - expC; - if ( expDiff < 0 ) { - expZ = expC; - if ( (signZ == signC) || (expDiff < -1) ) { - shiftDist -= expDiff; - if ( shiftDist) { - sigZ = softfloat_shiftRightJam64( sigZ, shiftDist ); - } - } else { - if ( ! shiftDist ) { - softfloat_shortShiftRight128M( sig128Z, 1, sig128Z ); - } - } - } else { - if ( shiftDist ) softfloat_add128M( sig128Z, sig128Z, sig128Z ); - if ( ! expDiff ) { - sigZ = - (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 - | sig128Z[indexWord( 4, 2 )]; - } else { - sig128C[indexWord( 4, 3 )] = sigC>>32; - sig128C[indexWord( 4, 2 )] = sigC; - sig128C[indexWord( 4, 1 )] = 0; - sig128C[indexWord( 4, 0 )] = 0; - softfloat_shiftRightJam128M( sig128C, expDiff, sig128C ); - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( signZ == signC ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expDiff <= 0 ) { - sigZ += sigC; - } else { - softfloat_add128M( sig128Z, sig128C, sig128Z ); - sigZ = - (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 - | sig128Z[indexWord( 4, 2 )]; - } - if ( sigZ & UINT64_C( 0x8000000000000000 ) ) { - ++expZ; - sigZ = softfloat_shortShiftRightJam64( sigZ, 1 ); - } - } else { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expDiff < 0 ) { - signZ = signC; - if ( expDiff < -1 ) { - sigZ = sigC - sigZ; - if ( - sig128Z[indexWord( 4, 1 )] || sig128Z[indexWord( 4, 0 )] - ) { - sigZ = (sigZ - 1) | 1; - } - if ( ! (sigZ & UINT64_C( 0x4000000000000000 )) ) { - --expZ; - sigZ <<= 1; - } - goto roundPack; - } else { - sig128C[indexWord( 4, 3 )] = sigC>>32; - sig128C[indexWord( 4, 2 )] = sigC; - sig128C[indexWord( 4, 1 )] = 0; - sig128C[indexWord( 4, 0 )] = 0; - softfloat_sub128M( sig128C, sig128Z, sig128Z ); - } - } else if ( ! expDiff ) { - sigZ -= sigC; - if ( - ! sigZ && ! sig128Z[indexWord( 4, 1 )] - && ! sig128Z[indexWord( 4, 0 )] - ) { - goto completeCancellation; - } - sig128Z[indexWord( 4, 3 )] = sigZ>>32; - sig128Z[indexWord( 4, 2 )] = sigZ; - if ( sigZ & UINT64_C( 0x8000000000000000 ) ) { - signZ = ! signZ; - softfloat_negX128M( sig128Z ); - } - } else { - softfloat_sub128M( sig128Z, sig128C, sig128Z ); - if ( 1 < expDiff ) { - sigZ = - (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 - | sig128Z[indexWord( 4, 2 )]; - if ( ! (sigZ & UINT64_C( 0x4000000000000000 )) ) { - --expZ; - sigZ <<= 1; - } - goto sigZ; - } - } - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - shiftDist = 0; - sigZ = - (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 - | sig128Z[indexWord( 4, 2 )]; - if ( ! sigZ ) { - shiftDist = 64; - sigZ = - (uint64_t) sig128Z[indexWord( 4, 1 )]<<32 - | sig128Z[indexWord( 4, 0 )]; - } - shiftDist += softfloat_countLeadingZeros64( sigZ ) - 1; - if ( shiftDist ) { - expZ -= shiftDist; - softfloat_shiftLeft128M( sig128Z, shiftDist, sig128Z ); - sigZ = - (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 - | sig128Z[indexWord( 4, 2 )]; - } - } - sigZ: - if ( sig128Z[indexWord( 4, 1 )] || sig128Z[indexWord( 4, 0 )] ) sigZ |= 1; - roundPack: - return softfloat_roundPackToF64( signZ, expZ - 1, sigZ ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN_ABC: - uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); - goto propagateNaN_ZC; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - infProdArg: - if ( magBits ) { - uiZ = packToF64UI( signZ, 0x7FF, 0 ); - if ( expC != 0x7FF ) goto uiZ; - if ( sigC ) goto propagateNaN_ZC; - if ( signZ == signC ) goto uiZ; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF64UI; - propagateNaN_ZC: - uiZ = softfloat_propagateNaNF64UI( uiZ, uiC ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - zeroProd: - uiZ = uiC; - if ( ! (expC | sigC) && (signZ != signC) ) { - completeCancellation: - uiZ = - packToF64UI( - (softfloat_roundingMode == softfloat_round_min), 0, 0 ); - } - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - -#endif - diff --git a/softfloat/source/s_negXM.c b/softfloat/source/s_negXM.c deleted file mode 100644 index ec8c928..0000000 --- a/softfloat/source/s_negXM.c +++ /dev/null @@ -1,63 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_negXM - -void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr ) -{ - unsigned int index, lastIndex; - uint_fast8_t carry; - uint32_t word; - - index = indexWordLo( size_words ); - lastIndex = indexWordHi( size_words ); - carry = 1; - for (;;) { - word = ~zPtr[index] + carry; - zPtr[index] = word; - if ( index == lastIndex ) break; - index += wordIncr; - if ( word ) carry = 0; - } - -} - -#endif - diff --git a/softfloat/source/s_normExtF80SigM.c b/softfloat/source/s_normExtF80SigM.c deleted file mode 100644 index acc54dc..0000000 --- a/softfloat/source/s_normExtF80SigM.c +++ /dev/null @@ -1,52 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" - -int softfloat_normExtF80SigM( uint64_t *sigPtr ) -{ - uint64_t sig; - int_fast8_t shiftDist; - - sig = *sigPtr; - shiftDist = softfloat_countLeadingZeros64( sig ); - *sigPtr = sig< -#include -#include "platform.h" -#include "internals.h" - -void - softfloat_normRoundPackMToExtF80M( - bool sign, - int32_t exp, - uint32_t *extSigPtr, - uint_fast8_t roundingPrecision, - struct extFloat80M *zSPtr - ) -{ - int_fast16_t shiftDist; - uint32_t wordSig; - - shiftDist = 0; - wordSig = extSigPtr[indexWord( 3, 2 )]; - if ( ! wordSig ) { - shiftDist = 32; - wordSig = extSigPtr[indexWord( 3, 1 )]; - if ( ! wordSig ) { - shiftDist = 64; - wordSig = extSigPtr[indexWord( 3, 0 )]; - if ( ! wordSig ) { - zSPtr->signExp = packToExtF80UI64( sign, 0 ); - zSPtr->signif = 0; - return; - } - } - } - shiftDist += softfloat_countLeadingZeros32( wordSig ); - if ( shiftDist ) { - exp -= shiftDist; - softfloat_shiftLeft96M( extSigPtr, shiftDist, extSigPtr ); - } - softfloat_roundPackMToExtF80M( - sign, exp, extSigPtr, roundingPrecision, zSPtr ); - -} - diff --git a/softfloat/source/s_normRoundPackMToF128M.c b/softfloat/source/s_normRoundPackMToF128M.c deleted file mode 100644 index 3094559..0000000 --- a/softfloat/source/s_normRoundPackMToF128M.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" - -void - softfloat_normRoundPackMToF128M( - bool sign, int32_t exp, uint32_t *extSigPtr, uint32_t *zWPtr ) -{ - const uint32_t *ptr; - int_fast16_t shiftDist; - uint32_t wordSig; - - ptr = extSigPtr + indexWordHi( 5 ); - shiftDist = 0; - for (;;) { - wordSig = *ptr; - if ( wordSig ) break; - shiftDist += 32; - if ( 160 <= shiftDist ) { - zWPtr[indexWordHi( 4 )] = packToF128UI96( sign, 0, 0 ); - zWPtr[indexWord( 4, 2 )] = 0; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - return; - } - ptr -= wordIncr; - } - shiftDist += softfloat_countLeadingZeros32( wordSig ) - 15; - if ( shiftDist ) { - exp -= shiftDist; - softfloat_shiftLeft160M( extSigPtr, shiftDist, extSigPtr ); - } - softfloat_roundPackMToF128M( sign, exp, extSigPtr, zWPtr ); - -} - diff --git a/softfloat/source/s_normRoundPackToExtF80.c b/softfloat/source/s_normRoundPackToExtF80.c deleted file mode 100644 index 76e791d..0000000 --- a/softfloat/source/s_normRoundPackToExtF80.c +++ /dev/null @@ -1,71 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" - -extFloat80_t - softfloat_normRoundPackToExtF80( - bool sign, - int_fast32_t exp, - uint_fast64_t sig, - uint_fast64_t sigExtra, - uint_fast8_t roundingPrecision - ) -{ - int_fast8_t shiftDist; - struct uint128 sig128; - - if ( ! sig ) { - exp -= 64; - sig = sigExtra; - sigExtra = 0; - } - shiftDist = softfloat_countLeadingZeros64( sig ); - exp -= shiftDist; - if ( shiftDist ) { - sig128 = softfloat_shortShiftLeft128( sig, sigExtra, shiftDist ); - sig = sig128.v64; - sigExtra = sig128.v0; - } - return - softfloat_roundPackToExtF80( - sign, exp, sig, sigExtra, roundingPrecision ); - -} - diff --git a/softfloat/source/s_normRoundPackToF128.c b/softfloat/source/s_normRoundPackToF128.c deleted file mode 100644 index 67f5b43..0000000 --- a/softfloat/source/s_normRoundPackToF128.c +++ /dev/null @@ -1,81 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" - -float128_t - softfloat_normRoundPackToF128( - bool sign, int_fast32_t exp, uint_fast64_t sig64, uint_fast64_t sig0 ) -{ - int_fast8_t shiftDist; - struct uint128 sig128; - union ui128_f128 uZ; - uint_fast64_t sigExtra; - struct uint128_extra sig128Extra; - - if ( ! sig64 ) { - exp -= 64; - sig64 = sig0; - sig0 = 0; - } - shiftDist = softfloat_countLeadingZeros64( sig64 ) - 15; - exp -= shiftDist; - if ( 0 <= shiftDist ) { - if ( shiftDist ) { - sig128 = softfloat_shortShiftLeft128( sig64, sig0, shiftDist ); - sig64 = sig128.v64; - sig0 = sig128.v0; - } - if ( (uint32_t) exp < 0x7FFD ) { - uZ.ui.v64 = packToF128UI64( sign, sig64 | sig0 ? exp : 0, sig64 ); - uZ.ui.v0 = sig0; - return uZ.f; - } - sigExtra = 0; - } else { - sig128Extra = - softfloat_shortShiftRightJam128Extra( sig64, sig0, 0, -shiftDist ); - sig64 = sig128Extra.v.v64; - sig0 = sig128Extra.v.v0; - sigExtra = sig128Extra.extra; - } - return softfloat_roundPackToF128( sign, exp, sig64, sig0, sigExtra ); - -} - diff --git a/softfloat/source/s_normRoundPackToF16.c b/softfloat/source/s_normRoundPackToF16.c deleted file mode 100644 index 1d184d5..0000000 --- a/softfloat/source/s_normRoundPackToF16.c +++ /dev/null @@ -1,58 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" - -float16_t - softfloat_normRoundPackToF16( bool sign, int_fast16_t exp, uint_fast16_t sig ) -{ - int_fast8_t shiftDist; - union ui16_f16 uZ; - - shiftDist = softfloat_countLeadingZeros16( sig ) - 1; - exp -= shiftDist; - if ( (4 <= shiftDist) && ((unsigned int) exp < 0x1D) ) { - uZ.ui = packToF16UI( sign, sig ? exp : 0, sig<<(shiftDist - 4) ); - return uZ.f; - } else { - return softfloat_roundPackToF16( sign, exp, sig< -#include -#include "platform.h" -#include "internals.h" - -float32_t - softfloat_normRoundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig ) -{ - int_fast8_t shiftDist; - union ui32_f32 uZ; - - shiftDist = softfloat_countLeadingZeros32( sig ) - 1; - exp -= shiftDist; - if ( (7 <= shiftDist) && ((unsigned int) exp < 0xFD) ) { - uZ.ui = packToF32UI( sign, sig ? exp : 0, sig<<(shiftDist - 7) ); - return uZ.f; - } else { - return softfloat_roundPackToF32( sign, exp, sig< -#include -#include "platform.h" -#include "internals.h" - -float64_t - softfloat_normRoundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig ) -{ - int_fast8_t shiftDist; - union ui64_f64 uZ; - - shiftDist = softfloat_countLeadingZeros64( sig ) - 1; - exp -= shiftDist; - if ( (10 <= shiftDist) && ((unsigned int) exp < 0x7FD) ) { - uZ.ui = packToF64UI( sign, sig ? exp : 0, sig<<(shiftDist - 10) ); - return uZ.f; - } else { - return softfloat_roundPackToF64( sign, exp, sig< -#include "platform.h" -#include "internals.h" - -struct exp8_sig16 softfloat_normSubnormalBF16Sig( uint_fast16_t sig ) -{ - int_fast8_t shiftDist; - struct exp8_sig16 z; - - shiftDist = softfloat_countLeadingZeros16( sig ) - 8; - z.exp = 1 - shiftDist; - z.sig = sig< -#include "platform.h" -#include "internals.h" - -struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t sig ) -{ - int_fast8_t shiftDist; - struct exp32_sig64 z; - - shiftDist = softfloat_countLeadingZeros64( sig ); - z.exp = -shiftDist; - z.sig = sig< -#include "platform.h" -#include "internals.h" - -struct exp32_sig128 - softfloat_normSubnormalF128Sig( uint_fast64_t sig64, uint_fast64_t sig0 ) -{ - int_fast8_t shiftDist; - struct exp32_sig128 z; - - if ( ! sig64 ) { - shiftDist = softfloat_countLeadingZeros64( sig0 ) - 15; - z.exp = -63 - shiftDist; - if ( shiftDist < 0 ) { - z.sig.v64 = sig0>>-shiftDist; - z.sig.v0 = sig0<<(shiftDist & 63); - } else { - z.sig.v64 = sig0< -#include "platform.h" -#include "internals.h" - -int softfloat_normSubnormalF128SigM( uint32_t *sigPtr ) -{ - const uint32_t *ptr; - int_fast16_t shiftDist; - uint32_t wordSig; - - ptr = sigPtr + indexWordHi( 4 ); - shiftDist = 0; - for (;;) { - wordSig = *ptr; - if ( wordSig ) break; - shiftDist += 32; - if ( 128 <= shiftDist ) return 1; - ptr -= wordIncr; - } - shiftDist += softfloat_countLeadingZeros32( wordSig ) - 15; - if ( shiftDist ) softfloat_shiftLeft128M( sigPtr, shiftDist, sigPtr ); - return 1 - shiftDist; - -} - diff --git a/softfloat/source/s_normSubnormalF16Sig.c b/softfloat/source/s_normSubnormalF16Sig.c deleted file mode 100644 index bb92adf..0000000 --- a/softfloat/source/s_normSubnormalF16Sig.c +++ /dev/null @@ -1,52 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" - -struct exp8_sig16 softfloat_normSubnormalF16Sig( uint_fast16_t sig ) -{ - int_fast8_t shiftDist; - struct exp8_sig16 z; - - shiftDist = softfloat_countLeadingZeros16( sig ) - 5; - z.exp = 1 - shiftDist; - z.sig = sig< -#include "platform.h" -#include "internals.h" - -struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t sig ) -{ - int_fast8_t shiftDist; - struct exp16_sig32 z; - - shiftDist = softfloat_countLeadingZeros32( sig ) - 8; - z.exp = 1 - shiftDist; - z.sig = sig< -#include "platform.h" -#include "internals.h" - -struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t sig ) -{ - int_fast8_t shiftDist; - struct exp16_sig64 z; - - shiftDist = softfloat_countLeadingZeros64( sig ) - 11; - z.exp = 1 - shiftDist; - z.sig = sig< -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_remStepMBy32 - -void - softfloat_remStepMBy32( - uint_fast8_t size_words, - const uint32_t *remPtr, - uint_fast8_t dist, - const uint32_t *bPtr, - uint32_t q, - uint32_t *zPtr - ) -{ - unsigned int index, lastIndex; - uint64_t dwordProd; - uint32_t wordRem, wordShiftedRem, wordProd; - uint_fast8_t uNegDist, borrow; - - index = indexWordLo( size_words ); - lastIndex = indexWordHi( size_words ); - dwordProd = (uint64_t) bPtr[index] * q; - wordRem = remPtr[index]; - wordShiftedRem = wordRem<>(uNegDist & 31); - index += wordIncr; - dwordProd = (uint64_t) bPtr[index] * q + (dwordProd>>32); - wordRem = remPtr[index]; - wordShiftedRem |= wordRem< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t - softfloat_roundMToI64( - bool sign, uint32_t *extSigPtr, uint_fast8_t roundingMode, bool exact ) -{ - uint64_t sig; - uint32_t sigExtra; - union { uint64_t ui; int64_t i; } uZ; - int64_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig = - (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32 - | extSigPtr[indexWord( 3, 1 )]; - sigExtra = extSigPtr[indexWordLo( 3 )]; - if ( - (roundingMode == softfloat_round_near_maxMag) - || (roundingMode == softfloat_round_near_even) - ) { - if ( 0x80000000 <= sigExtra ) goto increment; - } else { - if ( - sigExtra - && (sign - ? (roundingMode == softfloat_round_min) -#ifdef SOFTFLOAT_ROUND_ODD - || (roundingMode == softfloat_round_odd) -#endif - : (roundingMode == softfloat_round_max)) - ) { - increment: - ++sig; - if ( !sig ) goto invalid; - if ( - (sigExtra == 0x80000000) - && (roundingMode == softfloat_round_near_even) - ) { - sig &= ~(uint_fast64_t) 1; - } - } - } - uZ.ui = sign ? -sig : sig; - z = uZ.i; - if ( z && ((z < 0) ^ sign) ) goto invalid; - if ( sigExtra ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) z |= 1; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return z; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return sign ? i64_fromNegOverflow : i64_fromPosOverflow; - -} - diff --git a/softfloat/source/s_roundMToUI64.c b/softfloat/source/s_roundMToUI64.c deleted file mode 100644 index 196f537..0000000 --- a/softfloat/source/s_roundMToUI64.c +++ /dev/null @@ -1,98 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t - softfloat_roundMToUI64( - bool sign, uint32_t *extSigPtr, uint_fast8_t roundingMode, bool exact ) -{ - uint64_t sig; - uint32_t sigExtra; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig = - (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32 - | extSigPtr[indexWord( 3, 1 )]; - sigExtra = extSigPtr[indexWordLo( 3 )]; - if ( - (roundingMode == softfloat_round_near_maxMag) - || (roundingMode == softfloat_round_near_even) - ) { - if ( 0x80000000 <= sigExtra ) goto increment; - } else { - if ( sign ) { - if ( !(sig | sigExtra) ) return 0; - if ( roundingMode == softfloat_round_min ) goto invalid; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) goto invalid; -#endif - } else { - if ( (roundingMode == softfloat_round_max) && sigExtra ) { - increment: - ++sig; - if ( !sig ) goto invalid; - if ( - (sigExtra == 0x80000000) - && (roundingMode == softfloat_round_near_even) - ) { - sig &= ~(uint_fast64_t) 1; - } - } - } - } - if ( sign && sig ) goto invalid; - if ( sigExtra ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) sig |= 1; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return sig; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - -} - diff --git a/softfloat/source/s_roundPackMToExtF80M.c b/softfloat/source/s_roundPackMToExtF80M.c deleted file mode 100644 index 0862015..0000000 --- a/softfloat/source/s_roundPackMToExtF80M.c +++ /dev/null @@ -1,256 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -void - softfloat_roundPackMToExtF80M( - bool sign, - int32_t exp, - uint32_t *extSigPtr, - uint_fast8_t roundingPrecision, - struct extFloat80M *zSPtr - ) -{ - uint_fast8_t roundingMode; - bool roundNearEven; - uint64_t sig, roundIncrement, roundMask, roundBits; - bool isTiny; - uint32_t sigExtra; - bool doIncrement; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundingMode = softfloat_roundingMode; - roundNearEven = (roundingMode == softfloat_round_near_even); - sig = - (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32 - | extSigPtr[indexWord( 3, 1 )]; - if ( roundingPrecision == 80 ) goto precision80; - if ( roundingPrecision == 64 ) { - roundIncrement = UINT64_C( 0x0000000000000400 ); - roundMask = UINT64_C( 0x00000000000007FF ); - } else if ( roundingPrecision == 32 ) { - roundIncrement = UINT64_C( 0x0000008000000000 ); - roundMask = UINT64_C( 0x000000FFFFFFFFFF ); - } else { - goto precision80; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( extSigPtr[indexWordLo( 3 )] ) sig |= 1; - if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { - roundIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - ? roundMask - : 0; - } - roundBits = sig & roundMask; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x7FFD <= (uint32_t) (exp - 1) ) { - if ( exp <= 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - isTiny = - (softfloat_detectTininess - == softfloat_tininess_beforeRounding) - || (exp < 0) - || (sig <= (uint64_t) (sig + roundIncrement)); - sig = softfloat_shiftRightJam64( sig, 1 - exp ); - roundBits = sig & roundMask; - if ( roundBits ) { - if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow ); - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig |= roundMask + 1; - } -#endif - } - sig += roundIncrement; - exp = ((sig & UINT64_C( 0x8000000000000000 )) != 0); - roundIncrement = roundMask + 1; - if ( roundNearEven && (roundBits<<1 == roundIncrement) ) { - roundMask |= roundIncrement; - } - sig &= ~roundMask; - goto packReturn; - } - if ( - (0x7FFE < exp) - || ((exp == 0x7FFE) && ((uint64_t) (sig + roundIncrement) < sig)) - ) { - goto overflow; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( roundBits ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig = (sig & ~roundMask) | (roundMask + 1); - goto packReturn; - } -#endif - } - sig += roundIncrement; - if ( sig < roundIncrement ) { - ++exp; - sig = UINT64_C( 0x8000000000000000 ); - } - roundIncrement = roundMask + 1; - if ( roundNearEven && (roundBits<<1 == roundIncrement) ) { - roundMask |= roundIncrement; - } - sig &= ~roundMask; - goto packReturn; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - precision80: - sigExtra = extSigPtr[indexWordLo( 3 )]; - doIncrement = (0x80000000 <= sigExtra); - if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { - doIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - && sigExtra; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x7FFD <= (uint32_t) (exp - 1) ) { - if ( exp <= 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - isTiny = - (softfloat_detectTininess - == softfloat_tininess_beforeRounding) - || (exp < 0) - || ! doIncrement - || (sig < UINT64_C( 0xFFFFFFFFFFFFFFFF )); - softfloat_shiftRightJam96M( extSigPtr, 1 - exp, extSigPtr ); - exp = 0; - sig = - (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32 - | extSigPtr[indexWord( 3, 1 )]; - sigExtra = extSigPtr[indexWordLo( 3 )]; - if ( sigExtra ) { - if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow ); - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig |= 1; - goto packReturn; - } -#endif - } - doIncrement = (0x80000000 <= sigExtra); - if ( - ! roundNearEven - && (roundingMode != softfloat_round_near_maxMag) - ) { - doIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - && sigExtra; - } - if ( doIncrement ) { - ++sig; - sig &= ~(uint64_t) (! (sigExtra & 0x7FFFFFFF) & roundNearEven); - exp = ((sig & UINT64_C( 0x8000000000000000 )) != 0); - } - goto packReturn; - } - if ( - (0x7FFE < exp) - || ((exp == 0x7FFE) && (sig == UINT64_C( 0xFFFFFFFFFFFFFFFF )) - && doIncrement) - ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - roundMask = 0; - overflow: - softfloat_raiseFlags( - softfloat_flag_overflow | softfloat_flag_inexact ); - if ( - roundNearEven - || (roundingMode == softfloat_round_near_maxMag) - || (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - ) { - exp = 0x7FFF; - sig = UINT64_C( 0x8000000000000000 ); - } else { - exp = 0x7FFE; - sig = ~roundMask; - } - goto packReturn; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( sigExtra ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig |= 1; - goto packReturn; - } -#endif - } - if ( doIncrement ) { - ++sig; - if ( ! sig ) { - ++exp; - sig = UINT64_C( 0x8000000000000000 ); - } else { - sig &= ~(uint64_t) (! (sigExtra & 0x7FFFFFFF) & roundNearEven); - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - packReturn: - zSPtr->signExp = packToExtF80UI64( sign, exp ); - zSPtr->signif = sig; - -} - diff --git a/softfloat/source/s_roundPackMToF128M.c b/softfloat/source/s_roundPackMToF128M.c deleted file mode 100644 index 22591b8..0000000 --- a/softfloat/source/s_roundPackMToF128M.c +++ /dev/null @@ -1,178 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -void - softfloat_roundPackMToF128M( - bool sign, int32_t exp, uint32_t *extSigPtr, uint32_t *zWPtr ) -{ - uint_fast8_t roundingMode; - bool roundNearEven; - uint32_t sigExtra; - bool doIncrement, isTiny; - static const uint32_t maxSig[4] = - INIT_UINTM4( 0x0001FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF ); - uint32_t ui, uj; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundingMode = softfloat_roundingMode; - roundNearEven = (roundingMode == softfloat_round_near_even); - sigExtra = extSigPtr[indexWordLo( 5 )]; - doIncrement = (0x80000000 <= sigExtra); - if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { - doIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - && sigExtra; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x7FFD <= (uint32_t) exp ) { - if ( exp < 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - isTiny = - (softfloat_detectTininess - == softfloat_tininess_beforeRounding) - || (exp < -1) - || ! doIncrement - || (softfloat_compare128M( - extSigPtr + indexMultiwordHi( 5, 4 ), maxSig ) - < 0); - softfloat_shiftRightJam160M( extSigPtr, -exp, extSigPtr ); - exp = 0; - sigExtra = extSigPtr[indexWordLo( 5 )]; - if ( isTiny && sigExtra ) { - softfloat_raiseFlags( softfloat_flag_underflow ); - } - doIncrement = (0x80000000 <= sigExtra); - if ( - ! roundNearEven - && (roundingMode != softfloat_round_near_maxMag) - ) { - doIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - && sigExtra; - } - } else if ( - (0x7FFD < exp) - || ((exp == 0x7FFD) && doIncrement - && (softfloat_compare128M( - extSigPtr + indexMultiwordHi( 5, 4 ), maxSig ) - == 0)) - ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - softfloat_raiseFlags( - softfloat_flag_overflow | softfloat_flag_inexact ); - if ( - roundNearEven - || (roundingMode == softfloat_round_near_maxMag) - || (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - ) { - ui = packToF128UI96( sign, 0x7FFF, 0 ); - uj = 0; - } else { - ui = packToF128UI96( sign, 0x7FFE, 0x0000FFFF ); - uj = 0xFFFFFFFF; - } - zWPtr[indexWordHi( 4 )] = ui; - zWPtr[indexWord( 4, 2 )] = uj; - zWPtr[indexWord( 4, 1 )] = uj; - zWPtr[indexWord( 4, 0 )] = uj; - return; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - uj = extSigPtr[indexWord( 5, 1 )]; - if ( sigExtra ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - uj |= 1; - goto noIncrementPackReturn; - } -#endif - } - if ( doIncrement ) { - ++uj; - if ( uj ) { - if ( ! (sigExtra & 0x7FFFFFFF) && roundNearEven ) uj &= ~1; - zWPtr[indexWord( 4, 2 )] = extSigPtr[indexWord( 5, 3 )]; - zWPtr[indexWord( 4, 1 )] = extSigPtr[indexWord( 5, 2 )]; - zWPtr[indexWord( 4, 0 )] = uj; - ui = extSigPtr[indexWordHi( 5 )]; - } else { - zWPtr[indexWord( 4, 0 )] = uj; - ui = extSigPtr[indexWord( 5, 2 )] + 1; - zWPtr[indexWord( 4, 1 )] = ui; - uj = extSigPtr[indexWord( 5, 3 )]; - if ( ui ) { - zWPtr[indexWord( 4, 2 )] = uj; - ui = extSigPtr[indexWordHi( 5 )]; - } else { - ++uj; - zWPtr[indexWord( 4, 2 )] = uj; - ui = extSigPtr[indexWordHi( 5 )]; - if ( ! uj ) ++ui; - } - } - } else { - noIncrementPackReturn: - zWPtr[indexWord( 4, 0 )] = uj; - ui = extSigPtr[indexWord( 5, 2 )]; - zWPtr[indexWord( 4, 1 )] = ui; - uj |= ui; - ui = extSigPtr[indexWord( 5, 3 )]; - zWPtr[indexWord( 4, 2 )] = ui; - uj |= ui; - ui = extSigPtr[indexWordHi( 5 )]; - uj |= ui; - if ( ! uj ) exp = 0; - } - zWPtr[indexWordHi( 4 )] = packToF128UI96( sign, exp, ui ); - -} - diff --git a/softfloat/source/s_roundPackToBF16.c b/softfloat/source/s_roundPackToBF16.c deleted file mode 100644 index 57a7ae4..0000000 --- a/softfloat/source/s_roundPackToBF16.c +++ /dev/null @@ -1,114 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -/** sig last significant bit is sig[7], the 7 LSBs will be used for rounding */ -bfloat16_t - softfloat_roundPackToBF16( bool sign, int_fast16_t exp, uint_fast16_t sig ) -{ - uint_fast8_t roundingMode; - bool roundNearEven; - uint_fast8_t roundIncrement, roundBits; - bool isTiny; - uint_fast16_t uiZ; - union ui16_bf16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundingMode = softfloat_roundingMode; - roundNearEven = (roundingMode == softfloat_round_near_even); - roundIncrement = 0x40; - if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { - roundIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - ? 0x7F - : 0; - } - roundBits = sig & 0x7F; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0xFD <= (unsigned int) exp ) { - if ( exp < 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - isTiny = - (softfloat_detectTininess == softfloat_tininess_beforeRounding) - || (exp < -1) || (sig + roundIncrement < 0x8000); - sig = softfloat_shiftRightJam32( sig, -exp ); - exp = 0; - roundBits = sig & 0x7F; - if ( isTiny && roundBits ) { - softfloat_raiseFlags( softfloat_flag_underflow ); - } - } else if ( (0xFD < exp) || (0x8000 <= sig + roundIncrement) ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - softfloat_raiseFlags( - softfloat_flag_overflow | softfloat_flag_inexact ); - uiZ = packToBF16UI( sign, 0xFF, 0 ) - ! roundIncrement; - goto uiZ; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig = (sig + roundIncrement)>>7; - if ( roundBits ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig |= 1; - goto packReturn; - } -#endif - } - sig &= ~(uint_fast16_t) (! (roundBits ^ 0x40) & roundNearEven); - if ( ! sig ) exp = 0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - packReturn: - uiZ = packToBF16UI( sign, exp, sig ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_roundPackToExtF80.c b/softfloat/source/s_roundPackToExtF80.c deleted file mode 100644 index 0cc7af9..0000000 --- a/softfloat/source/s_roundPackToExtF80.c +++ /dev/null @@ -1,256 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -extFloat80_t - softfloat_roundPackToExtF80( - bool sign, - int_fast32_t exp, - uint_fast64_t sig, - uint_fast64_t sigExtra, - uint_fast8_t roundingPrecision - ) -{ - uint_fast8_t roundingMode; - bool roundNearEven; - uint_fast64_t roundIncrement, roundMask, roundBits; - bool isTiny, doIncrement; - struct uint64_extra sig64Extra; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundingMode = softfloat_roundingMode; - roundNearEven = (roundingMode == softfloat_round_near_even); - if ( roundingPrecision == 80 ) goto precision80; - if ( roundingPrecision == 64 ) { - roundIncrement = UINT64_C( 0x0000000000000400 ); - roundMask = UINT64_C( 0x00000000000007FF ); - } else if ( roundingPrecision == 32 ) { - roundIncrement = UINT64_C( 0x0000008000000000 ); - roundMask = UINT64_C( 0x000000FFFFFFFFFF ); - } else { - goto precision80; - } - sig |= (sigExtra != 0); - if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { - roundIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - ? roundMask - : 0; - } - roundBits = sig & roundMask; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x7FFD <= (uint32_t) (exp - 1) ) { - if ( exp <= 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - isTiny = - (softfloat_detectTininess - == softfloat_tininess_beforeRounding) - || (exp < 0) - || (sig <= (uint64_t) (sig + roundIncrement)); - sig = softfloat_shiftRightJam64( sig, 1 - exp ); - roundBits = sig & roundMask; - if ( roundBits ) { - if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow ); - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig |= roundMask + 1; - } -#endif - } - sig += roundIncrement; - exp = ((sig & UINT64_C( 0x8000000000000000 )) != 0); - roundIncrement = roundMask + 1; - if ( roundNearEven && (roundBits<<1 == roundIncrement) ) { - roundMask |= roundIncrement; - } - sig &= ~roundMask; - goto packReturn; - } - if ( - (0x7FFE < exp) - || ((exp == 0x7FFE) && ((uint64_t) (sig + roundIncrement) < sig)) - ) { - goto overflow; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( roundBits ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig = (sig & ~roundMask) | (roundMask + 1); - goto packReturn; - } -#endif - } - sig = (uint64_t) (sig + roundIncrement); - if ( sig < roundIncrement ) { - ++exp; - sig = UINT64_C( 0x8000000000000000 ); - } - roundIncrement = roundMask + 1; - if ( roundNearEven && (roundBits<<1 == roundIncrement) ) { - roundMask |= roundIncrement; - } - sig &= ~roundMask; - goto packReturn; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - precision80: - doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra); - if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { - doIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - && sigExtra; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x7FFD <= (uint32_t) (exp - 1) ) { - if ( exp <= 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - isTiny = - (softfloat_detectTininess - == softfloat_tininess_beforeRounding) - || (exp < 0) - || ! doIncrement - || (sig < UINT64_C( 0xFFFFFFFFFFFFFFFF )); - sig64Extra = - softfloat_shiftRightJam64Extra( sig, sigExtra, 1 - exp ); - exp = 0; - sig = sig64Extra.v; - sigExtra = sig64Extra.extra; - if ( sigExtra ) { - if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow ); - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig |= 1; - goto packReturn; - } -#endif - } - doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra); - if ( - ! roundNearEven - && (roundingMode != softfloat_round_near_maxMag) - ) { - doIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - && sigExtra; - } - if ( doIncrement ) { - ++sig; - sig &= - ~(uint_fast64_t) - (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - & roundNearEven); - exp = ((sig & UINT64_C( 0x8000000000000000 )) != 0); - } - goto packReturn; - } - if ( - (0x7FFE < exp) - || ((exp == 0x7FFE) && (sig == UINT64_C( 0xFFFFFFFFFFFFFFFF )) - && doIncrement) - ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - roundMask = 0; - overflow: - softfloat_raiseFlags( - softfloat_flag_overflow | softfloat_flag_inexact ); - if ( - roundNearEven - || (roundingMode == softfloat_round_near_maxMag) - || (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - ) { - exp = 0x7FFF; - sig = UINT64_C( 0x8000000000000000 ); - } else { - exp = 0x7FFE; - sig = ~roundMask; - } - goto packReturn; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( sigExtra ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig |= 1; - goto packReturn; - } -#endif - } - if ( doIncrement ) { - ++sig; - if ( ! sig ) { - ++exp; - sig = UINT64_C( 0x8000000000000000 ); - } else { - sig &= - ~(uint_fast64_t) - (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - & roundNearEven); - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - packReturn: - uZ.s.signExp = packToExtF80UI64( sign, exp ); - uZ.s.signif = sig; - return uZ.f; - -} - diff --git a/softfloat/source/s_roundPackToF128.c b/softfloat/source/s_roundPackToF128.c deleted file mode 100644 index 4158431..0000000 --- a/softfloat/source/s_roundPackToF128.c +++ /dev/null @@ -1,171 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float128_t - softfloat_roundPackToF128( - bool sign, - int_fast32_t exp, - uint_fast64_t sig64, - uint_fast64_t sig0, - uint_fast64_t sigExtra - ) -{ - uint_fast8_t roundingMode; - bool roundNearEven, doIncrement, isTiny; - struct uint128_extra sig128Extra; - uint_fast64_t uiZ64, uiZ0; - struct uint128 sig128; - union ui128_f128 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundingMode = softfloat_roundingMode; - roundNearEven = (roundingMode == softfloat_round_near_even); - doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra); - if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { - doIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - && sigExtra; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x7FFD <= (uint32_t) exp ) { - if ( exp < 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - isTiny = - (softfloat_detectTininess - == softfloat_tininess_beforeRounding) - || (exp < -1) - || ! doIncrement - || softfloat_lt128( - sig64, - sig0, - UINT64_C( 0x0001FFFFFFFFFFFF ), - UINT64_C( 0xFFFFFFFFFFFFFFFF ) - ); - sig128Extra = - softfloat_shiftRightJam128Extra( sig64, sig0, sigExtra, -exp ); - sig64 = sig128Extra.v.v64; - sig0 = sig128Extra.v.v0; - sigExtra = sig128Extra.extra; - exp = 0; - if ( isTiny && sigExtra ) { - softfloat_raiseFlags( softfloat_flag_underflow ); - } - doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra); - if ( - ! roundNearEven - && (roundingMode != softfloat_round_near_maxMag) - ) { - doIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - && sigExtra; - } - } else if ( - (0x7FFD < exp) - || ((exp == 0x7FFD) - && softfloat_eq128( - sig64, - sig0, - UINT64_C( 0x0001FFFFFFFFFFFF ), - UINT64_C( 0xFFFFFFFFFFFFFFFF ) - ) - && doIncrement) - ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - softfloat_raiseFlags( - softfloat_flag_overflow | softfloat_flag_inexact ); - if ( - roundNearEven - || (roundingMode == softfloat_round_near_maxMag) - || (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - ) { - uiZ64 = packToF128UI64( sign, 0x7FFF, 0 ); - uiZ0 = 0; - } else { - uiZ64 = - packToF128UI64( - sign, 0x7FFE, UINT64_C( 0x0000FFFFFFFFFFFF ) ); - uiZ0 = UINT64_C( 0xFFFFFFFFFFFFFFFF ); - } - goto uiZ; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( sigExtra ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig0 |= 1; - goto packReturn; - } -#endif - } - if ( doIncrement ) { - sig128 = softfloat_add128( sig64, sig0, 0, 1 ); - sig64 = sig128.v64; - sig0 = - sig128.v0 - & ~(uint64_t) - (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF )) - & roundNearEven); - } else { - if ( ! (sig64 | sig0) ) exp = 0; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - packReturn: - uiZ64 = packToF128UI64( sign, exp, sig64 ); - uiZ0 = sig0; - uiZ: - uZ.ui.v64 = uiZ64; - uZ.ui.v0 = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/s_roundPackToF16.c b/softfloat/source/s_roundPackToF16.c deleted file mode 100644 index 2dde55b..0000000 --- a/softfloat/source/s_roundPackToF16.c +++ /dev/null @@ -1,113 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float16_t - softfloat_roundPackToF16( bool sign, int_fast16_t exp, uint_fast16_t sig ) -{ - uint_fast8_t roundingMode; - bool roundNearEven; - uint_fast8_t roundIncrement, roundBits; - bool isTiny; - uint_fast16_t uiZ; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundingMode = softfloat_roundingMode; - roundNearEven = (roundingMode == softfloat_round_near_even); - roundIncrement = 0x8; - if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { - roundIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - ? 0xF - : 0; - } - roundBits = sig & 0xF; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x1D <= (unsigned int) exp ) { - if ( exp < 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - isTiny = - (softfloat_detectTininess == softfloat_tininess_beforeRounding) - || (exp < -1) || (sig + roundIncrement < 0x8000); - sig = softfloat_shiftRightJam32( sig, -exp ); - exp = 0; - roundBits = sig & 0xF; - if ( isTiny && roundBits ) { - softfloat_raiseFlags( softfloat_flag_underflow ); - } - } else if ( (0x1D < exp) || (0x8000 <= sig + roundIncrement) ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - softfloat_raiseFlags( - softfloat_flag_overflow | softfloat_flag_inexact ); - uiZ = packToF16UI( sign, 0x1F, 0 ) - ! roundIncrement; - goto uiZ; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig = (sig + roundIncrement)>>4; - if ( roundBits ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig |= 1; - goto packReturn; - } -#endif - } - sig &= ~(uint_fast16_t) (! (roundBits ^ 8) & roundNearEven); - if ( ! sig ) exp = 0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - packReturn: - uiZ = packToF16UI( sign, exp, sig ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_roundPackToF32.c b/softfloat/source/s_roundPackToF32.c deleted file mode 100644 index a69b8d4..0000000 --- a/softfloat/source/s_roundPackToF32.c +++ /dev/null @@ -1,113 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float32_t - softfloat_roundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig ) -{ - uint_fast8_t roundingMode; - bool roundNearEven; - uint_fast8_t roundIncrement, roundBits; - bool isTiny; - uint_fast32_t uiZ; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundingMode = softfloat_roundingMode; - roundNearEven = (roundingMode == softfloat_round_near_even); - roundIncrement = 0x40; - if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { - roundIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - ? 0x7F - : 0; - } - roundBits = sig & 0x7F; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0xFD <= (unsigned int) exp ) { - if ( exp < 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - isTiny = - (softfloat_detectTininess == softfloat_tininess_beforeRounding) - || (exp < -1) || (sig + roundIncrement < 0x80000000); - sig = softfloat_shiftRightJam32( sig, -exp ); - exp = 0; - roundBits = sig & 0x7F; - if ( isTiny && roundBits ) { - softfloat_raiseFlags( softfloat_flag_underflow ); - } - } else if ( (0xFD < exp) || (0x80000000 <= sig + roundIncrement) ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - softfloat_raiseFlags( - softfloat_flag_overflow | softfloat_flag_inexact ); - uiZ = packToF32UI( sign, 0xFF, 0 ) - ! roundIncrement; - goto uiZ; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig = (sig + roundIncrement)>>7; - if ( roundBits ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig |= 1; - goto packReturn; - } -#endif - } - sig &= ~(uint_fast32_t) (! (roundBits ^ 0x40) & roundNearEven); - if ( ! sig ) exp = 0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - packReturn: - uiZ = packToF32UI( sign, exp, sig ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_roundPackToF64.c b/softfloat/source/s_roundPackToF64.c deleted file mode 100644 index f7f3abf..0000000 --- a/softfloat/source/s_roundPackToF64.c +++ /dev/null @@ -1,117 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float64_t - softfloat_roundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig ) -{ - uint_fast8_t roundingMode; - bool roundNearEven; - uint_fast16_t roundIncrement, roundBits; - bool isTiny; - uint_fast64_t uiZ; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundingMode = softfloat_roundingMode; - roundNearEven = (roundingMode == softfloat_round_near_even); - roundIncrement = 0x200; - if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { - roundIncrement = - (roundingMode - == (sign ? softfloat_round_min : softfloat_round_max)) - ? 0x3FF - : 0; - } - roundBits = sig & 0x3FF; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( 0x7FD <= (uint16_t) exp ) { - if ( exp < 0 ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - isTiny = - (softfloat_detectTininess == softfloat_tininess_beforeRounding) - || (exp < -1) - || (sig + roundIncrement < UINT64_C( 0x8000000000000000 )); - sig = softfloat_shiftRightJam64( sig, -exp ); - exp = 0; - roundBits = sig & 0x3FF; - if ( isTiny && roundBits ) { - softfloat_raiseFlags( softfloat_flag_underflow ); - } - } else if ( - (0x7FD < exp) - || (UINT64_C( 0x8000000000000000 ) <= sig + roundIncrement) - ) { - /*---------------------------------------------------------------- - *----------------------------------------------------------------*/ - softfloat_raiseFlags( - softfloat_flag_overflow | softfloat_flag_inexact ); - uiZ = packToF64UI( sign, 0x7FF, 0 ) - ! roundIncrement; - goto uiZ; - } - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - sig = (sig + roundIncrement)>>10; - if ( roundBits ) { - softfloat_exceptionFlags |= softfloat_flag_inexact; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) { - sig |= 1; - goto packReturn; - } -#endif - } - sig &= ~(uint_fast64_t) (! (roundBits ^ 0x200) & roundNearEven); - if ( ! sig ) exp = 0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - packReturn: - uiZ = packToF64UI( sign, exp, sig ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_roundToI32.c b/softfloat/source/s_roundToI32.c deleted file mode 100644 index a3e727d..0000000 --- a/softfloat/source/s_roundToI32.c +++ /dev/null @@ -1,98 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast32_t - softfloat_roundToI32( - bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact ) -{ - uint_fast16_t roundIncrement, roundBits; - uint_fast32_t sig32; - union { uint32_t ui; int32_t i; } uZ; - int_fast32_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundIncrement = 0x800; - if ( - (roundingMode != softfloat_round_near_maxMag) - && (roundingMode != softfloat_round_near_even) - ) { - roundIncrement = 0; - if ( - sign - ? (roundingMode == softfloat_round_min) -#ifdef SOFTFLOAT_ROUND_ODD - || (roundingMode == softfloat_round_odd) -#endif - : (roundingMode == softfloat_round_max) - ) { - roundIncrement = 0xFFF; - } - } - roundBits = sig & 0xFFF; - sig += roundIncrement; - if ( sig & UINT64_C( 0xFFFFF00000000000 ) ) goto invalid; - sig32 = sig>>12; - if ( - (roundBits == 0x800) && (roundingMode == softfloat_round_near_even) - ) { - sig32 &= ~(uint_fast32_t) 1; - } - uZ.ui = sign ? -sig32 : sig32; - z = uZ.i; - if ( z && ((z < 0) ^ sign) ) goto invalid; - if ( roundBits ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) z |= 1; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return z; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return sign ? i32_fromNegOverflow : i32_fromPosOverflow; - -} - diff --git a/softfloat/source/s_roundToI64.c b/softfloat/source/s_roundToI64.c deleted file mode 100644 index 773c82c..0000000 --- a/softfloat/source/s_roundToI64.c +++ /dev/null @@ -1,101 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -int_fast64_t - softfloat_roundToI64( - bool sign, - uint_fast64_t sig, - uint_fast64_t sigExtra, - uint_fast8_t roundingMode, - bool exact - ) -{ - union { uint64_t ui; int64_t i; } uZ; - int_fast64_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( - (roundingMode == softfloat_round_near_maxMag) - || (roundingMode == softfloat_round_near_even) - ) { - if ( UINT64_C( 0x8000000000000000 ) <= sigExtra ) goto increment; - } else { - if ( - sigExtra - && (sign - ? (roundingMode == softfloat_round_min) -#ifdef SOFTFLOAT_ROUND_ODD - || (roundingMode == softfloat_round_odd) -#endif - : (roundingMode == softfloat_round_max)) - ) { - increment: - ++sig; - if ( !sig ) goto invalid; - if ( - (sigExtra == UINT64_C( 0x8000000000000000 )) - && (roundingMode == softfloat_round_near_even) - ) { - sig &= ~(uint_fast64_t) 1; - } - } - } - uZ.ui = sign ? -sig : sig; - z = uZ.i; - if ( z && ((z < 0) ^ sign) ) goto invalid; - if ( sigExtra ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) z |= 1; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return z; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return sign ? i64_fromNegOverflow : i64_fromPosOverflow; - -} - diff --git a/softfloat/source/s_roundToUI32.c b/softfloat/source/s_roundToUI32.c deleted file mode 100644 index 059e231..0000000 --- a/softfloat/source/s_roundToUI32.c +++ /dev/null @@ -1,93 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast32_t - softfloat_roundToUI32( - bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact ) -{ - uint_fast16_t roundIncrement, roundBits; - uint_fast32_t z; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - roundIncrement = 0x800; - if ( - (roundingMode != softfloat_round_near_maxMag) - && (roundingMode != softfloat_round_near_even) - ) { - roundIncrement = 0; - if ( sign ) { - if ( !sig ) return 0; - if ( roundingMode == softfloat_round_min ) goto invalid; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) goto invalid; -#endif - } else { - if ( roundingMode == softfloat_round_max ) roundIncrement = 0xFFF; - } - } - roundBits = sig & 0xFFF; - sig += roundIncrement; - if ( sig & UINT64_C( 0xFFFFF00000000000 ) ) goto invalid; - z = sig>>12; - if ( - (roundBits == 0x800) && (roundingMode == softfloat_round_near_even) - ) { - z &= ~(uint_fast32_t) 1; - } - if ( sign && z ) goto invalid; - if ( roundBits ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) z |= 1; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return z; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; - -} - diff --git a/softfloat/source/s_roundToUI64.c b/softfloat/source/s_roundToUI64.c deleted file mode 100644 index 856ad97..0000000 --- a/softfloat/source/s_roundToUI64.c +++ /dev/null @@ -1,97 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast64_t - softfloat_roundToUI64( - bool sign, - uint_fast64_t sig, - uint_fast64_t sigExtra, - uint_fast8_t roundingMode, - bool exact - ) -{ - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - if ( - (roundingMode == softfloat_round_near_maxMag) - || (roundingMode == softfloat_round_near_even) - ) { - if ( UINT64_C( 0x8000000000000000 ) <= sigExtra ) goto increment; - } else { - if ( sign ) { - if ( !(sig | sigExtra) ) return 0; - if ( roundingMode == softfloat_round_min ) goto invalid; -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) goto invalid; -#endif - } else { - if ( (roundingMode == softfloat_round_max) && sigExtra ) { - increment: - ++sig; - if ( !sig ) goto invalid; - if ( - (sigExtra == UINT64_C( 0x8000000000000000 )) - && (roundingMode == softfloat_round_near_even) - ) { - sig &= ~(uint_fast64_t) 1; - } - } - } - } - if ( sign && sig ) goto invalid; - if ( sigExtra ) { -#ifdef SOFTFLOAT_ROUND_ODD - if ( roundingMode == softfloat_round_odd ) sig |= 1; -#endif - if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; - } - return sig; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - invalid: - softfloat_raiseFlags( softfloat_flag_invalid ); - return sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; - -} - diff --git a/softfloat/source/s_shiftLeftM.c b/softfloat/source/s_shiftLeftM.c deleted file mode 100644 index 71a3099..0000000 --- a/softfloat/source/s_shiftLeftM.c +++ /dev/null @@ -1,91 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_shiftLeftM - -#define softfloat_shiftLeftM softfloat_shiftLeftM -#include "primitives.h" - -void - softfloat_shiftLeftM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint32_t dist, - uint32_t *zPtr - ) -{ - uint32_t wordDist; - uint_fast8_t innerDist; - uint32_t *destPtr; - uint_fast8_t i; - - wordDist = dist>>5; - if ( wordDist < size_words ) { - aPtr += indexMultiwordLoBut( size_words, wordDist ); - innerDist = dist & 31; - if ( innerDist ) { - softfloat_shortShiftLeftM( - size_words - wordDist, - aPtr, - innerDist, - zPtr + indexMultiwordHiBut( size_words, wordDist ) - ); - if ( ! wordDist ) return; - } else { - aPtr += indexWordHi( size_words - wordDist ); - destPtr = zPtr + indexWordHi( size_words ); - for ( i = size_words - wordDist; i; --i ) { - *destPtr = *aPtr; - aPtr -= wordIncr; - destPtr -= wordIncr; - } - } - zPtr += indexMultiwordLo( size_words, wordDist ); - } else { - wordDist = size_words; - } - do { - *zPtr++ = 0; - --wordDist; - } while ( wordDist ); - -} - -#endif - diff --git a/softfloat/source/s_shiftNormSigF128M.c b/softfloat/source/s_shiftNormSigF128M.c deleted file mode 100644 index fa4976c..0000000 --- a/softfloat/source/s_shiftNormSigF128M.c +++ /dev/null @@ -1,78 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" - -int - softfloat_shiftNormSigF128M( - const uint32_t *wPtr, uint_fast8_t shiftDist, uint32_t *sigPtr ) -{ - uint32_t wordSig; - int32_t exp; - uint32_t leadingBit; - - wordSig = wPtr[indexWordHi( 4 )]; - exp = expF128UI96( wordSig ); - if ( exp ) { - softfloat_shortShiftLeft128M( wPtr, shiftDist, sigPtr ); - leadingBit = 0x00010000< -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shiftRightJam128 - -struct uint128 - softfloat_shiftRightJam128( uint64_t a64, uint64_t a0, uint_fast32_t dist ) -{ - uint_fast8_t u8NegDist; - struct uint128 z; - - if ( dist < 64 ) { - u8NegDist = -dist; - z.v64 = a64>>dist; - z.v0 = - a64<<(u8NegDist & 63) | a0>>dist - | ((uint64_t) (a0<<(u8NegDist & 63)) != 0); - } else { - z.v64 = 0; - z.v0 = - (dist < 127) - ? a64>>(dist & 63) - | (((a64 & (((uint_fast64_t) 1<<(dist & 63)) - 1)) | a0) - != 0) - : ((a64 | a0) != 0); - } - return z; - -} - -#endif - diff --git a/softfloat/source/s_shiftRightJam128Extra.c b/softfloat/source/s_shiftRightJam128Extra.c deleted file mode 100644 index 7572288..0000000 --- a/softfloat/source/s_shiftRightJam128Extra.c +++ /dev/null @@ -1,77 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shiftRightJam128Extra - -struct uint128_extra - softfloat_shiftRightJam128Extra( - uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist ) -{ - uint_fast8_t u8NegDist; - struct uint128_extra z; - - u8NegDist = -dist; - if ( dist < 64 ) { - z.v.v64 = a64>>dist; - z.v.v0 = a64<<(u8NegDist & 63) | a0>>dist; - z.extra = a0<<(u8NegDist & 63); - } else { - z.v.v64 = 0; - if ( dist == 64 ) { - z.v.v0 = a64; - z.extra = a0; - } else { - extra |= a0; - if ( dist < 128 ) { - z.v.v0 = a64>>(dist & 63); - z.extra = a64<<(u8NegDist & 63); - } else { - z.v.v0 = 0; - z.extra = (dist == 128) ? a64 : (a64 != 0); - } - } - } - z.extra |= (extra != 0); - return z; - -} - -#endif - diff --git a/softfloat/source/s_shiftRightJam256M.c b/softfloat/source/s_shiftRightJam256M.c deleted file mode 100644 index 433870a..0000000 --- a/softfloat/source/s_shiftRightJam256M.c +++ /dev/null @@ -1,126 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shiftRightJam256M - -static - void - softfloat_shortShiftRightJamM( - uint_fast8_t size_words, - const uint64_t *aPtr, - uint_fast8_t dist, - uint64_t *zPtr - ) -{ - uint_fast8_t uNegDist; - unsigned int index, lastIndex; - uint64_t partWordZ, wordA; - - uNegDist = -dist; - index = indexWordLo( size_words ); - lastIndex = indexWordHi( size_words ); - wordA = aPtr[index]; - partWordZ = wordA>>dist; - if ( partWordZ<>dist; - } - zPtr[index] = partWordZ; - -} - -void - softfloat_shiftRightJam256M( - const uint64_t *aPtr, uint_fast32_t dist, uint64_t *zPtr ) -{ - uint64_t wordJam; - uint_fast32_t wordDist; - uint64_t *ptr; - uint_fast8_t i, innerDist; - - wordJam = 0; - wordDist = dist>>6; - if ( wordDist ) { - if ( 4 < wordDist ) wordDist = 4; - ptr = (uint64_t *) (aPtr + indexMultiwordLo( 4, wordDist )); - i = wordDist; - do { - wordJam = *ptr++; - if ( wordJam ) break; - --i; - } while ( i ); - ptr = zPtr; - } - if ( wordDist < 4 ) { - aPtr += indexMultiwordHiBut( 4, wordDist ); - innerDist = dist & 63; - if ( innerDist ) { - softfloat_shortShiftRightJamM( - 4 - wordDist, - aPtr, - innerDist, - zPtr + indexMultiwordLoBut( 4, wordDist ) - ); - if ( ! wordDist ) goto wordJam; - } else { - aPtr += indexWordLo( 4 - wordDist ); - ptr = zPtr + indexWordLo( 4 ); - for ( i = 4 - wordDist; i; --i ) { - *ptr = *aPtr; - aPtr += wordIncr; - ptr += wordIncr; - } - } - ptr = zPtr + indexMultiwordHi( 4, wordDist ); - } - do { - *ptr++ = 0; - --wordDist; - } while ( wordDist ); - wordJam: - if ( wordJam ) zPtr[indexWordLo( 4 )] |= 1; - -} - -#endif - diff --git a/softfloat/source/s_shiftRightJam32.c b/softfloat/source/s_shiftRightJam32.c deleted file mode 100644 index 2533fcd..0000000 --- a/softfloat/source/s_shiftRightJam32.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_shiftRightJam32 - -uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist ) -{ - - return - (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0); - -} - -#endif - diff --git a/softfloat/source/s_shiftRightJam64.c b/softfloat/source/s_shiftRightJam64.c deleted file mode 100644 index 4b40e3d..0000000 --- a/softfloat/source/s_shiftRightJam64.c +++ /dev/null @@ -1,51 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_shiftRightJam64 - -uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist ) -{ - - return - (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0); - -} - -#endif - diff --git a/softfloat/source/s_shiftRightJam64Extra.c b/softfloat/source/s_shiftRightJam64Extra.c deleted file mode 100644 index b93fad3..0000000 --- a/softfloat/source/s_shiftRightJam64Extra.c +++ /dev/null @@ -1,62 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shiftRightJam64Extra - -struct uint64_extra - softfloat_shiftRightJam64Extra( - uint64_t a, uint64_t extra, uint_fast32_t dist ) -{ - struct uint64_extra z; - - if ( dist < 64 ) { - z.v = a>>dist; - z.extra = a<<(-dist & 63); - } else { - z.v = 0; - z.extra = (dist == 64) ? a : (a != 0); - } - z.extra |= (extra != 0); - return z; - -} - -#endif - diff --git a/softfloat/source/s_shiftRightJamM.c b/softfloat/source/s_shiftRightJamM.c deleted file mode 100644 index edf5f95..0000000 --- a/softfloat/source/s_shiftRightJamM.c +++ /dev/null @@ -1,101 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_shiftRightJamM - -#define softfloat_shiftRightJamM softfloat_shiftRightJamM -#include "primitives.h" - -void - softfloat_shiftRightJamM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint32_t dist, - uint32_t *zPtr - ) -{ - uint32_t wordJam, wordDist, *ptr; - uint_fast8_t i, innerDist; - - wordJam = 0; - wordDist = dist>>5; - if ( wordDist ) { - if ( size_words < wordDist ) wordDist = size_words; - ptr = (uint32_t *) (aPtr + indexMultiwordLo( size_words, wordDist )); - i = wordDist; - do { - wordJam = *ptr++; - if ( wordJam ) break; - --i; - } while ( i ); - ptr = zPtr; - } - if ( wordDist < size_words ) { - aPtr += indexMultiwordHiBut( size_words, wordDist ); - innerDist = dist & 31; - if ( innerDist ) { - softfloat_shortShiftRightJamM( - size_words - wordDist, - aPtr, - innerDist, - zPtr + indexMultiwordLoBut( size_words, wordDist ) - ); - if ( ! wordDist ) goto wordJam; - } else { - aPtr += indexWordLo( size_words - wordDist ); - ptr = zPtr + indexWordLo( size_words ); - for ( i = size_words - wordDist; i; --i ) { - *ptr = *aPtr; - aPtr += wordIncr; - ptr += wordIncr; - } - } - ptr = zPtr + indexMultiwordHi( size_words, wordDist ); - } - do { - *ptr++ = 0; - --wordDist; - } while ( wordDist ); - wordJam: - if ( wordJam ) zPtr[indexWordLo( size_words )] |= 1; - -} - -#endif - diff --git a/softfloat/source/s_shiftRightM.c b/softfloat/source/s_shiftRightM.c deleted file mode 100644 index 00265ea..0000000 --- a/softfloat/source/s_shiftRightM.c +++ /dev/null @@ -1,91 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_shiftRightM - -#define softfloat_shiftRightM softfloat_shiftRightM -#include "primitives.h" - -void - softfloat_shiftRightM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint32_t dist, - uint32_t *zPtr - ) -{ - uint32_t wordDist; - uint_fast8_t innerDist; - uint32_t *destPtr; - uint_fast8_t i; - - wordDist = dist>>5; - if ( wordDist < size_words ) { - aPtr += indexMultiwordHiBut( size_words, wordDist ); - innerDist = dist & 31; - if ( innerDist ) { - softfloat_shortShiftRightM( - size_words - wordDist, - aPtr, - innerDist, - zPtr + indexMultiwordLoBut( size_words, wordDist ) - ); - if ( ! wordDist ) return; - } else { - aPtr += indexWordLo( size_words - wordDist ); - destPtr = zPtr + indexWordLo( size_words ); - for ( i = size_words - wordDist; i; --i ) { - *destPtr = *aPtr; - aPtr += wordIncr; - destPtr += wordIncr; - } - } - zPtr += indexMultiwordHi( size_words, wordDist ); - } else { - wordDist = size_words; - } - do { - *zPtr++ = 0; - --wordDist; - } while ( wordDist ); - -} - -#endif - diff --git a/softfloat/source/s_shortShiftLeft128.c b/softfloat/source/s_shortShiftLeft128.c deleted file mode 100644 index 7513bc6..0000000 --- a/softfloat/source/s_shortShiftLeft128.c +++ /dev/null @@ -1,55 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shortShiftLeft128 - -struct uint128 - softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist ) -{ - struct uint128 z; - - z.v64 = a64<>(-dist & 63); - z.v0 = a0< -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shortShiftLeft64To96M - -void - softfloat_shortShiftLeft64To96M( - uint64_t a, uint_fast8_t dist, uint32_t *zPtr ) -{ - - zPtr[indexWord( 3, 0 )] = (uint32_t) a<>= 32 - dist; - zPtr[indexWord( 3, 2 )] = a>>32; - zPtr[indexWord( 3, 1 )] = a; - -} - -#endif - diff --git a/softfloat/source/s_shortShiftLeftM.c b/softfloat/source/s_shortShiftLeftM.c deleted file mode 100644 index 48e6e03..0000000 --- a/softfloat/source/s_shortShiftLeftM.c +++ /dev/null @@ -1,70 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shortShiftLeftM - -void - softfloat_shortShiftLeftM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint_fast8_t dist, - uint32_t *zPtr - ) -{ - uint_fast8_t uNegDist; - unsigned int index, lastIndex; - uint32_t partWordZ, wordA; - - uNegDist = -dist; - index = indexWordHi( size_words ); - lastIndex = indexWordLo( size_words ); - partWordZ = aPtr[index]<>(uNegDist & 31); - index -= wordIncr; - partWordZ = wordA< -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shortShiftRight128 - -struct uint128 - softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist ) -{ - struct uint128 z; - - z.v64 = a64>>dist; - z.v0 = a64<<(-dist & 63) | a0>>dist; - return z; - -} - -#endif - diff --git a/softfloat/source/s_shortShiftRightExtendM.c b/softfloat/source/s_shortShiftRightExtendM.c deleted file mode 100644 index bc441c7..0000000 --- a/softfloat/source/s_shortShiftRightExtendM.c +++ /dev/null @@ -1,73 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shortShiftRightExtendM - -void - softfloat_shortShiftRightExtendM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint_fast8_t dist, - uint32_t *zPtr - ) -{ - uint_fast8_t uNegDist; - unsigned int indexA, lastIndexA; - uint32_t partWordZ, wordA; - - uNegDist = -dist; - indexA = indexWordLo( size_words ); - lastIndexA = indexWordHi( size_words ); - zPtr += indexWordLo( size_words + 1 ); - partWordZ = 0; - for (;;) { - wordA = aPtr[indexA]; - *zPtr = wordA<<(uNegDist & 31) | partWordZ; - zPtr += wordIncr; - partWordZ = wordA>>dist; - if ( indexA == lastIndexA ) break; - indexA += wordIncr; - } - *zPtr = partWordZ; - -} - -#endif - diff --git a/softfloat/source/s_shortShiftRightJam128.c b/softfloat/source/s_shortShiftRightJam128.c deleted file mode 100644 index 7600872..0000000 --- a/softfloat/source/s_shortShiftRightJam128.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shortShiftRightJam128 - -struct uint128 - softfloat_shortShiftRightJam128( - uint64_t a64, uint64_t a0, uint_fast8_t dist ) -{ - uint_fast8_t uNegDist; - struct uint128 z; - - uNegDist = -dist; - z.v64 = a64>>dist; - z.v0 = - a64<<(uNegDist & 63) | a0>>dist - | ((uint64_t) (a0<<(uNegDist & 63)) != 0); - return z; - -} - -#endif - diff --git a/softfloat/source/s_shortShiftRightJam128Extra.c b/softfloat/source/s_shortShiftRightJam128Extra.c deleted file mode 100644 index b077440..0000000 --- a/softfloat/source/s_shortShiftRightJam128Extra.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shortShiftRightJam128Extra - -struct uint128_extra - softfloat_shortShiftRightJam128Extra( - uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist ) -{ - uint_fast8_t uNegDist; - struct uint128_extra z; - - uNegDist = -dist; - z.v.v64 = a64>>dist; - z.v.v0 = a64<<(uNegDist & 63) | a0>>dist; - z.extra = a0<<(uNegDist & 63) | (extra != 0); - return z; - -} - -#endif - diff --git a/softfloat/source/s_shortShiftRightJam64.c b/softfloat/source/s_shortShiftRightJam64.c deleted file mode 100644 index d3044c8..0000000 --- a/softfloat/source/s_shortShiftRightJam64.c +++ /dev/null @@ -1,50 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" - -#ifndef softfloat_shortShiftRightJam64 - -uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist ) -{ - - return a>>dist | ((a & (((uint_fast64_t) 1< -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shortShiftRightJam64Extra - -struct uint64_extra - softfloat_shortShiftRightJam64Extra( - uint64_t a, uint64_t extra, uint_fast8_t dist ) -{ - struct uint64_extra z; - - z.v = a>>dist; - z.extra = a<<(-dist & 63) | (extra != 0); - return z; - -} - -#endif - diff --git a/softfloat/source/s_shortShiftRightJamM.c b/softfloat/source/s_shortShiftRightJamM.c deleted file mode 100644 index b567e48..0000000 --- a/softfloat/source/s_shortShiftRightJamM.c +++ /dev/null @@ -1,72 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shortShiftRightJamM - -void - softfloat_shortShiftRightJamM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint_fast8_t dist, - uint32_t *zPtr - ) -{ - uint_fast8_t uNegDist; - unsigned int index, lastIndex; - uint32_t partWordZ, wordA; - - uNegDist = -dist; - index = indexWordLo( size_words ); - lastIndex = indexWordHi( size_words ); - wordA = aPtr[index]; - partWordZ = wordA>>dist; - if ( partWordZ<>dist; - } - zPtr[index] = partWordZ; - -} - -#endif - diff --git a/softfloat/source/s_shortShiftRightM.c b/softfloat/source/s_shortShiftRightM.c deleted file mode 100644 index 54e0071..0000000 --- a/softfloat/source/s_shortShiftRightM.c +++ /dev/null @@ -1,70 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_shortShiftRightM - -void - softfloat_shortShiftRightM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint_fast8_t dist, - uint32_t *zPtr - ) -{ - uint_fast8_t uNegDist; - unsigned int index, lastIndex; - uint32_t partWordZ, wordA; - - uNegDist = -dist; - index = indexWordLo( size_words ); - lastIndex = indexWordHi( size_words ); - partWordZ = aPtr[index]>>dist; - while ( index != lastIndex ) { - wordA = aPtr[index + wordIncr]; - zPtr[index] = wordA<<(uNegDist & 31) | partWordZ; - index += wordIncr; - partWordZ = wordA>>dist; - } - zPtr[index] = partWordZ; - -} - -#endif - diff --git a/softfloat/source/s_sub128.c b/softfloat/source/s_sub128.c deleted file mode 100644 index 9bf3463..0000000 --- a/softfloat/source/s_sub128.c +++ /dev/null @@ -1,55 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_sub128 - -struct uint128 - softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) -{ - struct uint128 z; - - z.v0 = a0 - b0; - z.v64 = a64 - b64 - (a0 < b0); - return z; - -} - -#endif - diff --git a/softfloat/source/s_sub1XM.c b/softfloat/source/s_sub1XM.c deleted file mode 100644 index 30c5d36..0000000 --- a/softfloat/source/s_sub1XM.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_sub1XM - -void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr ) -{ - unsigned int index, lastIndex; - uint32_t wordA; - - index = indexWordLo( size_words ); - lastIndex = indexWordHi( size_words ); - for (;;) { - wordA = zPtr[index]; - zPtr[index] = wordA - 1; - if ( wordA || (index == lastIndex) ) break; - index += wordIncr; - } - -} - -#endif - diff --git a/softfloat/source/s_sub256M.c b/softfloat/source/s_sub256M.c deleted file mode 100644 index a4af5a1..0000000 --- a/softfloat/source/s_sub256M.c +++ /dev/null @@ -1,65 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_sub256M - -void - softfloat_sub256M( - const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr ) -{ - unsigned int index; - uint_fast8_t borrow; - uint64_t wordA, wordB; - - index = indexWordLo( 4 ); - borrow = 0; - for (;;) { - wordA = aPtr[index]; - wordB = bPtr[index]; - zPtr[index] = wordA - wordB - borrow; - if ( index == indexWordHi( 4 ) ) break; - borrow = borrow ? (wordA <= wordB) : (wordA < wordB); - index += wordIncr; - } - -} - -#endif - diff --git a/softfloat/source/s_subM.c b/softfloat/source/s_subM.c deleted file mode 100644 index fcccc74..0000000 --- a/softfloat/source/s_subM.c +++ /dev/null @@ -1,70 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "primitiveTypes.h" - -#ifndef softfloat_subM - -void - softfloat_subM( - uint_fast8_t size_words, - const uint32_t *aPtr, - const uint32_t *bPtr, - uint32_t *zPtr - ) -{ - unsigned int index, lastIndex; - uint_fast8_t borrow; - uint32_t wordA, wordB; - - index = indexWordLo( size_words ); - lastIndex = indexWordHi( size_words ); - borrow = 0; - for (;;) { - wordA = aPtr[index]; - wordB = bPtr[index]; - zPtr[index] = wordA - wordB - borrow; - if ( index == lastIndex ) break; - borrow = borrow ? (wordA <= wordB) : (wordA < wordB); - index += wordIncr; - } - -} - -#endif - diff --git a/softfloat/source/s_subMagsExtF80.c b/softfloat/source/s_subMagsExtF80.c deleted file mode 100644 index 0c46c61..0000000 --- a/softfloat/source/s_subMagsExtF80.c +++ /dev/null @@ -1,158 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -extFloat80_t - softfloat_subMagsExtF80( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0, - bool signZ - ) -{ - int_fast32_t expA; - uint_fast64_t sigA; - int_fast32_t expB; - uint_fast64_t sigB; - int_fast32_t expDiff; - uint_fast16_t uiZ64; - uint_fast64_t uiZ0; - int_fast32_t expZ; - uint_fast64_t sigExtra; - struct uint128 sig128, uiZ; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = expExtF80UI64( uiA64 ); - sigA = uiA0; - expB = expExtF80UI64( uiB64 ); - sigB = uiB0; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( 0 < expDiff ) goto expABigger; - if ( expDiff < 0 ) goto expBBigger; - if ( expA == 0x7FFF ) { - if ( (sigA | sigB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) { - goto propagateNaN; - } - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ64 = defaultNaNExtF80UI64; - uiZ0 = defaultNaNExtF80UI0; - goto uiZ; - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expZ = expA; - if ( ! expZ ) expZ = 1; - sigExtra = 0; - if ( sigB < sigA ) goto aBigger; - if ( sigA < sigB ) goto bBigger; - uiZ64 = - packToExtF80UI64( (softfloat_roundingMode == softfloat_round_min), 0 ); - uiZ0 = 0; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expBBigger: - if ( expB == 0x7FFF ) { - if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN; - uiZ64 = packToExtF80UI64( signZ ^ 1, 0x7FFF ); - uiZ0 = UINT64_C( 0x8000000000000000 ); - goto uiZ; - } - if ( ! expA ) { - ++expDiff; - sigExtra = 0; - if ( ! expDiff ) goto newlyAlignedBBigger; - } - sig128 = softfloat_shiftRightJam128( sigA, 0, -expDiff ); - sigA = sig128.v64; - sigExtra = sig128.v0; - newlyAlignedBBigger: - expZ = expB; - bBigger: - signZ = ! signZ; - sig128 = softfloat_sub128( sigB, 0, sigA, sigExtra ); - goto normRoundPack; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expABigger: - if ( expA == 0x7FFF ) { - if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN; - uiZ64 = uiA64; - uiZ0 = uiA0; - goto uiZ; - } - if ( ! expB ) { - --expDiff; - sigExtra = 0; - if ( ! expDiff ) goto newlyAlignedABigger; - } - sig128 = softfloat_shiftRightJam128( sigB, 0, expDiff ); - sigB = sig128.v64; - sigExtra = sig128.v0; - newlyAlignedABigger: - expZ = expA; - aBigger: - sig128 = softfloat_sub128( sigA, 0, sigB, sigExtra ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - normRoundPack: - return - softfloat_normRoundPackToExtF80( - signZ, expZ, sig128.v64, sig128.v0, extF80_roundingPrecision ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 ); - uiZ64 = uiZ.v64; - uiZ0 = uiZ.v0; - uiZ: - uZ.s.signExp = uiZ64; - uZ.s.signif = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/s_subMagsF128.c b/softfloat/source/s_subMagsF128.c deleted file mode 100644 index e93543f..0000000 --- a/softfloat/source/s_subMagsF128.c +++ /dev/null @@ -1,139 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float128_t - softfloat_subMagsF128( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0, - bool signZ - ) -{ - int_fast32_t expA; - struct uint128 sigA; - int_fast32_t expB; - struct uint128 sigB, sigZ; - int_fast32_t expDiff, expZ; - struct uint128 uiZ; - union ui128_f128 uZ; - - expA = expF128UI64( uiA64 ); - sigA.v64 = fracF128UI64( uiA64 ); - sigA.v0 = uiA0; - expB = expF128UI64( uiB64 ); - sigB.v64 = fracF128UI64( uiB64 ); - sigB.v0 = uiB0; - sigA = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 4 ); - sigB = softfloat_shortShiftLeft128( sigB.v64, sigB.v0, 4 ); - expDiff = expA - expB; - if ( 0 < expDiff ) goto expABigger; - if ( expDiff < 0 ) goto expBBigger; - if ( expA == 0x7FFF ) { - if ( sigA.v64 | sigA.v0 | sigB.v64 | sigB.v0 ) goto propagateNaN; - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; - goto uiZ; - } - expZ = expA; - if ( ! expZ ) expZ = 1; - if ( sigB.v64 < sigA.v64 ) goto aBigger; - if ( sigA.v64 < sigB.v64 ) goto bBigger; - if ( sigB.v0 < sigA.v0 ) goto aBigger; - if ( sigA.v0 < sigB.v0 ) goto bBigger; - uiZ.v64 = - packToF128UI64( - (softfloat_roundingMode == softfloat_round_min), 0, 0 ); - uiZ.v0 = 0; - goto uiZ; - expBBigger: - if ( expB == 0x7FFF ) { - if ( sigB.v64 | sigB.v0 ) goto propagateNaN; - uiZ.v64 = packToF128UI64( signZ ^ 1, 0x7FFF, 0 ); - uiZ.v0 = 0; - goto uiZ; - } - if ( expA ) { - sigA.v64 |= UINT64_C( 0x0010000000000000 ); - } else { - ++expDiff; - if ( ! expDiff ) goto newlyAlignedBBigger; - } - sigA = softfloat_shiftRightJam128( sigA.v64, sigA.v0, -expDiff ); - newlyAlignedBBigger: - expZ = expB; - sigB.v64 |= UINT64_C( 0x0010000000000000 ); - bBigger: - signZ = ! signZ; - sigZ = softfloat_sub128( sigB.v64, sigB.v0, sigA.v64, sigA.v0 ); - goto normRoundPack; - expABigger: - if ( expA == 0x7FFF ) { - if ( sigA.v64 | sigA.v0 ) goto propagateNaN; - uiZ.v64 = uiA64; - uiZ.v0 = uiA0; - goto uiZ; - } - if ( expB ) { - sigB.v64 |= UINT64_C( 0x0010000000000000 ); - } else { - --expDiff; - if ( ! expDiff ) goto newlyAlignedABigger; - } - sigB = softfloat_shiftRightJam128( sigB.v64, sigB.v0, expDiff ); - newlyAlignedABigger: - expZ = expA; - sigA.v64 |= UINT64_C( 0x0010000000000000 ); - aBigger: - sigZ = softfloat_sub128( sigA.v64, sigA.v0, sigB.v64, sigB.v0 ); - normRoundPack: - return softfloat_normRoundPackToF128( signZ, expZ - 5, sigZ.v64, sigZ.v0 ); - propagateNaN: - uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_subMagsF16.c b/softfloat/source/s_subMagsF16.c deleted file mode 100644 index ae1417e..0000000 --- a/softfloat/source/s_subMagsF16.c +++ /dev/null @@ -1,187 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float16_t softfloat_subMagsF16( uint_fast16_t uiA, uint_fast16_t uiB ) -{ - int_fast8_t expA; - uint_fast16_t sigA; - int_fast8_t expB; - uint_fast16_t sigB; - int_fast8_t expDiff; - uint_fast16_t uiZ; - int_fast16_t sigDiff; - bool signZ; - int_fast8_t shiftDist, expZ; - uint_fast16_t sigZ, sigX, sigY; - uint_fast32_t sig32Z; - int_fast8_t roundingMode; - union ui16_f16 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = expF16UI( uiA ); - sigA = fracF16UI( uiA ); - expB = expF16UI( uiB ); - sigB = fracF16UI( uiB ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( ! expDiff ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expA == 0x1F ) { - if ( sigA | sigB ) goto propagateNaN; - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF16UI; - goto uiZ; - } - sigDiff = sigA - sigB; - if ( ! sigDiff ) { - uiZ = - packToF16UI( - (softfloat_roundingMode == softfloat_round_min), 0, 0 ); - goto uiZ; - } - if ( expA ) --expA; - signZ = signF16UI( uiA ); - if ( sigDiff < 0 ) { - signZ = ! signZ; - sigDiff = -sigDiff; - } - shiftDist = softfloat_countLeadingZeros16( sigDiff ) - 5; - expZ = expA - shiftDist; - if ( expZ < 0 ) { - shiftDist = expA; - expZ = 0; - } - sigZ = sigDiff<>16; - if ( sig32Z & 0xFFFF ) { - sigZ |= 1; - } else { - if ( ! (sigZ & 0xF) && ((unsigned int) expZ < 0x1E) ) { - sigZ >>= 4; - goto pack; - } - } - return softfloat_roundPackToF16( signZ, expZ, sigZ ); - } - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - propagateNaN: - uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - subEpsilon: - roundingMode = softfloat_roundingMode; - if ( roundingMode != softfloat_round_near_even ) { - if ( - (roundingMode == softfloat_round_minMag) - || (roundingMode - == (signF16UI( uiZ ) ? softfloat_round_max - : softfloat_round_min)) - ) { - --uiZ; - } -#ifdef SOFTFLOAT_ROUND_ODD - else if ( roundingMode == softfloat_round_odd ) { - uiZ = (uiZ - 1) | 1; - } -#endif - } - softfloat_exceptionFlags |= softfloat_flag_inexact; - goto uiZ; - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - pack: - uiZ = packToF16UI( signZ, expZ, sigZ ); - uiZ: - uZ.ui = uiZ; - return uZ.f; - -} - diff --git a/softfloat/source/s_subMagsF32.c b/softfloat/source/s_subMagsF32.c deleted file mode 100644 index 0c1f32e..0000000 --- a/softfloat/source/s_subMagsF32.c +++ /dev/null @@ -1,143 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float32_t softfloat_subMagsF32( uint_fast32_t uiA, uint_fast32_t uiB ) -{ - int_fast16_t expA; - uint_fast32_t sigA; - int_fast16_t expB; - uint_fast32_t sigB; - int_fast16_t expDiff; - uint_fast32_t uiZ; - int_fast32_t sigDiff; - bool signZ; - int_fast8_t shiftDist; - int_fast16_t expZ; - uint_fast32_t sigX, sigY; - union ui32_f32 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = expF32UI( uiA ); - sigA = fracF32UI( uiA ); - expB = expF32UI( uiB ); - sigB = fracF32UI( uiB ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( ! expDiff ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expA == 0xFF ) { - if ( sigA | sigB ) goto propagateNaN; - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF32UI; - goto uiZ; - } - sigDiff = sigA - sigB; - if ( ! sigDiff ) { - uiZ = - packToF32UI( - (softfloat_roundingMode == softfloat_round_min), 0, 0 ); - goto uiZ; - } - if ( expA ) --expA; - signZ = signF32UI( uiA ); - if ( sigDiff < 0 ) { - signZ = ! signZ; - sigDiff = -sigDiff; - } - shiftDist = softfloat_countLeadingZeros32( sigDiff ) - 8; - expZ = expA - shiftDist; - if ( expZ < 0 ) { - shiftDist = expA; - expZ = 0; - } - uiZ = packToF32UI( signZ, expZ, sigDiff< -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -float64_t - softfloat_subMagsF64( uint_fast64_t uiA, uint_fast64_t uiB, bool signZ ) -{ - int_fast16_t expA; - uint_fast64_t sigA; - int_fast16_t expB; - uint_fast64_t sigB; - int_fast16_t expDiff; - uint_fast64_t uiZ; - int_fast64_t sigDiff; - int_fast8_t shiftDist; - int_fast16_t expZ; - uint_fast64_t sigZ; - union ui64_f64 uZ; - - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expA = expF64UI( uiA ); - sigA = fracF64UI( uiA ); - expB = expF64UI( uiB ); - sigB = fracF64UI( uiB ); - /*------------------------------------------------------------------------ - *------------------------------------------------------------------------*/ - expDiff = expA - expB; - if ( ! expDiff ) { - /*-------------------------------------------------------------------- - *--------------------------------------------------------------------*/ - if ( expA == 0x7FF ) { - if ( sigA | sigB ) goto propagateNaN; - softfloat_raiseFlags( softfloat_flag_invalid ); - uiZ = defaultNaNF64UI; - goto uiZ; - } - sigDiff = sigA - sigB; - if ( ! sigDiff ) { - uiZ = - packToF64UI( - (softfloat_roundingMode == softfloat_round_min), 0, 0 ); - goto uiZ; - } - if ( expA ) --expA; - if ( sigDiff < 0 ) { - signZ = ! signZ; - sigDiff = -sigDiff; - } - shiftDist = softfloat_countLeadingZeros64( sigDiff ) - 11; - expZ = expA - shiftDist; - if ( expZ < 0 ) { - shiftDist = expA; - expZ = 0; - } - uiZ = packToF64UI( signZ, expZ, sigDiff< -#include "platform.h" -#include "internals.h" -#include "specialize.h" - -bool - softfloat_tryPropagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ) -{ - uint_fast16_t ui64; - uint64_t ui0; - - ui64 = aSPtr->signExp; - ui0 = aSPtr->signif; - if ( isNaNExtF80UI( ui64, ui0 ) ) goto propagateNaN; - ui64 = bSPtr->signExp; - ui0 = bSPtr->signif; - if ( isNaNExtF80UI( ui64, ui0 ) ) goto propagateNaN; - return false; - propagateNaN: - softfloat_propagateNaNExtF80M( aSPtr, bSPtr, zSPtr ); - return true; - -} - diff --git a/softfloat/source/s_tryPropagateNaNF128M.c b/softfloat/source/s_tryPropagateNaNF128M.c deleted file mode 100644 index bab04a7..0000000 --- a/softfloat/source/s_tryPropagateNaNF128M.c +++ /dev/null @@ -1,55 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" - -bool - softfloat_tryPropagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ) -{ - - if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) { - softfloat_propagateNaNF128M( aWPtr, bWPtr, zWPtr ); - return true; - } - return false; - -} - diff --git a/softfloat/source/softfloat_state.c b/softfloat/source/softfloat_state.c deleted file mode 100644 index 0f29665..0000000 --- a/softfloat/source/softfloat_state.c +++ /dev/null @@ -1,52 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -#ifndef THREAD_LOCAL -#define THREAD_LOCAL -#endif - -THREAD_LOCAL uint_fast8_t softfloat_roundingMode = softfloat_round_near_even; -THREAD_LOCAL uint_fast8_t softfloat_detectTininess = init_detectTininess; -THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags = 0; - -THREAD_LOCAL uint_fast8_t extF80_roundingPrecision = 80; - diff --git a/softfloat/source/ui32_to_extF80.c b/softfloat/source/ui32_to_extF80.c deleted file mode 100644 index 34f7936..0000000 --- a/softfloat/source/ui32_to_extF80.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -extFloat80_t ui32_to_extF80( uint32_t a ) -{ - uint_fast16_t uiZ64; - int_fast8_t shiftDist; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - uiZ64 = 0; - if ( a ) { - shiftDist = softfloat_countLeadingZeros32( a ); - uiZ64 = 0x401E - shiftDist; - a <<= shiftDist; - } - uZ.s.signExp = uiZ64; - uZ.s.signif = (uint_fast64_t) a<<32; - return uZ.f; - -} - diff --git a/softfloat/source/ui32_to_extF80M.c b/softfloat/source/ui32_to_extF80M.c deleted file mode 100644 index 0a0c098..0000000 --- a/softfloat/source/ui32_to_extF80M.c +++ /dev/null @@ -1,74 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void ui32_to_extF80M( uint32_t a, extFloat80_t *zPtr ) -{ - - *zPtr = ui32_to_extF80( a ); - -} - -#else - -void ui32_to_extF80M( uint32_t a, extFloat80_t *zPtr ) -{ - struct extFloat80M *zSPtr; - uint_fast16_t uiZ64; - uint64_t sigZ; - int_fast8_t shiftDist; - - zSPtr = (struct extFloat80M *) zPtr; - uiZ64 = 0; - sigZ = 0; - if ( a ) { - shiftDist = softfloat_countLeadingZeros32( a ); - uiZ64 = packToExtF80UI64( 0, 0x401E - shiftDist ); - sigZ = (uint64_t) (a<signExp = uiZ64; - zSPtr->signif = sigZ; - -} - -#endif - diff --git a/softfloat/source/ui32_to_f128.c b/softfloat/source/ui32_to_f128.c deleted file mode 100644 index c3ab53d..0000000 --- a/softfloat/source/ui32_to_f128.c +++ /dev/null @@ -1,60 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float128_t ui32_to_f128( uint32_t a ) -{ - uint_fast64_t uiZ64; - int_fast8_t shiftDist; - union ui128_f128 uZ; - - uiZ64 = 0; - if ( a ) { - shiftDist = softfloat_countLeadingZeros32( a ) + 17; - uiZ64 = - packToF128UI64( - 0, 0x402E - shiftDist, (uint_fast64_t) a< -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void ui32_to_f128M( uint32_t a, float128_t *zPtr ) -{ - - *zPtr = ui32_to_f128( a ); - -} - -#else - -void ui32_to_f128M( uint32_t a, float128_t *zPtr ) -{ - uint32_t *zWPtr, uiZ96, uiZ64; - int_fast8_t shiftDist; - uint64_t normA; - - zWPtr = (uint32_t *) zPtr; - uiZ96 = 0; - uiZ64 = 0; - if ( a ) { - shiftDist = softfloat_countLeadingZeros32( a ) + 17; - normA = (uint64_t) a<>32 ); - uiZ64 = normA; - } - zWPtr[indexWord( 4, 3 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = uiZ64; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - -} - -#endif - diff --git a/softfloat/source/ui32_to_f16.c b/softfloat/source/ui32_to_f16.c deleted file mode 100644 index 6fc377b..0000000 --- a/softfloat/source/ui32_to_f16.c +++ /dev/null @@ -1,65 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float16_t ui32_to_f16( uint32_t a ) -{ - int_fast8_t shiftDist; - union ui16_f16 u; - uint_fast16_t sig; - - shiftDist = softfloat_countLeadingZeros32( a ) - 21; - if ( 0 <= shiftDist ) { - u.ui = - a ? packToF16UI( - 0, 0x18 - shiftDist, (uint_fast16_t) a<>(-shiftDist) | ((uint32_t) (a<<(shiftDist & 31)) != 0) - : (uint_fast16_t) a< -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float32_t ui32_to_f32( uint32_t a ) -{ - union ui32_f32 uZ; - - if ( ! a ) { - uZ.ui = 0; - return uZ.f; - } - if ( a & 0x80000000 ) { - return softfloat_roundPackToF32( 0, 0x9D, a>>1 | (a & 1) ); - } else { - return softfloat_normRoundPackToF32( 0, 0x9C, a ); - } - -} - diff --git a/softfloat/source/ui32_to_f64.c b/softfloat/source/ui32_to_f64.c deleted file mode 100644 index 504f96e..0000000 --- a/softfloat/source/ui32_to_f64.c +++ /dev/null @@ -1,59 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float64_t ui32_to_f64( uint32_t a ) -{ - uint_fast64_t uiZ; - int_fast8_t shiftDist; - union ui64_f64 uZ; - - if ( ! a ) { - uiZ = 0; - } else { - shiftDist = softfloat_countLeadingZeros32( a ) + 21; - uiZ = - packToF64UI( 0, 0x432 - shiftDist, (uint_fast64_t) a< -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -extFloat80_t ui64_to_extF80( uint64_t a ) -{ - uint_fast16_t uiZ64; - int_fast8_t shiftDist; - union { struct extFloat80M s; extFloat80_t f; } uZ; - - uiZ64 = 0; - if ( a ) { - shiftDist = softfloat_countLeadingZeros64( a ); - uiZ64 = 0x403E - shiftDist; - a <<= shiftDist; - } - uZ.s.signExp = uiZ64; - uZ.s.signif = a; - return uZ.f; - -} - diff --git a/softfloat/source/ui64_to_extF80M.c b/softfloat/source/ui64_to_extF80M.c deleted file mode 100644 index e676d90..0000000 --- a/softfloat/source/ui64_to_extF80M.c +++ /dev/null @@ -1,74 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void ui64_to_extF80M( uint64_t a, extFloat80_t *zPtr ) -{ - - *zPtr = ui64_to_extF80( a ); - -} - -#else - -void ui64_to_extF80M( uint64_t a, extFloat80_t *zPtr ) -{ - struct extFloat80M *zSPtr; - uint_fast16_t uiZ64; - uint64_t sigZ; - int_fast8_t shiftDist; - - zSPtr = (struct extFloat80M *) zPtr; - uiZ64 = 0; - sigZ = 0; - if ( a ) { - shiftDist = softfloat_countLeadingZeros64( a ); - uiZ64 = packToExtF80UI64( 0, 0x403E - shiftDist ); - sigZ = a<signExp = uiZ64; - zSPtr->signif = sigZ; - -} - -#endif - diff --git a/softfloat/source/ui64_to_f128.c b/softfloat/source/ui64_to_f128.c deleted file mode 100644 index 6ff6a6f..0000000 --- a/softfloat/source/ui64_to_f128.c +++ /dev/null @@ -1,68 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float128_t ui64_to_f128( uint64_t a ) -{ - uint_fast64_t uiZ64, uiZ0; - int_fast8_t shiftDist; - struct uint128 zSig; - union ui128_f128 uZ; - - if ( ! a ) { - uiZ64 = 0; - uiZ0 = 0; - } else { - shiftDist = softfloat_countLeadingZeros64( a ) + 49; - if ( 64 <= shiftDist ) { - zSig.v64 = a<<(shiftDist - 64); - zSig.v0 = 0; - } else { - zSig = softfloat_shortShiftLeft128( 0, a, shiftDist ); - } - uiZ64 = packToF128UI64( 0, 0x406E - shiftDist, zSig.v64 ); - uiZ0 = zSig.v0; - } - uZ.ui.v64 = uiZ64; - uZ.ui.v0 = uiZ0; - return uZ.f; - -} - diff --git a/softfloat/source/ui64_to_f128M.c b/softfloat/source/ui64_to_f128M.c deleted file mode 100644 index 043406c..0000000 --- a/softfloat/source/ui64_to_f128M.c +++ /dev/null @@ -1,86 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -#ifdef SOFTFLOAT_FAST_INT64 - -void ui64_to_f128M( uint64_t a, float128_t *zPtr ) -{ - - *zPtr = ui64_to_f128( a ); - -} - -#else - -void ui64_to_f128M( uint64_t a, float128_t *zPtr ) -{ - uint32_t *zWPtr, uiZ96, uiZ64; - uint_fast8_t shiftDist; - uint32_t *ptr; - - zWPtr = (uint32_t *) zPtr; - uiZ96 = 0; - uiZ64 = 0; - zWPtr[indexWord( 4, 1 )] = 0; - zWPtr[indexWord( 4, 0 )] = 0; - if ( a ) { - shiftDist = softfloat_countLeadingZeros64( a ) + 17; - if ( shiftDist < 32 ) { - ptr = zWPtr + indexMultiwordHi( 4, 3 ); - ptr[indexWord( 3, 2 )] = 0; - ptr[indexWord( 3, 1 )] = a>>32; - ptr[indexWord( 3, 0 )] = a; - softfloat_shortShiftLeft96M( ptr, shiftDist, ptr ); - ptr[indexWordHi( 3 )] = - packToF128UI96( 0, 0x404E - shiftDist, ptr[indexWordHi( 3 )] ); - return; - } - a <<= shiftDist - 32; - uiZ96 = packToF128UI96( 0, 0x404E - shiftDist, a>>32 ); - uiZ64 = a; - } - zWPtr[indexWord( 4, 3 )] = uiZ96; - zWPtr[indexWord( 4, 2 )] = uiZ64; - -} - -#endif - diff --git a/softfloat/source/ui64_to_f16.c b/softfloat/source/ui64_to_f16.c deleted file mode 100644 index 3d58e85..0000000 --- a/softfloat/source/ui64_to_f16.c +++ /dev/null @@ -1,64 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3e, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float16_t ui64_to_f16( uint64_t a ) -{ - int_fast8_t shiftDist; - union ui16_f16 u; - uint_fast16_t sig; - - shiftDist = softfloat_countLeadingZeros64( a ) - 53; - if ( 0 <= shiftDist ) { - u.ui = - a ? packToF16UI( - 0, 0x18 - shiftDist, (uint_fast16_t) a< -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float32_t ui64_to_f32( uint64_t a ) -{ - int_fast8_t shiftDist; - union ui32_f32 u; - uint_fast32_t sig; - - shiftDist = softfloat_countLeadingZeros64( a ) - 40; - if ( 0 <= shiftDist ) { - u.ui = - a ? packToF32UI( - 0, 0x95 - shiftDist, (uint_fast32_t) a< -#include "platform.h" -#include "internals.h" -#include "softfloat.h" - -float64_t ui64_to_f64( uint64_t a ) -{ - union ui64_f64 uZ; - - if ( ! a ) { - uZ.ui = 0; - return uZ.f; - } - if ( a & UINT64_C( 0x8000000000000000 ) ) { - return - softfloat_roundPackToF64( - 0, 0x43D, softfloat_shortShiftRightJam64( a, 1 ) ); - } else { - return softfloat_normRoundPackToF64( 0, 0x43C, a ); - } - -} - diff --git a/softvector b/softvector index f0f7cfb..ce60b58 160000 --- a/softvector +++ b/softvector @@ -1 +1 @@ -Subproject commit f0f7cfbb20adf67bbe5e3688051dab1cd7320be1 +Subproject commit ce60b58dd0548906fb0d7053c622cf6c881b0300 diff --git a/src/vm/aes_sbox.h b/src/vm/aes_sbox.h deleted file mode 100644 index 00b0b19..0000000 --- a/src/vm/aes_sbox.h +++ /dev/null @@ -1,70 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2025, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -// Contributors: -// ales@minres.com - initial API and implementation -//////////////////////////////////////////////////////////////////////////////// - -#ifndef _VM_AES_SBOX_H_ -#define _VM_AES_SBOX_H_ -#include -extern "C" { -const uint8_t AES_ENC_SBOX[] = { - 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, - 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, - 0x71, 0xD8, 0x31, 0x15, 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75, 0x09, 0x83, - 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, - 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF, 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, - 0x9F, 0xA8, 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, 0xCD, 0x0C, 0x13, 0xEC, - 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73, 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, - 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB, 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, - 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08, 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, - 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A, 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, - 0x86, 0xC1, 0x1D, 0x9E, 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF, 0x8C, 0xA1, - 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16}; -uint8_t inline aes_sbox_fwd(uint8_t index) { return AES_ENC_SBOX[index]; } - -const uint8_t AES_DEC_SBOX[] = { - 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB, 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, - 0xFF, 0x87, 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB, 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D, 0xEE, 0x4C, 0x95, 0x0B, - 0x42, 0xFA, 0xC3, 0x4E, 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25, 0x72, 0xF8, - 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92, 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA, - 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84, 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A, 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, - 0x45, 0x06, 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02, 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B, 0x3A, 0x91, 0x11, 0x41, - 0x4F, 0x67, 0xDC, 0xEA, 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73, 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85, 0xE2, 0xF9, - 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E, 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89, 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B, - 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20, 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4, 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, - 0xC7, 0x31, 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F, 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D, 0x2D, 0xE5, 0x7A, 0x9F, - 0x93, 0xC9, 0x9C, 0xEF, 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2B, - 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D}; -uint8_t inline aes_sbox_inv(uint8_t index) { return AES_DEC_SBOX[index]; } -} - -#endif /* _VM_AES_SBOX_H_ */ From e97f303b6312339eeb8d169a9638c9fc6b6771ec Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 25 Sep 2025 10:05:43 +0200 Subject: [PATCH 022/230] silences semihosting build warning --- src/iss/semihosting/semihosting.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/iss/semihosting/semihosting.cpp b/src/iss/semihosting/semihosting.cpp index 75b4ecc..21fe0c4 100644 --- a/src/iss/semihosting/semihosting.cpp +++ b/src/iss/semihosting/semihosting.cpp @@ -250,7 +250,7 @@ template void semihosting_callback::operator()(iss::arch_if* arc T cmd_addr = sh_read_field(arch_if_ptr, *parameter); T cmd_len = sh_read_field(arch_if_ptr, (*parameter) + 1); std::string cmd = sh_read_string(arch_if_ptr, cmd_addr, cmd_len); - system(cmd.c_str()); + auto _ = system(cmd.c_str()); break; } case semihosting_syscalls::SYS_TICKFREQ: { From fe2c7acda09f17560c9f8e77d6b4d2fdbda96439 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 25 Sep 2025 19:25:28 +0200 Subject: [PATCH 023/230] removes aes include for sbox const array as it is now part of CoreDSL --- gen_input/templates/CORENAME.h.gtl | 6 ++++++ gen_input/templates/asmjit/CORENAME.cpp.gtl | 5 +---- gen_input/templates/interp/CORENAME.cpp.gtl | 5 +---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl index 9b2bdb0..475352b 100644 --- a/gen_input/templates/CORENAME.h.gtl +++ b/gen_input/templates/CORENAME.h.gtl @@ -152,6 +152,12 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { ${constants.collect{c -> c.name+"="+getCString(c.value)}.collate(4).collect { it.join(', ') }.join(',\n ')} }; + <% for (array in const_arrays) { %> + static constexpr std::array<${array.clangValueType}, ${array.dimension}> ${array.name} = { + {${array.values.join(", ")}} + }; + + <% } %> constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0}; constexpr static unsigned V_REGS_SIZE = ${constants.find {it.name=='VLEN'}?.value?:0}; diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index e558bb8..61035df 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -32,7 +32,6 @@ <% def floating_point = registers.find {it.name=='FCSR'} != null def vector = registers.find {it.name=='vtype'} != null -def aes = functions.find { it.contains('aes') } != null def nativeTypeSize(int size){ if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64; } @@ -52,10 +51,8 @@ if(floating_point) {%> <%} if(vector){%> #include -<%} -if(aes) {%> -#include <%}%> + #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 00d5f0c..ca76232 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -32,7 +32,6 @@ <% def floating_point = registers.find {it.name=='FCSR'} != null def vector = registers.find {it.name=='vtype'} != null -def aes = functions.find { it.contains('aes') } != null def nativeTypeSize(int size){ if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64; } @@ -50,10 +49,8 @@ if(floating_point) {%> <%} if(vector) {%> #include -<%} -if(aes) {%> -#include <%}%> + #include #include #include From ce33d36dea497c5c0a8086f70c4bfbe99e47b71f Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 25 Sep 2025 19:27:33 +0200 Subject: [PATCH 024/230] updates ISA submodule --- gen_input/ISA | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gen_input/ISA b/gen_input/ISA index 34eef99..c0d5707 160000 --- a/gen_input/ISA +++ b/gen_input/ISA @@ -1 +1 @@ -Subproject commit 34eef9992295d9fbe2bdf9a5abdf8747e18dd54a +Subproject commit c0d570783c2c36080195496e6bcf5c64e9960601 From b6ef70da0b197759cefe0f5089df316bb908864b Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Fri, 26 Sep 2025 20:58:03 +0200 Subject: [PATCH 025/230] adds cryptofunctions --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 4 ++ gen_input/templates/interp/CORENAME.cpp.gtl | 4 ++ softvector | 2 +- src/vm/vector_functions.h | 63 +++++++++++++++++++++ 4 files changed, 72 insertions(+), 1 deletion(-) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 61035df..ffb1b99 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -160,6 +160,10 @@ public: static constexpr auto& fp_vector_unary_w = softvec_if::fp_vector_unary_w; static constexpr auto& fp_vector_unary_n = softvec_if::fp_vector_unary_n; static constexpr auto& vector_unary_op = softvec_if::vector_unary_op; + static constexpr auto& vector_vector_crypto = softvec_if::vector_vector_crypto; + static constexpr auto& vector_scalar_crypto = softvec_if::vector_scalar_crypto; + static constexpr auto& vector_imm_crypto = softvec_if::vector_imm_crypto; + static constexpr auto& vector_crypto = softvec_if::vector_crypto; <%}%> vm_impl(); diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index ca76232..0d088c3 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -157,6 +157,10 @@ public: static constexpr auto& fp_vector_unary_w = softvec_if::fp_vector_unary_w; static constexpr auto& fp_vector_unary_n = softvec_if::fp_vector_unary_n; static constexpr auto& vector_unary_op = softvec_if::vector_unary_op; + static constexpr auto& vector_vector_crypto = softvec_if::vector_vector_crypto; + static constexpr auto& vector_scalar_crypto = softvec_if::vector_scalar_crypto; + static constexpr auto& vector_imm_crypto = softvec_if::vector_imm_crypto; + static constexpr auto& vector_crypto = softvec_if::vector_crypto; <%}%> vm_impl(); diff --git a/softvector b/softvector index ce60b58..eee635c 160000 --- a/softvector +++ b/softvector @@ -1 +1 @@ -Subproject commit ce60b58dd0548906fb0d7053c622cf6c881b0300 +Subproject commit eee635c183d73d78450e4b996b49ce22b7629c49 diff --git a/src/vm/vector_functions.h b/src/vm/vector_functions.h index db04488..de8c78f 100644 --- a/src/vm/vector_functions.h +++ b/src/vm/vector_functions.h @@ -985,5 +985,68 @@ void vector_unary_op(uint8_t* V, uint8_t unary_op, uint64_t vl, uint64_t vstart, throw new std::runtime_error("Unsupported sew_val"); } } +template +void vector_vector_crypto(uint8_t* V, uint8_t funct6, uint64_t eg_len, uint64_t eg_start, softvector::vtype_t vtype, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t egs) { + switch(egs) { + case 4: + return softvector::vector_vector_crypto(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1); + case 8: + return softvector::vector_vector_crypto(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported egs"); + } +} +template +void vector_scalar_crypto(uint8_t* V, uint8_t funct6, uint64_t eg_len, uint64_t eg_start, softvector::vtype_t vtype, uint8_t vd, + uint8_t vs2, uint8_t vs1, uint8_t egs) { + switch(egs) { + case 4: + return softvector::vector_scalar_crypto(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1); + case 8: + return softvector::vector_scalar_crypto(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported egs"); + } +} +template +void vector_imm_crypto(uint8_t* V, uint8_t funct6, uint64_t eg_len, uint64_t eg_start, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, + uint8_t imm, uint8_t egs) { + switch(egs) { + case 4: + return softvector::vector_imm_crypto(V, funct6, eg_len, eg_start, vtype, vd, vs2, imm); + case 8: + return softvector::vector_imm_crypto(V, funct6, eg_len, eg_start, vtype, vd, vs2, imm); + default: + throw new std::runtime_error("Unsupported egs"); + } +} +template +void vector_crypto(uint8_t* V, uint8_t funct6, uint64_t eg_len, uint64_t eg_start, softvector::vtype_t vtype, uint8_t vd, uint8_t vs2, + uint8_t vs1, uint8_t egs, uint8_t sew) { + switch(egs) { + case 4: + switch(sew) { + case 32: + return softvector::vector_crypto(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1); + case 64: + return softvector::vector_crypto(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew"); + } + case 8: + switch(sew) { + case 32: + return softvector::vector_crypto(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1); + case 64: + return softvector::vector_crypto(V, funct6, eg_len, eg_start, vtype, vd, vs2, vs1); + default: + throw new std::runtime_error("Unsupported sew"); + } + default: + throw new std::runtime_error("Unsupported egs"); + } +} + } // namespace softvec_if #endif /* RISCV_SRC_VM_VECTOR_FUNCTIONS_H_ */ From a1b8d58b490730b082f46bc860ca32da3c782b57 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Sat, 27 Sep 2025 17:47:07 +0200 Subject: [PATCH 026/230] corrects when CYCLE gets incremented for asmjit instructions --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index ffb1b99..25af08d 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -387,6 +387,7 @@ void vm_impl::gen_instr_prologue(jit_holder& jh) { x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE); mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state); + cc.inc(get_ptr_for(jh, traits::CYCLE)); cc.comment("//Instruction prologue end"); } @@ -395,7 +396,6 @@ void vm_impl::gen_instr_epilogue(jit_holder& jh) { auto& cc = jh.cc; cc.comment("//Instruction epilogue begin"); - cc.inc(get_ptr_for(jh, traits::CYCLE)); x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE); mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cmp(cc, current_trap_state, 0); From 1fdd03248f16031c65de59a56d93654906086eb4 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Sat, 27 Sep 2025 17:47:45 +0200 Subject: [PATCH 027/230] adds iss_factory registration for rv32gcv - now up to par with rv64gcv --- src/sysc/register_rv32gcv.cpp | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/sysc/register_rv32gcv.cpp b/src/sysc/register_rv32gcv.cpp index 2047e08..32b7d63 100644 --- a/src/sysc/register_rv32gcv.cpp +++ b/src/sysc/register_rv32gcv.cpp @@ -95,5 +95,27 @@ volatile std::array rv32gcv_init = { }; } #endif +#if defined(WITH_ASMJIT) +namespace asmjit { +using namespace sysc; +volatile std::array rv32gcv_init = { + iss_factory::instance().register_creator("rv32gcv_msu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv32gcv_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }), + iss_factory::instance().register_creator("rv32gcv_mu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + auto* cc = reinterpret_cast(data); + auto* cpu = new sc_core_adapter>(cc); + return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; + }) +}; +} +#endif } // clang-format on From d99cdf098d3a4a6621717bbc29b6b1e6d67f2fcd Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Sat, 27 Sep 2025 23:51:30 +0200 Subject: [PATCH 028/230] updates asmjit gcv implementation, now allows vector --- CMakeLists.txt | 10 +- gen_input/templates/CORENAME.h.gtl | 6 +- src/iss/arch/rv32gcv.h | 69 +++++---- src/iss/arch/rv64gcv.h | 69 +++++---- src/vm/asmjit/vm_rv32gcv.cpp | 227 +++++++++++++++-------------- src/vm/asmjit/vm_rv64gcv.cpp | 227 +++++++++++++++-------------- 6 files changed, 315 insertions(+), 293 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index dd994dc..377c6fd 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -20,7 +20,7 @@ if(NOT TARGET dbt-rise-core) dbt_rise_core_git GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git" #GIT_TAG "origin/develop" - GIT_TAG d2bafe + GIT_TAG 0c7532f6 GIT_SHALLOW OFF UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped. ) @@ -262,13 +262,9 @@ if(TARGET scc-sysc) set(LIB_SOURCES src/sysc/core_complex.cpp src/sysc/register_cores.cpp + src/sysc/register_rv32gcv.cpp + src/sysc/register_rv64gcv.cpp ) - if(WITH_ASMJIT) - list(APPEND LIB_SOURCES - src/sysc/register_rv32gcv.cpp - src/sysc/register_rv64gcv.cpp - ) - endif() if(IS_DIRECTORY "${PROJECT_SOURCE_DIR}/../dbt-rise-custom") FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/../dbt-rise-custom/src/sysc/register_*.cpp) diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl index 475352b..f9e729f 100644 --- a/gen_input/templates/CORENAME.h.gtl +++ b/gen_input/templates/CORENAME.h.gtl @@ -81,11 +81,9 @@ struct ${coreDef.name.toLowerCase()}: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - -#pragma pack(push, 1) struct ${coreDef.name}_regs {<% registers.each { reg -> if(reg.size>64) {%> - uint8_t ${reg.name}[${reg.size/8}] = {0};<% + <% if(reg.size>128) {%>alignas(16) <%}%>uint8_t ${reg.name}[${reg.size/8}] = {0};<% }else if(reg.size>0) {%> uint${nativeSize(reg.size)}_t ${reg.name} = 0;<% }}%> @@ -96,7 +94,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if { uint32_t instruction = 0; uint32_t last_branch = 0; } reg; -#pragma pack(pop) + std::array addr_mode; uint64_t interrupt_sim=0; diff --git a/src/iss/arch/rv32gcv.h b/src/iss/arch/rv32gcv.h index d087ca2..cb17465 100644 --- a/src/iss/arch/rv32gcv.h +++ b/src/iss/arch/rv32gcv.h @@ -64,8 +64,6 @@ struct rv32gcv: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - -#pragma pack(push, 1) struct RV32GCV_regs { uint32_t X0 = 0; uint32_t X1 = 0; @@ -136,38 +134,38 @@ struct rv32gcv: public arch_if { uint64_t F30 = 0; uint64_t F31 = 0; uint32_t FCSR = 0; - uint8_t V0[32] = {0}; - uint8_t V1[32] = {0}; - uint8_t V2[32] = {0}; - uint8_t V3[32] = {0}; - uint8_t V4[32] = {0}; - uint8_t V5[32] = {0}; - uint8_t V6[32] = {0}; - uint8_t V7[32] = {0}; - uint8_t V8[32] = {0}; - uint8_t V9[32] = {0}; - uint8_t V10[32] = {0}; - uint8_t V11[32] = {0}; - uint8_t V12[32] = {0}; - uint8_t V13[32] = {0}; - uint8_t V14[32] = {0}; - uint8_t V15[32] = {0}; - uint8_t V16[32] = {0}; - uint8_t V17[32] = {0}; - uint8_t V18[32] = {0}; - uint8_t V19[32] = {0}; - uint8_t V20[32] = {0}; - uint8_t V21[32] = {0}; - uint8_t V22[32] = {0}; - uint8_t V23[32] = {0}; - uint8_t V24[32] = {0}; - uint8_t V25[32] = {0}; - uint8_t V26[32] = {0}; - uint8_t V27[32] = {0}; - uint8_t V28[32] = {0}; - uint8_t V29[32] = {0}; - uint8_t V30[32] = {0}; - uint8_t V31[32] = {0}; + alignas(16) uint8_t V0[32] = {0}; + alignas(16) uint8_t V1[32] = {0}; + alignas(16) uint8_t V2[32] = {0}; + alignas(16) uint8_t V3[32] = {0}; + alignas(16) uint8_t V4[32] = {0}; + alignas(16) uint8_t V5[32] = {0}; + alignas(16) uint8_t V6[32] = {0}; + alignas(16) uint8_t V7[32] = {0}; + alignas(16) uint8_t V8[32] = {0}; + alignas(16) uint8_t V9[32] = {0}; + alignas(16) uint8_t V10[32] = {0}; + alignas(16) uint8_t V11[32] = {0}; + alignas(16) uint8_t V12[32] = {0}; + alignas(16) uint8_t V13[32] = {0}; + alignas(16) uint8_t V14[32] = {0}; + alignas(16) uint8_t V15[32] = {0}; + alignas(16) uint8_t V16[32] = {0}; + alignas(16) uint8_t V17[32] = {0}; + alignas(16) uint8_t V18[32] = {0}; + alignas(16) uint8_t V19[32] = {0}; + alignas(16) uint8_t V20[32] = {0}; + alignas(16) uint8_t V21[32] = {0}; + alignas(16) uint8_t V22[32] = {0}; + alignas(16) uint8_t V23[32] = {0}; + alignas(16) uint8_t V24[32] = {0}; + alignas(16) uint8_t V25[32] = {0}; + alignas(16) uint8_t V26[32] = {0}; + alignas(16) uint8_t V27[32] = {0}; + alignas(16) uint8_t V28[32] = {0}; + alignas(16) uint8_t V29[32] = {0}; + alignas(16) uint8_t V30[32] = {0}; + alignas(16) uint8_t V31[32] = {0}; uint32_t vstart = 0; uint32_t vxsat = 0; uint32_t vxrm = 0; @@ -180,7 +178,7 @@ struct rv32gcv: public arch_if { uint32_t instruction = 0; uint32_t last_branch = 0; } reg; -#pragma pack(pop) + std::array addr_mode; uint64_t interrupt_sim=0; @@ -338,6 +336,7 @@ template <> struct traits { VLENB_ADDR=3106ULL, MISA_VAL=1073746221ULL, MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL }; + constexpr static unsigned FP_REGS_SIZE = 64; constexpr static unsigned V_REGS_SIZE = 256; diff --git a/src/iss/arch/rv64gcv.h b/src/iss/arch/rv64gcv.h index 76289bf..fc8f49a 100644 --- a/src/iss/arch/rv64gcv.h +++ b/src/iss/arch/rv64gcv.h @@ -64,8 +64,6 @@ struct rv64gcv: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - -#pragma pack(push, 1) struct RV64GCV_regs { uint64_t X0 = 0; uint64_t X1 = 0; @@ -136,38 +134,38 @@ struct rv64gcv: public arch_if { uint64_t F30 = 0; uint64_t F31 = 0; uint32_t FCSR = 0; - uint8_t V0[64] = {0}; - uint8_t V1[64] = {0}; - uint8_t V2[64] = {0}; - uint8_t V3[64] = {0}; - uint8_t V4[64] = {0}; - uint8_t V5[64] = {0}; - uint8_t V6[64] = {0}; - uint8_t V7[64] = {0}; - uint8_t V8[64] = {0}; - uint8_t V9[64] = {0}; - uint8_t V10[64] = {0}; - uint8_t V11[64] = {0}; - uint8_t V12[64] = {0}; - uint8_t V13[64] = {0}; - uint8_t V14[64] = {0}; - uint8_t V15[64] = {0}; - uint8_t V16[64] = {0}; - uint8_t V17[64] = {0}; - uint8_t V18[64] = {0}; - uint8_t V19[64] = {0}; - uint8_t V20[64] = {0}; - uint8_t V21[64] = {0}; - uint8_t V22[64] = {0}; - uint8_t V23[64] = {0}; - uint8_t V24[64] = {0}; - uint8_t V25[64] = {0}; - uint8_t V26[64] = {0}; - uint8_t V27[64] = {0}; - uint8_t V28[64] = {0}; - uint8_t V29[64] = {0}; - uint8_t V30[64] = {0}; - uint8_t V31[64] = {0}; + alignas(16) uint8_t V0[64] = {0}; + alignas(16) uint8_t V1[64] = {0}; + alignas(16) uint8_t V2[64] = {0}; + alignas(16) uint8_t V3[64] = {0}; + alignas(16) uint8_t V4[64] = {0}; + alignas(16) uint8_t V5[64] = {0}; + alignas(16) uint8_t V6[64] = {0}; + alignas(16) uint8_t V7[64] = {0}; + alignas(16) uint8_t V8[64] = {0}; + alignas(16) uint8_t V9[64] = {0}; + alignas(16) uint8_t V10[64] = {0}; + alignas(16) uint8_t V11[64] = {0}; + alignas(16) uint8_t V12[64] = {0}; + alignas(16) uint8_t V13[64] = {0}; + alignas(16) uint8_t V14[64] = {0}; + alignas(16) uint8_t V15[64] = {0}; + alignas(16) uint8_t V16[64] = {0}; + alignas(16) uint8_t V17[64] = {0}; + alignas(16) uint8_t V18[64] = {0}; + alignas(16) uint8_t V19[64] = {0}; + alignas(16) uint8_t V20[64] = {0}; + alignas(16) uint8_t V21[64] = {0}; + alignas(16) uint8_t V22[64] = {0}; + alignas(16) uint8_t V23[64] = {0}; + alignas(16) uint8_t V24[64] = {0}; + alignas(16) uint8_t V25[64] = {0}; + alignas(16) uint8_t V26[64] = {0}; + alignas(16) uint8_t V27[64] = {0}; + alignas(16) uint8_t V28[64] = {0}; + alignas(16) uint8_t V29[64] = {0}; + alignas(16) uint8_t V30[64] = {0}; + alignas(16) uint8_t V31[64] = {0}; uint64_t vstart = 0; uint64_t vxsat = 0; uint64_t vxrm = 0; @@ -180,7 +178,7 @@ struct rv64gcv: public arch_if { uint32_t instruction = 0; uint32_t last_branch = 0; } reg; -#pragma pack(pop) + std::array addr_mode; uint64_t interrupt_sim=0; @@ -338,6 +336,7 @@ template <> struct traits { VLENB_ADDR=3106ULL, MISA_VAL=9223372036854780205ULL, MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL }; + constexpr static unsigned FP_REGS_SIZE = 64; constexpr static unsigned V_REGS_SIZE = 512; diff --git a/src/vm/asmjit/vm_rv32gcv.cpp b/src/vm/asmjit/vm_rv32gcv.cpp index 9470b31..9a0ad8f 100644 --- a/src/vm/asmjit/vm_rv32gcv.cpp +++ b/src/vm/asmjit/vm_rv32gcv.cpp @@ -29,7 +29,7 @@ * POSSIBILITY OF SUCH DAMAGE. * *******************************************************************************/ - + // clang-format off #include #include @@ -44,6 +44,7 @@ #include + #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif @@ -151,6 +152,10 @@ template class vm_impl : public iss::asmjit::vm_base { static constexpr auto& fp_vector_unary_w = softvec_if::fp_vector_unary_w; static constexpr auto& fp_vector_unary_n = softvec_if::fp_vector_unary_n; static constexpr auto& vector_unary_op = softvec_if::vector_unary_op; + static constexpr auto& vector_vector_crypto = softvec_if::vector_vector_crypto; + static constexpr auto& vector_scalar_crypto = softvec_if::vector_scalar_crypto; + static constexpr auto& vector_imm_crypto = softvec_if::vector_imm_crypto; + static constexpr auto& vector_crypto = softvec_if::vector_crypto; vm_impl(); @@ -8602,7 +8607,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_unbox_s_97 = get_reg_Gp(cc, 32, false); cc.invoke(&call_unbox_s_97, &unbox_s, FuncSignature::build()); InvokeNode* call_NaNBox32_95; - auto NaNBox32_95_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_s_96, 31, 31-31+1), 32, false), 31), gen_ext(cc, gen_slice(cc, ret_val_unbox_s_97, 0, 30-0+1), 32, false)); + auto NaNBox32_95_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_s_96, (uint32_t)(31), (uint32_t)(31-31+1)), 32, false), (uint32_t)31), + gen_ext(cc, gen_slice(cc, ret_val_unbox_s_97, (uint32_t)(0), (uint32_t)(30-0+1)), 32, false)); x86::Gp ret_val_NaNBox32_95 = get_reg_Gp(cc, 64, false); cc.invoke(&call_NaNBox32_95, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::F0+ rd), @@ -8664,7 +8670,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_unbox_s_100 = get_reg_Gp(cc, 32, false); cc.invoke(&call_unbox_s_100, &unbox_s, FuncSignature::build()); InvokeNode* call_NaNBox32_98; - auto NaNBox32_98_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_s_99, 31, 31-31+1)), 32, false), 31), gen_ext(cc, gen_slice(cc, ret_val_unbox_s_100, 0, 30-0+1), 32, false)); + auto NaNBox32_98_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation( cc, band, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_s_99, (uint32_t)(31), (uint32_t)(31-31+1))), (uint8_t)((1ULL<<1)-1)), 32, false), (uint32_t)31), + gen_ext(cc, gen_slice(cc, ret_val_unbox_s_100, (uint32_t)(0), (uint32_t)(30-0+1)), 32, false)); x86::Gp ret_val_NaNBox32_98 = get_reg_Gp(cc, 64, false); cc.invoke(&call_NaNBox32_98, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::F0+ rd), @@ -10881,7 +10888,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_unbox_d_216 = get_reg_Gp(cc, 64, false); cc.invoke(&call_unbox_d_216, &unbox_d, FuncSignature::build()); InvokeNode* call_NaNBox64_214; - auto NaNBox64_214_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_d_215, 63, 63-63+1), 64, false), 63), gen_ext(cc, gen_slice(cc, ret_val_unbox_d_216, 0, 62-0+1), 64, false)); + auto NaNBox64_214_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_d_215, (uint64_t)(63), (uint64_t)(63-63+1)), 64, false), (uint64_t)63), + gen_ext(cc, gen_slice(cc, ret_val_unbox_d_216, (uint64_t)(0), (uint64_t)(62-0+1)), 64, false)); x86::Gp ret_val_NaNBox64_214 = get_reg_Gp(cc, 64, false); cc.invoke(&call_NaNBox64_214, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::F0+ rd), @@ -10943,7 +10951,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_unbox_d_219 = get_reg_Gp(cc, 64, false); cc.invoke(&call_unbox_d_219, &unbox_d, FuncSignature::build()); InvokeNode* call_NaNBox64_217; - auto NaNBox64_217_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_d_218, 63, 63-63+1)), 64, false), 63), gen_ext(cc, gen_slice(cc, ret_val_unbox_d_219, 0, 62-0+1), 64, false)); + auto NaNBox64_217_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation( cc, band, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_d_218, (uint64_t)(63), (uint64_t)(63-63+1))), (uint8_t)((1ULL<<1)-1)), 64, false), (uint64_t)63), + gen_ext(cc, gen_slice(cc, ret_val_unbox_d_219, (uint64_t)(0), (uint64_t)(62-0+1)), 64, false)); x86::Gp ret_val_NaNBox64_217 = get_reg_Gp(cc, 64, false); cc.invoke(&call_NaNBox64_217, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::F0+ rd), @@ -11911,7 +11920,7 @@ template class vm_impl : public iss::asmjit::vm_base { write_reg_to_mem(jh, tmp264, traits::vstart); { auto label_merge = cc.newLabel(); - auto cond = gen_slice(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 8, (static_cast(traits::XLEN)-2)-8+1); + auto cond = gen_slice(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), (uint32_t)(8), (uint32_t)((static_cast(traits::XLEN)-2)-8+1)); cmp(cc, cond, 0); cc.je(label_merge); { @@ -11998,7 +12007,7 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_272, 0, ret_val_get_sew_pow_272); setArg(call_get_lmul_pow_273, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_273, 0, ret_val_get_lmul_pow_273); - auto vill = gen_slice(cc, load_reg_from_mem(jh, traits::vtype), static_cast(traits::XLEN)-1, 1); + auto vill = gen_slice(cc, load_reg_from_mem(jh, traits::vtype), (uint32_t)(static_cast(traits::XLEN)-1), (uint32_t)1); { auto label_merge = cc.newLabel(); auto cond = gen_operation(cc, lor, vill, (gen_operation(cc, ne, orig_ratio, new_ratio))); @@ -31448,7 +31457,10 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 7, static_cast(traits::XLEN)-1-7+1), 32, false), 7), gen_operation(cc, shl, gen_ext(cc, 1, 32, false), 6)), gen_operation(cc, shl, gen_ext(cc, 0, 32, false), 3)), gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 0, 2-0+1), 32, false)); + auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), (uint32_t)(7), (uint32_t)(static_cast(traits::XLEN)-1-7+1)), 32, false), (uint32_t)7), + gen_operation(cc, shl, gen_ext(cc, 1, 32, false), (uint32_t)6)), + gen_operation(cc, shl, gen_ext(cc, 0, 32, false), (uint32_t)3)), + gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), (uint32_t)(0), (uint32_t)(2-0+1)), 32, false)); InvokeNode* call_vsseg_1077; auto vsseg_1077_arg1 = evl; auto vsseg_1077_arg2 = load_reg_from_mem(jh, traits::vstart); @@ -31541,7 +31553,10 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 7, static_cast(traits::XLEN)-1-7+1), 32, false), 7), gen_operation(cc, shl, gen_ext(cc, 1, 32, false), 6)), gen_operation(cc, shl, gen_ext(cc, 0, 32, false), 3)), gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 0, 2-0+1), 32, false)); + auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), (uint32_t)(7), (uint32_t)(static_cast(traits::XLEN)-1-7+1)), 32, false), (uint32_t)7), + gen_operation(cc, shl, gen_ext(cc, 1, 32, false), (uint32_t)6)), + gen_operation(cc, shl, gen_ext(cc, 0, 32, false), (uint32_t)3)), + gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), (uint32_t)(0), (uint32_t)(2-0+1)), 32, false)); InvokeNode* call_vlseg_1080; auto vlseg_1080_arg1 = evl; auto vlseg_1080_arg2 = load_reg_from_mem(jh, traits::vstart); @@ -70227,7 +70242,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3004, (ret_val_get_sew_pow_3003))), 8, false), ~ 1); setArg(call_get_sew_pow_3003, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3003, 0, ret_val_get_sew_pow_3003); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_reduction_3005; @@ -70344,7 +70359,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3011, (ret_val_get_sew_pow_3010))), 8, false), ~ 1); setArg(call_get_sew_pow_3010, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3010, 0, ret_val_get_sew_pow_3010); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_reduction_3012; @@ -70461,7 +70476,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3018, (ret_val_get_sew_pow_3017))), 8, false), ~ 1); setArg(call_get_sew_pow_3017, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3017, 0, ret_val_get_sew_pow_3017); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_reduction_3019; @@ -70572,7 +70587,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3024, (ret_val_get_sew_pow_3023))), 8, false), ~ 1); setArg(call_get_sew_pow_3023, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3023, 0, ret_val_get_sew_pow_3023); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_reduction_3025; @@ -70683,7 +70698,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3030, (ret_val_get_sew_pow_3029))), 8, false), ~ 1); setArg(call_get_sew_pow_3029, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3029, 0, ret_val_get_sew_pow_3029); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); { @@ -70804,7 +70819,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3037, (ret_val_get_sew_pow_3036))), 8, false), ~ 1); setArg(call_get_sew_pow_3036, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3036, 0, ret_val_get_sew_pow_3036); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); { @@ -73531,7 +73546,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3156, (ret_val_get_sew_pow_3155))), 8, false), ~ 1); setArg(call_get_sew_pow_3155, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3155, 0, ret_val_get_sew_pow_3155); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3157; @@ -73633,7 +73648,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3162, (ret_val_get_sew_pow_3161))), 8, false), ~ 1); setArg(call_get_sew_pow_3161, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3161, 0, ret_val_get_sew_pow_3161); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3163; @@ -73728,7 +73743,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3168, (ret_val_get_sew_pow_3167))), 8, false), ~ 1); setArg(call_get_sew_pow_3167, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3167, 0, ret_val_get_sew_pow_3167); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3169; @@ -73838,7 +73853,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3174, (ret_val_get_sew_pow_3173))), 8, false), ~ 1); setArg(call_get_sew_pow_3173, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3173, 0, ret_val_get_sew_pow_3173); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3175; @@ -73948,7 +73963,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3180, (ret_val_get_sew_pow_3179))), 8, false), ~ 1); setArg(call_get_sew_pow_3179, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3179, 0, ret_val_get_sew_pow_3179); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3181; @@ -74069,7 +74084,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3187, (ret_val_get_sew_pow_3186))), 8, false), ~ 1); setArg(call_get_sew_pow_3186, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3186, 0, ret_val_get_sew_pow_3186); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3188; @@ -74188,7 +74203,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3194, (ret_val_get_sew_pow_3193))), 8, false), ~ 1); setArg(call_get_sew_pow_3193, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3193, 0, ret_val_get_sew_pow_3193); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3195; @@ -74309,7 +74324,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3201, (ret_val_get_sew_pow_3200))), 8, false), ~ 1); setArg(call_get_sew_pow_3200, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3200, 0, ret_val_get_sew_pow_3200); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3202; @@ -74428,7 +74443,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3208, (ret_val_get_sew_pow_3207))), 8, false), ~ 1); setArg(call_get_sew_pow_3207, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3207, 0, ret_val_get_sew_pow_3207); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3209; @@ -74558,7 +74573,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3217; @@ -74703,7 +74718,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3226; @@ -74857,7 +74872,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3236; @@ -75002,7 +75017,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3245; @@ -75156,7 +75171,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3255; @@ -75290,7 +75305,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3263; @@ -75433,7 +75448,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3272; @@ -75567,7 +75582,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3280; @@ -75701,7 +75716,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3287, (ret_val_get_sew_pow_3286))), 8, false), ~ 1); setArg(call_get_sew_pow_3286, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3286, 0, ret_val_get_sew_pow_3286); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3288; @@ -75822,7 +75837,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3294, (ret_val_get_sew_pow_3293))), 8, false), ~ 1); setArg(call_get_sew_pow_3293, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3293, 0, ret_val_get_sew_pow_3293); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3295; @@ -75941,7 +75956,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3301, (ret_val_get_sew_pow_3300))), 8, false), ~ 1); setArg(call_get_sew_pow_3300, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3300, 0, ret_val_get_sew_pow_3300); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3302; @@ -76062,7 +76077,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3308, (ret_val_get_sew_pow_3307))), 8, false), ~ 1); setArg(call_get_sew_pow_3307, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3307, 0, ret_val_get_sew_pow_3307); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3309; @@ -76181,7 +76196,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3315, (ret_val_get_sew_pow_3314))), 8, false), ~ 1); setArg(call_get_sew_pow_3314, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3314, 0, ret_val_get_sew_pow_3314); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3316; @@ -76311,7 +76326,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3324; @@ -76456,7 +76471,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3333; @@ -76601,7 +76616,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3341, (ret_val_get_sew_pow_3340))), 8, false), ~ 1); setArg(call_get_sew_pow_3340, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3340, 0, ret_val_get_sew_pow_3340); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3342; @@ -76722,7 +76737,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3348, (ret_val_get_sew_pow_3347))), 8, false), ~ 1); setArg(call_get_sew_pow_3347, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3347, 0, ret_val_get_sew_pow_3347); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3349; @@ -76841,7 +76856,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3355, (ret_val_get_sew_pow_3354))), 8, false), ~ 1); setArg(call_get_sew_pow_3354, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3354, 0, ret_val_get_sew_pow_3354); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3356; @@ -76962,7 +76977,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3362, (ret_val_get_sew_pow_3361))), 8, false), ~ 1); setArg(call_get_sew_pow_3361, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3361, 0, ret_val_get_sew_pow_3361); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3363; @@ -77081,7 +77096,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3369, (ret_val_get_sew_pow_3368))), 8, false), ~ 1); setArg(call_get_sew_pow_3368, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3368, 0, ret_val_get_sew_pow_3368); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3370; @@ -77202,7 +77217,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3376, (ret_val_get_sew_pow_3375))), 8, false), ~ 1); setArg(call_get_sew_pow_3375, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3375, 0, ret_val_get_sew_pow_3375); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3377; @@ -77321,7 +77336,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3383, (ret_val_get_sew_pow_3382))), 8, false), ~ 1); setArg(call_get_sew_pow_3382, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3382, 0, ret_val_get_sew_pow_3382); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3384; @@ -77442,7 +77457,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3390, (ret_val_get_sew_pow_3389))), 8, false), ~ 1); setArg(call_get_sew_pow_3389, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3389, 0, ret_val_get_sew_pow_3389); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3391; @@ -77561,7 +77576,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3397, (ret_val_get_sew_pow_3396))), 8, false), ~ 1); setArg(call_get_sew_pow_3396, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3396, 0, ret_val_get_sew_pow_3396); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3398; @@ -77682,7 +77697,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3404, (ret_val_get_sew_pow_3403))), 8, false), ~ 1); setArg(call_get_sew_pow_3403, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3403, 0, ret_val_get_sew_pow_3403); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3405; @@ -77801,7 +77816,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3411, (ret_val_get_sew_pow_3410))), 8, false), ~ 1); setArg(call_get_sew_pow_3410, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3410, 0, ret_val_get_sew_pow_3410); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3412; @@ -77922,7 +77937,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3418, (ret_val_get_sew_pow_3417))), 8, false), ~ 1); setArg(call_get_sew_pow_3417, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3417, 0, ret_val_get_sew_pow_3417); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3419; @@ -78041,7 +78056,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3425, (ret_val_get_sew_pow_3424))), 8, false), ~ 1); setArg(call_get_sew_pow_3424, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3424, 0, ret_val_get_sew_pow_3424); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3426; @@ -78162,7 +78177,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3432, (ret_val_get_sew_pow_3431))), 8, false), ~ 1); setArg(call_get_sew_pow_3431, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3431, 0, ret_val_get_sew_pow_3431); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3433; @@ -78281,7 +78296,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3439, (ret_val_get_sew_pow_3438))), 8, false), ~ 1); setArg(call_get_sew_pow_3438, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3438, 0, ret_val_get_sew_pow_3438); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3440; @@ -78402,7 +78417,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3446, (ret_val_get_sew_pow_3445))), 8, false), ~ 1); setArg(call_get_sew_pow_3445, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3445, 0, ret_val_get_sew_pow_3445); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3447; @@ -78530,7 +78545,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3455; @@ -78675,7 +78690,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3464; @@ -78829,7 +78844,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3474; @@ -78974,7 +78989,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3483; @@ -79128,7 +79143,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3493; @@ -79273,7 +79288,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3502; @@ -79427,7 +79442,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3512; @@ -79572,7 +79587,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3521; @@ -79716,7 +79731,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3529, (ret_val_get_sew_pow_3528))), 8, false), ~ 1); setArg(call_get_sew_pow_3528, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3528, 0, ret_val_get_sew_pow_3528); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3530; @@ -79833,7 +79848,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3536, (ret_val_get_sew_pow_3535))), 8, false), ~ 1); setArg(call_get_sew_pow_3535, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3535, 0, ret_val_get_sew_pow_3535); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3537; @@ -79950,7 +79965,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3543, (ret_val_get_sew_pow_3542))), 8, false), ~ 1); setArg(call_get_sew_pow_3542, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3542, 0, ret_val_get_sew_pow_3542); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3544; @@ -80068,7 +80083,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3550, (ret_val_get_sew_pow_3549))), 8, false), ~ 1); setArg(call_get_sew_pow_3549, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3549, 0, ret_val_get_sew_pow_3549); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3551; @@ -80183,7 +80198,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3556, (ret_val_get_sew_pow_3555))), 8, false), ~ 1); setArg(call_get_sew_pow_3555, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3555, 0, ret_val_get_sew_pow_3555); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3557; @@ -80296,7 +80311,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3562, (ret_val_get_sew_pow_3561))), 8, false), ~ 1); setArg(call_get_sew_pow_3561, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3561, 0, ret_val_get_sew_pow_3561); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3563; @@ -80411,7 +80426,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3568, (ret_val_get_sew_pow_3567))), 8, false), ~ 1); setArg(call_get_sew_pow_3567, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3567, 0, ret_val_get_sew_pow_3567); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3569; @@ -80524,7 +80539,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3574, (ret_val_get_sew_pow_3573))), 8, false), ~ 1); setArg(call_get_sew_pow_3573, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3573, 0, ret_val_get_sew_pow_3573); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3575; @@ -80639,7 +80654,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3580, (ret_val_get_sew_pow_3579))), 8, false), ~ 1); setArg(call_get_sew_pow_3579, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3579, 0, ret_val_get_sew_pow_3579); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3581; @@ -80752,7 +80767,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3586, (ret_val_get_sew_pow_3585))), 8, false), ~ 1); setArg(call_get_sew_pow_3585, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3585, 0, ret_val_get_sew_pow_3585); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3587; @@ -80867,7 +80882,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3592, (ret_val_get_sew_pow_3591))), 8, false), ~ 1); setArg(call_get_sew_pow_3591, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3591, 0, ret_val_get_sew_pow_3591); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3593; @@ -80980,7 +80995,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3598, (ret_val_get_sew_pow_3597))), 8, false), ~ 1); setArg(call_get_sew_pow_3597, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3597, 0, ret_val_get_sew_pow_3597); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3599; @@ -81095,7 +81110,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3604, (ret_val_get_sew_pow_3603))), 8, false), ~ 1); setArg(call_get_sew_pow_3603, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3603, 0, ret_val_get_sew_pow_3603); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3605; @@ -81208,7 +81223,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3610, (ret_val_get_sew_pow_3609))), 8, false), ~ 1); setArg(call_get_sew_pow_3609, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3609, 0, ret_val_get_sew_pow_3609); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3611; @@ -81326,7 +81341,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3617, (ret_val_get_sew_pow_3616))), 8, false), ~ 1); setArg(call_get_sew_pow_3616, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3616, 0, ret_val_get_sew_pow_3616); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3618; @@ -81442,7 +81457,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3624, (ret_val_get_sew_pow_3623))), 8, false), ~ 1); setArg(call_get_sew_pow_3623, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3623, 0, ret_val_get_sew_pow_3623); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3625; @@ -81560,7 +81575,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3631, (ret_val_get_sew_pow_3630))), 8, false), ~ 1); setArg(call_get_sew_pow_3630, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3630, 0, ret_val_get_sew_pow_3630); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3632; @@ -81676,7 +81691,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3638, (ret_val_get_sew_pow_3637))), 8, false), ~ 1); setArg(call_get_sew_pow_3637, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3637, 0, ret_val_get_sew_pow_3637); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3639; @@ -81794,7 +81809,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3645, (ret_val_get_sew_pow_3644))), 8, false), ~ 1); setArg(call_get_sew_pow_3644, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3644, 0, ret_val_get_sew_pow_3644); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3646; @@ -81910,7 +81925,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3652, (ret_val_get_sew_pow_3651))), 8, false), ~ 1); setArg(call_get_sew_pow_3651, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3651, 0, ret_val_get_sew_pow_3651); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3653; @@ -82028,7 +82043,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3659, (ret_val_get_sew_pow_3658))), 8, false), ~ 1); setArg(call_get_sew_pow_3658, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3658, 0, ret_val_get_sew_pow_3658); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3660; @@ -82144,7 +82159,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3666, (ret_val_get_sew_pow_3665))), 8, false), ~ 1); setArg(call_get_sew_pow_3665, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3665, 0, ret_val_get_sew_pow_3665); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3667; @@ -82262,7 +82277,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3673, (ret_val_get_sew_pow_3672))), 8, false), ~ 1); setArg(call_get_sew_pow_3672, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3672, 0, ret_val_get_sew_pow_3672); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3674; @@ -82379,7 +82394,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3680, (ret_val_get_sew_pow_3679))), 8, false), ~ 1); setArg(call_get_sew_pow_3679, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3679, 0, ret_val_get_sew_pow_3679); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3681; @@ -82490,7 +82505,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3686, (ret_val_get_sew_pow_3685))), 8, false), ~ 1); setArg(call_get_sew_pow_3685, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3685, 0, ret_val_get_sew_pow_3685); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_masked_3687; @@ -82598,7 +82613,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3692, (ret_val_get_sew_pow_3691))), 8, false), ~ 1); setArg(call_get_sew_pow_3691, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3691, 0, ret_val_get_sew_pow_3691); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3693; @@ -82706,7 +82721,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3698, (ret_val_get_sew_pow_3697))), 8, false), ~ 1); setArg(call_get_sew_pow_3697, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3697, 0, ret_val_get_sew_pow_3697); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3699; @@ -82817,7 +82832,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3704, (ret_val_get_sew_pow_3703))), 8, false), ~ 1); setArg(call_get_sew_pow_3703, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3703, 0, ret_val_get_sew_pow_3703); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3705; @@ -83146,7 +83161,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3722, (ret_val_get_sew_pow_3721))), 8, false), ~ 1); setArg(call_get_sew_pow_3721, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3721, 0, ret_val_get_sew_pow_3721); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3723; @@ -83257,7 +83272,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3728, (ret_val_get_sew_pow_3727))), 8, false), ~ 1); setArg(call_get_sew_pow_3727, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3727, 0, ret_val_get_sew_pow_3727); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3729; @@ -83377,7 +83392,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3736; @@ -83511,7 +83526,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3744; @@ -83909,7 +83924,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3768; @@ -84043,7 +84058,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3776; @@ -84177,7 +84192,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3784; @@ -84311,7 +84326,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3792; @@ -84445,7 +84460,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3800; @@ -84843,7 +84858,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3824; @@ -84977,7 +84992,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3832; @@ -85111,7 +85126,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3840; @@ -85245,7 +85260,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3848; @@ -85398,6 +85413,7 @@ void vm_impl::gen_instr_prologue(jit_holder& jh) { x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE); mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state); + cc.inc(get_ptr_for(jh, traits::CYCLE)); cc.comment("//Instruction prologue end"); } @@ -85406,7 +85422,6 @@ void vm_impl::gen_instr_epilogue(jit_holder& jh) { auto& cc = jh.cc; cc.comment("//Instruction epilogue begin"); - cc.inc(get_ptr_for(jh, traits::CYCLE)); x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE); mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cmp(cc, current_trap_state, 0); @@ -85496,8 +85511,8 @@ std::unique_ptr create(arch::rv32gcv *core, unsigned short } // namespace iss #include -#include #include +#include #include namespace iss { namespace { diff --git a/src/vm/asmjit/vm_rv64gcv.cpp b/src/vm/asmjit/vm_rv64gcv.cpp index 80ebf7c..600f51d 100644 --- a/src/vm/asmjit/vm_rv64gcv.cpp +++ b/src/vm/asmjit/vm_rv64gcv.cpp @@ -29,7 +29,7 @@ * POSSIBILITY OF SUCH DAMAGE. * *******************************************************************************/ - + // clang-format off #include #include @@ -44,6 +44,7 @@ #include + #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif @@ -151,6 +152,10 @@ template class vm_impl : public iss::asmjit::vm_base { static constexpr auto& fp_vector_unary_w = softvec_if::fp_vector_unary_w; static constexpr auto& fp_vector_unary_n = softvec_if::fp_vector_unary_n; static constexpr auto& vector_unary_op = softvec_if::vector_unary_op; + static constexpr auto& vector_vector_crypto = softvec_if::vector_vector_crypto; + static constexpr auto& vector_scalar_crypto = softvec_if::vector_scalar_crypto; + static constexpr auto& vector_imm_crypto = softvec_if::vector_imm_crypto; + static constexpr auto& vector_crypto = softvec_if::vector_crypto; vm_impl(); @@ -10963,7 +10968,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_unbox_s_118 = get_reg_Gp(cc, 32, false); cc.invoke(&call_unbox_s_118, &unbox_s, FuncSignature::build()); InvokeNode* call_NaNBox32_116; - auto NaNBox32_116_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_s_117, 31, 31-31+1), 32, false), 31), gen_ext(cc, gen_slice(cc, ret_val_unbox_s_118, 0, 30-0+1), 32, false)); + auto NaNBox32_116_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_s_117, (uint32_t)(31), (uint32_t)(31-31+1)), 32, false), (uint32_t)31), + gen_ext(cc, gen_slice(cc, ret_val_unbox_s_118, (uint32_t)(0), (uint32_t)(30-0+1)), 32, false)); x86::Gp ret_val_NaNBox32_116 = get_reg_Gp(cc, 64, false); cc.invoke(&call_NaNBox32_116, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::F0+ rd), @@ -11025,7 +11031,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_unbox_s_121 = get_reg_Gp(cc, 32, false); cc.invoke(&call_unbox_s_121, &unbox_s, FuncSignature::build()); InvokeNode* call_NaNBox32_119; - auto NaNBox32_119_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_s_120, 31, 31-31+1)), 32, false), 31), gen_ext(cc, gen_slice(cc, ret_val_unbox_s_121, 0, 30-0+1), 32, false)); + auto NaNBox32_119_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation( cc, band, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_s_120, (uint32_t)(31), (uint32_t)(31-31+1))), (uint8_t)((1ULL<<1)-1)), 32, false), (uint32_t)31), + gen_ext(cc, gen_slice(cc, ret_val_unbox_s_121, (uint32_t)(0), (uint32_t)(30-0+1)), 32, false)); x86::Gp ret_val_NaNBox32_119 = get_reg_Gp(cc, 64, false); cc.invoke(&call_NaNBox32_119, (uintptr_t)&vm_impl::_NaNBox32, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::F0+ rd), @@ -13359,7 +13366,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_unbox_d_251 = get_reg_Gp(cc, 64, false); cc.invoke(&call_unbox_d_251, &unbox_d, FuncSignature::build()); InvokeNode* call_NaNBox64_249; - auto NaNBox64_249_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_d_250, 63, 63-63+1), 64, false), 63), gen_ext(cc, gen_slice(cc, ret_val_unbox_d_251, 0, 62-0+1), 64, false)); + auto NaNBox64_249_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, ret_val_unbox_d_250, (uint64_t)(63), (uint64_t)(63-63+1)), 64, false), (uint64_t)63), + gen_ext(cc, gen_slice(cc, ret_val_unbox_d_251, (uint64_t)(0), (uint64_t)(62-0+1)), 64, false)); x86::Gp ret_val_NaNBox64_249 = get_reg_Gp(cc, 64, false); cc.invoke(&call_NaNBox64_249, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::F0+ rd), @@ -13421,7 +13429,8 @@ template class vm_impl : public iss::asmjit::vm_base { x86::Gp ret_val_unbox_d_254 = get_reg_Gp(cc, 64, false); cc.invoke(&call_unbox_d_254, &unbox_d, FuncSignature::build()); InvokeNode* call_NaNBox64_252; - auto NaNBox64_252_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_d_253, 63, 63-63+1)), 64, false), 63), gen_ext(cc, gen_slice(cc, ret_val_unbox_d_254, 0, 62-0+1), 64, false)); + auto NaNBox64_252_arg0 = gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_operation( cc, band, gen_operation(cc, bnot, gen_slice(cc, ret_val_unbox_d_253, (uint64_t)(63), (uint64_t)(63-63+1))), (uint8_t)((1ULL<<1)-1)), 64, false), (uint64_t)63), + gen_ext(cc, gen_slice(cc, ret_val_unbox_d_254, (uint64_t)(0), (uint64_t)(62-0+1)), 64, false)); x86::Gp ret_val_NaNBox64_252 = get_reg_Gp(cc, 64, false); cc.invoke(&call_NaNBox64_252, (uintptr_t)&vm_impl::_NaNBox64, FuncSignature::build()); mov(cc, get_ptr_for(jh, traits::F0+ rd), @@ -14492,7 +14501,7 @@ template class vm_impl : public iss::asmjit::vm_base { write_reg_to_mem(jh, tmp300, traits::vstart); { auto label_merge = cc.newLabel(); - auto cond = gen_slice(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), 8, (static_cast(traits::XLEN)-2)-8+1); + auto cond = gen_slice(cc, load_reg_from_mem_Gp(jh, traits::X0 + rs2), (uint64_t)(8), (uint64_t)((static_cast(traits::XLEN)-2)-8+1)); cmp(cc, cond, 0); cc.je(label_merge); { @@ -14579,7 +14588,7 @@ template class vm_impl : public iss::asmjit::vm_base { setRet(call_get_sew_pow_308, 0, ret_val_get_sew_pow_308); setArg(call_get_lmul_pow_309, 0, reinterpret_cast(this)); setRet(call_get_lmul_pow_309, 0, ret_val_get_lmul_pow_309); - auto vill = gen_slice(cc, load_reg_from_mem(jh, traits::vtype), static_cast(traits::XLEN)-1, 1); + auto vill = gen_slice(cc, load_reg_from_mem(jh, traits::vtype), (uint64_t)(static_cast(traits::XLEN)-1), (uint64_t)1); { auto label_merge = cc.newLabel(); auto cond = gen_operation(cc, lor, vill, (gen_operation(cc, ne, orig_ratio, new_ratio))); @@ -34029,7 +34038,10 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 7, static_cast(traits::XLEN)-1-7+1), 64, false), 7), gen_operation(cc, shl, gen_ext(cc, 1, 64, false), 6)), gen_operation(cc, shl, gen_ext(cc, 0, 64, false), 3)), gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 0, 2-0+1), 64, false)); + auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), (uint64_t)(7), (uint64_t)(static_cast(traits::XLEN)-1-7+1)), 64, false), (uint64_t)7), + gen_operation(cc, shl, gen_ext(cc, 1, 64, false), (uint64_t)6)), + gen_operation(cc, shl, gen_ext(cc, 0, 64, false), (uint64_t)3)), + gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), (uint64_t)(0), (uint64_t)(2-0+1)), 64, false)); InvokeNode* call_vsseg_1113; auto vsseg_1113_arg1 = evl; auto vsseg_1113_arg2 = load_reg_from_mem(jh, traits::vstart); @@ -34122,7 +34134,10 @@ template class vm_impl : public iss::asmjit::vm_base { } cc.bind(label_merge); } - auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 7, static_cast(traits::XLEN)-1-7+1), 64, false), 7), gen_operation(cc, shl, gen_ext(cc, 1, 64, false), 6)), gen_operation(cc, shl, gen_ext(cc, 0, 64, false), 3)), gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), 0, 2-0+1), 64, false)); + auto _vtype = gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, bor, gen_operation(cc, shl, gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), (uint64_t)(7), (uint64_t)(static_cast(traits::XLEN)-1-7+1)), 64, false), (uint64_t)7), + gen_operation(cc, shl, gen_ext(cc, 1, 64, false), (uint64_t)6)), + gen_operation(cc, shl, gen_ext(cc, 0, 64, false), (uint64_t)3)), + gen_ext(cc, gen_slice(cc, load_reg_from_mem(jh, traits::vtype), (uint64_t)(0), (uint64_t)(2-0+1)), 64, false)); InvokeNode* call_vlseg_1116; auto vlseg_1116_arg1 = evl; auto vlseg_1116_arg2 = load_reg_from_mem(jh, traits::vstart); @@ -72808,7 +72823,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3040, (ret_val_get_sew_pow_3039))), 8, false), ~ 1); setArg(call_get_sew_pow_3039, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3039, 0, ret_val_get_sew_pow_3039); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_reduction_3041; @@ -72925,7 +72940,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3047, (ret_val_get_sew_pow_3046))), 8, false), ~ 1); setArg(call_get_sew_pow_3046, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3046, 0, ret_val_get_sew_pow_3046); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_reduction_3048; @@ -73042,7 +73057,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3054, (ret_val_get_sew_pow_3053))), 8, false), ~ 1); setArg(call_get_sew_pow_3053, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3053, 0, ret_val_get_sew_pow_3053); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_reduction_3055; @@ -73153,7 +73168,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3060, (ret_val_get_sew_pow_3059))), 8, false), ~ 1); setArg(call_get_sew_pow_3059, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3059, 0, ret_val_get_sew_pow_3059); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_reduction_3061; @@ -73264,7 +73279,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3066, (ret_val_get_sew_pow_3065))), 8, false), ~ 1); setArg(call_get_sew_pow_3065, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3065, 0, ret_val_get_sew_pow_3065); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); { @@ -73385,7 +73400,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3073, (ret_val_get_sew_pow_3072))), 8, false), ~ 1); setArg(call_get_sew_pow_3072, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3072, 0, ret_val_get_sew_pow_3072); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); { @@ -76112,7 +76127,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3192, (ret_val_get_sew_pow_3191))), 8, false), ~ 1); setArg(call_get_sew_pow_3191, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3191, 0, ret_val_get_sew_pow_3191); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3193; @@ -76214,7 +76229,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3198, (ret_val_get_sew_pow_3197))), 8, false), ~ 1); setArg(call_get_sew_pow_3197, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3197, 0, ret_val_get_sew_pow_3197); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3199; @@ -76309,7 +76324,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3204, (ret_val_get_sew_pow_3203))), 8, false), ~ 1); setArg(call_get_sew_pow_3203, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3203, 0, ret_val_get_sew_pow_3203); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3205; @@ -76419,7 +76434,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3210, (ret_val_get_sew_pow_3209))), 8, false), ~ 1); setArg(call_get_sew_pow_3209, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3209, 0, ret_val_get_sew_pow_3209); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3211; @@ -76529,7 +76544,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3216, (ret_val_get_sew_pow_3215))), 8, false), ~ 1); setArg(call_get_sew_pow_3215, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3215, 0, ret_val_get_sew_pow_3215); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3217; @@ -76650,7 +76665,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3223, (ret_val_get_sew_pow_3222))), 8, false), ~ 1); setArg(call_get_sew_pow_3222, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3222, 0, ret_val_get_sew_pow_3222); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3224; @@ -76769,7 +76784,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3230, (ret_val_get_sew_pow_3229))), 8, false), ~ 1); setArg(call_get_sew_pow_3229, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3229, 0, ret_val_get_sew_pow_3229); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3231; @@ -76890,7 +76905,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3237, (ret_val_get_sew_pow_3236))), 8, false), ~ 1); setArg(call_get_sew_pow_3236, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3236, 0, ret_val_get_sew_pow_3236); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3238; @@ -77009,7 +77024,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3244, (ret_val_get_sew_pow_3243))), 8, false), ~ 1); setArg(call_get_sew_pow_3243, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3243, 0, ret_val_get_sew_pow_3243); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3245; @@ -77139,7 +77154,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3253; @@ -77284,7 +77299,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3262; @@ -77438,7 +77453,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3272; @@ -77583,7 +77598,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3281; @@ -77737,7 +77752,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3291; @@ -77871,7 +77886,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3299; @@ -78014,7 +78029,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3308; @@ -78148,7 +78163,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3316; @@ -78282,7 +78297,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3323, (ret_val_get_sew_pow_3322))), 8, false), ~ 1); setArg(call_get_sew_pow_3322, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3322, 0, ret_val_get_sew_pow_3322); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3324; @@ -78403,7 +78418,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3330, (ret_val_get_sew_pow_3329))), 8, false), ~ 1); setArg(call_get_sew_pow_3329, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3329, 0, ret_val_get_sew_pow_3329); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3331; @@ -78522,7 +78537,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3337, (ret_val_get_sew_pow_3336))), 8, false), ~ 1); setArg(call_get_sew_pow_3336, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3336, 0, ret_val_get_sew_pow_3336); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3338; @@ -78643,7 +78658,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3344, (ret_val_get_sew_pow_3343))), 8, false), ~ 1); setArg(call_get_sew_pow_3343, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3343, 0, ret_val_get_sew_pow_3343); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3345; @@ -78762,7 +78777,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3351, (ret_val_get_sew_pow_3350))), 8, false), ~ 1); setArg(call_get_sew_pow_3350, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3350, 0, ret_val_get_sew_pow_3350); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3352; @@ -78892,7 +78907,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3360; @@ -79037,7 +79052,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3369; @@ -79182,7 +79197,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3377, (ret_val_get_sew_pow_3376))), 8, false), ~ 1); setArg(call_get_sew_pow_3376, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3376, 0, ret_val_get_sew_pow_3376); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3378; @@ -79303,7 +79318,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3384, (ret_val_get_sew_pow_3383))), 8, false), ~ 1); setArg(call_get_sew_pow_3383, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3383, 0, ret_val_get_sew_pow_3383); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3385; @@ -79422,7 +79437,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3391, (ret_val_get_sew_pow_3390))), 8, false), ~ 1); setArg(call_get_sew_pow_3390, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3390, 0, ret_val_get_sew_pow_3390); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3392; @@ -79543,7 +79558,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3398, (ret_val_get_sew_pow_3397))), 8, false), ~ 1); setArg(call_get_sew_pow_3397, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3397, 0, ret_val_get_sew_pow_3397); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3399; @@ -79662,7 +79677,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3405, (ret_val_get_sew_pow_3404))), 8, false), ~ 1); setArg(call_get_sew_pow_3404, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3404, 0, ret_val_get_sew_pow_3404); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3406; @@ -79783,7 +79798,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3412, (ret_val_get_sew_pow_3411))), 8, false), ~ 1); setArg(call_get_sew_pow_3411, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3411, 0, ret_val_get_sew_pow_3411); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3413; @@ -79902,7 +79917,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3419, (ret_val_get_sew_pow_3418))), 8, false), ~ 1); setArg(call_get_sew_pow_3418, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3418, 0, ret_val_get_sew_pow_3418); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3420; @@ -80023,7 +80038,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3426, (ret_val_get_sew_pow_3425))), 8, false), ~ 1); setArg(call_get_sew_pow_3425, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3425, 0, ret_val_get_sew_pow_3425); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3427; @@ -80142,7 +80157,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3433, (ret_val_get_sew_pow_3432))), 8, false), ~ 1); setArg(call_get_sew_pow_3432, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3432, 0, ret_val_get_sew_pow_3432); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3434; @@ -80263,7 +80278,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3440, (ret_val_get_sew_pow_3439))), 8, false), ~ 1); setArg(call_get_sew_pow_3439, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3439, 0, ret_val_get_sew_pow_3439); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3441; @@ -80382,7 +80397,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3447, (ret_val_get_sew_pow_3446))), 8, false), ~ 1); setArg(call_get_sew_pow_3446, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3446, 0, ret_val_get_sew_pow_3446); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3448; @@ -80503,7 +80518,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3454, (ret_val_get_sew_pow_3453))), 8, false), ~ 1); setArg(call_get_sew_pow_3453, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3453, 0, ret_val_get_sew_pow_3453); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3455; @@ -80622,7 +80637,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3461, (ret_val_get_sew_pow_3460))), 8, false), ~ 1); setArg(call_get_sew_pow_3460, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3460, 0, ret_val_get_sew_pow_3460); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3462; @@ -80743,7 +80758,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3468, (ret_val_get_sew_pow_3467))), 8, false), ~ 1); setArg(call_get_sew_pow_3467, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3467, 0, ret_val_get_sew_pow_3467); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3469; @@ -80862,7 +80877,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3475, (ret_val_get_sew_pow_3474))), 8, false), ~ 1); setArg(call_get_sew_pow_3474, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3474, 0, ret_val_get_sew_pow_3474); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3476; @@ -80983,7 +80998,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3482, (ret_val_get_sew_pow_3481))), 8, false), ~ 1); setArg(call_get_sew_pow_3481, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3481, 0, ret_val_get_sew_pow_3481); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3483; @@ -81111,7 +81126,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3491; @@ -81256,7 +81271,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3500; @@ -81410,7 +81425,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3510; @@ -81555,7 +81570,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3519; @@ -81709,7 +81724,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3529; @@ -81854,7 +81869,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3538; @@ -82008,7 +82023,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3548; @@ -82153,7 +82168,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3557; @@ -82297,7 +82312,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3565, (ret_val_get_sew_pow_3564))), 8, false), ~ 1); setArg(call_get_sew_pow_3564, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3564, 0, ret_val_get_sew_pow_3564); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3566; @@ -82414,7 +82429,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3572, (ret_val_get_sew_pow_3571))), 8, false), ~ 1); setArg(call_get_sew_pow_3571, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3571, 0, ret_val_get_sew_pow_3571); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3573; @@ -82531,7 +82546,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3579, (ret_val_get_sew_pow_3578))), 8, false), ~ 1); setArg(call_get_sew_pow_3578, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3578, 0, ret_val_get_sew_pow_3578); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3580; @@ -82649,7 +82664,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3586, (ret_val_get_sew_pow_3585))), 8, false), ~ 1); setArg(call_get_sew_pow_3585, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3585, 0, ret_val_get_sew_pow_3585); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3587; @@ -82764,7 +82779,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3592, (ret_val_get_sew_pow_3591))), 8, false), ~ 1); setArg(call_get_sew_pow_3591, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3591, 0, ret_val_get_sew_pow_3591); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3593; @@ -82877,7 +82892,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3598, (ret_val_get_sew_pow_3597))), 8, false), ~ 1); setArg(call_get_sew_pow_3597, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3597, 0, ret_val_get_sew_pow_3597); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3599; @@ -82992,7 +83007,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3604, (ret_val_get_sew_pow_3603))), 8, false), ~ 1); setArg(call_get_sew_pow_3603, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3603, 0, ret_val_get_sew_pow_3603); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3605; @@ -83105,7 +83120,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3610, (ret_val_get_sew_pow_3609))), 8, false), ~ 1); setArg(call_get_sew_pow_3609, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3609, 0, ret_val_get_sew_pow_3609); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3611; @@ -83220,7 +83235,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3616, (ret_val_get_sew_pow_3615))), 8, false), ~ 1); setArg(call_get_sew_pow_3615, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3615, 0, ret_val_get_sew_pow_3615); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3617; @@ -83333,7 +83348,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3622, (ret_val_get_sew_pow_3621))), 8, false), ~ 1); setArg(call_get_sew_pow_3621, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3621, 0, ret_val_get_sew_pow_3621); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3623; @@ -83448,7 +83463,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3628, (ret_val_get_sew_pow_3627))), 8, false), ~ 1); setArg(call_get_sew_pow_3627, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3627, 0, ret_val_get_sew_pow_3627); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3629; @@ -83561,7 +83576,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3634, (ret_val_get_sew_pow_3633))), 8, false), ~ 1); setArg(call_get_sew_pow_3633, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3633, 0, ret_val_get_sew_pow_3633); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3635; @@ -83676,7 +83691,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3640, (ret_val_get_sew_pow_3639))), 8, false), ~ 1); setArg(call_get_sew_pow_3639, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3639, 0, ret_val_get_sew_pow_3639); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3641; @@ -83789,7 +83804,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3646, (ret_val_get_sew_pow_3645))), 8, false), ~ 1); setArg(call_get_sew_pow_3645, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3645, 0, ret_val_get_sew_pow_3645); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3647; @@ -83907,7 +83922,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3653, (ret_val_get_sew_pow_3652))), 8, false), ~ 1); setArg(call_get_sew_pow_3652, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3652, 0, ret_val_get_sew_pow_3652); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3654; @@ -84023,7 +84038,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3660, (ret_val_get_sew_pow_3659))), 8, false), ~ 1); setArg(call_get_sew_pow_3659, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3659, 0, ret_val_get_sew_pow_3659); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3661; @@ -84141,7 +84156,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3667, (ret_val_get_sew_pow_3666))), 8, false), ~ 1); setArg(call_get_sew_pow_3666, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3666, 0, ret_val_get_sew_pow_3666); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3668; @@ -84257,7 +84272,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3674, (ret_val_get_sew_pow_3673))), 8, false), ~ 1); setArg(call_get_sew_pow_3673, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3673, 0, ret_val_get_sew_pow_3673); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3675; @@ -84375,7 +84390,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3681, (ret_val_get_sew_pow_3680))), 8, false), ~ 1); setArg(call_get_sew_pow_3680, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3680, 0, ret_val_get_sew_pow_3680); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3682; @@ -84491,7 +84506,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3688, (ret_val_get_sew_pow_3687))), 8, false), ~ 1); setArg(call_get_sew_pow_3687, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3687, 0, ret_val_get_sew_pow_3687); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3689; @@ -84609,7 +84624,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3695, (ret_val_get_sew_pow_3694))), 8, false), ~ 1); setArg(call_get_sew_pow_3694, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3694, 0, ret_val_get_sew_pow_3694); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3696; @@ -84725,7 +84740,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3702, (ret_val_get_sew_pow_3701))), 8, false), ~ 1); setArg(call_get_sew_pow_3701, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3701, 0, ret_val_get_sew_pow_3701); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3703; @@ -84843,7 +84858,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3709, (ret_val_get_sew_pow_3708))), 8, false), ~ 1); setArg(call_get_sew_pow_3708, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3708, 0, ret_val_get_sew_pow_3708); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3710; @@ -84960,7 +84975,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3716, (ret_val_get_sew_pow_3715))), 8, false), ~ 1); setArg(call_get_sew_pow_3715, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3715, 0, ret_val_get_sew_pow_3715); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3717; @@ -85071,7 +85086,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3722, (ret_val_get_sew_pow_3721))), 8, false), ~ 1); setArg(call_get_sew_pow_3721, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3721, 0, ret_val_get_sew_pow_3721); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_masked_3723; @@ -85179,7 +85194,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3728, (ret_val_get_sew_pow_3727))), 8, false), ~ 1); setArg(call_get_sew_pow_3727, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3727, 0, ret_val_get_sew_pow_3727); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_vd_unmasked_3729; @@ -85287,7 +85302,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3734, (ret_val_get_sew_pow_3733))), 8, false), ~ 1); setArg(call_get_sew_pow_3733, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3733, 0, ret_val_get_sew_pow_3733); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3735; @@ -85398,7 +85413,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3740, (ret_val_get_sew_pow_3739))), 8, false), ~ 1); setArg(call_get_sew_pow_3739, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3739, 0, ret_val_get_sew_pow_3739); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3741; @@ -85727,7 +85742,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3758, (ret_val_get_sew_pow_3757))), 8, false), ~ 1); setArg(call_get_sew_pow_3757, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3757, 0, ret_val_get_sew_pow_3757); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3759; @@ -85838,7 +85853,7 @@ template class vm_impl : public iss::asmjit::vm_base { (gen_operation(cc, shl, tmp3764, (ret_val_get_sew_pow_3763))), 8, false), ~ 1); setArg(call_get_sew_pow_3763, 0, reinterpret_cast(this)); setRet(call_get_sew_pow_3763, 0, ret_val_get_sew_pow_3763); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_normal_3765; @@ -85958,7 +85973,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3772; @@ -86092,7 +86107,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3780; @@ -86490,7 +86505,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3804; @@ -86624,7 +86639,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3812; @@ -86758,7 +86773,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3820; @@ -86892,7 +86907,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3828; @@ -87026,7 +87041,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3836; @@ -87424,7 +87439,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3860; @@ -87558,7 +87573,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3868; @@ -87692,7 +87707,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3876; @@ -87826,7 +87841,7 @@ template class vm_impl : public iss::asmjit::vm_base { auto SEW_widen = gen_ext(cc, (gen_operation(cc, umul, SEW, 2)), 8, false); auto LMUL_pow_widen = gen_operation(cc, add, LMUL_pow, 1); - auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), 5, 7-5+1); + auto rm = gen_slice(cc, load_reg_from_mem(jh, traits::FCSR), (uint32_t)(5), (uint32_t)(7-5+1)); { auto label_merge = cc.newLabel(); InvokeNode* call_illegal_fp_variable_width_3884; @@ -87979,6 +87994,7 @@ void vm_impl::gen_instr_prologue(jit_holder& jh) { x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE); mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state); + cc.inc(get_ptr_for(jh, traits::CYCLE)); cc.comment("//Instruction prologue end"); } @@ -87987,7 +88003,6 @@ void vm_impl::gen_instr_epilogue(jit_holder& jh) { auto& cc = jh.cc; cc.comment("//Instruction epilogue begin"); - cc.inc(get_ptr_for(jh, traits::CYCLE)); x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE); mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cmp(cc, current_trap_state, 0); @@ -88077,8 +88092,8 @@ std::unique_ptr create(arch::rv64gcv *core, unsigned short } // namespace iss #include -#include #include +#include #include namespace iss { namespace { From e833119291e1dadb965972c1ab6a9a03dc4e5151 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Wed, 1 Oct 2025 19:34:08 +0200 Subject: [PATCH 029/230] enables logging for dbt_rise_iss logger --- src/main.cpp | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/main.cpp b/src/main.cpp index d76f163..ca6a09e 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -101,14 +101,17 @@ int main(int argc, char* argv[]) { LOGGER(DEFAULT)::print_time() = false; LOGGER(connection)::print_time() = false; + LOGGER(dbt_rise_iss)::print_time() = false; auto l = logging::as_log_level(clim["verbose"].as()); LOGGER(DEFAULT)::reporting_level() = l; LOGGER(connection)::reporting_level() = l; + LOGGER(dbt_rise_iss)::reporting_level() = l; if(clim.count("logfile")) { // configure the connection logger auto f = fopen(clim["logfile"].as().c_str(), "w"); LOG_OUTPUT(DEFAULT)::stream() = f; LOG_OUTPUT(connection)::stream() = f; + LOG_OUTPUT(dbt_rise_iss)::stream() = f; } std::vector plugin_list; @@ -128,16 +131,16 @@ int main(int argc, char* argv[]) { std::string isa_opt(clim["isa"].as()); if(isa_opt.size() == 0 || isa_opt == "?") { std::unordered_map> core_by_backend; - for(auto& e: f.get_names()) { + for(auto& e : f.get_names()) { auto p = e.find(':'); - assert(p!=std::string::npos); - core_by_backend[e.substr(p+1)].push_back(e.substr(0, p)); + assert(p != std::string::npos); + core_by_backend[e.substr(p + 1)].push_back(e.substr(0, p)); } std::cout << "Available implementations\n"; std::cout << "=========================\n"; - for(auto& e:core_by_backend) { + for(auto& e : core_by_backend) { std::sort(std::begin(e.second), std::end(e.second)); - std::cout<<" backend "< Date: Sun, 5 Oct 2025 14:58:23 +0200 Subject: [PATCH 030/230] adds csr callback registration --- src/sysc/core_complex.cpp | 60 +++++++++++++++++++------------------- src/sysc/core_complex.h | 2 +- src/sysc/core_facade.h | 4 +++ src/sysc/sc_core_adapter.h | 47 +++++++++++++++++++---------- 4 files changed, 67 insertions(+), 46 deletions(-) diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index 81a74d2..a74c6db 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -138,21 +138,22 @@ class core_wrapper { void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) { auto& f = sysc::iss_factory::instance(); if(type.size() == 0 || type == "?") { - std::unordered_map> core_by_backend; - for(auto& e: f.get_names()) { + std::unordered_map> core_by_backend; + for(auto& e : f.get_names()) { auto p = e.find(':'); - assert(p!=std::string::npos); - core_by_backend[e.substr(p+1)].push_back(e.substr(0, p)); + assert(p != std::string::npos); + core_by_backend[e.substr(p + 1)].push_back(e.substr(0, p)); } std::ostringstream os; os << "Available implementations\n"; os << "=========================\n"; - for(auto& e:core_by_backend) { + for(auto& e : core_by_backend) { std::sort(std::begin(e.second), std::end(e.second)); - if(os.str().size()) os<<"\n"; - os<<" backend "<hier_name()) << "\n"<hier_name()) << "\n" << os.str(); sc_core::sc_stop(); } else if(type.find(':') == std::string::npos) { std::tie(core, vm) = f.create(type + ":" + backend, gdb_port, owner); @@ -277,7 +278,7 @@ template void core_complex::init() { } template core_complex::~core_complex() { - delete core; + delete core_holder; delete trc; for(auto* p : plugin_list) delete p; @@ -289,21 +290,20 @@ template void core_complex::before_end_of_elab auto& type = GET_PROP_VALUE(core_type); SCCDEBUG(SCMOD) << "instantiating core " << type << " with " << GET_PROP_VALUE(backend) << " backend"; // cpu = scc::make_unique(this); - core = new core_wrapper(this); - core->create_cpu(type, GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid)); + core_holder = new core_wrapper(this); + core_holder->create_cpu(type, GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid)); if(type == "?") return; #ifndef CWR_SYSTEMC if(!local_irq_num.is_default_value()) { - auto* sc_cpu_if = reinterpret_cast(core->core.get()); - sc_cpu_if->set_irq_count(16 + local_irq_num); + core_holder->core->set_irq_count(16 + local_irq_num); } #endif sc_assert(core->vm != nullptr); auto disass = GET_PROP_VALUE(enable_disass); if(disass && trc->m_db) SCCINFO(SCMOD) << "Disasssembly will only be in transaction trace database!"; - core->vm->setDisassEnabled(disass || trc->m_db != nullptr); + core_holder->vm->setDisassEnabled(disass || trc->m_db != nullptr); if(GET_PROP_VALUE(plugins).length()) { auto p = util::split(GET_PROP_VALUE(plugins), ';'); for(std::string const& opt_val : p) { @@ -316,11 +316,11 @@ template void core_complex::before_end_of_elab } if(plugin_name == "ic") { auto* plugin = new iss::plugin::instruction_count(filename); - core->vm->register_plugin(*plugin); + core_holder->vm->register_plugin(*plugin); plugin_list.push_back(plugin); } else if(plugin_name == "ce") { auto* plugin = new iss::plugin::cycle_estimate(filename); - core->vm->register_plugin(*plugin); + core_holder->vm->register_plugin(*plugin); plugin_list.push_back(plugin); } else { #ifndef WIN32 @@ -328,7 +328,7 @@ template void core_complex::before_end_of_elab iss::plugin::loader l(plugin_name, {{"initPlugin"}}); auto* plugin = l.call_function("initPlugin", a.size(), a.data()); if(plugin) { - core->vm->register_plugin(*plugin); + core_holder->vm->register_plugin(*plugin); plugin_list.push_back(plugin); } else #endif @@ -343,7 +343,7 @@ template void core_complex::start_of_simulatio if(GET_PROP_VALUE(elf_file).size() > 0) { auto file_names = util::split(GET_PROP_VALUE(elf_file), ','); for(auto& s : file_names) { - std::pair load_result = core->load_file(s); + std::pair load_result = core_holder->load_file(s); if(!std::get<1>(load_result)) { SCCWARN(SCMOD) << "Could not load FW file " << s; } else { @@ -372,8 +372,8 @@ template bool core_complex::disass_output(uint trc->tr_handle = trc->instr_tr_handle->begin_transaction(); trc->tr_handle.record_attribute("PC", pc); trc->tr_handle.record_attribute("INSTR", instr_str); - trc->tr_handle.record_attribute("MODE", lvl[core->core->get_mode()]); - trc->tr_handle.record_attribute("MSTATUS", core->core->get_state()); + trc->tr_handle.record_attribute("MODE", lvl[core_holder->core->get_mode()]); + trc->tr_handle.record_attribute("MSTATUS", core_holder->core->get_state()); trc->tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000); return true; } @@ -390,25 +390,25 @@ template void core_complex::forward() { template void core_complex::set_clock_period(sc_core::sc_time period) { curr_clk = period; if(period == SC_ZERO_TIME) - core->core->set_interrupt_execution(true); + core_holder->core->set_interrupt_execution(true); } template void core_complex::rst_cb() { if(rst_i.read()) - core->core->set_interrupt_execution(true); + core_holder->core->set_interrupt_execution(true); } #ifndef USE_TLM_SIGNAL -template void core_complex::sw_irq_cb() { core->core->local_irq(3, sw_irq_i.read()); } +template void core_complex::sw_irq_cb() { core_holder->core->local_irq(3, sw_irq_i.read()); } -template void core_complex::timer_irq_cb() { core->core->local_irq(7, timer_irq_i.read()); } +template void core_complex::timer_irq_cb() { core_holder->core->local_irq(7, timer_irq_i.read()); } -template void core_complex::ext_irq_cb() { core->core->local_irq(11, ext_irq_i.read()); } +template void core_complex::ext_irq_cb() { core_holder->core->local_irq(11, ext_irq_i.read()); } template void core_complex::local_irq_cb() { for(auto i = 0U; i < local_irq_i.size(); ++i) { if(local_irq_i[i].event()) { - core->core->local_irq(16 + i, local_irq_i[i].read()); + core_holder->core->local_irq(16 + i, local_irq_i[i].read()); } } } @@ -419,16 +419,16 @@ template void core_complex::run() { do { wait(SC_ZERO_TIME); if(rst_i.read()) { - core->reset(GET_PROP_VALUE(reset_address)); + core_holder->reset(GET_PROP_VALUE(reset_address)); wait(rst_i.negedge_event()); } while(curr_clk.read() == SC_ZERO_TIME) { wait(curr_clk.value_changed_event()); } quantum_keeper.reset(); - core->core->set_interrupt_execution(false); - core->start(dump_ir); - } while(!core->core->get_interrupt_execution()); + core_holder->core->set_interrupt_execution(false); + core_holder->start(dump_ir); + } while(!core_holder->core->get_interrupt_execution()); sc_stop(); } diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h index 918f974..a696f4b 100644 --- a/src/sysc/core_complex.h +++ b/src/sysc/core_complex.h @@ -236,7 +236,7 @@ template class core_complex : public sc_core:: util::range_lut fetch_lut, read_lut, write_lut; tlm_utils::tlm_quantumkeeper quantum_keeper; std::vector write_buf; - core_wrapper* core{nullptr}; + core_wrapper* core_holder{nullptr}; sc_core::sc_signal curr_clk; uint64_t ibus_inc{0}, dbus_inc{0}; core_trace* trc{nullptr}; diff --git a/src/sysc/core_facade.h b/src/sysc/core_facade.h index 314409e..27ff6a7 100644 --- a/src/sysc/core_facade.h +++ b/src/sysc/core_facade.h @@ -53,6 +53,10 @@ struct core_facade { util::delegate get_interrupt_execution; util::delegate set_interrupt_execution; util::delegate local_irq; // id, value + using rd_csr_f = std::function; + using wr_csr_f = std::function; + util::delegate register_csr_rd; + util::delegate register_csr_wr; }; } // namespace sysc #endif /* _SYSC_SC_CORE_ADAPTER_IF_H_ */ diff --git a/src/sysc/sc_core_adapter.h b/src/sysc/sc_core_adapter.h index 9e8d4e9..8d6066e 100644 --- a/src/sysc/sc_core_adapter.h +++ b/src/sysc/sc_core_adapter.h @@ -48,6 +48,7 @@ namespace sysc { template class sc_core_adapter : public PLAT, public core_facade { public: using this_class = sc_core_adapter; + using core = typename PLAT::core; using reg_t = typename iss::arch::traits::reg_t; using phys_addr_t = typename iss::arch::traits::phys_addr_t; sc_core_adapter(sysc::riscv::core_complex_if* owner) @@ -64,24 +65,12 @@ template class sc_core_adapter : public PLAT, public core_facade this->get_interrupt_execution = util::delegate::from(this); this->set_interrupt_execution = util::delegate::from(this); this->local_irq = util::delegate::from(this); + this->register_csr_rd = util::delegate::from(this); + this->register_csr_wr = util::delegate::from(this); } virtual ~sc_core_adapter() {} - iss::arch_if* _get_arch_if() { return this; } - - void _set_mhartid(unsigned id) { PLAT::set_mhartid(id); } - - void _set_irq_num(unsigned num) { PLAT::set_irq_num(num); } - - uint32_t _get_mode() { return this->reg.PRIV; } - - void _set_interrupt_execution(bool v) { this->interrupt_sim = v ? 1 : 0; } - - bool _get_interrupt_execution() { return this->interrupt_sim; } - - uint64_t _get_state() { return this->state.mstatus.backing.val; } - void notify_phase(iss::arch_if::exec_phase p) override { if(p == iss::arch_if::ISTART && !first) { auto cycle_incr = owner->get_last_bus_cycles(); @@ -188,6 +177,21 @@ template class sc_core_adapter : public PLAT, public core_facade } } +private: + iss::arch_if* _get_arch_if() { return this; } + + void _set_mhartid(unsigned id) { PLAT::set_mhartid(id); } + + void _set_irq_num(unsigned num) { PLAT::set_irq_num(num); } + + uint32_t _get_mode() { return this->reg.PRIV; } + + void _set_interrupt_execution(bool v) { this->interrupt_sim = v ? 1 : 0; } + + bool _get_interrupt_execution() { return this->interrupt_sim; } + + uint64_t _get_state() { return this->state.mstatus.backing.val; } + void _local_irq(short id, bool value) { reg_t mask = 0; switch(id) { @@ -215,7 +219,20 @@ template class sc_core_adapter : public PLAT, public core_facade SCCTRACE(owner->hier_name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap; } -private: + void _register_csr_rd(unsigned addr, rd_csr_f cb) { + std::function lambda = [cb](unsigned addr, reg_t& r) -> iss::status { + uint64_t temp = r; + auto ret = cb(addr, temp); + r = temp; + return ret; + }; + this->register_csr(addr, lambda); + } + void _register_csr_wr(unsigned addr, wr_csr_f cb) { + std::function lambda = [cb](unsigned addr, reg_t r) -> iss::status { return cb(addr, r); }; + this->register_csr(addr, lambda); + } + sysc::riscv::core_complex_if* const owner{nullptr}; sc_core::sc_event wfi_evt; unsigned to_host_wr_cnt = 0; From 5281431b8d5fde19bb3e2e9eedec2baf0c0b49f6 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sun, 5 Oct 2025 16:29:49 +0200 Subject: [PATCH 031/230] refactors RISC-V<->SystemC interface --- gen_input/templates/CORENAME_sysc.cpp.gtl | 68 ++- src/iss/arch/riscv_hart_m_p.h | 1 + src/iss/arch/riscv_hart_msu_vp.h | 1 + src/iss/arch/riscv_hart_mu_p.h | 1 + src/iss/arch/rv32gc.h | 5 +- src/iss/arch/rv32i.h | 5 +- src/iss/arch/rv32imac.h | 5 +- src/iss/arch/rv64gc.h | 5 +- src/iss/arch/rv64i.h | 5 +- src/iss/arch/tgc5c.h | 5 +- .../{sc_core_adapter.h => core2sc_adapter.h} | 35 +- src/sysc/core_complex.cpp | 217 +++++----- src/sysc/core_complex.h | 54 +-- src/sysc/core_complex_if.h | 66 +++ src/sysc/iss_factory.h | 9 +- src/sysc/register_cores.cpp | 153 +++---- src/sysc/register_rv32gcv.cpp | 42 +- src/sysc/register_rv64gcv.cpp | 42 +- src/sysc/{core_facade.h => sc2core_if.h} | 17 +- src/vm/asmjit/vm_rv32gc.cpp | 351 ++++++++-------- src/vm/asmjit/vm_rv32i.cpp | 18 +- src/vm/asmjit/vm_rv32imac.cpp | 18 +- src/vm/asmjit/vm_rv64gc.cpp | 391 +++++++++--------- src/vm/asmjit/vm_rv64i.cpp | 18 +- src/vm/asmjit/vm_tgc5c.cpp | 18 +- src/vm/interp/vm_rv32gc.cpp | 12 +- src/vm/interp/vm_rv32gcv.cpp | 7 +- src/vm/interp/vm_rv32i.cpp | 6 +- src/vm/interp/vm_rv32imac.cpp | 6 +- src/vm/interp/vm_rv64gc.cpp | 12 +- src/vm/interp/vm_rv64gcv.cpp | 7 +- src/vm/interp/vm_rv64i.cpp | 6 +- src/vm/interp/vm_tgc5c.cpp | 6 +- 33 files changed, 863 insertions(+), 749 deletions(-) rename src/sysc/{sc_core_adapter.h => core2sc_adapter.h} (91%) create mode 100644 src/sysc/core_complex_if.h rename src/sysc/{core_facade.h => sc2core_if.h} (82%) diff --git a/gen_input/templates/CORENAME_sysc.cpp.gtl b/gen_input/templates/CORENAME_sysc.cpp.gtl index 5d9e1d7..f9fdf95 100644 --- a/gen_input/templates/CORENAME_sysc.cpp.gtl +++ b/gen_input/templates/CORENAME_sysc.cpp.gtl @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include <% @@ -46,25 +46,25 @@ namespace interp { using namespace sysc; <% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) { %> volatile std::array ${coreDef.name.toLowerCase()}_init = { - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_msu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_msu:interp", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }),<% } else { %> volatile std::array ${coreDef.name.toLowerCase()}_init = {<% } %> - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:interp", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:interp", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>, - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:interp", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%}%> }; @@ -73,41 +73,19 @@ volatile std::array ${coreDef.name.toLowerCase()}_init = { namespace llvm { using namespace sysc; volatile std::array ${coreDef.name.toLowerCase()}_init = { - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:llvm", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:llvm", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>, - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:llvm", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); - return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; - })<%}%> -}; -} -#endif -#if defined(WITH_TCC) -namespace tcc { -using namespace sysc; -volatile std::array ${coreDef.name.toLowerCase()}_init = { - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); - return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; - }), - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); - return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; - })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>, - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t { - auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%}%> }; @@ -118,25 +96,25 @@ namespace asmjit { using namespace sysc; <% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) {%> volatile std::array ${coreDef.name.toLowerCase()}_init = { - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_msu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_msu:asmjit", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }),<% } else { %> volatile std::array ${coreDef.name.toLowerCase()}_init = {<% } %> - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_m:asmjit", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; }), - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu:asmjit", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>, - iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t { + iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}_mu_p_clic_pmp:asmjit", [](unsigned gdb_port, sysc::riscv::core_complex_if* data) -> iss_factory::base_t { auto* cc = reinterpret_cast(data); - auto* cpu = new sc_core_adapter>(cc); + auto* cpu = new core2sc_adapter>(cc); return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast(cpu), gdb_port)}}; })<%}%> }; diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 9c94636..ef7f96a 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -62,6 +62,7 @@ class riscv_hart_m_p : public riscv_hart_common { using base = riscv_hart_common; using this_class = riscv_hart_m_p; using reg_t = typename core::reg_t; + using phys_addr_t = typename core::phys_addr_t; static constexpr reg_t get_mstatus_mask() { if(sizeof(reg_t) == 4) diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index a4db91c..f398e75 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -66,6 +66,7 @@ class riscv_hart_msu_vp : public riscv_hart_common { using base = riscv_hart_common; using this_class = riscv_hart_msu_vp; using reg_t = typename core::reg_t; + using phys_addr_t = typename core::phys_addr_t; static constexpr reg_t get_mstatus_mask(unsigned priv_lvl) { if(sizeof(reg_t) == 4) { diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 2090c49..bf5ae73 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -63,6 +63,7 @@ class riscv_hart_mu_p : public riscv_hart_common { using base = riscv_hart_common; using this_class = riscv_hart_mu_p; using reg_t = typename core::reg_t; + using phys_addr_t = typename core::phys_addr_t; static constexpr reg_t get_mstatus_mask(unsigned priv_lvl) { if(sizeof(reg_t) == 4) { diff --git a/src/iss/arch/rv32gc.h b/src/iss/arch/rv32gc.h index 92dd6a0..453139f 100644 --- a/src/iss/arch/rv32gc.h +++ b/src/iss/arch/rv32gc.h @@ -64,8 +64,6 @@ struct rv32gc: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - -#pragma pack(push, 1) struct RV32GC_regs { uint32_t X0 = 0; uint32_t X1 = 0; @@ -143,7 +141,7 @@ struct rv32gc: public arch_if { uint32_t instruction = 0; uint32_t last_branch = 0; } reg; -#pragma pack(pop) + std::array addr_mode; uint64_t interrupt_sim=0; @@ -298,6 +296,7 @@ template <> struct traits { FFLAG_MASK=31ULL, MISA_VAL=1073746221ULL, MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL }; + constexpr static unsigned FP_REGS_SIZE = 64; constexpr static unsigned V_REGS_SIZE = 0; diff --git a/src/iss/arch/rv32i.h b/src/iss/arch/rv32i.h index dedb152..42d507f 100644 --- a/src/iss/arch/rv32i.h +++ b/src/iss/arch/rv32i.h @@ -64,8 +64,6 @@ struct rv32i: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - -#pragma pack(push, 1) struct RV32I_regs { uint32_t X0 = 0; uint32_t X1 = 0; @@ -110,7 +108,7 @@ struct rv32i: public arch_if { uint32_t instruction = 0; uint32_t last_branch = 0; } reg; -#pragma pack(pop) + std::array addr_mode; uint64_t interrupt_sim=0; @@ -265,6 +263,7 @@ template <> struct traits { MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL }; + constexpr static unsigned FP_REGS_SIZE = 0; constexpr static unsigned V_REGS_SIZE = 0; diff --git a/src/iss/arch/rv32imac.h b/src/iss/arch/rv32imac.h index 57b3810..1e0bdb9 100644 --- a/src/iss/arch/rv32imac.h +++ b/src/iss/arch/rv32imac.h @@ -64,8 +64,6 @@ struct rv32imac: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - -#pragma pack(push, 1) struct RV32IMAC_regs { uint32_t X0 = 0; uint32_t X1 = 0; @@ -110,7 +108,7 @@ struct rv32imac: public arch_if { uint32_t instruction = 0; uint32_t last_branch = 0; } reg; -#pragma pack(pop) + std::array addr_mode; uint64_t interrupt_sim=0; @@ -265,6 +263,7 @@ template <> struct traits { MISA_VAL=1073746181ULL, MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL }; + constexpr static unsigned FP_REGS_SIZE = 0; constexpr static unsigned V_REGS_SIZE = 0; diff --git a/src/iss/arch/rv64gc.h b/src/iss/arch/rv64gc.h index 57110b8..d76cdd2 100644 --- a/src/iss/arch/rv64gc.h +++ b/src/iss/arch/rv64gc.h @@ -64,8 +64,6 @@ struct rv64gc: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - -#pragma pack(push, 1) struct RV64GC_regs { uint64_t X0 = 0; uint64_t X1 = 0; @@ -143,7 +141,7 @@ struct rv64gc: public arch_if { uint32_t instruction = 0; uint32_t last_branch = 0; } reg; -#pragma pack(pop) + std::array addr_mode; uint64_t interrupt_sim=0; @@ -298,6 +296,7 @@ template <> struct traits { FFLAG_MASK=31ULL, MISA_VAL=9223372036854780205ULL, MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL }; + constexpr static unsigned FP_REGS_SIZE = 64; constexpr static unsigned V_REGS_SIZE = 0; diff --git a/src/iss/arch/rv64i.h b/src/iss/arch/rv64i.h index d4978b4..664f28c 100644 --- a/src/iss/arch/rv64i.h +++ b/src/iss/arch/rv64i.h @@ -64,8 +64,6 @@ struct rv64i: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - -#pragma pack(push, 1) struct RV64I_regs { uint64_t X0 = 0; uint64_t X1 = 0; @@ -110,7 +108,7 @@ struct rv64i: public arch_if { uint32_t instruction = 0; uint32_t last_branch = 0; } reg; -#pragma pack(pop) + std::array addr_mode; uint64_t interrupt_sim=0; @@ -265,6 +263,7 @@ template <> struct traits { MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL }; + constexpr static unsigned FP_REGS_SIZE = 0; constexpr static unsigned V_REGS_SIZE = 0; diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 1ed4cbc..3ce02ec 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -64,8 +64,6 @@ struct tgc5c: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - -#pragma pack(push, 1) struct TGC5C_regs { uint32_t X0 = 0; uint32_t X1 = 0; @@ -110,7 +108,7 @@ struct tgc5c: public arch_if { uint32_t instruction = 0; uint32_t last_branch = 0; } reg; -#pragma pack(pop) + std::array addr_mode; uint64_t interrupt_sim=0; @@ -265,6 +263,7 @@ template <> struct traits { MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, CLIC_NUM_IRQ=0ULL }; + constexpr static unsigned FP_REGS_SIZE = 0; constexpr static unsigned V_REGS_SIZE = 0; diff --git a/src/sysc/sc_core_adapter.h b/src/sysc/core2sc_adapter.h similarity index 91% rename from src/sysc/sc_core_adapter.h rename to src/sysc/core2sc_adapter.h index 8d6066e..368a5ac 100644 --- a/src/sysc/sc_core_adapter.h +++ b/src/sysc/core2sc_adapter.h @@ -32,32 +32,31 @@ * eyck@minres.com - initial implementation ******************************************************************************/ -#ifndef _SYSC_SC_CORE_ADAPTER_H_ -#define _SYSC_SC_CORE_ADAPTER_H_ +#ifndef _SYSC_CORE2SC_ADAPTER_H_ +#define _SYSC_CORE2SC_ADAPTER_H_ #include "core_complex.h" -#include "core_facade.h" +#include "sc2core_if.h" #include +#include #include #include #include #include #include - namespace sysc { -template class sc_core_adapter : public PLAT, public core_facade { +template class core2sc_adapter : public PLAT, public sc2core_if { public: - using this_class = sc_core_adapter; + using this_class = core2sc_adapter; using core = typename PLAT::core; - using reg_t = typename iss::arch::traits::reg_t; - using phys_addr_t = typename iss::arch::traits::phys_addr_t; - sc_core_adapter(sysc::riscv::core_complex_if* owner) + using reg_t = typename PLAT::reg_t; + using phys_addr_t = typename PLAT::phys_addr_t; + core2sc_adapter(sysc::riscv::core_complex_if* owner) : owner(owner) { this->csr_rd_cb[iss::arch::time] = MK_CSR_RD_CB(read_time); if(sizeof(reg_t) == 4) this->csr_rd_cb[iss::arch::timeh] = MK_CSR_RD_CB(read_time); this->memories.replace_last(*this); - this->get_arch_if = util::delegate::from(this); this->set_hartid = util::delegate::from(this); this->set_irq_count = util::delegate::from(this); this->get_mode = util::delegate::from(this); @@ -69,9 +68,9 @@ template class sc_core_adapter : public PLAT, public core_facade this->register_csr_wr = util::delegate::from(this); } - virtual ~sc_core_adapter() {} + virtual ~core2sc_adapter() {} - void notify_phase(iss::arch_if::exec_phase p) override { + void notify_phase(iss::arch_if::exec_phase p) { if(p == iss::arch_if::ISTART && !first) { auto cycle_incr = owner->get_last_bus_cycles(); if(cycle_incr > 1) @@ -81,9 +80,9 @@ template class sc_core_adapter : public PLAT, public core_facade first = false; } - iss::sync_type needed_sync() const override { return iss::PRE_SYNC; } + iss::sync_type needed_sync() const { return iss::PRE_SYNC; } - void disass_output(uint64_t pc, const std::string instr) override { + void disass_output(uint64_t pc, const std::string instr) { static constexpr std::array lvl = {{'U', 'S', 'H', 'M'}}; if(!owner->disass_output(pc, instr)) { std::stringstream s; @@ -94,7 +93,7 @@ template class sc_core_adapter : public PLAT, public core_facade } }; - iss::mem::memory_if get_mem_if() override { + iss::mem::memory_if get_mem_if() { return iss::mem::memory_if{.rd_mem{util::delegate::from(this)}, .wr_mem{util::delegate::from(this)}}; } @@ -169,7 +168,7 @@ template class sc_core_adapter : public PLAT, public core_facade return iss::Ok; } - void wait_until(uint64_t flags) override { + void wait_until(uint64_t flags) { SCCDEBUG(owner->hier_name()) << "Sleeping until interrupt"; PLAT::wait_until(flags); while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) { @@ -178,8 +177,6 @@ template class sc_core_adapter : public PLAT, public core_facade } private: - iss::arch_if* _get_arch_if() { return this; } - void _set_mhartid(unsigned id) { PLAT::set_mhartid(id); } void _set_irq_num(unsigned num) { PLAT::set_irq_num(num); } @@ -239,4 +236,4 @@ template class sc_core_adapter : public PLAT, public core_facade bool first{true}; }; } // namespace sysc -#endif /* _SYSC_SC_CORE_ADAPTER_H_ */ +#endif /* _SYSC_CORE2SC_ADAPTER_H_ */ diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index a74c6db..728048e 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -39,12 +39,12 @@ #include #include #include "iss_factory.h" +#include #include #include #ifndef WIN32 #include #endif -#include "core_facade.h" #include #include #include @@ -91,7 +91,9 @@ iss::debugger::encoder_decoder encdec; std::array lvl = {{'U', 'S', 'H', 'M'}}; } // namespace -int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df, debugger::target_adapter_if* tgt_adapter) { +template +int core_complex::cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df, + debugger::target_adapter_if* tgt_adapter) { if(argc > 1) { if(strcasecmp(argv[1], "print_time") == 0) { std::string t = sc_time_stamp().to_string(); @@ -120,86 +122,65 @@ int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func return Err; } -using cpu_ptr = std::unique_ptr; -using vm_ptr = std::unique_ptr; - -class core_wrapper { -public: - core_wrapper(core_complex_if* owner) - : owner(owner) {} - - void reset(uint64_t addr) { vm->reset(addr); } - inline void start(bool dump = false) { vm->start(std::numeric_limits::max(), dump); } - inline std::pair load_file(std::string const& name) { - iss::arch_if* cc = core->get_arch_if(); - return cc->load_file(name); - }; - - void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) { - auto& f = sysc::iss_factory::instance(); - if(type.size() == 0 || type == "?") { - std::unordered_map> core_by_backend; - for(auto& e : f.get_names()) { - auto p = e.find(':'); - assert(p != std::string::npos); - core_by_backend[e.substr(p + 1)].push_back(e.substr(0, p)); - } - std::ostringstream os; - os << "Available implementations\n"; - os << "=========================\n"; - for(auto& e : core_by_backend) { - std::sort(std::begin(e.second), std::end(e.second)); - if(os.str().size()) - os << "\n"; - os << " backend " << e.first << ":\n - " << util::join(e.second, "\n - "); - } - SCCINFO(owner->hier_name()) << "\n" << os.str(); - sc_core::sc_stop(); - } else if(type.find(':') == std::string::npos) { - std::tie(core, vm) = f.create(type + ":" + backend, gdb_port, owner); - } else { - auto base_isa = type.substr(0, 5); - if(base_isa == "tgc5d" || base_isa == "tgc5e") { - std::tie(core, vm) = f.create(type + "_clic_pmp:" + backend, gdb_port, owner); - } else { - std::tie(core, vm) = f.create(type + ":" + backend, gdb_port, owner); - } +template void core_complex::reset(uint64_t addr) { vm->reset(addr); } +template inline void core_complex::start(bool dump) { + vm->start(std::numeric_limits::max(), dump); +} +template inline std::pair core_complex::load_file(std::string const& name) { + iss::arch_if* cc = vm->get_arch(); + return cc->load_file(name); +}; + +template +void core_complex::create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) { + auto& f = sysc::iss_factory::instance(); + if(type.size() == 0 || type == "?") { + std::unordered_map> core_by_backend; + for(auto& e : f.get_names()) { + auto p = e.find(':'); + assert(p != std::string::npos); + core_by_backend[e.substr(p + 1)].push_back(e.substr(0, p)); } - if(!core) { - if(type != "?") - SCCFATAL() << "Could not create cpu for isa " << type << " and backend " << backend; - } else if(!vm) { - if(type != "?") - SCCFATAL() << "Could not create vm for isa " << type << " and backend " << backend; + std::ostringstream os; + os << "Available implementations\n"; + os << "=========================\n"; + for(auto& e : core_by_backend) { + std::sort(std::begin(e.second), std::end(e.second)); + if(os.str().size()) + os << "\n"; + os << " backend " << e.first << ":\n - " << util::join(e.second, "\n - "); + } + SCCINFO(SCMOD) << "\n" << os.str(); + sc_core::sc_stop(); + } else if(type.find(':') == std::string::npos) { + std::tie(core, vm) = f.create(type + ":" + backend, gdb_port, this); + } else { + auto base_isa = type.substr(0, 5); + if(base_isa == "tgc5d" || base_isa == "tgc5e") { + std::tie(core, vm) = f.create(type + "_clic_pmp:" + backend, gdb_port, this); } else { - core->set_hartid(hart_id); - auto* srv = debugger::server::get(); - if(srv) - tgt_adapter = srv->get_target(0); // FIXME: add core_id - if(tgt_adapter) - tgt_adapter->add_custom_command({"sysc", - [this](int argc, char* argv[], debugger::out_func of, debugger::data_func df) -> int { - return cmd_sysc(argc, argv, of, df, tgt_adapter); - }, - "SystemC sub-commands: break